Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:36:25.786546 lava-dispatcher, installed at version: 2024.03
2 13:36:25.786752 start: 0 validate
3 13:36:25.786886 Start time: 2024-05-28 13:36:25.786877+00:00 (UTC)
4 13:36:25.787009 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:36:25.787137 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:36:26.046359 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:36:26.046524 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:36:26.303051 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:36:26.303214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:26.612672 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:26.612832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:37:27.119473 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:37:27.119642 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:37:27.372030 validate duration: 61.59
16 13:37:27.372307 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:37:27.372416 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:37:27.372506 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:37:27.372632 Not decompressing ramdisk as can be used compressed.
20 13:37:27.372718 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:37:27.372782 saving as /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/ramdisk/initrd.cpio.gz
22 13:37:27.372846 total size: 5628169 (5 MB)
23 13:37:45.468937 progress 0 % (0 MB)
24 13:37:45.477472 progress 5 % (0 MB)
25 13:37:45.485864 progress 10 % (0 MB)
26 13:37:45.493419 progress 15 % (0 MB)
27 13:37:45.499651 progress 20 % (1 MB)
28 13:37:45.503823 progress 25 % (1 MB)
29 13:37:45.507724 progress 30 % (1 MB)
30 13:37:45.511088 progress 35 % (1 MB)
31 13:37:45.513633 progress 40 % (2 MB)
32 13:37:45.516369 progress 45 % (2 MB)
33 13:37:45.518585 progress 50 % (2 MB)
34 13:37:45.521066 progress 55 % (2 MB)
35 13:37:45.523345 progress 60 % (3 MB)
36 13:37:45.525337 progress 65 % (3 MB)
37 13:37:45.527388 progress 70 % (3 MB)
38 13:37:45.528771 progress 75 % (4 MB)
39 13:37:45.530510 progress 80 % (4 MB)
40 13:37:45.531951 progress 85 % (4 MB)
41 13:37:45.533562 progress 90 % (4 MB)
42 13:37:45.535164 progress 95 % (5 MB)
43 13:37:45.536554 progress 100 % (5 MB)
44 13:37:45.536761 5 MB downloaded in 18.16 s (0.30 MB/s)
45 13:37:45.536914 end: 1.1.1 http-download (duration 00:00:18) [common]
47 13:37:45.537141 end: 1.1 download-retry (duration 00:00:18) [common]
48 13:37:45.537225 start: 1.2 download-retry (timeout 00:09:42) [common]
49 13:37:45.537311 start: 1.2.1 http-download (timeout 00:09:42) [common]
50 13:37:45.537449 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:37:45.537517 saving as /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/kernel/Image
52 13:37:45.537576 total size: 54682112 (52 MB)
53 13:37:45.537652 No compression specified
54 13:37:45.538969 progress 0 % (0 MB)
55 13:37:45.553390 progress 5 % (2 MB)
56 13:37:45.567915 progress 10 % (5 MB)
57 13:37:45.582266 progress 15 % (7 MB)
58 13:37:45.596481 progress 20 % (10 MB)
59 13:37:45.610840 progress 25 % (13 MB)
60 13:37:45.625062 progress 30 % (15 MB)
61 13:37:45.639568 progress 35 % (18 MB)
62 13:37:45.653785 progress 40 % (20 MB)
63 13:37:45.667887 progress 45 % (23 MB)
64 13:37:45.682478 progress 50 % (26 MB)
65 13:37:45.696792 progress 55 % (28 MB)
66 13:37:45.711071 progress 60 % (31 MB)
67 13:37:45.725209 progress 65 % (33 MB)
68 13:37:45.739568 progress 70 % (36 MB)
69 13:37:45.753882 progress 75 % (39 MB)
70 13:37:45.768402 progress 80 % (41 MB)
71 13:37:45.782484 progress 85 % (44 MB)
72 13:37:45.796453 progress 90 % (46 MB)
73 13:37:45.810501 progress 95 % (49 MB)
74 13:37:45.824576 progress 100 % (52 MB)
75 13:37:45.824817 52 MB downloaded in 0.29 s (181.55 MB/s)
76 13:37:45.824966 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:37:45.825206 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:37:45.825295 start: 1.3 download-retry (timeout 00:09:42) [common]
80 13:37:45.825379 start: 1.3.1 http-download (timeout 00:09:42) [common]
81 13:37:45.825510 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:37:45.825577 saving as /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/dtb/mt8192-asurada-spherion-r0.dtb
83 13:37:45.825635 total size: 47258 (0 MB)
84 13:37:45.825705 No compression specified
85 13:37:46.083247 progress 69 % (0 MB)
86 13:37:46.083635 progress 100 % (0 MB)
87 13:37:46.083829 0 MB downloaded in 0.26 s (0.17 MB/s)
88 13:37:46.084057 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:37:46.084334 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:37:46.084480 start: 1.4 download-retry (timeout 00:09:41) [common]
92 13:37:46.084572 start: 1.4.1 http-download (timeout 00:09:41) [common]
93 13:37:46.084766 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:37:46.084851 saving as /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/nfsrootfs/full.rootfs.tar
95 13:37:46.084981 total size: 120894716 (115 MB)
96 13:37:46.085047 Using unxz to decompress xz
97 13:37:46.346556 progress 0 % (0 MB)
98 13:37:46.706196 progress 5 % (5 MB)
99 13:37:47.077644 progress 10 % (11 MB)
100 13:37:47.443696 progress 15 % (17 MB)
101 13:37:47.798545 progress 20 % (23 MB)
102 13:37:48.101007 progress 25 % (28 MB)
103 13:37:48.474677 progress 30 % (34 MB)
104 13:37:48.825062 progress 35 % (40 MB)
105 13:37:48.995773 progress 40 % (46 MB)
106 13:37:49.179463 progress 45 % (51 MB)
107 13:37:49.514279 progress 50 % (57 MB)
108 13:37:49.930964 progress 55 % (63 MB)
109 13:37:50.290939 progress 60 % (69 MB)
110 13:37:50.650780 progress 65 % (74 MB)
111 13:37:51.024751 progress 70 % (80 MB)
112 13:37:51.420267 progress 75 % (86 MB)
113 13:37:51.799000 progress 80 % (92 MB)
114 13:37:52.156616 progress 85 % (98 MB)
115 13:37:52.526027 progress 90 % (103 MB)
116 13:37:52.870214 progress 95 % (109 MB)
117 13:37:53.232829 progress 100 % (115 MB)
118 13:37:53.238330 115 MB downloaded in 7.15 s (16.12 MB/s)
119 13:37:53.238590 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:37:53.238854 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:37:53.238945 start: 1.5 download-retry (timeout 00:09:34) [common]
123 13:37:53.239030 start: 1.5.1 http-download (timeout 00:09:34) [common]
124 13:37:53.239190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:37:53.239260 saving as /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/modules/modules.tar
126 13:37:53.239324 total size: 8607916 (8 MB)
127 13:37:53.239389 Using unxz to decompress xz
128 13:37:53.243539 progress 0 % (0 MB)
129 13:37:53.263120 progress 5 % (0 MB)
130 13:37:53.287521 progress 10 % (0 MB)
131 13:37:53.312849 progress 15 % (1 MB)
132 13:37:53.337340 progress 20 % (1 MB)
133 13:37:53.362801 progress 25 % (2 MB)
134 13:37:53.387342 progress 30 % (2 MB)
135 13:37:53.410676 progress 35 % (2 MB)
136 13:37:53.436604 progress 40 % (3 MB)
137 13:37:53.461289 progress 45 % (3 MB)
138 13:37:53.485123 progress 50 % (4 MB)
139 13:37:53.509822 progress 55 % (4 MB)
140 13:37:53.533960 progress 60 % (4 MB)
141 13:37:53.557875 progress 65 % (5 MB)
142 13:37:53.584057 progress 70 % (5 MB)
143 13:37:53.611947 progress 75 % (6 MB)
144 13:37:53.636135 progress 80 % (6 MB)
145 13:37:53.660081 progress 85 % (7 MB)
146 13:37:53.684123 progress 90 % (7 MB)
147 13:37:53.713501 progress 95 % (7 MB)
148 13:37:53.741621 progress 100 % (8 MB)
149 13:37:53.747586 8 MB downloaded in 0.51 s (16.15 MB/s)
150 13:37:53.747851 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:37:53.748121 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:37:53.748216 start: 1.6 prepare-tftp-overlay (timeout 00:09:34) [common]
154 13:37:53.748322 start: 1.6.1 extract-nfsrootfs (timeout 00:09:34) [common]
155 13:37:57.779047 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s
156 13:37:57.779281 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 13:37:57.779409 start: 1.6.2 lava-overlay (timeout 00:09:30) [common]
158 13:37:57.779651 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8
159 13:37:57.779846 makedir: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin
160 13:37:57.780020 makedir: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/tests
161 13:37:57.780179 makedir: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/results
162 13:37:57.780334 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-add-keys
163 13:37:57.780507 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-add-sources
164 13:37:57.780674 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-background-process-start
165 13:37:57.780834 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-background-process-stop
166 13:37:57.780991 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-common-functions
167 13:37:57.781207 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-echo-ipv4
168 13:37:57.781362 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-install-packages
169 13:37:57.781515 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-installed-packages
170 13:37:57.781669 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-os-build
171 13:37:57.781841 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-probe-channel
172 13:37:57.782000 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-probe-ip
173 13:37:57.782153 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-target-ip
174 13:37:57.782319 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-target-mac
175 13:37:57.782440 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-target-storage
176 13:37:57.782563 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-case
177 13:37:57.782684 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-event
178 13:37:57.782802 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-feedback
179 13:37:57.782922 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-raise
180 13:37:57.783041 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-reference
181 13:37:57.783162 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-runner
182 13:37:57.783281 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-set
183 13:37:57.783406 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-test-shell
184 13:37:57.783533 Updating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-add-keys (debian)
185 13:37:57.783713 Updating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-add-sources (debian)
186 13:37:57.783858 Updating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-install-packages (debian)
187 13:37:57.783997 Updating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-installed-packages (debian)
188 13:37:57.784142 Updating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/bin/lava-os-build (debian)
189 13:37:57.784261 Creating /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/environment
190 13:37:57.784359 LAVA metadata
191 13:37:57.784424 - LAVA_JOB_ID=14063000
192 13:37:57.784485 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:37:57.784585 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:30) [common]
194 13:37:57.784650 skipped lava-vland-overlay
195 13:37:57.784723 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:37:57.784827 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:30) [common]
197 13:37:57.784913 skipped lava-multinode-overlay
198 13:37:57.784986 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:37:57.785061 start: 1.6.2.3 test-definition (timeout 00:09:30) [common]
200 13:37:57.785144 Loading test definitions
201 13:37:57.785242 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:30) [common]
202 13:37:57.785312 Using /lava-14063000 at stage 0
203 13:37:57.785620 uuid=14063000_1.6.2.3.1 testdef=None
204 13:37:57.785736 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:37:57.785854 start: 1.6.2.3.2 test-overlay (timeout 00:09:30) [common]
206 13:37:57.786569 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:37:57.786812 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:30) [common]
209 13:37:57.787430 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:37:57.787790 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:30) [common]
212 13:37:57.788516 runner path: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/0/tests/0_timesync-off test_uuid 14063000_1.6.2.3.1
213 13:37:57.788722 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:37:57.789076 start: 1.6.2.3.5 git-repo-action (timeout 00:09:30) [common]
216 13:37:57.789176 Using /lava-14063000 at stage 0
217 13:37:57.789312 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:37:57.789407 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/0/tests/1_kselftest-dt'
219 13:38:01.011327 Running '/usr/bin/git checkout kernelci.org
220 13:38:01.023379 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 13:38:01.024151 uuid=14063000_1.6.2.3.5 testdef=None
222 13:38:01.024313 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:38:01.024597 start: 1.6.2.3.6 test-overlay (timeout 00:09:26) [common]
225 13:38:01.025377 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:38:01.025644 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:26) [common]
228 13:38:01.026894 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:38:01.027135 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:26) [common]
231 13:38:01.028060 runner path: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/0/tests/1_kselftest-dt test_uuid 14063000_1.6.2.3.5
232 13:38:01.028152 BOARD='mt8192-asurada-spherion-r0'
233 13:38:01.028216 BRANCH='cip'
234 13:38:01.028273 SKIPFILE='/dev/null'
235 13:38:01.028330 SKIP_INSTALL='True'
236 13:38:01.028385 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:38:01.028443 TST_CASENAME=''
238 13:38:01.028498 TST_CMDFILES='dt'
239 13:38:01.028637 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:38:01.028846 Creating lava-test-runner.conf files
242 13:38:01.028908 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063000/lava-overlay-cq_0n9d8/lava-14063000/0 for stage 0
243 13:38:01.029001 - 0_timesync-off
244 13:38:01.029065 - 1_kselftest-dt
245 13:38:01.029160 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:38:01.029246 start: 1.6.2.4 compress-overlay (timeout 00:09:26) [common]
247 13:38:08.708081 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:38:08.708251 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:19) [common]
249 13:38:08.708349 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:38:08.708448 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 13:38:08.708539 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:19) [common]
252 13:38:08.886391 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:38:08.886789 start: 1.6.4 extract-modules (timeout 00:09:18) [common]
254 13:38:08.886916 extracting modules file /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s
255 13:38:09.129369 extracting modules file /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063000/extract-overlay-ramdisk-7_5fk409/ramdisk
256 13:38:09.370770 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:38:09.370946 start: 1.6.5 apply-overlay-tftp (timeout 00:09:18) [common]
258 13:38:09.371046 [common] Applying overlay to NFS
259 13:38:09.371118 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063000/compress-overlay-ng3bm2pb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s
260 13:38:10.340527 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:38:10.340724 start: 1.6.6 configure-preseed-file (timeout 00:09:17) [common]
262 13:38:10.340842 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:38:10.340955 start: 1.6.7 compress-ramdisk (timeout 00:09:17) [common]
264 13:38:10.341053 Building ramdisk /var/lib/lava/dispatcher/tmp/14063000/extract-overlay-ramdisk-7_5fk409/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063000/extract-overlay-ramdisk-7_5fk409/ramdisk
265 13:38:10.657420 >> 130335 blocks
266 13:38:12.761248 rename /var/lib/lava/dispatcher/tmp/14063000/extract-overlay-ramdisk-7_5fk409/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/ramdisk/ramdisk.cpio.gz
267 13:38:12.761737 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:38:12.761921 start: 1.6.8 prepare-kernel (timeout 00:09:15) [common]
269 13:38:12.762074 start: 1.6.8.1 prepare-fit (timeout 00:09:15) [common]
270 13:38:12.762230 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/kernel/Image']
271 13:38:27.321564 Returned 0 in 14 seconds
272 13:38:27.422219 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/kernel/image.itb
273 13:38:27.785735 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:38:27.786168 output: Created: Tue May 28 14:38:27 2024
275 13:38:27.786284 output: Image 0 (kernel-1)
276 13:38:27.786384 output: Description:
277 13:38:27.786479 output: Created: Tue May 28 14:38:27 2024
278 13:38:27.786573 output: Type: Kernel Image
279 13:38:27.786669 output: Compression: lzma compressed
280 13:38:27.786764 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
281 13:38:27.786872 output: Architecture: AArch64
282 13:38:27.786973 output: OS: Linux
283 13:38:27.787067 output: Load Address: 0x00000000
284 13:38:27.787158 output: Entry Point: 0x00000000
285 13:38:27.787249 output: Hash algo: crc32
286 13:38:27.787339 output: Hash value: 0578ee26
287 13:38:27.787423 output: Image 1 (fdt-1)
288 13:38:27.787509 output: Description: mt8192-asurada-spherion-r0
289 13:38:27.787598 output: Created: Tue May 28 14:38:27 2024
290 13:38:27.787687 output: Type: Flat Device Tree
291 13:38:27.787775 output: Compression: uncompressed
292 13:38:27.787857 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:38:27.787940 output: Architecture: AArch64
294 13:38:27.788025 output: Hash algo: crc32
295 13:38:27.788109 output: Hash value: 0f8e4d2e
296 13:38:27.788194 output: Image 2 (ramdisk-1)
297 13:38:27.788280 output: Description: unavailable
298 13:38:27.788362 output: Created: Tue May 28 14:38:27 2024
299 13:38:27.788445 output: Type: RAMDisk Image
300 13:38:27.788528 output: Compression: Unknown Compression
301 13:38:27.788613 output: Data Size: 18732953 Bytes = 18293.90 KiB = 17.87 MiB
302 13:38:27.788695 output: Architecture: AArch64
303 13:38:27.788783 output: OS: Linux
304 13:38:27.788865 output: Load Address: unavailable
305 13:38:27.788948 output: Entry Point: unavailable
306 13:38:27.789035 output: Hash algo: crc32
307 13:38:27.789119 output: Hash value: d6aac56e
308 13:38:27.789201 output: Default Configuration: 'conf-1'
309 13:38:27.789265 output: Configuration 0 (conf-1)
310 13:38:27.789320 output: Description: mt8192-asurada-spherion-r0
311 13:38:27.789373 output: Kernel: kernel-1
312 13:38:27.789426 output: Init Ramdisk: ramdisk-1
313 13:38:27.789479 output: FDT: fdt-1
314 13:38:27.789542 output: Loadables: kernel-1
315 13:38:27.789626 output:
316 13:38:27.789875 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 13:38:27.790010 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 13:38:27.790156 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 13:38:27.790297 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:00) [common]
320 13:38:27.790413 No LXC device requested
321 13:38:27.790528 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:38:27.790651 start: 1.8 deploy-device-env (timeout 00:09:00) [common]
323 13:38:27.790764 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:38:27.790869 Checking files for TFTP limit of 4294967296 bytes.
325 13:38:27.791555 end: 1 tftp-deploy (duration 00:01:00) [common]
326 13:38:27.791704 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:38:27.791833 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:38:27.792010 substitutions:
329 13:38:27.792106 - {DTB}: 14063000/tftp-deploy-9gkb3zig/dtb/mt8192-asurada-spherion-r0.dtb
330 13:38:27.792207 - {INITRD}: 14063000/tftp-deploy-9gkb3zig/ramdisk/ramdisk.cpio.gz
331 13:38:27.792303 - {KERNEL}: 14063000/tftp-deploy-9gkb3zig/kernel/Image
332 13:38:27.792391 - {LAVA_MAC}: None
333 13:38:27.792480 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s
334 13:38:27.792569 - {NFS_SERVER_IP}: 192.168.201.1
335 13:38:27.792655 - {PRESEED_CONFIG}: None
336 13:38:27.792745 - {PRESEED_LOCAL}: None
337 13:38:27.792835 - {RAMDISK}: 14063000/tftp-deploy-9gkb3zig/ramdisk/ramdisk.cpio.gz
338 13:38:27.792920 - {ROOT_PART}: None
339 13:38:27.793005 - {ROOT}: None
340 13:38:27.793093 - {SERVER_IP}: 192.168.201.1
341 13:38:27.793177 - {TEE}: None
342 13:38:27.793265 Parsed boot commands:
343 13:38:27.793326 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:38:27.793521 Parsed boot commands: tftpboot 192.168.201.1 14063000/tftp-deploy-9gkb3zig/kernel/image.itb 14063000/tftp-deploy-9gkb3zig/kernel/cmdline
345 13:38:27.793642 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:38:27.793762 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:38:27.793885 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:38:27.794004 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:38:27.794107 Not connected, no need to disconnect.
350 13:38:27.794222 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:38:27.794353 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:38:27.794452 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 13:38:27.798493 Setting prompt string to ['lava-test: # ']
354 13:38:27.798934 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:38:27.799087 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:38:27.799224 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:38:27.799362 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:38:27.799653 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 13:38:41.830671 Returned 0 in 14 seconds
360 13:38:41.931419 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 13:38:41.931854 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 13:38:41.931995 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 13:38:41.932124 Setting prompt string to 'Starting depthcharge on Spherion...'
365 13:38:41.932226 Changing prompt to 'Starting depthcharge on Spherion...'
366 13:38:41.932322 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 13:38:41.932924 [Enter `^Ec?' for help]
368 13:38:41.933047
369 13:38:41.933152 F0: 102B 0000
370 13:38:41.933255
371 13:38:41.933324 F3: 1001 0000 [0200]
372 13:38:41.933393
373 13:38:41.933454 F3: 1001 0000
374 13:38:41.933515
375 13:38:41.933618 F7: 102D 0000
376 13:38:41.933710
377 13:38:41.933796 F1: 0000 0000
378 13:38:41.933884
379 13:38:41.933969 V0: 0000 0000 [0001]
380 13:38:41.934062
381 13:38:41.934153 00: 0007 8000
382 13:38:41.934229
383 13:38:41.934308 01: 0000 0000
384 13:38:41.934373
385 13:38:41.934429 BP: 0C00 0209 [0000]
386 13:38:41.934485
387 13:38:41.934539 G0: 1182 0000
388 13:38:41.934617
389 13:38:41.934678 EC: 0000 0021 [4000]
390 13:38:41.934734
391 13:38:41.934788 S7: 0000 0000 [0000]
392 13:38:41.934844
393 13:38:41.934900 CC: 0000 0000 [0001]
394 13:38:41.934954
395 13:38:41.935007 T0: 0000 0040 [010F]
396 13:38:41.935069
397 13:38:41.935137 Jump to BL
398 13:38:41.935193
399 13:38:41.935247
400 13:38:41.935300
401 13:38:41.935358 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 13:38:41.935417 ARM64: Exception handlers installed.
403 13:38:41.935472 ARM64: Testing exception
404 13:38:41.935525 ARM64: Done test exception
405 13:38:41.935595 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 13:38:41.935689 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 13:38:41.935777 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 13:38:41.935865 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 13:38:41.935952 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 13:38:41.936038 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 13:38:41.936138 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 13:38:41.936239 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 13:38:41.936332 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 13:38:41.936420 WDT: Last reset was cold boot
415 13:38:41.936506 SPI1(PAD0) initialized at 2873684 Hz
416 13:38:41.936592 SPI5(PAD0) initialized at 992727 Hz
417 13:38:41.936690 VBOOT: Loading verstage.
418 13:38:41.936776 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 13:38:41.936863 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 13:38:41.936950 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 13:38:41.937035 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 13:38:41.937128 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 13:38:41.937222 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 13:38:41.937308 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
425 13:38:41.937395
426 13:38:41.937478
427 13:38:41.937564 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 13:38:41.937662 ARM64: Exception handlers installed.
429 13:38:41.937750 ARM64: Testing exception
430 13:38:41.937847 ARM64: Done test exception
431 13:38:41.937936 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 13:38:41.938022 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 13:38:41.938107 Probing TPM: . done!
434 13:38:41.938205 TPM ready after 0 ms
435 13:38:41.938263 Connected to device vid:did:rid of 1ae0:0028:00
436 13:38:41.938320 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 13:38:41.938379 Initialized TPM device CR50 revision 0
438 13:38:41.938435 tlcl_send_startup: Startup return code is 0
439 13:38:41.938490 TPM: setup succeeded
440 13:38:41.938543 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 13:38:41.938598 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 13:38:41.938667 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 13:38:41.938731 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 13:38:41.938787 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 13:38:41.938843 in-header: 03 07 00 00 08 00 00 00
446 13:38:41.938902 in-data: aa e4 47 04 13 02 00 00
447 13:38:41.938957 Chrome EC: UHEPI supported
448 13:38:41.939011 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 13:38:41.939066 in-header: 03 a9 00 00 08 00 00 00
450 13:38:41.939120 in-data: 84 60 60 08 00 00 00 00
451 13:38:41.939195 Phase 1
452 13:38:41.939254 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 13:38:41.939310 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 13:38:41.939365 VB2:vb2_check_recovery() Recovery was requested manually
455 13:38:41.939424 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 13:38:41.939478 Recovery requested (1009000e)
457 13:38:41.939532 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 13:38:41.939586 tlcl_extend: response is 0
459 13:38:41.939656 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 13:38:41.939728 tlcl_extend: response is 0
461 13:38:41.939783 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 13:38:41.939837 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
463 13:38:41.939896 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 13:38:41.939951
465 13:38:41.940004
466 13:38:41.940057 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 13:38:41.940112 ARM64: Exception handlers installed.
468 13:38:41.940176 ARM64: Testing exception
469 13:38:41.940241 ARM64: Done test exception
470 13:38:41.940295 pmic_efuse_setting: Set efuses in 11 msecs
471 13:38:41.940348 pmwrap_interface_init: Select PMIF_VLD_RDY
472 13:38:41.940406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 13:38:41.940658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 13:38:41.940769 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 13:38:41.940825 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 13:38:41.940881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 13:38:41.940935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 13:38:41.940987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 13:38:41.941040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 13:38:41.941142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 13:38:41.941251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 13:38:41.941308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 13:38:41.941366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 13:38:41.941468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 13:38:41.941554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 13:38:41.941640 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 13:38:41.941751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 13:38:41.941839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 13:38:41.941925 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 13:38:41.942009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 13:38:41.942093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 13:38:41.942217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 13:38:41.942289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 13:38:41.942345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 13:38:41.942402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 13:38:41.942456 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 13:38:41.942509 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 13:38:41.942563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 13:38:41.942616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 13:38:41.942669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 13:38:41.942735 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 13:38:41.942799 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 13:38:41.942872 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 13:38:41.942928 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 13:38:41.942995 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 13:38:41.943049 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 13:38:41.943101 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 13:38:41.943154 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 13:38:41.943207 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 13:38:41.943292 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 13:38:41.943379 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 13:38:41.943492 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 13:38:41.943575 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 13:38:41.943658 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 13:38:41.943750 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 13:38:41.943840 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 13:38:41.943924 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 13:38:41.944007 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 13:38:41.944089 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 13:38:41.944172 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 13:38:41.944269 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 13:38:41.944417 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 13:38:41.944526 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 13:38:41.944613 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 13:38:41.944698 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 13:38:41.944796 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 13:38:41.944884 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 13:38:41.944968 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 13:38:41.945051 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 13:38:41.945134 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:38:41.945224 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1b
532 13:38:41.945291 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 13:38:41.945350 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 13:38:41.945405 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 13:38:41.945458 [RTC]rtc_get_frequency_meter,154: input=15, output=834
536 13:38:41.945512 [RTC]rtc_get_frequency_meter,154: input=7, output=709
537 13:38:41.945566 [RTC]rtc_get_frequency_meter,154: input=11, output=772
538 13:38:41.945619 [RTC]rtc_get_frequency_meter,154: input=13, output=802
539 13:38:41.945671 [RTC]rtc_get_frequency_meter,154: input=12, output=787
540 13:38:41.945742 [RTC]rtc_get_frequency_meter,154: input=12, output=787
541 13:38:41.945832 [RTC]rtc_get_frequency_meter,154: input=13, output=803
542 13:38:41.945916 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 13:38:41.946229 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 13:38:41.946325 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 13:38:41.946410 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
546 13:38:41.946494 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 13:38:41.946578 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
548 13:38:41.946660 ADC[4]: Raw value=903031 ID=7
549 13:38:41.946755 ADC[3]: Raw value=213652 ID=1
550 13:38:41.946873 RAM Code: 0x71
551 13:38:41.946987 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 13:38:41.947071 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 13:38:41.947156 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 13:38:41.947251 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 13:38:41.947371 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 13:38:41.947455 in-header: 03 07 00 00 08 00 00 00
557 13:38:41.947538 in-data: aa e4 47 04 13 02 00 00
558 13:38:41.947621 Chrome EC: UHEPI supported
559 13:38:41.947712 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 13:38:41.947804 in-header: 03 a9 00 00 08 00 00 00
561 13:38:41.947891 in-data: 84 60 60 08 00 00 00 00
562 13:38:41.947984 MRC: failed to locate region type 0.
563 13:38:41.948068 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 13:38:41.948152 DRAM-K: Running full calibration
565 13:38:41.948249 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 13:38:41.948337 header.status = 0x0
567 13:38:41.948436 header.version = 0x6 (expected: 0x6)
568 13:38:41.948563 header.size = 0xd00 (expected: 0xd00)
569 13:38:41.948646 header.flags = 0x0
570 13:38:41.948776 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 13:38:41.948879 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
572 13:38:41.948978 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 13:38:41.949061 dram_init: ddr_geometry: 2
574 13:38:41.949144 [EMI] MDL number = 2
575 13:38:41.949251 [EMI] Get MDL freq = 0
576 13:38:41.949354 dram_init: ddr_type: 0
577 13:38:41.949437 is_discrete_lpddr4: 1
578 13:38:41.949536 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 13:38:41.949632
580 13:38:41.949719
581 13:38:41.949811 [Bian_co] ETT version 0.0.0.1
582 13:38:41.949898 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 13:38:41.949959
584 13:38:41.950013 dramc_set_vcore_voltage set vcore to 650000
585 13:38:41.950066 Read voltage for 800, 4
586 13:38:41.950135 Vio18 = 0
587 13:38:41.950217 Vcore = 650000
588 13:38:41.950321 Vdram = 0
589 13:38:41.950377 Vddq = 0
590 13:38:41.950430 Vmddr = 0
591 13:38:41.950483 dram_init: config_dvfs: 1
592 13:38:41.950537 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 13:38:41.950591 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 13:38:41.950644 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
595 13:38:41.950697 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
596 13:38:41.950774 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 13:38:41.950834 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 13:38:41.950889 MEM_TYPE=3, freq_sel=18
599 13:38:41.950978 sv_algorithm_assistance_LP4_1600
600 13:38:41.951031 ============ PULL DRAM RESETB DOWN ============
601 13:38:41.951099 ========== PULL DRAM RESETB DOWN end =========
602 13:38:41.951166 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 13:38:41.951233 ===================================
604 13:38:41.951315 LPDDR4 DRAM CONFIGURATION
605 13:38:41.951400 ===================================
606 13:38:41.951483 EX_ROW_EN[0] = 0x0
607 13:38:41.951566 EX_ROW_EN[1] = 0x0
608 13:38:41.951648 LP4Y_EN = 0x0
609 13:38:41.951739 WORK_FSP = 0x0
610 13:38:41.951802 WL = 0x2
611 13:38:41.951878 RL = 0x2
612 13:38:41.951961 BL = 0x2
613 13:38:41.952043 RPST = 0x0
614 13:38:41.952125 RD_PRE = 0x0
615 13:38:41.952207 WR_PRE = 0x1
616 13:38:41.952289 WR_PST = 0x0
617 13:38:41.952352 DBI_WR = 0x0
618 13:38:41.952436 DBI_RD = 0x0
619 13:38:41.952518 OTF = 0x1
620 13:38:41.952601 ===================================
621 13:38:41.952684 ===================================
622 13:38:41.952775 ANA top config
623 13:38:41.952835 ===================================
624 13:38:41.952921 DLL_ASYNC_EN = 0
625 13:38:41.953003 ALL_SLAVE_EN = 1
626 13:38:41.953086 NEW_RANK_MODE = 1
627 13:38:41.953169 DLL_IDLE_MODE = 1
628 13:38:41.953256 LP45_APHY_COMB_EN = 1
629 13:38:41.953325 TX_ODT_DIS = 1
630 13:38:41.953397 NEW_8X_MODE = 1
631 13:38:41.953481 ===================================
632 13:38:41.953564 ===================================
633 13:38:41.953648 data_rate = 1600
634 13:38:41.953730 CKR = 1
635 13:38:41.953811 DQ_P2S_RATIO = 8
636 13:38:41.953873 ===================================
637 13:38:41.953958 CA_P2S_RATIO = 8
638 13:38:41.954040 DQ_CA_OPEN = 0
639 13:38:41.954123 DQ_SEMI_OPEN = 0
640 13:38:41.954229 CA_SEMI_OPEN = 0
641 13:38:41.954307 CA_FULL_RATE = 0
642 13:38:41.954394 DQ_CKDIV4_EN = 1
643 13:38:41.954478 CA_CKDIV4_EN = 1
644 13:38:41.954560 CA_PREDIV_EN = 0
645 13:38:41.954643 PH8_DLY = 0
646 13:38:41.954725 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 13:38:41.954816 DQ_AAMCK_DIV = 4
648 13:38:41.954965 CA_AAMCK_DIV = 4
649 13:38:41.955115 CA_ADMCK_DIV = 4
650 13:38:41.955212 DQ_TRACK_CA_EN = 0
651 13:38:41.955300 CA_PICK = 800
652 13:38:41.955385 CA_MCKIO = 800
653 13:38:41.955442 MCKIO_SEMI = 0
654 13:38:41.955495 PLL_FREQ = 3068
655 13:38:41.955548 DQ_UI_PI_RATIO = 32
656 13:38:41.955601 CA_UI_PI_RATIO = 0
657 13:38:41.955654 ===================================
658 13:38:41.955708 ===================================
659 13:38:41.955762 memory_type:LPDDR4
660 13:38:41.955836 GP_NUM : 10
661 13:38:41.955898 SRAM_EN : 1
662 13:38:41.955982 MD32_EN : 0
663 13:38:41.956323 ===================================
664 13:38:41.956396 [ANA_INIT] >>>>>>>>>>>>>>
665 13:38:41.956481 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 13:38:41.956567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 13:38:41.956650 ===================================
668 13:38:41.956733 data_rate = 1600,PCW = 0X7600
669 13:38:41.956824 ===================================
670 13:38:41.956887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 13:38:41.956971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 13:38:41.957056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 13:38:41.957140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 13:38:41.957223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 13:38:41.957305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 13:38:41.957383 [ANA_INIT] flow start
677 13:38:41.957458 [ANA_INIT] PLL >>>>>>>>
678 13:38:41.957540 [ANA_INIT] PLL <<<<<<<<
679 13:38:41.957622 [ANA_INIT] MIDPI >>>>>>>>
680 13:38:41.957704 [ANA_INIT] MIDPI <<<<<<<<
681 13:38:41.957787 [ANA_INIT] DLL >>>>>>>>
682 13:38:41.957871 [ANA_INIT] flow end
683 13:38:41.957930 ============ LP4 DIFF to SE enter ============
684 13:38:41.958016 ============ LP4 DIFF to SE exit ============
685 13:38:41.958100 [ANA_INIT] <<<<<<<<<<<<<
686 13:38:41.958210 [Flow] Enable top DCM control >>>>>
687 13:38:41.958281 [Flow] Enable top DCM control <<<<<
688 13:38:41.958339 Enable DLL master slave shuffle
689 13:38:41.958408 ==============================================================
690 13:38:41.958466 Gating Mode config
691 13:38:41.958521 ==============================================================
692 13:38:41.958575 Config description:
693 13:38:41.958628 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 13:38:41.958682 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 13:38:41.958735 SELPH_MODE 0: By rank 1: By Phase
696 13:38:41.958788 ==============================================================
697 13:38:41.958843 GAT_TRACK_EN = 1
698 13:38:41.958913 RX_GATING_MODE = 2
699 13:38:41.958970 RX_GATING_TRACK_MODE = 2
700 13:38:41.959029 SELPH_MODE = 1
701 13:38:41.959118 PICG_EARLY_EN = 1
702 13:38:41.959221 VALID_LAT_VALUE = 1
703 13:38:41.959316 ==============================================================
704 13:38:41.959415 Enter into Gating configuration >>>>
705 13:38:41.959506 Exit from Gating configuration <<<<
706 13:38:41.959593 Enter into DVFS_PRE_config >>>>>
707 13:38:41.959679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 13:38:41.959768 Exit from DVFS_PRE_config <<<<<
709 13:38:41.959851 Enter into PICG configuration >>>>
710 13:38:41.959944 Exit from PICG configuration <<<<
711 13:38:41.960011 [RX_INPUT] configuration >>>>>
712 13:38:41.960070 [RX_INPUT] configuration <<<<<
713 13:38:41.960124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 13:38:41.960179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 13:38:41.960232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 13:38:41.960285 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 13:38:41.960339 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 13:38:41.960407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 13:38:41.960464 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 13:38:41.960522 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 13:38:41.960635 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 13:38:41.960719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 13:38:41.960802 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 13:38:41.960885 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 13:38:41.960962 ===================================
726 13:38:41.961020 LPDDR4 DRAM CONFIGURATION
727 13:38:41.961083 ===================================
728 13:38:41.961167 EX_ROW_EN[0] = 0x0
729 13:38:41.961250 EX_ROW_EN[1] = 0x0
730 13:38:41.961332 LP4Y_EN = 0x0
731 13:38:41.961416 WORK_FSP = 0x0
732 13:38:41.961483 WL = 0x2
733 13:38:41.961540 RL = 0x2
734 13:38:41.961601 BL = 0x2
735 13:38:41.961684 RPST = 0x0
736 13:38:41.961766 RD_PRE = 0x0
737 13:38:41.961848 WR_PRE = 0x1
738 13:38:41.961934 WR_PST = 0x0
739 13:38:41.962000 DBI_WR = 0x0
740 13:38:41.962057 DBI_RD = 0x0
741 13:38:41.962143 OTF = 0x1
742 13:38:41.962241 ===================================
743 13:38:41.962294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 13:38:41.962348 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 13:38:41.962401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 13:38:41.962469 ===================================
747 13:38:41.962525 LPDDR4 DRAM CONFIGURATION
748 13:38:41.962579 ===================================
749 13:38:41.962636 EX_ROW_EN[0] = 0x10
750 13:38:41.962694 EX_ROW_EN[1] = 0x0
751 13:38:41.962747 LP4Y_EN = 0x0
752 13:38:41.962800 WORK_FSP = 0x0
753 13:38:41.962853 WL = 0x2
754 13:38:41.962905 RL = 0x2
755 13:38:41.962970 BL = 0x2
756 13:38:41.963028 RPST = 0x0
757 13:38:41.963081 RD_PRE = 0x0
758 13:38:41.963139 WR_PRE = 0x1
759 13:38:41.963198 WR_PST = 0x0
760 13:38:41.963252 DBI_WR = 0x0
761 13:38:41.963305 DBI_RD = 0x0
762 13:38:41.963357 OTF = 0x1
763 13:38:41.963409 ===================================
764 13:38:41.963471 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 13:38:41.963534 nWR fixed to 40
766 13:38:41.963588 [ModeRegInit_LP4] CH0 RK0
767 13:38:41.963640 [ModeRegInit_LP4] CH0 RK1
768 13:38:41.963700 [ModeRegInit_LP4] CH1 RK0
769 13:38:41.963753 [ModeRegInit_LP4] CH1 RK1
770 13:38:41.963807 match AC timing 13
771 13:38:41.964057 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 13:38:41.964119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 13:38:41.964179 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 13:38:41.964235 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 13:38:41.964289 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 13:38:41.964346 [EMI DOE] emi_dcm 0
777 13:38:41.964400 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 13:38:41.964493 ==
779 13:38:41.964589 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:38:41.964669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:38:41.964727 ==
782 13:38:41.964781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 13:38:41.964835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 13:38:41.964893 [CA 0] Center 37 (7~68) winsize 62
785 13:38:41.964947 [CA 1] Center 37 (6~68) winsize 63
786 13:38:41.965000 [CA 2] Center 34 (4~65) winsize 62
787 13:38:41.965060 [CA 3] Center 34 (4~65) winsize 62
788 13:38:41.965148 [CA 4] Center 33 (3~64) winsize 62
789 13:38:41.965207 [CA 5] Center 33 (3~64) winsize 62
790 13:38:41.965260
791 13:38:41.965312 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 13:38:41.965365
793 13:38:41.965420 [CATrainingPosCal] consider 1 rank data
794 13:38:41.965474 u2DelayCellTimex100 = 270/100 ps
795 13:38:41.965526 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 13:38:41.965579 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
797 13:38:41.965638 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 13:38:41.965697 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 13:38:41.965750 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 13:38:41.965803 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 13:38:41.965856
802 13:38:41.965909 CA PerBit enable=1, Macro0, CA PI delay=33
803 13:38:41.965965
804 13:38:41.966018 [CBTSetCACLKResult] CA Dly = 33
805 13:38:41.966071 CS Dly: 6 (0~37)
806 13:38:41.966147 ==
807 13:38:41.966245 Dram Type= 6, Freq= 0, CH_0, rank 1
808 13:38:41.966301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 13:38:41.966355 ==
810 13:38:41.966408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 13:38:41.966461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 13:38:41.966519 [CA 0] Center 37 (7~68) winsize 62
813 13:38:41.966573 [CA 1] Center 37 (7~68) winsize 62
814 13:38:41.966630 [CA 2] Center 34 (4~65) winsize 62
815 13:38:41.966689 [CA 3] Center 34 (4~65) winsize 62
816 13:38:41.966742 [CA 4] Center 33 (3~64) winsize 62
817 13:38:41.966795 [CA 5] Center 33 (2~64) winsize 63
818 13:38:41.966848
819 13:38:41.966901 [CmdBusTrainingLP45] Vref(ca) range 1: 34
820 13:38:41.966954
821 13:38:41.967006 [CATrainingPosCal] consider 2 rank data
822 13:38:41.967061 u2DelayCellTimex100 = 270/100 ps
823 13:38:41.967115 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
824 13:38:41.967174 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
825 13:38:41.967232 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 13:38:41.967285 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 13:38:41.967338 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
828 13:38:41.967391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 13:38:41.967469
830 13:38:41.967523 CA PerBit enable=1, Macro0, CA PI delay=33
831 13:38:41.967581
832 13:38:41.967634 [CBTSetCACLKResult] CA Dly = 33
833 13:38:41.967691 CS Dly: 6 (0~38)
834 13:38:41.967762
835 13:38:41.967815 ----->DramcWriteLeveling(PI) begin...
836 13:38:41.967870 ==
837 13:38:41.967923 Dram Type= 6, Freq= 0, CH_0, rank 0
838 13:38:41.967976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 13:38:41.968029 ==
840 13:38:41.968083 Write leveling (Byte 0): 31 => 31
841 13:38:41.968138 Write leveling (Byte 1): 31 => 31
842 13:38:41.968191 DramcWriteLeveling(PI) end<-----
843 13:38:41.968277
844 13:38:41.968359 ==
845 13:38:41.968442 Dram Type= 6, Freq= 0, CH_0, rank 0
846 13:38:41.968525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 13:38:41.968608 ==
848 13:38:41.968666 [Gating] SW mode calibration
849 13:38:41.968728 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 13:38:41.968815 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 13:38:41.968898 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 13:38:41.968981 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 13:38:41.969066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
854 13:38:41.969176 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 13:38:41.969292 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:38:41.969417 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:38:41.969543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:38:41.969650 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:38:41.969738 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:38:41.969809 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:38:41.969883 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:38:41.969968 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:38:41.970051 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:38:41.970135 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:38:41.970242 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 13:38:41.970304 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 13:38:41.970362 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 13:38:41.970417 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:38:41.970470 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
870 13:38:41.970523 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
871 13:38:41.970576 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:38:41.970628 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:38:41.970684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:38:41.970738 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 13:38:41.970821 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 13:38:41.970884 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 13:38:41.970939 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
878 13:38:41.970992 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
879 13:38:41.971246 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:38:41.971321 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:38:41.971411 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:38:41.971496 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 13:38:41.971580 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 13:38:41.971694 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 13:38:41.971753 0 10 8 | B1->B0 | 3131 2e2e | 1 0 | (1 1) (0 0)
886 13:38:41.971811 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
887 13:38:41.971908 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:38:41.971992 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:38:41.972076 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:38:41.972160 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 13:38:41.972240 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 13:38:41.972294 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
893 13:38:41.972356 0 11 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
894 13:38:41.972451 0 11 12 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
895 13:38:41.972535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:38:41.972618 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:38:41.972701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:38:41.972779 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 13:38:41.972837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 13:38:41.972906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
901 13:38:41.972992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
902 13:38:41.973076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:38:41.973159 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:38:41.973242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:38:41.973319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:38:41.973378 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:38:41.973457 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:38:41.973542 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:38:41.973626 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:38:41.973709 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:38:41.973791 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:38:41.973871 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:38:41.973933 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:38:41.974038 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 13:38:41.974129 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 13:38:41.974242 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 13:38:41.974296 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 13:38:41.974350 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 13:38:41.974408 Total UI for P1: 0, mck2ui 16
920 13:38:41.974472 best dqsien dly found for B0: ( 0, 14, 8)
921 13:38:41.974539 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 13:38:41.974593 Total UI for P1: 0, mck2ui 16
923 13:38:41.974646 best dqsien dly found for B1: ( 0, 14, 12)
924 13:38:41.974698 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
925 13:38:41.974751 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
926 13:38:41.974804
927 13:38:41.974857 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 13:38:41.974913 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
929 13:38:41.974966 [Gating] SW calibration Done
930 13:38:41.975043 ==
931 13:38:41.975153 Dram Type= 6, Freq= 0, CH_0, rank 0
932 13:38:41.975265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 13:38:41.975361 ==
934 13:38:41.975416 RX Vref Scan: 0
935 13:38:41.975474
936 13:38:41.975572 RX Vref 0 -> 0, step: 1
937 13:38:41.975655
938 13:38:41.975738 RX Delay -130 -> 252, step: 16
939 13:38:41.975821 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 13:38:41.975904 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 13:38:41.975982 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 13:38:41.976062 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 13:38:41.976150 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 13:38:41.976233 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 13:38:41.976316 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 13:38:41.976398 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
947 13:38:41.976480 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 13:38:41.976566 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 13:38:41.976661 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 13:38:41.976744 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 13:38:41.976827 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 13:38:41.976909 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 13:38:41.976992 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 13:38:41.977071 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 13:38:41.977139 ==
956 13:38:41.977205 Dram Type= 6, Freq= 0, CH_0, rank 0
957 13:38:41.977289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 13:38:41.977383 ==
959 13:38:41.977480 DQS Delay:
960 13:38:41.977566 DQS0 = 0, DQS1 = 0
961 13:38:41.977658 DQM Delay:
962 13:38:41.977745 DQM0 = 85, DQM1 = 71
963 13:38:41.977828 DQ Delay:
964 13:38:41.977911 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
965 13:38:41.977993 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
966 13:38:41.978077 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
967 13:38:41.978192 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 13:38:41.978265
969 13:38:41.978348
970 13:38:41.978430 ==
971 13:38:41.978513 Dram Type= 6, Freq= 0, CH_0, rank 0
972 13:38:41.978591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 13:38:41.978648 ==
974 13:38:41.978718
975 13:38:41.978771
976 13:38:41.978832 TX Vref Scan disable
977 13:38:41.978886 == TX Byte 0 ==
978 13:38:41.978939 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 13:38:41.978992 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 13:38:41.979045 == TX Byte 1 ==
981 13:38:41.979103 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
982 13:38:41.979157 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
983 13:38:41.979227 ==
984 13:38:41.979282 Dram Type= 6, Freq= 0, CH_0, rank 0
985 13:38:41.979343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 13:38:41.979397 ==
987 13:38:41.979645 TX Vref=22, minBit 5, minWin=27, winSum=442
988 13:38:41.979737 TX Vref=24, minBit 5, minWin=27, winSum=445
989 13:38:41.979823 TX Vref=26, minBit 5, minWin=27, winSum=448
990 13:38:41.979881 TX Vref=28, minBit 0, minWin=28, winSum=448
991 13:38:41.979935 TX Vref=30, minBit 4, minWin=27, winSum=445
992 13:38:41.979988 TX Vref=32, minBit 4, minWin=27, winSum=447
993 13:38:41.980042 [TxChooseVref] Worse bit 0, Min win 28, Win sum 448, Final Vref 28
994 13:38:41.980101
995 13:38:41.980154 Final TX Range 1 Vref 28
996 13:38:41.980226
997 13:38:41.980282 ==
998 13:38:41.980345 Dram Type= 6, Freq= 0, CH_0, rank 0
999 13:38:41.980429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 13:38:41.980512 ==
1001 13:38:41.980590
1002 13:38:41.980645
1003 13:38:41.980699 TX Vref Scan disable
1004 13:38:41.980797 == TX Byte 0 ==
1005 13:38:41.980872 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 13:38:41.980956 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 13:38:41.981070 == TX Byte 1 ==
1008 13:38:41.981154 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1009 13:38:41.981248 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1010 13:38:41.981332
1011 13:38:41.981418 [DATLAT]
1012 13:38:41.981500 Freq=800, CH0 RK0
1013 13:38:41.981583
1014 13:38:41.981666 DATLAT Default: 0xa
1015 13:38:41.981758 0, 0xFFFF, sum = 0
1016 13:38:41.981846 1, 0xFFFF, sum = 0
1017 13:38:41.981931 2, 0xFFFF, sum = 0
1018 13:38:41.982015 3, 0xFFFF, sum = 0
1019 13:38:41.982100 4, 0xFFFF, sum = 0
1020 13:38:41.982220 5, 0xFFFF, sum = 0
1021 13:38:41.982320 6, 0xFFFF, sum = 0
1022 13:38:41.982384 7, 0xFFFF, sum = 0
1023 13:38:41.982439 8, 0xFFFF, sum = 0
1024 13:38:41.982498 9, 0x0, sum = 1
1025 13:38:41.982579 10, 0x0, sum = 2
1026 13:38:41.982653 11, 0x0, sum = 3
1027 13:38:41.982708 12, 0x0, sum = 4
1028 13:38:41.982783 best_step = 10
1029 13:38:41.982838
1030 13:38:41.982898 ==
1031 13:38:41.982951 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 13:38:41.983004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 13:38:41.983056 ==
1034 13:38:41.983111 RX Vref Scan: 1
1035 13:38:41.983164
1036 13:38:41.983216 Set Vref Range= 32 -> 127
1037 13:38:41.983284
1038 13:38:41.983339 RX Vref 32 -> 127, step: 1
1039 13:38:41.983398
1040 13:38:41.983451 RX Delay -111 -> 252, step: 8
1041 13:38:41.983503
1042 13:38:41.983555 Set Vref, RX VrefLevel [Byte0]: 32
1043 13:38:41.983610 [Byte1]: 32
1044 13:38:41.983663
1045 13:38:41.983714 Set Vref, RX VrefLevel [Byte0]: 33
1046 13:38:41.983776 [Byte1]: 33
1047 13:38:41.983864
1048 13:38:41.983949 Set Vref, RX VrefLevel [Byte0]: 34
1049 13:38:41.984030 [Byte1]: 34
1050 13:38:41.984112
1051 13:38:41.984197 Set Vref, RX VrefLevel [Byte0]: 35
1052 13:38:41.984297 [Byte1]: 35
1053 13:38:41.984380
1054 13:38:41.984464 Set Vref, RX VrefLevel [Byte0]: 36
1055 13:38:41.984546 [Byte1]: 36
1056 13:38:41.984628
1057 13:38:41.984709 Set Vref, RX VrefLevel [Byte0]: 37
1058 13:38:41.984794 [Byte1]: 37
1059 13:38:41.984881
1060 13:38:41.984965 Set Vref, RX VrefLevel [Byte0]: 38
1061 13:38:41.985046 [Byte1]: 38
1062 13:38:41.985127
1063 13:38:41.985210 Set Vref, RX VrefLevel [Byte0]: 39
1064 13:38:41.985296 [Byte1]: 39
1065 13:38:41.985386
1066 13:38:41.985484 Set Vref, RX VrefLevel [Byte0]: 40
1067 13:38:41.985584 [Byte1]: 40
1068 13:38:41.985692
1069 13:38:41.985794 Set Vref, RX VrefLevel [Byte0]: 41
1070 13:38:41.985891 [Byte1]: 41
1071 13:38:41.985977
1072 13:38:41.986059 Set Vref, RX VrefLevel [Byte0]: 42
1073 13:38:41.986141 [Byte1]: 42
1074 13:38:41.986266
1075 13:38:41.986357 Set Vref, RX VrefLevel [Byte0]: 43
1076 13:38:41.986444 [Byte1]: 43
1077 13:38:41.986525
1078 13:38:41.986606 Set Vref, RX VrefLevel [Byte0]: 44
1079 13:38:41.986690 [Byte1]: 44
1080 13:38:41.986770
1081 13:38:41.986859 Set Vref, RX VrefLevel [Byte0]: 45
1082 13:38:41.986920 [Byte1]: 45
1083 13:38:41.986974
1084 13:38:41.987026 Set Vref, RX VrefLevel [Byte0]: 46
1085 13:38:41.987078 [Byte1]: 46
1086 13:38:41.987130
1087 13:38:41.987199 Set Vref, RX VrefLevel [Byte0]: 47
1088 13:38:41.987283 [Byte1]: 47
1089 13:38:41.987384
1090 13:38:41.987471 Set Vref, RX VrefLevel [Byte0]: 48
1091 13:38:41.987552 [Byte1]: 48
1092 13:38:41.987632
1093 13:38:41.987715 Set Vref, RX VrefLevel [Byte0]: 49
1094 13:38:41.987796 [Byte1]: 49
1095 13:38:41.987885
1096 13:38:41.987950 Set Vref, RX VrefLevel [Byte0]: 50
1097 13:38:41.988003 [Byte1]: 50
1098 13:38:41.988056
1099 13:38:41.988108 Set Vref, RX VrefLevel [Byte0]: 51
1100 13:38:41.988160 [Byte1]: 51
1101 13:38:41.988216
1102 13:38:41.988267 Set Vref, RX VrefLevel [Byte0]: 52
1103 13:38:41.988318 [Byte1]: 52
1104 13:38:41.988369
1105 13:38:41.988431 Set Vref, RX VrefLevel [Byte0]: 53
1106 13:38:41.988485 [Byte1]: 53
1107 13:38:41.988537
1108 13:38:41.988588 Set Vref, RX VrefLevel [Byte0]: 54
1109 13:38:41.988640 [Byte1]: 54
1110 13:38:41.988696
1111 13:38:41.988747 Set Vref, RX VrefLevel [Byte0]: 55
1112 13:38:41.988799 [Byte1]: 55
1113 13:38:41.988851
1114 13:38:41.988905 Set Vref, RX VrefLevel [Byte0]: 56
1115 13:38:41.988963 [Byte1]: 56
1116 13:38:41.989016
1117 13:38:41.989067 Set Vref, RX VrefLevel [Byte0]: 57
1118 13:38:41.989119 [Byte1]: 57
1119 13:38:41.989173
1120 13:38:41.989225 Set Vref, RX VrefLevel [Byte0]: 58
1121 13:38:41.989277 [Byte1]: 58
1122 13:38:41.989347
1123 13:38:41.989428 Set Vref, RX VrefLevel [Byte0]: 59
1124 13:38:41.989493 [Byte1]: 59
1125 13:38:41.989555
1126 13:38:41.989607 Set Vref, RX VrefLevel [Byte0]: 60
1127 13:38:41.989659 [Byte1]: 60
1128 13:38:41.989740
1129 13:38:41.989821 Set Vref, RX VrefLevel [Byte0]: 61
1130 13:38:41.989902 [Byte1]: 61
1131 13:38:41.989986
1132 13:38:41.990070 Set Vref, RX VrefLevel [Byte0]: 62
1133 13:38:41.990151 [Byte1]: 62
1134 13:38:41.990282
1135 13:38:41.990361 Set Vref, RX VrefLevel [Byte0]: 63
1136 13:38:41.990421 [Byte1]: 63
1137 13:38:41.990475
1138 13:38:41.990564 Set Vref, RX VrefLevel [Byte0]: 64
1139 13:38:41.990620 [Byte1]: 64
1140 13:38:41.990676
1141 13:38:41.990751 Set Vref, RX VrefLevel [Byte0]: 65
1142 13:38:41.990805 [Byte1]: 65
1143 13:38:41.990884
1144 13:38:41.990958 Set Vref, RX VrefLevel [Byte0]: 66
1145 13:38:41.991036 [Byte1]: 66
1146 13:38:41.991136
1147 13:38:41.991228 Set Vref, RX VrefLevel [Byte0]: 67
1148 13:38:41.991286 [Byte1]: 67
1149 13:38:41.991341
1150 13:38:41.991393 Set Vref, RX VrefLevel [Byte0]: 68
1151 13:38:41.991450 [Byte1]: 68
1152 13:38:41.991503
1153 13:38:41.991555 Set Vref, RX VrefLevel [Byte0]: 69
1154 13:38:41.991804 [Byte1]: 69
1155 13:38:41.991864
1156 13:38:41.991917 Set Vref, RX VrefLevel [Byte0]: 70
1157 13:38:41.991977 [Byte1]: 70
1158 13:38:41.992031
1159 13:38:41.992083 Set Vref, RX VrefLevel [Byte0]: 71
1160 13:38:41.992136 [Byte1]: 71
1161 13:38:41.992194
1162 13:38:41.992249 Set Vref, RX VrefLevel [Byte0]: 72
1163 13:38:41.992301 [Byte1]: 72
1164 13:38:41.992352
1165 13:38:41.992404 Set Vref, RX VrefLevel [Byte0]: 73
1166 13:38:41.992459 [Byte1]: 73
1167 13:38:41.992513
1168 13:38:41.992565 Set Vref, RX VrefLevel [Byte0]: 74
1169 13:38:41.992616 [Byte1]: 74
1170 13:38:41.992671
1171 13:38:41.992726 Set Vref, RX VrefLevel [Byte0]: 75
1172 13:38:41.992817 [Byte1]: 75
1173 13:38:41.992868
1174 13:38:41.992920 Set Vref, RX VrefLevel [Byte0]: 76
1175 13:38:41.992976 [Byte1]: 76
1176 13:38:41.993029
1177 13:38:41.993080 Set Vref, RX VrefLevel [Byte0]: 77
1178 13:38:41.993131 [Byte1]: 77
1179 13:38:41.993187
1180 13:38:41.993239 Set Vref, RX VrefLevel [Byte0]: 78
1181 13:38:41.993297 [Byte1]: 78
1182 13:38:41.993350
1183 13:38:41.993401 Set Vref, RX VrefLevel [Byte0]: 79
1184 13:38:41.993453 [Byte1]: 79
1185 13:38:41.993511
1186 13:38:41.993563 Set Vref, RX VrefLevel [Byte0]: 80
1187 13:38:41.993614 [Byte1]: 80
1188 13:38:41.993668
1189 13:38:41.993751 Set Vref, RX VrefLevel [Byte0]: 81
1190 13:38:41.993833 [Byte1]: 81
1191 13:38:41.993888
1192 13:38:41.993939 Final RX Vref Byte 0 = 66 to rank0
1193 13:38:41.994027 Final RX Vref Byte 1 = 52 to rank0
1194 13:38:41.994119 Final RX Vref Byte 0 = 66 to rank1
1195 13:38:41.994242 Final RX Vref Byte 1 = 52 to rank1==
1196 13:38:41.994339 Dram Type= 6, Freq= 0, CH_0, rank 0
1197 13:38:41.994423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 13:38:41.994477 ==
1199 13:38:41.994550 DQS Delay:
1200 13:38:41.994603 DQS0 = 0, DQS1 = 0
1201 13:38:41.994656 DQM Delay:
1202 13:38:41.994732 DQM0 = 87, DQM1 = 76
1203 13:38:41.994823 DQ Delay:
1204 13:38:41.994907 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1205 13:38:41.994989 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1206 13:38:41.995073 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1207 13:38:41.995155 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1208 13:38:41.995238
1209 13:38:41.995328
1210 13:38:41.995413 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1211 13:38:41.995495 CH0 RK0: MR19=606, MR18=4627
1212 13:38:41.995581 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1213 13:38:41.995663
1214 13:38:41.995746 ----->DramcWriteLeveling(PI) begin...
1215 13:38:41.995869 ==
1216 13:38:41.995952 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 13:38:41.996039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 13:38:41.996137 ==
1219 13:38:41.996230 Write leveling (Byte 0): 35 => 35
1220 13:38:41.996321 Write leveling (Byte 1): 30 => 30
1221 13:38:41.996438 DramcWriteLeveling(PI) end<-----
1222 13:38:41.996519
1223 13:38:41.996603 ==
1224 13:38:41.996685 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 13:38:41.996768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 13:38:41.996861 ==
1227 13:38:41.996943 [Gating] SW mode calibration
1228 13:38:41.997026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1229 13:38:41.997112 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1230 13:38:41.997195 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1231 13:38:41.997279 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1232 13:38:41.997372 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1233 13:38:41.997496 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1234 13:38:41.997582 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:38:41.997666 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:38:41.997749 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:38:41.997840 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:38:41.997924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:38:41.998006 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:38:41.998088 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:38:41.998192 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:38:41.998261 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:38:41.998320 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:38:41.998388 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:38:41.998441 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:38:41.998494 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1247 13:38:41.998546 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1248 13:38:41.998630 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1249 13:38:41.998725 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 13:38:41.998777 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 13:38:41.998843 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 13:38:41.998903 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 13:38:41.998956 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 13:38:41.999014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 13:38:41.999111 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:38:41.999173 0 9 8 | B1->B0 | 2322 3232 | 1 0 | (0 0) (1 1)
1257 13:38:41.999226 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1258 13:38:41.999278 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 13:38:41.999353 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 13:38:41.999408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 13:38:41.999460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 13:38:41.999511 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 13:38:41.999563 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1264 13:38:41.999620 0 10 8 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)
1265 13:38:41.999676 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 13:38:41.999728 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 13:38:41.999780 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 13:38:42.000049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 13:38:42.000115 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 13:38:42.000170 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 13:38:42.000223 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 13:38:42.000307 0 11 8 | B1->B0 | 2b2b 4040 | 0 0 | (0 0) (0 0)
1273 13:38:42.000439 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 13:38:42.000495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 13:38:42.000548 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 13:38:42.000601 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 13:38:42.000659 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 13:38:42.000725 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 13:38:42.000790 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 13:38:42.000848 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1281 13:38:42.000901 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:38:42.000953 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 13:38:42.001050 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 13:38:42.001118 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 13:38:42.001177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 13:38:42.001229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 13:38:42.001329 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 13:38:42.001432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 13:38:42.001544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 13:38:42.001700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 13:38:42.001800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 13:38:42.001866 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 13:38:42.001926 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 13:38:42.001979 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 13:38:42.002054 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 13:38:42.002158 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1297 13:38:42.002229 Total UI for P1: 0, mck2ui 16
1298 13:38:42.002284 best dqsien dly found for B0: ( 0, 14, 6)
1299 13:38:42.002355 Total UI for P1: 0, mck2ui 16
1300 13:38:42.002409 best dqsien dly found for B1: ( 0, 14, 6)
1301 13:38:42.002467 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1302 13:38:42.002521 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1303 13:38:42.002573
1304 13:38:42.002624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1305 13:38:42.002680 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1306 13:38:42.002733 [Gating] SW calibration Done
1307 13:38:42.002785 ==
1308 13:38:42.002839 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 13:38:42.002892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 13:38:42.002996 ==
1311 13:38:42.003095 RX Vref Scan: 0
1312 13:38:42.003177
1313 13:38:42.003235 RX Vref 0 -> 0, step: 1
1314 13:38:42.003288
1315 13:38:42.003342 RX Delay -130 -> 252, step: 16
1316 13:38:42.003396 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1317 13:38:42.003448 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 13:38:42.003539 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1319 13:38:42.003594 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 13:38:42.003647 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 13:38:42.003761 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 13:38:42.003816 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1323 13:38:42.003869 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1324 13:38:42.003924 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 13:38:42.003977 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 13:38:42.004029 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 13:38:42.004111 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 13:38:42.004194 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 13:38:42.004250 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 13:38:42.004302 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 13:38:42.004355 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1332 13:38:42.004409 ==
1333 13:38:42.004462 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 13:38:42.004513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 13:38:42.004566 ==
1336 13:38:42.004622 DQS Delay:
1337 13:38:42.004674 DQS0 = 0, DQS1 = 0
1338 13:38:42.004731 DQM Delay:
1339 13:38:42.004783 DQM0 = 84, DQM1 = 77
1340 13:38:42.004835 DQ Delay:
1341 13:38:42.004886 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1342 13:38:42.004957 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1343 13:38:42.005048 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1344 13:38:42.005100 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1345 13:38:42.005160
1346 13:38:42.005219
1347 13:38:42.005272 ==
1348 13:38:42.005323 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 13:38:42.005375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 13:38:42.005432 ==
1351 13:38:42.005484
1352 13:38:42.005535
1353 13:38:42.005586 TX Vref Scan disable
1354 13:38:42.005638 == TX Byte 0 ==
1355 13:38:42.005727 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1356 13:38:42.005815 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1357 13:38:42.005868 == TX Byte 1 ==
1358 13:38:42.005925 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1359 13:38:42.005978 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1360 13:38:42.006030 ==
1361 13:38:42.006082 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 13:38:42.006136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 13:38:42.006235 ==
1364 13:38:42.006291 TX Vref=22, minBit 3, minWin=27, winSum=442
1365 13:38:42.006344 TX Vref=24, minBit 5, minWin=27, winSum=444
1366 13:38:42.006399 TX Vref=26, minBit 5, minWin=27, winSum=447
1367 13:38:42.006451 TX Vref=28, minBit 3, minWin=27, winSum=447
1368 13:38:42.006502 TX Vref=30, minBit 9, minWin=27, winSum=448
1369 13:38:42.006554 TX Vref=32, minBit 8, minWin=27, winSum=444
1370 13:38:42.006606 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 30
1371 13:38:42.006658
1372 13:38:42.006712 Final TX Range 1 Vref 30
1373 13:38:42.006770
1374 13:38:42.006844 ==
1375 13:38:42.006962 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 13:38:42.007093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 13:38:42.007192 ==
1378 13:38:42.007276
1379 13:38:42.007329
1380 13:38:42.007381 TX Vref Scan disable
1381 13:38:42.007433 == TX Byte 0 ==
1382 13:38:42.007488 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1383 13:38:42.007540 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1384 13:38:42.007610 == TX Byte 1 ==
1385 13:38:42.007924 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1386 13:38:42.007988 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1387 13:38:42.008041
1388 13:38:42.008092 [DATLAT]
1389 13:38:42.008148 Freq=800, CH0 RK1
1390 13:38:42.008201
1391 13:38:42.008261 DATLAT Default: 0xa
1392 13:38:42.008315 0, 0xFFFF, sum = 0
1393 13:38:42.008368 1, 0xFFFF, sum = 0
1394 13:38:42.008420 2, 0xFFFF, sum = 0
1395 13:38:42.008472 3, 0xFFFF, sum = 0
1396 13:38:42.008524 4, 0xFFFF, sum = 0
1397 13:38:42.008575 5, 0xFFFF, sum = 0
1398 13:38:42.008630 6, 0xFFFF, sum = 0
1399 13:38:42.008683 7, 0xFFFF, sum = 0
1400 13:38:42.008740 8, 0xFFFF, sum = 0
1401 13:38:42.008808 9, 0x0, sum = 1
1402 13:38:42.008896 10, 0x0, sum = 2
1403 13:38:42.009047 11, 0x0, sum = 3
1404 13:38:42.009144 12, 0x0, sum = 4
1405 13:38:42.009227 best_step = 10
1406 13:38:42.009292
1407 13:38:42.009372 ==
1408 13:38:42.009453 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 13:38:42.009534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 13:38:42.009615 ==
1411 13:38:42.009752 RX Vref Scan: 0
1412 13:38:42.009866
1413 13:38:42.009976 RX Vref 0 -> 0, step: 1
1414 13:38:42.010056
1415 13:38:42.010137 RX Delay -111 -> 252, step: 8
1416 13:38:42.010245 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1417 13:38:42.010335 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1418 13:38:42.010420 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1419 13:38:42.010472 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1420 13:38:42.010524 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1421 13:38:42.010574 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1422 13:38:42.010625 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1423 13:38:42.010681 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1424 13:38:42.010739 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1425 13:38:42.010822 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1426 13:38:42.010899 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1427 13:38:42.010952 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1428 13:38:42.011033 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1429 13:38:42.011122 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1430 13:38:42.011178 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1431 13:38:42.011230 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1432 13:38:42.011284 ==
1433 13:38:42.011340 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 13:38:42.011392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 13:38:42.011443 ==
1436 13:38:42.011494 DQS Delay:
1437 13:38:42.011545 DQS0 = 0, DQS1 = 0
1438 13:38:42.011596 DQM Delay:
1439 13:38:42.011654 DQM0 = 86, DQM1 = 77
1440 13:38:42.011741 DQ Delay:
1441 13:38:42.011812 DQ0 =84, DQ1 =88, DQ2 =76, DQ3 =84
1442 13:38:42.011916 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1443 13:38:42.012014 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1444 13:38:42.012116 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 13:38:42.012222
1446 13:38:42.012339
1447 13:38:42.012431 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1448 13:38:42.012530 CH0 RK1: MR19=606, MR18=4208
1449 13:38:42.012613 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 13:38:42.012695 [RxdqsGatingPostProcess] freq 800
1451 13:38:42.012777 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 13:38:42.012838 Pre-setting of DQS Precalculation
1453 13:38:42.012891 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 13:38:42.012943 ==
1455 13:38:42.013002 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 13:38:42.013142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 13:38:42.013202 ==
1458 13:38:42.013260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 13:38:42.013333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 13:38:42.013387 [CA 0] Center 36 (6~67) winsize 62
1461 13:38:42.013447 [CA 1] Center 36 (6~67) winsize 62
1462 13:38:42.013510 [CA 2] Center 34 (4~65) winsize 62
1463 13:38:42.013561 [CA 3] Center 34 (3~65) winsize 63
1464 13:38:42.013613 [CA 4] Center 34 (4~65) winsize 62
1465 13:38:42.013664 [CA 5] Center 34 (4~65) winsize 62
1466 13:38:42.013745
1467 13:38:42.013804 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1468 13:38:42.013859
1469 13:38:42.013942 [CATrainingPosCal] consider 1 rank data
1470 13:38:42.014023 u2DelayCellTimex100 = 270/100 ps
1471 13:38:42.014104 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 13:38:42.014219 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 13:38:42.014305 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 13:38:42.014390 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 13:38:42.014471 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 13:38:42.014551 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 13:38:42.014630
1478 13:38:42.014710 CA PerBit enable=1, Macro0, CA PI delay=34
1479 13:38:42.014794
1480 13:38:42.014882 [CBTSetCACLKResult] CA Dly = 34
1481 13:38:42.014974 CS Dly: 5 (0~36)
1482 13:38:42.015087 ==
1483 13:38:42.015168 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 13:38:42.015250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 13:38:42.015315 ==
1486 13:38:42.015409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 13:38:42.015472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 13:38:42.015525 [CA 0] Center 36 (6~67) winsize 62
1489 13:38:42.015577 [CA 1] Center 36 (6~67) winsize 62
1490 13:38:42.015628 [CA 2] Center 34 (4~65) winsize 62
1491 13:38:42.015679 [CA 3] Center 34 (3~65) winsize 63
1492 13:38:42.015730 [CA 4] Center 34 (4~65) winsize 62
1493 13:38:42.015819 [CA 5] Center 34 (3~65) winsize 63
1494 13:38:42.015902
1495 13:38:42.015984 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1496 13:38:42.016063
1497 13:38:42.016144 [CATrainingPosCal] consider 2 rank data
1498 13:38:42.016223 u2DelayCellTimex100 = 270/100 ps
1499 13:38:42.016305 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 13:38:42.016372 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 13:38:42.016456 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 13:38:42.016537 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1503 13:38:42.016617 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 13:38:42.016708 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1505 13:38:42.016763
1506 13:38:42.016819 CA PerBit enable=1, Macro0, CA PI delay=34
1507 13:38:42.016884
1508 13:38:42.016968 [CBTSetCACLKResult] CA Dly = 34
1509 13:38:42.017048 CS Dly: 6 (0~38)
1510 13:38:42.017128
1511 13:38:42.017216 ----->DramcWriteLeveling(PI) begin...
1512 13:38:42.017278 ==
1513 13:38:42.017343 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 13:38:42.017442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 13:38:42.017524 ==
1516 13:38:42.017605 Write leveling (Byte 0): 26 => 26
1517 13:38:42.017685 Write leveling (Byte 1): 29 => 29
1518 13:38:42.017988 DramcWriteLeveling(PI) end<-----
1519 13:38:42.018099
1520 13:38:42.018203 ==
1521 13:38:42.018259 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 13:38:42.018312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 13:38:42.018374 ==
1524 13:38:42.018430 [Gating] SW mode calibration
1525 13:38:42.018489 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 13:38:42.018543 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 13:38:42.018595 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1528 13:38:42.018647 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1529 13:38:42.018699 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:38:42.018751 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:38:42.018802 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:38:42.018860 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:38:42.018917 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:38:42.018997 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:38:42.019096 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:38:42.019199 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:38:42.019255 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:38:42.019353 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:38:42.019440 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:38:42.019538 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:38:42.019620 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:38:42.019701 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:38:42.019782 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1544 13:38:42.019866 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1545 13:38:42.019961 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1546 13:38:42.020059 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 13:38:42.020113 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 13:38:42.020164 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 13:38:42.020216 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 13:38:42.020267 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 13:38:42.020344 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 13:38:42.020399 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1553 13:38:42.020451 0 9 8 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 1)
1554 13:38:42.020503 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 13:38:42.020562 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 13:38:42.020660 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 13:38:42.020716 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 13:38:42.020768 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 13:38:42.020820 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 13:38:42.020905 0 10 4 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 1)
1561 13:38:42.020986 0 10 8 | B1->B0 | 2d2d 2626 | 0 0 | (1 1) (1 1)
1562 13:38:42.021070 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 13:38:42.021153 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 13:38:42.021234 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 13:38:42.021315 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 13:38:42.021399 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 13:38:42.021481 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 13:38:42.021583 0 11 4 | B1->B0 | 2727 2727 | 1 0 | (0 0) (0 0)
1569 13:38:42.021680 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1570 13:38:42.021817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 13:38:42.021946 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 13:38:42.022042 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 13:38:42.022130 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 13:38:42.022219 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 13:38:42.022273 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1576 13:38:42.022325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 13:38:42.022397 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:38:42.022481 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:38:42.022546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 13:38:42.022636 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 13:38:42.022689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 13:38:42.022740 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 13:38:42.022792 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 13:38:42.022843 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 13:38:42.022900 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 13:38:42.022952 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 13:38:42.023004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 13:38:42.023055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 13:38:42.023147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 13:38:42.023239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 13:38:42.023347 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 13:38:42.023473 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1593 13:38:42.023554 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1594 13:38:42.023609 Total UI for P1: 0, mck2ui 16
1595 13:38:42.023666 best dqsien dly found for B0: ( 0, 14, 4)
1596 13:38:42.023734 Total UI for P1: 0, mck2ui 16
1597 13:38:42.023799 best dqsien dly found for B1: ( 0, 14, 4)
1598 13:38:42.023850 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1599 13:38:42.023902 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1600 13:38:42.023971
1601 13:38:42.024038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 13:38:42.024090 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1603 13:38:42.024150 [Gating] SW calibration Done
1604 13:38:42.024204 ==
1605 13:38:42.024256 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 13:38:42.024506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 13:38:42.024579 ==
1608 13:38:42.024653 RX Vref Scan: 0
1609 13:38:42.024709
1610 13:38:42.024761 RX Vref 0 -> 0, step: 1
1611 13:38:42.024813
1612 13:38:42.024864 RX Delay -130 -> 252, step: 16
1613 13:38:42.024915 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 13:38:42.024971 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 13:38:42.025024 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 13:38:42.025076 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 13:38:42.025130 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 13:38:42.025186 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 13:38:42.025239 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 13:38:42.025319 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 13:38:42.025370 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 13:38:42.025421 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 13:38:42.025475 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1624 13:38:42.025528 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 13:38:42.025580 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 13:38:42.025630 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 13:38:42.025713 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 13:38:42.025795 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1629 13:38:42.025876 ==
1630 13:38:42.025990 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 13:38:42.026072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 13:38:42.026153 ==
1633 13:38:42.026253 DQS Delay:
1634 13:38:42.026306 DQS0 = 0, DQS1 = 0
1635 13:38:42.026358 DQM Delay:
1636 13:38:42.026413 DQM0 = 89, DQM1 = 79
1637 13:38:42.026465 DQ Delay:
1638 13:38:42.026522 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 13:38:42.026574 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 13:38:42.026642 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1641 13:38:42.026713 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1642 13:38:42.026765
1643 13:38:42.026816
1644 13:38:42.026867 ==
1645 13:38:42.026918 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 13:38:42.026974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 13:38:42.027033 ==
1648 13:38:42.027085
1649 13:38:42.027151
1650 13:38:42.027210 TX Vref Scan disable
1651 13:38:42.027264 == TX Byte 0 ==
1652 13:38:42.027316 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1653 13:38:42.027370 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1654 13:38:42.027451 == TX Byte 1 ==
1655 13:38:42.027510 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1656 13:38:42.027567 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1657 13:38:42.027620 ==
1658 13:38:42.027673 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 13:38:42.027744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 13:38:42.027796 ==
1661 13:38:42.027846 TX Vref=22, minBit 11, minWin=26, winSum=438
1662 13:38:42.027898 TX Vref=24, minBit 0, minWin=27, winSum=449
1663 13:38:42.027963 TX Vref=26, minBit 8, minWin=27, winSum=449
1664 13:38:42.028034 TX Vref=28, minBit 9, minWin=27, winSum=450
1665 13:38:42.028090 TX Vref=30, minBit 9, minWin=27, winSum=451
1666 13:38:42.028169 TX Vref=32, minBit 9, minWin=27, winSum=449
1667 13:38:42.028276 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 30
1668 13:38:42.028371
1669 13:38:42.028453 Final TX Range 1 Vref 30
1670 13:38:42.028541
1671 13:38:42.028653 ==
1672 13:38:42.028750 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 13:38:42.028831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 13:38:42.028912 ==
1675 13:38:42.028991
1676 13:38:42.029075
1677 13:38:42.029155 TX Vref Scan disable
1678 13:38:42.029238 == TX Byte 0 ==
1679 13:38:42.029319 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1680 13:38:42.029400 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1681 13:38:42.029480 == TX Byte 1 ==
1682 13:38:42.029566 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1683 13:38:42.029647 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1684 13:38:42.029730
1685 13:38:42.029810 [DATLAT]
1686 13:38:42.029890 Freq=800, CH1 RK0
1687 13:38:42.029985
1688 13:38:42.030071 DATLAT Default: 0xa
1689 13:38:42.030154 0, 0xFFFF, sum = 0
1690 13:38:42.030240 1, 0xFFFF, sum = 0
1691 13:38:42.030294 2, 0xFFFF, sum = 0
1692 13:38:42.030345 3, 0xFFFF, sum = 0
1693 13:38:42.030397 4, 0xFFFF, sum = 0
1694 13:38:42.030449 5, 0xFFFF, sum = 0
1695 13:38:42.030501 6, 0xFFFF, sum = 0
1696 13:38:42.030559 7, 0xFFFF, sum = 0
1697 13:38:42.030612 8, 0xFFFF, sum = 0
1698 13:38:42.030667 9, 0x0, sum = 1
1699 13:38:42.030761 10, 0x0, sum = 2
1700 13:38:42.030814 11, 0x0, sum = 3
1701 13:38:42.030866 12, 0x0, sum = 4
1702 13:38:42.030918 best_step = 10
1703 13:38:42.030968
1704 13:38:42.031019 ==
1705 13:38:42.031075 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 13:38:42.031129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 13:38:42.031182 ==
1708 13:38:42.031236 RX Vref Scan: 1
1709 13:38:42.031318
1710 13:38:42.031369 Set Vref Range= 32 -> 127
1711 13:38:42.031420
1712 13:38:42.031470 RX Vref 32 -> 127, step: 1
1713 13:38:42.031522
1714 13:38:42.031579 RX Delay -95 -> 252, step: 8
1715 13:38:42.031631
1716 13:38:42.031686 Set Vref, RX VrefLevel [Byte0]: 32
1717 13:38:42.031742 [Byte1]: 32
1718 13:38:42.031823
1719 13:38:42.031903 Set Vref, RX VrefLevel [Byte0]: 33
1720 13:38:42.032014 [Byte1]: 33
1721 13:38:42.032073
1722 13:38:42.032124 Set Vref, RX VrefLevel [Byte0]: 34
1723 13:38:42.032176 [Byte1]: 34
1724 13:38:42.032226
1725 13:38:42.032283 Set Vref, RX VrefLevel [Byte0]: 35
1726 13:38:42.032338 [Byte1]: 35
1727 13:38:42.032390
1728 13:38:42.032440 Set Vref, RX VrefLevel [Byte0]: 36
1729 13:38:42.032490 [Byte1]: 36
1730 13:38:42.032560
1731 13:38:42.032657 Set Vref, RX VrefLevel [Byte0]: 37
1732 13:38:42.032782 [Byte1]: 37
1733 13:38:42.032864
1734 13:38:42.032944 Set Vref, RX VrefLevel [Byte0]: 38
1735 13:38:42.033027 [Byte1]: 38
1736 13:38:42.033107
1737 13:38:42.033187 Set Vref, RX VrefLevel [Byte0]: 39
1738 13:38:42.033270 [Byte1]: 39
1739 13:38:42.033352
1740 13:38:42.033432 Set Vref, RX VrefLevel [Byte0]: 40
1741 13:38:42.033515 [Byte1]: 40
1742 13:38:42.033595
1743 13:38:42.033675 Set Vref, RX VrefLevel [Byte0]: 41
1744 13:38:42.033768 [Byte1]: 41
1745 13:38:42.033852
1746 13:38:42.033933 Set Vref, RX VrefLevel [Byte0]: 42
1747 13:38:42.034017 [Byte1]: 42
1748 13:38:42.034097
1749 13:38:42.034211 Set Vref, RX VrefLevel [Byte0]: 43
1750 13:38:42.034266 [Byte1]: 43
1751 13:38:42.034323
1752 13:38:42.034373 Set Vref, RX VrefLevel [Byte0]: 44
1753 13:38:42.034425 [Byte1]: 44
1754 13:38:42.034480
1755 13:38:42.034538 Set Vref, RX VrefLevel [Byte0]: 45
1756 13:38:42.034590 [Byte1]: 45
1757 13:38:42.034642
1758 13:38:42.034693 Set Vref, RX VrefLevel [Byte0]: 46
1759 13:38:42.034743 [Byte1]: 46
1760 13:38:42.034798
1761 13:38:42.034850 Set Vref, RX VrefLevel [Byte0]: 47
1762 13:38:42.035106 [Byte1]: 47
1763 13:38:42.035168
1764 13:38:42.035220 Set Vref, RX VrefLevel [Byte0]: 48
1765 13:38:42.035273 [Byte1]: 48
1766 13:38:42.035351
1767 13:38:42.035433 Set Vref, RX VrefLevel [Byte0]: 49
1768 13:38:42.035518 [Byte1]: 49
1769 13:38:42.035610
1770 13:38:42.035697 Set Vref, RX VrefLevel [Byte0]: 50
1771 13:38:42.035778 [Byte1]: 50
1772 13:38:42.035875
1773 13:38:42.035960 Set Vref, RX VrefLevel [Byte0]: 51
1774 13:38:42.036045 [Byte1]: 51
1775 13:38:42.036126
1776 13:38:42.036206 Set Vref, RX VrefLevel [Byte0]: 52
1777 13:38:42.036287 [Byte1]: 52
1778 13:38:42.036370
1779 13:38:42.036469 Set Vref, RX VrefLevel [Byte0]: 53
1780 13:38:42.036561 [Byte1]: 53
1781 13:38:42.036642
1782 13:38:42.036723 Set Vref, RX VrefLevel [Byte0]: 54
1783 13:38:42.036805 [Byte1]: 54
1784 13:38:42.036886
1785 13:38:42.036966 Set Vref, RX VrefLevel [Byte0]: 55
1786 13:38:42.037051 [Byte1]: 55
1787 13:38:42.037132
1788 13:38:42.037212 Set Vref, RX VrefLevel [Byte0]: 56
1789 13:38:42.037293 [Byte1]: 56
1790 13:38:42.037355
1791 13:38:42.037406 Set Vref, RX VrefLevel [Byte0]: 57
1792 13:38:42.037457 [Byte1]: 57
1793 13:38:42.037508
1794 13:38:42.037582 Set Vref, RX VrefLevel [Byte0]: 58
1795 13:38:42.037663 [Byte1]: 58
1796 13:38:42.037743
1797 13:38:42.037825 Set Vref, RX VrefLevel [Byte0]: 59
1798 13:38:42.037920 [Byte1]: 59
1799 13:38:42.038002
1800 13:38:42.038089 Set Vref, RX VrefLevel [Byte0]: 60
1801 13:38:42.038195 [Byte1]: 60
1802 13:38:42.038266
1803 13:38:42.038322 Set Vref, RX VrefLevel [Byte0]: 61
1804 13:38:42.038374 [Byte1]: 61
1805 13:38:42.038426
1806 13:38:42.038483 Set Vref, RX VrefLevel [Byte0]: 62
1807 13:38:42.038578 [Byte1]: 62
1808 13:38:42.038662
1809 13:38:42.038728 Set Vref, RX VrefLevel [Byte0]: 63
1810 13:38:42.038779 [Byte1]: 63
1811 13:38:42.038876
1812 13:38:42.038959 Set Vref, RX VrefLevel [Byte0]: 64
1813 13:38:42.039014 [Byte1]: 64
1814 13:38:42.039068
1815 13:38:42.039195 Set Vref, RX VrefLevel [Byte0]: 65
1816 13:38:42.039263 [Byte1]: 65
1817 13:38:42.039317
1818 13:38:42.039371 Set Vref, RX VrefLevel [Byte0]: 66
1819 13:38:42.039422 [Byte1]: 66
1820 13:38:42.039473
1821 13:38:42.039532 Set Vref, RX VrefLevel [Byte0]: 67
1822 13:38:42.039598 [Byte1]: 67
1823 13:38:42.039650
1824 13:38:42.039711 Set Vref, RX VrefLevel [Byte0]: 68
1825 13:38:42.039789 [Byte1]: 68
1826 13:38:42.039850
1827 13:38:42.039903 Set Vref, RX VrefLevel [Byte0]: 69
1828 13:38:42.039956 [Byte1]: 69
1829 13:38:42.040011
1830 13:38:42.040066 Set Vref, RX VrefLevel [Byte0]: 70
1831 13:38:42.040119 [Byte1]: 70
1832 13:38:42.040171
1833 13:38:42.040222 Set Vref, RX VrefLevel [Byte0]: 71
1834 13:38:42.040278 [Byte1]: 71
1835 13:38:42.040338
1836 13:38:42.040424 Set Vref, RX VrefLevel [Byte0]: 72
1837 13:38:42.040531 [Byte1]: 72
1838 13:38:42.040616
1839 13:38:42.040698 Set Vref, RX VrefLevel [Byte0]: 73
1840 13:38:42.040781 [Byte1]: 73
1841 13:38:42.040867
1842 13:38:42.040952 Set Vref, RX VrefLevel [Byte0]: 74
1843 13:38:42.041038 [Byte1]: 74
1844 13:38:42.041120
1845 13:38:42.041202 Set Vref, RX VrefLevel [Byte0]: 75
1846 13:38:42.041284 [Byte1]: 75
1847 13:38:42.041368
1848 13:38:42.041454 Set Vref, RX VrefLevel [Byte0]: 76
1849 13:38:42.041539 [Byte1]: 76
1850 13:38:42.041621
1851 13:38:42.041703 Set Vref, RX VrefLevel [Byte0]: 77
1852 13:38:42.041799 [Byte1]: 77
1853 13:38:42.041886
1854 13:38:42.041971 Set Vref, RX VrefLevel [Byte0]: 78
1855 13:38:42.042056 [Byte1]: 78
1856 13:38:42.042138
1857 13:38:42.042214 Final RX Vref Byte 0 = 57 to rank0
1858 13:38:42.042269 Final RX Vref Byte 1 = 67 to rank0
1859 13:38:42.042326 Final RX Vref Byte 0 = 57 to rank1
1860 13:38:42.042407 Final RX Vref Byte 1 = 67 to rank1==
1861 13:38:42.042467 Dram Type= 6, Freq= 0, CH_1, rank 0
1862 13:38:42.042521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 13:38:42.042604 ==
1864 13:38:42.042687 DQS Delay:
1865 13:38:42.042769 DQS0 = 0, DQS1 = 0
1866 13:38:42.042851 DQM Delay:
1867 13:38:42.042937 DQM0 = 86, DQM1 = 78
1868 13:38:42.043019 DQ Delay:
1869 13:38:42.043117 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1870 13:38:42.043175 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1871 13:38:42.043228 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1872 13:38:42.043281 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1873 13:38:42.043333
1874 13:38:42.043390
1875 13:38:42.043446 [DQSOSCAuto] RK0, (LSB)MR18= 0x321f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1876 13:38:42.043501 CH1 RK0: MR19=606, MR18=321F
1877 13:38:42.043573 CH1_RK0: MR19=0x606, MR18=0x321F, DQSOSC=397, MR23=63, INC=93, DEC=62
1878 13:38:42.043634
1879 13:38:42.043687 ----->DramcWriteLeveling(PI) begin...
1880 13:38:42.043771 ==
1881 13:38:42.043827 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 13:38:42.043885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 13:38:42.043945 ==
1884 13:38:42.044028 Write leveling (Byte 0): 29 => 29
1885 13:38:42.044090 Write leveling (Byte 1): 29 => 29
1886 13:38:42.044144 DramcWriteLeveling(PI) end<-----
1887 13:38:42.044196
1888 13:38:42.044248 ==
1889 13:38:42.044328 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 13:38:42.044386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 13:38:42.044445 ==
1892 13:38:42.044501 [Gating] SW mode calibration
1893 13:38:42.044560 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1894 13:38:42.044646 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1895 13:38:42.044729 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1896 13:38:42.044817 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1897 13:38:42.044889 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1898 13:38:42.044949 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:38:42.045006 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:38:42.045090 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 13:38:42.045176 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 13:38:42.045259 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:38:42.045342 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:38:42.045428 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:38:42.045713 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:38:42.045802 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:38:42.045886 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:38:42.045973 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 13:38:42.046056 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 13:38:42.046144 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 13:38:42.046218 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 13:38:42.046273 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1913 13:38:42.046326 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 13:38:42.046379 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 13:38:42.046468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 13:38:42.046524 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 13:38:42.046583 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 13:38:42.046642 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 13:38:42.046696 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 13:38:42.046748 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 13:38:42.046801 0 9 8 | B1->B0 | 3333 2928 | 0 1 | (0 0) (0 0)
1922 13:38:42.046853 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 13:38:42.046906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 13:38:42.046962 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 13:38:42.047042 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 13:38:42.047131 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 13:38:42.047186 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 13:38:42.047240 0 10 4 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 1)
1929 13:38:42.047298 0 10 8 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 0)
1930 13:38:42.047352 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 13:38:42.047405 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 13:38:42.047462 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 13:38:42.047517 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 13:38:42.047570 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 13:38:42.047627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 13:38:42.047680 0 11 4 | B1->B0 | 2c2c 2424 | 1 0 | (0 0) (0 0)
1937 13:38:42.047732 0 11 8 | B1->B0 | 4545 3838 | 0 0 | (0 0) (0 0)
1938 13:38:42.047789 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 13:38:42.047863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 13:38:42.047948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 13:38:42.048007 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 13:38:42.048060 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 13:38:42.048119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 13:38:42.048172 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 13:38:42.048224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1946 13:38:42.048276 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 13:38:42.048332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 13:38:42.048385 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 13:38:42.048437 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 13:38:42.048523 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 13:38:42.048578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 13:38:42.048637 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 13:38:42.048691 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 13:38:42.048743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 13:38:42.048796 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 13:38:42.048849 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 13:38:42.048903 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 13:38:42.048961 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 13:38:42.049015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 13:38:42.049067 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 13:38:42.049141 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1962 13:38:42.049229 Total UI for P1: 0, mck2ui 16
1963 13:38:42.049312 best dqsien dly found for B0: ( 0, 14, 6)
1964 13:38:42.049395 Total UI for P1: 0, mck2ui 16
1965 13:38:42.049482 best dqsien dly found for B1: ( 0, 14, 6)
1966 13:38:42.049566 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1967 13:38:42.049653 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1968 13:38:42.049746
1969 13:38:42.049830 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1970 13:38:42.049927 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1971 13:38:42.050028 [Gating] SW calibration Done
1972 13:38:42.050114 ==
1973 13:38:42.050199 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 13:38:42.050255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 13:38:42.050309 ==
1976 13:38:42.050362 RX Vref Scan: 0
1977 13:38:42.050415
1978 13:38:42.050467 RX Vref 0 -> 0, step: 1
1979 13:38:42.050552
1980 13:38:42.050610 RX Delay -130 -> 252, step: 16
1981 13:38:42.050672 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1982 13:38:42.050727 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1983 13:38:42.050780 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1984 13:38:42.050832 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1985 13:38:42.050885 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1986 13:38:42.050937 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1987 13:38:42.457100 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1988 13:38:42.457257 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1989 13:38:42.457353 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1990 13:38:42.457418 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1991 13:38:42.457489 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1992 13:38:42.457548 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1993 13:38:42.457614 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1994 13:38:42.457728 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1995 13:38:42.457813 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1996 13:38:42.458117 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1997 13:38:42.458218 ==
1998 13:38:42.458304 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 13:38:42.458383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 13:38:42.458440 ==
2001 13:38:42.458495 DQS Delay:
2002 13:38:42.458549 DQS0 = 0, DQS1 = 0
2003 13:38:42.458609 DQM Delay:
2004 13:38:42.458668 DQM0 = 87, DQM1 = 78
2005 13:38:42.458722 DQ Delay:
2006 13:38:42.458775 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2007 13:38:42.458828 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2008 13:38:42.458887 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2009 13:38:42.458941 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2010 13:38:42.458994
2011 13:38:42.459046
2012 13:38:42.459103 ==
2013 13:38:42.459188 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 13:38:42.459272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 13:38:42.459354 ==
2016 13:38:42.459440
2017 13:38:42.459525
2018 13:38:42.459609 TX Vref Scan disable
2019 13:38:42.459709 == TX Byte 0 ==
2020 13:38:42.459790 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2021 13:38:42.459873 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2022 13:38:42.459955 == TX Byte 1 ==
2023 13:38:42.460052 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 13:38:42.460137 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 13:38:42.460222 ==
2026 13:38:42.460318 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 13:38:42.460401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 13:38:42.460483 ==
2029 13:38:42.460563 TX Vref=22, minBit 8, minWin=27, winSum=446
2030 13:38:42.460696 TX Vref=24, minBit 9, minWin=27, winSum=450
2031 13:38:42.460780 TX Vref=26, minBit 9, minWin=27, winSum=451
2032 13:38:42.460863 TX Vref=28, minBit 13, minWin=27, winSum=451
2033 13:38:42.460949 TX Vref=30, minBit 15, minWin=27, winSum=450
2034 13:38:42.461032 TX Vref=32, minBit 8, minWin=27, winSum=446
2035 13:38:42.461128 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 26
2036 13:38:42.461228
2037 13:38:42.461281 Final TX Range 1 Vref 26
2038 13:38:42.461333
2039 13:38:42.461384 ==
2040 13:38:42.461497 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 13:38:42.461578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 13:38:42.461659 ==
2043 13:38:42.461744
2044 13:38:42.461824
2045 13:38:42.461923 TX Vref Scan disable
2046 13:38:42.462006 == TX Byte 0 ==
2047 13:38:42.462088 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2048 13:38:42.462175 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2049 13:38:42.462248 == TX Byte 1 ==
2050 13:38:42.462303 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2051 13:38:42.462356 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2052 13:38:42.462412
2053 13:38:42.462482 [DATLAT]
2054 13:38:42.462534 Freq=800, CH1 RK1
2055 13:38:42.462586
2056 13:38:42.462639 DATLAT Default: 0xa
2057 13:38:42.462691 0, 0xFFFF, sum = 0
2058 13:38:42.462765 1, 0xFFFF, sum = 0
2059 13:38:42.462820 2, 0xFFFF, sum = 0
2060 13:38:42.462872 3, 0xFFFF, sum = 0
2061 13:38:42.462929 4, 0xFFFF, sum = 0
2062 13:38:42.462983 5, 0xFFFF, sum = 0
2063 13:38:42.463035 6, 0xFFFF, sum = 0
2064 13:38:42.463087 7, 0xFFFF, sum = 0
2065 13:38:42.463138 8, 0xFFFF, sum = 0
2066 13:38:42.463189 9, 0x0, sum = 1
2067 13:38:42.463245 10, 0x0, sum = 2
2068 13:38:42.463305 11, 0x0, sum = 3
2069 13:38:42.463358 12, 0x0, sum = 4
2070 13:38:42.463414 best_step = 10
2071 13:38:42.463486
2072 13:38:42.463656 ==
2073 13:38:42.463770 Dram Type= 6, Freq= 0, CH_1, rank 1
2074 13:38:42.463886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2075 13:38:42.463971 ==
2076 13:38:42.464051 RX Vref Scan: 0
2077 13:38:42.464131
2078 13:38:42.464212 RX Vref 0 -> 0, step: 1
2079 13:38:42.464333
2080 13:38:42.464416 RX Delay -95 -> 252, step: 8
2081 13:38:42.464500 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2082 13:38:42.464582 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2083 13:38:42.464662 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2084 13:38:42.464744 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2085 13:38:42.464860 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2086 13:38:42.464944 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2087 13:38:42.465043 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2088 13:38:42.465137 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2089 13:38:42.465218 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
2090 13:38:42.465301 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2091 13:38:42.465423 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2092 13:38:42.465508 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2093 13:38:42.465589 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2094 13:38:42.465670 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224
2095 13:38:42.465751 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2096 13:38:42.465835 iDelay=217, Bit 15, Center 88 (-23 ~ 200) 224
2097 13:38:42.465949 ==
2098 13:38:42.466032 Dram Type= 6, Freq= 0, CH_1, rank 1
2099 13:38:42.466113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2100 13:38:42.466223 ==
2101 13:38:42.466293 DQS Delay:
2102 13:38:42.466365 DQS0 = 0, DQS1 = 0
2103 13:38:42.466443 DQM Delay:
2104 13:38:42.466541 DQM0 = 88, DQM1 = 79
2105 13:38:42.466622 DQ Delay:
2106 13:38:42.466702 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =88
2107 13:38:42.466783 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2108 13:38:42.466858 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
2109 13:38:42.466911 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
2110 13:38:42.467014
2111 13:38:42.467095
2112 13:38:42.467176 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2113 13:38:42.467258 CH1 RK1: MR19=606, MR18=1D15
2114 13:38:42.467338 CH1_RK1: MR19=0x606, MR18=0x1D15, DQSOSC=402, MR23=63, INC=91, DEC=60
2115 13:38:42.467394 [RxdqsGatingPostProcess] freq 800
2116 13:38:42.467451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2117 13:38:42.467568 Pre-setting of DQS Precalculation
2118 13:38:42.467649 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2119 13:38:42.467732 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2120 13:38:42.467815 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2121 13:38:42.467875
2122 13:38:42.467927
2123 13:38:42.467978 [Calibration Summary] 1600 Mbps
2124 13:38:42.468033 CH 0, Rank 0
2125 13:38:42.468124 SW Impedance : PASS
2126 13:38:42.468205 DUTY Scan : NO K
2127 13:38:42.468286 ZQ Calibration : PASS
2128 13:38:42.468371 Jitter Meter : NO K
2129 13:38:42.468452 CBT Training : PASS
2130 13:38:42.468533 Write leveling : PASS
2131 13:38:42.468617 RX DQS gating : PASS
2132 13:38:42.468738 RX DQ/DQS(RDDQC) : PASS
2133 13:38:42.468818 TX DQ/DQS : PASS
2134 13:38:42.468901 RX DATLAT : PASS
2135 13:38:42.469012 RX DQ/DQS(Engine): PASS
2136 13:38:42.469093 TX OE : NO K
2137 13:38:42.469173 All Pass.
2138 13:38:42.469296
2139 13:38:42.469377 CH 0, Rank 1
2140 13:38:42.469461 SW Impedance : PASS
2141 13:38:42.469542 DUTY Scan : NO K
2142 13:38:42.469848 ZQ Calibration : PASS
2143 13:38:42.469982 Jitter Meter : NO K
2144 13:38:42.470091 CBT Training : PASS
2145 13:38:42.470182 Write leveling : PASS
2146 13:38:42.470277 RX DQS gating : PASS
2147 13:38:42.470382 RX DQ/DQS(RDDQC) : PASS
2148 13:38:42.470481 TX DQ/DQS : PASS
2149 13:38:42.470563 RX DATLAT : PASS
2150 13:38:42.470644 RX DQ/DQS(Engine): PASS
2151 13:38:42.470725 TX OE : NO K
2152 13:38:42.470805 All Pass.
2153 13:38:42.470916
2154 13:38:42.470990 CH 1, Rank 0
2155 13:38:42.471091 SW Impedance : PASS
2156 13:38:42.471172 DUTY Scan : NO K
2157 13:38:42.471253 ZQ Calibration : PASS
2158 13:38:42.471369 Jitter Meter : NO K
2159 13:38:42.471499 CBT Training : PASS
2160 13:38:42.471599 Write leveling : PASS
2161 13:38:42.471681 RX DQS gating : PASS
2162 13:38:42.471768 RX DQ/DQS(RDDQC) : PASS
2163 13:38:42.471849 TX DQ/DQS : PASS
2164 13:38:42.471931 RX DATLAT : PASS
2165 13:38:42.472017 RX DQ/DQS(Engine): PASS
2166 13:38:42.472090 TX OE : NO K
2167 13:38:42.472145 All Pass.
2168 13:38:42.472197
2169 13:38:42.472249 CH 1, Rank 1
2170 13:38:42.472300 SW Impedance : PASS
2171 13:38:42.472352 DUTY Scan : NO K
2172 13:38:42.472403 ZQ Calibration : PASS
2173 13:38:42.472454 Jitter Meter : NO K
2174 13:38:42.472527 CBT Training : PASS
2175 13:38:42.472627 Write leveling : PASS
2176 13:38:42.472713 RX DQS gating : PASS
2177 13:38:42.472795 RX DQ/DQS(RDDQC) : PASS
2178 13:38:42.472891 TX DQ/DQS : PASS
2179 13:38:42.472971 RX DATLAT : PASS
2180 13:38:42.473024 RX DQ/DQS(Engine): PASS
2181 13:38:42.473093 TX OE : NO K
2182 13:38:42.473166 All Pass.
2183 13:38:42.473265
2184 13:38:42.473374 DramC Write-DBI off
2185 13:38:42.473456 PER_BANK_REFRESH: Hybrid Mode
2186 13:38:42.473512 TX_TRACKING: ON
2187 13:38:42.473565 [GetDramInforAfterCalByMRR] Vendor 6.
2188 13:38:42.473621 [GetDramInforAfterCalByMRR] Revision 606.
2189 13:38:42.473679 [GetDramInforAfterCalByMRR] Revision 2 0.
2190 13:38:42.473745 MR0 0x3b3b
2191 13:38:42.473797 MR8 0x5151
2192 13:38:42.473848 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2193 13:38:42.473916
2194 13:38:42.473975 MR0 0x3b3b
2195 13:38:42.474029 MR8 0x5151
2196 13:38:42.474081 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2197 13:38:42.474153
2198 13:38:42.474217 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2199 13:38:42.474286 [FAST_K] Save calibration result to emmc
2200 13:38:42.474338 [FAST_K] Save calibration result to emmc
2201 13:38:42.474390 dram_init: config_dvfs: 1
2202 13:38:42.474443 dramc_set_vcore_voltage set vcore to 662500
2203 13:38:42.474499 Read voltage for 1200, 2
2204 13:38:42.474551 Vio18 = 0
2205 13:38:42.474622 Vcore = 662500
2206 13:38:42.474710 Vdram = 0
2207 13:38:42.474763 Vddq = 0
2208 13:38:42.474815 Vmddr = 0
2209 13:38:42.474867 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2210 13:38:42.474920 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2211 13:38:42.474993 MEM_TYPE=3, freq_sel=15
2212 13:38:42.475045 sv_algorithm_assistance_LP4_1600
2213 13:38:42.475095 ============ PULL DRAM RESETB DOWN ============
2214 13:38:42.475184 ========== PULL DRAM RESETB DOWN end =========
2215 13:38:42.475237 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2216 13:38:42.475289 ===================================
2217 13:38:42.475341 LPDDR4 DRAM CONFIGURATION
2218 13:38:42.475409 ===================================
2219 13:38:42.475465 EX_ROW_EN[0] = 0x0
2220 13:38:42.475521 EX_ROW_EN[1] = 0x0
2221 13:38:42.475573 LP4Y_EN = 0x0
2222 13:38:42.475630 WORK_FSP = 0x0
2223 13:38:42.475687 WL = 0x4
2224 13:38:42.475753 RL = 0x4
2225 13:38:42.475805 BL = 0x2
2226 13:38:42.475857 RPST = 0x0
2227 13:38:42.475908 RD_PRE = 0x0
2228 13:38:42.475958 WR_PRE = 0x1
2229 13:38:42.476015 WR_PST = 0x0
2230 13:38:42.476066 DBI_WR = 0x0
2231 13:38:42.476136 DBI_RD = 0x0
2232 13:38:42.476194 OTF = 0x1
2233 13:38:42.476248 ===================================
2234 13:38:42.476301 ===================================
2235 13:38:42.476354 ANA top config
2236 13:38:42.476420 ===================================
2237 13:38:42.476475 DLL_ASYNC_EN = 0
2238 13:38:42.476555 ALL_SLAVE_EN = 0
2239 13:38:42.476623 NEW_RANK_MODE = 1
2240 13:38:42.476714 DLL_IDLE_MODE = 1
2241 13:38:42.476813 LP45_APHY_COMB_EN = 1
2242 13:38:42.476908 TX_ODT_DIS = 1
2243 13:38:42.476996 NEW_8X_MODE = 1
2244 13:38:42.477080 ===================================
2245 13:38:42.477179 ===================================
2246 13:38:42.477267 data_rate = 2400
2247 13:38:42.477360 CKR = 1
2248 13:38:42.477483 DQ_P2S_RATIO = 8
2249 13:38:42.477567 ===================================
2250 13:38:42.477656 CA_P2S_RATIO = 8
2251 13:38:42.477740 DQ_CA_OPEN = 0
2252 13:38:42.477829 DQ_SEMI_OPEN = 0
2253 13:38:42.477912 CA_SEMI_OPEN = 0
2254 13:38:42.477996 CA_FULL_RATE = 0
2255 13:38:42.478095 DQ_CKDIV4_EN = 0
2256 13:38:42.478183 CA_CKDIV4_EN = 0
2257 13:38:42.478276 CA_PREDIV_EN = 0
2258 13:38:42.478361 PH8_DLY = 17
2259 13:38:42.478427 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2260 13:38:42.478486 DQ_AAMCK_DIV = 4
2261 13:38:42.478539 CA_AAMCK_DIV = 4
2262 13:38:42.478591 CA_ADMCK_DIV = 4
2263 13:38:42.478660 DQ_TRACK_CA_EN = 0
2264 13:38:42.478750 CA_PICK = 1200
2265 13:38:42.478805 CA_MCKIO = 1200
2266 13:38:42.478858 MCKIO_SEMI = 0
2267 13:38:42.478911 PLL_FREQ = 2366
2268 13:38:42.478968 DQ_UI_PI_RATIO = 32
2269 13:38:42.479035 CA_UI_PI_RATIO = 0
2270 13:38:42.479087 ===================================
2271 13:38:42.479140 ===================================
2272 13:38:42.479227 memory_type:LPDDR4
2273 13:38:42.479284 GP_NUM : 10
2274 13:38:42.479337 SRAM_EN : 1
2275 13:38:42.479403 MD32_EN : 0
2276 13:38:42.479456 ===================================
2277 13:38:42.479516 [ANA_INIT] >>>>>>>>>>>>>>
2278 13:38:42.479569 <<<<<< [CONFIGURE PHASE]: ANA_TX
2279 13:38:42.479623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2280 13:38:42.479676 ===================================
2281 13:38:42.479733 data_rate = 2400,PCW = 0X5b00
2282 13:38:42.479797 ===================================
2283 13:38:42.479880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2284 13:38:42.479964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2285 13:38:42.480064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2286 13:38:42.480365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2287 13:38:42.480474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2288 13:38:42.480571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2289 13:38:42.480655 [ANA_INIT] flow start
2290 13:38:42.480755 [ANA_INIT] PLL >>>>>>>>
2291 13:38:42.480870 [ANA_INIT] PLL <<<<<<<<
2292 13:38:42.480952 [ANA_INIT] MIDPI >>>>>>>>
2293 13:38:42.481037 [ANA_INIT] MIDPI <<<<<<<<
2294 13:38:42.481132 [ANA_INIT] DLL >>>>>>>>
2295 13:38:42.481212 [ANA_INIT] DLL <<<<<<<<
2296 13:38:42.481328 [ANA_INIT] flow end
2297 13:38:42.481425 ============ LP4 DIFF to SE enter ============
2298 13:38:42.481512 ============ LP4 DIFF to SE exit ============
2299 13:38:42.481595 [ANA_INIT] <<<<<<<<<<<<<
2300 13:38:42.481692 [Flow] Enable top DCM control >>>>>
2301 13:38:42.481773 [Flow] Enable top DCM control <<<<<
2302 13:38:42.481889 Enable DLL master slave shuffle
2303 13:38:42.481971 ==============================================================
2304 13:38:42.482056 Gating Mode config
2305 13:38:42.482153 ==============================================================
2306 13:38:42.482245 Config description:
2307 13:38:42.482333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2308 13:38:42.482420 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2309 13:38:42.482516 SELPH_MODE 0: By rank 1: By Phase
2310 13:38:42.482571 ==============================================================
2311 13:38:42.482624 GAT_TRACK_EN = 1
2312 13:38:42.482675 RX_GATING_MODE = 2
2313 13:38:42.482727 RX_GATING_TRACK_MODE = 2
2314 13:38:42.482778 SELPH_MODE = 1
2315 13:38:42.482862 PICG_EARLY_EN = 1
2316 13:38:42.482958 VALID_LAT_VALUE = 1
2317 13:38:42.483043 ==============================================================
2318 13:38:42.483125 Enter into Gating configuration >>>>
2319 13:38:42.483206 Exit from Gating configuration <<<<
2320 13:38:42.483287 Enter into DVFS_PRE_config >>>>>
2321 13:38:42.483400 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2322 13:38:42.483457 Exit from DVFS_PRE_config <<<<<
2323 13:38:42.483513 Enter into PICG configuration >>>>
2324 13:38:42.483567 Exit from PICG configuration <<<<
2325 13:38:42.483618 [RX_INPUT] configuration >>>>>
2326 13:38:42.483669 [RX_INPUT] configuration <<<<<
2327 13:38:42.483720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2328 13:38:42.483772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2329 13:38:42.483823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2330 13:38:42.483911 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2331 13:38:42.483964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2332 13:38:42.484024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2333 13:38:42.484107 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2334 13:38:42.484202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2335 13:38:42.484285 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2336 13:38:42.484370 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2337 13:38:42.484438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2338 13:38:42.484532 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2339 13:38:42.484587 ===================================
2340 13:38:42.484639 LPDDR4 DRAM CONFIGURATION
2341 13:38:42.484691 ===================================
2342 13:38:42.484743 EX_ROW_EN[0] = 0x0
2343 13:38:42.484794 EX_ROW_EN[1] = 0x0
2344 13:38:42.484845 LP4Y_EN = 0x0
2345 13:38:42.484922 WORK_FSP = 0x0
2346 13:38:42.484976 WL = 0x4
2347 13:38:42.485033 RL = 0x4
2348 13:38:42.485086 BL = 0x2
2349 13:38:42.485139 RPST = 0x0
2350 13:38:42.485192 RD_PRE = 0x0
2351 13:38:42.485244 WR_PRE = 0x1
2352 13:38:42.485309 WR_PST = 0x0
2353 13:38:42.485360 DBI_WR = 0x0
2354 13:38:42.485432 DBI_RD = 0x0
2355 13:38:42.485525 OTF = 0x1
2356 13:38:42.485625 ===================================
2357 13:38:42.485753 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2358 13:38:42.485862 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2359 13:38:42.485950 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2360 13:38:42.486036 ===================================
2361 13:38:42.486120 LPDDR4 DRAM CONFIGURATION
2362 13:38:42.486210 ===================================
2363 13:38:42.486293 EX_ROW_EN[0] = 0x10
2364 13:38:42.486375 EX_ROW_EN[1] = 0x0
2365 13:38:42.486462 LP4Y_EN = 0x0
2366 13:38:42.486547 WORK_FSP = 0x0
2367 13:38:42.486629 WL = 0x4
2368 13:38:42.486711 RL = 0x4
2369 13:38:42.486792 BL = 0x2
2370 13:38:42.486873 RPST = 0x0
2371 13:38:42.486958 RD_PRE = 0x0
2372 13:38:42.487044 WR_PRE = 0x1
2373 13:38:42.487126 WR_PST = 0x0
2374 13:38:42.487207 DBI_WR = 0x0
2375 13:38:42.487289 DBI_RD = 0x0
2376 13:38:42.487370 OTF = 0x1
2377 13:38:42.487456 ===================================
2378 13:38:42.487545 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2379 13:38:42.487627 ==
2380 13:38:42.487710 Dram Type= 6, Freq= 0, CH_0, rank 0
2381 13:38:42.487792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 13:38:42.487874 ==
2383 13:38:42.487959 [Duty_Offset_Calibration]
2384 13:38:42.488045 B0:1 B1:-1 CA:0
2385 13:38:42.488127
2386 13:38:42.488209 [DutyScan_Calibration_Flow] k_type=0
2387 13:38:42.488290
2388 13:38:42.488371 ==CLK 0==
2389 13:38:42.488456 Final CLK duty delay cell = 0
2390 13:38:42.488543 [0] MAX Duty = 5094%(X100), DQS PI = 16
2391 13:38:42.488626 [0] MIN Duty = 4875%(X100), DQS PI = 8
2392 13:38:42.488708 [0] AVG Duty = 4984%(X100)
2393 13:38:42.488789
2394 13:38:42.488871 CH0 CLK Duty spec in!! Max-Min= 219%
2395 13:38:42.488956 [DutyScan_Calibration_Flow] ====Done====
2396 13:38:42.489042
2397 13:38:42.489125 [DutyScan_Calibration_Flow] k_type=1
2398 13:38:42.489206
2399 13:38:42.489287 ==DQS 0 ==
2400 13:38:42.489369 Final DQS duty delay cell = -4
2401 13:38:42.489455 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2402 13:38:42.489542 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2403 13:38:42.489825 [-4] AVG Duty = 4968%(X100)
2404 13:38:42.489917
2405 13:38:42.490005 ==DQS 1 ==
2406 13:38:42.490091 Final DQS duty delay cell = 0
2407 13:38:42.490189 [0] MAX Duty = 5124%(X100), DQS PI = 6
2408 13:38:42.490316 [0] MIN Duty = 5000%(X100), DQS PI = 20
2409 13:38:42.490396 [0] AVG Duty = 5062%(X100)
2410 13:38:42.490498
2411 13:38:42.490596 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2412 13:38:42.490676
2413 13:38:42.490756 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2414 13:38:42.490868 [DutyScan_Calibration_Flow] ====Done====
2415 13:38:42.490948
2416 13:38:42.491033 [DutyScan_Calibration_Flow] k_type=3
2417 13:38:42.491116
2418 13:38:42.491196 ==DQM 0 ==
2419 13:38:42.491276 Final DQM duty delay cell = 0
2420 13:38:42.491358 [0] MAX Duty = 5062%(X100), DQS PI = 18
2421 13:38:42.491439 [0] MIN Duty = 4875%(X100), DQS PI = 10
2422 13:38:42.491523 [0] AVG Duty = 4968%(X100)
2423 13:38:42.491638
2424 13:38:42.491717 ==DQM 1 ==
2425 13:38:42.491798 Final DQM duty delay cell = 4
2426 13:38:42.491879 [4] MAX Duty = 5187%(X100), DQS PI = 56
2427 13:38:42.491959 [4] MIN Duty = 4969%(X100), DQS PI = 26
2428 13:38:42.492044 [4] AVG Duty = 5078%(X100)
2429 13:38:42.492127
2430 13:38:42.492238 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2431 13:38:42.492317
2432 13:38:42.492397 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2433 13:38:42.492479 [DutyScan_Calibration_Flow] ====Done====
2434 13:38:42.492534
2435 13:38:42.492585 [DutyScan_Calibration_Flow] k_type=2
2436 13:38:42.492639
2437 13:38:42.492697 ==DQ 0 ==
2438 13:38:42.492778 Final DQ duty delay cell = -4
2439 13:38:42.492860 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2440 13:38:42.492940 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2441 13:38:42.493023 [-4] AVG Duty = 4969%(X100)
2442 13:38:42.493122
2443 13:38:42.493218 ==DQ 1 ==
2444 13:38:42.493299 Final DQ duty delay cell = -4
2445 13:38:42.493376 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2446 13:38:42.493430 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2447 13:38:42.493505 [-4] AVG Duty = 4922%(X100)
2448 13:38:42.493560
2449 13:38:42.493618 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2450 13:38:42.493703
2451 13:38:42.493798 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2452 13:38:42.493879 [DutyScan_Calibration_Flow] ====Done====
2453 13:38:42.493959 ==
2454 13:38:42.494043 Dram Type= 6, Freq= 0, CH_1, rank 0
2455 13:38:42.494142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2456 13:38:42.494226 ==
2457 13:38:42.494294 [Duty_Offset_Calibration]
2458 13:38:42.494360 B0:-1 B1:1 CA:1
2459 13:38:42.494412
2460 13:38:42.494462 [DutyScan_Calibration_Flow] k_type=0
2461 13:38:42.494520
2462 13:38:42.494572 ==CLK 0==
2463 13:38:42.494630 Final CLK duty delay cell = 0
2464 13:38:42.494685 [0] MAX Duty = 5156%(X100), DQS PI = 20
2465 13:38:42.494737 [0] MIN Duty = 4969%(X100), DQS PI = 60
2466 13:38:42.494789 [0] AVG Duty = 5062%(X100)
2467 13:38:42.494839
2468 13:38:42.494906 CH1 CLK Duty spec in!! Max-Min= 187%
2469 13:38:42.494971 [DutyScan_Calibration_Flow] ====Done====
2470 13:38:42.495028
2471 13:38:42.495079 [DutyScan_Calibration_Flow] k_type=1
2472 13:38:42.495136
2473 13:38:42.495191 ==DQS 0 ==
2474 13:38:42.495242 Final DQS duty delay cell = 0
2475 13:38:42.495294 [0] MAX Duty = 5125%(X100), DQS PI = 48
2476 13:38:42.495345 [0] MIN Duty = 4875%(X100), DQS PI = 6
2477 13:38:42.495395 [0] AVG Duty = 5000%(X100)
2478 13:38:42.495446
2479 13:38:42.495497 ==DQS 1 ==
2480 13:38:42.495570 Final DQS duty delay cell = 0
2481 13:38:42.495642 [0] MAX Duty = 5094%(X100), DQS PI = 12
2482 13:38:42.495722 [0] MIN Duty = 4969%(X100), DQS PI = 56
2483 13:38:42.495803 [0] AVG Duty = 5031%(X100)
2484 13:38:42.495883
2485 13:38:42.495963 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2486 13:38:42.496039
2487 13:38:42.496092 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2488 13:38:42.496150 [DutyScan_Calibration_Flow] ====Done====
2489 13:38:42.496216
2490 13:38:42.496327 [DutyScan_Calibration_Flow] k_type=3
2491 13:38:42.496407
2492 13:38:42.496520 ==DQM 0 ==
2493 13:38:42.496576 Final DQM duty delay cell = 0
2494 13:38:42.496627 [0] MAX Duty = 5187%(X100), DQS PI = 32
2495 13:38:42.496684 [0] MIN Duty = 5000%(X100), DQS PI = 6
2496 13:38:42.496760 [0] AVG Duty = 5093%(X100)
2497 13:38:42.496840
2498 13:38:42.496920 ==DQM 1 ==
2499 13:38:42.497032 Final DQM duty delay cell = 0
2500 13:38:42.497087 [0] MAX Duty = 5156%(X100), DQS PI = 6
2501 13:38:42.497143 [0] MIN Duty = 4969%(X100), DQS PI = 28
2502 13:38:42.497195 [0] AVG Duty = 5062%(X100)
2503 13:38:42.497261
2504 13:38:42.497341 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2505 13:38:42.497421
2506 13:38:42.497501 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2507 13:38:42.497569 [DutyScan_Calibration_Flow] ====Done====
2508 13:38:42.497621
2509 13:38:42.497678 [DutyScan_Calibration_Flow] k_type=2
2510 13:38:42.497729
2511 13:38:42.497784 ==DQ 0 ==
2512 13:38:42.497865 Final DQ duty delay cell = 0
2513 13:38:42.497946 [0] MAX Duty = 5156%(X100), DQS PI = 28
2514 13:38:42.498027 [0] MIN Duty = 4907%(X100), DQS PI = 6
2515 13:38:42.498111 [0] AVG Duty = 5031%(X100)
2516 13:38:42.498223
2517 13:38:42.498293 ==DQ 1 ==
2518 13:38:42.498362 Final DQ duty delay cell = 0
2519 13:38:42.498414 [0] MAX Duty = 5124%(X100), DQS PI = 10
2520 13:38:42.498466 [0] MIN Duty = 4969%(X100), DQS PI = 0
2521 13:38:42.498517 [0] AVG Duty = 5046%(X100)
2522 13:38:42.498574
2523 13:38:42.498630 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2524 13:38:42.498683
2525 13:38:42.498734 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2526 13:38:42.498785 [DutyScan_Calibration_Flow] ====Done====
2527 13:38:42.498853 nWR fixed to 30
2528 13:38:42.498922 [ModeRegInit_LP4] CH0 RK0
2529 13:38:42.498974 [ModeRegInit_LP4] CH0 RK1
2530 13:38:42.499024 [ModeRegInit_LP4] CH1 RK0
2531 13:38:42.499081 [ModeRegInit_LP4] CH1 RK1
2532 13:38:42.499136 match AC timing 7
2533 13:38:42.499190 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2534 13:38:42.499242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2535 13:38:42.499294 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2536 13:38:42.499346 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2537 13:38:42.499398 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2538 13:38:42.499454 ==
2539 13:38:42.499507 Dram Type= 6, Freq= 0, CH_0, rank 0
2540 13:38:42.499558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2541 13:38:42.499618 ==
2542 13:38:42.499671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2543 13:38:42.499722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2544 13:38:42.499773 [CA 0] Center 39 (9~70) winsize 62
2545 13:38:42.499824 [CA 1] Center 39 (9~70) winsize 62
2546 13:38:42.499874 [CA 2] Center 35 (5~66) winsize 62
2547 13:38:42.499925 [CA 3] Center 35 (5~65) winsize 61
2548 13:38:42.499976 [CA 4] Center 33 (3~64) winsize 62
2549 13:38:42.500094 [CA 5] Center 33 (4~63) winsize 60
2550 13:38:42.500191
2551 13:38:42.500243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2552 13:38:42.500294
2553 13:38:42.500345 [CATrainingPosCal] consider 1 rank data
2554 13:38:42.500426 u2DelayCellTimex100 = 270/100 ps
2555 13:38:42.500696 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2556 13:38:42.500799 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 13:38:42.500881 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 13:38:42.500962 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2559 13:38:42.501043 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2560 13:38:42.501111 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2561 13:38:42.501192
2562 13:38:42.501290 CA PerBit enable=1, Macro0, CA PI delay=33
2563 13:38:42.501372
2564 13:38:42.501454 [CBTSetCACLKResult] CA Dly = 33
2565 13:38:42.501537 CS Dly: 8 (0~39)
2566 13:38:42.501614 ==
2567 13:38:42.501688 Dram Type= 6, Freq= 0, CH_0, rank 1
2568 13:38:42.501774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 13:38:42.501856 ==
2570 13:38:42.501939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2571 13:38:42.502023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2572 13:38:42.502108 [CA 0] Center 39 (8~70) winsize 63
2573 13:38:42.502215 [CA 1] Center 39 (9~70) winsize 62
2574 13:38:42.502270 [CA 2] Center 35 (5~66) winsize 62
2575 13:38:42.502322 [CA 3] Center 34 (4~65) winsize 62
2576 13:38:42.502373 [CA 4] Center 33 (3~64) winsize 62
2577 13:38:42.502424 [CA 5] Center 33 (3~63) winsize 61
2578 13:38:42.502475
2579 13:38:42.502526 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2580 13:38:42.502578
2581 13:38:42.502633 [CATrainingPosCal] consider 2 rank data
2582 13:38:42.502690 u2DelayCellTimex100 = 270/100 ps
2583 13:38:42.502762 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2584 13:38:42.502829 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2585 13:38:42.502929 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2586 13:38:42.502995 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2587 13:38:42.503046 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2588 13:38:42.503096 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2589 13:38:42.503153
2590 13:38:42.503209 CA PerBit enable=1, Macro0, CA PI delay=33
2591 13:38:42.503267
2592 13:38:42.503319 [CBTSetCACLKResult] CA Dly = 33
2593 13:38:42.503388 CS Dly: 9 (0~41)
2594 13:38:42.503453
2595 13:38:42.503520 ----->DramcWriteLeveling(PI) begin...
2596 13:38:42.503587 ==
2597 13:38:42.503645 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 13:38:42.503702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 13:38:42.503758 ==
2600 13:38:42.503811 Write leveling (Byte 0): 32 => 32
2601 13:38:42.503862 Write leveling (Byte 1): 28 => 28
2602 13:38:42.503913 DramcWriteLeveling(PI) end<-----
2603 13:38:42.503964
2604 13:38:42.504014 ==
2605 13:38:42.504065 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 13:38:42.504119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 13:38:42.504173 ==
2608 13:38:42.504227 [Gating] SW mode calibration
2609 13:38:42.504312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2610 13:38:42.504394 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2611 13:38:42.504504 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2612 13:38:42.504629 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2613 13:38:42.504697 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 13:38:42.504755 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 13:38:42.504818 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2616 13:38:42.504899 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 13:38:42.504980 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 13:38:42.505060 0 15 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2619 13:38:42.505135 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2620 13:38:42.505188 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 13:38:42.505244 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 13:38:42.505329 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 13:38:42.505395 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 13:38:42.505493 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 13:38:42.505588 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 13:38:42.505661 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2627 13:38:42.505715 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2628 13:38:42.505771 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2629 13:38:42.505863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 13:38:42.505978 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 13:38:42.506078 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 13:38:42.506174 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 13:38:42.506243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2634 13:38:42.506300 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2635 13:38:42.506351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2636 13:38:42.506403 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 13:38:42.506484 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 13:38:42.506535 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 13:38:42.506586 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 13:38:42.506641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 13:38:42.506726 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 13:38:42.506799 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 13:38:42.506850 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 13:38:42.506901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 13:38:42.506953 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 13:38:42.507004 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 13:38:42.507054 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 13:38:42.507107 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 13:38:42.507159 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 13:38:42.507211 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2651 13:38:42.507266 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2652 13:38:42.507321 Total UI for P1: 0, mck2ui 16
2653 13:38:42.507374 best dqsien dly found for B0: ( 1, 3, 28)
2654 13:38:42.507426 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2655 13:38:42.507501 Total UI for P1: 0, mck2ui 16
2656 13:38:42.507589 best dqsien dly found for B1: ( 1, 4, 0)
2657 13:38:42.507654 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2658 13:38:42.507930 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2659 13:38:42.508045
2660 13:38:42.508127 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2661 13:38:42.508208 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2662 13:38:42.508286 [Gating] SW calibration Done
2663 13:38:42.508339 ==
2664 13:38:42.508402 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 13:38:42.508485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 13:38:42.508565 ==
2667 13:38:42.508645 RX Vref Scan: 0
2668 13:38:42.508725
2669 13:38:42.508802 RX Vref 0 -> 0, step: 1
2670 13:38:42.508859
2671 13:38:42.508920 RX Delay -40 -> 252, step: 8
2672 13:38:42.509002 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2673 13:38:42.509083 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2674 13:38:42.509164 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2675 13:38:42.509245 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2676 13:38:42.509328 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2677 13:38:42.509400 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2678 13:38:42.509486 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2679 13:38:42.509583 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2680 13:38:42.509712 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2681 13:38:42.509822 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2682 13:38:42.509919 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2683 13:38:42.510006 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2684 13:38:42.510088 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2685 13:38:42.510189 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2686 13:38:42.510257 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2687 13:38:42.510338 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2688 13:38:42.510413 ==
2689 13:38:42.510487 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 13:38:42.510558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 13:38:42.510625 ==
2692 13:38:42.510677 DQS Delay:
2693 13:38:42.510728 DQS0 = 0, DQS1 = 0
2694 13:38:42.510779 DQM Delay:
2695 13:38:42.510830 DQM0 = 119, DQM1 = 106
2696 13:38:42.510881 DQ Delay:
2697 13:38:42.510935 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2698 13:38:42.511029 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2699 13:38:42.511116 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2700 13:38:42.511168 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2701 13:38:42.511220
2702 13:38:42.511270
2703 13:38:42.511321 ==
2704 13:38:42.511372 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 13:38:42.511423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 13:38:42.511480 ==
2707 13:38:42.511564
2708 13:38:42.511646
2709 13:38:42.511725 TX Vref Scan disable
2710 13:38:42.511806 == TX Byte 0 ==
2711 13:38:42.511887 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2712 13:38:42.511967 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2713 13:38:42.512024 == TX Byte 1 ==
2714 13:38:42.512076 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2715 13:38:42.512136 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2716 13:38:42.512230 ==
2717 13:38:42.512325 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 13:38:42.512405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 13:38:42.512480 ==
2720 13:38:42.512533 TX Vref=22, minBit 5, minWin=25, winSum=413
2721 13:38:42.512589 TX Vref=24, minBit 0, minWin=26, winSum=419
2722 13:38:42.512641 TX Vref=26, minBit 1, minWin=26, winSum=429
2723 13:38:42.512711 TX Vref=28, minBit 10, minWin=26, winSum=431
2724 13:38:42.512793 TX Vref=30, minBit 5, minWin=26, winSum=429
2725 13:38:42.512903 TX Vref=32, minBit 4, minWin=26, winSum=428
2726 13:38:42.512981 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 28
2727 13:38:42.513036
2728 13:38:42.513087 Final TX Range 1 Vref 28
2729 13:38:42.513157
2730 13:38:42.513228 ==
2731 13:38:42.513290 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 13:38:42.513371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 13:38:42.513489 ==
2734 13:38:42.513544
2735 13:38:42.513596
2736 13:38:42.513661 TX Vref Scan disable
2737 13:38:42.513730 == TX Byte 0 ==
2738 13:38:42.513796 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2739 13:38:42.513878 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2740 13:38:42.513958 == TX Byte 1 ==
2741 13:38:42.514042 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2742 13:38:42.514123 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2743 13:38:42.514224
2744 13:38:42.514291 [DATLAT]
2745 13:38:42.514376 Freq=1200, CH0 RK0
2746 13:38:42.514430
2747 13:38:42.514488 DATLAT Default: 0xd
2748 13:38:42.514569 0, 0xFFFF, sum = 0
2749 13:38:42.514652 1, 0xFFFF, sum = 0
2750 13:38:42.514734 2, 0xFFFF, sum = 0
2751 13:38:42.514819 3, 0xFFFF, sum = 0
2752 13:38:42.514906 4, 0xFFFF, sum = 0
2753 13:38:42.514996 5, 0xFFFF, sum = 0
2754 13:38:42.515079 6, 0xFFFF, sum = 0
2755 13:38:42.515160 7, 0xFFFF, sum = 0
2756 13:38:42.515255 8, 0xFFFF, sum = 0
2757 13:38:42.515312 9, 0xFFFF, sum = 0
2758 13:38:42.515368 10, 0xFFFF, sum = 0
2759 13:38:42.515478 11, 0xFFFF, sum = 0
2760 13:38:42.515612 12, 0x0, sum = 1
2761 13:38:42.515744 13, 0x0, sum = 2
2762 13:38:42.515826 14, 0x0, sum = 3
2763 13:38:42.515908 15, 0x0, sum = 4
2764 13:38:42.516031 best_step = 13
2765 13:38:42.516114
2766 13:38:42.516194 ==
2767 13:38:42.516275 Dram Type= 6, Freq= 0, CH_0, rank 0
2768 13:38:42.516357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2769 13:38:42.516438 ==
2770 13:38:42.516536 RX Vref Scan: 1
2771 13:38:42.516633
2772 13:38:42.516714 Set Vref Range= 32 -> 127
2773 13:38:42.516793
2774 13:38:42.516873 RX Vref 32 -> 127, step: 1
2775 13:38:42.516953
2776 13:38:42.517036 RX Delay -21 -> 252, step: 4
2777 13:38:42.517157
2778 13:38:42.517238 Set Vref, RX VrefLevel [Byte0]: 32
2779 13:38:42.517318 [Byte1]: 32
2780 13:38:42.517398
2781 13:38:42.517492 Set Vref, RX VrefLevel [Byte0]: 33
2782 13:38:42.517606 [Byte1]: 33
2783 13:38:42.517704
2784 13:38:42.517791 Set Vref, RX VrefLevel [Byte0]: 34
2785 13:38:42.517873 [Byte1]: 34
2786 13:38:42.517958
2787 13:38:42.518040 Set Vref, RX VrefLevel [Byte0]: 35
2788 13:38:42.518122 [Byte1]: 35
2789 13:38:42.518244
2790 13:38:42.518302 Set Vref, RX VrefLevel [Byte0]: 36
2791 13:38:42.518355 [Byte1]: 36
2792 13:38:42.518425
2793 13:38:42.518478 Set Vref, RX VrefLevel [Byte0]: 37
2794 13:38:42.518529 [Byte1]: 37
2795 13:38:42.518595
2796 13:38:42.518654 Set Vref, RX VrefLevel [Byte0]: 38
2797 13:38:42.518710 [Byte1]: 38
2798 13:38:42.518763
2799 13:38:42.518829 Set Vref, RX VrefLevel [Byte0]: 39
2800 13:38:42.518917 [Byte1]: 39
2801 13:38:42.518995
2802 13:38:42.519075 Set Vref, RX VrefLevel [Byte0]: 40
2803 13:38:42.519158 [Byte1]: 40
2804 13:38:42.519241
2805 13:38:42.519322 Set Vref, RX VrefLevel [Byte0]: 41
2806 13:38:42.519402 [Byte1]: 41
2807 13:38:42.519512
2808 13:38:42.519592 Set Vref, RX VrefLevel [Byte0]: 42
2809 13:38:42.519678 [Byte1]: 42
2810 13:38:42.519758
2811 13:38:42.519839 Set Vref, RX VrefLevel [Byte0]: 43
2812 13:38:42.519920 [Byte1]: 43
2813 13:38:42.520001
2814 13:38:42.520280 Set Vref, RX VrefLevel [Byte0]: 44
2815 13:38:42.520366 [Byte1]: 44
2816 13:38:42.520447
2817 13:38:42.520530 Set Vref, RX VrefLevel [Byte0]: 45
2818 13:38:42.520611 [Byte1]: 45
2819 13:38:42.520724
2820 13:38:42.520804 Set Vref, RX VrefLevel [Byte0]: 46
2821 13:38:42.520885 [Byte1]: 46
2822 13:38:42.520969
2823 13:38:42.521088 Set Vref, RX VrefLevel [Byte0]: 47
2824 13:38:42.521176 [Byte1]: 47
2825 13:38:42.521250
2826 13:38:42.521316 Set Vref, RX VrefLevel [Byte0]: 48
2827 13:38:42.521404 [Byte1]: 48
2828 13:38:42.521460
2829 13:38:42.521531 Set Vref, RX VrefLevel [Byte0]: 49
2830 13:38:42.521689 [Byte1]: 49
2831 13:38:42.521770
2832 13:38:42.521850 Set Vref, RX VrefLevel [Byte0]: 50
2833 13:38:42.521959 [Byte1]: 50
2834 13:38:42.522047
2835 13:38:42.522129 Set Vref, RX VrefLevel [Byte0]: 51
2836 13:38:42.522254 [Byte1]: 51
2837 13:38:42.522375
2838 13:38:42.522487 Set Vref, RX VrefLevel [Byte0]: 52
2839 13:38:42.522583 [Byte1]: 52
2840 13:38:42.522683
2841 13:38:42.522768 Set Vref, RX VrefLevel [Byte0]: 53
2842 13:38:42.522851 [Byte1]: 53
2843 13:38:42.522944
2844 13:38:42.523024 Set Vref, RX VrefLevel [Byte0]: 54
2845 13:38:42.523106 [Byte1]: 54
2846 13:38:42.523164
2847 13:38:42.523248 Set Vref, RX VrefLevel [Byte0]: 55
2848 13:38:42.523329 [Byte1]: 55
2849 13:38:42.523409
2850 13:38:42.523489 Set Vref, RX VrefLevel [Byte0]: 56
2851 13:38:42.523569 [Byte1]: 56
2852 13:38:42.523651
2853 13:38:42.523735 Set Vref, RX VrefLevel [Byte0]: 57
2854 13:38:42.523817 [Byte1]: 57
2855 13:38:42.523918
2856 13:38:42.524015 Set Vref, RX VrefLevel [Byte0]: 58
2857 13:38:42.524096 [Byte1]: 58
2858 13:38:42.524180
2859 13:38:42.524263 Set Vref, RX VrefLevel [Byte0]: 59
2860 13:38:42.524346 [Byte1]: 59
2861 13:38:42.524425
2862 13:38:42.524505 Set Vref, RX VrefLevel [Byte0]: 60
2863 13:38:42.524586 [Byte1]: 60
2864 13:38:42.524698
2865 13:38:42.524779 Set Vref, RX VrefLevel [Byte0]: 61
2866 13:38:42.524834 [Byte1]: 61
2867 13:38:42.524886
2868 13:38:42.524937 Set Vref, RX VrefLevel [Byte0]: 62
2869 13:38:42.524988 [Byte1]: 62
2870 13:38:42.525039
2871 13:38:42.525090 Set Vref, RX VrefLevel [Byte0]: 63
2872 13:38:42.525167 [Byte1]: 63
2873 13:38:42.525249
2874 13:38:42.525361 Set Vref, RX VrefLevel [Byte0]: 64
2875 13:38:42.525442 [Byte1]: 64
2876 13:38:42.525521
2877 13:38:42.525602 Set Vref, RX VrefLevel [Byte0]: 65
2878 13:38:42.525684 [Byte1]: 65
2879 13:38:42.525766
2880 13:38:42.525860 Set Vref, RX VrefLevel [Byte0]: 66
2881 13:38:42.525941 [Byte1]: 66
2882 13:38:42.526021
2883 13:38:42.526119 Set Vref, RX VrefLevel [Byte0]: 67
2884 13:38:42.526198 [Byte1]: 67
2885 13:38:42.526298
2886 13:38:42.526379 Set Vref, RX VrefLevel [Byte0]: 68
2887 13:38:42.526459 [Byte1]: 68
2888 13:38:42.526539
2889 13:38:42.526620 Set Vref, RX VrefLevel [Byte0]: 69
2890 13:38:42.526675 [Byte1]: 69
2891 13:38:42.526762
2892 13:38:42.526844 Set Vref, RX VrefLevel [Byte0]: 70
2893 13:38:42.526955 [Byte1]: 70
2894 13:38:42.527035
2895 13:38:42.527115 Set Vref, RX VrefLevel [Byte0]: 71
2896 13:38:42.527199 [Byte1]: 71
2897 13:38:42.527311
2898 13:38:42.527392 Set Vref, RX VrefLevel [Byte0]: 72
2899 13:38:42.527473 [Byte1]: 72
2900 13:38:42.527552
2901 13:38:42.527634 Set Vref, RX VrefLevel [Byte0]: 73
2902 13:38:42.527714 [Byte1]: 73
2903 13:38:42.527798
2904 13:38:42.527883 Set Vref, RX VrefLevel [Byte0]: 74
2905 13:38:42.527978 [Byte1]: 74
2906 13:38:42.528072
2907 13:38:42.528154 Set Vref, RX VrefLevel [Byte0]: 75
2908 13:38:42.528234 [Byte1]: 75
2909 13:38:42.528319
2910 13:38:42.528400 Set Vref, RX VrefLevel [Byte0]: 76
2911 13:38:42.528480 [Byte1]: 76
2912 13:38:42.528560
2913 13:38:42.528656 Set Vref, RX VrefLevel [Byte0]: 77
2914 13:38:42.528750 [Byte1]: 77
2915 13:38:42.528834
2916 13:38:42.528915 Set Vref, RX VrefLevel [Byte0]: 78
2917 13:38:42.528995 [Byte1]: 78
2918 13:38:42.529075
2919 13:38:42.529174 Set Vref, RX VrefLevel [Byte0]: 79
2920 13:38:42.529248 [Byte1]: 79
2921 13:38:42.529302
2922 13:38:42.529388 Final RX Vref Byte 0 = 57 to rank0
2923 13:38:42.529440 Final RX Vref Byte 1 = 50 to rank0
2924 13:38:42.529491 Final RX Vref Byte 0 = 57 to rank1
2925 13:38:42.529542 Final RX Vref Byte 1 = 50 to rank1==
2926 13:38:42.529593 Dram Type= 6, Freq= 0, CH_0, rank 0
2927 13:38:42.529644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 13:38:42.529696 ==
2929 13:38:42.529790 DQS Delay:
2930 13:38:42.529916 DQS0 = 0, DQS1 = 0
2931 13:38:42.529997 DQM Delay:
2932 13:38:42.530077 DQM0 = 119, DQM1 = 106
2933 13:38:42.530177 DQ Delay:
2934 13:38:42.530245 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =116
2935 13:38:42.530300 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2936 13:38:42.530356 DQ8 =94, DQ9 =92, DQ10 =110, DQ11 =100
2937 13:38:42.530448 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =116
2938 13:38:42.530500
2939 13:38:42.530551
2940 13:38:42.530603 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2941 13:38:42.530655 CH0 RK0: MR19=403, MR18=11FC
2942 13:38:42.530707 CH0_RK0: MR19=0x403, MR18=0x11FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2943 13:38:42.530758
2944 13:38:42.530809 ----->DramcWriteLeveling(PI) begin...
2945 13:38:42.530865 ==
2946 13:38:42.530920 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 13:38:42.530990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 13:38:42.531042 ==
2949 13:38:42.531094 Write leveling (Byte 0): 30 => 30
2950 13:38:42.531159 Write leveling (Byte 1): 29 => 29
2951 13:38:42.531210 DramcWriteLeveling(PI) end<-----
2952 13:38:42.531260
2953 13:38:42.531328 ==
2954 13:38:42.531427 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 13:38:42.531511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 13:38:42.531592 ==
2957 13:38:42.531672 [Gating] SW mode calibration
2958 13:38:42.531754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2959 13:38:42.531836 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2960 13:38:42.531948 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2961 13:38:42.532033 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2962 13:38:42.532114 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 13:38:42.532194 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 13:38:42.532496 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 13:38:42.532616 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 13:38:42.532698 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2967 13:38:42.532831 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2968 13:38:42.532973 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2969 13:38:42.533069 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 13:38:42.533168 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 13:38:42.533251 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 13:38:42.533347 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 13:38:42.533427 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 13:38:42.533482 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 13:38:42.533534 1 0 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2976 13:38:42.533617 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2977 13:38:42.533699 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 13:38:42.533779 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 13:38:42.533867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 13:38:42.534002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 13:38:42.534112 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 13:38:42.534225 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 13:38:42.534308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2984 13:38:42.534389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2985 13:38:42.534474 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 13:38:42.534556 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 13:38:42.534637 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 13:38:42.534695 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 13:38:42.534748 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 13:38:42.534830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 13:38:42.534881 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 13:38:42.534933 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 13:38:42.534988 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 13:38:42.535040 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 13:38:42.535091 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 13:38:42.535142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 13:38:42.535197 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 13:38:42.535275 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 13:38:42.535356 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3000 13:38:42.535437 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3001 13:38:42.535536 Total UI for P1: 0, mck2ui 16
3002 13:38:42.535619 best dqsien dly found for B0: ( 1, 3, 28)
3003 13:38:42.535704 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3004 13:38:42.535802 Total UI for P1: 0, mck2ui 16
3005 13:38:42.535884 best dqsien dly found for B1: ( 1, 4, 0)
3006 13:38:42.535964 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3007 13:38:42.536093 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3008 13:38:42.536175
3009 13:38:42.734850 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3010 13:38:42.734992 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3011 13:38:42.735062 [Gating] SW calibration Done
3012 13:38:42.735129 ==
3013 13:38:42.735199 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 13:38:42.735257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 13:38:42.735320 ==
3016 13:38:42.735380 RX Vref Scan: 0
3017 13:38:42.735452
3018 13:38:42.735507 RX Vref 0 -> 0, step: 1
3019 13:38:42.735562
3020 13:38:42.735615 RX Delay -40 -> 252, step: 8
3021 13:38:42.735691 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3022 13:38:42.735747 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3023 13:38:42.735806 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3024 13:38:42.735863 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3025 13:38:42.735938 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3026 13:38:42.735993 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3027 13:38:42.736046 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3028 13:38:42.736099 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3029 13:38:42.736163 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3030 13:38:42.736252 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3031 13:38:42.736345 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3032 13:38:42.736442 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3033 13:38:42.736525 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3034 13:38:42.736608 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3035 13:38:42.736702 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3036 13:38:42.736785 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3037 13:38:42.736882 ==
3038 13:38:42.736973 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 13:38:42.737056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 13:38:42.737138 ==
3041 13:38:42.737231 DQS Delay:
3042 13:38:42.737319 DQS0 = 0, DQS1 = 0
3043 13:38:42.737416 DQM Delay:
3044 13:38:42.737498 DQM0 = 117, DQM1 = 107
3045 13:38:42.737580 DQ Delay:
3046 13:38:42.737670 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3047 13:38:42.737732 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3048 13:38:42.737785 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3049 13:38:42.737845 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3050 13:38:42.737940
3051 13:38:42.738022
3052 13:38:42.738102 ==
3053 13:38:42.738210 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 13:38:42.738268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 13:38:42.738328 ==
3056 13:38:42.738403
3057 13:38:42.738457
3058 13:38:42.738508 TX Vref Scan disable
3059 13:38:42.738561 == TX Byte 0 ==
3060 13:38:42.738613 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3061 13:38:42.738666 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3062 13:38:42.738755 == TX Byte 1 ==
3063 13:38:42.738849 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3064 13:38:42.738943 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3065 13:38:42.739025 ==
3066 13:38:42.739107 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 13:38:42.739191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 13:38:42.739284 ==
3069 13:38:42.739383 TX Vref=22, minBit 0, minWin=26, winSum=421
3070 13:38:42.739471 TX Vref=24, minBit 10, minWin=25, winSum=422
3071 13:38:42.739767 TX Vref=26, minBit 13, minWin=25, winSum=426
3072 13:38:42.739875 TX Vref=28, minBit 1, minWin=26, winSum=430
3073 13:38:42.739965 TX Vref=30, minBit 0, minWin=27, winSum=435
3074 13:38:42.740049 TX Vref=32, minBit 8, minWin=26, winSum=431
3075 13:38:42.740133 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
3076 13:38:42.740215
3077 13:38:42.740286 Final TX Range 1 Vref 30
3078 13:38:42.740366
3079 13:38:42.740430 ==
3080 13:38:42.740483 Dram Type= 6, Freq= 0, CH_0, rank 1
3081 13:38:42.740536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 13:38:42.740588 ==
3083 13:38:42.740640
3084 13:38:42.740691
3085 13:38:42.740756 TX Vref Scan disable
3086 13:38:42.740856 == TX Byte 0 ==
3087 13:38:42.740949 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3088 13:38:42.741033 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3089 13:38:42.741116 == TX Byte 1 ==
3090 13:38:42.741198 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3091 13:38:42.741286 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3092 13:38:42.741362
3093 13:38:42.741421 [DATLAT]
3094 13:38:42.741474 Freq=1200, CH0 RK1
3095 13:38:42.741536
3096 13:38:42.741623 DATLAT Default: 0xd
3097 13:38:42.741708 0, 0xFFFF, sum = 0
3098 13:38:42.741793 1, 0xFFFF, sum = 0
3099 13:38:42.741891 2, 0xFFFF, sum = 0
3100 13:38:42.741982 3, 0xFFFF, sum = 0
3101 13:38:42.742067 4, 0xFFFF, sum = 0
3102 13:38:42.742151 5, 0xFFFF, sum = 0
3103 13:38:42.742221 6, 0xFFFF, sum = 0
3104 13:38:42.742275 7, 0xFFFF, sum = 0
3105 13:38:42.742335 8, 0xFFFF, sum = 0
3106 13:38:42.742393 9, 0xFFFF, sum = 0
3107 13:38:42.742450 10, 0xFFFF, sum = 0
3108 13:38:42.742506 11, 0xFFFF, sum = 0
3109 13:38:42.742559 12, 0x0, sum = 1
3110 13:38:42.742612 13, 0x0, sum = 2
3111 13:38:42.742665 14, 0x0, sum = 3
3112 13:38:42.742717 15, 0x0, sum = 4
3113 13:38:42.742770 best_step = 13
3114 13:38:42.742827
3115 13:38:42.742883 ==
3116 13:38:42.742939 Dram Type= 6, Freq= 0, CH_0, rank 1
3117 13:38:42.742994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 13:38:42.743047 ==
3119 13:38:42.743099 RX Vref Scan: 0
3120 13:38:42.743151
3121 13:38:42.743202 RX Vref 0 -> 0, step: 1
3122 13:38:42.743255
3123 13:38:42.743306 RX Delay -21 -> 252, step: 4
3124 13:38:42.743368 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3125 13:38:42.743424 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3126 13:38:42.743480 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3127 13:38:42.743532 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3128 13:38:42.743584 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3129 13:38:42.743636 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3130 13:38:42.743688 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3131 13:38:42.743739 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3132 13:38:42.743791 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3133 13:38:42.743850 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3134 13:38:42.743905 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3135 13:38:42.743960 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3136 13:38:42.744014 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3137 13:38:42.744067 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3138 13:38:42.744120 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3139 13:38:42.744171 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3140 13:38:42.744223 ==
3141 13:38:42.744275 Dram Type= 6, Freq= 0, CH_0, rank 1
3142 13:38:42.744332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 13:38:42.744389 ==
3144 13:38:42.744441 DQS Delay:
3145 13:38:42.744496 DQS0 = 0, DQS1 = 0
3146 13:38:42.744554 DQM Delay:
3147 13:38:42.744607 DQM0 = 116, DQM1 = 107
3148 13:38:42.744658 DQ Delay:
3149 13:38:42.744710 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3150 13:38:42.744763 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3151 13:38:42.744819 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3152 13:38:42.744875 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3153 13:38:42.744928
3154 13:38:42.744983
3155 13:38:42.745035 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 403 ps
3156 13:38:42.745090 CH0 RK1: MR19=403, MR18=10EA
3157 13:38:42.745143 CH0_RK1: MR19=0x403, MR18=0x10EA, DQSOSC=403, MR23=63, INC=40, DEC=26
3158 13:38:42.745195 [RxdqsGatingPostProcess] freq 1200
3159 13:38:42.745248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3160 13:38:42.745300 best DQS0 dly(2T, 0.5T) = (0, 11)
3161 13:38:42.745358 best DQS1 dly(2T, 0.5T) = (0, 12)
3162 13:38:42.745413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3163 13:38:42.745468 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3164 13:38:42.745520 best DQS0 dly(2T, 0.5T) = (0, 11)
3165 13:38:42.745572 best DQS1 dly(2T, 0.5T) = (0, 12)
3166 13:38:42.745626 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3167 13:38:42.745678 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3168 13:38:42.745730 Pre-setting of DQS Precalculation
3169 13:38:42.745782 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3170 13:38:42.745839 ==
3171 13:38:42.745895 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 13:38:42.745948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 13:38:42.746003 ==
3174 13:38:42.746055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3175 13:38:42.746107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3176 13:38:42.746188 [CA 0] Center 37 (7~68) winsize 62
3177 13:38:42.746247 [CA 1] Center 37 (7~68) winsize 62
3178 13:38:42.746300 [CA 2] Center 34 (4~64) winsize 61
3179 13:38:42.746360 [CA 3] Center 33 (3~64) winsize 62
3180 13:38:42.746415 [CA 4] Center 34 (5~64) winsize 60
3181 13:38:42.746470 [CA 5] Center 33 (3~64) winsize 62
3182 13:38:42.746522
3183 13:38:42.746574 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3184 13:38:42.746626
3185 13:38:42.746691 [CATrainingPosCal] consider 1 rank data
3186 13:38:42.746750 u2DelayCellTimex100 = 270/100 ps
3187 13:38:42.746803 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3188 13:38:42.746863 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3189 13:38:42.746919 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 13:38:42.746972 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3191 13:38:42.747027 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3192 13:38:42.747079 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3193 13:38:42.747131
3194 13:38:42.747192 CA PerBit enable=1, Macro0, CA PI delay=33
3195 13:38:42.747255
3196 13:38:42.747307 [CBTSetCACLKResult] CA Dly = 33
3197 13:38:42.747367 CS Dly: 6 (0~37)
3198 13:38:42.747422 ==
3199 13:38:42.747476 Dram Type= 6, Freq= 0, CH_1, rank 1
3200 13:38:42.747531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 13:38:42.747584 ==
3202 13:38:42.747636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3203 13:38:42.747692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3204 13:38:42.747957 [CA 0] Center 37 (7~68) winsize 62
3205 13:38:42.748023 [CA 1] Center 38 (8~68) winsize 61
3206 13:38:42.748078 [CA 2] Center 34 (4~65) winsize 62
3207 13:38:42.748131 [CA 3] Center 33 (3~64) winsize 62
3208 13:38:42.748184 [CA 4] Center 34 (3~65) winsize 63
3209 13:38:42.748260 [CA 5] Center 33 (3~64) winsize 62
3210 13:38:42.748314
3211 13:38:42.748374 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3212 13:38:42.748430
3213 13:38:42.748482 [CATrainingPosCal] consider 2 rank data
3214 13:38:42.748539 u2DelayCellTimex100 = 270/100 ps
3215 13:38:42.748592 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3216 13:38:42.748645 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3217 13:38:42.748697 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3218 13:38:42.748771 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3219 13:38:42.748826 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3220 13:38:42.748886 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3221 13:38:42.748941
3222 13:38:42.748994 CA PerBit enable=1, Macro0, CA PI delay=33
3223 13:38:42.749049
3224 13:38:42.749101 [CBTSetCACLKResult] CA Dly = 33
3225 13:38:42.749154 CS Dly: 7 (0~40)
3226 13:38:42.749206
3227 13:38:42.749279 ----->DramcWriteLeveling(PI) begin...
3228 13:38:42.749334 ==
3229 13:38:42.749394 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 13:38:42.749450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 13:38:42.749506 ==
3232 13:38:42.749559 Write leveling (Byte 0): 24 => 24
3233 13:38:42.749612 Write leveling (Byte 1): 26 => 26
3234 13:38:42.749664 DramcWriteLeveling(PI) end<-----
3235 13:38:42.749717
3236 13:38:42.749790 ==
3237 13:38:42.749845 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 13:38:42.749907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 13:38:42.749962 ==
3240 13:38:42.750017 [Gating] SW mode calibration
3241 13:38:42.750084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3242 13:38:42.750181 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3243 13:38:42.750270 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
3244 13:38:42.750356 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3245 13:38:42.750440 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3246 13:38:42.750496 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 13:38:42.750554 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 13:38:42.750607 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3249 13:38:42.750660 0 15 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
3250 13:38:42.750712 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
3251 13:38:42.750766 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3252 13:38:42.750819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3253 13:38:42.750874 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 13:38:42.750933 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 13:38:42.750989 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 13:38:42.751045 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3257 13:38:42.751098 1 0 24 | B1->B0 | 2626 3434 | 0 1 | (0 0) (0 0)
3258 13:38:42.751150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3259 13:38:42.751202 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3260 13:38:42.751254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3261 13:38:42.751307 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 13:38:42.751359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 13:38:42.751417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 13:38:42.751474 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3265 13:38:42.751531 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3266 13:38:42.751583 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3267 13:38:42.751636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3268 13:38:42.751688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 13:38:42.751740 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 13:38:42.751792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 13:38:42.751844 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 13:38:42.751902 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 13:38:42.751957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 13:38:42.752012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 13:38:42.752067 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 13:38:42.752120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 13:38:42.752172 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 13:38:42.752224 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 13:38:42.752276 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 13:38:42.752328 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 13:38:42.752386 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3282 13:38:42.752442 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3283 13:38:42.752499 Total UI for P1: 0, mck2ui 16
3284 13:38:42.752571 best dqsien dly found for B0: ( 1, 3, 24)
3285 13:38:42.752625 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 13:38:42.752677 Total UI for P1: 0, mck2ui 16
3287 13:38:42.752730 best dqsien dly found for B1: ( 1, 3, 26)
3288 13:38:42.752782 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3289 13:38:42.752835 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3290 13:38:42.752894
3291 13:38:42.752950 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3292 13:38:42.753016 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3293 13:38:42.753080 [Gating] SW calibration Done
3294 13:38:42.753132 ==
3295 13:38:42.753185 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 13:38:42.753238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 13:38:42.753290 ==
3298 13:38:42.753342 RX Vref Scan: 0
3299 13:38:42.753400
3300 13:38:42.753456 RX Vref 0 -> 0, step: 1
3301 13:38:42.753519
3302 13:38:42.753579 RX Delay -40 -> 252, step: 8
3303 13:38:42.753632 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3304 13:38:42.753685 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3305 13:38:42.753737 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3306 13:38:42.753790 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3307 13:38:42.753847 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3308 13:38:42.753901 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3309 13:38:42.754177 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3310 13:38:42.754241 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3311 13:38:42.754295 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3312 13:38:42.754348 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3313 13:38:42.754407 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3314 13:38:42.754460 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3315 13:38:42.754516 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3316 13:38:42.754569 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3317 13:38:42.754643 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3318 13:38:42.754698 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3319 13:38:42.754753 ==
3320 13:38:42.754806 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 13:38:42.754859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 13:38:42.754912 ==
3323 13:38:42.754973 DQS Delay:
3324 13:38:42.755027 DQS0 = 0, DQS1 = 0
3325 13:38:42.755079 DQM Delay:
3326 13:38:42.755153 DQM0 = 118, DQM1 = 110
3327 13:38:42.755207 DQ Delay:
3328 13:38:42.755259 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3329 13:38:42.755315 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3330 13:38:42.755368 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3331 13:38:42.755420 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3332 13:38:42.755479
3333 13:38:42.755534
3334 13:38:42.755586 ==
3335 13:38:42.755660 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 13:38:42.755714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 13:38:42.755766 ==
3338 13:38:42.755818
3339 13:38:42.755873
3340 13:38:42.755925 TX Vref Scan disable
3341 13:38:42.755984 == TX Byte 0 ==
3342 13:38:42.756040 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3343 13:38:42.756093 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3344 13:38:42.756166 == TX Byte 1 ==
3345 13:38:42.756221 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3346 13:38:42.756274 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3347 13:38:42.756326 ==
3348 13:38:42.756378 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 13:38:42.756434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 13:38:42.756495 ==
3351 13:38:42.756548 TX Vref=22, minBit 8, minWin=25, winSum=415
3352 13:38:42.756600 TX Vref=24, minBit 10, minWin=25, winSum=421
3353 13:38:42.756674 TX Vref=26, minBit 10, minWin=25, winSum=428
3354 13:38:42.756729 TX Vref=28, minBit 9, minWin=26, winSum=434
3355 13:38:42.756782 TX Vref=30, minBit 9, minWin=25, winSum=431
3356 13:38:42.756835 TX Vref=32, minBit 9, minWin=25, winSum=424
3357 13:38:42.756887 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3358 13:38:42.756945
3359 13:38:42.757002 Final TX Range 1 Vref 28
3360 13:38:42.757056
3361 13:38:42.757111 ==
3362 13:38:42.757183 Dram Type= 6, Freq= 0, CH_1, rank 0
3363 13:38:42.757238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3364 13:38:42.757290 ==
3365 13:38:42.757342
3366 13:38:42.757394
3367 13:38:42.757452 TX Vref Scan disable
3368 13:38:42.757508 == TX Byte 0 ==
3369 13:38:42.757561 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3370 13:38:42.757614 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3371 13:38:42.757678 == TX Byte 1 ==
3372 13:38:42.757736 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3373 13:38:42.757788 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3374 13:38:42.757839
3375 13:38:42.757891 [DATLAT]
3376 13:38:42.757949 Freq=1200, CH1 RK0
3377 13:38:42.758005
3378 13:38:42.758059 DATLAT Default: 0xd
3379 13:38:42.758111 0, 0xFFFF, sum = 0
3380 13:38:42.758188 1, 0xFFFF, sum = 0
3381 13:38:42.758249 2, 0xFFFF, sum = 0
3382 13:38:42.758302 3, 0xFFFF, sum = 0
3383 13:38:42.758354 4, 0xFFFF, sum = 0
3384 13:38:42.758406 5, 0xFFFF, sum = 0
3385 13:38:42.758466 6, 0xFFFF, sum = 0
3386 13:38:42.758524 7, 0xFFFF, sum = 0
3387 13:38:42.758576 8, 0xFFFF, sum = 0
3388 13:38:42.758629 9, 0xFFFF, sum = 0
3389 13:38:42.758690 10, 0xFFFF, sum = 0
3390 13:38:42.758752 11, 0xFFFF, sum = 0
3391 13:38:42.758830 12, 0x0, sum = 1
3392 13:38:42.758915 13, 0x0, sum = 2
3393 13:38:42.759011 14, 0x0, sum = 3
3394 13:38:42.759097 15, 0x0, sum = 4
3395 13:38:42.759163 best_step = 13
3396 13:38:42.759239
3397 13:38:42.759294 ==
3398 13:38:42.759347 Dram Type= 6, Freq= 0, CH_1, rank 0
3399 13:38:42.759400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3400 13:38:42.759460 ==
3401 13:38:42.759516 RX Vref Scan: 1
3402 13:38:42.759571
3403 13:38:42.759622 Set Vref Range= 32 -> 127
3404 13:38:42.759674
3405 13:38:42.759753 RX Vref 32 -> 127, step: 1
3406 13:38:42.759837
3407 13:38:42.759919 RX Delay -21 -> 252, step: 4
3408 13:38:42.760009
3409 13:38:42.760096 Set Vref, RX VrefLevel [Byte0]: 32
3410 13:38:42.760162 [Byte1]: 32
3411 13:38:42.760226
3412 13:38:42.760286 Set Vref, RX VrefLevel [Byte0]: 33
3413 13:38:42.760339 [Byte1]: 33
3414 13:38:42.760390
3415 13:38:42.760442 Set Vref, RX VrefLevel [Byte0]: 34
3416 13:38:42.760502 [Byte1]: 34
3417 13:38:42.760554
3418 13:38:42.760609 Set Vref, RX VrefLevel [Byte0]: 35
3419 13:38:42.760661 [Byte1]: 35
3420 13:38:42.760713
3421 13:38:42.760784 Set Vref, RX VrefLevel [Byte0]: 36
3422 13:38:42.760837 [Byte1]: 36
3423 13:38:42.760888
3424 13:38:42.760939 Set Vref, RX VrefLevel [Byte0]: 37
3425 13:38:42.761000 [Byte1]: 37
3426 13:38:42.761052
3427 13:38:42.761104 Set Vref, RX VrefLevel [Byte0]: 38
3428 13:38:42.761157 [Byte1]: 38
3429 13:38:42.761209
3430 13:38:42.761285 Set Vref, RX VrefLevel [Byte0]: 39
3431 13:38:42.761339 [Byte1]: 39
3432 13:38:42.761392
3433 13:38:42.761443 Set Vref, RX VrefLevel [Byte0]: 40
3434 13:38:42.761503 [Byte1]: 40
3435 13:38:42.761556
3436 13:38:42.761608 Set Vref, RX VrefLevel [Byte0]: 41
3437 13:38:42.761660 [Byte1]: 41
3438 13:38:42.761714
3439 13:38:42.761785 Set Vref, RX VrefLevel [Byte0]: 42
3440 13:38:42.761838 [Byte1]: 42
3441 13:38:42.761890
3442 13:38:42.761947 Set Vref, RX VrefLevel [Byte0]: 43
3443 13:38:42.762003 [Byte1]: 43
3444 13:38:42.762055
3445 13:38:42.762107 Set Vref, RX VrefLevel [Byte0]: 44
3446 13:38:42.762158 [Byte1]: 44
3447 13:38:42.762224
3448 13:38:42.762278 Set Vref, RX VrefLevel [Byte0]: 45
3449 13:38:42.762353 [Byte1]: 45
3450 13:38:42.762408
3451 13:38:42.762459 Set Vref, RX VrefLevel [Byte0]: 46
3452 13:38:42.762512 [Byte1]: 46
3453 13:38:42.762570
3454 13:38:42.762625 Set Vref, RX VrefLevel [Byte0]: 47
3455 13:38:42.762677 [Byte1]: 47
3456 13:38:42.762732
3457 13:38:42.762784 Set Vref, RX VrefLevel [Byte0]: 48
3458 13:38:42.762836 [Byte1]: 48
3459 13:38:42.762888
3460 13:38:42.762958 Set Vref, RX VrefLevel [Byte0]: 49
3461 13:38:42.763011 [Byte1]: 49
3462 13:38:42.763070
3463 13:38:42.763124 Set Vref, RX VrefLevel [Byte0]: 50
3464 13:38:42.763176 [Byte1]: 50
3465 13:38:42.763228
3466 13:38:42.763280 Set Vref, RX VrefLevel [Byte0]: 51
3467 13:38:42.763334 [Byte1]: 51
3468 13:38:42.763386
3469 13:38:42.763458 Set Vref, RX VrefLevel [Byte0]: 52
3470 13:38:42.763711 [Byte1]: 52
3471 13:38:42.763771
3472 13:38:42.763824 Set Vref, RX VrefLevel [Byte0]: 53
3473 13:38:42.763876 [Byte1]: 53
3474 13:38:42.763929
3475 13:38:42.764001 Set Vref, RX VrefLevel [Byte0]: 54
3476 13:38:42.764057 [Byte1]: 54
3477 13:38:42.764116
3478 13:38:42.764170 Set Vref, RX VrefLevel [Byte0]: 55
3479 13:38:42.764225 [Byte1]: 55
3480 13:38:42.764277
3481 13:38:42.764328 Set Vref, RX VrefLevel [Byte0]: 56
3482 13:38:42.764380 [Byte1]: 56
3483 13:38:42.764431
3484 13:38:42.764502 Set Vref, RX VrefLevel [Byte0]: 57
3485 13:38:42.764559 [Byte1]: 57
3486 13:38:42.764619
3487 13:38:42.764671 Set Vref, RX VrefLevel [Byte0]: 58
3488 13:38:42.764723 [Byte1]: 58
3489 13:38:42.764775
3490 13:38:42.764826 Set Vref, RX VrefLevel [Byte0]: 59
3491 13:38:42.764879 [Byte1]: 59
3492 13:38:42.764930
3493 13:38:42.765003 Set Vref, RX VrefLevel [Byte0]: 60
3494 13:38:42.765060 [Byte1]: 60
3495 13:38:42.765119
3496 13:38:42.765173 Set Vref, RX VrefLevel [Byte0]: 61
3497 13:38:42.765225 [Byte1]: 61
3498 13:38:42.765276
3499 13:38:42.765328 Set Vref, RX VrefLevel [Byte0]: 62
3500 13:38:42.765380 [Byte1]: 62
3501 13:38:42.765431
3502 13:38:42.765483 Set Vref, RX VrefLevel [Byte0]: 63
3503 13:38:42.765554 [Byte1]: 63
3504 13:38:42.765614
3505 13:38:42.765669 Set Vref, RX VrefLevel [Byte0]: 64
3506 13:38:42.765723 [Byte1]: 64
3507 13:38:42.765775
3508 13:38:42.765826 Set Vref, RX VrefLevel [Byte0]: 65
3509 13:38:42.765878 [Byte1]: 65
3510 13:38:42.765930
3511 13:38:42.765981 Set Vref, RX VrefLevel [Byte0]: 66
3512 13:38:42.766072 [Byte1]: 66
3513 13:38:42.766174
3514 13:38:42.766232 Set Vref, RX VrefLevel [Byte0]: 67
3515 13:38:42.766285 [Byte1]: 67
3516 13:38:42.766337
3517 13:38:42.766388 Set Vref, RX VrefLevel [Byte0]: 68
3518 13:38:42.766440 [Byte1]: 68
3519 13:38:42.766492
3520 13:38:42.766563 Final RX Vref Byte 0 = 45 to rank0
3521 13:38:42.766623 Final RX Vref Byte 1 = 53 to rank0
3522 13:38:42.766680 Final RX Vref Byte 0 = 45 to rank1
3523 13:38:42.766740 Final RX Vref Byte 1 = 53 to rank1==
3524 13:38:42.766794 Dram Type= 6, Freq= 0, CH_1, rank 0
3525 13:38:42.766846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 13:38:42.766898 ==
3527 13:38:42.766950 DQS Delay:
3528 13:38:42.767011 DQS0 = 0, DQS1 = 0
3529 13:38:42.767071 DQM Delay:
3530 13:38:42.767132 DQM0 = 116, DQM1 = 110
3531 13:38:42.767187 DQ Delay:
3532 13:38:42.767239 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3533 13:38:42.767292 DQ4 =112, DQ5 =128, DQ6 =124, DQ7 =114
3534 13:38:42.767344 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3535 13:38:42.767396 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3536 13:38:42.767479
3537 13:38:42.767573
3538 13:38:42.767668 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3539 13:38:42.767757 CH1 RK0: MR19=403, MR18=3F6
3540 13:38:42.767816 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3541 13:38:42.767871
3542 13:38:42.767923 ----->DramcWriteLeveling(PI) begin...
3543 13:38:42.767976 ==
3544 13:38:42.768044 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 13:38:42.768106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 13:38:42.768163 ==
3547 13:38:42.768216 Write leveling (Byte 0): 25 => 25
3548 13:38:42.768271 Write leveling (Byte 1): 27 => 27
3549 13:38:42.768323 DramcWriteLeveling(PI) end<-----
3550 13:38:42.768375
3551 13:38:42.768426 ==
3552 13:38:42.768478 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 13:38:42.768539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 13:38:42.768601 ==
3555 13:38:42.768663 [Gating] SW mode calibration
3556 13:38:42.768716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3557 13:38:42.768769 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3558 13:38:42.768824 0 15 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3559 13:38:42.768876 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3560 13:38:42.768928 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 13:38:42.768980 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 13:38:42.769032 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 13:38:42.769101 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 13:38:42.769161 0 15 24 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (1 0)
3565 13:38:42.769217 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3566 13:38:42.769269 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3567 13:38:42.769320 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3568 13:38:42.769375 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 13:38:42.769427 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 13:38:42.769480 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 13:38:42.769532 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 13:38:42.769605 1 0 24 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
3573 13:38:42.769664 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3574 13:38:42.769720 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3575 13:38:42.769771 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 13:38:42.769823 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 13:38:42.769880 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 13:38:42.769932 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 13:38:42.769983 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 13:38:42.770035 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3581 13:38:42.770117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3582 13:38:42.770208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 13:38:42.770266 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 13:38:42.770319 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 13:38:42.770371 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 13:38:42.770427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 13:38:42.770478 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 13:38:42.770530 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 13:38:42.770603 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 13:38:42.770850 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 13:38:42.770911 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 13:38:42.770968 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 13:38:42.771021 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 13:38:42.771089 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 13:38:42.771148 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 13:38:42.771200 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3597 13:38:42.771260 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3598 13:38:42.771315 Total UI for P1: 0, mck2ui 16
3599 13:38:42.771369 best dqsien dly found for B1: ( 1, 3, 24)
3600 13:38:42.771421 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3601 13:38:42.771477 Total UI for P1: 0, mck2ui 16
3602 13:38:42.771528 best dqsien dly found for B0: ( 1, 3, 26)
3603 13:38:42.771592 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3604 13:38:42.771652 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3605 13:38:42.771704
3606 13:38:42.771761 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3607 13:38:42.771816 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3608 13:38:42.771868 [Gating] SW calibration Done
3609 13:38:42.771920 ==
3610 13:38:42.771972 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 13:38:42.772027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 13:38:42.772085 ==
3613 13:38:42.772176 RX Vref Scan: 0
3614 13:38:42.772264
3615 13:38:42.772348 RX Vref 0 -> 0, step: 1
3616 13:38:42.772429
3617 13:38:42.772512 RX Delay -40 -> 252, step: 8
3618 13:38:42.772598 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3619 13:38:42.772679 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3620 13:38:42.772739 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3621 13:38:42.772795 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3622 13:38:42.772847 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3623 13:38:42.772901 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3624 13:38:42.772953 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3625 13:38:42.773005 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3626 13:38:42.773056 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3627 13:38:42.773110 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3628 13:38:42.773205 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3629 13:38:42.773296 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3630 13:38:42.773379 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3631 13:38:42.773461 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3632 13:38:42.773541 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3633 13:38:42.773595 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3634 13:38:42.773665 ==
3635 13:38:42.773733 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 13:38:42.773797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 13:38:42.773850 ==
3638 13:38:42.773903 DQS Delay:
3639 13:38:42.773955 DQS0 = 0, DQS1 = 0
3640 13:38:42.774007 DQM Delay:
3641 13:38:42.774075 DQM0 = 116, DQM1 = 110
3642 13:38:42.774128 DQ Delay:
3643 13:38:42.774211 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3644 13:38:42.774276 DQ4 =111, DQ5 =123, DQ6 =127, DQ7 =115
3645 13:38:42.774339 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3646 13:38:42.774394 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3647 13:38:42.774455
3648 13:38:42.774510
3649 13:38:42.774573 ==
3650 13:38:42.774627 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 13:38:42.774698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 13:38:42.774762 ==
3653 13:38:42.774825
3654 13:38:42.774884
3655 13:38:42.774938 TX Vref Scan disable
3656 13:38:42.774997 == TX Byte 0 ==
3657 13:38:42.775049 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 13:38:42.775102 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 13:38:42.775178 == TX Byte 1 ==
3660 13:38:42.775260 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3661 13:38:42.775320 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3662 13:38:42.775393 ==
3663 13:38:42.775448 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 13:38:42.775508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 13:38:42.775561 ==
3666 13:38:42.775612 TX Vref=22, minBit 1, minWin=26, winSum=423
3667 13:38:42.775665 TX Vref=24, minBit 8, minWin=26, winSum=432
3668 13:38:42.775718 TX Vref=26, minBit 9, minWin=26, winSum=433
3669 13:38:42.775770 TX Vref=28, minBit 9, minWin=26, winSum=435
3670 13:38:42.775845 TX Vref=30, minBit 8, minWin=26, winSum=433
3671 13:38:42.775914 TX Vref=32, minBit 9, minWin=26, winSum=434
3672 13:38:42.775971 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 28
3673 13:38:42.776024
3674 13:38:42.776084 Final TX Range 1 Vref 28
3675 13:38:42.776147
3676 13:38:42.776202 ==
3677 13:38:42.776253 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 13:38:42.776357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 13:38:42.776455 ==
3680 13:38:42.776537
3681 13:38:42.776636
3682 13:38:42.776695 TX Vref Scan disable
3683 13:38:42.776760 == TX Byte 0 ==
3684 13:38:42.776820 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3685 13:38:42.776897 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3686 13:38:42.776957 == TX Byte 1 ==
3687 13:38:42.777011 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3688 13:38:42.777063 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3689 13:38:42.777115
3690 13:38:42.777167 [DATLAT]
3691 13:38:42.777218 Freq=1200, CH1 RK1
3692 13:38:42.777270
3693 13:38:42.777326 DATLAT Default: 0xd
3694 13:38:42.777386 0, 0xFFFF, sum = 0
3695 13:38:42.777460 1, 0xFFFF, sum = 0
3696 13:38:42.777517 2, 0xFFFF, sum = 0
3697 13:38:42.777570 3, 0xFFFF, sum = 0
3698 13:38:42.777623 4, 0xFFFF, sum = 0
3699 13:38:42.777676 5, 0xFFFF, sum = 0
3700 13:38:42.777728 6, 0xFFFF, sum = 0
3701 13:38:42.777781 7, 0xFFFF, sum = 0
3702 13:38:42.777840 8, 0xFFFF, sum = 0
3703 13:38:42.777897 9, 0xFFFF, sum = 0
3704 13:38:42.777972 10, 0xFFFF, sum = 0
3705 13:38:42.778027 11, 0xFFFF, sum = 0
3706 13:38:42.778081 12, 0x0, sum = 1
3707 13:38:42.778133 13, 0x0, sum = 2
3708 13:38:42.778200 14, 0x0, sum = 3
3709 13:38:42.778254 15, 0x0, sum = 4
3710 13:38:42.778313 best_step = 13
3711 13:38:42.778369
3712 13:38:42.778426 ==
3713 13:38:42.778493 Dram Type= 6, Freq= 0, CH_1, rank 1
3714 13:38:42.778547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3715 13:38:42.778599 ==
3716 13:38:42.778651 RX Vref Scan: 0
3717 13:38:42.778702
3718 13:38:42.778753 RX Vref 0 -> 0, step: 1
3719 13:38:42.778811
3720 13:38:42.778867 RX Delay -21 -> 252, step: 4
3721 13:38:42.778932 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3722 13:38:42.778991 iDelay=199, Bit 1, Center 110 (47 ~ 174) 128
3723 13:38:42.779043 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3724 13:38:42.779094 iDelay=199, Bit 3, Center 112 (51 ~ 174) 124
3725 13:38:42.779145 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3726 13:38:42.779196 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3727 13:38:42.779247 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3728 13:38:42.779506 iDelay=199, Bit 7, Center 110 (43 ~ 178) 136
3729 13:38:42.779568 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3730 13:38:42.779622 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3731 13:38:42.779675 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3732 13:38:42.779727 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3733 13:38:42.779779 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3734 13:38:42.779838 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3735 13:38:42.779895 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3736 13:38:42.779971 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3737 13:38:42.780025 ==
3738 13:38:42.780077 Dram Type= 6, Freq= 0, CH_1, rank 1
3739 13:38:42.780130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3740 13:38:42.780182 ==
3741 13:38:42.780234 DQS Delay:
3742 13:38:42.780286 DQS0 = 0, DQS1 = 0
3743 13:38:42.780345 DQM Delay:
3744 13:38:42.780400 DQM0 = 116, DQM1 = 109
3745 13:38:42.780475 DQ Delay:
3746 13:38:42.780529 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3747 13:38:42.780580 DQ4 =114, DQ5 =126, DQ6 =132, DQ7 =110
3748 13:38:42.780632 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3749 13:38:42.780684 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3750 13:38:42.780736
3751 13:38:42.780787
3752 13:38:42.780845 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3753 13:38:42.780928 CH1 RK1: MR19=303, MR18=F4EF
3754 13:38:42.780988 CH1_RK1: MR19=0x303, MR18=0xF4EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3755 13:38:42.781041 [RxdqsGatingPostProcess] freq 1200
3756 13:38:42.781094 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3757 13:38:42.781146 best DQS0 dly(2T, 0.5T) = (0, 11)
3758 13:38:42.781198 best DQS1 dly(2T, 0.5T) = (0, 11)
3759 13:38:42.781249 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3760 13:38:42.781301 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3761 13:38:42.781375 best DQS0 dly(2T, 0.5T) = (0, 11)
3762 13:38:42.781448 best DQS1 dly(2T, 0.5T) = (0, 11)
3763 13:38:42.781505 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3764 13:38:42.781558 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3765 13:38:42.781616 Pre-setting of DQS Precalculation
3766 13:38:42.781671 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3767 13:38:42.781724 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3768 13:38:42.781776 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3769 13:38:42.781839
3770 13:38:42.781921
3771 13:38:42.782008 [Calibration Summary] 2400 Mbps
3772 13:38:42.782099 CH 0, Rank 0
3773 13:38:42.782190 SW Impedance : PASS
3774 13:38:42.782289 DUTY Scan : NO K
3775 13:38:42.782388 ZQ Calibration : PASS
3776 13:38:42.782492 Jitter Meter : NO K
3777 13:38:42.782576 CBT Training : PASS
3778 13:38:42.782667 Write leveling : PASS
3779 13:38:42.782760 RX DQS gating : PASS
3780 13:38:42.782857 RX DQ/DQS(RDDQC) : PASS
3781 13:38:42.782957 TX DQ/DQS : PASS
3782 13:38:42.783041 RX DATLAT : PASS
3783 13:38:42.783123 RX DQ/DQS(Engine): PASS
3784 13:38:42.783204 TX OE : NO K
3785 13:38:42.783286 All Pass.
3786 13:38:42.783379
3787 13:38:42.783452 CH 0, Rank 1
3788 13:38:42.783508 SW Impedance : PASS
3789 13:38:42.783563 DUTY Scan : NO K
3790 13:38:42.783615 ZQ Calibration : PASS
3791 13:38:42.783667 Jitter Meter : NO K
3792 13:38:42.783721 CBT Training : PASS
3793 13:38:42.783772 Write leveling : PASS
3794 13:38:42.783824 RX DQS gating : PASS
3795 13:38:42.783898 RX DQ/DQS(RDDQC) : PASS
3796 13:38:42.783971 TX DQ/DQS : PASS
3797 13:38:42.784024 RX DATLAT : PASS
3798 13:38:42.784078 RX DQ/DQS(Engine): PASS
3799 13:38:42.784130 TX OE : NO K
3800 13:38:42.784182 All Pass.
3801 13:38:42.784267
3802 13:38:42.784349 CH 1, Rank 0
3803 13:38:42.784435 SW Impedance : PASS
3804 13:38:42.784527 DUTY Scan : NO K
3805 13:38:42.784588 ZQ Calibration : PASS
3806 13:38:42.784645 Jitter Meter : NO K
3807 13:38:42.784699 CBT Training : PASS
3808 13:38:42.784752 Write leveling : PASS
3809 13:38:42.784804 RX DQS gating : PASS
3810 13:38:42.784856 RX DQ/DQS(RDDQC) : PASS
3811 13:38:42.784908 TX DQ/DQS : PASS
3812 13:38:42.784980 RX DATLAT : PASS
3813 13:38:42.785037 RX DQ/DQS(Engine): PASS
3814 13:38:42.785094 TX OE : NO K
3815 13:38:42.785149 All Pass.
3816 13:38:42.785202
3817 13:38:42.785254 CH 1, Rank 1
3818 13:38:42.785306 SW Impedance : PASS
3819 13:38:42.785358 DUTY Scan : NO K
3820 13:38:42.785409 ZQ Calibration : PASS
3821 13:38:42.785476 Jitter Meter : NO K
3822 13:38:42.785534 CBT Training : PASS
3823 13:38:42.785586 Write leveling : PASS
3824 13:38:42.785644 RX DQS gating : PASS
3825 13:38:42.785699 RX DQ/DQS(RDDQC) : PASS
3826 13:38:42.785751 TX DQ/DQS : PASS
3827 13:38:42.785803 RX DATLAT : PASS
3828 13:38:42.785854 RX DQ/DQS(Engine): PASS
3829 13:38:42.785906 TX OE : NO K
3830 13:38:42.785959 All Pass.
3831 13:38:42.786055
3832 13:38:42.786137 DramC Write-DBI off
3833 13:38:42.786224 PER_BANK_REFRESH: Hybrid Mode
3834 13:38:42.786283 TX_TRACKING: ON
3835 13:38:42.786336 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3836 13:38:42.786390 [FAST_K] Save calibration result to emmc
3837 13:38:42.786441 dramc_set_vcore_voltage set vcore to 650000
3838 13:38:42.786510 Read voltage for 600, 5
3839 13:38:42.786565 Vio18 = 0
3840 13:38:42.786620 Vcore = 650000
3841 13:38:42.786673 Vdram = 0
3842 13:38:42.786729 Vddq = 0
3843 13:38:42.786783 Vmddr = 0
3844 13:38:42.786837 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3845 13:38:42.786889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3846 13:38:42.786941 MEM_TYPE=3, freq_sel=19
3847 13:38:42.786992 sv_algorithm_assistance_LP4_1600
3848 13:38:42.787063 ============ PULL DRAM RESETB DOWN ============
3849 13:38:42.787120 ========== PULL DRAM RESETB DOWN end =========
3850 13:38:42.787174 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 13:38:42.787226 ===================================
3852 13:38:42.787278 LPDDR4 DRAM CONFIGURATION
3853 13:38:42.787339 ===================================
3854 13:38:42.787391 EX_ROW_EN[0] = 0x0
3855 13:38:42.787443 EX_ROW_EN[1] = 0x0
3856 13:38:42.787494 LP4Y_EN = 0x0
3857 13:38:42.787568 WORK_FSP = 0x0
3858 13:38:42.787624 WL = 0x2
3859 13:38:42.787676 RL = 0x2
3860 13:38:42.787728 BL = 0x2
3861 13:38:42.787779 RPST = 0x0
3862 13:38:42.787838 RD_PRE = 0x0
3863 13:38:42.787892 WR_PRE = 0x1
3864 13:38:42.787944 WR_PST = 0x0
3865 13:38:42.787995 DBI_WR = 0x0
3866 13:38:42.788065 DBI_RD = 0x0
3867 13:38:42.788122 OTF = 0x1
3868 13:38:42.788176 ===================================
3869 13:38:42.788235 ===================================
3870 13:38:42.788289 ANA top config
3871 13:38:42.788541 ===================================
3872 13:38:42.788619 DLL_ASYNC_EN = 0
3873 13:38:42.788677 ALL_SLAVE_EN = 1
3874 13:38:42.788730 NEW_RANK_MODE = 1
3875 13:38:42.788783 DLL_IDLE_MODE = 1
3876 13:38:42.788841 LP45_APHY_COMB_EN = 1
3877 13:38:42.788906 TX_ODT_DIS = 1
3878 13:38:42.789003 NEW_8X_MODE = 1
3879 13:38:42.789097 ===================================
3880 13:38:42.789158 ===================================
3881 13:38:42.789211 data_rate = 1200
3882 13:38:42.789282 CKR = 1
3883 13:38:42.789336 DQ_P2S_RATIO = 8
3884 13:38:42.789388 ===================================
3885 13:38:42.789449 CA_P2S_RATIO = 8
3886 13:38:42.789504 DQ_CA_OPEN = 0
3887 13:38:42.789568 DQ_SEMI_OPEN = 0
3888 13:38:42.789638 CA_SEMI_OPEN = 0
3889 13:38:42.789696 CA_FULL_RATE = 0
3890 13:38:42.789748 DQ_CKDIV4_EN = 1
3891 13:38:42.789812 CA_CKDIV4_EN = 1
3892 13:38:42.789886 CA_PREDIV_EN = 0
3893 13:38:42.789951 PH8_DLY = 0
3894 13:38:42.790004 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3895 13:38:42.790057 DQ_AAMCK_DIV = 4
3896 13:38:42.790171 CA_AAMCK_DIV = 4
3897 13:38:42.790229 CA_ADMCK_DIV = 4
3898 13:38:42.790281 DQ_TRACK_CA_EN = 0
3899 13:38:42.790358 CA_PICK = 600
3900 13:38:42.790410 CA_MCKIO = 600
3901 13:38:42.790462 MCKIO_SEMI = 0
3902 13:38:42.790518 PLL_FREQ = 2288
3903 13:38:42.790577 DQ_UI_PI_RATIO = 32
3904 13:38:42.790637 CA_UI_PI_RATIO = 0
3905 13:38:42.790693 ===================================
3906 13:38:42.790748 ===================================
3907 13:38:42.790802 memory_type:LPDDR4
3908 13:38:42.790860 GP_NUM : 10
3909 13:38:42.790913 SRAM_EN : 1
3910 13:38:42.790967 MD32_EN : 0
3911 13:38:42.791019 ===================================
3912 13:38:42.791080 [ANA_INIT] >>>>>>>>>>>>>>
3913 13:38:42.791141 <<<<<< [CONFIGURE PHASE]: ANA_TX
3914 13:38:42.791195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3915 13:38:42.791247 ===================================
3916 13:38:42.791302 data_rate = 1200,PCW = 0X5800
3917 13:38:42.791354 ===================================
3918 13:38:42.791411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3919 13:38:42.791464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3920 13:38:42.791519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3921 13:38:42.791577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3922 13:38:42.791641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3923 13:38:42.791697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3924 13:38:42.791749 [ANA_INIT] flow start
3925 13:38:42.791801 [ANA_INIT] PLL >>>>>>>>
3926 13:38:42.791855 [ANA_INIT] PLL <<<<<<<<
3927 13:38:42.791907 [ANA_INIT] MIDPI >>>>>>>>
3928 13:38:42.791965 [ANA_INIT] MIDPI <<<<<<<<
3929 13:38:42.792019 [ANA_INIT] DLL >>>>>>>>
3930 13:38:42.792082 [ANA_INIT] flow end
3931 13:38:42.792141 ============ LP4 DIFF to SE enter ============
3932 13:38:42.792194 ============ LP4 DIFF to SE exit ============
3933 13:38:42.792246 [ANA_INIT] <<<<<<<<<<<<<
3934 13:38:42.792297 [Flow] Enable top DCM control >>>>>
3935 13:38:42.792349 [Flow] Enable top DCM control <<<<<
3936 13:38:42.792403 Enable DLL master slave shuffle
3937 13:38:42.792456 ==============================================================
3938 13:38:42.792555 Gating Mode config
3939 13:38:42.792654 ==============================================================
3940 13:38:42.792737 Config description:
3941 13:38:42.792822 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3942 13:38:42.792880 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3943 13:38:42.792937 SELPH_MODE 0: By rank 1: By Phase
3944 13:38:42.792997 ==============================================================
3945 13:38:42.793061 GAT_TRACK_EN = 1
3946 13:38:42.793126 RX_GATING_MODE = 2
3947 13:38:42.793179 RX_GATING_TRACK_MODE = 2
3948 13:38:42.793231 SELPH_MODE = 1
3949 13:38:42.793283 PICG_EARLY_EN = 1
3950 13:38:42.793335 VALID_LAT_VALUE = 1
3951 13:38:42.793387 ==============================================================
3952 13:38:42.793443 Enter into Gating configuration >>>>
3953 13:38:42.793501 Exit from Gating configuration <<<<
3954 13:38:42.793569 Enter into DVFS_PRE_config >>>>>
3955 13:38:42.793628 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3956 13:38:42.793684 Exit from DVFS_PRE_config <<<<<
3957 13:38:42.793737 Enter into PICG configuration >>>>
3958 13:38:42.793788 Exit from PICG configuration <<<<
3959 13:38:42.793840 [RX_INPUT] configuration >>>>>
3960 13:38:42.793891 [RX_INPUT] configuration <<<<<
3961 13:38:42.793946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3962 13:38:42.794004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3963 13:38:42.794079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3964 13:38:42.794174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3965 13:38:42.794233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3966 13:38:42.794286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3967 13:38:42.794338 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3968 13:38:42.794390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3969 13:38:42.794446 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3970 13:38:42.794503 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3971 13:38:42.794559 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3972 13:38:42.794823 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3973 13:38:42.794883 ===================================
3974 13:38:42.794940 LPDDR4 DRAM CONFIGURATION
3975 13:38:42.794999 ===================================
3976 13:38:42.795056 EX_ROW_EN[0] = 0x0
3977 13:38:42.795129 EX_ROW_EN[1] = 0x0
3978 13:38:42.795184 LP4Y_EN = 0x0
3979 13:38:42.795237 WORK_FSP = 0x0
3980 13:38:42.795288 WL = 0x2
3981 13:38:42.795340 RL = 0x2
3982 13:38:42.795392 BL = 0x2
3983 13:38:42.795446 RPST = 0x0
3984 13:38:42.795504 RD_PRE = 0x0
3985 13:38:42.795559 WR_PRE = 0x1
3986 13:38:42.795632 WR_PST = 0x0
3987 13:38:42.795686 DBI_WR = 0x0
3988 13:38:42.797687 DBI_RD = 0x0
3989 13:38:42.797753 OTF = 0x1
3990 13:38:42.801606 ===================================
3991 13:38:42.804784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3992 13:38:42.810849 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3993 13:38:42.814246 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3994 13:38:42.817589 ===================================
3995 13:38:42.820899 LPDDR4 DRAM CONFIGURATION
3996 13:38:42.824087 ===================================
3997 13:38:42.824190 EX_ROW_EN[0] = 0x10
3998 13:38:42.827511 EX_ROW_EN[1] = 0x0
3999 13:38:42.827583 LP4Y_EN = 0x0
4000 13:38:42.830660 WORK_FSP = 0x0
4001 13:38:42.830735 WL = 0x2
4002 13:38:42.834032 RL = 0x2
4003 13:38:42.834118 BL = 0x2
4004 13:38:43.131700 RPST = 0x0
4005 13:38:43.131851 RD_PRE = 0x0
4006 13:38:43.131915 WR_PRE = 0x1
4007 13:38:43.131997 WR_PST = 0x0
4008 13:38:43.132088 DBI_WR = 0x0
4009 13:38:43.132184 DBI_RD = 0x0
4010 13:38:43.132313 OTF = 0x1
4011 13:38:43.132429 ===================================
4012 13:38:43.132549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4013 13:38:43.132635 nWR fixed to 30
4014 13:38:43.132717 [ModeRegInit_LP4] CH0 RK0
4015 13:38:43.132804 [ModeRegInit_LP4] CH0 RK1
4016 13:38:43.132919 [ModeRegInit_LP4] CH1 RK0
4017 13:38:43.133018 [ModeRegInit_LP4] CH1 RK1
4018 13:38:43.133103 match AC timing 17
4019 13:38:43.133185 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4020 13:38:43.133267 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4021 13:38:43.133348 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4022 13:38:43.133479 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4023 13:38:43.133540 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4024 13:38:43.133592 ==
4025 13:38:43.133645 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 13:38:43.133697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 13:38:43.133749 ==
4028 13:38:43.133800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4029 13:38:43.133852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4030 13:38:43.133920 [CA 0] Center 36 (6~66) winsize 61
4031 13:38:43.133997 [CA 1] Center 36 (6~66) winsize 61
4032 13:38:43.134052 [CA 2] Center 34 (4~65) winsize 62
4033 13:38:43.134105 [CA 3] Center 34 (4~65) winsize 62
4034 13:38:43.134221 [CA 4] Center 33 (3~64) winsize 62
4035 13:38:43.134275 [CA 5] Center 33 (3~64) winsize 62
4036 13:38:43.134326
4037 13:38:43.134377 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4038 13:38:43.134451
4039 13:38:43.134543 [CATrainingPosCal] consider 1 rank data
4040 13:38:43.134623 u2DelayCellTimex100 = 270/100 ps
4041 13:38:43.134676 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4042 13:38:43.134730 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4043 13:38:43.134803 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4044 13:38:43.134859 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4045 13:38:43.134910 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4046 13:38:43.134984 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4047 13:38:43.135065
4048 13:38:43.135123 CA PerBit enable=1, Macro0, CA PI delay=33
4049 13:38:43.135174
4050 13:38:43.135225 [CBTSetCACLKResult] CA Dly = 33
4051 13:38:43.135276 CS Dly: 5 (0~36)
4052 13:38:43.135327 ==
4053 13:38:43.135378 Dram Type= 6, Freq= 0, CH_0, rank 1
4054 13:38:43.135429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 13:38:43.135502 ==
4056 13:38:43.135573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4057 13:38:43.135643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4058 13:38:43.135696 [CA 0] Center 36 (6~66) winsize 61
4059 13:38:43.135748 [CA 1] Center 36 (6~66) winsize 61
4060 13:38:43.135798 [CA 2] Center 34 (4~64) winsize 61
4061 13:38:43.135849 [CA 3] Center 34 (4~64) winsize 61
4062 13:38:43.135900 [CA 4] Center 33 (2~64) winsize 63
4063 13:38:43.135950 [CA 5] Center 33 (2~64) winsize 63
4064 13:38:43.136023
4065 13:38:43.136129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4066 13:38:43.136215
4067 13:38:43.136295 [CATrainingPosCal] consider 2 rank data
4068 13:38:43.136375 u2DelayCellTimex100 = 270/100 ps
4069 13:38:43.136455 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4070 13:38:43.136558 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4071 13:38:43.136665 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4072 13:38:43.136757 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4073 13:38:43.136876 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4074 13:38:43.136980 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4075 13:38:43.137069
4076 13:38:43.137177 CA PerBit enable=1, Macro0, CA PI delay=33
4077 13:38:43.137236
4078 13:38:43.137287 [CBTSetCACLKResult] CA Dly = 33
4079 13:38:43.137339 CS Dly: 5 (0~37)
4080 13:38:43.137390
4081 13:38:43.137440 ----->DramcWriteLeveling(PI) begin...
4082 13:38:43.137492 ==
4083 13:38:43.137543 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 13:38:43.137631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 13:38:43.137684 ==
4086 13:38:43.137756 Write leveling (Byte 0): 34 => 34
4087 13:38:43.137809 Write leveling (Byte 1): 29 => 29
4088 13:38:43.137860 DramcWriteLeveling(PI) end<-----
4089 13:38:43.137912
4090 13:38:43.137962 ==
4091 13:38:43.138013 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 13:38:43.138064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 13:38:43.138181 ==
4094 13:38:43.138272 [Gating] SW mode calibration
4095 13:38:43.138326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4096 13:38:43.138379 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4097 13:38:43.138431 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4098 13:38:43.138483 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4099 13:38:43.138535 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4100 13:38:43.138586 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4101 13:38:43.138659 0 9 16 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
4102 13:38:43.138736 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4103 13:38:43.138799 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4104 13:38:43.138851 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 13:38:43.138916 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 13:38:43.141371 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 13:38:43.144842 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 13:38:43.151211 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4109 13:38:43.154581 0 10 16 | B1->B0 | 3131 4141 | 0 0 | (0 0) (1 1)
4110 13:38:43.157988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4111 13:38:43.164601 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 13:38:43.168114 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 13:38:43.171456 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 13:38:43.177917 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 13:38:43.181380 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 13:38:43.184488 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 13:38:43.191223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 13:38:43.194394 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 13:38:43.197653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 13:38:43.204238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 13:38:43.207388 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 13:38:43.210759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 13:38:43.217539 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 13:38:43.220964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 13:38:43.224198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 13:38:43.230925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 13:38:43.234231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 13:38:43.237587 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 13:38:43.244058 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 13:38:43.246897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 13:38:43.250648 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 13:38:43.257356 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4133 13:38:43.259956 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4134 13:38:43.263402 Total UI for P1: 0, mck2ui 16
4135 13:38:43.266613 best dqsien dly found for B0: ( 0, 13, 12)
4136 13:38:43.269896 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4137 13:38:43.273355 Total UI for P1: 0, mck2ui 16
4138 13:38:43.276627 best dqsien dly found for B1: ( 0, 13, 14)
4139 13:38:43.279965 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4140 13:38:43.286485 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4141 13:38:43.286593
4142 13:38:43.289805 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4143 13:38:43.293428 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4144 13:38:43.296694 [Gating] SW calibration Done
4145 13:38:43.296783 ==
4146 13:38:43.299823 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 13:38:43.303262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 13:38:43.303379 ==
4149 13:38:43.306325 RX Vref Scan: 0
4150 13:38:43.306419
4151 13:38:43.306515 RX Vref 0 -> 0, step: 1
4152 13:38:43.306604
4153 13:38:43.309548 RX Delay -230 -> 252, step: 16
4154 13:38:43.312944 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4155 13:38:43.319975 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4156 13:38:43.323237 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4157 13:38:43.325950 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4158 13:38:43.329392 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4159 13:38:43.336050 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4160 13:38:43.339330 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4161 13:38:43.342636 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4162 13:38:43.345787 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4163 13:38:43.349244 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4164 13:38:43.355984 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4165 13:38:43.359391 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4166 13:38:43.362660 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4167 13:38:43.366096 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4168 13:38:43.372639 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4169 13:38:43.375881 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4170 13:38:43.375962 ==
4171 13:38:43.379316 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 13:38:43.381959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 13:38:43.382037 ==
4174 13:38:43.385338 DQS Delay:
4175 13:38:43.385417 DQS0 = 0, DQS1 = 0
4176 13:38:43.388854 DQM Delay:
4177 13:38:43.388936 DQM0 = 42, DQM1 = 29
4178 13:38:43.388997 DQ Delay:
4179 13:38:43.392085 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4180 13:38:43.395221 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4181 13:38:43.398657 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4182 13:38:43.401897 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4183 13:38:43.401981
4184 13:38:43.402078
4185 13:38:43.405242 ==
4186 13:38:43.405324 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 13:38:43.411554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 13:38:43.411636 ==
4189 13:38:43.411700
4190 13:38:43.411758
4191 13:38:43.415241 TX Vref Scan disable
4192 13:38:43.415360 == TX Byte 0 ==
4193 13:38:43.421589 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4194 13:38:43.425002 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4195 13:38:43.425091 == TX Byte 1 ==
4196 13:38:43.431671 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4197 13:38:43.435186 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4198 13:38:43.435261 ==
4199 13:38:43.438697 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 13:38:43.441697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 13:38:43.441781 ==
4202 13:38:43.441846
4203 13:38:43.441905
4204 13:38:43.444773 TX Vref Scan disable
4205 13:38:43.448012 == TX Byte 0 ==
4206 13:38:43.451775 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4207 13:38:43.454882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4208 13:38:43.457963 == TX Byte 1 ==
4209 13:38:43.461533 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4210 13:38:43.464905 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4211 13:38:43.467673
4212 13:38:43.467752 [DATLAT]
4213 13:38:43.467840 Freq=600, CH0 RK0
4214 13:38:43.467907
4215 13:38:43.471560 DATLAT Default: 0x9
4216 13:38:43.471651 0, 0xFFFF, sum = 0
4217 13:38:43.474769 1, 0xFFFF, sum = 0
4218 13:38:43.474853 2, 0xFFFF, sum = 0
4219 13:38:43.478112 3, 0xFFFF, sum = 0
4220 13:38:43.478208 4, 0xFFFF, sum = 0
4221 13:38:43.481343 5, 0xFFFF, sum = 0
4222 13:38:43.484968 6, 0xFFFF, sum = 0
4223 13:38:43.485047 7, 0xFFFF, sum = 0
4224 13:38:43.485111 8, 0x0, sum = 1
4225 13:38:43.488140 9, 0x0, sum = 2
4226 13:38:43.488212 10, 0x0, sum = 3
4227 13:38:43.491609 11, 0x0, sum = 4
4228 13:38:43.491684 best_step = 9
4229 13:38:43.491759
4230 13:38:43.491819 ==
4231 13:38:43.494799 Dram Type= 6, Freq= 0, CH_0, rank 0
4232 13:38:43.501261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 13:38:43.501341 ==
4234 13:38:43.501403 RX Vref Scan: 1
4235 13:38:43.501479
4236 13:38:43.503962 RX Vref 0 -> 0, step: 1
4237 13:38:43.504044
4238 13:38:43.507238 RX Delay -195 -> 252, step: 8
4239 13:38:43.507323
4240 13:38:43.510701 Set Vref, RX VrefLevel [Byte0]: 57
4241 13:38:43.514547 [Byte1]: 50
4242 13:38:43.514619
4243 13:38:43.517216 Final RX Vref Byte 0 = 57 to rank0
4244 13:38:43.520565 Final RX Vref Byte 1 = 50 to rank0
4245 13:38:43.524421 Final RX Vref Byte 0 = 57 to rank1
4246 13:38:43.527547 Final RX Vref Byte 1 = 50 to rank1==
4247 13:38:43.530341 Dram Type= 6, Freq= 0, CH_0, rank 0
4248 13:38:43.533658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 13:38:43.533759 ==
4250 13:38:43.537200 DQS Delay:
4251 13:38:43.537291 DQS0 = 0, DQS1 = 0
4252 13:38:43.540483 DQM Delay:
4253 13:38:43.540565 DQM0 = 43, DQM1 = 32
4254 13:38:43.540667 DQ Delay:
4255 13:38:43.543989 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4256 13:38:43.547318 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4257 13:38:43.550613 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4258 13:38:43.554038 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4259 13:38:43.554139
4260 13:38:43.554218
4261 13:38:43.564115 [DQSOSCAuto] RK0, (LSB)MR18= 0x643b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4262 13:38:43.567189 CH0 RK0: MR19=808, MR18=643B
4263 13:38:43.573659 CH0_RK0: MR19=0x808, MR18=0x643B, DQSOSC=391, MR23=63, INC=171, DEC=114
4264 13:38:43.573778
4265 13:38:43.576845 ----->DramcWriteLeveling(PI) begin...
4266 13:38:43.576950 ==
4267 13:38:43.580147 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 13:38:43.583823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 13:38:43.583941 ==
4270 13:38:43.586737 Write leveling (Byte 0): 33 => 33
4271 13:38:43.589972 Write leveling (Byte 1): 32 => 32
4272 13:38:43.593798 DramcWriteLeveling(PI) end<-----
4273 13:38:43.593905
4274 13:38:43.594004 ==
4275 13:38:43.596550 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 13:38:43.600134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 13:38:43.600213 ==
4278 13:38:43.603090 [Gating] SW mode calibration
4279 13:38:43.609843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4280 13:38:43.616815 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4281 13:38:43.619878 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4282 13:38:43.623228 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4283 13:38:43.629658 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4284 13:38:43.632842 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
4285 13:38:43.636168 0 9 16 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
4286 13:38:43.642902 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 13:38:43.646194 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4288 13:38:43.649741 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 13:38:43.656229 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 13:38:43.659715 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 13:38:43.662424 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 13:38:43.669240 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4293 13:38:43.672721 0 10 16 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (0 0)
4294 13:38:43.676034 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 13:38:43.682637 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4296 13:38:43.685521 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 13:38:43.689016 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 13:38:43.695821 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 13:38:43.699137 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 13:38:43.702178 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 13:38:43.708651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4302 13:38:43.711969 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 13:38:43.715319 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 13:38:43.722119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 13:38:43.725224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 13:38:43.728862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 13:38:43.735255 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 13:38:43.738372 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 13:38:43.741784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 13:38:43.748725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 13:38:43.752064 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 13:38:43.754837 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 13:38:43.761561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 13:38:43.765030 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 13:38:43.768325 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 13:38:43.774942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 13:38:43.778480 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4318 13:38:43.781980 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 13:38:43.784589 Total UI for P1: 0, mck2ui 16
4320 13:38:43.787983 best dqsien dly found for B0: ( 0, 13, 16)
4321 13:38:43.791448 Total UI for P1: 0, mck2ui 16
4322 13:38:43.794503 best dqsien dly found for B1: ( 0, 13, 16)
4323 13:38:43.798224 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4324 13:38:43.804506 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4325 13:38:43.804622
4326 13:38:43.808041 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4327 13:38:43.811046 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4328 13:38:43.814310 [Gating] SW calibration Done
4329 13:38:43.814391 ==
4330 13:38:43.817919 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 13:38:43.821014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 13:38:43.821096 ==
4333 13:38:43.821184 RX Vref Scan: 0
4334 13:38:43.824570
4335 13:38:43.824687 RX Vref 0 -> 0, step: 1
4336 13:38:43.824757
4337 13:38:43.827868 RX Delay -230 -> 252, step: 16
4338 13:38:43.831143 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4339 13:38:43.837726 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4340 13:38:43.841177 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4341 13:38:43.844435 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4342 13:38:43.847727 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4343 13:38:43.854022 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4344 13:38:43.857404 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4345 13:38:43.860565 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4346 13:38:43.864108 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4347 13:38:43.867539 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4348 13:38:43.874121 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4349 13:38:43.877475 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4350 13:38:43.880831 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4351 13:38:43.883775 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4352 13:38:43.890437 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4353 13:38:43.893693 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4354 13:38:43.893778 ==
4355 13:38:43.897055 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 13:38:43.900266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 13:38:43.900351 ==
4358 13:38:43.903512 DQS Delay:
4359 13:38:43.903594 DQS0 = 0, DQS1 = 0
4360 13:38:43.906922 DQM Delay:
4361 13:38:43.907005 DQM0 = 44, DQM1 = 39
4362 13:38:43.907069 DQ Delay:
4363 13:38:43.910330 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4364 13:38:43.913461 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4365 13:38:43.916793 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4366 13:38:43.919742 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4367 13:38:43.919824
4368 13:38:43.919888
4369 13:38:43.923340 ==
4370 13:38:43.926946 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 13:38:43.929836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 13:38:43.929919 ==
4373 13:38:43.929984
4374 13:38:43.930043
4375 13:38:43.933006 TX Vref Scan disable
4376 13:38:43.933102 == TX Byte 0 ==
4377 13:38:43.936432 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4378 13:38:43.943262 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4379 13:38:43.943346 == TX Byte 1 ==
4380 13:38:43.949739 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4381 13:38:43.953234 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4382 13:38:43.953318 ==
4383 13:38:43.956563 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 13:38:43.960022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 13:38:43.960106 ==
4386 13:38:43.960172
4387 13:38:43.960231
4388 13:38:43.962648 TX Vref Scan disable
4389 13:38:43.966188 == TX Byte 0 ==
4390 13:38:43.969458 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4391 13:38:43.972980 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4392 13:38:43.976132 == TX Byte 1 ==
4393 13:38:43.979527 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4394 13:38:43.982861 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4395 13:38:43.982944
4396 13:38:43.986169 [DATLAT]
4397 13:38:43.986252 Freq=600, CH0 RK1
4398 13:38:43.986317
4399 13:38:43.989051 DATLAT Default: 0x9
4400 13:38:43.989133 0, 0xFFFF, sum = 0
4401 13:38:43.992453 1, 0xFFFF, sum = 0
4402 13:38:43.992537 2, 0xFFFF, sum = 0
4403 13:38:43.995793 3, 0xFFFF, sum = 0
4404 13:38:43.995878 4, 0xFFFF, sum = 0
4405 13:38:43.999148 5, 0xFFFF, sum = 0
4406 13:38:43.999231 6, 0xFFFF, sum = 0
4407 13:38:44.002430 7, 0xFFFF, sum = 0
4408 13:38:44.002513 8, 0x0, sum = 1
4409 13:38:44.005635 9, 0x0, sum = 2
4410 13:38:44.005725 10, 0x0, sum = 3
4411 13:38:44.008851 11, 0x0, sum = 4
4412 13:38:44.008933 best_step = 9
4413 13:38:44.008997
4414 13:38:44.009055 ==
4415 13:38:44.012306 Dram Type= 6, Freq= 0, CH_0, rank 1
4416 13:38:44.019155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 13:38:44.019239 ==
4418 13:38:44.019303 RX Vref Scan: 0
4419 13:38:44.019362
4420 13:38:44.021958 RX Vref 0 -> 0, step: 1
4421 13:38:44.022041
4422 13:38:44.025846 RX Delay -179 -> 252, step: 8
4423 13:38:44.029160 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4424 13:38:44.035837 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4425 13:38:44.038989 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4426 13:38:44.042354 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4427 13:38:44.045763 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4428 13:38:44.051957 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4429 13:38:44.055056 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4430 13:38:44.058410 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4431 13:38:44.061625 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4432 13:38:44.065051 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4433 13:38:44.071514 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4434 13:38:44.075142 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4435 13:38:44.078008 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4436 13:38:44.081339 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4437 13:38:44.088087 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4438 13:38:44.091311 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4439 13:38:44.091396 ==
4440 13:38:44.094684 Dram Type= 6, Freq= 0, CH_0, rank 1
4441 13:38:44.098078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 13:38:44.098166 ==
4443 13:38:44.101318 DQS Delay:
4444 13:38:44.101400 DQS0 = 0, DQS1 = 0
4445 13:38:44.104693 DQM Delay:
4446 13:38:44.104775 DQM0 = 42, DQM1 = 36
4447 13:38:44.104840 DQ Delay:
4448 13:38:44.108146 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4449 13:38:44.111351 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =48
4450 13:38:44.114812 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4451 13:38:44.117655 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4452 13:38:44.117738
4453 13:38:44.117803
4454 13:38:44.127748 [DQSOSCAuto] RK1, (LSB)MR18= 0x6215, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4455 13:38:44.130924 CH0 RK1: MR19=808, MR18=6215
4456 13:38:44.137786 CH0_RK1: MR19=0x808, MR18=0x6215, DQSOSC=391, MR23=63, INC=171, DEC=114
4457 13:38:44.141053 [RxdqsGatingPostProcess] freq 600
4458 13:38:44.144321 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4459 13:38:44.147411 Pre-setting of DQS Precalculation
4460 13:38:44.151211 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4461 13:38:44.154066 ==
4462 13:38:44.157278 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 13:38:44.160652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 13:38:44.160732 ==
4465 13:38:44.167232 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4466 13:38:44.171073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4467 13:38:44.174486 [CA 0] Center 35 (5~66) winsize 62
4468 13:38:44.177904 [CA 1] Center 35 (5~66) winsize 62
4469 13:38:44.181329 [CA 2] Center 34 (3~65) winsize 63
4470 13:38:44.184386 [CA 3] Center 33 (3~64) winsize 62
4471 13:38:44.187974 [CA 4] Center 34 (4~65) winsize 62
4472 13:38:44.191240 [CA 5] Center 33 (3~64) winsize 62
4473 13:38:44.191340
4474 13:38:44.194845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4475 13:38:44.194929
4476 13:38:44.197473 [CATrainingPosCal] consider 1 rank data
4477 13:38:44.200994 u2DelayCellTimex100 = 270/100 ps
4478 13:38:44.204393 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4479 13:38:44.211188 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4480 13:38:44.214524 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4481 13:38:44.217695 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 13:38:44.220999 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4483 13:38:44.223885 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 13:38:44.223970
4485 13:38:44.227192 CA PerBit enable=1, Macro0, CA PI delay=33
4486 13:38:44.227279
4487 13:38:44.230557 [CBTSetCACLKResult] CA Dly = 33
4488 13:38:44.233802 CS Dly: 5 (0~36)
4489 13:38:44.233919 ==
4490 13:38:44.237283 Dram Type= 6, Freq= 0, CH_1, rank 1
4491 13:38:44.240582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 13:38:44.240662 ==
4493 13:38:44.246771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4494 13:38:44.253748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4495 13:38:44.257075 [CA 0] Center 35 (5~66) winsize 62
4496 13:38:44.260166 [CA 1] Center 36 (6~66) winsize 61
4497 13:38:44.263533 [CA 2] Center 34 (4~65) winsize 62
4498 13:38:44.266830 [CA 3] Center 34 (4~65) winsize 62
4499 13:38:44.269598 [CA 4] Center 34 (4~65) winsize 62
4500 13:38:44.273541 [CA 5] Center 34 (4~65) winsize 62
4501 13:38:44.273625
4502 13:38:44.276294 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4503 13:38:44.276378
4504 13:38:44.280169 [CATrainingPosCal] consider 2 rank data
4505 13:38:44.283241 u2DelayCellTimex100 = 270/100 ps
4506 13:38:44.286352 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4507 13:38:44.289390 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4508 13:38:44.292990 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4509 13:38:44.295853 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4510 13:38:44.299354 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4511 13:38:44.302660 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4512 13:38:44.302756
4513 13:38:44.309241 CA PerBit enable=1, Macro0, CA PI delay=34
4514 13:38:44.309333
4515 13:38:44.312748 [CBTSetCACLKResult] CA Dly = 34
4516 13:38:44.312832 CS Dly: 4 (0~35)
4517 13:38:44.312897
4518 13:38:44.316174 ----->DramcWriteLeveling(PI) begin...
4519 13:38:44.316259 ==
4520 13:38:44.318833 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 13:38:44.322082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 13:38:44.325505 ==
4523 13:38:44.325615 Write leveling (Byte 0): 30 => 30
4524 13:38:44.329048 Write leveling (Byte 1): 31 => 31
4525 13:38:44.332316 DramcWriteLeveling(PI) end<-----
4526 13:38:44.332419
4527 13:38:44.332485 ==
4528 13:38:44.335682 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 13:38:44.342437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 13:38:44.342527 ==
4531 13:38:44.345309 [Gating] SW mode calibration
4532 13:38:44.352379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4533 13:38:44.355054 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4534 13:38:44.361689 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4535 13:38:44.365318 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4536 13:38:44.368843 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4537 13:38:44.374802 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
4538 13:38:44.378946 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
4539 13:38:44.381439 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4540 13:38:44.388471 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4541 13:38:44.391785 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4542 13:38:44.395087 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4543 13:38:44.401336 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 13:38:44.404552 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4545 13:38:44.407586 0 10 12 | B1->B0 | 3434 3838 | 0 0 | (0 0) (0 0)
4546 13:38:44.414454 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4547 13:38:44.418142 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 13:38:44.421065 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4549 13:38:44.427581 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 13:38:44.430901 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 13:38:44.434339 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 13:38:44.441180 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 13:38:44.443989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4554 13:38:44.447939 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 13:38:44.453907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 13:38:44.457350 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 13:38:44.460750 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 13:38:44.467511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 13:38:44.470650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 13:38:44.473725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 13:38:44.480266 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 13:38:44.483602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 13:38:44.486806 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 13:38:44.493691 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 13:38:44.497020 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 13:38:44.500435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 13:38:44.506734 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 13:38:44.510458 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 13:38:44.513359 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 13:38:44.520199 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4571 13:38:44.520291 Total UI for P1: 0, mck2ui 16
4572 13:38:44.526714 best dqsien dly found for B0: ( 0, 13, 14)
4573 13:38:44.526805 Total UI for P1: 0, mck2ui 16
4574 13:38:44.529961 best dqsien dly found for B1: ( 0, 13, 14)
4575 13:38:44.536735 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4576 13:38:44.539728 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4577 13:38:44.539841
4578 13:38:44.543077 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4579 13:38:44.546351 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4580 13:38:44.549583 [Gating] SW calibration Done
4581 13:38:44.549665 ==
4582 13:38:44.553072 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 13:38:44.556598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:38:44.556677 ==
4585 13:38:44.560048 RX Vref Scan: 0
4586 13:38:44.560125
4587 13:38:44.560187 RX Vref 0 -> 0, step: 1
4588 13:38:44.560247
4589 13:38:44.562900 RX Delay -230 -> 252, step: 16
4590 13:38:44.569661 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4591 13:38:44.573084 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4592 13:38:44.576364 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4593 13:38:44.579835 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4594 13:38:44.582792 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4595 13:38:44.589889 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4596 13:38:44.593166 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4597 13:38:44.596022 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4598 13:38:44.599529 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4599 13:38:44.606321 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4600 13:38:44.609056 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4601 13:38:44.612340 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4602 13:38:44.615733 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4603 13:38:44.622280 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4604 13:38:44.625600 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4605 13:38:44.629020 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4606 13:38:44.629110 ==
4607 13:38:44.632974 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 13:38:44.636219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 13:38:44.636303 ==
4610 13:38:44.638866 DQS Delay:
4611 13:38:44.638949 DQS0 = 0, DQS1 = 0
4612 13:38:44.642696 DQM Delay:
4613 13:38:44.642779 DQM0 = 46, DQM1 = 38
4614 13:38:44.642843 DQ Delay:
4615 13:38:44.645828 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4616 13:38:44.648774 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4617 13:38:44.652174 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4618 13:38:44.655629 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4619 13:38:44.655714
4620 13:38:44.658596
4621 13:38:44.658680 ==
4622 13:38:44.662077 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 13:38:44.665486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 13:38:44.665569 ==
4625 13:38:44.665634
4626 13:38:44.665694
4627 13:38:44.668873 TX Vref Scan disable
4628 13:38:44.668954 == TX Byte 0 ==
4629 13:38:44.675140 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4630 13:38:44.678378 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4631 13:38:44.678483 == TX Byte 1 ==
4632 13:38:44.685196 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4633 13:38:44.688457 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4634 13:38:44.688540 ==
4635 13:38:44.691568 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 13:38:44.695250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 13:38:44.695335 ==
4638 13:38:44.695400
4639 13:38:44.695460
4640 13:38:44.698486 TX Vref Scan disable
4641 13:38:44.701966 == TX Byte 0 ==
4642 13:38:44.704735 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4643 13:38:44.711882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4644 13:38:44.711969 == TX Byte 1 ==
4645 13:38:44.714607 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4646 13:38:44.721381 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4647 13:38:44.721468
4648 13:38:44.721534 [DATLAT]
4649 13:38:44.721595 Freq=600, CH1 RK0
4650 13:38:44.721655
4651 13:38:44.724897 DATLAT Default: 0x9
4652 13:38:44.725007 0, 0xFFFF, sum = 0
4653 13:38:44.728124 1, 0xFFFF, sum = 0
4654 13:38:44.731732 2, 0xFFFF, sum = 0
4655 13:38:44.731816 3, 0xFFFF, sum = 0
4656 13:38:44.734445 4, 0xFFFF, sum = 0
4657 13:38:44.734531 5, 0xFFFF, sum = 0
4658 13:38:44.737757 6, 0xFFFF, sum = 0
4659 13:38:44.737842 7, 0xFFFF, sum = 0
4660 13:38:44.741251 8, 0x0, sum = 1
4661 13:38:44.741338 9, 0x0, sum = 2
4662 13:38:44.741405 10, 0x0, sum = 3
4663 13:38:44.744696 11, 0x0, sum = 4
4664 13:38:44.744781 best_step = 9
4665 13:38:44.744845
4666 13:38:44.748131 ==
4667 13:38:44.748214 Dram Type= 6, Freq= 0, CH_1, rank 0
4668 13:38:44.754379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 13:38:44.754463 ==
4670 13:38:44.754527 RX Vref Scan: 1
4671 13:38:44.754588
4672 13:38:44.757739 RX Vref 0 -> 0, step: 1
4673 13:38:44.757822
4674 13:38:44.760915 RX Delay -179 -> 252, step: 8
4675 13:38:44.761000
4676 13:38:44.764214 Set Vref, RX VrefLevel [Byte0]: 45
4677 13:38:44.767625 [Byte1]: 53
4678 13:38:44.767734
4679 13:38:44.770542 Final RX Vref Byte 0 = 45 to rank0
4680 13:38:44.774204 Final RX Vref Byte 1 = 53 to rank0
4681 13:38:44.777391 Final RX Vref Byte 0 = 45 to rank1
4682 13:38:44.780920 Final RX Vref Byte 1 = 53 to rank1==
4683 13:38:44.784328 Dram Type= 6, Freq= 0, CH_1, rank 0
4684 13:38:44.787864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 13:38:44.790455 ==
4686 13:38:44.790539 DQS Delay:
4687 13:38:44.790604 DQS0 = 0, DQS1 = 0
4688 13:38:44.794055 DQM Delay:
4689 13:38:44.794178 DQM0 = 47, DQM1 = 37
4690 13:38:44.797312 DQ Delay:
4691 13:38:44.797397 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4692 13:38:44.800737 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4693 13:38:44.803901 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4694 13:38:44.807249 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =44
4695 13:38:44.807363
4696 13:38:44.810719
4697 13:38:44.817283 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4698 13:38:44.820816 CH1 RK0: MR19=808, MR18=4C31
4699 13:38:44.827029 CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112
4700 13:38:44.827122
4701 13:38:44.830677 ----->DramcWriteLeveling(PI) begin...
4702 13:38:44.830774 ==
4703 13:38:44.833313 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 13:38:44.836779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 13:38:44.836864 ==
4706 13:38:44.840154 Write leveling (Byte 0): 29 => 29
4707 13:38:44.843528 Write leveling (Byte 1): 30 => 30
4708 13:38:44.846870 DramcWriteLeveling(PI) end<-----
4709 13:38:44.846949
4710 13:38:44.847013 ==
4711 13:38:44.850422 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 13:38:44.853681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 13:38:44.853765 ==
4714 13:38:44.857043 [Gating] SW mode calibration
4715 13:38:44.863892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4716 13:38:44.869946 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4717 13:38:44.873312 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4718 13:38:44.876563 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4719 13:38:44.883204 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4720 13:38:44.886867 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
4721 13:38:44.889846 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4722 13:38:44.896398 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4723 13:38:44.899763 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4724 13:38:44.903247 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4725 13:38:44.909904 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 13:38:44.913164 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 13:38:44.916319 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 13:38:44.922700 0 10 12 | B1->B0 | 3939 2e2d | 0 1 | (0 0) (0 0)
4729 13:38:44.926535 0 10 16 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
4730 13:38:44.929906 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 13:38:44.935927 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4732 13:38:44.939175 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 13:38:44.942626 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 13:38:44.949334 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 13:38:44.952570 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 13:38:44.956008 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4737 13:38:44.962985 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 13:38:44.965586 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 13:38:44.968982 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 13:38:44.975582 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 13:38:44.979080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 13:38:44.982434 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 13:38:44.989117 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 13:38:44.991789 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 13:38:44.995677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 13:38:45.002044 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 13:38:45.005651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 13:38:45.009195 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 13:38:45.015591 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 13:38:45.018319 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 13:38:45.022176 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4752 13:38:45.028332 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4753 13:38:45.032047 Total UI for P1: 0, mck2ui 16
4754 13:38:45.035232 best dqsien dly found for B1: ( 0, 13, 8)
4755 13:38:45.038095 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4756 13:38:45.041893 Total UI for P1: 0, mck2ui 16
4757 13:38:45.045172 best dqsien dly found for B0: ( 0, 13, 12)
4758 13:38:45.047931 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4759 13:38:45.051217 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4760 13:38:45.051305
4761 13:38:45.054460 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4762 13:38:45.061840 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4763 13:38:45.061925 [Gating] SW calibration Done
4764 13:38:45.061990 ==
4765 13:38:45.064579 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 13:38:45.071292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 13:38:45.071380 ==
4768 13:38:45.071473 RX Vref Scan: 0
4769 13:38:45.071538
4770 13:38:45.074741 RX Vref 0 -> 0, step: 1
4771 13:38:45.074821
4772 13:38:45.077514 RX Delay -230 -> 252, step: 16
4773 13:38:45.081043 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4774 13:38:45.084480 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4775 13:38:45.091255 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4776 13:38:45.093966 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4777 13:38:45.097282 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4778 13:38:45.100785 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4779 13:38:45.104364 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4780 13:38:45.110765 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4781 13:38:45.114410 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4782 13:38:45.117301 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4783 13:38:45.121036 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4784 13:38:45.127542 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4785 13:38:45.130871 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4786 13:38:45.134140 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4787 13:38:45.137112 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4788 13:38:45.144123 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4789 13:38:45.144214 ==
4790 13:38:45.147308 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 13:38:45.150057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 13:38:45.150169 ==
4793 13:38:45.150237 DQS Delay:
4794 13:38:45.153409 DQS0 = 0, DQS1 = 0
4795 13:38:45.153488 DQM Delay:
4796 13:38:45.157278 DQM0 = 43, DQM1 = 35
4797 13:38:45.157362 DQ Delay:
4798 13:38:45.160614 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4799 13:38:45.163535 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4800 13:38:45.166897 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =17
4801 13:38:45.170388 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4802 13:38:45.170476
4803 13:38:45.170541
4804 13:38:45.170612 ==
4805 13:38:45.173720 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 13:38:45.177229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 13:38:45.177329 ==
4808 13:38:45.180040
4809 13:38:45.180137
4810 13:38:45.180203 TX Vref Scan disable
4811 13:38:45.183470 == TX Byte 0 ==
4812 13:38:45.186828 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4813 13:38:45.190402 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4814 13:38:45.193571 == TX Byte 1 ==
4815 13:38:45.196868 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4816 13:38:45.200402 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4817 13:38:45.203752 ==
4818 13:38:45.203867 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 13:38:45.209933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 13:38:45.210013 ==
4821 13:38:45.210077
4822 13:38:45.210137
4823 13:38:45.213303 TX Vref Scan disable
4824 13:38:45.213385 == TX Byte 0 ==
4825 13:38:45.220081 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4826 13:38:45.223456 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4827 13:38:45.223528 == TX Byte 1 ==
4828 13:38:45.229731 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4829 13:38:45.233230 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4830 13:38:45.233307
4831 13:38:45.233370 [DATLAT]
4832 13:38:45.236185 Freq=600, CH1 RK1
4833 13:38:45.236253
4834 13:38:45.236312 DATLAT Default: 0x9
4835 13:38:45.239467 0, 0xFFFF, sum = 0
4836 13:38:45.239585 1, 0xFFFF, sum = 0
4837 13:38:45.242668 2, 0xFFFF, sum = 0
4838 13:38:45.245987 3, 0xFFFF, sum = 0
4839 13:38:45.246113 4, 0xFFFF, sum = 0
4840 13:38:45.249803 5, 0xFFFF, sum = 0
4841 13:38:45.249885 6, 0xFFFF, sum = 0
4842 13:38:45.252739 7, 0xFFFF, sum = 0
4843 13:38:45.252818 8, 0x0, sum = 1
4844 13:38:45.256427 9, 0x0, sum = 2
4845 13:38:45.256513 10, 0x0, sum = 3
4846 13:38:45.256577 11, 0x0, sum = 4
4847 13:38:45.259806 best_step = 9
4848 13:38:45.259891
4849 13:38:45.259959 ==
4850 13:38:45.262914 Dram Type= 6, Freq= 0, CH_1, rank 1
4851 13:38:45.266456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4852 13:38:45.266534 ==
4853 13:38:45.269208 RX Vref Scan: 0
4854 13:38:45.269307
4855 13:38:45.269398 RX Vref 0 -> 0, step: 1
4856 13:38:45.269491
4857 13:38:45.272669 RX Delay -195 -> 252, step: 8
4858 13:38:45.280278 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4859 13:38:45.283766 iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296
4860 13:38:45.287070 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4861 13:38:45.290474 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4862 13:38:45.296658 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4863 13:38:45.299879 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4864 13:38:45.303395 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4865 13:38:45.306802 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4866 13:38:45.310068 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4867 13:38:45.316373 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4868 13:38:45.319878 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4869 13:38:45.323161 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4870 13:38:45.326065 iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312
4871 13:38:45.333007 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4872 13:38:45.336178 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4873 13:38:45.339779 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4874 13:38:45.339865 ==
4875 13:38:45.343152 Dram Type= 6, Freq= 0, CH_1, rank 1
4876 13:38:45.349384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4877 13:38:45.349473 ==
4878 13:38:45.349555 DQS Delay:
4879 13:38:45.352390 DQS0 = 0, DQS1 = 0
4880 13:38:45.352467 DQM Delay:
4881 13:38:45.352528 DQM0 = 45, DQM1 = 36
4882 13:38:45.355735 DQ Delay:
4883 13:38:45.358953 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4884 13:38:45.362399 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4885 13:38:45.365842 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4886 13:38:45.369308 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4887 13:38:45.369397
4888 13:38:45.369473
4889 13:38:45.375408 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4890 13:38:45.378835 CH1 RK1: MR19=808, MR18=2F24
4891 13:38:45.385718 CH1_RK1: MR19=0x808, MR18=0x2F24, DQSOSC=400, MR23=63, INC=163, DEC=109
4892 13:38:45.389015 [RxdqsGatingPostProcess] freq 600
4893 13:38:45.392697 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4894 13:38:45.395501 Pre-setting of DQS Precalculation
4895 13:38:45.402076 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4896 13:38:45.408886 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4897 13:38:45.415152 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4898 13:38:45.415232
4899 13:38:45.415304
4900 13:38:45.418612 [Calibration Summary] 1200 Mbps
4901 13:38:45.421966 CH 0, Rank 0
4902 13:38:45.422052 SW Impedance : PASS
4903 13:38:45.424819 DUTY Scan : NO K
4904 13:38:45.424897 ZQ Calibration : PASS
4905 13:38:45.428277 Jitter Meter : NO K
4906 13:38:45.431743 CBT Training : PASS
4907 13:38:45.431824 Write leveling : PASS
4908 13:38:45.435327 RX DQS gating : PASS
4909 13:38:45.437956 RX DQ/DQS(RDDQC) : PASS
4910 13:38:45.438068 TX DQ/DQS : PASS
4911 13:38:45.441466 RX DATLAT : PASS
4912 13:38:45.444800 RX DQ/DQS(Engine): PASS
4913 13:38:45.444901 TX OE : NO K
4914 13:38:45.448344 All Pass.
4915 13:38:45.448424
4916 13:38:45.448489 CH 0, Rank 1
4917 13:38:45.451011 SW Impedance : PASS
4918 13:38:45.451086 DUTY Scan : NO K
4919 13:38:45.454307 ZQ Calibration : PASS
4920 13:38:45.457772 Jitter Meter : NO K
4921 13:38:45.457876 CBT Training : PASS
4922 13:38:45.461222 Write leveling : PASS
4923 13:38:45.464710 RX DQS gating : PASS
4924 13:38:45.464815 RX DQ/DQS(RDDQC) : PASS
4925 13:38:45.467827 TX DQ/DQS : PASS
4926 13:38:45.470989 RX DATLAT : PASS
4927 13:38:45.471106 RX DQ/DQS(Engine): PASS
4928 13:38:45.474504 TX OE : NO K
4929 13:38:45.474613 All Pass.
4930 13:38:45.474703
4931 13:38:45.477750 CH 1, Rank 0
4932 13:38:45.477827 SW Impedance : PASS
4933 13:38:45.481332 DUTY Scan : NO K
4934 13:38:45.484456 ZQ Calibration : PASS
4935 13:38:45.484562 Jitter Meter : NO K
4936 13:38:45.487408 CBT Training : PASS
4937 13:38:45.490992 Write leveling : PASS
4938 13:38:45.491068 RX DQS gating : PASS
4939 13:38:45.494193 RX DQ/DQS(RDDQC) : PASS
4940 13:38:45.497631 TX DQ/DQS : PASS
4941 13:38:45.497734 RX DATLAT : PASS
4942 13:38:45.500478 RX DQ/DQS(Engine): PASS
4943 13:38:45.500579 TX OE : NO K
4944 13:38:45.504077 All Pass.
4945 13:38:45.504181
4946 13:38:45.504279 CH 1, Rank 1
4947 13:38:45.507426 SW Impedance : PASS
4948 13:38:45.507526 DUTY Scan : NO K
4949 13:38:45.510707 ZQ Calibration : PASS
4950 13:38:45.514002 Jitter Meter : NO K
4951 13:38:45.514107 CBT Training : PASS
4952 13:38:45.517479 Write leveling : PASS
4953 13:38:45.520254 RX DQS gating : PASS
4954 13:38:45.520358 RX DQ/DQS(RDDQC) : PASS
4955 13:38:45.523765 TX DQ/DQS : PASS
4956 13:38:45.527270 RX DATLAT : PASS
4957 13:38:45.527357 RX DQ/DQS(Engine): PASS
4958 13:38:45.530591 TX OE : NO K
4959 13:38:45.530670 All Pass.
4960 13:38:45.530757
4961 13:38:45.533485 DramC Write-DBI off
4962 13:38:45.536872 PER_BANK_REFRESH: Hybrid Mode
4963 13:38:45.536969 TX_TRACKING: ON
4964 13:38:45.547024 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4965 13:38:45.550360 [FAST_K] Save calibration result to emmc
4966 13:38:45.553778 dramc_set_vcore_voltage set vcore to 662500
4967 13:38:45.556464 Read voltage for 933, 3
4968 13:38:45.556546 Vio18 = 0
4969 13:38:45.556610 Vcore = 662500
4970 13:38:45.559728 Vdram = 0
4971 13:38:45.559839 Vddq = 0
4972 13:38:45.559904 Vmddr = 0
4973 13:38:45.566706 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4974 13:38:45.569822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4975 13:38:45.573199 MEM_TYPE=3, freq_sel=17
4976 13:38:45.576863 sv_algorithm_assistance_LP4_1600
4977 13:38:45.579754 ============ PULL DRAM RESETB DOWN ============
4978 13:38:45.586325 ========== PULL DRAM RESETB DOWN end =========
4979 13:38:45.589839 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 13:38:45.593143 ===================================
4981 13:38:45.596217 LPDDR4 DRAM CONFIGURATION
4982 13:38:45.599354 ===================================
4983 13:38:45.599435 EX_ROW_EN[0] = 0x0
4984 13:38:45.602830 EX_ROW_EN[1] = 0x0
4985 13:38:45.602910 LP4Y_EN = 0x0
4986 13:38:45.606388 WORK_FSP = 0x0
4987 13:38:45.606489 WL = 0x3
4988 13:38:45.609577 RL = 0x3
4989 13:38:45.613194 BL = 0x2
4990 13:38:45.613271 RPST = 0x0
4991 13:38:45.615979 RD_PRE = 0x0
4992 13:38:45.616052 WR_PRE = 0x1
4993 13:38:45.619386 WR_PST = 0x0
4994 13:38:45.619465 DBI_WR = 0x0
4995 13:38:45.622657 DBI_RD = 0x0
4996 13:38:45.622734 OTF = 0x1
4997 13:38:45.625800 ===================================
4998 13:38:45.629088 ===================================
4999 13:38:45.632276 ANA top config
5000 13:38:45.635620 ===================================
5001 13:38:45.635727 DLL_ASYNC_EN = 0
5002 13:38:45.639053 ALL_SLAVE_EN = 1
5003 13:38:45.642461 NEW_RANK_MODE = 1
5004 13:38:45.645658 DLL_IDLE_MODE = 1
5005 13:38:45.649102 LP45_APHY_COMB_EN = 1
5006 13:38:45.649207 TX_ODT_DIS = 1
5007 13:38:45.651836 NEW_8X_MODE = 1
5008 13:38:45.655196 ===================================
5009 13:38:45.658741 ===================================
5010 13:38:45.662067 data_rate = 1866
5011 13:38:45.664988 CKR = 1
5012 13:38:45.668201 DQ_P2S_RATIO = 8
5013 13:38:45.671468 ===================================
5014 13:38:45.675557 CA_P2S_RATIO = 8
5015 13:38:45.675637 DQ_CA_OPEN = 0
5016 13:38:45.678227 DQ_SEMI_OPEN = 0
5017 13:38:45.681549 CA_SEMI_OPEN = 0
5018 13:38:45.684926 CA_FULL_RATE = 0
5019 13:38:45.688272 DQ_CKDIV4_EN = 1
5020 13:38:45.691487 CA_CKDIV4_EN = 1
5021 13:38:45.691562 CA_PREDIV_EN = 0
5022 13:38:45.695176 PH8_DLY = 0
5023 13:38:45.697998 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5024 13:38:45.701510 DQ_AAMCK_DIV = 4
5025 13:38:45.704750 CA_AAMCK_DIV = 4
5026 13:38:45.707996 CA_ADMCK_DIV = 4
5027 13:38:45.708104 DQ_TRACK_CA_EN = 0
5028 13:38:45.711202 CA_PICK = 933
5029 13:38:45.714937 CA_MCKIO = 933
5030 13:38:45.717727 MCKIO_SEMI = 0
5031 13:38:45.721089 PLL_FREQ = 3732
5032 13:38:45.724352 DQ_UI_PI_RATIO = 32
5033 13:38:45.727801 CA_UI_PI_RATIO = 0
5034 13:38:45.731049 ===================================
5035 13:38:45.734348 ===================================
5036 13:38:45.734452 memory_type:LPDDR4
5037 13:38:45.737600 GP_NUM : 10
5038 13:38:45.740818 SRAM_EN : 1
5039 13:38:45.740918 MD32_EN : 0
5040 13:38:45.744182 ===================================
5041 13:38:45.747544 [ANA_INIT] >>>>>>>>>>>>>>
5042 13:38:45.750997 <<<<<< [CONFIGURE PHASE]: ANA_TX
5043 13:38:45.754269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5044 13:38:45.757672 ===================================
5045 13:38:45.760999 data_rate = 1866,PCW = 0X8f00
5046 13:38:45.763710 ===================================
5047 13:38:45.767148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5048 13:38:45.770425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5049 13:38:45.777038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5050 13:38:45.783792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5051 13:38:45.787289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5052 13:38:45.790662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5053 13:38:45.790764 [ANA_INIT] flow start
5054 13:38:45.793482 [ANA_INIT] PLL >>>>>>>>
5055 13:38:45.796775 [ANA_INIT] PLL <<<<<<<<
5056 13:38:45.796898 [ANA_INIT] MIDPI >>>>>>>>
5057 13:38:45.800577 [ANA_INIT] MIDPI <<<<<<<<
5058 13:38:45.803736 [ANA_INIT] DLL >>>>>>>>
5059 13:38:45.803815 [ANA_INIT] flow end
5060 13:38:45.809947 ============ LP4 DIFF to SE enter ============
5061 13:38:45.813085 ============ LP4 DIFF to SE exit ============
5062 13:38:45.816881 [ANA_INIT] <<<<<<<<<<<<<
5063 13:38:45.820130 [Flow] Enable top DCM control >>>>>
5064 13:38:45.823420 [Flow] Enable top DCM control <<<<<
5065 13:38:45.823500 Enable DLL master slave shuffle
5066 13:38:45.829959 ==============================================================
5067 13:38:45.833316 Gating Mode config
5068 13:38:45.836581 ==============================================================
5069 13:38:45.840071 Config description:
5070 13:38:45.850093 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5071 13:38:45.856799 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5072 13:38:45.859654 SELPH_MODE 0: By rank 1: By Phase
5073 13:38:45.866456 ==============================================================
5074 13:38:45.869754 GAT_TRACK_EN = 1
5075 13:38:45.872754 RX_GATING_MODE = 2
5076 13:38:45.876085 RX_GATING_TRACK_MODE = 2
5077 13:38:45.879397 SELPH_MODE = 1
5078 13:38:45.879508 PICG_EARLY_EN = 1
5079 13:38:45.882911 VALID_LAT_VALUE = 1
5080 13:38:45.889259 ==============================================================
5081 13:38:45.892640 Enter into Gating configuration >>>>
5082 13:38:45.895977 Exit from Gating configuration <<<<
5083 13:38:45.899478 Enter into DVFS_PRE_config >>>>>
5084 13:38:45.908959 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5085 13:38:45.913068 Exit from DVFS_PRE_config <<<<<
5086 13:38:45.915936 Enter into PICG configuration >>>>
5087 13:38:45.919115 Exit from PICG configuration <<<<
5088 13:38:45.922250 [RX_INPUT] configuration >>>>>
5089 13:38:45.925520 [RX_INPUT] configuration <<<<<
5090 13:38:45.932389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5091 13:38:45.935636 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5092 13:38:45.942323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5093 13:38:45.948437 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5094 13:38:45.955075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5095 13:38:45.961755 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5096 13:38:45.965113 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5097 13:38:45.968778 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5098 13:38:45.971436 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5099 13:38:45.978448 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5100 13:38:45.981905 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5101 13:38:45.984714 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 13:38:45.988118 ===================================
5103 13:38:45.991701 LPDDR4 DRAM CONFIGURATION
5104 13:38:45.995043 ===================================
5105 13:38:45.995161 EX_ROW_EN[0] = 0x0
5106 13:38:45.998371 EX_ROW_EN[1] = 0x0
5107 13:38:46.001782 LP4Y_EN = 0x0
5108 13:38:46.001899 WORK_FSP = 0x0
5109 13:38:46.005234 WL = 0x3
5110 13:38:46.005339 RL = 0x3
5111 13:38:46.007889 BL = 0x2
5112 13:38:46.008003 RPST = 0x0
5113 13:38:46.011142 RD_PRE = 0x0
5114 13:38:46.011255 WR_PRE = 0x1
5115 13:38:46.014656 WR_PST = 0x0
5116 13:38:46.014753 DBI_WR = 0x0
5117 13:38:46.018006 DBI_RD = 0x0
5118 13:38:46.018120 OTF = 0x1
5119 13:38:46.021638 ===================================
5120 13:38:46.027526 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5121 13:38:46.031092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5122 13:38:46.034152 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5123 13:38:46.037513 ===================================
5124 13:38:46.041132 LPDDR4 DRAM CONFIGURATION
5125 13:38:46.044285 ===================================
5126 13:38:46.047699 EX_ROW_EN[0] = 0x10
5127 13:38:46.047825 EX_ROW_EN[1] = 0x0
5128 13:38:46.051119 LP4Y_EN = 0x0
5129 13:38:46.051246 WORK_FSP = 0x0
5130 13:38:46.054093 WL = 0x3
5131 13:38:46.054227 RL = 0x3
5132 13:38:46.057441 BL = 0x2
5133 13:38:46.057531 RPST = 0x0
5134 13:38:46.061013 RD_PRE = 0x0
5135 13:38:46.061124 WR_PRE = 0x1
5136 13:38:46.064012 WR_PST = 0x0
5137 13:38:46.064131 DBI_WR = 0x0
5138 13:38:46.067515 DBI_RD = 0x0
5139 13:38:46.067642 OTF = 0x1
5140 13:38:46.070953 ===================================
5141 13:38:46.077123 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5142 13:38:46.082018 nWR fixed to 30
5143 13:38:46.085386 [ModeRegInit_LP4] CH0 RK0
5144 13:38:46.085513 [ModeRegInit_LP4] CH0 RK1
5145 13:38:46.088952 [ModeRegInit_LP4] CH1 RK0
5146 13:38:46.091592 [ModeRegInit_LP4] CH1 RK1
5147 13:38:46.091722 match AC timing 9
5148 13:38:46.098339 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5149 13:38:46.101773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5150 13:38:46.104883 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5151 13:38:46.111970 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5152 13:38:46.114660 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5153 13:38:46.114824 ==
5154 13:38:46.118090 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 13:38:46.121231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 13:38:46.121367 ==
5157 13:38:46.128320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5158 13:38:46.134469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5159 13:38:46.137712 [CA 0] Center 37 (7~68) winsize 62
5160 13:38:46.141058 [CA 1] Center 37 (7~68) winsize 62
5161 13:38:46.144426 [CA 2] Center 34 (4~65) winsize 62
5162 13:38:46.147902 [CA 3] Center 35 (5~65) winsize 61
5163 13:38:46.151329 [CA 4] Center 33 (3~64) winsize 62
5164 13:38:46.154802 [CA 5] Center 33 (4~63) winsize 60
5165 13:38:46.154975
5166 13:38:46.157437 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5167 13:38:46.157555
5168 13:38:46.161293 [CATrainingPosCal] consider 1 rank data
5169 13:38:46.164757 u2DelayCellTimex100 = 270/100 ps
5170 13:38:46.167981 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5171 13:38:46.170738 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5172 13:38:46.173827 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5173 13:38:46.180916 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5174 13:38:46.184020 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5175 13:38:46.187153 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5176 13:38:46.187263
5177 13:38:46.190404 CA PerBit enable=1, Macro0, CA PI delay=33
5178 13:38:46.190524
5179 13:38:46.193836 [CBTSetCACLKResult] CA Dly = 33
5180 13:38:46.193957 CS Dly: 7 (0~38)
5181 13:38:46.194051 ==
5182 13:38:46.197118 Dram Type= 6, Freq= 0, CH_0, rank 1
5183 13:38:46.204178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 13:38:46.204278 ==
5185 13:38:46.206797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5186 13:38:46.213711 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5187 13:38:46.217397 [CA 0] Center 37 (7~68) winsize 62
5188 13:38:46.220741 [CA 1] Center 37 (7~68) winsize 62
5189 13:38:46.223980 [CA 2] Center 34 (4~65) winsize 62
5190 13:38:46.226697 [CA 3] Center 34 (4~65) winsize 62
5191 13:38:46.230194 [CA 4] Center 33 (3~64) winsize 62
5192 13:38:46.233748 [CA 5] Center 33 (3~63) winsize 61
5193 13:38:46.233864
5194 13:38:46.237043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5195 13:38:46.237166
5196 13:38:46.239650 [CATrainingPosCal] consider 2 rank data
5197 13:38:46.243239 u2DelayCellTimex100 = 270/100 ps
5198 13:38:46.246422 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5199 13:38:46.253354 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5200 13:38:46.256208 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5201 13:38:46.259742 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5202 13:38:46.262835 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5203 13:38:46.266352 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5204 13:38:46.266455
5205 13:38:46.269802 CA PerBit enable=1, Macro0, CA PI delay=33
5206 13:38:46.269904
5207 13:38:46.272431 [CBTSetCACLKResult] CA Dly = 33
5208 13:38:46.276241 CS Dly: 7 (0~39)
5209 13:38:46.276324
5210 13:38:46.279622 ----->DramcWriteLeveling(PI) begin...
5211 13:38:46.279706 ==
5212 13:38:46.282441 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 13:38:46.285843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 13:38:46.285961 ==
5215 13:38:46.289086 Write leveling (Byte 0): 32 => 32
5216 13:38:46.292490 Write leveling (Byte 1): 30 => 30
5217 13:38:46.295655 DramcWriteLeveling(PI) end<-----
5218 13:38:46.295741
5219 13:38:46.295831 ==
5220 13:38:46.298808 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 13:38:46.302242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 13:38:46.302328 ==
5223 13:38:46.305405 [Gating] SW mode calibration
5224 13:38:46.312203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5225 13:38:46.318999 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5226 13:38:46.321812 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5227 13:38:46.328764 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5228 13:38:46.332133 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5229 13:38:46.334918 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5230 13:38:46.342017 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5231 13:38:46.344725 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5232 13:38:46.348265 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 13:38:46.355107 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5234 13:38:46.358408 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5235 13:38:46.361728 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5236 13:38:46.368162 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5237 13:38:46.371483 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5238 13:38:46.374904 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5239 13:38:46.381652 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5240 13:38:46.384825 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 13:38:46.387538 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5242 13:38:46.394752 1 0 0 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (0 0)
5243 13:38:46.397553 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5244 13:38:46.400760 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5245 13:38:46.407547 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5246 13:38:46.410833 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5247 13:38:46.414410 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5248 13:38:46.420502 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 13:38:46.423963 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5250 13:38:46.427395 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5251 13:38:46.433871 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 13:38:46.437154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 13:38:46.440444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 13:38:46.447269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 13:38:46.450773 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5256 13:38:46.454134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 13:38:46.460227 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 13:38:46.463674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 13:38:46.466977 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 13:38:46.473893 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 13:38:46.477091 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 13:38:46.480091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 13:38:46.486962 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 13:38:46.490184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 13:38:46.493687 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5266 13:38:46.500154 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5267 13:38:46.500239 Total UI for P1: 0, mck2ui 16
5268 13:38:46.507015 best dqsien dly found for B0: ( 1, 2, 28)
5269 13:38:46.510113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5270 13:38:46.513396 Total UI for P1: 0, mck2ui 16
5271 13:38:46.516564 best dqsien dly found for B1: ( 1, 2, 30)
5272 13:38:46.520340 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5273 13:38:46.523412 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5274 13:38:46.523496
5275 13:38:46.526454 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5276 13:38:46.529904 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5277 13:38:46.533017 [Gating] SW calibration Done
5278 13:38:46.533124 ==
5279 13:38:46.536222 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 13:38:46.539562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 13:38:46.542759 ==
5282 13:38:46.542842 RX Vref Scan: 0
5283 13:38:46.542907
5284 13:38:46.546220 RX Vref 0 -> 0, step: 1
5285 13:38:46.546304
5286 13:38:46.549670 RX Delay -80 -> 252, step: 8
5287 13:38:46.553056 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5288 13:38:46.556397 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5289 13:38:46.559914 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5290 13:38:46.562640 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5291 13:38:46.566010 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5292 13:38:46.572694 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5293 13:38:46.576072 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5294 13:38:46.579546 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5295 13:38:46.582524 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5296 13:38:46.585964 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5297 13:38:46.592572 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5298 13:38:46.595802 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5299 13:38:46.599100 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5300 13:38:46.602266 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5301 13:38:46.605596 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5302 13:38:46.609093 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5303 13:38:46.612414 ==
5304 13:38:46.615957 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 13:38:46.619127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 13:38:46.619201 ==
5307 13:38:46.619263 DQS Delay:
5308 13:38:46.621987 DQS0 = 0, DQS1 = 0
5309 13:38:46.622060 DQM Delay:
5310 13:38:46.625313 DQM0 = 97, DQM1 = 87
5311 13:38:46.625408 DQ Delay:
5312 13:38:46.628590 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5313 13:38:46.631884 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5314 13:38:46.635627 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5315 13:38:46.638741 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5316 13:38:46.638821
5317 13:38:46.638894
5318 13:38:46.638955 ==
5319 13:38:46.641936 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 13:38:46.645075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 13:38:46.645151 ==
5322 13:38:46.648887
5323 13:38:46.648971
5324 13:38:46.649032 TX Vref Scan disable
5325 13:38:46.651549 == TX Byte 0 ==
5326 13:38:46.654827 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5327 13:38:46.658287 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5328 13:38:46.661605 == TX Byte 1 ==
5329 13:38:46.664983 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5330 13:38:46.668355 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5331 13:38:46.668432 ==
5332 13:38:46.671556 Dram Type= 6, Freq= 0, CH_0, rank 0
5333 13:38:46.678405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 13:38:46.678482 ==
5335 13:38:46.678549
5336 13:38:46.678608
5337 13:38:46.681125 TX Vref Scan disable
5338 13:38:46.681198 == TX Byte 0 ==
5339 13:38:46.688309 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5340 13:38:46.691825 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5341 13:38:46.691905 == TX Byte 1 ==
5342 13:38:46.698079 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5343 13:38:46.701247 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5344 13:38:46.701322
5345 13:38:46.701383 [DATLAT]
5346 13:38:46.704951 Freq=933, CH0 RK0
5347 13:38:46.705022
5348 13:38:46.705104 DATLAT Default: 0xd
5349 13:38:46.707976 0, 0xFFFF, sum = 0
5350 13:38:46.708048 1, 0xFFFF, sum = 0
5351 13:38:46.710892 2, 0xFFFF, sum = 0
5352 13:38:46.710989 3, 0xFFFF, sum = 0
5353 13:38:46.714648 4, 0xFFFF, sum = 0
5354 13:38:46.714726 5, 0xFFFF, sum = 0
5355 13:38:46.717979 6, 0xFFFF, sum = 0
5356 13:38:46.720786 7, 0xFFFF, sum = 0
5357 13:38:46.720858 8, 0xFFFF, sum = 0
5358 13:38:46.724232 9, 0xFFFF, sum = 0
5359 13:38:46.724304 10, 0x0, sum = 1
5360 13:38:46.724365 11, 0x0, sum = 2
5361 13:38:46.727492 12, 0x0, sum = 3
5362 13:38:46.727591 13, 0x0, sum = 4
5363 13:38:46.730874 best_step = 11
5364 13:38:46.730953
5365 13:38:46.731015 ==
5366 13:38:46.734084 Dram Type= 6, Freq= 0, CH_0, rank 0
5367 13:38:46.737529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 13:38:46.737602 ==
5369 13:38:46.740895 RX Vref Scan: 1
5370 13:38:46.740991
5371 13:38:46.741077 RX Vref 0 -> 0, step: 1
5372 13:38:46.744343
5373 13:38:46.744426 RX Delay -61 -> 252, step: 4
5374 13:38:46.744495
5375 13:38:46.747540 Set Vref, RX VrefLevel [Byte0]: 57
5376 13:38:46.750519 [Byte1]: 50
5377 13:38:46.754968
5378 13:38:46.755054 Final RX Vref Byte 0 = 57 to rank0
5379 13:38:46.758526 Final RX Vref Byte 1 = 50 to rank0
5380 13:38:46.761937 Final RX Vref Byte 0 = 57 to rank1
5381 13:38:46.764764 Final RX Vref Byte 1 = 50 to rank1==
5382 13:38:46.768063 Dram Type= 6, Freq= 0, CH_0, rank 0
5383 13:38:46.774832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 13:38:46.774911 ==
5385 13:38:46.774974 DQS Delay:
5386 13:38:46.778098 DQS0 = 0, DQS1 = 0
5387 13:38:46.778219 DQM Delay:
5388 13:38:46.778283 DQM0 = 96, DQM1 = 85
5389 13:38:46.781450 DQ Delay:
5390 13:38:46.784713 DQ0 =96, DQ1 =98, DQ2 =90, DQ3 =92
5391 13:38:46.788286 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =104
5392 13:38:46.791529 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5393 13:38:46.794799 DQ12 =92, DQ13 =88, DQ14 =98, DQ15 =94
5394 13:38:46.794898
5395 13:38:46.794961
5396 13:38:46.800813 [DQSOSCAuto] RK0, (LSB)MR18= 0x290f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5397 13:38:46.804089 CH0 RK0: MR19=505, MR18=290F
5398 13:38:46.811328 CH0_RK0: MR19=0x505, MR18=0x290F, DQSOSC=408, MR23=63, INC=65, DEC=43
5399 13:38:46.811431
5400 13:38:46.814415 ----->DramcWriteLeveling(PI) begin...
5401 13:38:46.814492 ==
5402 13:38:46.817606 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 13:38:46.820647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 13:38:46.820729 ==
5405 13:38:46.823936 Write leveling (Byte 0): 36 => 36
5406 13:38:46.827615 Write leveling (Byte 1): 31 => 31
5407 13:38:46.830476 DramcWriteLeveling(PI) end<-----
5408 13:38:46.830556
5409 13:38:46.830626 ==
5410 13:38:46.834402 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 13:38:46.840488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 13:38:46.840570 ==
5413 13:38:46.840634 [Gating] SW mode calibration
5414 13:38:46.850473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5415 13:38:46.853743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5416 13:38:46.857233 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (0 0)
5417 13:38:46.864154 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5418 13:38:46.867435 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 13:38:46.870651 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 13:38:46.877456 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5421 13:38:46.880191 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 13:38:46.883323 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5423 13:38:46.889856 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5424 13:38:46.893212 0 15 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
5425 13:38:46.896484 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 13:38:46.903054 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 13:38:46.907090 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 13:38:46.909790 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 13:38:46.916473 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 13:38:46.919770 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 13:38:46.923096 0 15 28 | B1->B0 | 2727 3636 | 1 1 | (0 0) (0 0)
5432 13:38:46.929715 1 0 0 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5433 13:38:46.933288 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 13:38:46.936281 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 13:38:46.942815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 13:38:46.945969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 13:38:46.949302 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 13:38:46.956191 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5439 13:38:46.959349 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 13:38:46.962785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 13:38:46.968826 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 13:38:46.972449 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 13:38:46.978928 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 13:38:46.982246 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 13:38:46.985646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 13:38:46.989039 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 13:38:46.995807 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 13:38:46.998984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 13:38:47.002354 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 13:38:47.009036 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 13:38:47.012413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 13:38:47.015101 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 13:38:47.021706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 13:38:47.024865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 13:38:47.028297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 13:38:47.034966 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5457 13:38:47.038412 Total UI for P1: 0, mck2ui 16
5458 13:38:47.041704 best dqsien dly found for B0: ( 1, 2, 30)
5459 13:38:47.044953 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5460 13:38:47.048193 Total UI for P1: 0, mck2ui 16
5461 13:38:47.051748 best dqsien dly found for B1: ( 1, 3, 0)
5462 13:38:47.054744 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5463 13:38:47.058277 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5464 13:38:47.058393
5465 13:38:47.061644 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5466 13:38:47.068416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5467 13:38:47.068498 [Gating] SW calibration Done
5468 13:38:47.068561 ==
5469 13:38:47.071139 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 13:38:47.078003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 13:38:47.078109 ==
5472 13:38:47.078230 RX Vref Scan: 0
5473 13:38:47.078291
5474 13:38:47.081080 RX Vref 0 -> 0, step: 1
5475 13:38:47.081160
5476 13:38:47.084223 RX Delay -80 -> 252, step: 8
5477 13:38:47.087530 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5478 13:38:47.090940 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5479 13:38:47.094389 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5480 13:38:47.097890 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5481 13:38:47.104552 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5482 13:38:47.107760 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5483 13:38:47.111195 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5484 13:38:47.114386 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5485 13:38:47.117949 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5486 13:38:47.121223 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5487 13:38:47.127272 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5488 13:38:47.130548 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5489 13:38:47.133912 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5490 13:38:47.137372 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5491 13:38:47.140820 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5492 13:38:47.147602 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5493 13:38:47.147686 ==
5494 13:38:47.150395 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 13:38:47.153831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 13:38:47.153907 ==
5497 13:38:47.153979 DQS Delay:
5498 13:38:47.157039 DQS0 = 0, DQS1 = 0
5499 13:38:47.157122 DQM Delay:
5500 13:38:47.160174 DQM0 = 97, DQM1 = 88
5501 13:38:47.160247 DQ Delay:
5502 13:38:47.163479 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5503 13:38:47.167081 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5504 13:38:47.169984 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5505 13:38:47.173553 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5506 13:38:47.173638
5507 13:38:47.173701
5508 13:38:47.173761 ==
5509 13:38:47.176787 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 13:38:47.183412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 13:38:47.183505 ==
5512 13:38:47.183571
5513 13:38:47.183632
5514 13:38:47.183705 TX Vref Scan disable
5515 13:38:47.186741 == TX Byte 0 ==
5516 13:38:47.189916 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5517 13:38:47.196734 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5518 13:38:47.196819 == TX Byte 1 ==
5519 13:38:47.199896 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5520 13:38:47.206653 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5521 13:38:47.206757 ==
5522 13:38:47.209993 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 13:38:47.213359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 13:38:47.213436 ==
5525 13:38:47.213503
5526 13:38:47.213562
5527 13:38:47.216088 TX Vref Scan disable
5528 13:38:47.219470 == TX Byte 0 ==
5529 13:38:47.222695 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5530 13:38:47.226170 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5531 13:38:47.229548 == TX Byte 1 ==
5532 13:38:47.232957 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5533 13:38:47.236193 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5534 13:38:47.236303
5535 13:38:47.236396 [DATLAT]
5536 13:38:47.239148 Freq=933, CH0 RK1
5537 13:38:47.239224
5538 13:38:47.242670 DATLAT Default: 0xb
5539 13:38:47.242751 0, 0xFFFF, sum = 0
5540 13:38:47.246023 1, 0xFFFF, sum = 0
5541 13:38:47.246123 2, 0xFFFF, sum = 0
5542 13:38:47.249449 3, 0xFFFF, sum = 0
5543 13:38:47.249519 4, 0xFFFF, sum = 0
5544 13:38:47.252729 5, 0xFFFF, sum = 0
5545 13:38:47.252846 6, 0xFFFF, sum = 0
5546 13:38:47.256225 7, 0xFFFF, sum = 0
5547 13:38:47.256296 8, 0xFFFF, sum = 0
5548 13:38:47.259340 9, 0xFFFF, sum = 0
5549 13:38:47.259415 10, 0x0, sum = 1
5550 13:38:47.262835 11, 0x0, sum = 2
5551 13:38:47.262915 12, 0x0, sum = 3
5552 13:38:47.265728 13, 0x0, sum = 4
5553 13:38:47.265820 best_step = 11
5554 13:38:47.265887
5555 13:38:47.265948 ==
5556 13:38:47.268993 Dram Type= 6, Freq= 0, CH_0, rank 1
5557 13:38:47.272227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 13:38:47.275595 ==
5559 13:38:47.275689 RX Vref Scan: 0
5560 13:38:47.275755
5561 13:38:47.278697 RX Vref 0 -> 0, step: 1
5562 13:38:47.278787
5563 13:38:47.282458 RX Delay -61 -> 252, step: 4
5564 13:38:47.285207 iDelay=203, Bit 0, Center 90 (-1 ~ 182) 184
5565 13:38:47.288534 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5566 13:38:47.295368 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5567 13:38:47.298394 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5568 13:38:47.302107 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5569 13:38:47.305045 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5570 13:38:47.308873 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5571 13:38:47.312230 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5572 13:38:47.318242 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5573 13:38:47.321455 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5574 13:38:47.324804 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5575 13:38:47.328263 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5576 13:38:47.335004 iDelay=203, Bit 12, Center 90 (-5 ~ 186) 192
5577 13:38:47.338459 iDelay=203, Bit 13, Center 92 (-5 ~ 190) 196
5578 13:38:47.341742 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5579 13:38:47.344813 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5580 13:38:47.344892 ==
5581 13:38:47.348016 Dram Type= 6, Freq= 0, CH_0, rank 1
5582 13:38:47.351447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 13:38:47.354742 ==
5584 13:38:47.354819 DQS Delay:
5585 13:38:47.354882 DQS0 = 0, DQS1 = 0
5586 13:38:47.358028 DQM Delay:
5587 13:38:47.358122 DQM0 = 95, DQM1 = 86
5588 13:38:47.361506 DQ Delay:
5589 13:38:47.364895 DQ0 =90, DQ1 =96, DQ2 =90, DQ3 =94
5590 13:38:47.367641 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5591 13:38:47.370916 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5592 13:38:47.375136 DQ12 =90, DQ13 =92, DQ14 =100, DQ15 =92
5593 13:38:47.375218
5594 13:38:47.375281
5595 13:38:47.381398 [DQSOSCAuto] RK1, (LSB)MR18= 0x29f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5596 13:38:47.384952 CH0 RK1: MR19=504, MR18=29F9
5597 13:38:47.390908 CH0_RK1: MR19=0x504, MR18=0x29F9, DQSOSC=408, MR23=63, INC=65, DEC=43
5598 13:38:47.394467 [RxdqsGatingPostProcess] freq 933
5599 13:38:47.397487 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5600 13:38:47.400961 best DQS0 dly(2T, 0.5T) = (0, 10)
5601 13:38:47.404072 best DQS1 dly(2T, 0.5T) = (0, 10)
5602 13:38:47.407060 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5603 13:38:47.410564 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5604 13:38:47.414126 best DQS0 dly(2T, 0.5T) = (0, 10)
5605 13:38:47.416986 best DQS1 dly(2T, 0.5T) = (0, 11)
5606 13:38:47.420766 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5607 13:38:47.423973 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5608 13:38:47.427235 Pre-setting of DQS Precalculation
5609 13:38:47.430523 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5610 13:38:47.433822 ==
5611 13:38:47.437091 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 13:38:47.440428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 13:38:47.440529 ==
5614 13:38:47.443991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5615 13:38:47.450547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5616 13:38:47.454462 [CA 0] Center 37 (7~67) winsize 61
5617 13:38:47.457590 [CA 1] Center 37 (7~68) winsize 62
5618 13:38:47.460904 [CA 2] Center 34 (4~65) winsize 62
5619 13:38:47.463612 [CA 3] Center 33 (3~64) winsize 62
5620 13:38:47.466983 [CA 4] Center 34 (5~64) winsize 60
5621 13:38:47.470397 [CA 5] Center 34 (4~64) winsize 61
5622 13:38:47.470473
5623 13:38:47.473838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5624 13:38:47.473913
5625 13:38:47.477079 [CATrainingPosCal] consider 1 rank data
5626 13:38:47.480617 u2DelayCellTimex100 = 270/100 ps
5627 13:38:47.483799 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5628 13:38:47.490569 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5629 13:38:47.493306 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5630 13:38:47.496571 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5631 13:38:47.499915 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5632 13:38:47.503226 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5633 13:38:47.503299
5634 13:38:47.506345 CA PerBit enable=1, Macro0, CA PI delay=33
5635 13:38:47.506423
5636 13:38:47.509775 [CBTSetCACLKResult] CA Dly = 33
5637 13:38:47.513594 CS Dly: 6 (0~37)
5638 13:38:47.513729 ==
5639 13:38:47.516644 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 13:38:47.519906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 13:38:47.519991 ==
5642 13:38:47.526334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5643 13:38:47.529859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5644 13:38:47.534015 [CA 0] Center 37 (7~67) winsize 61
5645 13:38:47.537404 [CA 1] Center 37 (7~68) winsize 62
5646 13:38:47.540232 [CA 2] Center 34 (4~65) winsize 62
5647 13:38:47.543599 [CA 3] Center 34 (3~65) winsize 63
5648 13:38:47.546838 [CA 4] Center 34 (3~65) winsize 63
5649 13:38:47.550371 [CA 5] Center 33 (3~64) winsize 62
5650 13:38:47.550459
5651 13:38:47.553764 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5652 13:38:47.553836
5653 13:38:47.557026 [CATrainingPosCal] consider 2 rank data
5654 13:38:47.560502 u2DelayCellTimex100 = 270/100 ps
5655 13:38:47.563873 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5656 13:38:47.570028 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5657 13:38:47.573395 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5658 13:38:47.576790 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5659 13:38:47.580101 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5660 13:38:47.583389 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5661 13:38:47.583479
5662 13:38:47.586601 CA PerBit enable=1, Macro0, CA PI delay=33
5663 13:38:47.586717
5664 13:38:47.590155 [CBTSetCACLKResult] CA Dly = 33
5665 13:38:47.593403 CS Dly: 7 (0~39)
5666 13:38:47.593478
5667 13:38:47.596839 ----->DramcWriteLeveling(PI) begin...
5668 13:38:47.596918 ==
5669 13:38:47.599566 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 13:38:47.602988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 13:38:47.603068 ==
5672 13:38:47.606252 Write leveling (Byte 0): 27 => 27
5673 13:38:47.609533 Write leveling (Byte 1): 31 => 31
5674 13:38:47.612778 DramcWriteLeveling(PI) end<-----
5675 13:38:47.612876
5676 13:38:47.612940 ==
5677 13:38:47.616071 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 13:38:47.619290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 13:38:47.619364 ==
5680 13:38:47.623068 [Gating] SW mode calibration
5681 13:38:47.629049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5682 13:38:47.635743 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5683 13:38:47.639686 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5684 13:38:47.642677 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5685 13:38:47.649134 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5686 13:38:47.652510 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5687 13:38:47.656084 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5688 13:38:47.662104 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 13:38:47.665613 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5690 13:38:47.672287 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
5691 13:38:47.675723 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5692 13:38:47.679070 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5693 13:38:47.685229 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5694 13:38:47.688643 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5695 13:38:47.691876 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5696 13:38:47.695123 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5697 13:38:47.701814 0 15 24 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
5698 13:38:47.705129 0 15 28 | B1->B0 | 3b3b 3737 | 0 0 | (0 0) (0 0)
5699 13:38:47.708506 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5700 13:38:47.715244 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5701 13:38:47.718457 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 13:38:47.725127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 13:38:47.728412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5704 13:38:47.731526 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5705 13:38:47.737817 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5706 13:38:47.741026 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5707 13:38:47.744504 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 13:38:47.751231 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 13:38:47.754436 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 13:38:47.757596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 13:38:47.764397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 13:38:47.767467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 13:38:47.771008 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 13:38:47.777292 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 13:38:47.780492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 13:38:47.784025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 13:38:47.790689 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 13:38:47.793932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 13:38:47.797504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 13:38:47.804124 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 13:38:47.807439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5722 13:38:47.810135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5723 13:38:47.813623 Total UI for P1: 0, mck2ui 16
5724 13:38:47.816710 best dqsien dly found for B0: ( 1, 2, 24)
5725 13:38:47.820223 Total UI for P1: 0, mck2ui 16
5726 13:38:47.823469 best dqsien dly found for B1: ( 1, 2, 26)
5727 13:38:47.826873 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5728 13:38:47.830154 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5729 13:38:47.830321
5730 13:38:47.836208 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5731 13:38:47.840150 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5732 13:38:47.840230 [Gating] SW calibration Done
5733 13:38:47.843532 ==
5734 13:38:47.846320 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 13:38:47.849493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 13:38:47.849575 ==
5737 13:38:47.849644 RX Vref Scan: 0
5738 13:38:47.849735
5739 13:38:47.853406 RX Vref 0 -> 0, step: 1
5740 13:38:47.853480
5741 13:38:47.856738 RX Delay -80 -> 252, step: 8
5742 13:38:47.860113 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5743 13:38:47.862845 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5744 13:38:47.865977 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5745 13:38:47.872881 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5746 13:38:47.876188 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5747 13:38:47.879505 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5748 13:38:47.882982 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5749 13:38:47.886008 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5750 13:38:47.892656 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5751 13:38:47.895643 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5752 13:38:47.898914 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5753 13:38:47.902689 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5754 13:38:47.905907 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5755 13:38:47.909240 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5756 13:38:47.916033 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5757 13:38:47.919346 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5758 13:38:47.919472 ==
5759 13:38:47.922118 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 13:38:47.925398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 13:38:47.925498 ==
5762 13:38:47.928798 DQS Delay:
5763 13:38:47.928897 DQS0 = 0, DQS1 = 0
5764 13:38:47.928985 DQM Delay:
5765 13:38:47.932120 DQM0 = 101, DQM1 = 90
5766 13:38:47.932218 DQ Delay:
5767 13:38:47.935422 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5768 13:38:47.938518 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5769 13:38:47.941787 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5770 13:38:47.945237 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5771 13:38:47.945313
5772 13:38:47.945379
5773 13:38:47.948826 ==
5774 13:38:47.948931 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 13:38:47.955351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 13:38:47.955474 ==
5777 13:38:47.955563
5778 13:38:47.955709
5779 13:38:47.958658 TX Vref Scan disable
5780 13:38:47.958763 == TX Byte 0 ==
5781 13:38:47.962244 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5782 13:38:47.968183 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5783 13:38:47.968259 == TX Byte 1 ==
5784 13:38:47.971566 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5785 13:38:47.978278 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5786 13:38:47.978360 ==
5787 13:38:47.981769 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 13:38:47.985008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 13:38:47.985116 ==
5790 13:38:47.985209
5791 13:38:47.985296
5792 13:38:47.988463 TX Vref Scan disable
5793 13:38:47.991760 == TX Byte 0 ==
5794 13:38:47.995051 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5795 13:38:47.998411 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5796 13:38:48.001612 == TX Byte 1 ==
5797 13:38:48.004831 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5798 13:38:48.007930 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5799 13:38:48.008007
5800 13:38:48.011583 [DATLAT]
5801 13:38:48.011655 Freq=933, CH1 RK0
5802 13:38:48.011720
5803 13:38:48.015028 DATLAT Default: 0xd
5804 13:38:48.015127 0, 0xFFFF, sum = 0
5805 13:38:48.018359 1, 0xFFFF, sum = 0
5806 13:38:48.018436 2, 0xFFFF, sum = 0
5807 13:38:48.021700 3, 0xFFFF, sum = 0
5808 13:38:48.021773 4, 0xFFFF, sum = 0
5809 13:38:48.024936 5, 0xFFFF, sum = 0
5810 13:38:48.025008 6, 0xFFFF, sum = 0
5811 13:38:48.028216 7, 0xFFFF, sum = 0
5812 13:38:48.028288 8, 0xFFFF, sum = 0
5813 13:38:48.031583 9, 0xFFFF, sum = 0
5814 13:38:48.031694 10, 0x0, sum = 1
5815 13:38:48.034267 11, 0x0, sum = 2
5816 13:38:48.034345 12, 0x0, sum = 3
5817 13:38:48.038201 13, 0x0, sum = 4
5818 13:38:48.038295 best_step = 11
5819 13:38:48.038428
5820 13:38:48.038492 ==
5821 13:38:48.041716 Dram Type= 6, Freq= 0, CH_1, rank 0
5822 13:38:48.048064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 13:38:48.048147 ==
5824 13:38:48.048211 RX Vref Scan: 1
5825 13:38:48.048271
5826 13:38:48.050892 RX Vref 0 -> 0, step: 1
5827 13:38:48.050963
5828 13:38:48.054196 RX Delay -69 -> 252, step: 4
5829 13:38:48.054282
5830 13:38:48.057675 Set Vref, RX VrefLevel [Byte0]: 45
5831 13:38:48.061025 [Byte1]: 53
5832 13:38:48.061202
5833 13:38:48.064292 Final RX Vref Byte 0 = 45 to rank0
5834 13:38:48.067182 Final RX Vref Byte 1 = 53 to rank0
5835 13:38:48.070534 Final RX Vref Byte 0 = 45 to rank1
5836 13:38:48.074409 Final RX Vref Byte 1 = 53 to rank1==
5837 13:38:48.077729 Dram Type= 6, Freq= 0, CH_1, rank 0
5838 13:38:48.081049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 13:38:48.081127 ==
5840 13:38:48.084367 DQS Delay:
5841 13:38:48.084457 DQS0 = 0, DQS1 = 0
5842 13:38:48.084518 DQM Delay:
5843 13:38:48.087523 DQM0 = 101, DQM1 = 95
5844 13:38:48.087595 DQ Delay:
5845 13:38:48.091008 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5846 13:38:48.094266 DQ4 =100, DQ5 =110, DQ6 =110, DQ7 =96
5847 13:38:48.097498 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5848 13:38:48.100804 DQ12 =104, DQ13 =100, DQ14 =106, DQ15 =104
5849 13:38:48.103603
5850 13:38:48.103679
5851 13:38:48.110380 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5852 13:38:48.113609 CH1 RK0: MR19=505, MR18=1E0E
5853 13:38:48.120698 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5854 13:38:48.120799
5855 13:38:48.123679 ----->DramcWriteLeveling(PI) begin...
5856 13:38:48.123770 ==
5857 13:38:48.127519 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 13:38:48.130570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 13:38:48.130643 ==
5860 13:38:48.133819 Write leveling (Byte 0): 24 => 24
5861 13:38:48.136804 Write leveling (Byte 1): 25 => 25
5862 13:38:48.140114 DramcWriteLeveling(PI) end<-----
5863 13:38:48.140190
5864 13:38:48.140267 ==
5865 13:38:48.144129 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 13:38:48.146716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 13:38:48.146792 ==
5868 13:38:48.150117 [Gating] SW mode calibration
5869 13:38:48.156963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5870 13:38:48.163740 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5871 13:38:48.166831 0 14 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 1)
5872 13:38:48.173189 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5873 13:38:48.176427 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5874 13:38:48.179746 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5875 13:38:48.186277 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5876 13:38:48.189919 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5877 13:38:48.193134 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
5878 13:38:48.199895 0 14 28 | B1->B0 | 2828 2f2f | 0 1 | (1 0) (1 0)
5879 13:38:48.203204 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5880 13:38:48.205899 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5881 13:38:48.212402 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5882 13:38:48.215838 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5883 13:38:48.219078 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5884 13:38:48.225752 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5885 13:38:48.229021 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5886 13:38:48.232261 0 15 28 | B1->B0 | 3a3a 2e2e | 0 0 | (1 1) (1 1)
5887 13:38:48.239271 1 0 0 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
5888 13:38:48.242745 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5889 13:38:48.245719 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 13:38:48.252173 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5891 13:38:48.255581 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 13:38:48.259012 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5893 13:38:48.265846 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5894 13:38:48.269078 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5895 13:38:48.272474 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5896 13:38:48.278497 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 13:38:48.281812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 13:38:48.285227 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 13:38:48.292378 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 13:38:48.294985 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 13:38:48.298450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 13:38:48.305001 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 13:38:48.308419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 13:38:48.311805 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 13:38:48.318555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 13:38:48.321938 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 13:38:48.324573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 13:38:48.331358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5909 13:38:48.334549 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5910 13:38:48.337840 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5911 13:38:48.341481 Total UI for P1: 0, mck2ui 16
5912 13:38:48.344727 best dqsien dly found for B1: ( 1, 2, 22)
5913 13:38:48.351487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5914 13:38:48.351583 Total UI for P1: 0, mck2ui 16
5915 13:38:48.358091 best dqsien dly found for B0: ( 1, 2, 28)
5916 13:38:48.360918 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5917 13:38:48.364119 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5918 13:38:48.364233
5919 13:38:48.367891 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5920 13:38:48.370772 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5921 13:38:48.374275 [Gating] SW calibration Done
5922 13:38:48.374380 ==
5923 13:38:48.377790 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 13:38:48.380904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 13:38:48.381019 ==
5926 13:38:48.384397 RX Vref Scan: 0
5927 13:38:48.384473
5928 13:38:48.384534 RX Vref 0 -> 0, step: 1
5929 13:38:48.384635
5930 13:38:48.387568 RX Delay -80 -> 252, step: 8
5931 13:38:48.391074 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5932 13:38:48.397739 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5933 13:38:48.400935 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5934 13:38:48.404288 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5935 13:38:48.407750 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5936 13:38:48.410418 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5937 13:38:48.413788 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5938 13:38:48.420492 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5939 13:38:48.423828 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5940 13:38:48.427239 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5941 13:38:48.430499 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5942 13:38:48.433932 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5943 13:38:48.440438 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5944 13:38:48.443831 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5945 13:38:48.447071 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5946 13:38:48.450476 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5947 13:38:48.450566 ==
5948 13:38:48.453712 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 13:38:48.459662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 13:38:48.459793 ==
5951 13:38:48.459866 DQS Delay:
5952 13:38:48.459945 DQS0 = 0, DQS1 = 0
5953 13:38:48.463489 DQM Delay:
5954 13:38:48.463574 DQM0 = 100, DQM1 = 92
5955 13:38:48.466209 DQ Delay:
5956 13:38:48.469792 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =95
5957 13:38:48.473122 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5958 13:38:48.476244 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5959 13:38:48.479628 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5960 13:38:48.479745
5961 13:38:48.479849
5962 13:38:48.479951 ==
5963 13:38:48.483255 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 13:38:48.486412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 13:38:48.486530 ==
5966 13:38:48.486630
5967 13:38:48.486728
5968 13:38:48.490012 TX Vref Scan disable
5969 13:38:48.493491 == TX Byte 0 ==
5970 13:38:48.496357 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5971 13:38:48.499395 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5972 13:38:48.502969 == TX Byte 1 ==
5973 13:38:48.506129 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5974 13:38:48.509392 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5975 13:38:48.509503 ==
5976 13:38:48.512867 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 13:38:48.516093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 13:38:48.519399 ==
5979 13:38:48.519512
5980 13:38:48.519611
5981 13:38:48.519711 TX Vref Scan disable
5982 13:38:48.522896 == TX Byte 0 ==
5983 13:38:48.526188 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5984 13:38:48.532854 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5985 13:38:48.532987 == TX Byte 1 ==
5986 13:38:48.536095 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5987 13:38:48.543022 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5988 13:38:48.543146
5989 13:38:48.543253 [DATLAT]
5990 13:38:48.543352 Freq=933, CH1 RK1
5991 13:38:48.543456
5992 13:38:48.546450 DATLAT Default: 0xb
5993 13:38:48.546563 0, 0xFFFF, sum = 0
5994 13:38:48.549731 1, 0xFFFF, sum = 0
5995 13:38:48.552984 2, 0xFFFF, sum = 0
5996 13:38:48.553095 3, 0xFFFF, sum = 0
5997 13:38:48.556399 4, 0xFFFF, sum = 0
5998 13:38:48.556500 5, 0xFFFF, sum = 0
5999 13:38:48.559763 6, 0xFFFF, sum = 0
6000 13:38:48.559870 7, 0xFFFF, sum = 0
6001 13:38:48.562908 8, 0xFFFF, sum = 0
6002 13:38:48.563010 9, 0xFFFF, sum = 0
6003 13:38:48.566113 10, 0x0, sum = 1
6004 13:38:48.566215 11, 0x0, sum = 2
6005 13:38:48.568988 12, 0x0, sum = 3
6006 13:38:48.569092 13, 0x0, sum = 4
6007 13:38:48.569184 best_step = 11
6008 13:38:48.572998
6009 13:38:48.573098 ==
6010 13:38:48.575553 Dram Type= 6, Freq= 0, CH_1, rank 1
6011 13:38:48.579051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6012 13:38:48.579139 ==
6013 13:38:48.579226 RX Vref Scan: 0
6014 13:38:48.579307
6015 13:38:48.582294 RX Vref 0 -> 0, step: 1
6016 13:38:48.582404
6017 13:38:48.585547 RX Delay -61 -> 252, step: 4
6018 13:38:48.592308 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
6019 13:38:48.595785 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
6020 13:38:48.599001 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
6021 13:38:48.602475 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
6022 13:38:48.605567 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
6023 13:38:48.608767 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
6024 13:38:48.615323 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
6025 13:38:48.618817 iDelay=203, Bit 7, Center 98 (11 ~ 186) 176
6026 13:38:48.622038 iDelay=203, Bit 8, Center 84 (-5 ~ 174) 180
6027 13:38:48.625456 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
6028 13:38:48.628719 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
6029 13:38:48.635243 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
6030 13:38:48.638180 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
6031 13:38:48.642382 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
6032 13:38:48.645562 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
6033 13:38:48.648985 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
6034 13:38:48.651545 ==
6035 13:38:48.654854 Dram Type= 6, Freq= 0, CH_1, rank 1
6036 13:38:48.658255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6037 13:38:48.658342 ==
6038 13:38:48.658428 DQS Delay:
6039 13:38:48.661592 DQS0 = 0, DQS1 = 0
6040 13:38:48.661705 DQM Delay:
6041 13:38:48.665084 DQM0 = 102, DQM1 = 93
6042 13:38:48.665196 DQ Delay:
6043 13:38:48.668267 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =100
6044 13:38:48.671558 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6045 13:38:48.675077 DQ8 =84, DQ9 =86, DQ10 =90, DQ11 =84
6046 13:38:48.677971 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
6047 13:38:48.678086
6048 13:38:48.678191
6049 13:38:48.688471 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6050 13:38:48.688600 CH1 RK1: MR19=504, MR18=6FF
6051 13:38:48.694688 CH1_RK1: MR19=0x504, MR18=0x6FF, DQSOSC=420, MR23=63, INC=61, DEC=40
6052 13:38:48.698053 [RxdqsGatingPostProcess] freq 933
6053 13:38:48.704731 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6054 13:38:48.708071 best DQS0 dly(2T, 0.5T) = (0, 10)
6055 13:38:48.711369 best DQS1 dly(2T, 0.5T) = (0, 10)
6056 13:38:48.714668 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6057 13:38:48.717951 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6058 13:38:48.721315 best DQS0 dly(2T, 0.5T) = (0, 10)
6059 13:38:48.721428 best DQS1 dly(2T, 0.5T) = (0, 10)
6060 13:38:48.724476 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6061 13:38:48.727471 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6062 13:38:48.731105 Pre-setting of DQS Precalculation
6063 13:38:48.737580 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6064 13:38:48.743894 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6065 13:38:48.751100 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6066 13:38:48.751191
6067 13:38:48.751255
6068 13:38:48.753727 [Calibration Summary] 1866 Mbps
6069 13:38:48.757041 CH 0, Rank 0
6070 13:38:48.757126 SW Impedance : PASS
6071 13:38:48.760409 DUTY Scan : NO K
6072 13:38:48.763894 ZQ Calibration : PASS
6073 13:38:48.763979 Jitter Meter : NO K
6074 13:38:48.767132 CBT Training : PASS
6075 13:38:48.767230 Write leveling : PASS
6076 13:38:48.770548 RX DQS gating : PASS
6077 13:38:48.773964 RX DQ/DQS(RDDQC) : PASS
6078 13:38:48.774073 TX DQ/DQS : PASS
6079 13:38:48.777334 RX DATLAT : PASS
6080 13:38:48.780586 RX DQ/DQS(Engine): PASS
6081 13:38:48.780700 TX OE : NO K
6082 13:38:48.784013 All Pass.
6083 13:38:48.784126
6084 13:38:48.784188 CH 0, Rank 1
6085 13:38:48.787327 SW Impedance : PASS
6086 13:38:48.787408 DUTY Scan : NO K
6087 13:38:48.790661 ZQ Calibration : PASS
6088 13:38:48.793951 Jitter Meter : NO K
6089 13:38:48.794032 CBT Training : PASS
6090 13:38:48.797072 Write leveling : PASS
6091 13:38:48.800416 RX DQS gating : PASS
6092 13:38:48.800531 RX DQ/DQS(RDDQC) : PASS
6093 13:38:48.803794 TX DQ/DQS : PASS
6094 13:38:48.806536 RX DATLAT : PASS
6095 13:38:48.806647 RX DQ/DQS(Engine): PASS
6096 13:38:48.809883 TX OE : NO K
6097 13:38:48.809994 All Pass.
6098 13:38:48.810094
6099 13:38:48.813161 CH 1, Rank 0
6100 13:38:48.813273 SW Impedance : PASS
6101 13:38:48.817054 DUTY Scan : NO K
6102 13:38:48.820131 ZQ Calibration : PASS
6103 13:38:48.820244 Jitter Meter : NO K
6104 13:38:48.823580 CBT Training : PASS
6105 13:38:48.826773 Write leveling : PASS
6106 13:38:48.826884 RX DQS gating : PASS
6107 13:38:48.829601 RX DQ/DQS(RDDQC) : PASS
6108 13:38:48.833439 TX DQ/DQS : PASS
6109 13:38:48.833552 RX DATLAT : PASS
6110 13:38:48.836517 RX DQ/DQS(Engine): PASS
6111 13:38:48.839604 TX OE : NO K
6112 13:38:48.839720 All Pass.
6113 13:38:48.839818
6114 13:38:48.839917 CH 1, Rank 1
6115 13:38:48.842931 SW Impedance : PASS
6116 13:38:48.846445 DUTY Scan : NO K
6117 13:38:48.846565 ZQ Calibration : PASS
6118 13:38:48.849948 Jitter Meter : NO K
6119 13:38:48.850077 CBT Training : PASS
6120 13:38:48.853097 Write leveling : PASS
6121 13:38:48.856002 RX DQS gating : PASS
6122 13:38:48.856120 RX DQ/DQS(RDDQC) : PASS
6123 13:38:48.859454 TX DQ/DQS : PASS
6124 13:38:48.862694 RX DATLAT : PASS
6125 13:38:48.862809 RX DQ/DQS(Engine): PASS
6126 13:38:48.866125 TX OE : NO K
6127 13:38:48.866248 All Pass.
6128 13:38:48.866346
6129 13:38:48.869543 DramC Write-DBI off
6130 13:38:48.873033 PER_BANK_REFRESH: Hybrid Mode
6131 13:38:48.873147 TX_TRACKING: ON
6132 13:38:48.882874 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6133 13:38:48.886387 [FAST_K] Save calibration result to emmc
6134 13:38:48.889529 dramc_set_vcore_voltage set vcore to 650000
6135 13:38:48.892239 Read voltage for 400, 6
6136 13:38:48.892357 Vio18 = 0
6137 13:38:48.895741 Vcore = 650000
6138 13:38:48.895854 Vdram = 0
6139 13:38:48.895953 Vddq = 0
6140 13:38:48.896050 Vmddr = 0
6141 13:38:48.902686 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6142 13:38:48.909297 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6143 13:38:48.909415 MEM_TYPE=3, freq_sel=20
6144 13:38:48.912802 sv_algorithm_assistance_LP4_800
6145 13:38:48.915936 ============ PULL DRAM RESETB DOWN ============
6146 13:38:48.922429 ========== PULL DRAM RESETB DOWN end =========
6147 13:38:48.925446 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 13:38:48.928648 ===================================
6149 13:38:48.931923 LPDDR4 DRAM CONFIGURATION
6150 13:38:48.935511 ===================================
6151 13:38:48.935634 EX_ROW_EN[0] = 0x0
6152 13:38:48.938752 EX_ROW_EN[1] = 0x0
6153 13:38:48.938871 LP4Y_EN = 0x0
6154 13:38:48.941897 WORK_FSP = 0x0
6155 13:38:48.945241 WL = 0x2
6156 13:38:48.945361 RL = 0x2
6157 13:38:48.948016 BL = 0x2
6158 13:38:48.948130 RPST = 0x0
6159 13:38:48.951380 RD_PRE = 0x0
6160 13:38:48.951496 WR_PRE = 0x1
6161 13:38:48.955052 WR_PST = 0x0
6162 13:38:48.955164 DBI_WR = 0x0
6163 13:38:48.958296 DBI_RD = 0x0
6164 13:38:48.958411 OTF = 0x1
6165 13:38:48.961201 ===================================
6166 13:38:48.964727 ===================================
6167 13:38:48.968175 ANA top config
6168 13:38:48.970923 ===================================
6169 13:38:48.971040 DLL_ASYNC_EN = 0
6170 13:38:48.974814 ALL_SLAVE_EN = 1
6171 13:38:48.977431 NEW_RANK_MODE = 1
6172 13:38:48.980871 DLL_IDLE_MODE = 1
6173 13:38:48.984877 LP45_APHY_COMB_EN = 1
6174 13:38:48.984998 TX_ODT_DIS = 1
6175 13:38:48.987425 NEW_8X_MODE = 1
6176 13:38:48.990832 ===================================
6177 13:38:48.994086 ===================================
6178 13:38:48.997498 data_rate = 800
6179 13:38:49.000956 CKR = 1
6180 13:38:49.004362 DQ_P2S_RATIO = 4
6181 13:38:49.007566 ===================================
6182 13:38:49.010986 CA_P2S_RATIO = 4
6183 13:38:49.011110 DQ_CA_OPEN = 0
6184 13:38:49.014415 DQ_SEMI_OPEN = 1
6185 13:38:49.017017 CA_SEMI_OPEN = 1
6186 13:38:49.020610 CA_FULL_RATE = 0
6187 13:38:49.023760 DQ_CKDIV4_EN = 0
6188 13:38:49.027083 CA_CKDIV4_EN = 1
6189 13:38:49.027206 CA_PREDIV_EN = 0
6190 13:38:49.030387 PH8_DLY = 0
6191 13:38:49.034144 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6192 13:38:49.037345 DQ_AAMCK_DIV = 0
6193 13:38:49.040426 CA_AAMCK_DIV = 0
6194 13:38:49.043806 CA_ADMCK_DIV = 4
6195 13:38:49.043920 DQ_TRACK_CA_EN = 0
6196 13:38:49.047117 CA_PICK = 800
6197 13:38:49.050529 CA_MCKIO = 400
6198 13:38:49.053915 MCKIO_SEMI = 400
6199 13:38:49.057324 PLL_FREQ = 3016
6200 13:38:49.060587 DQ_UI_PI_RATIO = 32
6201 13:38:49.064014 CA_UI_PI_RATIO = 32
6202 13:38:49.067100 ===================================
6203 13:38:49.070080 ===================================
6204 13:38:49.070219 memory_type:LPDDR4
6205 13:38:49.073342 GP_NUM : 10
6206 13:38:49.076825 SRAM_EN : 1
6207 13:38:49.076938 MD32_EN : 0
6208 13:38:49.080213 ===================================
6209 13:38:49.083493 [ANA_INIT] >>>>>>>>>>>>>>
6210 13:38:49.086738 <<<<<< [CONFIGURE PHASE]: ANA_TX
6211 13:38:49.090058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6212 13:38:49.092865 ===================================
6213 13:38:49.096226 data_rate = 800,PCW = 0X7400
6214 13:38:49.099709 ===================================
6215 13:38:49.103132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6216 13:38:49.106548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6217 13:38:49.119723 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6218 13:38:49.123012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6219 13:38:49.126347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6220 13:38:49.129597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6221 13:38:49.133023 [ANA_INIT] flow start
6222 13:38:49.136335 [ANA_INIT] PLL >>>>>>>>
6223 13:38:49.136444 [ANA_INIT] PLL <<<<<<<<
6224 13:38:49.139763 [ANA_INIT] MIDPI >>>>>>>>
6225 13:38:49.143310 [ANA_INIT] MIDPI <<<<<<<<
6226 13:38:49.146031 [ANA_INIT] DLL >>>>>>>>
6227 13:38:49.146152 [ANA_INIT] flow end
6228 13:38:49.149341 ============ LP4 DIFF to SE enter ============
6229 13:38:49.156110 ============ LP4 DIFF to SE exit ============
6230 13:38:49.156218 [ANA_INIT] <<<<<<<<<<<<<
6231 13:38:49.159560 [Flow] Enable top DCM control >>>>>
6232 13:38:49.162139 [Flow] Enable top DCM control <<<<<
6233 13:38:49.165545 Enable DLL master slave shuffle
6234 13:38:49.172269 ==============================================================
6235 13:38:49.172423 Gating Mode config
6236 13:38:49.179377 ==============================================================
6237 13:38:49.182546 Config description:
6238 13:38:49.192452 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6239 13:38:49.199113 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6240 13:38:49.202439 SELPH_MODE 0: By rank 1: By Phase
6241 13:38:49.209047 ==============================================================
6242 13:38:49.212447 GAT_TRACK_EN = 0
6243 13:38:49.215694 RX_GATING_MODE = 2
6244 13:38:49.215793 RX_GATING_TRACK_MODE = 2
6245 13:38:49.219033 SELPH_MODE = 1
6246 13:38:49.222363 PICG_EARLY_EN = 1
6247 13:38:49.224970 VALID_LAT_VALUE = 1
6248 13:38:49.231927 ==============================================================
6249 13:38:49.234961 Enter into Gating configuration >>>>
6250 13:38:49.238236 Exit from Gating configuration <<<<
6251 13:38:49.241514 Enter into DVFS_PRE_config >>>>>
6252 13:38:49.251722 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6253 13:38:49.254773 Exit from DVFS_PRE_config <<<<<
6254 13:38:49.258175 Enter into PICG configuration >>>>
6255 13:38:49.261345 Exit from PICG configuration <<<<
6256 13:38:49.264728 [RX_INPUT] configuration >>>>>
6257 13:38:49.268317 [RX_INPUT] configuration <<<<<
6258 13:38:49.271765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6259 13:38:49.277910 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6260 13:38:49.284388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6261 13:38:49.291071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6262 13:38:49.297839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6263 13:38:49.301050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6264 13:38:49.307707 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6265 13:38:49.311043 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6266 13:38:49.314542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6267 13:38:49.317738 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6268 13:38:49.324390 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6269 13:38:49.327776 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6270 13:38:49.331156 ===================================
6271 13:38:49.334411 LPDDR4 DRAM CONFIGURATION
6272 13:38:49.337715 ===================================
6273 13:38:49.337836 EX_ROW_EN[0] = 0x0
6274 13:38:49.341000 EX_ROW_EN[1] = 0x0
6275 13:38:49.341117 LP4Y_EN = 0x0
6276 13:38:49.344175 WORK_FSP = 0x0
6277 13:38:49.344287 WL = 0x2
6278 13:38:49.347518 RL = 0x2
6279 13:38:49.347629 BL = 0x2
6280 13:38:49.350800 RPST = 0x0
6281 13:38:49.354266 RD_PRE = 0x0
6282 13:38:49.354374 WR_PRE = 0x1
6283 13:38:49.356988 WR_PST = 0x0
6284 13:38:49.357094 DBI_WR = 0x0
6285 13:38:49.360663 DBI_RD = 0x0
6286 13:38:49.360779 OTF = 0x1
6287 13:38:49.363698 ===================================
6288 13:38:49.367010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6289 13:38:49.373572 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6290 13:38:49.376968 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6291 13:38:49.380358 ===================================
6292 13:38:49.383869 LPDDR4 DRAM CONFIGURATION
6293 13:38:49.386622 ===================================
6294 13:38:49.386707 EX_ROW_EN[0] = 0x10
6295 13:38:49.389950 EX_ROW_EN[1] = 0x0
6296 13:38:49.390054 LP4Y_EN = 0x0
6297 13:38:49.393190 WORK_FSP = 0x0
6298 13:38:49.393297 WL = 0x2
6299 13:38:49.397082 RL = 0x2
6300 13:38:49.400223 BL = 0x2
6301 13:38:49.400338 RPST = 0x0
6302 13:38:49.403122 RD_PRE = 0x0
6303 13:38:49.403239 WR_PRE = 0x1
6304 13:38:49.406823 WR_PST = 0x0
6305 13:38:49.406942 DBI_WR = 0x0
6306 13:38:49.410034 DBI_RD = 0x0
6307 13:38:49.410153 OTF = 0x1
6308 13:38:49.413642 ===================================
6309 13:38:49.419819 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6310 13:38:49.423775 nWR fixed to 30
6311 13:38:49.426822 [ModeRegInit_LP4] CH0 RK0
6312 13:38:49.426937 [ModeRegInit_LP4] CH0 RK1
6313 13:38:49.430206 [ModeRegInit_LP4] CH1 RK0
6314 13:38:49.433549 [ModeRegInit_LP4] CH1 RK1
6315 13:38:49.433659 match AC timing 19
6316 13:38:49.440351 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6317 13:38:49.443688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6318 13:38:49.446667 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6319 13:38:49.453451 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6320 13:38:49.456811 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6321 13:38:49.456918 ==
6322 13:38:49.460159 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 13:38:49.463130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 13:38:49.463241 ==
6325 13:38:49.469860 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6326 13:38:49.476389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6327 13:38:49.479838 [CA 0] Center 36 (8~64) winsize 57
6328 13:38:49.482983 [CA 1] Center 36 (8~64) winsize 57
6329 13:38:49.486100 [CA 2] Center 36 (8~64) winsize 57
6330 13:38:49.489684 [CA 3] Center 36 (8~64) winsize 57
6331 13:38:49.492702 [CA 4] Center 36 (8~64) winsize 57
6332 13:38:49.496227 [CA 5] Center 36 (8~64) winsize 57
6333 13:38:49.496342
6334 13:38:49.499649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6335 13:38:49.499762
6336 13:38:49.502956 [CATrainingPosCal] consider 1 rank data
6337 13:38:49.506202 u2DelayCellTimex100 = 270/100 ps
6338 13:38:49.509513 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 13:38:49.512364 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 13:38:49.515987 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 13:38:49.519615 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 13:38:49.522808 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 13:38:49.526037 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 13:38:49.526158
6345 13:38:49.532742 CA PerBit enable=1, Macro0, CA PI delay=36
6346 13:38:49.532860
6347 13:38:49.532965 [CBTSetCACLKResult] CA Dly = 36
6348 13:38:49.536143 CS Dly: 1 (0~32)
6349 13:38:49.536233 ==
6350 13:38:49.539435 Dram Type= 6, Freq= 0, CH_0, rank 1
6351 13:38:49.542725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 13:38:49.542804 ==
6353 13:38:49.548978 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6354 13:38:49.555385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6355 13:38:49.558902 [CA 0] Center 36 (8~64) winsize 57
6356 13:38:49.562187 [CA 1] Center 36 (8~64) winsize 57
6357 13:38:49.565521 [CA 2] Center 36 (8~64) winsize 57
6358 13:38:49.568933 [CA 3] Center 36 (8~64) winsize 57
6359 13:38:49.569020 [CA 4] Center 36 (8~64) winsize 57
6360 13:38:49.572245 [CA 5] Center 36 (8~64) winsize 57
6361 13:38:49.572373
6362 13:38:49.578862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6363 13:38:49.578984
6364 13:38:49.581676 [CATrainingPosCal] consider 2 rank data
6365 13:38:49.585201 u2DelayCellTimex100 = 270/100 ps
6366 13:38:49.588441 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6367 13:38:49.591889 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6368 13:38:49.595154 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6369 13:38:49.598879 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6370 13:38:49.601845 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 13:38:49.605090 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 13:38:49.605295
6373 13:38:49.608625 CA PerBit enable=1, Macro0, CA PI delay=36
6374 13:38:49.608806
6375 13:38:49.612052 [CBTSetCACLKResult] CA Dly = 36
6376 13:38:49.615340 CS Dly: 1 (0~32)
6377 13:38:49.615500
6378 13:38:49.618676 ----->DramcWriteLeveling(PI) begin...
6379 13:38:49.618840 ==
6380 13:38:49.622116 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 13:38:49.625273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 13:38:49.625388 ==
6383 13:38:49.628549 Write leveling (Byte 0): 40 => 8
6384 13:38:49.631512 Write leveling (Byte 1): 32 => 0
6385 13:38:49.635086 DramcWriteLeveling(PI) end<-----
6386 13:38:49.635213
6387 13:38:49.635313 ==
6388 13:38:49.638490 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 13:38:49.641901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 13:38:49.641984 ==
6391 13:38:49.645139 [Gating] SW mode calibration
6392 13:38:49.651810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6393 13:38:49.658261 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6394 13:38:49.661142 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6395 13:38:49.667881 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6396 13:38:49.671344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6397 13:38:49.674798 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6398 13:38:49.681508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6399 13:38:49.684867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6400 13:38:49.688218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6401 13:38:49.694705 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6402 13:38:49.698101 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 13:38:49.701230 Total UI for P1: 0, mck2ui 16
6404 13:38:49.704456 best dqsien dly found for B0: ( 0, 14, 24)
6405 13:38:49.707585 Total UI for P1: 0, mck2ui 16
6406 13:38:49.710675 best dqsien dly found for B1: ( 0, 14, 24)
6407 13:38:49.714131 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6408 13:38:49.717694 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6409 13:38:49.717779
6410 13:38:49.720975 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6411 13:38:49.723729 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6412 13:38:49.726960 [Gating] SW calibration Done
6413 13:38:49.727075 ==
6414 13:38:49.730360 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 13:38:49.733873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 13:38:49.737087 ==
6417 13:38:49.737207 RX Vref Scan: 0
6418 13:38:49.737312
6419 13:38:49.740606 RX Vref 0 -> 0, step: 1
6420 13:38:49.740710
6421 13:38:49.743686 RX Delay -410 -> 252, step: 16
6422 13:38:49.747196 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6423 13:38:49.750425 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6424 13:38:49.753611 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6425 13:38:49.760140 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6426 13:38:49.763322 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6427 13:38:49.766862 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6428 13:38:49.770198 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6429 13:38:49.776878 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6430 13:38:49.780116 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6431 13:38:49.783448 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6432 13:38:49.790233 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6433 13:38:49.793163 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6434 13:38:49.796597 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6435 13:38:49.799749 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6436 13:38:49.806439 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6437 13:38:49.809843 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6438 13:38:49.809922 ==
6439 13:38:49.813149 Dram Type= 6, Freq= 0, CH_0, rank 0
6440 13:38:49.816719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 13:38:49.816800 ==
6442 13:38:49.819841 DQS Delay:
6443 13:38:49.819920 DQS0 = 43, DQS1 = 59
6444 13:38:49.819983 DQM Delay:
6445 13:38:49.822804 DQM0 = 9, DQM1 = 11
6446 13:38:49.822884 DQ Delay:
6447 13:38:49.826499 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6448 13:38:49.829852 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6449 13:38:49.832699 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6450 13:38:49.836037 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6451 13:38:49.836122
6452 13:38:49.836186
6453 13:38:49.836245 ==
6454 13:38:49.839231 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 13:38:49.842623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 13:38:49.846152 ==
6457 13:38:49.846272
6458 13:38:49.846376
6459 13:38:49.846478 TX Vref Scan disable
6460 13:38:49.849483 == TX Byte 0 ==
6461 13:38:49.852531 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 13:38:49.856407 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 13:38:49.859221 == TX Byte 1 ==
6464 13:38:49.862187 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6465 13:38:49.865995 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6466 13:38:49.866106 ==
6467 13:38:49.869168 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 13:38:49.876057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 13:38:49.876160 ==
6470 13:38:49.876229
6471 13:38:49.876290
6472 13:38:49.876348 TX Vref Scan disable
6473 13:38:49.879286 == TX Byte 0 ==
6474 13:38:49.882694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6475 13:38:49.885833 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6476 13:38:49.889318 == TX Byte 1 ==
6477 13:38:49.892419 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6478 13:38:49.895940 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6479 13:38:49.899248
6480 13:38:49.899324 [DATLAT]
6481 13:38:49.899385 Freq=400, CH0 RK0
6482 13:38:49.899455
6483 13:38:49.902569 DATLAT Default: 0xf
6484 13:38:49.902666 0, 0xFFFF, sum = 0
6485 13:38:49.905275 1, 0xFFFF, sum = 0
6486 13:38:49.905366 2, 0xFFFF, sum = 0
6487 13:38:49.909149 3, 0xFFFF, sum = 0
6488 13:38:49.911781 4, 0xFFFF, sum = 0
6489 13:38:49.911860 5, 0xFFFF, sum = 0
6490 13:38:49.915274 6, 0xFFFF, sum = 0
6491 13:38:49.915357 7, 0xFFFF, sum = 0
6492 13:38:49.918348 8, 0xFFFF, sum = 0
6493 13:38:49.918421 9, 0xFFFF, sum = 0
6494 13:38:49.921658 10, 0xFFFF, sum = 0
6495 13:38:49.921740 11, 0xFFFF, sum = 0
6496 13:38:49.925009 12, 0xFFFF, sum = 0
6497 13:38:49.925088 13, 0x0, sum = 1
6498 13:38:49.928119 14, 0x0, sum = 2
6499 13:38:49.928202 15, 0x0, sum = 3
6500 13:38:49.931880 16, 0x0, sum = 4
6501 13:38:49.931958 best_step = 14
6502 13:38:49.932020
6503 13:38:49.932081 ==
6504 13:38:49.935054 Dram Type= 6, Freq= 0, CH_0, rank 0
6505 13:38:49.941531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 13:38:49.941623 ==
6507 13:38:49.941690 RX Vref Scan: 1
6508 13:38:49.941749
6509 13:38:49.945078 RX Vref 0 -> 0, step: 1
6510 13:38:49.945157
6511 13:38:49.947780 RX Delay -359 -> 252, step: 8
6512 13:38:49.947858
6513 13:38:49.951530 Set Vref, RX VrefLevel [Byte0]: 57
6514 13:38:49.954402 [Byte1]: 50
6515 13:38:49.954491
6516 13:38:49.957746 Final RX Vref Byte 0 = 57 to rank0
6517 13:38:49.961001 Final RX Vref Byte 1 = 50 to rank0
6518 13:38:49.964407 Final RX Vref Byte 0 = 57 to rank1
6519 13:38:49.967681 Final RX Vref Byte 1 = 50 to rank1==
6520 13:38:49.970992 Dram Type= 6, Freq= 0, CH_0, rank 0
6521 13:38:49.977925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 13:38:49.978044 ==
6523 13:38:49.978143 DQS Delay:
6524 13:38:49.981036 DQS0 = 48, DQS1 = 64
6525 13:38:49.981120 DQM Delay:
6526 13:38:49.981187 DQM0 = 12, DQM1 = 15
6527 13:38:49.984608 DQ Delay:
6528 13:38:49.988040 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6529 13:38:49.988135 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6530 13:38:49.990848 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6531 13:38:49.994604 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6532 13:38:49.994685
6533 13:38:49.994761
6534 13:38:50.004024 [DQSOSCAuto] RK0, (LSB)MR18= 0xc587, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6535 13:38:50.008026 CH0 RK0: MR19=C0C, MR18=C587
6536 13:38:50.014061 CH0_RK0: MR19=0xC0C, MR18=0xC587, DQSOSC=385, MR23=63, INC=398, DEC=265
6537 13:38:50.014186 ==
6538 13:38:50.017238 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 13:38:50.020630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 13:38:50.020711 ==
6541 13:38:50.024142 [Gating] SW mode calibration
6542 13:38:50.030834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6543 13:38:50.036890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6544 13:38:50.040632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6545 13:38:50.043736 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6546 13:38:50.050635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6547 13:38:50.053859 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6548 13:38:50.056625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6549 13:38:50.063352 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6550 13:38:50.067247 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6551 13:38:50.069891 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6552 13:38:50.076856 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6553 13:38:50.076963 Total UI for P1: 0, mck2ui 16
6554 13:38:50.083405 best dqsien dly found for B0: ( 0, 14, 24)
6555 13:38:50.083491 Total UI for P1: 0, mck2ui 16
6556 13:38:50.087285 best dqsien dly found for B1: ( 0, 14, 24)
6557 13:38:50.093106 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6558 13:38:50.096744 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6559 13:38:50.096849
6560 13:38:50.099860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6561 13:38:50.103143 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6562 13:38:50.106254 [Gating] SW calibration Done
6563 13:38:50.106354 ==
6564 13:38:50.109487 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 13:38:50.113522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 13:38:50.113624 ==
6567 13:38:50.116855 RX Vref Scan: 0
6568 13:38:50.116930
6569 13:38:50.116998 RX Vref 0 -> 0, step: 1
6570 13:38:50.117063
6571 13:38:50.120104 RX Delay -410 -> 252, step: 16
6572 13:38:50.126031 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6573 13:38:50.129489 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6574 13:38:50.132867 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6575 13:38:50.136152 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6576 13:38:50.142996 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6577 13:38:50.145776 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6578 13:38:50.149571 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6579 13:38:50.152849 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6580 13:38:50.158987 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6581 13:38:50.163028 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6582 13:38:50.165582 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6583 13:38:50.169042 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6584 13:38:50.175757 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6585 13:38:50.179013 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6586 13:38:50.182571 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6587 13:38:50.188666 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6588 13:38:50.188776 ==
6589 13:38:50.192062 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 13:38:50.195395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 13:38:50.195490 ==
6592 13:38:50.195557 DQS Delay:
6593 13:38:50.199418 DQS0 = 43, DQS1 = 59
6594 13:38:50.199504 DQM Delay:
6595 13:38:50.202233 DQM0 = 11, DQM1 = 16
6596 13:38:50.202317 DQ Delay:
6597 13:38:50.205206 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6598 13:38:50.208701 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6599 13:38:50.211909 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6600 13:38:50.215218 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6601 13:38:50.215353
6602 13:38:50.215434
6603 13:38:50.215499 ==
6604 13:38:50.218961 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 13:38:50.221995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 13:38:50.222092 ==
6607 13:38:50.222192
6608 13:38:50.222255
6609 13:38:50.225172 TX Vref Scan disable
6610 13:38:50.225267 == TX Byte 0 ==
6611 13:38:50.232454 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6612 13:38:50.235813 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6613 13:38:50.235904 == TX Byte 1 ==
6614 13:38:50.241750 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6615 13:38:50.245047 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6616 13:38:50.245131 ==
6617 13:38:50.248592 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 13:38:50.251965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 13:38:50.252049 ==
6620 13:38:50.252113
6621 13:38:50.252174
6622 13:38:50.255380 TX Vref Scan disable
6623 13:38:50.258941 == TX Byte 0 ==
6624 13:38:50.262077 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6625 13:38:50.265191 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6626 13:38:50.268264 == TX Byte 1 ==
6627 13:38:50.271692 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6628 13:38:50.274920 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6629 13:38:50.275004
6630 13:38:50.275069 [DATLAT]
6631 13:38:50.278143 Freq=400, CH0 RK1
6632 13:38:50.278236
6633 13:38:50.278300 DATLAT Default: 0xe
6634 13:38:50.281465 0, 0xFFFF, sum = 0
6635 13:38:50.281549 1, 0xFFFF, sum = 0
6636 13:38:50.284874 2, 0xFFFF, sum = 0
6637 13:38:50.288029 3, 0xFFFF, sum = 0
6638 13:38:50.288113 4, 0xFFFF, sum = 0
6639 13:38:50.291561 5, 0xFFFF, sum = 0
6640 13:38:50.291646 6, 0xFFFF, sum = 0
6641 13:38:50.294954 7, 0xFFFF, sum = 0
6642 13:38:50.295038 8, 0xFFFF, sum = 0
6643 13:38:50.297768 9, 0xFFFF, sum = 0
6644 13:38:50.297852 10, 0xFFFF, sum = 0
6645 13:38:50.300967 11, 0xFFFF, sum = 0
6646 13:38:50.301050 12, 0xFFFF, sum = 0
6647 13:38:50.304334 13, 0x0, sum = 1
6648 13:38:50.304418 14, 0x0, sum = 2
6649 13:38:50.307846 15, 0x0, sum = 3
6650 13:38:50.307930 16, 0x0, sum = 4
6651 13:38:50.310951 best_step = 14
6652 13:38:50.311033
6653 13:38:50.311097 ==
6654 13:38:50.314806 Dram Type= 6, Freq= 0, CH_0, rank 1
6655 13:38:50.317997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 13:38:50.318081 ==
6657 13:38:50.321089 RX Vref Scan: 0
6658 13:38:50.321172
6659 13:38:50.321236 RX Vref 0 -> 0, step: 1
6660 13:38:50.321296
6661 13:38:50.324247 RX Delay -359 -> 252, step: 8
6662 13:38:50.331851 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6663 13:38:50.335471 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6664 13:38:50.338696 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6665 13:38:50.345120 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6666 13:38:50.348714 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6667 13:38:50.351980 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6668 13:38:50.355267 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6669 13:38:50.361921 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6670 13:38:50.365293 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6671 13:38:50.368397 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6672 13:38:50.371781 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6673 13:38:50.378272 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6674 13:38:50.381599 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6675 13:38:50.384895 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6676 13:38:50.388259 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6677 13:38:50.394549 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6678 13:38:50.394635 ==
6679 13:38:50.397992 Dram Type= 6, Freq= 0, CH_0, rank 1
6680 13:38:50.401354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 13:38:50.401467 ==
6682 13:38:50.401565 DQS Delay:
6683 13:38:50.404704 DQS0 = 44, DQS1 = 60
6684 13:38:50.404787 DQM Delay:
6685 13:38:50.408097 DQM0 = 7, DQM1 = 13
6686 13:38:50.408180 DQ Delay:
6687 13:38:50.410837 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6688 13:38:50.414627 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6689 13:38:50.417904 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6690 13:38:50.421109 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6691 13:38:50.421190
6692 13:38:50.421255
6693 13:38:50.427747 [DQSOSCAuto] RK1, (LSB)MR18= 0xb33f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6694 13:38:50.430975 CH0 RK1: MR19=C0C, MR18=B33F
6695 13:38:50.437447 CH0_RK1: MR19=0xC0C, MR18=0xB33F, DQSOSC=387, MR23=63, INC=394, DEC=262
6696 13:38:50.440616 [RxdqsGatingPostProcess] freq 400
6697 13:38:50.447331 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6698 13:38:50.450883 best DQS0 dly(2T, 0.5T) = (0, 10)
6699 13:38:50.453993 best DQS1 dly(2T, 0.5T) = (0, 10)
6700 13:38:50.457589 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6701 13:38:50.460902 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6702 13:38:50.460985 best DQS0 dly(2T, 0.5T) = (0, 10)
6703 13:38:50.464148 best DQS1 dly(2T, 0.5T) = (0, 10)
6704 13:38:50.467045 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6705 13:38:50.470917 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6706 13:38:50.473525 Pre-setting of DQS Precalculation
6707 13:38:50.480730 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6708 13:38:50.480816 ==
6709 13:38:50.483759 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 13:38:50.486977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 13:38:50.487118 ==
6712 13:38:50.493459 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6713 13:38:50.499979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6714 13:38:50.503370 [CA 0] Center 36 (8~64) winsize 57
6715 13:38:50.506739 [CA 1] Center 36 (8~64) winsize 57
6716 13:38:50.506827 [CA 2] Center 36 (8~64) winsize 57
6717 13:38:50.510178 [CA 3] Center 36 (8~64) winsize 57
6718 13:38:50.513641 [CA 4] Center 36 (8~64) winsize 57
6719 13:38:50.517130 [CA 5] Center 36 (8~64) winsize 57
6720 13:38:50.517205
6721 13:38:50.520164 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6722 13:38:50.523576
6723 13:38:50.526754 [CATrainingPosCal] consider 1 rank data
6724 13:38:50.529921 u2DelayCellTimex100 = 270/100 ps
6725 13:38:50.533290 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 13:38:50.536641 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 13:38:50.539762 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 13:38:50.543201 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 13:38:50.546354 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 13:38:50.549969 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 13:38:50.550080
6732 13:38:50.553166 CA PerBit enable=1, Macro0, CA PI delay=36
6733 13:38:50.553248
6734 13:38:50.556198 [CBTSetCACLKResult] CA Dly = 36
6735 13:38:50.559946 CS Dly: 1 (0~32)
6736 13:38:50.560030 ==
6737 13:38:50.562921 Dram Type= 6, Freq= 0, CH_1, rank 1
6738 13:38:50.566316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 13:38:50.566402 ==
6740 13:38:50.572938 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6741 13:38:50.578930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6742 13:38:50.582966 [CA 0] Center 36 (8~64) winsize 57
6743 13:38:50.583052 [CA 1] Center 36 (8~64) winsize 57
6744 13:38:50.586110 [CA 2] Center 36 (8~64) winsize 57
6745 13:38:50.588797 [CA 3] Center 36 (8~64) winsize 57
6746 13:38:50.592478 [CA 4] Center 36 (8~64) winsize 57
6747 13:38:50.595665 [CA 5] Center 36 (8~64) winsize 57
6748 13:38:50.595749
6749 13:38:50.598824 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6750 13:38:50.602027
6751 13:38:50.605436 [CATrainingPosCal] consider 2 rank data
6752 13:38:50.605519 u2DelayCellTimex100 = 270/100 ps
6753 13:38:50.612304 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6754 13:38:50.615603 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6755 13:38:50.618397 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6756 13:38:50.621765 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6757 13:38:50.625041 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6758 13:38:50.628313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 13:38:50.628397
6760 13:38:50.632193 CA PerBit enable=1, Macro0, CA PI delay=36
6761 13:38:50.632268
6762 13:38:50.635190 [CBTSetCACLKResult] CA Dly = 36
6763 13:38:50.637987 CS Dly: 1 (0~32)
6764 13:38:50.638092
6765 13:38:50.641823 ----->DramcWriteLeveling(PI) begin...
6766 13:38:50.641929 ==
6767 13:38:50.644584 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 13:38:50.648290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 13:38:50.648411 ==
6770 13:38:50.651687 Write leveling (Byte 0): 40 => 8
6771 13:38:50.655086 Write leveling (Byte 1): 40 => 8
6772 13:38:50.658496 DramcWriteLeveling(PI) end<-----
6773 13:38:50.658602
6774 13:38:50.658665 ==
6775 13:38:50.661119 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 13:38:50.664379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 13:38:50.664464 ==
6778 13:38:50.667523 [Gating] SW mode calibration
6779 13:38:50.674451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6780 13:38:50.681060 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6781 13:38:50.684422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6782 13:38:50.690454 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6783 13:38:50.693710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6784 13:38:50.697783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6785 13:38:50.703946 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6786 13:38:50.706890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6787 13:38:50.710054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6788 13:38:50.717051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6789 13:38:50.720317 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 13:38:50.723728 Total UI for P1: 0, mck2ui 16
6791 13:38:50.726513 best dqsien dly found for B0: ( 0, 14, 24)
6792 13:38:50.729853 Total UI for P1: 0, mck2ui 16
6793 13:38:50.733191 best dqsien dly found for B1: ( 0, 14, 24)
6794 13:38:50.736560 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6795 13:38:50.740345 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6796 13:38:50.740445
6797 13:38:50.743431 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6798 13:38:50.746436 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6799 13:38:50.750103 [Gating] SW calibration Done
6800 13:38:50.750223 ==
6801 13:38:50.753432 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 13:38:50.760236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 13:38:50.760331 ==
6804 13:38:50.760426 RX Vref Scan: 0
6805 13:38:50.760491
6806 13:38:50.763004 RX Vref 0 -> 0, step: 1
6807 13:38:50.763115
6808 13:38:50.766372 RX Delay -410 -> 252, step: 16
6809 13:38:50.769706 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6810 13:38:50.773156 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6811 13:38:50.779641 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6812 13:38:50.783044 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6813 13:38:50.786033 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6814 13:38:50.789311 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6815 13:38:50.795981 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6816 13:38:50.799199 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6817 13:38:50.802814 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6818 13:38:50.806020 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6819 13:38:50.812556 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6820 13:38:50.815771 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6821 13:38:50.818845 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6822 13:38:50.822082 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6823 13:38:50.829118 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6824 13:38:50.832376 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6825 13:38:50.832457 ==
6826 13:38:50.835876 Dram Type= 6, Freq= 0, CH_1, rank 0
6827 13:38:50.838993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 13:38:50.839078 ==
6829 13:38:50.842318 DQS Delay:
6830 13:38:50.842390 DQS0 = 43, DQS1 = 51
6831 13:38:50.845825 DQM Delay:
6832 13:38:50.845932 DQM0 = 11, DQM1 = 14
6833 13:38:50.848788 DQ Delay:
6834 13:38:50.848866 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6835 13:38:50.851918 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6836 13:38:50.855108 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6837 13:38:50.858950 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6838 13:38:50.859032
6839 13:38:50.859116
6840 13:38:50.859194 ==
6841 13:38:50.862011 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 13:38:50.868650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 13:38:50.868773 ==
6844 13:38:50.868876
6845 13:38:50.868975
6846 13:38:50.869072 TX Vref Scan disable
6847 13:38:50.871971 == TX Byte 0 ==
6848 13:38:50.875499 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 13:38:50.878680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 13:38:50.882148 == TX Byte 1 ==
6851 13:38:50.885273 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6852 13:38:50.888608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6853 13:38:50.888723 ==
6854 13:38:50.891768 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 13:38:50.898344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 13:38:50.898443 ==
6857 13:38:50.898521
6858 13:38:50.898586
6859 13:38:50.901884 TX Vref Scan disable
6860 13:38:50.901990 == TX Byte 0 ==
6861 13:38:50.905017 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6862 13:38:50.911585 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6863 13:38:50.911708 == TX Byte 1 ==
6864 13:38:50.914752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6865 13:38:50.918047 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6866 13:38:50.921077
6867 13:38:50.921197 [DATLAT]
6868 13:38:50.921266 Freq=400, CH1 RK0
6869 13:38:50.921332
6870 13:38:50.924575 DATLAT Default: 0xf
6871 13:38:50.924693 0, 0xFFFF, sum = 0
6872 13:38:50.928349 1, 0xFFFF, sum = 0
6873 13:38:50.928474 2, 0xFFFF, sum = 0
6874 13:38:50.931201 3, 0xFFFF, sum = 0
6875 13:38:50.934371 4, 0xFFFF, sum = 0
6876 13:38:50.934464 5, 0xFFFF, sum = 0
6877 13:38:50.937815 6, 0xFFFF, sum = 0
6878 13:38:50.937943 7, 0xFFFF, sum = 0
6879 13:38:50.941214 8, 0xFFFF, sum = 0
6880 13:38:50.941328 9, 0xFFFF, sum = 0
6881 13:38:50.944796 10, 0xFFFF, sum = 0
6882 13:38:50.944878 11, 0xFFFF, sum = 0
6883 13:38:50.948084 12, 0xFFFF, sum = 0
6884 13:38:50.948170 13, 0x0, sum = 1
6885 13:38:50.951390 14, 0x0, sum = 2
6886 13:38:50.951474 15, 0x0, sum = 3
6887 13:38:50.954530 16, 0x0, sum = 4
6888 13:38:50.954609 best_step = 14
6889 13:38:50.954672
6890 13:38:50.954731 ==
6891 13:38:50.957690 Dram Type= 6, Freq= 0, CH_1, rank 0
6892 13:38:50.961017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 13:38:50.964494 ==
6894 13:38:50.964571 RX Vref Scan: 1
6895 13:38:50.964634
6896 13:38:50.967698 RX Vref 0 -> 0, step: 1
6897 13:38:50.967769
6898 13:38:50.970570 RX Delay -343 -> 252, step: 8
6899 13:38:50.970657
6900 13:38:50.973973 Set Vref, RX VrefLevel [Byte0]: 45
6901 13:38:50.977232 [Byte1]: 53
6902 13:38:50.977319
6903 13:38:50.980461 Final RX Vref Byte 0 = 45 to rank0
6904 13:38:50.983914 Final RX Vref Byte 1 = 53 to rank0
6905 13:38:50.987428 Final RX Vref Byte 0 = 45 to rank1
6906 13:38:50.990706 Final RX Vref Byte 1 = 53 to rank1==
6907 13:38:50.994238 Dram Type= 6, Freq= 0, CH_1, rank 0
6908 13:38:50.996932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 13:38:51.000181 ==
6910 13:38:51.000260 DQS Delay:
6911 13:38:51.000324 DQS0 = 44, DQS1 = 56
6912 13:38:51.003921 DQM Delay:
6913 13:38:51.004033 DQM0 = 7, DQM1 = 12
6914 13:38:51.007108 DQ Delay:
6915 13:38:51.007212 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6916 13:38:51.010386 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6917 13:38:51.013796 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6918 13:38:51.016702 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =20
6919 13:38:51.016809
6920 13:38:51.016910
6921 13:38:51.026755 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6922 13:38:51.029894 CH1 RK0: MR19=C0C, MR18=9C73
6923 13:38:51.033484 CH1_RK0: MR19=0xC0C, MR18=0x9C73, DQSOSC=390, MR23=63, INC=388, DEC=258
6924 13:38:51.036569 ==
6925 13:38:51.040280 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 13:38:51.043834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 13:38:51.043945 ==
6928 13:38:51.046417 [Gating] SW mode calibration
6929 13:38:51.053236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6930 13:38:51.056669 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6931 13:38:51.062900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6932 13:38:51.066308 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6933 13:38:51.069710 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6934 13:38:51.076135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6935 13:38:51.079156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6936 13:38:51.083114 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6937 13:38:51.089782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6938 13:38:51.092716 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6939 13:38:51.095927 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 13:38:51.099451 Total UI for P1: 0, mck2ui 16
6941 13:38:51.102877 best dqsien dly found for B0: ( 0, 14, 24)
6942 13:38:51.106243 Total UI for P1: 0, mck2ui 16
6943 13:38:51.108931 best dqsien dly found for B1: ( 0, 14, 24)
6944 13:38:51.115670 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6945 13:38:51.118846 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6946 13:38:51.118956
6947 13:38:51.122350 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6948 13:38:51.125475 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6949 13:38:51.128705 [Gating] SW calibration Done
6950 13:38:51.128803 ==
6951 13:38:51.132523 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 13:38:51.135557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 13:38:51.135663 ==
6954 13:38:51.138637 RX Vref Scan: 0
6955 13:38:51.138748
6956 13:38:51.138843 RX Vref 0 -> 0, step: 1
6957 13:38:51.138936
6958 13:38:51.142298 RX Delay -410 -> 252, step: 16
6959 13:38:51.148670 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6960 13:38:51.152251 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6961 13:38:51.155158 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6962 13:38:51.158719 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6963 13:38:51.164955 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6964 13:38:51.168712 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6965 13:38:51.172048 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6966 13:38:51.175144 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6967 13:38:51.181512 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6968 13:38:51.184748 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6969 13:38:51.188328 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6970 13:38:51.191848 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6971 13:38:51.197851 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6972 13:38:51.201221 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6973 13:38:51.204440 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6974 13:38:51.211198 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6975 13:38:51.211328 ==
6976 13:38:51.214724 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 13:38:51.218036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 13:38:51.218151 ==
6979 13:38:51.218246 DQS Delay:
6980 13:38:51.221296 DQS0 = 43, DQS1 = 51
6981 13:38:51.221381 DQM Delay:
6982 13:38:51.224563 DQM0 = 12, DQM1 = 14
6983 13:38:51.224644 DQ Delay:
6984 13:38:51.227555 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6985 13:38:51.230806 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6986 13:38:51.234833 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6987 13:38:51.237461 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6988 13:38:51.237556
6989 13:38:51.237620
6990 13:38:51.237680 ==
6991 13:38:51.240905 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 13:38:51.244091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 13:38:51.244179 ==
6994 13:38:51.244244
6995 13:38:51.244305
6996 13:38:51.247564 TX Vref Scan disable
6997 13:38:51.247647 == TX Byte 0 ==
6998 13:38:51.254028 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6999 13:38:51.257663 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7000 13:38:51.257760 == TX Byte 1 ==
7001 13:38:51.263868 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7002 13:38:51.267306 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7003 13:38:51.267435 ==
7004 13:38:51.270600 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 13:38:51.274072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 13:38:51.274169 ==
7007 13:38:51.274259
7008 13:38:51.274329
7009 13:38:51.277345 TX Vref Scan disable
7010 13:38:51.280752 == TX Byte 0 ==
7011 13:38:51.283928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7012 13:38:51.287295 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7013 13:38:51.287389 == TX Byte 1 ==
7014 13:38:51.293616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
7015 13:38:51.297338 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
7016 13:38:51.297431
7017 13:38:51.297499 [DATLAT]
7018 13:38:51.300150 Freq=400, CH1 RK1
7019 13:38:51.300235
7020 13:38:51.300299 DATLAT Default: 0xe
7021 13:38:51.304014 0, 0xFFFF, sum = 0
7022 13:38:51.304103 1, 0xFFFF, sum = 0
7023 13:38:51.306873 2, 0xFFFF, sum = 0
7024 13:38:51.306957 3, 0xFFFF, sum = 0
7025 13:38:51.310073 4, 0xFFFF, sum = 0
7026 13:38:51.313355 5, 0xFFFF, sum = 0
7027 13:38:51.313449 6, 0xFFFF, sum = 0
7028 13:38:51.316871 7, 0xFFFF, sum = 0
7029 13:38:51.316985 8, 0xFFFF, sum = 0
7030 13:38:51.320349 9, 0xFFFF, sum = 0
7031 13:38:51.320462 10, 0xFFFF, sum = 0
7032 13:38:51.323669 11, 0xFFFF, sum = 0
7033 13:38:51.323788 12, 0xFFFF, sum = 0
7034 13:38:51.327169 13, 0x0, sum = 1
7035 13:38:51.327253 14, 0x0, sum = 2
7036 13:38:51.329792 15, 0x0, sum = 3
7037 13:38:51.329872 16, 0x0, sum = 4
7038 13:38:51.333707 best_step = 14
7039 13:38:51.333809
7040 13:38:51.333905 ==
7041 13:38:51.337112 Dram Type= 6, Freq= 0, CH_1, rank 1
7042 13:38:51.339683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7043 13:38:51.339796 ==
7044 13:38:51.339899 RX Vref Scan: 0
7045 13:38:51.343109
7046 13:38:51.343226 RX Vref 0 -> 0, step: 1
7047 13:38:51.343329
7048 13:38:51.346449 RX Delay -343 -> 252, step: 8
7049 13:38:51.353890 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
7050 13:38:51.357137 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
7051 13:38:51.360527 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
7052 13:38:51.367213 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
7053 13:38:51.370659 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7054 13:38:51.373836 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
7055 13:38:51.376807 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7056 13:38:51.383755 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
7057 13:38:51.386787 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7058 13:38:51.389914 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7059 13:38:51.393660 iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504
7060 13:38:51.400203 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7061 13:38:51.403263 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
7062 13:38:51.406524 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7063 13:38:51.409837 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7064 13:38:51.416545 iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504
7065 13:38:51.416663 ==
7066 13:38:51.420176 Dram Type= 6, Freq= 0, CH_1, rank 1
7067 13:38:51.422805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7068 13:38:51.422893 ==
7069 13:38:51.426271 DQS Delay:
7070 13:38:51.426354 DQS0 = 48, DQS1 = 56
7071 13:38:51.426426 DQM Delay:
7072 13:38:51.429642 DQM0 = 12, DQM1 = 11
7073 13:38:51.429725 DQ Delay:
7074 13:38:51.432864 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7075 13:38:51.436209 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
7076 13:38:51.439558 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7077 13:38:51.442858 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7078 13:38:51.442946
7079 13:38:51.443011
7080 13:38:51.452879 [DQSOSCAuto] RK1, (LSB)MR18= 0x6858, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7081 13:38:51.453005 CH1 RK1: MR19=C0C, MR18=6858
7082 13:38:51.458783 CH1_RK1: MR19=0xC0C, MR18=0x6858, DQSOSC=396, MR23=63, INC=376, DEC=251
7083 13:38:51.462403 [RxdqsGatingPostProcess] freq 400
7084 13:38:51.468784 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7085 13:38:51.472295 best DQS0 dly(2T, 0.5T) = (0, 10)
7086 13:38:51.475546 best DQS1 dly(2T, 0.5T) = (0, 10)
7087 13:38:51.478849 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7088 13:38:51.482253 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7089 13:38:51.485369 best DQS0 dly(2T, 0.5T) = (0, 10)
7090 13:38:51.488686 best DQS1 dly(2T, 0.5T) = (0, 10)
7091 13:38:51.492051 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7092 13:38:51.495468 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7093 13:38:51.498682 Pre-setting of DQS Precalculation
7094 13:38:51.501822 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7095 13:38:51.508688 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7096 13:38:51.514962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7097 13:38:51.518279
7098 13:38:51.518397
7099 13:38:51.518499 [Calibration Summary] 800 Mbps
7100 13:38:51.521600 CH 0, Rank 0
7101 13:38:51.521710 SW Impedance : PASS
7102 13:38:51.524984 DUTY Scan : NO K
7103 13:38:51.528380 ZQ Calibration : PASS
7104 13:38:51.528459 Jitter Meter : NO K
7105 13:38:51.531691 CBT Training : PASS
7106 13:38:51.534983 Write leveling : PASS
7107 13:38:51.535059 RX DQS gating : PASS
7108 13:38:51.538328 RX DQ/DQS(RDDQC) : PASS
7109 13:38:51.541125 TX DQ/DQS : PASS
7110 13:38:51.541232 RX DATLAT : PASS
7111 13:38:51.544832 RX DQ/DQS(Engine): PASS
7112 13:38:51.548345 TX OE : NO K
7113 13:38:51.548432 All Pass.
7114 13:38:51.548497
7115 13:38:51.548557 CH 0, Rank 1
7116 13:38:51.551095 SW Impedance : PASS
7117 13:38:51.554356 DUTY Scan : NO K
7118 13:38:51.554440 ZQ Calibration : PASS
7119 13:38:51.557695 Jitter Meter : NO K
7120 13:38:51.560999 CBT Training : PASS
7121 13:38:51.561104 Write leveling : NO K
7122 13:38:51.564507 RX DQS gating : PASS
7123 13:38:51.567751 RX DQ/DQS(RDDQC) : PASS
7124 13:38:51.567866 TX DQ/DQS : PASS
7125 13:38:51.571175 RX DATLAT : PASS
7126 13:38:51.571261 RX DQ/DQS(Engine): PASS
7127 13:38:51.574121 TX OE : NO K
7128 13:38:51.574231 All Pass.
7129 13:38:51.574297
7130 13:38:51.577426 CH 1, Rank 0
7131 13:38:51.580786 SW Impedance : PASS
7132 13:38:51.580871 DUTY Scan : NO K
7133 13:38:51.584141 ZQ Calibration : PASS
7134 13:38:51.584223 Jitter Meter : NO K
7135 13:38:51.587385 CBT Training : PASS
7136 13:38:51.590771 Write leveling : PASS
7137 13:38:51.590851 RX DQS gating : PASS
7138 13:38:51.593905 RX DQ/DQS(RDDQC) : PASS
7139 13:38:51.597277 TX DQ/DQS : PASS
7140 13:38:51.597361 RX DATLAT : PASS
7141 13:38:51.600557 RX DQ/DQS(Engine): PASS
7142 13:38:51.603965 TX OE : NO K
7143 13:38:51.604043 All Pass.
7144 13:38:51.604106
7145 13:38:51.604165 CH 1, Rank 1
7146 13:38:51.607213 SW Impedance : PASS
7147 13:38:51.610450 DUTY Scan : NO K
7148 13:38:51.610535 ZQ Calibration : PASS
7149 13:38:51.613747 Jitter Meter : NO K
7150 13:38:51.617003 CBT Training : PASS
7151 13:38:51.617088 Write leveling : NO K
7152 13:38:51.620119 RX DQS gating : PASS
7153 13:38:51.623396 RX DQ/DQS(RDDQC) : PASS
7154 13:38:51.623480 TX DQ/DQS : PASS
7155 13:38:51.627122 RX DATLAT : PASS
7156 13:38:51.630073 RX DQ/DQS(Engine): PASS
7157 13:38:51.630158 TX OE : NO K
7158 13:38:51.633422 All Pass.
7159 13:38:51.633507
7160 13:38:51.633572 DramC Write-DBI off
7161 13:38:51.636728 PER_BANK_REFRESH: Hybrid Mode
7162 13:38:51.636859 TX_TRACKING: ON
7163 13:38:51.646750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7164 13:38:51.649915 [FAST_K] Save calibration result to emmc
7165 13:38:51.653247 dramc_set_vcore_voltage set vcore to 725000
7166 13:38:51.656411 Read voltage for 1600, 0
7167 13:38:51.656500 Vio18 = 0
7168 13:38:51.659657 Vcore = 725000
7169 13:38:51.659741 Vdram = 0
7170 13:38:51.659807 Vddq = 0
7171 13:38:51.663245 Vmddr = 0
7172 13:38:51.666252 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7173 13:38:51.673080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7174 13:38:51.673175 MEM_TYPE=3, freq_sel=13
7175 13:38:51.676340 sv_algorithm_assistance_LP4_3733
7176 13:38:51.682826 ============ PULL DRAM RESETB DOWN ============
7177 13:38:51.686150 ========== PULL DRAM RESETB DOWN end =========
7178 13:38:51.689340 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 13:38:51.692791 ===================================
7180 13:38:51.696042 LPDDR4 DRAM CONFIGURATION
7181 13:38:51.699268 ===================================
7182 13:38:51.702690 EX_ROW_EN[0] = 0x0
7183 13:38:51.702777 EX_ROW_EN[1] = 0x0
7184 13:38:51.705974 LP4Y_EN = 0x0
7185 13:38:51.706059 WORK_FSP = 0x1
7186 13:38:51.709270 WL = 0x5
7187 13:38:51.709354 RL = 0x5
7188 13:38:51.712518 BL = 0x2
7189 13:38:51.712602 RPST = 0x0
7190 13:38:51.715615 RD_PRE = 0x0
7191 13:38:51.715700 WR_PRE = 0x1
7192 13:38:51.719474 WR_PST = 0x1
7193 13:38:51.719560 DBI_WR = 0x0
7194 13:38:51.722344 DBI_RD = 0x0
7195 13:38:51.722429 OTF = 0x1
7196 13:38:51.725645 ===================================
7197 13:38:51.728998 ===================================
7198 13:38:51.732228 ANA top config
7199 13:38:51.735444 ===================================
7200 13:38:51.739099 DLL_ASYNC_EN = 0
7201 13:38:51.739194 ALL_SLAVE_EN = 0
7202 13:38:51.742185 NEW_RANK_MODE = 1
7203 13:38:51.745393 DLL_IDLE_MODE = 1
7204 13:38:51.748679 LP45_APHY_COMB_EN = 1
7205 13:38:51.751992 TX_ODT_DIS = 0
7206 13:38:51.752082 NEW_8X_MODE = 1
7207 13:38:51.755268 ===================================
7208 13:38:51.758573 ===================================
7209 13:38:51.761879 data_rate = 3200
7210 13:38:51.764979 CKR = 1
7211 13:38:51.768540 DQ_P2S_RATIO = 8
7212 13:38:51.771910 ===================================
7213 13:38:51.775281 CA_P2S_RATIO = 8
7214 13:38:51.778517 DQ_CA_OPEN = 0
7215 13:38:51.778613 DQ_SEMI_OPEN = 0
7216 13:38:51.781725 CA_SEMI_OPEN = 0
7217 13:38:51.784932 CA_FULL_RATE = 0
7218 13:38:51.788298 DQ_CKDIV4_EN = 0
7219 13:38:51.791636 CA_CKDIV4_EN = 0
7220 13:38:51.795040 CA_PREDIV_EN = 0
7221 13:38:51.795138 PH8_DLY = 12
7222 13:38:51.798414 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7223 13:38:51.801960 DQ_AAMCK_DIV = 4
7224 13:38:51.805123 CA_AAMCK_DIV = 4
7225 13:38:51.808453 CA_ADMCK_DIV = 4
7226 13:38:51.811597 DQ_TRACK_CA_EN = 0
7227 13:38:51.815143 CA_PICK = 1600
7228 13:38:51.815231 CA_MCKIO = 1600
7229 13:38:51.818375 MCKIO_SEMI = 0
7230 13:38:51.821572 PLL_FREQ = 3068
7231 13:38:51.824686 DQ_UI_PI_RATIO = 32
7232 13:38:51.828480 CA_UI_PI_RATIO = 0
7233 13:38:51.831196 ===================================
7234 13:38:51.834724 ===================================
7235 13:38:51.837952 memory_type:LPDDR4
7236 13:38:51.838075 GP_NUM : 10
7237 13:38:51.841306 SRAM_EN : 1
7238 13:38:51.841403 MD32_EN : 0
7239 13:38:51.844655 ===================================
7240 13:38:51.847944 [ANA_INIT] >>>>>>>>>>>>>>
7241 13:38:51.851058 <<<<<< [CONFIGURE PHASE]: ANA_TX
7242 13:38:51.854207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7243 13:38:51.857803 ===================================
7244 13:38:51.860722 data_rate = 3200,PCW = 0X7600
7245 13:38:51.864545 ===================================
7246 13:38:51.867486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7247 13:38:51.874179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7248 13:38:51.877688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7249 13:38:51.884256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7250 13:38:51.887097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7251 13:38:51.890919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7252 13:38:51.891005 [ANA_INIT] flow start
7253 13:38:51.894271 [ANA_INIT] PLL >>>>>>>>
7254 13:38:51.897073 [ANA_INIT] PLL <<<<<<<<
7255 13:38:51.900366 [ANA_INIT] MIDPI >>>>>>>>
7256 13:38:51.900447 [ANA_INIT] MIDPI <<<<<<<<
7257 13:38:51.903684 [ANA_INIT] DLL >>>>>>>>
7258 13:38:51.907130 [ANA_INIT] DLL <<<<<<<<
7259 13:38:51.907210 [ANA_INIT] flow end
7260 13:38:51.910535 ============ LP4 DIFF to SE enter ============
7261 13:38:51.917080 ============ LP4 DIFF to SE exit ============
7262 13:38:51.917189 [ANA_INIT] <<<<<<<<<<<<<
7263 13:38:51.920569 [Flow] Enable top DCM control >>>>>
7264 13:38:51.923844 [Flow] Enable top DCM control <<<<<
7265 13:38:51.927285 Enable DLL master slave shuffle
7266 13:38:51.933570 ==============================================================
7267 13:38:51.936854 Gating Mode config
7268 13:38:51.939740 ==============================================================
7269 13:38:51.943362 Config description:
7270 13:38:51.953557 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7271 13:38:51.960011 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7272 13:38:51.963514 SELPH_MODE 0: By rank 1: By Phase
7273 13:38:51.969973 ==============================================================
7274 13:38:51.972964 GAT_TRACK_EN = 1
7275 13:38:51.976380 RX_GATING_MODE = 2
7276 13:38:51.979260 RX_GATING_TRACK_MODE = 2
7277 13:38:51.983059 SELPH_MODE = 1
7278 13:38:51.983145 PICG_EARLY_EN = 1
7279 13:38:51.986367 VALID_LAT_VALUE = 1
7280 13:38:51.992891 ==============================================================
7281 13:38:51.996132 Enter into Gating configuration >>>>
7282 13:38:51.999489 Exit from Gating configuration <<<<
7283 13:38:52.002807 Enter into DVFS_PRE_config >>>>>
7284 13:38:52.012471 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7285 13:38:52.015879 Exit from DVFS_PRE_config <<<<<
7286 13:38:52.018968 Enter into PICG configuration >>>>
7287 13:38:52.022334 Exit from PICG configuration <<<<
7288 13:38:52.025749 [RX_INPUT] configuration >>>>>
7289 13:38:52.029195 [RX_INPUT] configuration <<<<<
7290 13:38:52.032468 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7291 13:38:52.039024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7292 13:38:52.045196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7293 13:38:52.052063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7294 13:38:52.058842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7295 13:38:52.065459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7296 13:38:52.068842 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7297 13:38:52.072260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7298 13:38:52.075718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7299 13:38:52.081738 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7300 13:38:52.085357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7301 13:38:52.088355 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7302 13:38:52.091674 ===================================
7303 13:38:52.094893 LPDDR4 DRAM CONFIGURATION
7304 13:38:52.098148 ===================================
7305 13:38:52.098239 EX_ROW_EN[0] = 0x0
7306 13:38:52.101747 EX_ROW_EN[1] = 0x0
7307 13:38:52.104808 LP4Y_EN = 0x0
7308 13:38:52.104889 WORK_FSP = 0x1
7309 13:38:52.108118 WL = 0x5
7310 13:38:52.108200 RL = 0x5
7311 13:38:52.112041 BL = 0x2
7312 13:38:52.112129 RPST = 0x0
7313 13:38:52.114701 RD_PRE = 0x0
7314 13:38:52.114778 WR_PRE = 0x1
7315 13:38:52.117984 WR_PST = 0x1
7316 13:38:52.118098 DBI_WR = 0x0
7317 13:38:52.121291 DBI_RD = 0x0
7318 13:38:52.121370 OTF = 0x1
7319 13:38:52.124744 ===================================
7320 13:38:52.128018 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7321 13:38:52.134778 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7322 13:38:52.138065 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7323 13:38:52.141354 ===================================
7324 13:38:52.144754 LPDDR4 DRAM CONFIGURATION
7325 13:38:52.147987 ===================================
7326 13:38:52.148067 EX_ROW_EN[0] = 0x10
7327 13:38:52.151203 EX_ROW_EN[1] = 0x0
7328 13:38:52.154736 LP4Y_EN = 0x0
7329 13:38:52.154818 WORK_FSP = 0x1
7330 13:38:52.158181 WL = 0x5
7331 13:38:52.158262 RL = 0x5
7332 13:38:52.160820 BL = 0x2
7333 13:38:52.160897 RPST = 0x0
7334 13:38:52.164034 RD_PRE = 0x0
7335 13:38:52.164110 WR_PRE = 0x1
7336 13:38:52.167414 WR_PST = 0x1
7337 13:38:52.167493 DBI_WR = 0x0
7338 13:38:52.170927 DBI_RD = 0x0
7339 13:38:52.171016 OTF = 0x1
7340 13:38:52.174250 ===================================
7341 13:38:52.180477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7342 13:38:52.180573 ==
7343 13:38:52.183834 Dram Type= 6, Freq= 0, CH_0, rank 0
7344 13:38:52.190598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 13:38:52.190684 ==
7346 13:38:52.190749 [Duty_Offset_Calibration]
7347 13:38:52.194069 B0:1 B1:-1 CA:0
7348 13:38:52.194189
7349 13:38:52.197337 [DutyScan_Calibration_Flow] k_type=0
7350 13:38:52.206525
7351 13:38:52.206624 ==CLK 0==
7352 13:38:52.209703 Final CLK duty delay cell = 0
7353 13:38:52.213322 [0] MAX Duty = 5093%(X100), DQS PI = 20
7354 13:38:52.216220 [0] MIN Duty = 4907%(X100), DQS PI = 4
7355 13:38:52.219755 [0] AVG Duty = 5000%(X100)
7356 13:38:52.219846
7357 13:38:52.222670 CH0 CLK Duty spec in!! Max-Min= 186%
7358 13:38:52.226461 [DutyScan_Calibration_Flow] ====Done====
7359 13:38:52.226549
7360 13:38:52.229177 [DutyScan_Calibration_Flow] k_type=1
7361 13:38:52.245906
7362 13:38:52.246035 ==DQS 0 ==
7363 13:38:52.248647 Final DQS duty delay cell = -4
7364 13:38:52.252055 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7365 13:38:52.255270 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7366 13:38:52.258482 [-4] AVG Duty = 4906%(X100)
7367 13:38:52.258567
7368 13:38:52.258631 ==DQS 1 ==
7369 13:38:52.262311 Final DQS duty delay cell = 0
7370 13:38:52.265434 [0] MAX Duty = 5156%(X100), DQS PI = 0
7371 13:38:52.268727 [0] MIN Duty = 5000%(X100), DQS PI = 22
7372 13:38:52.272107 [0] AVG Duty = 5078%(X100)
7373 13:38:52.272192
7374 13:38:52.275430 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7375 13:38:52.275524
7376 13:38:52.278117 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7377 13:38:52.281582 [DutyScan_Calibration_Flow] ====Done====
7378 13:38:52.281665
7379 13:38:52.284909 [DutyScan_Calibration_Flow] k_type=3
7380 13:38:52.302777
7381 13:38:52.302922 ==DQM 0 ==
7382 13:38:52.306111 Final DQM duty delay cell = 0
7383 13:38:52.309387 [0] MAX Duty = 5124%(X100), DQS PI = 24
7384 13:38:52.312897 [0] MIN Duty = 4875%(X100), DQS PI = 8
7385 13:38:52.316173 [0] AVG Duty = 4999%(X100)
7386 13:38:52.316260
7387 13:38:52.316324 ==DQM 1 ==
7388 13:38:52.319355 Final DQM duty delay cell = 0
7389 13:38:52.322659 [0] MAX Duty = 5000%(X100), DQS PI = 4
7390 13:38:52.325925 [0] MIN Duty = 4782%(X100), DQS PI = 22
7391 13:38:52.329686 [0] AVG Duty = 4891%(X100)
7392 13:38:52.329774
7393 13:38:52.333299 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7394 13:38:52.333413
7395 13:38:52.336187 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7396 13:38:52.339739 [DutyScan_Calibration_Flow] ====Done====
7397 13:38:52.339838
7398 13:38:52.342755 [DutyScan_Calibration_Flow] k_type=2
7399 13:38:52.359542
7400 13:38:52.359660 ==DQ 0 ==
7401 13:38:52.362745 Final DQ duty delay cell = -4
7402 13:38:52.366148 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7403 13:38:52.369326 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7404 13:38:52.372759 [-4] AVG Duty = 4953%(X100)
7405 13:38:52.372850
7406 13:38:52.372915 ==DQ 1 ==
7407 13:38:52.376182 Final DQ duty delay cell = 0
7408 13:38:52.378918 [0] MAX Duty = 5125%(X100), DQS PI = 2
7409 13:38:52.382118 [0] MIN Duty = 4969%(X100), DQS PI = 38
7410 13:38:52.385501 [0] AVG Duty = 5047%(X100)
7411 13:38:52.385587
7412 13:38:52.389004 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7413 13:38:52.389088
7414 13:38:52.392408 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7415 13:38:52.395736 [DutyScan_Calibration_Flow] ====Done====
7416 13:38:52.395821 ==
7417 13:38:52.399154 Dram Type= 6, Freq= 0, CH_1, rank 0
7418 13:38:52.401824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7419 13:38:52.401917 ==
7420 13:38:52.405281 [Duty_Offset_Calibration]
7421 13:38:52.405364 B0:-1 B1:1 CA:2
7422 13:38:52.405435
7423 13:38:52.408572 [DutyScan_Calibration_Flow] k_type=0
7424 13:38:52.419558
7425 13:38:52.419656 ==CLK 0==
7426 13:38:52.423000 Final CLK duty delay cell = 0
7427 13:38:52.426158 [0] MAX Duty = 5187%(X100), DQS PI = 22
7428 13:38:52.429567 [0] MIN Duty = 4969%(X100), DQS PI = 0
7429 13:38:52.432870 [0] AVG Duty = 5078%(X100)
7430 13:38:52.432979
7431 13:38:52.436190 CH1 CLK Duty spec in!! Max-Min= 218%
7432 13:38:52.439678 [DutyScan_Calibration_Flow] ====Done====
7433 13:38:52.439768
7434 13:38:52.442895 [DutyScan_Calibration_Flow] k_type=1
7435 13:38:52.459560
7436 13:38:52.459713 ==DQS 0 ==
7437 13:38:52.463169 Final DQS duty delay cell = 0
7438 13:38:52.466480 [0] MAX Duty = 5124%(X100), DQS PI = 18
7439 13:38:52.469117 [0] MIN Duty = 4907%(X100), DQS PI = 8
7440 13:38:52.472632 [0] AVG Duty = 5015%(X100)
7441 13:38:52.472742
7442 13:38:52.472843 ==DQS 1 ==
7443 13:38:52.475825 Final DQS duty delay cell = 0
7444 13:38:52.479183 [0] MAX Duty = 5093%(X100), DQS PI = 26
7445 13:38:52.482433 [0] MIN Duty = 4969%(X100), DQS PI = 54
7446 13:38:52.485930 [0] AVG Duty = 5031%(X100)
7447 13:38:52.486034
7448 13:38:52.489350 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7449 13:38:52.489455
7450 13:38:52.492153 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7451 13:38:52.495511 [DutyScan_Calibration_Flow] ====Done====
7452 13:38:52.495624
7453 13:38:52.498816 [DutyScan_Calibration_Flow] k_type=3
7454 13:38:52.516477
7455 13:38:52.516615 ==DQM 0 ==
7456 13:38:52.519535 Final DQM duty delay cell = 0
7457 13:38:52.522900 [0] MAX Duty = 5218%(X100), DQS PI = 34
7458 13:38:52.526444 [0] MIN Duty = 4969%(X100), DQS PI = 10
7459 13:38:52.529690 [0] AVG Duty = 5093%(X100)
7460 13:38:52.529801
7461 13:38:52.529900 ==DQM 1 ==
7462 13:38:52.532961 Final DQM duty delay cell = 0
7463 13:38:52.536105 [0] MAX Duty = 5156%(X100), DQS PI = 6
7464 13:38:52.539612 [0] MIN Duty = 4969%(X100), DQS PI = 28
7465 13:38:52.542717 [0] AVG Duty = 5062%(X100)
7466 13:38:52.542796
7467 13:38:52.545977 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7468 13:38:52.546078
7469 13:38:52.549296 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7470 13:38:52.552880 [DutyScan_Calibration_Flow] ====Done====
7471 13:38:52.552981
7472 13:38:52.556150 [DutyScan_Calibration_Flow] k_type=2
7473 13:38:52.573600
7474 13:38:52.573717 ==DQ 0 ==
7475 13:38:52.576194 Final DQ duty delay cell = 0
7476 13:38:52.579778 [0] MAX Duty = 5156%(X100), DQS PI = 30
7477 13:38:52.582930 [0] MIN Duty = 4906%(X100), DQS PI = 8
7478 13:38:52.583023 [0] AVG Duty = 5031%(X100)
7479 13:38:52.586304
7480 13:38:52.586388 ==DQ 1 ==
7481 13:38:52.589701 Final DQ duty delay cell = 0
7482 13:38:52.593158 [0] MAX Duty = 5156%(X100), DQS PI = 10
7483 13:38:52.595843 [0] MIN Duty = 4969%(X100), DQS PI = 56
7484 13:38:52.599261 [0] AVG Duty = 5062%(X100)
7485 13:38:52.599346
7486 13:38:52.603224 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7487 13:38:52.603330
7488 13:38:52.605905 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7489 13:38:52.609146 [DutyScan_Calibration_Flow] ====Done====
7490 13:38:52.612662 nWR fixed to 30
7491 13:38:52.616120 [ModeRegInit_LP4] CH0 RK0
7492 13:38:52.616210 [ModeRegInit_LP4] CH0 RK1
7493 13:38:52.619559 [ModeRegInit_LP4] CH1 RK0
7494 13:38:52.622851 [ModeRegInit_LP4] CH1 RK1
7495 13:38:52.622931 match AC timing 5
7496 13:38:52.628889 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7497 13:38:52.632167 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7498 13:38:52.636058 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7499 13:38:52.642137 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7500 13:38:52.645574 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7501 13:38:52.645656 [MiockJmeterHQA]
7502 13:38:52.645721
7503 13:38:52.648986 [DramcMiockJmeter] u1RxGatingPI = 0
7504 13:38:52.652208 0 : 4253, 4027
7505 13:38:52.652313 4 : 4253, 4026
7506 13:38:52.655602 8 : 4363, 4138
7507 13:38:52.655716 12 : 4363, 4138
7508 13:38:52.658962 16 : 4363, 4137
7509 13:38:52.659040 20 : 4252, 4027
7510 13:38:52.659104 24 : 4252, 4027
7511 13:38:52.662369 28 : 4253, 4026
7512 13:38:52.662449 32 : 4363, 4138
7513 13:38:52.665791 36 : 4252, 4027
7514 13:38:52.665878 40 : 4363, 4137
7515 13:38:52.668457 44 : 4252, 4027
7516 13:38:52.668534 48 : 4252, 4027
7517 13:38:52.672299 52 : 4253, 4027
7518 13:38:52.672408 56 : 4255, 4029
7519 13:38:52.672502 60 : 4360, 4138
7520 13:38:52.675468 64 : 4250, 4027
7521 13:38:52.675537 68 : 4361, 4137
7522 13:38:52.678510 72 : 4250, 4027
7523 13:38:52.678587 76 : 4250, 4026
7524 13:38:52.681940 80 : 4250, 4027
7525 13:38:52.682049 84 : 4361, 4138
7526 13:38:52.685046 88 : 4250, 4027
7527 13:38:52.685125 92 : 4360, 382
7528 13:38:52.685190 96 : 4253, 0
7529 13:38:52.688604 100 : 4251, 0
7530 13:38:52.688684 104 : 4250, 0
7531 13:38:52.691724 108 : 4250, 0
7532 13:38:52.691803 112 : 4252, 0
7533 13:38:52.691868 116 : 4250, 0
7534 13:38:52.695303 120 : 4250, 0
7535 13:38:52.695385 124 : 4250, 0
7536 13:38:52.695450 128 : 4361, 0
7537 13:38:52.698506 132 : 4250, 0
7538 13:38:52.698583 136 : 4250, 0
7539 13:38:52.701831 140 : 4249, 0
7540 13:38:52.701911 144 : 4250, 0
7541 13:38:52.701976 148 : 4250, 0
7542 13:38:52.705228 152 : 4250, 0
7543 13:38:52.705335 156 : 4250, 0
7544 13:38:52.708405 160 : 4250, 0
7545 13:38:52.708493 164 : 4252, 0
7546 13:38:52.708560 168 : 4250, 0
7547 13:38:52.711448 172 : 4250, 0
7548 13:38:52.711552 176 : 4252, 0
7549 13:38:52.714949 180 : 4361, 0
7550 13:38:52.715035 184 : 4250, 0
7551 13:38:52.715101 188 : 4250, 0
7552 13:38:52.718133 192 : 4251, 0
7553 13:38:52.718244 196 : 4361, 0
7554 13:38:52.721658 200 : 4361, 0
7555 13:38:52.721761 204 : 4250, 0
7556 13:38:52.721854 208 : 4361, 0
7557 13:38:52.725174 212 : 4250, 0
7558 13:38:52.725246 216 : 4250, 0
7559 13:38:52.725308 220 : 4250, 0
7560 13:38:52.728314 224 : 4250, 117
7561 13:38:52.728428 228 : 4361, 3080
7562 13:38:52.731662 232 : 4250, 4027
7563 13:38:52.731741 236 : 4360, 4137
7564 13:38:52.734977 240 : 4250, 4026
7565 13:38:52.735054 244 : 4250, 4027
7566 13:38:52.738033 248 : 4250, 4027
7567 13:38:52.738139 252 : 4252, 4029
7568 13:38:52.741350 256 : 4250, 4027
7569 13:38:52.741469 260 : 4250, 4027
7570 13:38:52.744687 264 : 4250, 4027
7571 13:38:52.744789 268 : 4253, 4029
7572 13:38:52.747887 272 : 4250, 4027
7573 13:38:52.747990 276 : 4360, 4138
7574 13:38:52.748083 280 : 4361, 4138
7575 13:38:52.751167 284 : 4250, 4026
7576 13:38:52.751265 288 : 4363, 4139
7577 13:38:52.754846 292 : 4360, 4138
7578 13:38:52.754948 296 : 4250, 4027
7579 13:38:52.757535 300 : 4250, 4027
7580 13:38:52.757610 304 : 4253, 4029
7581 13:38:52.761081 308 : 4250, 4027
7582 13:38:52.761183 312 : 4250, 4027
7583 13:38:52.764262 316 : 4250, 4027
7584 13:38:52.764371 320 : 4253, 4029
7585 13:38:52.767768 324 : 4250, 4027
7586 13:38:52.767873 328 : 4360, 4138
7587 13:38:52.771258 332 : 4361, 4138
7588 13:38:52.771366 336 : 4250, 3899
7589 13:38:52.774510 340 : 4363, 2090
7590 13:38:52.774615
7591 13:38:52.774693 MIOCK jitter meter ch=0
7592 13:38:52.774754
7593 13:38:52.777788 1T = (340-92) = 248 dly cells
7594 13:38:52.783872 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7595 13:38:52.783980 ==
7596 13:38:52.787771 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 13:38:52.790546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 13:38:52.790653 ==
7599 13:38:52.797559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7600 13:38:52.800579 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7601 13:38:52.804007 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7602 13:38:52.810847 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7603 13:38:52.820217 [CA 0] Center 43 (12~74) winsize 63
7604 13:38:52.823434 [CA 1] Center 43 (13~73) winsize 61
7605 13:38:52.826923 [CA 2] Center 38 (9~68) winsize 60
7606 13:38:52.830196 [CA 3] Center 38 (9~68) winsize 60
7607 13:38:52.833351 [CA 4] Center 36 (7~66) winsize 60
7608 13:38:52.836822 [CA 5] Center 36 (6~66) winsize 61
7609 13:38:52.836924
7610 13:38:52.840263 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7611 13:38:52.840382
7612 13:38:52.843339 [CATrainingPosCal] consider 1 rank data
7613 13:38:52.846685 u2DelayCellTimex100 = 262/100 ps
7614 13:38:52.853196 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7615 13:38:52.856535 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7616 13:38:52.860071 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7617 13:38:52.863473 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7618 13:38:52.866158 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7619 13:38:52.869535 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7620 13:38:52.869641
7621 13:38:52.872833 CA PerBit enable=1, Macro0, CA PI delay=36
7622 13:38:52.872945
7623 13:38:52.876179 [CBTSetCACLKResult] CA Dly = 36
7624 13:38:52.879396 CS Dly: 11 (0~42)
7625 13:38:52.882890 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7626 13:38:52.886180 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7627 13:38:52.886286 ==
7628 13:38:52.889489 Dram Type= 6, Freq= 0, CH_0, rank 1
7629 13:38:52.895985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 13:38:52.896104 ==
7631 13:38:52.899365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7632 13:38:52.906137 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7633 13:38:52.908991 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7634 13:38:52.915442 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7635 13:38:52.923759 [CA 0] Center 43 (13~74) winsize 62
7636 13:38:52.926928 [CA 1] Center 44 (14~74) winsize 61
7637 13:38:52.929987 [CA 2] Center 38 (9~68) winsize 60
7638 13:38:52.933293 [CA 3] Center 38 (9~68) winsize 60
7639 13:38:52.936476 [CA 4] Center 36 (7~66) winsize 60
7640 13:38:52.940145 [CA 5] Center 36 (6~66) winsize 61
7641 13:38:52.940264
7642 13:38:52.943378 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7643 13:38:52.943493
7644 13:38:52.949975 [CATrainingPosCal] consider 2 rank data
7645 13:38:52.950090 u2DelayCellTimex100 = 262/100 ps
7646 13:38:52.956780 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7647 13:38:52.960097 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7648 13:38:52.962806 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7649 13:38:52.966131 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7650 13:38:52.969454 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7651 13:38:52.972639 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7652 13:38:52.972749
7653 13:38:52.976107 CA PerBit enable=1, Macro0, CA PI delay=36
7654 13:38:52.976217
7655 13:38:52.979535 [CBTSetCACLKResult] CA Dly = 36
7656 13:38:52.982812 CS Dly: 11 (0~43)
7657 13:38:52.986331 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7658 13:38:52.989663 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7659 13:38:52.989776
7660 13:38:52.992397 ----->DramcWriteLeveling(PI) begin...
7661 13:38:52.992502 ==
7662 13:38:52.996174 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 13:38:53.002526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 13:38:53.002617 ==
7665 13:38:53.005706 Write leveling (Byte 0): 35 => 35
7666 13:38:53.009068 Write leveling (Byte 1): 27 => 27
7667 13:38:53.012136 DramcWriteLeveling(PI) end<-----
7668 13:38:53.012239
7669 13:38:53.012340 ==
7670 13:38:53.015553 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 13:38:53.019117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 13:38:53.019201 ==
7673 13:38:53.022303 [Gating] SW mode calibration
7674 13:38:53.029018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7675 13:38:53.035630 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7676 13:38:53.038702 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7677 13:38:53.042456 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7678 13:38:53.045514 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 13:38:53.052092 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7680 13:38:53.055676 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7681 13:38:53.058841 1 4 20 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7682 13:38:53.065282 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7683 13:38:53.068751 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7684 13:38:53.074939 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7685 13:38:53.078145 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7686 13:38:53.081462 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7687 13:38:53.084993 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7688 13:38:53.091649 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7689 13:38:53.095046 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7690 13:38:53.098613 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7691 13:38:53.105145 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7692 13:38:53.108307 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7693 13:38:53.111327 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7694 13:38:53.120939 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7695 13:38:53.121674 1 6 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7696 13:38:53.127626 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7697 13:38:53.130959 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7698 13:38:53.134122 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7699 13:38:53.140758 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 13:38:53.144072 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7701 13:38:53.147651 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7702 13:38:53.154244 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7703 13:38:53.157597 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7704 13:38:53.160731 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7705 13:38:53.167424 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7706 13:38:53.171107 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 13:38:53.174091 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 13:38:53.180443 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 13:38:53.183786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 13:38:53.186964 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 13:38:53.193627 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 13:38:53.196955 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 13:38:53.200295 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 13:38:53.207038 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 13:38:53.210311 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 13:38:53.213680 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 13:38:53.220235 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 13:38:53.223272 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7719 13:38:53.226459 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7720 13:38:53.233170 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7721 13:38:53.233307 Total UI for P1: 0, mck2ui 16
7722 13:38:53.239686 best dqsien dly found for B0: ( 1, 9, 10)
7723 13:38:53.242948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7724 13:38:53.246450 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7725 13:38:53.249745 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7726 13:38:53.252854 Total UI for P1: 0, mck2ui 16
7727 13:38:53.256114 best dqsien dly found for B1: ( 1, 9, 20)
7728 13:38:53.262836 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7729 13:38:53.266041 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7730 13:38:53.266152
7731 13:38:53.269344 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7732 13:38:53.272572 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7733 13:38:53.276237 [Gating] SW calibration Done
7734 13:38:53.276344 ==
7735 13:38:53.279306 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 13:38:53.282446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 13:38:53.282551 ==
7738 13:38:53.286246 RX Vref Scan: 0
7739 13:38:53.286362
7740 13:38:53.286455 RX Vref 0 -> 0, step: 1
7741 13:38:53.286544
7742 13:38:53.288975 RX Delay 0 -> 252, step: 8
7743 13:38:53.292323 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7744 13:38:53.298873 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7745 13:38:53.302792 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7746 13:38:53.306036 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7747 13:38:53.309179 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7748 13:38:53.312586 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7749 13:38:53.318856 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7750 13:38:53.322674 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7751 13:38:53.325755 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7752 13:38:53.328721 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7753 13:38:53.332402 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7754 13:38:53.338836 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7755 13:38:53.341974 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7756 13:38:53.345108 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7757 13:38:53.348450 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7758 13:38:53.351790 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7759 13:38:53.355721 ==
7760 13:38:53.358975 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 13:38:53.362088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 13:38:53.362207 ==
7763 13:38:53.362275 DQS Delay:
7764 13:38:53.365457 DQS0 = 0, DQS1 = 0
7765 13:38:53.365541 DQM Delay:
7766 13:38:53.368795 DQM0 = 134, DQM1 = 125
7767 13:38:53.368912 DQ Delay:
7768 13:38:53.371930 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7769 13:38:53.375256 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7770 13:38:53.378474 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7771 13:38:53.381808 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7772 13:38:53.381912
7773 13:38:53.382004
7774 13:38:53.384978 ==
7775 13:38:53.388139 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 13:38:53.391386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 13:38:53.391496 ==
7778 13:38:53.391588
7779 13:38:53.391685
7780 13:38:53.395090 TX Vref Scan disable
7781 13:38:53.395193 == TX Byte 0 ==
7782 13:38:53.401069 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7783 13:38:53.404367 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7784 13:38:53.404474 == TX Byte 1 ==
7785 13:38:53.410990 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7786 13:38:53.414450 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7787 13:38:53.414567 ==
7788 13:38:53.417873 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 13:38:53.420948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 13:38:53.421040 ==
7791 13:38:53.435011
7792 13:38:53.438581 TX Vref early break, caculate TX vref
7793 13:38:53.441424 TX Vref=16, minBit 6, minWin=22, winSum=368
7794 13:38:53.445149 TX Vref=18, minBit 0, minWin=23, winSum=380
7795 13:38:53.448319 TX Vref=20, minBit 6, minWin=23, winSum=388
7796 13:38:53.451396 TX Vref=22, minBit 4, minWin=23, winSum=396
7797 13:38:53.455251 TX Vref=24, minBit 7, minWin=24, winSum=406
7798 13:38:53.461799 TX Vref=26, minBit 0, minWin=25, winSum=413
7799 13:38:53.464386 TX Vref=28, minBit 0, minWin=24, winSum=417
7800 13:38:53.467718 TX Vref=30, minBit 5, minWin=24, winSum=411
7801 13:38:53.471036 TX Vref=32, minBit 0, minWin=24, winSum=400
7802 13:38:53.474909 TX Vref=34, minBit 4, minWin=23, winSum=387
7803 13:38:53.481023 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 26
7804 13:38:53.481218
7805 13:38:53.484393 Final TX Range 0 Vref 26
7806 13:38:53.484566
7807 13:38:53.484685 ==
7808 13:38:53.487658 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 13:38:53.490774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 13:38:53.490934 ==
7811 13:38:53.491054
7812 13:38:53.491171
7813 13:38:53.494027 TX Vref Scan disable
7814 13:38:53.500830 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7815 13:38:53.500947 == TX Byte 0 ==
7816 13:38:53.504152 u2DelayCellOfst[0]=14 cells (4 PI)
7817 13:38:53.507474 u2DelayCellOfst[1]=18 cells (5 PI)
7818 13:38:53.510641 u2DelayCellOfst[2]=14 cells (4 PI)
7819 13:38:53.513996 u2DelayCellOfst[3]=14 cells (4 PI)
7820 13:38:53.517447 u2DelayCellOfst[4]=11 cells (3 PI)
7821 13:38:53.520819 u2DelayCellOfst[5]=0 cells (0 PI)
7822 13:38:53.524052 u2DelayCellOfst[6]=18 cells (5 PI)
7823 13:38:53.527396 u2DelayCellOfst[7]=18 cells (5 PI)
7824 13:38:53.530038 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7825 13:38:53.533919 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7826 13:38:53.537202 == TX Byte 1 ==
7827 13:38:53.540411 u2DelayCellOfst[8]=0 cells (0 PI)
7828 13:38:53.543703 u2DelayCellOfst[9]=0 cells (0 PI)
7829 13:38:53.546632 u2DelayCellOfst[10]=7 cells (2 PI)
7830 13:38:53.549853 u2DelayCellOfst[11]=0 cells (0 PI)
7831 13:38:53.553369 u2DelayCellOfst[12]=7 cells (2 PI)
7832 13:38:53.556599 u2DelayCellOfst[13]=11 cells (3 PI)
7833 13:38:53.556711 u2DelayCellOfst[14]=11 cells (3 PI)
7834 13:38:53.560189 u2DelayCellOfst[15]=7 cells (2 PI)
7835 13:38:53.566411 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7836 13:38:53.570219 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7837 13:38:53.570309 DramC Write-DBI on
7838 13:38:53.573306 ==
7839 13:38:53.576403 Dram Type= 6, Freq= 0, CH_0, rank 0
7840 13:38:53.579779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7841 13:38:53.579863 ==
7842 13:38:53.579929
7843 13:38:53.579989
7844 13:38:53.583282 TX Vref Scan disable
7845 13:38:53.583362 == TX Byte 0 ==
7846 13:38:53.589814 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7847 13:38:53.589936 == TX Byte 1 ==
7848 13:38:53.592991 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7849 13:38:53.596128 DramC Write-DBI off
7850 13:38:53.596217
7851 13:38:53.596305 [DATLAT]
7852 13:38:53.599519 Freq=1600, CH0 RK0
7853 13:38:53.599607
7854 13:38:53.599695 DATLAT Default: 0xf
7855 13:38:53.602743 0, 0xFFFF, sum = 0
7856 13:38:53.602843 1, 0xFFFF, sum = 0
7857 13:38:53.605992 2, 0xFFFF, sum = 0
7858 13:38:53.606114 3, 0xFFFF, sum = 0
7859 13:38:53.609863 4, 0xFFFF, sum = 0
7860 13:38:53.612515 5, 0xFFFF, sum = 0
7861 13:38:53.612630 6, 0xFFFF, sum = 0
7862 13:38:53.615801 7, 0xFFFF, sum = 0
7863 13:38:53.615910 8, 0xFFFF, sum = 0
7864 13:38:53.619020 9, 0xFFFF, sum = 0
7865 13:38:53.619103 10, 0xFFFF, sum = 0
7866 13:38:53.622417 11, 0xFFFF, sum = 0
7867 13:38:53.622497 12, 0xFFFF, sum = 0
7868 13:38:53.625765 13, 0xFFFF, sum = 0
7869 13:38:53.625868 14, 0x0, sum = 1
7870 13:38:53.628995 15, 0x0, sum = 2
7871 13:38:53.629104 16, 0x0, sum = 3
7872 13:38:53.632361 17, 0x0, sum = 4
7873 13:38:53.632469 best_step = 15
7874 13:38:53.632561
7875 13:38:53.632648 ==
7876 13:38:53.635598 Dram Type= 6, Freq= 0, CH_0, rank 0
7877 13:38:53.642192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7878 13:38:53.642289 ==
7879 13:38:53.642376 RX Vref Scan: 1
7880 13:38:53.642441
7881 13:38:53.645479 Set Vref Range= 24 -> 127
7882 13:38:53.645557
7883 13:38:53.648776 RX Vref 24 -> 127, step: 1
7884 13:38:53.648878
7885 13:38:53.648971 RX Delay 11 -> 252, step: 4
7886 13:38:53.649060
7887 13:38:53.652772 Set Vref, RX VrefLevel [Byte0]: 24
7888 13:38:53.655971 [Byte1]: 24
7889 13:38:53.659800
7890 13:38:53.659906 Set Vref, RX VrefLevel [Byte0]: 25
7891 13:38:53.665825 [Byte1]: 25
7892 13:38:53.665908
7893 13:38:53.669422 Set Vref, RX VrefLevel [Byte0]: 26
7894 13:38:53.672522 [Byte1]: 26
7895 13:38:53.672633
7896 13:38:53.675943 Set Vref, RX VrefLevel [Byte0]: 27
7897 13:38:53.678863 [Byte1]: 27
7898 13:38:53.682308
7899 13:38:53.682402 Set Vref, RX VrefLevel [Byte0]: 28
7900 13:38:53.686158 [Byte1]: 28
7901 13:38:53.690381
7902 13:38:53.690476 Set Vref, RX VrefLevel [Byte0]: 29
7903 13:38:53.693128 [Byte1]: 29
7904 13:38:53.697697
7905 13:38:53.697801 Set Vref, RX VrefLevel [Byte0]: 30
7906 13:38:53.701040 [Byte1]: 30
7907 13:38:53.705685
7908 13:38:53.705790 Set Vref, RX VrefLevel [Byte0]: 31
7909 13:38:53.708385 [Byte1]: 31
7910 13:38:53.713013
7911 13:38:53.713122 Set Vref, RX VrefLevel [Byte0]: 32
7912 13:38:53.716062 [Byte1]: 32
7913 13:38:53.720434
7914 13:38:53.720547 Set Vref, RX VrefLevel [Byte0]: 33
7915 13:38:53.723680 [Byte1]: 33
7916 13:38:53.728406
7917 13:38:53.728504 Set Vref, RX VrefLevel [Byte0]: 34
7918 13:38:53.731557 [Byte1]: 34
7919 13:38:53.735522
7920 13:38:53.735605 Set Vref, RX VrefLevel [Byte0]: 35
7921 13:38:53.739120 [Byte1]: 35
7922 13:38:53.743763
7923 13:38:53.743882 Set Vref, RX VrefLevel [Byte0]: 36
7924 13:38:53.746461 [Byte1]: 36
7925 13:38:53.750854
7926 13:38:53.750960 Set Vref, RX VrefLevel [Byte0]: 37
7927 13:38:53.754025 [Byte1]: 37
7928 13:38:53.758716
7929 13:38:53.758831 Set Vref, RX VrefLevel [Byte0]: 38
7930 13:38:53.764827 [Byte1]: 38
7931 13:38:53.764934
7932 13:38:53.768009 Set Vref, RX VrefLevel [Byte0]: 39
7933 13:38:53.772033 [Byte1]: 39
7934 13:38:53.772135
7935 13:38:53.775102 Set Vref, RX VrefLevel [Byte0]: 40
7936 13:38:53.778189 [Byte1]: 40
7937 13:38:53.781446
7938 13:38:53.781523 Set Vref, RX VrefLevel [Byte0]: 41
7939 13:38:53.784686 [Byte1]: 41
7940 13:38:53.789009
7941 13:38:53.789089 Set Vref, RX VrefLevel [Byte0]: 42
7942 13:38:53.792567 [Byte1]: 42
7943 13:38:53.796824
7944 13:38:53.796934 Set Vref, RX VrefLevel [Byte0]: 43
7945 13:38:53.800004 [Byte1]: 43
7946 13:38:53.804423
7947 13:38:53.804529 Set Vref, RX VrefLevel [Byte0]: 44
7948 13:38:53.807745 [Byte1]: 44
7949 13:38:53.811742
7950 13:38:53.811845 Set Vref, RX VrefLevel [Byte0]: 45
7951 13:38:53.815000 [Byte1]: 45
7952 13:38:53.819553
7953 13:38:53.819663 Set Vref, RX VrefLevel [Byte0]: 46
7954 13:38:53.822851 [Byte1]: 46
7955 13:38:53.827265
7956 13:38:53.827375 Set Vref, RX VrefLevel [Byte0]: 47
7957 13:38:53.830386 [Byte1]: 47
7958 13:38:53.835020
7959 13:38:53.835132 Set Vref, RX VrefLevel [Byte0]: 48
7960 13:38:53.837782 [Byte1]: 48
7961 13:38:53.842465
7962 13:38:53.842557 Set Vref, RX VrefLevel [Byte0]: 49
7963 13:38:53.845772 [Byte1]: 49
7964 13:38:53.849742
7965 13:38:53.849841 Set Vref, RX VrefLevel [Byte0]: 50
7966 13:38:53.853120 [Byte1]: 50
7967 13:38:53.857675
7968 13:38:53.857781 Set Vref, RX VrefLevel [Byte0]: 51
7969 13:38:53.864074 [Byte1]: 51
7970 13:38:53.864166
7971 13:38:53.867210 Set Vref, RX VrefLevel [Byte0]: 52
7972 13:38:53.870674 [Byte1]: 52
7973 13:38:53.870776
7974 13:38:53.873766 Set Vref, RX VrefLevel [Byte0]: 53
7975 13:38:53.877104 [Byte1]: 53
7976 13:38:53.880319
7977 13:38:53.880422 Set Vref, RX VrefLevel [Byte0]: 54
7978 13:38:53.883604 [Byte1]: 54
7979 13:38:53.887838
7980 13:38:53.887916 Set Vref, RX VrefLevel [Byte0]: 55
7981 13:38:53.891369 [Byte1]: 55
7982 13:38:53.895718
7983 13:38:53.895823 Set Vref, RX VrefLevel [Byte0]: 56
7984 13:38:53.898967 [Byte1]: 56
7985 13:38:53.903384
7986 13:38:53.903466 Set Vref, RX VrefLevel [Byte0]: 57
7987 13:38:53.906530 [Byte1]: 57
7988 13:38:53.910750
7989 13:38:53.910856 Set Vref, RX VrefLevel [Byte0]: 58
7990 13:38:53.914035 [Byte1]: 58
7991 13:38:53.918717
7992 13:38:53.918795 Set Vref, RX VrefLevel [Byte0]: 59
7993 13:38:53.922017 [Byte1]: 59
7994 13:38:53.925920
7995 13:38:53.926032 Set Vref, RX VrefLevel [Byte0]: 60
7996 13:38:53.929071 [Byte1]: 60
7997 13:38:53.933554
7998 13:38:53.933635 Set Vref, RX VrefLevel [Byte0]: 61
7999 13:38:53.936806 [Byte1]: 61
8000 13:38:53.941314
8001 13:38:53.941402 Set Vref, RX VrefLevel [Byte0]: 62
8002 13:38:53.944450 [Byte1]: 62
8003 13:38:53.949104
8004 13:38:53.949221 Set Vref, RX VrefLevel [Byte0]: 63
8005 13:38:53.952464 [Byte1]: 63
8006 13:38:53.956226
8007 13:38:53.956308 Set Vref, RX VrefLevel [Byte0]: 64
8008 13:38:53.962676 [Byte1]: 64
8009 13:38:53.962762
8010 13:38:53.966480 Set Vref, RX VrefLevel [Byte0]: 65
8011 13:38:53.969986 [Byte1]: 65
8012 13:38:53.970086
8013 13:38:53.973272 Set Vref, RX VrefLevel [Byte0]: 66
8014 13:38:53.976278 [Byte1]: 66
8015 13:38:53.979468
8016 13:38:53.979555 Set Vref, RX VrefLevel [Byte0]: 67
8017 13:38:53.982886 [Byte1]: 67
8018 13:38:53.986674
8019 13:38:53.986794 Set Vref, RX VrefLevel [Byte0]: 68
8020 13:38:53.990614 [Byte1]: 68
8021 13:38:53.994836
8022 13:38:53.994947 Set Vref, RX VrefLevel [Byte0]: 69
8023 13:38:53.997960 [Byte1]: 69
8024 13:38:54.002328
8025 13:38:54.002428 Set Vref, RX VrefLevel [Byte0]: 70
8026 13:38:54.005422 [Byte1]: 70
8027 13:38:54.010070
8028 13:38:54.010198 Set Vref, RX VrefLevel [Byte0]: 71
8029 13:38:54.013298 [Byte1]: 71
8030 13:38:54.017496
8031 13:38:54.017581 Set Vref, RX VrefLevel [Byte0]: 72
8032 13:38:54.020777 [Byte1]: 72
8033 13:38:54.025234
8034 13:38:54.025353 Set Vref, RX VrefLevel [Byte0]: 73
8035 13:38:54.028461 [Byte1]: 73
8036 13:38:54.032643
8037 13:38:54.032751 Set Vref, RX VrefLevel [Byte0]: 74
8038 13:38:54.036083 [Byte1]: 74
8039 13:38:54.040049
8040 13:38:54.040165 Set Vref, RX VrefLevel [Byte0]: 75
8041 13:38:54.043799 [Byte1]: 75
8042 13:38:54.047616
8043 13:38:54.047737 Set Vref, RX VrefLevel [Byte0]: 76
8044 13:38:54.051035 [Byte1]: 76
8045 13:38:54.055589
8046 13:38:54.055698 Set Vref, RX VrefLevel [Byte0]: 77
8047 13:38:54.058831 [Byte1]: 77
8048 13:38:54.063339
8049 13:38:54.063429 Set Vref, RX VrefLevel [Byte0]: 78
8050 13:38:54.066448 [Byte1]: 78
8051 13:38:54.070593
8052 13:38:54.070703 Set Vref, RX VrefLevel [Byte0]: 79
8053 13:38:54.073912 [Byte1]: 79
8054 13:38:54.078406
8055 13:38:54.078492 Set Vref, RX VrefLevel [Byte0]: 80
8056 13:38:54.081603 [Byte1]: 80
8057 13:38:54.086086
8058 13:38:54.086208 Final RX Vref Byte 0 = 61 to rank0
8059 13:38:54.089391 Final RX Vref Byte 1 = 58 to rank0
8060 13:38:54.092715 Final RX Vref Byte 0 = 61 to rank1
8061 13:38:54.096051 Final RX Vref Byte 1 = 58 to rank1==
8062 13:38:54.099110 Dram Type= 6, Freq= 0, CH_0, rank 0
8063 13:38:54.105638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 13:38:54.105753 ==
8065 13:38:54.105848 DQS Delay:
8066 13:38:54.109344 DQS0 = 0, DQS1 = 0
8067 13:38:54.109451 DQM Delay:
8068 13:38:54.109545 DQM0 = 132, DQM1 = 123
8069 13:38:54.112419 DQ Delay:
8070 13:38:54.115771 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
8071 13:38:54.119038 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8072 13:38:54.122288 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =118
8073 13:38:54.125390 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =128
8074 13:38:54.125510
8075 13:38:54.125602
8076 13:38:54.125691
8077 13:38:54.128510 [DramC_TX_OE_Calibration] TA2
8078 13:38:54.132142 Original DQ_B0 (3 6) =30, OEN = 27
8079 13:38:54.135166 Original DQ_B1 (3 6) =30, OEN = 27
8080 13:38:54.138729 24, 0x0, End_B0=24 End_B1=24
8081 13:38:54.142071 25, 0x0, End_B0=25 End_B1=25
8082 13:38:54.142205 26, 0x0, End_B0=26 End_B1=26
8083 13:38:54.145355 27, 0x0, End_B0=27 End_B1=27
8084 13:38:54.148469 28, 0x0, End_B0=28 End_B1=28
8085 13:38:54.151628 29, 0x0, End_B0=29 End_B1=29
8086 13:38:54.151741 30, 0x0, End_B0=30 End_B1=30
8087 13:38:54.155466 31, 0x4141, End_B0=30 End_B1=30
8088 13:38:54.158835 Byte0 end_step=30 best_step=27
8089 13:38:54.162171 Byte1 end_step=30 best_step=27
8090 13:38:54.165492 Byte0 TX OE(2T, 0.5T) = (3, 3)
8091 13:38:54.168720 Byte1 TX OE(2T, 0.5T) = (3, 3)
8092 13:38:54.168836
8093 13:38:54.168930
8094 13:38:54.175141 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8095 13:38:54.178666 CH0 RK0: MR19=303, MR18=2112
8096 13:38:54.185107 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8097 13:38:54.185223
8098 13:38:54.188236 ----->DramcWriteLeveling(PI) begin...
8099 13:38:54.188326 ==
8100 13:38:54.191378 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 13:38:54.195181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 13:38:54.195268 ==
8103 13:38:54.198021 Write leveling (Byte 0): 35 => 35
8104 13:38:54.201407 Write leveling (Byte 1): 28 => 28
8105 13:38:54.205223 DramcWriteLeveling(PI) end<-----
8106 13:38:54.205302
8107 13:38:54.205366 ==
8108 13:38:54.207812 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 13:38:54.211442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 13:38:54.214646 ==
8111 13:38:54.214731 [Gating] SW mode calibration
8112 13:38:54.224443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8113 13:38:54.227768 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8114 13:38:54.230845 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 13:38:54.237317 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 13:38:54.241136 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 13:38:54.244324 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8118 13:38:54.250773 1 4 16 | B1->B0 | 2322 3232 | 1 1 | (0 0) (1 1)
8119 13:38:54.254090 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8120 13:38:54.257476 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 13:38:54.264340 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 13:38:54.267496 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 13:38:54.270900 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 13:38:54.277522 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8125 13:38:54.280859 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8126 13:38:54.284054 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8127 13:38:54.290785 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8128 13:38:54.293737 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 13:38:54.297110 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 13:38:54.303642 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 13:38:54.307043 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 13:38:54.310665 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 13:38:54.317109 1 6 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8134 13:38:54.320362 1 6 16 | B1->B0 | 2323 4343 | 0 1 | (0 0) (0 0)
8135 13:38:54.323490 1 6 20 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8136 13:38:54.330000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 13:38:54.333367 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 13:38:54.336641 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 13:38:54.343345 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 13:38:54.346475 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8141 13:38:54.350185 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8142 13:38:54.356835 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 13:38:54.360175 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 13:38:54.363337 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 13:38:54.369832 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 13:38:54.372756 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 13:38:54.376029 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 13:38:54.382957 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 13:38:54.386338 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 13:38:54.389781 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 13:38:54.396144 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 13:38:54.399346 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 13:38:54.402533 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 13:38:54.409044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 13:38:54.412215 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 13:38:54.415676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 13:38:54.422361 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8158 13:38:54.425564 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8159 13:38:54.428723 Total UI for P1: 0, mck2ui 16
8160 13:38:54.432620 best dqsien dly found for B0: ( 1, 9, 12)
8161 13:38:54.435307 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 13:38:54.442443 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 13:38:54.442570 Total UI for P1: 0, mck2ui 16
8164 13:38:54.448988 best dqsien dly found for B1: ( 1, 9, 18)
8165 13:38:54.452237 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8166 13:38:54.455378 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8167 13:38:54.455458
8168 13:38:54.458421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8169 13:38:54.462302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8170 13:38:54.465065 [Gating] SW calibration Done
8171 13:38:54.465145 ==
8172 13:38:54.469125 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 13:38:54.471864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 13:38:54.471949 ==
8175 13:38:54.475006 RX Vref Scan: 0
8176 13:38:54.475112
8177 13:38:54.478648 RX Vref 0 -> 0, step: 1
8178 13:38:54.478755
8179 13:38:54.478850 RX Delay 0 -> 252, step: 8
8180 13:38:54.484982 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8181 13:38:54.488101 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8182 13:38:54.491391 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8183 13:38:54.494649 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8184 13:38:54.498051 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8185 13:38:54.505142 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8186 13:38:54.508156 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8187 13:38:54.511498 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8188 13:38:54.514683 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8189 13:38:54.518123 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8190 13:38:54.524531 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8191 13:38:54.527905 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8192 13:38:54.530833 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8193 13:38:54.534284 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8194 13:38:54.541007 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8195 13:38:54.544087 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8196 13:38:54.544204 ==
8197 13:38:54.547348 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 13:38:54.550614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 13:38:54.550706 ==
8200 13:38:54.553913 DQS Delay:
8201 13:38:54.554018 DQS0 = 0, DQS1 = 0
8202 13:38:54.554119 DQM Delay:
8203 13:38:54.557808 DQM0 = 133, DQM1 = 128
8204 13:38:54.557892 DQ Delay:
8205 13:38:54.560548 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8206 13:38:54.563676 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8207 13:38:54.567261 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8208 13:38:54.573638 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8209 13:38:54.573733
8210 13:38:54.573821
8211 13:38:54.573903 ==
8212 13:38:54.577141 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 13:38:54.580333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 13:38:54.580413 ==
8215 13:38:54.580478
8216 13:38:54.580540
8217 13:38:54.583595 TX Vref Scan disable
8218 13:38:54.583672 == TX Byte 0 ==
8219 13:38:54.590534 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8220 13:38:54.593430 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8221 13:38:54.593541 == TX Byte 1 ==
8222 13:38:54.600599 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8223 13:38:54.603980 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8224 13:38:54.604059 ==
8225 13:38:54.607233 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 13:38:54.610408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 13:38:54.610486 ==
8228 13:38:54.624166
8229 13:38:54.627398 TX Vref early break, caculate TX vref
8230 13:38:54.630778 TX Vref=16, minBit 1, minWin=22, winSum=377
8231 13:38:54.634033 TX Vref=18, minBit 0, minWin=23, winSum=386
8232 13:38:54.637266 TX Vref=20, minBit 1, minWin=23, winSum=398
8233 13:38:54.640424 TX Vref=22, minBit 1, minWin=24, winSum=405
8234 13:38:54.643836 TX Vref=24, minBit 1, minWin=24, winSum=412
8235 13:38:54.650527 TX Vref=26, minBit 0, minWin=25, winSum=416
8236 13:38:54.653703 TX Vref=28, minBit 4, minWin=24, winSum=412
8237 13:38:54.656765 TX Vref=30, minBit 0, minWin=24, winSum=405
8238 13:38:54.660004 TX Vref=32, minBit 1, minWin=23, winSum=391
8239 13:38:54.666557 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8240 13:38:54.666705
8241 13:38:54.669834 Final TX Range 0 Vref 26
8242 13:38:54.669944
8243 13:38:54.670048 ==
8244 13:38:54.673624 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 13:38:54.676720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 13:38:54.676808 ==
8247 13:38:54.676875
8248 13:38:54.676936
8249 13:38:54.679768 TX Vref Scan disable
8250 13:38:54.686267 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8251 13:38:54.686359 == TX Byte 0 ==
8252 13:38:54.689708 u2DelayCellOfst[0]=14 cells (4 PI)
8253 13:38:54.693066 u2DelayCellOfst[1]=18 cells (5 PI)
8254 13:38:54.696250 u2DelayCellOfst[2]=14 cells (4 PI)
8255 13:38:54.699924 u2DelayCellOfst[3]=18 cells (5 PI)
8256 13:38:54.702905 u2DelayCellOfst[4]=11 cells (3 PI)
8257 13:38:54.706752 u2DelayCellOfst[5]=0 cells (0 PI)
8258 13:38:54.709904 u2DelayCellOfst[6]=18 cells (5 PI)
8259 13:38:54.713197 u2DelayCellOfst[7]=22 cells (6 PI)
8260 13:38:54.716421 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8261 13:38:54.719724 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8262 13:38:54.722811 == TX Byte 1 ==
8263 13:38:54.722914 u2DelayCellOfst[8]=0 cells (0 PI)
8264 13:38:54.726216 u2DelayCellOfst[9]=0 cells (0 PI)
8265 13:38:54.729380 u2DelayCellOfst[10]=7 cells (2 PI)
8266 13:38:54.733302 u2DelayCellOfst[11]=3 cells (1 PI)
8267 13:38:54.735812 u2DelayCellOfst[12]=14 cells (4 PI)
8268 13:38:54.739092 u2DelayCellOfst[13]=11 cells (3 PI)
8269 13:38:54.742927 u2DelayCellOfst[14]=18 cells (5 PI)
8270 13:38:54.745678 u2DelayCellOfst[15]=11 cells (3 PI)
8271 13:38:54.748973 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8272 13:38:54.756013 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8273 13:38:54.756143 DramC Write-DBI on
8274 13:38:54.756240 ==
8275 13:38:54.759421 Dram Type= 6, Freq= 0, CH_0, rank 1
8276 13:38:54.765835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 13:38:54.765958 ==
8278 13:38:54.766055
8279 13:38:54.766143
8280 13:38:54.766248 TX Vref Scan disable
8281 13:38:54.769489 == TX Byte 0 ==
8282 13:38:54.772921 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8283 13:38:54.776207 == TX Byte 1 ==
8284 13:38:54.779404 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8285 13:38:54.782415 DramC Write-DBI off
8286 13:38:54.782559
8287 13:38:54.782660 [DATLAT]
8288 13:38:54.782754 Freq=1600, CH0 RK1
8289 13:38:54.782836
8290 13:38:54.786212 DATLAT Default: 0xf
8291 13:38:54.789375 0, 0xFFFF, sum = 0
8292 13:38:54.789493 1, 0xFFFF, sum = 0
8293 13:38:54.792484 2, 0xFFFF, sum = 0
8294 13:38:54.792577 3, 0xFFFF, sum = 0
8295 13:38:54.796003 4, 0xFFFF, sum = 0
8296 13:38:54.796121 5, 0xFFFF, sum = 0
8297 13:38:54.799393 6, 0xFFFF, sum = 0
8298 13:38:54.799485 7, 0xFFFF, sum = 0
8299 13:38:54.802823 8, 0xFFFF, sum = 0
8300 13:38:54.802922 9, 0xFFFF, sum = 0
8301 13:38:54.805953 10, 0xFFFF, sum = 0
8302 13:38:54.806063 11, 0xFFFF, sum = 0
8303 13:38:54.809048 12, 0xFFFF, sum = 0
8304 13:38:54.809162 13, 0xFFFF, sum = 0
8305 13:38:54.812159 14, 0x0, sum = 1
8306 13:38:54.812243 15, 0x0, sum = 2
8307 13:38:54.815699 16, 0x0, sum = 3
8308 13:38:54.815780 17, 0x0, sum = 4
8309 13:38:54.819141 best_step = 15
8310 13:38:54.819252
8311 13:38:54.819356 ==
8312 13:38:54.822171 Dram Type= 6, Freq= 0, CH_0, rank 1
8313 13:38:54.825959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 13:38:54.826073 ==
8315 13:38:54.829005 RX Vref Scan: 0
8316 13:38:54.829114
8317 13:38:54.829207 RX Vref 0 -> 0, step: 1
8318 13:38:54.829296
8319 13:38:54.832357 RX Delay 11 -> 252, step: 4
8320 13:38:54.838930 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8321 13:38:54.842121 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8322 13:38:54.845495 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8323 13:38:54.848673 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8324 13:38:54.852027 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8325 13:38:54.858540 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
8326 13:38:54.861746 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8327 13:38:54.865090 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8328 13:38:54.868626 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8329 13:38:54.871772 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8330 13:38:54.878358 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8331 13:38:54.881515 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8332 13:38:54.885030 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8333 13:38:54.888294 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8334 13:38:54.895067 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8335 13:38:54.898181 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8336 13:38:54.898295 ==
8337 13:38:54.901596 Dram Type= 6, Freq= 0, CH_0, rank 1
8338 13:38:54.904739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 13:38:54.904841 ==
8340 13:38:54.907951 DQS Delay:
8341 13:38:54.908049 DQS0 = 0, DQS1 = 0
8342 13:38:54.908138 DQM Delay:
8343 13:38:54.911378 DQM0 = 130, DQM1 = 125
8344 13:38:54.911502 DQ Delay:
8345 13:38:54.914700 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8346 13:38:54.917830 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
8347 13:38:54.920999 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8348 13:38:54.927539 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8349 13:38:54.927626
8350 13:38:54.927695
8351 13:38:54.927766
8352 13:38:54.931046 [DramC_TX_OE_Calibration] TA2
8353 13:38:54.934151 Original DQ_B0 (3 6) =30, OEN = 27
8354 13:38:54.934263 Original DQ_B1 (3 6) =30, OEN = 27
8355 13:38:54.937670 24, 0x0, End_B0=24 End_B1=24
8356 13:38:54.941296 25, 0x0, End_B0=25 End_B1=25
8357 13:38:54.944088 26, 0x0, End_B0=26 End_B1=26
8358 13:38:54.947382 27, 0x0, End_B0=27 End_B1=27
8359 13:38:54.947502 28, 0x0, End_B0=28 End_B1=28
8360 13:38:54.950646 29, 0x0, End_B0=29 End_B1=29
8361 13:38:54.954487 30, 0x0, End_B0=30 End_B1=30
8362 13:38:54.957211 31, 0x4141, End_B0=30 End_B1=30
8363 13:38:54.960535 Byte0 end_step=30 best_step=27
8364 13:38:54.963820 Byte1 end_step=30 best_step=27
8365 13:38:54.963933 Byte0 TX OE(2T, 0.5T) = (3, 3)
8366 13:38:54.967169 Byte1 TX OE(2T, 0.5T) = (3, 3)
8367 13:38:54.967251
8368 13:38:54.967314
8369 13:38:54.976982 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8370 13:38:54.980747 CH0 RK1: MR19=303, MR18=1E01
8371 13:38:54.984102 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8372 13:38:54.987179 [RxdqsGatingPostProcess] freq 1600
8373 13:38:54.993755 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8374 13:38:54.997051 best DQS0 dly(2T, 0.5T) = (1, 1)
8375 13:38:55.000183 best DQS1 dly(2T, 0.5T) = (1, 1)
8376 13:38:55.003791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8377 13:38:55.006948 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8378 13:38:55.010398 best DQS0 dly(2T, 0.5T) = (1, 1)
8379 13:38:55.013658 best DQS1 dly(2T, 0.5T) = (1, 1)
8380 13:38:55.016416 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8381 13:38:55.016527 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8382 13:38:55.019749 Pre-setting of DQS Precalculation
8383 13:38:55.026376 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8384 13:38:55.026489 ==
8385 13:38:55.030122 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 13:38:55.033304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 13:38:55.033406 ==
8388 13:38:55.039560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8389 13:38:55.043335 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8390 13:38:55.046465 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8391 13:38:55.052902 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8392 13:38:55.063047 [CA 0] Center 41 (12~71) winsize 60
8393 13:38:55.066103 [CA 1] Center 42 (13~72) winsize 60
8394 13:38:55.069222 [CA 2] Center 37 (8~66) winsize 59
8395 13:38:55.072752 [CA 3] Center 36 (7~65) winsize 59
8396 13:38:55.075984 [CA 4] Center 36 (7~66) winsize 60
8397 13:38:55.079095 [CA 5] Center 36 (7~66) winsize 60
8398 13:38:55.079206
8399 13:38:55.082076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8400 13:38:55.082190
8401 13:38:55.089490 [CATrainingPosCal] consider 1 rank data
8402 13:38:55.089600 u2DelayCellTimex100 = 262/100 ps
8403 13:38:55.095439 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8404 13:38:55.098827 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8405 13:38:55.101992 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8406 13:38:55.105814 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8407 13:38:55.108523 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8408 13:38:55.112024 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8409 13:38:55.112132
8410 13:38:55.115337 CA PerBit enable=1, Macro0, CA PI delay=36
8411 13:38:55.115449
8412 13:38:55.118701 [CBTSetCACLKResult] CA Dly = 36
8413 13:38:55.122052 CS Dly: 9 (0~40)
8414 13:38:55.125166 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8415 13:38:55.128554 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8416 13:38:55.128654 ==
8417 13:38:55.131970 Dram Type= 6, Freq= 0, CH_1, rank 1
8418 13:38:55.138759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 13:38:55.138847 ==
8420 13:38:55.141467 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8421 13:38:55.148267 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8422 13:38:55.151466 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8423 13:38:55.158168 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8424 13:38:55.165701 [CA 0] Center 42 (13~72) winsize 60
8425 13:38:55.169202 [CA 1] Center 42 (13~72) winsize 60
8426 13:38:55.172144 [CA 2] Center 37 (8~67) winsize 60
8427 13:38:55.175647 [CA 3] Center 36 (7~66) winsize 60
8428 13:38:55.179358 [CA 4] Center 37 (8~67) winsize 60
8429 13:38:55.182097 [CA 5] Center 37 (7~67) winsize 61
8430 13:38:55.182233
8431 13:38:55.185793 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8432 13:38:55.185912
8433 13:38:55.192096 [CATrainingPosCal] consider 2 rank data
8434 13:38:55.192263 u2DelayCellTimex100 = 262/100 ps
8435 13:38:55.198762 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8436 13:38:55.202086 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8437 13:38:55.205458 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8438 13:38:55.208884 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8439 13:38:55.212032 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8440 13:38:55.215250 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8441 13:38:55.215397
8442 13:38:55.218187 CA PerBit enable=1, Macro0, CA PI delay=36
8443 13:38:55.218319
8444 13:38:55.221890 [CBTSetCACLKResult] CA Dly = 36
8445 13:38:55.225395 CS Dly: 10 (0~43)
8446 13:38:55.228670 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8447 13:38:55.231335 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8448 13:38:55.231437
8449 13:38:55.235238 ----->DramcWriteLeveling(PI) begin...
8450 13:38:55.235351 ==
8451 13:38:55.238740 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 13:38:55.244814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 13:38:55.244916 ==
8454 13:38:55.248042 Write leveling (Byte 0): 24 => 24
8455 13:38:55.251203 Write leveling (Byte 1): 27 => 27
8456 13:38:55.254932 DramcWriteLeveling(PI) end<-----
8457 13:38:55.255071
8458 13:38:55.255164 ==
8459 13:38:55.258076 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 13:38:55.261309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 13:38:55.261433 ==
8462 13:38:55.264506 [Gating] SW mode calibration
8463 13:38:55.271215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8464 13:38:55.274664 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8465 13:38:55.281564 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 13:38:55.284521 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 13:38:55.288523 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 13:38:55.294481 1 4 12 | B1->B0 | 2a2a 3332 | 1 1 | (1 1) (0 0)
8469 13:38:55.298033 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8470 13:38:55.301086 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8471 13:38:55.307681 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8472 13:38:55.310850 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8473 13:38:55.314332 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 13:38:55.321114 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 13:38:55.324360 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8476 13:38:55.327280 1 5 12 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
8477 13:38:55.333857 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8478 13:38:55.337038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8479 13:38:55.340240 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8480 13:38:55.347121 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8481 13:38:55.350215 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 13:38:55.356636 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 13:38:55.360420 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8484 13:38:55.363713 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8485 13:38:55.370261 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8486 13:38:55.373019 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 13:38:55.376293 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 13:38:55.383646 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 13:38:55.386257 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 13:38:55.389587 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 13:38:55.396366 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 13:38:55.400225 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8493 13:38:55.403150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8494 13:38:55.406181 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 13:38:55.412927 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 13:38:55.415994 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 13:38:55.419403 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 13:38:55.426788 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 13:38:55.429988 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 13:38:55.433047 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 13:38:55.439228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 13:38:55.442708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 13:38:55.445952 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 13:38:55.452626 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 13:38:55.455763 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 13:38:55.459096 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 13:38:55.465756 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8508 13:38:55.468940 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8509 13:38:55.472336 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 13:38:55.475441 Total UI for P1: 0, mck2ui 16
8511 13:38:55.479118 best dqsien dly found for B0: ( 1, 9, 10)
8512 13:38:55.482615 Total UI for P1: 0, mck2ui 16
8513 13:38:55.485167 best dqsien dly found for B1: ( 1, 9, 12)
8514 13:38:55.488537 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8515 13:38:55.495242 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8516 13:38:55.495344
8517 13:38:55.498634 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8518 13:38:55.502060 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8519 13:38:55.505311 [Gating] SW calibration Done
8520 13:38:55.505411 ==
8521 13:38:55.508660 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 13:38:55.511999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 13:38:55.512085 ==
8524 13:38:55.514884 RX Vref Scan: 0
8525 13:38:55.514989
8526 13:38:55.515087 RX Vref 0 -> 0, step: 1
8527 13:38:55.515191
8528 13:38:55.518518 RX Delay 0 -> 252, step: 8
8529 13:38:55.521491 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8530 13:38:55.528427 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8531 13:38:55.531318 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8532 13:38:55.534818 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8533 13:38:55.538056 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8534 13:38:55.541352 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8535 13:38:55.658188 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8536 13:38:55.658385 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8537 13:38:55.658464 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8538 13:38:55.658526 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8539 13:38:55.658586 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8540 13:38:55.658644 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8541 13:38:55.658700 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8542 13:38:55.658756 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8543 13:38:55.658812 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8544 13:38:55.658867 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8545 13:38:55.658922 ==
8546 13:38:55.658978 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 13:38:55.659035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 13:38:55.659091 ==
8549 13:38:55.659160 DQS Delay:
8550 13:38:55.659214 DQS0 = 0, DQS1 = 0
8551 13:38:55.659299 DQM Delay:
8552 13:38:55.659352 DQM0 = 138, DQM1 = 130
8553 13:38:55.659405 DQ Delay:
8554 13:38:55.659457 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8555 13:38:55.659555 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8556 13:38:55.659609 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8557 13:38:55.659663 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8558 13:38:55.659716
8559 13:38:55.659770
8560 13:38:55.659823 ==
8561 13:38:55.659876 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 13:38:55.659929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 13:38:55.659983 ==
8564 13:38:55.660037
8565 13:38:55.660090
8566 13:38:55.660149 TX Vref Scan disable
8567 13:38:55.660203 == TX Byte 0 ==
8568 13:38:55.660257 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8569 13:38:55.660311 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8570 13:38:55.660365 == TX Byte 1 ==
8571 13:38:55.660419 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8572 13:38:55.660472 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8573 13:38:55.660526 ==
8574 13:38:55.660579 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 13:38:55.660633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 13:38:55.660688 ==
8577 13:38:55.663611
8578 13:38:55.667082 TX Vref early break, caculate TX vref
8579 13:38:55.670321 TX Vref=16, minBit 0, minWin=22, winSum=376
8580 13:38:55.673699 TX Vref=18, minBit 0, minWin=22, winSum=382
8581 13:38:55.677177 TX Vref=20, minBit 0, minWin=24, winSum=398
8582 13:38:55.680138 TX Vref=22, minBit 6, minWin=23, winSum=407
8583 13:38:55.683662 TX Vref=24, minBit 0, minWin=24, winSum=415
8584 13:38:55.689999 TX Vref=26, minBit 15, minWin=25, winSum=423
8585 13:38:55.693040 TX Vref=28, minBit 0, minWin=25, winSum=420
8586 13:38:55.696811 TX Vref=30, minBit 0, minWin=25, winSum=415
8587 13:38:55.700124 TX Vref=32, minBit 5, minWin=23, winSum=404
8588 13:38:55.703410 TX Vref=34, minBit 5, minWin=23, winSum=397
8589 13:38:55.709365 [TxChooseVref] Worse bit 15, Min win 25, Win sum 423, Final Vref 26
8590 13:38:55.709584
8591 13:38:55.712820 Final TX Range 0 Vref 26
8592 13:38:55.713056
8593 13:38:55.713197 ==
8594 13:38:55.716094 Dram Type= 6, Freq= 0, CH_1, rank 0
8595 13:38:55.719358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8596 13:38:55.719516 ==
8597 13:38:55.719615
8598 13:38:55.722756
8599 13:38:55.722888 TX Vref Scan disable
8600 13:38:55.729072 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8601 13:38:55.729269 == TX Byte 0 ==
8602 13:38:55.732930 u2DelayCellOfst[0]=18 cells (5 PI)
8603 13:38:55.736278 u2DelayCellOfst[1]=11 cells (3 PI)
8604 13:38:55.739464 u2DelayCellOfst[2]=0 cells (0 PI)
8605 13:38:55.742621 u2DelayCellOfst[3]=7 cells (2 PI)
8606 13:38:55.745928 u2DelayCellOfst[4]=7 cells (2 PI)
8607 13:38:55.748948 u2DelayCellOfst[5]=18 cells (5 PI)
8608 13:38:55.752108 u2DelayCellOfst[6]=18 cells (5 PI)
8609 13:38:55.755539 u2DelayCellOfst[7]=3 cells (1 PI)
8610 13:38:55.759223 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8611 13:38:55.762320 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8612 13:38:55.765501 == TX Byte 1 ==
8613 13:38:55.768649 u2DelayCellOfst[8]=0 cells (0 PI)
8614 13:38:55.772243 u2DelayCellOfst[9]=3 cells (1 PI)
8615 13:38:55.775242 u2DelayCellOfst[10]=11 cells (3 PI)
8616 13:38:55.778717 u2DelayCellOfst[11]=3 cells (1 PI)
8617 13:38:55.778873 u2DelayCellOfst[12]=18 cells (5 PI)
8618 13:38:55.781875 u2DelayCellOfst[13]=18 cells (5 PI)
8619 13:38:55.785222 u2DelayCellOfst[14]=18 cells (5 PI)
8620 13:38:55.789302 u2DelayCellOfst[15]=14 cells (4 PI)
8621 13:38:55.795567 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8622 13:38:55.799027 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8623 13:38:55.799197 DramC Write-DBI on
8624 13:38:55.801887 ==
8625 13:38:55.802038 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 13:38:55.808697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 13:38:55.808854 ==
8628 13:38:55.808956
8629 13:38:55.809046
8630 13:38:55.812298 TX Vref Scan disable
8631 13:38:55.812462 == TX Byte 0 ==
8632 13:38:55.818290 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8633 13:38:55.818444 == TX Byte 1 ==
8634 13:38:55.821675 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8635 13:38:55.825111 DramC Write-DBI off
8636 13:38:55.825239
8637 13:38:55.825310 [DATLAT]
8638 13:38:55.828337 Freq=1600, CH1 RK0
8639 13:38:55.828447
8640 13:38:55.828517 DATLAT Default: 0xf
8641 13:38:55.831605 0, 0xFFFF, sum = 0
8642 13:38:55.831777 1, 0xFFFF, sum = 0
8643 13:38:55.834941 2, 0xFFFF, sum = 0
8644 13:38:55.835090 3, 0xFFFF, sum = 0
8645 13:38:55.838605 4, 0xFFFF, sum = 0
8646 13:38:55.838780 5, 0xFFFF, sum = 0
8647 13:38:55.842060 6, 0xFFFF, sum = 0
8648 13:38:55.842292 7, 0xFFFF, sum = 0
8649 13:38:55.845096 8, 0xFFFF, sum = 0
8650 13:38:55.845252 9, 0xFFFF, sum = 0
8651 13:38:55.848287 10, 0xFFFF, sum = 0
8652 13:38:55.851571 11, 0xFFFF, sum = 0
8653 13:38:55.851696 12, 0xFFFF, sum = 0
8654 13:38:55.854918 13, 0xFFFF, sum = 0
8655 13:38:55.855036 14, 0x0, sum = 1
8656 13:38:55.858213 15, 0x0, sum = 2
8657 13:38:55.858305 16, 0x0, sum = 3
8658 13:38:55.861782 17, 0x0, sum = 4
8659 13:38:55.861894 best_step = 15
8660 13:38:55.861988
8661 13:38:55.862077 ==
8662 13:38:55.864828 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 13:38:55.868052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 13:38:55.868142 ==
8665 13:38:55.871475 RX Vref Scan: 1
8666 13:38:55.871560
8667 13:38:55.875006 Set Vref Range= 24 -> 127
8668 13:38:55.875094
8669 13:38:55.875160 RX Vref 24 -> 127, step: 1
8670 13:38:55.878048
8671 13:38:55.878132 RX Delay 19 -> 252, step: 4
8672 13:38:55.878222
8673 13:38:55.881127 Set Vref, RX VrefLevel [Byte0]: 24
8674 13:38:55.884685 [Byte1]: 24
8675 13:38:55.887910
8676 13:38:55.888054 Set Vref, RX VrefLevel [Byte0]: 25
8677 13:38:55.891862 [Byte1]: 25
8678 13:38:55.895511
8679 13:38:55.895598 Set Vref, RX VrefLevel [Byte0]: 26
8680 13:38:55.898874 [Byte1]: 26
8681 13:38:55.903544
8682 13:38:55.903634 Set Vref, RX VrefLevel [Byte0]: 27
8683 13:38:55.906817 [Byte1]: 27
8684 13:38:55.910502
8685 13:38:55.910625 Set Vref, RX VrefLevel [Byte0]: 28
8686 13:38:55.914320 [Byte1]: 28
8687 13:38:55.918304
8688 13:38:55.918453 Set Vref, RX VrefLevel [Byte0]: 29
8689 13:38:55.921416 [Byte1]: 29
8690 13:38:55.926315
8691 13:38:55.926440 Set Vref, RX VrefLevel [Byte0]: 30
8692 13:38:55.929407 [Byte1]: 30
8693 13:38:55.933499
8694 13:38:55.933664 Set Vref, RX VrefLevel [Byte0]: 31
8695 13:38:55.936691 [Byte1]: 31
8696 13:38:55.941180
8697 13:38:55.941326 Set Vref, RX VrefLevel [Byte0]: 32
8698 13:38:55.944466 [Byte1]: 32
8699 13:38:55.948973
8700 13:38:55.949135 Set Vref, RX VrefLevel [Byte0]: 33
8701 13:38:55.952128 [Byte1]: 33
8702 13:38:55.956341
8703 13:38:55.956508 Set Vref, RX VrefLevel [Byte0]: 34
8704 13:38:55.959407 [Byte1]: 34
8705 13:38:55.963532
8706 13:38:55.963678 Set Vref, RX VrefLevel [Byte0]: 35
8707 13:38:55.967498 [Byte1]: 35
8708 13:38:55.971448
8709 13:38:55.971606 Set Vref, RX VrefLevel [Byte0]: 36
8710 13:38:55.974800 [Byte1]: 36
8711 13:38:55.979042
8712 13:38:55.979208 Set Vref, RX VrefLevel [Byte0]: 37
8713 13:38:55.982518 [Byte1]: 37
8714 13:38:55.986574
8715 13:38:55.986753 Set Vref, RX VrefLevel [Byte0]: 38
8716 13:38:55.989745 [Byte1]: 38
8717 13:38:55.994573
8718 13:38:55.994694 Set Vref, RX VrefLevel [Byte0]: 39
8719 13:38:55.997436 [Byte1]: 39
8720 13:38:56.001498
8721 13:38:56.001617 Set Vref, RX VrefLevel [Byte0]: 40
8722 13:38:56.007940 [Byte1]: 40
8723 13:38:56.008064
8724 13:38:56.011285 Set Vref, RX VrefLevel [Byte0]: 41
8725 13:38:56.015259 [Byte1]: 41
8726 13:38:56.015354
8727 13:38:56.018397 Set Vref, RX VrefLevel [Byte0]: 42
8728 13:38:56.021687 [Byte1]: 42
8729 13:38:56.021808
8730 13:38:56.025096 Set Vref, RX VrefLevel [Byte0]: 43
8731 13:38:56.028468 [Byte1]: 43
8732 13:38:56.032300
8733 13:38:56.032414 Set Vref, RX VrefLevel [Byte0]: 44
8734 13:38:56.035134 [Byte1]: 44
8735 13:38:56.039713
8736 13:38:56.039796 Set Vref, RX VrefLevel [Byte0]: 45
8737 13:38:56.042973 [Byte1]: 45
8738 13:38:56.047037
8739 13:38:56.047132 Set Vref, RX VrefLevel [Byte0]: 46
8740 13:38:56.050178 [Byte1]: 46
8741 13:38:56.054800
8742 13:38:56.054901 Set Vref, RX VrefLevel [Byte0]: 47
8743 13:38:56.058123 [Byte1]: 47
8744 13:38:56.062007
8745 13:38:56.062124 Set Vref, RX VrefLevel [Byte0]: 48
8746 13:38:56.065329 [Byte1]: 48
8747 13:38:56.070028
8748 13:38:56.070151 Set Vref, RX VrefLevel [Byte0]: 49
8749 13:38:56.073383 [Byte1]: 49
8750 13:38:56.077205
8751 13:38:56.077286 Set Vref, RX VrefLevel [Byte0]: 50
8752 13:38:56.080583 [Byte1]: 50
8753 13:38:56.085158
8754 13:38:56.085269 Set Vref, RX VrefLevel [Byte0]: 51
8755 13:38:56.088467 [Byte1]: 51
8756 13:38:56.093028
8757 13:38:56.093140 Set Vref, RX VrefLevel [Byte0]: 52
8758 13:38:56.095953 [Byte1]: 52
8759 13:38:56.099966
8760 13:38:56.100048 Set Vref, RX VrefLevel [Byte0]: 53
8761 13:38:56.103389 [Byte1]: 53
8762 13:38:56.108044
8763 13:38:56.108132 Set Vref, RX VrefLevel [Byte0]: 54
8764 13:38:56.110775 [Byte1]: 54
8765 13:38:56.115334
8766 13:38:56.115452 Set Vref, RX VrefLevel [Byte0]: 55
8767 13:38:56.118802 [Byte1]: 55
8768 13:38:56.122774
8769 13:38:56.122858 Set Vref, RX VrefLevel [Byte0]: 56
8770 13:38:56.126274 [Byte1]: 56
8771 13:38:56.130597
8772 13:38:56.130685 Set Vref, RX VrefLevel [Byte0]: 57
8773 13:38:56.133722 [Byte1]: 57
8774 13:38:56.138291
8775 13:38:56.138372 Set Vref, RX VrefLevel [Byte0]: 58
8776 13:38:56.141534 [Byte1]: 58
8777 13:38:56.145616
8778 13:38:56.145735 Set Vref, RX VrefLevel [Byte0]: 59
8779 13:38:56.148741 [Byte1]: 59
8780 13:38:56.153250
8781 13:38:56.153336 Set Vref, RX VrefLevel [Byte0]: 60
8782 13:38:56.156525 [Byte1]: 60
8783 13:38:56.160555
8784 13:38:56.160667 Set Vref, RX VrefLevel [Byte0]: 61
8785 13:38:56.163866 [Byte1]: 61
8786 13:38:56.168471
8787 13:38:56.168580 Set Vref, RX VrefLevel [Byte0]: 62
8788 13:38:56.171711 [Byte1]: 62
8789 13:38:56.175712
8790 13:38:56.175826 Set Vref, RX VrefLevel [Byte0]: 63
8791 13:38:56.178916 [Byte1]: 63
8792 13:38:56.183449
8793 13:38:56.183531 Set Vref, RX VrefLevel [Byte0]: 64
8794 13:38:56.186880 [Byte1]: 64
8795 13:38:56.190788
8796 13:38:56.190884 Set Vref, RX VrefLevel [Byte0]: 65
8797 13:38:56.194373 [Byte1]: 65
8798 13:38:56.198345
8799 13:38:56.198450 Set Vref, RX VrefLevel [Byte0]: 66
8800 13:38:56.201792 [Byte1]: 66
8801 13:38:56.206290
8802 13:38:56.206376 Set Vref, RX VrefLevel [Byte0]: 67
8803 13:38:56.209373 [Byte1]: 67
8804 13:38:56.213372
8805 13:38:56.213456 Set Vref, RX VrefLevel [Byte0]: 68
8806 13:38:56.217053 [Byte1]: 68
8807 13:38:56.221626
8808 13:38:56.221733 Set Vref, RX VrefLevel [Byte0]: 69
8809 13:38:56.224276 [Byte1]: 69
8810 13:38:56.229230
8811 13:38:56.229323 Set Vref, RX VrefLevel [Byte0]: 70
8812 13:38:56.231873 [Byte1]: 70
8813 13:38:56.236228
8814 13:38:56.236343 Set Vref, RX VrefLevel [Byte0]: 71
8815 13:38:56.239819 [Byte1]: 71
8816 13:38:56.243828
8817 13:38:56.243939 Set Vref, RX VrefLevel [Byte0]: 72
8818 13:38:56.247457 [Byte1]: 72
8819 13:38:56.251764
8820 13:38:56.251875 Final RX Vref Byte 0 = 53 to rank0
8821 13:38:56.254697 Final RX Vref Byte 1 = 59 to rank0
8822 13:38:56.258382 Final RX Vref Byte 0 = 53 to rank1
8823 13:38:56.261704 Final RX Vref Byte 1 = 59 to rank1==
8824 13:38:56.264879 Dram Type= 6, Freq= 0, CH_1, rank 0
8825 13:38:56.271585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 13:38:56.271703 ==
8827 13:38:56.271797 DQS Delay:
8828 13:38:56.274880 DQS0 = 0, DQS1 = 0
8829 13:38:56.274957 DQM Delay:
8830 13:38:56.275019 DQM0 = 135, DQM1 = 129
8831 13:38:56.278272 DQ Delay:
8832 13:38:56.281009 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8833 13:38:56.284901 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8834 13:38:56.287754 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =118
8835 13:38:56.291029 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8836 13:38:56.291126
8837 13:38:56.291209
8838 13:38:56.291297
8839 13:38:56.294793 [DramC_TX_OE_Calibration] TA2
8840 13:38:56.298294 Original DQ_B0 (3 6) =30, OEN = 27
8841 13:38:56.301444 Original DQ_B1 (3 6) =30, OEN = 27
8842 13:38:56.304824 24, 0x0, End_B0=24 End_B1=24
8843 13:38:56.304933 25, 0x0, End_B0=25 End_B1=25
8844 13:38:56.307468 26, 0x0, End_B0=26 End_B1=26
8845 13:38:56.310853 27, 0x0, End_B0=27 End_B1=27
8846 13:38:56.314704 28, 0x0, End_B0=28 End_B1=28
8847 13:38:56.317511 29, 0x0, End_B0=29 End_B1=29
8848 13:38:56.317590 30, 0x0, End_B0=30 End_B1=30
8849 13:38:56.320691 31, 0x4545, End_B0=30 End_B1=30
8850 13:38:56.324315 Byte0 end_step=30 best_step=27
8851 13:38:56.327436 Byte1 end_step=30 best_step=27
8852 13:38:56.331172 Byte0 TX OE(2T, 0.5T) = (3, 3)
8853 13:38:56.334300 Byte1 TX OE(2T, 0.5T) = (3, 3)
8854 13:38:56.334393
8855 13:38:56.334478
8856 13:38:56.340963 [DQSOSCAuto] RK0, (LSB)MR18= 0x190f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8857 13:38:56.344341 CH1 RK0: MR19=303, MR18=190F
8858 13:38:56.350291 CH1_RK0: MR19=0x303, MR18=0x190F, DQSOSC=397, MR23=63, INC=23, DEC=15
8859 13:38:56.350398
8860 13:38:56.353928 ----->DramcWriteLeveling(PI) begin...
8861 13:38:56.354047 ==
8862 13:38:56.357625 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 13:38:56.360474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 13:38:56.360595 ==
8865 13:38:56.363530 Write leveling (Byte 0): 25 => 25
8866 13:38:56.367023 Write leveling (Byte 1): 26 => 26
8867 13:38:56.370115 DramcWriteLeveling(PI) end<-----
8868 13:38:56.370224
8869 13:38:56.370290 ==
8870 13:38:56.373518 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 13:38:56.376833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 13:38:56.380573 ==
8873 13:38:56.380698 [Gating] SW mode calibration
8874 13:38:56.389895 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8875 13:38:56.393293 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8876 13:38:56.396617 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 13:38:56.403265 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 13:38:56.406747 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8879 13:38:56.409796 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8880 13:38:56.416947 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8881 13:38:56.419653 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 13:38:56.423408 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 13:38:56.429926 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 13:38:56.433117 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 13:38:56.436342 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8886 13:38:56.443153 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8887 13:38:56.445939 1 5 12 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 0)
8888 13:38:56.449708 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8889 13:38:56.456316 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 13:38:56.459483 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 13:38:56.462737 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 13:38:56.469271 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 13:38:56.472639 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8894 13:38:56.475835 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8895 13:38:56.482686 1 6 12 | B1->B0 | 4646 2929 | 0 0 | (0 0) (0 0)
8896 13:38:56.486051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 13:38:56.489270 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 13:38:56.495748 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 13:38:56.499168 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 13:38:56.502395 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 13:38:56.509021 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 13:38:56.512312 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8903 13:38:56.515662 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8904 13:38:56.522149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8905 13:38:56.525563 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 13:38:56.529147 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 13:38:56.535415 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 13:38:56.538730 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 13:38:56.542040 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 13:38:56.548901 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 13:38:56.552250 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 13:38:56.554777 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 13:38:56.562101 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 13:38:56.565327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 13:38:56.568535 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 13:38:56.575033 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 13:38:56.578354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 13:38:56.581462 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8919 13:38:56.588076 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8920 13:38:56.591352 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8921 13:38:56.594888 Total UI for P1: 0, mck2ui 16
8922 13:38:56.598028 best dqsien dly found for B1: ( 1, 9, 10)
8923 13:38:56.601726 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8924 13:38:56.604671 Total UI for P1: 0, mck2ui 16
8925 13:38:56.608194 best dqsien dly found for B0: ( 1, 9, 12)
8926 13:38:56.611633 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8927 13:38:56.614998 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8928 13:38:56.615107
8929 13:38:56.621389 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8930 13:38:56.624695 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8931 13:38:56.627985 [Gating] SW calibration Done
8932 13:38:56.628072 ==
8933 13:38:56.631348 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 13:38:56.634677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 13:38:56.634773 ==
8936 13:38:56.634884 RX Vref Scan: 0
8937 13:38:56.634978
8938 13:38:56.637882 RX Vref 0 -> 0, step: 1
8939 13:38:56.637970
8940 13:38:56.641010 RX Delay 0 -> 252, step: 8
8941 13:38:56.645205 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8942 13:38:56.647894 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8943 13:38:56.654000 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8944 13:38:56.657246 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8945 13:38:56.660700 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8946 13:38:56.663908 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8947 13:38:56.667385 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8948 13:38:56.673813 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8949 13:38:56.677048 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8950 13:38:56.680257 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8951 13:38:56.683557 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8952 13:38:56.687178 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8953 13:38:56.693984 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8954 13:38:56.697162 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8955 13:38:56.700623 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8956 13:38:56.703742 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8957 13:38:56.703826 ==
8958 13:38:56.707030 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 13:38:56.713678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 13:38:56.713802 ==
8961 13:38:56.713896 DQS Delay:
8962 13:38:56.716908 DQS0 = 0, DQS1 = 0
8963 13:38:56.716997 DQM Delay:
8964 13:38:56.720108 DQM0 = 136, DQM1 = 129
8965 13:38:56.720196 DQ Delay:
8966 13:38:56.723229 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8967 13:38:56.726694 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8968 13:38:56.729876 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8969 13:38:56.733119 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8970 13:38:56.733205
8971 13:38:56.733271
8972 13:38:56.733332 ==
8973 13:38:56.736624 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 13:38:56.743003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 13:38:56.743168 ==
8976 13:38:56.743258
8977 13:38:56.743320
8978 13:38:56.743379 TX Vref Scan disable
8979 13:38:56.746840 == TX Byte 0 ==
8980 13:38:56.750052 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8981 13:38:56.756566 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8982 13:38:56.756691 == TX Byte 1 ==
8983 13:38:56.760371 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8984 13:38:56.766408 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8985 13:38:56.766512 ==
8986 13:38:56.769771 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 13:38:56.773055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 13:38:56.773170 ==
8989 13:38:56.785469
8990 13:38:56.788659 TX Vref early break, caculate TX vref
8991 13:38:56.791876 TX Vref=16, minBit 1, minWin=23, winSum=391
8992 13:38:56.795393 TX Vref=18, minBit 0, minWin=24, winSum=399
8993 13:38:56.798655 TX Vref=20, minBit 8, minWin=24, winSum=410
8994 13:38:56.801903 TX Vref=22, minBit 8, minWin=24, winSum=417
8995 13:38:56.805388 TX Vref=24, minBit 0, minWin=26, winSum=427
8996 13:38:56.811759 TX Vref=26, minBit 3, minWin=26, winSum=432
8997 13:38:56.815000 TX Vref=28, minBit 0, minWin=25, winSum=425
8998 13:38:56.818505 TX Vref=30, minBit 0, minWin=26, winSum=425
8999 13:38:56.821963 TX Vref=32, minBit 0, minWin=25, winSum=414
9000 13:38:56.825168 TX Vref=34, minBit 0, minWin=24, winSum=404
9001 13:38:56.831811 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 26
9002 13:38:56.831931
9003 13:38:56.834929 Final TX Range 0 Vref 26
9004 13:38:56.835047
9005 13:38:56.835141 ==
9006 13:38:56.838678 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 13:38:56.841548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 13:38:56.841637 ==
9009 13:38:56.841711
9010 13:38:56.841773
9011 13:38:56.845050 TX Vref Scan disable
9012 13:38:56.851712 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9013 13:38:56.851842 == TX Byte 0 ==
9014 13:38:56.855003 u2DelayCellOfst[0]=22 cells (6 PI)
9015 13:38:56.858118 u2DelayCellOfst[1]=14 cells (4 PI)
9016 13:38:56.861804 u2DelayCellOfst[2]=0 cells (0 PI)
9017 13:38:56.865437 u2DelayCellOfst[3]=7 cells (2 PI)
9018 13:38:56.868028 u2DelayCellOfst[4]=7 cells (2 PI)
9019 13:38:56.871726 u2DelayCellOfst[5]=22 cells (6 PI)
9020 13:38:56.875052 u2DelayCellOfst[6]=22 cells (6 PI)
9021 13:38:56.878324 u2DelayCellOfst[7]=7 cells (2 PI)
9022 13:38:56.881430 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9023 13:38:56.884680 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9024 13:38:56.887824 == TX Byte 1 ==
9025 13:38:56.890968 u2DelayCellOfst[8]=0 cells (0 PI)
9026 13:38:56.891054 u2DelayCellOfst[9]=7 cells (2 PI)
9027 13:38:56.894880 u2DelayCellOfst[10]=11 cells (3 PI)
9028 13:38:56.898072 u2DelayCellOfst[11]=7 cells (2 PI)
9029 13:38:56.900872 u2DelayCellOfst[12]=14 cells (4 PI)
9030 13:38:56.904726 u2DelayCellOfst[13]=18 cells (5 PI)
9031 13:38:56.908137 u2DelayCellOfst[14]=18 cells (5 PI)
9032 13:38:56.910720 u2DelayCellOfst[15]=18 cells (5 PI)
9033 13:38:56.917156 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9034 13:38:56.920628 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9035 13:38:56.920746 DramC Write-DBI on
9036 13:38:56.920852 ==
9037 13:38:56.923955 Dram Type= 6, Freq= 0, CH_1, rank 1
9038 13:38:56.930487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9039 13:38:56.930610 ==
9040 13:38:56.930712
9041 13:38:56.930808
9042 13:38:56.934009 TX Vref Scan disable
9043 13:38:56.934121 == TX Byte 0 ==
9044 13:38:56.940626 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9045 13:38:56.940748 == TX Byte 1 ==
9046 13:38:56.943320 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9047 13:38:56.947021 DramC Write-DBI off
9048 13:38:56.947148
9049 13:38:56.947247 [DATLAT]
9050 13:38:56.950216 Freq=1600, CH1 RK1
9051 13:38:56.950330
9052 13:38:56.950429 DATLAT Default: 0xf
9053 13:38:56.953562 0, 0xFFFF, sum = 0
9054 13:38:56.953680 1, 0xFFFF, sum = 0
9055 13:38:56.956639 2, 0xFFFF, sum = 0
9056 13:38:56.956755 3, 0xFFFF, sum = 0
9057 13:38:56.959871 4, 0xFFFF, sum = 0
9058 13:38:56.959984 5, 0xFFFF, sum = 0
9059 13:38:56.963655 6, 0xFFFF, sum = 0
9060 13:38:56.963746 7, 0xFFFF, sum = 0
9061 13:38:56.966801 8, 0xFFFF, sum = 0
9062 13:38:56.969790 9, 0xFFFF, sum = 0
9063 13:38:56.969880 10, 0xFFFF, sum = 0
9064 13:38:56.973499 11, 0xFFFF, sum = 0
9065 13:38:56.973615 12, 0xFFFF, sum = 0
9066 13:38:56.976525 13, 0xFFFF, sum = 0
9067 13:38:56.976644 14, 0x0, sum = 1
9068 13:38:56.979618 15, 0x0, sum = 2
9069 13:38:56.979710 16, 0x0, sum = 3
9070 13:38:56.982939 17, 0x0, sum = 4
9071 13:38:56.983028 best_step = 15
9072 13:38:56.983116
9073 13:38:56.983217 ==
9074 13:38:56.986554 Dram Type= 6, Freq= 0, CH_1, rank 1
9075 13:38:56.989878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9076 13:38:56.992944 ==
9077 13:38:56.993041 RX Vref Scan: 0
9078 13:38:56.993144
9079 13:38:56.996446 RX Vref 0 -> 0, step: 1
9080 13:38:56.996535
9081 13:38:56.999452 RX Delay 11 -> 252, step: 4
9082 13:38:57.002720 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9083 13:38:57.005916 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9084 13:38:57.009251 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9085 13:38:57.015807 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9086 13:38:57.019009 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9087 13:38:57.022853 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9088 13:38:57.026076 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9089 13:38:57.029375 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9090 13:38:57.035973 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9091 13:38:57.039318 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9092 13:38:57.042672 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9093 13:38:57.045879 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9094 13:38:57.049360 iDelay=203, Bit 12, Center 138 (83 ~ 194) 112
9095 13:38:57.055522 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9096 13:38:57.058954 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9097 13:38:57.062166 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9098 13:38:57.062285 ==
9099 13:38:57.065452 Dram Type= 6, Freq= 0, CH_1, rank 1
9100 13:38:57.068702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9101 13:38:57.072371 ==
9102 13:38:57.072466 DQS Delay:
9103 13:38:57.072570 DQS0 = 0, DQS1 = 0
9104 13:38:57.075496 DQM Delay:
9105 13:38:57.075581 DQM0 = 134, DQM1 = 126
9106 13:38:57.078769 DQ Delay:
9107 13:38:57.081885 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9108 13:38:57.085179 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9109 13:38:57.088435 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9110 13:38:57.092389 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =138
9111 13:38:57.092473
9112 13:38:57.092537
9113 13:38:57.092597
9114 13:38:57.095360 [DramC_TX_OE_Calibration] TA2
9115 13:38:57.098554 Original DQ_B0 (3 6) =30, OEN = 27
9116 13:38:57.101731 Original DQ_B1 (3 6) =30, OEN = 27
9117 13:38:57.105107 24, 0x0, End_B0=24 End_B1=24
9118 13:38:57.105213 25, 0x0, End_B0=25 End_B1=25
9119 13:38:57.108462 26, 0x0, End_B0=26 End_B1=26
9120 13:38:57.111348 27, 0x0, End_B0=27 End_B1=27
9121 13:38:57.114680 28, 0x0, End_B0=28 End_B1=28
9122 13:38:57.118029 29, 0x0, End_B0=29 End_B1=29
9123 13:38:57.118112 30, 0x0, End_B0=30 End_B1=30
9124 13:38:57.121874 31, 0x4141, End_B0=30 End_B1=30
9125 13:38:57.124977 Byte0 end_step=30 best_step=27
9126 13:38:57.128289 Byte1 end_step=30 best_step=27
9127 13:38:57.131688 Byte0 TX OE(2T, 0.5T) = (3, 3)
9128 13:38:57.134996 Byte1 TX OE(2T, 0.5T) = (3, 3)
9129 13:38:57.135075
9130 13:38:57.135138
9131 13:38:57.141084 [DQSOSCAuto] RK1, (LSB)MR18= 0xc08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9132 13:38:57.144364 CH1 RK1: MR19=303, MR18=C08
9133 13:38:57.150994 CH1_RK1: MR19=0x303, MR18=0xC08, DQSOSC=403, MR23=63, INC=22, DEC=15
9134 13:38:57.154188 [RxdqsGatingPostProcess] freq 1600
9135 13:38:57.157545 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9136 13:38:57.160718 best DQS0 dly(2T, 0.5T) = (1, 1)
9137 13:38:57.164233 best DQS1 dly(2T, 0.5T) = (1, 1)
9138 13:38:57.167329 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9139 13:38:57.170618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9140 13:38:57.174032 best DQS0 dly(2T, 0.5T) = (1, 1)
9141 13:38:57.177653 best DQS1 dly(2T, 0.5T) = (1, 1)
9142 13:38:57.180955 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9143 13:38:57.184321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9144 13:38:57.187443 Pre-setting of DQS Precalculation
9145 13:38:57.190671 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9146 13:38:57.197415 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9147 13:38:57.206876 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9148 13:38:57.206997
9149 13:38:57.207094
9150 13:38:57.210872 [Calibration Summary] 3200 Mbps
9151 13:38:57.210954 CH 0, Rank 0
9152 13:38:57.214009 SW Impedance : PASS
9153 13:38:57.214115 DUTY Scan : NO K
9154 13:38:57.217044 ZQ Calibration : PASS
9155 13:38:57.220370 Jitter Meter : NO K
9156 13:38:57.220460 CBT Training : PASS
9157 13:38:57.223821 Write leveling : PASS
9158 13:38:57.226957 RX DQS gating : PASS
9159 13:38:57.227041 RX DQ/DQS(RDDQC) : PASS
9160 13:38:57.230275 TX DQ/DQS : PASS
9161 13:38:57.233546 RX DATLAT : PASS
9162 13:38:57.233630 RX DQ/DQS(Engine): PASS
9163 13:38:57.236618 TX OE : PASS
9164 13:38:57.236695 All Pass.
9165 13:38:57.236760
9166 13:38:57.239738 CH 0, Rank 1
9167 13:38:57.239817 SW Impedance : PASS
9168 13:38:57.242945 DUTY Scan : NO K
9169 13:38:57.246202 ZQ Calibration : PASS
9170 13:38:57.246284 Jitter Meter : NO K
9171 13:38:57.249531 CBT Training : PASS
9172 13:38:57.249639 Write leveling : PASS
9173 13:38:57.252933 RX DQS gating : PASS
9174 13:38:57.256345 RX DQ/DQS(RDDQC) : PASS
9175 13:38:57.256430 TX DQ/DQS : PASS
9176 13:38:57.259687 RX DATLAT : PASS
9177 13:38:57.262899 RX DQ/DQS(Engine): PASS
9178 13:38:57.263001 TX OE : PASS
9179 13:38:57.266129 All Pass.
9180 13:38:57.266222
9181 13:38:57.266305 CH 1, Rank 0
9182 13:38:57.269359 SW Impedance : PASS
9183 13:38:57.269459 DUTY Scan : NO K
9184 13:38:57.272862 ZQ Calibration : PASS
9185 13:38:57.276092 Jitter Meter : NO K
9186 13:38:57.276201 CBT Training : PASS
9187 13:38:57.279343 Write leveling : PASS
9188 13:38:57.282493 RX DQS gating : PASS
9189 13:38:57.282578 RX DQ/DQS(RDDQC) : PASS
9190 13:38:57.285809 TX DQ/DQS : PASS
9191 13:38:57.289087 RX DATLAT : PASS
9192 13:38:57.289180 RX DQ/DQS(Engine): PASS
9193 13:38:57.292399 TX OE : PASS
9194 13:38:57.292519 All Pass.
9195 13:38:57.292588
9196 13:38:57.295692 CH 1, Rank 1
9197 13:38:57.295818 SW Impedance : PASS
9198 13:38:57.299086 DUTY Scan : NO K
9199 13:38:57.302464 ZQ Calibration : PASS
9200 13:38:57.302544 Jitter Meter : NO K
9201 13:38:57.305738 CBT Training : PASS
9202 13:38:57.309148 Write leveling : PASS
9203 13:38:57.309253 RX DQS gating : PASS
9204 13:38:57.312202 RX DQ/DQS(RDDQC) : PASS
9205 13:38:57.315354 TX DQ/DQS : PASS
9206 13:38:57.315456 RX DATLAT : PASS
9207 13:38:57.318802 RX DQ/DQS(Engine): PASS
9208 13:38:57.322137 TX OE : PASS
9209 13:38:57.322233 All Pass.
9210 13:38:57.322299
9211 13:38:57.322360 DramC Write-DBI on
9212 13:38:57.325412 PER_BANK_REFRESH: Hybrid Mode
9213 13:38:57.328810 TX_TRACKING: ON
9214 13:38:57.335147 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9215 13:38:57.344898 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9216 13:38:57.351711 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9217 13:38:57.355288 [FAST_K] Save calibration result to emmc
9218 13:38:57.358359 sync common calibartion params.
9219 13:38:57.361675 sync cbt_mode0:1, 1:1
9220 13:38:57.361807 dram_init: ddr_geometry: 2
9221 13:38:57.364999 dram_init: ddr_geometry: 2
9222 13:38:57.368108 dram_init: ddr_geometry: 2
9223 13:38:57.371477 0:dram_rank_size:100000000
9224 13:38:57.371617 1:dram_rank_size:100000000
9225 13:38:57.377862 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9226 13:38:57.381064 DFS_SHUFFLE_HW_MODE: ON
9227 13:38:57.384401 dramc_set_vcore_voltage set vcore to 725000
9228 13:38:57.384498 Read voltage for 1600, 0
9229 13:38:57.388186 Vio18 = 0
9230 13:38:57.388278 Vcore = 725000
9231 13:38:57.388344 Vdram = 0
9232 13:38:57.391533 Vddq = 0
9233 13:38:57.391620 Vmddr = 0
9234 13:38:57.394671 switch to 3200 Mbps bootup
9235 13:38:57.394770 [DramcRunTimeConfig]
9236 13:38:57.397972 PHYPLL
9237 13:38:57.398061 DPM_CONTROL_AFTERK: ON
9238 13:38:57.401132 PER_BANK_REFRESH: ON
9239 13:38:57.404430 REFRESH_OVERHEAD_REDUCTION: ON
9240 13:38:57.404524 CMD_PICG_NEW_MODE: OFF
9241 13:38:57.407937 XRTWTW_NEW_MODE: ON
9242 13:38:57.408022 XRTRTR_NEW_MODE: ON
9243 13:38:57.410922 TX_TRACKING: ON
9244 13:38:57.411032 RDSEL_TRACKING: OFF
9245 13:38:57.414218 DQS Precalculation for DVFS: ON
9246 13:38:57.417715 RX_TRACKING: OFF
9247 13:38:57.417801 HW_GATING DBG: ON
9248 13:38:57.420677 ZQCS_ENABLE_LP4: ON
9249 13:38:57.420753 RX_PICG_NEW_MODE: ON
9250 13:38:57.423861 TX_PICG_NEW_MODE: ON
9251 13:38:57.423938 ENABLE_RX_DCM_DPHY: ON
9252 13:38:57.427417 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9253 13:38:57.430633 DUMMY_READ_FOR_TRACKING: OFF
9254 13:38:57.434079 !!! SPM_CONTROL_AFTERK: OFF
9255 13:38:57.437197 !!! SPM could not control APHY
9256 13:38:57.437279 IMPEDANCE_TRACKING: ON
9257 13:38:57.440463 TEMP_SENSOR: ON
9258 13:38:57.440549 HW_SAVE_FOR_SR: OFF
9259 13:38:57.443746 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9260 13:38:57.447632 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9261 13:38:57.451091 Read ODT Tracking: ON
9262 13:38:57.453722 Refresh Rate DeBounce: ON
9263 13:38:57.453799 DFS_NO_QUEUE_FLUSH: ON
9264 13:38:57.457361 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9265 13:38:57.460415 ENABLE_DFS_RUNTIME_MRW: OFF
9266 13:38:57.464056 DDR_RESERVE_NEW_MODE: ON
9267 13:38:57.464136 MR_CBT_SWITCH_FREQ: ON
9268 13:38:57.467161 =========================
9269 13:38:57.486022 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9270 13:38:57.489247 dram_init: ddr_geometry: 2
9271 13:38:57.507700 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9272 13:38:57.510968 dram_init: dram init end (result: 0)
9273 13:38:57.517528 DRAM-K: Full calibration passed in 24651 msecs
9274 13:38:57.520915 MRC: failed to locate region type 0.
9275 13:38:57.520995 DRAM rank0 size:0x100000000,
9276 13:38:57.524585 DRAM rank1 size=0x100000000
9277 13:38:57.534020 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9278 13:38:57.540501 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9279 13:38:57.547638 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9280 13:38:57.554174 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9281 13:38:57.557785 DRAM rank0 size:0x100000000,
9282 13:38:57.560424 DRAM rank1 size=0x100000000
9283 13:38:57.560499 CBMEM:
9284 13:38:57.563695 IMD: root @ 0xfffff000 254 entries.
9285 13:38:57.567677 IMD: root @ 0xffffec00 62 entries.
9286 13:38:57.570748 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9287 13:38:57.576935 WARNING: RO_VPD is uninitialized or empty.
9288 13:38:57.580447 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9289 13:38:57.588133 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9290 13:38:57.600471 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9291 13:38:57.612016 BS: romstage times (exec / console): total (unknown) / 24138 ms
9292 13:38:57.612116
9293 13:38:57.612182
9294 13:38:57.622138 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9295 13:38:57.625273 ARM64: Exception handlers installed.
9296 13:38:57.628491 ARM64: Testing exception
9297 13:38:57.631787 ARM64: Done test exception
9298 13:38:57.631873 Enumerating buses...
9299 13:38:57.635129 Show all devs... Before device enumeration.
9300 13:38:57.638443 Root Device: enabled 1
9301 13:38:57.641785 CPU_CLUSTER: 0: enabled 1
9302 13:38:57.641859 CPU: 00: enabled 1
9303 13:38:57.645018 Compare with tree...
9304 13:38:57.645090 Root Device: enabled 1
9305 13:38:57.648145 CPU_CLUSTER: 0: enabled 1
9306 13:38:57.651595 CPU: 00: enabled 1
9307 13:38:57.651679 Root Device scanning...
9308 13:38:57.654576 scan_static_bus for Root Device
9309 13:38:57.658033 CPU_CLUSTER: 0 enabled
9310 13:38:57.661199 scan_static_bus for Root Device done
9311 13:38:57.664567 scan_bus: bus Root Device finished in 8 msecs
9312 13:38:57.664648 done
9313 13:38:57.671320 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9314 13:38:57.674460 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9315 13:38:57.681067 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9316 13:38:57.684696 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9317 13:38:57.687679 Allocating resources...
9318 13:38:57.690956 Reading resources...
9319 13:38:57.694935 Root Device read_resources bus 0 link: 0
9320 13:38:57.697813 DRAM rank0 size:0x100000000,
9321 13:38:57.697933 DRAM rank1 size=0x100000000
9322 13:38:57.704071 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9323 13:38:57.704153 CPU: 00 missing read_resources
9324 13:38:57.710770 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9325 13:38:57.714401 Root Device read_resources bus 0 link: 0 done
9326 13:38:57.717423 Done reading resources.
9327 13:38:57.720697 Show resources in subtree (Root Device)...After reading.
9328 13:38:57.724247 Root Device child on link 0 CPU_CLUSTER: 0
9329 13:38:57.727522 CPU_CLUSTER: 0 child on link 0 CPU: 00
9330 13:38:57.737531 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9331 13:38:57.737625 CPU: 00
9332 13:38:57.740934 Root Device assign_resources, bus 0 link: 0
9333 13:38:57.744089 CPU_CLUSTER: 0 missing set_resources
9334 13:38:57.750276 Root Device assign_resources, bus 0 link: 0 done
9335 13:38:57.750365 Done setting resources.
9336 13:38:57.756834 Show resources in subtree (Root Device)...After assigning values.
9337 13:38:57.760090 Root Device child on link 0 CPU_CLUSTER: 0
9338 13:38:57.763566 CPU_CLUSTER: 0 child on link 0 CPU: 00
9339 13:38:57.773483 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9340 13:38:57.773570 CPU: 00
9341 13:38:57.776675 Done allocating resources.
9342 13:38:57.783178 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9343 13:38:57.783261 Enabling resources...
9344 13:38:57.786525 done.
9345 13:38:57.789921 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9346 13:38:57.793127 Initializing devices...
9347 13:38:57.793280 Root Device init
9348 13:38:57.796263 init hardware done!
9349 13:38:57.796365 0x00000018: ctrlr->caps
9350 13:38:57.799568 52.000 MHz: ctrlr->f_max
9351 13:38:57.803281 0.400 MHz: ctrlr->f_min
9352 13:38:57.806623 0x40ff8080: ctrlr->voltages
9353 13:38:57.806713 sclk: 390625
9354 13:38:57.806782 Bus Width = 1
9355 13:38:57.809624 sclk: 390625
9356 13:38:57.809696 Bus Width = 1
9357 13:38:57.812801 Early init status = 3
9358 13:38:57.815981 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9359 13:38:57.819722 in-header: 03 fc 00 00 01 00 00 00
9360 13:38:57.822884 in-data: 00
9361 13:38:57.826048 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9362 13:38:57.831255 in-header: 03 fd 00 00 00 00 00 00
9363 13:38:57.834251 in-data:
9364 13:38:57.837268 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9365 13:38:57.840568 in-header: 03 fc 00 00 01 00 00 00
9366 13:38:57.843773 in-data: 00
9367 13:38:57.847236 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9368 13:38:57.855230 in-header: 03 fd 00 00 00 00 00 00
9369 13:38:57.855319 in-data:
9370 13:38:57.858598 [SSUSB] Setting up USB HOST controller...
9371 13:38:57.861949 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9372 13:38:57.865238 [SSUSB] phy power-on done.
9373 13:38:57.868692 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9374 13:38:57.875285 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9375 13:38:57.878770 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9376 13:38:57.884914 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9377 13:38:57.891548 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9378 13:38:57.898373 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9379 13:38:57.905166 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9380 13:38:57.911596 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9381 13:38:57.914797 SPM: binary array size = 0x9dc
9382 13:38:57.917718 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9383 13:38:57.924624 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9384 13:38:57.931303 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9385 13:38:57.937599 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9386 13:38:57.940827 configure_display: Starting display init
9387 13:38:57.975227 anx7625_power_on_init: Init interface.
9388 13:38:57.978399 anx7625_disable_pd_protocol: Disabled PD feature.
9389 13:38:57.981749 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9390 13:38:58.009669 anx7625_start_dp_work: Secure OCM version=00
9391 13:38:58.012686 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9392 13:38:58.027582 sp_tx_get_edid_block: EDID Block = 1
9393 13:38:58.130189 Extracted contents:
9394 13:38:58.133618 header: 00 ff ff ff ff ff ff 00
9395 13:38:58.137132 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9396 13:38:58.140188 version: 01 04
9397 13:38:58.143624 basic params: 95 1f 11 78 0a
9398 13:38:58.146506 chroma info: 76 90 94 55 54 90 27 21 50 54
9399 13:38:58.150255 established: 00 00 00
9400 13:38:58.156840 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9401 13:38:58.160236 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9402 13:38:58.166633 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 13:38:58.173145 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9404 13:38:58.179831 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9405 13:38:58.183087 extensions: 00
9406 13:38:58.183172 checksum: fb
9407 13:38:58.183245
9408 13:38:58.189246 Manufacturer: IVO Model 57d Serial Number 0
9409 13:38:58.189327 Made week 0 of 2020
9410 13:38:58.193133 EDID version: 1.4
9411 13:38:58.193214 Digital display
9412 13:38:58.196447 6 bits per primary color channel
9413 13:38:58.199855 DisplayPort interface
9414 13:38:58.199936 Maximum image size: 31 cm x 17 cm
9415 13:38:58.203032 Gamma: 220%
9416 13:38:58.203113 Check DPMS levels
9417 13:38:58.209128 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9418 13:38:58.212468 First detailed timing is preferred timing
9419 13:38:58.215740 Established timings supported:
9420 13:38:58.215823 Standard timings supported:
9421 13:38:58.218991 Detailed timings
9422 13:38:58.222173 Hex of detail: 383680a07038204018303c0035ae10000019
9423 13:38:58.228788 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9424 13:38:58.232425 0780 0798 07c8 0820 hborder 0
9425 13:38:58.235990 0438 043b 0447 0458 vborder 0
9426 13:38:58.239001 -hsync -vsync
9427 13:38:58.239119 Did detailed timing
9428 13:38:58.246150 Hex of detail: 000000000000000000000000000000000000
9429 13:38:58.248732 Manufacturer-specified data, tag 0
9430 13:38:58.252456 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9431 13:38:58.255423 ASCII string: InfoVision
9432 13:38:58.258969 Hex of detail: 000000fe00523134304e574635205248200a
9433 13:38:58.262189 ASCII string: R140NWF5 RH
9434 13:38:58.262303 Checksum
9435 13:38:58.265710 Checksum: 0xfb (valid)
9436 13:38:58.268390 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9437 13:38:58.271732 DSI data_rate: 832800000 bps
9438 13:38:58.278328 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9439 13:38:58.281813 anx7625_parse_edid: pixelclock(138800).
9440 13:38:58.285050 hactive(1920), hsync(48), hfp(24), hbp(88)
9441 13:38:58.288173 vactive(1080), vsync(12), vfp(3), vbp(17)
9442 13:38:58.291482 anx7625_dsi_config: config dsi.
9443 13:38:58.298057 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9444 13:38:58.312639 anx7625_dsi_config: success to config DSI
9445 13:38:58.315986 anx7625_dp_start: MIPI phy setup OK.
9446 13:38:58.319208 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9447 13:38:58.322022 mtk_ddp_mode_set invalid vrefresh 60
9448 13:38:58.325934 main_disp_path_setup
9449 13:38:58.326038 ovl_layer_smi_id_en
9450 13:38:58.328705 ovl_layer_smi_id_en
9451 13:38:58.328816 ccorr_config
9452 13:38:58.328906 aal_config
9453 13:38:58.331918 gamma_config
9454 13:38:58.331990 postmask_config
9455 13:38:58.335383 dither_config
9456 13:38:58.338438 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9457 13:38:58.345194 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9458 13:38:58.349004 Root Device init finished in 551 msecs
9459 13:38:58.352053 CPU_CLUSTER: 0 init
9460 13:38:58.358592 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9461 13:38:58.364996 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9462 13:38:58.365120 APU_MBOX 0x190000b0 = 0x10001
9463 13:38:58.368684 APU_MBOX 0x190001b0 = 0x10001
9464 13:38:58.371649 APU_MBOX 0x190005b0 = 0x10001
9465 13:38:58.375137 APU_MBOX 0x190006b0 = 0x10001
9466 13:38:58.381798 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9467 13:38:58.391169 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9468 13:38:58.404155 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9469 13:38:58.409958 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9470 13:38:58.421827 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9471 13:38:58.431111 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9472 13:38:58.434407 CPU_CLUSTER: 0 init finished in 81 msecs
9473 13:38:58.437719 Devices initialized
9474 13:38:58.441029 Show all devs... After init.
9475 13:38:58.441152 Root Device: enabled 1
9476 13:38:58.444139 CPU_CLUSTER: 0: enabled 1
9477 13:38:58.447383 CPU: 00: enabled 1
9478 13:38:58.450640 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9479 13:38:58.454047 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9480 13:38:58.457290 ELOG: NV offset 0x57f000 size 0x1000
9481 13:38:58.464424 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9482 13:38:58.470902 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9483 13:38:58.474186 ELOG: Event(17) added with size 13 at 2024-05-28 13:38:58 UTC
9484 13:38:58.480450 out: cmd=0x121: 03 db 21 01 00 00 00 00
9485 13:38:58.483886 in-header: 03 27 00 00 2c 00 00 00
9486 13:38:58.494071 in-data: 15 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9487 13:38:58.500247 ELOG: Event(A1) added with size 10 at 2024-05-28 13:38:58 UTC
9488 13:38:58.507126 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9489 13:38:58.513742 ELOG: Event(A0) added with size 9 at 2024-05-28 13:38:58 UTC
9490 13:38:58.517018 elog_add_boot_reason: Logged dev mode boot
9491 13:38:58.523535 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9492 13:38:58.523677 Finalize devices...
9493 13:38:58.526803 Devices finalized
9494 13:38:58.530204 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9495 13:38:58.533403 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9496 13:38:58.536892 in-header: 03 07 00 00 08 00 00 00
9497 13:38:58.540239 in-data: aa e4 47 04 13 02 00 00
9498 13:38:58.542957 Chrome EC: UHEPI supported
9499 13:38:58.550111 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9500 13:38:58.553375 in-header: 03 a9 00 00 08 00 00 00
9501 13:38:58.556425 in-data: 84 60 60 08 00 00 00 00
9502 13:38:58.563068 ELOG: Event(91) added with size 10 at 2024-05-28 13:38:58 UTC
9503 13:38:58.566277 Chrome EC: clear events_b mask to 0x0000000020004000
9504 13:38:58.572541 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9505 13:38:58.576539 in-header: 03 fd 00 00 00 00 00 00
9506 13:38:58.579926 in-data:
9507 13:38:58.583184 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9508 13:38:58.586626 Writing coreboot table at 0xffe64000
9509 13:38:58.593389 0. 000000000010a000-0000000000113fff: RAMSTAGE
9510 13:38:58.596808 1. 0000000040000000-00000000400fffff: RAM
9511 13:38:58.600183 2. 0000000040100000-000000004032afff: RAMSTAGE
9512 13:38:58.603692 3. 000000004032b000-00000000545fffff: RAM
9513 13:38:58.606737 4. 0000000054600000-000000005465ffff: BL31
9514 13:38:58.609973 5. 0000000054660000-00000000ffe63fff: RAM
9515 13:38:58.616958 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9516 13:38:58.620064 7. 0000000100000000-000000023fffffff: RAM
9517 13:38:58.623157 Passing 5 GPIOs to payload:
9518 13:38:58.626525 NAME | PORT | POLARITY | VALUE
9519 13:38:58.633080 EC in RW | 0x000000aa | low | undefined
9520 13:38:58.636494 EC interrupt | 0x00000005 | low | undefined
9521 13:38:58.643219 TPM interrupt | 0x000000ab | high | undefined
9522 13:38:58.646408 SD card detect | 0x00000011 | high | undefined
9523 13:38:58.649839 speaker enable | 0x00000093 | high | undefined
9524 13:38:58.653045 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9525 13:38:58.656200 in-header: 03 f9 00 00 02 00 00 00
9526 13:38:58.660164 in-data: 02 00
9527 13:38:58.663329 ADC[4]: Raw value=901552 ID=7
9528 13:38:58.666526 ADC[3]: Raw value=213652 ID=1
9529 13:38:58.666622 RAM Code: 0x71
9530 13:38:58.669985 ADC[6]: Raw value=75036 ID=0
9531 13:38:58.673207 ADC[5]: Raw value=212912 ID=1
9532 13:38:58.673311 SKU Code: 0x1
9533 13:38:58.679319 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6da6
9534 13:38:58.679428 coreboot table: 964 bytes.
9535 13:38:58.682588 IMD ROOT 0. 0xfffff000 0x00001000
9536 13:38:58.685969 IMD SMALL 1. 0xffffe000 0x00001000
9537 13:38:58.689284 RO MCACHE 2. 0xffffc000 0x00001104
9538 13:38:58.692766 CONSOLE 3. 0xfff7c000 0x00080000
9539 13:38:58.696073 FMAP 4. 0xfff7b000 0x00000452
9540 13:38:58.699214 TIME STAMP 5. 0xfff7a000 0x00000910
9541 13:38:58.702951 VBOOT WORK 6. 0xfff66000 0x00014000
9542 13:38:58.705832 RAMOOPS 7. 0xffe66000 0x00100000
9543 13:38:58.709100 COREBOOT 8. 0xffe64000 0x00002000
9544 13:38:58.712342 IMD small region:
9545 13:38:58.715804 IMD ROOT 0. 0xffffec00 0x00000400
9546 13:38:58.718884 VPD 1. 0xffffeb80 0x0000006c
9547 13:38:58.722158 MMC STATUS 2. 0xffffeb60 0x00000004
9548 13:38:58.728991 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9549 13:38:58.735570 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9550 13:38:58.773891 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9551 13:38:58.777795 Checking segment from ROM address 0x40100000
9552 13:38:58.780964 Checking segment from ROM address 0x4010001c
9553 13:38:58.787650 Loading segment from ROM address 0x40100000
9554 13:38:58.787741 code (compression=0)
9555 13:38:58.797478 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9556 13:38:58.804083 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9557 13:38:58.804177 it's not compressed!
9558 13:38:58.810432 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9559 13:38:58.816694 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9560 13:38:58.834821 Loading segment from ROM address 0x4010001c
9561 13:38:58.834983 Entry Point 0x80000000
9562 13:38:58.837956 Loaded segments
9563 13:38:58.840908 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9564 13:38:58.847824 Jumping to boot code at 0x80000000(0xffe64000)
9565 13:38:58.854086 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9566 13:38:58.860770 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9567 13:38:58.869352 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9568 13:38:58.872628 Checking segment from ROM address 0x40100000
9569 13:38:58.875601 Checking segment from ROM address 0x4010001c
9570 13:38:58.881918 Loading segment from ROM address 0x40100000
9571 13:38:58.882011 code (compression=1)
9572 13:38:58.888642 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9573 13:38:58.898697 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9574 13:38:58.898807 using LZMA
9575 13:38:58.907279 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9576 13:38:58.914008 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9577 13:38:58.917363 Loading segment from ROM address 0x4010001c
9578 13:38:58.917442 Entry Point 0x54601000
9579 13:38:58.920692 Loaded segments
9580 13:38:58.923777 NOTICE: MT8192 bl31_setup
9581 13:38:58.931051 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9582 13:38:58.934272 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9583 13:38:58.937125 WARNING: region 0:
9584 13:38:58.940805 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9585 13:38:58.940900 WARNING: region 1:
9586 13:38:58.947488 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9587 13:38:58.950578 WARNING: region 2:
9588 13:38:58.953693 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9589 13:38:58.957194 WARNING: region 3:
9590 13:38:58.960824 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9591 13:38:58.963988 WARNING: region 4:
9592 13:38:58.970853 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9593 13:38:58.970963 WARNING: region 5:
9594 13:38:58.974025 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9595 13:38:58.977324 WARNING: region 6:
9596 13:38:58.980379 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9597 13:38:58.983408 WARNING: region 7:
9598 13:38:58.987095 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9599 13:38:58.993721 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9600 13:38:58.996964 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9601 13:38:59.003761 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9602 13:38:59.006499 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9603 13:38:59.009722 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9604 13:38:59.016562 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9605 13:38:59.019920 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9606 13:38:59.023137 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9607 13:38:59.029853 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9608 13:38:59.033164 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9609 13:38:59.039592 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9610 13:38:59.042856 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9611 13:38:59.046420 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9612 13:38:59.052776 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9613 13:38:59.056372 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9614 13:38:59.059572 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9615 13:38:59.066067 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9616 13:38:59.069806 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9617 13:38:59.075865 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9618 13:38:59.079087 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9619 13:38:59.082485 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9620 13:38:59.089382 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9621 13:38:59.092581 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9622 13:38:59.099019 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9623 13:38:59.102475 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9624 13:38:59.105778 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9625 13:38:59.112445 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9626 13:38:59.115533 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9627 13:38:59.122246 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9628 13:38:59.125488 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9629 13:38:59.132307 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9630 13:38:59.135487 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9631 13:38:59.138995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9632 13:38:59.142265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9633 13:38:59.148666 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9634 13:38:59.152435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9635 13:38:59.155833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9636 13:38:59.158763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9637 13:38:59.165390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9638 13:38:59.168752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9639 13:38:59.171875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9640 13:38:59.175391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9641 13:38:59.182415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9642 13:38:59.185152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9643 13:38:59.188853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9644 13:38:59.191890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9645 13:38:59.198206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9646 13:38:59.202115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9647 13:38:59.205128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9648 13:38:59.211459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9649 13:38:59.214666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9650 13:38:59.221234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9651 13:38:59.224832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9652 13:38:59.231157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9653 13:38:59.234636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9654 13:38:59.241152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9655 13:38:59.244543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9656 13:38:59.247691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9657 13:38:59.254180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9658 13:38:59.258082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9659 13:38:59.264033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9660 13:38:59.267560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9661 13:38:59.274206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9662 13:38:59.277329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9663 13:38:59.284082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9664 13:38:59.287354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9665 13:38:59.294071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9666 13:38:59.297109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9667 13:38:59.300522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9668 13:38:59.307063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9669 13:38:59.310122 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9670 13:38:59.317305 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9671 13:38:59.320116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9672 13:38:59.327182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9673 13:38:59.329987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9674 13:38:59.336505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9675 13:38:59.339876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9676 13:38:59.343352 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9677 13:38:59.349934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9678 13:38:59.353800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9679 13:38:59.359759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9680 13:38:59.363631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9681 13:38:59.370109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9682 13:38:59.373527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9683 13:38:59.380251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9684 13:38:59.383453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9685 13:38:59.386773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9686 13:38:59.393305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9687 13:38:59.396534 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9688 13:38:59.402806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9689 13:38:59.406261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9690 13:38:59.412935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9691 13:38:59.416044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9692 13:38:59.422804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9693 13:38:59.426342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9694 13:38:59.429212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9695 13:38:59.436286 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9696 13:38:59.439139 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9697 13:38:59.442649 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9698 13:38:59.445787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9699 13:38:59.452631 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9700 13:38:59.455908 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9701 13:38:59.462303 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9702 13:38:59.465747 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9703 13:38:59.468867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9704 13:38:59.475556 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9705 13:38:59.478876 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9706 13:38:59.485762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9707 13:38:59.489013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9708 13:38:59.492172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9709 13:38:59.498712 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9710 13:38:59.502093 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9711 13:38:59.508615 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9712 13:38:59.511947 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9713 13:38:59.518863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9714 13:38:59.522003 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9715 13:38:59.525299 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9716 13:38:59.528766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9717 13:38:59.535142 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9718 13:38:59.538418 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9719 13:38:59.541892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9720 13:38:59.548465 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9721 13:38:59.551397 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9722 13:38:59.555203 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9723 13:38:59.558756 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9724 13:38:59.565027 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9725 13:38:59.568183 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9726 13:38:59.574957 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9727 13:38:59.578066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9728 13:38:59.584695 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9729 13:38:59.587953 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9730 13:38:59.591314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9731 13:38:59.597900 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9732 13:38:59.601029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9733 13:38:59.607578 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9734 13:38:59.611073 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9735 13:38:59.614217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9736 13:38:59.621087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9737 13:38:59.624328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9738 13:38:59.627577 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9739 13:38:59.634758 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9740 13:38:59.637561 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9741 13:38:59.644367 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9742 13:38:59.647559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9743 13:38:59.650735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9744 13:38:59.657168 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9745 13:38:59.660771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9746 13:38:59.667238 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9747 13:38:59.670371 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9748 13:38:59.673981 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9749 13:38:59.680404 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9750 13:38:59.683904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9751 13:38:59.690328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9752 13:38:59.693752 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9753 13:38:59.697106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9754 13:38:59.703739 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9755 13:38:59.706981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9756 13:38:59.713598 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9757 13:38:59.716327 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9758 13:38:59.719672 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9759 13:38:59.726811 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9760 13:38:59.730175 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9761 13:38:59.736635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9762 13:38:59.739443 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9763 13:38:59.743365 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9764 13:38:59.749658 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9765 13:38:59.752880 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9766 13:38:59.759253 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9767 13:38:59.763016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9768 13:38:59.766176 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9769 13:38:59.772723 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9770 13:38:59.776247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9771 13:38:59.782769 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9772 13:38:59.785781 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9773 13:38:59.789030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9774 13:38:59.795764 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9775 13:38:59.799160 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9776 13:38:59.805600 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9777 13:38:59.808953 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9778 13:38:59.812337 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9779 13:38:59.818887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9780 13:38:59.822298 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9781 13:38:59.829112 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9782 13:38:59.832337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9783 13:38:59.835011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9784 13:38:59.841974 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9785 13:38:59.845298 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9786 13:38:59.851899 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9787 13:38:59.855135 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9788 13:38:59.861796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9789 13:38:59.864709 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9790 13:38:59.868493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9791 13:38:59.875430 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9792 13:38:59.878311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9793 13:38:59.885001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9794 13:38:59.888173 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9795 13:38:59.891784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9796 13:38:59.898456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9797 13:38:59.901667 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9798 13:38:59.908439 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9799 13:38:59.911650 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9800 13:38:59.918273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9801 13:38:59.921516 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9802 13:38:59.924786 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9803 13:38:59.931567 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9804 13:38:59.934714 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9805 13:38:59.941487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9806 13:38:59.944715 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9807 13:38:59.950793 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9808 13:38:59.953883 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9809 13:38:59.957112 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9810 13:38:59.963717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9811 13:38:59.967117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9812 13:38:59.973650 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9813 13:38:59.977325 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9814 13:38:59.983848 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9815 13:38:59.987266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9816 13:38:59.990167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9817 13:38:59.996947 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9818 13:39:00.000487 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9819 13:39:00.007039 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9820 13:39:00.010035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9821 13:39:00.017145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9822 13:39:00.020465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9823 13:39:00.023102 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9824 13:39:00.030238 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9825 13:39:00.033416 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9826 13:39:00.039976 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9827 13:39:00.043398 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9828 13:39:00.046119 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9829 13:39:00.052939 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9830 13:39:00.056546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9831 13:39:00.059707 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9832 13:39:00.062918 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9833 13:39:00.069464 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9834 13:39:00.072923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9835 13:39:00.076268 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9836 13:39:00.082768 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9837 13:39:00.086121 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9838 13:39:00.092252 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9839 13:39:00.096047 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9840 13:39:00.099228 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9841 13:39:00.105586 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9842 13:39:00.109396 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9843 13:39:00.112425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9844 13:39:00.119268 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9845 13:39:00.122123 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9846 13:39:00.128829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9847 13:39:00.132265 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9848 13:39:00.135470 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9849 13:39:00.142041 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9850 13:39:00.145441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9851 13:39:00.148785 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9852 13:39:00.155286 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9853 13:39:00.158412 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9854 13:39:00.161796 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9855 13:39:00.169005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9856 13:39:00.171656 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9857 13:39:00.178396 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9858 13:39:00.181735 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9859 13:39:00.184917 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9860 13:39:00.191683 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9861 13:39:00.195063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9862 13:39:00.198357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9863 13:39:00.204554 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9864 13:39:00.208303 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9865 13:39:00.214787 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9866 13:39:00.218175 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9867 13:39:00.221264 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9868 13:39:00.228143 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9869 13:39:00.231051 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9870 13:39:00.234752 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9871 13:39:00.237713 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9872 13:39:00.240778 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9873 13:39:00.247780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9874 13:39:00.251045 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9875 13:39:00.254468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9876 13:39:00.257815 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9877 13:39:00.264064 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9878 13:39:00.267636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9879 13:39:00.270792 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9880 13:39:00.277432 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9881 13:39:00.280760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9882 13:39:00.287328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9883 13:39:00.290734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9884 13:39:00.293829 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9885 13:39:00.300632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9886 13:39:00.303876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9887 13:39:00.310432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9888 13:39:00.313377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9889 13:39:00.316585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9890 13:39:00.323768 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9891 13:39:00.326961 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9892 13:39:00.333308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9893 13:39:00.336468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9894 13:39:00.343320 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9895 13:39:00.346618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9896 13:39:00.349906 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9897 13:39:00.356615 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9898 13:39:00.359730 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9899 13:39:00.366685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9900 13:39:00.369966 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9901 13:39:00.373329 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9902 13:39:00.380078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9903 13:39:00.383328 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9904 13:39:00.389967 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9905 13:39:00.392529 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9906 13:39:00.399240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9907 13:39:00.402636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9908 13:39:00.405915 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9909 13:39:00.412407 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9910 13:39:00.415764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9911 13:39:00.422535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9912 13:39:00.425962 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9913 13:39:00.429277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9914 13:39:00.435673 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9915 13:39:00.438831 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9916 13:39:00.445917 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9917 13:39:00.448912 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9918 13:39:00.455527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9919 13:39:00.459031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9920 13:39:00.462408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9921 13:39:00.468839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9922 13:39:00.471913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9923 13:39:00.478226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9924 13:39:00.482140 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9925 13:39:00.484848 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9926 13:39:00.491465 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9927 13:39:00.494901 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9928 13:39:00.501419 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9929 13:39:00.504696 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9930 13:39:00.511468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9931 13:39:00.514760 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9932 13:39:00.517907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9933 13:39:00.524818 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9934 13:39:00.528043 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9935 13:39:00.534607 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9936 13:39:00.538013 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9937 13:39:00.541107 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9938 13:39:00.547849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9939 13:39:00.551050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9940 13:39:00.557690 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9941 13:39:00.560857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9942 13:39:00.567531 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9943 13:39:00.570712 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9944 13:39:00.573956 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9945 13:39:00.580936 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9946 13:39:00.584033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9947 13:39:00.590657 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9948 13:39:00.593902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9949 13:39:00.597281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9950 13:39:00.603737 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9951 13:39:00.607251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9952 13:39:00.613880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9953 13:39:00.617169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9954 13:39:00.623670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9955 13:39:00.627290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9956 13:39:00.630463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9957 13:39:00.636858 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9958 13:39:00.640026 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9959 13:39:00.647181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9960 13:39:00.650302 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9961 13:39:00.657126 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9962 13:39:00.660301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9963 13:39:00.663419 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9964 13:39:00.670153 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9965 13:39:00.673272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9966 13:39:00.680263 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9967 13:39:00.683627 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9968 13:39:00.689986 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9969 13:39:00.693291 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9970 13:39:00.699853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9971 13:39:00.703067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9972 13:39:00.706213 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9973 13:39:00.712877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9974 13:39:00.716289 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9975 13:39:00.723138 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9976 13:39:00.726368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9977 13:39:00.732925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9978 13:39:00.735952 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9979 13:39:00.742430 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9980 13:39:00.745720 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9981 13:39:00.752265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9982 13:39:00.756082 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9983 13:39:00.759236 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9984 13:39:00.765976 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9985 13:39:00.768966 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9986 13:39:00.776119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9987 13:39:00.778878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9988 13:39:00.786055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9989 13:39:00.789091 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9990 13:39:00.792237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9991 13:39:00.799265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9992 13:39:00.802628 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9993 13:39:00.808659 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9994 13:39:00.812440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9995 13:39:00.818530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9996 13:39:00.821848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9997 13:39:00.828687 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9998 13:39:00.831813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9999 13:39:00.835224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10000 13:39:00.841613 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10001 13:39:00.844967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10002 13:39:00.851760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10003 13:39:00.855077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10004 13:39:00.858197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10005 13:39:00.865384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10006 13:39:00.868699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10007 13:39:00.875117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10008 13:39:00.878446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10009 13:39:00.884933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10010 13:39:00.888336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10011 13:39:00.894334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10012 13:39:00.898041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10013 13:39:00.904774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10014 13:39:00.908083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10015 13:39:00.914754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10016 13:39:00.918071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10017 13:39:00.924961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10018 13:39:00.927734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10019 13:39:00.934177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10020 13:39:00.938107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10021 13:39:00.944159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10022 13:39:00.947251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10023 13:39:00.953831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10024 13:39:00.957636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10025 13:39:00.963805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10026 13:39:00.967557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10027 13:39:00.973931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10028 13:39:00.977279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10029 13:39:00.983764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10030 13:39:00.987362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10031 13:39:00.993673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10032 13:39:00.997136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10033 13:39:01.003686 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10034 13:39:01.003772 INFO: [APUAPC] vio 0
10035 13:39:01.010499 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10036 13:39:01.014329 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10037 13:39:01.017609 INFO: [APUAPC] D0_APC_0: 0x400510
10038 13:39:01.020751 INFO: [APUAPC] D0_APC_1: 0x0
10039 13:39:01.024032 INFO: [APUAPC] D0_APC_2: 0x1540
10040 13:39:01.027500 INFO: [APUAPC] D0_APC_3: 0x0
10041 13:39:01.030878 INFO: [APUAPC] D1_APC_0: 0xffffffff
10042 13:39:01.033662 INFO: [APUAPC] D1_APC_1: 0xffffffff
10043 13:39:01.037627 INFO: [APUAPC] D1_APC_2: 0x3fffff
10044 13:39:01.040867 INFO: [APUAPC] D1_APC_3: 0x0
10045 13:39:01.044146 INFO: [APUAPC] D2_APC_0: 0xffffffff
10046 13:39:01.046993 INFO: [APUAPC] D2_APC_1: 0xffffffff
10047 13:39:01.050767 INFO: [APUAPC] D2_APC_2: 0x3fffff
10048 13:39:01.054111 INFO: [APUAPC] D2_APC_3: 0x0
10049 13:39:01.056823 INFO: [APUAPC] D3_APC_0: 0xffffffff
10050 13:39:01.060656 INFO: [APUAPC] D3_APC_1: 0xffffffff
10051 13:39:01.063914 INFO: [APUAPC] D3_APC_2: 0x3fffff
10052 13:39:01.067172 INFO: [APUAPC] D3_APC_3: 0x0
10053 13:39:01.070203 INFO: [APUAPC] D4_APC_0: 0xffffffff
10054 13:39:01.073666 INFO: [APUAPC] D4_APC_1: 0xffffffff
10055 13:39:01.076754 INFO: [APUAPC] D4_APC_2: 0x3fffff
10056 13:39:01.076870 INFO: [APUAPC] D4_APC_3: 0x0
10057 13:39:01.083673 INFO: [APUAPC] D5_APC_0: 0xffffffff
10058 13:39:01.087091 INFO: [APUAPC] D5_APC_1: 0xffffffff
10059 13:39:01.090355 INFO: [APUAPC] D5_APC_2: 0x3fffff
10060 13:39:01.090463 INFO: [APUAPC] D5_APC_3: 0x0
10061 13:39:01.093263 INFO: [APUAPC] D6_APC_0: 0xffffffff
10062 13:39:01.096928 INFO: [APUAPC] D6_APC_1: 0xffffffff
10063 13:39:01.100392 INFO: [APUAPC] D6_APC_2: 0x3fffff
10064 13:39:01.103519 INFO: [APUAPC] D6_APC_3: 0x0
10065 13:39:01.106918 INFO: [APUAPC] D7_APC_0: 0xffffffff
10066 13:39:01.110230 INFO: [APUAPC] D7_APC_1: 0xffffffff
10067 13:39:01.113750 INFO: [APUAPC] D7_APC_2: 0x3fffff
10068 13:39:01.116745 INFO: [APUAPC] D7_APC_3: 0x0
10069 13:39:01.119838 INFO: [APUAPC] D8_APC_0: 0xffffffff
10070 13:39:01.123682 INFO: [APUAPC] D8_APC_1: 0xffffffff
10071 13:39:01.126639 INFO: [APUAPC] D8_APC_2: 0x3fffff
10072 13:39:01.129889 INFO: [APUAPC] D8_APC_3: 0x0
10073 13:39:01.133283 INFO: [APUAPC] D9_APC_0: 0xffffffff
10074 13:39:01.136659 INFO: [APUAPC] D9_APC_1: 0xffffffff
10075 13:39:01.139815 INFO: [APUAPC] D9_APC_2: 0x3fffff
10076 13:39:01.142942 INFO: [APUAPC] D9_APC_3: 0x0
10077 13:39:01.146330 INFO: [APUAPC] D10_APC_0: 0xffffffff
10078 13:39:01.149559 INFO: [APUAPC] D10_APC_1: 0xffffffff
10079 13:39:01.152961 INFO: [APUAPC] D10_APC_2: 0x3fffff
10080 13:39:01.156060 INFO: [APUAPC] D10_APC_3: 0x0
10081 13:39:01.159995 INFO: [APUAPC] D11_APC_0: 0xffffffff
10082 13:39:01.163123 INFO: [APUAPC] D11_APC_1: 0xffffffff
10083 13:39:01.166380 INFO: [APUAPC] D11_APC_2: 0x3fffff
10084 13:39:01.169696 INFO: [APUAPC] D11_APC_3: 0x0
10085 13:39:01.172887 INFO: [APUAPC] D12_APC_0: 0xffffffff
10086 13:39:01.176270 INFO: [APUAPC] D12_APC_1: 0xffffffff
10087 13:39:01.179331 INFO: [APUAPC] D12_APC_2: 0x3fffff
10088 13:39:01.182852 INFO: [APUAPC] D12_APC_3: 0x0
10089 13:39:01.186225 INFO: [APUAPC] D13_APC_0: 0xffffffff
10090 13:39:01.189306 INFO: [APUAPC] D13_APC_1: 0xffffffff
10091 13:39:01.192687 INFO: [APUAPC] D13_APC_2: 0x3fffff
10092 13:39:01.196218 INFO: [APUAPC] D13_APC_3: 0x0
10093 13:39:01.199270 INFO: [APUAPC] D14_APC_0: 0xffffffff
10094 13:39:01.202629 INFO: [APUAPC] D14_APC_1: 0xffffffff
10095 13:39:01.205662 INFO: [APUAPC] D14_APC_2: 0x3fffff
10096 13:39:01.209210 INFO: [APUAPC] D14_APC_3: 0x0
10097 13:39:01.212485 INFO: [APUAPC] D15_APC_0: 0xffffffff
10098 13:39:01.215853 INFO: [APUAPC] D15_APC_1: 0xffffffff
10099 13:39:01.222303 INFO: [APUAPC] D15_APC_2: 0x3fffff
10100 13:39:01.222384 INFO: [APUAPC] D15_APC_3: 0x0
10101 13:39:01.225661 INFO: [APUAPC] APC_CON: 0x4
10102 13:39:01.228901 INFO: [NOCDAPC] D0_APC_0: 0x0
10103 13:39:01.232141 INFO: [NOCDAPC] D0_APC_1: 0x0
10104 13:39:01.235853 INFO: [NOCDAPC] D1_APC_0: 0x0
10105 13:39:01.238898 INFO: [NOCDAPC] D1_APC_1: 0xfff
10106 13:39:01.242254 INFO: [NOCDAPC] D2_APC_0: 0x0
10107 13:39:01.245328 INFO: [NOCDAPC] D2_APC_1: 0xfff
10108 13:39:01.248708 INFO: [NOCDAPC] D3_APC_0: 0x0
10109 13:39:01.248812 INFO: [NOCDAPC] D3_APC_1: 0xfff
10110 13:39:01.251985 INFO: [NOCDAPC] D4_APC_0: 0x0
10111 13:39:01.255343 INFO: [NOCDAPC] D4_APC_1: 0xfff
10112 13:39:01.259009 INFO: [NOCDAPC] D5_APC_0: 0x0
10113 13:39:01.261810 INFO: [NOCDAPC] D5_APC_1: 0xfff
10114 13:39:01.265152 INFO: [NOCDAPC] D6_APC_0: 0x0
10115 13:39:01.268314 INFO: [NOCDAPC] D6_APC_1: 0xfff
10116 13:39:01.271614 INFO: [NOCDAPC] D7_APC_0: 0x0
10117 13:39:01.274912 INFO: [NOCDAPC] D7_APC_1: 0xfff
10118 13:39:01.278872 INFO: [NOCDAPC] D8_APC_0: 0x0
10119 13:39:01.282005 INFO: [NOCDAPC] D8_APC_1: 0xfff
10120 13:39:01.285196 INFO: [NOCDAPC] D9_APC_0: 0x0
10121 13:39:01.285299 INFO: [NOCDAPC] D9_APC_1: 0xfff
10122 13:39:01.288350 INFO: [NOCDAPC] D10_APC_0: 0x0
10123 13:39:01.291601 INFO: [NOCDAPC] D10_APC_1: 0xfff
10124 13:39:01.295238 INFO: [NOCDAPC] D11_APC_0: 0x0
10125 13:39:01.298267 INFO: [NOCDAPC] D11_APC_1: 0xfff
10126 13:39:01.301422 INFO: [NOCDAPC] D12_APC_0: 0x0
10127 13:39:01.305014 INFO: [NOCDAPC] D12_APC_1: 0xfff
10128 13:39:01.308393 INFO: [NOCDAPC] D13_APC_0: 0x0
10129 13:39:01.311657 INFO: [NOCDAPC] D13_APC_1: 0xfff
10130 13:39:01.314831 INFO: [NOCDAPC] D14_APC_0: 0x0
10131 13:39:01.317973 INFO: [NOCDAPC] D14_APC_1: 0xfff
10132 13:39:01.321659 INFO: [NOCDAPC] D15_APC_0: 0x0
10133 13:39:01.324653 INFO: [NOCDAPC] D15_APC_1: 0xfff
10134 13:39:01.327653 INFO: [NOCDAPC] APC_CON: 0x4
10135 13:39:01.331259 INFO: [APUAPC] set_apusys_apc done
10136 13:39:01.334777 INFO: [DEVAPC] devapc_init done
10137 13:39:01.337808 INFO: GICv3 without legacy support detected.
10138 13:39:01.340890 INFO: ARM GICv3 driver initialized in EL3
10139 13:39:01.344586 INFO: Maximum SPI INTID supported: 639
10140 13:39:01.347832 INFO: BL31: Initializing runtime services
10141 13:39:01.354611 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10142 13:39:01.357809 INFO: SPM: enable CPC mode
10143 13:39:01.364306 INFO: mcdi ready for mcusys-off-idle and system suspend
10144 13:39:01.367444 INFO: BL31: Preparing for EL3 exit to normal world
10145 13:39:01.370848 INFO: Entry point address = 0x80000000
10146 13:39:01.373999 INFO: SPSR = 0x8
10147 13:39:01.378753
10148 13:39:01.378864
10149 13:39:01.378957
10150 13:39:01.382211 Starting depthcharge on Spherion...
10151 13:39:01.382309
10152 13:39:01.382396 Wipe memory regions:
10153 13:39:01.382482
10154 13:39:01.383218 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10155 13:39:01.383345 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10156 13:39:01.383458 Setting prompt string to ['asurada:']
10157 13:39:01.383571 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10158 13:39:01.385468 [0x00000040000000, 0x00000054600000)
10159 13:39:01.507412
10160 13:39:01.507561 [0x00000054660000, 0x00000080000000)
10161 13:39:01.768228
10162 13:39:01.768374 [0x000000821a7280, 0x000000ffe64000)
10163 13:39:02.513288
10164 13:39:02.513428 [0x00000100000000, 0x00000240000000)
10165 13:39:04.403003
10166 13:39:04.406509 Initializing XHCI USB controller at 0x11200000.
10167 13:39:05.444452
10168 13:39:05.447880 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10169 13:39:05.447969
10170 13:39:05.448035
10171 13:39:05.448321 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10173 13:39:05.548692 asurada: tftpboot 192.168.201.1 14063000/tftp-deploy-9gkb3zig/kernel/image.itb 14063000/tftp-deploy-9gkb3zig/kernel/cmdline
10174 13:39:05.548851 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 13:39:05.548964 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10176 13:39:05.552709 tftpboot 192.168.201.1 14063000/tftp-deploy-9gkb3zig/kernel/image.ittp-deploy-9gkb3zig/kernel/cmdline
10177 13:39:05.552793
10178 13:39:05.552887 Waiting for link
10179 13:39:05.710917
10180 13:39:05.711054 R8152: Initializing
10181 13:39:05.711121
10182 13:39:05.714098 Version 6 (ocp_data = 5c30)
10183 13:39:05.714187
10184 13:39:05.717853 R8152: Done initializing
10185 13:39:05.717933
10186 13:39:05.718029 Adding net device
10187 13:39:07.623715
10188 13:39:07.623873 done.
10189 13:39:07.623965
10190 13:39:07.624052 MAC: 00:e0:4c:68:02:81
10191 13:39:07.624137
10192 13:39:07.626925 Sending DHCP discover... done.
10193 13:39:07.627011
10194 13:39:11.087456 Waiting for reply... done.
10195 13:39:11.087593
10196 13:39:11.087689 Sending DHCP request... done.
10197 13:39:11.090713
10198 13:39:11.094016 Waiting for reply... done.
10199 13:39:11.094118
10200 13:39:11.094232 My ip is 192.168.201.14
10201 13:39:11.094317
10202 13:39:11.097387 The DHCP server ip is 192.168.201.1
10203 13:39:11.097468
10204 13:39:11.104038 TFTP server IP predefined by user: 192.168.201.1
10205 13:39:11.104120
10206 13:39:11.110141 Bootfile predefined by user: 14063000/tftp-deploy-9gkb3zig/kernel/image.itb
10207 13:39:11.110285
10208 13:39:11.113954 Sending tftp read request... done.
10209 13:39:11.114060
10210 13:39:11.117716 Waiting for the transfer...
10211 13:39:11.117847
10212 13:39:11.688035 00000000 ################################################################
10213 13:39:11.688171
10214 13:39:12.243458 00080000 ################################################################
10215 13:39:12.243615
10216 13:39:12.820660 00100000 ################################################################
10217 13:39:12.820791
10218 13:39:13.391941 00180000 ################################################################
10219 13:39:13.392120
10220 13:39:13.956633 00200000 ################################################################
10221 13:39:13.956771
10222 13:39:14.513272 00280000 ################################################################
10223 13:39:14.513404
10224 13:39:15.068752 00300000 ################################################################
10225 13:39:15.068890
10226 13:39:15.611338 00380000 ################################################################
10227 13:39:15.611487
10228 13:39:16.157496 00400000 ################################################################
10229 13:39:16.157644
10230 13:39:16.773672 00480000 ################################################################
10231 13:39:16.773804
10232 13:39:17.315688 00500000 ################################################################
10233 13:39:17.315848
10234 13:39:17.863723 00580000 ################################################################
10235 13:39:17.863869
10236 13:39:18.404561 00600000 ################################################################
10237 13:39:18.404731
10238 13:39:18.953777 00680000 ################################################################
10239 13:39:18.953930
10240 13:39:19.479812 00700000 ################################################################
10241 13:39:19.479972
10242 13:39:20.022717 00780000 ################################################################
10243 13:39:20.022853
10244 13:39:20.569682 00800000 ################################################################
10245 13:39:20.569821
10246 13:39:21.131200 00880000 ################################################################
10247 13:39:21.131341
10248 13:39:21.682437 00900000 ################################################################
10249 13:39:21.682581
10250 13:39:22.261357 00980000 ################################################################
10251 13:39:22.261514
10252 13:39:22.820404 00a00000 ################################################################
10253 13:39:22.820546
10254 13:39:23.368536 00a80000 ################################################################
10255 13:39:23.368708
10256 13:39:23.916261 00b00000 ################################################################
10257 13:39:23.916407
10258 13:39:24.475585 00b80000 ################################################################
10259 13:39:24.475769
10260 13:39:25.015301 00c00000 ################################################################
10261 13:39:25.015432
10262 13:39:25.557742 00c80000 ################################################################
10263 13:39:25.557882
10264 13:39:26.098720 00d00000 ################################################################
10265 13:39:26.098878
10266 13:39:26.638249 00d80000 ################################################################
10267 13:39:26.638401
10268 13:39:27.171739 00e00000 ################################################################
10269 13:39:27.171881
10270 13:39:27.711640 00e80000 ################################################################
10271 13:39:27.711769
10272 13:39:28.255736 00f00000 ################################################################
10273 13:39:28.255868
10274 13:39:28.816668 00f80000 ################################################################
10275 13:39:28.816797
10276 13:39:29.380737 01000000 ################################################################
10277 13:39:29.380899
10278 13:39:29.921613 01080000 ################################################################
10279 13:39:29.921750
10280 13:39:30.454347 01100000 ################################################################
10281 13:39:30.454481
10282 13:39:31.009136 01180000 ################################################################
10283 13:39:31.009300
10284 13:39:31.554033 01200000 ################################################################
10285 13:39:31.554206
10286 13:39:32.094440 01280000 ################################################################
10287 13:39:32.094571
10288 13:39:32.652527 01300000 ################################################################
10289 13:39:32.652679
10290 13:39:33.194075 01380000 ################################################################
10291 13:39:33.194245
10292 13:39:33.727580 01400000 ################################################################
10293 13:39:33.727744
10294 13:39:34.255313 01480000 ################################################################
10295 13:39:34.255501
10296 13:39:34.799274 01500000 ################################################################
10297 13:39:34.799438
10298 13:39:35.345357 01580000 ################################################################
10299 13:39:35.345501
10300 13:39:35.903944 01600000 ################################################################
10301 13:39:35.904141
10302 13:39:36.450619 01680000 ################################################################
10303 13:39:36.450796
10304 13:39:37.003081 01700000 ################################################################
10305 13:39:37.003227
10306 13:39:37.535517 01780000 ################################################################
10307 13:39:37.535684
10308 13:39:38.077099 01800000 ################################################################
10309 13:39:38.077302
10310 13:39:38.639947 01880000 ################################################################
10311 13:39:38.640113
10312 13:39:39.213694 01900000 ################################################################
10313 13:39:39.213861
10314 13:39:39.772768 01980000 ################################################################
10315 13:39:39.772916
10316 13:39:40.332634 01a00000 ################################################################
10317 13:39:40.332794
10318 13:39:40.876491 01a80000 ################################################################
10319 13:39:40.876632
10320 13:39:41.441133 01b00000 ################################################################
10321 13:39:41.441264
10322 13:39:41.986861 01b80000 ################################################################
10323 13:39:41.986994
10324 13:39:42.527687 01c00000 ################################################################
10325 13:39:42.527856
10326 13:39:43.060232 01c80000 ################################################################
10327 13:39:43.060366
10328 13:39:43.592005 01d00000 ################################################################
10329 13:39:43.592139
10330 13:39:44.118900 01d80000 ################################################################
10331 13:39:44.119054
10332 13:39:44.512281 01e00000 ################################################ done.
10333 13:39:44.512422
10334 13:39:44.515192 The bootfile was 31843550 bytes long.
10335 13:39:44.515274
10336 13:39:44.518642 Sending tftp read request... done.
10337 13:39:44.518752
10338 13:39:44.521871 Waiting for the transfer...
10339 13:39:44.521983
10340 13:39:44.522078 00000000 # done.
10341 13:39:44.522194
10342 13:39:44.531786 Command line loaded dynamically from TFTP file: 14063000/tftp-deploy-9gkb3zig/kernel/cmdline
10343 13:39:44.531938
10344 13:39:44.551831 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10345 13:39:44.551993
10346 13:39:44.555164 Loading FIT.
10347 13:39:44.555251
10348 13:39:44.558268 Image ramdisk-1 has 18732953 bytes.
10349 13:39:44.558346
10350 13:39:44.561455 Image fdt-1 has 47258 bytes.
10351 13:39:44.561561
10352 13:39:44.561659 Image kernel-1 has 13061303 bytes.
10353 13:39:44.564645
10354 13:39:44.571154 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10355 13:39:44.571262
10356 13:39:44.591033 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10357 13:39:44.591173
10358 13:39:44.594090 Choosing best match conf-1 for compat google,spherion-rev2.
10359 13:39:44.598645
10360 13:39:44.602986 Connected to device vid:did:rid of 1ae0:0028:00
10361 13:39:44.610181
10362 13:39:44.613461 tpm_get_response: command 0x17b, return code 0x0
10363 13:39:44.613586
10364 13:39:44.616678 ec_init: CrosEC protocol v3 supported (256, 248)
10365 13:39:44.620985
10366 13:39:44.624180 tpm_cleanup: add release locality here.
10367 13:39:44.624303
10368 13:39:44.624375 Shutting down all USB controllers.
10369 13:39:44.627269
10370 13:39:44.627368 Removing current net device
10371 13:39:44.627435
10372 13:39:44.634546 Exiting depthcharge with code 4 at timestamp: 72722414
10373 13:39:44.634675
10374 13:39:44.638062 LZMA decompressing kernel-1 to 0x821a6718
10375 13:39:44.638153
10376 13:39:44.640978 LZMA decompressing kernel-1 to 0x40000000
10377 13:39:46.251721
10378 13:39:46.251876 jumping to kernel
10379 13:39:46.252401 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10380 13:39:46.252502 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10381 13:39:46.252580 Setting prompt string to ['Linux version [0-9]']
10382 13:39:46.252650 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10383 13:39:46.252747 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10384 13:39:46.333771
10385 13:39:46.336858 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10386 13:39:46.340438 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10387 13:39:46.340546 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10388 13:39:46.340618 Setting prompt string to []
10389 13:39:46.340692 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10390 13:39:46.340763 Using line separator: #'\n'#
10391 13:39:46.340820 No login prompt set.
10392 13:39:46.340896 Parsing kernel messages
10393 13:39:46.340951 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10394 13:39:46.341053 [login-action] Waiting for messages, (timeout 00:03:41)
10395 13:39:46.341120 Waiting using forced prompt support (timeout 00:01:51)
10396 13:39:46.359933 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10397 13:39:46.363109 [ 0.000000] random: crng init done
10398 13:39:46.369724 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10399 13:39:46.372998 [ 0.000000] efi: UEFI not found.
10400 13:39:46.379903 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10401 13:39:46.389771 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10402 13:39:46.399552 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10403 13:39:46.405903 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10404 13:39:46.412657 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10405 13:39:46.419206 [ 0.000000] printk: bootconsole [mtk8250] enabled
10406 13:39:46.425550 [ 0.000000] NUMA: No NUMA configuration found
10407 13:39:46.432196 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10408 13:39:46.438666 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10409 13:39:46.438810 [ 0.000000] Zone ranges:
10410 13:39:46.445018 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10411 13:39:46.448796 [ 0.000000] DMA32 empty
10412 13:39:46.455336 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10413 13:39:46.458361 [ 0.000000] Movable zone start for each node
10414 13:39:46.461442 [ 0.000000] Early memory node ranges
10415 13:39:46.468716 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10416 13:39:46.475354 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10417 13:39:46.481787 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10418 13:39:46.487812 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10419 13:39:46.494921 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10420 13:39:46.500813 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10421 13:39:46.558113 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10422 13:39:46.564981 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10423 13:39:46.571472 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10424 13:39:46.574637 [ 0.000000] psci: probing for conduit method from DT.
10425 13:39:46.581168 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10426 13:39:46.584372 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10427 13:39:46.591394 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10428 13:39:46.594521 [ 0.000000] psci: SMC Calling Convention v1.2
10429 13:39:46.600926 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10430 13:39:46.604482 [ 0.000000] Detected VIPT I-cache on CPU0
10431 13:39:46.610761 [ 0.000000] CPU features: detected: GIC system register CPU interface
10432 13:39:46.617674 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10433 13:39:46.624198 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10434 13:39:46.630903 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10435 13:39:46.640947 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10436 13:39:46.647466 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10437 13:39:46.650567 [ 0.000000] alternatives: applying boot alternatives
10438 13:39:46.657595 [ 0.000000] Fallback order for Node 0: 0
10439 13:39:46.664161 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10440 13:39:46.667247 [ 0.000000] Policy zone: Normal
10441 13:39:46.690379 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10442 13:39:46.700447 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10443 13:39:46.710704 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10444 13:39:46.721224 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10445 13:39:46.727548 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10446 13:39:46.730980 <6>[ 0.000000] software IO TLB: area num 8.
10447 13:39:46.787419 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10448 13:39:46.936745 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10449 13:39:46.943222 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10450 13:39:46.949665 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10451 13:39:46.953095 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10452 13:39:46.959660 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10453 13:39:46.966476 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10454 13:39:46.969103 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10455 13:39:46.979624 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10456 13:39:46.985699 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10457 13:39:46.992700 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10458 13:39:46.999320 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10459 13:39:47.002554 <6>[ 0.000000] GICv3: 608 SPIs implemented
10460 13:39:47.005869 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10461 13:39:47.012358 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10462 13:39:47.015785 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10463 13:39:47.022077 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10464 13:39:47.035614 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10465 13:39:47.048625 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10466 13:39:47.055306 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10467 13:39:47.063072 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10468 13:39:47.076070 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10469 13:39:47.083002 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10470 13:39:47.089517 <6>[ 0.009177] Console: colour dummy device 80x25
10471 13:39:47.099342 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10472 13:39:47.105954 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10473 13:39:47.109265 <6>[ 0.029218] LSM: Security Framework initializing
10474 13:39:47.116247 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10475 13:39:47.125619 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10476 13:39:47.135742 <6>[ 0.051467] cblist_init_generic: Setting adjustable number of callback queues.
10477 13:39:47.142039 <6>[ 0.058911] cblist_init_generic: Setting shift to 3 and lim to 1.
10478 13:39:47.148825 <6>[ 0.065251] cblist_init_generic: Setting adjustable number of callback queues.
10479 13:39:47.155393 <6>[ 0.072678] cblist_init_generic: Setting shift to 3 and lim to 1.
10480 13:39:47.158672 <6>[ 0.079119] rcu: Hierarchical SRCU implementation.
10481 13:39:47.165406 <6>[ 0.084135] rcu: Max phase no-delay instances is 1000.
10482 13:39:47.171817 <6>[ 0.091165] EFI services will not be available.
10483 13:39:47.175210 <6>[ 0.096124] smp: Bringing up secondary CPUs ...
10484 13:39:47.184121 <6>[ 0.101175] Detected VIPT I-cache on CPU1
10485 13:39:47.190542 <6>[ 0.101246] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10486 13:39:47.197228 <6>[ 0.101275] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10487 13:39:47.200478 <6>[ 0.101620] Detected VIPT I-cache on CPU2
10488 13:39:47.210289 <6>[ 0.101672] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10489 13:39:47.216694 <6>[ 0.101690] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10490 13:39:47.220041 <6>[ 0.101949] Detected VIPT I-cache on CPU3
10491 13:39:47.227106 <6>[ 0.101995] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10492 13:39:47.233642 <6>[ 0.102009] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10493 13:39:47.236958 <6>[ 0.102311] CPU features: detected: Spectre-v4
10494 13:39:47.243013 <6>[ 0.102318] CPU features: detected: Spectre-BHB
10495 13:39:47.246749 <6>[ 0.102323] Detected PIPT I-cache on CPU4
10496 13:39:47.253278 <6>[ 0.102381] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10497 13:39:47.259467 <6>[ 0.102397] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10498 13:39:47.266497 <6>[ 0.102692] Detected PIPT I-cache on CPU5
10499 13:39:47.273149 <6>[ 0.102755] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10500 13:39:47.279788 <6>[ 0.102771] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10501 13:39:47.282902 <6>[ 0.103052] Detected PIPT I-cache on CPU6
10502 13:39:47.289255 <6>[ 0.103118] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10503 13:39:47.299686 <6>[ 0.103134] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10504 13:39:47.302350 <6>[ 0.103432] Detected PIPT I-cache on CPU7
10505 13:39:47.309164 <6>[ 0.103497] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10506 13:39:47.315765 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10507 13:39:47.318871 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10508 13:39:47.325868 <6>[ 0.244970] SMP: Total of 8 processors activated.
10509 13:39:47.332021 <6>[ 0.249891] CPU features: detected: 32-bit EL0 Support
10510 13:39:47.338982 <6>[ 0.255253] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10511 13:39:47.345618 <6>[ 0.264053] CPU features: detected: Common not Private translations
10512 13:39:47.352200 <6>[ 0.270529] CPU features: detected: CRC32 instructions
10513 13:39:47.358541 <6>[ 0.275880] CPU features: detected: RCpc load-acquire (LDAPR)
10514 13:39:47.361812 <6>[ 0.281878] CPU features: detected: LSE atomic instructions
10515 13:39:47.368349 <6>[ 0.287659] CPU features: detected: Privileged Access Never
10516 13:39:47.374731 <6>[ 0.293439] CPU features: detected: RAS Extension Support
10517 13:39:47.381928 <6>[ 0.299047] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10518 13:39:47.384605 <6>[ 0.306268] CPU: All CPU(s) started at EL2
10519 13:39:47.391756 <6>[ 0.310585] alternatives: applying system-wide alternatives
10520 13:39:47.401589 <6>[ 0.321439] devtmpfs: initialized
10521 13:39:47.417754 <6>[ 0.330508] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10522 13:39:47.423699 <6>[ 0.340471] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10523 13:39:47.430871 <6>[ 0.348639] pinctrl core: initialized pinctrl subsystem
10524 13:39:47.434033 <6>[ 0.355321] DMI not present or invalid.
10525 13:39:47.440557 <6>[ 0.359734] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10526 13:39:47.450584 <6>[ 0.366602] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10527 13:39:47.456890 <6>[ 0.374188] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10528 13:39:47.466625 <6>[ 0.382416] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10529 13:39:47.470467 <6>[ 0.390661] audit: initializing netlink subsys (disabled)
10530 13:39:47.480563 <5>[ 0.396356] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10531 13:39:47.486345 <6>[ 0.397064] thermal_sys: Registered thermal governor 'step_wise'
10532 13:39:47.493351 <6>[ 0.404323] thermal_sys: Registered thermal governor 'power_allocator'
10533 13:39:47.496502 <6>[ 0.410575] cpuidle: using governor menu
10534 13:39:47.503523 <6>[ 0.421537] NET: Registered PF_QIPCRTR protocol family
10535 13:39:47.510062 <6>[ 0.427023] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10536 13:39:47.516582 <6>[ 0.434127] ASID allocator initialised with 32768 entries
10537 13:39:47.519911 <6>[ 0.440719] Serial: AMBA PL011 UART driver
10538 13:39:47.529643 <4>[ 0.449580] Trying to register duplicate clock ID: 134
10539 13:39:47.589844 <6>[ 0.512894] KASLR enabled
10540 13:39:47.604150 <6>[ 0.520721] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10541 13:39:47.611348 <6>[ 0.527736] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10542 13:39:47.617875 <6>[ 0.534226] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10543 13:39:47.624063 <6>[ 0.541231] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10544 13:39:47.630636 <6>[ 0.547720] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10545 13:39:47.637668 <6>[ 0.554721] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10546 13:39:47.643706 <6>[ 0.561209] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10547 13:39:47.650331 <6>[ 0.568212] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10548 13:39:47.653826 <6>[ 0.575748] ACPI: Interpreter disabled.
10549 13:39:47.662183 <6>[ 0.582203] iommu: Default domain type: Translated
10550 13:39:47.668993 <6>[ 0.587311] iommu: DMA domain TLB invalidation policy: strict mode
10551 13:39:47.672490 <5>[ 0.593975] SCSI subsystem initialized
10552 13:39:47.679339 <6>[ 0.598138] usbcore: registered new interface driver usbfs
10553 13:39:47.685561 <6>[ 0.603869] usbcore: registered new interface driver hub
10554 13:39:47.688983 <6>[ 0.609424] usbcore: registered new device driver usb
10555 13:39:47.695738 <6>[ 0.615528] pps_core: LinuxPPS API ver. 1 registered
10556 13:39:47.705812 <6>[ 0.620723] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10557 13:39:47.709183 <6>[ 0.630066] PTP clock support registered
10558 13:39:47.712523 <6>[ 0.634311] EDAC MC: Ver: 3.0.0
10559 13:39:47.719600 <6>[ 0.639471] FPGA manager framework
10560 13:39:47.726056 <6>[ 0.643158] Advanced Linux Sound Architecture Driver Initialized.
10561 13:39:47.729772 <6>[ 0.649942] vgaarb: loaded
10562 13:39:47.736351 <6>[ 0.653112] clocksource: Switched to clocksource arch_sys_counter
10563 13:39:47.739499 <5>[ 0.659551] VFS: Disk quotas dquot_6.6.0
10564 13:39:47.746055 <6>[ 0.663733] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10565 13:39:47.749320 <6>[ 0.670925] pnp: PnP ACPI: disabled
10566 13:39:47.757924 <6>[ 0.677683] NET: Registered PF_INET protocol family
10567 13:39:47.767908 <6>[ 0.683279] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10568 13:39:47.779011 <6>[ 0.695594] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10569 13:39:47.789030 <6>[ 0.704405] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10570 13:39:47.795744 <6>[ 0.712378] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10571 13:39:47.805589 <6>[ 0.721076] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10572 13:39:47.811835 <6>[ 0.730818] TCP: Hash tables configured (established 65536 bind 65536)
10573 13:39:47.818423 <6>[ 0.737682] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10574 13:39:47.828274 <6>[ 0.744882] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10575 13:39:47.835207 <6>[ 0.752592] NET: Registered PF_UNIX/PF_LOCAL protocol family
10576 13:39:47.841311 <6>[ 0.758770] RPC: Registered named UNIX socket transport module.
10577 13:39:47.845034 <6>[ 0.764921] RPC: Registered udp transport module.
10578 13:39:47.851890 <6>[ 0.769852] RPC: Registered tcp transport module.
10579 13:39:47.858484 <6>[ 0.774784] RPC: Registered tcp NFSv4.1 backchannel transport module.
10580 13:39:47.861191 <6>[ 0.781454] PCI: CLS 0 bytes, default 64
10581 13:39:47.865008 <6>[ 0.785824] Unpacking initramfs...
10582 13:39:47.881317 <6>[ 0.797675] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10583 13:39:47.891159 <6>[ 0.806347] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10584 13:39:47.894346 <6>[ 0.815161] kvm [1]: IPA Size Limit: 40 bits
10585 13:39:47.901124 <6>[ 0.819690] kvm [1]: GICv3: no GICV resource entry
10586 13:39:47.904261 <6>[ 0.824712] kvm [1]: disabling GICv2 emulation
10587 13:39:47.910876 <6>[ 0.829398] kvm [1]: GIC system register CPU interface enabled
10588 13:39:47.917301 <6>[ 0.837161] kvm [1]: vgic interrupt IRQ18
10589 13:39:47.920749 <6>[ 0.841535] kvm [1]: VHE mode initialized successfully
10590 13:39:47.928520 <5>[ 0.847969] Initialise system trusted keyrings
10591 13:39:47.934558 <6>[ 0.852753] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10592 13:39:47.943248 <6>[ 0.862836] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10593 13:39:47.949814 <5>[ 0.869235] NFS: Registering the id_resolver key type
10594 13:39:47.952792 <5>[ 0.874547] Key type id_resolver registered
10595 13:39:47.959395 <5>[ 0.878960] Key type id_legacy registered
10596 13:39:47.965876 <6>[ 0.883237] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10597 13:39:47.972719 <6>[ 0.890160] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10598 13:39:47.979483 <6>[ 0.897874] 9p: Installing v9fs 9p2000 file system support
10599 13:39:48.015468 <5>[ 0.935305] Key type asymmetric registered
10600 13:39:48.018752 <5>[ 0.939635] Asymmetric key parser 'x509' registered
10601 13:39:48.028574 <6>[ 0.944772] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10602 13:39:48.032091 <6>[ 0.952388] io scheduler mq-deadline registered
10603 13:39:48.035199 <6>[ 0.957164] io scheduler kyber registered
10604 13:39:48.054473 <6>[ 0.974126] EINJ: ACPI disabled.
10605 13:39:48.087690 <4>[ 1.000939] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10606 13:39:48.097714 <4>[ 1.011580] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 13:39:48.113038 <6>[ 1.032733] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10608 13:39:48.120843 <6>[ 1.040842] printk: console [ttyS0] disabled
10609 13:39:48.149270 <6>[ 1.065478] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10610 13:39:48.155820 <6>[ 1.074950] printk: console [ttyS0] enabled
10611 13:39:48.159027 <6>[ 1.074950] printk: console [ttyS0] enabled
10612 13:39:48.165630 <6>[ 1.083845] printk: bootconsole [mtk8250] disabled
10613 13:39:48.168761 <6>[ 1.083845] printk: bootconsole [mtk8250] disabled
10614 13:39:48.175716 <6>[ 1.095103] SuperH (H)SCI(F) driver initialized
10615 13:39:48.178581 <6>[ 1.100389] msm_serial: driver initialized
10616 13:39:48.192928 <6>[ 1.109428] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10617 13:39:48.203114 <6>[ 1.117975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10618 13:39:48.209529 <6>[ 1.126522] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10619 13:39:48.219895 <6>[ 1.135149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10620 13:39:48.229075 <6>[ 1.143856] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10621 13:39:48.235596 <6>[ 1.152570] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10622 13:39:48.245555 <6>[ 1.161114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10623 13:39:48.252555 <6>[ 1.169920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10624 13:39:48.261810 <6>[ 1.178467] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10625 13:39:48.274923 <6>[ 1.194317] loop: module loaded
10626 13:39:48.280831 <6>[ 1.200274] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10627 13:39:48.303677 <4>[ 1.223687] mtk-pmic-keys: Failed to locate of_node [id: -1]
10628 13:39:48.311004 <6>[ 1.230596] megasas: 07.719.03.00-rc1
10629 13:39:48.320466 <6>[ 1.240102] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10630 13:39:48.332537 <6>[ 1.252502] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10631 13:39:48.349455 <6>[ 1.269181] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10632 13:39:48.409718 <6>[ 1.322997] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10633 13:39:48.657289 <6>[ 1.577314] Freeing initrd memory: 18288K
10634 13:39:48.669099 <6>[ 1.589070] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10635 13:39:48.680054 <6>[ 1.599985] tun: Universal TUN/TAP device driver, 1.6
10636 13:39:48.683371 <6>[ 1.606048] thunder_xcv, ver 1.0
10637 13:39:48.686552 <6>[ 1.609559] thunder_bgx, ver 1.0
10638 13:39:48.689850 <6>[ 1.613050] nicpf, ver 1.0
10639 13:39:48.700630 <6>[ 1.617063] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10640 13:39:48.704000 <6>[ 1.624538] hns3: Copyright (c) 2017 Huawei Corporation.
10641 13:39:48.710438 <6>[ 1.630128] hclge is initializing
10642 13:39:48.713586 <6>[ 1.633708] e1000: Intel(R) PRO/1000 Network Driver
10643 13:39:48.720107 <6>[ 1.638837] e1000: Copyright (c) 1999-2006 Intel Corporation.
10644 13:39:48.726825 <6>[ 1.644849] e1000e: Intel(R) PRO/1000 Network Driver
10645 13:39:48.729978 <6>[ 1.650064] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10646 13:39:48.736365 <6>[ 1.656249] igb: Intel(R) Gigabit Ethernet Network Driver
10647 13:39:48.743396 <6>[ 1.661899] igb: Copyright (c) 2007-2014 Intel Corporation.
10648 13:39:48.749683 <6>[ 1.667735] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10649 13:39:48.756453 <6>[ 1.674253] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10650 13:39:48.759762 <6>[ 1.680721] sky2: driver version 1.30
10651 13:39:48.766621 <6>[ 1.685656] usbcore: registered new device driver r8152-cfgselector
10652 13:39:48.772893 <6>[ 1.692190] usbcore: registered new interface driver r8152
10653 13:39:48.779465 <6>[ 1.698006] VFIO - User Level meta-driver version: 0.3
10654 13:39:48.786509 <6>[ 1.706257] usbcore: registered new interface driver usb-storage
10655 13:39:48.792983 <6>[ 1.712698] usbcore: registered new device driver onboard-usb-hub
10656 13:39:48.802438 <6>[ 1.721846] mt6397-rtc mt6359-rtc: registered as rtc0
10657 13:39:48.812115 <6>[ 1.727304] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:39:48 UTC (1716903588)
10658 13:39:48.815433 <6>[ 1.736866] i2c_dev: i2c /dev entries driver
10659 13:39:48.831999 <6>[ 1.748694] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10660 13:39:48.838877 <4>[ 1.757430] cpu cpu0: supply cpu not found, using dummy regulator
10661 13:39:48.845017 <4>[ 1.763855] cpu cpu1: supply cpu not found, using dummy regulator
10662 13:39:48.852154 <4>[ 1.770270] cpu cpu2: supply cpu not found, using dummy regulator
10663 13:39:48.858450 <4>[ 1.776674] cpu cpu3: supply cpu not found, using dummy regulator
10664 13:39:48.864902 <4>[ 1.783092] cpu cpu4: supply cpu not found, using dummy regulator
10665 13:39:48.871541 <4>[ 1.789486] cpu cpu5: supply cpu not found, using dummy regulator
10666 13:39:48.878198 <4>[ 1.795885] cpu cpu6: supply cpu not found, using dummy regulator
10667 13:39:48.885125 <4>[ 1.802282] cpu cpu7: supply cpu not found, using dummy regulator
10668 13:39:48.903397 <6>[ 1.822941] cpu cpu0: EM: created perf domain
10669 13:39:48.906740 <6>[ 1.827867] cpu cpu4: EM: created perf domain
10670 13:39:48.913916 <6>[ 1.833469] sdhci: Secure Digital Host Controller Interface driver
10671 13:39:48.920419 <6>[ 1.839898] sdhci: Copyright(c) Pierre Ossman
10672 13:39:48.926945 <6>[ 1.844848] Synopsys Designware Multimedia Card Interface Driver
10673 13:39:48.933510 <6>[ 1.851486] sdhci-pltfm: SDHCI platform and OF driver helper
10674 13:39:48.936883 <6>[ 1.851562] mmc0: CQHCI version 5.10
10675 13:39:48.943276 <6>[ 1.861835] ledtrig-cpu: registered to indicate activity on CPUs
10676 13:39:48.950358 <6>[ 1.868919] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10677 13:39:48.956875 <6>[ 1.875991] usbcore: registered new interface driver usbhid
10678 13:39:48.960057 <6>[ 1.881812] usbhid: USB HID core driver
10679 13:39:48.966520 <6>[ 1.886002] spi_master spi0: will run message pump with realtime priority
10680 13:39:49.014478 <6>[ 1.927619] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10681 13:39:49.033688 <6>[ 1.943228] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10682 13:39:49.037173 <6>[ 1.957094] mmc0: Command Queue Engine enabled
10683 13:39:49.043680 <6>[ 1.958155] cros-ec-spi spi0.0: Chrome EC device registered
10684 13:39:49.050341 <6>[ 1.961855] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10685 13:39:49.053359 <6>[ 1.975124] mmcblk0: mmc0:0001 DA4128 116 GiB
10686 13:39:49.064813 <6>[ 1.981494] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10687 13:39:49.071911 <6>[ 1.991622] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10688 13:39:49.078685 <6>[ 1.991902] NET: Registered PF_PACKET protocol family
10689 13:39:49.081466 <6>[ 1.998979] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10690 13:39:49.088652 <6>[ 2.002940] 9pnet: Installing 9P2000 support
10691 13:39:49.091766 <6>[ 2.008723] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10692 13:39:49.098304 <5>[ 2.012627] Key type dns_resolver registered
10693 13:39:49.104681 <6>[ 2.018474] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10694 13:39:49.107894 <6>[ 2.022878] registered taskstats version 1
10695 13:39:49.114879 <5>[ 2.033269] Loading compiled-in X.509 certificates
10696 13:39:49.140851 <4>[ 2.054269] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10697 13:39:49.151217 <4>[ 2.064977] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10698 13:39:49.165219 <6>[ 2.084645] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10699 13:39:49.171565 <6>[ 2.091515] xhci-mtk 11200000.usb: xHCI Host Controller
10700 13:39:49.178065 <6>[ 2.097021] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10701 13:39:49.188473 <6>[ 2.104880] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10702 13:39:49.195023 <6>[ 2.114317] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10703 13:39:49.201625 <6>[ 2.120503] xhci-mtk 11200000.usb: xHCI Host Controller
10704 13:39:49.208253 <6>[ 2.126014] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10705 13:39:49.215019 <6>[ 2.133668] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10706 13:39:49.222318 <6>[ 2.141578] hub 1-0:1.0: USB hub found
10707 13:39:49.224872 <6>[ 2.145605] hub 1-0:1.0: 1 port detected
10708 13:39:49.234886 <6>[ 2.149883] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10709 13:39:49.238549 <6>[ 2.158640] hub 2-0:1.0: USB hub found
10710 13:39:49.241683 <6>[ 2.162667] hub 2-0:1.0: 1 port detected
10711 13:39:49.250874 <6>[ 2.170748] mtk-msdc 11f70000.mmc: Got CD GPIO
10712 13:39:49.263459 <6>[ 2.180134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10713 13:39:49.270609 <6>[ 2.188155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10714 13:39:49.280105 <4>[ 2.196077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10715 13:39:49.289883 <6>[ 2.205613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10716 13:39:49.296515 <6>[ 2.213692] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10717 13:39:49.303101 <6>[ 2.221871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10718 13:39:49.313711 <6>[ 2.229799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10719 13:39:49.320046 <6>[ 2.237698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10720 13:39:49.329759 <6>[ 2.245518] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10721 13:39:49.339602 <6>[ 2.255945] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10722 13:39:49.346801 <6>[ 2.264310] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10723 13:39:49.356645 <6>[ 2.272680] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10724 13:39:49.363011 <6>[ 2.281019] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10725 13:39:49.372862 <6>[ 2.289369] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10726 13:39:49.379702 <6>[ 2.297708] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10727 13:39:49.389794 <6>[ 2.306057] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10728 13:39:49.396392 <6>[ 2.314396] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10729 13:39:49.405879 <6>[ 2.322741] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10730 13:39:49.416262 <6>[ 2.331080] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10731 13:39:49.422754 <6>[ 2.339417] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10732 13:39:49.432580 <6>[ 2.347756] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10733 13:39:49.439266 <6>[ 2.356093] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10734 13:39:49.449094 <6>[ 2.364430] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10735 13:39:49.455788 <6>[ 2.372767] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10736 13:39:49.462617 <6>[ 2.381515] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10737 13:39:49.468600 <6>[ 2.388705] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10738 13:39:49.475566 <6>[ 2.395481] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10739 13:39:49.485731 <6>[ 2.402249] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10740 13:39:49.492390 <6>[ 2.409179] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10741 13:39:49.498907 <6>[ 2.416038] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10742 13:39:49.508900 <6>[ 2.425168] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10743 13:39:49.518773 <6>[ 2.434313] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10744 13:39:49.528519 <6>[ 2.443613] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10745 13:39:49.538581 <6>[ 2.453082] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10746 13:39:49.548314 <6>[ 2.462554] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10747 13:39:49.554914 <6>[ 2.471674] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10748 13:39:49.564616 <6>[ 2.481140] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10749 13:39:49.574578 <6>[ 2.490259] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10750 13:39:49.584998 <6>[ 2.499556] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10751 13:39:49.594200 <6>[ 2.509716] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10752 13:39:49.605520 <6>[ 2.521768] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10753 13:39:49.612076 <6>[ 2.531442] Trying to probe devices needed for running init ...
10754 13:39:49.632683 <6>[ 2.549490] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10755 13:39:49.661263 <6>[ 2.581329] hub 2-1:1.0: USB hub found
10756 13:39:49.664593 <6>[ 2.585824] hub 2-1:1.0: 3 ports detected
10757 13:39:49.673275 <6>[ 2.593265] hub 2-1:1.0: USB hub found
10758 13:39:49.676906 <6>[ 2.597727] hub 2-1:1.0: 3 ports detected
10759 13:39:49.784613 <6>[ 2.701321] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10760 13:39:49.939475 <6>[ 2.859320] hub 1-1:1.0: USB hub found
10761 13:39:49.942576 <6>[ 2.863819] hub 1-1:1.0: 4 ports detected
10762 13:39:49.952776 <6>[ 2.872537] hub 1-1:1.0: USB hub found
10763 13:39:49.955938 <6>[ 2.877071] hub 1-1:1.0: 4 ports detected
10764 13:39:50.024681 <6>[ 2.941509] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10765 13:39:50.133546 <6>[ 3.050116] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10766 13:39:50.170741 <4>[ 3.087108] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10767 13:39:50.180071 <4>[ 3.096182] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10768 13:39:50.219662 <6>[ 3.139175] r8152 2-1.3:1.0 eth0: v1.12.13
10769 13:39:50.276418 <6>[ 3.193438] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10770 13:39:50.409591 <6>[ 3.329563] hub 1-1.4:1.0: USB hub found
10771 13:39:50.412917 <6>[ 3.334250] hub 1-1.4:1.0: 2 ports detected
10772 13:39:50.422649 <6>[ 3.342864] hub 1-1.4:1.0: USB hub found
10773 13:39:50.426049 <6>[ 3.347477] hub 1-1.4:1.0: 2 ports detected
10774 13:39:50.724613 <6>[ 3.641454] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10775 13:39:50.916864 <6>[ 3.833424] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10776 13:39:51.895230 <6>[ 4.815619] r8152 2-1.3:1.0 eth0: carrier on
10777 13:39:54.369064 <5>[ 4.837161] Sending DHCP requests .., OK
10778 13:39:54.375720 <6>[ 7.293521] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10779 13:39:54.378558 <6>[ 7.301816] IP-Config: Complete:
10780 13:39:54.391846 <6>[ 7.305318] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10781 13:39:54.398664 <6>[ 7.316048] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10782 13:39:54.405407 <6>[ 7.324669] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10783 13:39:54.411913 <6>[ 7.324680] nameserver0=192.168.201.1
10784 13:39:54.415168 <6>[ 7.336872] clk: Disabling unused clocks
10785 13:39:54.418996 <6>[ 7.342447] ALSA device list:
10786 13:39:54.424986 <6>[ 7.345716] No soundcards found.
10787 13:39:54.432978 <6>[ 7.353075] Freeing unused kernel memory: 8512K
10788 13:39:54.436138 <6>[ 7.358103] Run /init as init process
10789 13:39:54.446115 Loading, please wait...
10790 13:39:54.472459 Starting systemd-udevd version 252.22-1~deb12u1
10791 13:39:54.714471 <6>[ 7.631637] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10792 13:39:54.728666 <6>[ 7.645555] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10793 13:39:54.734993 <3>[ 7.646404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 13:39:54.745398 <6>[ 7.653874] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10795 13:39:54.751802 <6>[ 7.660719] remoteproc remoteproc0: scp is available
10796 13:39:54.755205 <6>[ 7.660922] remoteproc remoteproc0: powering up scp
10797 13:39:54.765124 <6>[ 7.660932] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10798 13:39:54.768236 <6>[ 7.660974] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10799 13:39:54.778015 <3>[ 7.668497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 13:39:54.784474 <6>[ 7.670330] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10801 13:39:54.794229 <3>[ 7.676672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 13:39:54.801271 <4>[ 7.695712] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10803 13:39:54.810841 <3>[ 7.708258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 13:39:54.817954 <4>[ 7.719852] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10805 13:39:54.824617 <3>[ 7.727295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 13:39:54.830809 <6>[ 7.738849] mc: Linux media interface: v0.10
10807 13:39:54.837543 <3>[ 7.742600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10808 13:39:54.847158 <3>[ 7.742611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 13:39:54.853694 <3>[ 7.742616] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 13:39:54.863719 <3>[ 7.751323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 13:39:54.870106 <6>[ 7.755045] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10812 13:39:54.880524 <4>[ 7.783460] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10813 13:39:54.884040 <4>[ 7.783460] Fallback method does not support PEC.
10814 13:39:54.890754 <6>[ 7.786765] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10815 13:39:54.901275 <6>[ 7.786826] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10816 13:39:54.904311 <6>[ 7.786832] remoteproc remoteproc0: remote processor scp is now up
10817 13:39:54.914741 <3>[ 7.787898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 13:39:54.921489 <6>[ 7.802409] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10819 13:39:54.927958 <3>[ 7.809080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 13:39:54.937769 <6>[ 7.810240] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10821 13:39:54.944584 <6>[ 7.811955] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10822 13:39:54.954082 <3>[ 7.812232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 13:39:54.961067 <6>[ 7.816120] pci_bus 0000:00: root bus resource [bus 00-ff]
10824 13:39:54.967499 <3>[ 7.824626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 13:39:54.974123 <6>[ 7.831053] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10826 13:39:54.983898 <3>[ 7.834517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10827 13:39:54.990513 <3>[ 7.839163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 13:39:55.000507 <6>[ 7.845988] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10829 13:39:55.010357 <6>[ 7.848706] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10830 13:39:55.019916 <3>[ 7.854066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 13:39:55.030051 <6>[ 7.857931] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10832 13:39:55.039694 <6>[ 7.858242] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10833 13:39:55.042901 <6>[ 7.863683] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10834 13:39:55.052980 <3>[ 7.870570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 13:39:55.059774 <3>[ 7.870585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 13:39:55.066448 <6>[ 7.871965] videodev: Linux video capture interface: v2.00
10837 13:39:55.073065 <6>[ 7.879381] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10838 13:39:55.079629 <6>[ 7.879527] pci 0000:00:00.0: supports D1 D2
10839 13:39:55.086034 <3>[ 7.885322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 13:39:55.089229 <6>[ 7.885843] Bluetooth: Core ver 2.22
10841 13:39:55.095880 <6>[ 7.885917] NET: Registered PF_BLUETOOTH protocol family
10842 13:39:55.102929 <6>[ 7.885918] Bluetooth: HCI device and connection manager initialized
10843 13:39:55.109404 <6>[ 7.885937] Bluetooth: HCI socket layer initialized
10844 13:39:55.112766 <6>[ 7.885941] Bluetooth: L2CAP socket layer initialized
10845 13:39:55.118982 <6>[ 7.885948] Bluetooth: SCO socket layer initialized
10846 13:39:55.125785 <6>[ 7.893414] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10847 13:39:55.132196 <3>[ 7.900554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 13:39:55.142389 <6>[ 7.910347] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10849 13:39:55.148883 <6>[ 7.928396] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10850 13:39:55.155684 <6>[ 7.936983] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10851 13:39:55.165328 <6>[ 7.946962] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10852 13:39:55.174914 <6>[ 7.955412] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10853 13:39:55.178748 <6>[ 7.955872] usbcore: registered new interface driver btusb
10854 13:39:55.191812 <4>[ 7.956892] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10855 13:39:55.198398 <3>[ 7.956904] Bluetooth: hci0: Failed to load firmware file (-2)
10856 13:39:55.201906 <3>[ 7.956907] Bluetooth: hci0: Failed to set up firmware (-2)
10857 13:39:55.211644 <4>[ 7.956911] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10858 13:39:55.218105 <6>[ 7.963974] usbcore: registered new interface driver uvcvideo
10859 13:39:55.227886 <6>[ 7.970066] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10860 13:39:55.234743 <6>[ 7.970083] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10861 13:39:55.241148 <6>[ 7.970691] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10862 13:39:55.244257 <6>[ 8.165998] pci 0000:01:00.0: supports D1 D2
10863 13:39:55.250901 <6>[ 8.170519] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10864 13:39:55.275923 <6>[ 8.193255] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10865 13:39:55.282488 <6>[ 8.200167] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10866 13:39:55.289403 <6>[ 8.208245] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10867 13:39:55.298937 <6>[ 8.216249] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10868 13:39:55.305582 <6>[ 8.224249] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10869 13:39:55.315648 <6>[ 8.232251] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10870 13:39:55.318952 <6>[ 8.240253] pci 0000:00:00.0: PCI bridge to [bus 01]
10871 13:39:55.329004 <6>[ 8.245469] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10872 13:39:55.335337 <6>[ 8.253594] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10873 13:39:55.342016 <6>[ 8.260430] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10874 13:39:55.348421 <6>[ 8.267192] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10875 13:39:55.372924 <5>[ 8.290093] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10876 13:39:55.394878 <5>[ 8.312161] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10877 13:39:55.401511 <5>[ 8.320176] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10878 13:39:55.411730 <4>[ 8.328678] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10879 13:39:55.417791 <6>[ 8.337659] cfg80211: failed to load regulatory.db
10880 13:39:55.477114 <6>[ 8.394243] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10881 13:39:55.483620 <6>[ 8.401937] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10882 13:39:55.508144 <6>[ 8.428891] mt7921e 0000:01:00.0: ASIC revision: 79610010
10883 13:39:55.612917 <6>[ 8.530090] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10884 13:39:55.616089 <6>[ 8.530090]
10885 13:39:55.625812 Begin: Loading essential drivers ... done.
10886 13:39:55.629542 Begin: Running /scripts/init-premount ... done.
10887 13:39:55.636086 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10888 13:39:55.645790 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10889 13:39:55.649177 Device /sys/class/net/eth0 found
10890 13:39:55.649303 done.
10891 13:39:55.655854 Begin: Waiting up to 180 secs for any network device to become available ... done.
10892 13:39:55.720505 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10893 13:39:55.727577 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10894 13:39:55.733875 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10895 13:39:55.740225 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10896 13:39:55.747037 host : mt8192-asurada-spherion-r0-cbg-9
10897 13:39:55.753908 domain : lava-rack
10898 13:39:55.756659 rootserver: 192.168.201.1 rootpath:
10899 13:39:55.756779 filename :
10900 13:39:55.878890 <6>[ 8.796241] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10901 13:39:55.887733 done.
10902 13:39:55.895814 Begin: Running /scripts/nfs-bottom ... done.
10903 13:39:55.906572 Begin: Running /scripts/init-bottom ... done.
10904 13:39:57.292994 <6>[ 10.213811] NET: Registered PF_INET6 protocol family
10905 13:39:57.300590 <6>[ 10.221182] Segment Routing with IPv6
10906 13:39:57.303907 <6>[ 10.225144] In-situ OAM (IOAM) with IPv6
10907 13:39:57.483690 <30>[ 10.374534] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10908 13:39:57.486335 <30>[ 10.407704] systemd[1]: Detected architecture arm64.
10909 13:39:57.496903
10910 13:39:57.500044 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10911 13:39:57.500148
10912 13:39:57.526126 <30>[ 10.447268] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10913 13:39:58.706143 <30>[ 11.624087] systemd[1]: Queued start job for default target graphical.target.
10914 13:39:58.757517 <30>[ 11.675336] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10915 13:39:58.764375 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10916 13:39:58.785478 <30>[ 11.703457] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10917 13:39:58.795633 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10918 13:39:58.813741 <30>[ 11.731416] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10919 13:39:58.823656 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10920 13:39:58.841027 <30>[ 11.758999] systemd[1]: Created slice user.slice - User and Session Slice.
10921 13:39:58.847643 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10922 13:39:58.872324 <30>[ 11.786355] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10923 13:39:58.881570 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10924 13:39:58.899586 <30>[ 11.813708] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10925 13:39:58.906087 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10926 13:39:58.934630 <30>[ 11.842082] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10927 13:39:58.944739 <30>[ 11.861995] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10928 13:39:58.951198 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10929 13:39:58.968087 <30>[ 11.885813] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10930 13:39:58.977806 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10931 13:39:58.996204 <30>[ 11.913954] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10932 13:39:59.006468 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10933 13:39:59.020866 <30>[ 11.941975] systemd[1]: Reached target paths.target - Path Units.
10934 13:39:59.030888 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10935 13:39:59.048280 <30>[ 11.965911] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10936 13:39:59.054554 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10937 13:39:59.068452 <30>[ 11.989408] systemd[1]: Reached target slices.target - Slice Units.
10938 13:39:59.078882 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10939 13:39:59.093142 <30>[ 12.013912] systemd[1]: Reached target swap.target - Swaps.
10940 13:39:59.099683 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10941 13:39:59.120700 <30>[ 12.037925] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10942 13:39:59.130028 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10943 13:39:59.148918 <30>[ 12.066450] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10944 13:39:59.158802 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10945 13:39:59.178462 <30>[ 12.096065] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10946 13:39:59.188140 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10947 13:39:59.205215 <30>[ 12.122796] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10948 13:39:59.215003 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10949 13:39:59.236808 <30>[ 12.154049] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10950 13:39:59.243214 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10951 13:39:59.261387 <30>[ 12.178885] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10952 13:39:59.271369 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10953 13:39:59.290369 <30>[ 12.208221] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10954 13:39:59.300321 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10955 13:39:59.316882 <30>[ 12.234555] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10956 13:39:59.326665 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10957 13:39:59.384210 <30>[ 12.301844] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10958 13:39:59.390455 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10959 13:39:59.410200 <30>[ 12.328188] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10960 13:39:59.416918 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10961 13:39:59.439388 <30>[ 12.357329] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10962 13:39:59.446308 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10963 13:39:59.470702 <30>[ 12.382018] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10964 13:39:59.524452 <30>[ 12.442302] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10965 13:39:59.534345 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10966 13:39:59.558504 <30>[ 12.476043] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10967 13:39:59.564760 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10968 13:39:59.590379 <30>[ 12.507799] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10969 13:39:59.596796 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10970 13:39:59.630892 <6>[ 12.548873] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10971 13:39:59.656439 <30>[ 12.574542] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10972 13:39:59.663077 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10973 13:39:59.690486 <30>[ 12.608122] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10974 13:39:59.700363 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10975 13:39:59.722175 <30>[ 12.639975] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10976 13:39:59.728733 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10977 13:39:59.754609 <30>[ 12.672318] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10978 13:39:59.761174 Startin<6>[ 12.681167] fuse: init (API version 7.37)
10979 13:39:59.767866 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10980 13:39:59.828921 <30>[ 12.746338] systemd[1]: Starting systemd-journald.service - Journal Service...
10981 13:39:59.835213 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10982 13:39:59.869157 <30>[ 12.786920] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10983 13:39:59.875939 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10984 13:39:59.906874 <30>[ 12.821031] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10985 13:39:59.913429 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10986 13:39:59.937582 <30>[ 12.855119] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10987 13:39:59.947242 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10988 13:39:59.969666 <30>[ 12.887262] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10989 13:39:59.975944 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10990 13:40:00.005812 <30>[ 12.923071] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10991 13:40:00.012683 <3>[ 12.923332] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 13:40:00.022028 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10993 13:40:00.040797 <30>[ 12.958438] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10994 13:40:00.050551 <3>[ 12.961814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 13:40:00.057618 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10996 13:40:00.076622 <30>[ 12.994266] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10997 13:40:00.090385 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 13.008020] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 13:40:00.093875 File System.
10999 13:40:00.113416 <30>[ 13.030053] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11000 13:40:00.122967 [[0;32m OK [<3>[ 13.040041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11001 13:40:00.129911 0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11002 13:40:00.149198 <30>[ 13.066443] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11003 13:40:00.155392 <3>[ 13.069624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 13:40:00.165224 <30>[ 13.074295] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11005 13:40:00.172570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11006 13:40:00.185095 <3>[ 13.103065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11007 13:40:00.196192 <30>[ 13.113977] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11008 13:40:00.202907 <30>[ 13.121842] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11009 13:40:00.216501 [[0;32m OK [0m] Finished [0<3>[ 13.132790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 13:40:00.219745 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11011 13:40:00.241534 <30>[ 13.159317] systemd[1]: modprobe@drm.service: Deactivated successfully.
11012 13:40:00.248069 <3>[ 13.162422] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 13:40:00.258197 <30>[ 13.167100] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11014 13:40:00.264801 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11015 13:40:00.279540 <3>[ 13.197318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 13:40:00.290030 <30>[ 13.208079] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11017 13:40:00.300635 <30>[ 13.216529] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11018 13:40:00.310678 [[0;32m OK [0m] Finished [0<3>[ 13.227319] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 13:40:00.316985 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11020 13:40:00.337562 <30>[ 13.255427] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11021 13:40:00.344283 <30>[ 13.263392] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11022 13:40:00.354368 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11023 13:40:00.374038 <30>[ 13.291564] systemd[1]: modprobe@loop.service: Deactivated successfully.
11024 13:40:00.380299 <30>[ 13.299735] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11025 13:40:00.390788 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11026 13:40:00.411233 <4>[ 13.322143] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11027 13:40:00.420794 <3>[ 13.337798] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11028 13:40:00.427260 <30>[ 13.338639] systemd[1]: Started systemd-journald.service - Journal Service.
11029 13:40:00.434085 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11030 13:40:00.458593 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11031 13:40:00.477462 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11032 13:40:00.497578 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11033 13:40:00.517208 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11034 13:40:00.539372 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11035 13:40:00.592780 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11036 13:40:00.615766 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11037 13:40:00.638345 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11038 13:40:00.662273 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11039 13:40:00.694343 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11040 13:40:00.704372 <46>[ 13.621762] systemd-journald[299]: Received client request to flush runtime journal.
11041 13:40:00.717735 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11042 13:40:00.746584 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11043 13:40:00.764682 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11044 13:40:00.785140 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11045 13:40:01.389854 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11046 13:40:01.815514 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11047 13:40:01.860060 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11048 13:40:02.128501 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11049 13:40:02.236058 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11050 13:40:02.252433 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11051 13:40:02.275727 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11052 13:40:02.324409 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11053 13:40:02.352201 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11054 13:40:02.621875 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11055 13:40:02.669206 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11056 13:40:02.744001 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11057 13:40:03.052269 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11058 13:40:03.084115 <6>[ 16.005756] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11059 13:40:03.094211 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11060 13:40:03.153247 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11061 13:40:03.248237 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11062 13:40:03.265517 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11063 13:40:03.298687 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11064 13:40:03.319555 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11065 13:40:03.390017 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11066 13:40:03.404989 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11067 13:40:03.423653 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11068 13:40:03.444948 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11069 13:40:03.504113 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11070 13:40:03.527886 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11071 13:40:03.549222 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11072 13:40:03.567992 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11073 13:40:03.583801 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11074 13:40:03.607000 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11075 13:40:03.643517 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11076 13:40:03.659626 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11077 13:40:03.679108 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11078 13:40:03.699408 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11079 13:40:03.715252 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11080 13:40:03.734092 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11081 13:40:03.751677 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11082 13:40:03.772883 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11083 13:40:03.817577 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11084 13:40:03.852202 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11085 13:40:03.911797 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11086 13:40:03.934663 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11087 13:40:03.951611 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11088 13:40:04.030673 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11089 13:40:04.084742 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11090 13:40:04.107088 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11091 13:40:04.124425 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11092 13:40:04.155374 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11093 13:40:04.200565 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11094 13:40:04.315396 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11095 13:40:04.334147 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11096 13:40:04.350955 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11097 13:40:04.402713 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11098 13:40:04.459881 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11099 13:40:04.556822
11100 13:40:04.560360 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11101 13:40:04.560996
11102 13:40:04.563364 debian-bookworm-arm64 login: root (automatic login)
11103 13:40:04.563854
11104 13:40:04.910331 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11105 13:40:04.910546
11106 13:40:04.917171 The programs included with the Debian GNU/Linux system are free software;
11107 13:40:04.923334 the exact distribution terms for each program are described in the
11108 13:40:04.927203 individual files in /usr/share/doc/*/copyright.
11109 13:40:04.927358
11110 13:40:04.933193 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11111 13:40:04.936485 permitted by applicable law.
11112 13:40:05.926259 Matched prompt #10: / #
11114 13:40:05.926548 Setting prompt string to ['/ #']
11115 13:40:05.926643 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11117 13:40:05.926835 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11118 13:40:05.926922 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11119 13:40:05.926994 Setting prompt string to ['/ #']
11120 13:40:05.927061 Forcing a shell prompt, looking for ['/ #']
11122 13:40:05.977258 / #
11123 13:40:05.977398 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11124 13:40:05.977487 Waiting using forced prompt support (timeout 00:02:30)
11125 13:40:05.982641
11126 13:40:05.983001 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11127 13:40:05.983153 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11129 13:40:06.083646 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s'
11130 13:40:06.089087 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063000/extract-nfsrootfs-cj124k4s'
11132 13:40:06.189568 / # export NFS_SERVER_IP='192.168.201.1'
11133 13:40:06.194397 export NFS_SERVER_IP='192.168.201.1'
11134 13:40:06.194709 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11135 13:40:06.194817 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11136 13:40:06.194907 end: 2 depthcharge-action (duration 00:01:38) [common]
11137 13:40:06.194996 start: 3 lava-test-retry (timeout 00:07:21) [common]
11138 13:40:06.195081 start: 3.1 lava-test-shell (timeout 00:07:21) [common]
11139 13:40:06.195157 Using namespace: common
11141 13:40:06.295460 / # #
11142 13:40:06.295630 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11143 13:40:06.301229 #
11144 13:40:06.301489 Using /lava-14063000
11146 13:40:06.401777 / # export SHELL=/bin/bash
11147 13:40:06.407524 export SHELL=/bin/bash
11149 13:40:06.508002 / # . /lava-14063000/environment
11150 13:40:06.512883 . /lava-14063000/environment
11152 13:40:06.619648 / # /lava-14063000/bin/lava-test-runner /lava-14063000/0
11153 13:40:06.619806 Test shell timeout: 10s (minimum of the action and connection timeout)
11154 13:40:06.624591 /lava-14063000/bin/lava-test-runner /lava-14063000/0
11155 13:40:06.895427 + export TESTRUN_ID=0_timesync-off
11156 13:40:06.898731 + TESTRUN_ID=0_timesync-off
11157 13:40:06.901986 + cd /lava-14063000/0/tests/0_timesync-off
11158 13:40:06.904844 ++ cat uuid
11159 13:40:06.910024 + UUID=14063000_1.6.2.3.1
11160 13:40:06.910100 + set +x
11161 13:40:06.916301 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14063000_1.6.2.3.1>
11162 13:40:06.916557 Received signal: <STARTRUN> 0_timesync-off 14063000_1.6.2.3.1
11163 13:40:06.916630 Starting test lava.0_timesync-off (14063000_1.6.2.3.1)
11164 13:40:06.916724 Skipping test definition patterns.
11165 13:40:06.919719 + systemctl stop systemd-timesyncd
11166 13:40:06.975253 + set +x
11167 13:40:06.978514 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14063000_1.6.2.3.1>
11168 13:40:06.978772 Received signal: <ENDRUN> 0_timesync-off 14063000_1.6.2.3.1
11169 13:40:06.978897 Ending use of test pattern.
11170 13:40:06.978988 Ending test lava.0_timesync-off (14063000_1.6.2.3.1), duration 0.06
11172 13:40:07.056911 + export TESTRUN_ID=1_kselftest-dt
11173 13:40:07.060209 + TESTRUN_ID=1_kselftest-dt
11174 13:40:07.063422 + cd /lava-14063000/0/tests/1_kselftest-dt
11175 13:40:07.066524 ++ cat uuid
11176 13:40:07.072032 + UUID=14063000_1.6.2.3.5
11177 13:40:07.072110 + set +x
11178 13:40:07.078759 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14063000_1.6.2.3.5>
11179 13:40:07.079031 Received signal: <STARTRUN> 1_kselftest-dt 14063000_1.6.2.3.5
11180 13:40:07.079104 Starting test lava.1_kselftest-dt (14063000_1.6.2.3.5)
11181 13:40:07.079185 Skipping test definition patterns.
11182 13:40:07.081942 + cd ./automated/linux/kselftest/
11183 13:40:07.105547 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11184 13:40:07.162023 INFO: install_deps skipped
11185 13:40:07.689626 --2024-05-28 13:40:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11186 13:40:07.700209 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11187 13:40:07.830998 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11188 13:40:07.962536 HTTP request sent, awaiting response... 200 OK
11189 13:40:07.965564 Length: 1642660 (1.6M) [application/octet-stream]
11190 13:40:07.969221 Saving to: 'kselftest_armhf.tar.gz'
11191 13:40:07.969643
11192 13:40:07.969968
11193 13:40:08.219612 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11194 13:40:08.476821 kselftest_armhf.tar 2%[ ] 47.81K 182KB/s
11195 13:40:08.817517 kselftest_armhf.tar 13%[=> ] 216.08K 411KB/s
11196 13:40:08.884534 kselftest_armhf.tar 35%[======> ] 563.94K 645KB/s
11197 13:40:08.890782 kselftest_armhf.tar 100%[===================>] 1.57M 1.66MB/s in 0.9s
11198 13:40:08.891251
11199 13:40:09.042754 2024-05-28 13:40:08 (1.66 MB/s) - 'kselftest_armhf.tar.gz' saved [1642660/1642660]
11200 13:40:09.042885
11201 13:40:13.791823 skiplist:
11202 13:40:13.795546 ========================================
11203 13:40:13.798318 ========================================
11204 13:40:13.871998 ============== Tests to run ===============
11205 13:40:13.875101 ===========End Tests to run ===============
11206 13:40:13.882520 shardfile-dt fail
11207 13:40:13.907145 ./kselftest.sh: 131: cannot open /lava-14063000/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11208 13:40:13.910488 + ../../utils/send-to-lava.sh ./output/result.txt
11209 13:40:13.983925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11210 13:40:13.984051 + set +x
11211 13:40:13.984297 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11213 13:40:13.990468 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14063000_1.6.2.3.5>
11214 13:40:13.990722 Received signal: <ENDRUN> 1_kselftest-dt 14063000_1.6.2.3.5
11215 13:40:13.990797 Ending use of test pattern.
11216 13:40:13.990857 Ending test lava.1_kselftest-dt (14063000_1.6.2.3.5), duration 6.91
11218 13:40:13.991068 ok: lava_test_shell seems to have completed
11219 13:40:13.991156 shardfile-dt: fail
11220 13:40:13.991244 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11221 13:40:13.991325 end: 3 lava-test-retry (duration 00:00:08) [common]
11222 13:40:13.991411 start: 4 finalize (timeout 00:07:13) [common]
11223 13:40:13.991498 start: 4.1 power-off (timeout 00:00:30) [common]
11224 13:40:13.991651 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11225 13:40:14.192298 >> Command sent successfully.
11226 13:40:14.194734 Returned 0 in 0 seconds
11227 13:40:14.295119 end: 4.1 power-off (duration 00:00:00) [common]
11229 13:40:14.295465 start: 4.2 read-feedback (timeout 00:07:13) [common]
11231 13:40:14.296088 Listened to connection for namespace 'common' for up to 1s
11232 13:40:15.296690 Finalising connection for namespace 'common'
11233 13:40:15.296849 Disconnecting from shell: Finalise
11234 13:40:15.296923 / #
11235 13:40:15.397241 end: 4.2 read-feedback (duration 00:00:01) [common]
11236 13:40:15.397484 end: 4 finalize (duration 00:00:01) [common]
11237 13:40:15.397735 Cleaning after the job
11238 13:40:15.397926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/ramdisk
11239 13:40:15.400042 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/kernel
11240 13:40:15.410745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/dtb
11241 13:40:15.410957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/nfsrootfs
11242 13:40:15.473918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063000/tftp-deploy-9gkb3zig/modules
11243 13:40:15.479675 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063000
11244 13:40:16.042411 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063000
11245 13:40:16.042591 Job finished correctly