Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:37:35.312963 lava-dispatcher, installed at version: 2024.03
2 13:37:35.313202 start: 0 validate
3 13:37:35.313368 Start time: 2024-05-28 13:37:35.313361+00:00 (UTC)
4 13:37:35.313493 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:37:35.313621 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:37:35.571221 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:37:35.571383 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:37:35.827566 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:37:35.827740 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:37:51.963322 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:37:51.963583 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:37:52.466019 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:37:52.466207 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:37:52.725698 validate duration: 17.41
16 13:37:52.725979 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:37:52.726129 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:37:52.726259 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:37:52.726418 Not decompressing ramdisk as can be used compressed.
20 13:37:52.726536 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:37:52.726640 saving as /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/ramdisk/initrd.cpio.gz
22 13:37:52.726736 total size: 5628169 (5 MB)
23 13:37:56.305365 progress 0 % (0 MB)
24 13:37:56.314523 progress 5 % (0 MB)
25 13:37:56.323144 progress 10 % (0 MB)
26 13:37:56.329881 progress 15 % (0 MB)
27 13:37:56.335191 progress 20 % (1 MB)
28 13:37:56.339103 progress 25 % (1 MB)
29 13:37:56.342799 progress 30 % (1 MB)
30 13:37:56.346083 progress 35 % (1 MB)
31 13:37:56.348767 progress 40 % (2 MB)
32 13:37:56.351418 progress 45 % (2 MB)
33 13:37:56.353745 progress 50 % (2 MB)
34 13:37:56.356077 progress 55 % (2 MB)
35 13:37:56.358032 progress 60 % (3 MB)
36 13:37:56.359458 progress 65 % (3 MB)
37 13:37:56.361079 progress 70 % (3 MB)
38 13:37:56.362597 progress 75 % (4 MB)
39 13:37:56.364213 progress 80 % (4 MB)
40 13:37:56.365720 progress 85 % (4 MB)
41 13:37:56.367279 progress 90 % (4 MB)
42 13:37:56.368927 progress 95 % (5 MB)
43 13:37:56.370419 progress 100 % (5 MB)
44 13:37:56.370630 5 MB downloaded in 3.64 s (1.47 MB/s)
45 13:37:56.370787 end: 1.1.1 http-download (duration 00:00:04) [common]
47 13:37:56.371047 end: 1.1 download-retry (duration 00:00:04) [common]
48 13:37:56.371148 start: 1.2 download-retry (timeout 00:09:56) [common]
49 13:37:56.371245 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 13:37:56.371374 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:37:56.371477 saving as /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/kernel/Image
52 13:37:56.371573 total size: 54682112 (52 MB)
53 13:37:56.371668 No compression specified
54 13:37:56.373113 progress 0 % (0 MB)
55 13:37:56.387842 progress 5 % (2 MB)
56 13:37:56.402378 progress 10 % (5 MB)
57 13:37:56.416570 progress 15 % (7 MB)
58 13:37:56.430727 progress 20 % (10 MB)
59 13:37:56.444987 progress 25 % (13 MB)
60 13:37:56.459210 progress 30 % (15 MB)
61 13:37:56.473572 progress 35 % (18 MB)
62 13:37:56.488116 progress 40 % (20 MB)
63 13:37:56.502210 progress 45 % (23 MB)
64 13:37:56.516476 progress 50 % (26 MB)
65 13:37:56.530657 progress 55 % (28 MB)
66 13:37:56.544872 progress 60 % (31 MB)
67 13:37:56.558969 progress 65 % (33 MB)
68 13:37:56.573429 progress 70 % (36 MB)
69 13:37:56.587964 progress 75 % (39 MB)
70 13:37:56.602255 progress 80 % (41 MB)
71 13:37:56.616334 progress 85 % (44 MB)
72 13:37:56.630542 progress 90 % (46 MB)
73 13:37:56.644491 progress 95 % (49 MB)
74 13:37:56.658334 progress 100 % (52 MB)
75 13:37:56.658589 52 MB downloaded in 0.29 s (181.70 MB/s)
76 13:37:56.658749 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:37:56.658995 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:37:56.659085 start: 1.3 download-retry (timeout 00:09:56) [common]
80 13:37:56.659171 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 13:37:56.659298 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:37:56.659370 saving as /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/dtb/mt8192-asurada-spherion-r0.dtb
83 13:37:56.659433 total size: 47258 (0 MB)
84 13:37:56.659495 No compression specified
85 13:37:56.660531 progress 69 % (0 MB)
86 13:37:56.660811 progress 100 % (0 MB)
87 13:37:56.660967 0 MB downloaded in 0.00 s (29.42 MB/s)
88 13:37:56.661089 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:37:56.661380 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:37:56.661469 start: 1.4 download-retry (timeout 00:09:56) [common]
92 13:37:56.661553 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 13:37:56.661709 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:37:56.661782 saving as /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/nfsrootfs/full.rootfs.tar
95 13:37:56.661927 total size: 120894716 (115 MB)
96 13:37:56.662007 Using unxz to decompress xz
97 13:37:56.665703 progress 0 % (0 MB)
98 13:37:57.010802 progress 5 % (5 MB)
99 13:37:57.372977 progress 10 % (11 MB)
100 13:37:57.724792 progress 15 % (17 MB)
101 13:37:58.052362 progress 20 % (23 MB)
102 13:37:58.344109 progress 25 % (28 MB)
103 13:37:58.705395 progress 30 % (34 MB)
104 13:37:59.041276 progress 35 % (40 MB)
105 13:37:59.206203 progress 40 % (46 MB)
106 13:37:59.393126 progress 45 % (51 MB)
107 13:37:59.711980 progress 50 % (57 MB)
108 13:38:00.086492 progress 55 % (63 MB)
109 13:38:00.431504 progress 60 % (69 MB)
110 13:38:00.770060 progress 65 % (74 MB)
111 13:38:01.111521 progress 70 % (80 MB)
112 13:38:01.468955 progress 75 % (86 MB)
113 13:38:01.807852 progress 80 % (92 MB)
114 13:38:02.144116 progress 85 % (98 MB)
115 13:38:02.499161 progress 90 % (103 MB)
116 13:38:02.831494 progress 95 % (109 MB)
117 13:38:03.189266 progress 100 % (115 MB)
118 13:38:03.194751 115 MB downloaded in 6.53 s (17.65 MB/s)
119 13:38:03.194991 end: 1.4.1 http-download (duration 00:00:07) [common]
121 13:38:03.195296 end: 1.4 download-retry (duration 00:00:07) [common]
122 13:38:03.195391 start: 1.5 download-retry (timeout 00:09:50) [common]
123 13:38:03.195479 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 13:38:03.195638 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:38:03.195710 saving as /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/modules/modules.tar
126 13:38:03.195773 total size: 8607916 (8 MB)
127 13:38:03.195838 Using unxz to decompress xz
128 13:38:03.448456 progress 0 % (0 MB)
129 13:38:03.503904 progress 5 % (0 MB)
130 13:38:03.530389 progress 10 % (0 MB)
131 13:38:03.555902 progress 15 % (1 MB)
132 13:38:03.580998 progress 20 % (1 MB)
133 13:38:03.606730 progress 25 % (2 MB)
134 13:38:03.631767 progress 30 % (2 MB)
135 13:38:03.655070 progress 35 % (2 MB)
136 13:38:03.681462 progress 40 % (3 MB)
137 13:38:03.706219 progress 45 % (3 MB)
138 13:38:03.730513 progress 50 % (4 MB)
139 13:38:03.755287 progress 55 % (4 MB)
140 13:38:03.779628 progress 60 % (4 MB)
141 13:38:03.803493 progress 65 % (5 MB)
142 13:38:03.830024 progress 70 % (5 MB)
143 13:38:03.856970 progress 75 % (6 MB)
144 13:38:03.880661 progress 80 % (6 MB)
145 13:38:03.904667 progress 85 % (7 MB)
146 13:38:03.928570 progress 90 % (7 MB)
147 13:38:03.957593 progress 95 % (7 MB)
148 13:38:03.986002 progress 100 % (8 MB)
149 13:38:03.991829 8 MB downloaded in 0.80 s (10.31 MB/s)
150 13:38:03.992070 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:38:03.992341 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:38:03.992437 start: 1.6 prepare-tftp-overlay (timeout 00:09:49) [common]
154 13:38:03.992533 start: 1.6.1 extract-nfsrootfs (timeout 00:09:49) [common]
155 13:38:07.303551 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e
156 13:38:07.303762 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 13:38:07.303885 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 13:38:07.304073 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf
159 13:38:07.304200 makedir: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin
160 13:38:07.304312 makedir: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/tests
161 13:38:07.304417 makedir: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/results
162 13:38:07.304520 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-add-keys
163 13:38:07.304672 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-add-sources
164 13:38:07.304809 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-background-process-start
165 13:38:07.304934 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-background-process-stop
166 13:38:07.305058 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-common-functions
167 13:38:07.305179 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-echo-ipv4
168 13:38:07.305330 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-install-packages
169 13:38:07.305464 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-installed-packages
170 13:38:07.305595 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-os-build
171 13:38:07.305728 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-probe-channel
172 13:38:07.305856 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-probe-ip
173 13:38:07.305978 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-target-ip
174 13:38:07.306108 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-target-mac
175 13:38:07.306228 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-target-storage
176 13:38:07.306349 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-case
177 13:38:07.306469 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-event
178 13:38:07.306587 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-feedback
179 13:38:07.306705 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-raise
180 13:38:07.306823 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-reference
181 13:38:07.306943 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-runner
182 13:38:07.307062 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-set
183 13:38:07.307182 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-test-shell
184 13:38:07.307303 Updating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-add-keys (debian)
185 13:38:07.307449 Updating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-add-sources (debian)
186 13:38:07.307590 Updating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-install-packages (debian)
187 13:38:07.307724 Updating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-installed-packages (debian)
188 13:38:07.307855 Updating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/bin/lava-os-build (debian)
189 13:38:07.307985 Creating /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/environment
190 13:38:07.308080 LAVA metadata
191 13:38:07.308151 - LAVA_JOB_ID=14063028
192 13:38:07.308231 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:38:07.308328 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 13:38:07.308408 skipped lava-vland-overlay
195 13:38:07.308485 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:38:07.308565 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 13:38:07.308627 skipped lava-multinode-overlay
198 13:38:07.308699 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:38:07.308778 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 13:38:07.308850 Loading test definitions
201 13:38:07.308938 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 13:38:07.309008 Using /lava-14063028 at stage 0
203 13:38:07.309273 uuid=14063028_1.6.2.3.1 testdef=None
204 13:38:07.309413 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:38:07.309500 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 13:38:07.309938 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:38:07.310158 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 13:38:07.310702 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:38:07.310936 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 13:38:07.311461 runner path: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/0/tests/0_timesync-off test_uuid 14063028_1.6.2.3.1
213 13:38:07.311613 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:38:07.311838 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 13:38:07.311910 Using /lava-14063028 at stage 0
217 13:38:07.312008 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:38:07.312093 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/0/tests/1_kselftest-rtc'
219 13:38:09.861077 Running '/usr/bin/git checkout kernelci.org
220 13:38:10.005728 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 13:38:10.006436 uuid=14063028_1.6.2.3.5 testdef=None
222 13:38:10.006594 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:38:10.006857 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 13:38:10.007582 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:38:10.007814 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 13:38:10.008767 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:38:10.009012 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 13:38:10.009970 runner path: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/0/tests/1_kselftest-rtc test_uuid 14063028_1.6.2.3.5
232 13:38:10.010064 BOARD='mt8192-asurada-spherion-r0'
233 13:38:10.010131 BRANCH='cip'
234 13:38:10.010192 SKIPFILE='/dev/null'
235 13:38:10.010251 SKIP_INSTALL='True'
236 13:38:10.010308 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:38:10.010370 TST_CASENAME=''
238 13:38:10.010428 TST_CMDFILES='rtc'
239 13:38:10.010567 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:38:10.010775 Creating lava-test-runner.conf files
242 13:38:10.010840 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063028/lava-overlay-x2lqlxmf/lava-14063028/0 for stage 0
243 13:38:10.010930 - 0_timesync-off
244 13:38:10.010999 - 1_kselftest-rtc
245 13:38:10.011094 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:38:10.011184 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 13:38:17.557175 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 13:38:17.557370 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 13:38:17.557475 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:38:17.557578 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:38:17.557670 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 13:38:17.720104 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:38:17.720471 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 13:38:17.720587 extracting modules file /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e
255 13:38:17.939500 extracting modules file /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063028/extract-overlay-ramdisk-fnkh2ui_/ramdisk
256 13:38:18.182596 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:38:18.182765 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 13:38:18.182865 [common] Applying overlay to NFS
259 13:38:18.182938 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063028/compress-overlay-1bgxflpk/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e
260 13:38:19.120966 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:38:19.121136 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 13:38:19.121236 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:38:19.121353 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 13:38:19.121440 Building ramdisk /var/lib/lava/dispatcher/tmp/14063028/extract-overlay-ramdisk-fnkh2ui_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063028/extract-overlay-ramdisk-fnkh2ui_/ramdisk
265 13:38:19.450359 >> 130335 blocks
266 13:38:21.515353 rename /var/lib/lava/dispatcher/tmp/14063028/extract-overlay-ramdisk-fnkh2ui_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/ramdisk/ramdisk.cpio.gz
267 13:38:21.515776 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:38:21.515902 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 13:38:21.516007 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 13:38:21.516117 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/kernel/Image']
271 13:38:34.940718 Returned 0 in 13 seconds
272 13:38:35.041392 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/kernel/image.itb
273 13:38:35.392328 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:38:35.392709 output: Created: Tue May 28 14:38:35 2024
275 13:38:35.392816 output: Image 0 (kernel-1)
276 13:38:35.392917 output: Description:
277 13:38:35.392990 output: Created: Tue May 28 14:38:35 2024
278 13:38:35.393053 output: Type: Kernel Image
279 13:38:35.393119 output: Compression: lzma compressed
280 13:38:35.393209 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
281 13:38:35.393308 output: Architecture: AArch64
282 13:38:35.393371 output: OS: Linux
283 13:38:35.393431 output: Load Address: 0x00000000
284 13:38:35.393493 output: Entry Point: 0x00000000
285 13:38:35.393578 output: Hash algo: crc32
286 13:38:35.393657 output: Hash value: 0578ee26
287 13:38:35.393717 output: Image 1 (fdt-1)
288 13:38:35.393774 output: Description: mt8192-asurada-spherion-r0
289 13:38:35.393833 output: Created: Tue May 28 14:38:35 2024
290 13:38:35.393890 output: Type: Flat Device Tree
291 13:38:35.393943 output: Compression: uncompressed
292 13:38:35.393996 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:38:35.394049 output: Architecture: AArch64
294 13:38:35.394103 output: Hash algo: crc32
295 13:38:35.394156 output: Hash value: 0f8e4d2e
296 13:38:35.394213 output: Image 2 (ramdisk-1)
297 13:38:35.394269 output: Description: unavailable
298 13:38:35.394323 output: Created: Tue May 28 14:38:35 2024
299 13:38:35.394378 output: Type: RAMDisk Image
300 13:38:35.394432 output: Compression: Unknown Compression
301 13:38:35.394486 output: Data Size: 18735655 Bytes = 18296.54 KiB = 17.87 MiB
302 13:38:35.394540 output: Architecture: AArch64
303 13:38:35.394593 output: OS: Linux
304 13:38:35.394647 output: Load Address: unavailable
305 13:38:35.394700 output: Entry Point: unavailable
306 13:38:35.394757 output: Hash algo: crc32
307 13:38:35.394815 output: Hash value: 93d72379
308 13:38:35.394869 output: Default Configuration: 'conf-1'
309 13:38:35.394922 output: Configuration 0 (conf-1)
310 13:38:35.394976 output: Description: mt8192-asurada-spherion-r0
311 13:38:35.395029 output: Kernel: kernel-1
312 13:38:35.395083 output: Init Ramdisk: ramdisk-1
313 13:38:35.395137 output: FDT: fdt-1
314 13:38:35.395190 output: Loadables: kernel-1
315 13:38:35.395243 output:
316 13:38:35.395451 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 13:38:35.395559 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 13:38:35.395670 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 13:38:35.395766 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 13:38:35.395850 No LXC device requested
321 13:38:35.395931 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:38:35.396019 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 13:38:35.396097 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:38:35.396169 Checking files for TFTP limit of 4294967296 bytes.
325 13:38:35.396646 end: 1 tftp-deploy (duration 00:00:43) [common]
326 13:38:35.396757 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:38:35.396850 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:38:35.396986 substitutions:
329 13:38:35.397055 - {DTB}: 14063028/tftp-deploy-13dlhag1/dtb/mt8192-asurada-spherion-r0.dtb
330 13:38:35.397120 - {INITRD}: 14063028/tftp-deploy-13dlhag1/ramdisk/ramdisk.cpio.gz
331 13:38:35.397180 - {KERNEL}: 14063028/tftp-deploy-13dlhag1/kernel/Image
332 13:38:35.397240 - {LAVA_MAC}: None
333 13:38:35.397305 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e
334 13:38:35.397397 - {NFS_SERVER_IP}: 192.168.201.1
335 13:38:35.397491 - {PRESEED_CONFIG}: None
336 13:38:35.397551 - {PRESEED_LOCAL}: None
337 13:38:35.397607 - {RAMDISK}: 14063028/tftp-deploy-13dlhag1/ramdisk/ramdisk.cpio.gz
338 13:38:35.397663 - {ROOT_PART}: None
339 13:38:35.397719 - {ROOT}: None
340 13:38:35.397777 - {SERVER_IP}: 192.168.201.1
341 13:38:35.397833 - {TEE}: None
342 13:38:35.397889 Parsed boot commands:
343 13:38:35.397943 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:38:35.398120 Parsed boot commands: tftpboot 192.168.201.1 14063028/tftp-deploy-13dlhag1/kernel/image.itb 14063028/tftp-deploy-13dlhag1/kernel/cmdline
345 13:38:35.398210 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:38:35.398295 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:38:35.398387 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:38:35.398475 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:38:35.398551 Not connected, no need to disconnect.
350 13:38:35.398631 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:38:35.398716 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:38:35.398786 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 13:38:35.402090 Setting prompt string to ['lava-test: # ']
354 13:38:35.402496 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:38:35.402620 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:38:35.402738 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:38:35.402845 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:38:35.403023 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 13:38:48.916827 Returned 0 in 13 seconds
360 13:38:49.017498 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 13:38:49.017847 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 13:38:49.017954 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 13:38:49.018044 Setting prompt string to 'Starting depthcharge on Spherion...'
365 13:38:49.018119 Changing prompt to 'Starting depthcharge on Spherion...'
366 13:38:49.018193 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 13:38:49.018624 [Enter `^Ec?' for help]
368 13:38:49.018709
369 13:38:49.018780
370 13:38:49.018847 F0: 102B 0000
371 13:38:49.018914
372 13:38:49.018988 F3: 1001 0000 [0200]
373 13:38:49.019047
374 13:38:49.019109 F3: 1001 0000
375 13:38:49.019169
376 13:38:49.019225 F7: 102D 0000
377 13:38:49.019281
378 13:38:49.019336 F1: 0000 0000
379 13:38:49.019391
380 13:38:49.019446 V0: 0000 0000 [0001]
381 13:38:49.019501
382 13:38:49.019555 00: 0007 8000
383 13:38:49.019614
384 13:38:49.019668 01: 0000 0000
385 13:38:49.019724
386 13:38:49.019778 BP: 0C00 0209 [0000]
387 13:38:49.019833
388 13:38:49.019887 G0: 1182 0000
389 13:38:49.019941
390 13:38:49.019995 EC: 0000 0021 [4000]
391 13:38:49.020049
392 13:38:49.020103 S7: 0000 0000 [0000]
393 13:38:49.020157
394 13:38:49.020211 CC: 0000 0000 [0001]
395 13:38:49.020266
396 13:38:49.020320 T0: 0000 0040 [010F]
397 13:38:49.020374
398 13:38:49.020428 Jump to BL
399 13:38:49.020482
400 13:38:49.020536
401 13:38:49.020589
402 13:38:49.020643 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 13:38:49.020701 ARM64: Exception handlers installed.
404 13:38:49.020758 ARM64: Testing exception
405 13:38:49.020813 ARM64: Done test exception
406 13:38:49.020872 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 13:38:49.020928 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 13:38:49.020985 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 13:38:49.021040 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 13:38:49.021123 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 13:38:49.021178 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 13:38:49.021233 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 13:38:49.021288 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 13:38:49.021382 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 13:38:49.021439 WDT: Last reset was cold boot
416 13:38:49.021495 SPI1(PAD0) initialized at 2873684 Hz
417 13:38:49.021550 SPI5(PAD0) initialized at 992727 Hz
418 13:38:49.021605 VBOOT: Loading verstage.
419 13:38:49.021659 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 13:38:49.021714 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 13:38:49.021770 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 13:38:49.021826 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 13:38:49.021881 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 13:38:49.021936 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 13:38:49.021991 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 13:38:49.022046
427 13:38:49.022100
428 13:38:49.022155 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 13:38:49.022210 ARM64: Exception handlers installed.
430 13:38:49.022264 ARM64: Testing exception
431 13:38:49.022319 ARM64: Done test exception
432 13:38:49.022373 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 13:38:49.022428 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 13:38:49.022483 Probing TPM: . done!
435 13:38:49.022538 TPM ready after 0 ms
436 13:38:49.022593 Connected to device vid:did:rid of 1ae0:0028:00
437 13:38:49.022647 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 13:38:49.022703 Initialized TPM device CR50 revision 0
439 13:38:49.022758 tlcl_send_startup: Startup return code is 0
440 13:38:49.022812 TPM: setup succeeded
441 13:38:49.022867 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 13:38:49.022922 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 13:38:49.022976 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 13:38:49.023032 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:38:49.023087 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 13:38:49.023141 in-header: 03 07 00 00 08 00 00 00
447 13:38:49.023195 in-data: aa e4 47 04 13 02 00 00
448 13:38:49.023250 Chrome EC: UHEPI supported
449 13:38:49.023304 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 13:38:49.023359 in-header: 03 a9 00 00 08 00 00 00
451 13:38:49.023413 in-data: 84 60 60 08 00 00 00 00
452 13:38:49.023467 Phase 1
453 13:38:49.023522 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 13:38:49.023577 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 13:38:49.023632 VB2:vb2_check_recovery() Recovery was requested manually
456 13:38:49.023687 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 13:38:49.023741 Recovery requested (1009000e)
458 13:38:49.023795 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 13:38:49.023849 tlcl_extend: response is 0
460 13:38:49.023903 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 13:38:49.023958 tlcl_extend: response is 0
462 13:38:49.024012 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 13:38:49.024067 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 13:38:49.024122 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 13:38:49.024181
466 13:38:49.024252
467 13:38:49.024308 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 13:38:49.024378 ARM64: Exception handlers installed.
469 13:38:49.024461 ARM64: Testing exception
470 13:38:49.024516 ARM64: Done test exception
471 13:38:49.024570 pmic_efuse_setting: Set efuses in 11 msecs
472 13:38:49.024625 pmwrap_interface_init: Select PMIF_VLD_RDY
473 13:38:49.024679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 13:38:49.024733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 13:38:49.025007 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 13:38:49.025074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 13:38:49.025131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 13:38:49.025187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 13:38:49.025243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 13:38:49.025308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 13:38:49.025366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 13:38:49.025422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 13:38:49.025491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 13:38:49.025546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 13:38:49.025602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 13:38:49.025656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 13:38:49.025711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 13:38:49.025766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 13:38:49.025821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 13:38:49.025875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 13:38:49.025930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 13:38:49.025984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 13:38:49.026039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 13:38:49.026094 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 13:38:49.026148 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 13:38:49.026203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 13:38:49.026257 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 13:38:49.026312 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 13:38:49.026366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 13:38:49.026422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 13:38:49.026476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 13:38:49.026531 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 13:38:49.026585 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 13:38:49.026640 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 13:38:49.026696 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 13:38:49.026750 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 13:38:49.026805 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 13:38:49.026859 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 13:38:49.026914 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 13:38:49.026969 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 13:38:49.027023 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 13:38:49.027077 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 13:38:49.027131 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 13:38:49.027186 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 13:38:49.027240 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 13:38:49.027295 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 13:38:49.027349 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 13:38:49.027403 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 13:38:49.027458 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 13:38:49.027512 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 13:38:49.027566 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 13:38:49.027620 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 13:38:49.027690 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 13:38:49.027759 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 13:38:49.027815 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 13:38:49.027870 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 13:38:49.027925 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 13:38:49.027980 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 13:38:49.028034 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 13:38:49.028088 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:38:49.028143 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:38:49.028212 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x28
533 13:38:49.028280 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 13:38:49.028335 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 13:38:49.028390 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 13:38:49.028445 [RTC]rtc_get_frequency_meter,154: input=15, output=773
537 13:38:49.028499 [RTC]rtc_get_frequency_meter,154: input=23, output=957
538 13:38:49.028554 [RTC]rtc_get_frequency_meter,154: input=19, output=866
539 13:38:49.028609 [RTC]rtc_get_frequency_meter,154: input=17, output=817
540 13:38:49.028663 [RTC]rtc_get_frequency_meter,154: input=16, output=795
541 13:38:49.028717 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 13:38:49.028771 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 13:38:49.028826 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 13:38:49.028880 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 13:38:49.029138 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 13:38:49.029201 ADC[4]: Raw value=902876 ID=7
547 13:38:49.029257 ADC[3]: Raw value=212810 ID=1
548 13:38:49.029323 RAM Code: 0x71
549 13:38:49.029381 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 13:38:49.029438 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 13:38:49.029495 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 13:38:49.029567 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 13:38:49.029621 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 13:38:49.029677 in-header: 03 07 00 00 08 00 00 00
555 13:38:49.029732 in-data: aa e4 47 04 13 02 00 00
556 13:38:49.029786 Chrome EC: UHEPI supported
557 13:38:49.029841 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 13:38:49.029896 in-header: 03 a9 00 00 08 00 00 00
559 13:38:49.029951 in-data: 84 60 60 08 00 00 00 00
560 13:38:49.030005 MRC: failed to locate region type 0.
561 13:38:49.030060 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 13:38:49.030115 DRAM-K: Running full calibration
563 13:38:49.030170 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 13:38:49.030242 header.status = 0x0
565 13:38:49.030357 header.version = 0x6 (expected: 0x6)
566 13:38:49.030413 header.size = 0xd00 (expected: 0xd00)
567 13:38:49.030480 header.flags = 0x0
568 13:38:49.030536 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 13:38:49.030591 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
570 13:38:49.030645 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 13:38:49.030700 dram_init: ddr_geometry: 2
572 13:38:49.030754 [EMI] MDL number = 2
573 13:38:49.030868 [EMI] Get MDL freq = 0
574 13:38:49.030922 dram_init: ddr_type: 0
575 13:38:49.030976 is_discrete_lpddr4: 1
576 13:38:49.031031 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 13:38:49.031085
578 13:38:49.031139
579 13:38:49.031193 [Bian_co] ETT version 0.0.0.1
580 13:38:49.031248 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 13:38:49.031303
582 13:38:49.031357 dramc_set_vcore_voltage set vcore to 650000
583 13:38:49.031412 Read voltage for 800, 4
584 13:38:49.031467 Vio18 = 0
585 13:38:49.031521 Vcore = 650000
586 13:38:49.031575 Vdram = 0
587 13:38:49.031630 Vddq = 0
588 13:38:49.031684 Vmddr = 0
589 13:38:49.031739 dram_init: config_dvfs: 1
590 13:38:49.031793 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 13:38:49.031848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 13:38:49.031903 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 13:38:49.031958 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 13:38:49.032015 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 13:38:49.032070 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 13:38:49.032125 MEM_TYPE=3, freq_sel=18
597 13:38:49.032180 sv_algorithm_assistance_LP4_1600
598 13:38:49.032234 ============ PULL DRAM RESETB DOWN ============
599 13:38:49.032292 ========== PULL DRAM RESETB DOWN end =========
600 13:38:49.032347 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 13:38:49.032401 ===================================
602 13:38:49.032456 LPDDR4 DRAM CONFIGURATION
603 13:38:49.032510 ===================================
604 13:38:49.032565 EX_ROW_EN[0] = 0x0
605 13:38:49.032619 EX_ROW_EN[1] = 0x0
606 13:38:49.032674 LP4Y_EN = 0x0
607 13:38:49.032729 WORK_FSP = 0x0
608 13:38:49.032783 WL = 0x2
609 13:38:49.032837 RL = 0x2
610 13:38:49.032891 BL = 0x2
611 13:38:49.032945 RPST = 0x0
612 13:38:49.032999 RD_PRE = 0x0
613 13:38:49.033053 WR_PRE = 0x1
614 13:38:49.033108 WR_PST = 0x0
615 13:38:49.033162 DBI_WR = 0x0
616 13:38:49.033216 DBI_RD = 0x0
617 13:38:49.033270 OTF = 0x1
618 13:38:49.033366 ===================================
619 13:38:49.033422 ===================================
620 13:38:49.033477 ANA top config
621 13:38:49.033530 ===================================
622 13:38:49.033585 DLL_ASYNC_EN = 0
623 13:38:49.033639 ALL_SLAVE_EN = 1
624 13:38:49.033693 NEW_RANK_MODE = 1
625 13:38:49.033748 DLL_IDLE_MODE = 1
626 13:38:49.033802 LP45_APHY_COMB_EN = 1
627 13:38:49.033856 TX_ODT_DIS = 1
628 13:38:49.033911 NEW_8X_MODE = 1
629 13:38:49.033965 ===================================
630 13:38:49.034035 ===================================
631 13:38:49.034103 data_rate = 1600
632 13:38:49.034157 CKR = 1
633 13:38:49.034211 DQ_P2S_RATIO = 8
634 13:38:49.034266 ===================================
635 13:38:49.034321 CA_P2S_RATIO = 8
636 13:38:49.034375 DQ_CA_OPEN = 0
637 13:38:49.034429 DQ_SEMI_OPEN = 0
638 13:38:49.034484 CA_SEMI_OPEN = 0
639 13:38:49.034538 CA_FULL_RATE = 0
640 13:38:49.034592 DQ_CKDIV4_EN = 1
641 13:38:49.034645 CA_CKDIV4_EN = 1
642 13:38:49.034699 CA_PREDIV_EN = 0
643 13:38:49.034753 PH8_DLY = 0
644 13:38:49.034807 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 13:38:49.034861 DQ_AAMCK_DIV = 4
646 13:38:49.034915 CA_AAMCK_DIV = 4
647 13:38:49.034968 CA_ADMCK_DIV = 4
648 13:38:49.035022 DQ_TRACK_CA_EN = 0
649 13:38:49.035076 CA_PICK = 800
650 13:38:49.035130 CA_MCKIO = 800
651 13:38:49.035184 MCKIO_SEMI = 0
652 13:38:49.035238 PLL_FREQ = 3068
653 13:38:49.035292 DQ_UI_PI_RATIO = 32
654 13:38:49.035347 CA_UI_PI_RATIO = 0
655 13:38:49.035402 ===================================
656 13:38:49.035457 ===================================
657 13:38:49.035511 memory_type:LPDDR4
658 13:38:49.035566 GP_NUM : 10
659 13:38:49.035620 SRAM_EN : 1
660 13:38:49.035675 MD32_EN : 0
661 13:38:49.035728 ===================================
662 13:38:49.035783 [ANA_INIT] >>>>>>>>>>>>>>
663 13:38:49.035837 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 13:38:49.035894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 13:38:49.035948 ===================================
666 13:38:49.036233 data_rate = 1600,PCW = 0X7600
667 13:38:49.036311 ===================================
668 13:38:49.036367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:38:49.036423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 13:38:49.036479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 13:38:49.036534 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 13:38:49.036589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 13:38:49.036644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 13:38:49.036699 [ANA_INIT] flow start
675 13:38:49.036754 [ANA_INIT] PLL >>>>>>>>
676 13:38:49.036808 [ANA_INIT] PLL <<<<<<<<
677 13:38:49.036862 [ANA_INIT] MIDPI >>>>>>>>
678 13:38:49.036916 [ANA_INIT] MIDPI <<<<<<<<
679 13:38:49.036970 [ANA_INIT] DLL >>>>>>>>
680 13:38:49.037024 [ANA_INIT] flow end
681 13:38:49.037079 ============ LP4 DIFF to SE enter ============
682 13:38:49.037134 ============ LP4 DIFF to SE exit ============
683 13:38:49.037206 [ANA_INIT] <<<<<<<<<<<<<
684 13:38:49.037262 [Flow] Enable top DCM control >>>>>
685 13:38:49.037349 [Flow] Enable top DCM control <<<<<
686 13:38:49.037407 Enable DLL master slave shuffle
687 13:38:49.037462 ==============================================================
688 13:38:49.037518 Gating Mode config
689 13:38:49.037573 ==============================================================
690 13:38:49.037628 Config description:
691 13:38:49.037682 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 13:38:49.037739 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 13:38:49.037794 SELPH_MODE 0: By rank 1: By Phase
694 13:38:49.037849 ==============================================================
695 13:38:49.037905 GAT_TRACK_EN = 1
696 13:38:49.037960 RX_GATING_MODE = 2
697 13:38:49.038014 RX_GATING_TRACK_MODE = 2
698 13:38:49.038068 SELPH_MODE = 1
699 13:38:49.038122 PICG_EARLY_EN = 1
700 13:38:49.038176 VALID_LAT_VALUE = 1
701 13:38:49.038249 ==============================================================
702 13:38:49.038324 Enter into Gating configuration >>>>
703 13:38:49.038398 Exit from Gating configuration <<<<
704 13:38:49.038456 Enter into DVFS_PRE_config >>>>>
705 13:38:49.038513 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 13:38:49.038574 Exit from DVFS_PRE_config <<<<<
707 13:38:49.038630 Enter into PICG configuration >>>>
708 13:38:49.038685 Exit from PICG configuration <<<<
709 13:38:49.038739 [RX_INPUT] configuration >>>>>
710 13:38:49.038794 [RX_INPUT] configuration <<<<<
711 13:38:49.038849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 13:38:49.038904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 13:38:49.038959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 13:38:49.039015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 13:38:49.039087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 13:38:49.039155 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 13:38:49.039210 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 13:38:49.039265 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 13:38:49.039319 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 13:38:49.039373 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 13:38:49.039427 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 13:38:49.039481 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 13:38:49.039536 ===================================
724 13:38:49.039591 LPDDR4 DRAM CONFIGURATION
725 13:38:49.039646 ===================================
726 13:38:49.039701 EX_ROW_EN[0] = 0x0
727 13:38:49.039755 EX_ROW_EN[1] = 0x0
728 13:38:49.039809 LP4Y_EN = 0x0
729 13:38:49.039864 WORK_FSP = 0x0
730 13:38:49.039918 WL = 0x2
731 13:38:49.039972 RL = 0x2
732 13:38:49.040027 BL = 0x2
733 13:38:49.040081 RPST = 0x0
734 13:38:49.040135 RD_PRE = 0x0
735 13:38:49.040190 WR_PRE = 0x1
736 13:38:49.040281 WR_PST = 0x0
737 13:38:49.040336 DBI_WR = 0x0
738 13:38:49.040390 DBI_RD = 0x0
739 13:38:49.040444 OTF = 0x1
740 13:38:49.040499 ===================================
741 13:38:49.040553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 13:38:49.040608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 13:38:49.040662 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 13:38:49.040717 ===================================
745 13:38:49.040809 LPDDR4 DRAM CONFIGURATION
746 13:38:49.040863 ===================================
747 13:38:49.040917 EX_ROW_EN[0] = 0x10
748 13:38:49.040971 EX_ROW_EN[1] = 0x0
749 13:38:49.041025 LP4Y_EN = 0x0
750 13:38:49.041079 WORK_FSP = 0x0
751 13:38:49.041133 WL = 0x2
752 13:38:49.041187 RL = 0x2
753 13:38:49.041241 BL = 0x2
754 13:38:49.041299 RPST = 0x0
755 13:38:49.041388 RD_PRE = 0x0
756 13:38:49.041443 WR_PRE = 0x1
757 13:38:49.041497 WR_PST = 0x0
758 13:38:49.041552 DBI_WR = 0x0
759 13:38:49.041605 DBI_RD = 0x0
760 13:38:49.041659 OTF = 0x1
761 13:38:49.041714 ===================================
762 13:38:49.041769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 13:38:49.041824 nWR fixed to 40
764 13:38:49.041879 [ModeRegInit_LP4] CH0 RK0
765 13:38:49.041934 [ModeRegInit_LP4] CH0 RK1
766 13:38:49.041988 [ModeRegInit_LP4] CH1 RK0
767 13:38:49.042042 [ModeRegInit_LP4] CH1 RK1
768 13:38:49.042115 match AC timing 13
769 13:38:49.042183 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 13:38:49.042237 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 13:38:49.042292 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 13:38:49.042346 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 13:38:49.042604 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 13:38:49.042709 [EMI DOE] emi_dcm 0
775 13:38:49.042815 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 13:38:49.042920 ==
777 13:38:49.043025 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:38:49.043130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:38:49.043235 ==
780 13:38:49.043341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 13:38:49.043448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 13:38:49.043553 [CA 0] Center 38 (7~69) winsize 63
783 13:38:49.043658 [CA 1] Center 38 (7~69) winsize 63
784 13:38:49.043754 [CA 2] Center 35 (5~66) winsize 62
785 13:38:49.043874 [CA 3] Center 35 (5~66) winsize 62
786 13:38:49.043961 [CA 4] Center 35 (4~66) winsize 63
787 13:38:49.044046 [CA 5] Center 33 (3~64) winsize 62
788 13:38:49.044130
789 13:38:49.044231 [CmdBusTrainingLP45] Vref(ca) range 1: 32
790 13:38:49.044359
791 13:38:49.044443 [CATrainingPosCal] consider 1 rank data
792 13:38:49.044528 u2DelayCellTimex100 = 270/100 ps
793 13:38:49.044613 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 13:38:49.044699 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 13:38:49.044784 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 13:38:49.044871 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 13:38:49.044956 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
798 13:38:49.045041 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 13:38:49.045125
800 13:38:49.045209 CA PerBit enable=1, Macro0, CA PI delay=33
801 13:38:49.045293
802 13:38:49.045391 [CBTSetCACLKResult] CA Dly = 33
803 13:38:49.045447 CS Dly: 6 (0~37)
804 13:38:49.045501 ==
805 13:38:49.045556 Dram Type= 6, Freq= 0, CH_0, rank 1
806 13:38:49.045611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 13:38:49.045666 ==
808 13:38:49.045721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 13:38:49.045805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 13:38:49.045860 [CA 0] Center 38 (7~69) winsize 63
811 13:38:49.045915 [CA 1] Center 38 (7~69) winsize 63
812 13:38:49.045970 [CA 2] Center 35 (5~66) winsize 62
813 13:38:49.046024 [CA 3] Center 35 (5~66) winsize 62
814 13:38:49.046079 [CA 4] Center 35 (4~66) winsize 63
815 13:38:49.046133 [CA 5] Center 34 (4~65) winsize 62
816 13:38:49.046187
817 13:38:49.046272 [CmdBusTrainingLP45] Vref(ca) range 1: 32
818 13:38:49.046326
819 13:38:49.046381 [CATrainingPosCal] consider 2 rank data
820 13:38:49.046435 u2DelayCellTimex100 = 270/100 ps
821 13:38:49.046489 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 13:38:49.046544 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
823 13:38:49.046598 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
824 13:38:49.046653 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 13:38:49.046724 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
826 13:38:49.046792 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 13:38:49.046846
828 13:38:49.046899 CA PerBit enable=1, Macro0, CA PI delay=34
829 13:38:49.046954
830 13:38:49.047008 [CBTSetCACLKResult] CA Dly = 34
831 13:38:49.047062 CS Dly: 6 (0~38)
832 13:38:49.047116
833 13:38:49.047170 ----->DramcWriteLeveling(PI) begin...
834 13:38:49.047226 ==
835 13:38:49.047281 Dram Type= 6, Freq= 0, CH_0, rank 0
836 13:38:49.047336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 13:38:49.047395 ==
838 13:38:49.047487 Write leveling (Byte 0): 31 => 31
839 13:38:49.047595 Write leveling (Byte 1): 29 => 29
840 13:38:49.047701 DramcWriteLeveling(PI) end<-----
841 13:38:49.047806
842 13:38:49.047910 ==
843 13:38:49.048017 Dram Type= 6, Freq= 0, CH_0, rank 0
844 13:38:49.048116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 13:38:49.048222 ==
846 13:38:49.048323 [Gating] SW mode calibration
847 13:38:49.048451 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 13:38:49.048564 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 13:38:49.048654 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 13:38:49.048741 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
851 13:38:49.048828 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 13:38:49.048914 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:38:49.049000 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:38:49.049091 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:38:49.049179 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:38:49.049265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:38:49.049391 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:38:49.049477 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:38:49.049562 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:38:49.049649 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:38:49.049734 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:38:49.049819 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:38:49.049904 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:38:49.050005 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:38:49.050105 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
866 13:38:49.050226 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
867 13:38:49.050301 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
868 13:38:49.050375 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:38:49.050462 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:38:49.050549 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:38:49.050618 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:38:49.050672 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:38:49.050727 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:38:49.050782 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
875 13:38:49.050837 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
876 13:38:49.050892 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
877 13:38:49.050947 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 13:38:49.051001 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 13:38:49.051056 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:38:49.051110 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:38:49.051383 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:38:49.051460 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
883 13:38:49.051516 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
884 13:38:49.051573 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
885 13:38:49.051629 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 13:38:49.051684 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 13:38:49.051754 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:38:49.051822 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:38:49.051891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:38:49.051975 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
891 13:38:49.052042 0 11 8 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
892 13:38:49.052097 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
893 13:38:49.052166 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 13:38:49.052250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 13:38:49.052318 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:38:49.052373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:38:49.052441 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:38:49.052497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
899 13:38:49.052552 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 13:38:49.052608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:38:49.052664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:38:49.052731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:38:49.052785 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:38:49.052881 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:38:49.052951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:38:49.053019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:38:49.053075 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:38:49.053131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:38:49.053187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:38:49.053242 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:38:49.053307 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:38:49.053397 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:38:49.053466 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
914 13:38:49.053520 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
915 13:38:49.053589 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 13:38:49.053657 Total UI for P1: 0, mck2ui 16
917 13:38:49.053740 best dqsien dly found for B0: ( 0, 14, 2)
918 13:38:49.053823 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 13:38:49.053877 Total UI for P1: 0, mck2ui 16
920 13:38:49.053932 best dqsien dly found for B1: ( 0, 14, 6)
921 13:38:49.054014 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
922 13:38:49.054068 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
923 13:38:49.054122
924 13:38:49.054204 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
925 13:38:49.054259 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 13:38:49.054313 [Gating] SW calibration Done
927 13:38:49.054381 ==
928 13:38:49.054449 Dram Type= 6, Freq= 0, CH_0, rank 0
929 13:38:49.054503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 13:38:49.054586 ==
931 13:38:49.054640 RX Vref Scan: 0
932 13:38:49.054694
933 13:38:49.054762 RX Vref 0 -> 0, step: 1
934 13:38:49.054816
935 13:38:49.054872 RX Delay -130 -> 252, step: 16
936 13:38:49.054955 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
937 13:38:49.055024 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 13:38:49.055092 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
939 13:38:49.055161 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
940 13:38:49.055242 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 13:38:49.055310 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 13:38:49.055377 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 13:38:49.055432 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 13:38:49.055486 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 13:38:49.055584 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
946 13:38:49.055640 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
947 13:38:49.055708 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 13:38:49.055762 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
949 13:38:49.055821 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 13:38:49.055875 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 13:38:49.055929 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
952 13:38:49.055983 ==
953 13:38:49.056037 Dram Type= 6, Freq= 0, CH_0, rank 0
954 13:38:49.056091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 13:38:49.056146 ==
956 13:38:49.056200 DQS Delay:
957 13:38:49.056254 DQS0 = 0, DQS1 = 0
958 13:38:49.056308 DQM Delay:
959 13:38:49.056361 DQM0 = 93, DQM1 = 81
960 13:38:49.056415 DQ Delay:
961 13:38:49.056469 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
962 13:38:49.056523 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 13:38:49.056582 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
964 13:38:49.056636 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
965 13:38:49.056691
966 13:38:49.056760
967 13:38:49.056815 ==
968 13:38:49.056899 Dram Type= 6, Freq= 0, CH_0, rank 0
969 13:38:49.056982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 13:38:49.057067 ==
971 13:38:49.057135
972 13:38:49.057204
973 13:38:49.057258 TX Vref Scan disable
974 13:38:49.057331 == TX Byte 0 ==
975 13:38:49.057389 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
976 13:38:49.057449 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
977 13:38:49.057505 == TX Byte 1 ==
978 13:38:49.057560 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
979 13:38:49.057616 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
980 13:38:49.057671 ==
981 13:38:49.057727 Dram Type= 6, Freq= 0, CH_0, rank 0
982 13:38:49.057783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 13:38:49.057845 ==
984 13:38:49.057902 TX Vref=22, minBit 11, minWin=26, winSum=438
985 13:38:49.057959 TX Vref=24, minBit 8, minWin=27, winSum=449
986 13:38:49.058015 TX Vref=26, minBit 8, minWin=27, winSum=452
987 13:38:49.058071 TX Vref=28, minBit 12, minWin=27, winSum=452
988 13:38:49.058127 TX Vref=30, minBit 5, minWin=28, winSum=458
989 13:38:49.058384 TX Vref=32, minBit 8, minWin=27, winSum=452
990 13:38:49.058448 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
991 13:38:49.058506
992 13:38:49.058562 Final TX Range 1 Vref 30
993 13:38:49.058619
994 13:38:49.058675 ==
995 13:38:49.058731 Dram Type= 6, Freq= 0, CH_0, rank 0
996 13:38:49.058787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 13:38:49.058843 ==
998 13:38:49.058899
999 13:38:49.058954
1000 13:38:49.059009 TX Vref Scan disable
1001 13:38:49.059064 == TX Byte 0 ==
1002 13:38:49.059120 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1003 13:38:49.059176 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1004 13:38:49.059232 == TX Byte 1 ==
1005 13:38:49.059288 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1006 13:38:49.059343 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1007 13:38:49.059398
1008 13:38:49.059453 [DATLAT]
1009 13:38:49.059508 Freq=800, CH0 RK0
1010 13:38:49.059563
1011 13:38:49.059618 DATLAT Default: 0xa
1012 13:38:49.059675 0, 0xFFFF, sum = 0
1013 13:38:49.059731 1, 0xFFFF, sum = 0
1014 13:38:49.059788 2, 0xFFFF, sum = 0
1015 13:38:49.059859 3, 0xFFFF, sum = 0
1016 13:38:49.059918 4, 0xFFFF, sum = 0
1017 13:38:49.059974 5, 0xFFFF, sum = 0
1018 13:38:49.060030 6, 0xFFFF, sum = 0
1019 13:38:49.060085 7, 0xFFFF, sum = 0
1020 13:38:49.060141 8, 0xFFFF, sum = 0
1021 13:38:49.060196 9, 0x0, sum = 1
1022 13:38:49.060252 10, 0x0, sum = 2
1023 13:38:49.060309 11, 0x0, sum = 3
1024 13:38:49.060366 12, 0x0, sum = 4
1025 13:38:49.060428 best_step = 10
1026 13:38:49.060487
1027 13:38:49.060543 ==
1028 13:38:49.060599 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 13:38:49.060654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 13:38:49.060710 ==
1031 13:38:49.060766 RX Vref Scan: 1
1032 13:38:49.060821
1033 13:38:49.060876 Set Vref Range= 32 -> 127
1034 13:38:49.060931
1035 13:38:49.060985 RX Vref 32 -> 127, step: 1
1036 13:38:49.061040
1037 13:38:49.061094 RX Delay -95 -> 252, step: 8
1038 13:38:49.061149
1039 13:38:49.061203 Set Vref, RX VrefLevel [Byte0]: 32
1040 13:38:49.061258 [Byte1]: 32
1041 13:38:49.061337
1042 13:38:49.061392 Set Vref, RX VrefLevel [Byte0]: 33
1043 13:38:49.061446 [Byte1]: 33
1044 13:38:49.061500
1045 13:38:49.061571 Set Vref, RX VrefLevel [Byte0]: 34
1046 13:38:49.061626 [Byte1]: 34
1047 13:38:49.061681
1048 13:38:49.061735 Set Vref, RX VrefLevel [Byte0]: 35
1049 13:38:49.061790 [Byte1]: 35
1050 13:38:49.061851
1051 13:38:49.061907 Set Vref, RX VrefLevel [Byte0]: 36
1052 13:38:49.061975 [Byte1]: 36
1053 13:38:49.062029
1054 13:38:49.062083 Set Vref, RX VrefLevel [Byte0]: 37
1055 13:38:49.062136 [Byte1]: 37
1056 13:38:49.062190
1057 13:38:49.062244 Set Vref, RX VrefLevel [Byte0]: 38
1058 13:38:49.062297 [Byte1]: 38
1059 13:38:49.062351
1060 13:38:49.062404 Set Vref, RX VrefLevel [Byte0]: 39
1061 13:38:49.062457 [Byte1]: 39
1062 13:38:49.062511
1063 13:38:49.062564 Set Vref, RX VrefLevel [Byte0]: 40
1064 13:38:49.062617 [Byte1]: 40
1065 13:38:49.062670
1066 13:38:49.062723 Set Vref, RX VrefLevel [Byte0]: 41
1067 13:38:49.062777 [Byte1]: 41
1068 13:38:49.062830
1069 13:38:49.062883 Set Vref, RX VrefLevel [Byte0]: 42
1070 13:38:49.062937 [Byte1]: 42
1071 13:38:49.062991
1072 13:38:49.063044 Set Vref, RX VrefLevel [Byte0]: 43
1073 13:38:49.063098 [Byte1]: 43
1074 13:38:49.063152
1075 13:38:49.063205 Set Vref, RX VrefLevel [Byte0]: 44
1076 13:38:49.063258 [Byte1]: 44
1077 13:38:49.063311
1078 13:38:49.063364 Set Vref, RX VrefLevel [Byte0]: 45
1079 13:38:49.063417 [Byte1]: 45
1080 13:38:49.063470
1081 13:38:49.063523 Set Vref, RX VrefLevel [Byte0]: 46
1082 13:38:49.063577 [Byte1]: 46
1083 13:38:49.063630
1084 13:38:49.063683 Set Vref, RX VrefLevel [Byte0]: 47
1085 13:38:49.063736 [Byte1]: 47
1086 13:38:49.063789
1087 13:38:49.063892 Set Vref, RX VrefLevel [Byte0]: 48
1088 13:38:49.063981 [Byte1]: 48
1089 13:38:49.064073
1090 13:38:49.064132 Set Vref, RX VrefLevel [Byte0]: 49
1091 13:38:49.064187 [Byte1]: 49
1092 13:38:49.064242
1093 13:38:49.064296 Set Vref, RX VrefLevel [Byte0]: 50
1094 13:38:49.064350 [Byte1]: 50
1095 13:38:49.064404
1096 13:38:49.064473 Set Vref, RX VrefLevel [Byte0]: 51
1097 13:38:49.064541 [Byte1]: 51
1098 13:38:49.064595
1099 13:38:49.064648 Set Vref, RX VrefLevel [Byte0]: 52
1100 13:38:49.064701 [Byte1]: 52
1101 13:38:49.064754
1102 13:38:49.064808 Set Vref, RX VrefLevel [Byte0]: 53
1103 13:38:49.064862 [Byte1]: 53
1104 13:38:49.064916
1105 13:38:49.064969 Set Vref, RX VrefLevel [Byte0]: 54
1106 13:38:49.065022 [Byte1]: 54
1107 13:38:49.065093
1108 13:38:49.065161 Set Vref, RX VrefLevel [Byte0]: 55
1109 13:38:49.065215 [Byte1]: 55
1110 13:38:49.065268
1111 13:38:49.065359 Set Vref, RX VrefLevel [Byte0]: 56
1112 13:38:49.065414 [Byte1]: 56
1113 13:38:49.065468
1114 13:38:49.065521 Set Vref, RX VrefLevel [Byte0]: 57
1115 13:38:49.065575 [Byte1]: 57
1116 13:38:49.065628
1117 13:38:49.065682 Set Vref, RX VrefLevel [Byte0]: 58
1118 13:38:49.065735 [Byte1]: 58
1119 13:38:49.065789
1120 13:38:49.065842 Set Vref, RX VrefLevel [Byte0]: 59
1121 13:38:49.065912 [Byte1]: 59
1122 13:38:49.065980
1123 13:38:49.066034 Set Vref, RX VrefLevel [Byte0]: 60
1124 13:38:49.066087 [Byte1]: 60
1125 13:38:49.066140
1126 13:38:49.066193 Set Vref, RX VrefLevel [Byte0]: 61
1127 13:38:49.066246 [Byte1]: 61
1128 13:38:49.066299
1129 13:38:49.066352 Set Vref, RX VrefLevel [Byte0]: 62
1130 13:38:49.066405 [Byte1]: 62
1131 13:38:49.066459
1132 13:38:49.066512 Set Vref, RX VrefLevel [Byte0]: 63
1133 13:38:49.066581 [Byte1]: 63
1134 13:38:49.066648
1135 13:38:49.066701 Set Vref, RX VrefLevel [Byte0]: 64
1136 13:38:49.066754 [Byte1]: 64
1137 13:38:49.066808
1138 13:38:49.066861 Set Vref, RX VrefLevel [Byte0]: 65
1139 13:38:49.066914 [Byte1]: 65
1140 13:38:49.066967
1141 13:38:49.067020 Set Vref, RX VrefLevel [Byte0]: 66
1142 13:38:49.067074 [Byte1]: 66
1143 13:38:49.067128
1144 13:38:49.067197 Set Vref, RX VrefLevel [Byte0]: 67
1145 13:38:49.067264 [Byte1]: 67
1146 13:38:49.067332
1147 13:38:49.067386 Set Vref, RX VrefLevel [Byte0]: 68
1148 13:38:49.067440 [Byte1]: 68
1149 13:38:49.067493
1150 13:38:49.067546 Set Vref, RX VrefLevel [Byte0]: 69
1151 13:38:49.067600 [Byte1]: 69
1152 13:38:49.067653
1153 13:38:49.067706 Set Vref, RX VrefLevel [Byte0]: 70
1154 13:38:49.067759 [Byte1]: 70
1155 13:38:49.067842
1156 13:38:49.067896 Set Vref, RX VrefLevel [Byte0]: 71
1157 13:38:49.067950 [Byte1]: 71
1158 13:38:49.068003
1159 13:38:49.068056 Set Vref, RX VrefLevel [Byte0]: 72
1160 13:38:49.068313 [Byte1]: 72
1161 13:38:49.068378
1162 13:38:49.068449 Set Vref, RX VrefLevel [Byte0]: 73
1163 13:38:49.068506 [Byte1]: 73
1164 13:38:49.068562
1165 13:38:49.068645 Set Vref, RX VrefLevel [Byte0]: 74
1166 13:38:49.068713 [Byte1]: 74
1167 13:38:49.068784
1168 13:38:49.068869 Set Vref, RX VrefLevel [Byte0]: 75
1169 13:38:49.068950 [Byte1]: 75
1170 13:38:49.069004
1171 13:38:49.069059 Set Vref, RX VrefLevel [Byte0]: 76
1172 13:38:49.069114 [Byte1]: 76
1173 13:38:49.069169
1174 13:38:49.069224 Set Vref, RX VrefLevel [Byte0]: 77
1175 13:38:49.069279 [Byte1]: 77
1176 13:38:49.069353
1177 13:38:49.069410 Set Vref, RX VrefLevel [Byte0]: 78
1178 13:38:49.069465 [Byte1]: 78
1179 13:38:49.069520
1180 13:38:49.069574 Set Vref, RX VrefLevel [Byte0]: 79
1181 13:38:49.069629 [Byte1]: 79
1182 13:38:49.069684
1183 13:38:49.069739 Final RX Vref Byte 0 = 63 to rank0
1184 13:38:49.069794 Final RX Vref Byte 1 = 60 to rank0
1185 13:38:49.069849 Final RX Vref Byte 0 = 63 to rank1
1186 13:38:49.069904 Final RX Vref Byte 1 = 60 to rank1==
1187 13:38:49.069960 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 13:38:49.070015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 13:38:49.070070 ==
1190 13:38:49.070125 DQS Delay:
1191 13:38:49.070180 DQS0 = 0, DQS1 = 0
1192 13:38:49.070234 DQM Delay:
1193 13:38:49.070289 DQM0 = 93, DQM1 = 81
1194 13:38:49.070343 DQ Delay:
1195 13:38:49.070398 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1196 13:38:49.070453 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1197 13:38:49.070508 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1198 13:38:49.070562 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1199 13:38:49.070617
1200 13:38:49.070672
1201 13:38:49.070727 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 393 ps
1202 13:38:49.070783 CH0 RK0: MR19=606, MR18=3F3A
1203 13:38:49.070839 CH0_RK0: MR19=0x606, MR18=0x3F3A, DQSOSC=393, MR23=63, INC=95, DEC=63
1204 13:38:49.070894
1205 13:38:49.070948 ----->DramcWriteLeveling(PI) begin...
1206 13:38:49.071005 ==
1207 13:38:49.071060 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 13:38:49.071114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 13:38:49.071170 ==
1210 13:38:49.071224 Write leveling (Byte 0): 33 => 33
1211 13:38:49.071280 Write leveling (Byte 1): 27 => 27
1212 13:38:49.071335 DramcWriteLeveling(PI) end<-----
1213 13:38:49.071389
1214 13:38:49.071444 ==
1215 13:38:49.071498 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 13:38:49.071553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 13:38:49.071608 ==
1218 13:38:49.071663 [Gating] SW mode calibration
1219 13:38:49.071718 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 13:38:49.071774 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 13:38:49.071829 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1222 13:38:49.071884 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1223 13:38:49.071940 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1224 13:38:49.071995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:38:49.072051 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:38:49.072106 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:38:49.072162 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:38:49.072217 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:38:49.072271 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:38:49.072327 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:38:49.072382 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:38:49.072438 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:38:49.072493 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 13:38:49.072548 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 13:38:49.072603 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:38:49.072658 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:38:49.072714 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:38:49.072769 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1239 13:38:49.072824 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:38:49.072879 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:38:49.072935 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:38:49.072990 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 13:38:49.073045 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 13:38:49.073100 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 13:38:49.073154 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 13:38:49.073209 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1247 13:38:49.073264 0 9 8 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
1248 13:38:49.073333 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:38:49.073389 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 13:38:49.073444 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 13:38:49.073499 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 13:38:49.073554 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 13:38:49.073609 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 13:38:49.073663 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
1255 13:38:49.073718 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1256 13:38:49.073772 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:38:49.073828 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:38:49.073882 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 13:38:49.073937 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 13:38:49.073992 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 13:38:49.074047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 13:38:49.074102 0 11 4 | B1->B0 | 2424 3332 | 0 1 | (0 0) (0 0)
1263 13:38:49.074157 0 11 8 | B1->B0 | 3d3d 4545 | 1 0 | (1 1) (0 0)
1264 13:38:49.074212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:38:49.074267 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 13:38:49.074322 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 13:38:49.074574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 13:38:49.074637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 13:38:49.074693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 13:38:49.074749 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 13:38:49.074804 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1272 13:38:49.074862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:38:49.074919 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:38:49.074973 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:38:49.075028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:38:49.075084 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:38:49.075139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:38:49.075194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:38:49.075249 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:38:49.075304 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:38:49.075359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:38:49.075414 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 13:38:49.075470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 13:38:49.075524 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 13:38:49.075579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 13:38:49.075634 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1287 13:38:49.075689 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 13:38:49.075743 Total UI for P1: 0, mck2ui 16
1289 13:38:49.075799 best dqsien dly found for B0: ( 0, 14, 4)
1290 13:38:49.075854 Total UI for P1: 0, mck2ui 16
1291 13:38:49.075909 best dqsien dly found for B1: ( 0, 14, 6)
1292 13:38:49.075964 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1293 13:38:49.076020 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1294 13:38:49.076074
1295 13:38:49.076128 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1296 13:38:49.076183 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1297 13:38:49.076239 [Gating] SW calibration Done
1298 13:38:49.076294 ==
1299 13:38:49.076349 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 13:38:49.076404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 13:38:49.076459 ==
1302 13:38:49.076514 RX Vref Scan: 0
1303 13:38:49.076569
1304 13:38:49.076623 RX Vref 0 -> 0, step: 1
1305 13:38:49.076677
1306 13:38:49.076732 RX Delay -130 -> 252, step: 16
1307 13:38:49.076788 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1308 13:38:49.076843 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1309 13:38:49.076898 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1310 13:38:49.076953 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1311 13:38:49.077008 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1312 13:38:49.077063 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1313 13:38:49.077118 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1314 13:38:49.077172 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1315 13:38:49.077227 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1316 13:38:49.077282 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1317 13:38:49.077348 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1318 13:38:49.077403 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1319 13:38:49.077458 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1320 13:38:49.077513 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1321 13:38:49.077568 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1322 13:38:49.077622 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1323 13:38:49.077678 ==
1324 13:38:49.077733 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 13:38:49.077787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 13:38:49.077843 ==
1327 13:38:49.077897 DQS Delay:
1328 13:38:49.077951 DQS0 = 0, DQS1 = 0
1329 13:38:49.078006 DQM Delay:
1330 13:38:49.078061 DQM0 = 90, DQM1 = 80
1331 13:38:49.078115 DQ Delay:
1332 13:38:49.078170 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1333 13:38:49.078225 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1334 13:38:49.078280 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1335 13:38:49.078334 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1336 13:38:49.078389
1337 13:38:49.078443
1338 13:38:49.078498 ==
1339 13:38:49.078552 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 13:38:49.078607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 13:38:49.078662 ==
1342 13:38:49.078716
1343 13:38:49.078771
1344 13:38:49.078826 TX Vref Scan disable
1345 13:38:49.078881 == TX Byte 0 ==
1346 13:38:49.078935 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1347 13:38:49.078991 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1348 13:38:49.079046 == TX Byte 1 ==
1349 13:38:49.079100 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1350 13:38:49.079154 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1351 13:38:49.079209 ==
1352 13:38:49.079264 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 13:38:49.079319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 13:38:49.079373 ==
1355 13:38:49.079428 TX Vref=22, minBit 8, minWin=27, winSum=448
1356 13:38:49.079484 TX Vref=24, minBit 8, minWin=27, winSum=453
1357 13:38:49.079539 TX Vref=26, minBit 8, minWin=27, winSum=453
1358 13:38:49.079593 TX Vref=28, minBit 8, minWin=27, winSum=455
1359 13:38:49.079648 TX Vref=30, minBit 8, minWin=27, winSum=458
1360 13:38:49.079703 TX Vref=32, minBit 6, minWin=28, winSum=459
1361 13:38:49.079758 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 32
1362 13:38:49.079811
1363 13:38:49.079864 Final TX Range 1 Vref 32
1364 13:38:49.079918
1365 13:38:49.079971 ==
1366 13:38:49.080025 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 13:38:49.080078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 13:38:49.080132 ==
1369 13:38:49.080185
1370 13:38:49.080237
1371 13:38:49.080290 TX Vref Scan disable
1372 13:38:49.080343 == TX Byte 0 ==
1373 13:38:49.080397 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1374 13:38:49.080451 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1375 13:38:49.080504 == TX Byte 1 ==
1376 13:38:49.080557 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1377 13:38:49.080611 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1378 13:38:49.080664
1379 13:38:49.080717 [DATLAT]
1380 13:38:49.080770 Freq=800, CH0 RK1
1381 13:38:49.080824
1382 13:38:49.080876 DATLAT Default: 0xa
1383 13:38:49.080929 0, 0xFFFF, sum = 0
1384 13:38:49.080983 1, 0xFFFF, sum = 0
1385 13:38:49.081037 2, 0xFFFF, sum = 0
1386 13:38:49.081092 3, 0xFFFF, sum = 0
1387 13:38:49.081145 4, 0xFFFF, sum = 0
1388 13:38:49.081198 5, 0xFFFF, sum = 0
1389 13:38:49.081252 6, 0xFFFF, sum = 0
1390 13:38:49.081316 7, 0xFFFF, sum = 0
1391 13:38:49.081372 8, 0xFFFF, sum = 0
1392 13:38:49.081426 9, 0x0, sum = 1
1393 13:38:49.081480 10, 0x0, sum = 2
1394 13:38:49.081534 11, 0x0, sum = 3
1395 13:38:49.081784 12, 0x0, sum = 4
1396 13:38:49.081845 best_step = 10
1397 13:38:49.081900
1398 13:38:49.081954 ==
1399 13:38:49.082006 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 13:38:49.082064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 13:38:49.082164 ==
1402 13:38:49.082264 RX Vref Scan: 0
1403 13:38:49.082349
1404 13:38:49.082432 RX Vref 0 -> 0, step: 1
1405 13:38:49.082516
1406 13:38:49.082599 RX Delay -95 -> 252, step: 8
1407 13:38:49.082683 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1408 13:38:49.082767 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1409 13:38:49.082851 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1410 13:38:49.082934 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1411 13:38:49.083018 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1412 13:38:49.083101 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1413 13:38:49.083185 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1414 13:38:49.083268 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 13:38:49.083351 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1416 13:38:49.083435 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1417 13:38:49.083518 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1418 13:38:49.083592 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1419 13:38:49.083653 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1420 13:38:49.083707 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1421 13:38:49.083761 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 13:38:49.083815 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1423 13:38:49.083869 ==
1424 13:38:49.083922 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 13:38:49.083976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 13:38:49.084030 ==
1427 13:38:49.084084 DQS Delay:
1428 13:38:49.084137 DQS0 = 0, DQS1 = 0
1429 13:38:49.084190 DQM Delay:
1430 13:38:49.084243 DQM0 = 90, DQM1 = 81
1431 13:38:49.084296 DQ Delay:
1432 13:38:49.084349 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1433 13:38:49.084402 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1434 13:38:49.084456 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1435 13:38:49.084509 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1436 13:38:49.084563
1437 13:38:49.084616
1438 13:38:49.084668 [DQSOSCAuto] RK1, (LSB)MR18= 0x441e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1439 13:38:49.084723 CH0 RK1: MR19=606, MR18=441E
1440 13:38:49.084776 CH0_RK1: MR19=0x606, MR18=0x441E, DQSOSC=392, MR23=63, INC=96, DEC=64
1441 13:38:49.084830 [RxdqsGatingPostProcess] freq 800
1442 13:38:49.084888 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 13:38:49.084944 Pre-setting of DQS Precalculation
1444 13:38:49.084998 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 13:38:49.085052 ==
1446 13:38:49.085105 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 13:38:49.085158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 13:38:49.085211 ==
1449 13:38:49.085264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 13:38:49.085328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 13:38:49.085383 [CA 0] Center 36 (6~67) winsize 62
1452 13:38:49.085437 [CA 1] Center 37 (6~68) winsize 63
1453 13:38:49.085491 [CA 2] Center 35 (5~65) winsize 61
1454 13:38:49.085544 [CA 3] Center 34 (4~65) winsize 62
1455 13:38:49.085596 [CA 4] Center 34 (4~64) winsize 61
1456 13:38:49.085649 [CA 5] Center 34 (3~65) winsize 63
1457 13:38:49.085702
1458 13:38:49.085754 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1459 13:38:49.085807
1460 13:38:49.085859 [CATrainingPosCal] consider 1 rank data
1461 13:38:49.085913 u2DelayCellTimex100 = 270/100 ps
1462 13:38:49.085966 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 13:38:49.086020 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1464 13:38:49.086073 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 13:38:49.086126 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 13:38:49.086192 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 13:38:49.086249 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1468 13:38:49.086302
1469 13:38:49.086356 CA PerBit enable=1, Macro0, CA PI delay=34
1470 13:38:49.086409
1471 13:38:49.086462 [CBTSetCACLKResult] CA Dly = 34
1472 13:38:49.086516 CS Dly: 5 (0~36)
1473 13:38:49.086569 ==
1474 13:38:49.086622 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 13:38:49.086676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 13:38:49.086729 ==
1477 13:38:49.086782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 13:38:49.086836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 13:38:49.086894 [CA 0] Center 37 (7~68) winsize 62
1480 13:38:49.086952 [CA 1] Center 37 (6~68) winsize 63
1481 13:38:49.087007 [CA 2] Center 35 (5~66) winsize 62
1482 13:38:49.087061 [CA 3] Center 34 (4~65) winsize 62
1483 13:38:49.087114 [CA 4] Center 35 (5~65) winsize 61
1484 13:38:49.087167 [CA 5] Center 34 (4~65) winsize 62
1485 13:38:49.087220
1486 13:38:49.087273 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1487 13:38:49.087327
1488 13:38:49.087380 [CATrainingPosCal] consider 2 rank data
1489 13:38:49.087433 u2DelayCellTimex100 = 270/100 ps
1490 13:38:49.087487 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1491 13:38:49.087541 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1492 13:38:49.087594 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 13:38:49.087647 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 13:38:49.087700 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1495 13:38:49.087753 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 13:38:49.087806
1497 13:38:49.087860 CA PerBit enable=1, Macro0, CA PI delay=34
1498 13:38:49.087912
1499 13:38:49.087965 [CBTSetCACLKResult] CA Dly = 34
1500 13:38:49.088019 CS Dly: 5 (0~37)
1501 13:38:49.088072
1502 13:38:49.088125 ----->DramcWriteLeveling(PI) begin...
1503 13:38:49.088179 ==
1504 13:38:49.088232 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 13:38:49.088291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 13:38:49.088345 ==
1507 13:38:49.088398 Write leveling (Byte 0): 28 => 28
1508 13:38:49.088451 Write leveling (Byte 1): 29 => 29
1509 13:38:49.088504 DramcWriteLeveling(PI) end<-----
1510 13:38:49.088557
1511 13:38:49.088610 ==
1512 13:38:49.088662 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 13:38:49.088716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 13:38:49.088769 ==
1515 13:38:49.088822 [Gating] SW mode calibration
1516 13:38:49.088875 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 13:38:49.088929 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 13:38:49.088982 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 13:38:49.089036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 13:38:49.089311 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:38:49.089383 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:38:49.089468 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:38:49.089553 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:38:49.089637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:38:49.089721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:38:49.089805 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:38:49.089872 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:38:49.089927 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:38:49.089981 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:38:49.090035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 13:38:49.090089 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 13:38:49.090142 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 13:38:49.090197 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:38:49.090250 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1535 13:38:49.090303 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:38:49.090357 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:38:49.090411 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:38:49.090465 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:38:49.090518 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:38:49.090572 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 13:38:49.090625 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 13:38:49.090678 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 13:38:49.090732 0 9 4 | B1->B0 | 2323 2626 | 1 0 | (1 1) (0 0)
1544 13:38:49.090785 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1545 13:38:49.090839 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 13:38:49.090892 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:38:49.090945 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 13:38:49.090998 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 13:38:49.091052 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 13:38:49.091105 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 13:38:49.091159 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1552 13:38:49.091212 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 13:38:49.091265 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 13:38:49.091319 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:38:49.091372 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:38:49.091426 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 13:38:49.091479 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 13:38:49.091532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 13:38:49.091585 0 11 4 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
1560 13:38:49.091638 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1561 13:38:49.091692 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:38:49.091745 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:38:49.091799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 13:38:49.091851 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 13:38:49.091916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 13:38:49.091971 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1567 13:38:49.092025 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 13:38:49.092078 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1569 13:38:49.092132 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:38:49.092185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:38:49.092239 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:38:49.092292 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:38:49.092345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:38:49.092398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:38:49.092452 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:38:49.092505 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:38:49.092558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:38:49.092612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:38:49.092665 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 13:38:49.092718 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 13:38:49.092772 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 13:38:49.092825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 13:38:49.092878 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 13:38:49.092931 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 13:38:49.092984 Total UI for P1: 0, mck2ui 16
1586 13:38:49.093037 best dqsien dly found for B0: ( 0, 14, 4)
1587 13:38:49.093091 Total UI for P1: 0, mck2ui 16
1588 13:38:49.093145 best dqsien dly found for B1: ( 0, 14, 4)
1589 13:38:49.093199 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 13:38:49.093252 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1591 13:38:49.093310
1592 13:38:49.093364 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 13:38:49.093417 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1594 13:38:49.093471 [Gating] SW calibration Done
1595 13:38:49.093524 ==
1596 13:38:49.093578 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 13:38:49.093631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 13:38:49.093685 ==
1599 13:38:49.093738 RX Vref Scan: 0
1600 13:38:49.093791
1601 13:38:49.093844 RX Vref 0 -> 0, step: 1
1602 13:38:49.093897
1603 13:38:49.093950 RX Delay -130 -> 252, step: 16
1604 13:38:49.094003 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1605 13:38:49.094057 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1606 13:38:49.094109 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1607 13:38:49.094163 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1608 13:38:49.094216 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1609 13:38:49.094468 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1610 13:38:49.094529 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1611 13:38:49.094584 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1612 13:38:49.094638 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1613 13:38:49.094691 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1614 13:38:49.094745 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1615 13:38:49.094798 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1616 13:38:49.094851 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1617 13:38:49.094904 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1618 13:38:49.094958 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1619 13:38:49.095011 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1620 13:38:49.095064 ==
1621 13:38:49.095118 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 13:38:49.095171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 13:38:49.095225 ==
1624 13:38:49.095278 DQS Delay:
1625 13:38:49.095330 DQS0 = 0, DQS1 = 0
1626 13:38:49.095384 DQM Delay:
1627 13:38:49.095438 DQM0 = 92, DQM1 = 80
1628 13:38:49.095491 DQ Delay:
1629 13:38:49.095544 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1630 13:38:49.095597 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1631 13:38:49.095650 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1632 13:38:49.095703 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 13:38:49.095756
1634 13:38:49.095808
1635 13:38:49.095860 ==
1636 13:38:49.095914 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 13:38:49.095967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 13:38:49.096021 ==
1639 13:38:49.096074
1640 13:38:49.096126
1641 13:38:49.096179 TX Vref Scan disable
1642 13:38:49.096232 == TX Byte 0 ==
1643 13:38:49.096285 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 13:38:49.096338 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 13:38:49.096392 == TX Byte 1 ==
1646 13:38:49.096445 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1647 13:38:49.096499 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1648 13:38:49.096552 ==
1649 13:38:49.096605 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 13:38:49.096659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 13:38:49.096712 ==
1652 13:38:49.096765 TX Vref=22, minBit 8, minWin=27, winSum=445
1653 13:38:49.096819 TX Vref=24, minBit 8, minWin=27, winSum=450
1654 13:38:49.096873 TX Vref=26, minBit 8, minWin=27, winSum=453
1655 13:38:49.096927 TX Vref=28, minBit 8, minWin=27, winSum=454
1656 13:38:49.096980 TX Vref=30, minBit 8, minWin=27, winSum=457
1657 13:38:49.097034 TX Vref=32, minBit 8, minWin=27, winSum=454
1658 13:38:49.097088 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1659 13:38:49.097142
1660 13:38:49.097194 Final TX Range 1 Vref 30
1661 13:38:49.097248
1662 13:38:49.097307 ==
1663 13:38:49.097361 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 13:38:49.097415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 13:38:49.097468 ==
1666 13:38:49.097521
1667 13:38:49.097574
1668 13:38:49.097626 TX Vref Scan disable
1669 13:38:49.097680 == TX Byte 0 ==
1670 13:38:49.097733 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 13:38:49.097787 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 13:38:49.097840 == TX Byte 1 ==
1673 13:38:49.097893 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1674 13:38:49.097947 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1675 13:38:49.098000
1676 13:38:49.098052 [DATLAT]
1677 13:38:49.098106 Freq=800, CH1 RK0
1678 13:38:49.098159
1679 13:38:49.098211 DATLAT Default: 0xa
1680 13:38:49.098264 0, 0xFFFF, sum = 0
1681 13:38:49.098319 1, 0xFFFF, sum = 0
1682 13:38:49.098374 2, 0xFFFF, sum = 0
1683 13:38:49.098428 3, 0xFFFF, sum = 0
1684 13:38:49.098482 4, 0xFFFF, sum = 0
1685 13:38:49.098536 5, 0xFFFF, sum = 0
1686 13:38:49.098590 6, 0xFFFF, sum = 0
1687 13:38:49.098644 7, 0xFFFF, sum = 0
1688 13:38:49.098698 8, 0xFFFF, sum = 0
1689 13:38:49.098752 9, 0x0, sum = 1
1690 13:38:49.098805 10, 0x0, sum = 2
1691 13:38:49.098859 11, 0x0, sum = 3
1692 13:38:49.098913 12, 0x0, sum = 4
1693 13:38:49.098967 best_step = 10
1694 13:38:49.099020
1695 13:38:49.099072 ==
1696 13:38:49.099125 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 13:38:49.099179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 13:38:49.099232 ==
1699 13:38:49.099285 RX Vref Scan: 1
1700 13:38:49.099338
1701 13:38:49.099391 Set Vref Range= 32 -> 127
1702 13:38:49.099443
1703 13:38:49.099496 RX Vref 32 -> 127, step: 1
1704 13:38:49.099549
1705 13:38:49.099602 RX Delay -95 -> 252, step: 8
1706 13:38:49.099655
1707 13:38:49.099708 Set Vref, RX VrefLevel [Byte0]: 32
1708 13:38:49.099761 [Byte1]: 32
1709 13:38:49.099814
1710 13:38:49.099867 Set Vref, RX VrefLevel [Byte0]: 33
1711 13:38:49.099920 [Byte1]: 33
1712 13:38:49.099974
1713 13:38:49.100027 Set Vref, RX VrefLevel [Byte0]: 34
1714 13:38:49.100080 [Byte1]: 34
1715 13:38:49.100134
1716 13:38:49.100187 Set Vref, RX VrefLevel [Byte0]: 35
1717 13:38:49.100259 [Byte1]: 35
1718 13:38:49.100313
1719 13:38:49.100366 Set Vref, RX VrefLevel [Byte0]: 36
1720 13:38:49.100420 [Byte1]: 36
1721 13:38:49.100473
1722 13:38:49.100526 Set Vref, RX VrefLevel [Byte0]: 37
1723 13:38:49.100579 [Byte1]: 37
1724 13:38:49.100632
1725 13:38:49.100684 Set Vref, RX VrefLevel [Byte0]: 38
1726 13:38:49.100737 [Byte1]: 38
1727 13:38:49.100790
1728 13:38:49.100843 Set Vref, RX VrefLevel [Byte0]: 39
1729 13:38:49.100896 [Byte1]: 39
1730 13:38:49.100949
1731 13:38:49.101002 Set Vref, RX VrefLevel [Byte0]: 40
1732 13:38:49.101055 [Byte1]: 40
1733 13:38:49.101108
1734 13:38:49.101161 Set Vref, RX VrefLevel [Byte0]: 41
1735 13:38:49.101214 [Byte1]: 41
1736 13:38:49.101267
1737 13:38:49.101323 Set Vref, RX VrefLevel [Byte0]: 42
1738 13:38:49.101376 [Byte1]: 42
1739 13:38:49.101429
1740 13:38:49.101482 Set Vref, RX VrefLevel [Byte0]: 43
1741 13:38:49.101535 [Byte1]: 43
1742 13:38:49.101588
1743 13:38:49.101641 Set Vref, RX VrefLevel [Byte0]: 44
1744 13:38:49.101694 [Byte1]: 44
1745 13:38:49.101747
1746 13:38:49.101799 Set Vref, RX VrefLevel [Byte0]: 45
1747 13:38:49.101852 [Byte1]: 45
1748 13:38:49.101905
1749 13:38:49.101958 Set Vref, RX VrefLevel [Byte0]: 46
1750 13:38:49.102011 [Byte1]: 46
1751 13:38:49.102064
1752 13:38:49.102117 Set Vref, RX VrefLevel [Byte0]: 47
1753 13:38:49.102170 [Byte1]: 47
1754 13:38:49.102250
1755 13:38:49.102332 Set Vref, RX VrefLevel [Byte0]: 48
1756 13:38:49.102391 [Byte1]: 48
1757 13:38:49.102445
1758 13:38:49.102499 Set Vref, RX VrefLevel [Byte0]: 49
1759 13:38:49.102552 [Byte1]: 49
1760 13:38:49.102605
1761 13:38:49.102658 Set Vref, RX VrefLevel [Byte0]: 50
1762 13:38:49.102712 [Byte1]: 50
1763 13:38:49.102765
1764 13:38:49.102818 Set Vref, RX VrefLevel [Byte0]: 51
1765 13:38:49.102871 [Byte1]: 51
1766 13:38:49.102924
1767 13:38:49.102978 Set Vref, RX VrefLevel [Byte0]: 52
1768 13:38:49.103030 [Byte1]: 52
1769 13:38:49.103083
1770 13:38:49.103336 Set Vref, RX VrefLevel [Byte0]: 53
1771 13:38:49.103396 [Byte1]: 53
1772 13:38:49.103450
1773 13:38:49.103548 Set Vref, RX VrefLevel [Byte0]: 54
1774 13:38:49.103634 [Byte1]: 54
1775 13:38:49.103717
1776 13:38:49.103801 Set Vref, RX VrefLevel [Byte0]: 55
1777 13:38:49.103884 [Byte1]: 55
1778 13:38:49.103967
1779 13:38:49.104050 Set Vref, RX VrefLevel [Byte0]: 56
1780 13:38:49.104133 [Byte1]: 56
1781 13:38:49.104216
1782 13:38:49.104299 Set Vref, RX VrefLevel [Byte0]: 57
1783 13:38:49.104383 [Byte1]: 57
1784 13:38:49.104465
1785 13:38:49.104548 Set Vref, RX VrefLevel [Byte0]: 58
1786 13:38:49.104631 [Byte1]: 58
1787 13:38:49.104713
1788 13:38:49.104797 Set Vref, RX VrefLevel [Byte0]: 59
1789 13:38:49.104880 [Byte1]: 59
1790 13:38:49.104962
1791 13:38:49.105045 Set Vref, RX VrefLevel [Byte0]: 60
1792 13:38:49.105128 [Byte1]: 60
1793 13:38:49.105210
1794 13:38:49.105293 Set Vref, RX VrefLevel [Byte0]: 61
1795 13:38:49.105393 [Byte1]: 61
1796 13:38:49.105476
1797 13:38:49.105559 Set Vref, RX VrefLevel [Byte0]: 62
1798 13:38:49.105643 [Byte1]: 62
1799 13:38:49.105726
1800 13:38:49.105808 Set Vref, RX VrefLevel [Byte0]: 63
1801 13:38:49.105892 [Byte1]: 63
1802 13:38:49.105974
1803 13:38:49.106057 Set Vref, RX VrefLevel [Byte0]: 64
1804 13:38:49.106140 [Byte1]: 64
1805 13:38:49.106223
1806 13:38:49.106306 Set Vref, RX VrefLevel [Byte0]: 65
1807 13:38:49.106389 [Byte1]: 65
1808 13:38:49.106471
1809 13:38:49.106554 Set Vref, RX VrefLevel [Byte0]: 66
1810 13:38:49.106637 [Byte1]: 66
1811 13:38:49.106719
1812 13:38:49.106802 Set Vref, RX VrefLevel [Byte0]: 67
1813 13:38:49.106885 [Byte1]: 67
1814 13:38:49.106967
1815 13:38:49.107050 Set Vref, RX VrefLevel [Byte0]: 68
1816 13:38:49.107134 [Byte1]: 68
1817 13:38:49.107216
1818 13:38:49.107299 Set Vref, RX VrefLevel [Byte0]: 69
1819 13:38:49.107381 [Byte1]: 69
1820 13:38:49.107463
1821 13:38:49.107546 Set Vref, RX VrefLevel [Byte0]: 70
1822 13:38:49.107629 [Byte1]: 70
1823 13:38:49.107712
1824 13:38:49.107795 Set Vref, RX VrefLevel [Byte0]: 71
1825 13:38:49.107878 [Byte1]: 71
1826 13:38:49.107960
1827 13:38:49.108043 Set Vref, RX VrefLevel [Byte0]: 72
1828 13:38:49.108126 [Byte1]: 72
1829 13:38:49.108208
1830 13:38:49.108291 Set Vref, RX VrefLevel [Byte0]: 73
1831 13:38:49.108374 [Byte1]: 73
1832 13:38:49.108456
1833 13:38:49.108539 Final RX Vref Byte 0 = 52 to rank0
1834 13:38:49.108623 Final RX Vref Byte 1 = 61 to rank0
1835 13:38:49.108706 Final RX Vref Byte 0 = 52 to rank1
1836 13:38:49.108790 Final RX Vref Byte 1 = 61 to rank1==
1837 13:38:49.108874 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 13:38:49.108958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 13:38:49.109041 ==
1840 13:38:49.109124 DQS Delay:
1841 13:38:49.109207 DQS0 = 0, DQS1 = 0
1842 13:38:49.109290 DQM Delay:
1843 13:38:49.109353 DQM0 = 93, DQM1 = 83
1844 13:38:49.109407 DQ Delay:
1845 13:38:49.109461 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1846 13:38:49.109515 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1847 13:38:49.109568 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1848 13:38:49.109622 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1849 13:38:49.109674
1850 13:38:49.109727
1851 13:38:49.109780 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1852 13:38:49.109834 CH1 RK0: MR19=606, MR18=3451
1853 13:38:49.109888 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1854 13:38:49.109941
1855 13:38:49.109994 ----->DramcWriteLeveling(PI) begin...
1856 13:38:49.110048 ==
1857 13:38:49.110101 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 13:38:49.110154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 13:38:49.110208 ==
1860 13:38:49.110261 Write leveling (Byte 0): 29 => 29
1861 13:38:49.110314 Write leveling (Byte 1): 29 => 29
1862 13:38:49.110366 DramcWriteLeveling(PI) end<-----
1863 13:38:49.110419
1864 13:38:49.110472 ==
1865 13:38:49.110524 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 13:38:49.110577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 13:38:49.110631 ==
1868 13:38:49.110684 [Gating] SW mode calibration
1869 13:38:49.110737 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 13:38:49.110791 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 13:38:49.110845 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 13:38:49.110899 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1873 13:38:49.110953 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 13:38:49.111006 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 13:38:49.111060 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 13:38:49.111113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 13:38:49.111166 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 13:38:49.111220 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 13:38:49.111273 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 13:38:49.111327 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 13:38:49.111379 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 13:38:49.111433 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 13:38:49.111486 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 13:38:49.111539 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 13:38:49.111591 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 13:38:49.111645 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:38:49.111697 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1888 13:38:49.111750 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1889 13:38:49.111802 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:38:49.111855 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:38:49.111908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:38:49.111961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 13:38:49.112014 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 13:38:49.112067 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:38:49.112119 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:38:49.112173 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 13:38:49.112431 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1898 13:38:49.112496 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 13:38:49.112551 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 13:38:49.112605 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 13:38:49.112659 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 13:38:49.112712 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 13:38:49.112766 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1904 13:38:49.112819 0 10 4 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
1905 13:38:49.112873 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:38:49.112927 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:38:49.112981 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:38:49.113034 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 13:38:49.113088 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 13:38:49.113141 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 13:38:49.113195 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 13:38:49.113249 0 11 4 | B1->B0 | 3535 2e2e | 0 0 | (0 0) (0 0)
1913 13:38:49.113310 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1914 13:38:49.113365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 13:38:49.113418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 13:38:49.113472 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 13:38:49.113526 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 13:38:49.113579 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 13:38:49.113632 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1920 13:38:49.113686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1921 13:38:49.113739 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 13:38:49.113793 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 13:38:49.113847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 13:38:49.113900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 13:38:49.113953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 13:38:49.114007 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 13:38:49.114060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 13:38:49.114114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 13:38:49.114167 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 13:38:49.114220 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 13:38:49.114273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 13:38:49.114326 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 13:38:49.114380 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 13:38:49.114433 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:38:49.114486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1936 13:38:49.114540 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1937 13:38:49.114593 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 13:38:49.114646 Total UI for P1: 0, mck2ui 16
1939 13:38:49.114700 best dqsien dly found for B0: ( 0, 14, 6)
1940 13:38:49.114753 Total UI for P1: 0, mck2ui 16
1941 13:38:49.114807 best dqsien dly found for B1: ( 0, 14, 2)
1942 13:38:49.114860 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1943 13:38:49.114914 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1944 13:38:49.114967
1945 13:38:49.115020 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1946 13:38:49.115074 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 13:38:49.115128 [Gating] SW calibration Done
1948 13:38:49.115181 ==
1949 13:38:49.115234 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 13:38:49.115287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 13:38:49.115341 ==
1952 13:38:49.115395 RX Vref Scan: 0
1953 13:38:49.115447
1954 13:38:49.115500 RX Vref 0 -> 0, step: 1
1955 13:38:49.115553
1956 13:38:49.115606 RX Delay -130 -> 252, step: 16
1957 13:38:49.115659 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1958 13:38:49.115712 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1959 13:38:49.115765 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1960 13:38:49.115818 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1961 13:38:49.115871 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1962 13:38:49.115924 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1963 13:38:49.115977 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1964 13:38:49.116029 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1965 13:38:49.116082 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1966 13:38:49.116135 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1967 13:38:49.116187 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1968 13:38:49.116240 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1969 13:38:49.116293 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1970 13:38:49.116353 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1971 13:38:49.116408 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1972 13:38:49.116461 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1973 13:38:49.116515 ==
1974 13:38:49.116567 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 13:38:49.116620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 13:38:49.116675 ==
1977 13:38:49.116728 DQS Delay:
1978 13:38:49.116780 DQS0 = 0, DQS1 = 0
1979 13:38:49.116832 DQM Delay:
1980 13:38:49.116884 DQM0 = 90, DQM1 = 84
1981 13:38:49.116937 DQ Delay:
1982 13:38:49.116990 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1983 13:38:49.117043 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1984 13:38:49.117096 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1985 13:38:49.397634 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1986 13:38:49.397769
1987 13:38:49.397839
1988 13:38:49.397941 ==
1989 13:38:49.398007 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 13:38:49.398066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 13:38:49.398130 ==
1992 13:38:49.398220
1993 13:38:49.398309
1994 13:38:49.398395 TX Vref Scan disable
1995 13:38:49.398480 == TX Byte 0 ==
1996 13:38:49.398566 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1997 13:38:49.398655 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1998 13:38:49.398740 == TX Byte 1 ==
1999 13:38:49.398824 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 13:38:49.398912 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 13:38:49.398996 ==
2002 13:38:49.399087 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 13:38:49.399391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 13:38:49.399486 ==
2005 13:38:49.399572 TX Vref=22, minBit 10, minWin=27, winSum=450
2006 13:38:49.399658 TX Vref=24, minBit 8, minWin=27, winSum=453
2007 13:38:49.399743 TX Vref=26, minBit 13, minWin=27, winSum=452
2008 13:38:49.399828 TX Vref=28, minBit 8, minWin=28, winSum=459
2009 13:38:49.399913 TX Vref=30, minBit 9, minWin=27, winSum=457
2010 13:38:49.400003 TX Vref=32, minBit 9, minWin=27, winSum=456
2011 13:38:49.400091 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
2012 13:38:49.400175
2013 13:38:49.400259 Final TX Range 1 Vref 28
2014 13:38:49.400348
2015 13:38:49.400437 ==
2016 13:38:49.400525 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 13:38:49.400610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 13:38:49.400699 ==
2019 13:38:49.400784
2020 13:38:49.400876
2021 13:38:49.400974 TX Vref Scan disable
2022 13:38:49.401063 == TX Byte 0 ==
2023 13:38:49.401149 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2024 13:38:49.401234 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2025 13:38:49.401331 == TX Byte 1 ==
2026 13:38:49.401429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 13:38:49.401525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 13:38:49.401610
2029 13:38:49.401698 [DATLAT]
2030 13:38:49.401794 Freq=800, CH1 RK1
2031 13:38:49.401884
2032 13:38:49.401968 DATLAT Default: 0xa
2033 13:38:49.402052 0, 0xFFFF, sum = 0
2034 13:38:49.402138 1, 0xFFFF, sum = 0
2035 13:38:49.402224 2, 0xFFFF, sum = 0
2036 13:38:49.402314 3, 0xFFFF, sum = 0
2037 13:38:49.402388 4, 0xFFFF, sum = 0
2038 13:38:49.402445 5, 0xFFFF, sum = 0
2039 13:38:49.402499 6, 0xFFFF, sum = 0
2040 13:38:49.402565 7, 0xFFFF, sum = 0
2041 13:38:49.402651 8, 0xFFFF, sum = 0
2042 13:38:49.402737 9, 0x0, sum = 1
2043 13:38:49.402823 10, 0x0, sum = 2
2044 13:38:49.402909 11, 0x0, sum = 3
2045 13:38:49.402995 12, 0x0, sum = 4
2046 13:38:49.403086 best_step = 10
2047 13:38:49.403144
2048 13:38:49.403198 ==
2049 13:38:49.403252 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 13:38:49.403307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 13:38:49.403361 ==
2052 13:38:49.403415 RX Vref Scan: 0
2053 13:38:49.403469
2054 13:38:49.403522 RX Vref 0 -> 0, step: 1
2055 13:38:49.403576
2056 13:38:49.403638 RX Delay -95 -> 252, step: 8
2057 13:38:49.403721 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2058 13:38:49.403778 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2059 13:38:49.403833 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2060 13:38:49.403887 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2061 13:38:49.403942 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2062 13:38:49.403996 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2063 13:38:49.404051 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2064 13:38:49.404104 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2065 13:38:49.404157 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2066 13:38:49.404253 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2067 13:38:49.404349 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2068 13:38:49.404435 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2069 13:38:49.404519 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2070 13:38:49.404604 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2071 13:38:49.404699 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2072 13:38:49.404786 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2073 13:38:49.404875 ==
2074 13:38:49.404969 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 13:38:49.405061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 13:38:49.405156 ==
2077 13:38:49.405243 DQS Delay:
2078 13:38:49.405333 DQS0 = 0, DQS1 = 0
2079 13:38:49.405391 DQM Delay:
2080 13:38:49.405445 DQM0 = 92, DQM1 = 85
2081 13:38:49.405500 DQ Delay:
2082 13:38:49.405553 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2083 13:38:49.405608 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2084 13:38:49.405662 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =84
2085 13:38:49.405716 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =96
2086 13:38:49.405770
2087 13:38:49.405824
2088 13:38:49.405878 [DQSOSCAuto] RK1, (LSB)MR18= 0x4015, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
2089 13:38:49.405935 CH1 RK1: MR19=606, MR18=4015
2090 13:38:49.405990 CH1_RK1: MR19=0x606, MR18=0x4015, DQSOSC=393, MR23=63, INC=95, DEC=63
2091 13:38:49.406045 [RxdqsGatingPostProcess] freq 800
2092 13:38:49.406100 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 13:38:49.406156 Pre-setting of DQS Precalculation
2094 13:38:49.406210 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 13:38:49.406265 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 13:38:49.406322 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 13:38:49.406378
2098 13:38:49.406433
2099 13:38:49.406488 [Calibration Summary] 1600 Mbps
2100 13:38:49.406543 CH 0, Rank 0
2101 13:38:49.406616 SW Impedance : PASS
2102 13:38:49.406673 DUTY Scan : NO K
2103 13:38:49.406729 ZQ Calibration : PASS
2104 13:38:49.406784 Jitter Meter : NO K
2105 13:38:49.406840 CBT Training : PASS
2106 13:38:49.406895 Write leveling : PASS
2107 13:38:49.406950 RX DQS gating : PASS
2108 13:38:49.407004 RX DQ/DQS(RDDQC) : PASS
2109 13:38:49.407059 TX DQ/DQS : PASS
2110 13:38:49.407114 RX DATLAT : PASS
2111 13:38:49.407169 RX DQ/DQS(Engine): PASS
2112 13:38:49.407224 TX OE : NO K
2113 13:38:49.407279 All Pass.
2114 13:38:49.407334
2115 13:38:49.407389 CH 0, Rank 1
2116 13:38:49.407444 SW Impedance : PASS
2117 13:38:49.407499 DUTY Scan : NO K
2118 13:38:49.407578 ZQ Calibration : PASS
2119 13:38:49.407641 Jitter Meter : NO K
2120 13:38:49.407697 CBT Training : PASS
2121 13:38:49.407753 Write leveling : PASS
2122 13:38:49.407808 RX DQS gating : PASS
2123 13:38:49.407863 RX DQ/DQS(RDDQC) : PASS
2124 13:38:49.407919 TX DQ/DQS : PASS
2125 13:38:49.407975 RX DATLAT : PASS
2126 13:38:49.408030 RX DQ/DQS(Engine): PASS
2127 13:38:49.408085 TX OE : NO K
2128 13:38:49.408176 All Pass.
2129 13:38:49.408268
2130 13:38:49.408363 CH 1, Rank 0
2131 13:38:49.408457 SW Impedance : PASS
2132 13:38:49.408548 DUTY Scan : NO K
2133 13:38:49.408643 ZQ Calibration : PASS
2134 13:38:49.408731 Jitter Meter : NO K
2135 13:38:49.408792 CBT Training : PASS
2136 13:38:49.408850 Write leveling : PASS
2137 13:38:49.408907 RX DQS gating : PASS
2138 13:38:49.408964 RX DQ/DQS(RDDQC) : PASS
2139 13:38:49.409019 TX DQ/DQS : PASS
2140 13:38:49.409075 RX DATLAT : PASS
2141 13:38:49.409131 RX DQ/DQS(Engine): PASS
2142 13:38:49.409186 TX OE : NO K
2143 13:38:49.409242 All Pass.
2144 13:38:49.409304
2145 13:38:49.409363 CH 1, Rank 1
2146 13:38:49.409419 SW Impedance : PASS
2147 13:38:49.409474 DUTY Scan : NO K
2148 13:38:49.409530 ZQ Calibration : PASS
2149 13:38:49.409585 Jitter Meter : NO K
2150 13:38:49.409640 CBT Training : PASS
2151 13:38:49.409696 Write leveling : PASS
2152 13:38:49.409751 RX DQS gating : PASS
2153 13:38:49.409806 RX DQ/DQS(RDDQC) : PASS
2154 13:38:49.410073 TX DQ/DQS : PASS
2155 13:38:49.410136 RX DATLAT : PASS
2156 13:38:49.410192 RX DQ/DQS(Engine): PASS
2157 13:38:49.410248 TX OE : NO K
2158 13:38:49.410304 All Pass.
2159 13:38:49.410359
2160 13:38:49.410414 DramC Write-DBI off
2161 13:38:49.410474 PER_BANK_REFRESH: Hybrid Mode
2162 13:38:49.410557 TX_TRACKING: ON
2163 13:38:49.410654 [GetDramInforAfterCalByMRR] Vendor 6.
2164 13:38:49.410740 [GetDramInforAfterCalByMRR] Revision 606.
2165 13:38:49.410826 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 13:38:49.410914 MR0 0x3b3b
2167 13:38:49.410980 MR8 0x5151
2168 13:38:49.411036 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 13:38:49.411092
2170 13:38:49.411148 MR0 0x3b3b
2171 13:38:49.411203 MR8 0x5151
2172 13:38:49.411258 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 13:38:49.411319
2174 13:38:49.411376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 13:38:49.411432 [FAST_K] Save calibration result to emmc
2176 13:38:49.411495 [FAST_K] Save calibration result to emmc
2177 13:38:49.411558 dram_init: config_dvfs: 1
2178 13:38:49.411614 dramc_set_vcore_voltage set vcore to 662500
2179 13:38:49.411672 Read voltage for 1200, 2
2180 13:38:49.411749 Vio18 = 0
2181 13:38:49.411806 Vcore = 662500
2182 13:38:49.411862 Vdram = 0
2183 13:38:49.411917 Vddq = 0
2184 13:38:49.411977 Vmddr = 0
2185 13:38:49.412033 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 13:38:49.412090 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 13:38:49.412146 MEM_TYPE=3, freq_sel=15
2188 13:38:49.412201 sv_algorithm_assistance_LP4_1600
2189 13:38:49.412257 ============ PULL DRAM RESETB DOWN ============
2190 13:38:49.412312 ========== PULL DRAM RESETB DOWN end =========
2191 13:38:49.412368 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 13:38:49.412423 ===================================
2193 13:38:49.412480 LPDDR4 DRAM CONFIGURATION
2194 13:38:49.412546 ===================================
2195 13:38:49.412601 EX_ROW_EN[0] = 0x0
2196 13:38:49.412656 EX_ROW_EN[1] = 0x0
2197 13:38:49.412711 LP4Y_EN = 0x0
2198 13:38:49.412766 WORK_FSP = 0x0
2199 13:38:49.412821 WL = 0x4
2200 13:38:49.412877 RL = 0x4
2201 13:38:49.412939 BL = 0x2
2202 13:38:49.412996 RPST = 0x0
2203 13:38:49.413051 RD_PRE = 0x0
2204 13:38:49.413106 WR_PRE = 0x1
2205 13:38:49.413161 WR_PST = 0x0
2206 13:38:49.413216 DBI_WR = 0x0
2207 13:38:49.413310 DBI_RD = 0x0
2208 13:38:49.413369 OTF = 0x1
2209 13:38:49.413425 ===================================
2210 13:38:49.413481 ===================================
2211 13:38:49.413537 ANA top config
2212 13:38:49.413607 ===================================
2213 13:38:49.413664 DLL_ASYNC_EN = 0
2214 13:38:49.413720 ALL_SLAVE_EN = 0
2215 13:38:49.413776 NEW_RANK_MODE = 1
2216 13:38:49.413833 DLL_IDLE_MODE = 1
2217 13:38:49.413889 LP45_APHY_COMB_EN = 1
2218 13:38:49.413981 TX_ODT_DIS = 1
2219 13:38:49.414041 NEW_8X_MODE = 1
2220 13:38:49.414098 ===================================
2221 13:38:49.414153 ===================================
2222 13:38:49.414209 data_rate = 2400
2223 13:38:49.414266 CKR = 1
2224 13:38:49.414335 DQ_P2S_RATIO = 8
2225 13:38:49.414396 ===================================
2226 13:38:49.414457 CA_P2S_RATIO = 8
2227 13:38:49.414513 DQ_CA_OPEN = 0
2228 13:38:49.414568 DQ_SEMI_OPEN = 0
2229 13:38:49.414623 CA_SEMI_OPEN = 0
2230 13:38:49.414678 CA_FULL_RATE = 0
2231 13:38:49.414742 DQ_CKDIV4_EN = 0
2232 13:38:49.414829 CA_CKDIV4_EN = 0
2233 13:38:49.414914 CA_PREDIV_EN = 0
2234 13:38:49.414999 PH8_DLY = 17
2235 13:38:49.415077 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 13:38:49.415144 DQ_AAMCK_DIV = 4
2237 13:38:49.415200 CA_AAMCK_DIV = 4
2238 13:38:49.415255 CA_ADMCK_DIV = 4
2239 13:38:49.415311 DQ_TRACK_CA_EN = 0
2240 13:38:49.415366 CA_PICK = 1200
2241 13:38:49.415435 CA_MCKIO = 1200
2242 13:38:49.415491 MCKIO_SEMI = 0
2243 13:38:49.415547 PLL_FREQ = 2366
2244 13:38:49.415602 DQ_UI_PI_RATIO = 32
2245 13:38:49.415657 CA_UI_PI_RATIO = 0
2246 13:38:49.415712 ===================================
2247 13:38:49.415790 ===================================
2248 13:38:49.415847 memory_type:LPDDR4
2249 13:38:49.415902 GP_NUM : 10
2250 13:38:49.415958 SRAM_EN : 1
2251 13:38:49.416013 MD32_EN : 0
2252 13:38:49.416068 ===================================
2253 13:38:49.416134 [ANA_INIT] >>>>>>>>>>>>>>
2254 13:38:49.416191 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 13:38:49.416260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 13:38:49.416347 ===================================
2257 13:38:49.416433 data_rate = 2400,PCW = 0X5b00
2258 13:38:49.416492 ===================================
2259 13:38:49.416548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 13:38:49.416604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 13:38:49.416660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 13:38:49.416728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 13:38:49.416786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 13:38:49.416841 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 13:38:49.416897 [ANA_INIT] flow start
2266 13:38:49.416952 [ANA_INIT] PLL >>>>>>>>
2267 13:38:49.417008 [ANA_INIT] PLL <<<<<<<<
2268 13:38:49.417063 [ANA_INIT] MIDPI >>>>>>>>
2269 13:38:49.417119 [ANA_INIT] MIDPI <<<<<<<<
2270 13:38:49.417183 [ANA_INIT] DLL >>>>>>>>
2271 13:38:49.417269 [ANA_INIT] DLL <<<<<<<<
2272 13:38:49.417345 [ANA_INIT] flow end
2273 13:38:49.417403 ============ LP4 DIFF to SE enter ============
2274 13:38:49.417459 ============ LP4 DIFF to SE exit ============
2275 13:38:49.417515 [ANA_INIT] <<<<<<<<<<<<<
2276 13:38:49.417571 [Flow] Enable top DCM control >>>>>
2277 13:38:49.417633 [Flow] Enable top DCM control <<<<<
2278 13:38:49.417688 Enable DLL master slave shuffle
2279 13:38:49.417757 ==============================================================
2280 13:38:49.417820 Gating Mode config
2281 13:38:49.417877 ==============================================================
2282 13:38:49.417954 Config description:
2283 13:38:49.418259 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 13:38:49.418357 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 13:38:49.418445 SELPH_MODE 0: By rank 1: By Phase
2286 13:38:49.418533 ==============================================================
2287 13:38:49.418620 GAT_TRACK_EN = 1
2288 13:38:49.418706 RX_GATING_MODE = 2
2289 13:38:49.418792 RX_GATING_TRACK_MODE = 2
2290 13:38:49.418877 SELPH_MODE = 1
2291 13:38:49.418966 PICG_EARLY_EN = 1
2292 13:38:49.419052 VALID_LAT_VALUE = 1
2293 13:38:49.419138 ==============================================================
2294 13:38:49.419224 Enter into Gating configuration >>>>
2295 13:38:49.419310 Exit from Gating configuration <<<<
2296 13:38:49.419402 Enter into DVFS_PRE_config >>>>>
2297 13:38:49.419490 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 13:38:49.419577 Exit from DVFS_PRE_config <<<<<
2299 13:38:49.419663 Enter into PICG configuration >>>>
2300 13:38:49.419748 Exit from PICG configuration <<<<
2301 13:38:49.419833 [RX_INPUT] configuration >>>>>
2302 13:38:49.419918 [RX_INPUT] configuration <<<<<
2303 13:38:49.420004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 13:38:49.420090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 13:38:49.420176 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 13:38:49.420262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 13:38:49.420348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 13:38:49.420430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 13:38:49.420488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 13:38:49.420544 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 13:38:49.420599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 13:38:49.420655 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 13:38:49.420711 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 13:38:49.420767 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 13:38:49.420823 ===================================
2316 13:38:49.420878 LPDDR4 DRAM CONFIGURATION
2317 13:38:49.420934 ===================================
2318 13:38:49.420989 EX_ROW_EN[0] = 0x0
2319 13:38:49.421044 EX_ROW_EN[1] = 0x0
2320 13:38:49.421103 LP4Y_EN = 0x0
2321 13:38:49.421193 WORK_FSP = 0x0
2322 13:38:49.421278 WL = 0x4
2323 13:38:49.421375 RL = 0x4
2324 13:38:49.421466 BL = 0x2
2325 13:38:49.421525 RPST = 0x0
2326 13:38:49.421581 RD_PRE = 0x0
2327 13:38:49.421637 WR_PRE = 0x1
2328 13:38:49.421692 WR_PST = 0x0
2329 13:38:49.421746 DBI_WR = 0x0
2330 13:38:49.421801 DBI_RD = 0x0
2331 13:38:49.421855 OTF = 0x1
2332 13:38:49.421910 ===================================
2333 13:38:49.421967 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 13:38:49.422023 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 13:38:49.422078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 13:38:49.422134 ===================================
2337 13:38:49.422190 LPDDR4 DRAM CONFIGURATION
2338 13:38:49.422245 ===================================
2339 13:38:49.422301 EX_ROW_EN[0] = 0x10
2340 13:38:49.422356 EX_ROW_EN[1] = 0x0
2341 13:38:49.422411 LP4Y_EN = 0x0
2342 13:38:49.422466 WORK_FSP = 0x0
2343 13:38:49.422531 WL = 0x4
2344 13:38:49.422590 RL = 0x4
2345 13:38:49.422645 BL = 0x2
2346 13:38:49.422700 RPST = 0x0
2347 13:38:49.422768 RD_PRE = 0x0
2348 13:38:49.422821 WR_PRE = 0x1
2349 13:38:49.422875 WR_PST = 0x0
2350 13:38:49.422928 DBI_WR = 0x0
2351 13:38:49.422982 DBI_RD = 0x0
2352 13:38:49.423035 OTF = 0x1
2353 13:38:49.423089 ===================================
2354 13:38:49.423179 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 13:38:49.423234 ==
2356 13:38:49.423288 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 13:38:49.423342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 13:38:49.423396 ==
2359 13:38:49.423450 [Duty_Offset_Calibration]
2360 13:38:49.423503 B0:2 B1:0 CA:1
2361 13:38:49.423556
2362 13:38:49.423609 [DutyScan_Calibration_Flow] k_type=0
2363 13:38:49.423661
2364 13:38:49.423751 ==CLK 0==
2365 13:38:49.423805 Final CLK duty delay cell = -4
2366 13:38:49.423857 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2367 13:38:49.423911 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2368 13:38:49.423963 [-4] AVG Duty = 4953%(X100)
2369 13:38:49.424015
2370 13:38:49.424067 CH0 CLK Duty spec in!! Max-Min= 156%
2371 13:38:49.424120 [DutyScan_Calibration_Flow] ====Done====
2372 13:38:49.424172
2373 13:38:49.424249 [DutyScan_Calibration_Flow] k_type=1
2374 13:38:49.424331
2375 13:38:49.424443 ==DQS 0 ==
2376 13:38:49.424496 Final DQS duty delay cell = 0
2377 13:38:49.424602 [0] MAX Duty = 5187%(X100), DQS PI = 30
2378 13:38:49.424718 [0] MIN Duty = 4938%(X100), DQS PI = 0
2379 13:38:49.424805 [0] AVG Duty = 5062%(X100)
2380 13:38:49.424919
2381 13:38:49.425002 ==DQS 1 ==
2382 13:38:49.425080 Final DQS duty delay cell = -4
2383 13:38:49.425176 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2384 13:38:49.425262 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2385 13:38:49.425382 [-4] AVG Duty = 5015%(X100)
2386 13:38:49.425453
2387 13:38:49.425524 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2388 13:38:49.425578
2389 13:38:49.425661 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2390 13:38:49.425715 [DutyScan_Calibration_Flow] ====Done====
2391 13:38:49.425769
2392 13:38:49.425821 [DutyScan_Calibration_Flow] k_type=3
2393 13:38:49.425875
2394 13:38:49.425927 ==DQM 0 ==
2395 13:38:49.425980 Final DQM duty delay cell = 0
2396 13:38:49.426033 [0] MAX Duty = 5062%(X100), DQS PI = 24
2397 13:38:49.426086 [0] MIN Duty = 4813%(X100), DQS PI = 0
2398 13:38:49.426138 [0] AVG Duty = 4937%(X100)
2399 13:38:49.426191
2400 13:38:49.426242 ==DQM 1 ==
2401 13:38:49.426295 Final DQM duty delay cell = 0
2402 13:38:49.426347 [0] MAX Duty = 5187%(X100), DQS PI = 46
2403 13:38:49.426400 [0] MIN Duty = 5000%(X100), DQS PI = 12
2404 13:38:49.426454 [0] AVG Duty = 5093%(X100)
2405 13:38:49.426506
2406 13:38:49.426558 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2407 13:38:49.426611
2408 13:38:49.426663 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2409 13:38:49.426942 [DutyScan_Calibration_Flow] ====Done====
2410 13:38:49.427038
2411 13:38:49.427092 [DutyScan_Calibration_Flow] k_type=2
2412 13:38:49.427159
2413 13:38:49.427249 ==DQ 0 ==
2414 13:38:49.427359 Final DQ duty delay cell = -4
2415 13:38:49.427426 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2416 13:38:49.427479 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2417 13:38:49.427545 [-4] AVG Duty = 4953%(X100)
2418 13:38:49.427628
2419 13:38:49.427710 ==DQ 1 ==
2420 13:38:49.427764 Final DQ duty delay cell = 4
2421 13:38:49.427818 [4] MAX Duty = 5093%(X100), DQS PI = 4
2422 13:38:49.427878 [4] MIN Duty = 5000%(X100), DQS PI = 18
2423 13:38:49.427933 [4] AVG Duty = 5046%(X100)
2424 13:38:49.427999
2425 13:38:49.428080 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2426 13:38:49.428133
2427 13:38:49.428217 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2428 13:38:49.428300 [DutyScan_Calibration_Flow] ====Done====
2429 13:38:49.428383 ==
2430 13:38:49.428458 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 13:38:49.428568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 13:38:49.428625 ==
2433 13:38:49.428679 [Duty_Offset_Calibration]
2434 13:38:49.428783 B0:0 B1:-1 CA:2
2435 13:38:49.428838
2436 13:38:49.428919 [DutyScan_Calibration_Flow] k_type=0
2437 13:38:49.428972
2438 13:38:49.429024 ==CLK 0==
2439 13:38:49.429076 Final CLK duty delay cell = 0
2440 13:38:49.429129 [0] MAX Duty = 5156%(X100), DQS PI = 16
2441 13:38:49.429183 [0] MIN Duty = 4938%(X100), DQS PI = 46
2442 13:38:49.429236 [0] AVG Duty = 5047%(X100)
2443 13:38:49.429289
2444 13:38:49.429380 CH1 CLK Duty spec in!! Max-Min= 218%
2445 13:38:49.429434 [DutyScan_Calibration_Flow] ====Done====
2446 13:38:49.429487
2447 13:38:49.429540 [DutyScan_Calibration_Flow] k_type=1
2448 13:38:49.429592
2449 13:38:49.429645 ==DQS 0 ==
2450 13:38:49.429697 Final DQS duty delay cell = 0
2451 13:38:49.429749 [0] MAX Duty = 5093%(X100), DQS PI = 24
2452 13:38:49.429802 [0] MIN Duty = 4969%(X100), DQS PI = 0
2453 13:38:49.429883 [0] AVG Duty = 5031%(X100)
2454 13:38:49.429935
2455 13:38:49.429986 ==DQS 1 ==
2456 13:38:49.430039 Final DQS duty delay cell = 0
2457 13:38:49.430091 [0] MAX Duty = 5156%(X100), DQS PI = 0
2458 13:38:49.430143 [0] MIN Duty = 4844%(X100), DQS PI = 34
2459 13:38:49.430196 [0] AVG Duty = 5000%(X100)
2460 13:38:49.430248
2461 13:38:49.430300 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2462 13:38:49.430352
2463 13:38:49.430404 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2464 13:38:49.430456 [DutyScan_Calibration_Flow] ====Done====
2465 13:38:49.430508
2466 13:38:49.430560 [DutyScan_Calibration_Flow] k_type=3
2467 13:38:49.430612
2468 13:38:49.430664 ==DQM 0 ==
2469 13:38:49.430738 Final DQM duty delay cell = 4
2470 13:38:49.430823 [4] MAX Duty = 5093%(X100), DQS PI = 22
2471 13:38:49.430881 [4] MIN Duty = 4907%(X100), DQS PI = 46
2472 13:38:49.430935 [4] AVG Duty = 5000%(X100)
2473 13:38:49.431018
2474 13:38:49.431118 ==DQM 1 ==
2475 13:38:49.431201 Final DQM duty delay cell = -4
2476 13:38:49.431297 [-4] MAX Duty = 5000%(X100), DQS PI = 60
2477 13:38:49.431393 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2478 13:38:49.431502 [-4] AVG Duty = 4875%(X100)
2479 13:38:49.431604
2480 13:38:49.431684 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2481 13:38:49.431780
2482 13:38:49.431838 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2483 13:38:49.431895 [DutyScan_Calibration_Flow] ====Done====
2484 13:38:49.431949
2485 13:38:49.432002 [DutyScan_Calibration_Flow] k_type=2
2486 13:38:49.432055
2487 13:38:49.432108 ==DQ 0 ==
2488 13:38:49.432160 Final DQ duty delay cell = 0
2489 13:38:49.432214 [0] MAX Duty = 5062%(X100), DQS PI = 20
2490 13:38:49.432268 [0] MIN Duty = 4938%(X100), DQS PI = 0
2491 13:38:49.432322 [0] AVG Duty = 5000%(X100)
2492 13:38:49.432374
2493 13:38:49.432427 ==DQ 1 ==
2494 13:38:49.432479 Final DQ duty delay cell = 0
2495 13:38:49.432531 [0] MAX Duty = 5031%(X100), DQS PI = 2
2496 13:38:49.432584 [0] MIN Duty = 4813%(X100), DQS PI = 36
2497 13:38:49.432637 [0] AVG Duty = 4922%(X100)
2498 13:38:49.432689
2499 13:38:49.432740 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2500 13:38:49.432835
2501 13:38:49.432901 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2502 13:38:49.432953 [DutyScan_Calibration_Flow] ====Done====
2503 13:38:49.433006 nWR fixed to 30
2504 13:38:49.433059 [ModeRegInit_LP4] CH0 RK0
2505 13:38:49.433111 [ModeRegInit_LP4] CH0 RK1
2506 13:38:49.433179 [ModeRegInit_LP4] CH1 RK0
2507 13:38:49.433232 [ModeRegInit_LP4] CH1 RK1
2508 13:38:49.433285 match AC timing 7
2509 13:38:49.433367 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 13:38:49.433421 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 13:38:49.433474 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 13:38:49.433527 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 13:38:49.433581 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 13:38:49.433634 ==
2515 13:38:49.433686 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 13:38:49.433740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 13:38:49.433792 ==
2518 13:38:49.433845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 13:38:49.433897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 13:38:49.433950 [CA 0] Center 38 (7~69) winsize 63
2521 13:38:49.434002 [CA 1] Center 38 (8~69) winsize 62
2522 13:38:49.434055 [CA 2] Center 35 (5~66) winsize 62
2523 13:38:49.434107 [CA 3] Center 35 (4~66) winsize 63
2524 13:38:49.434159 [CA 4] Center 34 (4~65) winsize 62
2525 13:38:49.434211 [CA 5] Center 33 (3~63) winsize 61
2526 13:38:49.434277
2527 13:38:49.434344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 13:38:49.434396
2529 13:38:49.434448 [CATrainingPosCal] consider 1 rank data
2530 13:38:49.434536 u2DelayCellTimex100 = 270/100 ps
2531 13:38:49.434649 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2532 13:38:49.434749 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2533 13:38:49.434847 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 13:38:49.434925 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2535 13:38:49.435013 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 13:38:49.435070 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 13:38:49.435124
2538 13:38:49.435177 CA PerBit enable=1, Macro0, CA PI delay=33
2539 13:38:49.435230
2540 13:38:49.435283 [CBTSetCACLKResult] CA Dly = 33
2541 13:38:49.435336 CS Dly: 6 (0~37)
2542 13:38:49.435388 ==
2543 13:38:49.435441 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 13:38:49.435494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 13:38:49.435548 ==
2546 13:38:49.435600 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 13:38:49.435654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 13:38:49.435706 [CA 0] Center 39 (8~70) winsize 63
2549 13:38:49.435759 [CA 1] Center 38 (8~69) winsize 62
2550 13:38:49.435828 [CA 2] Center 35 (5~66) winsize 62
2551 13:38:49.435894 [CA 3] Center 35 (5~66) winsize 62
2552 13:38:49.435946 [CA 4] Center 34 (4~65) winsize 62
2553 13:38:49.435999 [CA 5] Center 34 (4~64) winsize 61
2554 13:38:49.436051
2555 13:38:49.436325 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2556 13:38:49.436387
2557 13:38:49.436455 [CATrainingPosCal] consider 2 rank data
2558 13:38:49.436508 u2DelayCellTimex100 = 270/100 ps
2559 13:38:49.436561 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2560 13:38:49.436614 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2561 13:38:49.436684 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 13:38:49.436737 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 13:38:49.436791 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 13:38:49.436844 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2565 13:38:49.436910
2566 13:38:49.436962 CA PerBit enable=1, Macro0, CA PI delay=33
2567 13:38:49.437015
2568 13:38:49.437066 [CBTSetCACLKResult] CA Dly = 33
2569 13:38:49.437119 CS Dly: 7 (0~39)
2570 13:38:49.437171
2571 13:38:49.437223 ----->DramcWriteLeveling(PI) begin...
2572 13:38:49.437291 ==
2573 13:38:49.437388 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 13:38:49.437443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 13:38:49.437497 ==
2576 13:38:49.437553 Write leveling (Byte 0): 33 => 33
2577 13:38:49.437644 Write leveling (Byte 1): 31 => 31
2578 13:38:49.437762 DramcWriteLeveling(PI) end<-----
2579 13:38:49.437868
2580 13:38:49.437962 ==
2581 13:38:49.438020 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 13:38:49.438092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 13:38:49.438161 ==
2584 13:38:49.438213 [Gating] SW mode calibration
2585 13:38:49.438266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 13:38:49.438320 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 13:38:49.438374 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2588 13:38:49.438427 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2589 13:38:49.438481 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 13:38:49.438533 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 13:38:49.438586 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 13:38:49.438638 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 13:38:49.438691 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2594 13:38:49.438744 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2595 13:38:49.438795 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2596 13:38:49.438848 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 13:38:49.438901 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 13:38:49.438953 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 13:38:49.439005 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 13:38:49.439058 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 13:38:49.439110 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2602 13:38:49.439163 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2603 13:38:49.439216 1 1 0 | B1->B0 | 3332 4646 | 1 0 | (0 0) (0 0)
2604 13:38:49.439268 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 13:38:49.439320 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 13:38:49.439374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 13:38:49.439427 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 13:38:49.439479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 13:38:49.439531 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 13:38:49.439583 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 13:38:49.439635 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 13:38:49.439688 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 13:38:49.439741 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 13:38:49.439793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 13:38:49.439845 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 13:38:49.439898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 13:38:49.439950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 13:38:49.440003 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 13:38:49.440055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 13:38:49.440107 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 13:38:49.440159 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 13:38:49.440212 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 13:38:49.440264 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 13:38:49.440316 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 13:38:49.440369 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 13:38:49.440422 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2627 13:38:49.440475 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 13:38:49.440527 Total UI for P1: 0, mck2ui 16
2629 13:38:49.440597 best dqsien dly found for B0: ( 1, 3, 28)
2630 13:38:49.440672 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 13:38:49.440754 Total UI for P1: 0, mck2ui 16
2632 13:38:49.440887 best dqsien dly found for B1: ( 1, 3, 30)
2633 13:38:49.441006 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 13:38:49.441100 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2635 13:38:49.441194
2636 13:38:49.441292 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 13:38:49.441416 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2638 13:38:49.441478 [Gating] SW calibration Done
2639 13:38:49.441536 ==
2640 13:38:49.441592 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 13:38:49.441648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 13:38:49.441703 ==
2643 13:38:49.441757 RX Vref Scan: 0
2644 13:38:49.441811
2645 13:38:49.441864 RX Vref 0 -> 0, step: 1
2646 13:38:49.441917
2647 13:38:49.441969 RX Delay -40 -> 252, step: 8
2648 13:38:49.442022 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2649 13:38:49.442075 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2650 13:38:49.442128 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2651 13:38:49.442180 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2652 13:38:49.442233 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2653 13:38:49.442286 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2654 13:38:49.442337 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2655 13:38:49.442389 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2656 13:38:49.442442 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2657 13:38:49.442498 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2658 13:38:49.442761 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2659 13:38:49.442841 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2660 13:38:49.442909 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2661 13:38:49.442964 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2662 13:38:49.443019 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2663 13:38:49.443074 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2664 13:38:49.443142 ==
2665 13:38:49.443196 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 13:38:49.443263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 13:38:49.443317 ==
2668 13:38:49.443369 DQS Delay:
2669 13:38:49.443420 DQS0 = 0, DQS1 = 0
2670 13:38:49.443472 DQM Delay:
2671 13:38:49.443523 DQM0 = 123, DQM1 = 110
2672 13:38:49.443575 DQ Delay:
2673 13:38:49.443627 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2674 13:38:49.443680 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2675 13:38:49.443731 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2676 13:38:49.443784 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2677 13:38:49.443836
2678 13:38:49.443888
2679 13:38:49.443939 ==
2680 13:38:49.443991 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 13:38:49.444044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 13:38:49.444098 ==
2683 13:38:49.444150
2684 13:38:49.444218
2685 13:38:49.444271 TX Vref Scan disable
2686 13:38:49.444338 == TX Byte 0 ==
2687 13:38:49.444391 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2688 13:38:49.444443 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2689 13:38:49.444496 == TX Byte 1 ==
2690 13:38:49.444548 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2691 13:38:49.444601 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2692 13:38:49.444653 ==
2693 13:38:49.444744 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 13:38:49.444796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 13:38:49.444849 ==
2696 13:38:49.444901 TX Vref=22, minBit 1, minWin=24, winSum=411
2697 13:38:49.444954 TX Vref=24, minBit 0, minWin=25, winSum=411
2698 13:38:49.445006 TX Vref=26, minBit 0, minWin=25, winSum=415
2699 13:38:49.445058 TX Vref=28, minBit 2, minWin=25, winSum=421
2700 13:38:49.445110 TX Vref=30, minBit 4, minWin=25, winSum=424
2701 13:38:49.445162 TX Vref=32, minBit 1, minWin=25, winSum=421
2702 13:38:49.445214 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 30
2703 13:38:49.445267
2704 13:38:49.445357 Final TX Range 1 Vref 30
2705 13:38:49.445409
2706 13:38:49.445461 ==
2707 13:38:49.445514 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 13:38:49.445566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 13:38:49.445659 ==
2710 13:38:49.445710
2711 13:38:49.445762
2712 13:38:49.445813 TX Vref Scan disable
2713 13:38:49.445865 == TX Byte 0 ==
2714 13:38:49.445917 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2715 13:38:49.446001 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2716 13:38:49.446053 == TX Byte 1 ==
2717 13:38:49.446104 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2718 13:38:49.446157 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2719 13:38:49.446208
2720 13:38:49.446260 [DATLAT]
2721 13:38:49.446311 Freq=1200, CH0 RK0
2722 13:38:49.446364
2723 13:38:49.446415 DATLAT Default: 0xd
2724 13:38:49.446467 0, 0xFFFF, sum = 0
2725 13:38:49.446520 1, 0xFFFF, sum = 0
2726 13:38:49.446573 2, 0xFFFF, sum = 0
2727 13:38:49.446625 3, 0xFFFF, sum = 0
2728 13:38:49.446678 4, 0xFFFF, sum = 0
2729 13:38:49.446749 5, 0xFFFF, sum = 0
2730 13:38:49.446815 6, 0xFFFF, sum = 0
2731 13:38:49.446867 7, 0xFFFF, sum = 0
2732 13:38:49.446920 8, 0xFFFF, sum = 0
2733 13:38:49.446972 9, 0xFFFF, sum = 0
2734 13:38:49.447025 10, 0xFFFF, sum = 0
2735 13:38:49.447077 11, 0xFFFF, sum = 0
2736 13:38:49.447130 12, 0x0, sum = 1
2737 13:38:49.447183 13, 0x0, sum = 2
2738 13:38:49.447235 14, 0x0, sum = 3
2739 13:38:49.447287 15, 0x0, sum = 4
2740 13:38:49.447369 best_step = 13
2741 13:38:49.447421
2742 13:38:49.447511 ==
2743 13:38:49.447563 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 13:38:49.447615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 13:38:49.447668 ==
2746 13:38:49.447736 RX Vref Scan: 1
2747 13:38:49.447801
2748 13:38:49.447853 Set Vref Range= 32 -> 127
2749 13:38:49.447904
2750 13:38:49.447955 RX Vref 32 -> 127, step: 1
2751 13:38:49.448036
2752 13:38:49.448088 RX Delay -13 -> 252, step: 4
2753 13:38:49.448139
2754 13:38:49.448191 Set Vref, RX VrefLevel [Byte0]: 32
2755 13:38:49.448243 [Byte1]: 32
2756 13:38:49.448295
2757 13:38:49.448347 Set Vref, RX VrefLevel [Byte0]: 33
2758 13:38:49.448398 [Byte1]: 33
2759 13:38:49.448450
2760 13:38:49.448501 Set Vref, RX VrefLevel [Byte0]: 34
2761 13:38:49.448553 [Byte1]: 34
2762 13:38:49.448606
2763 13:38:49.448658 Set Vref, RX VrefLevel [Byte0]: 35
2764 13:38:49.448710 [Byte1]: 35
2765 13:38:49.448761
2766 13:38:49.448813 Set Vref, RX VrefLevel [Byte0]: 36
2767 13:38:49.448866 [Byte1]: 36
2768 13:38:49.448917
2769 13:38:49.448969 Set Vref, RX VrefLevel [Byte0]: 37
2770 13:38:49.449020 [Byte1]: 37
2771 13:38:49.449072
2772 13:38:49.449124 Set Vref, RX VrefLevel [Byte0]: 38
2773 13:38:49.449176 [Byte1]: 38
2774 13:38:49.449228
2775 13:38:49.449280 Set Vref, RX VrefLevel [Byte0]: 39
2776 13:38:49.449373 [Byte1]: 39
2777 13:38:49.449426
2778 13:38:49.449478 Set Vref, RX VrefLevel [Byte0]: 40
2779 13:38:49.449530 [Byte1]: 40
2780 13:38:49.449582
2781 13:38:49.449633 Set Vref, RX VrefLevel [Byte0]: 41
2782 13:38:49.449685 [Byte1]: 41
2783 13:38:49.449737
2784 13:38:49.449788 Set Vref, RX VrefLevel [Byte0]: 42
2785 13:38:49.449840 [Byte1]: 42
2786 13:38:49.449892
2787 13:38:49.449944 Set Vref, RX VrefLevel [Byte0]: 43
2788 13:38:49.449995 [Byte1]: 43
2789 13:38:49.450048
2790 13:38:49.450099 Set Vref, RX VrefLevel [Byte0]: 44
2791 13:38:49.450151 [Byte1]: 44
2792 13:38:49.450203
2793 13:38:49.450256 Set Vref, RX VrefLevel [Byte0]: 45
2794 13:38:49.450349 [Byte1]: 45
2795 13:38:49.450423
2796 13:38:49.450478 Set Vref, RX VrefLevel [Byte0]: 46
2797 13:38:49.450531 [Byte1]: 46
2798 13:38:49.450584
2799 13:38:49.450636 Set Vref, RX VrefLevel [Byte0]: 47
2800 13:38:49.450704 [Byte1]: 47
2801 13:38:49.450808
2802 13:38:49.450864 Set Vref, RX VrefLevel [Byte0]: 48
2803 13:38:49.450966 [Byte1]: 48
2804 13:38:49.451095
2805 13:38:49.451188 Set Vref, RX VrefLevel [Byte0]: 49
2806 13:38:49.451255 [Byte1]: 49
2807 13:38:49.451308
2808 13:38:49.451361 Set Vref, RX VrefLevel [Byte0]: 50
2809 13:38:49.451414 [Byte1]: 50
2810 13:38:49.451467
2811 13:38:49.451520 Set Vref, RX VrefLevel [Byte0]: 51
2812 13:38:49.451610 [Byte1]: 51
2813 13:38:49.451662
2814 13:38:49.451715 Set Vref, RX VrefLevel [Byte0]: 52
2815 13:38:49.451767 [Byte1]: 52
2816 13:38:49.451819
2817 13:38:49.451871 Set Vref, RX VrefLevel [Byte0]: 53
2818 13:38:49.451940 [Byte1]: 53
2819 13:38:49.452005
2820 13:38:49.452057 Set Vref, RX VrefLevel [Byte0]: 54
2821 13:38:49.452315 [Byte1]: 54
2822 13:38:49.452375
2823 13:38:49.452429 Set Vref, RX VrefLevel [Byte0]: 55
2824 13:38:49.452524 [Byte1]: 55
2825 13:38:49.452577
2826 13:38:49.452645 Set Vref, RX VrefLevel [Byte0]: 56
2827 13:38:49.452718 [Byte1]: 56
2828 13:38:49.452796
2829 13:38:49.452849 Set Vref, RX VrefLevel [Byte0]: 57
2830 13:38:49.452901 [Byte1]: 57
2831 13:38:49.452953
2832 13:38:49.453005 Set Vref, RX VrefLevel [Byte0]: 58
2833 13:38:49.453058 [Byte1]: 58
2834 13:38:49.453110
2835 13:38:49.453162 Set Vref, RX VrefLevel [Byte0]: 59
2836 13:38:49.453214 [Byte1]: 59
2837 13:38:49.453266
2838 13:38:49.453364 Set Vref, RX VrefLevel [Byte0]: 60
2839 13:38:49.453419 [Byte1]: 60
2840 13:38:49.453471
2841 13:38:49.453523 Set Vref, RX VrefLevel [Byte0]: 61
2842 13:38:49.453575 [Byte1]: 61
2843 13:38:49.453627
2844 13:38:49.453679 Set Vref, RX VrefLevel [Byte0]: 62
2845 13:38:49.453731 [Byte1]: 62
2846 13:38:49.453784
2847 13:38:49.453836 Set Vref, RX VrefLevel [Byte0]: 63
2848 13:38:49.453888 [Byte1]: 63
2849 13:38:49.453940
2850 13:38:49.453991 Set Vref, RX VrefLevel [Byte0]: 64
2851 13:38:49.454045 [Byte1]: 64
2852 13:38:49.454114
2853 13:38:49.454180 Set Vref, RX VrefLevel [Byte0]: 65
2854 13:38:49.454249 [Byte1]: 65
2855 13:38:49.454328
2856 13:38:49.454395 Set Vref, RX VrefLevel [Byte0]: 66
2857 13:38:49.454447 [Byte1]: 66
2858 13:38:49.454499
2859 13:38:49.454551 Set Vref, RX VrefLevel [Byte0]: 67
2860 13:38:49.454603 [Byte1]: 67
2861 13:38:49.454684
2862 13:38:49.454739 Set Vref, RX VrefLevel [Byte0]: 68
2863 13:38:49.454791 [Byte1]: 68
2864 13:38:49.454843
2865 13:38:49.454895 Set Vref, RX VrefLevel [Byte0]: 69
2866 13:38:49.454948 [Byte1]: 69
2867 13:38:49.454999
2868 13:38:49.455051 Set Vref, RX VrefLevel [Byte0]: 70
2869 13:38:49.455103 [Byte1]: 70
2870 13:38:49.455154
2871 13:38:49.455206 Final RX Vref Byte 0 = 58 to rank0
2872 13:38:49.455258 Final RX Vref Byte 1 = 50 to rank0
2873 13:38:49.455311 Final RX Vref Byte 0 = 58 to rank1
2874 13:38:49.455363 Final RX Vref Byte 1 = 50 to rank1==
2875 13:38:49.455416 Dram Type= 6, Freq= 0, CH_0, rank 0
2876 13:38:49.455468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 13:38:49.455521 ==
2878 13:38:49.455573 DQS Delay:
2879 13:38:49.455625 DQS0 = 0, DQS1 = 0
2880 13:38:49.455677 DQM Delay:
2881 13:38:49.455728 DQM0 = 122, DQM1 = 109
2882 13:38:49.455780 DQ Delay:
2883 13:38:49.455832 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2884 13:38:49.455884 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2885 13:38:49.455936 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2886 13:38:49.455989 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2887 13:38:49.456041
2888 13:38:49.456091
2889 13:38:49.456175 [DQSOSCAuto] RK0, (LSB)MR18= 0xd09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2890 13:38:49.456228 CH0 RK0: MR19=404, MR18=D09
2891 13:38:49.456280 CH0_RK0: MR19=0x404, MR18=0xD09, DQSOSC=405, MR23=63, INC=39, DEC=26
2892 13:38:49.456334
2893 13:38:49.456386 ----->DramcWriteLeveling(PI) begin...
2894 13:38:49.456438 ==
2895 13:38:49.456490 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 13:38:49.456543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 13:38:49.456595 ==
2898 13:38:49.456687 Write leveling (Byte 0): 33 => 33
2899 13:38:49.456773 Write leveling (Byte 1): 30 => 30
2900 13:38:49.456848 DramcWriteLeveling(PI) end<-----
2901 13:38:49.456909
2902 13:38:49.456962 ==
2903 13:38:49.457016 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 13:38:49.457069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 13:38:49.457123 ==
2906 13:38:49.457175 [Gating] SW mode calibration
2907 13:38:49.457228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2908 13:38:49.457281 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2909 13:38:49.457379 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2910 13:38:49.457433 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 13:38:49.457486 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 13:38:49.457554 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 13:38:49.457621 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 13:38:49.457703 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 13:38:49.457756 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 13:38:49.457824 0 15 28 | B1->B0 | 2d2d 2b2b | 1 0 | (1 0) (0 0)
2917 13:38:49.457878 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2918 13:38:49.457944 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 13:38:49.457996 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 13:38:49.458048 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 13:38:49.458101 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 13:38:49.458154 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 13:38:49.458206 1 0 24 | B1->B0 | 2525 2a2a | 1 1 | (0 0) (1 1)
2924 13:38:49.458259 1 0 28 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (1 1)
2925 13:38:49.458310 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 13:38:49.458363 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 13:38:49.458415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 13:38:49.458469 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 13:38:49.458522 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 13:38:49.458574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 13:38:49.458627 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2932 13:38:49.458679 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2933 13:38:49.458731 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 13:38:49.458784 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 13:38:49.458836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 13:38:49.458889 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 13:38:49.458941 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 13:38:49.458994 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 13:38:49.459046 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 13:38:49.459098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 13:38:49.459355 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 13:38:49.459468 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 13:38:49.459523 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 13:38:49.459577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 13:38:49.459631 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 13:38:49.459684 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 13:38:49.459737 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2948 13:38:49.459818 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2949 13:38:49.459872 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 13:38:49.459938 Total UI for P1: 0, mck2ui 16
2951 13:38:49.459991 best dqsien dly found for B0: ( 1, 3, 26)
2952 13:38:49.460044 Total UI for P1: 0, mck2ui 16
2953 13:38:49.460097 best dqsien dly found for B1: ( 1, 3, 28)
2954 13:38:49.460149 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2955 13:38:49.460201 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2956 13:38:49.460253
2957 13:38:49.460305 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2958 13:38:49.460357 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2959 13:38:49.460467 [Gating] SW calibration Done
2960 13:38:49.460519 ==
2961 13:38:49.460572 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 13:38:49.460624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 13:38:49.460678 ==
2964 13:38:49.460730 RX Vref Scan: 0
2965 13:38:49.460782
2966 13:38:49.460834 RX Vref 0 -> 0, step: 1
2967 13:38:49.460886
2968 13:38:49.460937 RX Delay -40 -> 252, step: 8
2969 13:38:49.460989 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2970 13:38:49.461042 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2971 13:38:49.461094 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2972 13:38:49.461146 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2973 13:38:49.461199 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2974 13:38:49.461251 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2975 13:38:49.461330 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2976 13:38:49.461398 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2977 13:38:49.461450 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2978 13:38:49.461502 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2979 13:38:49.461554 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2980 13:38:49.461606 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2981 13:38:49.461658 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2982 13:38:49.461710 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2983 13:38:49.461762 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2984 13:38:49.461814 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2985 13:38:49.461866 ==
2986 13:38:49.461918 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 13:38:49.461970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 13:38:49.462023 ==
2989 13:38:49.462075 DQS Delay:
2990 13:38:49.462126 DQS0 = 0, DQS1 = 0
2991 13:38:49.462178 DQM Delay:
2992 13:38:49.462229 DQM0 = 120, DQM1 = 108
2993 13:38:49.462282 DQ Delay:
2994 13:38:49.462334 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2995 13:38:49.462386 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2996 13:38:49.462438 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2997 13:38:49.462490 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2998 13:38:49.462542
2999 13:38:49.462594
3000 13:38:49.462645 ==
3001 13:38:49.462697 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 13:38:49.462750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 13:38:49.610852 ==
3004 13:38:49.611082
3005 13:38:49.611220
3006 13:38:49.611324 TX Vref Scan disable
3007 13:38:49.611486 == TX Byte 0 ==
3008 13:38:49.611624 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3009 13:38:49.611742 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3010 13:38:49.611886 == TX Byte 1 ==
3011 13:38:49.611982 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3012 13:38:49.612071 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3013 13:38:49.612157 ==
3014 13:38:49.612244 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 13:38:49.612330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 13:38:49.612453 ==
3017 13:38:49.612581 TX Vref=22, minBit 1, minWin=24, winSum=416
3018 13:38:49.612677 TX Vref=24, minBit 0, minWin=25, winSum=418
3019 13:38:49.612774 TX Vref=26, minBit 0, minWin=25, winSum=423
3020 13:38:49.612868 TX Vref=28, minBit 1, minWin=25, winSum=428
3021 13:38:49.612957 TX Vref=30, minBit 1, minWin=25, winSum=428
3022 13:38:49.613045 TX Vref=32, minBit 0, minWin=26, winSum=425
3023 13:38:49.613101 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
3024 13:38:49.613189
3025 13:38:49.613276 Final TX Range 1 Vref 32
3026 13:38:49.613395
3027 13:38:49.613454 ==
3028 13:38:49.613509 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 13:38:49.613564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 13:38:49.613619 ==
3031 13:38:49.613674
3032 13:38:49.613728
3033 13:38:49.613782 TX Vref Scan disable
3034 13:38:49.613836 == TX Byte 0 ==
3035 13:38:49.613897 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3036 13:38:49.613954 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3037 13:38:49.614008 == TX Byte 1 ==
3038 13:38:49.614062 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3039 13:38:49.614116 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3040 13:38:49.614170
3041 13:38:49.614223 [DATLAT]
3042 13:38:49.614284 Freq=1200, CH0 RK1
3043 13:38:49.614342
3044 13:38:49.614396 DATLAT Default: 0xd
3045 13:38:49.614450 0, 0xFFFF, sum = 0
3046 13:38:49.614505 1, 0xFFFF, sum = 0
3047 13:38:49.614560 2, 0xFFFF, sum = 0
3048 13:38:49.614614 3, 0xFFFF, sum = 0
3049 13:38:49.614669 4, 0xFFFF, sum = 0
3050 13:38:49.614723 5, 0xFFFF, sum = 0
3051 13:38:49.614778 6, 0xFFFF, sum = 0
3052 13:38:49.614832 7, 0xFFFF, sum = 0
3053 13:38:49.614886 8, 0xFFFF, sum = 0
3054 13:38:49.614940 9, 0xFFFF, sum = 0
3055 13:38:49.614995 10, 0xFFFF, sum = 0
3056 13:38:49.615049 11, 0xFFFF, sum = 0
3057 13:38:49.615103 12, 0x0, sum = 1
3058 13:38:49.615157 13, 0x0, sum = 2
3059 13:38:49.615210 14, 0x0, sum = 3
3060 13:38:49.615264 15, 0x0, sum = 4
3061 13:38:49.615317 best_step = 13
3062 13:38:49.615370
3063 13:38:49.615423 ==
3064 13:38:49.615476 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 13:38:49.615529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 13:38:49.615585 ==
3067 13:38:49.615670 RX Vref Scan: 0
3068 13:38:49.615727
3069 13:38:49.615780 RX Vref 0 -> 0, step: 1
3070 13:38:49.615834
3071 13:38:49.615887 RX Delay -21 -> 252, step: 4
3072 13:38:49.615941 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3073 13:38:49.615995 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3074 13:38:49.616048 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3075 13:38:49.616102 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3076 13:38:49.616155 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3077 13:38:49.616208 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3078 13:38:49.616262 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3079 13:38:49.616562 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3080 13:38:49.616707 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3081 13:38:49.616767 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3082 13:38:49.616822 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3083 13:38:49.616877 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3084 13:38:49.616930 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3085 13:38:49.616984 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3086 13:38:49.617038 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3087 13:38:49.617092 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3088 13:38:49.617145 ==
3089 13:38:49.617198 Dram Type= 6, Freq= 0, CH_0, rank 1
3090 13:38:49.617252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 13:38:49.617319 ==
3092 13:38:49.617375 DQS Delay:
3093 13:38:49.617429 DQS0 = 0, DQS1 = 0
3094 13:38:49.617482 DQM Delay:
3095 13:38:49.617535 DQM0 = 119, DQM1 = 107
3096 13:38:49.617589 DQ Delay:
3097 13:38:49.617642 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3098 13:38:49.617696 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3099 13:38:49.617749 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3100 13:38:49.617802 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3101 13:38:49.617856
3102 13:38:49.617908
3103 13:38:49.617962 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3104 13:38:49.618016 CH0 RK1: MR19=403, MR18=12F8
3105 13:38:49.618070 CH0_RK1: MR19=0x403, MR18=0x12F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3106 13:38:49.618124 [RxdqsGatingPostProcess] freq 1200
3107 13:38:49.618194 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3108 13:38:49.618277 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 13:38:49.618331 best DQS1 dly(2T, 0.5T) = (0, 11)
3110 13:38:49.618385 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 13:38:49.618439 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3112 13:38:49.618492 best DQS0 dly(2T, 0.5T) = (0, 11)
3113 13:38:49.618545 best DQS1 dly(2T, 0.5T) = (0, 11)
3114 13:38:49.618599 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3115 13:38:49.618652 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3116 13:38:49.618706 Pre-setting of DQS Precalculation
3117 13:38:49.618760 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3118 13:38:49.618814 ==
3119 13:38:49.618867 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 13:38:49.618937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 13:38:49.619022 ==
3122 13:38:49.619137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 13:38:49.619208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3124 13:38:49.619263 [CA 0] Center 37 (7~68) winsize 62
3125 13:38:49.619318 [CA 1] Center 37 (7~68) winsize 62
3126 13:38:49.619371 [CA 2] Center 35 (5~65) winsize 61
3127 13:38:49.619425 [CA 3] Center 34 (4~65) winsize 62
3128 13:38:49.619524 [CA 4] Center 34 (4~65) winsize 62
3129 13:38:49.619635 [CA 5] Center 33 (3~64) winsize 62
3130 13:38:49.619705
3131 13:38:49.619758 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3132 13:38:49.619812
3133 13:38:49.619866 [CATrainingPosCal] consider 1 rank data
3134 13:38:49.619920 u2DelayCellTimex100 = 270/100 ps
3135 13:38:49.619973 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3136 13:38:49.620027 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3137 13:38:49.620081 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3138 13:38:49.620135 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3139 13:38:49.620188 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3140 13:38:49.620242 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 13:38:49.620309
3142 13:38:49.620414 CA PerBit enable=1, Macro0, CA PI delay=33
3143 13:38:49.620468
3144 13:38:49.620521 [CBTSetCACLKResult] CA Dly = 33
3145 13:38:49.620574 CS Dly: 5 (0~36)
3146 13:38:49.620628 ==
3147 13:38:49.620681 Dram Type= 6, Freq= 0, CH_1, rank 1
3148 13:38:49.620735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3149 13:38:49.620789 ==
3150 13:38:49.620843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3151 13:38:49.620897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3152 13:38:49.620951 [CA 0] Center 38 (8~68) winsize 61
3153 13:38:49.621005 [CA 1] Center 38 (8~68) winsize 61
3154 13:38:49.621058 [CA 2] Center 35 (5~66) winsize 62
3155 13:38:49.621113 [CA 3] Center 34 (4~65) winsize 62
3156 13:38:49.621166 [CA 4] Center 35 (5~65) winsize 61
3157 13:38:49.621219 [CA 5] Center 34 (4~65) winsize 62
3158 13:38:49.621272
3159 13:38:49.621365 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3160 13:38:49.621420
3161 13:38:49.621474 [CATrainingPosCal] consider 2 rank data
3162 13:38:49.621528 u2DelayCellTimex100 = 270/100 ps
3163 13:38:49.621582 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3164 13:38:49.621635 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3165 13:38:49.621689 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3166 13:38:49.621743 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3167 13:38:49.621797 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3168 13:38:49.621850 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3169 13:38:49.621903
3170 13:38:49.621956 CA PerBit enable=1, Macro0, CA PI delay=34
3171 13:38:49.622009
3172 13:38:49.622062 [CBTSetCACLKResult] CA Dly = 34
3173 13:38:49.622115 CS Dly: 6 (0~38)
3174 13:38:49.622169
3175 13:38:49.622221 ----->DramcWriteLeveling(PI) begin...
3176 13:38:49.622277 ==
3177 13:38:49.622330 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 13:38:49.622417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 13:38:49.622475 ==
3180 13:38:49.622530 Write leveling (Byte 0): 24 => 24
3181 13:38:49.622585 Write leveling (Byte 1): 28 => 28
3182 13:38:49.622639 DramcWriteLeveling(PI) end<-----
3183 13:38:49.622694
3184 13:38:49.622747 ==
3185 13:38:49.622801 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 13:38:49.622855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 13:38:49.622909 ==
3188 13:38:49.622963 [Gating] SW mode calibration
3189 13:38:49.623017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3190 13:38:49.623071 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3191 13:38:49.623125 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 13:38:49.623185 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 13:38:49.623262 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 13:38:49.623319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 13:38:49.623374 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 13:38:49.623429 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3197 13:38:49.623686 0 15 24 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
3198 13:38:49.623749 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 13:38:49.623804 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 13:38:49.623859 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 13:38:49.623914 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 13:38:49.623968 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 13:38:49.624022 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 13:38:49.624076 1 0 20 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
3205 13:38:49.624130 1 0 24 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
3206 13:38:49.624184 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 13:38:49.624238 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 13:38:49.624292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 13:38:49.624346 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 13:38:49.624400 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 13:38:49.624454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 13:38:49.624508 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 13:38:49.624562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3214 13:38:49.624615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3215 13:38:49.624669 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 13:38:49.624722 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 13:38:49.624777 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 13:38:49.624831 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 13:38:49.624884 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 13:38:49.624954 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 13:38:49.625022 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 13:38:49.625076 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 13:38:49.625130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 13:38:49.625184 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 13:38:49.625238 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 13:38:49.625292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 13:38:49.625386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 13:38:49.625440 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3229 13:38:49.625494 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3230 13:38:49.625547 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 13:38:49.625601 Total UI for P1: 0, mck2ui 16
3232 13:38:49.625655 best dqsien dly found for B0: ( 1, 3, 22)
3233 13:38:49.625709 Total UI for P1: 0, mck2ui 16
3234 13:38:49.625763 best dqsien dly found for B1: ( 1, 3, 24)
3235 13:38:49.625817 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3236 13:38:49.625871 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3237 13:38:49.625937
3238 13:38:49.626004 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3239 13:38:49.626059 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3240 13:38:49.626113 [Gating] SW calibration Done
3241 13:38:49.626167 ==
3242 13:38:49.626260 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 13:38:49.626315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 13:38:49.626396 ==
3245 13:38:49.626452 RX Vref Scan: 0
3246 13:38:49.626506
3247 13:38:49.626560 RX Vref 0 -> 0, step: 1
3248 13:38:49.626614
3249 13:38:49.626667 RX Delay -40 -> 252, step: 8
3250 13:38:49.626721 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3251 13:38:49.626776 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3252 13:38:49.626830 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3253 13:38:49.626884 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3254 13:38:49.626937 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3255 13:38:49.626991 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3256 13:38:49.627045 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3257 13:38:49.627099 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3258 13:38:49.627152 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3259 13:38:49.627206 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3260 13:38:49.627260 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3261 13:38:49.627314 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3262 13:38:49.627399 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3263 13:38:49.627453 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3264 13:38:49.627507 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3265 13:38:49.627561 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3266 13:38:49.627615 ==
3267 13:38:49.627686 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 13:38:49.627783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 13:38:49.627837 ==
3270 13:38:49.627890 DQS Delay:
3271 13:38:49.627944 DQS0 = 0, DQS1 = 0
3272 13:38:49.627998 DQM Delay:
3273 13:38:49.628051 DQM0 = 119, DQM1 = 113
3274 13:38:49.628105 DQ Delay:
3275 13:38:49.628158 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3276 13:38:49.628212 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3277 13:38:49.628266 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3278 13:38:49.628320 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3279 13:38:49.628373
3280 13:38:49.628427
3281 13:38:49.628480 ==
3282 13:38:49.628534 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 13:38:49.628588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 13:38:49.628642 ==
3285 13:38:49.628696
3286 13:38:49.628749
3287 13:38:49.628802 TX Vref Scan disable
3288 13:38:49.628855 == TX Byte 0 ==
3289 13:38:49.628908 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3290 13:38:49.628963 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3291 13:38:49.629017 == TX Byte 1 ==
3292 13:38:49.629071 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3293 13:38:49.629126 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3294 13:38:49.629179 ==
3295 13:38:49.629233 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 13:38:49.629307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 13:38:49.629379 ==
3298 13:38:49.629434 TX Vref=22, minBit 1, minWin=24, winSum=404
3299 13:38:49.629493 TX Vref=24, minBit 11, minWin=24, winSum=409
3300 13:38:49.629578 TX Vref=26, minBit 8, minWin=25, winSum=417
3301 13:38:49.629635 TX Vref=28, minBit 8, minWin=25, winSum=420
3302 13:38:49.629690 TX Vref=30, minBit 11, minWin=25, winSum=424
3303 13:38:49.629745 TX Vref=32, minBit 0, minWin=26, winSum=421
3304 13:38:49.629830 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 32
3305 13:38:49.629902
3306 13:38:49.630193 Final TX Range 1 Vref 32
3307 13:38:49.630283
3308 13:38:49.630339 ==
3309 13:38:49.630394 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 13:38:49.630448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 13:38:49.630502 ==
3312 13:38:49.630556
3313 13:38:49.630609
3314 13:38:49.630663 TX Vref Scan disable
3315 13:38:49.630716 == TX Byte 0 ==
3316 13:38:49.630770 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3317 13:38:49.630824 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3318 13:38:49.630877 == TX Byte 1 ==
3319 13:38:49.630931 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3320 13:38:49.630984 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3321 13:38:49.631038
3322 13:38:49.631091 [DATLAT]
3323 13:38:49.631175 Freq=1200, CH1 RK0
3324 13:38:49.631229
3325 13:38:49.631282 DATLAT Default: 0xd
3326 13:38:49.631336 0, 0xFFFF, sum = 0
3327 13:38:49.631392 1, 0xFFFF, sum = 0
3328 13:38:49.631481 2, 0xFFFF, sum = 0
3329 13:38:49.631565 3, 0xFFFF, sum = 0
3330 13:38:49.631620 4, 0xFFFF, sum = 0
3331 13:38:49.631674 5, 0xFFFF, sum = 0
3332 13:38:49.631728 6, 0xFFFF, sum = 0
3333 13:38:49.631782 7, 0xFFFF, sum = 0
3334 13:38:49.631887 8, 0xFFFF, sum = 0
3335 13:38:49.631955 9, 0xFFFF, sum = 0
3336 13:38:49.632038 10, 0xFFFF, sum = 0
3337 13:38:49.632093 11, 0xFFFF, sum = 0
3338 13:38:49.632164 12, 0x0, sum = 1
3339 13:38:49.632219 13, 0x0, sum = 2
3340 13:38:49.632274 14, 0x0, sum = 3
3341 13:38:49.632330 15, 0x0, sum = 4
3342 13:38:49.632428 best_step = 13
3343 13:38:49.632515
3344 13:38:49.632569 ==
3345 13:38:49.632623 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 13:38:49.632677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 13:38:49.632731 ==
3348 13:38:49.632785 RX Vref Scan: 1
3349 13:38:49.632838
3350 13:38:49.632919 Set Vref Range= 32 -> 127
3351 13:38:49.632975
3352 13:38:49.633029 RX Vref 32 -> 127, step: 1
3353 13:38:49.633084
3354 13:38:49.633137 RX Delay -13 -> 252, step: 4
3355 13:38:49.633190
3356 13:38:49.633244 Set Vref, RX VrefLevel [Byte0]: 32
3357 13:38:49.633305 [Byte1]: 32
3358 13:38:49.633388
3359 13:38:49.633442 Set Vref, RX VrefLevel [Byte0]: 33
3360 13:38:49.633495 [Byte1]: 33
3361 13:38:49.633548
3362 13:38:49.633601 Set Vref, RX VrefLevel [Byte0]: 34
3363 13:38:49.633653 [Byte1]: 34
3364 13:38:49.633706
3365 13:38:49.633758 Set Vref, RX VrefLevel [Byte0]: 35
3366 13:38:49.633810 [Byte1]: 35
3367 13:38:49.633862
3368 13:38:49.633913 Set Vref, RX VrefLevel [Byte0]: 36
3369 13:38:49.633965 [Byte1]: 36
3370 13:38:49.634017
3371 13:38:49.634069 Set Vref, RX VrefLevel [Byte0]: 37
3372 13:38:49.634120 [Byte1]: 37
3373 13:38:49.634173
3374 13:38:49.634224 Set Vref, RX VrefLevel [Byte0]: 38
3375 13:38:49.634276 [Byte1]: 38
3376 13:38:49.634328
3377 13:38:49.634379 Set Vref, RX VrefLevel [Byte0]: 39
3378 13:38:49.634431 [Byte1]: 39
3379 13:38:49.634483
3380 13:38:49.634534 Set Vref, RX VrefLevel [Byte0]: 40
3381 13:38:49.634586 [Byte1]: 40
3382 13:38:49.634638
3383 13:38:49.634689 Set Vref, RX VrefLevel [Byte0]: 41
3384 13:38:49.634741 [Byte1]: 41
3385 13:38:49.634793
3386 13:38:49.634844 Set Vref, RX VrefLevel [Byte0]: 42
3387 13:38:49.634897 [Byte1]: 42
3388 13:38:49.634948
3389 13:38:49.635000 Set Vref, RX VrefLevel [Byte0]: 43
3390 13:38:49.635052 [Byte1]: 43
3391 13:38:49.635103
3392 13:38:49.635155 Set Vref, RX VrefLevel [Byte0]: 44
3393 13:38:49.635206 [Byte1]: 44
3394 13:38:49.635258
3395 13:38:49.635309 Set Vref, RX VrefLevel [Byte0]: 45
3396 13:38:49.635361 [Byte1]: 45
3397 13:38:49.635412
3398 13:38:49.635464 Set Vref, RX VrefLevel [Byte0]: 46
3399 13:38:49.635515 [Byte1]: 46
3400 13:38:49.635567
3401 13:38:49.635618 Set Vref, RX VrefLevel [Byte0]: 47
3402 13:38:49.635670 [Byte1]: 47
3403 13:38:49.635723
3404 13:38:49.635775 Set Vref, RX VrefLevel [Byte0]: 48
3405 13:38:49.635827 [Byte1]: 48
3406 13:38:49.635879
3407 13:38:49.635931 Set Vref, RX VrefLevel [Byte0]: 49
3408 13:38:49.635983 [Byte1]: 49
3409 13:38:49.636035
3410 13:38:49.636090 Set Vref, RX VrefLevel [Byte0]: 50
3411 13:38:49.636168 [Byte1]: 50
3412 13:38:49.636222
3413 13:38:49.636275 Set Vref, RX VrefLevel [Byte0]: 51
3414 13:38:49.636327 [Byte1]: 51
3415 13:38:49.636380
3416 13:38:49.636431 Set Vref, RX VrefLevel [Byte0]: 52
3417 13:38:49.636483 [Byte1]: 52
3418 13:38:49.636535
3419 13:38:49.636587 Set Vref, RX VrefLevel [Byte0]: 53
3420 13:38:49.636639 [Byte1]: 53
3421 13:38:49.636691
3422 13:38:49.636744 Set Vref, RX VrefLevel [Byte0]: 54
3423 13:38:49.636796 [Byte1]: 54
3424 13:38:49.636848
3425 13:38:49.636899 Set Vref, RX VrefLevel [Byte0]: 55
3426 13:38:49.636951 [Byte1]: 55
3427 13:38:49.637032
3428 13:38:49.637085 Set Vref, RX VrefLevel [Byte0]: 56
3429 13:38:49.637136 [Byte1]: 56
3430 13:38:49.637188
3431 13:38:49.637239 Set Vref, RX VrefLevel [Byte0]: 57
3432 13:38:49.637292 [Byte1]: 57
3433 13:38:49.637385
3434 13:38:49.637437 Set Vref, RX VrefLevel [Byte0]: 58
3435 13:38:49.637489 [Byte1]: 58
3436 13:38:49.637542
3437 13:38:49.637594 Set Vref, RX VrefLevel [Byte0]: 59
3438 13:38:49.637646 [Byte1]: 59
3439 13:38:49.637698
3440 13:38:49.637750 Set Vref, RX VrefLevel [Byte0]: 60
3441 13:38:49.637802 [Byte1]: 60
3442 13:38:49.637855
3443 13:38:49.637907 Set Vref, RX VrefLevel [Byte0]: 61
3444 13:38:49.637959 [Byte1]: 61
3445 13:38:49.638012
3446 13:38:49.638064 Set Vref, RX VrefLevel [Byte0]: 62
3447 13:38:49.638117 [Byte1]: 62
3448 13:38:49.638168
3449 13:38:49.638220 Set Vref, RX VrefLevel [Byte0]: 63
3450 13:38:49.638273 [Byte1]: 63
3451 13:38:49.638325
3452 13:38:49.638376 Set Vref, RX VrefLevel [Byte0]: 64
3453 13:38:49.638428 [Byte1]: 64
3454 13:38:49.638480
3455 13:38:49.638531 Set Vref, RX VrefLevel [Byte0]: 65
3456 13:38:49.638583 [Byte1]: 65
3457 13:38:49.638635
3458 13:38:49.638687 Set Vref, RX VrefLevel [Byte0]: 66
3459 13:38:49.638740 [Byte1]: 66
3460 13:38:49.638791
3461 13:38:49.638843 Final RX Vref Byte 0 = 51 to rank0
3462 13:38:49.638895 Final RX Vref Byte 1 = 50 to rank0
3463 13:38:49.638948 Final RX Vref Byte 0 = 51 to rank1
3464 13:38:49.639000 Final RX Vref Byte 1 = 50 to rank1==
3465 13:38:49.639052 Dram Type= 6, Freq= 0, CH_1, rank 0
3466 13:38:49.639105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 13:38:49.639158 ==
3468 13:38:49.639210 DQS Delay:
3469 13:38:49.639262 DQS0 = 0, DQS1 = 0
3470 13:38:49.639314 DQM Delay:
3471 13:38:49.639366 DQM0 = 119, DQM1 = 111
3472 13:38:49.639418 DQ Delay:
3473 13:38:49.639470 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3474 13:38:49.639522 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3475 13:38:49.639574 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3476 13:38:49.639841 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3477 13:38:49.639971
3478 13:38:49.640027
3479 13:38:49.640081 [DQSOSCAuto] RK0, (LSB)MR18= 0x71b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 407 ps
3480 13:38:49.640136 CH1 RK0: MR19=404, MR18=71B
3481 13:38:49.640189 CH1_RK0: MR19=0x404, MR18=0x71B, DQSOSC=399, MR23=63, INC=41, DEC=27
3482 13:38:49.640243
3483 13:38:49.640296 ----->DramcWriteLeveling(PI) begin...
3484 13:38:49.640349 ==
3485 13:38:49.640402 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 13:38:49.640456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 13:38:49.640510 ==
3488 13:38:49.640562 Write leveling (Byte 0): 25 => 25
3489 13:38:49.640615 Write leveling (Byte 1): 32 => 32
3490 13:38:49.640667 DramcWriteLeveling(PI) end<-----
3491 13:38:49.640720
3492 13:38:49.640772 ==
3493 13:38:49.640825 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 13:38:49.640877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 13:38:49.640930 ==
3496 13:38:49.641021 [Gating] SW mode calibration
3497 13:38:49.641074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3498 13:38:49.641127 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3499 13:38:49.641180 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 13:38:49.641233 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 13:38:49.641286 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 13:38:49.641410 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 13:38:49.641494 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 13:38:49.641576 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 13:38:49.641659 0 15 24 | B1->B0 | 2727 3434 | 1 0 | (1 0) (0 1)
3506 13:38:49.641742 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3507 13:38:49.641824 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 13:38:49.641907 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 13:38:49.641989 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 13:38:49.642071 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 13:38:49.642154 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 13:38:49.642236 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3513 13:38:49.642318 1 0 24 | B1->B0 | 3f3f 3232 | 0 0 | (0 0) (1 1)
3514 13:38:49.642401 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
3515 13:38:49.642483 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 13:38:49.642565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 13:38:49.642648 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 13:38:49.642730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 13:38:49.642812 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 13:38:49.642910 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 13:38:49.643024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3522 13:38:49.643109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3523 13:38:49.643192 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 13:38:49.643275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 13:38:49.643357 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 13:38:49.643440 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 13:38:49.643522 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 13:38:49.643605 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 13:38:49.643687 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 13:38:49.643769 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 13:38:49.643852 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 13:38:49.643950 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 13:38:49.644047 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 13:38:49.644129 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 13:38:49.644212 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 13:38:49.644295 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 13:38:49.644377 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3538 13:38:49.644460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 13:38:49.644542 Total UI for P1: 0, mck2ui 16
3540 13:38:49.644625 best dqsien dly found for B0: ( 1, 3, 24)
3541 13:38:49.644707 Total UI for P1: 0, mck2ui 16
3542 13:38:49.644790 best dqsien dly found for B1: ( 1, 3, 24)
3543 13:38:49.644872 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3544 13:38:49.644955 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3545 13:38:49.645036
3546 13:38:49.645119 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 13:38:49.645201 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3548 13:38:49.645283 [Gating] SW calibration Done
3549 13:38:49.645386 ==
3550 13:38:49.645440 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 13:38:49.645494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 13:38:49.645548 ==
3553 13:38:49.645601 RX Vref Scan: 0
3554 13:38:49.645653
3555 13:38:49.645705 RX Vref 0 -> 0, step: 1
3556 13:38:49.645758
3557 13:38:49.645810 RX Delay -40 -> 252, step: 8
3558 13:38:49.645864 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3559 13:38:49.645917 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3560 13:38:49.645970 iDelay=200, Bit 2, Center 103 (40 ~ 167) 128
3561 13:38:49.646023 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3562 13:38:49.646075 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3563 13:38:49.646127 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3564 13:38:49.646179 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3565 13:38:49.646232 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3566 13:38:49.646284 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3567 13:38:49.646344 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3568 13:38:49.646455 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3569 13:38:49.646525 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3570 13:38:49.646578 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3571 13:38:49.646631 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3572 13:38:49.646685 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3573 13:38:49.646737 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3574 13:38:49.646790 ==
3575 13:38:49.646872 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 13:38:49.647131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 13:38:49.647193 ==
3578 13:38:49.647247 DQS Delay:
3579 13:38:49.647300 DQS0 = 0, DQS1 = 0
3580 13:38:49.647353 DQM Delay:
3581 13:38:49.647406 DQM0 = 118, DQM1 = 113
3582 13:38:49.647459 DQ Delay:
3583 13:38:49.647511 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3584 13:38:49.647564 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3585 13:38:49.647616 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3586 13:38:49.647669 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3587 13:38:49.647721
3588 13:38:49.647772
3589 13:38:49.647824 ==
3590 13:38:49.647877 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 13:38:49.647929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 13:38:49.647983 ==
3593 13:38:49.648035
3594 13:38:49.648087
3595 13:38:49.648139 TX Vref Scan disable
3596 13:38:49.648192 == TX Byte 0 ==
3597 13:38:49.648244 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3598 13:38:49.648299 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3599 13:38:49.648351 == TX Byte 1 ==
3600 13:38:49.648403 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3601 13:38:49.648456 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3602 13:38:49.648508 ==
3603 13:38:49.648561 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 13:38:49.648613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 13:38:49.648666 ==
3606 13:38:49.648719 TX Vref=22, minBit 1, minWin=25, winSum=416
3607 13:38:49.648772 TX Vref=24, minBit 1, minWin=25, winSum=421
3608 13:38:49.648824 TX Vref=26, minBit 0, minWin=26, winSum=426
3609 13:38:49.648876 TX Vref=28, minBit 3, minWin=26, winSum=431
3610 13:38:49.648929 TX Vref=30, minBit 1, minWin=26, winSum=429
3611 13:38:49.648981 TX Vref=32, minBit 7, minWin=26, winSum=428
3612 13:38:49.649034 [TxChooseVref] Worse bit 3, Min win 26, Win sum 431, Final Vref 28
3613 13:38:49.649087
3614 13:38:49.649139 Final TX Range 1 Vref 28
3615 13:38:49.649191
3616 13:38:49.649243 ==
3617 13:38:49.649319 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 13:38:49.649391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 13:38:49.649444 ==
3620 13:38:49.649496
3621 13:38:49.649548
3622 13:38:49.649600 TX Vref Scan disable
3623 13:38:49.649659 == TX Byte 0 ==
3624 13:38:49.649754 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3625 13:38:49.649839 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3626 13:38:49.649921 == TX Byte 1 ==
3627 13:38:49.650004 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3628 13:38:49.650086 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3629 13:38:49.650167
3630 13:38:49.650248 [DATLAT]
3631 13:38:49.650329 Freq=1200, CH1 RK1
3632 13:38:49.650411
3633 13:38:49.650509 DATLAT Default: 0xd
3634 13:38:49.650641 0, 0xFFFF, sum = 0
3635 13:38:49.650741 1, 0xFFFF, sum = 0
3636 13:38:49.650829 2, 0xFFFF, sum = 0
3637 13:38:49.650913 3, 0xFFFF, sum = 0
3638 13:38:49.650997 4, 0xFFFF, sum = 0
3639 13:38:49.651096 5, 0xFFFF, sum = 0
3640 13:38:49.651211 6, 0xFFFF, sum = 0
3641 13:38:49.651319 7, 0xFFFF, sum = 0
3642 13:38:49.651394 8, 0xFFFF, sum = 0
3643 13:38:49.651451 9, 0xFFFF, sum = 0
3644 13:38:49.651505 10, 0xFFFF, sum = 0
3645 13:38:49.651558 11, 0xFFFF, sum = 0
3646 13:38:49.651612 12, 0x0, sum = 1
3647 13:38:49.651666 13, 0x0, sum = 2
3648 13:38:49.651718 14, 0x0, sum = 3
3649 13:38:49.651772 15, 0x0, sum = 4
3650 13:38:49.651825 best_step = 13
3651 13:38:49.651907
3652 13:38:49.651958 ==
3653 13:38:49.652011 Dram Type= 6, Freq= 0, CH_1, rank 1
3654 13:38:49.652064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3655 13:38:49.652117 ==
3656 13:38:49.652170 RX Vref Scan: 0
3657 13:38:49.652223
3658 13:38:49.652275 RX Vref 0 -> 0, step: 1
3659 13:38:49.652327
3660 13:38:49.652380 RX Delay -13 -> 252, step: 4
3661 13:38:49.652432 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3662 13:38:49.652485 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3663 13:38:49.652537 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3664 13:38:49.652589 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3665 13:38:49.652641 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3666 13:38:49.652694 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3667 13:38:49.652746 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3668 13:38:49.652799 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3669 13:38:49.652852 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3670 13:38:49.652904 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3671 13:38:49.653012 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3672 13:38:49.653128 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3673 13:38:49.653213 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3674 13:38:49.653304 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3675 13:38:49.653375 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3676 13:38:49.653429 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3677 13:38:49.653481 ==
3678 13:38:49.653534 Dram Type= 6, Freq= 0, CH_1, rank 1
3679 13:38:49.653587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3680 13:38:49.653641 ==
3681 13:38:49.653693 DQS Delay:
3682 13:38:49.653745 DQS0 = 0, DQS1 = 0
3683 13:38:49.653825 DQM Delay:
3684 13:38:49.653877 DQM0 = 119, DQM1 = 112
3685 13:38:49.653929 DQ Delay:
3686 13:38:49.653981 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3687 13:38:49.654033 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3688 13:38:49.654086 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3689 13:38:49.654138 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3690 13:38:49.654190
3691 13:38:49.654242
3692 13:38:49.654295 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3693 13:38:49.654349 CH1 RK1: MR19=403, MR18=9EE
3694 13:38:49.654401 CH1_RK1: MR19=0x403, MR18=0x9EE, DQSOSC=406, MR23=63, INC=39, DEC=26
3695 13:38:49.654454 [RxdqsGatingPostProcess] freq 1200
3696 13:38:49.654506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3697 13:38:49.654559 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 13:38:49.654611 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 13:38:49.654664 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 13:38:49.654717 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 13:38:49.654769 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 13:38:49.654821 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 13:38:49.654873 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 13:38:49.654925 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 13:38:49.654977 Pre-setting of DQS Precalculation
3706 13:38:49.655029 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3707 13:38:49.655082 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3708 13:38:49.655136 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3709 13:38:49.655189
3710 13:38:49.655241
3711 13:38:49.655292 [Calibration Summary] 2400 Mbps
3712 13:38:49.655345 CH 0, Rank 0
3713 13:38:49.655397 SW Impedance : PASS
3714 13:38:49.655450 DUTY Scan : NO K
3715 13:38:49.655502 ZQ Calibration : PASS
3716 13:38:49.655555 Jitter Meter : NO K
3717 13:38:49.655608 CBT Training : PASS
3718 13:38:49.655873 Write leveling : PASS
3719 13:38:49.655936 RX DQS gating : PASS
3720 13:38:49.655990 RX DQ/DQS(RDDQC) : PASS
3721 13:38:49.656043 TX DQ/DQS : PASS
3722 13:38:49.656096 RX DATLAT : PASS
3723 13:38:49.656149 RX DQ/DQS(Engine): PASS
3724 13:38:49.656240 TX OE : NO K
3725 13:38:49.656332 All Pass.
3726 13:38:49.656438
3727 13:38:49.656491 CH 0, Rank 1
3728 13:38:49.656543 SW Impedance : PASS
3729 13:38:49.656595 DUTY Scan : NO K
3730 13:38:49.656648 ZQ Calibration : PASS
3731 13:38:49.656701 Jitter Meter : NO K
3732 13:38:49.656753 CBT Training : PASS
3733 13:38:49.656806 Write leveling : PASS
3734 13:38:49.656858 RX DQS gating : PASS
3735 13:38:49.656910 RX DQ/DQS(RDDQC) : PASS
3736 13:38:49.656963 TX DQ/DQS : PASS
3737 13:38:49.657016 RX DATLAT : PASS
3738 13:38:49.657084 RX DQ/DQS(Engine): PASS
3739 13:38:49.657152 TX OE : NO K
3740 13:38:49.657204 All Pass.
3741 13:38:49.657257
3742 13:38:49.657339 CH 1, Rank 0
3743 13:38:49.657407 SW Impedance : PASS
3744 13:38:49.657459 DUTY Scan : NO K
3745 13:38:49.657511 ZQ Calibration : PASS
3746 13:38:49.657563 Jitter Meter : NO K
3747 13:38:49.657615 CBT Training : PASS
3748 13:38:49.657667 Write leveling : PASS
3749 13:38:49.657719 RX DQS gating : PASS
3750 13:38:49.657771 RX DQ/DQS(RDDQC) : PASS
3751 13:38:49.657823 TX DQ/DQS : PASS
3752 13:38:49.657875 RX DATLAT : PASS
3753 13:38:49.657927 RX DQ/DQS(Engine): PASS
3754 13:38:49.657978 TX OE : NO K
3755 13:38:49.658030 All Pass.
3756 13:38:49.658082
3757 13:38:49.658134 CH 1, Rank 1
3758 13:38:49.658185 SW Impedance : PASS
3759 13:38:49.658237 DUTY Scan : NO K
3760 13:38:49.658289 ZQ Calibration : PASS
3761 13:38:49.658341 Jitter Meter : NO K
3762 13:38:49.658392 CBT Training : PASS
3763 13:38:49.658446 Write leveling : PASS
3764 13:38:49.658498 RX DQS gating : PASS
3765 13:38:49.658550 RX DQ/DQS(RDDQC) : PASS
3766 13:38:49.658602 TX DQ/DQS : PASS
3767 13:38:49.658655 RX DATLAT : PASS
3768 13:38:49.658706 RX DQ/DQS(Engine): PASS
3769 13:38:49.658758 TX OE : NO K
3770 13:38:49.658809 All Pass.
3771 13:38:49.658861
3772 13:38:49.658913 DramC Write-DBI off
3773 13:38:49.658965 PER_BANK_REFRESH: Hybrid Mode
3774 13:38:49.659017 TX_TRACKING: ON
3775 13:38:49.659069 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3776 13:38:49.659123 [FAST_K] Save calibration result to emmc
3777 13:38:49.659177 dramc_set_vcore_voltage set vcore to 650000
3778 13:38:49.659229 Read voltage for 600, 5
3779 13:38:49.659281 Vio18 = 0
3780 13:38:49.659335 Vcore = 650000
3781 13:38:49.659436 Vdram = 0
3782 13:38:49.659495 Vddq = 0
3783 13:38:49.659583 Vmddr = 0
3784 13:38:49.659636 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3785 13:38:49.659689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3786 13:38:49.659743 MEM_TYPE=3, freq_sel=19
3787 13:38:49.659795 sv_algorithm_assistance_LP4_1600
3788 13:38:49.659848 ============ PULL DRAM RESETB DOWN ============
3789 13:38:49.659902 ========== PULL DRAM RESETB DOWN end =========
3790 13:38:49.659955 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3791 13:38:49.660008 ===================================
3792 13:38:49.660061 LPDDR4 DRAM CONFIGURATION
3793 13:38:49.660114 ===================================
3794 13:38:49.660212 EX_ROW_EN[0] = 0x0
3795 13:38:49.660279 EX_ROW_EN[1] = 0x0
3796 13:38:49.660332 LP4Y_EN = 0x0
3797 13:38:49.660384 WORK_FSP = 0x0
3798 13:38:49.660436 WL = 0x2
3799 13:38:49.660488 RL = 0x2
3800 13:38:49.660540 BL = 0x2
3801 13:38:49.660593 RPST = 0x0
3802 13:38:49.660645 RD_PRE = 0x0
3803 13:38:49.660697 WR_PRE = 0x1
3804 13:38:49.660750 WR_PST = 0x0
3805 13:38:49.660802 DBI_WR = 0x0
3806 13:38:49.660855 DBI_RD = 0x0
3807 13:38:49.660907 OTF = 0x1
3808 13:38:49.660960 ===================================
3809 13:38:49.661012 ===================================
3810 13:38:49.661065 ANA top config
3811 13:38:49.661117 ===================================
3812 13:38:49.661169 DLL_ASYNC_EN = 0
3813 13:38:49.661221 ALL_SLAVE_EN = 1
3814 13:38:49.661273 NEW_RANK_MODE = 1
3815 13:38:49.661370 DLL_IDLE_MODE = 1
3816 13:38:49.661424 LP45_APHY_COMB_EN = 1
3817 13:38:49.661476 TX_ODT_DIS = 1
3818 13:38:49.661529 NEW_8X_MODE = 1
3819 13:38:49.661582 ===================================
3820 13:38:49.661635 ===================================
3821 13:38:49.661688 data_rate = 1200
3822 13:38:49.661741 CKR = 1
3823 13:38:49.661793 DQ_P2S_RATIO = 8
3824 13:38:49.661845 ===================================
3825 13:38:49.661898 CA_P2S_RATIO = 8
3826 13:38:49.661950 DQ_CA_OPEN = 0
3827 13:38:49.662003 DQ_SEMI_OPEN = 0
3828 13:38:49.662055 CA_SEMI_OPEN = 0
3829 13:38:49.662108 CA_FULL_RATE = 0
3830 13:38:49.662160 DQ_CKDIV4_EN = 1
3831 13:38:49.662212 CA_CKDIV4_EN = 1
3832 13:38:49.662265 CA_PREDIV_EN = 0
3833 13:38:49.662317 PH8_DLY = 0
3834 13:38:49.662369 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3835 13:38:49.662421 DQ_AAMCK_DIV = 4
3836 13:38:49.662473 CA_AAMCK_DIV = 4
3837 13:38:49.662526 CA_ADMCK_DIV = 4
3838 13:38:49.662578 DQ_TRACK_CA_EN = 0
3839 13:38:49.662651 CA_PICK = 600
3840 13:38:49.662760 CA_MCKIO = 600
3841 13:38:49.662815 MCKIO_SEMI = 0
3842 13:38:49.662868 PLL_FREQ = 2288
3843 13:38:49.662921 DQ_UI_PI_RATIO = 32
3844 13:38:49.663012 CA_UI_PI_RATIO = 0
3845 13:38:49.663066 ===================================
3846 13:38:49.663120 ===================================
3847 13:38:49.663173 memory_type:LPDDR4
3848 13:38:49.663225 GP_NUM : 10
3849 13:38:49.663278 SRAM_EN : 1
3850 13:38:49.663347 MD32_EN : 0
3851 13:38:49.663413 ===================================
3852 13:38:49.663496 [ANA_INIT] >>>>>>>>>>>>>>
3853 13:38:49.663549 <<<<<< [CONFIGURE PHASE]: ANA_TX
3854 13:38:49.663603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3855 13:38:49.663656 ===================================
3856 13:38:49.663708 data_rate = 1200,PCW = 0X5800
3857 13:38:49.663761 ===================================
3858 13:38:49.663813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3859 13:38:49.663866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 13:38:49.663918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3861 13:38:49.663971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3862 13:38:49.664228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3863 13:38:49.664289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3864 13:38:49.664343 [ANA_INIT] flow start
3865 13:38:49.664396 [ANA_INIT] PLL >>>>>>>>
3866 13:38:49.664449 [ANA_INIT] PLL <<<<<<<<
3867 13:38:49.664501 [ANA_INIT] MIDPI >>>>>>>>
3868 13:38:49.664553 [ANA_INIT] MIDPI <<<<<<<<
3869 13:38:49.664605 [ANA_INIT] DLL >>>>>>>>
3870 13:38:49.664710 [ANA_INIT] flow end
3871 13:38:49.664832 ============ LP4 DIFF to SE enter ============
3872 13:38:49.664949 ============ LP4 DIFF to SE exit ============
3873 13:38:49.665056 [ANA_INIT] <<<<<<<<<<<<<
3874 13:38:49.665151 [Flow] Enable top DCM control >>>>>
3875 13:38:49.665257 [Flow] Enable top DCM control <<<<<
3876 13:38:49.665372 Enable DLL master slave shuffle
3877 13:38:49.665474 ==============================================================
3878 13:38:49.665579 Gating Mode config
3879 13:38:49.665686 ==============================================================
3880 13:38:49.665796 Config description:
3881 13:38:49.665899 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3882 13:38:49.666008 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3883 13:38:49.666118 SELPH_MODE 0: By rank 1: By Phase
3884 13:38:49.666224 ==============================================================
3885 13:38:49.666328 GAT_TRACK_EN = 1
3886 13:38:49.666433 RX_GATING_MODE = 2
3887 13:38:49.666534 RX_GATING_TRACK_MODE = 2
3888 13:38:49.666637 SELPH_MODE = 1
3889 13:38:49.666730 PICG_EARLY_EN = 1
3890 13:38:49.666821 VALID_LAT_VALUE = 1
3891 13:38:49.666909 ==============================================================
3892 13:38:49.666995 Enter into Gating configuration >>>>
3893 13:38:49.667082 Exit from Gating configuration <<<<
3894 13:38:49.667167 Enter into DVFS_PRE_config >>>>>
3895 13:38:49.667254 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3896 13:38:49.667340 Exit from DVFS_PRE_config <<<<<
3897 13:38:49.667425 Enter into PICG configuration >>>>
3898 13:38:49.667509 Exit from PICG configuration <<<<
3899 13:38:49.667594 [RX_INPUT] configuration >>>>>
3900 13:38:49.667678 [RX_INPUT] configuration <<<<<
3901 13:38:49.667763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3902 13:38:49.667848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3903 13:38:49.667933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 13:38:49.668018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 13:38:49.668106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 13:38:49.668218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 13:38:49.670390 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3908 13:38:49.673942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3909 13:38:49.677080 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3910 13:38:49.683748 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3911 13:38:49.686960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3912 13:38:49.690014 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 13:38:49.693424 ===================================
3914 13:38:49.696778 LPDDR4 DRAM CONFIGURATION
3915 13:38:49.700269 ===================================
3916 13:38:49.700449 EX_ROW_EN[0] = 0x0
3917 13:38:49.703572 EX_ROW_EN[1] = 0x0
3918 13:38:49.706878 LP4Y_EN = 0x0
3919 13:38:49.706990 WORK_FSP = 0x0
3920 13:38:49.710281 WL = 0x2
3921 13:38:49.710374 RL = 0x2
3922 13:38:49.713476 BL = 0x2
3923 13:38:49.713565 RPST = 0x0
3924 13:38:49.716954 RD_PRE = 0x0
3925 13:38:49.717041 WR_PRE = 0x1
3926 13:38:49.720248 WR_PST = 0x0
3927 13:38:49.720336 DBI_WR = 0x0
3928 13:38:49.723628 DBI_RD = 0x0
3929 13:38:49.723717 OTF = 0x1
3930 13:38:49.726883 ===================================
3931 13:38:49.730252 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3932 13:38:49.736578 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3933 13:38:49.739903 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 13:38:49.743566 ===================================
3935 13:38:49.746769 LPDDR4 DRAM CONFIGURATION
3936 13:38:49.750047 ===================================
3937 13:38:49.750198 EX_ROW_EN[0] = 0x10
3938 13:38:49.753417 EX_ROW_EN[1] = 0x0
3939 13:38:49.753552 LP4Y_EN = 0x0
3940 13:38:49.756745 WORK_FSP = 0x0
3941 13:38:49.759770 WL = 0x2
3942 13:38:49.759899 RL = 0x2
3943 13:38:49.763667 BL = 0x2
3944 13:38:49.763767 RPST = 0x0
3945 13:38:49.766442 RD_PRE = 0x0
3946 13:38:49.766529 WR_PRE = 0x1
3947 13:38:49.769980 WR_PST = 0x0
3948 13:38:49.770068 DBI_WR = 0x0
3949 13:38:49.773205 DBI_RD = 0x0
3950 13:38:49.773291 OTF = 0x1
3951 13:38:49.776552 ===================================
3952 13:38:49.783221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3953 13:38:49.786997 nWR fixed to 30
3954 13:38:49.790355 [ModeRegInit_LP4] CH0 RK0
3955 13:38:49.790462 [ModeRegInit_LP4] CH0 RK1
3956 13:38:49.793968 [ModeRegInit_LP4] CH1 RK0
3957 13:38:49.797312 [ModeRegInit_LP4] CH1 RK1
3958 13:38:49.797412 match AC timing 17
3959 13:38:49.803763 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3960 13:38:49.807038 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3961 13:38:49.810735 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3962 13:38:49.817323 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3963 13:38:49.820720 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3964 13:38:49.820825 ==
3965 13:38:49.824093 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 13:38:49.827033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 13:38:49.827137 ==
3968 13:38:49.833824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3969 13:38:49.840667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3970 13:38:49.844006 [CA 0] Center 36 (6~67) winsize 62
3971 13:38:49.847219 [CA 1] Center 36 (6~67) winsize 62
3972 13:38:49.850464 [CA 2] Center 34 (4~65) winsize 62
3973 13:38:49.853924 [CA 3] Center 34 (3~65) winsize 63
3974 13:38:49.857325 [CA 4] Center 34 (3~65) winsize 63
3975 13:38:49.860616 [CA 5] Center 33 (2~64) winsize 63
3976 13:38:49.860783
3977 13:38:49.863758 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3978 13:38:49.863843
3979 13:38:49.867049 [CATrainingPosCal] consider 1 rank data
3980 13:38:49.870399 u2DelayCellTimex100 = 270/100 ps
3981 13:38:49.873684 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3982 13:38:49.876986 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3983 13:38:49.880357 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3984 13:38:49.883692 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3985 13:38:49.887158 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3986 13:38:49.890521 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3987 13:38:49.893464
3988 13:38:49.896645 CA PerBit enable=1, Macro0, CA PI delay=33
3989 13:38:49.896729
3990 13:38:49.900099 [CBTSetCACLKResult] CA Dly = 33
3991 13:38:49.900186 CS Dly: 4 (0~35)
3992 13:38:49.900259 ==
3993 13:38:49.903487 Dram Type= 6, Freq= 0, CH_0, rank 1
3994 13:38:49.906741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 13:38:49.906828 ==
3996 13:38:49.913563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3997 13:38:49.920066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3998 13:38:49.923167 [CA 0] Center 36 (6~67) winsize 62
3999 13:38:49.926538 [CA 1] Center 36 (6~67) winsize 62
4000 13:38:49.929894 [CA 2] Center 35 (4~66) winsize 63
4001 13:38:49.933226 [CA 3] Center 34 (4~65) winsize 62
4002 13:38:49.936605 [CA 4] Center 34 (3~65) winsize 63
4003 13:38:49.939989 [CA 5] Center 33 (3~64) winsize 62
4004 13:38:49.940077
4005 13:38:49.943397 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4006 13:38:49.943507
4007 13:38:49.946784 [CATrainingPosCal] consider 2 rank data
4008 13:38:49.950235 u2DelayCellTimex100 = 270/100 ps
4009 13:38:49.953061 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4010 13:38:49.956406 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4011 13:38:49.959733 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4012 13:38:49.963241 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4013 13:38:49.966808 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4014 13:38:49.973185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4015 13:38:49.973309
4016 13:38:49.976666 CA PerBit enable=1, Macro0, CA PI delay=33
4017 13:38:49.976782
4018 13:38:49.979915 [CBTSetCACLKResult] CA Dly = 33
4019 13:38:49.980033 CS Dly: 5 (0~37)
4020 13:38:49.980128
4021 13:38:49.983593 ----->DramcWriteLeveling(PI) begin...
4022 13:38:49.983705 ==
4023 13:38:49.986929 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 13:38:49.989952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 13:38:49.993223 ==
4026 13:38:49.993343 Write leveling (Byte 0): 33 => 33
4027 13:38:49.996488 Write leveling (Byte 1): 30 => 30
4028 13:38:50.000027 DramcWriteLeveling(PI) end<-----
4029 13:38:50.000140
4030 13:38:50.000240 ==
4031 13:38:50.003376 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 13:38:50.010386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 13:38:50.010477 ==
4034 13:38:50.010545 [Gating] SW mode calibration
4035 13:38:50.019986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4036 13:38:50.023623 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4037 13:38:50.029876 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 13:38:50.033211 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 13:38:50.036677 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 13:38:50.040004 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
4041 13:38:50.046693 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
4042 13:38:50.049906 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 13:38:50.053215 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 13:38:50.059844 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 13:38:50.063391 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 13:38:50.066308 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 13:38:50.073101 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4048 13:38:50.076767 0 10 12 | B1->B0 | 2525 3a3a | 0 0 | (0 0) (1 1)
4049 13:38:50.079750 0 10 16 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
4050 13:38:50.086561 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 13:38:50.089892 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 13:38:50.093282 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 13:38:50.099935 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 13:38:50.103215 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 13:38:50.106475 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4056 13:38:50.113089 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4057 13:38:50.116695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 13:38:50.119579 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 13:38:50.126587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 13:38:50.129721 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 13:38:50.133165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 13:38:50.139847 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 13:38:50.143167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 13:38:50.146539 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 13:38:50.153262 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 13:38:50.156587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 13:38:50.159958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 13:38:50.163121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 13:38:50.169660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 13:38:50.173017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 13:38:50.176125 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 13:38:50.183089 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4073 13:38:50.186439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 13:38:50.189667 Total UI for P1: 0, mck2ui 16
4075 13:38:50.192870 best dqsien dly found for B0: ( 0, 13, 10)
4076 13:38:50.196273 Total UI for P1: 0, mck2ui 16
4077 13:38:50.199659 best dqsien dly found for B1: ( 0, 13, 14)
4078 13:38:50.203086 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4079 13:38:50.206472 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4080 13:38:50.206557
4081 13:38:50.209661 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4082 13:38:50.212825 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4083 13:38:50.216189 [Gating] SW calibration Done
4084 13:38:50.216274 ==
4085 13:38:50.219581 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 13:38:50.226611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 13:38:50.226697 ==
4088 13:38:50.226765 RX Vref Scan: 0
4089 13:38:50.226869
4090 13:38:50.229494 RX Vref 0 -> 0, step: 1
4091 13:38:50.229579
4092 13:38:50.232726 RX Delay -230 -> 252, step: 16
4093 13:38:50.236252 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4094 13:38:50.239489 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4095 13:38:50.242886 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 13:38:50.249632 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4097 13:38:50.252553 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4098 13:38:50.256410 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4099 13:38:50.259766 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4100 13:38:50.262656 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4101 13:38:50.269359 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4102 13:38:50.272728 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4103 13:38:50.276062 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4104 13:38:50.279671 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4105 13:38:50.286408 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4106 13:38:50.289370 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4107 13:38:50.293039 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4108 13:38:50.296353 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4109 13:38:50.296440 ==
4110 13:38:50.299607 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 13:38:50.306235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 13:38:50.306320 ==
4113 13:38:50.306388 DQS Delay:
4114 13:38:50.309646 DQS0 = 0, DQS1 = 0
4115 13:38:50.309732 DQM Delay:
4116 13:38:50.309823 DQM0 = 50, DQM1 = 40
4117 13:38:50.312551 DQ Delay:
4118 13:38:50.316057 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4119 13:38:50.319502 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4120 13:38:50.322764 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4121 13:38:50.326048 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4122 13:38:50.326157
4123 13:38:50.326243
4124 13:38:50.326328 ==
4125 13:38:50.329274 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 13:38:50.332538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 13:38:50.332638 ==
4128 13:38:50.332742
4129 13:38:50.332846
4130 13:38:50.335783 TX Vref Scan disable
4131 13:38:50.339559 == TX Byte 0 ==
4132 13:38:50.342443 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4133 13:38:50.345769 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4134 13:38:50.349094 == TX Byte 1 ==
4135 13:38:50.352429 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4136 13:38:50.355825 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4137 13:38:50.355933 ==
4138 13:38:50.359245 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 13:38:50.362742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 13:38:50.362823 ==
4141 13:38:50.365657
4142 13:38:50.365736
4143 13:38:50.365822 TX Vref Scan disable
4144 13:38:50.369433 == TX Byte 0 ==
4145 13:38:50.373143 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 13:38:50.379357 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 13:38:50.379465 == TX Byte 1 ==
4148 13:38:50.382716 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4149 13:38:50.389632 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4150 13:38:50.389715
4151 13:38:50.389799 [DATLAT]
4152 13:38:50.389877 Freq=600, CH0 RK0
4153 13:38:50.389955
4154 13:38:50.392896 DATLAT Default: 0x9
4155 13:38:50.392997 0, 0xFFFF, sum = 0
4156 13:38:50.396120 1, 0xFFFF, sum = 0
4157 13:38:50.396225 2, 0xFFFF, sum = 0
4158 13:38:50.399562 3, 0xFFFF, sum = 0
4159 13:38:50.399645 4, 0xFFFF, sum = 0
4160 13:38:50.402926 5, 0xFFFF, sum = 0
4161 13:38:50.406323 6, 0xFFFF, sum = 0
4162 13:38:50.406427 7, 0xFFFF, sum = 0
4163 13:38:50.406532 8, 0x0, sum = 1
4164 13:38:50.409752 9, 0x0, sum = 2
4165 13:38:50.409829 10, 0x0, sum = 3
4166 13:38:50.412885 11, 0x0, sum = 4
4167 13:38:50.412960 best_step = 9
4168 13:38:50.413038
4169 13:38:50.413114 ==
4170 13:38:50.416058 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 13:38:50.422901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 13:38:50.423012 ==
4173 13:38:50.423115 RX Vref Scan: 1
4174 13:38:50.423216
4175 13:38:50.426164 RX Vref 0 -> 0, step: 1
4176 13:38:50.426264
4177 13:38:50.429480 RX Delay -179 -> 252, step: 8
4178 13:38:50.429593
4179 13:38:50.432782 Set Vref, RX VrefLevel [Byte0]: 58
4180 13:38:50.435952 [Byte1]: 50
4181 13:38:50.436059
4182 13:38:50.439672 Final RX Vref Byte 0 = 58 to rank0
4183 13:38:50.442852 Final RX Vref Byte 1 = 50 to rank0
4184 13:38:50.446200 Final RX Vref Byte 0 = 58 to rank1
4185 13:38:50.449623 Final RX Vref Byte 1 = 50 to rank1==
4186 13:38:50.452977 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 13:38:50.456274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 13:38:50.456385 ==
4189 13:38:50.459289 DQS Delay:
4190 13:38:50.459392 DQS0 = 0, DQS1 = 0
4191 13:38:50.459497 DQM Delay:
4192 13:38:50.462778 DQM0 = 49, DQM1 = 37
4193 13:38:50.462883 DQ Delay:
4194 13:38:50.466089 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4195 13:38:50.469464 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4196 13:38:50.472763 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4197 13:38:50.475999 DQ12 =44, DQ13 =36, DQ14 =48, DQ15 =48
4198 13:38:50.476107
4199 13:38:50.476207
4200 13:38:50.486029 [DQSOSCAuto] RK0, (LSB)MR18= 0x645e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4201 13:38:50.486122 CH0 RK0: MR19=808, MR18=645E
4202 13:38:50.492477 CH0_RK0: MR19=0x808, MR18=0x645E, DQSOSC=391, MR23=63, INC=171, DEC=114
4203 13:38:50.492564
4204 13:38:50.496066 ----->DramcWriteLeveling(PI) begin...
4205 13:38:50.499338 ==
4206 13:38:50.502898 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 13:38:50.505898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 13:38:50.505984 ==
4209 13:38:50.509243 Write leveling (Byte 0): 35 => 35
4210 13:38:50.512695 Write leveling (Byte 1): 31 => 31
4211 13:38:50.516006 DramcWriteLeveling(PI) end<-----
4212 13:38:50.516093
4213 13:38:50.516159 ==
4214 13:38:50.519237 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 13:38:50.522603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 13:38:50.522693 ==
4217 13:38:50.525872 [Gating] SW mode calibration
4218 13:38:50.532585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4219 13:38:50.535861 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4220 13:38:50.542794 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 13:38:50.545852 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 13:38:50.549555 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 13:38:50.555855 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 0)
4224 13:38:50.559057 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4225 13:38:50.562431 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 13:38:50.569258 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 13:38:50.572522 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 13:38:50.575854 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 13:38:50.582680 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 13:38:50.586027 0 10 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
4231 13:38:50.589320 0 10 12 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 0)
4232 13:38:50.595876 0 10 16 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
4233 13:38:50.599482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 13:38:50.602785 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 13:38:50.609669 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 13:38:50.612556 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 13:38:50.616015 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 13:38:50.619266 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 13:38:50.626368 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 13:38:50.629661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4241 13:38:50.633037 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 13:38:50.639526 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 13:38:50.642937 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 13:38:50.646074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 13:38:50.652682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 13:38:50.656054 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 13:38:50.659454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 13:38:50.666285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 13:38:50.669690 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 13:38:50.672520 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 13:38:50.679320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 13:38:50.682499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 13:38:50.685760 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 13:38:50.692434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 13:38:50.695649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4256 13:38:50.699069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 13:38:50.702468 Total UI for P1: 0, mck2ui 16
4258 13:38:50.705923 best dqsien dly found for B0: ( 0, 13, 12)
4259 13:38:50.709085 Total UI for P1: 0, mck2ui 16
4260 13:38:50.712377 best dqsien dly found for B1: ( 0, 13, 12)
4261 13:38:50.715558 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 13:38:50.718936 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4263 13:38:50.719037
4264 13:38:50.722701 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 13:38:50.729105 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4266 13:38:50.729213 [Gating] SW calibration Done
4267 13:38:50.732333 ==
4268 13:38:50.732429 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 13:38:50.738948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 13:38:50.739056 ==
4271 13:38:50.739149 RX Vref Scan: 0
4272 13:38:50.739241
4273 13:38:50.742585 RX Vref 0 -> 0, step: 1
4274 13:38:50.742684
4275 13:38:50.745951 RX Delay -230 -> 252, step: 16
4276 13:38:50.749190 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4277 13:38:50.752444 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4278 13:38:50.759143 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4279 13:38:50.762530 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4280 13:38:50.765898 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4281 13:38:50.769080 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4282 13:38:50.772494 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 13:38:50.778950 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4284 13:38:50.782339 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4285 13:38:50.785470 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4286 13:38:50.788726 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4287 13:38:50.795284 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4288 13:38:50.799030 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4289 13:38:50.801943 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4290 13:38:50.805561 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4291 13:38:50.812368 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4292 13:38:50.812472 ==
4293 13:38:50.815479 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 13:38:50.818702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 13:38:50.818781 ==
4296 13:38:50.818844 DQS Delay:
4297 13:38:50.821965 DQS0 = 0, DQS1 = 0
4298 13:38:50.822038 DQM Delay:
4299 13:38:50.825235 DQM0 = 48, DQM1 = 40
4300 13:38:50.825390 DQ Delay:
4301 13:38:50.828666 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =49
4302 13:38:50.832154 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4303 13:38:50.835631 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4304 13:38:50.838984 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4305 13:38:50.839085
4306 13:38:50.839175
4307 13:38:50.839266 ==
4308 13:38:50.841867 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 13:38:50.845565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 13:38:50.845645 ==
4311 13:38:50.845724
4312 13:38:50.848748
4313 13:38:50.848850 TX Vref Scan disable
4314 13:38:50.851877 == TX Byte 0 ==
4315 13:38:50.855254 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4316 13:38:50.858495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4317 13:38:50.861871 == TX Byte 1 ==
4318 13:38:50.865180 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4319 13:38:50.868617 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4320 13:38:50.868721 ==
4321 13:38:50.871961 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 13:38:50.878853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 13:38:50.878956 ==
4324 13:38:50.879049
4325 13:38:50.879137
4326 13:38:50.879223 TX Vref Scan disable
4327 13:38:50.883177 == TX Byte 0 ==
4328 13:38:50.886563 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4329 13:38:50.889841 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4330 13:38:50.893017 == TX Byte 1 ==
4331 13:38:50.896375 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4332 13:38:50.900113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4333 13:38:50.903427
4334 13:38:50.903525 [DATLAT]
4335 13:38:50.903616 Freq=600, CH0 RK1
4336 13:38:50.903709
4337 13:38:50.906789 DATLAT Default: 0x9
4338 13:38:50.906887 0, 0xFFFF, sum = 0
4339 13:38:50.910034 1, 0xFFFF, sum = 0
4340 13:38:50.910109 2, 0xFFFF, sum = 0
4341 13:38:50.913204 3, 0xFFFF, sum = 0
4342 13:38:50.913351 4, 0xFFFF, sum = 0
4343 13:38:50.916657 5, 0xFFFF, sum = 0
4344 13:38:50.919830 6, 0xFFFF, sum = 0
4345 13:38:50.919931 7, 0xFFFF, sum = 0
4346 13:38:50.920030 8, 0x0, sum = 1
4347 13:38:50.923141 9, 0x0, sum = 2
4348 13:38:50.923271 10, 0x0, sum = 3
4349 13:38:50.926556 11, 0x0, sum = 4
4350 13:38:50.926636 best_step = 9
4351 13:38:50.926708
4352 13:38:50.926797 ==
4353 13:38:50.929915 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 13:38:50.936579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 13:38:50.936657 ==
4356 13:38:50.936752 RX Vref Scan: 0
4357 13:38:50.936841
4358 13:38:50.939736 RX Vref 0 -> 0, step: 1
4359 13:38:50.939835
4360 13:38:50.942941 RX Delay -179 -> 252, step: 8
4361 13:38:50.946305 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4362 13:38:50.949581 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4363 13:38:50.956252 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4364 13:38:50.959544 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4365 13:38:50.963160 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4366 13:38:50.966515 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4367 13:38:50.969920 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4368 13:38:50.976175 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4369 13:38:50.979764 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4370 13:38:50.982970 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4371 13:38:50.986366 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4372 13:38:50.993092 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4373 13:38:50.996138 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4374 13:38:50.999899 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4375 13:38:51.002810 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4376 13:38:51.009477 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4377 13:38:51.009586 ==
4378 13:38:51.012798 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 13:38:51.016418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 13:38:51.016519 ==
4381 13:38:51.016608 DQS Delay:
4382 13:38:51.019785 DQS0 = 0, DQS1 = 0
4383 13:38:51.019882 DQM Delay:
4384 13:38:51.023047 DQM0 = 47, DQM1 = 40
4385 13:38:51.023148 DQ Delay:
4386 13:38:51.026322 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4387 13:38:51.029628 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4388 13:38:51.032586 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4389 13:38:51.035902 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =44
4390 13:38:51.036000
4391 13:38:51.036088
4392 13:38:51.042697 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4393 13:38:51.045980 CH0 RK1: MR19=808, MR18=6532
4394 13:38:51.052678 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4395 13:38:51.055871 [RxdqsGatingPostProcess] freq 600
4396 13:38:51.062807 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 13:38:51.062891 Pre-setting of DQS Precalculation
4398 13:38:51.069414 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 13:38:51.069497 ==
4400 13:38:51.072710 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 13:38:51.075902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 13:38:51.076023 ==
4403 13:38:51.082772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 13:38:51.089588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4405 13:38:51.092924 [CA 0] Center 35 (5~66) winsize 62
4406 13:38:51.096263 [CA 1] Center 35 (5~66) winsize 62
4407 13:38:51.099544 [CA 2] Center 34 (4~64) winsize 61
4408 13:38:51.102765 [CA 3] Center 33 (3~64) winsize 62
4409 13:38:51.105960 [CA 4] Center 33 (3~64) winsize 62
4410 13:38:51.109202 [CA 5] Center 33 (3~64) winsize 62
4411 13:38:51.109323
4412 13:38:51.112657 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4413 13:38:51.112758
4414 13:38:51.116003 [CATrainingPosCal] consider 1 rank data
4415 13:38:51.119126 u2DelayCellTimex100 = 270/100 ps
4416 13:38:51.122490 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4417 13:38:51.125893 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4418 13:38:51.129053 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4419 13:38:51.132689 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4420 13:38:51.135945 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 13:38:51.139329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 13:38:51.139408
4423 13:38:51.145743 CA PerBit enable=1, Macro0, CA PI delay=33
4424 13:38:51.145830
4425 13:38:51.145922 [CBTSetCACLKResult] CA Dly = 33
4426 13:38:51.148989 CS Dly: 4 (0~35)
4427 13:38:51.149112 ==
4428 13:38:51.152354 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 13:38:51.155714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 13:38:51.155823 ==
4431 13:38:51.162547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 13:38:51.169143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4433 13:38:51.172824 [CA 0] Center 36 (6~66) winsize 61
4434 13:38:51.176132 [CA 1] Center 36 (5~67) winsize 63
4435 13:38:51.179140 [CA 2] Center 34 (4~65) winsize 62
4436 13:38:51.182488 [CA 3] Center 34 (4~65) winsize 62
4437 13:38:51.185923 [CA 4] Center 34 (4~65) winsize 62
4438 13:38:51.189138 [CA 5] Center 34 (3~65) winsize 63
4439 13:38:51.189237
4440 13:38:51.192405 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4441 13:38:51.192505
4442 13:38:51.195928 [CATrainingPosCal] consider 2 rank data
4443 13:38:51.199103 u2DelayCellTimex100 = 270/100 ps
4444 13:38:51.202418 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 13:38:51.205646 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 13:38:51.209170 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4447 13:38:51.212488 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4448 13:38:51.215859 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4449 13:38:51.219142 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 13:38:51.219243
4451 13:38:51.225850 CA PerBit enable=1, Macro0, CA PI delay=33
4452 13:38:51.225927
4453 13:38:51.229266 [CBTSetCACLKResult] CA Dly = 33
4454 13:38:51.229370 CS Dly: 4 (0~36)
4455 13:38:51.229434
4456 13:38:51.232461 ----->DramcWriteLeveling(PI) begin...
4457 13:38:51.232536 ==
4458 13:38:51.235933 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 13:38:51.239238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 13:38:51.239341 ==
4461 13:38:51.242585 Write leveling (Byte 0): 30 => 30
4462 13:38:51.245874 Write leveling (Byte 1): 32 => 32
4463 13:38:51.249210 DramcWriteLeveling(PI) end<-----
4464 13:38:51.249346
4465 13:38:51.249440 ==
4466 13:38:51.252511 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 13:38:51.259365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 13:38:51.259484 ==
4469 13:38:51.259578 [Gating] SW mode calibration
4470 13:38:51.269289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 13:38:51.272523 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 13:38:51.275848 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 13:38:51.282370 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 13:38:51.285991 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4475 13:38:51.289163 0 9 12 | B1->B0 | 2c2c 2727 | 1 0 | (1 1) (1 0)
4476 13:38:51.295801 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 13:38:51.299110 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 13:38:51.302835 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 13:38:51.309529 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 13:38:51.312744 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 13:38:51.315961 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 13:38:51.322697 0 10 8 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
4483 13:38:51.326015 0 10 12 | B1->B0 | 3e3e 3d3d | 0 0 | (0 0) (0 0)
4484 13:38:51.329231 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 13:38:51.332633 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 13:38:51.345233 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 13:38:51.345391 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 13:38:51.346216 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 13:38:51.352491 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 13:38:51.355794 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4491 13:38:51.359598 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 13:38:51.366331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 13:38:51.369595 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 13:38:51.372923 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 13:38:51.379341 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 13:38:51.382709 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 13:38:51.386225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 13:38:51.393067 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 13:38:51.396462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 13:38:51.399874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 13:38:51.406332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 13:38:51.409571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 13:38:51.412961 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 13:38:51.416153 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 13:38:51.422847 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 13:38:51.426198 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 13:38:51.429964 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4508 13:38:51.433112 Total UI for P1: 0, mck2ui 16
4509 13:38:51.436450 best dqsien dly found for B1: ( 0, 13, 10)
4510 13:38:51.443033 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 13:38:51.446049 Total UI for P1: 0, mck2ui 16
4512 13:38:51.449373 best dqsien dly found for B0: ( 0, 13, 12)
4513 13:38:51.452810 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4514 13:38:51.455999 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4515 13:38:51.456423
4516 13:38:51.459272 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 13:38:51.462563 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4518 13:38:51.466209 [Gating] SW calibration Done
4519 13:38:51.466923 ==
4520 13:38:51.469448 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 13:38:51.472598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 13:38:51.473026 ==
4523 13:38:51.475963 RX Vref Scan: 0
4524 13:38:51.476386
4525 13:38:51.479326 RX Vref 0 -> 0, step: 1
4526 13:38:51.479754
4527 13:38:51.480091 RX Delay -230 -> 252, step: 16
4528 13:38:51.485867 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4529 13:38:51.489170 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4530 13:38:51.492617 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4531 13:38:51.495987 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4532 13:38:51.502511 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4533 13:38:51.505794 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4534 13:38:51.509451 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4535 13:38:51.512829 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4536 13:38:51.516247 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4537 13:38:51.522378 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4538 13:38:51.525708 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4539 13:38:51.528981 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4540 13:38:51.532130 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4541 13:38:51.539117 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4542 13:38:51.542465 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4543 13:38:51.545791 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4544 13:38:51.546258 ==
4545 13:38:51.548882 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 13:38:51.552069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 13:38:51.555562 ==
4548 13:38:51.555988 DQS Delay:
4549 13:38:51.556318 DQS0 = 0, DQS1 = 0
4550 13:38:51.558971 DQM Delay:
4551 13:38:51.559410 DQM0 = 49, DQM1 = 40
4552 13:38:51.562459 DQ Delay:
4553 13:38:51.562883 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4554 13:38:51.565684 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4555 13:38:51.568759 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4556 13:38:51.572107 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4557 13:38:51.575524
4558 13:38:51.575606
4559 13:38:51.575672 ==
4560 13:38:51.578620 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 13:38:51.582076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 13:38:51.582159 ==
4563 13:38:51.582226
4564 13:38:51.582287
4565 13:38:51.585453 TX Vref Scan disable
4566 13:38:51.585542 == TX Byte 0 ==
4567 13:38:51.591671 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 13:38:51.594918 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 13:38:51.595002 == TX Byte 1 ==
4570 13:38:51.602156 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4571 13:38:51.605006 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4572 13:38:51.605100 ==
4573 13:38:51.608681 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 13:38:51.612104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 13:38:51.612201 ==
4576 13:38:51.612277
4577 13:38:51.612346
4578 13:38:51.615494 TX Vref Scan disable
4579 13:38:51.618830 == TX Byte 0 ==
4580 13:38:51.621768 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4581 13:38:51.625245 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4582 13:38:51.628706 == TX Byte 1 ==
4583 13:38:51.632072 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4584 13:38:51.635364 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4585 13:38:51.635448
4586 13:38:51.638269 [DATLAT]
4587 13:38:51.638366 Freq=600, CH1 RK0
4588 13:38:51.638432
4589 13:38:51.641988 DATLAT Default: 0x9
4590 13:38:51.642071 0, 0xFFFF, sum = 0
4591 13:38:51.645043 1, 0xFFFF, sum = 0
4592 13:38:51.645128 2, 0xFFFF, sum = 0
4593 13:38:51.648381 3, 0xFFFF, sum = 0
4594 13:38:51.648466 4, 0xFFFF, sum = 0
4595 13:38:51.651709 5, 0xFFFF, sum = 0
4596 13:38:51.651794 6, 0xFFFF, sum = 0
4597 13:38:51.655425 7, 0xFFFF, sum = 0
4598 13:38:51.655510 8, 0x0, sum = 1
4599 13:38:51.658291 9, 0x0, sum = 2
4600 13:38:51.658382 10, 0x0, sum = 3
4601 13:38:51.661655 11, 0x0, sum = 4
4602 13:38:51.661745 best_step = 9
4603 13:38:51.661816
4604 13:38:51.661881 ==
4605 13:38:51.665009 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 13:38:51.668323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 13:38:51.671892 ==
4608 13:38:51.671975 RX Vref Scan: 1
4609 13:38:51.672041
4610 13:38:51.675034 RX Vref 0 -> 0, step: 1
4611 13:38:51.675118
4612 13:38:51.678431 RX Delay -179 -> 252, step: 8
4613 13:38:51.678519
4614 13:38:51.681637 Set Vref, RX VrefLevel [Byte0]: 51
4615 13:38:51.684959 [Byte1]: 50
4616 13:38:51.685045
4617 13:38:51.688388 Final RX Vref Byte 0 = 51 to rank0
4618 13:38:51.691577 Final RX Vref Byte 1 = 50 to rank0
4619 13:38:51.694862 Final RX Vref Byte 0 = 51 to rank1
4620 13:38:51.698727 Final RX Vref Byte 1 = 50 to rank1==
4621 13:38:51.701652 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 13:38:51.704989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 13:38:51.705062 ==
4624 13:38:51.705135 DQS Delay:
4625 13:38:51.708333 DQS0 = 0, DQS1 = 0
4626 13:38:51.708402 DQM Delay:
4627 13:38:51.711954 DQM0 = 48, DQM1 = 41
4628 13:38:51.712034 DQ Delay:
4629 13:38:51.715278 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4630 13:38:51.718702 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4631 13:38:51.721654 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4632 13:38:51.725506 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4633 13:38:51.725581
4634 13:38:51.725644
4635 13:38:51.735168 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4636 13:38:51.735251 CH1 RK0: MR19=808, MR18=4B72
4637 13:38:51.742075 CH1_RK0: MR19=0x808, MR18=0x4B72, DQSOSC=388, MR23=63, INC=174, DEC=116
4638 13:38:51.742160
4639 13:38:51.745075 ----->DramcWriteLeveling(PI) begin...
4640 13:38:51.745166 ==
4641 13:38:51.748633 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 13:38:51.755235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 13:38:51.755750 ==
4644 13:38:51.758977 Write leveling (Byte 0): 27 => 27
4645 13:38:51.759418 Write leveling (Byte 1): 29 => 29
4646 13:38:51.761888 DramcWriteLeveling(PI) end<-----
4647 13:38:51.762309
4648 13:38:51.765758 ==
4649 13:38:51.766184 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 13:38:51.771844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 13:38:51.772352 ==
4652 13:38:51.775541 [Gating] SW mode calibration
4653 13:38:51.781985 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 13:38:51.785138 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 13:38:51.792154 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 13:38:51.795557 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 13:38:51.798955 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
4658 13:38:51.805471 0 9 12 | B1->B0 | 2b2b 2f2f | 0 0 | (1 1) (1 1)
4659 13:38:51.808847 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4660 13:38:51.812172 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 13:38:51.815476 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 13:38:51.822009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 13:38:51.825558 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 13:38:51.828867 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 13:38:51.835336 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 13:38:51.839084 0 10 12 | B1->B0 | 3838 2e2e | 0 0 | (0 0) (0 0)
4667 13:38:51.842298 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4668 13:38:51.848898 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 13:38:51.852223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 13:38:51.855413 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 13:38:51.862285 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 13:38:51.865381 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 13:38:51.868744 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4674 13:38:51.875414 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 13:38:51.878969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 13:38:51.882112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 13:38:51.888797 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 13:38:51.891876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 13:38:51.895065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 13:38:51.901548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 13:38:51.904746 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 13:38:51.908067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 13:38:51.914723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 13:38:51.918077 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 13:38:51.921344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 13:38:51.927924 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 13:38:51.931776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 13:38:51.934685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 13:38:51.938009 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 13:38:51.945066 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4691 13:38:51.948406 Total UI for P1: 0, mck2ui 16
4692 13:38:51.951578 best dqsien dly found for B1: ( 0, 13, 10)
4693 13:38:51.954905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 13:38:51.958218 Total UI for P1: 0, mck2ui 16
4695 13:38:51.961283 best dqsien dly found for B0: ( 0, 13, 12)
4696 13:38:51.964647 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4697 13:38:51.967761 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 13:38:51.967859
4699 13:38:51.971469 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4700 13:38:51.978094 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 13:38:51.978181 [Gating] SW calibration Done
4702 13:38:51.978248 ==
4703 13:38:51.981483 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 13:38:51.987904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 13:38:51.987991 ==
4706 13:38:51.988058 RX Vref Scan: 0
4707 13:38:51.988120
4708 13:38:51.991397 RX Vref 0 -> 0, step: 1
4709 13:38:51.991481
4710 13:38:51.994621 RX Delay -230 -> 252, step: 16
4711 13:38:51.997878 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4712 13:38:52.001217 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4713 13:38:52.004394 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4714 13:38:52.011121 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4715 13:38:52.014471 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4716 13:38:52.017757 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4717 13:38:52.021087 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4718 13:38:52.024486 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4719 13:38:52.031103 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4720 13:38:52.034436 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4721 13:38:52.037875 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4722 13:38:52.041116 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4723 13:38:52.047892 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4724 13:38:52.051197 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4725 13:38:52.054541 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4726 13:38:52.057827 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4727 13:38:52.057924 ==
4728 13:38:52.061109 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 13:38:52.067936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 13:38:52.068057 ==
4731 13:38:52.068163 DQS Delay:
4732 13:38:52.071230 DQS0 = 0, DQS1 = 0
4733 13:38:52.071339 DQM Delay:
4734 13:38:52.071441 DQM0 = 52, DQM1 = 46
4735 13:38:52.074265 DQ Delay:
4736 13:38:52.077694 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4737 13:38:52.081284 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4738 13:38:52.084672 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4739 13:38:52.087524 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4740 13:38:52.087631
4741 13:38:52.087733
4742 13:38:52.087835 ==
4743 13:38:52.091104 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 13:38:52.094251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 13:38:52.094354 ==
4746 13:38:52.094455
4747 13:38:52.094555
4748 13:38:52.097575 TX Vref Scan disable
4749 13:38:52.100874 == TX Byte 0 ==
4750 13:38:52.104202 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4751 13:38:52.107470 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4752 13:38:52.110899 == TX Byte 1 ==
4753 13:38:52.114112 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4754 13:38:52.117484 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4755 13:38:52.117569 ==
4756 13:38:52.121090 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 13:38:52.124427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 13:38:52.124539 ==
4759 13:38:52.127306
4760 13:38:52.127412
4761 13:38:52.127513 TX Vref Scan disable
4762 13:38:52.131111 == TX Byte 0 ==
4763 13:38:52.134351 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4764 13:38:52.137677 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4765 13:38:52.141095 == TX Byte 1 ==
4766 13:38:52.144829 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4767 13:38:52.148094 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4768 13:38:52.151320
4769 13:38:52.151402 [DATLAT]
4770 13:38:52.151505 Freq=600, CH1 RK1
4771 13:38:52.151607
4772 13:38:52.154564 DATLAT Default: 0x9
4773 13:38:52.154642 0, 0xFFFF, sum = 0
4774 13:38:52.157830 1, 0xFFFF, sum = 0
4775 13:38:52.157939 2, 0xFFFF, sum = 0
4776 13:38:52.161282 3, 0xFFFF, sum = 0
4777 13:38:52.161411 4, 0xFFFF, sum = 0
4778 13:38:52.164740 5, 0xFFFF, sum = 0
4779 13:38:52.164845 6, 0xFFFF, sum = 0
4780 13:38:52.167941 7, 0xFFFF, sum = 0
4781 13:38:52.168049 8, 0x0, sum = 1
4782 13:38:52.171216 9, 0x0, sum = 2
4783 13:38:52.171296 10, 0x0, sum = 3
4784 13:38:52.174897 11, 0x0, sum = 4
4785 13:38:52.175024 best_step = 9
4786 13:38:52.175129
4787 13:38:52.175228 ==
4788 13:38:52.178067 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 13:38:52.184560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 13:38:52.184671 ==
4791 13:38:52.184774 RX Vref Scan: 0
4792 13:38:52.184877
4793 13:38:52.188344 RX Vref 0 -> 0, step: 1
4794 13:38:52.188449
4795 13:38:52.191191 RX Delay -163 -> 252, step: 8
4796 13:38:52.194859 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4797 13:38:52.198037 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4798 13:38:52.204701 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4799 13:38:52.208040 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4800 13:38:52.211283 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4801 13:38:52.214646 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4802 13:38:52.217881 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4803 13:38:52.224832 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4804 13:38:52.227894 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4805 13:38:52.231510 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4806 13:38:52.234753 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4807 13:38:52.238141 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4808 13:38:52.244861 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4809 13:38:52.248135 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4810 13:38:52.251435 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4811 13:38:52.254690 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4812 13:38:52.254796 ==
4813 13:38:52.257878 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 13:38:52.264798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 13:38:52.264946 ==
4816 13:38:52.265051 DQS Delay:
4817 13:38:52.268135 DQS0 = 0, DQS1 = 0
4818 13:38:52.268216 DQM Delay:
4819 13:38:52.268319 DQM0 = 48, DQM1 = 42
4820 13:38:52.271241 DQ Delay:
4821 13:38:52.274860 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4822 13:38:52.278257 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4823 13:38:52.281399 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4824 13:38:52.284422 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4825 13:38:52.284529
4826 13:38:52.284633
4827 13:38:52.291239 [DQSOSCAuto] RK1, (LSB)MR18= 0x6026, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4828 13:38:52.294697 CH1 RK1: MR19=808, MR18=6026
4829 13:38:52.301183 CH1_RK1: MR19=0x808, MR18=0x6026, DQSOSC=391, MR23=63, INC=171, DEC=114
4830 13:38:52.304608 [RxdqsGatingPostProcess] freq 600
4831 13:38:52.307799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 13:38:52.311117 Pre-setting of DQS Precalculation
4833 13:38:52.317803 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 13:38:52.324815 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 13:38:52.331562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 13:38:52.331679
4837 13:38:52.331783
4838 13:38:52.334911 [Calibration Summary] 1200 Mbps
4839 13:38:52.335003 CH 0, Rank 0
4840 13:38:52.338232 SW Impedance : PASS
4841 13:38:52.341158 DUTY Scan : NO K
4842 13:38:52.341262 ZQ Calibration : PASS
4843 13:38:52.344592 Jitter Meter : NO K
4844 13:38:52.347871 CBT Training : PASS
4845 13:38:52.347955 Write leveling : PASS
4846 13:38:52.351252 RX DQS gating : PASS
4847 13:38:52.351338 RX DQ/DQS(RDDQC) : PASS
4848 13:38:52.354716 TX DQ/DQS : PASS
4849 13:38:52.357871 RX DATLAT : PASS
4850 13:38:52.357959 RX DQ/DQS(Engine): PASS
4851 13:38:52.361077 TX OE : NO K
4852 13:38:52.361163 All Pass.
4853 13:38:52.361231
4854 13:38:52.364547 CH 0, Rank 1
4855 13:38:52.364633 SW Impedance : PASS
4856 13:38:52.367876 DUTY Scan : NO K
4857 13:38:52.371217 ZQ Calibration : PASS
4858 13:38:52.371302 Jitter Meter : NO K
4859 13:38:52.374455 CBT Training : PASS
4860 13:38:52.378018 Write leveling : PASS
4861 13:38:52.378103 RX DQS gating : PASS
4862 13:38:52.381307 RX DQ/DQS(RDDQC) : PASS
4863 13:38:52.384556 TX DQ/DQS : PASS
4864 13:38:52.384641 RX DATLAT : PASS
4865 13:38:52.387939 RX DQ/DQS(Engine): PASS
4866 13:38:52.391194 TX OE : NO K
4867 13:38:52.391280 All Pass.
4868 13:38:52.391347
4869 13:38:52.391410 CH 1, Rank 0
4870 13:38:52.394545 SW Impedance : PASS
4871 13:38:52.397815 DUTY Scan : NO K
4872 13:38:52.397899 ZQ Calibration : PASS
4873 13:38:52.401127 Jitter Meter : NO K
4874 13:38:52.404511 CBT Training : PASS
4875 13:38:52.404600 Write leveling : PASS
4876 13:38:52.407637 RX DQS gating : PASS
4877 13:38:52.407751 RX DQ/DQS(RDDQC) : PASS
4878 13:38:52.411000 TX DQ/DQS : PASS
4879 13:38:52.414263 RX DATLAT : PASS
4880 13:38:52.414351 RX DQ/DQS(Engine): PASS
4881 13:38:52.417637 TX OE : NO K
4882 13:38:52.417722 All Pass.
4883 13:38:52.417788
4884 13:38:52.420843 CH 1, Rank 1
4885 13:38:52.420928 SW Impedance : PASS
4886 13:38:52.424237 DUTY Scan : NO K
4887 13:38:52.427891 ZQ Calibration : PASS
4888 13:38:52.427983 Jitter Meter : NO K
4889 13:38:52.431215 CBT Training : PASS
4890 13:38:52.434487 Write leveling : PASS
4891 13:38:52.434572 RX DQS gating : PASS
4892 13:38:52.437829 RX DQ/DQS(RDDQC) : PASS
4893 13:38:52.440756 TX DQ/DQS : PASS
4894 13:38:52.440840 RX DATLAT : PASS
4895 13:38:52.444111 RX DQ/DQS(Engine): PASS
4896 13:38:52.447379 TX OE : NO K
4897 13:38:52.447463 All Pass.
4898 13:38:52.447528
4899 13:38:52.447590 DramC Write-DBI off
4900 13:38:52.450784 PER_BANK_REFRESH: Hybrid Mode
4901 13:38:52.454094 TX_TRACKING: ON
4902 13:38:52.461096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 13:38:52.464547 [FAST_K] Save calibration result to emmc
4904 13:38:52.470761 dramc_set_vcore_voltage set vcore to 662500
4905 13:38:52.470847 Read voltage for 933, 3
4906 13:38:52.470914 Vio18 = 0
4907 13:38:52.474197 Vcore = 662500
4908 13:38:52.474280 Vdram = 0
4909 13:38:52.474347 Vddq = 0
4910 13:38:52.477475 Vmddr = 0
4911 13:38:52.480974 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 13:38:52.487629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 13:38:52.487715 MEM_TYPE=3, freq_sel=17
4914 13:38:52.490843 sv_algorithm_assistance_LP4_1600
4915 13:38:52.497600 ============ PULL DRAM RESETB DOWN ============
4916 13:38:52.500934 ========== PULL DRAM RESETB DOWN end =========
4917 13:38:52.504242 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 13:38:52.507486 ===================================
4919 13:38:52.510656 LPDDR4 DRAM CONFIGURATION
4920 13:38:52.514367 ===================================
4921 13:38:52.517612 EX_ROW_EN[0] = 0x0
4922 13:38:52.517713 EX_ROW_EN[1] = 0x0
4923 13:38:52.522007 LP4Y_EN = 0x0
4924 13:38:52.522091 WORK_FSP = 0x0
4925 13:38:52.524226 WL = 0x3
4926 13:38:52.524311 RL = 0x3
4927 13:38:52.527575 BL = 0x2
4928 13:38:52.527660 RPST = 0x0
4929 13:38:52.530762 RD_PRE = 0x0
4930 13:38:52.530862 WR_PRE = 0x1
4931 13:38:52.534355 WR_PST = 0x0
4932 13:38:52.534440 DBI_WR = 0x0
4933 13:38:52.537728 DBI_RD = 0x0
4934 13:38:52.537819 OTF = 0x1
4935 13:38:52.540981 ===================================
4936 13:38:52.544355 ===================================
4937 13:38:52.547210 ANA top config
4938 13:38:52.550484 ===================================
4939 13:38:52.554285 DLL_ASYNC_EN = 0
4940 13:38:52.554392 ALL_SLAVE_EN = 1
4941 13:38:52.557521 NEW_RANK_MODE = 1
4942 13:38:52.560549 DLL_IDLE_MODE = 1
4943 13:38:52.564326 LP45_APHY_COMB_EN = 1
4944 13:38:52.564409 TX_ODT_DIS = 1
4945 13:38:52.567534 NEW_8X_MODE = 1
4946 13:38:52.570459 ===================================
4947 13:38:52.574030 ===================================
4948 13:38:52.577236 data_rate = 1866
4949 13:38:52.580542 CKR = 1
4950 13:38:52.584025 DQ_P2S_RATIO = 8
4951 13:38:52.587339 ===================================
4952 13:38:52.590596 CA_P2S_RATIO = 8
4953 13:38:52.590684 DQ_CA_OPEN = 0
4954 13:38:52.594231 DQ_SEMI_OPEN = 0
4955 13:38:52.597341 CA_SEMI_OPEN = 0
4956 13:38:52.600814 CA_FULL_RATE = 0
4957 13:38:52.604224 DQ_CKDIV4_EN = 1
4958 13:38:52.607159 CA_CKDIV4_EN = 1
4959 13:38:52.607255 CA_PREDIV_EN = 0
4960 13:38:52.610695 PH8_DLY = 0
4961 13:38:52.613901 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 13:38:52.617208 DQ_AAMCK_DIV = 4
4963 13:38:52.620896 CA_AAMCK_DIV = 4
4964 13:38:52.621016 CA_ADMCK_DIV = 4
4965 13:38:52.624181 DQ_TRACK_CA_EN = 0
4966 13:38:52.627641 CA_PICK = 933
4967 13:38:52.630501 CA_MCKIO = 933
4968 13:38:52.634050 MCKIO_SEMI = 0
4969 13:38:52.637233 PLL_FREQ = 3732
4970 13:38:52.640437 DQ_UI_PI_RATIO = 32
4971 13:38:52.643794 CA_UI_PI_RATIO = 0
4972 13:38:52.643884 ===================================
4973 13:38:52.647189 ===================================
4974 13:38:52.650615 memory_type:LPDDR4
4975 13:38:52.653998 GP_NUM : 10
4976 13:38:52.654086 SRAM_EN : 1
4977 13:38:52.657219 MD32_EN : 0
4978 13:38:52.660586 ===================================
4979 13:38:52.663850 [ANA_INIT] >>>>>>>>>>>>>>
4980 13:38:52.667227 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 13:38:52.670407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 13:38:52.673613 ===================================
4983 13:38:52.673698 data_rate = 1866,PCW = 0X8f00
4984 13:38:52.676948 ===================================
4985 13:38:52.680462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 13:38:52.687043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 13:38:52.693749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 13:38:52.697146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 13:38:52.700236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 13:38:52.704091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 13:38:52.707496 [ANA_INIT] flow start
4992 13:38:52.710404 [ANA_INIT] PLL >>>>>>>>
4993 13:38:52.710492 [ANA_INIT] PLL <<<<<<<<
4994 13:38:52.713840 [ANA_INIT] MIDPI >>>>>>>>
4995 13:38:52.717118 [ANA_INIT] MIDPI <<<<<<<<
4996 13:38:52.717221 [ANA_INIT] DLL >>>>>>>>
4997 13:38:52.720365 [ANA_INIT] flow end
4998 13:38:52.723550 ============ LP4 DIFF to SE enter ============
4999 13:38:52.727387 ============ LP4 DIFF to SE exit ============
5000 13:38:52.730595 [ANA_INIT] <<<<<<<<<<<<<
5001 13:38:52.733805 [Flow] Enable top DCM control >>>>>
5002 13:38:52.737066 [Flow] Enable top DCM control <<<<<
5003 13:38:52.740805 Enable DLL master slave shuffle
5004 13:38:52.747274 ==============================================================
5005 13:38:52.747396 Gating Mode config
5006 13:38:52.753863 ==============================================================
5007 13:38:52.753962 Config description:
5008 13:38:52.764009 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 13:38:52.770536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 13:38:52.777059 SELPH_MODE 0: By rank 1: By Phase
5011 13:38:52.780436 ==============================================================
5012 13:38:52.783747 GAT_TRACK_EN = 1
5013 13:38:52.787140 RX_GATING_MODE = 2
5014 13:38:52.790461 RX_GATING_TRACK_MODE = 2
5015 13:38:52.793586 SELPH_MODE = 1
5016 13:38:52.797178 PICG_EARLY_EN = 1
5017 13:38:52.800540 VALID_LAT_VALUE = 1
5018 13:38:52.803719 ==============================================================
5019 13:38:52.806909 Enter into Gating configuration >>>>
5020 13:38:52.810282 Exit from Gating configuration <<<<
5021 13:38:52.813695 Enter into DVFS_PRE_config >>>>>
5022 13:38:52.827344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 13:38:52.830446 Exit from DVFS_PRE_config <<<<<
5024 13:38:52.833774 Enter into PICG configuration >>>>
5025 13:38:52.833849 Exit from PICG configuration <<<<
5026 13:38:52.836972 [RX_INPUT] configuration >>>>>
5027 13:38:52.840264 [RX_INPUT] configuration <<<<<
5028 13:38:52.847201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 13:38:52.850381 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 13:38:52.856841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 13:38:52.863449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 13:38:52.870055 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 13:38:52.876706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 13:38:52.879989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 13:38:52.883704 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 13:38:52.886623 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 13:38:52.893310 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 13:38:52.896463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 13:38:52.900052 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 13:38:52.903234 ===================================
5041 13:38:52.906629 LPDDR4 DRAM CONFIGURATION
5042 13:38:52.909727 ===================================
5043 13:38:52.913091 EX_ROW_EN[0] = 0x0
5044 13:38:52.913174 EX_ROW_EN[1] = 0x0
5045 13:38:52.916429 LP4Y_EN = 0x0
5046 13:38:52.916513 WORK_FSP = 0x0
5047 13:38:52.920039 WL = 0x3
5048 13:38:52.920123 RL = 0x3
5049 13:38:52.923311 BL = 0x2
5050 13:38:52.923393 RPST = 0x0
5051 13:38:52.926484 RD_PRE = 0x0
5052 13:38:52.926568 WR_PRE = 0x1
5053 13:38:52.929786 WR_PST = 0x0
5054 13:38:52.929869 DBI_WR = 0x0
5055 13:38:52.933105 DBI_RD = 0x0
5056 13:38:52.933189 OTF = 0x1
5057 13:38:52.936412 ===================================
5058 13:38:52.943223 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 13:38:52.946562 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 13:38:52.949847 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 13:38:52.953489 ===================================
5062 13:38:52.956391 LPDDR4 DRAM CONFIGURATION
5063 13:38:52.959752 ===================================
5064 13:38:52.963058 EX_ROW_EN[0] = 0x10
5065 13:38:52.963145 EX_ROW_EN[1] = 0x0
5066 13:38:52.966411 LP4Y_EN = 0x0
5067 13:38:52.966495 WORK_FSP = 0x0
5068 13:38:52.969733 WL = 0x3
5069 13:38:52.969817 RL = 0x3
5070 13:38:52.972959 BL = 0x2
5071 13:38:52.973044 RPST = 0x0
5072 13:38:52.976385 RD_PRE = 0x0
5073 13:38:52.976501 WR_PRE = 0x1
5074 13:38:52.979707 WR_PST = 0x0
5075 13:38:52.979790 DBI_WR = 0x0
5076 13:38:52.983123 DBI_RD = 0x0
5077 13:38:52.983207 OTF = 0x1
5078 13:38:52.986422 ===================================
5079 13:38:52.993122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 13:38:52.997433 nWR fixed to 30
5081 13:38:53.000763 [ModeRegInit_LP4] CH0 RK0
5082 13:38:53.000873 [ModeRegInit_LP4] CH0 RK1
5083 13:38:53.004213 [ModeRegInit_LP4] CH1 RK0
5084 13:38:53.007490 [ModeRegInit_LP4] CH1 RK1
5085 13:38:53.007574 match AC timing 9
5086 13:38:53.013911 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 13:38:53.017209 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 13:38:53.020639 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 13:38:53.027258 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 13:38:53.030510 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 13:38:53.030594 ==
5092 13:38:53.033852 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 13:38:53.037220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 13:38:53.037347 ==
5095 13:38:53.043833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 13:38:53.050839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5097 13:38:53.054065 [CA 0] Center 37 (7~68) winsize 62
5098 13:38:53.057274 [CA 1] Center 38 (8~68) winsize 61
5099 13:38:53.060662 [CA 2] Center 35 (5~65) winsize 61
5100 13:38:53.063879 [CA 3] Center 34 (4~65) winsize 62
5101 13:38:53.067233 [CA 4] Center 34 (4~65) winsize 62
5102 13:38:53.070427 [CA 5] Center 33 (3~64) winsize 62
5103 13:38:53.070511
5104 13:38:53.073907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5105 13:38:53.073991
5106 13:38:53.077258 [CATrainingPosCal] consider 1 rank data
5107 13:38:53.080736 u2DelayCellTimex100 = 270/100 ps
5108 13:38:53.084101 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5109 13:38:53.087353 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5110 13:38:53.090573 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5111 13:38:53.093768 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5112 13:38:53.097170 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5113 13:38:53.100547 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5114 13:38:53.100621
5115 13:38:53.107138 CA PerBit enable=1, Macro0, CA PI delay=33
5116 13:38:53.107239
5117 13:38:53.110720 [CBTSetCACLKResult] CA Dly = 33
5118 13:38:53.110822 CS Dly: 6 (0~37)
5119 13:38:53.110913 ==
5120 13:38:53.114157 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 13:38:53.117193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 13:38:53.117306 ==
5123 13:38:53.124005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 13:38:53.130681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5125 13:38:53.134003 [CA 0] Center 38 (7~69) winsize 63
5126 13:38:53.137160 [CA 1] Center 38 (8~69) winsize 62
5127 13:38:53.140537 [CA 2] Center 35 (5~66) winsize 62
5128 13:38:53.144105 [CA 3] Center 35 (5~66) winsize 62
5129 13:38:53.147395 [CA 4] Center 34 (4~65) winsize 62
5130 13:38:53.150699 [CA 5] Center 34 (4~64) winsize 61
5131 13:38:53.150770
5132 13:38:53.153900 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5133 13:38:53.153972
5134 13:38:53.157248 [CATrainingPosCal] consider 2 rank data
5135 13:38:53.160562 u2DelayCellTimex100 = 270/100 ps
5136 13:38:53.163967 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5137 13:38:53.167340 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5138 13:38:53.170678 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5139 13:38:53.174038 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5140 13:38:53.177291 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5141 13:38:53.180660 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5142 13:38:53.180733
5143 13:38:53.187375 CA PerBit enable=1, Macro0, CA PI delay=34
5144 13:38:53.187478
5145 13:38:53.190795 [CBTSetCACLKResult] CA Dly = 34
5146 13:38:53.190868 CS Dly: 7 (0~39)
5147 13:38:53.190928
5148 13:38:53.193989 ----->DramcWriteLeveling(PI) begin...
5149 13:38:53.194072 ==
5150 13:38:53.197193 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 13:38:53.200581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 13:38:53.200686 ==
5153 13:38:53.203893 Write leveling (Byte 0): 31 => 31
5154 13:38:53.207173 Write leveling (Byte 1): 29 => 29
5155 13:38:53.210402 DramcWriteLeveling(PI) end<-----
5156 13:38:53.210506
5157 13:38:53.210599 ==
5158 13:38:53.214081 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 13:38:53.217517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 13:38:53.220781 ==
5161 13:38:53.220889 [Gating] SW mode calibration
5162 13:38:53.230588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 13:38:53.233969 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 13:38:53.237212 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5165 13:38:53.243712 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 13:38:53.247233 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 13:38:53.250626 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 13:38:53.257519 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 13:38:53.260712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 13:38:53.263881 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5171 13:38:53.270527 0 14 28 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
5172 13:38:53.273878 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5173 13:38:53.277432 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 13:38:53.283865 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 13:38:53.287240 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 13:38:53.290708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 13:38:53.297276 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 13:38:53.300658 0 15 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5179 13:38:53.303849 0 15 28 | B1->B0 | 2f2f 4545 | 1 0 | (0 0) (0 0)
5180 13:38:53.307181 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5181 13:38:53.313752 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 13:38:53.317253 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 13:38:53.320692 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 13:38:53.326990 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 13:38:53.330328 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 13:38:53.333760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 13:38:53.340351 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5188 13:38:53.343950 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 13:38:53.347325 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 13:38:53.353731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 13:38:53.357038 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 13:38:53.360340 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 13:38:53.367295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 13:38:53.370596 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 13:38:53.373953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 13:38:53.380211 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 13:38:53.383673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 13:38:53.386997 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 13:38:53.393904 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 13:38:53.397256 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 13:38:53.400762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 13:38:53.407259 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 13:38:53.410646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 13:38:53.413999 Total UI for P1: 0, mck2ui 16
5205 13:38:53.417243 best dqsien dly found for B0: ( 1, 2, 26)
5206 13:38:53.420479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5207 13:38:53.423783 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 13:38:53.427015 Total UI for P1: 0, mck2ui 16
5209 13:38:53.430631 best dqsien dly found for B1: ( 1, 2, 30)
5210 13:38:53.433864 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5211 13:38:53.437218 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5212 13:38:53.440589
5213 13:38:53.443846 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5214 13:38:53.447109 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5215 13:38:53.450418 [Gating] SW calibration Done
5216 13:38:53.450502 ==
5217 13:38:53.453618 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 13:38:53.457334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 13:38:53.457430 ==
5220 13:38:53.457511 RX Vref Scan: 0
5221 13:38:53.457616
5222 13:38:53.460557 RX Vref 0 -> 0, step: 1
5223 13:38:53.460639
5224 13:38:53.463819 RX Delay -80 -> 252, step: 8
5225 13:38:53.467090 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5226 13:38:53.470303 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5227 13:38:53.477218 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5228 13:38:53.480577 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5229 13:38:53.483925 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5230 13:38:53.487151 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5231 13:38:53.490584 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5232 13:38:53.493916 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5233 13:38:53.500452 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5234 13:38:53.503882 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5235 13:38:53.507065 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5236 13:38:53.510236 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5237 13:38:53.514054 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5238 13:38:53.517308 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5239 13:38:53.523587 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5240 13:38:53.527017 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5241 13:38:53.527145 ==
5242 13:38:53.530430 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 13:38:53.533646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 13:38:53.533733 ==
5245 13:38:53.533801 DQS Delay:
5246 13:38:53.536805 DQS0 = 0, DQS1 = 0
5247 13:38:53.536911 DQM Delay:
5248 13:38:53.540564 DQM0 = 105, DQM1 = 90
5249 13:38:53.540642 DQ Delay:
5250 13:38:53.543947 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5251 13:38:53.547201 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5252 13:38:53.550456 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5253 13:38:53.553708 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5254 13:38:53.553823
5255 13:38:53.553922
5256 13:38:53.554013 ==
5257 13:38:53.556987 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 13:38:53.563450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 13:38:53.563561 ==
5260 13:38:53.563667
5261 13:38:53.563760
5262 13:38:53.563851 TX Vref Scan disable
5263 13:38:53.566825 == TX Byte 0 ==
5264 13:38:53.570132 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 13:38:53.577062 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 13:38:53.577172 == TX Byte 1 ==
5267 13:38:53.580337 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5268 13:38:53.583850 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5269 13:38:53.586924 ==
5270 13:38:53.590204 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 13:38:53.593534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 13:38:53.593617 ==
5273 13:38:53.593683
5274 13:38:53.593744
5275 13:38:53.596922 TX Vref Scan disable
5276 13:38:53.597006 == TX Byte 0 ==
5277 13:38:53.603683 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5278 13:38:53.606973 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5279 13:38:53.607073 == TX Byte 1 ==
5280 13:38:53.613431 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5281 13:38:53.616649 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5282 13:38:53.616732
5283 13:38:53.616797 [DATLAT]
5284 13:38:53.620096 Freq=933, CH0 RK0
5285 13:38:53.620202
5286 13:38:53.620295 DATLAT Default: 0xd
5287 13:38:53.623424 0, 0xFFFF, sum = 0
5288 13:38:53.623510 1, 0xFFFF, sum = 0
5289 13:38:53.626841 2, 0xFFFF, sum = 0
5290 13:38:53.626964 3, 0xFFFF, sum = 0
5291 13:38:53.630086 4, 0xFFFF, sum = 0
5292 13:38:53.630171 5, 0xFFFF, sum = 0
5293 13:38:53.633696 6, 0xFFFF, sum = 0
5294 13:38:53.633780 7, 0xFFFF, sum = 0
5295 13:38:53.636930 8, 0xFFFF, sum = 0
5296 13:38:53.640074 9, 0xFFFF, sum = 0
5297 13:38:53.640158 10, 0x0, sum = 1
5298 13:38:53.640225 11, 0x0, sum = 2
5299 13:38:53.643453 12, 0x0, sum = 3
5300 13:38:53.643537 13, 0x0, sum = 4
5301 13:38:53.646912 best_step = 11
5302 13:38:53.646995
5303 13:38:53.647060 ==
5304 13:38:53.650182 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 13:38:53.653617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 13:38:53.653704 ==
5307 13:38:53.656788 RX Vref Scan: 1
5308 13:38:53.656873
5309 13:38:53.656957 RX Vref 0 -> 0, step: 1
5310 13:38:53.657037
5311 13:38:53.660025 RX Delay -53 -> 252, step: 4
5312 13:38:53.660110
5313 13:38:53.663657 Set Vref, RX VrefLevel [Byte0]: 58
5314 13:38:53.666974 [Byte1]: 50
5315 13:38:53.670674
5316 13:38:53.670764 Final RX Vref Byte 0 = 58 to rank0
5317 13:38:53.674015 Final RX Vref Byte 1 = 50 to rank0
5318 13:38:53.677690 Final RX Vref Byte 0 = 58 to rank1
5319 13:38:53.680615 Final RX Vref Byte 1 = 50 to rank1==
5320 13:38:53.684341 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 13:38:53.690796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 13:38:53.690879 ==
5323 13:38:53.690945 DQS Delay:
5324 13:38:53.691006 DQS0 = 0, DQS1 = 0
5325 13:38:53.694189 DQM Delay:
5326 13:38:53.694272 DQM0 = 107, DQM1 = 91
5327 13:38:53.697604 DQ Delay:
5328 13:38:53.700883 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5329 13:38:53.704195 DQ4 =108, DQ5 =100, DQ6 =116, DQ7 =112
5330 13:38:53.707593 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5331 13:38:53.710882 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5332 13:38:53.711040
5333 13:38:53.711205
5334 13:38:53.717738 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5335 13:38:53.720883 CH0 RK0: MR19=505, MR18=2723
5336 13:38:53.727719 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5337 13:38:53.727856
5338 13:38:53.730875 ----->DramcWriteLeveling(PI) begin...
5339 13:38:53.731023 ==
5340 13:38:53.734129 Dram Type= 6, Freq= 0, CH_0, rank 1
5341 13:38:53.737509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 13:38:53.737619 ==
5343 13:38:53.740786 Write leveling (Byte 0): 33 => 33
5344 13:38:53.744413 Write leveling (Byte 1): 30 => 30
5345 13:38:53.747362 DramcWriteLeveling(PI) end<-----
5346 13:38:53.747472
5347 13:38:53.747565 ==
5348 13:38:53.750785 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 13:38:53.754262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 13:38:53.757338 ==
5351 13:38:53.757441 [Gating] SW mode calibration
5352 13:38:53.764169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5353 13:38:53.770776 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5354 13:38:53.773913 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 13:38:53.780681 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 13:38:53.783870 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 13:38:53.787155 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 13:38:53.793871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 13:38:53.797191 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 13:38:53.800551 0 14 24 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 1)
5361 13:38:53.807398 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5362 13:38:53.810796 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 13:38:53.814175 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 13:38:53.820615 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 13:38:53.823657 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 13:38:53.827110 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 13:38:53.833786 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 13:38:53.837051 0 15 24 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5369 13:38:53.840207 0 15 28 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
5370 13:38:53.846895 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 13:38:53.850661 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 13:38:53.853975 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 13:38:53.856939 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 13:38:53.863869 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 13:38:53.867428 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 13:38:53.870403 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 13:38:53.877039 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5378 13:38:53.880437 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5379 13:38:53.883721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 13:38:53.890736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 13:38:53.894024 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 13:38:53.897254 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 13:38:53.904049 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 13:38:53.907483 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 13:38:53.910662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 13:38:53.917085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 13:38:53.920299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 13:38:53.923679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 13:38:53.927306 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 13:38:53.933944 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 13:38:53.937316 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 13:38:53.940674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5393 13:38:53.947186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5394 13:38:53.950399 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 13:38:53.953938 Total UI for P1: 0, mck2ui 16
5396 13:38:53.957195 best dqsien dly found for B0: ( 1, 2, 28)
5397 13:38:53.960587 Total UI for P1: 0, mck2ui 16
5398 13:38:53.963753 best dqsien dly found for B1: ( 1, 2, 26)
5399 13:38:53.967596 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5400 13:38:53.970792 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5401 13:38:53.970867
5402 13:38:53.973952 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5403 13:38:53.977163 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5404 13:38:53.980503 [Gating] SW calibration Done
5405 13:38:53.980578 ==
5406 13:38:53.983734 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 13:38:53.990395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 13:38:53.990481 ==
5409 13:38:53.990546 RX Vref Scan: 0
5410 13:38:53.990605
5411 13:38:53.993598 RX Vref 0 -> 0, step: 1
5412 13:38:53.993669
5413 13:38:53.997085 RX Delay -80 -> 252, step: 8
5414 13:38:54.000397 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5415 13:38:54.003808 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5416 13:38:54.007180 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5417 13:38:54.010045 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5418 13:38:54.016713 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5419 13:38:54.020009 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5420 13:38:54.023398 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5421 13:38:54.026819 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5422 13:38:54.030096 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5423 13:38:54.033278 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5424 13:38:54.039998 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5425 13:38:54.043388 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5426 13:38:54.046641 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5427 13:38:54.049839 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5428 13:38:54.053048 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5429 13:38:54.056720 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5430 13:38:54.060118 ==
5431 13:38:54.063490 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 13:38:54.066631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 13:38:54.066714 ==
5434 13:38:54.066780 DQS Delay:
5435 13:38:54.070034 DQS0 = 0, DQS1 = 0
5436 13:38:54.070107 DQM Delay:
5437 13:38:54.073284 DQM0 = 105, DQM1 = 91
5438 13:38:54.073413 DQ Delay:
5439 13:38:54.076539 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5440 13:38:54.079979 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5441 13:38:54.083205 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5442 13:38:54.086476 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =95
5443 13:38:54.086549
5444 13:38:54.086610
5445 13:38:54.086667 ==
5446 13:38:54.089834 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 13:38:54.093144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 13:38:54.093253 ==
5449 13:38:54.093375
5450 13:38:54.093442
5451 13:38:54.096481 TX Vref Scan disable
5452 13:38:54.099757 == TX Byte 0 ==
5453 13:38:54.103404 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5454 13:38:54.106748 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5455 13:38:54.110070 == TX Byte 1 ==
5456 13:38:54.112993 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5457 13:38:54.116286 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5458 13:38:54.116356 ==
5459 13:38:54.119987 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 13:38:54.126468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 13:38:54.126555 ==
5462 13:38:54.126618
5463 13:38:54.126677
5464 13:38:54.126732 TX Vref Scan disable
5465 13:38:54.130737 == TX Byte 0 ==
5466 13:38:54.133567 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5467 13:38:54.136891 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5468 13:38:54.140664 == TX Byte 1 ==
5469 13:38:54.143595 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5470 13:38:54.147344 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5471 13:38:54.150458
5472 13:38:54.150539 [DATLAT]
5473 13:38:54.150603 Freq=933, CH0 RK1
5474 13:38:54.150662
5475 13:38:54.153632 DATLAT Default: 0xb
5476 13:38:54.153742 0, 0xFFFF, sum = 0
5477 13:38:54.156878 1, 0xFFFF, sum = 0
5478 13:38:54.156960 2, 0xFFFF, sum = 0
5479 13:38:54.160450 3, 0xFFFF, sum = 0
5480 13:38:54.160548 4, 0xFFFF, sum = 0
5481 13:38:54.163755 5, 0xFFFF, sum = 0
5482 13:38:54.167036 6, 0xFFFF, sum = 0
5483 13:38:54.167118 7, 0xFFFF, sum = 0
5484 13:38:54.170183 8, 0xFFFF, sum = 0
5485 13:38:54.170291 9, 0xFFFF, sum = 0
5486 13:38:54.173688 10, 0x0, sum = 1
5487 13:38:54.173769 11, 0x0, sum = 2
5488 13:38:54.173834 12, 0x0, sum = 3
5489 13:38:54.176814 13, 0x0, sum = 4
5490 13:38:54.176896 best_step = 11
5491 13:38:54.176959
5492 13:38:54.180439 ==
5493 13:38:54.180520 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 13:38:54.186825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 13:38:54.186907 ==
5496 13:38:54.186970 RX Vref Scan: 0
5497 13:38:54.187029
5498 13:38:54.190547 RX Vref 0 -> 0, step: 1
5499 13:38:54.190627
5500 13:38:54.193817 RX Delay -53 -> 252, step: 4
5501 13:38:54.197159 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5502 13:38:54.203563 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5503 13:38:54.206766 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5504 13:38:54.210085 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5505 13:38:54.213830 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5506 13:38:54.217188 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5507 13:38:54.220187 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5508 13:38:54.226865 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5509 13:38:54.230151 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5510 13:38:54.233537 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5511 13:38:54.236916 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5512 13:38:54.240150 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5513 13:38:54.246836 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5514 13:38:54.250322 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5515 13:38:54.253495 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5516 13:38:54.257073 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5517 13:38:54.257154 ==
5518 13:38:54.260473 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 13:38:54.263613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 13:38:54.266890 ==
5521 13:38:54.266978 DQS Delay:
5522 13:38:54.267042 DQS0 = 0, DQS1 = 0
5523 13:38:54.270131 DQM Delay:
5524 13:38:54.270212 DQM0 = 104, DQM1 = 92
5525 13:38:54.273545 DQ Delay:
5526 13:38:54.276921 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5527 13:38:54.280245 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5528 13:38:54.283609 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5529 13:38:54.286804 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5530 13:38:54.286885
5531 13:38:54.286948
5532 13:38:54.293307 [DQSOSCAuto] RK1, (LSB)MR18= 0x3010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5533 13:38:54.297036 CH0 RK1: MR19=505, MR18=3010
5534 13:38:54.303574 CH0_RK1: MR19=0x505, MR18=0x3010, DQSOSC=406, MR23=63, INC=65, DEC=43
5535 13:38:54.307059 [RxdqsGatingPostProcess] freq 933
5536 13:38:54.310336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 13:38:54.313445 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 13:38:54.316841 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 13:38:54.320327 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 13:38:54.323200 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 13:38:54.326948 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 13:38:54.330267 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 13:38:54.333599 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 13:38:54.336564 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 13:38:54.339944 Pre-setting of DQS Precalculation
5546 13:38:54.343554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 13:38:54.343655 ==
5548 13:38:54.346827 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 13:38:54.353602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 13:38:54.353677 ==
5551 13:38:54.356834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 13:38:54.363405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5553 13:38:54.366895 [CA 0] Center 38 (8~68) winsize 61
5554 13:38:54.370467 [CA 1] Center 38 (8~68) winsize 61
5555 13:38:54.373751 [CA 2] Center 36 (6~66) winsize 61
5556 13:38:54.377075 [CA 3] Center 35 (5~65) winsize 61
5557 13:38:54.379975 [CA 4] Center 35 (5~66) winsize 62
5558 13:38:54.383315 [CA 5] Center 34 (4~65) winsize 62
5559 13:38:54.383396
5560 13:38:54.386590 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5561 13:38:54.386670
5562 13:38:54.390211 [CATrainingPosCal] consider 1 rank data
5563 13:38:54.393575 u2DelayCellTimex100 = 270/100 ps
5564 13:38:54.396791 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5565 13:38:54.400044 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5566 13:38:54.403446 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5567 13:38:54.410226 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5568 13:38:54.413397 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5569 13:38:54.416672 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5570 13:38:54.416753
5571 13:38:54.419988 CA PerBit enable=1, Macro0, CA PI delay=34
5572 13:38:54.420069
5573 13:38:54.423364 [CBTSetCACLKResult] CA Dly = 34
5574 13:38:54.423475 CS Dly: 7 (0~38)
5575 13:38:54.423538 ==
5576 13:38:54.426735 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 13:38:54.433272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 13:38:54.433377 ==
5579 13:38:54.436683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 13:38:54.443652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5581 13:38:54.446521 [CA 0] Center 38 (8~68) winsize 61
5582 13:38:54.450097 [CA 1] Center 38 (8~69) winsize 62
5583 13:38:54.453430 [CA 2] Center 35 (5~66) winsize 62
5584 13:38:54.456363 [CA 3] Center 35 (5~66) winsize 62
5585 13:38:54.459767 [CA 4] Center 35 (5~66) winsize 62
5586 13:38:54.462967 [CA 5] Center 35 (5~65) winsize 61
5587 13:38:54.463073
5588 13:38:54.466323 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5589 13:38:54.466410
5590 13:38:54.470120 [CATrainingPosCal] consider 2 rank data
5591 13:38:54.473147 u2DelayCellTimex100 = 270/100 ps
5592 13:38:54.476720 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5593 13:38:54.483162 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5594 13:38:54.486639 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5595 13:38:54.489833 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5596 13:38:54.492965 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5597 13:38:54.496285 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5598 13:38:54.496357
5599 13:38:54.500041 CA PerBit enable=1, Macro0, CA PI delay=35
5600 13:38:54.500108
5601 13:38:54.503260 [CBTSetCACLKResult] CA Dly = 35
5602 13:38:54.503329 CS Dly: 7 (0~38)
5603 13:38:54.503388
5604 13:38:54.506665 ----->DramcWriteLeveling(PI) begin...
5605 13:38:54.509744 ==
5606 13:38:54.513178 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 13:38:54.516333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 13:38:54.516402 ==
5609 13:38:54.519547 Write leveling (Byte 0): 27 => 27
5610 13:38:54.523079 Write leveling (Byte 1): 27 => 27
5611 13:38:54.526395 DramcWriteLeveling(PI) end<-----
5612 13:38:54.526469
5613 13:38:54.526530 ==
5614 13:38:54.529735 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 13:38:54.532962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 13:38:54.533036 ==
5617 13:38:54.536289 [Gating] SW mode calibration
5618 13:38:54.542960 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 13:38:54.549756 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 13:38:54.553003 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 13:38:54.556217 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 13:38:54.559599 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 13:38:54.566227 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 13:38:54.569863 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 13:38:54.572770 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5626 13:38:54.579511 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5627 13:38:54.582898 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5628 13:38:54.586091 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 13:38:54.592659 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 13:38:54.596309 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 13:38:54.599551 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 13:38:54.606295 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 13:38:54.609316 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 13:38:54.612734 0 15 24 | B1->B0 | 2626 2c2c | 1 0 | (0 0) (1 1)
5635 13:38:54.619506 0 15 28 | B1->B0 | 4040 4444 | 1 0 | (0 0) (0 0)
5636 13:38:54.622926 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 13:38:54.626080 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 13:38:54.632963 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 13:38:54.636317 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 13:38:54.639622 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 13:38:54.645877 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 13:38:54.649385 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5643 13:38:54.652678 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5644 13:38:54.659171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 13:38:54.662645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 13:38:54.666063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 13:38:54.672599 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 13:38:54.676018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 13:38:54.679273 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 13:38:54.682741 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 13:38:54.689345 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 13:38:54.692828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 13:38:54.696131 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 13:38:54.702671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 13:38:54.706416 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 13:38:54.709598 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 13:38:54.716201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 13:38:54.719551 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5659 13:38:54.722565 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 13:38:54.726022 Total UI for P1: 0, mck2ui 16
5661 13:38:54.729290 best dqsien dly found for B0: ( 1, 2, 24)
5662 13:38:54.732854 Total UI for P1: 0, mck2ui 16
5663 13:38:54.735985 best dqsien dly found for B1: ( 1, 2, 26)
5664 13:38:54.739737 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5665 13:38:54.743023 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5666 13:38:54.743098
5667 13:38:54.746380 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5668 13:38:54.752651 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5669 13:38:54.752737 [Gating] SW calibration Done
5670 13:38:54.756116 ==
5671 13:38:54.756222 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 13:38:54.763073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 13:38:54.763184 ==
5674 13:38:54.763281 RX Vref Scan: 0
5675 13:38:54.763460
5676 13:38:54.766433 RX Vref 0 -> 0, step: 1
5677 13:38:54.766542
5678 13:38:54.769840 RX Delay -80 -> 252, step: 8
5679 13:38:54.773147 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5680 13:38:54.776315 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5681 13:38:54.779556 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5682 13:38:54.782930 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5683 13:38:54.789358 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5684 13:38:54.792738 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5685 13:38:54.796115 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5686 13:38:54.799606 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5687 13:38:54.802933 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5688 13:38:54.806143 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5689 13:38:54.812820 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5690 13:38:54.816057 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5691 13:38:54.819333 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5692 13:38:54.822704 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5693 13:38:54.826144 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5694 13:38:54.832920 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5695 13:38:54.833028 ==
5696 13:38:54.835797 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 13:38:54.839526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 13:38:54.839637 ==
5699 13:38:54.839731 DQS Delay:
5700 13:38:54.842840 DQS0 = 0, DQS1 = 0
5701 13:38:54.842924 DQM Delay:
5702 13:38:54.846058 DQM0 = 101, DQM1 = 94
5703 13:38:54.846143 DQ Delay:
5704 13:38:54.849200 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5705 13:38:54.852424 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5706 13:38:54.855779 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5707 13:38:54.859177 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5708 13:38:54.859279
5709 13:38:54.859372
5710 13:38:54.859460 ==
5711 13:38:54.862540 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 13:38:54.865754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 13:38:54.869048 ==
5714 13:38:54.869154
5715 13:38:54.869255
5716 13:38:54.869370 TX Vref Scan disable
5717 13:38:54.872450 == TX Byte 0 ==
5718 13:38:54.875630 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5719 13:38:54.879323 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5720 13:38:54.882574 == TX Byte 1 ==
5721 13:38:54.885820 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5722 13:38:54.889135 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5723 13:38:54.889238 ==
5724 13:38:54.892225 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 13:38:54.898879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 13:38:54.898958 ==
5727 13:38:54.899022
5728 13:38:54.899083
5729 13:38:54.902125 TX Vref Scan disable
5730 13:38:54.902201 == TX Byte 0 ==
5731 13:38:54.908756 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5732 13:38:54.912028 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5733 13:38:54.912105 == TX Byte 1 ==
5734 13:38:54.918964 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5735 13:38:54.922247 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5736 13:38:54.922340
5737 13:38:54.922407 [DATLAT]
5738 13:38:54.925624 Freq=933, CH1 RK0
5739 13:38:54.925734
5740 13:38:54.925829 DATLAT Default: 0xd
5741 13:38:54.928988 0, 0xFFFF, sum = 0
5742 13:38:54.929064 1, 0xFFFF, sum = 0
5743 13:38:54.932332 2, 0xFFFF, sum = 0
5744 13:38:54.932407 3, 0xFFFF, sum = 0
5745 13:38:54.935334 4, 0xFFFF, sum = 0
5746 13:38:54.935436 5, 0xFFFF, sum = 0
5747 13:38:54.938573 6, 0xFFFF, sum = 0
5748 13:38:54.938675 7, 0xFFFF, sum = 0
5749 13:38:54.941936 8, 0xFFFF, sum = 0
5750 13:38:54.945411 9, 0xFFFF, sum = 0
5751 13:38:54.945487 10, 0x0, sum = 1
5752 13:38:54.945550 11, 0x0, sum = 2
5753 13:38:54.948702 12, 0x0, sum = 3
5754 13:38:54.948815 13, 0x0, sum = 4
5755 13:38:54.952029 best_step = 11
5756 13:38:54.952157
5757 13:38:54.952266 ==
5758 13:38:54.955491 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 13:38:54.958908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 13:38:54.959062 ==
5761 13:38:54.962342 RX Vref Scan: 1
5762 13:38:54.962480
5763 13:38:54.962547 RX Vref 0 -> 0, step: 1
5764 13:38:54.962610
5765 13:38:54.965742 RX Delay -53 -> 252, step: 4
5766 13:38:54.965870
5767 13:38:54.969106 Set Vref, RX VrefLevel [Byte0]: 51
5768 13:38:54.971883 [Byte1]: 50
5769 13:38:54.976340
5770 13:38:54.976509 Final RX Vref Byte 0 = 51 to rank0
5771 13:38:54.979076 Final RX Vref Byte 1 = 50 to rank0
5772 13:38:54.982460 Final RX Vref Byte 0 = 51 to rank1
5773 13:38:54.985822 Final RX Vref Byte 1 = 50 to rank1==
5774 13:38:54.989534 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 13:38:54.996116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 13:38:54.996528 ==
5777 13:38:54.996839 DQS Delay:
5778 13:38:54.997160 DQS0 = 0, DQS1 = 0
5779 13:38:54.999856 DQM Delay:
5780 13:38:55.000357 DQM0 = 104, DQM1 = 97
5781 13:38:55.002639 DQ Delay:
5782 13:38:55.006035 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5783 13:38:55.009405 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =100
5784 13:38:55.012799 DQ8 =86, DQ9 =86, DQ10 =102, DQ11 =90
5785 13:38:55.016059 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5786 13:38:55.016573
5787 13:38:55.017013
5788 13:38:55.022872 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5789 13:38:55.026039 CH1 RK0: MR19=505, MR18=1B34
5790 13:38:55.033017 CH1_RK0: MR19=0x505, MR18=0x1B34, DQSOSC=405, MR23=63, INC=66, DEC=44
5791 13:38:55.033582
5792 13:38:55.036027 ----->DramcWriteLeveling(PI) begin...
5793 13:38:55.036606 ==
5794 13:38:55.039314 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 13:38:55.042791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 13:38:55.043409 ==
5797 13:38:55.046087 Write leveling (Byte 0): 28 => 28
5798 13:38:55.049516 Write leveling (Byte 1): 27 => 27
5799 13:38:55.052682 DramcWriteLeveling(PI) end<-----
5800 13:38:55.053276
5801 13:38:55.053799 ==
5802 13:38:55.055915 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 13:38:55.059278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 13:38:55.062495 ==
5805 13:38:55.062740 [Gating] SW mode calibration
5806 13:38:55.072692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 13:38:55.076026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 13:38:55.079438 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5809 13:38:55.085740 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 13:38:55.088995 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 13:38:55.092155 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 13:38:55.099072 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 13:38:55.102291 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 13:38:55.105591 0 14 24 | B1->B0 | 3030 3434 | 0 0 | (0 1) (0 0)
5815 13:38:55.112385 0 14 28 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
5816 13:38:55.115854 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5817 13:38:55.119197 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 13:38:55.125533 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 13:38:55.128959 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 13:38:55.132354 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 13:38:55.139094 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 13:38:55.142487 0 15 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5823 13:38:55.145907 0 15 28 | B1->B0 | 4141 3b3b | 0 0 | (0 0) (0 0)
5824 13:38:55.152203 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 13:38:55.155925 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 13:38:55.159319 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 13:38:55.162215 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 13:38:55.169194 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 13:38:55.172591 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 13:38:55.175511 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5831 13:38:55.182139 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5832 13:38:55.185557 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 13:38:55.189074 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 13:38:55.195593 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 13:38:55.198842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 13:38:55.202223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 13:38:55.208860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 13:38:55.212143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 13:38:55.215850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 13:38:55.222482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 13:38:55.225392 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 13:38:55.229076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 13:38:55.235751 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 13:38:55.239063 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 13:38:55.242312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 13:38:55.248778 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 13:38:55.252266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 13:38:55.255455 Total UI for P1: 0, mck2ui 16
5849 13:38:55.258922 best dqsien dly found for B0: ( 1, 2, 26)
5850 13:38:55.262103 Total UI for P1: 0, mck2ui 16
5851 13:38:55.265675 best dqsien dly found for B1: ( 1, 2, 26)
5852 13:38:55.269013 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5853 13:38:55.272430 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5854 13:38:55.272514
5855 13:38:55.275662 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5856 13:38:55.279040 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5857 13:38:55.282238 [Gating] SW calibration Done
5858 13:38:55.282321 ==
5859 13:38:55.285544 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 13:38:55.288911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 13:38:55.288995 ==
5862 13:38:55.292485 RX Vref Scan: 0
5863 13:38:55.292567
5864 13:38:55.295744 RX Vref 0 -> 0, step: 1
5865 13:38:55.295827
5866 13:38:55.295893 RX Delay -80 -> 252, step: 8
5867 13:38:55.301839 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5868 13:38:55.305304 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5869 13:38:55.308634 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5870 13:38:55.311750 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5871 13:38:55.315161 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5872 13:38:55.322000 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5873 13:38:55.324921 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5874 13:38:55.328471 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5875 13:38:55.331638 iDelay=200, Bit 8, Center 87 (0 ~ 175) 176
5876 13:38:55.335085 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5877 13:38:55.338401 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5878 13:38:55.345015 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5879 13:38:55.348354 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5880 13:38:55.351601 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5881 13:38:55.355142 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5882 13:38:55.358427 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5883 13:38:55.358560 ==
5884 13:38:55.361690 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 13:38:55.368406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 13:38:55.368619 ==
5887 13:38:55.368806 DQS Delay:
5888 13:38:55.371386 DQS0 = 0, DQS1 = 0
5889 13:38:55.371538 DQM Delay:
5890 13:38:55.374881 DQM0 = 103, DQM1 = 95
5891 13:38:55.375059 DQ Delay:
5892 13:38:55.378307 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5893 13:38:55.381759 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5894 13:38:55.385063 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =91
5895 13:38:55.388294 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5896 13:38:55.388393
5897 13:38:55.388483
5898 13:38:55.388574 ==
5899 13:38:55.391376 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 13:38:55.394797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 13:38:55.394917 ==
5902 13:38:55.395014
5903 13:38:55.398209
5904 13:38:55.398302 TX Vref Scan disable
5905 13:38:55.401570 == TX Byte 0 ==
5906 13:38:55.404972 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 13:38:55.407939 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 13:38:55.411369 == TX Byte 1 ==
5909 13:38:55.414594 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5910 13:38:55.418291 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5911 13:38:55.418417 ==
5912 13:38:55.421642 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 13:38:55.428048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 13:38:55.428153 ==
5915 13:38:55.428224
5916 13:38:55.428286
5917 13:38:55.428344 TX Vref Scan disable
5918 13:38:55.431903 == TX Byte 0 ==
5919 13:38:55.435677 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 13:38:55.438994 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 13:38:55.442060 == TX Byte 1 ==
5922 13:38:55.445419 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5923 13:38:55.451933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5924 13:38:55.452024
5925 13:38:55.452092 [DATLAT]
5926 13:38:55.452155 Freq=933, CH1 RK1
5927 13:38:55.452216
5928 13:38:55.455292 DATLAT Default: 0xb
5929 13:38:55.455379 0, 0xFFFF, sum = 0
5930 13:38:55.458694 1, 0xFFFF, sum = 0
5931 13:38:55.458782 2, 0xFFFF, sum = 0
5932 13:38:55.461951 3, 0xFFFF, sum = 0
5933 13:38:55.465414 4, 0xFFFF, sum = 0
5934 13:38:55.465508 5, 0xFFFF, sum = 0
5935 13:38:55.468751 6, 0xFFFF, sum = 0
5936 13:38:55.468842 7, 0xFFFF, sum = 0
5937 13:38:55.471918 8, 0xFFFF, sum = 0
5938 13:38:55.472011 9, 0xFFFF, sum = 0
5939 13:38:55.475357 10, 0x0, sum = 1
5940 13:38:55.475442 11, 0x0, sum = 2
5941 13:38:55.475508 12, 0x0, sum = 3
5942 13:38:55.478777 13, 0x0, sum = 4
5943 13:38:55.478856 best_step = 11
5944 13:38:55.478918
5945 13:38:55.482198 ==
5946 13:38:55.482275 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 13:38:55.488669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 13:38:55.488770 ==
5949 13:38:55.488837 RX Vref Scan: 0
5950 13:38:55.488897
5951 13:38:55.491881 RX Vref 0 -> 0, step: 1
5952 13:38:55.491960
5953 13:38:55.495640 RX Delay -45 -> 252, step: 4
5954 13:38:55.498488 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5955 13:38:55.505589 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5956 13:38:55.508504 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5957 13:38:55.512112 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5958 13:38:55.515367 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5959 13:38:55.518758 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5960 13:38:55.525417 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5961 13:38:55.528768 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5962 13:38:55.531717 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5963 13:38:55.535220 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5964 13:38:55.538401 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5965 13:38:55.541836 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5966 13:38:55.548543 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5967 13:38:55.551673 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5968 13:38:55.555169 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5969 13:38:55.558712 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5970 13:38:55.558816 ==
5971 13:38:55.562078 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 13:38:55.568731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 13:38:55.568855 ==
5974 13:38:55.568951 DQS Delay:
5975 13:38:55.569042 DQS0 = 0, DQS1 = 0
5976 13:38:55.571814 DQM Delay:
5977 13:38:55.571936 DQM0 = 104, DQM1 = 96
5978 13:38:55.575231 DQ Delay:
5979 13:38:55.578255 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5980 13:38:55.581704 DQ4 =104, DQ5 =114, DQ6 =114, DQ7 =102
5981 13:38:55.585147 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5982 13:38:55.588471 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =106
5983 13:38:55.588626
5984 13:38:55.588793
5985 13:38:55.595057 [DQSOSCAuto] RK1, (LSB)MR18= 0x2704, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5986 13:38:55.598795 CH1 RK1: MR19=505, MR18=2704
5987 13:38:55.605338 CH1_RK1: MR19=0x505, MR18=0x2704, DQSOSC=409, MR23=63, INC=64, DEC=43
5988 13:38:55.608659 [RxdqsGatingPostProcess] freq 933
5989 13:38:55.615284 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 13:38:55.615645 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 13:38:55.618484 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 13:38:55.622032 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 13:38:55.625226 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 13:38:55.628356 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 13:38:55.631602 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 13:38:55.635011 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 13:38:55.638488 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 13:38:55.642027 Pre-setting of DQS Precalculation
5999 13:38:55.645194 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 13:38:55.655308 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 13:38:55.661642 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 13:38:55.661769
6003 13:38:55.661847
6004 13:38:55.665095 [Calibration Summary] 1866 Mbps
6005 13:38:55.665178 CH 0, Rank 0
6006 13:38:55.668523 SW Impedance : PASS
6007 13:38:55.668606 DUTY Scan : NO K
6008 13:38:55.671936 ZQ Calibration : PASS
6009 13:38:55.674936 Jitter Meter : NO K
6010 13:38:55.675032 CBT Training : PASS
6011 13:38:55.678486 Write leveling : PASS
6012 13:38:55.681882 RX DQS gating : PASS
6013 13:38:55.682007 RX DQ/DQS(RDDQC) : PASS
6014 13:38:55.684908 TX DQ/DQS : PASS
6015 13:38:55.688267 RX DATLAT : PASS
6016 13:38:55.688440 RX DQ/DQS(Engine): PASS
6017 13:38:55.691707 TX OE : NO K
6018 13:38:55.691860 All Pass.
6019 13:38:55.691981
6020 13:38:55.695148 CH 0, Rank 1
6021 13:38:55.695329 SW Impedance : PASS
6022 13:38:55.698579 DUTY Scan : NO K
6023 13:38:55.701864 ZQ Calibration : PASS
6024 13:38:55.702070 Jitter Meter : NO K
6025 13:38:55.704976 CBT Training : PASS
6026 13:38:55.708255 Write leveling : PASS
6027 13:38:55.708511 RX DQS gating : PASS
6028 13:38:55.711861 RX DQ/DQS(RDDQC) : PASS
6029 13:38:55.712161 TX DQ/DQS : PASS
6030 13:38:55.715424 RX DATLAT : PASS
6031 13:38:55.718715 RX DQ/DQS(Engine): PASS
6032 13:38:55.719114 TX OE : NO K
6033 13:38:55.722281 All Pass.
6034 13:38:55.722665
6035 13:38:55.723005 CH 1, Rank 0
6036 13:38:55.725290 SW Impedance : PASS
6037 13:38:55.725766 DUTY Scan : NO K
6038 13:38:55.728396 ZQ Calibration : PASS
6039 13:38:55.731893 Jitter Meter : NO K
6040 13:38:55.732316 CBT Training : PASS
6041 13:38:55.735432 Write leveling : PASS
6042 13:38:55.738896 RX DQS gating : PASS
6043 13:38:55.739318 RX DQ/DQS(RDDQC) : PASS
6044 13:38:55.741850 TX DQ/DQS : PASS
6045 13:38:55.745091 RX DATLAT : PASS
6046 13:38:55.745668 RX DQ/DQS(Engine): PASS
6047 13:38:55.748419 TX OE : NO K
6048 13:38:55.748841 All Pass.
6049 13:38:55.749210
6050 13:38:55.751797 CH 1, Rank 1
6051 13:38:55.752398 SW Impedance : PASS
6052 13:38:55.755162 DUTY Scan : NO K
6053 13:38:55.758397 ZQ Calibration : PASS
6054 13:38:55.758784 Jitter Meter : NO K
6055 13:38:55.761997 CBT Training : PASS
6056 13:38:55.762544 Write leveling : PASS
6057 13:38:55.764828 RX DQS gating : PASS
6058 13:38:55.768816 RX DQ/DQS(RDDQC) : PASS
6059 13:38:55.769257 TX DQ/DQS : PASS
6060 13:38:55.771706 RX DATLAT : PASS
6061 13:38:55.775036 RX DQ/DQS(Engine): PASS
6062 13:38:55.775473 TX OE : NO K
6063 13:38:55.778489 All Pass.
6064 13:38:55.778996
6065 13:38:55.779340 DramC Write-DBI off
6066 13:38:55.781740 PER_BANK_REFRESH: Hybrid Mode
6067 13:38:55.782171 TX_TRACKING: ON
6068 13:38:55.791889 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 13:38:55.794762 [FAST_K] Save calibration result to emmc
6070 13:38:55.798188 dramc_set_vcore_voltage set vcore to 650000
6071 13:38:55.801737 Read voltage for 400, 6
6072 13:38:55.802167 Vio18 = 0
6073 13:38:55.805111 Vcore = 650000
6074 13:38:55.805592 Vdram = 0
6075 13:38:55.805934 Vddq = 0
6076 13:38:55.808122 Vmddr = 0
6077 13:38:55.811768 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 13:38:55.818267 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 13:38:55.818742 MEM_TYPE=3, freq_sel=20
6080 13:38:55.821176 sv_algorithm_assistance_LP4_800
6081 13:38:55.828005 ============ PULL DRAM RESETB DOWN ============
6082 13:38:55.831458 ========== PULL DRAM RESETB DOWN end =========
6083 13:38:55.834656 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 13:38:55.837963 ===================================
6085 13:38:55.841352 LPDDR4 DRAM CONFIGURATION
6086 13:38:55.844799 ===================================
6087 13:38:55.845259 EX_ROW_EN[0] = 0x0
6088 13:38:55.848110 EX_ROW_EN[1] = 0x0
6089 13:38:55.851614 LP4Y_EN = 0x0
6090 13:38:55.852037 WORK_FSP = 0x0
6091 13:38:55.854837 WL = 0x2
6092 13:38:55.855257 RL = 0x2
6093 13:38:55.858211 BL = 0x2
6094 13:38:55.858648 RPST = 0x0
6095 13:38:55.861568 RD_PRE = 0x0
6096 13:38:55.861986 WR_PRE = 0x1
6097 13:38:55.865028 WR_PST = 0x0
6098 13:38:55.865499 DBI_WR = 0x0
6099 13:38:55.868321 DBI_RD = 0x0
6100 13:38:55.868755 OTF = 0x1
6101 13:38:55.871729 ===================================
6102 13:38:55.874706 ===================================
6103 13:38:55.878159 ANA top config
6104 13:38:55.881415 ===================================
6105 13:38:55.881839 DLL_ASYNC_EN = 0
6106 13:38:55.884816 ALL_SLAVE_EN = 1
6107 13:38:55.888248 NEW_RANK_MODE = 1
6108 13:38:55.891457 DLL_IDLE_MODE = 1
6109 13:38:55.891755 LP45_APHY_COMB_EN = 1
6110 13:38:55.894538 TX_ODT_DIS = 1
6111 13:38:55.897891 NEW_8X_MODE = 1
6112 13:38:55.901265 ===================================
6113 13:38:55.904665 ===================================
6114 13:38:55.907683 data_rate = 800
6115 13:38:55.910881 CKR = 1
6116 13:38:55.914222 DQ_P2S_RATIO = 4
6117 13:38:55.917676 ===================================
6118 13:38:55.917760 CA_P2S_RATIO = 4
6119 13:38:55.921006 DQ_CA_OPEN = 0
6120 13:38:55.924288 DQ_SEMI_OPEN = 1
6121 13:38:55.927703 CA_SEMI_OPEN = 1
6122 13:38:55.930821 CA_FULL_RATE = 0
6123 13:38:55.934236 DQ_CKDIV4_EN = 0
6124 13:38:55.934318 CA_CKDIV4_EN = 1
6125 13:38:55.937585 CA_PREDIV_EN = 0
6126 13:38:55.940738 PH8_DLY = 0
6127 13:38:55.944099 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 13:38:55.947517 DQ_AAMCK_DIV = 0
6129 13:38:55.950970 CA_AAMCK_DIV = 0
6130 13:38:55.951052 CA_ADMCK_DIV = 4
6131 13:38:55.954422 DQ_TRACK_CA_EN = 0
6132 13:38:55.957794 CA_PICK = 800
6133 13:38:55.961135 CA_MCKIO = 400
6134 13:38:55.964393 MCKIO_SEMI = 400
6135 13:38:55.967814 PLL_FREQ = 3016
6136 13:38:55.970658 DQ_UI_PI_RATIO = 32
6137 13:38:55.970760 CA_UI_PI_RATIO = 32
6138 13:38:55.974016 ===================================
6139 13:38:55.977455 ===================================
6140 13:38:55.981016 memory_type:LPDDR4
6141 13:38:55.984366 GP_NUM : 10
6142 13:38:55.984458 SRAM_EN : 1
6143 13:38:55.987661 MD32_EN : 0
6144 13:38:55.991054 ===================================
6145 13:38:55.993865 [ANA_INIT] >>>>>>>>>>>>>>
6146 13:38:55.997830 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 13:38:56.000844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 13:38:56.004332 ===================================
6149 13:38:56.004405 data_rate = 800,PCW = 0X7400
6150 13:38:56.007196 ===================================
6151 13:38:56.010699 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 13:38:56.017528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 13:38:56.030600 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 13:38:56.034011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 13:38:56.037697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 13:38:56.040843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 13:38:56.043908 [ANA_INIT] flow start
6158 13:38:56.043980 [ANA_INIT] PLL >>>>>>>>
6159 13:38:56.047287 [ANA_INIT] PLL <<<<<<<<
6160 13:38:56.050713 [ANA_INIT] MIDPI >>>>>>>>
6161 13:38:56.050819 [ANA_INIT] MIDPI <<<<<<<<
6162 13:38:56.054136 [ANA_INIT] DLL >>>>>>>>
6163 13:38:56.057584 [ANA_INIT] flow end
6164 13:38:56.060882 ============ LP4 DIFF to SE enter ============
6165 13:38:56.064271 ============ LP4 DIFF to SE exit ============
6166 13:38:56.067477 [ANA_INIT] <<<<<<<<<<<<<
6167 13:38:56.070519 [Flow] Enable top DCM control >>>>>
6168 13:38:56.074083 [Flow] Enable top DCM control <<<<<
6169 13:38:56.077391 Enable DLL master slave shuffle
6170 13:38:56.080695 ==============================================================
6171 13:38:56.083784 Gating Mode config
6172 13:38:56.090731 ==============================================================
6173 13:38:56.090840 Config description:
6174 13:38:56.100558 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 13:38:56.106879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 13:38:56.110362 SELPH_MODE 0: By rank 1: By Phase
6177 13:38:56.116751 ==============================================================
6178 13:38:56.120179 GAT_TRACK_EN = 0
6179 13:38:56.123549 RX_GATING_MODE = 2
6180 13:38:56.126987 RX_GATING_TRACK_MODE = 2
6181 13:38:56.130413 SELPH_MODE = 1
6182 13:38:56.133224 PICG_EARLY_EN = 1
6183 13:38:56.136817 VALID_LAT_VALUE = 1
6184 13:38:56.140170 ==============================================================
6185 13:38:56.143743 Enter into Gating configuration >>>>
6186 13:38:56.146597 Exit from Gating configuration <<<<
6187 13:38:56.149899 Enter into DVFS_PRE_config >>>>>
6188 13:38:56.160248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 13:38:56.163632 Exit from DVFS_PRE_config <<<<<
6190 13:38:56.166916 Enter into PICG configuration >>>>
6191 13:38:56.170229 Exit from PICG configuration <<<<
6192 13:38:56.173560 [RX_INPUT] configuration >>>>>
6193 13:38:56.176764 [RX_INPUT] configuration <<<<<
6194 13:38:56.183568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 13:38:56.186621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 13:38:56.193481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 13:38:56.199971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 13:38:56.206424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 13:38:56.213167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 13:38:56.216802 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 13:38:56.219765 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 13:38:56.223430 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 13:38:56.229573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 13:38:56.233048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 13:38:56.236674 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 13:38:56.239465 ===================================
6207 13:38:56.243173 LPDDR4 DRAM CONFIGURATION
6208 13:38:56.246340 ===================================
6209 13:38:56.246448 EX_ROW_EN[0] = 0x0
6210 13:38:56.249832 EX_ROW_EN[1] = 0x0
6211 13:38:56.252993 LP4Y_EN = 0x0
6212 13:38:56.253105 WORK_FSP = 0x0
6213 13:38:56.256371 WL = 0x2
6214 13:38:56.256532 RL = 0x2
6215 13:38:56.259371 BL = 0x2
6216 13:38:56.259468 RPST = 0x0
6217 13:38:56.263140 RD_PRE = 0x0
6218 13:38:56.263260 WR_PRE = 0x1
6219 13:38:56.266345 WR_PST = 0x0
6220 13:38:56.266487 DBI_WR = 0x0
6221 13:38:56.269812 DBI_RD = 0x0
6222 13:38:56.269916 OTF = 0x1
6223 13:38:56.272735 ===================================
6224 13:38:56.276382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 13:38:56.283002 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 13:38:56.286488 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 13:38:56.289448 ===================================
6228 13:38:56.293152 LPDDR4 DRAM CONFIGURATION
6229 13:38:56.296117 ===================================
6230 13:38:56.296230 EX_ROW_EN[0] = 0x10
6231 13:38:56.299668 EX_ROW_EN[1] = 0x0
6232 13:38:56.299757 LP4Y_EN = 0x0
6233 13:38:56.303043 WORK_FSP = 0x0
6234 13:38:56.306433 WL = 0x2
6235 13:38:56.306520 RL = 0x2
6236 13:38:56.309234 BL = 0x2
6237 13:38:56.309329 RPST = 0x0
6238 13:38:56.312732 RD_PRE = 0x0
6239 13:38:56.312819 WR_PRE = 0x1
6240 13:38:56.316158 WR_PST = 0x0
6241 13:38:56.316245 DBI_WR = 0x0
6242 13:38:56.319357 DBI_RD = 0x0
6243 13:38:56.319443 OTF = 0x1
6244 13:38:56.322794 ===================================
6245 13:38:56.329367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 13:38:56.333273 nWR fixed to 30
6247 13:38:56.336663 [ModeRegInit_LP4] CH0 RK0
6248 13:38:56.336738 [ModeRegInit_LP4] CH0 RK1
6249 13:38:56.340047 [ModeRegInit_LP4] CH1 RK0
6250 13:38:56.343393 [ModeRegInit_LP4] CH1 RK1
6251 13:38:56.343466 match AC timing 19
6252 13:38:56.349878 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 13:38:56.353524 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 13:38:56.356677 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 13:38:56.363740 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 13:38:56.366788 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 13:38:56.367252 ==
6258 13:38:56.370168 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 13:38:56.373561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 13:38:56.374007 ==
6261 13:38:56.379990 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 13:38:56.387024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6263 13:38:56.390290 [CA 0] Center 36 (8~64) winsize 57
6264 13:38:56.393400 [CA 1] Center 36 (8~64) winsize 57
6265 13:38:56.397006 [CA 2] Center 36 (8~64) winsize 57
6266 13:38:56.397480 [CA 3] Center 36 (8~64) winsize 57
6267 13:38:56.400384 [CA 4] Center 36 (8~64) winsize 57
6268 13:38:56.403390 [CA 5] Center 36 (8~64) winsize 57
6269 13:38:56.403830
6270 13:38:56.406808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6271 13:38:56.410434
6272 13:38:56.413722 [CATrainingPosCal] consider 1 rank data
6273 13:38:56.414150 u2DelayCellTimex100 = 270/100 ps
6274 13:38:56.419988 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 13:38:56.423795 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 13:38:56.426785 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 13:38:56.430264 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 13:38:56.433709 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 13:38:56.437169 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 13:38:56.437669
6281 13:38:56.440490 CA PerBit enable=1, Macro0, CA PI delay=36
6282 13:38:56.441007
6283 13:38:56.443837 [CBTSetCACLKResult] CA Dly = 36
6284 13:38:56.447073 CS Dly: 1 (0~32)
6285 13:38:56.447502 ==
6286 13:38:56.450401 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 13:38:56.453619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 13:38:56.454055 ==
6289 13:38:56.460176 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 13:38:56.463412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6291 13:38:56.466926 [CA 0] Center 36 (8~64) winsize 57
6292 13:38:56.470217 [CA 1] Center 36 (8~64) winsize 57
6293 13:38:56.473622 [CA 2] Center 36 (8~64) winsize 57
6294 13:38:56.477170 [CA 3] Center 36 (8~64) winsize 57
6295 13:38:56.480111 [CA 4] Center 36 (8~64) winsize 57
6296 13:38:56.483681 [CA 5] Center 36 (8~64) winsize 57
6297 13:38:56.484113
6298 13:38:56.486941 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6299 13:38:56.487370
6300 13:38:56.490269 [CATrainingPosCal] consider 2 rank data
6301 13:38:56.493567 u2DelayCellTimex100 = 270/100 ps
6302 13:38:56.497072 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 13:38:56.500087 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 13:38:56.503667 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 13:38:56.506642 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 13:38:56.513597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 13:38:56.517024 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 13:38:56.517502
6309 13:38:56.520131 CA PerBit enable=1, Macro0, CA PI delay=36
6310 13:38:56.520638
6311 13:38:56.523785 [CBTSetCACLKResult] CA Dly = 36
6312 13:38:56.524213 CS Dly: 1 (0~32)
6313 13:38:56.524553
6314 13:38:56.526919 ----->DramcWriteLeveling(PI) begin...
6315 13:38:56.527352 ==
6316 13:38:56.530123 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 13:38:56.536612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 13:38:56.536697 ==
6319 13:38:56.539977 Write leveling (Byte 0): 40 => 8
6320 13:38:56.540067 Write leveling (Byte 1): 32 => 0
6321 13:38:56.543387 DramcWriteLeveling(PI) end<-----
6322 13:38:56.543476
6323 13:38:56.543546 ==
6324 13:38:56.546722 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 13:38:56.553516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 13:38:56.553625 ==
6327 13:38:56.556837 [Gating] SW mode calibration
6328 13:38:56.563082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 13:38:56.566426 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 13:38:56.573259 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 13:38:56.576711 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 13:38:56.580122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 13:38:56.586903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 13:38:56.590016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 13:38:56.593206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 13:38:56.596574 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 13:38:56.603340 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 13:38:56.606651 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 13:38:56.609881 Total UI for P1: 0, mck2ui 16
6340 13:38:56.613455 best dqsien dly found for B0: ( 0, 14, 24)
6341 13:38:56.616764 Total UI for P1: 0, mck2ui 16
6342 13:38:56.620290 best dqsien dly found for B1: ( 0, 14, 24)
6343 13:38:56.623550 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 13:38:56.626838 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 13:38:56.627263
6346 13:38:56.629993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 13:38:56.636387 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 13:38:56.636692 [Gating] SW calibration Done
6349 13:38:56.636933 ==
6350 13:38:56.639679 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 13:38:56.646526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 13:38:56.646714 ==
6353 13:38:56.646860 RX Vref Scan: 0
6354 13:38:56.646996
6355 13:38:56.649909 RX Vref 0 -> 0, step: 1
6356 13:38:56.650063
6357 13:38:56.652968 RX Delay -410 -> 252, step: 16
6358 13:38:56.656395 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6359 13:38:56.659727 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6360 13:38:56.666192 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6361 13:38:56.669465 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6362 13:38:56.672742 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6363 13:38:56.676137 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6364 13:38:56.679523 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6365 13:38:56.686236 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6366 13:38:56.689514 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6367 13:38:56.692676 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6368 13:38:56.695896 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6369 13:38:56.702580 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6370 13:38:56.706027 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6371 13:38:56.709437 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6372 13:38:56.716118 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6373 13:38:56.719576 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6374 13:38:56.719667 ==
6375 13:38:56.722947 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 13:38:56.726411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 13:38:56.726496 ==
6378 13:38:56.726560 DQS Delay:
6379 13:38:56.729291 DQS0 = 19, DQS1 = 43
6380 13:38:56.729419 DQM Delay:
6381 13:38:56.732550 DQM0 = 9, DQM1 = 14
6382 13:38:56.732636 DQ Delay:
6383 13:38:56.735886 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6384 13:38:56.739209 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6385 13:38:56.742676 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6386 13:38:56.745959 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6387 13:38:56.746055
6388 13:38:56.746118
6389 13:38:56.746177 ==
6390 13:38:56.749412 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 13:38:56.752859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 13:38:56.752976 ==
6393 13:38:56.753042
6394 13:38:56.753100
6395 13:38:56.755825 TX Vref Scan disable
6396 13:38:56.759297 == TX Byte 0 ==
6397 13:38:56.762610 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 13:38:56.765834 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 13:38:56.769630 == TX Byte 1 ==
6400 13:38:56.772469 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6401 13:38:56.776164 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6402 13:38:56.776257 ==
6403 13:38:56.779551 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 13:38:56.782904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 13:38:56.783002 ==
6406 13:38:56.785792
6407 13:38:56.785874
6408 13:38:56.785937 TX Vref Scan disable
6409 13:38:56.789284 == TX Byte 0 ==
6410 13:38:56.792701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 13:38:56.796002 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 13:38:56.799179 == TX Byte 1 ==
6413 13:38:56.802416 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 13:38:56.806186 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 13:38:56.806273
6416 13:38:56.806337 [DATLAT]
6417 13:38:56.809118 Freq=400, CH0 RK0
6418 13:38:56.809211
6419 13:38:56.812718 DATLAT Default: 0xf
6420 13:38:56.812802 0, 0xFFFF, sum = 0
6421 13:38:56.816141 1, 0xFFFF, sum = 0
6422 13:38:56.816247 2, 0xFFFF, sum = 0
6423 13:38:56.819073 3, 0xFFFF, sum = 0
6424 13:38:56.819160 4, 0xFFFF, sum = 0
6425 13:38:56.822424 5, 0xFFFF, sum = 0
6426 13:38:56.822507 6, 0xFFFF, sum = 0
6427 13:38:56.825852 7, 0xFFFF, sum = 0
6428 13:38:56.825934 8, 0xFFFF, sum = 0
6429 13:38:56.829291 9, 0xFFFF, sum = 0
6430 13:38:56.829413 10, 0xFFFF, sum = 0
6431 13:38:56.832711 11, 0xFFFF, sum = 0
6432 13:38:56.832793 12, 0xFFFF, sum = 0
6433 13:38:56.835955 13, 0x0, sum = 1
6434 13:38:56.836045 14, 0x0, sum = 2
6435 13:38:56.839383 15, 0x0, sum = 3
6436 13:38:56.839465 16, 0x0, sum = 4
6437 13:38:56.842798 best_step = 14
6438 13:38:56.842879
6439 13:38:56.842942 ==
6440 13:38:56.845790 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 13:38:56.849148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 13:38:56.849230 ==
6443 13:38:56.852529 RX Vref Scan: 1
6444 13:38:56.852611
6445 13:38:56.852676 RX Vref 0 -> 0, step: 1
6446 13:38:56.852736
6447 13:38:56.855936 RX Delay -327 -> 252, step: 8
6448 13:38:56.856023
6449 13:38:56.859349 Set Vref, RX VrefLevel [Byte0]: 58
6450 13:38:56.862298 [Byte1]: 50
6451 13:38:56.866672
6452 13:38:56.866757 Final RX Vref Byte 0 = 58 to rank0
6453 13:38:56.869986 Final RX Vref Byte 1 = 50 to rank0
6454 13:38:56.873721 Final RX Vref Byte 0 = 58 to rank1
6455 13:38:56.876956 Final RX Vref Byte 1 = 50 to rank1==
6456 13:38:56.880284 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 13:38:56.886551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 13:38:56.886633 ==
6459 13:38:56.886696 DQS Delay:
6460 13:38:56.890014 DQS0 = 28, DQS1 = 48
6461 13:38:56.890098 DQM Delay:
6462 13:38:56.890162 DQM0 = 12, DQM1 = 15
6463 13:38:56.893417 DQ Delay:
6464 13:38:56.896784 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6465 13:38:56.896865 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6466 13:38:56.900079 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6467 13:38:56.903671 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6468 13:38:56.903752
6469 13:38:56.903883
6470 13:38:56.913721 [DQSOSCAuto] RK0, (LSB)MR18= 0xb5ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6471 13:38:56.917166 CH0 RK0: MR19=C0C, MR18=B5AC
6472 13:38:56.923642 CH0_RK0: MR19=0xC0C, MR18=0xB5AC, DQSOSC=387, MR23=63, INC=394, DEC=262
6473 13:38:56.923723 ==
6474 13:38:56.927074 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 13:38:56.930425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 13:38:56.930506 ==
6477 13:38:56.933717 [Gating] SW mode calibration
6478 13:38:56.940350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 13:38:56.943781 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 13:38:56.949962 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 13:38:56.953445 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 13:38:56.956740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 13:38:56.963544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 13:38:56.966948 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 13:38:56.970316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 13:38:56.976740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 13:38:56.979977 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 13:38:56.983711 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 13:38:56.986674 Total UI for P1: 0, mck2ui 16
6490 13:38:56.990127 best dqsien dly found for B0: ( 0, 14, 24)
6491 13:38:56.993507 Total UI for P1: 0, mck2ui 16
6492 13:38:56.996935 best dqsien dly found for B1: ( 0, 14, 24)
6493 13:38:57.000429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 13:38:57.003580 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 13:38:57.003661
6496 13:38:57.010216 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 13:38:57.013349 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 13:38:57.016630 [Gating] SW calibration Done
6499 13:38:57.016710 ==
6500 13:38:57.020461 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 13:38:57.023443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 13:38:57.023524 ==
6503 13:38:57.023587 RX Vref Scan: 0
6504 13:38:57.023646
6505 13:38:57.026863 RX Vref 0 -> 0, step: 1
6506 13:38:57.026943
6507 13:38:57.030402 RX Delay -410 -> 252, step: 16
6508 13:38:57.033662 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6509 13:38:57.036957 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6510 13:38:57.043423 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6511 13:38:57.046767 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6512 13:38:57.050314 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6513 13:38:57.053662 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6514 13:38:57.060072 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6515 13:38:57.063390 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6516 13:38:57.066840 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6517 13:38:57.070247 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6518 13:38:57.076505 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6519 13:38:57.080150 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6520 13:38:57.083453 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6521 13:38:57.090045 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6522 13:38:57.093022 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6523 13:38:57.096413 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6524 13:38:57.096494 ==
6525 13:38:57.099821 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 13:38:57.103235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 13:38:57.106532 ==
6528 13:38:57.106612 DQS Delay:
6529 13:38:57.106675 DQS0 = 27, DQS1 = 43
6530 13:38:57.109779 DQM Delay:
6531 13:38:57.109859 DQM0 = 9, DQM1 = 15
6532 13:38:57.113000 DQ Delay:
6533 13:38:57.113080 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6534 13:38:57.116360 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6535 13:38:57.119298 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6536 13:38:57.122647 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6537 13:38:57.122727
6538 13:38:57.122791
6539 13:38:57.122849 ==
6540 13:38:57.126023 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 13:38:57.132859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 13:38:57.132940 ==
6543 13:38:57.133003
6544 13:38:57.133061
6545 13:38:57.133117 TX Vref Scan disable
6546 13:38:57.136228 == TX Byte 0 ==
6547 13:38:57.139532 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6548 13:38:57.143016 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6549 13:38:57.146261 == TX Byte 1 ==
6550 13:38:57.149615 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6551 13:38:57.153099 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6552 13:38:57.153180 ==
6553 13:38:57.156478 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 13:38:57.162731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 13:38:57.162813 ==
6556 13:38:57.162878
6557 13:38:57.162937
6558 13:38:57.162995 TX Vref Scan disable
6559 13:38:57.166218 == TX Byte 0 ==
6560 13:38:57.169512 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6561 13:38:57.172967 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6562 13:38:57.176458 == TX Byte 1 ==
6563 13:38:57.179626 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6564 13:38:57.182863 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6565 13:38:57.182944
6566 13:38:57.186241 [DATLAT]
6567 13:38:57.186322 Freq=400, CH0 RK1
6568 13:38:57.186385
6569 13:38:57.189574 DATLAT Default: 0xe
6570 13:38:57.189655 0, 0xFFFF, sum = 0
6571 13:38:57.192791 1, 0xFFFF, sum = 0
6572 13:38:57.192872 2, 0xFFFF, sum = 0
6573 13:38:57.196211 3, 0xFFFF, sum = 0
6574 13:38:57.196293 4, 0xFFFF, sum = 0
6575 13:38:57.199567 5, 0xFFFF, sum = 0
6576 13:38:57.199649 6, 0xFFFF, sum = 0
6577 13:38:57.202911 7, 0xFFFF, sum = 0
6578 13:38:57.202992 8, 0xFFFF, sum = 0
6579 13:38:57.206324 9, 0xFFFF, sum = 0
6580 13:38:57.209688 10, 0xFFFF, sum = 0
6581 13:38:57.209770 11, 0xFFFF, sum = 0
6582 13:38:57.212565 12, 0xFFFF, sum = 0
6583 13:38:57.212679 13, 0x0, sum = 1
6584 13:38:57.216070 14, 0x0, sum = 2
6585 13:38:57.216157 15, 0x0, sum = 3
6586 13:38:57.216225 16, 0x0, sum = 4
6587 13:38:57.219595 best_step = 14
6588 13:38:57.219676
6589 13:38:57.219751 ==
6590 13:38:57.222432 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 13:38:57.226321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 13:38:57.226489 ==
6593 13:38:57.229353 RX Vref Scan: 0
6594 13:38:57.229481
6595 13:38:57.232626 RX Vref 0 -> 0, step: 1
6596 13:38:57.232727
6597 13:38:57.232800 RX Delay -327 -> 252, step: 8
6598 13:38:57.241168 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6599 13:38:57.244514 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6600 13:38:57.247998 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6601 13:38:57.250999 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6602 13:38:57.257895 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6603 13:38:57.261252 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6604 13:38:57.264203 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6605 13:38:57.267475 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6606 13:38:57.274277 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6607 13:38:57.277667 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6608 13:38:57.280772 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6609 13:38:57.284566 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6610 13:38:57.290887 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6611 13:38:57.294338 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6612 13:38:57.297559 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6613 13:38:57.304343 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6614 13:38:57.304424 ==
6615 13:38:57.307705 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 13:38:57.310958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 13:38:57.311040 ==
6618 13:38:57.311103 DQS Delay:
6619 13:38:57.314358 DQS0 = 28, DQS1 = 44
6620 13:38:57.314438 DQM Delay:
6621 13:38:57.317842 DQM0 = 10, DQM1 = 15
6622 13:38:57.317922 DQ Delay:
6623 13:38:57.320934 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6624 13:38:57.324020 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6625 13:38:57.327432 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6626 13:38:57.330873 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6627 13:38:57.330954
6628 13:38:57.331018
6629 13:38:57.337706 [DQSOSCAuto] RK1, (LSB)MR18= 0xc073, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6630 13:38:57.341159 CH0 RK1: MR19=C0C, MR18=C073
6631 13:38:57.347606 CH0_RK1: MR19=0xC0C, MR18=0xC073, DQSOSC=386, MR23=63, INC=396, DEC=264
6632 13:38:57.351088 [RxdqsGatingPostProcess] freq 400
6633 13:38:57.354410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 13:38:57.357860 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 13:38:57.361209 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 13:38:57.364212 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 13:38:57.367596 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 13:38:57.370937 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 13:38:57.374430 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 13:38:57.377588 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 13:38:57.380947 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 13:38:57.384579 Pre-setting of DQS Precalculation
6643 13:38:57.387767 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 13:38:57.387854 ==
6645 13:38:57.391119 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 13:38:57.397968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 13:38:57.398070 ==
6648 13:38:57.401013 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 13:38:57.407568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6650 13:38:57.411088 [CA 0] Center 36 (8~64) winsize 57
6651 13:38:57.414832 [CA 1] Center 36 (8~64) winsize 57
6652 13:38:57.417563 [CA 2] Center 36 (8~64) winsize 57
6653 13:38:57.420928 [CA 3] Center 36 (8~64) winsize 57
6654 13:38:57.424466 [CA 4] Center 36 (8~64) winsize 57
6655 13:38:57.427635 [CA 5] Center 36 (8~64) winsize 57
6656 13:38:57.427823
6657 13:38:57.430943 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6658 13:38:57.431195
6659 13:38:57.434236 [CATrainingPosCal] consider 1 rank data
6660 13:38:57.437666 u2DelayCellTimex100 = 270/100 ps
6661 13:38:57.441103 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 13:38:57.444910 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 13:38:57.448284 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 13:38:57.451223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 13:38:57.454569 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 13:38:57.458050 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 13:38:57.461427
6668 13:38:57.464784 CA PerBit enable=1, Macro0, CA PI delay=36
6669 13:38:57.465213
6670 13:38:57.467981 [CBTSetCACLKResult] CA Dly = 36
6671 13:38:57.468486 CS Dly: 1 (0~32)
6672 13:38:57.468916 ==
6673 13:38:57.471610 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 13:38:57.474429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 13:38:57.474846 ==
6676 13:38:57.481340 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 13:38:57.487993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6678 13:38:57.491346 [CA 0] Center 36 (8~64) winsize 57
6679 13:38:57.494659 [CA 1] Center 36 (8~64) winsize 57
6680 13:38:57.498048 [CA 2] Center 36 (8~64) winsize 57
6681 13:38:57.501387 [CA 3] Center 36 (8~64) winsize 57
6682 13:38:57.501854 [CA 4] Center 36 (8~64) winsize 57
6683 13:38:57.504582 [CA 5] Center 36 (8~64) winsize 57
6684 13:38:57.504837
6685 13:38:57.511081 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6686 13:38:57.511162
6687 13:38:57.514313 [CATrainingPosCal] consider 2 rank data
6688 13:38:57.517589 u2DelayCellTimex100 = 270/100 ps
6689 13:38:57.521160 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 13:38:57.524576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 13:38:57.527851 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 13:38:57.531177 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 13:38:57.534529 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 13:38:57.537492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 13:38:57.537602
6696 13:38:57.541161 CA PerBit enable=1, Macro0, CA PI delay=36
6697 13:38:57.541292
6698 13:38:57.544484 [CBTSetCACLKResult] CA Dly = 36
6699 13:38:57.547879 CS Dly: 1 (0~32)
6700 13:38:57.548015
6701 13:38:57.551176 ----->DramcWriteLeveling(PI) begin...
6702 13:38:57.551312 ==
6703 13:38:57.554142 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 13:38:57.557476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 13:38:57.557617 ==
6706 13:38:57.560944 Write leveling (Byte 0): 40 => 8
6707 13:38:57.564467 Write leveling (Byte 1): 32 => 0
6708 13:38:57.567884 DramcWriteLeveling(PI) end<-----
6709 13:38:57.568027
6710 13:38:57.568132 ==
6711 13:38:57.571158 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 13:38:57.574667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 13:38:57.574773 ==
6714 13:38:57.577491 [Gating] SW mode calibration
6715 13:38:57.584392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 13:38:57.591175 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 13:38:57.594057 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 13:38:57.597343 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 13:38:57.604090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 13:38:57.607509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 13:38:57.610831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 13:38:57.617605 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 13:38:57.620953 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 13:38:57.624247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 13:38:57.630908 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 13:38:57.631000 Total UI for P1: 0, mck2ui 16
6727 13:38:57.637612 best dqsien dly found for B0: ( 0, 14, 24)
6728 13:38:57.637700 Total UI for P1: 0, mck2ui 16
6729 13:38:57.643816 best dqsien dly found for B1: ( 0, 14, 24)
6730 13:38:57.647289 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 13:38:57.650612 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 13:38:57.650699
6733 13:38:57.653968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 13:38:57.657469 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 13:38:57.660719 [Gating] SW calibration Done
6736 13:38:57.660807 ==
6737 13:38:57.664079 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 13:38:57.667441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 13:38:57.667529 ==
6740 13:38:57.670842 RX Vref Scan: 0
6741 13:38:57.670926
6742 13:38:57.670990 RX Vref 0 -> 0, step: 1
6743 13:38:57.671049
6744 13:38:57.674133 RX Delay -410 -> 252, step: 16
6745 13:38:57.680850 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6746 13:38:57.683743 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6747 13:38:57.687132 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6748 13:38:57.690491 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6749 13:38:57.697322 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6750 13:38:57.700593 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6751 13:38:57.703946 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6752 13:38:57.707309 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6753 13:38:57.713741 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6754 13:38:57.717103 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6755 13:38:57.720368 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6756 13:38:57.723759 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6757 13:38:57.730262 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6758 13:38:57.733693 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6759 13:38:57.736983 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6760 13:38:57.740720 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6761 13:38:57.740802 ==
6762 13:38:57.743599 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 13:38:57.750695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 13:38:57.750785 ==
6765 13:38:57.750850 DQS Delay:
6766 13:38:57.753901 DQS0 = 27, DQS1 = 43
6767 13:38:57.753983 DQM Delay:
6768 13:38:57.754048 DQM0 = 6, DQM1 = 17
6769 13:38:57.757409 DQ Delay:
6770 13:38:57.760813 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6771 13:38:57.760894 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6772 13:38:57.764106 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6773 13:38:57.766996 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6774 13:38:57.767078
6775 13:38:57.770907
6776 13:38:57.770987 ==
6777 13:38:57.773723 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 13:38:57.777290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 13:38:57.777409 ==
6780 13:38:57.777473
6781 13:38:57.777531
6782 13:38:57.780692 TX Vref Scan disable
6783 13:38:57.780772 == TX Byte 0 ==
6784 13:38:57.784133 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 13:38:57.790799 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 13:38:57.790896 == TX Byte 1 ==
6787 13:38:57.793676 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6788 13:38:57.800501 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6789 13:38:57.800583 ==
6790 13:38:57.804048 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 13:38:57.807379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 13:38:57.807547 ==
6793 13:38:57.807622
6794 13:38:57.807686
6795 13:38:57.810838 TX Vref Scan disable
6796 13:38:57.810935 == TX Byte 0 ==
6797 13:38:57.814006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 13:38:57.820493 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 13:38:57.820621 == TX Byte 1 ==
6800 13:38:57.823950 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6801 13:38:57.830639 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6802 13:38:57.830776
6803 13:38:57.830884 [DATLAT]
6804 13:38:57.833981 Freq=400, CH1 RK0
6805 13:38:57.834135
6806 13:38:57.834256 DATLAT Default: 0xf
6807 13:38:57.837314 0, 0xFFFF, sum = 0
6808 13:38:57.837470 1, 0xFFFF, sum = 0
6809 13:38:57.840440 2, 0xFFFF, sum = 0
6810 13:38:57.840616 3, 0xFFFF, sum = 0
6811 13:38:57.844011 4, 0xFFFF, sum = 0
6812 13:38:57.844308 5, 0xFFFF, sum = 0
6813 13:38:57.847078 6, 0xFFFF, sum = 0
6814 13:38:57.847292 7, 0xFFFF, sum = 0
6815 13:38:57.850448 8, 0xFFFF, sum = 0
6816 13:38:57.850695 9, 0xFFFF, sum = 0
6817 13:38:57.854197 10, 0xFFFF, sum = 0
6818 13:38:57.854503 11, 0xFFFF, sum = 0
6819 13:38:57.857090 12, 0xFFFF, sum = 0
6820 13:38:57.857414 13, 0x0, sum = 1
6821 13:38:57.860584 14, 0x0, sum = 2
6822 13:38:57.860978 15, 0x0, sum = 3
6823 13:38:57.863981 16, 0x0, sum = 4
6824 13:38:57.864410 best_step = 14
6825 13:38:57.864796
6826 13:38:57.865111 ==
6827 13:38:57.867351 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 13:38:57.874101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 13:38:57.874532 ==
6830 13:38:57.874872 RX Vref Scan: 1
6831 13:38:57.875186
6832 13:38:57.877130 RX Vref 0 -> 0, step: 1
6833 13:38:57.877586
6834 13:38:57.880686 RX Delay -327 -> 252, step: 8
6835 13:38:57.881126
6836 13:38:57.884011 Set Vref, RX VrefLevel [Byte0]: 51
6837 13:38:57.887351 [Byte1]: 50
6838 13:38:57.887775
6839 13:38:57.890824 Final RX Vref Byte 0 = 51 to rank0
6840 13:38:57.894213 Final RX Vref Byte 1 = 50 to rank0
6841 13:38:57.897067 Final RX Vref Byte 0 = 51 to rank1
6842 13:38:57.900402 Final RX Vref Byte 1 = 50 to rank1==
6843 13:38:57.903783 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 13:38:57.907096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 13:38:57.910351 ==
6846 13:38:57.910821 DQS Delay:
6847 13:38:57.911357 DQS0 = 32, DQS1 = 40
6848 13:38:57.913719 DQM Delay:
6849 13:38:57.914145 DQM0 = 10, DQM1 = 13
6850 13:38:57.916993 DQ Delay:
6851 13:38:57.917478 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6852 13:38:57.920282 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6853 13:38:57.924142 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =8
6854 13:38:57.927327 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6855 13:38:57.927952
6856 13:38:57.928310
6857 13:38:57.936921 [DQSOSCAuto] RK0, (LSB)MR18= 0x9dd8, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6858 13:38:57.940310 CH1 RK0: MR19=C0C, MR18=9DD8
6859 13:38:57.943773 CH1_RK0: MR19=0xC0C, MR18=0x9DD8, DQSOSC=383, MR23=63, INC=402, DEC=268
6860 13:38:57.946878 ==
6861 13:38:57.950009 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 13:38:57.953906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 13:38:57.954332 ==
6864 13:38:57.956789 [Gating] SW mode calibration
6865 13:38:57.963751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 13:38:57.966655 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 13:38:57.973623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 13:38:57.977100 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 13:38:57.979991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 13:38:57.986764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 13:38:57.990111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 13:38:57.993521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 13:38:58.000248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 13:38:58.003545 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 13:38:58.006611 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 13:38:58.010058 Total UI for P1: 0, mck2ui 16
6877 13:38:58.013358 best dqsien dly found for B0: ( 0, 14, 24)
6878 13:38:58.016741 Total UI for P1: 0, mck2ui 16
6879 13:38:58.019905 best dqsien dly found for B1: ( 0, 14, 24)
6880 13:38:58.023426 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 13:38:58.026806 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 13:38:58.027390
6883 13:38:58.033143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 13:38:58.036566 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 13:38:58.036991 [Gating] SW calibration Done
6886 13:38:58.039917 ==
6887 13:38:58.043256 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 13:38:58.046958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 13:38:58.047495 ==
6890 13:38:58.047839 RX Vref Scan: 0
6891 13:38:58.048153
6892 13:38:58.050124 RX Vref 0 -> 0, step: 1
6893 13:38:58.050547
6894 13:38:58.053550 RX Delay -410 -> 252, step: 16
6895 13:38:58.057022 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6896 13:38:58.062921 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6897 13:38:58.066693 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6898 13:38:58.069665 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6899 13:38:58.073052 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6900 13:38:58.079843 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6901 13:38:58.082823 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6902 13:38:58.086453 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6903 13:38:58.089492 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6904 13:38:58.093285 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6905 13:38:58.099499 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6906 13:38:58.102883 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6907 13:38:58.106300 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6908 13:38:58.112773 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6909 13:38:58.116438 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6910 13:38:58.119834 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6911 13:38:58.120319 ==
6912 13:38:58.123019 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 13:38:58.126278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 13:38:58.129590 ==
6915 13:38:58.130030 DQS Delay:
6916 13:38:58.130366 DQS0 = 35, DQS1 = 35
6917 13:38:58.133018 DQM Delay:
6918 13:38:58.133491 DQM0 = 16, DQM1 = 13
6919 13:38:58.136191 DQ Delay:
6920 13:38:58.136747 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6921 13:38:58.139628 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6922 13:38:58.143013 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6923 13:38:58.146483 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6924 13:38:58.146904
6925 13:38:58.147252
6926 13:38:58.149290 ==
6927 13:38:58.149743 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 13:38:58.156139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 13:38:58.156688 ==
6930 13:38:58.157032
6931 13:38:58.157444
6932 13:38:58.159785 TX Vref Scan disable
6933 13:38:58.160224 == TX Byte 0 ==
6934 13:38:58.163002 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6935 13:38:58.166389 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6936 13:38:58.169252 == TX Byte 1 ==
6937 13:38:58.172618 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6938 13:38:58.176022 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6939 13:38:58.179289 ==
6940 13:38:58.182674 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 13:38:58.186171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 13:38:58.186771 ==
6943 13:38:58.187287
6944 13:38:58.187797
6945 13:38:58.189271 TX Vref Scan disable
6946 13:38:58.189751 == TX Byte 0 ==
6947 13:38:58.192458 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6948 13:38:58.199087 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6949 13:38:58.199531 == TX Byte 1 ==
6950 13:38:58.202509 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6951 13:38:58.209292 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6952 13:38:58.209774
6953 13:38:58.210211 [DATLAT]
6954 13:38:58.210629 Freq=400, CH1 RK1
6955 13:38:58.211038
6956 13:38:58.212814 DATLAT Default: 0xe
6957 13:38:58.213254 0, 0xFFFF, sum = 0
6958 13:38:58.215862 1, 0xFFFF, sum = 0
6959 13:38:58.216306 2, 0xFFFF, sum = 0
6960 13:38:58.219511 3, 0xFFFF, sum = 0
6961 13:38:58.222699 4, 0xFFFF, sum = 0
6962 13:38:58.223168 5, 0xFFFF, sum = 0
6963 13:38:58.225829 6, 0xFFFF, sum = 0
6964 13:38:58.226371 7, 0xFFFF, sum = 0
6965 13:38:58.229221 8, 0xFFFF, sum = 0
6966 13:38:58.229798 9, 0xFFFF, sum = 0
6967 13:38:58.232205 10, 0xFFFF, sum = 0
6968 13:38:58.232638 11, 0xFFFF, sum = 0
6969 13:38:58.235960 12, 0xFFFF, sum = 0
6970 13:38:58.236389 13, 0x0, sum = 1
6971 13:38:58.239180 14, 0x0, sum = 2
6972 13:38:58.239610 15, 0x0, sum = 3
6973 13:38:58.242352 16, 0x0, sum = 4
6974 13:38:58.242807 best_step = 14
6975 13:38:58.243189
6976 13:38:58.243504 ==
6977 13:38:58.245834 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 13:38:58.249369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 13:38:58.249794 ==
6980 13:38:58.252658 RX Vref Scan: 0
6981 13:38:58.253114
6982 13:38:58.255953 RX Vref 0 -> 0, step: 1
6983 13:38:58.256400
6984 13:38:58.256729 RX Delay -311 -> 252, step: 8
6985 13:38:58.264496 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6986 13:38:58.267633 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6987 13:38:58.271026 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6988 13:38:58.274345 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6989 13:38:58.281034 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6990 13:38:58.284499 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6991 13:38:58.287902 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6992 13:38:58.291368 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6993 13:38:58.298193 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6994 13:38:58.301047 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6995 13:38:58.304261 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6996 13:38:58.307937 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6997 13:38:58.314455 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6998 13:38:58.317815 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6999 13:38:58.321190 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7000 13:38:58.328009 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7001 13:38:58.328452 ==
7002 13:38:58.330917 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 13:38:58.334709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 13:38:58.335139 ==
7005 13:38:58.335551 DQS Delay:
7006 13:38:58.337816 DQS0 = 32, DQS1 = 36
7007 13:38:58.338288 DQM Delay:
7008 13:38:58.340841 DQM0 = 11, DQM1 = 10
7009 13:38:58.341016 DQ Delay:
7010 13:38:58.344060 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7011 13:38:58.347359 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7012 13:38:58.350708 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7013 13:38:58.354218 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7014 13:38:58.354304
7015 13:38:58.354389
7016 13:38:58.360449 [DQSOSCAuto] RK1, (LSB)MR18= 0xae57, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7017 13:38:58.363850 CH1 RK1: MR19=C0C, MR18=AE57
7018 13:38:58.370742 CH1_RK1: MR19=0xC0C, MR18=0xAE57, DQSOSC=388, MR23=63, INC=392, DEC=261
7019 13:38:58.374158 [RxdqsGatingPostProcess] freq 400
7020 13:38:58.380593 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 13:38:58.380681 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 13:38:58.384184 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 13:38:58.387436 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 13:38:58.390572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 13:38:58.393975 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 13:38:58.397478 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 13:38:58.400361 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 13:38:58.403922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 13:38:58.407173 Pre-setting of DQS Precalculation
7030 13:38:58.410823 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 13:38:58.420866 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 13:38:58.427560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 13:38:58.428003
7034 13:38:58.428443
7035 13:38:58.430879 [Calibration Summary] 800 Mbps
7036 13:38:58.431320 CH 0, Rank 0
7037 13:38:58.434230 SW Impedance : PASS
7038 13:38:58.434672 DUTY Scan : NO K
7039 13:38:58.437577 ZQ Calibration : PASS
7040 13:38:58.440774 Jitter Meter : NO K
7041 13:38:58.441213 CBT Training : PASS
7042 13:38:58.444223 Write leveling : PASS
7043 13:38:58.447566 RX DQS gating : PASS
7044 13:38:58.448006 RX DQ/DQS(RDDQC) : PASS
7045 13:38:58.450827 TX DQ/DQS : PASS
7046 13:38:58.454446 RX DATLAT : PASS
7047 13:38:58.454941 RX DQ/DQS(Engine): PASS
7048 13:38:58.457426 TX OE : NO K
7049 13:38:58.458061 All Pass.
7050 13:38:58.458627
7051 13:38:58.460453 CH 0, Rank 1
7052 13:38:58.460527 SW Impedance : PASS
7053 13:38:58.463831 DUTY Scan : NO K
7054 13:38:58.463914 ZQ Calibration : PASS
7055 13:38:58.467377 Jitter Meter : NO K
7056 13:38:58.470230 CBT Training : PASS
7057 13:38:58.470314 Write leveling : NO K
7058 13:38:58.473901 RX DQS gating : PASS
7059 13:38:58.477198 RX DQ/DQS(RDDQC) : PASS
7060 13:38:58.477400 TX DQ/DQS : PASS
7061 13:38:58.480465 RX DATLAT : PASS
7062 13:38:58.483802 RX DQ/DQS(Engine): PASS
7063 13:38:58.483877 TX OE : NO K
7064 13:38:58.487213 All Pass.
7065 13:38:58.487288
7066 13:38:58.487350 CH 1, Rank 0
7067 13:38:58.490636 SW Impedance : PASS
7068 13:38:58.490708 DUTY Scan : NO K
7069 13:38:58.493643 ZQ Calibration : PASS
7070 13:38:58.496888 Jitter Meter : NO K
7071 13:38:58.496960 CBT Training : PASS
7072 13:38:58.500344 Write leveling : PASS
7073 13:38:58.503811 RX DQS gating : PASS
7074 13:38:58.503896 RX DQ/DQS(RDDQC) : PASS
7075 13:38:58.507224 TX DQ/DQS : PASS
7076 13:38:58.507321 RX DATLAT : PASS
7077 13:38:58.510802 RX DQ/DQS(Engine): PASS
7078 13:38:58.514082 TX OE : NO K
7079 13:38:58.514258 All Pass.
7080 13:38:58.514372
7081 13:38:58.514482 CH 1, Rank 1
7082 13:38:58.517582 SW Impedance : PASS
7083 13:38:58.520389 DUTY Scan : NO K
7084 13:38:58.520584 ZQ Calibration : PASS
7085 13:38:58.523773 Jitter Meter : NO K
7086 13:38:58.527194 CBT Training : PASS
7087 13:38:58.527423 Write leveling : NO K
7088 13:38:58.530566 RX DQS gating : PASS
7089 13:38:58.533813 RX DQ/DQS(RDDQC) : PASS
7090 13:38:58.533915 TX DQ/DQS : PASS
7091 13:38:58.537221 RX DATLAT : PASS
7092 13:38:58.540076 RX DQ/DQS(Engine): PASS
7093 13:38:58.540150 TX OE : NO K
7094 13:38:58.543843 All Pass.
7095 13:38:58.543919
7096 13:38:58.543997 DramC Write-DBI off
7097 13:38:58.546965 PER_BANK_REFRESH: Hybrid Mode
7098 13:38:58.547054 TX_TRACKING: ON
7099 13:38:58.557034 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 13:38:58.560449 [FAST_K] Save calibration result to emmc
7101 13:38:58.563827 dramc_set_vcore_voltage set vcore to 725000
7102 13:38:58.566802 Read voltage for 1600, 0
7103 13:38:58.566873 Vio18 = 0
7104 13:38:58.570256 Vcore = 725000
7105 13:38:58.570345 Vdram = 0
7106 13:38:58.570411 Vddq = 0
7107 13:38:58.570488 Vmddr = 0
7108 13:38:58.577060 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 13:38:58.583634 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 13:38:58.583720 MEM_TYPE=3, freq_sel=13
7111 13:38:58.586916 sv_algorithm_assistance_LP4_3733
7112 13:38:58.590425 ============ PULL DRAM RESETB DOWN ============
7113 13:38:58.596930 ========== PULL DRAM RESETB DOWN end =========
7114 13:38:58.600535 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 13:38:58.603558 ===================================
7116 13:38:58.607034 LPDDR4 DRAM CONFIGURATION
7117 13:38:58.610439 ===================================
7118 13:38:58.610564 EX_ROW_EN[0] = 0x0
7119 13:38:58.613522 EX_ROW_EN[1] = 0x0
7120 13:38:58.616657 LP4Y_EN = 0x0
7121 13:38:58.616824 WORK_FSP = 0x1
7122 13:38:58.620113 WL = 0x5
7123 13:38:58.620267 RL = 0x5
7124 13:38:58.623587 BL = 0x2
7125 13:38:58.623773 RPST = 0x0
7126 13:38:58.627008 RD_PRE = 0x0
7127 13:38:58.627163 WR_PRE = 0x1
7128 13:38:58.630392 WR_PST = 0x1
7129 13:38:58.630601 DBI_WR = 0x0
7130 13:38:58.633249 DBI_RD = 0x0
7131 13:38:58.633363 OTF = 0x1
7132 13:38:58.636673 ===================================
7133 13:38:58.639996 ===================================
7134 13:38:58.643346 ANA top config
7135 13:38:58.646823 ===================================
7136 13:38:58.646898 DLL_ASYNC_EN = 0
7137 13:38:58.649696 ALL_SLAVE_EN = 0
7138 13:38:58.653458 NEW_RANK_MODE = 1
7139 13:38:58.656667 DLL_IDLE_MODE = 1
7140 13:38:58.660040 LP45_APHY_COMB_EN = 1
7141 13:38:58.660125 TX_ODT_DIS = 0
7142 13:38:58.663475 NEW_8X_MODE = 1
7143 13:38:58.666971 ===================================
7144 13:38:58.669926 ===================================
7145 13:38:58.673401 data_rate = 3200
7146 13:38:58.676763 CKR = 1
7147 13:38:58.679681 DQ_P2S_RATIO = 8
7148 13:38:58.683416 ===================================
7149 13:38:58.683520 CA_P2S_RATIO = 8
7150 13:38:58.686618 DQ_CA_OPEN = 0
7151 13:38:58.690061 DQ_SEMI_OPEN = 0
7152 13:38:58.693251 CA_SEMI_OPEN = 0
7153 13:38:58.696365 CA_FULL_RATE = 0
7154 13:38:58.700010 DQ_CKDIV4_EN = 0
7155 13:38:58.700163 CA_CKDIV4_EN = 0
7156 13:38:58.703311 CA_PREDIV_EN = 0
7157 13:38:58.706240 PH8_DLY = 12
7158 13:38:58.709592 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 13:38:58.712890 DQ_AAMCK_DIV = 4
7160 13:38:58.716292 CA_AAMCK_DIV = 4
7161 13:38:58.716370 CA_ADMCK_DIV = 4
7162 13:38:58.719470 DQ_TRACK_CA_EN = 0
7163 13:38:58.722878 CA_PICK = 1600
7164 13:38:58.726413 CA_MCKIO = 1600
7165 13:38:58.729430 MCKIO_SEMI = 0
7166 13:38:58.732993 PLL_FREQ = 3068
7167 13:38:58.736307 DQ_UI_PI_RATIO = 32
7168 13:38:58.736382 CA_UI_PI_RATIO = 0
7169 13:38:58.739658 ===================================
7170 13:38:58.743069 ===================================
7171 13:38:58.746380 memory_type:LPDDR4
7172 13:38:58.749516 GP_NUM : 10
7173 13:38:58.749609 SRAM_EN : 1
7174 13:38:58.752745 MD32_EN : 0
7175 13:38:58.756410 ===================================
7176 13:38:58.759638 [ANA_INIT] >>>>>>>>>>>>>>
7177 13:38:58.762790 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 13:38:58.765986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 13:38:58.769455 ===================================
7180 13:38:58.769624 data_rate = 3200,PCW = 0X7600
7181 13:38:58.773036 ===================================
7182 13:38:58.776338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 13:38:58.783029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 13:38:58.789649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 13:38:58.792923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 13:38:58.796233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 13:38:58.799783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 13:38:58.803085 [ANA_INIT] flow start
7189 13:38:58.803495 [ANA_INIT] PLL >>>>>>>>
7190 13:38:58.806491 [ANA_INIT] PLL <<<<<<<<
7191 13:38:58.809849 [ANA_INIT] MIDPI >>>>>>>>
7192 13:38:58.813152 [ANA_INIT] MIDPI <<<<<<<<
7193 13:38:58.813538 [ANA_INIT] DLL >>>>>>>>
7194 13:38:58.816508 [ANA_INIT] DLL <<<<<<<<
7195 13:38:58.819955 [ANA_INIT] flow end
7196 13:38:58.823200 ============ LP4 DIFF to SE enter ============
7197 13:38:58.826205 ============ LP4 DIFF to SE exit ============
7198 13:38:58.829537 [ANA_INIT] <<<<<<<<<<<<<
7199 13:38:58.832976 [Flow] Enable top DCM control >>>>>
7200 13:38:58.835974 [Flow] Enable top DCM control <<<<<
7201 13:38:58.839387 Enable DLL master slave shuffle
7202 13:38:58.842722 ==============================================================
7203 13:38:58.846034 Gating Mode config
7204 13:38:58.849370 ==============================================================
7205 13:38:58.852586 Config description:
7206 13:38:58.862527 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 13:38:58.869488 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 13:38:58.872676 SELPH_MODE 0: By rank 1: By Phase
7209 13:38:58.879492 ==============================================================
7210 13:38:58.882864 GAT_TRACK_EN = 1
7211 13:38:58.885830 RX_GATING_MODE = 2
7212 13:38:58.889430 RX_GATING_TRACK_MODE = 2
7213 13:38:58.892530 SELPH_MODE = 1
7214 13:38:58.895742 PICG_EARLY_EN = 1
7215 13:38:58.895836 VALID_LAT_VALUE = 1
7216 13:38:58.902889 ==============================================================
7217 13:38:58.906127 Enter into Gating configuration >>>>
7218 13:38:58.909018 Exit from Gating configuration <<<<
7219 13:38:58.912350 Enter into DVFS_PRE_config >>>>>
7220 13:38:58.922608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 13:38:58.925931 Exit from DVFS_PRE_config <<<<<
7222 13:38:58.929188 Enter into PICG configuration >>>>
7223 13:38:58.932516 Exit from PICG configuration <<<<
7224 13:38:58.935971 [RX_INPUT] configuration >>>>>
7225 13:38:58.939302 [RX_INPUT] configuration <<<<<
7226 13:38:58.942415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 13:38:58.948812 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 13:38:58.955964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 13:38:58.962343 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 13:38:58.969092 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 13:38:58.975971 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 13:38:58.979094 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 13:38:58.982348 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 13:38:58.985652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 13:38:58.989058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 13:38:58.995746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 13:38:58.999194 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 13:38:59.002349 ===================================
7239 13:38:59.005701 LPDDR4 DRAM CONFIGURATION
7240 13:38:59.009089 ===================================
7241 13:38:59.009191 EX_ROW_EN[0] = 0x0
7242 13:38:59.012438 EX_ROW_EN[1] = 0x0
7243 13:38:59.012527 LP4Y_EN = 0x0
7244 13:38:59.015941 WORK_FSP = 0x1
7245 13:38:59.016027 WL = 0x5
7246 13:38:59.018943 RL = 0x5
7247 13:38:59.019027 BL = 0x2
7248 13:38:59.022446 RPST = 0x0
7249 13:38:59.022537 RD_PRE = 0x0
7250 13:38:59.025705 WR_PRE = 0x1
7251 13:38:59.025818 WR_PST = 0x1
7252 13:38:59.029175 DBI_WR = 0x0
7253 13:38:59.032078 DBI_RD = 0x0
7254 13:38:59.032188 OTF = 0x1
7255 13:38:59.035514 ===================================
7256 13:38:59.038899 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 13:38:59.042309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 13:38:59.049170 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 13:38:59.052481 ===================================
7260 13:38:59.052617 LPDDR4 DRAM CONFIGURATION
7261 13:38:59.055817 ===================================
7262 13:38:59.059234 EX_ROW_EN[0] = 0x10
7263 13:38:59.062635 EX_ROW_EN[1] = 0x0
7264 13:38:59.062776 LP4Y_EN = 0x0
7265 13:38:59.065998 WORK_FSP = 0x1
7266 13:38:59.066111 WL = 0x5
7267 13:38:59.069006 RL = 0x5
7268 13:38:59.069123 BL = 0x2
7269 13:38:59.072357 RPST = 0x0
7270 13:38:59.072476 RD_PRE = 0x0
7271 13:38:59.075788 WR_PRE = 0x1
7272 13:38:59.075915 WR_PST = 0x1
7273 13:38:59.079391 DBI_WR = 0x0
7274 13:38:59.079525 DBI_RD = 0x0
7275 13:38:59.082681 OTF = 0x1
7276 13:38:59.085735 ===================================
7277 13:38:59.092395 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 13:38:59.092510 ==
7279 13:38:59.095757 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 13:38:59.099182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 13:38:59.099300 ==
7282 13:38:59.102138 [Duty_Offset_Calibration]
7283 13:38:59.102217 B0:2 B1:0 CA:1
7284 13:38:59.102281
7285 13:38:59.105456 [DutyScan_Calibration_Flow] k_type=0
7286 13:38:59.116436
7287 13:38:59.116552 ==CLK 0==
7288 13:38:59.119903 Final CLK duty delay cell = 0
7289 13:38:59.122762 [0] MAX Duty = 5187%(X100), DQS PI = 20
7290 13:38:59.126165 [0] MIN Duty = 5000%(X100), DQS PI = 62
7291 13:38:59.126249 [0] AVG Duty = 5093%(X100)
7292 13:38:59.129630
7293 13:38:59.133035 CH0 CLK Duty spec in!! Max-Min= 187%
7294 13:38:59.136397 [DutyScan_Calibration_Flow] ====Done====
7295 13:38:59.136475
7296 13:38:59.139754 [DutyScan_Calibration_Flow] k_type=1
7297 13:38:59.155475
7298 13:38:59.155607 ==DQS 0 ==
7299 13:38:59.158699 Final DQS duty delay cell = 0
7300 13:38:59.162331 [0] MAX Duty = 5218%(X100), DQS PI = 32
7301 13:38:59.165703 [0] MIN Duty = 4938%(X100), DQS PI = 60
7302 13:38:59.168730 [0] AVG Duty = 5078%(X100)
7303 13:38:59.168835
7304 13:38:59.168914 ==DQS 1 ==
7305 13:38:59.172438 Final DQS duty delay cell = -4
7306 13:38:59.175433 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7307 13:38:59.178840 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7308 13:38:59.182270 [-4] AVG Duty = 4969%(X100)
7309 13:38:59.182376
7310 13:38:59.185284 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7311 13:38:59.185393
7312 13:38:59.188907 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7313 13:38:59.192285 [DutyScan_Calibration_Flow] ====Done====
7314 13:38:59.192388
7315 13:38:59.195342 [DutyScan_Calibration_Flow] k_type=3
7316 13:38:59.212897
7317 13:38:59.213056 ==DQM 0 ==
7318 13:38:59.216254 Final DQM duty delay cell = 0
7319 13:38:59.219607 [0] MAX Duty = 5062%(X100), DQS PI = 10
7320 13:38:59.223039 [0] MIN Duty = 4813%(X100), DQS PI = 50
7321 13:38:59.226416 [0] AVG Duty = 4937%(X100)
7322 13:38:59.226515
7323 13:38:59.226599 ==DQM 1 ==
7324 13:38:59.229810 Final DQM duty delay cell = 0
7325 13:38:59.232715 [0] MAX Duty = 5249%(X100), DQS PI = 30
7326 13:38:59.236311 [0] MIN Duty = 5000%(X100), DQS PI = 20
7327 13:38:59.239313 [0] AVG Duty = 5124%(X100)
7328 13:38:59.239401
7329 13:38:59.243036 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7330 13:38:59.243140
7331 13:38:59.246457 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7332 13:38:59.249834 [DutyScan_Calibration_Flow] ====Done====
7333 13:38:59.249936
7334 13:38:59.252773 [DutyScan_Calibration_Flow] k_type=2
7335 13:38:59.270019
7336 13:38:59.270150 ==DQ 0 ==
7337 13:38:59.273520 Final DQ duty delay cell = 0
7338 13:38:59.276822 [0] MAX Duty = 5124%(X100), DQS PI = 34
7339 13:38:59.279834 [0] MIN Duty = 5000%(X100), DQS PI = 0
7340 13:38:59.279986 [0] AVG Duty = 5062%(X100)
7341 13:38:59.283251
7342 13:38:59.283364 ==DQ 1 ==
7343 13:38:59.286524 Final DQ duty delay cell = 0
7344 13:38:59.289891 [0] MAX Duty = 4969%(X100), DQS PI = 44
7345 13:38:59.293459 [0] MIN Duty = 4875%(X100), DQS PI = 10
7346 13:38:59.293542 [0] AVG Duty = 4922%(X100)
7347 13:38:59.293608
7348 13:38:59.296919 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7349 13:38:59.300136
7350 13:38:59.300232 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7351 13:38:59.306721 [DutyScan_Calibration_Flow] ====Done====
7352 13:38:59.306821 ==
7353 13:38:59.310132 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 13:38:59.313421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 13:38:59.313517 ==
7356 13:38:59.317102 [Duty_Offset_Calibration]
7357 13:38:59.317195 B0:0 B1:-1 CA:2
7358 13:38:59.317264
7359 13:38:59.320138 [DutyScan_Calibration_Flow] k_type=0
7360 13:38:59.330251
7361 13:38:59.330380 ==CLK 0==
7362 13:38:59.333702 Final CLK duty delay cell = 0
7363 13:38:59.336945 [0] MAX Duty = 5156%(X100), DQS PI = 10
7364 13:38:59.340392 [0] MIN Duty = 4906%(X100), DQS PI = 46
7365 13:38:59.340484 [0] AVG Duty = 5031%(X100)
7366 13:38:59.343845
7367 13:38:59.347209 CH1 CLK Duty spec in!! Max-Min= 250%
7368 13:38:59.350502 [DutyScan_Calibration_Flow] ====Done====
7369 13:38:59.350628
7370 13:38:59.353392 [DutyScan_Calibration_Flow] k_type=1
7371 13:38:59.369883
7372 13:38:59.370046 ==DQS 0 ==
7373 13:38:59.373318 Final DQS duty delay cell = 0
7374 13:38:59.376772 [0] MAX Duty = 5093%(X100), DQS PI = 26
7375 13:38:59.379769 [0] MIN Duty = 4969%(X100), DQS PI = 2
7376 13:38:59.379860 [0] AVG Duty = 5031%(X100)
7377 13:38:59.383190
7378 13:38:59.383304 ==DQS 1 ==
7379 13:38:59.386514 Final DQS duty delay cell = 0
7380 13:38:59.389878 [0] MAX Duty = 5187%(X100), DQS PI = 2
7381 13:38:59.393284 [0] MIN Duty = 4844%(X100), DQS PI = 32
7382 13:38:59.393412 [0] AVG Duty = 5015%(X100)
7383 13:38:59.396404
7384 13:38:59.400069 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7385 13:38:59.400192
7386 13:38:59.403232 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7387 13:38:59.406839 [DutyScan_Calibration_Flow] ====Done====
7388 13:38:59.406962
7389 13:38:59.409865 [DutyScan_Calibration_Flow] k_type=3
7390 13:38:59.427508
7391 13:38:59.427682 ==DQM 0 ==
7392 13:38:59.430864 Final DQM duty delay cell = 4
7393 13:38:59.434325 [4] MAX Duty = 5125%(X100), DQS PI = 22
7394 13:38:59.437698 [4] MIN Duty = 4938%(X100), DQS PI = 46
7395 13:38:59.440695 [4] AVG Duty = 5031%(X100)
7396 13:38:59.440817
7397 13:38:59.440915 ==DQM 1 ==
7398 13:38:59.444076 Final DQM duty delay cell = 0
7399 13:38:59.447594 [0] MAX Duty = 5281%(X100), DQS PI = 58
7400 13:38:59.450915 [0] MIN Duty = 4876%(X100), DQS PI = 34
7401 13:38:59.454237 [0] AVG Duty = 5078%(X100)
7402 13:38:59.454373
7403 13:38:59.457654 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7404 13:38:59.457772
7405 13:38:59.460604 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7406 13:38:59.464020 [DutyScan_Calibration_Flow] ====Done====
7407 13:38:59.464137
7408 13:38:59.467390 [DutyScan_Calibration_Flow] k_type=2
7409 13:38:59.484351
7410 13:38:59.484524 ==DQ 0 ==
7411 13:38:59.487735 Final DQ duty delay cell = 0
7412 13:38:59.491352 [0] MAX Duty = 5062%(X100), DQS PI = 18
7413 13:38:59.494625 [0] MIN Duty = 4969%(X100), DQS PI = 0
7414 13:38:59.494743 [0] AVG Duty = 5015%(X100)
7415 13:38:59.497499
7416 13:38:59.497613 ==DQ 1 ==
7417 13:38:59.500951 Final DQ duty delay cell = 0
7418 13:38:59.504566 [0] MAX Duty = 5062%(X100), DQS PI = 0
7419 13:38:59.507823 [0] MIN Duty = 4813%(X100), DQS PI = 32
7420 13:38:59.507941 [0] AVG Duty = 4937%(X100)
7421 13:38:59.508046
7422 13:38:59.511023 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7423 13:38:59.511138
7424 13:38:59.514441 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7425 13:38:59.520869 [DutyScan_Calibration_Flow] ====Done====
7426 13:38:59.524248 nWR fixed to 30
7427 13:38:59.524373 [ModeRegInit_LP4] CH0 RK0
7428 13:38:59.527529 [ModeRegInit_LP4] CH0 RK1
7429 13:38:59.530999 [ModeRegInit_LP4] CH1 RK0
7430 13:38:59.531116 [ModeRegInit_LP4] CH1 RK1
7431 13:38:59.534306 match AC timing 5
7432 13:38:59.537707 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 13:38:59.541189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 13:38:59.547625 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 13:38:59.551009 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 13:38:59.557575 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 13:38:59.557716 [MiockJmeterHQA]
7438 13:38:59.557818
7439 13:38:59.560957 [DramcMiockJmeter] u1RxGatingPI = 0
7440 13:38:59.564413 0 : 4255, 4026
7441 13:38:59.564532 4 : 4255, 4027
7442 13:38:59.564637 8 : 4257, 4029
7443 13:38:59.567776 12 : 4253, 4026
7444 13:38:59.567890 16 : 4253, 4026
7445 13:38:59.571310 20 : 4363, 4137
7446 13:38:59.571434 24 : 4252, 4027
7447 13:38:59.574707 28 : 4253, 4026
7448 13:38:59.574836 32 : 4253, 4027
7449 13:38:59.574940 36 : 4254, 4029
7450 13:38:59.577602 40 : 4255, 4029
7451 13:38:59.577717 44 : 4363, 4138
7452 13:38:59.581065 48 : 4363, 4137
7453 13:38:59.581181 52 : 4366, 4140
7454 13:38:59.584414 56 : 4254, 4029
7455 13:38:59.584540 60 : 4255, 4029
7456 13:38:59.584641 64 : 4252, 4027
7457 13:38:59.587779 68 : 4255, 4029
7458 13:38:59.587894 72 : 4360, 4138
7459 13:38:59.591288 76 : 4250, 4027
7460 13:38:59.591404 80 : 4250, 4027
7461 13:38:59.594236 84 : 4250, 4027
7462 13:38:59.594361 88 : 4253, 3770
7463 13:38:59.594461 92 : 4253, 0
7464 13:38:59.597693 96 : 4363, 0
7465 13:38:59.597810 100 : 4252, 0
7466 13:38:59.601520 104 : 4250, 0
7467 13:38:59.601638 108 : 4361, 0
7468 13:38:59.601738 112 : 4250, 0
7469 13:38:59.604480 116 : 4361, 0
7470 13:38:59.604593 120 : 4360, 0
7471 13:38:59.607810 124 : 4250, 0
7472 13:38:59.607923 128 : 4255, 0
7473 13:38:59.608024 132 : 4250, 0
7474 13:38:59.610980 136 : 4250, 0
7475 13:38:59.611095 140 : 4252, 0
7476 13:38:59.614444 144 : 4250, 0
7477 13:38:59.614559 148 : 4250, 0
7478 13:38:59.614660 152 : 4253, 0
7479 13:38:59.617604 156 : 4250, 0
7480 13:38:59.617716 160 : 4250, 0
7481 13:38:59.617820 164 : 4253, 0
7482 13:38:59.621148 168 : 4360, 0
7483 13:38:59.621261 172 : 4252, 0
7484 13:38:59.624344 176 : 4363, 0
7485 13:38:59.624461 180 : 4252, 0
7486 13:38:59.624559 184 : 4250, 0
7487 13:38:59.627566 188 : 4361, 0
7488 13:38:59.627686 192 : 4255, 0
7489 13:38:59.630755 196 : 4250, 0
7490 13:38:59.630870 200 : 4250, 1
7491 13:38:59.630974 204 : 4253, 2337
7492 13:38:59.634226 208 : 4250, 4027
7493 13:38:59.634342 212 : 4360, 4138
7494 13:38:59.637566 216 : 4360, 4138
7495 13:38:59.637679 220 : 4249, 4027
7496 13:38:59.641006 224 : 4250, 4027
7497 13:38:59.641120 228 : 4250, 4027
7498 13:38:59.644302 232 : 4250, 4027
7499 13:38:59.644416 236 : 4250, 4027
7500 13:38:59.647802 240 : 4363, 4140
7501 13:38:59.647916 244 : 4253, 4029
7502 13:38:59.650908 248 : 4250, 4027
7503 13:38:59.651024 252 : 4363, 4140
7504 13:38:59.651126 256 : 4249, 4027
7505 13:38:59.654334 260 : 4250, 4027
7506 13:38:59.654449 264 : 4360, 4138
7507 13:38:59.657813 268 : 4363, 4140
7508 13:38:59.657928 272 : 4249, 4027
7509 13:38:59.661067 276 : 4250, 4026
7510 13:38:59.661178 280 : 4253, 4029
7511 13:38:59.664458 284 : 4253, 4029
7512 13:38:59.664574 288 : 4250, 4027
7513 13:38:59.667749 292 : 4360, 4137
7514 13:38:59.667865 296 : 4250, 4027
7515 13:38:59.671128 300 : 4250, 4027
7516 13:38:59.671245 304 : 4363, 4140
7517 13:38:59.674492 308 : 4252, 4029
7518 13:38:59.674608 312 : 4250, 3973
7519 13:38:59.674711 316 : 4363, 1950
7520 13:38:59.674813
7521 13:38:59.677852 MIOCK jitter meter ch=0
7522 13:38:59.677962
7523 13:38:59.680748 1T = (316-92) = 224 dly cells
7524 13:38:59.687678 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7525 13:38:59.687795 ==
7526 13:38:59.690888 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 13:38:59.694284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 13:38:59.694403 ==
7529 13:38:59.700897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 13:38:59.704222 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 13:38:59.707652 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 13:38:59.714000 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 13:38:59.723226 [CA 0] Center 42 (12~73) winsize 62
7534 13:38:59.726518 [CA 1] Center 43 (13~73) winsize 61
7535 13:38:59.729560 [CA 2] Center 37 (7~67) winsize 61
7536 13:38:59.733241 [CA 3] Center 37 (7~67) winsize 61
7537 13:38:59.736550 [CA 4] Center 36 (6~66) winsize 61
7538 13:38:59.739452 [CA 5] Center 35 (5~65) winsize 61
7539 13:38:59.739574
7540 13:38:59.743312 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 13:38:59.743433
7542 13:38:59.746218 [CATrainingPosCal] consider 1 rank data
7543 13:38:59.749817 u2DelayCellTimex100 = 290/100 ps
7544 13:38:59.752890 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7545 13:38:59.759787 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7546 13:38:59.762830 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7547 13:38:59.766581 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7548 13:38:59.769883 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7549 13:38:59.772814 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7550 13:38:59.772957
7551 13:38:59.776325 CA PerBit enable=1, Macro0, CA PI delay=35
7552 13:38:59.776449
7553 13:38:59.779757 [CBTSetCACLKResult] CA Dly = 35
7554 13:38:59.779889 CS Dly: 9 (0~40)
7555 13:38:59.786570 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 13:38:59.789440 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 13:38:59.789566 ==
7558 13:38:59.792841 Dram Type= 6, Freq= 0, CH_0, rank 1
7559 13:38:59.796306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 13:38:59.799333 ==
7561 13:38:59.802688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 13:38:59.806050 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 13:38:59.812775 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 13:38:59.816173 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 13:38:59.826464 [CA 0] Center 43 (13~73) winsize 61
7566 13:38:59.829609 [CA 1] Center 43 (13~73) winsize 61
7567 13:38:59.832788 [CA 2] Center 37 (8~67) winsize 60
7568 13:38:59.836412 [CA 3] Center 38 (9~68) winsize 60
7569 13:38:59.839503 [CA 4] Center 37 (7~67) winsize 61
7570 13:38:59.843195 [CA 5] Center 36 (7~66) winsize 60
7571 13:38:59.843293
7572 13:38:59.846437 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7573 13:38:59.846526
7574 13:38:59.849816 [CATrainingPosCal] consider 2 rank data
7575 13:38:59.852837 u2DelayCellTimex100 = 290/100 ps
7576 13:38:59.856345 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7577 13:38:59.863105 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7578 13:38:59.866496 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
7579 13:38:59.869745 CA3 delay=38 (9~67),Diff = 2 PI (6 cell)
7580 13:38:59.872980 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7581 13:38:59.876448 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7582 13:38:59.876597
7583 13:38:59.879814 CA PerBit enable=1, Macro0, CA PI delay=36
7584 13:38:59.879927
7585 13:38:59.882775 [CBTSetCACLKResult] CA Dly = 36
7586 13:38:59.886108 CS Dly: 10 (0~43)
7587 13:38:59.889441 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 13:38:59.892854 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 13:38:59.892983
7590 13:38:59.896277 ----->DramcWriteLeveling(PI) begin...
7591 13:38:59.896373 ==
7592 13:38:59.899701 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 13:38:59.903070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 13:38:59.903215 ==
7595 13:38:59.906555 Write leveling (Byte 0): 35 => 35
7596 13:38:59.909937 Write leveling (Byte 1): 29 => 29
7597 13:38:59.912838 DramcWriteLeveling(PI) end<-----
7598 13:38:59.912932
7599 13:38:59.913036 ==
7600 13:38:59.916286 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 13:38:59.923093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 13:38:59.923188 ==
7603 13:38:59.923254 [Gating] SW mode calibration
7604 13:38:59.933247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7605 13:38:59.936465 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7606 13:38:59.939629 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 13:38:59.946352 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 13:38:59.949837 1 4 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7609 13:38:59.953216 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7610 13:38:59.959971 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7611 13:38:59.962787 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7612 13:38:59.966240 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 13:38:59.972954 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 13:38:59.976103 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 13:38:59.979483 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 13:38:59.986247 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7617 13:38:59.989656 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7618 13:38:59.993022 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7619 13:38:59.999477 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7620 13:39:00.003300 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 13:39:00.006278 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 13:39:00.013114 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 13:39:00.016537 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 13:39:00.019374 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7625 13:39:00.026299 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7626 13:39:00.029727 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7627 13:39:00.032732 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7628 13:39:00.036196 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 13:39:00.042704 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 13:39:00.046307 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 13:39:00.049573 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 13:39:00.056258 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 13:39:00.059391 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7634 13:39:00.062794 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7635 13:39:00.069629 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7636 13:39:00.072602 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 13:39:00.075966 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 13:39:00.082930 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 13:39:00.086018 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 13:39:00.089270 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 13:39:00.096054 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 13:39:00.099371 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 13:39:00.102812 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 13:39:00.109120 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 13:39:00.112871 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 13:39:00.115763 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 13:39:00.122666 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7648 13:39:00.126126 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 13:39:00.129486 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7650 13:39:00.132876 Total UI for P1: 0, mck2ui 16
7651 13:39:00.135841 best dqsien dly found for B0: ( 1, 9, 6)
7652 13:39:00.142738 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 13:39:00.146101 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7654 13:39:00.149391 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 13:39:00.152799 Total UI for P1: 0, mck2ui 16
7656 13:39:00.156049 best dqsien dly found for B1: ( 1, 9, 18)
7657 13:39:00.159528 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7658 13:39:00.162558 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7659 13:39:00.162650
7660 13:39:00.166197 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7661 13:39:00.172479 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7662 13:39:00.172612 [Gating] SW calibration Done
7663 13:39:00.172718 ==
7664 13:39:00.175855 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 13:39:00.182479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 13:39:00.182579 ==
7667 13:39:00.182652 RX Vref Scan: 0
7668 13:39:00.182720
7669 13:39:00.185774 RX Vref 0 -> 0, step: 1
7670 13:39:00.185880
7671 13:39:00.189179 RX Delay 0 -> 252, step: 8
7672 13:39:00.192577 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7673 13:39:00.195586 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7674 13:39:00.198958 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7675 13:39:00.202367 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7676 13:39:00.208970 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7677 13:39:00.212386 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7678 13:39:00.215675 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7679 13:39:00.219117 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7680 13:39:00.222394 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7681 13:39:00.228839 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7682 13:39:00.232301 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7683 13:39:00.235803 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7684 13:39:00.239235 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7685 13:39:00.242236 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7686 13:39:00.249146 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7687 13:39:00.252511 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7688 13:39:00.252623 ==
7689 13:39:00.255717 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 13:39:00.258895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 13:39:00.259018 ==
7692 13:39:00.262415 DQS Delay:
7693 13:39:00.262532 DQS0 = 0, DQS1 = 0
7694 13:39:00.262636 DQM Delay:
7695 13:39:00.265510 DQM0 = 138, DQM1 = 128
7696 13:39:00.265626 DQ Delay:
7697 13:39:00.268993 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7698 13:39:00.272137 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7699 13:39:00.275311 DQ8 =123, DQ9 =115, DQ10 =127, DQ11 =127
7700 13:39:00.282486 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7701 13:39:00.282625
7702 13:39:00.282733
7703 13:39:00.282831 ==
7704 13:39:00.285432 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 13:39:00.288697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 13:39:00.288816 ==
7707 13:39:00.288921
7708 13:39:00.289019
7709 13:39:00.292488 TX Vref Scan disable
7710 13:39:00.292605 == TX Byte 0 ==
7711 13:39:00.298944 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7712 13:39:00.302341 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7713 13:39:00.302458 == TX Byte 1 ==
7714 13:39:00.308695 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7715 13:39:00.312087 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7716 13:39:00.312207 ==
7717 13:39:00.315490 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 13:39:00.318778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 13:39:00.318890 ==
7720 13:39:00.332649
7721 13:39:00.336067 TX Vref early break, caculate TX vref
7722 13:39:00.339622 TX Vref=16, minBit 1, minWin=23, winSum=380
7723 13:39:00.343025 TX Vref=18, minBit 8, minWin=23, winSum=387
7724 13:39:00.345985 TX Vref=20, minBit 8, minWin=23, winSum=396
7725 13:39:00.349445 TX Vref=22, minBit 12, minWin=24, winSum=408
7726 13:39:00.352881 TX Vref=24, minBit 0, minWin=25, winSum=416
7727 13:39:00.359584 TX Vref=26, minBit 0, minWin=26, winSum=425
7728 13:39:00.362831 TX Vref=28, minBit 0, minWin=25, winSum=431
7729 13:39:00.366243 TX Vref=30, minBit 0, minWin=25, winSum=426
7730 13:39:00.369364 TX Vref=32, minBit 0, minWin=25, winSum=413
7731 13:39:00.372586 TX Vref=34, minBit 9, minWin=24, winSum=403
7732 13:39:00.379213 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
7733 13:39:00.379328
7734 13:39:00.382575 Final TX Range 0 Vref 26
7735 13:39:00.382656
7736 13:39:00.382722 ==
7737 13:39:00.386198 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 13:39:00.389466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 13:39:00.389556 ==
7740 13:39:00.389626
7741 13:39:00.389694
7742 13:39:00.392733 TX Vref Scan disable
7743 13:39:00.399439 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7744 13:39:00.399533 == TX Byte 0 ==
7745 13:39:00.402781 u2DelayCellOfst[0]=16 cells (5 PI)
7746 13:39:00.406186 u2DelayCellOfst[1]=20 cells (6 PI)
7747 13:39:00.409261 u2DelayCellOfst[2]=13 cells (4 PI)
7748 13:39:00.412624 u2DelayCellOfst[3]=13 cells (4 PI)
7749 13:39:00.416133 u2DelayCellOfst[4]=10 cells (3 PI)
7750 13:39:00.419491 u2DelayCellOfst[5]=0 cells (0 PI)
7751 13:39:00.422395 u2DelayCellOfst[6]=20 cells (6 PI)
7752 13:39:00.425712 u2DelayCellOfst[7]=20 cells (6 PI)
7753 13:39:00.429057 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7754 13:39:00.432451 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7755 13:39:00.435888 == TX Byte 1 ==
7756 13:39:00.435970 u2DelayCellOfst[8]=0 cells (0 PI)
7757 13:39:00.439391 u2DelayCellOfst[9]=0 cells (0 PI)
7758 13:39:00.442384 u2DelayCellOfst[10]=6 cells (2 PI)
7759 13:39:00.445770 u2DelayCellOfst[11]=0 cells (0 PI)
7760 13:39:00.449276 u2DelayCellOfst[12]=13 cells (4 PI)
7761 13:39:00.452210 u2DelayCellOfst[13]=10 cells (3 PI)
7762 13:39:00.455583 u2DelayCellOfst[14]=13 cells (4 PI)
7763 13:39:00.459088 u2DelayCellOfst[15]=10 cells (3 PI)
7764 13:39:00.462454 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7765 13:39:00.468954 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7766 13:39:00.469066 DramC Write-DBI on
7767 13:39:00.469168 ==
7768 13:39:00.472261 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 13:39:00.475615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 13:39:00.478822 ==
7771 13:39:00.478915
7772 13:39:00.478982
7773 13:39:00.479044 TX Vref Scan disable
7774 13:39:00.482489 == TX Byte 0 ==
7775 13:39:00.485587 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7776 13:39:00.489155 == TX Byte 1 ==
7777 13:39:00.492275 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7778 13:39:00.495751 DramC Write-DBI off
7779 13:39:00.495840
7780 13:39:00.495908 [DATLAT]
7781 13:39:00.495971 Freq=1600, CH0 RK0
7782 13:39:00.496033
7783 13:39:00.499328 DATLAT Default: 0xf
7784 13:39:00.499437 0, 0xFFFF, sum = 0
7785 13:39:00.502639 1, 0xFFFF, sum = 0
7786 13:39:00.502735 2, 0xFFFF, sum = 0
7787 13:39:00.506030 3, 0xFFFF, sum = 0
7788 13:39:00.506107 4, 0xFFFF, sum = 0
7789 13:39:00.509426 5, 0xFFFF, sum = 0
7790 13:39:00.512402 6, 0xFFFF, sum = 0
7791 13:39:00.512490 7, 0xFFFF, sum = 0
7792 13:39:00.515891 8, 0xFFFF, sum = 0
7793 13:39:00.515981 9, 0xFFFF, sum = 0
7794 13:39:00.519203 10, 0xFFFF, sum = 0
7795 13:39:00.519282 11, 0xFFFF, sum = 0
7796 13:39:00.522479 12, 0xFFFF, sum = 0
7797 13:39:00.522554 13, 0xFFFF, sum = 0
7798 13:39:00.525497 14, 0x0, sum = 1
7799 13:39:00.525574 15, 0x0, sum = 2
7800 13:39:00.528909 16, 0x0, sum = 3
7801 13:39:00.528989 17, 0x0, sum = 4
7802 13:39:00.532765 best_step = 15
7803 13:39:00.532837
7804 13:39:00.532899 ==
7805 13:39:00.535587 Dram Type= 6, Freq= 0, CH_0, rank 0
7806 13:39:00.538903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7807 13:39:00.539013 ==
7808 13:39:00.539114 RX Vref Scan: 1
7809 13:39:00.542344
7810 13:39:00.542423 Set Vref Range= 24 -> 127
7811 13:39:00.542511
7812 13:39:00.545737 RX Vref 24 -> 127, step: 1
7813 13:39:00.545843
7814 13:39:00.549119 RX Delay 19 -> 252, step: 4
7815 13:39:00.549221
7816 13:39:00.552648 Set Vref, RX VrefLevel [Byte0]: 24
7817 13:39:00.555641 [Byte1]: 24
7818 13:39:00.555748
7819 13:39:00.558950 Set Vref, RX VrefLevel [Byte0]: 25
7820 13:39:00.562309 [Byte1]: 25
7821 13:39:00.562425
7822 13:39:00.565775 Set Vref, RX VrefLevel [Byte0]: 26
7823 13:39:00.569306 [Byte1]: 26
7824 13:39:00.573029
7825 13:39:00.573140 Set Vref, RX VrefLevel [Byte0]: 27
7826 13:39:00.575955 [Byte1]: 27
7827 13:39:00.580273
7828 13:39:00.580386 Set Vref, RX VrefLevel [Byte0]: 28
7829 13:39:00.584006 [Byte1]: 28
7830 13:39:00.588116
7831 13:39:00.588215 Set Vref, RX VrefLevel [Byte0]: 29
7832 13:39:00.591157 [Byte1]: 29
7833 13:39:00.595425
7834 13:39:00.595509 Set Vref, RX VrefLevel [Byte0]: 30
7835 13:39:00.598938 [Byte1]: 30
7836 13:39:00.603073
7837 13:39:00.603183 Set Vref, RX VrefLevel [Byte0]: 31
7838 13:39:00.606353 [Byte1]: 31
7839 13:39:00.610628
7840 13:39:00.610708 Set Vref, RX VrefLevel [Byte0]: 32
7841 13:39:00.614094 [Byte1]: 32
7842 13:39:00.617981
7843 13:39:00.618093 Set Vref, RX VrefLevel [Byte0]: 33
7844 13:39:00.621308 [Byte1]: 33
7845 13:39:00.625692
7846 13:39:00.625779 Set Vref, RX VrefLevel [Byte0]: 34
7847 13:39:00.629076 [Byte1]: 34
7848 13:39:00.633433
7849 13:39:00.633520 Set Vref, RX VrefLevel [Byte0]: 35
7850 13:39:00.636869 [Byte1]: 35
7851 13:39:00.640830
7852 13:39:00.640917 Set Vref, RX VrefLevel [Byte0]: 36
7853 13:39:00.644382 [Byte1]: 36
7854 13:39:00.648701
7855 13:39:00.648821 Set Vref, RX VrefLevel [Byte0]: 37
7856 13:39:00.651677 [Byte1]: 37
7857 13:39:00.656006
7858 13:39:00.656086 Set Vref, RX VrefLevel [Byte0]: 38
7859 13:39:00.659475 [Byte1]: 38
7860 13:39:00.663429
7861 13:39:00.663507 Set Vref, RX VrefLevel [Byte0]: 39
7862 13:39:00.666836 [Byte1]: 39
7863 13:39:00.671322
7864 13:39:00.671440 Set Vref, RX VrefLevel [Byte0]: 40
7865 13:39:00.674658 [Byte1]: 40
7866 13:39:00.678752
7867 13:39:00.678837 Set Vref, RX VrefLevel [Byte0]: 41
7868 13:39:00.682227 [Byte1]: 41
7869 13:39:00.686532
7870 13:39:00.686603 Set Vref, RX VrefLevel [Byte0]: 42
7871 13:39:00.689867 [Byte1]: 42
7872 13:39:00.693997
7873 13:39:00.694101 Set Vref, RX VrefLevel [Byte0]: 43
7874 13:39:00.697347 [Byte1]: 43
7875 13:39:00.701571
7876 13:39:00.701679 Set Vref, RX VrefLevel [Byte0]: 44
7877 13:39:00.704679 [Byte1]: 44
7878 13:39:00.709137
7879 13:39:00.709222 Set Vref, RX VrefLevel [Byte0]: 45
7880 13:39:00.712462 [Byte1]: 45
7881 13:39:00.716829
7882 13:39:00.716911 Set Vref, RX VrefLevel [Byte0]: 46
7883 13:39:00.719781 [Byte1]: 46
7884 13:39:00.724034
7885 13:39:00.724121 Set Vref, RX VrefLevel [Byte0]: 47
7886 13:39:00.727339 [Byte1]: 47
7887 13:39:00.731722
7888 13:39:00.731802 Set Vref, RX VrefLevel [Byte0]: 48
7889 13:39:00.735139 [Byte1]: 48
7890 13:39:00.739517
7891 13:39:00.739594 Set Vref, RX VrefLevel [Byte0]: 49
7892 13:39:00.742961 [Byte1]: 49
7893 13:39:00.746739
7894 13:39:00.746819 Set Vref, RX VrefLevel [Byte0]: 50
7895 13:39:00.750154 [Byte1]: 50
7896 13:39:00.754493
7897 13:39:00.754574 Set Vref, RX VrefLevel [Byte0]: 51
7898 13:39:00.757971 [Byte1]: 51
7899 13:39:00.761971
7900 13:39:00.762049 Set Vref, RX VrefLevel [Byte0]: 52
7901 13:39:00.765336 [Byte1]: 52
7902 13:39:00.769768
7903 13:39:00.769879 Set Vref, RX VrefLevel [Byte0]: 53
7904 13:39:00.772768 [Byte1]: 53
7905 13:39:00.777167
7906 13:39:00.777257 Set Vref, RX VrefLevel [Byte0]: 54
7907 13:39:00.780275 [Byte1]: 54
7908 13:39:00.784926
7909 13:39:00.785013 Set Vref, RX VrefLevel [Byte0]: 55
7910 13:39:00.788331 [Byte1]: 55
7911 13:39:00.792262
7912 13:39:00.792346 Set Vref, RX VrefLevel [Byte0]: 56
7913 13:39:00.795555 [Byte1]: 56
7914 13:39:00.799948
7915 13:39:00.800032 Set Vref, RX VrefLevel [Byte0]: 57
7916 13:39:00.803093 [Byte1]: 57
7917 13:39:00.807596
7918 13:39:00.807695 Set Vref, RX VrefLevel [Byte0]: 58
7919 13:39:00.810769 [Byte1]: 58
7920 13:39:00.815047
7921 13:39:00.815132 Set Vref, RX VrefLevel [Byte0]: 59
7922 13:39:00.818427 [Byte1]: 59
7923 13:39:00.822782
7924 13:39:00.822868 Set Vref, RX VrefLevel [Byte0]: 60
7925 13:39:00.825911 [Byte1]: 60
7926 13:39:00.830033
7927 13:39:00.830117 Set Vref, RX VrefLevel [Byte0]: 61
7928 13:39:00.833387 [Byte1]: 61
7929 13:39:00.837672
7930 13:39:00.837757 Set Vref, RX VrefLevel [Byte0]: 62
7931 13:39:00.841020 [Byte1]: 62
7932 13:39:00.845332
7933 13:39:00.845416 Set Vref, RX VrefLevel [Byte0]: 63
7934 13:39:00.848762 [Byte1]: 63
7935 13:39:00.853061
7936 13:39:00.853146 Set Vref, RX VrefLevel [Byte0]: 64
7937 13:39:00.856393 [Byte1]: 64
7938 13:39:00.860376
7939 13:39:00.860461 Set Vref, RX VrefLevel [Byte0]: 65
7940 13:39:00.863814 [Byte1]: 65
7941 13:39:00.868353
7942 13:39:00.868437 Set Vref, RX VrefLevel [Byte0]: 66
7943 13:39:00.871375 [Byte1]: 66
7944 13:39:00.875780
7945 13:39:00.875866 Set Vref, RX VrefLevel [Byte0]: 67
7946 13:39:00.879140 [Byte1]: 67
7947 13:39:00.883054
7948 13:39:00.883173 Set Vref, RX VrefLevel [Byte0]: 68
7949 13:39:00.886643 [Byte1]: 68
7950 13:39:00.890905
7951 13:39:00.890991 Set Vref, RX VrefLevel [Byte0]: 69
7952 13:39:00.893873 [Byte1]: 69
7953 13:39:00.898275
7954 13:39:00.898360 Set Vref, RX VrefLevel [Byte0]: 70
7955 13:39:00.901531 [Byte1]: 70
7956 13:39:00.905810
7957 13:39:00.905896 Set Vref, RX VrefLevel [Byte0]: 71
7958 13:39:00.909025 [Byte1]: 71
7959 13:39:00.913568
7960 13:39:00.913682 Set Vref, RX VrefLevel [Byte0]: 72
7961 13:39:00.916750 [Byte1]: 72
7962 13:39:00.920855
7963 13:39:00.920939 Set Vref, RX VrefLevel [Byte0]: 73
7964 13:39:00.924154 [Byte1]: 73
7965 13:39:00.928580
7966 13:39:00.928666 Set Vref, RX VrefLevel [Byte0]: 74
7967 13:39:00.931915 [Byte1]: 74
7968 13:39:00.936234
7969 13:39:00.936319 Set Vref, RX VrefLevel [Byte0]: 75
7970 13:39:00.939658 [Byte1]: 75
7971 13:39:00.944051
7972 13:39:00.944137 Set Vref, RX VrefLevel [Byte0]: 76
7973 13:39:00.946947 [Byte1]: 76
7974 13:39:00.951270
7975 13:39:00.951356 Set Vref, RX VrefLevel [Byte0]: 77
7976 13:39:00.954621 [Byte1]: 77
7977 13:39:00.959071
7978 13:39:00.959158 Set Vref, RX VrefLevel [Byte0]: 78
7979 13:39:00.962396 [Byte1]: 78
7980 13:39:00.966361
7981 13:39:00.966446 Set Vref, RX VrefLevel [Byte0]: 79
7982 13:39:00.969809 [Byte1]: 79
7983 13:39:00.974038
7984 13:39:00.974155 Final RX Vref Byte 0 = 64 to rank0
7985 13:39:00.977512 Final RX Vref Byte 1 = 62 to rank0
7986 13:39:00.980885 Final RX Vref Byte 0 = 64 to rank1
7987 13:39:00.983887 Final RX Vref Byte 1 = 62 to rank1==
7988 13:39:00.987201 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 13:39:00.993907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 13:39:00.993993 ==
7991 13:39:00.994062 DQS Delay:
7992 13:39:00.994124 DQS0 = 0, DQS1 = 0
7993 13:39:00.997185 DQM Delay:
7994 13:39:00.997291 DQM0 = 134, DQM1 = 126
7995 13:39:01.000685 DQ Delay:
7996 13:39:01.004040 DQ0 =134, DQ1 =134, DQ2 =130, DQ3 =132
7997 13:39:01.007271 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7998 13:39:01.010586 DQ8 =116, DQ9 =114, DQ10 =128, DQ11 =120
7999 13:39:01.013729 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =132
8000 13:39:01.013816
8001 13:39:01.013898
8002 13:39:01.013988
8003 13:39:01.017390 [DramC_TX_OE_Calibration] TA2
8004 13:39:01.020456 Original DQ_B0 (3 6) =30, OEN = 27
8005 13:39:01.023676 Original DQ_B1 (3 6) =30, OEN = 27
8006 13:39:01.027264 24, 0x0, End_B0=24 End_B1=24
8007 13:39:01.027344 25, 0x0, End_B0=25 End_B1=25
8008 13:39:01.030639 26, 0x0, End_B0=26 End_B1=26
8009 13:39:01.033700 27, 0x0, End_B0=27 End_B1=27
8010 13:39:01.037452 28, 0x0, End_B0=28 End_B1=28
8011 13:39:01.037534 29, 0x0, End_B0=29 End_B1=29
8012 13:39:01.040314 30, 0x0, End_B0=30 End_B1=30
8013 13:39:01.043671 31, 0x4141, End_B0=30 End_B1=30
8014 13:39:01.047264 Byte0 end_step=30 best_step=27
8015 13:39:01.050778 Byte1 end_step=30 best_step=27
8016 13:39:01.053732 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 13:39:01.053834 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 13:39:01.053929
8019 13:39:01.057129
8020 13:39:01.063915 [DQSOSCAuto] RK0, (LSB)MR18= 0x211f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8021 13:39:01.067325 CH0 RK0: MR19=303, MR18=211F
8022 13:39:01.074132 CH0_RK0: MR19=0x303, MR18=0x211F, DQSOSC=393, MR23=63, INC=23, DEC=15
8023 13:39:01.074267
8024 13:39:01.077624 ----->DramcWriteLeveling(PI) begin...
8025 13:39:01.077750 ==
8026 13:39:01.080542 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 13:39:01.083895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 13:39:01.084015 ==
8029 13:39:01.087274 Write leveling (Byte 0): 38 => 38
8030 13:39:01.090353 Write leveling (Byte 1): 28 => 28
8031 13:39:01.093850 DramcWriteLeveling(PI) end<-----
8032 13:39:01.093941
8033 13:39:01.094009 ==
8034 13:39:01.097061 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 13:39:01.100341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 13:39:01.100431 ==
8037 13:39:01.103760 [Gating] SW mode calibration
8038 13:39:01.110573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 13:39:01.117198 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 13:39:01.120523 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 13:39:01.123705 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 13:39:01.130314 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 13:39:01.133883 1 4 12 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
8044 13:39:01.136833 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 13:39:01.143640 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 13:39:01.147291 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 13:39:01.150495 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 13:39:01.156896 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 13:39:01.160311 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 13:39:01.163759 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8051 13:39:01.170309 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8052 13:39:01.173771 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
8053 13:39:01.177025 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 13:39:01.180452 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 13:39:01.187324 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 13:39:01.190341 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 13:39:01.193748 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 13:39:01.200371 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8059 13:39:01.203633 1 6 12 | B1->B0 | 2c2c 4141 | 0 1 | (0 0) (0 0)
8060 13:39:01.207047 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 13:39:01.213565 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 13:39:01.217040 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 13:39:01.220547 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 13:39:01.227431 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 13:39:01.230223 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 13:39:01.233760 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8067 13:39:01.240515 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8068 13:39:01.243794 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 13:39:01.247103 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 13:39:01.253657 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 13:39:01.256733 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 13:39:01.260282 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 13:39:01.267031 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 13:39:01.269963 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 13:39:01.273460 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 13:39:01.279975 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 13:39:01.283409 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 13:39:01.286819 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 13:39:01.293338 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 13:39:01.296739 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 13:39:01.300199 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 13:39:01.303536 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 13:39:01.310420 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8084 13:39:01.313581 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 13:39:01.316702 Total UI for P1: 0, mck2ui 16
8086 13:39:01.320365 best dqsien dly found for B0: ( 1, 9, 10)
8087 13:39:01.323558 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 13:39:01.326901 Total UI for P1: 0, mck2ui 16
8089 13:39:01.330143 best dqsien dly found for B1: ( 1, 9, 14)
8090 13:39:01.333349 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8091 13:39:01.336751 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8092 13:39:01.336879
8093 13:39:01.343425 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8094 13:39:01.346587 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8095 13:39:01.350273 [Gating] SW calibration Done
8096 13:39:01.350363 ==
8097 13:39:01.353483 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 13:39:01.356939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 13:39:01.357031 ==
8100 13:39:01.357100 RX Vref Scan: 0
8101 13:39:01.359883
8102 13:39:01.359969 RX Vref 0 -> 0, step: 1
8103 13:39:01.360036
8104 13:39:01.363249 RX Delay 0 -> 252, step: 8
8105 13:39:01.366614 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8106 13:39:01.370015 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8107 13:39:01.376799 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8108 13:39:01.380198 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8109 13:39:01.383133 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8110 13:39:01.386543 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8111 13:39:01.390010 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8112 13:39:01.396938 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8113 13:39:01.399757 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8114 13:39:01.403345 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8115 13:39:01.406478 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8116 13:39:01.409937 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8117 13:39:01.416865 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8118 13:39:01.419702 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8119 13:39:01.423274 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8120 13:39:01.426642 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8121 13:39:01.426808 ==
8122 13:39:01.430111 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 13:39:01.433560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 13:39:01.436799 ==
8125 13:39:01.436974 DQS Delay:
8126 13:39:01.437081 DQS0 = 0, DQS1 = 0
8127 13:39:01.439715 DQM Delay:
8128 13:39:01.439832 DQM0 = 135, DQM1 = 126
8129 13:39:01.443271 DQ Delay:
8130 13:39:01.446680 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8131 13:39:01.450041 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8132 13:39:01.453407 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8133 13:39:01.456581 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8134 13:39:01.456737
8135 13:39:01.456841
8136 13:39:01.456939 ==
8137 13:39:01.459853 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 13:39:01.463103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 13:39:01.463250 ==
8140 13:39:01.463355
8141 13:39:01.466649
8142 13:39:01.466775 TX Vref Scan disable
8143 13:39:01.469705 == TX Byte 0 ==
8144 13:39:01.473060 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8145 13:39:01.476509 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8146 13:39:01.479974 == TX Byte 1 ==
8147 13:39:01.483558 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8148 13:39:01.486642 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8149 13:39:01.486772 ==
8150 13:39:01.490049 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 13:39:01.496376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 13:39:01.496500 ==
8153 13:39:01.510200
8154 13:39:01.513616 TX Vref early break, caculate TX vref
8155 13:39:01.516826 TX Vref=16, minBit 0, minWin=23, winSum=388
8156 13:39:01.520144 TX Vref=18, minBit 0, minWin=23, winSum=394
8157 13:39:01.523666 TX Vref=20, minBit 0, minWin=24, winSum=406
8158 13:39:01.526765 TX Vref=22, minBit 8, minWin=24, winSum=411
8159 13:39:01.530316 TX Vref=24, minBit 3, minWin=25, winSum=420
8160 13:39:01.536861 TX Vref=26, minBit 2, minWin=25, winSum=431
8161 13:39:01.540133 TX Vref=28, minBit 0, minWin=26, winSum=426
8162 13:39:01.543385 TX Vref=30, minBit 0, minWin=26, winSum=424
8163 13:39:01.546365 TX Vref=32, minBit 0, minWin=25, winSum=417
8164 13:39:01.549700 TX Vref=34, minBit 2, minWin=24, winSum=410
8165 13:39:01.553374 TX Vref=36, minBit 2, minWin=24, winSum=396
8166 13:39:01.559617 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8167 13:39:01.559766
8168 13:39:01.563048 Final TX Range 0 Vref 28
8169 13:39:01.563154
8170 13:39:01.563241 ==
8171 13:39:01.566486 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 13:39:01.569902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 13:39:01.569995 ==
8174 13:39:01.572829
8175 13:39:01.572917
8176 13:39:01.573020 TX Vref Scan disable
8177 13:39:01.579717 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8178 13:39:01.579814 == TX Byte 0 ==
8179 13:39:01.583188 u2DelayCellOfst[0]=13 cells (4 PI)
8180 13:39:01.586615 u2DelayCellOfst[1]=20 cells (6 PI)
8181 13:39:01.589652 u2DelayCellOfst[2]=13 cells (4 PI)
8182 13:39:01.593129 u2DelayCellOfst[3]=13 cells (4 PI)
8183 13:39:01.596526 u2DelayCellOfst[4]=10 cells (3 PI)
8184 13:39:01.599984 u2DelayCellOfst[5]=0 cells (0 PI)
8185 13:39:01.603117 u2DelayCellOfst[6]=20 cells (6 PI)
8186 13:39:01.606543 u2DelayCellOfst[7]=20 cells (6 PI)
8187 13:39:01.609571 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8188 13:39:01.613161 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8189 13:39:01.616197 == TX Byte 1 ==
8190 13:39:01.619602 u2DelayCellOfst[8]=0 cells (0 PI)
8191 13:39:01.623392 u2DelayCellOfst[9]=0 cells (0 PI)
8192 13:39:01.626720 u2DelayCellOfst[10]=3 cells (1 PI)
8193 13:39:01.626807 u2DelayCellOfst[11]=0 cells (0 PI)
8194 13:39:01.629693 u2DelayCellOfst[12]=10 cells (3 PI)
8195 13:39:01.633222 u2DelayCellOfst[13]=6 cells (2 PI)
8196 13:39:01.636124 u2DelayCellOfst[14]=10 cells (3 PI)
8197 13:39:01.639722 u2DelayCellOfst[15]=6 cells (2 PI)
8198 13:39:01.646487 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8199 13:39:01.649962 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8200 13:39:01.650054 DramC Write-DBI on
8201 13:39:01.650122 ==
8202 13:39:01.652924 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 13:39:01.659572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 13:39:01.659662 ==
8205 13:39:01.659730
8206 13:39:01.659819
8207 13:39:01.659882 TX Vref Scan disable
8208 13:39:01.663668 == TX Byte 0 ==
8209 13:39:01.667489 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8210 13:39:01.670385 == TX Byte 1 ==
8211 13:39:01.673692 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8212 13:39:01.677144 DramC Write-DBI off
8213 13:39:01.677234
8214 13:39:01.677310 [DATLAT]
8215 13:39:01.677375 Freq=1600, CH0 RK1
8216 13:39:01.677436
8217 13:39:01.680610 DATLAT Default: 0xf
8218 13:39:01.680698 0, 0xFFFF, sum = 0
8219 13:39:01.683625 1, 0xFFFF, sum = 0
8220 13:39:01.683712 2, 0xFFFF, sum = 0
8221 13:39:01.687225 3, 0xFFFF, sum = 0
8222 13:39:01.690260 4, 0xFFFF, sum = 0
8223 13:39:01.690348 5, 0xFFFF, sum = 0
8224 13:39:01.693751 6, 0xFFFF, sum = 0
8225 13:39:01.693840 7, 0xFFFF, sum = 0
8226 13:39:01.697147 8, 0xFFFF, sum = 0
8227 13:39:01.697234 9, 0xFFFF, sum = 0
8228 13:39:01.700239 10, 0xFFFF, sum = 0
8229 13:39:01.700367 11, 0xFFFF, sum = 0
8230 13:39:01.703770 12, 0xFFFF, sum = 0
8231 13:39:01.703929 13, 0xFFFF, sum = 0
8232 13:39:01.707238 14, 0x0, sum = 1
8233 13:39:01.707401 15, 0x0, sum = 2
8234 13:39:01.710264 16, 0x0, sum = 3
8235 13:39:01.710407 17, 0x0, sum = 4
8236 13:39:01.713764 best_step = 15
8237 13:39:01.713915
8238 13:39:01.713987 ==
8239 13:39:01.717203 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 13:39:01.720281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 13:39:01.720429 ==
8242 13:39:01.720536 RX Vref Scan: 0
8243 13:39:01.723688
8244 13:39:01.723846 RX Vref 0 -> 0, step: 1
8245 13:39:01.723952
8246 13:39:01.727061 RX Delay 19 -> 252, step: 4
8247 13:39:01.730312 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8248 13:39:01.737289 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8249 13:39:01.740206 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8250 13:39:01.743663 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8251 13:39:01.747042 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8252 13:39:01.750275 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8253 13:39:01.753747 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8254 13:39:01.760250 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8255 13:39:01.763650 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8256 13:39:01.766866 iDelay=191, Bit 9, Center 112 (63 ~ 162) 100
8257 13:39:01.770147 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8258 13:39:01.773649 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8259 13:39:01.780360 iDelay=191, Bit 12, Center 130 (83 ~ 178) 96
8260 13:39:01.783625 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8261 13:39:01.787167 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8262 13:39:01.790243 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8263 13:39:01.790397 ==
8264 13:39:01.793627 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 13:39:01.800441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 13:39:01.800623 ==
8267 13:39:01.800748 DQS Delay:
8268 13:39:01.800862 DQS0 = 0, DQS1 = 0
8269 13:39:01.803336 DQM Delay:
8270 13:39:01.803476 DQM0 = 132, DQM1 = 125
8271 13:39:01.806818 DQ Delay:
8272 13:39:01.810350 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8273 13:39:01.813831 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8274 13:39:01.816930 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =122
8275 13:39:01.820382 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
8276 13:39:01.820546
8277 13:39:01.820665
8278 13:39:01.820776
8279 13:39:01.823366 [DramC_TX_OE_Calibration] TA2
8280 13:39:01.826873 Original DQ_B0 (3 6) =30, OEN = 27
8281 13:39:01.830256 Original DQ_B1 (3 6) =30, OEN = 27
8282 13:39:01.833548 24, 0x0, End_B0=24 End_B1=24
8283 13:39:01.833705 25, 0x0, End_B0=25 End_B1=25
8284 13:39:01.836789 26, 0x0, End_B0=26 End_B1=26
8285 13:39:01.840400 27, 0x0, End_B0=27 End_B1=27
8286 13:39:01.843843 28, 0x0, End_B0=28 End_B1=28
8287 13:39:01.844017 29, 0x0, End_B0=29 End_B1=29
8288 13:39:01.846746 30, 0x0, End_B0=30 End_B1=30
8289 13:39:01.850213 31, 0x4545, End_B0=30 End_B1=30
8290 13:39:01.853568 Byte0 end_step=30 best_step=27
8291 13:39:01.856851 Byte1 end_step=30 best_step=27
8292 13:39:01.860254 Byte0 TX OE(2T, 0.5T) = (3, 3)
8293 13:39:01.860458 Byte1 TX OE(2T, 0.5T) = (3, 3)
8294 13:39:01.860583
8295 13:39:01.863871
8296 13:39:01.870374 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8297 13:39:01.873604 CH0 RK1: MR19=303, MR18=220F
8298 13:39:01.879981 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8299 13:39:01.883382 [RxdqsGatingPostProcess] freq 1600
8300 13:39:01.886819 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8301 13:39:01.890280 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 13:39:01.893236 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 13:39:01.896779 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 13:39:01.900205 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 13:39:01.903192 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 13:39:01.906714 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 13:39:01.910178 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 13:39:01.913641 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 13:39:01.916629 Pre-setting of DQS Precalculation
8310 13:39:01.920044 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8311 13:39:01.920161 ==
8312 13:39:01.923126 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 13:39:01.926648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 13:39:01.926778 ==
8315 13:39:01.933550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 13:39:01.936850 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 13:39:01.943370 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 13:39:01.946819 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 13:39:01.956170 [CA 0] Center 42 (12~72) winsize 61
8320 13:39:01.959891 [CA 1] Center 42 (12~72) winsize 61
8321 13:39:01.962742 [CA 2] Center 38 (9~68) winsize 60
8322 13:39:01.966348 [CA 3] Center 37 (8~67) winsize 60
8323 13:39:01.969785 [CA 4] Center 37 (8~67) winsize 60
8324 13:39:01.973100 [CA 5] Center 37 (7~67) winsize 61
8325 13:39:01.973215
8326 13:39:01.976270 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8327 13:39:01.976387
8328 13:39:01.979586 [CATrainingPosCal] consider 1 rank data
8329 13:39:01.982812 u2DelayCellTimex100 = 290/100 ps
8330 13:39:01.986270 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8331 13:39:01.993150 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8332 13:39:01.996400 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8333 13:39:01.999743 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8334 13:39:02.002802 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 13:39:02.006304 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8336 13:39:02.006425
8337 13:39:02.009723 CA PerBit enable=1, Macro0, CA PI delay=37
8338 13:39:02.009827
8339 13:39:02.012704 [CBTSetCACLKResult] CA Dly = 37
8340 13:39:02.016190 CS Dly: 8 (0~39)
8341 13:39:02.019797 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 13:39:02.022713 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 13:39:02.022826 ==
8344 13:39:02.026186 Dram Type= 6, Freq= 0, CH_1, rank 1
8345 13:39:02.029738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 13:39:02.029821 ==
8347 13:39:02.036264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 13:39:02.039322 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 13:39:02.046110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 13:39:02.049123 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 13:39:02.059460 [CA 0] Center 41 (12~71) winsize 60
8352 13:39:02.062699 [CA 1] Center 41 (11~71) winsize 61
8353 13:39:02.066410 [CA 2] Center 38 (9~68) winsize 60
8354 13:39:02.069388 [CA 3] Center 37 (8~67) winsize 60
8355 13:39:02.072829 [CA 4] Center 37 (8~67) winsize 60
8356 13:39:02.076060 [CA 5] Center 37 (7~67) winsize 61
8357 13:39:02.076181
8358 13:39:02.079454 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8359 13:39:02.079569
8360 13:39:02.082811 [CATrainingPosCal] consider 2 rank data
8361 13:39:02.086204 u2DelayCellTimex100 = 290/100 ps
8362 13:39:02.089573 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8363 13:39:02.096125 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8364 13:39:02.099662 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8365 13:39:02.102696 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8366 13:39:02.106086 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8367 13:39:02.109598 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8368 13:39:02.109713
8369 13:39:02.112962 CA PerBit enable=1, Macro0, CA PI delay=37
8370 13:39:02.113067
8371 13:39:02.115933 [CBTSetCACLKResult] CA Dly = 37
8372 13:39:02.116045 CS Dly: 9 (0~41)
8373 13:39:02.122877 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 13:39:02.125843 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 13:39:02.125960
8376 13:39:02.129464 ----->DramcWriteLeveling(PI) begin...
8377 13:39:02.129593 ==
8378 13:39:02.132777 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 13:39:02.136186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 13:39:02.136307 ==
8381 13:39:02.139276 Write leveling (Byte 0): 25 => 25
8382 13:39:02.142748 Write leveling (Byte 1): 27 => 27
8383 13:39:02.146228 DramcWriteLeveling(PI) end<-----
8384 13:39:02.146314
8385 13:39:02.146380 ==
8386 13:39:02.149329 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 13:39:02.155995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 13:39:02.156109 ==
8389 13:39:02.156204 [Gating] SW mode calibration
8390 13:39:02.165968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8391 13:39:02.169820 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8392 13:39:02.172665 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 13:39:02.179522 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 13:39:02.182836 1 4 8 | B1->B0 | 2727 2d2d | 1 1 | (0 0) (1 1)
8395 13:39:02.186131 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 13:39:02.192927 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 13:39:02.196387 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 13:39:02.199279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 13:39:02.206285 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 13:39:02.209246 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 13:39:02.212629 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8402 13:39:02.219389 1 5 8 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (1 0)
8403 13:39:02.222427 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8404 13:39:02.225907 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 13:39:02.232763 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 13:39:02.235701 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 13:39:02.239167 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 13:39:02.245593 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 13:39:02.248805 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8410 13:39:02.252610 1 6 8 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)
8411 13:39:02.259091 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 13:39:02.262466 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 13:39:02.265958 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 13:39:02.272574 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 13:39:02.275604 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 13:39:02.280179 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 13:39:02.282417 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8418 13:39:02.289114 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8419 13:39:02.292556 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8420 13:39:02.295898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 13:39:02.302215 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 13:39:02.305837 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 13:39:02.309256 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 13:39:02.315615 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 13:39:02.319059 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 13:39:02.322584 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 13:39:02.328937 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 13:39:02.332336 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 13:39:02.335682 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 13:39:02.342362 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 13:39:02.345774 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 13:39:02.348701 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 13:39:02.355545 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8434 13:39:02.358730 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8435 13:39:02.362207 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8436 13:39:02.365658 Total UI for P1: 0, mck2ui 16
8437 13:39:02.368797 best dqsien dly found for B0: ( 1, 9, 6)
8438 13:39:02.372471 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 13:39:02.375639 Total UI for P1: 0, mck2ui 16
8440 13:39:02.378906 best dqsien dly found for B1: ( 1, 9, 10)
8441 13:39:02.382208 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8442 13:39:02.388680 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8443 13:39:02.388766
8444 13:39:02.391988 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8445 13:39:02.395644 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 13:39:02.398939 [Gating] SW calibration Done
8447 13:39:02.399024 ==
8448 13:39:02.401965 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 13:39:02.405770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 13:39:02.405916 ==
8451 13:39:02.408819 RX Vref Scan: 0
8452 13:39:02.408902
8453 13:39:02.408966 RX Vref 0 -> 0, step: 1
8454 13:39:02.409025
8455 13:39:02.412471 RX Delay 0 -> 252, step: 8
8456 13:39:02.415371 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8457 13:39:02.418774 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8458 13:39:02.425213 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8459 13:39:02.428627 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8460 13:39:02.432069 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8461 13:39:02.435508 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8462 13:39:02.438508 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8463 13:39:02.445251 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8464 13:39:02.448871 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8465 13:39:02.451800 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8466 13:39:02.455352 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8467 13:39:02.458803 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8468 13:39:02.465189 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8469 13:39:02.468650 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8470 13:39:02.472111 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8471 13:39:02.475084 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8472 13:39:02.475166 ==
8473 13:39:02.478487 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 13:39:02.485364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 13:39:02.485463 ==
8476 13:39:02.485531 DQS Delay:
8477 13:39:02.485591 DQS0 = 0, DQS1 = 0
8478 13:39:02.488422 DQM Delay:
8479 13:39:02.488495 DQM0 = 137, DQM1 = 130
8480 13:39:02.492025 DQ Delay:
8481 13:39:02.495325 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8482 13:39:02.498668 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8483 13:39:02.502004 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8484 13:39:02.505279 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8485 13:39:02.505386
8486 13:39:02.505480
8487 13:39:02.505539 ==
8488 13:39:02.508358 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 13:39:02.511708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 13:39:02.511792 ==
8491 13:39:02.515349
8492 13:39:02.515432
8493 13:39:02.515495 TX Vref Scan disable
8494 13:39:02.518749 == TX Byte 0 ==
8495 13:39:02.521944 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8496 13:39:02.525311 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 13:39:02.528520 == TX Byte 1 ==
8498 13:39:02.531798 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 13:39:02.535128 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8500 13:39:02.535216 ==
8501 13:39:02.538804 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 13:39:02.545181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 13:39:02.545271 ==
8504 13:39:02.556801
8505 13:39:02.559791 TX Vref early break, caculate TX vref
8506 13:39:02.563356 TX Vref=16, minBit 1, minWin=22, winSum=375
8507 13:39:02.566646 TX Vref=18, minBit 11, minWin=23, winSum=384
8508 13:39:02.569714 TX Vref=20, minBit 10, minWin=23, winSum=401
8509 13:39:02.573178 TX Vref=22, minBit 10, minWin=24, winSum=402
8510 13:39:02.576318 TX Vref=24, minBit 1, minWin=25, winSum=409
8511 13:39:02.583093 TX Vref=26, minBit 0, minWin=25, winSum=420
8512 13:39:02.586421 TX Vref=28, minBit 10, minWin=25, winSum=423
8513 13:39:02.589612 TX Vref=30, minBit 8, minWin=25, winSum=418
8514 13:39:02.592791 TX Vref=32, minBit 12, minWin=24, winSum=408
8515 13:39:02.596322 TX Vref=34, minBit 5, minWin=24, winSum=398
8516 13:39:02.603107 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 28
8517 13:39:02.603206
8518 13:39:02.606404 Final TX Range 0 Vref 28
8519 13:39:02.606497
8520 13:39:02.606593 ==
8521 13:39:02.609746 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 13:39:02.613039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 13:39:02.613120 ==
8524 13:39:02.613184
8525 13:39:02.613277
8526 13:39:02.616536 TX Vref Scan disable
8527 13:39:02.622943 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8528 13:39:02.623035 == TX Byte 0 ==
8529 13:39:02.625919 u2DelayCellOfst[0]=16 cells (5 PI)
8530 13:39:02.629314 u2DelayCellOfst[1]=10 cells (3 PI)
8531 13:39:02.632911 u2DelayCellOfst[2]=0 cells (0 PI)
8532 13:39:02.636350 u2DelayCellOfst[3]=3 cells (1 PI)
8533 13:39:02.639327 u2DelayCellOfst[4]=6 cells (2 PI)
8534 13:39:02.642608 u2DelayCellOfst[5]=16 cells (5 PI)
8535 13:39:02.646088 u2DelayCellOfst[6]=16 cells (5 PI)
8536 13:39:02.649492 u2DelayCellOfst[7]=3 cells (1 PI)
8537 13:39:02.652967 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8538 13:39:02.656382 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8539 13:39:02.659478 == TX Byte 1 ==
8540 13:39:02.659566 u2DelayCellOfst[8]=0 cells (0 PI)
8541 13:39:02.662735 u2DelayCellOfst[9]=3 cells (1 PI)
8542 13:39:02.666316 u2DelayCellOfst[10]=10 cells (3 PI)
8543 13:39:02.669570 u2DelayCellOfst[11]=3 cells (1 PI)
8544 13:39:02.672593 u2DelayCellOfst[12]=16 cells (5 PI)
8545 13:39:02.676143 u2DelayCellOfst[13]=16 cells (5 PI)
8546 13:39:02.679707 u2DelayCellOfst[14]=16 cells (5 PI)
8547 13:39:02.682617 u2DelayCellOfst[15]=16 cells (5 PI)
8548 13:39:02.685910 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8549 13:39:02.693152 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8550 13:39:02.693285 DramC Write-DBI on
8551 13:39:02.693367 ==
8552 13:39:02.695995 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 13:39:02.699357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 13:39:02.702870 ==
8555 13:39:02.702953
8556 13:39:02.703017
8557 13:39:02.703079 TX Vref Scan disable
8558 13:39:02.706136 == TX Byte 0 ==
8559 13:39:02.709579 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8560 13:39:02.712473 == TX Byte 1 ==
8561 13:39:02.715862 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8562 13:39:02.719210 DramC Write-DBI off
8563 13:39:02.719293
8564 13:39:02.719377 [DATLAT]
8565 13:39:02.719457 Freq=1600, CH1 RK0
8566 13:39:02.719534
8567 13:39:02.722313 DATLAT Default: 0xf
8568 13:39:02.725874 0, 0xFFFF, sum = 0
8569 13:39:02.725988 1, 0xFFFF, sum = 0
8570 13:39:02.729415 2, 0xFFFF, sum = 0
8571 13:39:02.729499 3, 0xFFFF, sum = 0
8572 13:39:02.732415 4, 0xFFFF, sum = 0
8573 13:39:02.732499 5, 0xFFFF, sum = 0
8574 13:39:02.735910 6, 0xFFFF, sum = 0
8575 13:39:02.736021 7, 0xFFFF, sum = 0
8576 13:39:02.739238 8, 0xFFFF, sum = 0
8577 13:39:02.739345 9, 0xFFFF, sum = 0
8578 13:39:02.742247 10, 0xFFFF, sum = 0
8579 13:39:02.742358 11, 0xFFFF, sum = 0
8580 13:39:02.745736 12, 0xFFFF, sum = 0
8581 13:39:02.745847 13, 0xFFFF, sum = 0
8582 13:39:02.749072 14, 0x0, sum = 1
8583 13:39:02.749151 15, 0x0, sum = 2
8584 13:39:02.752394 16, 0x0, sum = 3
8585 13:39:02.752478 17, 0x0, sum = 4
8586 13:39:02.755909 best_step = 15
8587 13:39:02.756022
8588 13:39:02.756121 ==
8589 13:39:02.758855 Dram Type= 6, Freq= 0, CH_1, rank 0
8590 13:39:02.762196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8591 13:39:02.762287 ==
8592 13:39:02.765868 RX Vref Scan: 1
8593 13:39:02.765954
8594 13:39:02.766019 Set Vref Range= 24 -> 127
8595 13:39:02.766079
8596 13:39:02.769262 RX Vref 24 -> 127, step: 1
8597 13:39:02.769351
8598 13:39:02.772259 RX Delay 19 -> 252, step: 4
8599 13:39:02.772358
8600 13:39:02.775460 Set Vref, RX VrefLevel [Byte0]: 24
8601 13:39:02.778991 [Byte1]: 24
8602 13:39:02.779101
8603 13:39:02.782438 Set Vref, RX VrefLevel [Byte0]: 25
8604 13:39:02.785265 [Byte1]: 25
8605 13:39:02.788793
8606 13:39:02.788878 Set Vref, RX VrefLevel [Byte0]: 26
8607 13:39:02.792037 [Byte1]: 26
8608 13:39:02.796284
8609 13:39:02.796386 Set Vref, RX VrefLevel [Byte0]: 27
8610 13:39:02.800007 [Byte1]: 27
8611 13:39:02.803906
8612 13:39:02.803990 Set Vref, RX VrefLevel [Byte0]: 28
8613 13:39:02.807353 [Byte1]: 28
8614 13:39:02.811778
8615 13:39:02.811862 Set Vref, RX VrefLevel [Byte0]: 29
8616 13:39:02.815109 [Byte1]: 29
8617 13:39:02.819030
8618 13:39:02.819114 Set Vref, RX VrefLevel [Byte0]: 30
8619 13:39:02.822340 [Byte1]: 30
8620 13:39:02.826849
8621 13:39:02.826934 Set Vref, RX VrefLevel [Byte0]: 31
8622 13:39:02.830193 [Byte1]: 31
8623 13:39:02.834186
8624 13:39:02.834271 Set Vref, RX VrefLevel [Byte0]: 32
8625 13:39:02.837778 [Byte1]: 32
8626 13:39:02.841868
8627 13:39:02.841953 Set Vref, RX VrefLevel [Byte0]: 33
8628 13:39:02.845209 [Byte1]: 33
8629 13:39:02.849418
8630 13:39:02.849505 Set Vref, RX VrefLevel [Byte0]: 34
8631 13:39:02.852640 [Byte1]: 34
8632 13:39:02.857149
8633 13:39:02.857234 Set Vref, RX VrefLevel [Byte0]: 35
8634 13:39:02.860619 [Byte1]: 35
8635 13:39:02.864733
8636 13:39:02.864847 Set Vref, RX VrefLevel [Byte0]: 36
8637 13:39:02.868190 [Byte1]: 36
8638 13:39:02.872175
8639 13:39:02.872259 Set Vref, RX VrefLevel [Byte0]: 37
8640 13:39:02.875648 [Byte1]: 37
8641 13:39:02.879792
8642 13:39:02.879877 Set Vref, RX VrefLevel [Byte0]: 38
8643 13:39:02.883314 [Byte1]: 38
8644 13:39:02.887343
8645 13:39:02.887420 Set Vref, RX VrefLevel [Byte0]: 39
8646 13:39:02.890850 [Byte1]: 39
8647 13:39:02.894995
8648 13:39:02.895074 Set Vref, RX VrefLevel [Byte0]: 40
8649 13:39:02.898278 [Byte1]: 40
8650 13:39:02.902558
8651 13:39:02.902636 Set Vref, RX VrefLevel [Byte0]: 41
8652 13:39:02.906021 [Byte1]: 41
8653 13:39:02.909948
8654 13:39:02.910026 Set Vref, RX VrefLevel [Byte0]: 42
8655 13:39:02.913459 [Byte1]: 42
8656 13:39:02.917828
8657 13:39:02.917912 Set Vref, RX VrefLevel [Byte0]: 43
8658 13:39:02.921149 [Byte1]: 43
8659 13:39:02.925065
8660 13:39:02.925150 Set Vref, RX VrefLevel [Byte0]: 44
8661 13:39:02.928479 [Byte1]: 44
8662 13:39:02.932915
8663 13:39:02.932999 Set Vref, RX VrefLevel [Byte0]: 45
8664 13:39:02.935874 [Byte1]: 45
8665 13:39:02.940296
8666 13:39:02.940379 Set Vref, RX VrefLevel [Byte0]: 46
8667 13:39:02.943803 [Byte1]: 46
8668 13:39:02.947728
8669 13:39:02.947820 Set Vref, RX VrefLevel [Byte0]: 47
8670 13:39:02.951326 [Byte1]: 47
8671 13:39:02.955648
8672 13:39:02.955733 Set Vref, RX VrefLevel [Byte0]: 48
8673 13:39:02.958655 [Byte1]: 48
8674 13:39:02.963089
8675 13:39:02.963175 Set Vref, RX VrefLevel [Byte0]: 49
8676 13:39:02.966608 [Byte1]: 49
8677 13:39:02.970575
8678 13:39:02.970659 Set Vref, RX VrefLevel [Byte0]: 50
8679 13:39:02.973967 [Byte1]: 50
8680 13:39:02.978540
8681 13:39:02.978635 Set Vref, RX VrefLevel [Byte0]: 51
8682 13:39:02.981253 [Byte1]: 51
8683 13:39:02.985951
8684 13:39:02.986035 Set Vref, RX VrefLevel [Byte0]: 52
8685 13:39:02.988892 [Byte1]: 52
8686 13:39:02.993188
8687 13:39:02.993310 Set Vref, RX VrefLevel [Byte0]: 53
8688 13:39:02.996449 [Byte1]: 53
8689 13:39:03.000759
8690 13:39:03.000884 Set Vref, RX VrefLevel [Byte0]: 54
8691 13:39:03.004091 [Byte1]: 54
8692 13:39:03.008368
8693 13:39:03.008452 Set Vref, RX VrefLevel [Byte0]: 55
8694 13:39:03.011683 [Byte1]: 55
8695 13:39:03.016145
8696 13:39:03.016229 Set Vref, RX VrefLevel [Byte0]: 56
8697 13:39:03.019392 [Byte1]: 56
8698 13:39:03.023840
8699 13:39:03.023925 Set Vref, RX VrefLevel [Byte0]: 57
8700 13:39:03.026735 [Byte1]: 57
8701 13:39:03.031115
8702 13:39:03.031200 Set Vref, RX VrefLevel [Byte0]: 58
8703 13:39:03.034661 [Byte1]: 58
8704 13:39:03.038649
8705 13:39:03.038734 Set Vref, RX VrefLevel [Byte0]: 59
8706 13:39:03.042221 [Byte1]: 59
8707 13:39:03.046461
8708 13:39:03.046545 Set Vref, RX VrefLevel [Byte0]: 60
8709 13:39:03.049854 [Byte1]: 60
8710 13:39:03.053798
8711 13:39:03.053882 Set Vref, RX VrefLevel [Byte0]: 61
8712 13:39:03.057117 [Byte1]: 61
8713 13:39:03.061529
8714 13:39:03.061639 Set Vref, RX VrefLevel [Byte0]: 62
8715 13:39:03.064933 [Byte1]: 62
8716 13:39:03.068827
8717 13:39:03.068911 Set Vref, RX VrefLevel [Byte0]: 63
8718 13:39:03.072300 [Byte1]: 63
8719 13:39:03.076836
8720 13:39:03.076944 Set Vref, RX VrefLevel [Byte0]: 64
8721 13:39:03.079840 [Byte1]: 64
8722 13:39:03.084234
8723 13:39:03.084324 Set Vref, RX VrefLevel [Byte0]: 65
8724 13:39:03.087493 [Byte1]: 65
8725 13:39:03.091896
8726 13:39:03.091981 Set Vref, RX VrefLevel [Byte0]: 66
8727 13:39:03.094839 [Byte1]: 66
8728 13:39:03.099369
8729 13:39:03.102615 Set Vref, RX VrefLevel [Byte0]: 67
8730 13:39:03.106098 [Byte1]: 67
8731 13:39:03.106209
8732 13:39:03.108964 Set Vref, RX VrefLevel [Byte0]: 68
8733 13:39:03.112203 [Byte1]: 68
8734 13:39:03.112306
8735 13:39:03.115686 Set Vref, RX VrefLevel [Byte0]: 69
8736 13:39:03.119290 [Byte1]: 69
8737 13:39:03.119367
8738 13:39:03.122714 Set Vref, RX VrefLevel [Byte0]: 70
8739 13:39:03.126111 [Byte1]: 70
8740 13:39:03.129477
8741 13:39:03.129562 Set Vref, RX VrefLevel [Byte0]: 71
8742 13:39:03.132816 [Byte1]: 71
8743 13:39:03.137269
8744 13:39:03.137385 Set Vref, RX VrefLevel [Byte0]: 72
8745 13:39:03.140675 [Byte1]: 72
8746 13:39:03.144821
8747 13:39:03.144937 Set Vref, RX VrefLevel [Byte0]: 73
8748 13:39:03.148238 [Byte1]: 73
8749 13:39:03.152129
8750 13:39:03.152327 Set Vref, RX VrefLevel [Byte0]: 74
8751 13:39:03.155630 [Byte1]: 74
8752 13:39:03.159822
8753 13:39:03.159955 Final RX Vref Byte 0 = 51 to rank0
8754 13:39:03.163117 Final RX Vref Byte 1 = 61 to rank0
8755 13:39:03.166602 Final RX Vref Byte 0 = 51 to rank1
8756 13:39:03.170091 Final RX Vref Byte 1 = 61 to rank1==
8757 13:39:03.173068 Dram Type= 6, Freq= 0, CH_1, rank 0
8758 13:39:03.180167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 13:39:03.180306 ==
8760 13:39:03.180402 DQS Delay:
8761 13:39:03.180516 DQS0 = 0, DQS1 = 0
8762 13:39:03.183091 DQM Delay:
8763 13:39:03.183232 DQM0 = 133, DQM1 = 129
8764 13:39:03.186662 DQ Delay:
8765 13:39:03.189813 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8766 13:39:03.193245 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8767 13:39:03.196628 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8768 13:39:03.200119 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8769 13:39:03.200240
8770 13:39:03.200340
8771 13:39:03.200427
8772 13:39:03.203094 [DramC_TX_OE_Calibration] TA2
8773 13:39:03.206556 Original DQ_B0 (3 6) =30, OEN = 27
8774 13:39:03.210058 Original DQ_B1 (3 6) =30, OEN = 27
8775 13:39:03.213217 24, 0x0, End_B0=24 End_B1=24
8776 13:39:03.213330 25, 0x0, End_B0=25 End_B1=25
8777 13:39:03.216553 26, 0x0, End_B0=26 End_B1=26
8778 13:39:03.219603 27, 0x0, End_B0=27 End_B1=27
8779 13:39:03.223037 28, 0x0, End_B0=28 End_B1=28
8780 13:39:03.223147 29, 0x0, End_B0=29 End_B1=29
8781 13:39:03.226497 30, 0x0, End_B0=30 End_B1=30
8782 13:39:03.229810 31, 0x4545, End_B0=30 End_B1=30
8783 13:39:03.232959 Byte0 end_step=30 best_step=27
8784 13:39:03.236603 Byte1 end_step=30 best_step=27
8785 13:39:03.239907 Byte0 TX OE(2T, 0.5T) = (3, 3)
8786 13:39:03.240019 Byte1 TX OE(2T, 0.5T) = (3, 3)
8787 13:39:03.243429
8788 13:39:03.243535
8789 13:39:03.249731 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8790 13:39:03.253208 CH1 RK0: MR19=303, MR18=1725
8791 13:39:03.259603 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8792 13:39:03.259730
8793 13:39:03.262973 ----->DramcWriteLeveling(PI) begin...
8794 13:39:03.263074 ==
8795 13:39:03.266362 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 13:39:03.269862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 13:39:03.269961 ==
8798 13:39:03.273288 Write leveling (Byte 0): 25 => 25
8799 13:39:03.276358 Write leveling (Byte 1): 29 => 29
8800 13:39:03.279753 DramcWriteLeveling(PI) end<-----
8801 13:39:03.279896
8802 13:39:03.279969 ==
8803 13:39:03.283236 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 13:39:03.286249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 13:39:03.286384 ==
8806 13:39:03.289796 [Gating] SW mode calibration
8807 13:39:03.296385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8808 13:39:03.303109 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8809 13:39:03.306195 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 13:39:03.309749 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 13:39:03.316569 1 4 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8812 13:39:03.319770 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8813 13:39:03.322910 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 13:39:03.329719 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 13:39:03.333154 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 13:39:03.336145 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 13:39:03.343102 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 13:39:03.346445 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8819 13:39:03.349388 1 5 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 0)
8820 13:39:03.356338 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (1 0) (1 0)
8821 13:39:03.359700 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 13:39:03.363191 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 13:39:03.366638 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 13:39:03.373014 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 13:39:03.376464 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 13:39:03.379967 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8827 13:39:03.386184 1 6 8 | B1->B0 | 4646 2727 | 0 0 | (0 0) (1 1)
8828 13:39:03.389568 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8829 13:39:03.393124 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 13:39:03.399959 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 13:39:03.402918 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 13:39:03.406641 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 13:39:03.413214 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 13:39:03.416248 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 13:39:03.419603 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8836 13:39:03.426335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 13:39:03.429726 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 13:39:03.432677 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 13:39:03.439507 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 13:39:03.442788 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 13:39:03.446294 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 13:39:03.453132 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 13:39:03.456112 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 13:39:03.459703 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 13:39:03.465989 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 13:39:03.469347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 13:39:03.472460 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 13:39:03.479414 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 13:39:03.482821 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 13:39:03.485884 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 13:39:03.492623 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8852 13:39:03.496155 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 13:39:03.499139 Total UI for P1: 0, mck2ui 16
8854 13:39:03.502557 best dqsien dly found for B0: ( 1, 9, 8)
8855 13:39:03.505826 Total UI for P1: 0, mck2ui 16
8856 13:39:03.509434 best dqsien dly found for B1: ( 1, 9, 8)
8857 13:39:03.512331 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8858 13:39:03.515775 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8859 13:39:03.515854
8860 13:39:03.519291 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8861 13:39:03.522689 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8862 13:39:03.525918 [Gating] SW calibration Done
8863 13:39:03.525997 ==
8864 13:39:03.528792 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 13:39:03.532243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 13:39:03.532325 ==
8867 13:39:03.535678 RX Vref Scan: 0
8868 13:39:03.535758
8869 13:39:03.535821 RX Vref 0 -> 0, step: 1
8870 13:39:03.538955
8871 13:39:03.539049 RX Delay 0 -> 252, step: 8
8872 13:39:03.542344 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8873 13:39:03.548899 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8874 13:39:03.552378 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8875 13:39:03.555679 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8876 13:39:03.559163 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8877 13:39:03.562223 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8878 13:39:03.568896 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8879 13:39:03.572406 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8880 13:39:03.575473 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8881 13:39:03.578976 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8882 13:39:03.582370 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8883 13:39:03.588862 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8884 13:39:03.592350 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8885 13:39:03.595886 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8886 13:39:03.598855 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8887 13:39:03.602412 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8888 13:39:03.605822 ==
8889 13:39:03.609020 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 13:39:03.612348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 13:39:03.612501 ==
8892 13:39:03.612619 DQS Delay:
8893 13:39:03.615698 DQS0 = 0, DQS1 = 0
8894 13:39:03.615825 DQM Delay:
8895 13:39:03.618611 DQM0 = 136, DQM1 = 133
8896 13:39:03.618756 DQ Delay:
8897 13:39:03.622240 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8898 13:39:03.625673 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8899 13:39:03.628982 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8900 13:39:03.632363 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8901 13:39:03.632465
8902 13:39:03.632531
8903 13:39:03.632592 ==
8904 13:39:03.635344 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 13:39:03.641838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 13:39:03.641929 ==
8907 13:39:03.641995
8908 13:39:03.642057
8909 13:39:03.642116 TX Vref Scan disable
8910 13:39:03.645640 == TX Byte 0 ==
8911 13:39:03.649058 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8912 13:39:03.652481 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 13:39:03.655478 == TX Byte 1 ==
8914 13:39:03.658858 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8915 13:39:03.662275 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8916 13:39:03.665775 ==
8917 13:39:03.669060 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 13:39:03.672052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 13:39:03.672140 ==
8920 13:39:03.684630
8921 13:39:03.688121 TX Vref early break, caculate TX vref
8922 13:39:03.691017 TX Vref=16, minBit 8, minWin=22, winSum=378
8923 13:39:03.694439 TX Vref=18, minBit 8, minWin=23, winSum=387
8924 13:39:03.697861 TX Vref=20, minBit 8, minWin=23, winSum=396
8925 13:39:03.701276 TX Vref=22, minBit 9, minWin=23, winSum=404
8926 13:39:03.704262 TX Vref=24, minBit 9, minWin=23, winSum=407
8927 13:39:03.710980 TX Vref=26, minBit 8, minWin=25, winSum=419
8928 13:39:03.714280 TX Vref=28, minBit 8, minWin=25, winSum=420
8929 13:39:03.717613 TX Vref=30, minBit 8, minWin=24, winSum=412
8930 13:39:03.721074 TX Vref=32, minBit 0, minWin=24, winSum=403
8931 13:39:03.724536 TX Vref=34, minBit 9, minWin=23, winSum=392
8932 13:39:03.730911 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8933 13:39:03.731023
8934 13:39:03.734220 Final TX Range 0 Vref 28
8935 13:39:03.734300
8936 13:39:03.734365 ==
8937 13:39:03.737988 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 13:39:03.740982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 13:39:03.741082 ==
8940 13:39:03.741148
8941 13:39:03.741209
8942 13:39:03.744595 TX Vref Scan disable
8943 13:39:03.751145 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8944 13:39:03.751273 == TX Byte 0 ==
8945 13:39:03.754399 u2DelayCellOfst[0]=13 cells (4 PI)
8946 13:39:03.757755 u2DelayCellOfst[1]=10 cells (3 PI)
8947 13:39:03.761205 u2DelayCellOfst[2]=0 cells (0 PI)
8948 13:39:03.764594 u2DelayCellOfst[3]=3 cells (1 PI)
8949 13:39:03.767551 u2DelayCellOfst[4]=3 cells (1 PI)
8950 13:39:03.771105 u2DelayCellOfst[5]=16 cells (5 PI)
8951 13:39:03.774443 u2DelayCellOfst[6]=16 cells (5 PI)
8952 13:39:03.774559 u2DelayCellOfst[7]=3 cells (1 PI)
8953 13:39:03.780927 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8954 13:39:03.784286 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8955 13:39:03.784389 == TX Byte 1 ==
8956 13:39:03.787662 u2DelayCellOfst[8]=0 cells (0 PI)
8957 13:39:03.791219 u2DelayCellOfst[9]=3 cells (1 PI)
8958 13:39:03.794209 u2DelayCellOfst[10]=10 cells (3 PI)
8959 13:39:03.797621 u2DelayCellOfst[11]=3 cells (1 PI)
8960 13:39:03.801123 u2DelayCellOfst[12]=10 cells (3 PI)
8961 13:39:03.804054 u2DelayCellOfst[13]=16 cells (5 PI)
8962 13:39:03.807559 u2DelayCellOfst[14]=16 cells (5 PI)
8963 13:39:03.811113 u2DelayCellOfst[15]=16 cells (5 PI)
8964 13:39:03.814509 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8965 13:39:03.817680 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8966 13:39:03.821071 DramC Write-DBI on
8967 13:39:03.821157 ==
8968 13:39:03.824393 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 13:39:03.827715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 13:39:03.827803 ==
8971 13:39:03.827871
8972 13:39:03.827932
8973 13:39:03.831078 TX Vref Scan disable
8974 13:39:03.834453 == TX Byte 0 ==
8975 13:39:03.837825 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8976 13:39:03.841168 == TX Byte 1 ==
8977 13:39:03.844569 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8978 13:39:03.844660 DramC Write-DBI off
8979 13:39:03.844728
8980 13:39:03.847573 [DATLAT]
8981 13:39:03.847699 Freq=1600, CH1 RK1
8982 13:39:03.847801
8983 13:39:03.850898 DATLAT Default: 0xf
8984 13:39:03.851012 0, 0xFFFF, sum = 0
8985 13:39:03.854717 1, 0xFFFF, sum = 0
8986 13:39:03.854807 2, 0xFFFF, sum = 0
8987 13:39:03.857893 3, 0xFFFF, sum = 0
8988 13:39:03.857973 4, 0xFFFF, sum = 0
8989 13:39:03.861185 5, 0xFFFF, sum = 0
8990 13:39:03.861302 6, 0xFFFF, sum = 0
8991 13:39:03.864250 7, 0xFFFF, sum = 0
8992 13:39:03.864328 8, 0xFFFF, sum = 0
8993 13:39:03.867595 9, 0xFFFF, sum = 0
8994 13:39:03.867715 10, 0xFFFF, sum = 0
8995 13:39:03.870904 11, 0xFFFF, sum = 0
8996 13:39:03.874668 12, 0xFFFF, sum = 0
8997 13:39:03.874756 13, 0xFFFF, sum = 0
8998 13:39:03.877670 14, 0x0, sum = 1
8999 13:39:03.877765 15, 0x0, sum = 2
9000 13:39:03.877874 16, 0x0, sum = 3
9001 13:39:03.881241 17, 0x0, sum = 4
9002 13:39:03.881358 best_step = 15
9003 13:39:03.881450
9004 13:39:03.884651 ==
9005 13:39:03.884765 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 13:39:03.891124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 13:39:03.891222 ==
9008 13:39:03.891308 RX Vref Scan: 0
9009 13:39:03.891410
9010 13:39:03.894508 RX Vref 0 -> 0, step: 1
9011 13:39:03.894625
9012 13:39:03.897952 RX Delay 19 -> 252, step: 4
9013 13:39:03.901044 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9014 13:39:03.904458 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9015 13:39:03.907911 iDelay=195, Bit 2, Center 118 (71 ~ 166) 96
9016 13:39:03.914374 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9017 13:39:03.917837 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9018 13:39:03.921118 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9019 13:39:03.924538 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9020 13:39:03.927837 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9021 13:39:03.931207 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9022 13:39:03.937635 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9023 13:39:03.941163 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9024 13:39:03.944389 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9025 13:39:03.947865 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9026 13:39:03.954356 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9027 13:39:03.957812 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9028 13:39:03.961133 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9029 13:39:03.961221 ==
9030 13:39:03.964342 Dram Type= 6, Freq= 0, CH_1, rank 1
9031 13:39:03.967806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9032 13:39:03.967894 ==
9033 13:39:03.971184 DQS Delay:
9034 13:39:03.971289 DQS0 = 0, DQS1 = 0
9035 13:39:03.974175 DQM Delay:
9036 13:39:03.974259 DQM0 = 133, DQM1 = 130
9037 13:39:03.974325 DQ Delay:
9038 13:39:03.977560 DQ0 =136, DQ1 =130, DQ2 =118, DQ3 =130
9039 13:39:03.980908 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9040 13:39:03.987798 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9041 13:39:03.991321 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9042 13:39:03.991412
9043 13:39:03.991484
9044 13:39:03.991547
9045 13:39:03.994225 [DramC_TX_OE_Calibration] TA2
9046 13:39:03.997689 Original DQ_B0 (3 6) =30, OEN = 27
9047 13:39:04.000742 Original DQ_B1 (3 6) =30, OEN = 27
9048 13:39:04.000827 24, 0x0, End_B0=24 End_B1=24
9049 13:39:04.004142 25, 0x0, End_B0=25 End_B1=25
9050 13:39:04.007519 26, 0x0, End_B0=26 End_B1=26
9051 13:39:04.010858 27, 0x0, End_B0=27 End_B1=27
9052 13:39:04.010943 28, 0x0, End_B0=28 End_B1=28
9053 13:39:04.014124 29, 0x0, End_B0=29 End_B1=29
9054 13:39:04.017748 30, 0x0, End_B0=30 End_B1=30
9055 13:39:04.021071 31, 0x4141, End_B0=30 End_B1=30
9056 13:39:04.024031 Byte0 end_step=30 best_step=27
9057 13:39:04.027720 Byte1 end_step=30 best_step=27
9058 13:39:04.027805 Byte0 TX OE(2T, 0.5T) = (3, 3)
9059 13:39:04.030757 Byte1 TX OE(2T, 0.5T) = (3, 3)
9060 13:39:04.030841
9061 13:39:04.030907
9062 13:39:04.041076 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9063 13:39:04.041192 CH1 RK1: MR19=303, MR18=1B07
9064 13:39:04.047366 CH1_RK1: MR19=0x303, MR18=0x1B07, DQSOSC=396, MR23=63, INC=23, DEC=15
9065 13:39:04.050737 [RxdqsGatingPostProcess] freq 1600
9066 13:39:04.057759 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9067 13:39:04.061228 best DQS0 dly(2T, 0.5T) = (1, 1)
9068 13:39:04.064152 best DQS1 dly(2T, 0.5T) = (1, 1)
9069 13:39:04.067507 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9070 13:39:04.070747 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9071 13:39:04.070832 best DQS0 dly(2T, 0.5T) = (1, 1)
9072 13:39:04.074120 best DQS1 dly(2T, 0.5T) = (1, 1)
9073 13:39:04.077556 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9074 13:39:04.080833 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9075 13:39:04.084220 Pre-setting of DQS Precalculation
9076 13:39:04.090588 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9077 13:39:04.097641 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9078 13:39:04.104096 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 13:39:04.104192
9080 13:39:04.104259
9081 13:39:04.107625 [Calibration Summary] 3200 Mbps
9082 13:39:04.107712 CH 0, Rank 0
9083 13:39:04.111025 SW Impedance : PASS
9084 13:39:04.114001 DUTY Scan : NO K
9085 13:39:04.114090 ZQ Calibration : PASS
9086 13:39:04.117731 Jitter Meter : NO K
9087 13:39:04.120720 CBT Training : PASS
9088 13:39:04.120831 Write leveling : PASS
9089 13:39:04.124233 RX DQS gating : PASS
9090 13:39:04.127581 RX DQ/DQS(RDDQC) : PASS
9091 13:39:04.127665 TX DQ/DQS : PASS
9092 13:39:04.130894 RX DATLAT : PASS
9093 13:39:04.130983 RX DQ/DQS(Engine): PASS
9094 13:39:04.134293 TX OE : PASS
9095 13:39:04.134378 All Pass.
9096 13:39:04.134444
9097 13:39:04.137279 CH 0, Rank 1
9098 13:39:04.137433 SW Impedance : PASS
9099 13:39:04.140817 DUTY Scan : NO K
9100 13:39:04.144467 ZQ Calibration : PASS
9101 13:39:04.144547 Jitter Meter : NO K
9102 13:39:04.147715 CBT Training : PASS
9103 13:39:04.150891 Write leveling : PASS
9104 13:39:04.150968 RX DQS gating : PASS
9105 13:39:04.154156 RX DQ/DQS(RDDQC) : PASS
9106 13:39:04.157175 TX DQ/DQS : PASS
9107 13:39:04.157281 RX DATLAT : PASS
9108 13:39:04.160737 RX DQ/DQS(Engine): PASS
9109 13:39:04.164162 TX OE : PASS
9110 13:39:04.164243 All Pass.
9111 13:39:04.164308
9112 13:39:04.164369 CH 1, Rank 0
9113 13:39:04.167571 SW Impedance : PASS
9114 13:39:04.170939 DUTY Scan : NO K
9115 13:39:04.171018 ZQ Calibration : PASS
9116 13:39:04.173885 Jitter Meter : NO K
9117 13:39:04.177245 CBT Training : PASS
9118 13:39:04.177351 Write leveling : PASS
9119 13:39:04.180737 RX DQS gating : PASS
9120 13:39:04.180852 RX DQ/DQS(RDDQC) : PASS
9121 13:39:04.184049 TX DQ/DQS : PASS
9122 13:39:04.187485 RX DATLAT : PASS
9123 13:39:04.187565 RX DQ/DQS(Engine): PASS
9124 13:39:04.190927 TX OE : PASS
9125 13:39:04.191028 All Pass.
9126 13:39:04.191127
9127 13:39:04.194009 CH 1, Rank 1
9128 13:39:04.194087 SW Impedance : PASS
9129 13:39:04.197480 DUTY Scan : NO K
9130 13:39:04.200919 ZQ Calibration : PASS
9131 13:39:04.201015 Jitter Meter : NO K
9132 13:39:04.203872 CBT Training : PASS
9133 13:39:04.207304 Write leveling : PASS
9134 13:39:04.207400 RX DQS gating : PASS
9135 13:39:04.210764 RX DQ/DQS(RDDQC) : PASS
9136 13:39:04.214073 TX DQ/DQS : PASS
9137 13:39:04.214169 RX DATLAT : PASS
9138 13:39:04.217201 RX DQ/DQS(Engine): PASS
9139 13:39:04.220422 TX OE : PASS
9140 13:39:04.220513 All Pass.
9141 13:39:04.220580
9142 13:39:04.220641 DramC Write-DBI on
9143 13:39:04.223806 PER_BANK_REFRESH: Hybrid Mode
9144 13:39:04.227291 TX_TRACKING: ON
9145 13:39:04.234067 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9146 13:39:04.243841 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9147 13:39:04.250735 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9148 13:39:04.254105 [FAST_K] Save calibration result to emmc
9149 13:39:04.257425 sync common calibartion params.
9150 13:39:04.257514 sync cbt_mode0:1, 1:1
9151 13:39:04.260407 dram_init: ddr_geometry: 2
9152 13:39:04.263776 dram_init: ddr_geometry: 2
9153 13:39:04.267264 dram_init: ddr_geometry: 2
9154 13:39:04.267345 0:dram_rank_size:100000000
9155 13:39:04.270316 1:dram_rank_size:100000000
9156 13:39:04.276977 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9157 13:39:04.277079 DFS_SHUFFLE_HW_MODE: ON
9158 13:39:04.283601 dramc_set_vcore_voltage set vcore to 725000
9159 13:39:04.283699 Read voltage for 1600, 0
9160 13:39:04.286955 Vio18 = 0
9161 13:39:04.287036 Vcore = 725000
9162 13:39:04.287102 Vdram = 0
9163 13:39:04.287165 Vddq = 0
9164 13:39:04.290288 Vmddr = 0
9165 13:39:04.293837 switch to 3200 Mbps bootup
9166 13:39:04.293923 [DramcRunTimeConfig]
9167 13:39:04.293991 PHYPLL
9168 13:39:04.297221 DPM_CONTROL_AFTERK: ON
9169 13:39:04.297335 PER_BANK_REFRESH: ON
9170 13:39:04.300253 REFRESH_OVERHEAD_REDUCTION: ON
9171 13:39:04.303717 CMD_PICG_NEW_MODE: OFF
9172 13:39:04.303803 XRTWTW_NEW_MODE: ON
9173 13:39:04.307331 XRTRTR_NEW_MODE: ON
9174 13:39:04.307441 TX_TRACKING: ON
9175 13:39:04.310282 RDSEL_TRACKING: OFF
9176 13:39:04.313721 DQS Precalculation for DVFS: ON
9177 13:39:04.313816 RX_TRACKING: OFF
9178 13:39:04.317079 HW_GATING DBG: ON
9179 13:39:04.317165 ZQCS_ENABLE_LP4: ON
9180 13:39:04.320063 RX_PICG_NEW_MODE: ON
9181 13:39:04.323582 TX_PICG_NEW_MODE: ON
9182 13:39:04.323692 ENABLE_RX_DCM_DPHY: ON
9183 13:39:04.327217 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9184 13:39:04.330319 DUMMY_READ_FOR_TRACKING: OFF
9185 13:39:04.333872 !!! SPM_CONTROL_AFTERK: OFF
9186 13:39:04.334004 !!! SPM could not control APHY
9187 13:39:04.336781 IMPEDANCE_TRACKING: ON
9188 13:39:04.336868 TEMP_SENSOR: ON
9189 13:39:04.340528 HW_SAVE_FOR_SR: OFF
9190 13:39:04.343866 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9191 13:39:04.346769 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9192 13:39:04.350277 Read ODT Tracking: ON
9193 13:39:04.350389 Refresh Rate DeBounce: ON
9194 13:39:04.353718 DFS_NO_QUEUE_FLUSH: ON
9195 13:39:04.356977 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9196 13:39:04.360305 ENABLE_DFS_RUNTIME_MRW: OFF
9197 13:39:04.360394 DDR_RESERVE_NEW_MODE: ON
9198 13:39:04.363637 MR_CBT_SWITCH_FREQ: ON
9199 13:39:04.367104 =========================
9200 13:39:04.384391 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9201 13:39:04.387656 dram_init: ddr_geometry: 2
9202 13:39:04.406153 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9203 13:39:04.409654 dram_init: dram init end (result: 0)
9204 13:39:04.416152 DRAM-K: Full calibration passed in 24462 msecs
9205 13:39:04.419600 MRC: failed to locate region type 0.
9206 13:39:04.419730 DRAM rank0 size:0x100000000,
9207 13:39:04.422672 DRAM rank1 size=0x100000000
9208 13:39:04.432853 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9209 13:39:04.439592 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9210 13:39:04.446261 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9211 13:39:04.452825 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9212 13:39:04.455922 DRAM rank0 size:0x100000000,
9213 13:39:04.459368 DRAM rank1 size=0x100000000
9214 13:39:04.459453 CBMEM:
9215 13:39:04.462756 IMD: root @ 0xfffff000 254 entries.
9216 13:39:04.465911 IMD: root @ 0xffffec00 62 entries.
9217 13:39:04.469534 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9218 13:39:04.472608 WARNING: RO_VPD is uninitialized or empty.
9219 13:39:04.479111 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9220 13:39:04.486372 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9221 13:39:04.498740 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9222 13:39:04.510265 BS: romstage times (exec / console): total (unknown) / 23963 ms
9223 13:39:04.510380
9224 13:39:04.510447
9225 13:39:04.520579 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9226 13:39:04.523577 ARM64: Exception handlers installed.
9227 13:39:04.526926 ARM64: Testing exception
9228 13:39:04.530352 ARM64: Done test exception
9229 13:39:04.530440 Enumerating buses...
9230 13:39:04.533863 Show all devs... Before device enumeration.
9231 13:39:04.536770 Root Device: enabled 1
9232 13:39:04.540402 CPU_CLUSTER: 0: enabled 1
9233 13:39:04.540557 CPU: 00: enabled 1
9234 13:39:04.543598 Compare with tree...
9235 13:39:04.543761 Root Device: enabled 1
9236 13:39:04.547063 CPU_CLUSTER: 0: enabled 1
9237 13:39:04.550452 CPU: 00: enabled 1
9238 13:39:04.550545 Root Device scanning...
9239 13:39:04.553597 scan_static_bus for Root Device
9240 13:39:04.556915 CPU_CLUSTER: 0 enabled
9241 13:39:04.560491 scan_static_bus for Root Device done
9242 13:39:04.563749 scan_bus: bus Root Device finished in 8 msecs
9243 13:39:04.563834 done
9244 13:39:04.570355 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9245 13:39:04.573786 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9246 13:39:04.580248 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9247 13:39:04.583616 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9248 13:39:04.587058 Allocating resources...
9249 13:39:04.587151 Reading resources...
9250 13:39:04.593858 Root Device read_resources bus 0 link: 0
9251 13:39:04.593949 DRAM rank0 size:0x100000000,
9252 13:39:04.597199 DRAM rank1 size=0x100000000
9253 13:39:04.600075 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9254 13:39:04.603520 CPU: 00 missing read_resources
9255 13:39:04.606986 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9256 13:39:04.613427 Root Device read_resources bus 0 link: 0 done
9257 13:39:04.613513 Done reading resources.
9258 13:39:04.619887 Show resources in subtree (Root Device)...After reading.
9259 13:39:04.623337 Root Device child on link 0 CPU_CLUSTER: 0
9260 13:39:04.626777 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 13:39:04.636607 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 13:39:04.636708 CPU: 00
9263 13:39:04.640215 Root Device assign_resources, bus 0 link: 0
9264 13:39:04.643640 CPU_CLUSTER: 0 missing set_resources
9265 13:39:04.646652 Root Device assign_resources, bus 0 link: 0 done
9266 13:39:04.649939 Done setting resources.
9267 13:39:04.656666 Show resources in subtree (Root Device)...After assigning values.
9268 13:39:04.660170 Root Device child on link 0 CPU_CLUSTER: 0
9269 13:39:04.663198 CPU_CLUSTER: 0 child on link 0 CPU: 00
9270 13:39:04.673081 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9271 13:39:04.673191 CPU: 00
9272 13:39:04.676425 Done allocating resources.
9273 13:39:04.679781 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9274 13:39:04.683298 Enabling resources...
9275 13:39:04.683424 done.
9276 13:39:04.689774 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9277 13:39:04.689871 Initializing devices...
9278 13:39:04.693222 Root Device init
9279 13:39:04.693352 init hardware done!
9280 13:39:04.696582 0x00000018: ctrlr->caps
9281 13:39:04.699977 52.000 MHz: ctrlr->f_max
9282 13:39:04.700065 0.400 MHz: ctrlr->f_min
9283 13:39:04.703321 0x40ff8080: ctrlr->voltages
9284 13:39:04.703407 sclk: 390625
9285 13:39:04.706238 Bus Width = 1
9286 13:39:04.706323 sclk: 390625
9287 13:39:04.706390 Bus Width = 1
9288 13:39:04.709794 Early init status = 3
9289 13:39:04.713279 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9290 13:39:04.717883 in-header: 03 fc 00 00 01 00 00 00
9291 13:39:04.720956 in-data: 00
9292 13:39:04.724397 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9293 13:39:04.728863 in-header: 03 fd 00 00 00 00 00 00
9294 13:39:04.732321 in-data:
9295 13:39:04.735847 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9296 13:39:04.739278 in-header: 03 fc 00 00 01 00 00 00
9297 13:39:04.742364 in-data: 00
9298 13:39:04.745851 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9299 13:39:04.750287 in-header: 03 fd 00 00 00 00 00 00
9300 13:39:04.753791 in-data:
9301 13:39:04.757071 [SSUSB] Setting up USB HOST controller...
9302 13:39:04.760394 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9303 13:39:04.763448 [SSUSB] phy power-on done.
9304 13:39:04.766980 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9305 13:39:04.773794 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9306 13:39:04.776995 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9307 13:39:04.783660 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9308 13:39:04.790103 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9309 13:39:04.796615 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9310 13:39:04.803278 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9311 13:39:04.809853 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9312 13:39:04.813185 SPM: binary array size = 0x9dc
9313 13:39:04.816691 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9314 13:39:04.823275 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9315 13:39:04.829744 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9316 13:39:04.833376 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9317 13:39:04.839686 configure_display: Starting display init
9318 13:39:04.873626 anx7625_power_on_init: Init interface.
9319 13:39:04.876593 anx7625_disable_pd_protocol: Disabled PD feature.
9320 13:39:04.880183 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9321 13:39:04.908129 anx7625_start_dp_work: Secure OCM version=00
9322 13:39:04.911506 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9323 13:39:04.926246 sp_tx_get_edid_block: EDID Block = 1
9324 13:39:05.028686 Extracted contents:
9325 13:39:05.031661 header: 00 ff ff ff ff ff ff 00
9326 13:39:05.035206 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9327 13:39:05.038637 version: 01 04
9328 13:39:05.041587 basic params: 95 1f 11 78 0a
9329 13:39:05.045122 chroma info: 76 90 94 55 54 90 27 21 50 54
9330 13:39:05.048507 established: 00 00 00
9331 13:39:05.054895 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9332 13:39:05.058425 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9333 13:39:05.064861 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9334 13:39:05.071791 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9335 13:39:05.078364 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9336 13:39:05.081817 extensions: 00
9337 13:39:05.081921 checksum: fb
9338 13:39:05.082030
9339 13:39:05.084802 Manufacturer: IVO Model 57d Serial Number 0
9340 13:39:05.088272 Made week 0 of 2020
9341 13:39:05.088378 EDID version: 1.4
9342 13:39:05.091657 Digital display
9343 13:39:05.094985 6 bits per primary color channel
9344 13:39:05.095084 DisplayPort interface
9345 13:39:05.098331 Maximum image size: 31 cm x 17 cm
9346 13:39:05.101594 Gamma: 220%
9347 13:39:05.101686 Check DPMS levels
9348 13:39:05.104969 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9349 13:39:05.108284 First detailed timing is preferred timing
9350 13:39:05.111325 Established timings supported:
9351 13:39:05.114714 Standard timings supported:
9352 13:39:05.118006 Detailed timings
9353 13:39:05.121508 Hex of detail: 383680a07038204018303c0035ae10000019
9354 13:39:05.124813 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9355 13:39:05.131300 0780 0798 07c8 0820 hborder 0
9356 13:39:05.134799 0438 043b 0447 0458 vborder 0
9357 13:39:05.138236 -hsync -vsync
9358 13:39:05.138324 Did detailed timing
9359 13:39:05.141721 Hex of detail: 000000000000000000000000000000000000
9360 13:39:05.144606 Manufacturer-specified data, tag 0
9361 13:39:05.151501 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9362 13:39:05.151598 ASCII string: InfoVision
9363 13:39:05.158023 Hex of detail: 000000fe00523134304e574635205248200a
9364 13:39:05.161456 ASCII string: R140NWF5 RH
9365 13:39:05.161541 Checksum
9366 13:39:05.161605 Checksum: 0xfb (valid)
9367 13:39:05.168141 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9368 13:39:05.171569 DSI data_rate: 832800000 bps
9369 13:39:05.174875 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9370 13:39:05.181317 anx7625_parse_edid: pixelclock(138800).
9371 13:39:05.184420 hactive(1920), hsync(48), hfp(24), hbp(88)
9372 13:39:05.187808 vactive(1080), vsync(12), vfp(3), vbp(17)
9373 13:39:05.191241 anx7625_dsi_config: config dsi.
9374 13:39:05.197679 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9375 13:39:05.210792 anx7625_dsi_config: success to config DSI
9376 13:39:05.213753 anx7625_dp_start: MIPI phy setup OK.
9377 13:39:05.217187 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9378 13:39:05.220510 mtk_ddp_mode_set invalid vrefresh 60
9379 13:39:05.223866 main_disp_path_setup
9380 13:39:05.223950 ovl_layer_smi_id_en
9381 13:39:05.227234 ovl_layer_smi_id_en
9382 13:39:05.227320 ccorr_config
9383 13:39:05.227388 aal_config
9384 13:39:05.230598 gamma_config
9385 13:39:05.230681 postmask_config
9386 13:39:05.234040 dither_config
9387 13:39:05.237494 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9388 13:39:05.243794 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9389 13:39:05.247343 Root Device init finished in 551 msecs
9390 13:39:05.247428 CPU_CLUSTER: 0 init
9391 13:39:05.256961 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9392 13:39:05.260405 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9393 13:39:05.263968 APU_MBOX 0x190000b0 = 0x10001
9394 13:39:05.267313 APU_MBOX 0x190001b0 = 0x10001
9395 13:39:05.270233 APU_MBOX 0x190005b0 = 0x10001
9396 13:39:05.273805 APU_MBOX 0x190006b0 = 0x10001
9397 13:39:05.277030 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9398 13:39:05.289575 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9399 13:39:05.302187 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9400 13:39:05.308581 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9401 13:39:05.320292 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9402 13:39:05.329211 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9403 13:39:05.332570 CPU_CLUSTER: 0 init finished in 81 msecs
9404 13:39:05.336060 Devices initialized
9405 13:39:05.339536 Show all devs... After init.
9406 13:39:05.339620 Root Device: enabled 1
9407 13:39:05.342618 CPU_CLUSTER: 0: enabled 1
9408 13:39:05.346063 CPU: 00: enabled 1
9409 13:39:05.349517 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9410 13:39:05.352962 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9411 13:39:05.355886 ELOG: NV offset 0x57f000 size 0x1000
9412 13:39:05.362755 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9413 13:39:05.369642 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9414 13:39:05.372605 ELOG: Event(17) added with size 13 at 2024-05-28 13:37:55 UTC
9415 13:39:05.376100 out: cmd=0x121: 03 db 21 01 00 00 00 00
9416 13:39:05.380035 in-header: 03 97 00 00 2c 00 00 00
9417 13:39:05.393392 in-data: a8 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9418 13:39:05.400327 ELOG: Event(A1) added with size 10 at 2024-05-28 13:37:55 UTC
9419 13:39:05.406709 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9420 13:39:05.413273 ELOG: Event(A0) added with size 9 at 2024-05-28 13:37:55 UTC
9421 13:39:05.417083 elog_add_boot_reason: Logged dev mode boot
9422 13:39:05.419913 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9423 13:39:05.423602 Finalize devices...
9424 13:39:05.423685 Devices finalized
9425 13:39:05.430039 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9426 13:39:05.433419 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9427 13:39:05.436653 in-header: 03 07 00 00 08 00 00 00
9428 13:39:05.440147 in-data: aa e4 47 04 13 02 00 00
9429 13:39:05.443130 Chrome EC: UHEPI supported
9430 13:39:05.449714 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9431 13:39:05.453194 in-header: 03 a9 00 00 08 00 00 00
9432 13:39:05.456772 in-data: 84 60 60 08 00 00 00 00
9433 13:39:05.459752 ELOG: Event(91) added with size 10 at 2024-05-28 13:37:56 UTC
9434 13:39:05.466252 ELOG: Event(16) added with size 11 at 2024-05-28 13:37:56 UTC
9435 13:39:05.549742 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9436 13:39:05.552720 Chrome EC: clear events_b mask to 0x0000000020004000
9437 13:39:05.559286 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9438 13:39:05.564237 in-header: 03 fd 00 00 00 00 00 00
9439 13:39:05.567362 in-data:
9440 13:39:05.570801 BS: BS_WRITE_TABLES entry times (exec / console): 81 / 56 ms
9441 13:39:05.574191 Writing coreboot table at 0xffe64000
9442 13:39:05.577260 0. 000000000010a000-0000000000113fff: RAMSTAGE
9443 13:39:05.583777 1. 0000000040000000-00000000400fffff: RAM
9444 13:39:05.587294 2. 0000000040100000-000000004032afff: RAMSTAGE
9445 13:39:05.590613 3. 000000004032b000-00000000545fffff: RAM
9446 13:39:05.593852 4. 0000000054600000-000000005465ffff: BL31
9447 13:39:05.597402 5. 0000000054660000-00000000ffe63fff: RAM
9448 13:39:05.604070 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9449 13:39:05.607535 7. 0000000100000000-000000023fffffff: RAM
9450 13:39:05.610528 Passing 5 GPIOs to payload:
9451 13:39:05.614029 NAME | PORT | POLARITY | VALUE
9452 13:39:05.620310 EC in RW | 0x000000aa | low | undefined
9453 13:39:05.623787 EC interrupt | 0x00000005 | low | undefined
9454 13:39:05.627308 TPM interrupt | 0x000000ab | high | undefined
9455 13:39:05.633682 SD card detect | 0x00000011 | high | undefined
9456 13:39:05.636859 speaker enable | 0x00000093 | high | undefined
9457 13:39:05.640381 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9458 13:39:05.643586 in-header: 03 f9 00 00 02 00 00 00
9459 13:39:05.646823 in-data: 02 00
9460 13:39:05.650495 ADC[4]: Raw value=901401 ID=7
9461 13:39:05.650580 ADC[3]: Raw value=212810 ID=1
9462 13:39:05.653684 RAM Code: 0x71
9463 13:39:05.656913 ADC[6]: Raw value=74502 ID=0
9464 13:39:05.656995 ADC[5]: Raw value=211703 ID=1
9465 13:39:05.660340 SKU Code: 0x1
9466 13:39:05.663773 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f33f
9467 13:39:05.666814 coreboot table: 964 bytes.
9468 13:39:05.670220 IMD ROOT 0. 0xfffff000 0x00001000
9469 13:39:05.673651 IMD SMALL 1. 0xffffe000 0x00001000
9470 13:39:05.677081 RO MCACHE 2. 0xffffc000 0x00001104
9471 13:39:05.680586 CONSOLE 3. 0xfff7c000 0x00080000
9472 13:39:05.683523 FMAP 4. 0xfff7b000 0x00000452
9473 13:39:05.687045 TIME STAMP 5. 0xfff7a000 0x00000910
9474 13:39:05.690063 VBOOT WORK 6. 0xfff66000 0x00014000
9475 13:39:05.693589 RAMOOPS 7. 0xffe66000 0x00100000
9476 13:39:05.696716 COREBOOT 8. 0xffe64000 0x00002000
9477 13:39:05.700237 IMD small region:
9478 13:39:05.703643 IMD ROOT 0. 0xffffec00 0x00000400
9479 13:39:05.706717 VPD 1. 0xffffeb80 0x0000006c
9480 13:39:05.710278 MMC STATUS 2. 0xffffeb60 0x00000004
9481 13:39:05.713239 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9482 13:39:05.720179 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9483 13:39:05.761007 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9484 13:39:05.764139 Checking segment from ROM address 0x40100000
9485 13:39:05.767425 Checking segment from ROM address 0x4010001c
9486 13:39:05.773856 Loading segment from ROM address 0x40100000
9487 13:39:05.773985 code (compression=0)
9488 13:39:05.784275 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9489 13:39:05.790678 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9490 13:39:05.790775 it's not compressed!
9491 13:39:05.797115 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9492 13:39:05.803760 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9493 13:39:05.821168 Loading segment from ROM address 0x4010001c
9494 13:39:05.821272 Entry Point 0x80000000
9495 13:39:05.824496 Loaded segments
9496 13:39:05.827522 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9497 13:39:05.834591 Jumping to boot code at 0x80000000(0xffe64000)
9498 13:39:05.841057 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9499 13:39:05.847374 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9500 13:39:05.855786 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9501 13:39:05.858693 Checking segment from ROM address 0x40100000
9502 13:39:05.862289 Checking segment from ROM address 0x4010001c
9503 13:39:05.868688 Loading segment from ROM address 0x40100000
9504 13:39:05.868778 code (compression=1)
9505 13:39:05.875655 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9506 13:39:05.885352 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9507 13:39:05.885453 using LZMA
9508 13:39:05.893876 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9509 13:39:05.900735 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9510 13:39:05.904103 Loading segment from ROM address 0x4010001c
9511 13:39:05.904190 Entry Point 0x54601000
9512 13:39:05.907417 Loaded segments
9513 13:39:05.910719 NOTICE: MT8192 bl31_setup
9514 13:39:05.917857 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9515 13:39:05.920839 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9516 13:39:05.924224 WARNING: region 0:
9517 13:39:05.927634 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 13:39:05.927723 WARNING: region 1:
9519 13:39:05.934301 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9520 13:39:05.937268 WARNING: region 2:
9521 13:39:05.940759 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9522 13:39:05.944285 WARNING: region 3:
9523 13:39:05.947659 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9524 13:39:05.950976 WARNING: region 4:
9525 13:39:05.957684 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9526 13:39:05.957801 WARNING: region 5:
9527 13:39:05.961043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 13:39:05.964105 WARNING: region 6:
9529 13:39:05.967633 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 13:39:05.967748 WARNING: region 7:
9531 13:39:05.974443 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 13:39:05.980981 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9533 13:39:05.984315 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9534 13:39:05.987587 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9535 13:39:05.994351 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9536 13:39:05.997289 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9537 13:39:06.000804 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9538 13:39:06.007511 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9539 13:39:06.010793 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9540 13:39:06.017686 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9541 13:39:06.020628 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9542 13:39:06.024052 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9543 13:39:06.030850 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9544 13:39:06.034333 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9545 13:39:06.037293 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9546 13:39:06.044291 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9547 13:39:06.047340 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9548 13:39:06.054011 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9549 13:39:06.057257 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9550 13:39:06.060796 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9551 13:39:06.067351 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9552 13:39:06.070372 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9553 13:39:06.073815 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9554 13:39:06.080811 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9555 13:39:06.083777 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9556 13:39:06.090403 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9557 13:39:06.093626 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9558 13:39:06.096928 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9559 13:39:06.103858 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9560 13:39:06.107114 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9561 13:39:06.113859 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9562 13:39:06.117101 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9563 13:39:06.120593 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9564 13:39:06.127104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9565 13:39:06.130524 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9566 13:39:06.133961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9567 13:39:06.137400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9568 13:39:06.143875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9569 13:39:06.147363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9570 13:39:06.150807 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9571 13:39:06.153795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9572 13:39:06.160669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9573 13:39:06.163668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9574 13:39:06.166958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9575 13:39:06.170437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9576 13:39:06.177251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9577 13:39:06.180780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9578 13:39:06.183711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9579 13:39:06.187242 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9580 13:39:06.193971 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9581 13:39:06.197225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9582 13:39:06.203888 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9583 13:39:06.207446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9584 13:39:06.213645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9585 13:39:06.217171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9586 13:39:06.220346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9587 13:39:06.227264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9588 13:39:06.230304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9589 13:39:06.237049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9590 13:39:06.240678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9591 13:39:06.247172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9592 13:39:06.250316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9593 13:39:06.253848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9594 13:39:06.260633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9595 13:39:06.263981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9596 13:39:06.270315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9597 13:39:06.273715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9598 13:39:06.280221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9599 13:39:06.283631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9600 13:39:06.287115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9601 13:39:06.293602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9602 13:39:06.297190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9603 13:39:06.303661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9604 13:39:06.307002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9605 13:39:06.313519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9606 13:39:06.316933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9607 13:39:06.320382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9608 13:39:06.327067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9609 13:39:06.330571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9610 13:39:06.336877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9611 13:39:06.340385 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9612 13:39:06.346966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9613 13:39:06.350478 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9614 13:39:06.357167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9615 13:39:06.360546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9616 13:39:06.363558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9617 13:39:06.370392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9618 13:39:06.373988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9619 13:39:06.380798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9620 13:39:06.383692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9621 13:39:06.387214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9622 13:39:06.393641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9623 13:39:06.397164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9624 13:39:06.403718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9625 13:39:06.407160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9626 13:39:06.413576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9627 13:39:06.417021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9628 13:39:06.420013 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9629 13:39:06.426848 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9630 13:39:06.430058 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9631 13:39:06.433448 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9632 13:39:06.437182 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9633 13:39:06.443681 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9634 13:39:06.447308 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9635 13:39:06.453936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9636 13:39:06.456886 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9637 13:39:06.460406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9638 13:39:06.467260 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9639 13:39:06.470655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9640 13:39:06.476971 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9641 13:39:06.480285 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9642 13:39:06.483699 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9643 13:39:06.490396 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9644 13:39:06.493833 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9645 13:39:06.500240 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9646 13:39:06.503678 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9647 13:39:06.507296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9648 13:39:06.510205 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9649 13:39:06.516963 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9650 13:39:06.520459 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9651 13:39:06.523444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9652 13:39:06.530534 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9653 13:39:06.533665 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9654 13:39:06.537111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9655 13:39:06.540325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9656 13:39:06.547226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9657 13:39:06.550199 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9658 13:39:06.557265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9659 13:39:06.560192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9660 13:39:06.563647 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9661 13:39:06.570264 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9662 13:39:06.573568 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9663 13:39:06.580072 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9664 13:39:06.583554 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9665 13:39:06.586811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9666 13:39:06.593359 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9667 13:39:06.596806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9668 13:39:06.603806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9669 13:39:06.606900 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9670 13:39:06.610497 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9671 13:39:06.616720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9672 13:39:06.620387 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9673 13:39:06.623716 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9674 13:39:06.630082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9675 13:39:06.633554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9676 13:39:06.640197 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9677 13:39:06.643481 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9678 13:39:06.646869 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9679 13:39:06.653424 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9680 13:39:06.656862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9681 13:39:06.663931 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9682 13:39:06.666839 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9683 13:39:06.670331 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9684 13:39:06.676982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9685 13:39:06.680294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9686 13:39:06.683683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9687 13:39:06.690481 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9688 13:39:06.693806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9689 13:39:06.700181 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9690 13:39:06.703534 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9691 13:39:06.706881 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9692 13:39:06.713690 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9693 13:39:06.717031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9694 13:39:06.719983 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9695 13:39:06.727173 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9696 13:39:06.730546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9697 13:39:06.736986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9698 13:39:06.739985 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9699 13:39:06.743513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9700 13:39:06.750317 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9701 13:39:06.753688 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9702 13:39:06.760150 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9703 13:39:06.763758 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9704 13:39:06.766744 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9705 13:39:06.773653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9706 13:39:06.776619 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9707 13:39:06.783591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9708 13:39:06.787027 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9709 13:39:06.789970 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9710 13:39:06.796630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9711 13:39:06.799975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9712 13:39:06.803569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9713 13:39:06.809995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9714 13:39:06.813382 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9715 13:39:06.820011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9716 13:39:06.823698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9717 13:39:06.826527 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9718 13:39:06.833321 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9719 13:39:06.836914 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9720 13:39:06.843611 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9721 13:39:06.846973 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9722 13:39:06.849962 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9723 13:39:06.856828 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9724 13:39:06.860253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9725 13:39:06.866811 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9726 13:39:06.870413 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9727 13:39:06.873767 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9728 13:39:06.880165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9729 13:39:06.883601 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9730 13:39:06.890281 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9731 13:39:06.893763 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9732 13:39:06.896694 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9733 13:39:06.903551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9734 13:39:06.906863 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9735 13:39:06.913293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9736 13:39:06.916807 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9737 13:39:06.923271 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9738 13:39:06.926668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9739 13:39:06.930144 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9740 13:39:06.936484 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9741 13:39:06.939549 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9742 13:39:06.946567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9743 13:39:06.949860 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9744 13:39:06.956540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9745 13:39:06.959700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9746 13:39:06.963039 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9747 13:39:06.969841 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9748 13:39:06.973270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9749 13:39:06.979679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9750 13:39:06.983172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9751 13:39:06.986689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9752 13:39:06.993001 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9753 13:39:06.996583 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9754 13:39:07.003295 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9755 13:39:07.006773 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9756 13:39:07.009838 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9757 13:39:07.016702 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9758 13:39:07.020243 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9759 13:39:07.026705 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9760 13:39:07.030156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9761 13:39:07.033224 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9762 13:39:07.036556 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9763 13:39:07.043346 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9764 13:39:07.046937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9765 13:39:07.049878 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9766 13:39:07.053266 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9767 13:39:07.060133 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9768 13:39:07.063492 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9769 13:39:07.069942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9770 13:39:07.073491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9771 13:39:07.076556 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9772 13:39:07.083482 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9773 13:39:07.086486 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9774 13:39:07.089951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9775 13:39:07.096766 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9776 13:39:07.165242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9777 13:39:07.165401 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9778 13:39:07.165482 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9779 13:39:07.165557 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9780 13:39:07.165621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9781 13:39:07.165682 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9782 13:39:07.165742 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9783 13:39:07.165800 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9784 13:39:07.165857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9785 13:39:07.165914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9786 13:39:07.165971 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9787 13:39:07.166045 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9788 13:39:07.166105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9789 13:39:07.166162 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9790 13:39:07.166218 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9791 13:39:07.166473 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9792 13:39:07.173238 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9793 13:39:07.176805 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9794 13:39:07.183259 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9795 13:39:07.186824 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9796 13:39:07.189837 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9797 13:39:07.196743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9798 13:39:07.200094 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9799 13:39:07.203229 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9800 13:39:07.210093 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9801 13:39:07.213513 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9802 13:39:07.216282 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9803 13:39:07.219750 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9804 13:39:07.226727 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9805 13:39:07.229681 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9806 13:39:07.233264 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9807 13:39:07.236273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9808 13:39:07.243376 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9809 13:39:07.246644 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9810 13:39:07.249937 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9811 13:39:07.253252 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9812 13:39:07.259739 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9813 13:39:07.263293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9814 13:39:07.266464 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9815 13:39:07.273354 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9816 13:39:07.276362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9817 13:39:07.282932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9818 13:39:07.286254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9819 13:39:07.289760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9820 13:39:07.296662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9821 13:39:07.299726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9822 13:39:07.303176 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9823 13:39:07.309750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9824 13:39:07.312918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9825 13:39:07.319799 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9826 13:39:07.323311 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9827 13:39:07.329658 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9828 13:39:07.332829 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9829 13:39:07.336458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9830 13:39:07.343072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9831 13:39:07.346432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9832 13:39:07.353257 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9833 13:39:07.356283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9834 13:39:07.359694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9835 13:39:07.366154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9836 13:39:07.369574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9837 13:39:07.376433 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9838 13:39:07.379277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9839 13:39:07.382973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9840 13:39:07.389312 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9841 13:39:07.392781 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9842 13:39:07.399637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9843 13:39:07.402677 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9844 13:39:07.409143 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9845 13:39:07.412937 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9846 13:39:07.415973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9847 13:39:07.422596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9848 13:39:07.426130 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9849 13:39:07.432704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9850 13:39:07.435871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9851 13:39:07.439389 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9852 13:39:07.445759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9853 13:39:07.449272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9854 13:39:07.455926 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9855 13:39:07.459393 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9856 13:39:07.462788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9857 13:39:07.469200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9858 13:39:07.472778 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9859 13:39:07.479018 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9860 13:39:07.482524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9861 13:39:07.486041 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9862 13:39:07.492663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9863 13:39:07.495640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9864 13:39:07.502523 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9865 13:39:07.505598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9866 13:39:07.509191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9867 13:39:07.515800 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9868 13:39:07.518918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9869 13:39:07.525917 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9870 13:39:07.529438 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9871 13:39:07.532323 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9872 13:39:07.539358 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9873 13:39:07.542659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9874 13:39:07.549283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9875 13:39:07.552471 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9876 13:39:07.559108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9877 13:39:07.562495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9878 13:39:07.565858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9879 13:39:07.572500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9880 13:39:07.575656 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9881 13:39:07.579296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9882 13:39:07.585711 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9883 13:39:07.589166 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9884 13:39:07.596137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9885 13:39:07.599182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9886 13:39:07.602722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9887 13:39:07.609189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9888 13:39:07.612632 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9889 13:39:07.619106 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9890 13:39:07.622623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9891 13:39:07.629259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9892 13:39:07.632777 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9893 13:39:07.636122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9894 13:39:07.642626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9895 13:39:07.645614 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9896 13:39:07.652368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9897 13:39:07.655889 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9898 13:39:07.662436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9899 13:39:07.665461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9900 13:39:07.672266 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9901 13:39:07.675771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9902 13:39:07.679383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9903 13:39:07.685572 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9904 13:39:07.689422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9905 13:39:07.695762 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9906 13:39:07.698849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9907 13:39:07.705633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9908 13:39:07.709148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9909 13:39:07.712160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9910 13:39:07.718779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9911 13:39:07.722416 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9912 13:39:07.728775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9913 13:39:07.732211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9914 13:39:07.739001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9915 13:39:07.742022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9916 13:39:07.748994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9917 13:39:07.752063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9918 13:39:07.755746 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9919 13:39:07.762233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9920 13:39:07.765661 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9921 13:39:07.772164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9922 13:39:07.775523 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9923 13:39:07.778981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9924 13:39:07.785639 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9925 13:39:07.788762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9926 13:39:07.795610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9927 13:39:07.799037 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9928 13:39:07.805654 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9929 13:39:07.808663 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9930 13:39:07.812286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9931 13:39:07.818825 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9932 13:39:07.822392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9933 13:39:07.828980 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9934 13:39:07.832325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9935 13:39:07.835916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9936 13:39:07.842257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9937 13:39:07.845522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9938 13:39:07.852382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9939 13:39:07.855837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9940 13:39:07.862074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9941 13:39:07.865536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9942 13:39:07.872339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9943 13:39:07.875363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9944 13:39:07.882297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9945 13:39:07.885392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9946 13:39:07.891815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9947 13:39:07.895359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9948 13:39:07.901942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9949 13:39:07.905402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9950 13:39:07.912297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9951 13:39:07.915222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9952 13:39:07.921762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9953 13:39:07.925215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9954 13:39:07.932097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9955 13:39:07.935386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9956 13:39:07.941847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9957 13:39:07.945185 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9958 13:39:07.951793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9959 13:39:07.955306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9960 13:39:07.961865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9961 13:39:07.964929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9962 13:39:07.971430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9963 13:39:07.974806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9964 13:39:07.981896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9965 13:39:07.984904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9966 13:39:07.988401 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9967 13:39:07.991400 INFO: [APUAPC] vio 0
9968 13:39:07.994708 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9969 13:39:08.001673 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9970 13:39:08.005224 INFO: [APUAPC] D0_APC_0: 0x400510
9971 13:39:08.008688 INFO: [APUAPC] D0_APC_1: 0x0
9972 13:39:08.012157 INFO: [APUAPC] D0_APC_2: 0x1540
9973 13:39:08.012270 INFO: [APUAPC] D0_APC_3: 0x0
9974 13:39:08.015219 INFO: [APUAPC] D1_APC_0: 0xffffffff
9975 13:39:08.018729 INFO: [APUAPC] D1_APC_1: 0xffffffff
9976 13:39:08.022215 INFO: [APUAPC] D1_APC_2: 0x3fffff
9977 13:39:08.025281 INFO: [APUAPC] D1_APC_3: 0x0
9978 13:39:08.028841 INFO: [APUAPC] D2_APC_0: 0xffffffff
9979 13:39:08.031837 INFO: [APUAPC] D2_APC_1: 0xffffffff
9980 13:39:08.035332 INFO: [APUAPC] D2_APC_2: 0x3fffff
9981 13:39:08.038343 INFO: [APUAPC] D2_APC_3: 0x0
9982 13:39:08.041812 INFO: [APUAPC] D3_APC_0: 0xffffffff
9983 13:39:08.045464 INFO: [APUAPC] D3_APC_1: 0xffffffff
9984 13:39:08.048476 INFO: [APUAPC] D3_APC_2: 0x3fffff
9985 13:39:08.052017 INFO: [APUAPC] D3_APC_3: 0x0
9986 13:39:08.055507 INFO: [APUAPC] D4_APC_0: 0xffffffff
9987 13:39:08.058548 INFO: [APUAPC] D4_APC_1: 0xffffffff
9988 13:39:08.062072 INFO: [APUAPC] D4_APC_2: 0x3fffff
9989 13:39:08.065220 INFO: [APUAPC] D4_APC_3: 0x0
9990 13:39:08.068811 INFO: [APUAPC] D5_APC_0: 0xffffffff
9991 13:39:08.072394 INFO: [APUAPC] D5_APC_1: 0xffffffff
9992 13:39:08.075406 INFO: [APUAPC] D5_APC_2: 0x3fffff
9993 13:39:08.078932 INFO: [APUAPC] D5_APC_3: 0x0
9994 13:39:08.082197 INFO: [APUAPC] D6_APC_0: 0xffffffff
9995 13:39:08.085274 INFO: [APUAPC] D6_APC_1: 0xffffffff
9996 13:39:08.088724 INFO: [APUAPC] D6_APC_2: 0x3fffff
9997 13:39:08.092258 INFO: [APUAPC] D6_APC_3: 0x0
9998 13:39:08.095274 INFO: [APUAPC] D7_APC_0: 0xffffffff
9999 13:39:08.098394 INFO: [APUAPC] D7_APC_1: 0xffffffff
10000 13:39:08.101830 INFO: [APUAPC] D7_APC_2: 0x3fffff
10001 13:39:08.105115 INFO: [APUAPC] D7_APC_3: 0x0
10002 13:39:08.108577 INFO: [APUAPC] D8_APC_0: 0xffffffff
10003 13:39:08.112014 INFO: [APUAPC] D8_APC_1: 0xffffffff
10004 13:39:08.115149 INFO: [APUAPC] D8_APC_2: 0x3fffff
10005 13:39:08.118586 INFO: [APUAPC] D8_APC_3: 0x0
10006 13:39:08.122054 INFO: [APUAPC] D9_APC_0: 0xffffffff
10007 13:39:08.125258 INFO: [APUAPC] D9_APC_1: 0xffffffff
10008 13:39:08.128724 INFO: [APUAPC] D9_APC_2: 0x3fffff
10009 13:39:08.131801 INFO: [APUAPC] D9_APC_3: 0x0
10010 13:39:08.135358 INFO: [APUAPC] D10_APC_0: 0xffffffff
10011 13:39:08.138404 INFO: [APUAPC] D10_APC_1: 0xffffffff
10012 13:39:08.141990 INFO: [APUAPC] D10_APC_2: 0x3fffff
10013 13:39:08.145024 INFO: [APUAPC] D10_APC_3: 0x0
10014 13:39:08.148481 INFO: [APUAPC] D11_APC_0: 0xffffffff
10015 13:39:08.152034 INFO: [APUAPC] D11_APC_1: 0xffffffff
10016 13:39:08.155032 INFO: [APUAPC] D11_APC_2: 0x3fffff
10017 13:39:08.158408 INFO: [APUAPC] D11_APC_3: 0x0
10018 13:39:08.161825 INFO: [APUAPC] D12_APC_0: 0xffffffff
10019 13:39:08.164989 INFO: [APUAPC] D12_APC_1: 0xffffffff
10020 13:39:08.168605 INFO: [APUAPC] D12_APC_2: 0x3fffff
10021 13:39:08.171645 INFO: [APUAPC] D12_APC_3: 0x0
10022 13:39:08.175348 INFO: [APUAPC] D13_APC_0: 0xffffffff
10023 13:39:08.178333 INFO: [APUAPC] D13_APC_1: 0xffffffff
10024 13:39:08.181996 INFO: [APUAPC] D13_APC_2: 0x3fffff
10025 13:39:08.184978 INFO: [APUAPC] D13_APC_3: 0x0
10026 13:39:08.188571 INFO: [APUAPC] D14_APC_0: 0xffffffff
10027 13:39:08.191524 INFO: [APUAPC] D14_APC_1: 0xffffffff
10028 13:39:08.194954 INFO: [APUAPC] D14_APC_2: 0x3fffff
10029 13:39:08.198367 INFO: [APUAPC] D14_APC_3: 0x0
10030 13:39:08.201882 INFO: [APUAPC] D15_APC_0: 0xffffffff
10031 13:39:08.205270 INFO: [APUAPC] D15_APC_1: 0xffffffff
10032 13:39:08.208612 INFO: [APUAPC] D15_APC_2: 0x3fffff
10033 13:39:08.212008 INFO: [APUAPC] D15_APC_3: 0x0
10034 13:39:08.212094 INFO: [APUAPC] APC_CON: 0x4
10035 13:39:08.215303 INFO: [NOCDAPC] D0_APC_0: 0x0
10036 13:39:08.218301 INFO: [NOCDAPC] D0_APC_1: 0x0
10037 13:39:08.221793 INFO: [NOCDAPC] D1_APC_0: 0x0
10038 13:39:08.225506 INFO: [NOCDAPC] D1_APC_1: 0xfff
10039 13:39:08.228433 INFO: [NOCDAPC] D2_APC_0: 0x0
10040 13:39:08.231559 INFO: [NOCDAPC] D2_APC_1: 0xfff
10041 13:39:08.235240 INFO: [NOCDAPC] D3_APC_0: 0x0
10042 13:39:08.238400 INFO: [NOCDAPC] D3_APC_1: 0xfff
10043 13:39:08.241853 INFO: [NOCDAPC] D4_APC_0: 0x0
10044 13:39:08.241966 INFO: [NOCDAPC] D4_APC_1: 0xfff
10045 13:39:08.245018 INFO: [NOCDAPC] D5_APC_0: 0x0
10046 13:39:08.248346 INFO: [NOCDAPC] D5_APC_1: 0xfff
10047 13:39:08.251446 INFO: [NOCDAPC] D6_APC_0: 0x0
10048 13:39:08.254941 INFO: [NOCDAPC] D6_APC_1: 0xfff
10049 13:39:08.258538 INFO: [NOCDAPC] D7_APC_0: 0x0
10050 13:39:08.261563 INFO: [NOCDAPC] D7_APC_1: 0xfff
10051 13:39:08.265004 INFO: [NOCDAPC] D8_APC_0: 0x0
10052 13:39:08.268138 INFO: [NOCDAPC] D8_APC_1: 0xfff
10053 13:39:08.271694 INFO: [NOCDAPC] D9_APC_0: 0x0
10054 13:39:08.275225 INFO: [NOCDAPC] D9_APC_1: 0xfff
10055 13:39:08.275339 INFO: [NOCDAPC] D10_APC_0: 0x0
10056 13:39:08.278218 INFO: [NOCDAPC] D10_APC_1: 0xfff
10057 13:39:08.281765 INFO: [NOCDAPC] D11_APC_0: 0x0
10058 13:39:08.285142 INFO: [NOCDAPC] D11_APC_1: 0xfff
10059 13:39:08.288198 INFO: [NOCDAPC] D12_APC_0: 0x0
10060 13:39:08.291406 INFO: [NOCDAPC] D12_APC_1: 0xfff
10061 13:39:08.294955 INFO: [NOCDAPC] D13_APC_0: 0x0
10062 13:39:08.298573 INFO: [NOCDAPC] D13_APC_1: 0xfff
10063 13:39:08.301604 INFO: [NOCDAPC] D14_APC_0: 0x0
10064 13:39:08.305017 INFO: [NOCDAPC] D14_APC_1: 0xfff
10065 13:39:08.308142 INFO: [NOCDAPC] D15_APC_0: 0x0
10066 13:39:08.311517 INFO: [NOCDAPC] D15_APC_1: 0xfff
10067 13:39:08.314939 INFO: [NOCDAPC] APC_CON: 0x4
10068 13:39:08.318456 INFO: [APUAPC] set_apusys_apc done
10069 13:39:08.318543 INFO: [DEVAPC] devapc_init done
10070 13:39:08.324925 INFO: GICv3 without legacy support detected.
10071 13:39:08.328470 INFO: ARM GICv3 driver initialized in EL3
10072 13:39:08.331497 INFO: Maximum SPI INTID supported: 639
10073 13:39:08.335089 INFO: BL31: Initializing runtime services
10074 13:39:08.341771 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10075 13:39:08.344861 INFO: SPM: enable CPC mode
10076 13:39:08.348466 INFO: mcdi ready for mcusys-off-idle and system suspend
10077 13:39:08.354900 INFO: BL31: Preparing for EL3 exit to normal world
10078 13:39:08.358480 INFO: Entry point address = 0x80000000
10079 13:39:08.358607 INFO: SPSR = 0x8
10080 13:39:08.365517
10081 13:39:08.365643
10082 13:39:08.365761
10083 13:39:08.368817 Starting depthcharge on Spherion...
10084 13:39:08.368939
10085 13:39:08.369051 Wipe memory regions:
10086 13:39:08.369159
10087 13:39:08.369949 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10088 13:39:08.370108 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10089 13:39:08.370246 Setting prompt string to ['asurada:']
10090 13:39:08.370384 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10091 13:39:08.372042 [0x00000040000000, 0x00000054600000)
10092 13:39:08.494374
10093 13:39:08.494559 [0x00000054660000, 0x00000080000000)
10094 13:39:08.755165
10095 13:39:08.755312 [0x000000821a7280, 0x000000ffe64000)
10096 13:39:09.498831
10097 13:39:09.499013 [0x00000100000000, 0x00000240000000)
10098 13:39:11.388068
10099 13:39:11.391470 Initializing XHCI USB controller at 0x11200000.
10100 13:39:12.429584
10101 13:39:12.432446 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10102 13:39:12.432544
10103 13:39:12.432618
10104 13:39:12.432912 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 13:39:12.533237 asurada: tftpboot 192.168.201.1 14063028/tftp-deploy-13dlhag1/kernel/image.itb 14063028/tftp-deploy-13dlhag1/kernel/cmdline
10107 13:39:12.533463 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10108 13:39:12.533587 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10109 13:39:12.537898 tftpboot 192.168.201.1 14063028/tftp-deploy-13dlhag1/kernel/image.ittp-deploy-13dlhag1/kernel/cmdline
10110 13:39:12.537995
10111 13:39:12.538064 Waiting for link
10112 13:39:12.696373
10113 13:39:12.696548 R8152: Initializing
10114 13:39:12.696651
10115 13:39:12.699147 Version 9 (ocp_data = 6010)
10116 13:39:12.699235
10117 13:39:12.702548 R8152: Done initializing
10118 13:39:12.702654
10119 13:39:12.702747 Adding net device
10120 13:39:14.650576
10121 13:39:14.650712 done.
10122 13:39:14.650781
10123 13:39:14.650843 MAC: 00:e0:4c:72:2d:d6
10124 13:39:14.650903
10125 13:39:14.654337 Sending DHCP discover... done.
10126 13:39:14.654432
10127 13:39:14.657666 Waiting for reply... done.
10128 13:39:14.657748
10129 13:39:14.660832 Sending DHCP request... done.
10130 13:39:14.660913
10131 13:39:14.660979 Waiting for reply... done.
10132 13:39:14.661042
10133 13:39:14.664118 My ip is 192.168.201.21
10134 13:39:14.664191
10135 13:39:14.667337 The DHCP server ip is 192.168.201.1
10136 13:39:14.667440
10137 13:39:14.670597 TFTP server IP predefined by user: 192.168.201.1
10138 13:39:14.670671
10139 13:39:14.677317 Bootfile predefined by user: 14063028/tftp-deploy-13dlhag1/kernel/image.itb
10140 13:39:14.677411
10141 13:39:14.680415 Sending tftp read request... done.
10142 13:39:14.680527
10143 13:39:14.683874 Waiting for the transfer...
10144 13:39:14.684055
10145 13:39:14.939054 00000000 ################################################################
10146 13:39:14.939198
10147 13:39:15.190807 00080000 ################################################################
10148 13:39:15.190986
10149 13:39:15.445539 00100000 ################################################################
10150 13:39:15.445679
10151 13:39:15.695326 00180000 ################################################################
10152 13:39:15.695512
10153 13:39:15.946563 00200000 ################################################################
10154 13:39:15.946730
10155 13:39:16.198260 00280000 ################################################################
10156 13:39:16.198414
10157 13:39:16.451197 00300000 ################################################################
10158 13:39:16.451333
10159 13:39:16.703947 00380000 ################################################################
10160 13:39:16.704115
10161 13:39:16.960528 00400000 ################################################################
10162 13:39:16.960708
10163 13:39:17.210276 00480000 ################################################################
10164 13:39:17.210458
10165 13:39:17.459277 00500000 ################################################################
10166 13:39:17.459415
10167 13:39:17.716875 00580000 ################################################################
10168 13:39:17.717023
10169 13:39:17.970321 00600000 ################################################################
10170 13:39:17.970467
10171 13:39:18.227689 00680000 ################################################################
10172 13:39:18.227869
10173 13:39:18.477317 00700000 ################################################################
10174 13:39:18.477519
10175 13:39:18.726731 00780000 ################################################################
10176 13:39:18.726891
10177 13:39:18.979081 00800000 ################################################################
10178 13:39:18.979222
10179 13:39:19.229617 00880000 ################################################################
10180 13:39:19.229788
10181 13:39:19.479454 00900000 ################################################################
10182 13:39:19.479588
10183 13:39:19.737307 00980000 ################################################################
10184 13:39:19.737446
10185 13:39:19.990803 00a00000 ################################################################
10186 13:39:19.990972
10187 13:39:20.241590 00a80000 ################################################################
10188 13:39:20.241726
10189 13:39:20.494463 00b00000 ################################################################
10190 13:39:20.494610
10191 13:39:20.745118 00b80000 ################################################################
10192 13:39:20.745288
10193 13:39:20.995519 00c00000 ################################################################
10194 13:39:20.995657
10195 13:39:21.247940 00c80000 ################################################################
10196 13:39:21.248116
10197 13:39:21.498157 00d00000 ################################################################
10198 13:39:21.498296
10199 13:39:21.748512 00d80000 ################################################################
10200 13:39:21.748648
10201 13:39:21.998255 00e00000 ################################################################
10202 13:39:21.998391
10203 13:39:22.251796 00e80000 ################################################################
10204 13:39:22.251965
10205 13:39:22.502250 00f00000 ################################################################
10206 13:39:22.502388
10207 13:39:22.751530 00f80000 ################################################################
10208 13:39:22.751689
10209 13:39:22.999913 01000000 ################################################################
10210 13:39:23.000065
10211 13:39:23.249121 01080000 ################################################################
10212 13:39:23.249307
10213 13:39:23.496925 01100000 ################################################################
10214 13:39:23.497059
10215 13:39:23.743476 01180000 ################################################################
10216 13:39:23.743640
10217 13:39:23.991537 01200000 ################################################################
10218 13:39:23.991708
10219 13:39:24.238637 01280000 ################################################################
10220 13:39:24.238837
10221 13:39:24.486881 01300000 ################################################################
10222 13:39:24.487060
10223 13:39:24.733475 01380000 ################################################################
10224 13:39:24.733629
10225 13:39:24.981628 01400000 ################################################################
10226 13:39:24.981765
10227 13:39:25.228022 01480000 ################################################################
10228 13:39:25.228192
10229 13:39:25.474764 01500000 ################################################################
10230 13:39:25.474938
10231 13:39:25.720255 01580000 ################################################################
10232 13:39:25.720436
10233 13:39:25.968638 01600000 ################################################################
10234 13:39:25.968822
10235 13:39:26.212377 01680000 ################################################################
10236 13:39:26.212523
10237 13:39:26.458731 01700000 ################################################################
10238 13:39:26.458901
10239 13:39:26.704671 01780000 ################################################################
10240 13:39:26.704838
10241 13:39:26.951555 01800000 ################################################################
10242 13:39:26.951725
10243 13:39:27.198295 01880000 ################################################################
10244 13:39:27.198434
10245 13:39:27.446541 01900000 ################################################################
10246 13:39:27.446711
10247 13:39:27.698620 01980000 ################################################################
10248 13:39:27.698770
10249 13:39:27.946041 01a00000 ################################################################
10250 13:39:27.946189
10251 13:39:28.362758 01a80000 ################################################################
10252 13:39:28.362971
10253 13:39:28.439008 01b00000 ################################################################
10254 13:39:28.439146
10255 13:39:28.682034 01b80000 ################################################################
10256 13:39:28.682180
10257 13:39:28.926774 01c00000 ################################################################
10258 13:39:28.926945
10259 13:39:29.167659 01c80000 ################################################################
10260 13:39:29.167828
10261 13:39:29.413083 01d00000 ################################################################
10262 13:39:29.413221
10263 13:39:29.655755 01d80000 ################################################################
10264 13:39:29.655893
10265 13:39:29.835432 01e00000 ################################################ done.
10266 13:39:29.835597
10267 13:39:29.839273 The bootfile was 31846250 bytes long.
10268 13:39:29.839355
10269 13:39:29.842603 Sending tftp read request... done.
10270 13:39:29.842694
10271 13:39:29.845374 Waiting for the transfer...
10272 13:39:29.845464
10273 13:39:29.845551 00000000 # done.
10274 13:39:29.845636
10275 13:39:29.855661 Command line loaded dynamically from TFTP file: 14063028/tftp-deploy-13dlhag1/kernel/cmdline
10276 13:39:29.855779
10277 13:39:29.878918 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10278 13:39:29.879023
10279 13:39:29.879092 Loading FIT.
10280 13:39:29.879156
10281 13:39:29.882296 Image ramdisk-1 has 18735655 bytes.
10282 13:39:29.882384
10283 13:39:29.885472 Image fdt-1 has 47258 bytes.
10284 13:39:29.885559
10285 13:39:29.888891 Image kernel-1 has 13061303 bytes.
10286 13:39:29.888983
10287 13:39:29.895271 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10288 13:39:29.895362
10289 13:39:29.915129 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10290 13:39:29.915231
10291 13:39:29.918488 Choosing best match conf-1 for compat google,spherion-rev2.
10292 13:39:29.923341
10293 13:39:29.928009 Connected to device vid:did:rid of 1ae0:0028:00
10294 13:39:29.936192
10295 13:39:29.939424 tpm_get_response: command 0x17b, return code 0x0
10296 13:39:29.939516
10297 13:39:29.946010 ec_init: CrosEC protocol v3 supported (256, 248)
10298 13:39:29.946100
10299 13:39:29.949384 tpm_cleanup: add release locality here.
10300 13:39:29.949473
10301 13:39:29.952575 Shutting down all USB controllers.
10302 13:39:29.952659
10303 13:39:29.956296 Removing current net device
10304 13:39:29.956381
10305 13:39:29.959504 Exiting depthcharge with code 4 at timestamp: 50948238
10306 13:39:29.959587
10307 13:39:29.965913 LZMA decompressing kernel-1 to 0x821a6718
10308 13:39:29.965997
10309 13:39:29.969100 LZMA decompressing kernel-1 to 0x40000000
10310 13:39:31.579388
10311 13:39:31.579534 jumping to kernel
10312 13:39:31.580020 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10313 13:39:31.580129 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10314 13:39:31.580229 Setting prompt string to ['Linux version [0-9]']
10315 13:39:31.580302 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10316 13:39:31.580372 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10317 13:39:31.662504
10318 13:39:31.665843 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10319 13:39:31.669665 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10320 13:39:31.669765 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10321 13:39:31.669859 Setting prompt string to []
10322 13:39:31.669940 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10323 13:39:31.670016 Using line separator: #'\n'#
10324 13:39:31.670084 No login prompt set.
10325 13:39:31.670149 Parsing kernel messages
10326 13:39:31.670206 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10327 13:39:31.670328 [login-action] Waiting for messages, (timeout 00:04:04)
10328 13:39:31.670403 Waiting using forced prompt support (timeout 00:02:02)
10329 13:39:31.688965 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10330 13:39:31.692585 [ 0.000000] random: crng init done
10331 13:39:31.699297 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 13:39:31.702564 [ 0.000000] efi: UEFI not found.
10333 13:39:31.709031 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 13:39:31.715670 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 13:39:31.725518 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 13:39:31.735109 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 13:39:31.742247 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 13:39:31.748161 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 13:39:31.755022 [ 0.000000] NUMA: No NUMA configuration found
10340 13:39:31.761721 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 13:39:31.765025 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10342 13:39:31.768198 [ 0.000000] Zone ranges:
10343 13:39:31.775119 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 13:39:31.777843 [ 0.000000] DMA32 empty
10345 13:39:31.784988 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 13:39:31.788239 [ 0.000000] Movable zone start for each node
10347 13:39:31.791011 [ 0.000000] Early memory node ranges
10348 13:39:31.797844 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 13:39:31.804159 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 13:39:31.810726 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 13:39:31.817393 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 13:39:31.824014 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 13:39:31.830479 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 13:39:31.886815 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 13:39:31.893217 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 13:39:31.900197 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 13:39:31.903243 [ 0.000000] psci: probing for conduit method from DT.
10358 13:39:31.910198 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 13:39:31.913241 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 13:39:31.919788 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 13:39:31.923163 [ 0.000000] psci: SMC Calling Convention v1.2
10362 13:39:31.929810 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10363 13:39:31.933062 [ 0.000000] Detected VIPT I-cache on CPU0
10364 13:39:31.939521 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 13:39:31.946472 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 13:39:31.953036 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 13:39:31.959284 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 13:39:31.966412 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 13:39:31.976156 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 13:39:31.979422 [ 0.000000] alternatives: applying boot alternatives
10371 13:39:31.986100 [ 0.000000] Fallback order for Node 0: 0
10372 13:39:31.992467 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 13:39:31.995799 [ 0.000000] Policy zone: Normal
10374 13:39:32.018746 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10375 13:39:32.028627 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 13:39:32.040096 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 13:39:32.049703 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 13:39:32.056262 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 13:39:32.060082 <6>[ 0.000000] software IO TLB: area num 8.
10380 13:39:32.116124 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 13:39:32.265064 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10382 13:39:32.271822 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 13:39:32.278494 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 13:39:32.281710 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 13:39:32.288446 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 13:39:32.295039 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 13:39:32.298172 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 13:39:32.308369 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 13:39:32.314778 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 13:39:32.321182 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 13:39:32.328249 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 13:39:32.331434 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 13:39:32.334701 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 13:39:32.341399 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 13:39:32.344701 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 13:39:32.351211 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 13:39:32.364283 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 13:39:32.377662 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 13:39:32.384085 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 13:39:32.392185 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 13:39:32.405236 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 13:39:32.411612 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 13:39:32.418647 <6>[ 0.009178] Console: colour dummy device 80x25
10404 13:39:32.428674 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 13:39:32.434983 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10406 13:39:32.438238 <6>[ 0.029219] LSM: Security Framework initializing
10407 13:39:32.444731 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 13:39:32.454596 <6>[ 0.041972] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 13:39:32.464510 <6>[ 0.051390] cblist_init_generic: Setting adjustable number of callback queues.
10410 13:39:32.470969 <6>[ 0.058834] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 13:39:32.478008 <6>[ 0.065212] cblist_init_generic: Setting adjustable number of callback queues.
10412 13:39:32.484522 <6>[ 0.072672] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 13:39:32.487754 <6>[ 0.079070] rcu: Hierarchical SRCU implementation.
10414 13:39:32.494259 <6>[ 0.084116] rcu: Max phase no-delay instances is 1000.
10415 13:39:32.501041 <6>[ 0.091187] EFI services will not be available.
10416 13:39:32.504160 <6>[ 0.096143] smp: Bringing up secondary CPUs ...
10417 13:39:32.512730 <6>[ 0.101192] Detected VIPT I-cache on CPU1
10418 13:39:32.519588 <6>[ 0.101262] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10419 13:39:32.525963 <6>[ 0.101291] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10420 13:39:32.529249 <6>[ 0.101625] Detected VIPT I-cache on CPU2
10421 13:39:32.539225 <6>[ 0.101674] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10422 13:39:32.546149 <6>[ 0.101689] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10423 13:39:32.549250 <6>[ 0.101947] Detected VIPT I-cache on CPU3
10424 13:39:32.555778 <6>[ 0.101994] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10425 13:39:32.562342 <6>[ 0.102008] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10426 13:39:32.565657 <6>[ 0.102312] CPU features: detected: Spectre-v4
10427 13:39:32.572587 <6>[ 0.102318] CPU features: detected: Spectre-BHB
10428 13:39:32.575903 <6>[ 0.102323] Detected PIPT I-cache on CPU4
10429 13:39:32.582339 <6>[ 0.102380] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10430 13:39:32.588863 <6>[ 0.102396] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10431 13:39:32.595309 <6>[ 0.102689] Detected PIPT I-cache on CPU5
10432 13:39:32.601754 <6>[ 0.102751] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10433 13:39:32.608206 <6>[ 0.102767] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10434 13:39:32.611922 <6>[ 0.103049] Detected PIPT I-cache on CPU6
10435 13:39:32.621681 <6>[ 0.103115] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10436 13:39:32.628104 <6>[ 0.103131] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10437 13:39:32.631545 <6>[ 0.103426] Detected PIPT I-cache on CPU7
10438 13:39:32.637970 <6>[ 0.103492] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10439 13:39:32.645054 <6>[ 0.103508] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10440 13:39:32.648175 <6>[ 0.103555] smp: Brought up 1 node, 8 CPUs
10441 13:39:32.654633 <6>[ 0.244979] SMP: Total of 8 processors activated.
10442 13:39:32.661060 <6>[ 0.249899] CPU features: detected: 32-bit EL0 Support
10443 13:39:32.668173 <6>[ 0.255262] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10444 13:39:32.674658 <6>[ 0.264062] CPU features: detected: Common not Private translations
10445 13:39:32.681240 <6>[ 0.270578] CPU features: detected: CRC32 instructions
10446 13:39:32.687756 <6>[ 0.275929] CPU features: detected: RCpc load-acquire (LDAPR)
10447 13:39:32.691043 <6>[ 0.281889] CPU features: detected: LSE atomic instructions
10448 13:39:32.697583 <6>[ 0.287706] CPU features: detected: Privileged Access Never
10449 13:39:32.704526 <6>[ 0.293486] CPU features: detected: RAS Extension Support
10450 13:39:32.710977 <6>[ 0.299129] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10451 13:39:32.714380 <6>[ 0.306394] CPU: All CPU(s) started at EL2
10452 13:39:32.720784 <6>[ 0.310711] alternatives: applying system-wide alternatives
10453 13:39:32.730663 <6>[ 0.321554] devtmpfs: initialized
10454 13:39:32.743207 <6>[ 0.330632] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10455 13:39:32.753445 <6>[ 0.340596] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10456 13:39:32.759801 <6>[ 0.348531] pinctrl core: initialized pinctrl subsystem
10457 13:39:32.763150 <6>[ 0.355215] DMI not present or invalid.
10458 13:39:32.769969 <6>[ 0.359629] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10459 13:39:32.779658 <6>[ 0.366503] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10460 13:39:32.785953 <6>[ 0.374089] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10461 13:39:32.796168 <6>[ 0.382304] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10462 13:39:32.799393 <6>[ 0.390545] audit: initializing netlink subsys (disabled)
10463 13:39:32.809116 <5>[ 0.396238] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10464 13:39:32.815713 <6>[ 0.396955] thermal_sys: Registered thermal governor 'step_wise'
10465 13:39:32.822120 <6>[ 0.404201] thermal_sys: Registered thermal governor 'power_allocator'
10466 13:39:32.825454 <6>[ 0.410455] cpuidle: using governor menu
10467 13:39:32.831898 <6>[ 0.421416] NET: Registered PF_QIPCRTR protocol family
10468 13:39:32.838511 <6>[ 0.426902] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10469 13:39:32.845039 <6>[ 0.434003] ASID allocator initialised with 32768 entries
10470 13:39:32.848346 <6>[ 0.440599] Serial: AMBA PL011 UART driver
10471 13:39:32.858734 <4>[ 0.449480] Trying to register duplicate clock ID: 134
10472 13:39:32.918872 <6>[ 0.512769] KASLR enabled
10473 13:39:32.933198 <6>[ 0.520603] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10474 13:39:32.939744 <6>[ 0.527616] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10475 13:39:32.946194 <6>[ 0.534105] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10476 13:39:32.953330 <6>[ 0.541110] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10477 13:39:32.959790 <6>[ 0.547595] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10478 13:39:32.966183 <6>[ 0.554599] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10479 13:39:32.972638 <6>[ 0.561086] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10480 13:39:32.979386 <6>[ 0.568089] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10481 13:39:32.982602 <6>[ 0.575625] ACPI: Interpreter disabled.
10482 13:39:32.991330 <6>[ 0.582060] iommu: Default domain type: Translated
10483 13:39:32.998276 <6>[ 0.587171] iommu: DMA domain TLB invalidation policy: strict mode
10484 13:39:33.001392 <5>[ 0.593831] SCSI subsystem initialized
10485 13:39:33.008173 <6>[ 0.597997] usbcore: registered new interface driver usbfs
10486 13:39:33.014597 <6>[ 0.603730] usbcore: registered new interface driver hub
10487 13:39:33.017753 <6>[ 0.609283] usbcore: registered new device driver usb
10488 13:39:33.024625 <6>[ 0.615390] pps_core: LinuxPPS API ver. 1 registered
10489 13:39:33.034464 <6>[ 0.620583] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10490 13:39:33.037755 <6>[ 0.629929] PTP clock support registered
10491 13:39:33.041028 <6>[ 0.634172] EDAC MC: Ver: 3.0.0
10492 13:39:33.048450 <6>[ 0.639327] FPGA manager framework
10493 13:39:33.055283 <6>[ 0.643012] Advanced Linux Sound Architecture Driver Initialized.
10494 13:39:33.058671 <6>[ 0.649794] vgaarb: loaded
10495 13:39:33.065112 <6>[ 0.652963] clocksource: Switched to clocksource arch_sys_counter
10496 13:39:33.068624 <5>[ 0.659408] VFS: Disk quotas dquot_6.6.0
10497 13:39:33.075004 <6>[ 0.663593] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10498 13:39:33.078555 <6>[ 0.670784] pnp: PnP ACPI: disabled
10499 13:39:33.087161 <6>[ 0.677591] NET: Registered PF_INET protocol family
10500 13:39:33.097013 <6>[ 0.683201] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10501 13:39:33.108501 <6>[ 0.695529] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10502 13:39:33.118215 <6>[ 0.704342] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10503 13:39:33.124697 <6>[ 0.712313] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10504 13:39:33.131183 <6>[ 0.721018] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10505 13:39:33.143353 <6>[ 0.730751] TCP: Hash tables configured (established 65536 bind 65536)
10506 13:39:33.149883 <6>[ 0.737612] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 13:39:33.156632 <6>[ 0.744809] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 13:39:33.163260 <6>[ 0.752521] NET: Registered PF_UNIX/PF_LOCAL protocol family
10509 13:39:33.169649 <6>[ 0.758691] RPC: Registered named UNIX socket transport module.
10510 13:39:33.173245 <6>[ 0.764847] RPC: Registered udp transport module.
10511 13:39:33.179902 <6>[ 0.769780] RPC: Registered tcp transport module.
10512 13:39:33.186289 <6>[ 0.774713] RPC: Registered tcp NFSv4.1 backchannel transport module.
10513 13:39:33.190122 <6>[ 0.781380] PCI: CLS 0 bytes, default 64
10514 13:39:33.193212 <6>[ 0.785747] Unpacking initramfs...
10515 13:39:33.214030 <6>[ 0.801369] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10516 13:39:33.223847 <6>[ 0.810026] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10517 13:39:33.227127 <6>[ 0.818930] kvm [1]: IPA Size Limit: 40 bits
10518 13:39:33.233623 <6>[ 0.823457] kvm [1]: GICv3: no GICV resource entry
10519 13:39:33.237367 <6>[ 0.828477] kvm [1]: disabling GICv2 emulation
10520 13:39:33.243965 <6>[ 0.833167] kvm [1]: GIC system register CPU interface enabled
10521 13:39:33.247209 <6>[ 0.839330] kvm [1]: vgic interrupt IRQ18
10522 13:39:33.253587 <6>[ 0.843680] kvm [1]: VHE mode initialized successfully
10523 13:39:33.260478 <5>[ 0.850041] Initialise system trusted keyrings
10524 13:39:33.267017 <6>[ 0.854826] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10525 13:39:33.274473 <6>[ 0.864862] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10526 13:39:33.280725 <5>[ 0.871233] NFS: Registering the id_resolver key type
10527 13:39:33.284082 <5>[ 0.876530] Key type id_resolver registered
10528 13:39:33.291043 <5>[ 0.880944] Key type id_legacy registered
10529 13:39:33.297631 <6>[ 0.885220] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10530 13:39:33.304195 <6>[ 0.892146] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10531 13:39:33.310551 <6>[ 0.899842] 9p: Installing v9fs 9p2000 file system support
10532 13:39:33.346952 <5>[ 0.937589] Key type asymmetric registered
10533 13:39:33.350231 <5>[ 0.941920] Asymmetric key parser 'x509' registered
10534 13:39:33.360124 <6>[ 0.947055] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10535 13:39:33.363329 <6>[ 0.954670] io scheduler mq-deadline registered
10536 13:39:33.367076 <6>[ 0.959431] io scheduler kyber registered
10537 13:39:33.385302 <6>[ 0.976307] EINJ: ACPI disabled.
10538 13:39:33.417907 <4>[ 1.001961] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 13:39:33.428099 <4>[ 1.012581] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 13:39:33.443096 <6>[ 1.033630] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10541 13:39:33.450998 <6>[ 1.041647] printk: console [ttyS0] disabled
10542 13:39:33.479240 <6>[ 1.066278] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10543 13:39:33.485655 <6>[ 1.075754] printk: console [ttyS0] enabled
10544 13:39:33.488812 <6>[ 1.075754] printk: console [ttyS0] enabled
10545 13:39:33.495313 <6>[ 1.084650] printk: bootconsole [mtk8250] disabled
10546 13:39:33.498897 <6>[ 1.084650] printk: bootconsole [mtk8250] disabled
10547 13:39:33.505384 <6>[ 1.095766] SuperH (H)SCI(F) driver initialized
10548 13:39:33.508735 <6>[ 1.101055] msm_serial: driver initialized
10549 13:39:33.522489 <6>[ 1.109963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10550 13:39:33.532578 <6>[ 1.118510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10551 13:39:33.539398 <6>[ 1.127052] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10552 13:39:33.549278 <6>[ 1.135679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10553 13:39:33.555672 <6>[ 1.144385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10554 13:39:33.565857 <6>[ 1.153099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10555 13:39:33.575945 <6>[ 1.161639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10556 13:39:33.582374 <6>[ 1.170434] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10557 13:39:33.592471 <6>[ 1.178981] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10558 13:39:33.604227 <6>[ 1.194845] loop: module loaded
10559 13:39:33.610755 <6>[ 1.200882] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10560 13:39:33.633903 <4>[ 1.224500] mtk-pmic-keys: Failed to locate of_node [id: -1]
10561 13:39:33.640786 <6>[ 1.231638] megasas: 07.719.03.00-rc1
10562 13:39:33.650521 <6>[ 1.241444] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10563 13:39:33.661495 <6>[ 1.252344] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10564 13:39:33.677587 <6>[ 1.268360] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10565 13:39:33.734017 <6>[ 1.317946] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10566 13:39:34.015143 <6>[ 1.606127] Freeing initrd memory: 18292K
10567 13:39:34.027071 <6>[ 1.617906] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10568 13:39:34.038482 <6>[ 1.629124] tun: Universal TUN/TAP device driver, 1.6
10569 13:39:34.042071 <6>[ 1.635197] thunder_xcv, ver 1.0
10570 13:39:34.045088 <6>[ 1.638705] thunder_bgx, ver 1.0
10571 13:39:34.048236 <6>[ 1.642201] nicpf, ver 1.0
10572 13:39:34.058898 <6>[ 1.646251] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10573 13:39:34.062154 <6>[ 1.653726] hns3: Copyright (c) 2017 Huawei Corporation.
10574 13:39:34.065310 <6>[ 1.659317] hclge is initializing
10575 13:39:34.072453 <6>[ 1.662898] e1000: Intel(R) PRO/1000 Network Driver
10576 13:39:34.079032 <6>[ 1.668028] e1000: Copyright (c) 1999-2006 Intel Corporation.
10577 13:39:34.082219 <6>[ 1.674043] e1000e: Intel(R) PRO/1000 Network Driver
10578 13:39:34.089123 <6>[ 1.679259] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10579 13:39:34.095455 <6>[ 1.685445] igb: Intel(R) Gigabit Ethernet Network Driver
10580 13:39:34.102171 <6>[ 1.691094] igb: Copyright (c) 2007-2014 Intel Corporation.
10581 13:39:34.109091 <6>[ 1.696930] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10582 13:39:34.115452 <6>[ 1.703448] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10583 13:39:34.118742 <6>[ 1.709913] sky2: driver version 1.30
10584 13:39:34.125740 <6>[ 1.714849] usbcore: registered new device driver r8152-cfgselector
10585 13:39:34.132176 <6>[ 1.721383] usbcore: registered new interface driver r8152
10586 13:39:34.135373 <6>[ 1.727207] VFIO - User Level meta-driver version: 0.3
10587 13:39:34.144788 <6>[ 1.735458] usbcore: registered new interface driver usb-storage
10588 13:39:34.151211 <6>[ 1.741906] usbcore: registered new device driver onboard-usb-hub
10589 13:39:34.160308 <6>[ 1.751064] mt6397-rtc mt6359-rtc: registered as rtc0
10590 13:39:34.170547 <6>[ 1.756524] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:38:24 UTC (1716903504)
10591 13:39:34.173784 <6>[ 1.766101] i2c_dev: i2c /dev entries driver
10592 13:39:34.190550 <6>[ 1.777944] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10593 13:39:34.197082 <4>[ 1.786673] cpu cpu0: supply cpu not found, using dummy regulator
10594 13:39:34.203961 <4>[ 1.793107] cpu cpu1: supply cpu not found, using dummy regulator
10595 13:39:34.210317 <4>[ 1.799516] cpu cpu2: supply cpu not found, using dummy regulator
10596 13:39:34.217351 <4>[ 1.805914] cpu cpu3: supply cpu not found, using dummy regulator
10597 13:39:34.223725 <4>[ 1.812315] cpu cpu4: supply cpu not found, using dummy regulator
10598 13:39:34.230626 <4>[ 1.818727] cpu cpu5: supply cpu not found, using dummy regulator
10599 13:39:34.237163 <4>[ 1.825127] cpu cpu6: supply cpu not found, using dummy regulator
10600 13:39:34.240437 <4>[ 1.831526] cpu cpu7: supply cpu not found, using dummy regulator
10601 13:39:34.261666 <6>[ 1.852161] cpu cpu0: EM: created perf domain
10602 13:39:34.264819 <6>[ 1.857014] cpu cpu4: EM: created perf domain
10603 13:39:34.271951 <6>[ 1.862655] sdhci: Secure Digital Host Controller Interface driver
10604 13:39:34.278411 <6>[ 1.869090] sdhci: Copyright(c) Pierre Ossman
10605 13:39:34.285155 <6>[ 1.874058] Synopsys Designware Multimedia Card Interface Driver
10606 13:39:34.292087 <6>[ 1.880694] sdhci-pltfm: SDHCI platform and OF driver helper
10607 13:39:34.295370 <6>[ 1.880810] mmc0: CQHCI version 5.10
10608 13:39:34.301897 <6>[ 1.890628] ledtrig-cpu: registered to indicate activity on CPUs
10609 13:39:34.308549 <6>[ 1.897643] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10610 13:39:34.314792 <6>[ 1.904689] usbcore: registered new interface driver usbhid
10611 13:39:34.318116 <6>[ 1.910511] usbhid: USB HID core driver
10612 13:39:34.325168 <6>[ 1.914714] spi_master spi0: will run message pump with realtime priority
10613 13:39:34.371046 <6>[ 1.955223] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10614 13:39:34.387343 <6>[ 1.971212] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10615 13:39:34.394846 <6>[ 1.985106] mmc0: Command Queue Engine enabled
10616 13:39:34.401342 <6>[ 1.989880] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10617 13:39:34.408136 <6>[ 1.997046] cros-ec-spi spi0.0: Chrome EC device registered
10618 13:39:34.411272 <6>[ 1.997374] mmcblk0: mmc0:0001 DA4128 116 GiB
10619 13:39:34.427961 <6>[ 2.018555] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10620 13:39:34.437797 <6>[ 2.023837] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10621 13:39:34.444775 <6>[ 2.025541] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 13:39:34.448159 <6>[ 2.035082] NET: Registered PF_PACKET protocol family
10623 13:39:34.454710 <6>[ 2.039730] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 13:39:34.458258 <6>[ 2.044445] 9pnet: Installing 9P2000 support
10625 13:39:34.464356 <6>[ 2.050436] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 13:39:34.467893 <5>[ 2.054104] Key type dns_resolver registered
10627 13:39:34.474952 <6>[ 2.065647] registered taskstats version 1
10628 13:39:34.478101 <5>[ 2.070046] Loading compiled-in X.509 certificates
10629 13:39:34.508465 <4>[ 2.092635] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 13:39:34.518386 <4>[ 2.103386] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 13:39:34.534217 <6>[ 2.124753] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 13:39:34.541189 <6>[ 2.131722] xhci-mtk 11200000.usb: xHCI Host Controller
10633 13:39:34.547585 <6>[ 2.137230] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 13:39:34.557864 <6>[ 2.145079] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 13:39:34.564240 <6>[ 2.154512] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 13:39:34.570963 <6>[ 2.160606] xhci-mtk 11200000.usb: xHCI Host Controller
10637 13:39:34.577589 <6>[ 2.166094] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 13:39:34.584102 <6>[ 2.173844] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 13:39:34.591230 <6>[ 2.181671] hub 1-0:1.0: USB hub found
10640 13:39:34.594394 <6>[ 2.185695] hub 1-0:1.0: 1 port detected
10641 13:39:34.600818 <6>[ 2.189984] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 13:39:34.608015 <6>[ 2.198687] hub 2-0:1.0: USB hub found
10643 13:39:34.611141 <6>[ 2.202710] hub 2-0:1.0: 1 port detected
10644 13:39:34.618865 <6>[ 2.209633] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 13:39:34.632172 <6>[ 2.219606] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10646 13:39:34.639111 <6>[ 2.227633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10647 13:39:34.648730 <4>[ 2.235552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10648 13:39:34.659002 <6>[ 2.245087] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10649 13:39:34.665425 <6>[ 2.253164] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10650 13:39:34.672102 <6>[ 2.261188] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10651 13:39:34.682298 <6>[ 2.269136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10652 13:39:34.689010 <6>[ 2.276956] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10653 13:39:34.698693 <6>[ 2.284773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10654 13:39:34.709180 <6>[ 2.295153] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 13:39:34.715528 <6>[ 2.303514] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 13:39:34.725550 <6>[ 2.311860] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 13:39:34.732205 <6>[ 2.320200] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 13:39:34.742297 <6>[ 2.328540] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 13:39:34.748782 <6>[ 2.336879] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 13:39:34.758596 <6>[ 2.345217] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 13:39:34.764984 <6>[ 2.353556] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 13:39:34.775267 <6>[ 2.361895] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 13:39:34.781838 <6>[ 2.370233] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 13:39:34.791813 <6>[ 2.378571] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 13:39:34.798341 <6>[ 2.386910] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 13:39:34.808142 <6>[ 2.395251] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 13:39:34.814850 <6>[ 2.403590] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 13:39:34.824865 <6>[ 2.411928] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 13:39:34.831355 <6>[ 2.420659] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 13:39:34.838075 <6>[ 2.427819] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 13:39:34.844556 <6>[ 2.434586] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 13:39:34.851011 <6>[ 2.441352] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 13:39:34.857515 <6>[ 2.448286] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 13:39:34.867741 <6>[ 2.455166] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 13:39:34.877435 <6>[ 2.464297] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 13:39:34.887557 <6>[ 2.473419] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 13:39:34.897523 <6>[ 2.482714] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 13:39:34.904388 <6>[ 2.492183] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 13:39:34.914240 <6>[ 2.501651] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 13:39:34.924033 <6>[ 2.510771] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 13:39:34.934171 <6>[ 2.520238] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 13:39:34.943619 <6>[ 2.529356] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 13:39:34.953889 <6>[ 2.538651] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 13:39:34.963596 <6>[ 2.548825] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 13:39:34.974029 <6>[ 2.560296] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 13:39:34.980862 <6>[ 2.569848] Trying to probe devices needed for running init ...
10687 13:39:35.013587 <6>[ 2.601241] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10688 13:39:35.168436 <6>[ 2.759149] hub 1-1:1.0: USB hub found
10689 13:39:35.171595 <6>[ 2.763645] hub 1-1:1.0: 4 ports detected
10690 13:39:35.180633 <6>[ 2.771697] hub 1-1:1.0: USB hub found
10691 13:39:35.184420 <6>[ 2.776093] hub 1-1:1.0: 4 ports detected
10692 13:39:35.294042 <6>[ 2.881579] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10693 13:39:35.320419 <6>[ 2.911115] hub 2-1:1.0: USB hub found
10694 13:39:35.323527 <6>[ 2.915606] hub 2-1:1.0: 3 ports detected
10695 13:39:35.332648 <6>[ 2.923733] hub 2-1:1.0: USB hub found
10696 13:39:35.336351 <6>[ 2.928189] hub 2-1:1.0: 3 ports detected
10697 13:39:35.509388 <6>[ 3.097202] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10698 13:39:35.642242 <6>[ 3.232821] hub 1-1.4:1.0: USB hub found
10699 13:39:35.645400 <6>[ 3.237493] hub 1-1.4:1.0: 2 ports detected
10700 13:39:35.654153 <6>[ 3.245070] hub 1-1.4:1.0: USB hub found
10701 13:39:35.657418 <6>[ 3.249658] hub 1-1.4:1.0: 2 ports detected
10702 13:39:35.721950 <6>[ 3.309419] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10703 13:39:35.830071 <6>[ 3.417912] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10704 13:39:35.865792 <4>[ 3.453329] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10705 13:39:35.875800 <4>[ 3.462419] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10706 13:39:35.920069 <6>[ 3.510880] r8152 2-1.3:1.0 eth0: v1.12.13
10707 13:39:35.953812 <6>[ 3.541277] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10708 13:39:36.145487 <6>[ 3.733298] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10709 13:39:37.538978 <6>[ 5.129814] r8152 2-1.3:1.0 eth0: carrier on
10710 13:39:37.582094 <5>[ 5.157077] Sending DHCP requests ., OK
10711 13:39:37.588557 <6>[ 5.177313] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10712 13:39:37.591793 <6>[ 5.185602] IP-Config: Complete:
10713 13:39:37.604907 <6>[ 5.189101] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10714 13:39:37.611804 <6>[ 5.199809] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10715 13:39:37.618381 <6>[ 5.208428] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10716 13:39:37.624774 <6>[ 5.208437] nameserver0=192.168.201.1
10717 13:39:37.628278 <6>[ 5.220554] clk: Disabling unused clocks
10718 13:39:37.631366 <6>[ 5.226057] ALSA device list:
10719 13:39:37.638222 <6>[ 5.229335] No soundcards found.
10720 13:39:37.645920 <6>[ 5.237104] Freeing unused kernel memory: 8512K
10721 13:39:37.649065 <6>[ 5.242064] Run /init as init process
10722 13:39:37.658175 Loading, please wait...
10723 13:39:37.684962 Starting systemd-udevd version 252.22-1~deb12u1
10724 13:39:37.955231 <6>[ 5.542688] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10725 13:39:37.961474 <6>[ 5.545351] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10726 13:39:37.968521 <6>[ 5.554687] remoteproc remoteproc0: scp is available
10727 13:39:37.974892 <6>[ 5.557995] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10728 13:39:37.982005 <6>[ 5.563825] remoteproc remoteproc0: powering up scp
10729 13:39:37.988477 <6>[ 5.571813] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10730 13:39:37.998180 <6>[ 5.585740] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10731 13:39:38.004810 <3>[ 5.587994] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 13:39:38.011250 <6>[ 5.590100] mc: Linux media interface: v0.10
10733 13:39:38.018309 <6>[ 5.594341] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10734 13:39:38.024823 <4>[ 5.600212] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10735 13:39:38.031193 <4>[ 5.600379] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10736 13:39:38.038153 <3>[ 5.604053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 13:39:38.048191 <6>[ 5.611811] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10738 13:39:38.054531 <3>[ 5.613899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 13:39:38.064592 <4>[ 5.635367] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10740 13:39:38.068331 <4>[ 5.635367] Fallback method does not support PEC.
10741 13:39:38.074999 <6>[ 5.637046] videodev: Linux video capture interface: v2.00
10742 13:39:38.081444 <3>[ 5.643586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 13:39:38.091485 <3>[ 5.669917] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10744 13:39:38.098114 <3>[ 5.670907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 13:39:38.105590 <6>[ 5.694479] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10746 13:39:38.115238 <3>[ 5.695793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 13:39:38.121790 <3>[ 5.700617] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 13:39:38.128392 <6>[ 5.702665] pci_bus 0000:00: root bus resource [bus 00-ff]
10749 13:39:38.138754 <3>[ 5.710732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 13:39:38.145215 <6>[ 5.711504] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10751 13:39:38.155008 <6>[ 5.719507] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10752 13:39:38.165380 <6>[ 5.721736] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10753 13:39:38.171887 <6>[ 5.722084] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10754 13:39:38.181597 <3>[ 5.725241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 13:39:38.188390 <3>[ 5.725288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 13:39:38.195354 <6>[ 5.732921] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10757 13:39:38.205505 <6>[ 5.733095] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10758 13:39:38.211756 <6>[ 5.733104] remoteproc remoteproc0: remote processor scp is now up
10759 13:39:38.221475 <6>[ 5.733348] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10760 13:39:38.228314 <3>[ 5.742738] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 13:39:38.238352 <3>[ 5.742744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 13:39:38.244886 <3>[ 5.742748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 13:39:38.254963 <3>[ 5.742848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 13:39:38.261608 <3>[ 5.742856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 13:39:38.268059 <3>[ 5.742862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 13:39:38.278084 <3>[ 5.742871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 13:39:38.284610 <3>[ 5.742875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 13:39:38.294583 <3>[ 5.742905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 13:39:38.297945 <6>[ 5.743495] Bluetooth: Core ver 2.22
10770 13:39:38.304327 <6>[ 5.743580] NET: Registered PF_BLUETOOTH protocol family
10771 13:39:38.311267 <6>[ 5.743582] Bluetooth: HCI device and connection manager initialized
10772 13:39:38.314512 <6>[ 5.743606] Bluetooth: HCI socket layer initialized
10773 13:39:38.320921 <6>[ 5.743613] Bluetooth: L2CAP socket layer initialized
10774 13:39:38.324444 <6>[ 5.743624] Bluetooth: SCO socket layer initialized
10775 13:39:38.334397 <6>[ 5.744907] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10776 13:39:38.341093 <6>[ 5.747557] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10777 13:39:38.347519 <6>[ 5.750501] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10778 13:39:38.354285 <6>[ 5.778350] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10779 13:39:38.364022 <6>[ 5.785535] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10780 13:39:38.373749 <6>[ 5.793687] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10781 13:39:38.380597 <6>[ 5.800986] pci 0000:00:00.0: supports D1 D2
10782 13:39:38.383872 <6>[ 5.807566] usbcore: registered new interface driver uvcvideo
10783 13:39:38.393963 <6>[ 5.817243] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10784 13:39:38.397247 <6>[ 5.817939] usbcore: registered new interface driver btusb
10785 13:39:38.407058 <6>[ 5.818403] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10786 13:39:38.413472 <6>[ 5.818489] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10787 13:39:38.420422 <6>[ 5.818514] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10788 13:39:38.426767 <6>[ 5.818530] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10789 13:39:38.433715 <6>[ 5.818545] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10790 13:39:38.440095 <6>[ 5.818647] pci 0000:01:00.0: supports D1 D2
10791 13:39:38.446557 <6>[ 5.818649] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10792 13:39:38.456862 <4>[ 5.818689] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10793 13:39:38.463157 <3>[ 5.818700] Bluetooth: hci0: Failed to load firmware file (-2)
10794 13:39:38.469829 <3>[ 5.818703] Bluetooth: hci0: Failed to set up firmware (-2)
10795 13:39:38.479733 <4>[ 5.818706] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10796 13:39:38.486709 <6>[ 5.826887] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10797 13:39:38.493057 <6>[ 5.833024] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10798 13:39:38.499996 <6>[ 5.833052] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10799 13:39:38.509672 <6>[ 5.833056] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10800 13:39:38.516116 <6>[ 5.833064] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10801 13:39:38.522977 <6>[ 5.833077] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10802 13:39:38.533109 <6>[ 5.833089] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10803 13:39:38.536242 <6>[ 5.833101] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 13:39:38.546053 <6>[ 5.833107] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10805 13:39:38.552993 <6>[ 6.142158] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10806 13:39:38.559482 <6>[ 6.149087] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10807 13:39:38.565928 <6>[ 6.155763] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10808 13:39:38.586443 <5>[ 6.174433] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10809 13:39:38.607814 <5>[ 6.195652] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10810 13:39:38.614240 <5>[ 6.203156] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10811 13:39:38.624331 <4>[ 6.211689] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10812 13:39:38.630646 <6>[ 6.220602] cfg80211: failed to load regulatory.db
10813 13:39:38.687724 <6>[ 6.275573] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10814 13:39:38.694417 <6>[ 6.283124] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10815 13:39:38.718479 <6>[ 6.309865] mt7921e 0000:01:00.0: ASIC revision: 79610010
10816 13:39:38.821704 <6>[ 6.409723] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10817 13:39:38.825505 <6>[ 6.409723]
10818 13:39:38.828642 Begin: Loading essential drivers ... done.
10819 13:39:38.831882 Begin: Running /scripts/init-premount ... done.
10820 13:39:38.838372 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10821 13:39:38.848512 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10822 13:39:38.851766 Device /sys/class/net/eth0 found
10823 13:39:38.851849 done.
10824 13:39:38.862637 Begin: Waiting up to 180 secs for any network device to become available ... done.
10825 13:39:38.914316 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10826 13:39:38.920913 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10827 13:39:38.927661 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10828 13:39:38.933961 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10829 13:39:38.940517 host : mt8192-asurada-spherion-r0-cbg-1
10830 13:39:38.947306 domain : lava-rack
10831 13:39:38.950527 rootserver: 192.168.201.1 rootpath:
10832 13:39:38.950667 filename :
10833 13:39:39.083391 done.
10834 13:39:39.089741 <6>[ 6.678295] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10835 13:39:39.096719 Begin: Running /scripts/nfs-bottom ... done.
10836 13:39:39.114406 Begin: Running /scripts/init-bottom ... done.
10837 13:39:40.411140 <6>[ 8.002609] NET: Registered PF_INET6 protocol family
10838 13:39:40.418566 <6>[ 8.010069] Segment Routing with IPv6
10839 13:39:40.421977 <6>[ 8.014072] In-situ OAM (IOAM) with IPv6
10840 13:39:40.584417 <30>[ 8.149470] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10841 13:39:40.591301 <30>[ 8.182642] systemd[1]: Detected architecture arm64.
10842 13:39:40.597402
10843 13:39:40.600587 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10844 13:39:40.600674
10845 13:39:40.622516 <30>[ 8.213864] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10846 13:39:41.562796 <30>[ 9.151178] systemd[1]: Queued start job for default target graphical.target.
10847 13:39:41.601742 <30>[ 9.190183] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10848 13:39:41.608811 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10849 13:39:41.630932 <30>[ 9.219174] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10850 13:39:41.640537 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10851 13:39:41.659138 <30>[ 9.247111] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10852 13:39:41.668833 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10853 13:39:41.687156 <30>[ 9.275496] systemd[1]: Created slice user.slice - User and Session Slice.
10854 13:39:41.694011 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10855 13:39:41.717257 <30>[ 9.302125] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10856 13:39:41.727028 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10857 13:39:41.744397 <30>[ 9.329535] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10858 13:39:41.751305 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10859 13:39:41.779272 <30>[ 9.357461] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10860 13:39:41.788998 <30>[ 9.377290] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10861 13:39:41.795776 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10862 13:39:41.813433 <30>[ 9.401683] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10863 13:39:41.823406 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10864 13:39:41.840876 <30>[ 9.429340] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10865 13:39:41.850725 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10866 13:39:41.866450 <30>[ 9.457821] systemd[1]: Reached target paths.target - Path Units.
10867 13:39:41.876092 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10868 13:39:41.893721 <30>[ 9.481612] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10869 13:39:41.900075 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10870 13:39:41.913822 <30>[ 9.505251] systemd[1]: Reached target slices.target - Slice Units.
10871 13:39:41.923887 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10872 13:39:41.938126 <30>[ 9.529740] systemd[1]: Reached target swap.target - Swaps.
10873 13:39:41.944893 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10874 13:39:41.964815 <30>[ 9.553347] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10875 13:39:41.974988 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10876 13:39:41.993648 <30>[ 9.582206] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10877 13:39:42.003795 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10878 13:39:42.023838 <30>[ 9.612179] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10879 13:39:42.033543 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10880 13:39:42.050392 <30>[ 9.638707] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10881 13:39:42.060219 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10882 13:39:42.077729 <30>[ 9.665953] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10883 13:39:42.084161 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10884 13:39:42.102597 <30>[ 9.690643] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10885 13:39:42.112245 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10886 13:39:42.131478 <30>[ 9.719967] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10887 13:39:42.141334 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10888 13:39:42.158229 <30>[ 9.746346] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10889 13:39:42.164783 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10890 13:39:42.217053 <30>[ 9.805483] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10891 13:39:42.223622 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10892 13:39:42.245122 <30>[ 9.833414] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10893 13:39:42.251358 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10894 13:39:42.273972 <30>[ 9.862150] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10895 13:39:42.280606 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10896 13:39:42.307947 <30>[ 9.889945] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10897 13:39:42.341501 <30>[ 9.930053] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10898 13:39:42.351633 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10899 13:39:42.375088 <30>[ 9.963222] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10900 13:39:42.381517 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10901 13:39:42.407087 <30>[ 9.995142] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10902 13:39:42.413568 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10903 13:39:42.439059 <30>[ 10.027320] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10904 13:39:42.449095 Startin<6>[ 10.036677] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10905 13:39:42.455728 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10906 13:39:42.509860 <30>[ 10.098020] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10907 13:39:42.519855 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10908 13:39:42.540162 <30>[ 10.128627] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10909 13:39:42.546868 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10910 13:39:42.580406 <6>[ 10.171981] fuse: init (API version 7.37)
10911 13:39:42.597688 <30>[ 10.186115] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10912 13:39:42.604406 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10913 13:39:42.634600 <30>[ 10.222799] systemd[1]: Starting systemd-journald.service - Journal Service...
10914 13:39:42.641125 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10915 13:39:42.672697 <30>[ 10.260835] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10916 13:39:42.679047 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10917 13:39:42.707941 <30>[ 10.292521] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10918 13:39:42.714053 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10919 13:39:42.740743 <30>[ 10.329269] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10920 13:39:42.751184 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10921 13:39:42.776653 <30>[ 10.364608] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10922 13:39:42.790140 Starting [0;1;39msyste<3>[ 10.376013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 13:39:42.793292 md-udev-trig…[0m - Coldplug All udev Devices...
10924 13:39:42.818030 <30>[ 10.406042] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10925 13:39:42.824328 <3>[ 10.406959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 13:39:42.834491 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10927 13:39:42.853725 <30>[ 10.442235] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10928 13:39:42.863850 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10929 13:39:42.879539 <3>[ 10.467547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 13:39:42.889412 <30>[ 10.476999] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10931 13:39:42.896209 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10932 13:39:42.911399 <3>[ 10.499830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 13:39:42.922033 <30>[ 10.510245] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10934 13:39:42.932247 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10935 13:39:42.942364 <3>[ 10.530529] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 13:39:42.952933 <30>[ 10.541260] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10937 13:39:42.962763 <30>[ 10.549954] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10938 13:39:42.976489 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 10.564036] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 13:39:42.979589 Load Kernel Module configfs.
10940 13:39:42.998468 <30>[ 10.586131] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10941 13:39:43.004922 <30>[ 10.593814] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10942 13:39:43.014780 <3>[ 10.594316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 13:39:43.021631 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10944 13:39:43.042985 <30>[ 10.631339] systemd[1]: modprobe@drm.service: Deactivated successfully.
10945 13:39:43.049542 <3>[ 10.637114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 13:39:43.056220 <30>[ 10.639432] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10947 13:39:43.067083 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10948 13:39:43.082888 <3>[ 10.671206] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 13:39:43.093838 <30>[ 10.682430] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10950 13:39:43.104424 <30>[ 10.690937] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10951 13:39:43.117676 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 10.704152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 13:39:43.121316 fi_psto…m - Load Kernel Module efi_pstore.
10953 13:39:43.138804 <30>[ 10.727217] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10954 13:39:43.145355 <30>[ 10.734770] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10955 13:39:43.153152 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10956 13:39:43.162473 <3>[ 10.750698] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 13:39:43.174221 <30>[ 10.762700] systemd[1]: modprobe@loop.service: Deactivated successfully.
10958 13:39:43.181524 <30>[ 10.770128] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10959 13:39:43.194730 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 10.782103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 13:39:43.198537 oop.service[0m - Load Kernel Module loop.
10961 13:39:43.218761 <30>[ 10.806072] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10962 13:39:43.225036 <3>[ 10.812216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 13:39:43.242722 <4>[ 10.822952] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10964 13:39:43.249404 <3>[ 10.822955] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10965 13:39:43.259467 <3>[ 10.829881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 13:39:43.266174 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10967 13:39:43.289621 <30>[ 10.874166] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10968 13:39:43.296025 <3>[ 10.877671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 13:39:43.305851 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10970 13:39:43.326381 <30>[ 10.913941] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10971 13:39:43.336697 <3>[ 10.918905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 13:39:43.343201 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10973 13:39:43.362068 <30>[ 10.950027] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10974 13:39:43.372051 <3>[ 10.957669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 13:39:43.378636 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10976 13:39:43.398649 <30>[ 10.986187] systemd[1]: Reached target network-pre.target - Preparation for Network.
10977 13:39:43.405633 <3>[ 10.993609] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:39:43.415331 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10979 13:39:43.458266 <30>[ 11.045556] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10980 13:39:43.464425 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10981 13:39:43.487806 <30>[ 11.076430] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10982 13:39:43.494738 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10983 13:39:43.520394 <30>[ 11.105298] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10984 13:39:43.537110 <30>[ 11.118962] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10985 13:39:43.573220 <30>[ 11.161931] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10986 13:39:43.580009 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10987 13:39:43.606500 <30>[ 11.191703] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10988 13:39:43.619000 <30>[ 11.207459] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10989 13:39:43.625838 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10990 13:39:43.657064 <30>[ 11.245500] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10991 13:39:43.663977 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10992 13:39:43.693039 <30>[ 11.281160] systemd[1]: Started systemd-journald.service - Journal Service.
10993 13:39:43.699541 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10994 13:39:43.722523 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10995 13:39:43.746008 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10996 13:39:43.770599 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10997 13:39:43.790452 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10998 13:39:43.810721 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10999 13:39:43.861863 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11000 13:39:43.888332 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11001 13:39:43.925866 <46>[ 11.514430] systemd-journald[311]: Received client request to flush runtime journal.
11002 13:39:43.978461 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11003 13:39:43.997741 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11004 13:39:44.017192 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11005 13:39:44.734065 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11006 13:39:45.352587 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11007 13:39:45.402220 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11008 13:39:45.478988 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11009 13:39:45.555355 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11010 13:39:45.594261 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11011 13:39:45.863177 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11012 13:39:45.922121 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11013 13:39:45.942015 <6>[ 13.534085] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11014 13:39:45.960922 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11015 13:39:46.093648 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11016 13:39:46.113792 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11017 13:39:46.157215 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11018 13:39:46.177946 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11019 13:39:46.222758 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11020 13:39:46.256270 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11021 13:39:46.274359 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11022 13:39:46.316895 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11023 13:39:46.335207 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11024 13:39:46.369461 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11025 13:39:46.392968 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11026 13:39:46.413098 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11027 13:39:46.433614 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11028 13:39:46.456779 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11029 13:39:46.482580 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11030 13:39:46.503378 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11031 13:39:46.521427 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11032 13:39:46.540510 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11033 13:39:46.560649 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11034 13:39:46.576648 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11035 13:39:46.595117 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11036 13:39:46.612872 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11037 13:39:46.629356 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11038 13:39:46.677926 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11039 13:39:46.735306 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11040 13:39:46.840672 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11041 13:39:46.866031 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11042 13:39:46.952447 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11043 13:39:46.974334 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11044 13:39:47.043528 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11045 13:39:47.064633 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11046 13:39:47.081241 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11047 13:39:47.098145 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11048 13:39:47.188507 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11049 13:39:47.208385 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11050 13:39:47.225388 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11051 13:39:47.285149 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11052 13:39:47.324594 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11053 13:39:47.414036
11054 13:39:47.417165 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11055 13:39:47.417275
11056 13:39:47.424173 debian-bookworm-arm64 login: root (automatic login)
11057 13:39:47.424259
11058 13:39:47.695483 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11059 13:39:47.695612
11060 13:39:47.701960 The programs included with the Debian GNU/Linux system are free software;
11061 13:39:47.708442 the exact distribution terms for each program are described in the
11062 13:39:47.711781 individual files in /usr/share/doc/*/copyright.
11063 13:39:47.711883
11064 13:39:47.718607 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11065 13:39:47.721552 permitted by applicable law.
11066 13:39:48.726224 Matched prompt #10: / #
11068 13:39:48.726493 Setting prompt string to ['/ #']
11069 13:39:48.726592 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11071 13:39:48.726791 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11072 13:39:48.726882 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
11073 13:39:48.726954 Setting prompt string to ['/ #']
11074 13:39:48.727016 Forcing a shell prompt, looking for ['/ #']
11076 13:39:48.777264 / #
11077 13:39:48.777618 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11078 13:39:48.777907 Waiting using forced prompt support (timeout 00:02:30)
11079 13:39:48.782658
11080 13:39:48.783223 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11081 13:39:48.783561 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
11083 13:39:48.884367 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e'
11084 13:39:48.889686 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063028/extract-nfsrootfs-8bkawp2e'
11086 13:39:48.990571 / # export NFS_SERVER_IP='192.168.201.1'
11087 13:39:48.996185 export NFS_SERVER_IP='192.168.201.1'
11088 13:39:48.996626 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11089 13:39:48.996850 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
11090 13:39:48.997062 end: 2 depthcharge-action (duration 00:01:14) [common]
11091 13:39:48.997264 start: 3 lava-test-retry (timeout 00:08:04) [common]
11092 13:39:48.997485 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
11093 13:39:48.997665 Using namespace: common
11095 13:39:49.098204 / # #
11096 13:39:49.098496 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11097 13:39:49.103682 #
11098 13:39:49.104086 Using /lava-14063028
11100 13:39:49.204646 / # export SHELL=/bin/bash
11101 13:39:49.210087 export SHELL=/bin/bash
11103 13:39:49.310626 / # . /lava-14063028/environment
11104 13:39:49.315552 . /lava-14063028/environment
11106 13:39:49.421365 / # /lava-14063028/bin/lava-test-runner /lava-14063028/0
11107 13:39:49.421545 Test shell timeout: 10s (minimum of the action and connection timeout)
11108 13:39:49.426588 /lava-14063028/bin/lava-test-runner /lava-14063028/0
11109 13:39:49.669325 + export TESTRUN_ID=0_timesync-off
11110 13:39:49.672328 + TESTRUN_ID=0_timesync-off
11111 13:39:49.675913 + cd /lava-14063028/0/tests/0_timesync-off
11112 13:39:49.679266 ++ cat uuid
11113 13:39:49.682377 + UUID=14063028_1.6.2.3.1
11114 13:39:49.682462 + set +x
11115 13:39:49.689047 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14063028_1.6.2.3.1>
11116 13:39:49.689335 Received signal: <STARTRUN> 0_timesync-off 14063028_1.6.2.3.1
11117 13:39:49.689431 Starting test lava.0_timesync-off (14063028_1.6.2.3.1)
11118 13:39:49.689522 Skipping test definition patterns.
11119 13:39:49.692501 + systemctl stop systemd-timesyncd
11120 13:39:49.762636 + set +x
11121 13:39:49.765968 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14063028_1.6.2.3.1>
11122 13:39:49.766272 Received signal: <ENDRUN> 0_timesync-off 14063028_1.6.2.3.1
11123 13:39:49.766393 Ending use of test pattern.
11124 13:39:49.766473 Ending test lava.0_timesync-off (14063028_1.6.2.3.1), duration 0.08
11126 13:39:49.824024 + export TESTRUN_ID=1_kselftest-rtc
11127 13:39:49.827009 + TESTRUN_ID=1_kselftest-rtc
11128 13:39:49.830441 + cd /lava-14063028/0/tests/1_kselftest-rtc
11129 13:39:49.833826 ++ cat uuid
11130 13:39:49.836884 + UUID=14063028_1.6.2.3.5
11131 13:39:49.836969 + set +x
11132 13:39:49.840036 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14063028_1.6.2.3.5>
11133 13:39:49.840294 Received signal: <STARTRUN> 1_kselftest-rtc 14063028_1.6.2.3.5
11134 13:39:49.840365 Starting test lava.1_kselftest-rtc (14063028_1.6.2.3.5)
11135 13:39:49.840482 Skipping test definition patterns.
11136 13:39:49.843602 + cd ./automated/linux/kselftest/
11137 13:39:49.869992 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11138 13:39:49.902071 INFO: install_deps skipped
11139 13:39:50.389602 --2024-05-28 13:38:40-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11140 13:39:50.401673 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11141 13:39:50.530685 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11142 13:39:50.662271 HTTP request sent, awaiting response... 200 OK
11143 13:39:50.665696 Length: 1642660 (1.6M) [application/octet-stream]
11144 13:39:50.669130 Saving to: 'kselftest_armhf.tar.gz'
11145 13:39:50.669234
11146 13:39:50.669373
11147 13:39:50.920191 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11148 13:39:51.177791 kselftest_armhf.tar 3%[ ] 49.22K 187KB/s
11149 13:39:51.482174 kselftest_armhf.tar 13%[=> ] 217.50K 413KB/s
11150 13:39:51.614452 kselftest_armhf.tar 51%[=========> ] 825.54K 986KB/s
11151 13:39:51.621207 kselftest_armhf.tar 100%[===================>] 1.57M 1.61MB/s in 1.0s
11152 13:39:51.621365
11153 13:39:51.765160 2024-05-28 13:38:42 (1.61 MB/s) - 'kselftest_armhf.tar.gz' saved [1642660/1642660]
11154 13:39:51.765373
11155 13:39:55.373240 skiplist:
11156 13:39:55.376570 ========================================
11157 13:39:55.379707 ========================================
11158 13:39:55.418176 rtc:rtctest
11159 13:39:55.436479 ============== Tests to run ===============
11160 13:39:55.436574 rtc:rtctest
11161 13:39:55.439787 ===========End Tests to run ===============
11162 13:39:55.442924 shardfile-rtc pass
11163 13:39:55.534153 <12>[ 23.126846] kselftest: Running tests in rtc
11164 13:39:55.542648 TAP version 13
11165 13:39:55.557365 1..1
11166 13:39:55.587010 # selftests: rtc: rtctest
11167 13:39:56.044874 # TAP version 13
11168 13:39:56.045291 # 1..8
11169 13:39:56.048100 # # Starting 8 tests from 2 test cases.
11170 13:39:56.051687 # # RUN rtc.date_read ...
11171 13:39:56.058172 # # rtctest.c:49:date_read:Current RTC date/time is 28/05/2024 13:38:46.
11172 13:39:56.061945 # # OK rtc.date_read
11173 13:39:56.064756 # ok 1 rtc.date_read
11174 13:39:56.068388 # # RUN rtc.date_read_loop ...
11175 13:39:56.078153 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11176 13:40:08.045622 <6>[ 35.643464] vpu: disabling
11177 13:40:08.052488 <6>[ 35.650192] vproc2: disabling
11178 13:40:08.055580 <6>[ 35.653686] vproc1: disabling
11179 13:40:08.059129 <6>[ 35.657012] vaud18: disabling
11180 13:40:08.065699 <6>[ 35.660522] vsram_others: disabling
11181 13:40:08.069202 <6>[ 35.664478] va09: disabling
11182 13:40:08.072763 <6>[ 35.667644] vsram_md: disabling
11183 13:40:08.075624 <6>[ 35.671207] Vgpu: disabling
11184 13:40:26.639792 # # rtctest.c:115:date_read_loop:Performed 2689 RTC time reads.
11185 13:40:26.643281 # # OK rtc.date_read_loop
11186 13:40:26.646866 # ok 2 rtc.date_read_loop
11187 13:40:26.649912 # # RUN rtc.uie_read ...
11188 13:40:29.618488 # # OK rtc.uie_read
11189 13:40:29.621822 # ok 3 rtc.uie_read
11190 13:40:29.625276 # # RUN rtc.uie_select ...
11191 13:40:32.618138 # # OK rtc.uie_select
11192 13:40:32.621510 # ok 4 rtc.uie_select
11193 13:40:32.624390 # # RUN rtc.alarm_alm_set ...
11194 13:40:32.630995 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 13:39:26.
11195 13:40:32.634664 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11196 13:40:32.641069 # # alarm_alm_set: Test terminated by assertion
11197 13:40:32.644497 # # FAIL rtc.alarm_alm_set
11198 13:40:32.644865 # not ok 5 rtc.alarm_alm_set
11199 13:40:32.650917 # # RUN rtc.alarm_wkalm_set ...
11200 13:40:32.657817 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 28/05/2024 13:39:26.
11201 13:40:35.661992 # # OK rtc.alarm_wkalm_set
11202 13:40:35.662518 # ok 6 rtc.alarm_wkalm_set
11203 13:40:35.662859 # # RUN rtc.alarm_alm_set_minute ...
11204 13:40:35.663214 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 13:40:00.
11205 13:40:35.663526 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11206 13:40:35.663825 # # alarm_alm_set_minute: Test terminated by assertion
11207 13:40:35.664117 # # FAIL rtc.alarm_alm_set_minute
11208 13:40:35.664403 # not ok 7 rtc.alarm_alm_set_minute
11209 13:40:35.664684 # # RUN rtc.alarm_wkalm_set_minute ...
11210 13:40:35.664978 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 28/05/2024 13:40:00.
11211 13:41:09.616938 # # OK rtc.alarm_wkalm_set_minute
11212 13:41:09.620313 # ok 8 rtc.alarm_wkalm_set_minute
11213 13:41:09.620873 # # FAILED: 6 / 8 tests passed.
11214 13:41:09.626984 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11215 13:41:09.630102 not ok 1 selftests: rtc: rtctest # exit=1
11216 13:41:11.632322 rtc_rtctest_rtc_date_read pass
11217 13:41:11.635473 rtc_rtctest_rtc_date_read_loop pass
11218 13:41:11.638935 rtc_rtctest_rtc_uie_read pass
11219 13:41:11.641918 rtc_rtctest_rtc_uie_select pass
11220 13:41:11.645266 rtc_rtctest_rtc_alarm_alm_set fail
11221 13:41:11.648339 rtc_rtctest_rtc_alarm_wkalm_set pass
11222 13:41:11.651806 rtc_rtctest_rtc_alarm_alm_set_minute fail
11223 13:41:11.655538 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11224 13:41:11.658529 rtc_rtctest fail
11225 13:41:11.707352 + ../../utils/send-to-lava.sh ./output/result.txt
11226 13:41:11.819672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11227 13:41:11.820000 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11229 13:41:11.851394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11230 13:41:11.851705 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11232 13:41:11.886764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11233 13:41:11.887050 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11235 13:41:11.911556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11236 13:41:11.911853 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11238 13:41:11.939013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11239 13:41:11.939285 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11241 13:41:11.979050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11242 13:41:11.979431 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11244 13:41:12.014119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11245 13:41:12.014525 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11247 13:41:12.054010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11248 13:41:12.054652 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11250 13:41:12.088603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11251 13:41:12.089139 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11253 13:41:12.125198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11254 13:41:12.125382 + set +x
11255 13:41:12.125648 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11257 13:41:12.131631 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14063028_1.6.2.3.5>
11258 13:41:12.131984 Received signal: <ENDRUN> 1_kselftest-rtc 14063028_1.6.2.3.5
11259 13:41:12.132077 Ending use of test pattern.
11260 13:41:12.132151 Ending test lava.1_kselftest-rtc (14063028_1.6.2.3.5), duration 82.29
11262 13:41:12.132416 ok: lava_test_shell seems to have completed
11263 13:41:12.132573 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11264 13:41:12.132678 end: 3.1 lava-test-shell (duration 00:01:23) [common]
11265 13:41:12.132773 end: 3 lava-test-retry (duration 00:01:23) [common]
11266 13:41:12.132872 start: 4 finalize (timeout 00:06:41) [common]
11267 13:41:12.132980 start: 4.1 power-off (timeout 00:00:30) [common]
11268 13:41:12.133166 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11269 13:41:12.396414 >> Command sent successfully.
11270 13:41:12.399193 Returned 0 in 0 seconds
11271 13:41:12.499885 end: 4.1 power-off (duration 00:00:00) [common]
11273 13:41:12.501432 start: 4.2 read-feedback (timeout 00:06:40) [common]
11275 13:41:12.503540 Listened to connection for namespace 'common' for up to 1s
11276 13:41:13.503264 Finalising connection for namespace 'common'
11277 13:41:13.503874 Disconnecting from shell: Finalise
11278 13:41:13.504578 / #
11279 13:41:13.605552 end: 4.2 read-feedback (duration 00:00:01) [common]
11280 13:41:13.606209 end: 4 finalize (duration 00:00:01) [common]
11281 13:41:13.606768 Cleaning after the job
11282 13:41:13.607234 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/ramdisk
11283 13:41:13.616629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/kernel
11284 13:41:13.649173 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/dtb
11285 13:41:13.649527 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/nfsrootfs
11286 13:41:13.716976 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063028/tftp-deploy-13dlhag1/modules
11287 13:41:13.722590 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063028
11288 13:41:14.245658 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063028
11289 13:41:14.245837 Job finished correctly