Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 13:42:15.182886 lava-dispatcher, installed at version: 2024.03
2 13:42:15.183087 start: 0 validate
3 13:42:15.183218 Start time: 2024-05-28 13:42:15.183208+00:00 (UTC)
4 13:42:15.183365 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:42:15.183493 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:42:15.443602 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:42:15.444311 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:42:15.706993 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:42:15.707723 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:42:15.960197 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:42:15.960967 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:42:16.213858 Using caching service: 'http://localhost/cache/?uri=%s'
13 13:42:16.214621 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 13:42:16.480254 validate duration: 1.30
16 13:42:16.480520 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:42:16.480621 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:42:16.480706 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:42:16.480827 Not decompressing ramdisk as can be used compressed.
20 13:42:16.480914 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 13:42:16.480979 saving as /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/ramdisk/initrd.cpio.gz
22 13:42:16.481044 total size: 5628169 (5 MB)
23 13:42:16.482173 progress 0 % (0 MB)
24 13:42:16.483794 progress 5 % (0 MB)
25 13:42:16.485341 progress 10 % (0 MB)
26 13:42:16.486738 progress 15 % (0 MB)
27 13:42:16.488262 progress 20 % (1 MB)
28 13:42:16.489702 progress 25 % (1 MB)
29 13:42:16.491257 progress 30 % (1 MB)
30 13:42:16.492781 progress 35 % (1 MB)
31 13:42:16.494192 progress 40 % (2 MB)
32 13:42:16.495714 progress 45 % (2 MB)
33 13:42:16.497074 progress 50 % (2 MB)
34 13:42:16.498596 progress 55 % (2 MB)
35 13:42:16.500112 progress 60 % (3 MB)
36 13:42:16.501525 progress 65 % (3 MB)
37 13:42:16.503036 progress 70 % (3 MB)
38 13:42:16.504397 progress 75 % (4 MB)
39 13:42:16.505935 progress 80 % (4 MB)
40 13:42:16.507270 progress 85 % (4 MB)
41 13:42:16.508756 progress 90 % (4 MB)
42 13:42:16.510281 progress 95 % (5 MB)
43 13:42:16.511690 progress 100 % (5 MB)
44 13:42:16.511895 5 MB downloaded in 0.03 s (173.99 MB/s)
45 13:42:16.512092 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:42:16.512331 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:42:16.512418 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:42:16.512501 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:42:16.512629 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 13:42:16.512699 saving as /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/kernel/Image
52 13:42:16.512761 total size: 54682112 (52 MB)
53 13:42:16.512823 No compression specified
54 13:42:16.513939 progress 0 % (0 MB)
55 13:42:16.527339 progress 5 % (2 MB)
56 13:42:16.540806 progress 10 % (5 MB)
57 13:42:16.554288 progress 15 % (7 MB)
58 13:42:16.567616 progress 20 % (10 MB)
59 13:42:16.581220 progress 25 % (13 MB)
60 13:42:16.594756 progress 30 % (15 MB)
61 13:42:16.608404 progress 35 % (18 MB)
62 13:42:16.621855 progress 40 % (20 MB)
63 13:42:16.635129 progress 45 % (23 MB)
64 13:42:16.648813 progress 50 % (26 MB)
65 13:42:16.662405 progress 55 % (28 MB)
66 13:42:16.676121 progress 60 % (31 MB)
67 13:42:16.690846 progress 65 % (33 MB)
68 13:42:16.704949 progress 70 % (36 MB)
69 13:42:16.718498 progress 75 % (39 MB)
70 13:42:16.732174 progress 80 % (41 MB)
71 13:42:16.745565 progress 85 % (44 MB)
72 13:42:16.759056 progress 90 % (46 MB)
73 13:42:16.772643 progress 95 % (49 MB)
74 13:42:16.785956 progress 100 % (52 MB)
75 13:42:16.786184 52 MB downloaded in 0.27 s (190.73 MB/s)
76 13:42:16.786335 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:42:16.786582 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:42:16.786670 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:42:16.786755 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:42:16.786886 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 13:42:16.786957 saving as /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/dtb/mt8192-asurada-spherion-r0.dtb
83 13:42:16.787020 total size: 47258 (0 MB)
84 13:42:16.787083 No compression specified
85 13:42:16.788194 progress 69 % (0 MB)
86 13:42:16.788470 progress 100 % (0 MB)
87 13:42:16.788626 0 MB downloaded in 0.00 s (28.10 MB/s)
88 13:42:16.788749 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:42:16.788970 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:42:16.789055 start: 1.4 download-retry (timeout 00:10:00) [common]
92 13:42:16.789139 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 13:42:16.789248 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 13:42:16.789346 saving as /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/nfsrootfs/full.rootfs.tar
95 13:42:16.789424 total size: 120894716 (115 MB)
96 13:42:16.789487 Using unxz to decompress xz
97 13:42:16.792983 progress 0 % (0 MB)
98 13:42:17.133270 progress 5 % (5 MB)
99 13:42:17.479420 progress 10 % (11 MB)
100 13:42:17.822485 progress 15 % (17 MB)
101 13:42:18.149829 progress 20 % (23 MB)
102 13:42:18.435972 progress 25 % (28 MB)
103 13:42:18.786509 progress 30 % (34 MB)
104 13:42:19.122486 progress 35 % (40 MB)
105 13:42:19.284153 progress 40 % (46 MB)
106 13:42:19.459927 progress 45 % (51 MB)
107 13:42:19.763246 progress 50 % (57 MB)
108 13:42:20.138944 progress 55 % (63 MB)
109 13:42:20.474487 progress 60 % (69 MB)
110 13:42:20.808139 progress 65 % (74 MB)
111 13:42:21.150760 progress 70 % (80 MB)
112 13:42:21.501246 progress 75 % (86 MB)
113 13:42:21.833001 progress 80 % (92 MB)
114 13:42:22.167585 progress 85 % (98 MB)
115 13:42:22.519523 progress 90 % (103 MB)
116 13:42:22.840891 progress 95 % (109 MB)
117 13:42:23.195783 progress 100 % (115 MB)
118 13:42:23.201335 115 MB downloaded in 6.41 s (17.98 MB/s)
119 13:42:23.201745 end: 1.4.1 http-download (duration 00:00:06) [common]
121 13:42:23.202136 end: 1.4 download-retry (duration 00:00:06) [common]
122 13:42:23.202231 start: 1.5 download-retry (timeout 00:09:53) [common]
123 13:42:23.202319 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 13:42:23.202467 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 13:42:23.202537 saving as /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/modules/modules.tar
126 13:42:23.202598 total size: 8607916 (8 MB)
127 13:42:23.202664 Using unxz to decompress xz
128 13:42:23.206883 progress 0 % (0 MB)
129 13:42:23.226688 progress 5 % (0 MB)
130 13:42:23.250939 progress 10 % (0 MB)
131 13:42:23.276046 progress 15 % (1 MB)
132 13:42:23.300823 progress 20 % (1 MB)
133 13:42:23.325976 progress 25 % (2 MB)
134 13:42:23.350377 progress 30 % (2 MB)
135 13:42:23.373437 progress 35 % (2 MB)
136 13:42:23.399377 progress 40 % (3 MB)
137 13:42:23.423936 progress 45 % (3 MB)
138 13:42:23.447798 progress 50 % (4 MB)
139 13:42:23.472396 progress 55 % (4 MB)
140 13:42:23.496867 progress 60 % (4 MB)
141 13:42:23.520559 progress 65 % (5 MB)
142 13:42:23.546407 progress 70 % (5 MB)
143 13:42:23.572967 progress 75 % (6 MB)
144 13:42:23.596370 progress 80 % (6 MB)
145 13:42:23.619798 progress 85 % (7 MB)
146 13:42:23.643183 progress 90 % (7 MB)
147 13:42:23.671897 progress 95 % (7 MB)
148 13:42:23.699751 progress 100 % (8 MB)
149 13:42:23.705546 8 MB downloaded in 0.50 s (16.32 MB/s)
150 13:42:23.705803 end: 1.5.1 http-download (duration 00:00:01) [common]
152 13:42:23.706066 end: 1.5 download-retry (duration 00:00:01) [common]
153 13:42:23.706160 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 13:42:23.706254 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 13:42:26.965857 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha
156 13:42:26.966052 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 13:42:26.966153 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 13:42:26.966320 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2
159 13:42:26.966447 makedir: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin
160 13:42:26.966544 makedir: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/tests
161 13:42:26.966638 makedir: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/results
162 13:42:26.966738 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-add-keys
163 13:42:26.966875 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-add-sources
164 13:42:26.966997 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-background-process-start
165 13:42:26.967124 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-background-process-stop
166 13:42:26.967254 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-common-functions
167 13:42:26.967374 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-echo-ipv4
168 13:42:26.967491 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-install-packages
169 13:42:26.967609 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-installed-packages
170 13:42:26.967725 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-os-build
171 13:42:26.967842 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-probe-channel
172 13:42:26.967958 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-probe-ip
173 13:42:26.968072 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-target-ip
174 13:42:26.968186 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-target-mac
175 13:42:26.968300 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-target-storage
176 13:42:26.968416 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-case
177 13:42:26.968534 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-event
178 13:42:26.968649 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-feedback
179 13:42:26.968768 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-raise
180 13:42:26.968884 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-reference
181 13:42:26.969018 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-runner
182 13:42:26.969137 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-set
183 13:42:26.969382 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-test-shell
184 13:42:26.969616 Updating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-add-keys (debian)
185 13:42:26.969900 Updating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-add-sources (debian)
186 13:42:26.970125 Updating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-install-packages (debian)
187 13:42:26.970347 Updating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-installed-packages (debian)
188 13:42:26.970558 Updating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/bin/lava-os-build (debian)
189 13:42:26.970724 Creating /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/environment
190 13:42:26.970859 LAVA metadata
191 13:42:26.971007 - LAVA_JOB_ID=14063105
192 13:42:26.971122 - LAVA_DISPATCHER_IP=192.168.201.1
193 13:42:26.971268 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
194 13:42:26.971370 skipped lava-vland-overlay
195 13:42:26.971512 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 13:42:26.971648 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
197 13:42:26.971711 skipped lava-multinode-overlay
198 13:42:26.971791 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 13:42:26.971882 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
200 13:42:26.971973 Loading test definitions
201 13:42:26.972064 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
202 13:42:26.972137 Using /lava-14063105 at stage 0
203 13:42:26.972420 uuid=14063105_1.6.2.3.1 testdef=None
204 13:42:26.972522 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 13:42:26.972604 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
206 13:42:26.973034 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 13:42:26.973245 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
209 13:42:26.973955 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 13:42:26.974180 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
212 13:42:26.974693 runner path: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/0/tests/0_timesync-off test_uuid 14063105_1.6.2.3.1
213 13:42:26.974840 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 13:42:26.975057 start: 1.6.2.3.5 git-repo-action (timeout 00:09:50) [common]
216 13:42:26.975128 Using /lava-14063105 at stage 0
217 13:42:26.975223 Fetching tests from https://github.com/kernelci/test-definitions.git
218 13:42:26.975307 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/0/tests/1_kselftest-tpm2'
219 13:42:29.628127 Running '/usr/bin/git checkout kernelci.org
220 13:42:29.769780 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 13:42:29.770482 uuid=14063105_1.6.2.3.5 testdef=None
222 13:42:29.770635 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 13:42:29.770879 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 13:42:29.771605 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 13:42:29.771830 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 13:42:29.772762 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 13:42:29.772997 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 13:42:29.773967 runner path: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/0/tests/1_kselftest-tpm2 test_uuid 14063105_1.6.2.3.5
232 13:42:29.774057 BOARD='mt8192-asurada-spherion-r0'
233 13:42:29.774121 BRANCH='cip'
234 13:42:29.774179 SKIPFILE='/dev/null'
235 13:42:29.774236 SKIP_INSTALL='True'
236 13:42:29.774290 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 13:42:29.774347 TST_CASENAME=''
238 13:42:29.774400 TST_CMDFILES='tpm2'
239 13:42:29.774533 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 13:42:29.774734 Creating lava-test-runner.conf files
242 13:42:29.774797 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063105/lava-overlay-mgb1nsl2/lava-14063105/0 for stage 0
243 13:42:29.774886 - 0_timesync-off
244 13:42:29.774955 - 1_kselftest-tpm2
245 13:42:29.775046 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 13:42:29.775133 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 13:42:37.245860 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 13:42:37.246022 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 13:42:37.246114 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 13:42:37.246214 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 13:42:37.246305 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 13:42:37.406045 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 13:42:37.406415 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 13:42:37.406529 extracting modules file /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha
255 13:42:37.620572 extracting modules file /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063105/extract-overlay-ramdisk-qo1y18i2/ramdisk
256 13:42:37.827602 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 13:42:37.827780 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 13:42:37.827880 [common] Applying overlay to NFS
259 13:42:37.827953 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063105/compress-overlay-rgrtypz4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha
260 13:42:38.735737 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 13:42:38.735904 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 13:42:38.735999 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 13:42:38.736093 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 13:42:38.736181 Building ramdisk /var/lib/lava/dispatcher/tmp/14063105/extract-overlay-ramdisk-qo1y18i2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063105/extract-overlay-ramdisk-qo1y18i2/ramdisk
265 13:42:39.060325 >> 130335 blocks
266 13:42:41.138974 rename /var/lib/lava/dispatcher/tmp/14063105/extract-overlay-ramdisk-qo1y18i2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/ramdisk/ramdisk.cpio.gz
267 13:42:41.139439 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 13:42:41.139571 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 13:42:41.139673 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 13:42:41.139776 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/kernel/Image']
271 13:42:54.810336 Returned 0 in 13 seconds
272 13:42:54.910978 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/kernel/image.itb
273 13:42:55.254576 output: FIT description: Kernel Image image with one or more FDT blobs
274 13:42:55.254934 output: Created: Tue May 28 14:42:55 2024
275 13:42:55.255015 output: Image 0 (kernel-1)
276 13:42:55.255090 output: Description:
277 13:42:55.255155 output: Created: Tue May 28 14:42:55 2024
278 13:42:55.255219 output: Type: Kernel Image
279 13:42:55.255279 output: Compression: lzma compressed
280 13:42:55.255339 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
281 13:42:55.255398 output: Architecture: AArch64
282 13:42:55.255454 output: OS: Linux
283 13:42:55.255510 output: Load Address: 0x00000000
284 13:42:55.255562 output: Entry Point: 0x00000000
285 13:42:55.255615 output: Hash algo: crc32
286 13:42:55.255669 output: Hash value: 0578ee26
287 13:42:55.255724 output: Image 1 (fdt-1)
288 13:42:55.255777 output: Description: mt8192-asurada-spherion-r0
289 13:42:55.255830 output: Created: Tue May 28 14:42:55 2024
290 13:42:55.255881 output: Type: Flat Device Tree
291 13:42:55.255933 output: Compression: uncompressed
292 13:42:55.255985 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 13:42:55.256037 output: Architecture: AArch64
294 13:42:55.256088 output: Hash algo: crc32
295 13:42:55.256139 output: Hash value: 0f8e4d2e
296 13:42:55.256190 output: Image 2 (ramdisk-1)
297 13:42:55.256241 output: Description: unavailable
298 13:42:55.256293 output: Created: Tue May 28 14:42:55 2024
299 13:42:55.256345 output: Type: RAMDisk Image
300 13:42:55.256396 output: Compression: Unknown Compression
301 13:42:55.256449 output: Data Size: 18735926 Bytes = 18296.80 KiB = 17.87 MiB
302 13:42:55.256500 output: Architecture: AArch64
303 13:42:55.256551 output: OS: Linux
304 13:42:55.256602 output: Load Address: unavailable
305 13:42:55.256653 output: Entry Point: unavailable
306 13:42:55.256704 output: Hash algo: crc32
307 13:42:55.256755 output: Hash value: 2618e369
308 13:42:55.256808 output: Default Configuration: 'conf-1'
309 13:42:55.256859 output: Configuration 0 (conf-1)
310 13:42:55.256909 output: Description: mt8192-asurada-spherion-r0
311 13:42:55.256961 output: Kernel: kernel-1
312 13:42:55.257012 output: Init Ramdisk: ramdisk-1
313 13:42:55.257063 output: FDT: fdt-1
314 13:42:55.257114 output: Loadables: kernel-1
315 13:42:55.257165 output:
316 13:42:55.257401 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 13:42:55.257503 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 13:42:55.257606 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 13:42:55.257701 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 13:42:55.257775 No LXC device requested
321 13:42:55.257850 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 13:42:55.257936 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 13:42:55.258012 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 13:42:55.258076 Checking files for TFTP limit of 4294967296 bytes.
325 13:42:55.258560 end: 1 tftp-deploy (duration 00:00:39) [common]
326 13:42:55.258666 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 13:42:55.258756 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 13:42:55.258879 substitutions:
329 13:42:55.258944 - {DTB}: 14063105/tftp-deploy-o8z8wbql/dtb/mt8192-asurada-spherion-r0.dtb
330 13:42:55.259004 - {INITRD}: 14063105/tftp-deploy-o8z8wbql/ramdisk/ramdisk.cpio.gz
331 13:42:55.259063 - {KERNEL}: 14063105/tftp-deploy-o8z8wbql/kernel/Image
332 13:42:55.259119 - {LAVA_MAC}: None
333 13:42:55.259174 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha
334 13:42:55.259229 - {NFS_SERVER_IP}: 192.168.201.1
335 13:42:55.259282 - {PRESEED_CONFIG}: None
336 13:42:55.259335 - {PRESEED_LOCAL}: None
337 13:42:55.259388 - {RAMDISK}: 14063105/tftp-deploy-o8z8wbql/ramdisk/ramdisk.cpio.gz
338 13:42:55.259441 - {ROOT_PART}: None
339 13:42:55.259494 - {ROOT}: None
340 13:42:55.259546 - {SERVER_IP}: 192.168.201.1
341 13:42:55.259598 - {TEE}: None
342 13:42:55.259651 Parsed boot commands:
343 13:42:55.259705 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 13:42:55.259877 Parsed boot commands: tftpboot 192.168.201.1 14063105/tftp-deploy-o8z8wbql/kernel/image.itb 14063105/tftp-deploy-o8z8wbql/kernel/cmdline
345 13:42:55.259964 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 13:42:55.260045 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 13:42:55.260133 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 13:42:55.260215 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 13:42:55.260287 Not connected, no need to disconnect.
350 13:42:55.260359 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 13:42:55.260441 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 13:42:55.260506 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 13:42:55.263827 Setting prompt string to ['lava-test: # ']
354 13:42:55.264160 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 13:42:55.264268 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 13:42:55.264365 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 13:42:55.264487 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 13:42:55.264655 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 13:43:08.830900 Returned 0 in 13 seconds
360 13:43:08.931629 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 13:43:08.931956 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 13:43:08.932058 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 13:43:08.932144 Setting prompt string to 'Starting depthcharge on Spherion...'
365 13:43:08.932213 Changing prompt to 'Starting depthcharge on Spherion...'
366 13:43:08.932284 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 13:43:08.932797 [Enter `^Ec?' for help]
368 13:43:08.932929
369 13:43:08.933032
370 13:43:08.933129 F0: 102B 0000
371 13:43:08.933222
372 13:43:08.933342 F3: 1001 0000 [0200]
373 13:43:08.933452
374 13:43:08.933513 F3: 1001 0000
375 13:43:08.933583
376 13:43:08.933642 F7: 102D 0000
377 13:43:08.933699
378 13:43:08.933755 F1: 0000 0000
379 13:43:08.933811
380 13:43:08.933867 V0: 0000 0000 [0001]
381 13:43:08.933926
382 13:43:08.933999 00: 0007 8000
383 13:43:08.934072
384 13:43:08.934126 01: 0000 0000
385 13:43:08.934212
386 13:43:08.934265 BP: 0C00 0209 [0000]
387 13:43:08.934320
388 13:43:08.934375 G0: 1182 0000
389 13:43:08.934430
390 13:43:08.934483 EC: 0000 0021 [4000]
391 13:43:08.934538
392 13:43:08.934591 S7: 0000 0000 [0000]
393 13:43:08.934645
394 13:43:08.934699 CC: 0000 0000 [0001]
395 13:43:08.934754
396 13:43:08.934808 T0: 0000 0040 [010F]
397 13:43:08.934863
398 13:43:08.934917 Jump to BL
399 13:43:08.934972
400 13:43:08.935033
401 13:43:08.935093
402 13:43:08.935181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 13:43:08.935240 ARM64: Exception handlers installed.
404 13:43:08.935297 ARM64: Testing exception
405 13:43:08.935353 ARM64: Done test exception
406 13:43:08.935407 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 13:43:08.935463 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 13:43:08.935518 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 13:43:08.935574 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 13:43:08.935629 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 13:43:08.935685 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 13:43:08.935757 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 13:43:08.935830 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 13:43:08.935885 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 13:43:08.935963 WDT: Last reset was cold boot
416 13:43:08.936044 SPI1(PAD0) initialized at 2873684 Hz
417 13:43:08.936111 SPI5(PAD0) initialized at 992727 Hz
418 13:43:08.936168 VBOOT: Loading verstage.
419 13:43:08.936223 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 13:43:08.936279 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 13:43:08.936334 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 13:43:08.936423 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 13:43:08.936479 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 13:43:08.936534 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 13:43:08.936589 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 13:43:08.936644
427 13:43:08.936699
428 13:43:08.936755 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 13:43:08.936811 ARM64: Exception handlers installed.
430 13:43:08.936872 ARM64: Testing exception
431 13:43:08.936928 ARM64: Done test exception
432 13:43:08.937014 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 13:43:08.937069 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 13:43:08.937125 Probing TPM: . done!
435 13:43:08.937179 TPM ready after 0 ms
436 13:43:08.937233 Connected to device vid:did:rid of 1ae0:0028:00
437 13:43:08.937288 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 13:43:08.937382 Initialized TPM device CR50 revision 0
439 13:43:08.937437 tlcl_send_startup: Startup return code is 0
440 13:43:08.937491 TPM: setup succeeded
441 13:43:08.937546 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 13:43:08.937632 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 13:43:08.937687 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 13:43:08.937742 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 13:43:08.937797 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 13:43:08.937852 in-header: 03 07 00 00 08 00 00 00
447 13:43:08.937907 in-data: aa e4 47 04 13 02 00 00
448 13:43:08.937961 Chrome EC: UHEPI supported
449 13:43:08.938015 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 13:43:08.938070 in-header: 03 a9 00 00 08 00 00 00
451 13:43:08.938124 in-data: 84 60 60 08 00 00 00 00
452 13:43:08.938209 Phase 1
453 13:43:08.938263 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 13:43:08.938318 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 13:43:08.938373 VB2:vb2_check_recovery() Recovery was requested manually
456 13:43:08.938428 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 13:43:08.938483 Recovery requested (1009000e)
458 13:43:08.938537 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 13:43:08.938592 tlcl_extend: response is 0
460 13:43:08.938646 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 13:43:08.938701 tlcl_extend: response is 0
462 13:43:08.938772 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 13:43:08.938841 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 13:43:08.938896 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 13:43:08.938951
466 13:43:08.939005
467 13:43:08.939060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 13:43:08.939115 ARM64: Exception handlers installed.
469 13:43:08.939170 ARM64: Testing exception
470 13:43:08.939224 ARM64: Done test exception
471 13:43:08.939278 pmic_efuse_setting: Set efuses in 11 msecs
472 13:43:08.939333 pmwrap_interface_init: Select PMIF_VLD_RDY
473 13:43:08.939418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 13:43:08.939473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 13:43:08.939721 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 13:43:08.939784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 13:43:08.939840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 13:43:08.939895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 13:43:08.939951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 13:43:08.940006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 13:43:08.940061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 13:43:08.940121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 13:43:08.940176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 13:43:08.940231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 13:43:08.940286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 13:43:08.940340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 13:43:08.940395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 13:43:08.940449 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 13:43:08.940504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 13:43:08.940558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 13:43:08.940613 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 13:43:08.940667 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 13:43:08.940722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 13:43:08.940777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 13:43:08.940831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 13:43:08.940885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 13:43:08.940940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 13:43:08.940995 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 13:43:08.941049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 13:43:08.941104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 13:43:08.941159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 13:43:08.941213 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 13:43:08.941267 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 13:43:08.941329 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 13:43:08.941384 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 13:43:08.941439 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 13:43:08.941493 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 13:43:08.941547 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 13:43:08.941602 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 13:43:08.941657 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 13:43:08.941712 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 13:43:08.941766 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 13:43:08.941821 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 13:43:08.941876 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 13:43:08.941930 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 13:43:08.941985 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 13:43:08.942040 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 13:43:08.942094 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 13:43:08.942149 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 13:43:08.942203 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 13:43:08.942257 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 13:43:08.942311 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 13:43:08.942365 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 13:43:08.942420 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 13:43:08.942475 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 13:43:08.942530 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 13:43:08.942585 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 13:43:08.942640 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 13:43:08.942695 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 13:43:08.942749 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 13:43:08.942804 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 13:43:08.942858 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 13:43:08.942913 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 13:43:08.942968 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 13:43:08.943023 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 13:43:08.943077 [RTC]rtc_get_frequency_meter,154: input=15, output=774
537 13:43:08.943132 [RTC]rtc_get_frequency_meter,154: input=23, output=957
538 13:43:08.943186 [RTC]rtc_get_frequency_meter,154: input=19, output=865
539 13:43:08.943240 [RTC]rtc_get_frequency_meter,154: input=17, output=819
540 13:43:08.943294 [RTC]rtc_get_frequency_meter,154: input=16, output=796
541 13:43:08.943349 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 13:43:08.943403 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 13:43:08.943463 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
544 13:43:08.943519 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 13:43:08.943762 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
546 13:43:08.943875 ADC[4]: Raw value=903245 ID=7
547 13:43:08.943981 ADC[3]: Raw value=213179 ID=1
548 13:43:08.944086 RAM Code: 0x71
549 13:43:08.944191 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 13:43:08.944299 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 13:43:08.944408 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 13:43:08.944513 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 13:43:08.944633 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 13:43:08.944720 in-header: 03 07 00 00 08 00 00 00
555 13:43:08.944805 in-data: aa e4 47 04 13 02 00 00
556 13:43:08.944889 Chrome EC: UHEPI supported
557 13:43:08.944975 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 13:43:08.945078 in-header: 03 a9 00 00 08 00 00 00
559 13:43:08.945177 in-data: 84 60 60 08 00 00 00 00
560 13:43:08.945262 MRC: failed to locate region type 0.
561 13:43:08.945383 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 13:43:08.945469 DRAM-K: Running full calibration
563 13:43:08.945554 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 13:43:08.945639 header.status = 0x0
565 13:43:08.945723 header.version = 0x6 (expected: 0x6)
566 13:43:08.945807 header.size = 0xd00 (expected: 0xd00)
567 13:43:08.945892 header.flags = 0x0
568 13:43:08.945977 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 13:43:08.946062 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
570 13:43:08.946148 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 13:43:08.946233 dram_init: ddr_geometry: 2
572 13:43:08.946317 [EMI] MDL number = 2
573 13:43:08.946401 [EMI] Get MDL freq = 0
574 13:43:08.946485 dram_init: ddr_type: 0
575 13:43:08.946569 is_discrete_lpddr4: 1
576 13:43:08.946653 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 13:43:08.946737
578 13:43:08.946820
579 13:43:08.946905 [Bian_co] ETT version 0.0.0.1
580 13:43:08.946990 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 13:43:08.947074
582 13:43:08.947158 dramc_set_vcore_voltage set vcore to 650000
583 13:43:08.947243 Read voltage for 800, 4
584 13:43:08.947326 Vio18 = 0
585 13:43:08.947410 Vcore = 650000
586 13:43:08.947494 Vdram = 0
587 13:43:08.947577 Vddq = 0
588 13:43:08.947661 Vmddr = 0
589 13:43:08.947744 dram_init: config_dvfs: 1
590 13:43:08.947829 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 13:43:08.947914 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 13:43:08.947999 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 13:43:08.948084 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 13:43:08.948171 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 13:43:08.948255 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 13:43:08.948340 MEM_TYPE=3, freq_sel=18
597 13:43:08.948424 sv_algorithm_assistance_LP4_1600
598 13:43:08.948508 ============ PULL DRAM RESETB DOWN ============
599 13:43:08.948596 ========== PULL DRAM RESETB DOWN end =========
600 13:43:08.948681 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 13:43:08.948766 ===================================
602 13:43:08.948850 LPDDR4 DRAM CONFIGURATION
603 13:43:08.948934 ===================================
604 13:43:08.949018 EX_ROW_EN[0] = 0x0
605 13:43:08.949102 EX_ROW_EN[1] = 0x0
606 13:43:08.949186 LP4Y_EN = 0x0
607 13:43:08.949287 WORK_FSP = 0x0
608 13:43:08.949367 WL = 0x2
609 13:43:08.949422 RL = 0x2
610 13:43:08.949476 BL = 0x2
611 13:43:08.949530 RPST = 0x0
612 13:43:08.949584 RD_PRE = 0x0
613 13:43:08.949638 WR_PRE = 0x1
614 13:43:08.949693 WR_PST = 0x0
615 13:43:08.949746 DBI_WR = 0x0
616 13:43:08.949800 DBI_RD = 0x0
617 13:43:08.949854 OTF = 0x1
618 13:43:08.949909 ===================================
619 13:43:08.949963 ===================================
620 13:43:08.950018 ANA top config
621 13:43:08.950072 ===================================
622 13:43:08.950126 DLL_ASYNC_EN = 0
623 13:43:08.950181 ALL_SLAVE_EN = 1
624 13:43:08.950235 NEW_RANK_MODE = 1
625 13:43:08.950290 DLL_IDLE_MODE = 1
626 13:43:08.950344 LP45_APHY_COMB_EN = 1
627 13:43:08.950398 TX_ODT_DIS = 1
628 13:43:08.950453 NEW_8X_MODE = 1
629 13:43:08.950508 ===================================
630 13:43:08.950561 ===================================
631 13:43:08.950615 data_rate = 1600
632 13:43:08.950669 CKR = 1
633 13:43:08.950723 DQ_P2S_RATIO = 8
634 13:43:08.950776 ===================================
635 13:43:08.950831 CA_P2S_RATIO = 8
636 13:43:08.950884 DQ_CA_OPEN = 0
637 13:43:08.950954 DQ_SEMI_OPEN = 0
638 13:43:08.951009 CA_SEMI_OPEN = 0
639 13:43:08.951064 CA_FULL_RATE = 0
640 13:43:08.951118 DQ_CKDIV4_EN = 1
641 13:43:08.951172 CA_CKDIV4_EN = 1
642 13:43:08.951226 CA_PREDIV_EN = 0
643 13:43:08.951280 PH8_DLY = 0
644 13:43:08.951334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 13:43:08.951388 DQ_AAMCK_DIV = 4
646 13:43:08.951442 CA_AAMCK_DIV = 4
647 13:43:08.951497 CA_ADMCK_DIV = 4
648 13:43:08.951551 DQ_TRACK_CA_EN = 0
649 13:43:08.951605 CA_PICK = 800
650 13:43:08.951659 CA_MCKIO = 800
651 13:43:08.951714 MCKIO_SEMI = 0
652 13:43:08.951768 PLL_FREQ = 3068
653 13:43:08.951821 DQ_UI_PI_RATIO = 32
654 13:43:08.951875 CA_UI_PI_RATIO = 0
655 13:43:08.951929 ===================================
656 13:43:08.951984 ===================================
657 13:43:08.952039 memory_type:LPDDR4
658 13:43:08.952093 GP_NUM : 10
659 13:43:08.952147 SRAM_EN : 1
660 13:43:08.952201 MD32_EN : 0
661 13:43:08.952255 ===================================
662 13:43:08.952310 [ANA_INIT] >>>>>>>>>>>>>>
663 13:43:08.952364 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 13:43:08.952420 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 13:43:08.952475 ===================================
666 13:43:08.952740 data_rate = 1600,PCW = 0X7600
667 13:43:08.952804 ===================================
668 13:43:08.952861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 13:43:08.952925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 13:43:08.953014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 13:43:08.953075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 13:43:08.953131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 13:43:08.953186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 13:43:08.953241 [ANA_INIT] flow start
675 13:43:08.953317 [ANA_INIT] PLL >>>>>>>>
676 13:43:08.953386 [ANA_INIT] PLL <<<<<<<<
677 13:43:08.953440 [ANA_INIT] MIDPI >>>>>>>>
678 13:43:08.953495 [ANA_INIT] MIDPI <<<<<<<<
679 13:43:08.953549 [ANA_INIT] DLL >>>>>>>>
680 13:43:08.953604 [ANA_INIT] flow end
681 13:43:08.953658 ============ LP4 DIFF to SE enter ============
682 13:43:08.953713 ============ LP4 DIFF to SE exit ============
683 13:43:08.953769 [ANA_INIT] <<<<<<<<<<<<<
684 13:43:08.953823 [Flow] Enable top DCM control >>>>>
685 13:43:08.953877 [Flow] Enable top DCM control <<<<<
686 13:43:08.953932 Enable DLL master slave shuffle
687 13:43:08.953987 ==============================================================
688 13:43:08.954042 Gating Mode config
689 13:43:08.954096 ==============================================================
690 13:43:08.954150 Config description:
691 13:43:08.954205 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 13:43:08.954261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 13:43:08.954316 SELPH_MODE 0: By rank 1: By Phase
694 13:43:08.954371 ==============================================================
695 13:43:08.954425 GAT_TRACK_EN = 1
696 13:43:08.954480 RX_GATING_MODE = 2
697 13:43:08.954534 RX_GATING_TRACK_MODE = 2
698 13:43:08.954589 SELPH_MODE = 1
699 13:43:08.954643 PICG_EARLY_EN = 1
700 13:43:08.954697 VALID_LAT_VALUE = 1
701 13:43:08.954751 ==============================================================
702 13:43:08.954806 Enter into Gating configuration >>>>
703 13:43:08.954861 Exit from Gating configuration <<<<
704 13:43:08.954915 Enter into DVFS_PRE_config >>>>>
705 13:43:08.954970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 13:43:08.955029 Exit from DVFS_PRE_config <<<<<
707 13:43:08.955084 Enter into PICG configuration >>>>
708 13:43:08.955138 Exit from PICG configuration <<<<
709 13:43:08.955193 [RX_INPUT] configuration >>>>>
710 13:43:08.955247 [RX_INPUT] configuration <<<<<
711 13:43:08.955302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 13:43:08.955356 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 13:43:08.955411 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 13:43:08.955466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 13:43:08.955520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 13:43:08.955575 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 13:43:08.955630 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 13:43:08.955684 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 13:43:08.955739 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 13:43:08.955793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 13:43:08.955847 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 13:43:08.955902 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 13:43:08.955956 ===================================
724 13:43:08.956011 LPDDR4 DRAM CONFIGURATION
725 13:43:08.956065 ===================================
726 13:43:08.956119 EX_ROW_EN[0] = 0x0
727 13:43:08.956173 EX_ROW_EN[1] = 0x0
728 13:43:08.956228 LP4Y_EN = 0x0
729 13:43:08.956282 WORK_FSP = 0x0
730 13:43:08.956336 WL = 0x2
731 13:43:08.956390 RL = 0x2
732 13:43:08.956444 BL = 0x2
733 13:43:08.956498 RPST = 0x0
734 13:43:08.956553 RD_PRE = 0x0
735 13:43:08.956606 WR_PRE = 0x1
736 13:43:08.956660 WR_PST = 0x0
737 13:43:08.956715 DBI_WR = 0x0
738 13:43:08.956769 DBI_RD = 0x0
739 13:43:08.956823 OTF = 0x1
740 13:43:08.956877 ===================================
741 13:43:08.956932 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 13:43:08.956986 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 13:43:08.957041 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 13:43:08.957095 ===================================
745 13:43:08.957150 LPDDR4 DRAM CONFIGURATION
746 13:43:08.957204 ===================================
747 13:43:08.957259 EX_ROW_EN[0] = 0x10
748 13:43:08.957342 EX_ROW_EN[1] = 0x0
749 13:43:08.957411 LP4Y_EN = 0x0
750 13:43:08.957465 WORK_FSP = 0x0
751 13:43:08.957519 WL = 0x2
752 13:43:08.957574 RL = 0x2
753 13:43:08.957628 BL = 0x2
754 13:43:08.957682 RPST = 0x0
755 13:43:08.957736 RD_PRE = 0x0
756 13:43:08.957790 WR_PRE = 0x1
757 13:43:08.957845 WR_PST = 0x0
758 13:43:08.957899 DBI_WR = 0x0
759 13:43:08.957953 DBI_RD = 0x0
760 13:43:08.958007 OTF = 0x1
761 13:43:08.958061 ===================================
762 13:43:08.958116 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 13:43:08.958175 nWR fixed to 40
764 13:43:08.958231 [ModeRegInit_LP4] CH0 RK0
765 13:43:08.958285 [ModeRegInit_LP4] CH0 RK1
766 13:43:08.958339 [ModeRegInit_LP4] CH1 RK0
767 13:43:08.958394 [ModeRegInit_LP4] CH1 RK1
768 13:43:08.958448 match AC timing 13
769 13:43:08.958501 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 13:43:08.958556 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 13:43:08.958610 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 13:43:08.958665 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 13:43:08.958911 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 13:43:08.958973 [EMI DOE] emi_dcm 0
775 13:43:08.959029 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 13:43:08.959084 ==
777 13:43:08.959141 Dram Type= 6, Freq= 0, CH_0, rank 0
778 13:43:08.959212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 13:43:08.959284 ==
780 13:43:08.959339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 13:43:08.959394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 13:43:08.959449 [CA 0] Center 38 (7~69) winsize 63
783 13:43:08.959504 [CA 1] Center 38 (7~69) winsize 63
784 13:43:08.959558 [CA 2] Center 35 (5~66) winsize 62
785 13:43:08.959613 [CA 3] Center 35 (5~66) winsize 62
786 13:43:08.959667 [CA 4] Center 34 (4~65) winsize 62
787 13:43:08.959721 [CA 5] Center 34 (3~65) winsize 63
788 13:43:08.959775
789 13:43:08.959830 [CmdBusTrainingLP45] Vref(ca) range 1: 34
790 13:43:08.959885
791 13:43:08.959939 [CATrainingPosCal] consider 1 rank data
792 13:43:08.959994 u2DelayCellTimex100 = 270/100 ps
793 13:43:08.960049 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
794 13:43:08.960105 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
795 13:43:08.960159 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
796 13:43:08.960213 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
797 13:43:08.960267 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
798 13:43:08.960321 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
799 13:43:08.960375
800 13:43:08.960430 CA PerBit enable=1, Macro0, CA PI delay=34
801 13:43:08.960484
802 13:43:08.960539 [CBTSetCACLKResult] CA Dly = 34
803 13:43:08.960593 CS Dly: 5 (0~36)
804 13:43:08.960647 ==
805 13:43:08.960702 Dram Type= 6, Freq= 0, CH_0, rank 1
806 13:43:08.960757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 13:43:08.960812 ==
808 13:43:08.960867 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 13:43:08.960922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 13:43:08.960977 [CA 0] Center 38 (7~69) winsize 63
811 13:43:08.961031 [CA 1] Center 38 (8~69) winsize 62
812 13:43:08.961085 [CA 2] Center 36 (6~67) winsize 62
813 13:43:08.961140 [CA 3] Center 36 (5~67) winsize 63
814 13:43:08.961194 [CA 4] Center 35 (4~66) winsize 63
815 13:43:08.961248 [CA 5] Center 34 (4~65) winsize 62
816 13:43:08.961309
817 13:43:08.961402 [CmdBusTrainingLP45] Vref(ca) range 1: 34
818 13:43:08.961457
819 13:43:08.961512 [CATrainingPosCal] consider 2 rank data
820 13:43:08.961567 u2DelayCellTimex100 = 270/100 ps
821 13:43:08.961622 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 13:43:08.961725 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 13:43:08.961793 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 13:43:08.961848 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 13:43:08.961903 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
826 13:43:08.961957 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
827 13:43:08.962011
828 13:43:08.962065 CA PerBit enable=1, Macro0, CA PI delay=34
829 13:43:08.962120
830 13:43:08.962174 [CBTSetCACLKResult] CA Dly = 34
831 13:43:08.962229 CS Dly: 6 (0~38)
832 13:43:08.962283
833 13:43:08.962338 ----->DramcWriteLeveling(PI) begin...
834 13:43:08.962394 ==
835 13:43:08.962448 Dram Type= 6, Freq= 0, CH_0, rank 0
836 13:43:08.962504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 13:43:08.962559 ==
838 13:43:08.962614 Write leveling (Byte 0): 33 => 33
839 13:43:08.962669 Write leveling (Byte 1): 27 => 27
840 13:43:08.962723 DramcWriteLeveling(PI) end<-----
841 13:43:08.962777
842 13:43:08.962831 ==
843 13:43:08.962886 Dram Type= 6, Freq= 0, CH_0, rank 0
844 13:43:08.962941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 13:43:08.962995 ==
846 13:43:08.963050 [Gating] SW mode calibration
847 13:43:08.963105 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 13:43:08.963161 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 13:43:08.963216 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
850 13:43:08.963271 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 13:43:08.963326 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 13:43:08.963381 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 13:43:08.963435 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 13:43:08.963490 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 13:43:08.963545 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 13:43:08.963599 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 13:43:08.963653 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 13:43:08.963707 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 13:43:08.963762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 13:43:08.963816 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 13:43:08.963871 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 13:43:08.963925 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 13:43:08.963979 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 13:43:08.964034 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 13:43:08.964088 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
866 13:43:08.964143 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
867 13:43:08.964197 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
868 13:43:08.964251 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 13:43:08.964306 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 13:43:08.964360 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 13:43:08.964415 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 13:43:08.964469 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 13:43:08.964524 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 13:43:08.964578 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
875 13:43:08.964632 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
876 13:43:08.964687 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
877 13:43:08.964741 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 13:43:08.964795 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 13:43:08.964850 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 13:43:08.964904 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 13:43:08.965154 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 13:43:08.965266 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
883 13:43:08.965417 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
884 13:43:08.965524 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
885 13:43:08.965631 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 13:43:08.965726 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 13:43:08.965812 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 13:43:08.965898 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 13:43:08.965984 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 13:43:08.966069 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
891 13:43:08.966155 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
892 13:43:08.966240 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
893 13:43:08.966325 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 13:43:08.966411 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 13:43:08.966495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 13:43:08.966580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 13:43:08.966665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 13:43:08.966750 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
899 13:43:08.966835 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 13:43:08.966920 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 13:43:08.967005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 13:43:08.967090 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 13:43:08.967177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 13:43:08.967238 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 13:43:08.967293 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 13:43:08.967348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 13:43:08.967403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 13:43:08.967458 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 13:43:08.967512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 13:43:08.967566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 13:43:08.967621 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 13:43:08.967679 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 13:43:08.967734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 13:43:08.967789 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 13:43:08.967843 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
916 13:43:08.967897 Total UI for P1: 0, mck2ui 16
917 13:43:08.967952 best dqsien dly found for B0: ( 0, 14, 4)
918 13:43:08.968007 Total UI for P1: 0, mck2ui 16
919 13:43:08.968062 best dqsien dly found for B1: ( 0, 14, 6)
920 13:43:08.968117 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
921 13:43:08.968172 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
922 13:43:08.968226
923 13:43:08.968282 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
924 13:43:08.968336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
925 13:43:08.968391 [Gating] SW calibration Done
926 13:43:08.968445 ==
927 13:43:08.968501 Dram Type= 6, Freq= 0, CH_0, rank 0
928 13:43:08.968555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 13:43:08.968610 ==
930 13:43:08.968664 RX Vref Scan: 0
931 13:43:08.968719
932 13:43:08.968773 RX Vref 0 -> 0, step: 1
933 13:43:08.968827
934 13:43:08.968881 RX Delay -130 -> 252, step: 16
935 13:43:08.968936 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
936 13:43:08.968990 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
937 13:43:08.969045 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
938 13:43:08.969100 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
939 13:43:08.969154 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
940 13:43:08.969208 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
941 13:43:08.969262 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
942 13:43:08.969320 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
943 13:43:08.969374 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
944 13:43:08.969428 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
945 13:43:08.969482 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
946 13:43:08.969536 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
947 13:43:08.969590 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
948 13:43:08.969644 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
949 13:43:08.969698 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
950 13:43:08.969753 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
951 13:43:08.969807 ==
952 13:43:08.969862 Dram Type= 6, Freq= 0, CH_0, rank 0
953 13:43:08.969918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 13:43:08.969973 ==
955 13:43:08.970027 DQS Delay:
956 13:43:08.970081 DQS0 = 0, DQS1 = 0
957 13:43:08.970135 DQM Delay:
958 13:43:08.970189 DQM0 = 91, DQM1 = 80
959 13:43:08.970248 DQ Delay:
960 13:43:08.970304 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
961 13:43:08.970359 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
962 13:43:08.970414 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
963 13:43:08.970469 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
964 13:43:08.970523
965 13:43:08.970577
966 13:43:08.970631 ==
967 13:43:08.970685 Dram Type= 6, Freq= 0, CH_0, rank 0
968 13:43:08.970740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 13:43:08.970795 ==
970 13:43:08.970849
971 13:43:08.970904
972 13:43:08.970958 TX Vref Scan disable
973 13:43:08.971012 == TX Byte 0 ==
974 13:43:08.971066 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
975 13:43:08.971121 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
976 13:43:08.971175 == TX Byte 1 ==
977 13:43:08.971229 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
978 13:43:08.971283 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
979 13:43:08.971338 ==
980 13:43:08.971392 Dram Type= 6, Freq= 0, CH_0, rank 0
981 13:43:08.971448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
982 13:43:08.971502 ==
983 13:43:08.971557 TX Vref=22, minBit 8, minWin=27, winSum=444
984 13:43:08.971611 TX Vref=24, minBit 11, minWin=27, winSum=449
985 13:43:08.971667 TX Vref=26, minBit 8, minWin=27, winSum=449
986 13:43:08.971721 TX Vref=28, minBit 9, minWin=27, winSum=454
987 13:43:08.971776 TX Vref=30, minBit 6, minWin=28, winSum=459
988 13:43:08.971831 TX Vref=32, minBit 1, minWin=28, winSum=456
989 13:43:08.972082 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 30
990 13:43:08.972154
991 13:43:08.972211 Final TX Range 1 Vref 30
992 13:43:08.972267
993 13:43:08.972321 ==
994 13:43:08.972376 Dram Type= 6, Freq= 0, CH_0, rank 0
995 13:43:08.972434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
996 13:43:08.972490 ==
997 13:43:08.972554
998 13:43:08.972679
999 13:43:08.972763 TX Vref Scan disable
1000 13:43:08.972848 == TX Byte 0 ==
1001 13:43:08.972933 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1002 13:43:08.973018 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1003 13:43:08.973102 == TX Byte 1 ==
1004 13:43:08.973186 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1005 13:43:08.973271 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1006 13:43:08.973362
1007 13:43:08.973447 [DATLAT]
1008 13:43:08.973530 Freq=800, CH0 RK0
1009 13:43:08.973614
1010 13:43:08.973698 DATLAT Default: 0xa
1011 13:43:08.973783 0, 0xFFFF, sum = 0
1012 13:43:08.973870 1, 0xFFFF, sum = 0
1013 13:43:08.973959 2, 0xFFFF, sum = 0
1014 13:43:08.974045 3, 0xFFFF, sum = 0
1015 13:43:08.974133 4, 0xFFFF, sum = 0
1016 13:43:08.974218 5, 0xFFFF, sum = 0
1017 13:43:08.974303 6, 0xFFFF, sum = 0
1018 13:43:08.974388 7, 0xFFFF, sum = 0
1019 13:43:08.974474 8, 0xFFFF, sum = 0
1020 13:43:08.974559 9, 0x0, sum = 1
1021 13:43:08.974644 10, 0x0, sum = 2
1022 13:43:08.974729 11, 0x0, sum = 3
1023 13:43:08.974815 12, 0x0, sum = 4
1024 13:43:08.974901 best_step = 10
1025 13:43:08.974990
1026 13:43:08.975075 ==
1027 13:43:08.975159 Dram Type= 6, Freq= 0, CH_0, rank 0
1028 13:43:08.975244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1029 13:43:08.975327 ==
1030 13:43:08.975410 RX Vref Scan: 1
1031 13:43:08.975493
1032 13:43:08.975575 Set Vref Range= 32 -> 127
1033 13:43:08.975657
1034 13:43:08.975739 RX Vref 32 -> 127, step: 1
1035 13:43:08.975822
1036 13:43:08.975904 RX Delay -95 -> 252, step: 8
1037 13:43:08.975986
1038 13:43:08.976069 Set Vref, RX VrefLevel [Byte0]: 32
1039 13:43:08.976152 [Byte1]: 32
1040 13:43:08.976234
1041 13:43:08.976316 Set Vref, RX VrefLevel [Byte0]: 33
1042 13:43:08.976399 [Byte1]: 33
1043 13:43:08.976481
1044 13:43:08.976564 Set Vref, RX VrefLevel [Byte0]: 34
1045 13:43:08.976647 [Byte1]: 34
1046 13:43:08.976729
1047 13:43:08.976811 Set Vref, RX VrefLevel [Byte0]: 35
1048 13:43:08.976894 [Byte1]: 35
1049 13:43:08.976976
1050 13:43:08.977058 Set Vref, RX VrefLevel [Byte0]: 36
1051 13:43:08.977141 [Byte1]: 36
1052 13:43:08.977223
1053 13:43:08.977312 Set Vref, RX VrefLevel [Byte0]: 37
1054 13:43:08.977402 [Byte1]: 37
1055 13:43:08.977455
1056 13:43:08.977508 Set Vref, RX VrefLevel [Byte0]: 38
1057 13:43:08.977561 [Byte1]: 38
1058 13:43:08.977614
1059 13:43:08.977667 Set Vref, RX VrefLevel [Byte0]: 39
1060 13:43:08.977720 [Byte1]: 39
1061 13:43:08.977774
1062 13:43:08.977827 Set Vref, RX VrefLevel [Byte0]: 40
1063 13:43:08.977881 [Byte1]: 40
1064 13:43:08.977934
1065 13:43:08.977988 Set Vref, RX VrefLevel [Byte0]: 41
1066 13:43:08.978042 [Byte1]: 41
1067 13:43:08.978095
1068 13:43:08.978148 Set Vref, RX VrefLevel [Byte0]: 42
1069 13:43:08.978201 [Byte1]: 42
1070 13:43:08.978254
1071 13:43:08.978307 Set Vref, RX VrefLevel [Byte0]: 43
1072 13:43:08.978361 [Byte1]: 43
1073 13:43:08.978414
1074 13:43:08.978467 Set Vref, RX VrefLevel [Byte0]: 44
1075 13:43:08.978521 [Byte1]: 44
1076 13:43:08.978574
1077 13:43:08.978627 Set Vref, RX VrefLevel [Byte0]: 45
1078 13:43:08.978681 [Byte1]: 45
1079 13:43:08.978734
1080 13:43:08.978787 Set Vref, RX VrefLevel [Byte0]: 46
1081 13:43:08.978840 [Byte1]: 46
1082 13:43:08.978894
1083 13:43:08.978947 Set Vref, RX VrefLevel [Byte0]: 47
1084 13:43:08.979000 [Byte1]: 47
1085 13:43:08.979053
1086 13:43:08.979106 Set Vref, RX VrefLevel [Byte0]: 48
1087 13:43:08.979160 [Byte1]: 48
1088 13:43:08.979213
1089 13:43:08.979265 Set Vref, RX VrefLevel [Byte0]: 49
1090 13:43:08.979319 [Byte1]: 49
1091 13:43:08.979372
1092 13:43:08.979425 Set Vref, RX VrefLevel [Byte0]: 50
1093 13:43:08.979478 [Byte1]: 50
1094 13:43:08.979532
1095 13:43:08.979585 Set Vref, RX VrefLevel [Byte0]: 51
1096 13:43:08.979638 [Byte1]: 51
1097 13:43:08.979692
1098 13:43:08.979744 Set Vref, RX VrefLevel [Byte0]: 52
1099 13:43:08.979797 [Byte1]: 52
1100 13:43:08.979851
1101 13:43:08.979904 Set Vref, RX VrefLevel [Byte0]: 53
1102 13:43:08.979958 [Byte1]: 53
1103 13:43:08.980012
1104 13:43:08.980064 Set Vref, RX VrefLevel [Byte0]: 54
1105 13:43:08.980117 [Byte1]: 54
1106 13:43:08.980170
1107 13:43:08.980223 Set Vref, RX VrefLevel [Byte0]: 55
1108 13:43:08.980277 [Byte1]: 55
1109 13:43:08.980342
1110 13:43:08.980396 Set Vref, RX VrefLevel [Byte0]: 56
1111 13:43:08.980450 [Byte1]: 56
1112 13:43:08.980504
1113 13:43:08.980557 Set Vref, RX VrefLevel [Byte0]: 57
1114 13:43:08.980611 [Byte1]: 57
1115 13:43:08.980665
1116 13:43:08.980718 Set Vref, RX VrefLevel [Byte0]: 58
1117 13:43:08.980771 [Byte1]: 58
1118 13:43:08.980825
1119 13:43:08.980878 Set Vref, RX VrefLevel [Byte0]: 59
1120 13:43:08.980931 [Byte1]: 59
1121 13:43:08.980985
1122 13:43:08.981037 Set Vref, RX VrefLevel [Byte0]: 60
1123 13:43:08.981091 [Byte1]: 60
1124 13:43:08.981144
1125 13:43:08.981197 Set Vref, RX VrefLevel [Byte0]: 61
1126 13:43:08.981250 [Byte1]: 61
1127 13:43:08.981306
1128 13:43:08.981397 Set Vref, RX VrefLevel [Byte0]: 62
1129 13:43:08.981451 [Byte1]: 62
1130 13:43:08.981504
1131 13:43:08.981557 Set Vref, RX VrefLevel [Byte0]: 63
1132 13:43:08.981611 [Byte1]: 63
1133 13:43:08.981664
1134 13:43:08.981718 Set Vref, RX VrefLevel [Byte0]: 64
1135 13:43:08.981771 [Byte1]: 64
1136 13:43:08.981825
1137 13:43:08.981878 Set Vref, RX VrefLevel [Byte0]: 65
1138 13:43:08.981932 [Byte1]: 65
1139 13:43:08.981986
1140 13:43:08.982039 Set Vref, RX VrefLevel [Byte0]: 66
1141 13:43:08.982093 [Byte1]: 66
1142 13:43:08.982146
1143 13:43:08.982199 Set Vref, RX VrefLevel [Byte0]: 67
1144 13:43:08.982253 [Byte1]: 67
1145 13:43:08.982330
1146 13:43:08.982408 Set Vref, RX VrefLevel [Byte0]: 68
1147 13:43:08.982465 [Byte1]: 68
1148 13:43:08.982519
1149 13:43:08.982573 Set Vref, RX VrefLevel [Byte0]: 69
1150 13:43:08.982627 [Byte1]: 69
1151 13:43:08.982681
1152 13:43:08.982734 Set Vref, RX VrefLevel [Byte0]: 70
1153 13:43:08.982788 [Byte1]: 70
1154 13:43:08.982842
1155 13:43:08.982895 Set Vref, RX VrefLevel [Byte0]: 71
1156 13:43:08.982949 [Byte1]: 71
1157 13:43:08.983002
1158 13:43:08.983055 Set Vref, RX VrefLevel [Byte0]: 72
1159 13:43:08.983108 [Byte1]: 72
1160 13:43:08.983161
1161 13:43:08.983214 Set Vref, RX VrefLevel [Byte0]: 73
1162 13:43:08.983461 [Byte1]: 73
1163 13:43:08.983521
1164 13:43:08.983575 Set Vref, RX VrefLevel [Byte0]: 74
1165 13:43:08.983629 [Byte1]: 74
1166 13:43:08.983683
1167 13:43:08.983736 Set Vref, RX VrefLevel [Byte0]: 75
1168 13:43:08.983789 [Byte1]: 75
1169 13:43:08.983843
1170 13:43:08.983896 Set Vref, RX VrefLevel [Byte0]: 76
1171 13:43:08.983951 [Byte1]: 76
1172 13:43:08.984004
1173 13:43:08.984056 Set Vref, RX VrefLevel [Byte0]: 77
1174 13:43:08.984110 [Byte1]: 77
1175 13:43:08.984163
1176 13:43:08.984216 Set Vref, RX VrefLevel [Byte0]: 78
1177 13:43:08.984269 [Byte1]: 78
1178 13:43:08.984322
1179 13:43:08.984375 Final RX Vref Byte 0 = 62 to rank0
1180 13:43:08.984429 Final RX Vref Byte 1 = 60 to rank0
1181 13:43:08.984483 Final RX Vref Byte 0 = 62 to rank1
1182 13:43:08.984536 Final RX Vref Byte 1 = 60 to rank1==
1183 13:43:08.984590 Dram Type= 6, Freq= 0, CH_0, rank 0
1184 13:43:08.984644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 13:43:08.984698 ==
1186 13:43:08.984751 DQS Delay:
1187 13:43:08.984804 DQS0 = 0, DQS1 = 0
1188 13:43:08.984857 DQM Delay:
1189 13:43:08.984910 DQM0 = 92, DQM1 = 82
1190 13:43:08.984963 DQ Delay:
1191 13:43:08.985016 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1192 13:43:08.985069 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1193 13:43:08.985123 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1194 13:43:08.985176 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1195 13:43:08.985229
1196 13:43:08.985282
1197 13:43:08.985375 [DQSOSCAuto] RK0, (LSB)MR18= 0x423e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1198 13:43:08.985430 CH0 RK0: MR19=606, MR18=423E
1199 13:43:08.985483 CH0_RK0: MR19=0x606, MR18=0x423E, DQSOSC=393, MR23=63, INC=95, DEC=63
1200 13:43:08.985537
1201 13:43:08.985590 ----->DramcWriteLeveling(PI) begin...
1202 13:43:08.985645 ==
1203 13:43:08.985698 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 13:43:08.985752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 13:43:08.985807 ==
1206 13:43:08.985860 Write leveling (Byte 0): 34 => 34
1207 13:43:08.985913 Write leveling (Byte 1): 27 => 27
1208 13:43:08.985966 DramcWriteLeveling(PI) end<-----
1209 13:43:08.986019
1210 13:43:08.986072 ==
1211 13:43:08.986125 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 13:43:08.986178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 13:43:08.986232 ==
1214 13:43:08.986285 [Gating] SW mode calibration
1215 13:43:08.986338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1216 13:43:08.986391 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1217 13:43:08.986445 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 13:43:08.986499 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 13:43:08.986552 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1220 13:43:08.986605 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 13:43:08.986658 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 13:43:08.986711 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 13:43:08.986765 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 13:43:08.986818 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 13:43:08.986871 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 13:43:08.986924 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 13:43:08.986977 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 13:43:08.987030 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 13:43:08.987083 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 13:43:08.987136 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 13:43:08.987190 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 13:43:08.987243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 13:43:08.987296 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1234 13:43:08.987350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1235 13:43:08.987403 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 13:43:08.987456 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 13:43:08.987509 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 13:43:08.987562 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 13:43:08.987615 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 13:43:08.987668 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 13:43:08.987721 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 13:43:08.987774 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
1243 13:43:08.987827 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1244 13:43:08.987880 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 13:43:08.987933 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 13:43:08.987986 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 13:43:08.988039 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 13:43:08.988092 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 13:43:08.988145 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 13:43:08.988198 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
1251 13:43:08.988252 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1252 13:43:08.988305 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 13:43:08.988358 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 13:43:08.988411 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 13:43:08.988465 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 13:43:08.988518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 13:43:08.988571 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 13:43:08.988624 0 11 4 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
1259 13:43:08.988677 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1260 13:43:08.988730 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 13:43:08.988783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 13:43:08.988836 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 13:43:08.988889 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 13:43:08.988942 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 13:43:08.988996 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 13:43:08.989241 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1267 13:43:08.989326 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 13:43:08.989397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 13:43:08.989451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 13:43:08.989504 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 13:43:08.989558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 13:43:08.989612 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 13:43:08.989666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 13:43:08.989720 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 13:43:08.989774 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 13:43:08.989827 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 13:43:08.989880 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 13:43:08.989933 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 13:43:08.989987 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 13:43:08.990040 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 13:43:08.990093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 13:43:08.990147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1283 13:43:08.990201 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1284 13:43:08.990254 Total UI for P1: 0, mck2ui 16
1285 13:43:08.990308 best dqsien dly found for B0: ( 0, 14, 4)
1286 13:43:08.990362 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 13:43:08.990415 Total UI for P1: 0, mck2ui 16
1288 13:43:08.990468 best dqsien dly found for B1: ( 0, 14, 6)
1289 13:43:08.990522 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1290 13:43:08.990575 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1291 13:43:08.990628
1292 13:43:08.990680 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1293 13:43:08.990734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1294 13:43:08.990788 [Gating] SW calibration Done
1295 13:43:08.990841 ==
1296 13:43:08.990894 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 13:43:08.990947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 13:43:08.991002 ==
1299 13:43:08.991054 RX Vref Scan: 0
1300 13:43:08.991107
1301 13:43:08.991160 RX Vref 0 -> 0, step: 1
1302 13:43:08.991213
1303 13:43:08.991266 RX Delay -130 -> 252, step: 16
1304 13:43:08.991319 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1305 13:43:08.991372 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1306 13:43:08.991426 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1307 13:43:08.991479 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1308 13:43:08.991533 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1309 13:43:08.991586 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1310 13:43:08.991639 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1311 13:43:08.991693 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1312 13:43:08.991747 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1313 13:43:08.991800 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1314 13:43:08.991854 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1315 13:43:08.991907 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1316 13:43:08.991961 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1317 13:43:08.992015 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1318 13:43:08.992068 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1319 13:43:08.992122 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1320 13:43:08.992175 ==
1321 13:43:08.992229 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 13:43:08.992282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 13:43:08.992336 ==
1324 13:43:08.992389 DQS Delay:
1325 13:43:08.992442 DQS0 = 0, DQS1 = 0
1326 13:43:08.992496 DQM Delay:
1327 13:43:08.992549 DQM0 = 89, DQM1 = 79
1328 13:43:08.992602 DQ Delay:
1329 13:43:08.992655 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1330 13:43:08.992708 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1331 13:43:08.992761 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1332 13:43:08.992815 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1333 13:43:08.992868
1334 13:43:08.992921
1335 13:43:08.992973 ==
1336 13:43:08.993026 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 13:43:08.993079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 13:43:08.993132 ==
1339 13:43:08.993185
1340 13:43:08.993237
1341 13:43:08.993290 TX Vref Scan disable
1342 13:43:08.993381 == TX Byte 0 ==
1343 13:43:08.993434 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1344 13:43:08.993488 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1345 13:43:08.993542 == TX Byte 1 ==
1346 13:43:08.993595 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1347 13:43:08.993649 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1348 13:43:08.993702 ==
1349 13:43:08.993756 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 13:43:08.993810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 13:43:08.993864 ==
1352 13:43:08.993916 TX Vref=22, minBit 0, minWin=27, winSum=447
1353 13:43:08.993971 TX Vref=24, minBit 8, minWin=27, winSum=451
1354 13:43:08.994025 TX Vref=26, minBit 8, minWin=27, winSum=453
1355 13:43:08.994080 TX Vref=28, minBit 8, minWin=27, winSum=455
1356 13:43:08.994133 TX Vref=30, minBit 8, minWin=28, winSum=459
1357 13:43:08.994187 TX Vref=32, minBit 6, minWin=28, winSum=459
1358 13:43:08.994241 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1359 13:43:08.994294
1360 13:43:08.994347 Final TX Range 1 Vref 30
1361 13:43:08.994399
1362 13:43:08.994451 ==
1363 13:43:08.994503 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 13:43:08.994555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 13:43:08.994607 ==
1366 13:43:08.994658
1367 13:43:08.994709
1368 13:43:08.994760 TX Vref Scan disable
1369 13:43:08.994811 == TX Byte 0 ==
1370 13:43:08.994862 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1371 13:43:08.994914 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1372 13:43:08.994966 == TX Byte 1 ==
1373 13:43:08.995017 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1374 13:43:08.995068 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1375 13:43:08.995120
1376 13:43:08.995170 [DATLAT]
1377 13:43:08.995221 Freq=800, CH0 RK1
1378 13:43:08.995273
1379 13:43:08.995324 DATLAT Default: 0xa
1380 13:43:08.995375 0, 0xFFFF, sum = 0
1381 13:43:08.995428 1, 0xFFFF, sum = 0
1382 13:43:08.995480 2, 0xFFFF, sum = 0
1383 13:43:08.995537 3, 0xFFFF, sum = 0
1384 13:43:08.995590 4, 0xFFFF, sum = 0
1385 13:43:08.995642 5, 0xFFFF, sum = 0
1386 13:43:08.995694 6, 0xFFFF, sum = 0
1387 13:43:08.995747 7, 0xFFFF, sum = 0
1388 13:43:08.995800 8, 0xFFFF, sum = 0
1389 13:43:08.995852 9, 0x0, sum = 1
1390 13:43:08.995905 10, 0x0, sum = 2
1391 13:43:08.995958 11, 0x0, sum = 3
1392 13:43:08.996010 12, 0x0, sum = 4
1393 13:43:08.996063 best_step = 10
1394 13:43:08.996114
1395 13:43:08.996165 ==
1396 13:43:08.996217 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 13:43:08.996464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 13:43:08.996525 ==
1399 13:43:08.996578 RX Vref Scan: 0
1400 13:43:08.996631
1401 13:43:08.996682 RX Vref 0 -> 0, step: 1
1402 13:43:08.996735
1403 13:43:08.996786 RX Delay -79 -> 252, step: 8
1404 13:43:08.996839 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1405 13:43:08.996891 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1406 13:43:08.996944 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1407 13:43:08.996997 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1408 13:43:08.997048 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1409 13:43:08.997100 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1410 13:43:08.997151 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1411 13:43:08.997203 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1412 13:43:08.997255 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1413 13:43:08.997333 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1414 13:43:08.997401 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1415 13:43:08.997453 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1416 13:43:08.997505 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1417 13:43:08.997566 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1418 13:43:08.997620 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1419 13:43:08.997672 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1420 13:43:08.997724 ==
1421 13:43:08.997776 Dram Type= 6, Freq= 0, CH_0, rank 1
1422 13:43:08.997828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 13:43:08.997880 ==
1424 13:43:08.997932 DQS Delay:
1425 13:43:08.997984 DQS0 = 0, DQS1 = 0
1426 13:43:08.998035 DQM Delay:
1427 13:43:08.998087 DQM0 = 90, DQM1 = 81
1428 13:43:08.998138 DQ Delay:
1429 13:43:08.998190 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1430 13:43:08.998241 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1431 13:43:08.998294 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1432 13:43:08.998346 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1433 13:43:08.998398
1434 13:43:08.998450
1435 13:43:08.998500 [DQSOSCAuto] RK1, (LSB)MR18= 0x421b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1436 13:43:08.998553 CH0 RK1: MR19=606, MR18=421B
1437 13:43:08.998605 CH0_RK1: MR19=0x606, MR18=0x421B, DQSOSC=393, MR23=63, INC=95, DEC=63
1438 13:43:08.998658 [RxdqsGatingPostProcess] freq 800
1439 13:43:08.998709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1440 13:43:08.998761 Pre-setting of DQS Precalculation
1441 13:43:08.998813 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1442 13:43:08.998865 ==
1443 13:43:08.998916 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 13:43:08.998969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 13:43:08.999021 ==
1446 13:43:08.999073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 13:43:08.999125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 13:43:08.999177 [CA 0] Center 36 (6~67) winsize 62
1449 13:43:08.999229 [CA 1] Center 36 (6~67) winsize 62
1450 13:43:08.999281 [CA 2] Center 34 (4~65) winsize 62
1451 13:43:08.999333 [CA 3] Center 34 (3~65) winsize 63
1452 13:43:08.999385 [CA 4] Center 34 (4~65) winsize 62
1453 13:43:08.999437 [CA 5] Center 33 (3~64) winsize 62
1454 13:43:08.999488
1455 13:43:08.999539 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1456 13:43:08.999591
1457 13:43:08.999642 [CATrainingPosCal] consider 1 rank data
1458 13:43:08.999693 u2DelayCellTimex100 = 270/100 ps
1459 13:43:08.999745 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 13:43:08.999797 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1461 13:43:08.999848 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 13:43:08.999900 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1463 13:43:08.999952 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 13:43:09.000003 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1465 13:43:09.000054
1466 13:43:09.000105 CA PerBit enable=1, Macro0, CA PI delay=33
1467 13:43:09.000157
1468 13:43:09.000208 [CBTSetCACLKResult] CA Dly = 33
1469 13:43:09.000260 CS Dly: 5 (0~36)
1470 13:43:09.000312 ==
1471 13:43:09.000363 Dram Type= 6, Freq= 0, CH_1, rank 1
1472 13:43:09.000415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 13:43:09.000466 ==
1474 13:43:09.000518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1475 13:43:09.000570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1476 13:43:09.000622 [CA 0] Center 37 (6~68) winsize 63
1477 13:43:09.000673 [CA 1] Center 37 (6~68) winsize 63
1478 13:43:09.000725 [CA 2] Center 35 (4~66) winsize 63
1479 13:43:09.000776 [CA 3] Center 34 (4~65) winsize 62
1480 13:43:09.000828 [CA 4] Center 34 (4~65) winsize 62
1481 13:43:09.000880 [CA 5] Center 34 (4~64) winsize 61
1482 13:43:09.000931
1483 13:43:09.000983 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1484 13:43:09.001035
1485 13:43:09.001087 [CATrainingPosCal] consider 2 rank data
1486 13:43:09.001138 u2DelayCellTimex100 = 270/100 ps
1487 13:43:09.001190 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 13:43:09.001242 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1489 13:43:09.001294 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 13:43:09.001395 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 13:43:09.001447 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 13:43:09.001499 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 13:43:09.001551
1494 13:43:09.001602 CA PerBit enable=1, Macro0, CA PI delay=34
1495 13:43:09.001654
1496 13:43:09.001705 [CBTSetCACLKResult] CA Dly = 34
1497 13:43:09.001757 CS Dly: 6 (0~38)
1498 13:43:09.001808
1499 13:43:09.001860 ----->DramcWriteLeveling(PI) begin...
1500 13:43:09.001912 ==
1501 13:43:09.001964 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 13:43:09.002017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 13:43:09.002069 ==
1504 13:43:09.002121 Write leveling (Byte 0): 25 => 25
1505 13:43:09.002173 Write leveling (Byte 1): 31 => 31
1506 13:43:09.002224 DramcWriteLeveling(PI) end<-----
1507 13:43:09.002275
1508 13:43:09.002327 ==
1509 13:43:09.002378 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 13:43:09.002430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 13:43:09.002482 ==
1512 13:43:09.002533 [Gating] SW mode calibration
1513 13:43:09.002585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1514 13:43:09.002638 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1515 13:43:09.002690 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 13:43:09.002742 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1517 13:43:09.002794 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 13:43:09.003039 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 13:43:09.003097 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 13:43:09.003150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 13:43:09.003203 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 13:43:09.003255 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 13:43:09.003307 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 13:43:09.003359 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 13:43:09.003411 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 13:43:09.003463 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 13:43:09.003515 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 13:43:09.003584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 13:43:09.003650 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 13:43:09.003702 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1531 13:43:09.003753 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1532 13:43:09.003805 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1533 13:43:09.003857 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 13:43:09.003909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 13:43:09.003960 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 13:43:09.004012 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 13:43:09.004063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 13:43:09.004115 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 13:43:09.004167 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 13:43:09.004218 0 9 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1541 13:43:09.004270 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1542 13:43:09.004322 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 13:43:09.004374 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 13:43:09.004425 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 13:43:09.004477 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 13:43:09.004528 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 13:43:09.004580 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1548 13:43:09.004631 0 10 4 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (0 0)
1549 13:43:09.004683 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 13:43:09.004734 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 13:43:09.004785 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 13:43:09.004836 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 13:43:09.004888 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 13:43:09.004940 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 13:43:09.004992 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 13:43:09.005043 0 11 4 | B1->B0 | 3434 3b3b | 0 0 | (0 0) (0 0)
1557 13:43:09.005095 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1558 13:43:09.005146 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 13:43:09.005198 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 13:43:09.005249 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 13:43:09.005311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 13:43:09.005402 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 13:43:09.005454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 13:43:09.005506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 13:43:09.005558 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1566 13:43:09.005609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 13:43:09.005659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 13:43:09.005711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 13:43:09.005763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 13:43:09.005815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 13:43:09.005867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 13:43:09.005919 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 13:43:09.005970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 13:43:09.006022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 13:43:09.006074 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 13:43:09.006126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 13:43:09.006177 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 13:43:09.006229 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 13:43:09.006280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1580 13:43:09.006332 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 13:43:09.006384 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1582 13:43:09.006436 Total UI for P1: 0, mck2ui 16
1583 13:43:09.006488 best dqsien dly found for B0: ( 0, 14, 2)
1584 13:43:09.006540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 13:43:09.006592 Total UI for P1: 0, mck2ui 16
1586 13:43:09.006644 best dqsien dly found for B1: ( 0, 14, 6)
1587 13:43:09.006696 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1588 13:43:09.006749 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1589 13:43:09.006801
1590 13:43:09.006853 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1591 13:43:09.006906 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 13:43:09.006958 [Gating] SW calibration Done
1593 13:43:09.007010 ==
1594 13:43:09.007062 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 13:43:09.007114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 13:43:09.007166 ==
1597 13:43:09.007218 RX Vref Scan: 0
1598 13:43:09.007269
1599 13:43:09.007320 RX Vref 0 -> 0, step: 1
1600 13:43:09.007371
1601 13:43:09.007423 RX Delay -130 -> 252, step: 16
1602 13:43:09.007475 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1603 13:43:09.007527 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1604 13:43:09.007580 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1605 13:43:09.007631 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1606 13:43:09.007683 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1607 13:43:09.007735 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1608 13:43:09.007978 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1609 13:43:09.008036 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1610 13:43:09.008089 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1611 13:43:09.008141 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1612 13:43:09.008210 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1613 13:43:09.008278 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1614 13:43:09.008329 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1615 13:43:09.008381 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1616 13:43:09.008433 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1617 13:43:09.008485 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1618 13:43:09.008536 ==
1619 13:43:09.008601 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 13:43:09.008654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 13:43:09.008707 ==
1622 13:43:09.008758 DQS Delay:
1623 13:43:09.008809 DQS0 = 0, DQS1 = 0
1624 13:43:09.008861 DQM Delay:
1625 13:43:09.008913 DQM0 = 90, DQM1 = 85
1626 13:43:09.008965 DQ Delay:
1627 13:43:09.009017 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1628 13:43:09.009069 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1629 13:43:09.009122 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =77
1630 13:43:09.009175 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1631 13:43:09.009231
1632 13:43:09.009284
1633 13:43:09.009382 ==
1634 13:43:09.009435 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 13:43:09.009487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 13:43:09.009539 ==
1637 13:43:09.009591
1638 13:43:09.009642
1639 13:43:09.009693 TX Vref Scan disable
1640 13:43:09.009744 == TX Byte 0 ==
1641 13:43:09.009796 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1642 13:43:09.009848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1643 13:43:09.009900 == TX Byte 1 ==
1644 13:43:09.009951 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1645 13:43:09.010003 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1646 13:43:09.010055 ==
1647 13:43:09.010107 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 13:43:09.010158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 13:43:09.010210 ==
1650 13:43:09.010262 TX Vref=22, minBit 8, minWin=27, winSum=451
1651 13:43:09.010315 TX Vref=24, minBit 8, minWin=27, winSum=450
1652 13:43:09.010367 TX Vref=26, minBit 15, minWin=27, winSum=455
1653 13:43:09.010419 TX Vref=28, minBit 8, minWin=27, winSum=458
1654 13:43:09.010471 TX Vref=30, minBit 15, minWin=27, winSum=458
1655 13:43:09.010523 TX Vref=32, minBit 15, minWin=27, winSum=459
1656 13:43:09.010574 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 32
1657 13:43:09.010627
1658 13:43:09.010678 Final TX Range 1 Vref 32
1659 13:43:09.010730
1660 13:43:09.010782 ==
1661 13:43:09.010833 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 13:43:09.010885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 13:43:09.010937 ==
1664 13:43:09.010988
1665 13:43:09.011039
1666 13:43:09.011090 TX Vref Scan disable
1667 13:43:09.011142 == TX Byte 0 ==
1668 13:43:09.011194 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1669 13:43:09.011246 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1670 13:43:09.011298 == TX Byte 1 ==
1671 13:43:09.011351 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1672 13:43:09.011402 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1673 13:43:09.011454
1674 13:43:09.011506 [DATLAT]
1675 13:43:09.011557 Freq=800, CH1 RK0
1676 13:43:09.011609
1677 13:43:09.011660 DATLAT Default: 0xa
1678 13:43:09.011712 0, 0xFFFF, sum = 0
1679 13:43:09.011765 1, 0xFFFF, sum = 0
1680 13:43:09.011818 2, 0xFFFF, sum = 0
1681 13:43:09.011870 3, 0xFFFF, sum = 0
1682 13:43:09.011922 4, 0xFFFF, sum = 0
1683 13:43:09.011974 5, 0xFFFF, sum = 0
1684 13:43:09.012027 6, 0xFFFF, sum = 0
1685 13:43:09.012079 7, 0xFFFF, sum = 0
1686 13:43:09.012131 8, 0xFFFF, sum = 0
1687 13:43:09.012184 9, 0x0, sum = 1
1688 13:43:09.012236 10, 0x0, sum = 2
1689 13:43:09.012288 11, 0x0, sum = 3
1690 13:43:09.012340 12, 0x0, sum = 4
1691 13:43:09.012393 best_step = 10
1692 13:43:09.012444
1693 13:43:09.012495 ==
1694 13:43:09.012547 Dram Type= 6, Freq= 0, CH_1, rank 0
1695 13:43:09.012599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1696 13:43:09.012651 ==
1697 13:43:09.012702 RX Vref Scan: 1
1698 13:43:09.012753
1699 13:43:09.012804 Set Vref Range= 32 -> 127
1700 13:43:09.012856
1701 13:43:09.012907 RX Vref 32 -> 127, step: 1
1702 13:43:09.012959
1703 13:43:09.013009 RX Delay -95 -> 252, step: 8
1704 13:43:09.013061
1705 13:43:09.013112 Set Vref, RX VrefLevel [Byte0]: 32
1706 13:43:09.013164 [Byte1]: 32
1707 13:43:09.013215
1708 13:43:09.013266 Set Vref, RX VrefLevel [Byte0]: 33
1709 13:43:09.013352 [Byte1]: 33
1710 13:43:09.013447
1711 13:43:09.013528 Set Vref, RX VrefLevel [Byte0]: 34
1712 13:43:09.013610 [Byte1]: 34
1713 13:43:09.013690
1714 13:43:09.013770 Set Vref, RX VrefLevel [Byte0]: 35
1715 13:43:09.013825 [Byte1]: 35
1716 13:43:09.013878
1717 13:43:09.013929 Set Vref, RX VrefLevel [Byte0]: 36
1718 13:43:09.013981 [Byte1]: 36
1719 13:43:09.014032
1720 13:43:09.014084 Set Vref, RX VrefLevel [Byte0]: 37
1721 13:43:09.014136 [Byte1]: 37
1722 13:43:09.014188
1723 13:43:09.014238 Set Vref, RX VrefLevel [Byte0]: 38
1724 13:43:09.014291 [Byte1]: 38
1725 13:43:09.014342
1726 13:43:09.014393 Set Vref, RX VrefLevel [Byte0]: 39
1727 13:43:09.014445 [Byte1]: 39
1728 13:43:09.014496
1729 13:43:09.014547 Set Vref, RX VrefLevel [Byte0]: 40
1730 13:43:09.014600 [Byte1]: 40
1731 13:43:09.014651
1732 13:43:09.014702 Set Vref, RX VrefLevel [Byte0]: 41
1733 13:43:09.014754 [Byte1]: 41
1734 13:43:09.014806
1735 13:43:09.014857 Set Vref, RX VrefLevel [Byte0]: 42
1736 13:43:09.014909 [Byte1]: 42
1737 13:43:09.014960
1738 13:43:09.015011 Set Vref, RX VrefLevel [Byte0]: 43
1739 13:43:09.015063 [Byte1]: 43
1740 13:43:09.015114
1741 13:43:09.015165 Set Vref, RX VrefLevel [Byte0]: 44
1742 13:43:09.015217 [Byte1]: 44
1743 13:43:09.015268
1744 13:43:09.015319 Set Vref, RX VrefLevel [Byte0]: 45
1745 13:43:09.015371 [Byte1]: 45
1746 13:43:09.015422
1747 13:43:09.015473 Set Vref, RX VrefLevel [Byte0]: 46
1748 13:43:09.015525 [Byte1]: 46
1749 13:43:09.015576
1750 13:43:09.015627 Set Vref, RX VrefLevel [Byte0]: 47
1751 13:43:09.015679 [Byte1]: 47
1752 13:43:09.015730
1753 13:43:09.015781 Set Vref, RX VrefLevel [Byte0]: 48
1754 13:43:09.015839 [Byte1]: 48
1755 13:43:09.015892
1756 13:43:09.015943 Set Vref, RX VrefLevel [Byte0]: 49
1757 13:43:09.015996 [Byte1]: 49
1758 13:43:09.016048
1759 13:43:09.016099 Set Vref, RX VrefLevel [Byte0]: 50
1760 13:43:09.016151 [Byte1]: 50
1761 13:43:09.016202
1762 13:43:09.016254 Set Vref, RX VrefLevel [Byte0]: 51
1763 13:43:09.016305 [Byte1]: 51
1764 13:43:09.016357
1765 13:43:09.016409 Set Vref, RX VrefLevel [Byte0]: 52
1766 13:43:09.016460 [Byte1]: 52
1767 13:43:09.016512
1768 13:43:09.016759 Set Vref, RX VrefLevel [Byte0]: 53
1769 13:43:09.016821 [Byte1]: 53
1770 13:43:09.016874
1771 13:43:09.016927 Set Vref, RX VrefLevel [Byte0]: 54
1772 13:43:09.016979 [Byte1]: 54
1773 13:43:09.017031
1774 13:43:09.017082 Set Vref, RX VrefLevel [Byte0]: 55
1775 13:43:09.017134 [Byte1]: 55
1776 13:43:09.017186
1777 13:43:09.017237 Set Vref, RX VrefLevel [Byte0]: 56
1778 13:43:09.017289 [Byte1]: 56
1779 13:43:09.017386
1780 13:43:09.017438 Set Vref, RX VrefLevel [Byte0]: 57
1781 13:43:09.017491 [Byte1]: 57
1782 13:43:09.017543
1783 13:43:09.017595 Set Vref, RX VrefLevel [Byte0]: 58
1784 13:43:09.017646 [Byte1]: 58
1785 13:43:09.017698
1786 13:43:09.017749 Set Vref, RX VrefLevel [Byte0]: 59
1787 13:43:09.017801 [Byte1]: 59
1788 13:43:09.017853
1789 13:43:09.017904 Set Vref, RX VrefLevel [Byte0]: 60
1790 13:43:09.017957 [Byte1]: 60
1791 13:43:09.018009
1792 13:43:09.018060 Set Vref, RX VrefLevel [Byte0]: 61
1793 13:43:09.018111 [Byte1]: 61
1794 13:43:09.018163
1795 13:43:09.018214 Set Vref, RX VrefLevel [Byte0]: 62
1796 13:43:09.018266 [Byte1]: 62
1797 13:43:09.018317
1798 13:43:09.018369 Set Vref, RX VrefLevel [Byte0]: 63
1799 13:43:09.018422 [Byte1]: 63
1800 13:43:09.018473
1801 13:43:09.018525 Set Vref, RX VrefLevel [Byte0]: 64
1802 13:43:09.018577 [Byte1]: 64
1803 13:43:09.018629
1804 13:43:09.018680 Set Vref, RX VrefLevel [Byte0]: 65
1805 13:43:09.018732 [Byte1]: 65
1806 13:43:09.018783
1807 13:43:09.018834 Set Vref, RX VrefLevel [Byte0]: 66
1808 13:43:09.018885 [Byte1]: 66
1809 13:43:09.018937
1810 13:43:09.018988 Set Vref, RX VrefLevel [Byte0]: 67
1811 13:43:09.019040 [Byte1]: 67
1812 13:43:09.019092
1813 13:43:09.019143 Set Vref, RX VrefLevel [Byte0]: 68
1814 13:43:09.019195 [Byte1]: 68
1815 13:43:09.019246
1816 13:43:09.019298 Set Vref, RX VrefLevel [Byte0]: 69
1817 13:43:09.019349 [Byte1]: 69
1818 13:43:09.019401
1819 13:43:09.019451 Set Vref, RX VrefLevel [Byte0]: 70
1820 13:43:09.019503 [Byte1]: 70
1821 13:43:09.019554
1822 13:43:09.019606 Set Vref, RX VrefLevel [Byte0]: 71
1823 13:43:09.019657 [Byte1]: 71
1824 13:43:09.019709
1825 13:43:09.019760 Set Vref, RX VrefLevel [Byte0]: 72
1826 13:43:09.019812 [Byte1]: 72
1827 13:43:09.019864
1828 13:43:09.019915 Set Vref, RX VrefLevel [Byte0]: 73
1829 13:43:09.019967 [Byte1]: 73
1830 13:43:09.020019
1831 13:43:09.020070 Set Vref, RX VrefLevel [Byte0]: 74
1832 13:43:09.020122 [Byte1]: 74
1833 13:43:09.020173
1834 13:43:09.020225 Set Vref, RX VrefLevel [Byte0]: 75
1835 13:43:09.020276 [Byte1]: 75
1836 13:43:09.020328
1837 13:43:09.020379 Set Vref, RX VrefLevel [Byte0]: 76
1838 13:43:09.020430 [Byte1]: 76
1839 13:43:09.020481
1840 13:43:09.020531 Set Vref, RX VrefLevel [Byte0]: 77
1841 13:43:09.020584 [Byte1]: 77
1842 13:43:09.020636
1843 13:43:09.020687 Set Vref, RX VrefLevel [Byte0]: 78
1844 13:43:09.020739 [Byte1]: 78
1845 13:43:09.020790
1846 13:43:09.020841 Final RX Vref Byte 0 = 53 to rank0
1847 13:43:09.020894 Final RX Vref Byte 1 = 63 to rank0
1848 13:43:09.020946 Final RX Vref Byte 0 = 53 to rank1
1849 13:43:09.020998 Final RX Vref Byte 1 = 63 to rank1==
1850 13:43:09.021050 Dram Type= 6, Freq= 0, CH_1, rank 0
1851 13:43:09.021102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 13:43:09.021154 ==
1853 13:43:09.021206 DQS Delay:
1854 13:43:09.021257 DQS0 = 0, DQS1 = 0
1855 13:43:09.021333 DQM Delay:
1856 13:43:09.021400 DQM0 = 90, DQM1 = 83
1857 13:43:09.021452 DQ Delay:
1858 13:43:09.021503 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
1859 13:43:09.021555 DQ4 =88, DQ5 =100, DQ6 =100, DQ7 =84
1860 13:43:09.021607 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1861 13:43:09.021659 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1862 13:43:09.021711
1863 13:43:09.021762
1864 13:43:09.021813 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1865 13:43:09.021866 CH1 RK0: MR19=606, MR18=324F
1866 13:43:09.021918 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1867 13:43:09.021969
1868 13:43:09.022021 ----->DramcWriteLeveling(PI) begin...
1869 13:43:09.022073 ==
1870 13:43:09.022124 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 13:43:09.022176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 13:43:09.022228 ==
1873 13:43:09.022279 Write leveling (Byte 0): 27 => 27
1874 13:43:09.022331 Write leveling (Byte 1): 28 => 28
1875 13:43:09.022383 DramcWriteLeveling(PI) end<-----
1876 13:43:09.022434
1877 13:43:09.022485 ==
1878 13:43:09.022536 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 13:43:09.022587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 13:43:09.022639 ==
1881 13:43:09.022691 [Gating] SW mode calibration
1882 13:43:09.022743 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1883 13:43:09.022795 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1884 13:43:09.022847 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1885 13:43:09.022899 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1886 13:43:09.022951 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 13:43:09.023003 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 13:43:09.023054 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 13:43:09.023106 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 13:43:09.023157 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 13:43:09.023209 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 13:43:09.023260 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 13:43:09.023311 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 13:43:09.023363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 13:43:09.023415 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 13:43:09.023466 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 13:43:09.023518 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 13:43:09.023570 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 13:43:09.023621 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 13:43:09.023672 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1901 13:43:09.023724 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 13:43:09.023776 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 13:43:09.024018 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 13:43:09.024077 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 13:43:09.024130 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 13:43:09.024182 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 13:43:09.024235 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 13:43:09.024287 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 13:43:09.024338 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1910 13:43:09.024390 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1911 13:43:09.024441 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 13:43:09.024493 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 13:43:09.024545 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 13:43:09.024597 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 13:43:09.024649 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 13:43:09.024702 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1917 13:43:09.024753 0 10 4 | B1->B0 | 2b2b 2f2f | 0 1 | (1 0) (1 1)
1918 13:43:09.024805 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1919 13:43:09.024857 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 13:43:09.024908 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 13:43:09.024960 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 13:43:09.025015 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 13:43:09.025067 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 13:43:09.025119 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 13:43:09.025170 0 11 4 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
1926 13:43:09.025222 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1927 13:43:09.025273 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 13:43:09.025368 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 13:43:09.025421 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 13:43:09.025473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 13:43:09.025525 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 13:43:09.025577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 13:43:09.025629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1934 13:43:09.025680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 13:43:09.025732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 13:43:09.025783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 13:43:09.025835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 13:43:09.025886 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 13:43:09.025937 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 13:43:09.025989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 13:43:09.026041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 13:43:09.026092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 13:43:09.026144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 13:43:09.026196 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 13:43:09.026246 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 13:43:09.026298 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 13:43:09.026349 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 13:43:09.026401 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 13:43:09.026453 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1950 13:43:09.026505 Total UI for P1: 0, mck2ui 16
1951 13:43:09.026557 best dqsien dly found for B0: ( 0, 14, 2)
1952 13:43:09.026609 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1953 13:43:09.026661 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1954 13:43:09.026712 Total UI for P1: 0, mck2ui 16
1955 13:43:09.026764 best dqsien dly found for B1: ( 0, 14, 6)
1956 13:43:09.026816 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1957 13:43:09.026868 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1958 13:43:09.026920
1959 13:43:09.026971 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1960 13:43:09.027023 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1961 13:43:09.027075 [Gating] SW calibration Done
1962 13:43:09.027126 ==
1963 13:43:09.027178 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:43:09.027230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:43:09.027282 ==
1966 13:43:09.027333 RX Vref Scan: 0
1967 13:43:09.027385
1968 13:43:09.027436 RX Vref 0 -> 0, step: 1
1969 13:43:09.027487
1970 13:43:09.027538 RX Delay -130 -> 252, step: 16
1971 13:43:09.027590 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1972 13:43:09.027642 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1973 13:43:09.027693 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1974 13:43:09.027745 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1975 13:43:09.027796 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1976 13:43:09.027847 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1977 13:43:09.027898 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1978 13:43:09.027950 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1979 13:43:09.028001 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1980 13:43:09.028052 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1981 13:43:09.028103 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1982 13:43:09.028155 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1983 13:43:09.028206 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1984 13:43:09.028257 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1985 13:43:09.028309 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1986 13:43:09.288447 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1987 13:43:09.288965 ==
1988 13:43:09.289380 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 13:43:09.289729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 13:43:09.290042 ==
1991 13:43:09.290214 DQS Delay:
1992 13:43:09.290270 DQS0 = 0, DQS1 = 0
1993 13:43:09.290346 DQM Delay:
1994 13:43:09.290454 DQM0 = 86, DQM1 = 81
1995 13:43:09.290522 DQ Delay:
1996 13:43:09.290575 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1997 13:43:09.290629 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =77
1998 13:43:09.290682 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1999 13:43:09.290734 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
2000 13:43:09.290787
2001 13:43:09.290839
2002 13:43:09.290914 ==
2003 13:43:09.291230 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 13:43:09.291365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 13:43:09.291497 ==
2006 13:43:09.291625
2007 13:43:09.291723
2008 13:43:09.291821 TX Vref Scan disable
2009 13:43:09.291920 == TX Byte 0 ==
2010 13:43:09.292021 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2011 13:43:09.292125 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2012 13:43:09.292214 == TX Byte 1 ==
2013 13:43:09.292302 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2014 13:43:09.292392 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2015 13:43:09.292480 ==
2016 13:43:09.292571 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 13:43:09.292665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 13:43:09.292753 ==
2019 13:43:09.292842 TX Vref=22, minBit 13, minWin=27, winSum=453
2020 13:43:09.292932 TX Vref=24, minBit 1, minWin=28, winSum=460
2021 13:43:09.293021 TX Vref=26, minBit 9, minWin=28, winSum=460
2022 13:43:09.293113 TX Vref=28, minBit 3, minWin=28, winSum=459
2023 13:43:09.293202 TX Vref=30, minBit 8, minWin=28, winSum=457
2024 13:43:09.293291 TX Vref=32, minBit 8, minWin=28, winSum=458
2025 13:43:09.293361 [TxChooseVref] Worse bit 1, Min win 28, Win sum 460, Final Vref 24
2026 13:43:09.293420
2027 13:43:09.293476 Final TX Range 1 Vref 24
2028 13:43:09.293533
2029 13:43:09.293589 ==
2030 13:43:09.293651 Dram Type= 6, Freq= 0, CH_1, rank 1
2031 13:43:09.293710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2032 13:43:09.293768 ==
2033 13:43:09.293824
2034 13:43:09.293880
2035 13:43:09.293936 TX Vref Scan disable
2036 13:43:09.293993 == TX Byte 0 ==
2037 13:43:09.294049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2038 13:43:09.294106 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2039 13:43:09.294163 == TX Byte 1 ==
2040 13:43:09.294228 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2041 13:43:09.294287 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2042 13:43:09.294344
2043 13:43:09.294400 [DATLAT]
2044 13:43:09.294456 Freq=800, CH1 RK1
2045 13:43:09.294513
2046 13:43:09.294569 DATLAT Default: 0xa
2047 13:43:09.294625 0, 0xFFFF, sum = 0
2048 13:43:09.294683 1, 0xFFFF, sum = 0
2049 13:43:09.294741 2, 0xFFFF, sum = 0
2050 13:43:09.294806 3, 0xFFFF, sum = 0
2051 13:43:09.294865 4, 0xFFFF, sum = 0
2052 13:43:09.294922 5, 0xFFFF, sum = 0
2053 13:43:09.294979 6, 0xFFFF, sum = 0
2054 13:43:09.295037 7, 0xFFFF, sum = 0
2055 13:43:09.295094 8, 0xFFFF, sum = 0
2056 13:43:09.295151 9, 0x0, sum = 1
2057 13:43:09.295208 10, 0x0, sum = 2
2058 13:43:09.295266 11, 0x0, sum = 3
2059 13:43:09.295324 12, 0x0, sum = 4
2060 13:43:09.295387 best_step = 10
2061 13:43:09.295443
2062 13:43:09.295499 ==
2063 13:43:09.295556 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 13:43:09.295613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 13:43:09.295670 ==
2066 13:43:09.295734 RX Vref Scan: 0
2067 13:43:09.295795
2068 13:43:09.295853 RX Vref 0 -> 0, step: 1
2069 13:43:09.295915
2070 13:43:09.295973 RX Delay -95 -> 252, step: 8
2071 13:43:09.296031 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2072 13:43:09.296088 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2073 13:43:09.296151 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2074 13:43:09.296209 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2075 13:43:09.296267 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2076 13:43:09.296325 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2077 13:43:09.296383 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2078 13:43:09.296449 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2079 13:43:09.296509 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2080 13:43:09.296566 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2081 13:43:09.296623 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2082 13:43:09.296680 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2083 13:43:09.296738 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2084 13:43:09.296795 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2085 13:43:09.296853 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2086 13:43:09.296911 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2087 13:43:09.296969 ==
2088 13:43:09.297034 Dram Type= 6, Freq= 0, CH_1, rank 1
2089 13:43:09.297093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2090 13:43:09.297152 ==
2091 13:43:09.297210 DQS Delay:
2092 13:43:09.297268 DQS0 = 0, DQS1 = 0
2093 13:43:09.297335 DQM Delay:
2094 13:43:09.297394 DQM0 = 90, DQM1 = 83
2095 13:43:09.297453 DQ Delay:
2096 13:43:09.297511 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2097 13:43:09.297578 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2098 13:43:09.297638 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2099 13:43:09.297696 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2100 13:43:09.297754
2101 13:43:09.297812
2102 13:43:09.297870 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2103 13:43:09.297929 CH1 RK1: MR19=606, MR18=3B11
2104 13:43:09.297987 CH1_RK1: MR19=0x606, MR18=0x3B11, DQSOSC=394, MR23=63, INC=95, DEC=63
2105 13:43:09.298046 [RxdqsGatingPostProcess] freq 800
2106 13:43:09.298109 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2107 13:43:09.298170 Pre-setting of DQS Precalculation
2108 13:43:09.298229 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2109 13:43:09.298287 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2110 13:43:09.298346 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2111 13:43:09.298405
2112 13:43:09.298463
2113 13:43:09.298521 [Calibration Summary] 1600 Mbps
2114 13:43:09.298580 CH 0, Rank 0
2115 13:43:09.298638 SW Impedance : PASS
2116 13:43:09.298705 DUTY Scan : NO K
2117 13:43:09.298764 ZQ Calibration : PASS
2118 13:43:09.298823 Jitter Meter : NO K
2119 13:43:09.298881 CBT Training : PASS
2120 13:43:09.298939 Write leveling : PASS
2121 13:43:09.298997 RX DQS gating : PASS
2122 13:43:09.299055 RX DQ/DQS(RDDQC) : PASS
2123 13:43:09.299114 TX DQ/DQS : PASS
2124 13:43:09.299172 RX DATLAT : PASS
2125 13:43:09.299233 RX DQ/DQS(Engine): PASS
2126 13:43:09.299294 TX OE : NO K
2127 13:43:09.299353 All Pass.
2128 13:43:09.299411
2129 13:43:09.299469 CH 0, Rank 1
2130 13:43:09.299527 SW Impedance : PASS
2131 13:43:09.299586 DUTY Scan : NO K
2132 13:43:09.299649 ZQ Calibration : PASS
2133 13:43:09.299709 Jitter Meter : NO K
2134 13:43:09.299767 CBT Training : PASS
2135 13:43:09.299834 Write leveling : PASS
2136 13:43:09.299894 RX DQS gating : PASS
2137 13:43:09.299951 RX DQ/DQS(RDDQC) : PASS
2138 13:43:09.300009 TX DQ/DQS : PASS
2139 13:43:09.300068 RX DATLAT : PASS
2140 13:43:09.300126 RX DQ/DQS(Engine): PASS
2141 13:43:09.300183 TX OE : NO K
2142 13:43:09.300241 All Pass.
2143 13:43:09.300299
2144 13:43:09.300357 CH 1, Rank 0
2145 13:43:09.300421 SW Impedance : PASS
2146 13:43:09.300479 DUTY Scan : NO K
2147 13:43:09.300538 ZQ Calibration : PASS
2148 13:43:09.300596 Jitter Meter : NO K
2149 13:43:09.300851 CBT Training : PASS
2150 13:43:09.300922 Write leveling : PASS
2151 13:43:09.301035 RX DQS gating : PASS
2152 13:43:09.301147 RX DQ/DQS(RDDQC) : PASS
2153 13:43:09.301259 TX DQ/DQS : PASS
2154 13:43:09.301376 RX DATLAT : PASS
2155 13:43:09.301470 RX DQ/DQS(Engine): PASS
2156 13:43:09.301565 TX OE : NO K
2157 13:43:09.301655 All Pass.
2158 13:43:09.301744
2159 13:43:09.301833 CH 1, Rank 1
2160 13:43:09.301922 SW Impedance : PASS
2161 13:43:09.302012 DUTY Scan : NO K
2162 13:43:09.302106 ZQ Calibration : PASS
2163 13:43:09.302196 Jitter Meter : NO K
2164 13:43:09.302285 CBT Training : PASS
2165 13:43:09.302375 Write leveling : PASS
2166 13:43:09.302464 RX DQS gating : PASS
2167 13:43:09.302553 RX DQ/DQS(RDDQC) : PASS
2168 13:43:09.302645 TX DQ/DQS : PASS
2169 13:43:09.302738 RX DATLAT : PASS
2170 13:43:09.302828 RX DQ/DQS(Engine): PASS
2171 13:43:09.302917 TX OE : NO K
2172 13:43:09.303007 All Pass.
2173 13:43:09.303095
2174 13:43:09.303187 DramC Write-DBI off
2175 13:43:09.303279 PER_BANK_REFRESH: Hybrid Mode
2176 13:43:09.303368 TX_TRACKING: ON
2177 13:43:09.303457 [GetDramInforAfterCalByMRR] Vendor 6.
2178 13:43:09.303547 [GetDramInforAfterCalByMRR] Revision 606.
2179 13:43:09.303637 [GetDramInforAfterCalByMRR] Revision 2 0.
2180 13:43:09.303726 MR0 0x3b3b
2181 13:43:09.303819 MR8 0x5151
2182 13:43:09.303908 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 13:43:09.303997
2184 13:43:09.304086 MR0 0x3b3b
2185 13:43:09.304174 MR8 0x5151
2186 13:43:09.304264 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 13:43:09.304347
2188 13:43:09.304413 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2189 13:43:09.304473 [FAST_K] Save calibration result to emmc
2190 13:43:09.304531 [FAST_K] Save calibration result to emmc
2191 13:43:09.304589 dram_init: config_dvfs: 1
2192 13:43:09.304646 dramc_set_vcore_voltage set vcore to 662500
2193 13:43:09.304704 Read voltage for 1200, 2
2194 13:43:09.304762 Vio18 = 0
2195 13:43:09.304819 Vcore = 662500
2196 13:43:09.304885 Vdram = 0
2197 13:43:09.304943 Vddq = 0
2198 13:43:09.305001 Vmddr = 0
2199 13:43:09.305058 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2200 13:43:09.305117 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2201 13:43:09.305176 MEM_TYPE=3, freq_sel=15
2202 13:43:09.305234 sv_algorithm_assistance_LP4_1600
2203 13:43:09.305292 ============ PULL DRAM RESETB DOWN ============
2204 13:43:09.305359 ========== PULL DRAM RESETB DOWN end =========
2205 13:43:09.305422 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2206 13:43:09.305483 ===================================
2207 13:43:09.305541 LPDDR4 DRAM CONFIGURATION
2208 13:43:09.305599 ===================================
2209 13:43:09.305658 EX_ROW_EN[0] = 0x0
2210 13:43:09.305716 EX_ROW_EN[1] = 0x0
2211 13:43:09.305774 LP4Y_EN = 0x0
2212 13:43:09.305832 WORK_FSP = 0x0
2213 13:43:09.305889 WL = 0x4
2214 13:43:09.305947 RL = 0x4
2215 13:43:09.306013 BL = 0x2
2216 13:43:09.306072 RPST = 0x0
2217 13:43:09.306135 RD_PRE = 0x0
2218 13:43:09.306194 WR_PRE = 0x1
2219 13:43:09.306252 WR_PST = 0x0
2220 13:43:09.306310 DBI_WR = 0x0
2221 13:43:09.306368 DBI_RD = 0x0
2222 13:43:09.306426 OTF = 0x1
2223 13:43:09.306484 ===================================
2224 13:43:09.306549 ===================================
2225 13:43:09.306608 ANA top config
2226 13:43:09.306666 ===================================
2227 13:43:09.306724 DLL_ASYNC_EN = 0
2228 13:43:09.306783 ALL_SLAVE_EN = 0
2229 13:43:09.306841 NEW_RANK_MODE = 1
2230 13:43:09.306900 DLL_IDLE_MODE = 1
2231 13:43:09.306959 LP45_APHY_COMB_EN = 1
2232 13:43:09.307017 TX_ODT_DIS = 1
2233 13:43:09.307082 NEW_8X_MODE = 1
2234 13:43:09.307143 ===================================
2235 13:43:09.307201 ===================================
2236 13:43:09.307260 data_rate = 2400
2237 13:43:09.307318 CKR = 1
2238 13:43:09.307377 DQ_P2S_RATIO = 8
2239 13:43:09.307436 ===================================
2240 13:43:09.307494 CA_P2S_RATIO = 8
2241 13:43:09.307552 DQ_CA_OPEN = 0
2242 13:43:09.307610 DQ_SEMI_OPEN = 0
2243 13:43:09.307702 CA_SEMI_OPEN = 0
2244 13:43:09.307792 CA_FULL_RATE = 0
2245 13:43:09.307882 DQ_CKDIV4_EN = 0
2246 13:43:09.307971 CA_CKDIV4_EN = 0
2247 13:43:09.308061 CA_PREDIV_EN = 0
2248 13:43:09.308150 PH8_DLY = 17
2249 13:43:09.308244 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2250 13:43:09.308334 DQ_AAMCK_DIV = 4
2251 13:43:09.308423 CA_AAMCK_DIV = 4
2252 13:43:09.308512 CA_ADMCK_DIV = 4
2253 13:43:09.308602 DQ_TRACK_CA_EN = 0
2254 13:43:09.308691 CA_PICK = 1200
2255 13:43:09.308779 CA_MCKIO = 1200
2256 13:43:09.308841 MCKIO_SEMI = 0
2257 13:43:09.308899 PLL_FREQ = 2366
2258 13:43:09.308958 DQ_UI_PI_RATIO = 32
2259 13:43:09.309016 CA_UI_PI_RATIO = 0
2260 13:43:09.309074 ===================================
2261 13:43:09.309134 ===================================
2262 13:43:09.309210 memory_type:LPDDR4
2263 13:43:09.309307 GP_NUM : 10
2264 13:43:09.309377 SRAM_EN : 1
2265 13:43:09.309436 MD32_EN : 0
2266 13:43:09.309495 ===================================
2267 13:43:09.309553 [ANA_INIT] >>>>>>>>>>>>>>
2268 13:43:09.309612 <<<<<< [CONFIGURE PHASE]: ANA_TX
2269 13:43:09.309671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2270 13:43:09.309730 ===================================
2271 13:43:09.309788 data_rate = 2400,PCW = 0X5b00
2272 13:43:09.309847 ===================================
2273 13:43:09.309909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2274 13:43:09.309971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 13:43:09.310030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 13:43:09.310090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2277 13:43:09.310148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2278 13:43:09.310207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2279 13:43:09.310265 [ANA_INIT] flow start
2280 13:43:09.310323 [ANA_INIT] PLL >>>>>>>>
2281 13:43:09.310382 [ANA_INIT] PLL <<<<<<<<
2282 13:43:09.310440 [ANA_INIT] MIDPI >>>>>>>>
2283 13:43:09.310507 [ANA_INIT] MIDPI <<<<<<<<
2284 13:43:09.310565 [ANA_INIT] DLL >>>>>>>>
2285 13:43:09.310623 [ANA_INIT] DLL <<<<<<<<
2286 13:43:09.310681 [ANA_INIT] flow end
2287 13:43:09.310941 ============ LP4 DIFF to SE enter ============
2288 13:43:09.311013 ============ LP4 DIFF to SE exit ============
2289 13:43:09.311083 [ANA_INIT] <<<<<<<<<<<<<
2290 13:43:09.311142 [Flow] Enable top DCM control >>>>>
2291 13:43:09.311201 [Flow] Enable top DCM control <<<<<
2292 13:43:09.311260 Enable DLL master slave shuffle
2293 13:43:09.311319 ==============================================================
2294 13:43:09.311378 Gating Mode config
2295 13:43:09.311436 ==============================================================
2296 13:43:09.311495 Config description:
2297 13:43:09.311553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2298 13:43:09.311617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2299 13:43:09.311677 SELPH_MODE 0: By rank 1: By Phase
2300 13:43:09.311736 ==============================================================
2301 13:43:09.311795 GAT_TRACK_EN = 1
2302 13:43:09.311854 RX_GATING_MODE = 2
2303 13:43:09.311912 RX_GATING_TRACK_MODE = 2
2304 13:43:09.311970 SELPH_MODE = 1
2305 13:43:09.312028 PICG_EARLY_EN = 1
2306 13:43:09.312086 VALID_LAT_VALUE = 1
2307 13:43:09.312144 ==============================================================
2308 13:43:09.312209 Enter into Gating configuration >>>>
2309 13:43:09.312269 Exit from Gating configuration <<<<
2310 13:43:09.312327 Enter into DVFS_PRE_config >>>>>
2311 13:43:09.312385 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2312 13:43:09.312445 Exit from DVFS_PRE_config <<<<<
2313 13:43:09.312503 Enter into PICG configuration >>>>
2314 13:43:09.312562 Exit from PICG configuration <<<<
2315 13:43:09.312620 [RX_INPUT] configuration >>>>>
2316 13:43:09.312677 [RX_INPUT] configuration <<<<<
2317 13:43:09.312741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2318 13:43:09.312801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2319 13:43:09.312859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2320 13:43:09.312918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2321 13:43:09.312976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2322 13:43:09.313035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2323 13:43:09.313093 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2324 13:43:09.313151 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2325 13:43:09.313210 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2326 13:43:09.313268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2327 13:43:09.313342 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2328 13:43:09.313403 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2329 13:43:09.313461 ===================================
2330 13:43:09.313520 LPDDR4 DRAM CONFIGURATION
2331 13:43:09.313578 ===================================
2332 13:43:09.313636 EX_ROW_EN[0] = 0x0
2333 13:43:09.313694 EX_ROW_EN[1] = 0x0
2334 13:43:09.313752 LP4Y_EN = 0x0
2335 13:43:09.313810 WORK_FSP = 0x0
2336 13:43:09.313869 WL = 0x4
2337 13:43:09.313933 RL = 0x4
2338 13:43:09.313991 BL = 0x2
2339 13:43:09.314049 RPST = 0x0
2340 13:43:09.314106 RD_PRE = 0x0
2341 13:43:09.314165 WR_PRE = 0x1
2342 13:43:09.314223 WR_PST = 0x0
2343 13:43:09.314281 DBI_WR = 0x0
2344 13:43:09.314339 DBI_RD = 0x0
2345 13:43:09.314397 OTF = 0x1
2346 13:43:09.314460 ===================================
2347 13:43:09.314521 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2348 13:43:09.314579 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2349 13:43:09.314637 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2350 13:43:09.314696 ===================================
2351 13:43:09.314755 LPDDR4 DRAM CONFIGURATION
2352 13:43:09.314813 ===================================
2353 13:43:09.314871 EX_ROW_EN[0] = 0x10
2354 13:43:09.314930 EX_ROW_EN[1] = 0x0
2355 13:43:09.314988 LP4Y_EN = 0x0
2356 13:43:09.315053 WORK_FSP = 0x0
2357 13:43:09.315111 WL = 0x4
2358 13:43:09.315170 RL = 0x4
2359 13:43:09.315228 BL = 0x2
2360 13:43:09.315285 RPST = 0x0
2361 13:43:09.315342 RD_PRE = 0x0
2362 13:43:09.315399 WR_PRE = 0x1
2363 13:43:09.315455 WR_PST = 0x0
2364 13:43:09.315511 DBI_WR = 0x0
2365 13:43:09.315567 DBI_RD = 0x0
2366 13:43:09.315630 OTF = 0x1
2367 13:43:09.315686 ===================================
2368 13:43:09.315743 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2369 13:43:09.315800 ==
2370 13:43:09.315856 Dram Type= 6, Freq= 0, CH_0, rank 0
2371 13:43:09.315913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 13:43:09.315970 ==
2373 13:43:09.316027 [Duty_Offset_Calibration]
2374 13:43:09.316083 B0:2 B1:0 CA:1
2375 13:43:09.316141
2376 13:43:09.316202 [DutyScan_Calibration_Flow] k_type=0
2377 13:43:09.316259
2378 13:43:09.316315 ==CLK 0==
2379 13:43:09.316372 Final CLK duty delay cell = -4
2380 13:43:09.316428 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2381 13:43:09.316485 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2382 13:43:09.316541 [-4] AVG Duty = 4953%(X100)
2383 13:43:09.316597
2384 13:43:09.316652 CH0 CLK Duty spec in!! Max-Min= 156%
2385 13:43:09.316709 [DutyScan_Calibration_Flow] ====Done====
2386 13:43:09.316771
2387 13:43:09.316827 [DutyScan_Calibration_Flow] k_type=1
2388 13:43:09.316883
2389 13:43:09.316938 ==DQS 0 ==
2390 13:43:09.316994 Final DQS duty delay cell = 0
2391 13:43:09.317051 [0] MAX Duty = 5187%(X100), DQS PI = 32
2392 13:43:09.317118 [0] MIN Duty = 4938%(X100), DQS PI = 0
2393 13:43:09.317169 [0] AVG Duty = 5062%(X100)
2394 13:43:09.317221
2395 13:43:09.317272 ==DQS 1 ==
2396 13:43:09.317395 Final DQS duty delay cell = -4
2397 13:43:09.317487 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2398 13:43:09.317552 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2399 13:43:09.317604 [-4] AVG Duty = 5015%(X100)
2400 13:43:09.317656
2401 13:43:09.317707 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2402 13:43:09.317760
2403 13:43:09.317811 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2404 13:43:09.317865 [DutyScan_Calibration_Flow] ====Done====
2405 13:43:09.317952
2406 13:43:09.318030 [DutyScan_Calibration_Flow] k_type=3
2407 13:43:09.318082
2408 13:43:09.318134 ==DQM 0 ==
2409 13:43:09.318391 Final DQM duty delay cell = 0
2410 13:43:09.318546 [0] MAX Duty = 5062%(X100), DQS PI = 24
2411 13:43:09.318690 [0] MIN Duty = 4813%(X100), DQS PI = 0
2412 13:43:09.318790 [0] AVG Duty = 4937%(X100)
2413 13:43:09.318888
2414 13:43:09.318986 ==DQM 1 ==
2415 13:43:09.319129 Final DQM duty delay cell = 0
2416 13:43:09.319211 [0] MAX Duty = 5187%(X100), DQS PI = 46
2417 13:43:09.319293 [0] MIN Duty = 5000%(X100), DQS PI = 12
2418 13:43:09.319373 [0] AVG Duty = 5093%(X100)
2419 13:43:09.319453
2420 13:43:09.319552 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2421 13:43:09.319663
2422 13:43:09.319783 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2423 13:43:09.319864 [DutyScan_Calibration_Flow] ====Done====
2424 13:43:09.319944
2425 13:43:09.320024 [DutyScan_Calibration_Flow] k_type=2
2426 13:43:09.320104
2427 13:43:09.320242 ==DQ 0 ==
2428 13:43:09.320323 Final DQ duty delay cell = -4
2429 13:43:09.320404 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2430 13:43:09.320485 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2431 13:43:09.320580 [-4] AVG Duty = 4953%(X100)
2432 13:43:09.320721
2433 13:43:09.320860 ==DQ 1 ==
2434 13:43:09.320954 Final DQ duty delay cell = 4
2435 13:43:09.321064 [4] MAX Duty = 5093%(X100), DQS PI = 4
2436 13:43:09.321158 [4] MIN Duty = 5031%(X100), DQS PI = 0
2437 13:43:09.321240 [4] AVG Duty = 5062%(X100)
2438 13:43:09.321330
2439 13:43:09.321407 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2440 13:43:09.321459
2441 13:43:09.321511 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2442 13:43:09.321564 [DutyScan_Calibration_Flow] ====Done====
2443 13:43:09.321616 ==
2444 13:43:09.321668 Dram Type= 6, Freq= 0, CH_1, rank 0
2445 13:43:09.321721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 13:43:09.321774 ==
2447 13:43:09.321826 [Duty_Offset_Calibration]
2448 13:43:09.321877 B0:0 B1:-1 CA:2
2449 13:43:09.321933
2450 13:43:09.321986 [DutyScan_Calibration_Flow] k_type=0
2451 13:43:09.322038
2452 13:43:09.322090 ==CLK 0==
2453 13:43:09.322141 Final CLK duty delay cell = 0
2454 13:43:09.322193 [0] MAX Duty = 5156%(X100), DQS PI = 16
2455 13:43:09.322244 [0] MIN Duty = 4938%(X100), DQS PI = 44
2456 13:43:09.322296 [0] AVG Duty = 5047%(X100)
2457 13:43:09.322347
2458 13:43:09.322399 CH1 CLK Duty spec in!! Max-Min= 218%
2459 13:43:09.322450 [DutyScan_Calibration_Flow] ====Done====
2460 13:43:09.322507
2461 13:43:09.322580 [DutyScan_Calibration_Flow] k_type=1
2462 13:43:09.322682
2463 13:43:09.322735 ==DQS 0 ==
2464 13:43:09.322793 Final DQS duty delay cell = 0
2465 13:43:09.322845 [0] MAX Duty = 5093%(X100), DQS PI = 24
2466 13:43:09.322924 [0] MIN Duty = 4969%(X100), DQS PI = 0
2467 13:43:09.323005 [0] AVG Duty = 5031%(X100)
2468 13:43:09.323056
2469 13:43:09.323113 ==DQS 1 ==
2470 13:43:09.323165 Final DQS duty delay cell = 0
2471 13:43:09.323217 [0] MAX Duty = 5156%(X100), DQS PI = 0
2472 13:43:09.323270 [0] MIN Duty = 4813%(X100), DQS PI = 36
2473 13:43:09.323321 [0] AVG Duty = 4984%(X100)
2474 13:43:09.323373
2475 13:43:09.323424 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2476 13:43:09.323476
2477 13:43:09.323527 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2478 13:43:09.323579 [DutyScan_Calibration_Flow] ====Done====
2479 13:43:09.323634
2480 13:43:09.323716 [DutyScan_Calibration_Flow] k_type=3
2481 13:43:09.323796
2482 13:43:09.323876 ==DQM 0 ==
2483 13:43:09.323957 Final DQM duty delay cell = 4
2484 13:43:09.324038 [4] MAX Duty = 5093%(X100), DQS PI = 22
2485 13:43:09.324118 [4] MIN Duty = 4938%(X100), DQS PI = 30
2486 13:43:09.324200 [4] AVG Duty = 5015%(X100)
2487 13:43:09.324281
2488 13:43:09.324361 ==DQM 1 ==
2489 13:43:09.324442 Final DQM duty delay cell = -4
2490 13:43:09.324528 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2491 13:43:09.324609 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2492 13:43:09.324690 [-4] AVG Duty = 4875%(X100)
2493 13:43:09.324771
2494 13:43:09.324827 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2495 13:43:09.324879
2496 13:43:09.324931 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2497 13:43:09.324982 [DutyScan_Calibration_Flow] ====Done====
2498 13:43:09.325033
2499 13:43:09.325085 [DutyScan_Calibration_Flow] k_type=2
2500 13:43:09.325136
2501 13:43:09.325187 ==DQ 0 ==
2502 13:43:09.325239 Final DQ duty delay cell = 0
2503 13:43:09.325291 [0] MAX Duty = 5031%(X100), DQS PI = 16
2504 13:43:09.325405 [0] MIN Duty = 4938%(X100), DQS PI = 30
2505 13:43:09.325457 [0] AVG Duty = 4984%(X100)
2506 13:43:09.325509
2507 13:43:09.325560 ==DQ 1 ==
2508 13:43:09.325612 Final DQ duty delay cell = 0
2509 13:43:09.325663 [0] MAX Duty = 5031%(X100), DQS PI = 2
2510 13:43:09.325715 [0] MIN Duty = 4813%(X100), DQS PI = 34
2511 13:43:09.325766 [0] AVG Duty = 4922%(X100)
2512 13:43:09.325818
2513 13:43:09.325874 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2514 13:43:09.325929
2515 13:43:09.325980 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2516 13:43:09.326032 [DutyScan_Calibration_Flow] ====Done====
2517 13:43:09.326084 nWR fixed to 30
2518 13:43:09.326143 [ModeRegInit_LP4] CH0 RK0
2519 13:43:09.326196 [ModeRegInit_LP4] CH0 RK1
2520 13:43:09.326247 [ModeRegInit_LP4] CH1 RK0
2521 13:43:09.326299 [ModeRegInit_LP4] CH1 RK1
2522 13:43:09.326350 match AC timing 7
2523 13:43:09.326402 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2524 13:43:09.326461 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2525 13:43:09.326515 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2526 13:43:09.326567 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2527 13:43:09.326619 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2528 13:43:09.326672 ==
2529 13:43:09.326724 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 13:43:09.326776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 13:43:09.326829 ==
2532 13:43:09.326881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 13:43:09.326933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 13:43:09.326986 [CA 0] Center 38 (7~69) winsize 63
2535 13:43:09.327044 [CA 1] Center 38 (8~69) winsize 62
2536 13:43:09.327095 [CA 2] Center 35 (5~66) winsize 62
2537 13:43:09.327148 [CA 3] Center 34 (4~65) winsize 62
2538 13:43:09.327200 [CA 4] Center 34 (4~65) winsize 62
2539 13:43:09.327252 [CA 5] Center 33 (3~63) winsize 61
2540 13:43:09.327303
2541 13:43:09.327354 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2542 13:43:09.327407
2543 13:43:09.327458 [CATrainingPosCal] consider 1 rank data
2544 13:43:09.327510 u2DelayCellTimex100 = 270/100 ps
2545 13:43:09.327564 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2546 13:43:09.327620 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2547 13:43:09.327673 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2548 13:43:09.327725 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2549 13:43:09.327776 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2550 13:43:09.327828 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2551 13:43:09.327880
2552 13:43:09.327931 CA PerBit enable=1, Macro0, CA PI delay=33
2553 13:43:09.327982
2554 13:43:09.328034 [CBTSetCACLKResult] CA Dly = 33
2555 13:43:09.328086 CS Dly: 6 (0~37)
2556 13:43:09.328142 ==
2557 13:43:09.328224 Dram Type= 6, Freq= 0, CH_0, rank 1
2558 13:43:09.328499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 13:43:09.328581 ==
2560 13:43:09.328682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2561 13:43:09.328786 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2562 13:43:09.328887 [CA 0] Center 39 (8~70) winsize 63
2563 13:43:09.329015 [CA 1] Center 38 (8~69) winsize 62
2564 13:43:09.329096 [CA 2] Center 35 (5~66) winsize 62
2565 13:43:09.329177 [CA 3] Center 35 (5~66) winsize 62
2566 13:43:09.329259 [CA 4] Center 34 (4~65) winsize 62
2567 13:43:09.329372 [CA 5] Center 34 (4~64) winsize 61
2568 13:43:09.329439
2569 13:43:09.329491 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2570 13:43:09.329543
2571 13:43:09.329595 [CATrainingPosCal] consider 2 rank data
2572 13:43:09.329653 u2DelayCellTimex100 = 270/100 ps
2573 13:43:09.329706 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2574 13:43:09.329759 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2575 13:43:09.329811 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2576 13:43:09.329869 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2577 13:43:09.329922 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2578 13:43:09.329973 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2579 13:43:09.330025
2580 13:43:09.330077 CA PerBit enable=1, Macro0, CA PI delay=33
2581 13:43:09.330129
2582 13:43:09.330180 [CBTSetCACLKResult] CA Dly = 33
2583 13:43:09.330232 CS Dly: 7 (0~39)
2584 13:43:09.330283
2585 13:43:09.330334 ----->DramcWriteLeveling(PI) begin...
2586 13:43:09.330391 ==
2587 13:43:09.330444 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 13:43:09.330496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 13:43:09.330548 ==
2590 13:43:09.330599 Write leveling (Byte 0): 35 => 35
2591 13:43:09.330651 Write leveling (Byte 1): 30 => 30
2592 13:43:09.330703 DramcWriteLeveling(PI) end<-----
2593 13:43:09.330754
2594 13:43:09.330805 ==
2595 13:43:09.330857 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 13:43:09.330908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2597 13:43:09.330966 ==
2598 13:43:09.331019 [Gating] SW mode calibration
2599 13:43:09.331070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2600 13:43:09.331123 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2601 13:43:09.331175 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2602 13:43:09.331228 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2603 13:43:09.331280 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 13:43:09.331332 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 13:43:09.331383 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 13:43:09.331435 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 13:43:09.331486 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2608 13:43:09.331546 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2609 13:43:09.331599 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2610 13:43:09.331651 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 13:43:09.331703 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 13:43:09.331754 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 13:43:09.331812 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 13:43:09.331865 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 13:43:09.331923 1 0 24 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
2616 13:43:09.331976 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2617 13:43:09.332028 1 1 0 | B1->B0 | 3837 4646 | 1 0 | (0 0) (0 0)
2618 13:43:09.332084 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 13:43:09.332138 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 13:43:09.332189 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 13:43:09.332241 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 13:43:09.332293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 13:43:09.332345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 13:43:09.332397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2625 13:43:09.332449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 13:43:09.332500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 13:43:09.332552 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 13:43:09.332608 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 13:43:09.332662 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 13:43:09.332717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 13:43:09.332771 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 13:43:09.332823 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 13:43:09.332875 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 13:43:09.332928 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 13:43:09.332979 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 13:43:09.333031 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 13:43:09.333083 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 13:43:09.333134 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 13:43:09.333213 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 13:43:09.333299 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2641 13:43:09.333412 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2642 13:43:09.333465 Total UI for P1: 0, mck2ui 16
2643 13:43:09.333518 best dqsien dly found for B0: ( 1, 3, 26)
2644 13:43:09.333571 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 13:43:09.333623 Total UI for P1: 0, mck2ui 16
2646 13:43:09.333676 best dqsien dly found for B1: ( 1, 4, 0)
2647 13:43:09.333733 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2648 13:43:09.333787 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2649 13:43:09.333838
2650 13:43:09.333890 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2651 13:43:09.333942 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2652 13:43:09.333994 [Gating] SW calibration Done
2653 13:43:09.334045 ==
2654 13:43:09.334098 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 13:43:09.334150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 13:43:09.334202 ==
2657 13:43:09.334253 RX Vref Scan: 0
2658 13:43:09.334312
2659 13:43:09.334365 RX Vref 0 -> 0, step: 1
2660 13:43:09.334417
2661 13:43:09.334469 RX Delay -40 -> 252, step: 8
2662 13:43:09.334521 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2663 13:43:09.334770 iDelay=208, Bit 1, Center 127 (56 ~ 199) 144
2664 13:43:09.334855 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2665 13:43:09.335028 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2666 13:43:09.335142 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2667 13:43:09.335273 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2668 13:43:09.335374 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2669 13:43:09.335462 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2670 13:43:09.335544 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2671 13:43:09.335625 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2672 13:43:09.335706 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2673 13:43:09.335787 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2674 13:43:09.335868 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2675 13:43:09.335929 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2676 13:43:09.335981 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2677 13:43:09.336033 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2678 13:43:09.336092 ==
2679 13:43:09.336146 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 13:43:09.336199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 13:43:09.336252 ==
2682 13:43:09.336304 DQS Delay:
2683 13:43:09.336355 DQS0 = 0, DQS1 = 0
2684 13:43:09.336407 DQM Delay:
2685 13:43:09.336464 DQM0 = 123, DQM1 = 110
2686 13:43:09.336518 DQ Delay:
2687 13:43:09.336570 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2688 13:43:09.336622 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2689 13:43:09.336674 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2690 13:43:09.336726 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2691 13:43:09.336778
2692 13:43:09.336835
2693 13:43:09.336887 ==
2694 13:43:09.336939 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 13:43:09.336991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 13:43:09.337051 ==
2697 13:43:09.337103
2698 13:43:09.337154
2699 13:43:09.337206 TX Vref Scan disable
2700 13:43:09.337257 == TX Byte 0 ==
2701 13:43:09.337366 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2702 13:43:09.337435 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2703 13:43:09.337487 == TX Byte 1 ==
2704 13:43:09.337539 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 13:43:09.337596 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 13:43:09.337650 ==
2707 13:43:09.337702 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 13:43:09.337754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 13:43:09.337806 ==
2710 13:43:09.337857 TX Vref=22, minBit 3, minWin=24, winSum=412
2711 13:43:09.337910 TX Vref=24, minBit 4, minWin=24, winSum=412
2712 13:43:09.337962 TX Vref=26, minBit 7, minWin=24, winSum=417
2713 13:43:09.338014 TX Vref=28, minBit 0, minWin=25, winSum=422
2714 13:43:09.338066 TX Vref=30, minBit 4, minWin=25, winSum=423
2715 13:43:09.338118 TX Vref=32, minBit 1, minWin=25, winSum=420
2716 13:43:09.338175 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 30
2717 13:43:09.338229
2718 13:43:09.338280 Final TX Range 1 Vref 30
2719 13:43:09.338332
2720 13:43:09.338384 ==
2721 13:43:09.338437 Dram Type= 6, Freq= 0, CH_0, rank 0
2722 13:43:09.338488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2723 13:43:09.338541 ==
2724 13:43:09.338593
2725 13:43:09.338644
2726 13:43:09.338695 TX Vref Scan disable
2727 13:43:09.338754 == TX Byte 0 ==
2728 13:43:09.338807 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2729 13:43:09.338859 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2730 13:43:09.338911 == TX Byte 1 ==
2731 13:43:09.338962 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2732 13:43:09.339015 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2733 13:43:09.339066
2734 13:43:09.339118 [DATLAT]
2735 13:43:09.339169 Freq=1200, CH0 RK0
2736 13:43:09.339226
2737 13:43:09.339279 DATLAT Default: 0xd
2738 13:43:09.339337 0, 0xFFFF, sum = 0
2739 13:43:09.339390 1, 0xFFFF, sum = 0
2740 13:43:09.339443 2, 0xFFFF, sum = 0
2741 13:43:09.339496 3, 0xFFFF, sum = 0
2742 13:43:09.339549 4, 0xFFFF, sum = 0
2743 13:43:09.339601 5, 0xFFFF, sum = 0
2744 13:43:09.339654 6, 0xFFFF, sum = 0
2745 13:43:09.339706 7, 0xFFFF, sum = 0
2746 13:43:09.339759 8, 0xFFFF, sum = 0
2747 13:43:09.339811 9, 0xFFFF, sum = 0
2748 13:43:09.339868 10, 0xFFFF, sum = 0
2749 13:43:09.339922 11, 0xFFFF, sum = 0
2750 13:43:09.339975 12, 0x0, sum = 1
2751 13:43:09.340027 13, 0x0, sum = 2
2752 13:43:09.340080 14, 0x0, sum = 3
2753 13:43:09.340132 15, 0x0, sum = 4
2754 13:43:09.340184 best_step = 13
2755 13:43:09.340236
2756 13:43:09.340288 ==
2757 13:43:09.340344 Dram Type= 6, Freq= 0, CH_0, rank 0
2758 13:43:09.340398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2759 13:43:09.340462 ==
2760 13:43:09.340515 RX Vref Scan: 1
2761 13:43:09.340567
2762 13:43:09.340619 Set Vref Range= 32 -> 127
2763 13:43:09.340671
2764 13:43:09.340723 RX Vref 32 -> 127, step: 1
2765 13:43:09.340775
2766 13:43:09.340827 RX Delay -13 -> 252, step: 4
2767 13:43:09.340879
2768 13:43:09.340931 Set Vref, RX VrefLevel [Byte0]: 32
2769 13:43:09.340988 [Byte1]: 32
2770 13:43:09.341042
2771 13:43:09.341094 Set Vref, RX VrefLevel [Byte0]: 33
2772 13:43:09.341146 [Byte1]: 33
2773 13:43:09.341199
2774 13:43:09.341251 Set Vref, RX VrefLevel [Byte0]: 34
2775 13:43:09.341309 [Byte1]: 34
2776 13:43:09.341396
2777 13:43:09.341448 Set Vref, RX VrefLevel [Byte0]: 35
2778 13:43:09.341500 [Byte1]: 35
2779 13:43:09.341554
2780 13:43:09.341609 Set Vref, RX VrefLevel [Byte0]: 36
2781 13:43:09.341662 [Byte1]: 36
2782 13:43:09.341714
2783 13:43:09.341766 Set Vref, RX VrefLevel [Byte0]: 37
2784 13:43:09.341817 [Byte1]: 37
2785 13:43:09.341869
2786 13:43:09.341921 Set Vref, RX VrefLevel [Byte0]: 38
2787 13:43:09.341973 [Byte1]: 38
2788 13:43:09.342026
2789 13:43:09.342077 Set Vref, RX VrefLevel [Byte0]: 39
2790 13:43:09.342134 [Byte1]: 39
2791 13:43:09.342187
2792 13:43:09.342239 Set Vref, RX VrefLevel [Byte0]: 40
2793 13:43:09.342291 [Byte1]: 40
2794 13:43:09.342344
2795 13:43:09.342395 Set Vref, RX VrefLevel [Byte0]: 41
2796 13:43:09.342447 [Byte1]: 41
2797 13:43:09.342498
2798 13:43:09.342550 Set Vref, RX VrefLevel [Byte0]: 42
2799 13:43:09.342601 [Byte1]: 42
2800 13:43:09.342653
2801 13:43:09.342711 Set Vref, RX VrefLevel [Byte0]: 43
2802 13:43:09.342764 [Byte1]: 43
2803 13:43:09.342834
2804 13:43:09.342901 Set Vref, RX VrefLevel [Byte0]: 44
2805 13:43:09.342954 [Byte1]: 44
2806 13:43:09.343005
2807 13:43:09.343057 Set Vref, RX VrefLevel [Byte0]: 45
2808 13:43:09.343109 [Byte1]: 45
2809 13:43:09.343161
2810 13:43:09.343213 Set Vref, RX VrefLevel [Byte0]: 46
2811 13:43:09.343269 [Byte1]: 46
2812 13:43:09.343323
2813 13:43:09.343375 Set Vref, RX VrefLevel [Byte0]: 47
2814 13:43:09.343427 [Byte1]: 47
2815 13:43:09.343479
2816 13:43:09.343530 Set Vref, RX VrefLevel [Byte0]: 48
2817 13:43:09.343582 [Byte1]: 48
2818 13:43:09.343634
2819 13:43:09.343879 Set Vref, RX VrefLevel [Byte0]: 49
2820 13:43:09.344019 [Byte1]: 49
2821 13:43:09.344119
2822 13:43:09.344219 Set Vref, RX VrefLevel [Byte0]: 50
2823 13:43:09.344320 [Byte1]: 50
2824 13:43:09.344414
2825 13:43:09.344497 Set Vref, RX VrefLevel [Byte0]: 51
2826 13:43:09.344579 [Byte1]: 51
2827 13:43:09.344659
2828 13:43:09.344740 Set Vref, RX VrefLevel [Byte0]: 52
2829 13:43:09.344821 [Byte1]: 52
2830 13:43:09.344901
2831 13:43:09.344985 Set Vref, RX VrefLevel [Byte0]: 53
2832 13:43:09.345100 [Byte1]: 53
2833 13:43:09.345180
2834 13:43:09.345261 Set Vref, RX VrefLevel [Byte0]: 54
2835 13:43:09.345393 [Byte1]: 54
2836 13:43:09.345475
2837 13:43:09.345533 Set Vref, RX VrefLevel [Byte0]: 55
2838 13:43:09.345586 [Byte1]: 55
2839 13:43:09.345639
2840 13:43:09.345691 Set Vref, RX VrefLevel [Byte0]: 56
2841 13:43:09.345744 [Byte1]: 56
2842 13:43:09.345796
2843 13:43:09.345849 Set Vref, RX VrefLevel [Byte0]: 57
2844 13:43:09.345901 [Byte1]: 57
2845 13:43:09.345980
2846 13:43:09.346052 Set Vref, RX VrefLevel [Byte0]: 58
2847 13:43:09.346104 [Byte1]: 58
2848 13:43:09.346156
2849 13:43:09.346207 Set Vref, RX VrefLevel [Byte0]: 59
2850 13:43:09.346260 [Byte1]: 59
2851 13:43:09.346313
2852 13:43:09.346365 Set Vref, RX VrefLevel [Byte0]: 60
2853 13:43:09.346417 [Byte1]: 60
2854 13:43:09.346470
2855 13:43:09.346526 Set Vref, RX VrefLevel [Byte0]: 61
2856 13:43:09.346579 [Byte1]: 61
2857 13:43:09.346631
2858 13:43:09.346684 Set Vref, RX VrefLevel [Byte0]: 62
2859 13:43:09.346736 [Byte1]: 62
2860 13:43:09.346788
2861 13:43:09.346840 Set Vref, RX VrefLevel [Byte0]: 63
2862 13:43:09.346893 [Byte1]: 63
2863 13:43:09.346945
2864 13:43:09.346996 Set Vref, RX VrefLevel [Byte0]: 64
2865 13:43:09.347056 [Byte1]: 64
2866 13:43:09.347109
2867 13:43:09.347160 Set Vref, RX VrefLevel [Byte0]: 65
2868 13:43:09.347212 [Byte1]: 65
2869 13:43:09.347264
2870 13:43:09.347316 Set Vref, RX VrefLevel [Byte0]: 66
2871 13:43:09.347369 [Byte1]: 66
2872 13:43:09.347420
2873 13:43:09.347471 Set Vref, RX VrefLevel [Byte0]: 67
2874 13:43:09.347529 [Byte1]: 67
2875 13:43:09.347582
2876 13:43:09.347634 Set Vref, RX VrefLevel [Byte0]: 68
2877 13:43:09.347686 [Byte1]: 68
2878 13:43:09.347739
2879 13:43:09.347791 Set Vref, RX VrefLevel [Byte0]: 69
2880 13:43:09.347843 [Byte1]: 69
2881 13:43:09.347894
2882 13:43:09.347946 Set Vref, RX VrefLevel [Byte0]: 70
2883 13:43:09.347998 [Byte1]: 70
2884 13:43:09.348058
2885 13:43:09.348111 Final RX Vref Byte 0 = 60 to rank0
2886 13:43:09.348164 Final RX Vref Byte 1 = 51 to rank0
2887 13:43:09.348216 Final RX Vref Byte 0 = 60 to rank1
2888 13:43:09.348269 Final RX Vref Byte 1 = 51 to rank1==
2889 13:43:09.348322 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 13:43:09.348375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 13:43:09.348428 ==
2892 13:43:09.348480 DQS Delay:
2893 13:43:09.348536 DQS0 = 0, DQS1 = 0
2894 13:43:09.348591 DQM Delay:
2895 13:43:09.348644 DQM0 = 122, DQM1 = 109
2896 13:43:09.348696 DQ Delay:
2897 13:43:09.348748 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2898 13:43:09.348800 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2899 13:43:09.348853 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2900 13:43:09.348905 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2901 13:43:09.348957
2902 13:43:09.349008
2903 13:43:09.349059 [DQSOSCAuto] RK0, (LSB)MR18= 0xb07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2904 13:43:09.349121 CH0 RK0: MR19=404, MR18=B07
2905 13:43:09.349218 CH0_RK0: MR19=0x404, MR18=0xB07, DQSOSC=405, MR23=63, INC=39, DEC=26
2906 13:43:09.349327
2907 13:43:09.349397 ----->DramcWriteLeveling(PI) begin...
2908 13:43:09.349451 ==
2909 13:43:09.349504 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 13:43:09.349556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 13:43:09.349616 ==
2912 13:43:09.349677 Write leveling (Byte 0): 35 => 35
2913 13:43:09.349736 Write leveling (Byte 1): 29 => 29
2914 13:43:09.349789 DramcWriteLeveling(PI) end<-----
2915 13:43:09.349847
2916 13:43:09.349900 ==
2917 13:43:09.349952 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 13:43:09.350005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 13:43:09.350057 ==
2920 13:43:09.350109 [Gating] SW mode calibration
2921 13:43:09.350161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 13:43:09.350217 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 13:43:09.350273 0 15 0 | B1->B0 | 2f2f 3434 | 1 0 | (0 0) (0 0)
2924 13:43:09.350327 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 13:43:09.350380 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 13:43:09.350432 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 13:43:09.350484 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 13:43:09.350536 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 13:43:09.350588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2930 13:43:09.350641 0 15 28 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
2931 13:43:09.350693 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 13:43:09.350746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 13:43:09.350804 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 13:43:09.350859 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 13:43:09.350911 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 13:43:09.350964 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 13:43:09.351016 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2938 13:43:09.351067 1 0 28 | B1->B0 | 3535 3e3d | 0 1 | (0 0) (0 0)
2939 13:43:09.351119 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 13:43:09.351171 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 13:43:09.351222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 13:43:09.351275 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 13:43:09.351326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 13:43:09.351385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 13:43:09.351439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 13:43:09.351491 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 13:43:09.351737 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 13:43:09.351821 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 13:43:09.351924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 13:43:09.352028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 13:43:09.352129 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 13:43:09.352223 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 13:43:09.352305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 13:43:09.352387 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 13:43:09.352468 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 13:43:09.352568 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 13:43:09.352623 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 13:43:09.352675 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 13:43:09.352728 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 13:43:09.352781 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 13:43:09.352833 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 13:43:09.352886 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 13:43:09.352937 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2964 13:43:09.352990 Total UI for P1: 0, mck2ui 16
2965 13:43:09.353042 best dqsien dly found for B1: ( 1, 3, 30)
2966 13:43:09.353104 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 13:43:09.353157 Total UI for P1: 0, mck2ui 16
2968 13:43:09.353210 best dqsien dly found for B0: ( 1, 3, 30)
2969 13:43:09.353262 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2970 13:43:09.353357 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2971 13:43:09.353424
2972 13:43:09.353475 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2973 13:43:09.353527 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2974 13:43:09.353579 [Gating] SW calibration Done
2975 13:43:09.353634 ==
2976 13:43:09.353689 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 13:43:09.353741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 13:43:09.353794 ==
2979 13:43:09.353846 RX Vref Scan: 0
2980 13:43:09.353897
2981 13:43:09.353949 RX Vref 0 -> 0, step: 1
2982 13:43:09.354001
2983 13:43:09.354052 RX Delay -40 -> 252, step: 8
2984 13:43:09.354104 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2985 13:43:09.354156 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2986 13:43:09.354216 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2987 13:43:09.354270 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2988 13:43:09.354322 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2989 13:43:09.354375 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2990 13:43:09.354427 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2991 13:43:09.354479 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2992 13:43:09.354531 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2993 13:43:09.354582 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 13:43:09.354634 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2995 13:43:09.354686 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2996 13:43:09.354738 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2997 13:43:09.354797 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2998 13:43:09.354850 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 13:43:09.354903 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3000 13:43:09.354954 ==
3001 13:43:09.355006 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 13:43:09.355059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 13:43:09.355112 ==
3004 13:43:09.510562 DQS Delay:
3005 13:43:09.511238 DQS0 = 0, DQS1 = 0
3006 13:43:09.511707 DQM Delay:
3007 13:43:09.512026 DQM0 = 120, DQM1 = 108
3008 13:43:09.512328 DQ Delay:
3009 13:43:09.512619 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3010 13:43:09.513028 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3011 13:43:09.513516 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3012 13:43:09.513895 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3013 13:43:09.514371
3014 13:43:09.514860
3015 13:43:09.515295 ==
3016 13:43:09.515588 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 13:43:09.515868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 13:43:09.516146 ==
3019 13:43:09.516419
3020 13:43:09.516857
3021 13:43:09.517481 TX Vref Scan disable
3022 13:43:09.518027 == TX Byte 0 ==
3023 13:43:09.518547 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3024 13:43:09.518999 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3025 13:43:09.519427 == TX Byte 1 ==
3026 13:43:09.519852 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3027 13:43:09.520300 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3028 13:43:09.520720 ==
3029 13:43:09.521168 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 13:43:09.521539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 13:43:09.521820 ==
3032 13:43:09.522093 TX Vref=22, minBit 2, minWin=24, winSum=408
3033 13:43:09.522367 TX Vref=24, minBit 1, minWin=24, winSum=419
3034 13:43:09.522641 TX Vref=26, minBit 1, minWin=24, winSum=419
3035 13:43:09.522913 TX Vref=28, minBit 2, minWin=25, winSum=425
3036 13:43:09.523182 TX Vref=30, minBit 1, minWin=25, winSum=423
3037 13:43:09.523450 TX Vref=32, minBit 2, minWin=25, winSum=422
3038 13:43:09.523719 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 28
3039 13:43:09.523989
3040 13:43:09.524256 Final TX Range 1 Vref 28
3041 13:43:09.524523
3042 13:43:09.524788 ==
3043 13:43:09.525055 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 13:43:09.525363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 13:43:09.525808 ==
3046 13:43:09.526098
3047 13:43:09.526368
3048 13:43:09.526638 TX Vref Scan disable
3049 13:43:09.526907 == TX Byte 0 ==
3050 13:43:09.527177 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3051 13:43:09.527450 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3052 13:43:09.527721 == TX Byte 1 ==
3053 13:43:09.527988 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3054 13:43:09.528258 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3055 13:43:09.528525
3056 13:43:09.528792 [DATLAT]
3057 13:43:09.529057 Freq=1200, CH0 RK1
3058 13:43:09.529357
3059 13:43:09.529632 DATLAT Default: 0xd
3060 13:43:09.529900 0, 0xFFFF, sum = 0
3061 13:43:09.530175 1, 0xFFFF, sum = 0
3062 13:43:09.530447 2, 0xFFFF, sum = 0
3063 13:43:09.530716 3, 0xFFFF, sum = 0
3064 13:43:09.530985 4, 0xFFFF, sum = 0
3065 13:43:09.531258 5, 0xFFFF, sum = 0
3066 13:43:09.531586 6, 0xFFFF, sum = 0
3067 13:43:09.531864 7, 0xFFFF, sum = 0
3068 13:43:09.532136 8, 0xFFFF, sum = 0
3069 13:43:09.532410 9, 0xFFFF, sum = 0
3070 13:43:09.532678 10, 0xFFFF, sum = 0
3071 13:43:09.532950 11, 0xFFFF, sum = 0
3072 13:43:09.533220 12, 0x0, sum = 1
3073 13:43:09.533697 13, 0x0, sum = 2
3074 13:43:09.534097 14, 0x0, sum = 3
3075 13:43:09.534382 15, 0x0, sum = 4
3076 13:43:09.534655 best_step = 13
3077 13:43:09.534924
3078 13:43:09.535189 ==
3079 13:43:09.535454 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 13:43:09.536126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 13:43:09.536432 ==
3082 13:43:09.536708 RX Vref Scan: 0
3083 13:43:09.536977
3084 13:43:09.537213 RX Vref 0 -> 0, step: 1
3085 13:43:09.537459
3086 13:43:09.537656 RX Delay -21 -> 252, step: 4
3087 13:43:09.537849 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3088 13:43:09.538043 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3089 13:43:09.538236 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3090 13:43:09.538428 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3091 13:43:09.538621 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3092 13:43:09.538812 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3093 13:43:09.539004 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3094 13:43:09.539197 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3095 13:43:09.539389 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3096 13:43:09.539581 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3097 13:43:09.539772 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3098 13:43:09.539963 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3099 13:43:09.540155 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3100 13:43:09.540353 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3101 13:43:09.540553 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3102 13:43:09.540753 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3103 13:43:09.540949 ==
3104 13:43:09.541146 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 13:43:09.541372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 13:43:09.541675 ==
3107 13:43:09.541884 DQS Delay:
3108 13:43:09.542084 DQS0 = 0, DQS1 = 0
3109 13:43:09.542235 DQM Delay:
3110 13:43:09.542384 DQM0 = 119, DQM1 = 108
3111 13:43:09.542535 DQ Delay:
3112 13:43:09.542685 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3113 13:43:09.542837 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3114 13:43:09.542988 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3115 13:43:09.543138 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
3116 13:43:09.543286
3117 13:43:09.543433
3118 13:43:09.543581 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3119 13:43:09.543733 CH0 RK1: MR19=403, MR18=DF4
3120 13:43:09.543881 CH0_RK1: MR19=0x403, MR18=0xDF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3121 13:43:09.544032 [RxdqsGatingPostProcess] freq 1200
3122 13:43:09.544182 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 13:43:09.544332 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 13:43:09.544481 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 13:43:09.544630 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 13:43:09.544779 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 13:43:09.544928 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 13:43:09.545077 best DQS1 dly(2T, 0.5T) = (0, 11)
3129 13:43:09.545224 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 13:43:09.545402 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3131 13:43:09.545553 Pre-setting of DQS Precalculation
3132 13:43:09.545702 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 13:43:09.545850 ==
3134 13:43:09.546000 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 13:43:09.546151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 13:43:09.546301 ==
3137 13:43:09.546451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 13:43:09.546603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3139 13:43:09.546753 [CA 0] Center 37 (7~68) winsize 62
3140 13:43:09.546902 [CA 1] Center 37 (7~68) winsize 62
3141 13:43:09.547051 [CA 2] Center 35 (5~65) winsize 61
3142 13:43:09.547192 [CA 3] Center 34 (4~65) winsize 62
3143 13:43:09.547312 [CA 4] Center 34 (4~65) winsize 62
3144 13:43:09.547433 [CA 5] Center 33 (3~64) winsize 62
3145 13:43:09.547551
3146 13:43:09.547669 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3147 13:43:09.547789
3148 13:43:09.547908 [CATrainingPosCal] consider 1 rank data
3149 13:43:09.548028 u2DelayCellTimex100 = 270/100 ps
3150 13:43:09.548147 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 13:43:09.548267 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 13:43:09.548385 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3153 13:43:09.548504 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3154 13:43:09.548623 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3155 13:43:09.548743 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 13:43:09.548861
3157 13:43:09.548981 CA PerBit enable=1, Macro0, CA PI delay=33
3158 13:43:09.549101
3159 13:43:09.549219 [CBTSetCACLKResult] CA Dly = 33
3160 13:43:09.549359 CS Dly: 5 (0~36)
3161 13:43:09.549484 ==
3162 13:43:09.549604 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 13:43:09.549723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 13:43:09.549845 ==
3165 13:43:09.549964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 13:43:09.550085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 13:43:09.550206 [CA 0] Center 38 (8~68) winsize 61
3168 13:43:09.550326 [CA 1] Center 38 (7~69) winsize 63
3169 13:43:09.550445 [CA 2] Center 35 (5~66) winsize 62
3170 13:43:09.550564 [CA 3] Center 34 (4~65) winsize 62
3171 13:43:09.550682 [CA 4] Center 34 (4~65) winsize 62
3172 13:43:09.550801 [CA 5] Center 34 (4~64) winsize 61
3173 13:43:09.550920
3174 13:43:09.551038 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 13:43:09.551157
3176 13:43:09.551276 [CATrainingPosCal] consider 2 rank data
3177 13:43:09.551395 u2DelayCellTimex100 = 270/100 ps
3178 13:43:09.551515 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3179 13:43:09.551633 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3180 13:43:09.551752 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3181 13:43:09.551871 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3182 13:43:09.551992 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3183 13:43:09.552115 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3184 13:43:09.552215
3185 13:43:09.552316 CA PerBit enable=1, Macro0, CA PI delay=34
3186 13:43:09.552416
3187 13:43:09.552515 [CBTSetCACLKResult] CA Dly = 34
3188 13:43:09.552615 CS Dly: 6 (0~39)
3189 13:43:09.552715
3190 13:43:09.552814 ----->DramcWriteLeveling(PI) begin...
3191 13:43:09.552916 ==
3192 13:43:09.553016 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 13:43:09.553116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 13:43:09.553217 ==
3195 13:43:09.553329 Write leveling (Byte 0): 24 => 24
3196 13:43:09.553432 Write leveling (Byte 1): 28 => 28
3197 13:43:09.553532 DramcWriteLeveling(PI) end<-----
3198 13:43:09.553631
3199 13:43:09.553729 ==
3200 13:43:09.553827 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 13:43:09.553928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 13:43:09.554030 ==
3203 13:43:09.554130 [Gating] SW mode calibration
3204 13:43:09.554461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 13:43:09.554575 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 13:43:09.554679 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 13:43:09.554782 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 13:43:09.554883 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 13:43:09.554983 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 13:43:09.555084 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 13:43:09.555184 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3212 13:43:09.555283 0 15 24 | B1->B0 | 2b2b 2323 | 0 1 | (0 0) (1 0)
3213 13:43:09.555383 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 13:43:09.555483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 13:43:09.555583 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 13:43:09.555683 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 13:43:09.555784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 13:43:09.555885 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 13:43:09.555985 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3220 13:43:09.556084 1 0 24 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
3221 13:43:09.556185 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 13:43:09.556285 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 13:43:09.556385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 13:43:09.556485 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 13:43:09.556585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 13:43:09.556686 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 13:43:09.556785 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 13:43:09.556884 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3229 13:43:09.556984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3230 13:43:09.557091 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 13:43:09.557177 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 13:43:09.557262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 13:43:09.557366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 13:43:09.557453 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 13:43:09.557540 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 13:43:09.557626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 13:43:09.557711 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 13:43:09.557797 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 13:43:09.557883 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 13:43:09.557969 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 13:43:09.558055 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 13:43:09.558141 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 13:43:09.558227 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3244 13:43:09.558312 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 13:43:09.558398 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3246 13:43:09.558484 Total UI for P1: 0, mck2ui 16
3247 13:43:09.558570 best dqsien dly found for B0: ( 1, 3, 22)
3248 13:43:09.558657 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 13:43:09.558743 Total UI for P1: 0, mck2ui 16
3250 13:43:09.558830 best dqsien dly found for B1: ( 1, 3, 26)
3251 13:43:09.558917 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3252 13:43:09.559004 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3253 13:43:09.559089
3254 13:43:09.559176 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3255 13:43:09.559262 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3256 13:43:09.559348 [Gating] SW calibration Done
3257 13:43:09.559434 ==
3258 13:43:09.559520 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 13:43:09.559605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 13:43:09.559692 ==
3261 13:43:09.559777 RX Vref Scan: 0
3262 13:43:09.559863
3263 13:43:09.559947 RX Vref 0 -> 0, step: 1
3264 13:43:09.560033
3265 13:43:09.560118 RX Delay -40 -> 252, step: 8
3266 13:43:09.560204 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3267 13:43:09.560290 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3268 13:43:09.560376 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3269 13:43:09.560462 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3270 13:43:09.560548 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3271 13:43:09.560635 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3272 13:43:09.560721 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3273 13:43:09.560807 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3274 13:43:09.560892 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3275 13:43:09.560978 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3276 13:43:09.561064 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3277 13:43:09.561149 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3278 13:43:09.561234 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3279 13:43:09.561334 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3280 13:43:09.561422 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3281 13:43:09.561509 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3282 13:43:09.561594 ==
3283 13:43:09.561681 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 13:43:09.561767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 13:43:09.561855 ==
3286 13:43:09.561939 DQS Delay:
3287 13:43:09.562025 DQS0 = 0, DQS1 = 0
3288 13:43:09.562115 DQM Delay:
3289 13:43:09.562190 DQM0 = 120, DQM1 = 112
3290 13:43:09.562265 DQ Delay:
3291 13:43:09.562340 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3292 13:43:09.562416 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3293 13:43:09.562491 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3294 13:43:09.562566 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3295 13:43:09.562641
3296 13:43:09.562715
3297 13:43:09.562789 ==
3298 13:43:09.562864 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 13:43:09.562938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 13:43:09.563014 ==
3301 13:43:09.563089
3302 13:43:09.563164
3303 13:43:09.563237 TX Vref Scan disable
3304 13:43:09.563312 == TX Byte 0 ==
3305 13:43:09.563387 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3306 13:43:09.563462 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3307 13:43:09.563538 == TX Byte 1 ==
3308 13:43:09.563817 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 13:43:09.563901 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 13:43:09.563978 ==
3311 13:43:09.564053 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 13:43:09.564128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 13:43:09.564182 ==
3314 13:43:09.564236 TX Vref=22, minBit 10, minWin=24, winSum=404
3315 13:43:09.564290 TX Vref=24, minBit 11, minWin=24, winSum=408
3316 13:43:09.564344 TX Vref=26, minBit 8, minWin=25, winSum=418
3317 13:43:09.564398 TX Vref=28, minBit 9, minWin=25, winSum=420
3318 13:43:09.564453 TX Vref=30, minBit 10, minWin=25, winSum=421
3319 13:43:09.564506 TX Vref=32, minBit 11, minWin=25, winSum=419
3320 13:43:09.564560 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 30
3321 13:43:09.564613
3322 13:43:09.564666 Final TX Range 1 Vref 30
3323 13:43:09.564720
3324 13:43:09.564773 ==
3325 13:43:09.564827 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 13:43:09.564881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 13:43:09.564934 ==
3328 13:43:09.564988
3329 13:43:09.565041
3330 13:43:09.565094 TX Vref Scan disable
3331 13:43:09.565147 == TX Byte 0 ==
3332 13:43:09.565201 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3333 13:43:09.565255 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3334 13:43:09.565346 == TX Byte 1 ==
3335 13:43:09.565402 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3336 13:43:09.565455 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3337 13:43:09.565510
3338 13:43:09.565563 [DATLAT]
3339 13:43:09.565616 Freq=1200, CH1 RK0
3340 13:43:09.565669
3341 13:43:09.565723 DATLAT Default: 0xd
3342 13:43:09.565777 0, 0xFFFF, sum = 0
3343 13:43:09.565832 1, 0xFFFF, sum = 0
3344 13:43:09.565886 2, 0xFFFF, sum = 0
3345 13:43:09.565941 3, 0xFFFF, sum = 0
3346 13:43:09.565996 4, 0xFFFF, sum = 0
3347 13:43:09.566052 5, 0xFFFF, sum = 0
3348 13:43:09.566105 6, 0xFFFF, sum = 0
3349 13:43:09.566159 7, 0xFFFF, sum = 0
3350 13:43:09.566212 8, 0xFFFF, sum = 0
3351 13:43:09.566267 9, 0xFFFF, sum = 0
3352 13:43:09.566320 10, 0xFFFF, sum = 0
3353 13:43:09.566374 11, 0xFFFF, sum = 0
3354 13:43:09.566427 12, 0x0, sum = 1
3355 13:43:09.566481 13, 0x0, sum = 2
3356 13:43:09.566534 14, 0x0, sum = 3
3357 13:43:09.566588 15, 0x0, sum = 4
3358 13:43:09.566641 best_step = 13
3359 13:43:09.566693
3360 13:43:09.566745 ==
3361 13:43:09.566797 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 13:43:09.566849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 13:43:09.566902 ==
3364 13:43:09.566954 RX Vref Scan: 1
3365 13:43:09.567005
3366 13:43:09.567057 Set Vref Range= 32 -> 127
3367 13:43:09.567109
3368 13:43:09.567160 RX Vref 32 -> 127, step: 1
3369 13:43:09.567211
3370 13:43:09.567263 RX Delay -13 -> 252, step: 4
3371 13:43:09.567315
3372 13:43:09.567366 Set Vref, RX VrefLevel [Byte0]: 32
3373 13:43:09.567418 [Byte1]: 32
3374 13:43:09.567470
3375 13:43:09.567522 Set Vref, RX VrefLevel [Byte0]: 33
3376 13:43:09.567574 [Byte1]: 33
3377 13:43:09.567626
3378 13:43:09.567677 Set Vref, RX VrefLevel [Byte0]: 34
3379 13:43:09.567729 [Byte1]: 34
3380 13:43:09.567781
3381 13:43:09.567832 Set Vref, RX VrefLevel [Byte0]: 35
3382 13:43:09.567883 [Byte1]: 35
3383 13:43:09.567935
3384 13:43:09.567987 Set Vref, RX VrefLevel [Byte0]: 36
3385 13:43:09.568039 [Byte1]: 36
3386 13:43:09.568091
3387 13:43:09.568171 Set Vref, RX VrefLevel [Byte0]: 37
3388 13:43:09.568239 [Byte1]: 37
3389 13:43:09.568291
3390 13:43:09.568342 Set Vref, RX VrefLevel [Byte0]: 38
3391 13:43:09.568394 [Byte1]: 38
3392 13:43:09.568446
3393 13:43:09.568497 Set Vref, RX VrefLevel [Byte0]: 39
3394 13:43:09.568549 [Byte1]: 39
3395 13:43:09.568601
3396 13:43:09.568653 Set Vref, RX VrefLevel [Byte0]: 40
3397 13:43:09.568705 [Byte1]: 40
3398 13:43:09.568757
3399 13:43:09.568809 Set Vref, RX VrefLevel [Byte0]: 41
3400 13:43:09.568861 [Byte1]: 41
3401 13:43:09.568913
3402 13:43:09.568964 Set Vref, RX VrefLevel [Byte0]: 42
3403 13:43:09.569016 [Byte1]: 42
3404 13:43:09.569069
3405 13:43:09.569121 Set Vref, RX VrefLevel [Byte0]: 43
3406 13:43:09.569173 [Byte1]: 43
3407 13:43:09.569224
3408 13:43:09.569275 Set Vref, RX VrefLevel [Byte0]: 44
3409 13:43:09.569359 [Byte1]: 44
3410 13:43:09.569426
3411 13:43:09.569509 Set Vref, RX VrefLevel [Byte0]: 45
3412 13:43:09.569561 [Byte1]: 45
3413 13:43:09.569613
3414 13:43:09.569665 Set Vref, RX VrefLevel [Byte0]: 46
3415 13:43:09.569717 [Byte1]: 46
3416 13:43:09.569768
3417 13:43:09.569820 Set Vref, RX VrefLevel [Byte0]: 47
3418 13:43:09.569872 [Byte1]: 47
3419 13:43:09.569924
3420 13:43:09.569975 Set Vref, RX VrefLevel [Byte0]: 48
3421 13:43:09.570027 [Byte1]: 48
3422 13:43:09.570078
3423 13:43:09.570130 Set Vref, RX VrefLevel [Byte0]: 49
3424 13:43:09.570182 [Byte1]: 49
3425 13:43:09.570270
3426 13:43:09.570352 Set Vref, RX VrefLevel [Byte0]: 50
3427 13:43:09.570434 [Byte1]: 50
3428 13:43:09.570515
3429 13:43:09.570601 Set Vref, RX VrefLevel [Byte0]: 51
3430 13:43:09.570658 [Byte1]: 51
3431 13:43:09.570711
3432 13:43:09.570763 Set Vref, RX VrefLevel [Byte0]: 52
3433 13:43:09.570815 [Byte1]: 52
3434 13:43:09.570867
3435 13:43:09.570919 Set Vref, RX VrefLevel [Byte0]: 53
3436 13:43:09.570971 [Byte1]: 53
3437 13:43:09.571022
3438 13:43:09.571074 Set Vref, RX VrefLevel [Byte0]: 54
3439 13:43:09.571125 [Byte1]: 54
3440 13:43:09.571177
3441 13:43:09.571229 Set Vref, RX VrefLevel [Byte0]: 55
3442 13:43:09.571281 [Byte1]: 55
3443 13:43:09.571333
3444 13:43:09.571385 Set Vref, RX VrefLevel [Byte0]: 56
3445 13:43:09.571436 [Byte1]: 56
3446 13:43:09.571489
3447 13:43:09.571541 Set Vref, RX VrefLevel [Byte0]: 57
3448 13:43:09.571593 [Byte1]: 57
3449 13:43:09.571644
3450 13:43:09.571696 Set Vref, RX VrefLevel [Byte0]: 58
3451 13:43:09.571747 [Byte1]: 58
3452 13:43:09.571799
3453 13:43:09.571850 Set Vref, RX VrefLevel [Byte0]: 59
3454 13:43:09.571901 [Byte1]: 59
3455 13:43:09.571953
3456 13:43:09.572005 Set Vref, RX VrefLevel [Byte0]: 60
3457 13:43:09.572056 [Byte1]: 60
3458 13:43:09.572108
3459 13:43:09.572159 Set Vref, RX VrefLevel [Byte0]: 61
3460 13:43:09.572211 [Byte1]: 61
3461 13:43:09.572263
3462 13:43:09.572314 Set Vref, RX VrefLevel [Byte0]: 62
3463 13:43:09.572365 [Byte1]: 62
3464 13:43:09.572417
3465 13:43:09.572468 Set Vref, RX VrefLevel [Byte0]: 63
3466 13:43:09.572535 [Byte1]: 63
3467 13:43:09.572600
3468 13:43:09.572652 Set Vref, RX VrefLevel [Byte0]: 64
3469 13:43:09.572703 [Byte1]: 64
3470 13:43:09.572755
3471 13:43:09.572806 Set Vref, RX VrefLevel [Byte0]: 65
3472 13:43:09.572858 [Byte1]: 65
3473 13:43:09.572910
3474 13:43:09.572961 Set Vref, RX VrefLevel [Byte0]: 66
3475 13:43:09.573208 [Byte1]: 66
3476 13:43:09.573266
3477 13:43:09.573359 Set Vref, RX VrefLevel [Byte0]: 67
3478 13:43:09.573412 [Byte1]: 67
3479 13:43:09.573463
3480 13:43:09.573515 Final RX Vref Byte 0 = 52 to rank0
3481 13:43:09.573568 Final RX Vref Byte 1 = 53 to rank0
3482 13:43:09.573620 Final RX Vref Byte 0 = 52 to rank1
3483 13:43:09.573672 Final RX Vref Byte 1 = 53 to rank1==
3484 13:43:09.573724 Dram Type= 6, Freq= 0, CH_1, rank 0
3485 13:43:09.573777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 13:43:09.573830 ==
3487 13:43:09.573882 DQS Delay:
3488 13:43:09.573934 DQS0 = 0, DQS1 = 0
3489 13:43:09.573987 DQM Delay:
3490 13:43:09.574038 DQM0 = 119, DQM1 = 112
3491 13:43:09.574090 DQ Delay:
3492 13:43:09.574141 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3493 13:43:09.574194 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3494 13:43:09.574247 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3495 13:43:09.574299 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3496 13:43:09.574351
3497 13:43:09.574402
3498 13:43:09.574453 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3499 13:43:09.574506 CH1 RK0: MR19=404, MR18=518
3500 13:43:09.574559 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3501 13:43:09.574611
3502 13:43:09.574663 ----->DramcWriteLeveling(PI) begin...
3503 13:43:09.574715 ==
3504 13:43:09.574767 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 13:43:09.574819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 13:43:09.574872 ==
3507 13:43:09.574923 Write leveling (Byte 0): 24 => 24
3508 13:43:09.574975 Write leveling (Byte 1): 29 => 29
3509 13:43:09.575028 DramcWriteLeveling(PI) end<-----
3510 13:43:09.575079
3511 13:43:09.575130 ==
3512 13:43:09.575182 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 13:43:09.575233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 13:43:09.575285 ==
3515 13:43:09.575337 [Gating] SW mode calibration
3516 13:43:09.575389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3517 13:43:09.575441 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3518 13:43:09.575493 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 13:43:09.575545 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 13:43:09.575597 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 13:43:09.575649 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 13:43:09.575701 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 13:43:09.575754 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 13:43:09.575806 0 15 24 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 1)
3525 13:43:09.575858 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
3526 13:43:09.575909 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 13:43:09.575962 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 13:43:09.576015 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 13:43:09.576067 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 13:43:09.576119 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 13:43:09.576171 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 13:43:09.576222 1 0 24 | B1->B0 | 3838 2424 | 0 0 | (1 1) (0 0)
3533 13:43:09.576274 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
3534 13:43:09.576327 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 13:43:09.576378 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 13:43:09.576430 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 13:43:09.576482 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 13:43:09.576534 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 13:43:09.576586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 13:43:09.576638 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3541 13:43:09.576690 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3542 13:43:09.576742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 13:43:09.576793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 13:43:09.576845 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 13:43:09.576897 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 13:43:09.576949 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 13:43:09.577000 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 13:43:09.577053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 13:43:09.577104 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 13:43:09.577156 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 13:43:09.577208 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 13:43:09.577260 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 13:43:09.577352 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 13:43:09.577406 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 13:43:09.577458 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3556 13:43:09.577510 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3557 13:43:09.577562 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 13:43:09.577614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 13:43:09.577666 Total UI for P1: 0, mck2ui 16
3560 13:43:09.577719 best dqsien dly found for B0: ( 1, 3, 26)
3561 13:43:09.577772 Total UI for P1: 0, mck2ui 16
3562 13:43:09.577825 best dqsien dly found for B1: ( 1, 3, 24)
3563 13:43:09.577877 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3564 13:43:09.577929 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3565 13:43:09.577981
3566 13:43:09.578032 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 13:43:09.578084 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3568 13:43:09.578136 [Gating] SW calibration Done
3569 13:43:09.578188 ==
3570 13:43:09.578240 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 13:43:09.578293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 13:43:09.578345 ==
3573 13:43:09.578397 RX Vref Scan: 0
3574 13:43:09.578449
3575 13:43:09.578500 RX Vref 0 -> 0, step: 1
3576 13:43:09.578551
3577 13:43:09.578603 RX Delay -40 -> 252, step: 8
3578 13:43:09.578655 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3579 13:43:09.578707 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3580 13:43:09.578759 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3581 13:43:09.578810 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3582 13:43:09.579051 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3583 13:43:09.579109 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3584 13:43:09.579162 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3585 13:43:09.579214 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3586 13:43:09.579266 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3587 13:43:09.579318 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3588 13:43:09.579370 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3589 13:43:09.579422 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3590 13:43:09.579474 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3591 13:43:09.579526 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3592 13:43:09.579577 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3593 13:43:09.579629 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3594 13:43:09.579681 ==
3595 13:43:09.579733 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 13:43:09.579785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 13:43:09.579837 ==
3598 13:43:09.579889 DQS Delay:
3599 13:43:09.579940 DQS0 = 0, DQS1 = 0
3600 13:43:09.579993 DQM Delay:
3601 13:43:09.580044 DQM0 = 119, DQM1 = 113
3602 13:43:09.580097 DQ Delay:
3603 13:43:09.580149 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3604 13:43:09.580201 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3605 13:43:09.580254 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3606 13:43:09.580306 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =123
3607 13:43:09.580358
3608 13:43:09.580409
3609 13:43:09.580461 ==
3610 13:43:09.580512 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 13:43:09.580564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 13:43:09.580617 ==
3613 13:43:09.580668
3614 13:43:09.580719
3615 13:43:09.580771 TX Vref Scan disable
3616 13:43:09.580822 == TX Byte 0 ==
3617 13:43:09.580874 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3618 13:43:09.580927 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3619 13:43:09.580979 == TX Byte 1 ==
3620 13:43:09.581031 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3621 13:43:09.581083 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3622 13:43:09.581135 ==
3623 13:43:09.581187 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 13:43:09.581238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 13:43:09.581290 ==
3626 13:43:09.581419 TX Vref=22, minBit 1, minWin=25, winSum=415
3627 13:43:09.581499 TX Vref=24, minBit 1, minWin=25, winSum=417
3628 13:43:09.581555 TX Vref=26, minBit 0, minWin=26, winSum=425
3629 13:43:09.581608 TX Vref=28, minBit 1, minWin=26, winSum=429
3630 13:43:09.581661 TX Vref=30, minBit 1, minWin=26, winSum=428
3631 13:43:09.581714 TX Vref=32, minBit 1, minWin=26, winSum=426
3632 13:43:09.581767 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3633 13:43:09.581819
3634 13:43:09.581871 Final TX Range 1 Vref 28
3635 13:43:09.581923
3636 13:43:09.581975 ==
3637 13:43:09.582026 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 13:43:09.582078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 13:43:09.582131 ==
3640 13:43:09.582182
3641 13:43:09.582238
3642 13:43:09.582292 TX Vref Scan disable
3643 13:43:09.582343 == TX Byte 0 ==
3644 13:43:09.582395 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3645 13:43:09.582447 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3646 13:43:09.582500 == TX Byte 1 ==
3647 13:43:09.582552 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3648 13:43:09.582603 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3649 13:43:09.582656
3650 13:43:09.582707 [DATLAT]
3651 13:43:09.582758 Freq=1200, CH1 RK1
3652 13:43:09.582810
3653 13:43:09.582861 DATLAT Default: 0xd
3654 13:43:09.582913 0, 0xFFFF, sum = 0
3655 13:43:09.582966 1, 0xFFFF, sum = 0
3656 13:43:09.583019 2, 0xFFFF, sum = 0
3657 13:43:09.583071 3, 0xFFFF, sum = 0
3658 13:43:09.583124 4, 0xFFFF, sum = 0
3659 13:43:09.583177 5, 0xFFFF, sum = 0
3660 13:43:09.583230 6, 0xFFFF, sum = 0
3661 13:43:09.583282 7, 0xFFFF, sum = 0
3662 13:43:09.583335 8, 0xFFFF, sum = 0
3663 13:43:09.583387 9, 0xFFFF, sum = 0
3664 13:43:09.583439 10, 0xFFFF, sum = 0
3665 13:43:09.583492 11, 0xFFFF, sum = 0
3666 13:43:09.583545 12, 0x0, sum = 1
3667 13:43:09.583598 13, 0x0, sum = 2
3668 13:43:09.583651 14, 0x0, sum = 3
3669 13:43:09.583703 15, 0x0, sum = 4
3670 13:43:09.583755 best_step = 13
3671 13:43:09.583807
3672 13:43:09.583858 ==
3673 13:43:09.583910 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 13:43:09.583962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 13:43:09.584014 ==
3676 13:43:09.584064 RX Vref Scan: 0
3677 13:43:09.584115
3678 13:43:09.584166 RX Vref 0 -> 0, step: 1
3679 13:43:09.584218
3680 13:43:09.584270 RX Delay -13 -> 252, step: 4
3681 13:43:09.584322 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3682 13:43:09.584374 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3683 13:43:09.584426 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3684 13:43:09.584479 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3685 13:43:09.584530 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3686 13:43:09.584583 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3687 13:43:09.584635 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3688 13:43:09.584687 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3689 13:43:09.584738 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3690 13:43:09.584791 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3691 13:43:09.584843 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3692 13:43:09.584895 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3693 13:43:09.584946 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3694 13:43:09.584998 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3695 13:43:09.585050 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3696 13:43:09.585102 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3697 13:43:09.585153 ==
3698 13:43:09.585205 Dram Type= 6, Freq= 0, CH_1, rank 1
3699 13:43:09.585257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3700 13:43:09.585316 ==
3701 13:43:09.585407 DQS Delay:
3702 13:43:09.585459 DQS0 = 0, DQS1 = 0
3703 13:43:09.585511 DQM Delay:
3704 13:43:09.585563 DQM0 = 119, DQM1 = 113
3705 13:43:09.585615 DQ Delay:
3706 13:43:09.585667 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3707 13:43:09.585719 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3708 13:43:09.585771 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3709 13:43:09.585823 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3710 13:43:09.585875
3711 13:43:09.585926
3712 13:43:09.585992 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3713 13:43:09.586058 CH1 RK1: MR19=403, MR18=CF1
3714 13:43:09.586110 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3715 13:43:09.586163 [RxdqsGatingPostProcess] freq 1200
3716 13:43:09.586215 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3717 13:43:09.586267 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 13:43:09.586319 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 13:43:09.586563 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 13:43:09.586622 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 13:43:09.586676 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 13:43:09.586728 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 13:43:09.586781 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 13:43:09.586834 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 13:43:09.586887 Pre-setting of DQS Precalculation
3726 13:43:09.586939 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3727 13:43:09.586992 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3728 13:43:09.587045 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3729 13:43:09.587098
3730 13:43:09.587150
3731 13:43:09.587201 [Calibration Summary] 2400 Mbps
3732 13:43:09.587254 CH 0, Rank 0
3733 13:43:09.587306 SW Impedance : PASS
3734 13:43:09.587358 DUTY Scan : NO K
3735 13:43:09.587409 ZQ Calibration : PASS
3736 13:43:09.587461 Jitter Meter : NO K
3737 13:43:09.587513 CBT Training : PASS
3738 13:43:09.587565 Write leveling : PASS
3739 13:43:09.587617 RX DQS gating : PASS
3740 13:43:09.587668 RX DQ/DQS(RDDQC) : PASS
3741 13:43:09.587720 TX DQ/DQS : PASS
3742 13:43:09.587772 RX DATLAT : PASS
3743 13:43:09.587824 RX DQ/DQS(Engine): PASS
3744 13:43:09.587876 TX OE : NO K
3745 13:43:09.587928 All Pass.
3746 13:43:09.587979
3747 13:43:09.588030 CH 0, Rank 1
3748 13:43:09.588082 SW Impedance : PASS
3749 13:43:09.588134 DUTY Scan : NO K
3750 13:43:09.588186 ZQ Calibration : PASS
3751 13:43:09.588238 Jitter Meter : NO K
3752 13:43:09.588290 CBT Training : PASS
3753 13:43:09.588342 Write leveling : PASS
3754 13:43:09.588393 RX DQS gating : PASS
3755 13:43:09.588445 RX DQ/DQS(RDDQC) : PASS
3756 13:43:09.588497 TX DQ/DQS : PASS
3757 13:43:09.588549 RX DATLAT : PASS
3758 13:43:09.588601 RX DQ/DQS(Engine): PASS
3759 13:43:09.588652 TX OE : NO K
3760 13:43:09.588704 All Pass.
3761 13:43:09.588756
3762 13:43:09.588807 CH 1, Rank 0
3763 13:43:09.588859 SW Impedance : PASS
3764 13:43:09.588911 DUTY Scan : NO K
3765 13:43:09.588963 ZQ Calibration : PASS
3766 13:43:09.589016 Jitter Meter : NO K
3767 13:43:09.589068 CBT Training : PASS
3768 13:43:09.589120 Write leveling : PASS
3769 13:43:09.589171 RX DQS gating : PASS
3770 13:43:09.589223 RX DQ/DQS(RDDQC) : PASS
3771 13:43:09.589275 TX DQ/DQS : PASS
3772 13:43:09.589370 RX DATLAT : PASS
3773 13:43:09.589423 RX DQ/DQS(Engine): PASS
3774 13:43:09.589475 TX OE : NO K
3775 13:43:09.589527 All Pass.
3776 13:43:09.589579
3777 13:43:09.589630 CH 1, Rank 1
3778 13:43:09.589682 SW Impedance : PASS
3779 13:43:09.589734 DUTY Scan : NO K
3780 13:43:09.589786 ZQ Calibration : PASS
3781 13:43:09.589837 Jitter Meter : NO K
3782 13:43:09.589889 CBT Training : PASS
3783 13:43:09.589941 Write leveling : PASS
3784 13:43:09.589992 RX DQS gating : PASS
3785 13:43:09.590044 RX DQ/DQS(RDDQC) : PASS
3786 13:43:09.590095 TX DQ/DQS : PASS
3787 13:43:09.590147 RX DATLAT : PASS
3788 13:43:09.590198 RX DQ/DQS(Engine): PASS
3789 13:43:09.590250 TX OE : NO K
3790 13:43:09.590302 All Pass.
3791 13:43:09.590354
3792 13:43:09.590405 DramC Write-DBI off
3793 13:43:09.590457 PER_BANK_REFRESH: Hybrid Mode
3794 13:43:09.590509 TX_TRACKING: ON
3795 13:43:09.590562 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3796 13:43:09.590615 [FAST_K] Save calibration result to emmc
3797 13:43:09.590667 dramc_set_vcore_voltage set vcore to 650000
3798 13:43:09.590719 Read voltage for 600, 5
3799 13:43:09.590771 Vio18 = 0
3800 13:43:09.590822 Vcore = 650000
3801 13:43:09.590874 Vdram = 0
3802 13:43:09.590926 Vddq = 0
3803 13:43:09.590978 Vmddr = 0
3804 13:43:09.591029 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3805 13:43:09.591082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3806 13:43:09.591135 MEM_TYPE=3, freq_sel=19
3807 13:43:09.591186 sv_algorithm_assistance_LP4_1600
3808 13:43:09.591239 ============ PULL DRAM RESETB DOWN ============
3809 13:43:09.591292 ========== PULL DRAM RESETB DOWN end =========
3810 13:43:09.591344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3811 13:43:09.591396 ===================================
3812 13:43:09.591448 LPDDR4 DRAM CONFIGURATION
3813 13:43:09.591500 ===================================
3814 13:43:09.591552 EX_ROW_EN[0] = 0x0
3815 13:43:09.591603 EX_ROW_EN[1] = 0x0
3816 13:43:09.591655 LP4Y_EN = 0x0
3817 13:43:09.591718 WORK_FSP = 0x0
3818 13:43:09.591770 WL = 0x2
3819 13:43:09.591822 RL = 0x2
3820 13:43:09.591873 BL = 0x2
3821 13:43:09.591925 RPST = 0x0
3822 13:43:09.591976 RD_PRE = 0x0
3823 13:43:09.592028 WR_PRE = 0x1
3824 13:43:09.592080 WR_PST = 0x0
3825 13:43:09.592131 DBI_WR = 0x0
3826 13:43:09.592182 DBI_RD = 0x0
3827 13:43:09.592234 OTF = 0x1
3828 13:43:09.592286 ===================================
3829 13:43:09.592338 ===================================
3830 13:43:09.592405 ANA top config
3831 13:43:09.592458 ===================================
3832 13:43:09.592510 DLL_ASYNC_EN = 0
3833 13:43:09.592562 ALL_SLAVE_EN = 1
3834 13:43:09.592614 NEW_RANK_MODE = 1
3835 13:43:09.592667 DLL_IDLE_MODE = 1
3836 13:43:09.592719 LP45_APHY_COMB_EN = 1
3837 13:43:09.592770 TX_ODT_DIS = 1
3838 13:43:09.592822 NEW_8X_MODE = 1
3839 13:43:09.592874 ===================================
3840 13:43:09.592931 ===================================
3841 13:43:09.592983 data_rate = 1200
3842 13:43:09.593036 CKR = 1
3843 13:43:09.593087 DQ_P2S_RATIO = 8
3844 13:43:09.593139 ===================================
3845 13:43:09.593191 CA_P2S_RATIO = 8
3846 13:43:09.593243 DQ_CA_OPEN = 0
3847 13:43:09.593305 DQ_SEMI_OPEN = 0
3848 13:43:09.593425 CA_SEMI_OPEN = 0
3849 13:43:09.593514 CA_FULL_RATE = 0
3850 13:43:09.593572 DQ_CKDIV4_EN = 1
3851 13:43:09.593624 CA_CKDIV4_EN = 1
3852 13:43:09.593677 CA_PREDIV_EN = 0
3853 13:43:09.593729 PH8_DLY = 0
3854 13:43:09.593781 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3855 13:43:09.593833 DQ_AAMCK_DIV = 4
3856 13:43:09.593885 CA_AAMCK_DIV = 4
3857 13:43:09.593936 CA_ADMCK_DIV = 4
3858 13:43:09.593988 DQ_TRACK_CA_EN = 0
3859 13:43:09.594039 CA_PICK = 600
3860 13:43:09.594091 CA_MCKIO = 600
3861 13:43:09.594143 MCKIO_SEMI = 0
3862 13:43:09.594194 PLL_FREQ = 2288
3863 13:43:09.594246 DQ_UI_PI_RATIO = 32
3864 13:43:09.594302 CA_UI_PI_RATIO = 0
3865 13:43:09.594543 ===================================
3866 13:43:09.594602 ===================================
3867 13:43:09.594655 memory_type:LPDDR4
3868 13:43:09.594706 GP_NUM : 10
3869 13:43:09.594758 SRAM_EN : 1
3870 13:43:09.594810 MD32_EN : 0
3871 13:43:09.594862 ===================================
3872 13:43:09.594914 [ANA_INIT] >>>>>>>>>>>>>>
3873 13:43:09.594967 <<<<<< [CONFIGURE PHASE]: ANA_TX
3874 13:43:09.595019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3875 13:43:09.595071 ===================================
3876 13:43:09.595123 data_rate = 1200,PCW = 0X5800
3877 13:43:09.595175 ===================================
3878 13:43:09.595227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3879 13:43:09.595280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 13:43:09.595332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 13:43:09.595385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3882 13:43:09.595437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3883 13:43:09.595489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3884 13:43:09.595542 [ANA_INIT] flow start
3885 13:43:09.595593 [ANA_INIT] PLL >>>>>>>>
3886 13:43:09.595645 [ANA_INIT] PLL <<<<<<<<
3887 13:43:09.595696 [ANA_INIT] MIDPI >>>>>>>>
3888 13:43:09.595748 [ANA_INIT] MIDPI <<<<<<<<
3889 13:43:09.595799 [ANA_INIT] DLL >>>>>>>>
3890 13:43:09.595850 [ANA_INIT] flow end
3891 13:43:09.595902 ============ LP4 DIFF to SE enter ============
3892 13:43:09.595954 ============ LP4 DIFF to SE exit ============
3893 13:43:09.596006 [ANA_INIT] <<<<<<<<<<<<<
3894 13:43:09.596058 [Flow] Enable top DCM control >>>>>
3895 13:43:09.596110 [Flow] Enable top DCM control <<<<<
3896 13:43:09.596161 Enable DLL master slave shuffle
3897 13:43:09.596213 ==============================================================
3898 13:43:09.596265 Gating Mode config
3899 13:43:09.596347 ==============================================================
3900 13:43:09.596418 Config description:
3901 13:43:09.596472 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3902 13:43:09.596526 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3903 13:43:09.596578 SELPH_MODE 0: By rank 1: By Phase
3904 13:43:09.596631 ==============================================================
3905 13:43:09.596683 GAT_TRACK_EN = 1
3906 13:43:09.596735 RX_GATING_MODE = 2
3907 13:43:09.596787 RX_GATING_TRACK_MODE = 2
3908 13:43:09.596838 SELPH_MODE = 1
3909 13:43:09.596890 PICG_EARLY_EN = 1
3910 13:43:09.596942 VALID_LAT_VALUE = 1
3911 13:43:09.596994 ==============================================================
3912 13:43:09.597046 Enter into Gating configuration >>>>
3913 13:43:09.597098 Exit from Gating configuration <<<<
3914 13:43:09.597150 Enter into DVFS_PRE_config >>>>>
3915 13:43:09.597202 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3916 13:43:09.597255 Exit from DVFS_PRE_config <<<<<
3917 13:43:09.597337 Enter into PICG configuration >>>>
3918 13:43:09.597407 Exit from PICG configuration <<<<
3919 13:43:09.597458 [RX_INPUT] configuration >>>>>
3920 13:43:09.597510 [RX_INPUT] configuration <<<<<
3921 13:43:09.597562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3922 13:43:09.597614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3923 13:43:09.597667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 13:43:09.599439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 13:43:09.605752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 13:43:09.612533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 13:43:09.616080 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3928 13:43:09.619133 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3929 13:43:09.625751 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3930 13:43:09.629234 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3931 13:43:09.632410 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3932 13:43:09.635964 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 13:43:09.639104 ===================================
3934 13:43:09.642572 LPDDR4 DRAM CONFIGURATION
3935 13:43:09.645658 ===================================
3936 13:43:09.649287 EX_ROW_EN[0] = 0x0
3937 13:43:09.649403 EX_ROW_EN[1] = 0x0
3938 13:43:09.652440 LP4Y_EN = 0x0
3939 13:43:09.652521 WORK_FSP = 0x0
3940 13:43:09.655655 WL = 0x2
3941 13:43:09.655736 RL = 0x2
3942 13:43:09.659251 BL = 0x2
3943 13:43:09.659331 RPST = 0x0
3944 13:43:09.662353 RD_PRE = 0x0
3945 13:43:09.662434 WR_PRE = 0x1
3946 13:43:09.666120 WR_PST = 0x0
3947 13:43:09.666201 DBI_WR = 0x0
3948 13:43:09.669024 DBI_RD = 0x0
3949 13:43:09.672384 OTF = 0x1
3950 13:43:09.672465 ===================================
3951 13:43:09.678899 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3952 13:43:09.682645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3953 13:43:09.685684 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 13:43:09.689227 ===================================
3955 13:43:09.692683 LPDDR4 DRAM CONFIGURATION
3956 13:43:09.696031 ===================================
3957 13:43:09.698878 EX_ROW_EN[0] = 0x10
3958 13:43:09.698958 EX_ROW_EN[1] = 0x0
3959 13:43:09.702555 LP4Y_EN = 0x0
3960 13:43:09.702636 WORK_FSP = 0x0
3961 13:43:09.705456 WL = 0x2
3962 13:43:09.705539 RL = 0x2
3963 13:43:09.708804 BL = 0x2
3964 13:43:09.708898 RPST = 0x0
3965 13:43:09.712353 RD_PRE = 0x0
3966 13:43:09.712434 WR_PRE = 0x1
3967 13:43:09.715529 WR_PST = 0x0
3968 13:43:09.715629 DBI_WR = 0x0
3969 13:43:09.719116 DBI_RD = 0x0
3970 13:43:09.719197 OTF = 0x1
3971 13:43:09.722272 ===================================
3972 13:43:09.728928 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3973 13:43:09.733707 nWR fixed to 30
3974 13:43:09.736787 [ModeRegInit_LP4] CH0 RK0
3975 13:43:09.736867 [ModeRegInit_LP4] CH0 RK1
3976 13:43:09.740354 [ModeRegInit_LP4] CH1 RK0
3977 13:43:09.743394 [ModeRegInit_LP4] CH1 RK1
3978 13:43:09.743475 match AC timing 17
3979 13:43:09.750099 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3980 13:43:09.753608 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3981 13:43:09.756703 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3982 13:43:09.763317 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3983 13:43:09.766949 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3984 13:43:09.767033 ==
3985 13:43:09.770013 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 13:43:09.773528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 13:43:09.773612 ==
3988 13:43:09.779942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 13:43:09.786895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3990 13:43:09.790028 [CA 0] Center 36 (6~67) winsize 62
3991 13:43:09.793584 [CA 1] Center 36 (6~67) winsize 62
3992 13:43:09.796716 [CA 2] Center 34 (4~65) winsize 62
3993 13:43:09.800100 [CA 3] Center 34 (3~65) winsize 63
3994 13:43:09.803473 [CA 4] Center 33 (3~64) winsize 62
3995 13:43:09.806789 [CA 5] Center 33 (3~64) winsize 62
3996 13:43:09.806872
3997 13:43:09.810074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3998 13:43:09.810157
3999 13:43:09.813430 [CATrainingPosCal] consider 1 rank data
4000 13:43:09.816872 u2DelayCellTimex100 = 270/100 ps
4001 13:43:09.819945 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 13:43:09.823380 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 13:43:09.826590 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 13:43:09.830091 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4005 13:43:09.833160 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 13:43:09.836682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 13:43:09.836765
4008 13:43:09.843398 CA PerBit enable=1, Macro0, CA PI delay=33
4009 13:43:09.843481
4010 13:43:09.846707 [CBTSetCACLKResult] CA Dly = 33
4011 13:43:09.846790 CS Dly: 4 (0~35)
4012 13:43:09.846857 ==
4013 13:43:09.849788 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 13:43:09.853426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 13:43:09.853510 ==
4016 13:43:09.860134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 13:43:09.866582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4018 13:43:09.870179 [CA 0] Center 36 (6~67) winsize 62
4019 13:43:09.873567 [CA 1] Center 36 (6~67) winsize 62
4020 13:43:09.876631 [CA 2] Center 34 (4~65) winsize 62
4021 13:43:09.880127 [CA 3] Center 34 (4~65) winsize 62
4022 13:43:09.883379 [CA 4] Center 34 (3~65) winsize 63
4023 13:43:09.886806 [CA 5] Center 33 (3~64) winsize 62
4024 13:43:09.886887
4025 13:43:09.890337 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4026 13:43:09.890419
4027 13:43:09.893852 [CATrainingPosCal] consider 2 rank data
4028 13:43:09.897065 u2DelayCellTimex100 = 270/100 ps
4029 13:43:09.900140 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4030 13:43:09.903603 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4031 13:43:09.906873 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 13:43:09.910077 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 13:43:09.913592 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 13:43:09.916936 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 13:43:09.917031
4036 13:43:09.923603 CA PerBit enable=1, Macro0, CA PI delay=33
4037 13:43:09.923696
4038 13:43:09.927323 [CBTSetCACLKResult] CA Dly = 33
4039 13:43:09.927424 CS Dly: 5 (0~37)
4040 13:43:09.927504
4041 13:43:09.930394 ----->DramcWriteLeveling(PI) begin...
4042 13:43:09.930496 ==
4043 13:43:09.933522 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 13:43:09.937138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 13:43:09.937263 ==
4046 13:43:09.940198 Write leveling (Byte 0): 33 => 33
4047 13:43:09.944128 Write leveling (Byte 1): 31 => 31
4048 13:43:09.947242 DramcWriteLeveling(PI) end<-----
4049 13:43:09.947482
4050 13:43:09.947633 ==
4051 13:43:09.950712 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 13:43:09.953739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 13:43:09.956992 ==
4054 13:43:09.957243 [Gating] SW mode calibration
4055 13:43:09.966838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 13:43:09.970412 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4057 13:43:09.973740 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 13:43:09.980351 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 13:43:09.983764 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 13:43:09.987281 0 9 12 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
4061 13:43:09.993688 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
4062 13:43:09.997384 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 13:43:10.000385 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 13:43:10.007368 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 13:43:10.010749 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 13:43:10.013640 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 13:43:10.020873 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4068 13:43:10.024130 0 10 12 | B1->B0 | 2828 3c3c | 0 0 | (1 1) (0 0)
4069 13:43:10.027507 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4070 13:43:10.030786 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 13:43:10.037213 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 13:43:10.040694 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 13:43:10.043823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 13:43:10.050287 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 13:43:10.053942 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 13:43:10.059941 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4077 13:43:10.063509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4078 13:43:10.066995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 13:43:10.070154 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 13:43:10.076879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 13:43:10.079941 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 13:43:10.083567 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 13:43:10.089927 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 13:43:10.093259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 13:43:10.096691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 13:43:10.103723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 13:43:10.106696 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 13:43:10.109655 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 13:43:10.116487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 13:43:10.119676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 13:43:10.123056 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 13:43:10.129660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4093 13:43:10.132918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4094 13:43:10.136542 Total UI for P1: 0, mck2ui 16
4095 13:43:10.139448 best dqsien dly found for B0: ( 0, 13, 12)
4096 13:43:10.142874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 13:43:10.146801 Total UI for P1: 0, mck2ui 16
4098 13:43:10.149790 best dqsien dly found for B1: ( 0, 13, 16)
4099 13:43:10.153060 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4100 13:43:10.159385 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4101 13:43:10.159960
4102 13:43:10.162847 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4103 13:43:10.165929 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4104 13:43:10.169436 [Gating] SW calibration Done
4105 13:43:10.169908 ==
4106 13:43:10.172666 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 13:43:10.175869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 13:43:10.176346 ==
4109 13:43:10.179407 RX Vref Scan: 0
4110 13:43:10.179876
4111 13:43:10.180254 RX Vref 0 -> 0, step: 1
4112 13:43:10.180606
4113 13:43:10.182480 RX Delay -230 -> 252, step: 16
4114 13:43:10.186013 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4115 13:43:10.192524 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4116 13:43:10.195996 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4117 13:43:10.199103 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4118 13:43:10.202494 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4119 13:43:10.206113 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4120 13:43:10.212379 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4121 13:43:10.215953 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4122 13:43:10.218745 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4123 13:43:10.222402 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4124 13:43:10.229086 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4125 13:43:10.231966 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4126 13:43:10.235291 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4127 13:43:10.238484 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4128 13:43:10.245294 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4129 13:43:10.248516 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4130 13:43:10.248984 ==
4131 13:43:10.251926 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 13:43:10.255540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 13:43:10.256018 ==
4134 13:43:10.258557 DQS Delay:
4135 13:43:10.258987 DQS0 = 0, DQS1 = 0
4136 13:43:10.259373 DQM Delay:
4137 13:43:10.262186 DQM0 = 52, DQM1 = 39
4138 13:43:10.262662 DQ Delay:
4139 13:43:10.265217 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4140 13:43:10.268414 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4141 13:43:10.271881 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4142 13:43:10.275005 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4143 13:43:10.275483
4144 13:43:10.275827
4145 13:43:10.276183 ==
4146 13:43:10.278592 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 13:43:10.284961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 13:43:10.285430 ==
4149 13:43:10.285817
4150 13:43:10.286162
4151 13:43:10.286474 TX Vref Scan disable
4152 13:43:10.289096 == TX Byte 0 ==
4153 13:43:10.292083 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4154 13:43:10.298617 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4155 13:43:10.299052 == TX Byte 1 ==
4156 13:43:10.302040 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 13:43:10.308662 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 13:43:10.309092 ==
4159 13:43:10.312274 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 13:43:10.315322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 13:43:10.315799 ==
4162 13:43:10.316176
4163 13:43:10.316498
4164 13:43:10.318900 TX Vref Scan disable
4165 13:43:10.322005 == TX Byte 0 ==
4166 13:43:10.325455 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4167 13:43:10.328582 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4168 13:43:10.332126 == TX Byte 1 ==
4169 13:43:10.335468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 13:43:10.338578 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 13:43:10.339068
4172 13:43:10.339453 [DATLAT]
4173 13:43:10.341975 Freq=600, CH0 RK0
4174 13:43:10.342444
4175 13:43:10.342851 DATLAT Default: 0x9
4176 13:43:10.345189 0, 0xFFFF, sum = 0
4177 13:43:10.345748 1, 0xFFFF, sum = 0
4178 13:43:10.348481 2, 0xFFFF, sum = 0
4179 13:43:10.352235 3, 0xFFFF, sum = 0
4180 13:43:10.352715 4, 0xFFFF, sum = 0
4181 13:43:10.355443 5, 0xFFFF, sum = 0
4182 13:43:10.355922 6, 0xFFFF, sum = 0
4183 13:43:10.358708 7, 0xFFFF, sum = 0
4184 13:43:10.359180 8, 0x0, sum = 1
4185 13:43:10.359535 9, 0x0, sum = 2
4186 13:43:10.361890 10, 0x0, sum = 3
4187 13:43:10.362324 11, 0x0, sum = 4
4188 13:43:10.365428 best_step = 9
4189 13:43:10.365854
4190 13:43:10.366234 ==
4191 13:43:10.368461 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 13:43:10.372122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 13:43:10.372551 ==
4194 13:43:10.375150 RX Vref Scan: 1
4195 13:43:10.375622
4196 13:43:10.375963 RX Vref 0 -> 0, step: 1
4197 13:43:10.376318
4198 13:43:10.378812 RX Delay -179 -> 252, step: 8
4199 13:43:10.379239
4200 13:43:10.381839 Set Vref, RX VrefLevel [Byte0]: 60
4201 13:43:10.385279 [Byte1]: 51
4202 13:43:10.389476
4203 13:43:10.389947 Final RX Vref Byte 0 = 60 to rank0
4204 13:43:10.392512 Final RX Vref Byte 1 = 51 to rank0
4205 13:43:10.396052 Final RX Vref Byte 0 = 60 to rank1
4206 13:43:10.399521 Final RX Vref Byte 1 = 51 to rank1==
4207 13:43:10.402485 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 13:43:10.409384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 13:43:10.409952 ==
4210 13:43:10.410461 DQS Delay:
4211 13:43:10.411023 DQS0 = 0, DQS1 = 0
4212 13:43:10.412421 DQM Delay:
4213 13:43:10.413008 DQM0 = 49, DQM1 = 39
4214 13:43:10.415690 DQ Delay:
4215 13:43:10.419133 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4216 13:43:10.422216 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4217 13:43:10.422509 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =32
4218 13:43:10.429306 DQ12 =48, DQ13 =40, DQ14 =52, DQ15 =44
4219 13:43:10.429512
4220 13:43:10.429662
4221 13:43:10.435884 [DQSOSCAuto] RK0, (LSB)MR18= 0x605a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
4222 13:43:10.438822 CH0 RK0: MR19=808, MR18=605A
4223 13:43:10.445900 CH0_RK0: MR19=0x808, MR18=0x605A, DQSOSC=391, MR23=63, INC=171, DEC=114
4224 13:43:10.446035
4225 13:43:10.448793 ----->DramcWriteLeveling(PI) begin...
4226 13:43:10.448942 ==
4227 13:43:10.452369 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 13:43:10.455623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 13:43:10.455770 ==
4230 13:43:10.459045 Write leveling (Byte 0): 32 => 32
4231 13:43:10.462344 Write leveling (Byte 1): 31 => 31
4232 13:43:10.465551 DramcWriteLeveling(PI) end<-----
4233 13:43:10.465681
4234 13:43:10.465786 ==
4235 13:43:10.468528 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 13:43:10.472170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 13:43:10.472316 ==
4238 13:43:10.475246 [Gating] SW mode calibration
4239 13:43:10.482316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 13:43:10.488724 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 13:43:10.492318 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 13:43:10.495327 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 13:43:10.502239 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 13:43:10.505326 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
4245 13:43:10.508720 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4246 13:43:10.515508 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 13:43:10.519124 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 13:43:10.522138 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 13:43:10.528696 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 13:43:10.532160 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 13:43:10.535745 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 13:43:10.542105 0 10 12 | B1->B0 | 2f2f 2b2b | 1 0 | (0 0) (0 0)
4253 13:43:10.545609 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4254 13:43:10.548716 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 13:43:10.555283 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 13:43:10.558660 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 13:43:10.562057 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 13:43:10.568612 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 13:43:10.572116 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 13:43:10.575737 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4261 13:43:10.581834 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4262 13:43:10.585516 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 13:43:10.588478 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 13:43:10.592041 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 13:43:10.598776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 13:43:10.601812 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 13:43:10.605318 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 13:43:10.611806 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 13:43:10.615336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 13:43:10.618689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 13:43:10.625421 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 13:43:10.628394 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 13:43:10.631837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 13:43:10.638377 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 13:43:10.642098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 13:43:10.645110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4277 13:43:10.651709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4278 13:43:10.651840 Total UI for P1: 0, mck2ui 16
4279 13:43:10.659075 best dqsien dly found for B0: ( 0, 13, 14)
4280 13:43:10.661971 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 13:43:10.665511 Total UI for P1: 0, mck2ui 16
4282 13:43:10.668760 best dqsien dly found for B1: ( 0, 13, 14)
4283 13:43:10.671961 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4284 13:43:10.675760 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4285 13:43:10.676228
4286 13:43:10.678963 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 13:43:10.681920 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4288 13:43:10.685614 [Gating] SW calibration Done
4289 13:43:10.686077 ==
4290 13:43:10.688315 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 13:43:10.691717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 13:43:10.695126 ==
4293 13:43:10.695208 RX Vref Scan: 0
4294 13:43:10.695273
4295 13:43:10.698376 RX Vref 0 -> 0, step: 1
4296 13:43:10.698457
4297 13:43:10.701488 RX Delay -230 -> 252, step: 16
4298 13:43:10.705019 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4299 13:43:10.708121 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4300 13:43:10.711706 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4301 13:43:10.718259 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4302 13:43:10.721732 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4303 13:43:10.724672 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4304 13:43:10.728114 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4305 13:43:10.731673 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4306 13:43:10.738396 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4307 13:43:10.741277 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4308 13:43:10.744852 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4309 13:43:10.747829 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4310 13:43:10.754602 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4311 13:43:10.758123 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4312 13:43:10.761164 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4313 13:43:10.764681 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4314 13:43:10.764774 ==
4315 13:43:10.768178 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 13:43:10.774559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 13:43:10.774649 ==
4318 13:43:10.774720 DQS Delay:
4319 13:43:10.778095 DQS0 = 0, DQS1 = 0
4320 13:43:10.778191 DQM Delay:
4321 13:43:10.778268 DQM0 = 50, DQM1 = 41
4322 13:43:10.781291 DQ Delay:
4323 13:43:10.784669 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4324 13:43:10.788031 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4325 13:43:10.791157 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4326 13:43:10.794601 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4327 13:43:10.794726
4328 13:43:10.794825
4329 13:43:10.794918 ==
4330 13:43:10.798329 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 13:43:10.801414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 13:43:10.801553 ==
4333 13:43:10.801662
4334 13:43:10.801763
4335 13:43:10.804964 TX Vref Scan disable
4336 13:43:10.805101 == TX Byte 0 ==
4337 13:43:10.811445 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4338 13:43:10.814637 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4339 13:43:10.814813 == TX Byte 1 ==
4340 13:43:10.821180 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 13:43:10.824753 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 13:43:10.824999 ==
4343 13:43:10.828204 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 13:43:10.831694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 13:43:10.832032 ==
4346 13:43:10.832348
4347 13:43:10.832637
4348 13:43:10.834849 TX Vref Scan disable
4349 13:43:10.838317 == TX Byte 0 ==
4350 13:43:10.841476 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4351 13:43:10.845132 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4352 13:43:10.848058 == TX Byte 1 ==
4353 13:43:10.851685 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 13:43:10.854744 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 13:43:10.858118
4356 13:43:10.858396 [DATLAT]
4357 13:43:10.858620 Freq=600, CH0 RK1
4358 13:43:10.858831
4359 13:43:10.861499 DATLAT Default: 0x9
4360 13:43:10.861776 0, 0xFFFF, sum = 0
4361 13:43:10.864466 1, 0xFFFF, sum = 0
4362 13:43:10.864679 2, 0xFFFF, sum = 0
4363 13:43:10.868002 3, 0xFFFF, sum = 0
4364 13:43:10.868177 4, 0xFFFF, sum = 0
4365 13:43:10.871437 5, 0xFFFF, sum = 0
4366 13:43:10.874516 6, 0xFFFF, sum = 0
4367 13:43:10.874668 7, 0xFFFF, sum = 0
4368 13:43:10.874786 8, 0x0, sum = 1
4369 13:43:10.877653 9, 0x0, sum = 2
4370 13:43:10.877780 10, 0x0, sum = 3
4371 13:43:10.881045 11, 0x0, sum = 4
4372 13:43:10.881172 best_step = 9
4373 13:43:10.881270
4374 13:43:10.881376 ==
4375 13:43:10.884337 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 13:43:10.891359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 13:43:10.891458 ==
4378 13:43:10.891536 RX Vref Scan: 0
4379 13:43:10.891609
4380 13:43:10.894320 RX Vref 0 -> 0, step: 1
4381 13:43:10.894418
4382 13:43:10.897851 RX Delay -179 -> 252, step: 8
4383 13:43:10.900975 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4384 13:43:10.907971 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4385 13:43:10.911561 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4386 13:43:10.914535 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4387 13:43:10.917950 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4388 13:43:10.921091 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4389 13:43:10.928275 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4390 13:43:10.931084 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4391 13:43:10.934848 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4392 13:43:10.937911 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4393 13:43:10.941508 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4394 13:43:10.948110 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4395 13:43:10.951043 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4396 13:43:10.954767 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4397 13:43:10.958342 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4398 13:43:10.961421 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4399 13:43:10.964889 ==
4400 13:43:10.968162 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 13:43:10.971583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 13:43:10.972049 ==
4403 13:43:10.972415 DQS Delay:
4404 13:43:10.975076 DQS0 = 0, DQS1 = 0
4405 13:43:10.975530 DQM Delay:
4406 13:43:10.978037 DQM0 = 48, DQM1 = 40
4407 13:43:10.978494 DQ Delay:
4408 13:43:10.981756 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4409 13:43:10.984819 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4410 13:43:10.988137 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4411 13:43:10.991554 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4412 13:43:10.991964
4413 13:43:10.992288
4414 13:43:10.997956 [DQSOSCAuto] RK1, (LSB)MR18= 0x6935, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4415 13:43:11.001212 CH0 RK1: MR19=808, MR18=6935
4416 13:43:11.007914 CH0_RK1: MR19=0x808, MR18=0x6935, DQSOSC=390, MR23=63, INC=172, DEC=114
4417 13:43:11.011397 [RxdqsGatingPostProcess] freq 600
4418 13:43:11.014295 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 13:43:11.017734 Pre-setting of DQS Precalculation
4420 13:43:11.024518 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 13:43:11.024646 ==
4422 13:43:11.027577 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 13:43:11.031223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 13:43:11.031345 ==
4425 13:43:11.037892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 13:43:11.044200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 13:43:11.047778 [CA 0] Center 35 (5~66) winsize 62
4428 13:43:11.051009 [CA 1] Center 35 (5~66) winsize 62
4429 13:43:11.054482 [CA 2] Center 34 (3~65) winsize 63
4430 13:43:11.057660 [CA 3] Center 33 (3~64) winsize 62
4431 13:43:11.061123 [CA 4] Center 34 (3~65) winsize 63
4432 13:43:11.061206 [CA 5] Center 33 (3~64) winsize 62
4433 13:43:11.064758
4434 13:43:11.067622 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 13:43:11.067705
4436 13:43:11.071168 [CATrainingPosCal] consider 1 rank data
4437 13:43:11.074508 u2DelayCellTimex100 = 270/100 ps
4438 13:43:11.078036 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 13:43:11.081227 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 13:43:11.085024 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4441 13:43:11.088096 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 13:43:11.091140 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4443 13:43:11.094880 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 13:43:11.095365
4445 13:43:11.098147 CA PerBit enable=1, Macro0, CA PI delay=33
4446 13:43:11.098739
4447 13:43:11.101036 [CBTSetCACLKResult] CA Dly = 33
4448 13:43:11.104914 CS Dly: 4 (0~35)
4449 13:43:11.105491 ==
4450 13:43:11.107995 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 13:43:11.111296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 13:43:11.111880 ==
4453 13:43:11.117990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 13:43:11.124567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 13:43:11.128077 [CA 0] Center 35 (5~66) winsize 62
4456 13:43:11.131175 [CA 1] Center 35 (5~66) winsize 62
4457 13:43:11.134481 [CA 2] Center 34 (4~65) winsize 62
4458 13:43:11.137352 [CA 3] Center 34 (4~65) winsize 62
4459 13:43:11.140619 [CA 4] Center 34 (3~65) winsize 63
4460 13:43:11.144327 [CA 5] Center 33 (3~64) winsize 62
4461 13:43:11.144515
4462 13:43:11.147702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 13:43:11.147864
4464 13:43:11.150834 [CATrainingPosCal] consider 2 rank data
4465 13:43:11.154267 u2DelayCellTimex100 = 270/100 ps
4466 13:43:11.157288 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 13:43:11.160816 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 13:43:11.163910 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 13:43:11.167319 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4470 13:43:11.170874 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4471 13:43:11.174288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 13:43:11.174611
4473 13:43:11.180769 CA PerBit enable=1, Macro0, CA PI delay=33
4474 13:43:11.181007
4475 13:43:11.181196 [CBTSetCACLKResult] CA Dly = 33
4476 13:43:11.184046 CS Dly: 5 (0~37)
4477 13:43:11.184282
4478 13:43:11.187112 ----->DramcWriteLeveling(PI) begin...
4479 13:43:11.187351 ==
4480 13:43:11.190769 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 13:43:11.193876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 13:43:11.194116 ==
4483 13:43:11.197347 Write leveling (Byte 0): 31 => 31
4484 13:43:11.200961 Write leveling (Byte 1): 31 => 31
4485 13:43:11.203971 DramcWriteLeveling(PI) end<-----
4486 13:43:11.204206
4487 13:43:11.204391 ==
4488 13:43:11.207440 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 13:43:11.213749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 13:43:11.213997 ==
4491 13:43:11.214187 [Gating] SW mode calibration
4492 13:43:11.224192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 13:43:11.227439 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 13:43:11.231077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 13:43:11.237556 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 13:43:11.240661 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4497 13:43:11.244165 0 9 12 | B1->B0 | 2828 2626 | 0 0 | (1 0) (1 1)
4498 13:43:11.250902 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 13:43:11.254285 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 13:43:11.257338 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 13:43:11.263975 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 13:43:11.267678 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 13:43:11.270635 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 13:43:11.277411 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 13:43:11.280853 0 10 12 | B1->B0 | 3737 3a3a | 1 0 | (0 0) (0 0)
4506 13:43:11.284341 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 13:43:11.290527 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 13:43:11.294258 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 13:43:11.297282 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 13:43:11.300742 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 13:43:11.307359 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 13:43:11.310837 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4513 13:43:11.314272 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 13:43:11.320980 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 13:43:11.324186 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 13:43:11.327192 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 13:43:11.333790 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 13:43:11.337312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 13:43:11.340192 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 13:43:11.347343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 13:43:11.350311 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 13:43:11.353681 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 13:43:11.360661 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 13:43:11.363754 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 13:43:11.367331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 13:43:11.373733 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 13:43:11.377243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 13:43:11.380356 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4529 13:43:11.387371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4530 13:43:11.390323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 13:43:11.394181 Total UI for P1: 0, mck2ui 16
4532 13:43:11.397133 best dqsien dly found for B0: ( 0, 13, 10)
4533 13:43:11.400700 Total UI for P1: 0, mck2ui 16
4534 13:43:11.403770 best dqsien dly found for B1: ( 0, 13, 14)
4535 13:43:11.407424 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4536 13:43:11.410034 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4537 13:43:11.410114
4538 13:43:11.413545 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4539 13:43:11.416896 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4540 13:43:11.420303 [Gating] SW calibration Done
4541 13:43:11.420396 ==
4542 13:43:11.423500 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 13:43:11.427071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 13:43:11.427160 ==
4545 13:43:11.430112 RX Vref Scan: 0
4546 13:43:11.430198
4547 13:43:11.433732 RX Vref 0 -> 0, step: 1
4548 13:43:11.433818
4549 13:43:11.433886 RX Delay -230 -> 252, step: 16
4550 13:43:11.440494 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4551 13:43:11.443796 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4552 13:43:11.447201 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4553 13:43:11.450282 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4554 13:43:11.456808 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4555 13:43:11.460159 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4556 13:43:11.463642 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4557 13:43:11.466810 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4558 13:43:11.470245 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4559 13:43:11.476757 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4560 13:43:11.480360 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4561 13:43:11.483343 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4562 13:43:11.486717 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4563 13:43:11.493415 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4564 13:43:11.497033 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4565 13:43:11.500192 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4566 13:43:11.500428 ==
4567 13:43:11.503375 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 13:43:11.506921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 13:43:11.510529 ==
4570 13:43:11.510900 DQS Delay:
4571 13:43:11.511194 DQS0 = 0, DQS1 = 0
4572 13:43:11.513687 DQM Delay:
4573 13:43:11.514146 DQM0 = 49, DQM1 = 40
4574 13:43:11.517101 DQ Delay:
4575 13:43:11.517680 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4576 13:43:11.520494 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4577 13:43:11.523823 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4578 13:43:11.526883 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4579 13:43:11.530524
4580 13:43:11.530972
4581 13:43:11.531325 ==
4582 13:43:11.533600 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 13:43:11.537172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 13:43:11.537682 ==
4585 13:43:11.538039
4586 13:43:11.538398
4587 13:43:11.540246 TX Vref Scan disable
4588 13:43:11.540694 == TX Byte 0 ==
4589 13:43:11.547290 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 13:43:11.550072 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 13:43:11.550624 == TX Byte 1 ==
4592 13:43:11.556558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4593 13:43:11.560026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4594 13:43:11.560488 ==
4595 13:43:11.563522 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 13:43:11.566762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 13:43:11.567272 ==
4598 13:43:11.567837
4599 13:43:11.568486
4600 13:43:11.569671 TX Vref Scan disable
4601 13:43:11.573359 == TX Byte 0 ==
4602 13:43:11.576387 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 13:43:11.580093 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 13:43:11.583169 == TX Byte 1 ==
4605 13:43:11.586545 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4606 13:43:11.590095 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4607 13:43:11.593065
4608 13:43:11.593647 [DATLAT]
4609 13:43:11.594013 Freq=600, CH1 RK0
4610 13:43:11.594352
4611 13:43:11.596256 DATLAT Default: 0x9
4612 13:43:11.597000 0, 0xFFFF, sum = 0
4613 13:43:11.599889 1, 0xFFFF, sum = 0
4614 13:43:11.600506 2, 0xFFFF, sum = 0
4615 13:43:11.602977 3, 0xFFFF, sum = 0
4616 13:43:11.603432 4, 0xFFFF, sum = 0
4617 13:43:11.606371 5, 0xFFFF, sum = 0
4618 13:43:11.606929 6, 0xFFFF, sum = 0
4619 13:43:11.609859 7, 0xFFFF, sum = 0
4620 13:43:11.610276 8, 0x0, sum = 1
4621 13:43:11.613009 9, 0x0, sum = 2
4622 13:43:11.613462 10, 0x0, sum = 3
4623 13:43:11.616474 11, 0x0, sum = 4
4624 13:43:11.617004 best_step = 9
4625 13:43:11.617495
4626 13:43:11.617813 ==
4627 13:43:11.619945 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 13:43:11.626273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 13:43:11.626689 ==
4630 13:43:11.627027 RX Vref Scan: 1
4631 13:43:11.627340
4632 13:43:11.629666 RX Vref 0 -> 0, step: 1
4633 13:43:11.630120
4634 13:43:11.633332 RX Delay -179 -> 252, step: 8
4635 13:43:11.633760
4636 13:43:11.636376 Set Vref, RX VrefLevel [Byte0]: 52
4637 13:43:11.639937 [Byte1]: 53
4638 13:43:11.640358
4639 13:43:11.642992 Final RX Vref Byte 0 = 52 to rank0
4640 13:43:11.646519 Final RX Vref Byte 1 = 53 to rank0
4641 13:43:11.649396 Final RX Vref Byte 0 = 52 to rank1
4642 13:43:11.652878 Final RX Vref Byte 1 = 53 to rank1==
4643 13:43:11.656303 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 13:43:11.659680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 13:43:11.660108 ==
4646 13:43:11.662920 DQS Delay:
4647 13:43:11.663377 DQS0 = 0, DQS1 = 0
4648 13:43:11.663886 DQM Delay:
4649 13:43:11.666310 DQM0 = 48, DQM1 = 41
4650 13:43:11.666731 DQ Delay:
4651 13:43:11.669637 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4652 13:43:11.673204 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4653 13:43:11.676220 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4654 13:43:11.679612 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4655 13:43:11.680055
4656 13:43:11.680391
4657 13:43:11.689890 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4658 13:43:11.690317 CH1 RK0: MR19=808, MR18=4A71
4659 13:43:11.696099 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4660 13:43:11.696525
4661 13:43:11.699679 ----->DramcWriteLeveling(PI) begin...
4662 13:43:11.702835 ==
4663 13:43:11.703256 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 13:43:11.709387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 13:43:11.709815 ==
4666 13:43:11.712992 Write leveling (Byte 0): 30 => 30
4667 13:43:11.716054 Write leveling (Byte 1): 29 => 29
4668 13:43:11.719697 DramcWriteLeveling(PI) end<-----
4669 13:43:11.720119
4670 13:43:11.720454 ==
4671 13:43:11.722834 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 13:43:11.726348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 13:43:11.726773 ==
4674 13:43:11.729718 [Gating] SW mode calibration
4675 13:43:11.736446 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4676 13:43:11.739408 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4677 13:43:11.746008 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 13:43:11.749557 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 13:43:11.752996 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4680 13:43:11.759296 0 9 12 | B1->B0 | 2d2d 3030 | 0 0 | (1 0) (1 1)
4681 13:43:11.763050 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 13:43:11.765942 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 13:43:11.772726 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 13:43:11.776055 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 13:43:11.779429 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 13:43:11.785995 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 13:43:11.789120 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4688 13:43:11.792700 0 10 12 | B1->B0 | 3f3f 3535 | 0 1 | (0 0) (1 1)
4689 13:43:11.799255 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4690 13:43:11.802386 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 13:43:11.806066 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 13:43:11.812590 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 13:43:11.815565 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 13:43:11.819221 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 13:43:11.825825 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 13:43:11.829011 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4697 13:43:11.832571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 13:43:11.838908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 13:43:11.842480 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 13:43:11.846315 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 13:43:11.852203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 13:43:11.855743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 13:43:11.859045 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 13:43:11.865573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 13:43:11.869060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 13:43:11.872138 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 13:43:11.875467 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 13:43:11.882115 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 13:43:11.885453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 13:43:11.889071 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 13:43:11.895355 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 13:43:11.898820 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4713 13:43:11.902450 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 13:43:11.905518 Total UI for P1: 0, mck2ui 16
4715 13:43:11.909332 best dqsien dly found for B0: ( 0, 13, 12)
4716 13:43:11.912229 Total UI for P1: 0, mck2ui 16
4717 13:43:11.915695 best dqsien dly found for B1: ( 0, 13, 12)
4718 13:43:11.918808 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4719 13:43:11.922479 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4720 13:43:11.922952
4721 13:43:11.928960 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 13:43:11.932049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 13:43:11.935628 [Gating] SW calibration Done
4724 13:43:11.936101 ==
4725 13:43:11.939040 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 13:43:11.942316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 13:43:11.942930 ==
4728 13:43:11.943395 RX Vref Scan: 0
4729 13:43:11.943751
4730 13:43:11.945772 RX Vref 0 -> 0, step: 1
4731 13:43:11.946244
4732 13:43:11.948941 RX Delay -230 -> 252, step: 16
4733 13:43:11.951964 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4734 13:43:11.955541 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4735 13:43:11.962080 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4736 13:43:11.965670 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4737 13:43:11.968905 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4738 13:43:11.972418 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4739 13:43:11.975458 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4740 13:43:11.982187 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4741 13:43:11.985399 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4742 13:43:11.988582 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4743 13:43:11.991899 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4744 13:43:11.998594 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4745 13:43:12.002179 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4746 13:43:12.005273 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4747 13:43:12.008775 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4748 13:43:12.015543 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4749 13:43:12.016049 ==
4750 13:43:12.018634 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 13:43:12.022349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 13:43:12.022882 ==
4753 13:43:12.023261 DQS Delay:
4754 13:43:12.025444 DQS0 = 0, DQS1 = 0
4755 13:43:12.025916 DQM Delay:
4756 13:43:12.028437 DQM0 = 52, DQM1 = 47
4757 13:43:12.028946 DQ Delay:
4758 13:43:12.032080 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4759 13:43:12.035515 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4760 13:43:12.038506 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4761 13:43:12.042148 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4762 13:43:12.042644
4763 13:43:12.043027
4764 13:43:12.043427 ==
4765 13:43:12.045620 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 13:43:12.049008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 13:43:12.049583 ==
4768 13:43:12.049966
4769 13:43:12.050349
4770 13:43:12.052081 TX Vref Scan disable
4771 13:43:12.055599 == TX Byte 0 ==
4772 13:43:12.058526 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4773 13:43:12.062171 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4774 13:43:12.065230 == TX Byte 1 ==
4775 13:43:12.068702 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4776 13:43:12.071964 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4777 13:43:12.072453 ==
4778 13:43:12.075338 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 13:43:12.082006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 13:43:12.082438 ==
4781 13:43:12.082776
4782 13:43:12.083088
4783 13:43:12.083384 TX Vref Scan disable
4784 13:43:12.086056 == TX Byte 0 ==
4785 13:43:12.089590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4786 13:43:12.093004 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4787 13:43:12.096148 == TX Byte 1 ==
4788 13:43:12.099851 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4789 13:43:12.103010 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4790 13:43:12.106151
4791 13:43:12.106572 [DATLAT]
4792 13:43:12.106908 Freq=600, CH1 RK1
4793 13:43:12.107226
4794 13:43:12.109696 DATLAT Default: 0x9
4795 13:43:12.110118 0, 0xFFFF, sum = 0
4796 13:43:12.113000 1, 0xFFFF, sum = 0
4797 13:43:12.113469 2, 0xFFFF, sum = 0
4798 13:43:12.116049 3, 0xFFFF, sum = 0
4799 13:43:12.116478 4, 0xFFFF, sum = 0
4800 13:43:12.119590 5, 0xFFFF, sum = 0
4801 13:43:12.122709 6, 0xFFFF, sum = 0
4802 13:43:12.123140 7, 0xFFFF, sum = 0
4803 13:43:12.123484 8, 0x0, sum = 1
4804 13:43:12.126238 9, 0x0, sum = 2
4805 13:43:12.126670 10, 0x0, sum = 3
4806 13:43:12.129378 11, 0x0, sum = 4
4807 13:43:12.129808 best_step = 9
4808 13:43:12.130147
4809 13:43:12.130457 ==
4810 13:43:12.132940 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 13:43:12.139524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 13:43:12.139952 ==
4813 13:43:12.140288 RX Vref Scan: 0
4814 13:43:12.140602
4815 13:43:12.142631 RX Vref 0 -> 0, step: 1
4816 13:43:12.143054
4817 13:43:12.146069 RX Delay -163 -> 252, step: 8
4818 13:43:12.149568 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4819 13:43:12.152976 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4820 13:43:12.159407 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4821 13:43:12.162461 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4822 13:43:12.165944 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4823 13:43:12.169496 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4824 13:43:12.172887 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4825 13:43:12.179281 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4826 13:43:12.182447 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4827 13:43:12.186030 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4828 13:43:12.189631 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4829 13:43:12.196216 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4830 13:43:12.199213 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4831 13:43:12.202522 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4832 13:43:12.205762 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4833 13:43:12.209108 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4834 13:43:12.212493 ==
4835 13:43:12.215902 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 13:43:12.219472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 13:43:12.219910 ==
4838 13:43:12.220302 DQS Delay:
4839 13:43:12.222324 DQS0 = 0, DQS1 = 0
4840 13:43:12.222745 DQM Delay:
4841 13:43:12.225937 DQM0 = 49, DQM1 = 44
4842 13:43:12.226359 DQ Delay:
4843 13:43:12.229058 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4844 13:43:12.232564 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4845 13:43:12.235610 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4846 13:43:12.239185 DQ12 =52, DQ13 =48, DQ14 =52, DQ15 =52
4847 13:43:12.239607
4848 13:43:12.239942
4849 13:43:12.245889 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4850 13:43:12.248838 CH1 RK1: MR19=808, MR18=5D24
4851 13:43:12.255377 CH1_RK1: MR19=0x808, MR18=0x5D24, DQSOSC=392, MR23=63, INC=170, DEC=113
4852 13:43:12.258651 [RxdqsGatingPostProcess] freq 600
4853 13:43:12.265757 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4854 13:43:12.266184 Pre-setting of DQS Precalculation
4855 13:43:12.272323 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4856 13:43:12.278893 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4857 13:43:12.285531 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4858 13:43:12.285954
4859 13:43:12.286286
4860 13:43:12.289095 [Calibration Summary] 1200 Mbps
4861 13:43:12.292118 CH 0, Rank 0
4862 13:43:12.292554 SW Impedance : PASS
4863 13:43:12.295671 DUTY Scan : NO K
4864 13:43:12.298662 ZQ Calibration : PASS
4865 13:43:12.299085 Jitter Meter : NO K
4866 13:43:12.302301 CBT Training : PASS
4867 13:43:12.302724 Write leveling : PASS
4868 13:43:12.305400 RX DQS gating : PASS
4869 13:43:12.308976 RX DQ/DQS(RDDQC) : PASS
4870 13:43:12.309421 TX DQ/DQS : PASS
4871 13:43:12.312165 RX DATLAT : PASS
4872 13:43:12.315424 RX DQ/DQS(Engine): PASS
4873 13:43:12.315846 TX OE : NO K
4874 13:43:12.318762 All Pass.
4875 13:43:12.319183
4876 13:43:12.319515 CH 0, Rank 1
4877 13:43:12.321807 SW Impedance : PASS
4878 13:43:12.322232 DUTY Scan : NO K
4879 13:43:12.325374 ZQ Calibration : PASS
4880 13:43:12.328818 Jitter Meter : NO K
4881 13:43:12.329243 CBT Training : PASS
4882 13:43:12.331912 Write leveling : PASS
4883 13:43:12.335432 RX DQS gating : PASS
4884 13:43:12.335856 RX DQ/DQS(RDDQC) : PASS
4885 13:43:12.338952 TX DQ/DQS : PASS
4886 13:43:12.342152 RX DATLAT : PASS
4887 13:43:12.342636 RX DQ/DQS(Engine): PASS
4888 13:43:12.345632 TX OE : NO K
4889 13:43:12.346057 All Pass.
4890 13:43:12.346392
4891 13:43:12.348659 CH 1, Rank 0
4892 13:43:12.349083 SW Impedance : PASS
4893 13:43:12.352187 DUTY Scan : NO K
4894 13:43:12.352607 ZQ Calibration : PASS
4895 13:43:12.355317 Jitter Meter : NO K
4896 13:43:12.358802 CBT Training : PASS
4897 13:43:12.359222 Write leveling : PASS
4898 13:43:12.361758 RX DQS gating : PASS
4899 13:43:12.365106 RX DQ/DQS(RDDQC) : PASS
4900 13:43:12.365575 TX DQ/DQS : PASS
4901 13:43:12.368582 RX DATLAT : PASS
4902 13:43:12.372059 RX DQ/DQS(Engine): PASS
4903 13:43:12.372525 TX OE : NO K
4904 13:43:12.375050 All Pass.
4905 13:43:12.375467
4906 13:43:12.375795 CH 1, Rank 1
4907 13:43:12.378607 SW Impedance : PASS
4908 13:43:12.379032 DUTY Scan : NO K
4909 13:43:12.381681 ZQ Calibration : PASS
4910 13:43:12.385225 Jitter Meter : NO K
4911 13:43:12.385690 CBT Training : PASS
4912 13:43:12.388542 Write leveling : PASS
4913 13:43:12.391646 RX DQS gating : PASS
4914 13:43:12.392081 RX DQ/DQS(RDDQC) : PASS
4915 13:43:12.395244 TX DQ/DQS : PASS
4916 13:43:12.398251 RX DATLAT : PASS
4917 13:43:12.398722 RX DQ/DQS(Engine): PASS
4918 13:43:12.401752 TX OE : NO K
4919 13:43:12.402218 All Pass.
4920 13:43:12.402641
4921 13:43:12.404877 DramC Write-DBI off
4922 13:43:12.408482 PER_BANK_REFRESH: Hybrid Mode
4923 13:43:12.408903 TX_TRACKING: ON
4924 13:43:12.418464 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4925 13:43:12.421726 [FAST_K] Save calibration result to emmc
4926 13:43:12.424993 dramc_set_vcore_voltage set vcore to 662500
4927 13:43:12.425503 Read voltage for 933, 3
4928 13:43:12.428384 Vio18 = 0
4929 13:43:12.428848 Vcore = 662500
4930 13:43:12.429218 Vdram = 0
4931 13:43:12.431908 Vddq = 0
4932 13:43:12.432420 Vmddr = 0
4933 13:43:12.434972 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4934 13:43:12.441602 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4935 13:43:12.445112 MEM_TYPE=3, freq_sel=17
4936 13:43:12.448595 sv_algorithm_assistance_LP4_1600
4937 13:43:12.451773 ============ PULL DRAM RESETB DOWN ============
4938 13:43:12.455277 ========== PULL DRAM RESETB DOWN end =========
4939 13:43:12.461774 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4940 13:43:12.465350 ===================================
4941 13:43:12.465772 LPDDR4 DRAM CONFIGURATION
4942 13:43:12.468222 ===================================
4943 13:43:12.471519 EX_ROW_EN[0] = 0x0
4944 13:43:12.471918 EX_ROW_EN[1] = 0x0
4945 13:43:12.475114 LP4Y_EN = 0x0
4946 13:43:12.475530 WORK_FSP = 0x0
4947 13:43:12.478104 WL = 0x3
4948 13:43:12.481627 RL = 0x3
4949 13:43:12.482090 BL = 0x2
4950 13:43:12.485142 RPST = 0x0
4951 13:43:12.485599 RD_PRE = 0x0
4952 13:43:12.488128 WR_PRE = 0x1
4953 13:43:12.488550 WR_PST = 0x0
4954 13:43:12.491624 DBI_WR = 0x0
4955 13:43:12.492047 DBI_RD = 0x0
4956 13:43:12.494981 OTF = 0x1
4957 13:43:12.498062 ===================================
4958 13:43:12.501616 ===================================
4959 13:43:12.502041 ANA top config
4960 13:43:12.504658 ===================================
4961 13:43:12.508280 DLL_ASYNC_EN = 0
4962 13:43:12.511509 ALL_SLAVE_EN = 1
4963 13:43:12.512078 NEW_RANK_MODE = 1
4964 13:43:12.514990 DLL_IDLE_MODE = 1
4965 13:43:12.518457 LP45_APHY_COMB_EN = 1
4966 13:43:12.521458 TX_ODT_DIS = 1
4967 13:43:12.521931 NEW_8X_MODE = 1
4968 13:43:12.525098 ===================================
4969 13:43:12.527992 ===================================
4970 13:43:12.531274 data_rate = 1866
4971 13:43:12.534762 CKR = 1
4972 13:43:12.538386 DQ_P2S_RATIO = 8
4973 13:43:12.541407 ===================================
4974 13:43:12.544965 CA_P2S_RATIO = 8
4975 13:43:12.547955 DQ_CA_OPEN = 0
4976 13:43:12.548425 DQ_SEMI_OPEN = 0
4977 13:43:12.551451 CA_SEMI_OPEN = 0
4978 13:43:12.554931 CA_FULL_RATE = 0
4979 13:43:12.557965 DQ_CKDIV4_EN = 1
4980 13:43:12.561420 CA_CKDIV4_EN = 1
4981 13:43:12.564585 CA_PREDIV_EN = 0
4982 13:43:12.565059 PH8_DLY = 0
4983 13:43:12.568070 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4984 13:43:12.571547 DQ_AAMCK_DIV = 4
4985 13:43:12.574412 CA_AAMCK_DIV = 4
4986 13:43:12.577918 CA_ADMCK_DIV = 4
4987 13:43:12.581390 DQ_TRACK_CA_EN = 0
4988 13:43:12.584445 CA_PICK = 933
4989 13:43:12.584865 CA_MCKIO = 933
4990 13:43:12.588123 MCKIO_SEMI = 0
4991 13:43:12.591151 PLL_FREQ = 3732
4992 13:43:12.594650 DQ_UI_PI_RATIO = 32
4993 13:43:12.598029 CA_UI_PI_RATIO = 0
4994 13:43:12.600942 ===================================
4995 13:43:12.604643 ===================================
4996 13:43:12.608061 memory_type:LPDDR4
4997 13:43:12.608486 GP_NUM : 10
4998 13:43:12.611150 SRAM_EN : 1
4999 13:43:12.611574 MD32_EN : 0
5000 13:43:12.614766 ===================================
5001 13:43:12.617834 [ANA_INIT] >>>>>>>>>>>>>>
5002 13:43:12.621264 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 13:43:12.624359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 13:43:12.628090 ===================================
5005 13:43:12.631094 data_rate = 1866,PCW = 0X8f00
5006 13:43:12.634439 ===================================
5007 13:43:12.637773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 13:43:12.640959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 13:43:12.648061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 13:43:12.650929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 13:43:12.654397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 13:43:12.660969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 13:43:12.661443 [ANA_INIT] flow start
5014 13:43:12.664514 [ANA_INIT] PLL >>>>>>>>
5015 13:43:12.664941 [ANA_INIT] PLL <<<<<<<<
5016 13:43:12.667628 [ANA_INIT] MIDPI >>>>>>>>
5017 13:43:12.671096 [ANA_INIT] MIDPI <<<<<<<<
5018 13:43:12.674701 [ANA_INIT] DLL >>>>>>>>
5019 13:43:12.675128 [ANA_INIT] flow end
5020 13:43:12.677626 ============ LP4 DIFF to SE enter ============
5021 13:43:12.684231 ============ LP4 DIFF to SE exit ============
5022 13:43:12.684662 [ANA_INIT] <<<<<<<<<<<<<
5023 13:43:12.687685 [Flow] Enable top DCM control >>>>>
5024 13:43:12.691223 [Flow] Enable top DCM control <<<<<
5025 13:43:12.694524 Enable DLL master slave shuffle
5026 13:43:12.700997 ==============================================================
5027 13:43:12.701478 Gating Mode config
5028 13:43:12.707387 ==============================================================
5029 13:43:12.711093 Config description:
5030 13:43:12.721251 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 13:43:12.727362 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 13:43:12.731000 SELPH_MODE 0: By rank 1: By Phase
5033 13:43:12.737480 ==============================================================
5034 13:43:12.740936 GAT_TRACK_EN = 1
5035 13:43:12.741452 RX_GATING_MODE = 2
5036 13:43:12.744309 RX_GATING_TRACK_MODE = 2
5037 13:43:12.747280 SELPH_MODE = 1
5038 13:43:12.750764 PICG_EARLY_EN = 1
5039 13:43:12.754088 VALID_LAT_VALUE = 1
5040 13:43:12.760600 ==============================================================
5041 13:43:12.763691 Enter into Gating configuration >>>>
5042 13:43:12.767111 Exit from Gating configuration <<<<
5043 13:43:12.770149 Enter into DVFS_PRE_config >>>>>
5044 13:43:12.780275 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 13:43:12.783830 Exit from DVFS_PRE_config <<<<<
5046 13:43:12.787157 Enter into PICG configuration >>>>
5047 13:43:12.790108 Exit from PICG configuration <<<<
5048 13:43:12.793575 [RX_INPUT] configuration >>>>>
5049 13:43:12.797162 [RX_INPUT] configuration <<<<<
5050 13:43:12.800217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 13:43:12.806918 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 13:43:12.813914 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 13:43:12.816954 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 13:43:12.823619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 13:43:12.830313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 13:43:12.833442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5057 13:43:12.836950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5058 13:43:12.843545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5059 13:43:12.846851 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5060 13:43:12.849932 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5061 13:43:12.856523 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 13:43:12.860080 ===================================
5063 13:43:12.860169 LPDDR4 DRAM CONFIGURATION
5064 13:43:12.863639 ===================================
5065 13:43:12.866697 EX_ROW_EN[0] = 0x0
5066 13:43:12.870132 EX_ROW_EN[1] = 0x0
5067 13:43:12.870212 LP4Y_EN = 0x0
5068 13:43:12.873135 WORK_FSP = 0x0
5069 13:43:12.873237 WL = 0x3
5070 13:43:12.876684 RL = 0x3
5071 13:43:12.876757 BL = 0x2
5072 13:43:12.880164 RPST = 0x0
5073 13:43:12.880236 RD_PRE = 0x0
5074 13:43:12.883544 WR_PRE = 0x1
5075 13:43:12.883625 WR_PST = 0x0
5076 13:43:12.886666 DBI_WR = 0x0
5077 13:43:12.886738 DBI_RD = 0x0
5078 13:43:12.889961 OTF = 0x1
5079 13:43:12.893255 ===================================
5080 13:43:12.896942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5081 13:43:12.899959 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5082 13:43:12.906570 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 13:43:12.910074 ===================================
5084 13:43:12.910158 LPDDR4 DRAM CONFIGURATION
5085 13:43:12.913549 ===================================
5086 13:43:12.916500 EX_ROW_EN[0] = 0x10
5087 13:43:12.916583 EX_ROW_EN[1] = 0x0
5088 13:43:12.919976 LP4Y_EN = 0x0
5089 13:43:12.920093 WORK_FSP = 0x0
5090 13:43:12.923717 WL = 0x3
5091 13:43:12.923803 RL = 0x3
5092 13:43:12.926720 BL = 0x2
5093 13:43:12.926829 RPST = 0x0
5094 13:43:12.930329 RD_PRE = 0x0
5095 13:43:12.933499 WR_PRE = 0x1
5096 13:43:12.933576 WR_PST = 0x0
5097 13:43:12.936645 DBI_WR = 0x0
5098 13:43:12.936717 DBI_RD = 0x0
5099 13:43:12.939908 OTF = 0x1
5100 13:43:12.943366 ===================================
5101 13:43:12.946994 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5102 13:43:12.952255 nWR fixed to 30
5103 13:43:12.955367 [ModeRegInit_LP4] CH0 RK0
5104 13:43:12.955445 [ModeRegInit_LP4] CH0 RK1
5105 13:43:12.958543 [ModeRegInit_LP4] CH1 RK0
5106 13:43:12.961852 [ModeRegInit_LP4] CH1 RK1
5107 13:43:12.961937 match AC timing 9
5108 13:43:12.968960 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5109 13:43:12.971919 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5110 13:43:12.975579 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5111 13:43:12.982100 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5112 13:43:12.985567 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5113 13:43:12.985641 ==
5114 13:43:12.988622 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 13:43:12.992246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 13:43:12.992320 ==
5117 13:43:12.998645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 13:43:13.005592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 13:43:13.008640 [CA 0] Center 38 (7~69) winsize 63
5120 13:43:13.012178 [CA 1] Center 38 (8~69) winsize 62
5121 13:43:13.015337 [CA 2] Center 35 (5~66) winsize 62
5122 13:43:13.018680 [CA 3] Center 34 (4~65) winsize 62
5123 13:43:13.021974 [CA 4] Center 34 (4~65) winsize 62
5124 13:43:13.025136 [CA 5] Center 33 (3~64) winsize 62
5125 13:43:13.025213
5126 13:43:13.028567 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 13:43:13.028645
5128 13:43:13.032109 [CATrainingPosCal] consider 1 rank data
5129 13:43:13.035258 u2DelayCellTimex100 = 270/100 ps
5130 13:43:13.038417 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5131 13:43:13.041944 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5132 13:43:13.045453 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5133 13:43:13.048604 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 13:43:13.052060 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 13:43:13.055026 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5136 13:43:13.055102
5137 13:43:13.061972 CA PerBit enable=1, Macro0, CA PI delay=33
5138 13:43:13.062055
5139 13:43:13.065012 [CBTSetCACLKResult] CA Dly = 33
5140 13:43:13.065087 CS Dly: 6 (0~37)
5141 13:43:13.065151 ==
5142 13:43:13.068626 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 13:43:13.071572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 13:43:13.071648 ==
5145 13:43:13.078373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 13:43:13.084982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5147 13:43:13.088655 [CA 0] Center 38 (8~69) winsize 62
5148 13:43:13.091555 [CA 1] Center 38 (8~69) winsize 62
5149 13:43:13.095086 [CA 2] Center 36 (6~66) winsize 61
5150 13:43:13.098661 [CA 3] Center 35 (5~66) winsize 62
5151 13:43:13.101956 [CA 4] Center 34 (4~65) winsize 62
5152 13:43:13.105099 [CA 5] Center 34 (4~65) winsize 62
5153 13:43:13.105172
5154 13:43:13.108236 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5155 13:43:13.108308
5156 13:43:13.111735 [CATrainingPosCal] consider 2 rank data
5157 13:43:13.115243 u2DelayCellTimex100 = 270/100 ps
5158 13:43:13.118334 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5159 13:43:13.121523 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5160 13:43:13.124992 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5161 13:43:13.128485 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5162 13:43:13.131536 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5163 13:43:13.138310 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5164 13:43:13.138408
5165 13:43:13.141501 CA PerBit enable=1, Macro0, CA PI delay=34
5166 13:43:13.141576
5167 13:43:13.144976 [CBTSetCACLKResult] CA Dly = 34
5168 13:43:13.145054 CS Dly: 7 (0~39)
5169 13:43:13.145122
5170 13:43:13.148021 ----->DramcWriteLeveling(PI) begin...
5171 13:43:13.148098 ==
5172 13:43:13.151702 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 13:43:13.158111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 13:43:13.158191 ==
5175 13:43:13.161442 Write leveling (Byte 0): 31 => 31
5176 13:43:13.161518 Write leveling (Byte 1): 28 => 28
5177 13:43:13.164687 DramcWriteLeveling(PI) end<-----
5178 13:43:13.164760
5179 13:43:13.164823 ==
5180 13:43:13.167646 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 13:43:13.174487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 13:43:13.174568 ==
5183 13:43:13.177848 [Gating] SW mode calibration
5184 13:43:13.184679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5185 13:43:13.187768 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5186 13:43:13.194362 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5187 13:43:13.197957 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 13:43:13.201033 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 13:43:13.207601 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 13:43:13.211073 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 13:43:13.214605 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 13:43:13.220565 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5193 13:43:13.224202 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
5194 13:43:13.227663 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
5195 13:43:13.234100 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 13:43:13.237123 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 13:43:13.240672 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 13:43:13.247219 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 13:43:13.250701 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 13:43:13.253791 0 15 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5201 13:43:13.260900 0 15 28 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
5202 13:43:13.263875 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5203 13:43:13.267212 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 13:43:13.273855 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 13:43:13.276958 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 13:43:13.280561 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 13:43:13.283577 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 13:43:13.290330 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5209 13:43:13.293589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5210 13:43:13.297063 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5211 13:43:13.303710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 13:43:13.306747 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 13:43:13.310117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 13:43:13.317098 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 13:43:13.320087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 13:43:13.323598 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 13:43:13.330217 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 13:43:13.333545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 13:43:13.336933 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 13:43:13.343707 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 13:43:13.346689 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 13:43:13.350312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 13:43:13.356735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 13:43:13.359740 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 13:43:13.363345 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 13:43:13.366383 Total UI for P1: 0, mck2ui 16
5227 13:43:13.369642 best dqsien dly found for B0: ( 1, 2, 24)
5228 13:43:13.376687 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 13:43:13.376775 Total UI for P1: 0, mck2ui 16
5230 13:43:13.383466 best dqsien dly found for B1: ( 1, 2, 28)
5231 13:43:13.386523 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5232 13:43:13.389551 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5233 13:43:13.389626
5234 13:43:13.392947 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5235 13:43:13.396269 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5236 13:43:13.399500 [Gating] SW calibration Done
5237 13:43:13.399575 ==
5238 13:43:13.402966 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 13:43:13.406060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 13:43:13.406137 ==
5241 13:43:13.409661 RX Vref Scan: 0
5242 13:43:13.409744
5243 13:43:13.409820 RX Vref 0 -> 0, step: 1
5244 13:43:13.409895
5245 13:43:13.412638 RX Delay -80 -> 252, step: 8
5246 13:43:13.419590 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5247 13:43:13.423017 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5248 13:43:13.426087 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5249 13:43:13.429643 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5250 13:43:13.432691 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5251 13:43:13.436054 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5252 13:43:13.442768 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5253 13:43:13.446484 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5254 13:43:13.449587 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5255 13:43:13.452616 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5256 13:43:13.456160 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5257 13:43:13.459748 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5258 13:43:13.466340 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5259 13:43:13.469437 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5260 13:43:13.472719 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5261 13:43:13.476092 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5262 13:43:13.476175 ==
5263 13:43:13.479663 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 13:43:13.482609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 13:43:13.482692 ==
5266 13:43:13.486181 DQS Delay:
5267 13:43:13.486263 DQS0 = 0, DQS1 = 0
5268 13:43:13.489576 DQM Delay:
5269 13:43:13.489659 DQM0 = 105, DQM1 = 90
5270 13:43:13.489725 DQ Delay:
5271 13:43:13.492744 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5272 13:43:13.495783 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5273 13:43:13.499381 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5274 13:43:13.502858 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5275 13:43:13.505822
5276 13:43:13.505904
5277 13:43:13.505969 ==
5278 13:43:13.509149 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 13:43:13.512607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 13:43:13.512694 ==
5281 13:43:13.512764
5282 13:43:13.512826
5283 13:43:13.516033 TX Vref Scan disable
5284 13:43:13.516142 == TX Byte 0 ==
5285 13:43:13.522541 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5286 13:43:13.526159 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5287 13:43:13.526242 == TX Byte 1 ==
5288 13:43:13.532701 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5289 13:43:13.536308 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5290 13:43:13.536394 ==
5291 13:43:13.539168 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 13:43:13.542607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 13:43:13.542690 ==
5294 13:43:13.542756
5295 13:43:13.542816
5296 13:43:13.546038 TX Vref Scan disable
5297 13:43:13.549185 == TX Byte 0 ==
5298 13:43:13.552883 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5299 13:43:13.555854 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5300 13:43:13.559494 == TX Byte 1 ==
5301 13:43:13.562637 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5302 13:43:13.566161 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5303 13:43:13.566244
5304 13:43:13.569208 [DATLAT]
5305 13:43:13.569337 Freq=933, CH0 RK0
5306 13:43:13.569419
5307 13:43:13.572792 DATLAT Default: 0xd
5308 13:43:13.572875 0, 0xFFFF, sum = 0
5309 13:43:13.575763 1, 0xFFFF, sum = 0
5310 13:43:13.575848 2, 0xFFFF, sum = 0
5311 13:43:13.579620 3, 0xFFFF, sum = 0
5312 13:43:13.579731 4, 0xFFFF, sum = 0
5313 13:43:13.582523 5, 0xFFFF, sum = 0
5314 13:43:13.582610 6, 0xFFFF, sum = 0
5315 13:43:13.586044 7, 0xFFFF, sum = 0
5316 13:43:13.586154 8, 0xFFFF, sum = 0
5317 13:43:13.589185 9, 0xFFFF, sum = 0
5318 13:43:13.589317 10, 0x0, sum = 1
5319 13:43:13.592703 11, 0x0, sum = 2
5320 13:43:13.592790 12, 0x0, sum = 3
5321 13:43:13.596237 13, 0x0, sum = 4
5322 13:43:13.596321 best_step = 11
5323 13:43:13.596386
5324 13:43:13.596445 ==
5325 13:43:13.599156 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 13:43:13.602718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 13:43:13.605746 ==
5328 13:43:13.605833 RX Vref Scan: 1
5329 13:43:13.605899
5330 13:43:13.608986 RX Vref 0 -> 0, step: 1
5331 13:43:13.609094
5332 13:43:13.612304 RX Delay -53 -> 252, step: 4
5333 13:43:13.612412
5334 13:43:13.615615 Set Vref, RX VrefLevel [Byte0]: 60
5335 13:43:13.619040 [Byte1]: 51
5336 13:43:13.619123
5337 13:43:13.622418 Final RX Vref Byte 0 = 60 to rank0
5338 13:43:13.625868 Final RX Vref Byte 1 = 51 to rank0
5339 13:43:13.629435 Final RX Vref Byte 0 = 60 to rank1
5340 13:43:13.632512 Final RX Vref Byte 1 = 51 to rank1==
5341 13:43:13.635946 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 13:43:13.639000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 13:43:13.639083 ==
5344 13:43:13.639149 DQS Delay:
5345 13:43:13.642530 DQS0 = 0, DQS1 = 0
5346 13:43:13.642620 DQM Delay:
5347 13:43:13.645629 DQM0 = 107, DQM1 = 92
5348 13:43:13.645711 DQ Delay:
5349 13:43:13.649080 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5350 13:43:13.652729 DQ4 =108, DQ5 =98, DQ6 =114, DQ7 =114
5351 13:43:13.655803 DQ8 =88, DQ9 =80, DQ10 =92, DQ11 =90
5352 13:43:13.659207 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =98
5353 13:43:13.659290
5354 13:43:13.659354
5355 13:43:13.668805 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5356 13:43:13.672398 CH0 RK0: MR19=505, MR18=2723
5357 13:43:13.675531 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5358 13:43:13.679051
5359 13:43:13.682341 ----->DramcWriteLeveling(PI) begin...
5360 13:43:13.682425 ==
5361 13:43:13.685549 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 13:43:13.689089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 13:43:13.689184 ==
5364 13:43:13.692176 Write leveling (Byte 0): 33 => 33
5365 13:43:13.695698 Write leveling (Byte 1): 27 => 27
5366 13:43:13.698743 DramcWriteLeveling(PI) end<-----
5367 13:43:13.698824
5368 13:43:13.698946 ==
5369 13:43:13.702344 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 13:43:13.705448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 13:43:13.705530 ==
5372 13:43:13.709006 [Gating] SW mode calibration
5373 13:43:13.715676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 13:43:13.721955 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 13:43:13.725384 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 13:43:13.728850 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 13:43:13.735383 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 13:43:13.738911 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 13:43:13.742479 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 13:43:13.745494 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 13:43:13.752572 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5382 13:43:13.755603 0 14 28 | B1->B0 | 2f2f 2828 | 0 1 | (0 1) (1 0)
5383 13:43:13.759057 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 13:43:13.765870 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 13:43:13.768932 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 13:43:13.772130 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 13:43:13.779248 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 13:43:13.782272 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 13:43:13.785753 0 15 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5390 13:43:13.792416 0 15 28 | B1->B0 | 3737 4040 | 0 1 | (0 0) (0 0)
5391 13:43:13.795597 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 13:43:13.799070 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 13:43:13.805619 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 13:43:13.809086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 13:43:13.812144 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 13:43:13.818745 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 13:43:13.822383 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 13:43:13.825413 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 13:43:13.832150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 13:43:13.835507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 13:43:13.838930 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 13:43:13.842051 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 13:43:13.849145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 13:43:13.852287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 13:43:13.855630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 13:43:13.862083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 13:43:13.865629 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 13:43:13.868695 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 13:43:13.875279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 13:43:13.878896 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 13:43:13.881920 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 13:43:13.888300 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 13:43:13.891621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5414 13:43:13.894930 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5415 13:43:13.901861 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 13:43:13.905324 Total UI for P1: 0, mck2ui 16
5417 13:43:13.908375 best dqsien dly found for B0: ( 1, 2, 26)
5418 13:43:13.911949 Total UI for P1: 0, mck2ui 16
5419 13:43:13.914991 best dqsien dly found for B1: ( 1, 2, 28)
5420 13:43:13.918172 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5421 13:43:13.921661 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5422 13:43:13.921742
5423 13:43:13.925219 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5424 13:43:13.928417 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5425 13:43:13.931517 [Gating] SW calibration Done
5426 13:43:13.931597 ==
5427 13:43:13.934922 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 13:43:13.938173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 13:43:13.938255 ==
5430 13:43:13.941828 RX Vref Scan: 0
5431 13:43:13.941908
5432 13:43:13.941971 RX Vref 0 -> 0, step: 1
5433 13:43:13.942065
5434 13:43:13.945206 RX Delay -80 -> 252, step: 8
5435 13:43:13.951741 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5436 13:43:13.954853 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5437 13:43:13.958552 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5438 13:43:13.961487 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5439 13:43:13.964944 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5440 13:43:13.968099 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5441 13:43:13.974621 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5442 13:43:13.978198 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5443 13:43:13.981213 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5444 13:43:13.984925 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5445 13:43:13.987897 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5446 13:43:13.991552 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5447 13:43:13.998003 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5448 13:43:14.001530 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5449 13:43:14.005054 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5450 13:43:14.008007 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5451 13:43:14.008088 ==
5452 13:43:14.011654 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 13:43:14.014753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 13:43:14.014834 ==
5455 13:43:14.018260 DQS Delay:
5456 13:43:14.018341 DQS0 = 0, DQS1 = 0
5457 13:43:14.021734 DQM Delay:
5458 13:43:14.021814 DQM0 = 104, DQM1 = 90
5459 13:43:14.021877 DQ Delay:
5460 13:43:14.024779 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5461 13:43:14.028458 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5462 13:43:14.031542 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5463 13:43:14.034676 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5464 13:43:14.038179
5465 13:43:14.038259
5466 13:43:14.038323 ==
5467 13:43:14.041606 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 13:43:14.044965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 13:43:14.045046 ==
5470 13:43:14.045109
5471 13:43:14.045168
5472 13:43:14.047857 TX Vref Scan disable
5473 13:43:14.047940 == TX Byte 0 ==
5474 13:43:14.054818 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5475 13:43:14.057904 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5476 13:43:14.057985 == TX Byte 1 ==
5477 13:43:14.064634 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5478 13:43:14.067950 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5479 13:43:14.068031 ==
5480 13:43:14.071624 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 13:43:14.074575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 13:43:14.074657 ==
5483 13:43:14.074721
5484 13:43:14.074781
5485 13:43:14.078260 TX Vref Scan disable
5486 13:43:14.081429 == TX Byte 0 ==
5487 13:43:14.084581 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5488 13:43:14.088035 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5489 13:43:14.091553 == TX Byte 1 ==
5490 13:43:14.094618 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5491 13:43:14.098167 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5492 13:43:14.098249
5493 13:43:14.101192 [DATLAT]
5494 13:43:14.101326 Freq=933, CH0 RK1
5495 13:43:14.101410
5496 13:43:14.104601 DATLAT Default: 0xb
5497 13:43:14.104682 0, 0xFFFF, sum = 0
5498 13:43:14.108132 1, 0xFFFF, sum = 0
5499 13:43:14.108215 2, 0xFFFF, sum = 0
5500 13:43:14.111217 3, 0xFFFF, sum = 0
5501 13:43:14.111300 4, 0xFFFF, sum = 0
5502 13:43:14.114754 5, 0xFFFF, sum = 0
5503 13:43:14.114836 6, 0xFFFF, sum = 0
5504 13:43:14.117902 7, 0xFFFF, sum = 0
5505 13:43:14.117985 8, 0xFFFF, sum = 0
5506 13:43:14.121465 9, 0xFFFF, sum = 0
5507 13:43:14.121548 10, 0x0, sum = 1
5508 13:43:14.124492 11, 0x0, sum = 2
5509 13:43:14.124574 12, 0x0, sum = 3
5510 13:43:14.128049 13, 0x0, sum = 4
5511 13:43:14.128137 best_step = 11
5512 13:43:14.128202
5513 13:43:14.128262 ==
5514 13:43:14.131057 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 13:43:14.138125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 13:43:14.138209 ==
5517 13:43:14.138273 RX Vref Scan: 0
5518 13:43:14.138333
5519 13:43:14.141106 RX Vref 0 -> 0, step: 1
5520 13:43:14.141188
5521 13:43:14.144679 RX Delay -53 -> 252, step: 4
5522 13:43:14.147777 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5523 13:43:14.151146 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5524 13:43:14.158304 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5525 13:43:14.161486 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5526 13:43:14.164490 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5527 13:43:14.167994 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5528 13:43:14.170825 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5529 13:43:14.177854 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5530 13:43:14.181314 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5531 13:43:14.184421 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5532 13:43:14.187625 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5533 13:43:14.191125 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5534 13:43:14.194565 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5535 13:43:14.201253 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5536 13:43:14.204659 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5537 13:43:14.207622 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5538 13:43:14.207706 ==
5539 13:43:14.210919 Dram Type= 6, Freq= 0, CH_0, rank 1
5540 13:43:14.214538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 13:43:14.214622 ==
5542 13:43:14.217558 DQS Delay:
5543 13:43:14.217641 DQS0 = 0, DQS1 = 0
5544 13:43:14.221003 DQM Delay:
5545 13:43:14.221119 DQM0 = 104, DQM1 = 92
5546 13:43:14.221186 DQ Delay:
5547 13:43:14.224599 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5548 13:43:14.227544 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5549 13:43:14.231130 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5550 13:43:14.237491 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5551 13:43:14.237600
5552 13:43:14.237693
5553 13:43:14.244035 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5554 13:43:14.247754 CH0 RK1: MR19=505, MR18=2B0C
5555 13:43:14.254220 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5556 13:43:14.258258 [RxdqsGatingPostProcess] freq 933
5557 13:43:14.261100 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5558 13:43:14.264465 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 13:43:14.267684 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 13:43:14.271013 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 13:43:14.274106 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 13:43:14.277712 best DQS0 dly(2T, 0.5T) = (0, 10)
5563 13:43:14.280679 best DQS1 dly(2T, 0.5T) = (0, 10)
5564 13:43:14.284254 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5565 13:43:14.287266 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5566 13:43:14.290840 Pre-setting of DQS Precalculation
5567 13:43:14.293803 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5568 13:43:14.293887 ==
5569 13:43:14.297259 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 13:43:14.303795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 13:43:14.303879 ==
5572 13:43:14.307320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5573 13:43:14.313629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5574 13:43:14.317062 [CA 0] Center 37 (7~68) winsize 62
5575 13:43:14.320524 [CA 1] Center 37 (7~68) winsize 62
5576 13:43:14.323677 [CA 2] Center 35 (5~66) winsize 62
5577 13:43:14.327113 [CA 3] Center 35 (5~65) winsize 61
5578 13:43:14.330296 [CA 4] Center 35 (5~66) winsize 62
5579 13:43:14.333803 [CA 5] Center 35 (5~65) winsize 61
5580 13:43:14.333913
5581 13:43:14.337015 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5582 13:43:14.337126
5583 13:43:14.340184 [CATrainingPosCal] consider 1 rank data
5584 13:43:14.343738 u2DelayCellTimex100 = 270/100 ps
5585 13:43:14.347181 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5586 13:43:14.350287 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5587 13:43:14.356935 CA2 delay=35 (5~66),Diff = 0 PI (0 cell)
5588 13:43:14.360591 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5589 13:43:14.363454 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5590 13:43:14.367177 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5591 13:43:14.367261
5592 13:43:14.370092 CA PerBit enable=1, Macro0, CA PI delay=35
5593 13:43:14.370176
5594 13:43:14.373438 [CBTSetCACLKResult] CA Dly = 35
5595 13:43:14.373521 CS Dly: 7 (0~38)
5596 13:43:14.376702 ==
5597 13:43:14.380223 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 13:43:14.383483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 13:43:14.383567 ==
5600 13:43:14.386922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 13:43:14.393220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 13:43:14.397234 [CA 0] Center 38 (7~69) winsize 63
5603 13:43:14.400266 [CA 1] Center 38 (8~69) winsize 62
5604 13:43:14.403738 [CA 2] Center 35 (5~66) winsize 62
5605 13:43:14.407214 [CA 3] Center 35 (5~65) winsize 61
5606 13:43:14.410285 [CA 4] Center 35 (5~66) winsize 62
5607 13:43:14.413649 [CA 5] Center 35 (5~65) winsize 61
5608 13:43:14.413732
5609 13:43:14.416981 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 13:43:14.417065
5611 13:43:14.420167 [CATrainingPosCal] consider 2 rank data
5612 13:43:14.423702 u2DelayCellTimex100 = 270/100 ps
5613 13:43:14.427132 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5614 13:43:14.433354 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5615 13:43:14.436871 CA2 delay=35 (5~66),Diff = 0 PI (0 cell)
5616 13:43:14.439989 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5617 13:43:14.443595 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5618 13:43:14.446616 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5619 13:43:14.446694
5620 13:43:14.450118 CA PerBit enable=1, Macro0, CA PI delay=35
5621 13:43:14.450196
5622 13:43:14.453714 [CBTSetCACLKResult] CA Dly = 35
5623 13:43:14.453786 CS Dly: 7 (0~39)
5624 13:43:14.453848
5625 13:43:14.456822 ----->DramcWriteLeveling(PI) begin...
5626 13:43:14.459957 ==
5627 13:43:14.463381 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 13:43:14.466907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 13:43:14.467014 ==
5630 13:43:14.470162 Write leveling (Byte 0): 26 => 26
5631 13:43:14.473794 Write leveling (Byte 1): 31 => 31
5632 13:43:14.476759 DramcWriteLeveling(PI) end<-----
5633 13:43:14.476856
5634 13:43:14.476947 ==
5635 13:43:14.480078 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:43:14.483541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:43:14.483647 ==
5638 13:43:14.486874 [Gating] SW mode calibration
5639 13:43:14.493243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5640 13:43:14.500182 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5641 13:43:14.503189 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 13:43:14.506690 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 13:43:14.513301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 13:43:14.516345 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 13:43:14.519871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 13:43:14.523276 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5647 13:43:14.530087 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
5648 13:43:14.533076 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5649 13:43:14.536574 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 13:43:14.543293 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 13:43:14.546888 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 13:43:14.549894 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 13:43:14.556564 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 13:43:14.560115 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 13:43:14.563114 0 15 24 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
5656 13:43:14.569710 0 15 28 | B1->B0 | 4040 4040 | 0 0 | (0 0) (0 0)
5657 13:43:14.573240 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 13:43:14.576426 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 13:43:14.582935 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 13:43:14.586468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 13:43:14.589843 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 13:43:14.596384 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5663 13:43:14.599591 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5664 13:43:14.602939 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 13:43:14.609917 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 13:43:14.613055 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 13:43:14.616515 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 13:43:14.623187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 13:43:14.626219 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 13:43:14.629741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 13:43:14.636249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 13:43:14.639746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 13:43:14.643328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 13:43:14.646412 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 13:43:14.652876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 13:43:14.656137 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 13:43:14.659719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 13:43:14.666346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 13:43:14.669790 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5680 13:43:14.672868 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 13:43:14.676434 Total UI for P1: 0, mck2ui 16
5682 13:43:14.679464 best dqsien dly found for B0: ( 1, 2, 24)
5683 13:43:14.682958 Total UI for P1: 0, mck2ui 16
5684 13:43:14.686020 best dqsien dly found for B1: ( 1, 2, 26)
5685 13:43:14.689611 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5686 13:43:14.692596 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5687 13:43:14.692693
5688 13:43:14.699728 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5689 13:43:14.702670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5690 13:43:14.706059 [Gating] SW calibration Done
5691 13:43:14.706141 ==
5692 13:43:14.709422 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 13:43:14.712699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 13:43:14.712808 ==
5695 13:43:14.712903 RX Vref Scan: 0
5696 13:43:14.712992
5697 13:43:14.715874 RX Vref 0 -> 0, step: 1
5698 13:43:14.716056
5699 13:43:14.719251 RX Delay -80 -> 252, step: 8
5700 13:43:14.722820 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5701 13:43:14.726179 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5702 13:43:14.732627 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5703 13:43:14.736003 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5704 13:43:14.739590 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5705 13:43:14.743042 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5706 13:43:14.746162 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5707 13:43:14.749724 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5708 13:43:14.752810 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5709 13:43:14.759340 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5710 13:43:14.762959 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5711 13:43:14.765974 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5712 13:43:14.769580 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5713 13:43:14.772477 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5714 13:43:14.779114 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5715 13:43:14.782699 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5716 13:43:14.782771 ==
5717 13:43:14.786082 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 13:43:14.789217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 13:43:14.789338 ==
5720 13:43:14.789429 DQS Delay:
5721 13:43:14.792878 DQS0 = 0, DQS1 = 0
5722 13:43:14.792974 DQM Delay:
5723 13:43:14.795904 DQM0 = 102, DQM1 = 95
5724 13:43:14.795999 DQ Delay:
5725 13:43:14.799218 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5726 13:43:14.802804 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5727 13:43:14.805903 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5728 13:43:14.808877 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =99
5729 13:43:14.808950
5730 13:43:14.809030
5731 13:43:14.809091 ==
5732 13:43:14.812249 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 13:43:14.818748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 13:43:14.818823 ==
5735 13:43:14.818886
5736 13:43:14.818943
5737 13:43:14.819020 TX Vref Scan disable
5738 13:43:14.822880 == TX Byte 0 ==
5739 13:43:14.826067 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 13:43:14.832775 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 13:43:14.832885 == TX Byte 1 ==
5742 13:43:14.836266 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5743 13:43:14.839182 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5744 13:43:14.842519 ==
5745 13:43:14.846195 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 13:43:14.849250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 13:43:14.849376 ==
5748 13:43:14.849440
5749 13:43:14.849512
5750 13:43:14.852752 TX Vref Scan disable
5751 13:43:14.852849 == TX Byte 0 ==
5752 13:43:14.859287 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5753 13:43:14.862422 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5754 13:43:14.862495 == TX Byte 1 ==
5755 13:43:14.869025 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5756 13:43:14.872640 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5757 13:43:14.872710
5758 13:43:14.872772 [DATLAT]
5759 13:43:14.876084 Freq=933, CH1 RK0
5760 13:43:14.876188
5761 13:43:14.876300 DATLAT Default: 0xd
5762 13:43:14.879099 0, 0xFFFF, sum = 0
5763 13:43:14.879175 1, 0xFFFF, sum = 0
5764 13:43:14.882180 2, 0xFFFF, sum = 0
5765 13:43:14.882248 3, 0xFFFF, sum = 0
5766 13:43:14.885724 4, 0xFFFF, sum = 0
5767 13:43:14.885792 5, 0xFFFF, sum = 0
5768 13:43:14.889250 6, 0xFFFF, sum = 0
5769 13:43:14.892348 7, 0xFFFF, sum = 0
5770 13:43:14.892452 8, 0xFFFF, sum = 0
5771 13:43:14.895497 9, 0xFFFF, sum = 0
5772 13:43:14.895594 10, 0x0, sum = 1
5773 13:43:14.899004 11, 0x0, sum = 2
5774 13:43:14.899101 12, 0x0, sum = 3
5775 13:43:14.899191 13, 0x0, sum = 4
5776 13:43:14.902455 best_step = 11
5777 13:43:14.902523
5778 13:43:14.902582 ==
5779 13:43:14.905566 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 13:43:14.908752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 13:43:14.908848 ==
5782 13:43:14.912128 RX Vref Scan: 1
5783 13:43:14.912225
5784 13:43:14.915553 RX Vref 0 -> 0, step: 1
5785 13:43:14.915647
5786 13:43:14.915737 RX Delay -53 -> 252, step: 4
5787 13:43:14.915829
5788 13:43:14.918891 Set Vref, RX VrefLevel [Byte0]: 52
5789 13:43:14.921912 [Byte1]: 53
5790 13:43:14.926626
5791 13:43:14.926703 Final RX Vref Byte 0 = 52 to rank0
5792 13:43:14.930008 Final RX Vref Byte 1 = 53 to rank0
5793 13:43:14.933222 Final RX Vref Byte 0 = 52 to rank1
5794 13:43:14.936627 Final RX Vref Byte 1 = 53 to rank1==
5795 13:43:14.939700 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 13:43:14.946510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 13:43:14.946610 ==
5798 13:43:14.946707 DQS Delay:
5799 13:43:14.946795 DQS0 = 0, DQS1 = 0
5800 13:43:14.950036 DQM Delay:
5801 13:43:14.950109 DQM0 = 104, DQM1 = 97
5802 13:43:14.953136 DQ Delay:
5803 13:43:14.956660 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5804 13:43:14.960079 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5805 13:43:14.963037 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5806 13:43:14.966672 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5807 13:43:14.966758
5808 13:43:14.966842
5809 13:43:14.973509 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5810 13:43:14.976566 CH1 RK0: MR19=505, MR18=1A32
5811 13:43:14.983392 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5812 13:43:14.983480
5813 13:43:14.986519 ----->DramcWriteLeveling(PI) begin...
5814 13:43:14.986606 ==
5815 13:43:14.990076 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 13:43:14.993161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 13:43:14.993248 ==
5818 13:43:14.996320 Write leveling (Byte 0): 27 => 27
5819 13:43:14.999887 Write leveling (Byte 1): 29 => 29
5820 13:43:15.002980 DramcWriteLeveling(PI) end<-----
5821 13:43:15.003065
5822 13:43:15.003151 ==
5823 13:43:15.006345 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 13:43:15.012962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 13:43:15.013063 ==
5826 13:43:15.013150 [Gating] SW mode calibration
5827 13:43:15.022843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5828 13:43:15.026375 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5829 13:43:15.029879 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 13:43:15.036437 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 13:43:15.039838 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 13:43:15.043122 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 13:43:15.049567 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 13:43:15.052923 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 13:43:15.056482 0 14 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (1 0)
5836 13:43:15.063083 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5837 13:43:15.066172 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 13:43:15.069735 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 13:43:15.076369 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 13:43:15.079406 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 13:43:15.083059 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 13:43:15.089622 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 13:43:15.092665 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5844 13:43:15.096369 0 15 28 | B1->B0 | 4141 3838 | 0 0 | (0 0) (0 0)
5845 13:43:15.103006 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5846 13:43:15.106118 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 13:43:15.109523 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 13:43:15.113024 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 13:43:15.119603 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 13:43:15.123033 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 13:43:15.126410 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5852 13:43:15.132840 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5853 13:43:15.136316 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 13:43:15.139384 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 13:43:15.146375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 13:43:15.149763 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 13:43:15.152784 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 13:43:15.159640 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 13:43:15.162711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 13:43:15.166209 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 13:43:15.172543 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 13:43:15.176163 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 13:43:15.179158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 13:43:15.185770 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 13:43:15.189445 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 13:43:15.192914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 13:43:15.199449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5868 13:43:15.202904 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5869 13:43:15.206028 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 13:43:15.209592 Total UI for P1: 0, mck2ui 16
5871 13:43:15.212589 best dqsien dly found for B0: ( 1, 2, 26)
5872 13:43:15.216001 Total UI for P1: 0, mck2ui 16
5873 13:43:15.219490 best dqsien dly found for B1: ( 1, 2, 28)
5874 13:43:15.222491 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5875 13:43:15.225946 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5876 13:43:15.226029
5877 13:43:15.229437 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5878 13:43:15.235769 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5879 13:43:15.235856 [Gating] SW calibration Done
5880 13:43:15.235924 ==
5881 13:43:15.239296 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 13:43:15.245864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 13:43:15.245941 ==
5884 13:43:15.246005 RX Vref Scan: 0
5885 13:43:15.246064
5886 13:43:15.248993 RX Vref 0 -> 0, step: 1
5887 13:43:15.249066
5888 13:43:15.252518 RX Delay -80 -> 252, step: 8
5889 13:43:15.255901 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5890 13:43:15.259224 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5891 13:43:15.262628 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5892 13:43:15.266116 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5893 13:43:15.272282 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5894 13:43:15.275924 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5895 13:43:15.279134 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5896 13:43:15.282478 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5897 13:43:15.285543 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5898 13:43:15.292693 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5899 13:43:15.295514 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5900 13:43:15.299090 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5901 13:43:15.302245 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5902 13:43:15.305828 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5903 13:43:15.308950 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5904 13:43:15.315691 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5905 13:43:15.315773 ==
5906 13:43:15.318979 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 13:43:15.322420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 13:43:15.322503 ==
5909 13:43:15.322568 DQS Delay:
5910 13:43:15.325418 DQS0 = 0, DQS1 = 0
5911 13:43:15.325502 DQM Delay:
5912 13:43:15.328747 DQM0 = 101, DQM1 = 95
5913 13:43:15.328906 DQ Delay:
5914 13:43:15.332258 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5915 13:43:15.335813 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5916 13:43:15.339045 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =91
5917 13:43:15.342536 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5918 13:43:15.342618
5919 13:43:15.342684
5920 13:43:15.342744 ==
5921 13:43:15.345622 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 13:43:15.352039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 13:43:15.352122 ==
5924 13:43:15.352188
5925 13:43:15.352247
5926 13:43:15.352305 TX Vref Scan disable
5927 13:43:15.355616 == TX Byte 0 ==
5928 13:43:15.359105 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5929 13:43:15.362357 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5930 13:43:15.365705 == TX Byte 1 ==
5931 13:43:15.368999 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5932 13:43:15.372401 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5933 13:43:15.375495 ==
5934 13:43:15.379095 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 13:43:15.382262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 13:43:15.382345 ==
5937 13:43:15.382411
5938 13:43:15.382470
5939 13:43:15.385712 TX Vref Scan disable
5940 13:43:15.385827 == TX Byte 0 ==
5941 13:43:15.392094 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5942 13:43:15.395598 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5943 13:43:15.395681 == TX Byte 1 ==
5944 13:43:15.401966 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 13:43:15.405534 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 13:43:15.405617
5947 13:43:15.405682 [DATLAT]
5948 13:43:15.408602 Freq=933, CH1 RK1
5949 13:43:15.408684
5950 13:43:15.408807 DATLAT Default: 0xb
5951 13:43:15.412227 0, 0xFFFF, sum = 0
5952 13:43:15.412311 1, 0xFFFF, sum = 0
5953 13:43:15.415292 2, 0xFFFF, sum = 0
5954 13:43:15.415376 3, 0xFFFF, sum = 0
5955 13:43:15.418425 4, 0xFFFF, sum = 0
5956 13:43:15.418509 5, 0xFFFF, sum = 0
5957 13:43:15.421954 6, 0xFFFF, sum = 0
5958 13:43:15.425214 7, 0xFFFF, sum = 0
5959 13:43:15.425319 8, 0xFFFF, sum = 0
5960 13:43:15.428623 9, 0xFFFF, sum = 0
5961 13:43:15.428707 10, 0x0, sum = 1
5962 13:43:15.431627 11, 0x0, sum = 2
5963 13:43:15.431711 12, 0x0, sum = 3
5964 13:43:15.431777 13, 0x0, sum = 4
5965 13:43:15.435128 best_step = 11
5966 13:43:15.435211
5967 13:43:15.435276 ==
5968 13:43:15.438508 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 13:43:15.441549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 13:43:15.441632 ==
5971 13:43:15.444989 RX Vref Scan: 0
5972 13:43:15.445072
5973 13:43:15.445137 RX Vref 0 -> 0, step: 1
5974 13:43:15.448637
5975 13:43:15.448719 RX Delay -61 -> 252, step: 4
5976 13:43:15.455714 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5977 13:43:15.459271 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5978 13:43:15.462273 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5979 13:43:15.465739 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5980 13:43:15.469028 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5981 13:43:15.475766 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5982 13:43:15.479085 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5983 13:43:15.482275 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5984 13:43:15.485761 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5985 13:43:15.489173 iDelay=199, Bit 9, Center 86 (-1 ~ 174) 176
5986 13:43:15.495771 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5987 13:43:15.498843 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5988 13:43:15.502410 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5989 13:43:15.505507 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5990 13:43:15.509039 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5991 13:43:15.515667 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5992 13:43:15.515751 ==
5993 13:43:15.519204 Dram Type= 6, Freq= 0, CH_1, rank 1
5994 13:43:15.522334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5995 13:43:15.522446 ==
5996 13:43:15.522556 DQS Delay:
5997 13:43:15.525703 DQS0 = 0, DQS1 = 0
5998 13:43:15.525786 DQM Delay:
5999 13:43:15.529007 DQM0 = 104, DQM1 = 96
6000 13:43:15.529091 DQ Delay:
6001 13:43:15.532362 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
6002 13:43:15.535620 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
6003 13:43:15.538883 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90
6004 13:43:15.542417 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
6005 13:43:15.542502
6006 13:43:15.542567
6007 13:43:15.552196 [DQSOSCAuto] RK1, (LSB)MR18= 0x2602, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
6008 13:43:15.555281 CH1 RK1: MR19=505, MR18=2602
6009 13:43:15.558828 CH1_RK1: MR19=0x505, MR18=0x2602, DQSOSC=409, MR23=63, INC=64, DEC=43
6010 13:43:15.561927 [RxdqsGatingPostProcess] freq 933
6011 13:43:15.568732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6012 13:43:15.572188 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 13:43:15.575483 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 13:43:15.578732 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 13:43:15.581975 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 13:43:15.585375 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 13:43:15.588900 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 13:43:15.591981 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 13:43:15.592065 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 13:43:15.595663 Pre-setting of DQS Precalculation
6021 13:43:15.601806 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6022 13:43:15.608478 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6023 13:43:15.615560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6024 13:43:15.615645
6025 13:43:15.615710
6026 13:43:15.618491 [Calibration Summary] 1866 Mbps
6027 13:43:15.621969 CH 0, Rank 0
6028 13:43:15.622053 SW Impedance : PASS
6029 13:43:15.625030 DUTY Scan : NO K
6030 13:43:15.628460 ZQ Calibration : PASS
6031 13:43:15.628545 Jitter Meter : NO K
6032 13:43:15.632053 CBT Training : PASS
6033 13:43:15.632137 Write leveling : PASS
6034 13:43:15.634998 RX DQS gating : PASS
6035 13:43:15.638492 RX DQ/DQS(RDDQC) : PASS
6036 13:43:15.638575 TX DQ/DQS : PASS
6037 13:43:15.641948 RX DATLAT : PASS
6038 13:43:15.644981 RX DQ/DQS(Engine): PASS
6039 13:43:15.645065 TX OE : NO K
6040 13:43:15.648667 All Pass.
6041 13:43:15.648751
6042 13:43:15.648817 CH 0, Rank 1
6043 13:43:15.652045 SW Impedance : PASS
6044 13:43:15.652129 DUTY Scan : NO K
6045 13:43:15.655058 ZQ Calibration : PASS
6046 13:43:15.658629 Jitter Meter : NO K
6047 13:43:15.658713 CBT Training : PASS
6048 13:43:15.661675 Write leveling : PASS
6049 13:43:15.665162 RX DQS gating : PASS
6050 13:43:15.665245 RX DQ/DQS(RDDQC) : PASS
6051 13:43:15.668191 TX DQ/DQS : PASS
6052 13:43:15.671756 RX DATLAT : PASS
6053 13:43:15.671839 RX DQ/DQS(Engine): PASS
6054 13:43:15.674920 TX OE : NO K
6055 13:43:15.675003 All Pass.
6056 13:43:15.675069
6057 13:43:15.678396 CH 1, Rank 0
6058 13:43:15.678479 SW Impedance : PASS
6059 13:43:15.681848 DUTY Scan : NO K
6060 13:43:15.681932 ZQ Calibration : PASS
6061 13:43:15.685177 Jitter Meter : NO K
6062 13:43:15.688337 CBT Training : PASS
6063 13:43:15.688420 Write leveling : PASS
6064 13:43:15.691536 RX DQS gating : PASS
6065 13:43:15.694952 RX DQ/DQS(RDDQC) : PASS
6066 13:43:15.695036 TX DQ/DQS : PASS
6067 13:43:15.698547 RX DATLAT : PASS
6068 13:43:15.701585 RX DQ/DQS(Engine): PASS
6069 13:43:15.701668 TX OE : NO K
6070 13:43:15.704985 All Pass.
6071 13:43:15.705068
6072 13:43:15.705134 CH 1, Rank 1
6073 13:43:15.708618 SW Impedance : PASS
6074 13:43:15.708702 DUTY Scan : NO K
6075 13:43:15.711602 ZQ Calibration : PASS
6076 13:43:15.715053 Jitter Meter : NO K
6077 13:43:15.715137 CBT Training : PASS
6078 13:43:15.718654 Write leveling : PASS
6079 13:43:15.718737 RX DQS gating : PASS
6080 13:43:15.721731 RX DQ/DQS(RDDQC) : PASS
6081 13:43:15.725263 TX DQ/DQS : PASS
6082 13:43:15.725403 RX DATLAT : PASS
6083 13:43:15.728412 RX DQ/DQS(Engine): PASS
6084 13:43:15.732022 TX OE : NO K
6085 13:43:15.732129 All Pass.
6086 13:43:15.732222
6087 13:43:15.735018 DramC Write-DBI off
6088 13:43:15.735123 PER_BANK_REFRESH: Hybrid Mode
6089 13:43:15.738547 TX_TRACKING: ON
6090 13:43:15.748253 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6091 13:43:15.751444 [FAST_K] Save calibration result to emmc
6092 13:43:15.754933 dramc_set_vcore_voltage set vcore to 650000
6093 13:43:15.755035 Read voltage for 400, 6
6094 13:43:15.758401 Vio18 = 0
6095 13:43:15.758476 Vcore = 650000
6096 13:43:15.758540 Vdram = 0
6097 13:43:15.761881 Vddq = 0
6098 13:43:15.761954 Vmddr = 0
6099 13:43:15.764739 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6100 13:43:15.771461 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6101 13:43:15.774589 MEM_TYPE=3, freq_sel=20
6102 13:43:15.778169 sv_algorithm_assistance_LP4_800
6103 13:43:15.781666 ============ PULL DRAM RESETB DOWN ============
6104 13:43:15.784613 ========== PULL DRAM RESETB DOWN end =========
6105 13:43:15.791307 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6106 13:43:15.794989 ===================================
6107 13:43:15.795100 LPDDR4 DRAM CONFIGURATION
6108 13:43:15.798230 ===================================
6109 13:43:15.801605 EX_ROW_EN[0] = 0x0
6110 13:43:15.801724 EX_ROW_EN[1] = 0x0
6111 13:43:15.804879 LP4Y_EN = 0x0
6112 13:43:15.804993 WORK_FSP = 0x0
6113 13:43:15.807994 WL = 0x2
6114 13:43:15.808102 RL = 0x2
6115 13:43:15.811665 BL = 0x2
6116 13:43:15.814719 RPST = 0x0
6117 13:43:15.814847 RD_PRE = 0x0
6118 13:43:15.818381 WR_PRE = 0x1
6119 13:43:15.818500 WR_PST = 0x0
6120 13:43:15.821358 DBI_WR = 0x0
6121 13:43:15.821436 DBI_RD = 0x0
6122 13:43:15.825000 OTF = 0x1
6123 13:43:15.828147 ===================================
6124 13:43:15.831630 ===================================
6125 13:43:15.831736 ANA top config
6126 13:43:15.834641 ===================================
6127 13:43:15.838095 DLL_ASYNC_EN = 0
6128 13:43:15.841635 ALL_SLAVE_EN = 1
6129 13:43:15.841719 NEW_RANK_MODE = 1
6130 13:43:15.844638 DLL_IDLE_MODE = 1
6131 13:43:15.847936 LP45_APHY_COMB_EN = 1
6132 13:43:15.851430 TX_ODT_DIS = 1
6133 13:43:15.851532 NEW_8X_MODE = 1
6134 13:43:15.854933 ===================================
6135 13:43:15.858019 ===================================
6136 13:43:15.861420 data_rate = 800
6137 13:43:15.864852 CKR = 1
6138 13:43:15.868050 DQ_P2S_RATIO = 4
6139 13:43:15.871647 ===================================
6140 13:43:15.874856 CA_P2S_RATIO = 4
6141 13:43:15.877955 DQ_CA_OPEN = 0
6142 13:43:15.878064 DQ_SEMI_OPEN = 1
6143 13:43:15.881590 CA_SEMI_OPEN = 1
6144 13:43:15.884561 CA_FULL_RATE = 0
6145 13:43:15.888132 DQ_CKDIV4_EN = 0
6146 13:43:15.891222 CA_CKDIV4_EN = 1
6147 13:43:15.894764 CA_PREDIV_EN = 0
6148 13:43:15.894847 PH8_DLY = 0
6149 13:43:15.897796 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6150 13:43:15.901279 DQ_AAMCK_DIV = 0
6151 13:43:15.904716 CA_AAMCK_DIV = 0
6152 13:43:15.907865 CA_ADMCK_DIV = 4
6153 13:43:15.911211 DQ_TRACK_CA_EN = 0
6154 13:43:15.911294 CA_PICK = 800
6155 13:43:15.914767 CA_MCKIO = 400
6156 13:43:15.917774 MCKIO_SEMI = 400
6157 13:43:15.921249 PLL_FREQ = 3016
6158 13:43:15.924769 DQ_UI_PI_RATIO = 32
6159 13:43:15.927919 CA_UI_PI_RATIO = 32
6160 13:43:15.931306 ===================================
6161 13:43:15.934784 ===================================
6162 13:43:15.937839 memory_type:LPDDR4
6163 13:43:15.937922 GP_NUM : 10
6164 13:43:15.941315 SRAM_EN : 1
6165 13:43:15.941398 MD32_EN : 0
6166 13:43:15.944783 ===================================
6167 13:43:15.947962 [ANA_INIT] >>>>>>>>>>>>>>
6168 13:43:15.951369 <<<<<< [CONFIGURE PHASE]: ANA_TX
6169 13:43:15.954720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6170 13:43:15.957886 ===================================
6171 13:43:15.960976 data_rate = 800,PCW = 0X7400
6172 13:43:15.964396 ===================================
6173 13:43:15.967969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6174 13:43:15.970938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6175 13:43:15.984532 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 13:43:15.987528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6177 13:43:15.990942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6178 13:43:15.994504 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6179 13:43:15.997708 [ANA_INIT] flow start
6180 13:43:16.000755 [ANA_INIT] PLL >>>>>>>>
6181 13:43:16.000837 [ANA_INIT] PLL <<<<<<<<
6182 13:43:16.004215 [ANA_INIT] MIDPI >>>>>>>>
6183 13:43:16.007362 [ANA_INIT] MIDPI <<<<<<<<
6184 13:43:16.007444 [ANA_INIT] DLL >>>>>>>>
6185 13:43:16.010960 [ANA_INIT] flow end
6186 13:43:16.014270 ============ LP4 DIFF to SE enter ============
6187 13:43:16.017502 ============ LP4 DIFF to SE exit ============
6188 13:43:16.020656 [ANA_INIT] <<<<<<<<<<<<<
6189 13:43:16.024165 [Flow] Enable top DCM control >>>>>
6190 13:43:16.027763 [Flow] Enable top DCM control <<<<<
6191 13:43:16.030856 Enable DLL master slave shuffle
6192 13:43:16.037705 ==============================================================
6193 13:43:16.037789 Gating Mode config
6194 13:43:16.044271 ==============================================================
6195 13:43:16.044355 Config description:
6196 13:43:16.054385 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6197 13:43:16.060915 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6198 13:43:16.067480 SELPH_MODE 0: By rank 1: By Phase
6199 13:43:16.070905 ==============================================================
6200 13:43:16.074394 GAT_TRACK_EN = 0
6201 13:43:16.077528 RX_GATING_MODE = 2
6202 13:43:16.080635 RX_GATING_TRACK_MODE = 2
6203 13:43:16.084200 SELPH_MODE = 1
6204 13:43:16.087742 PICG_EARLY_EN = 1
6205 13:43:16.090675 VALID_LAT_VALUE = 1
6206 13:43:16.097240 ==============================================================
6207 13:43:16.100937 Enter into Gating configuration >>>>
6208 13:43:16.103930 Exit from Gating configuration <<<<
6209 13:43:16.107561 Enter into DVFS_PRE_config >>>>>
6210 13:43:16.117149 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6211 13:43:16.120513 Exit from DVFS_PRE_config <<<<<
6212 13:43:16.123779 Enter into PICG configuration >>>>
6213 13:43:16.127277 Exit from PICG configuration <<<<
6214 13:43:16.130550 [RX_INPUT] configuration >>>>>
6215 13:43:16.130635 [RX_INPUT] configuration <<<<<
6216 13:43:16.137156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6217 13:43:16.143967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6218 13:43:16.146973 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6219 13:43:16.153891 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6220 13:43:16.160389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 13:43:16.167142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 13:43:16.170583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6223 13:43:16.173932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6224 13:43:16.180327 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6225 13:43:16.183881 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6226 13:43:16.186912 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6227 13:43:16.190454 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6228 13:43:16.193619 ===================================
6229 13:43:16.197228 LPDDR4 DRAM CONFIGURATION
6230 13:43:16.200446 ===================================
6231 13:43:16.203983 EX_ROW_EN[0] = 0x0
6232 13:43:16.204059 EX_ROW_EN[1] = 0x0
6233 13:43:16.206882 LP4Y_EN = 0x0
6234 13:43:16.206955 WORK_FSP = 0x0
6235 13:43:16.210600 WL = 0x2
6236 13:43:16.210686 RL = 0x2
6237 13:43:16.213541 BL = 0x2
6238 13:43:16.213624 RPST = 0x0
6239 13:43:16.217191 RD_PRE = 0x0
6240 13:43:16.217265 WR_PRE = 0x1
6241 13:43:16.220303 WR_PST = 0x0
6242 13:43:16.220381 DBI_WR = 0x0
6243 13:43:16.223816 DBI_RD = 0x0
6244 13:43:16.226904 OTF = 0x1
6245 13:43:16.226979 ===================================
6246 13:43:16.233553 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6247 13:43:16.237243 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6248 13:43:16.240493 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6249 13:43:16.243896 ===================================
6250 13:43:16.246924 LPDDR4 DRAM CONFIGURATION
6251 13:43:16.250446 ===================================
6252 13:43:16.253901 EX_ROW_EN[0] = 0x10
6253 13:43:16.253976 EX_ROW_EN[1] = 0x0
6254 13:43:16.257338 LP4Y_EN = 0x0
6255 13:43:16.257419 WORK_FSP = 0x0
6256 13:43:16.260450 WL = 0x2
6257 13:43:16.260538 RL = 0x2
6258 13:43:16.263973 BL = 0x2
6259 13:43:16.264044 RPST = 0x0
6260 13:43:16.266926 RD_PRE = 0x0
6261 13:43:16.267000 WR_PRE = 0x1
6262 13:43:16.270482 WR_PST = 0x0
6263 13:43:16.270557 DBI_WR = 0x0
6264 13:43:16.273975 DBI_RD = 0x0
6265 13:43:16.274048 OTF = 0x1
6266 13:43:16.276957 ===================================
6267 13:43:16.283838 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6268 13:43:16.288448 nWR fixed to 30
6269 13:43:16.291461 [ModeRegInit_LP4] CH0 RK0
6270 13:43:16.291534 [ModeRegInit_LP4] CH0 RK1
6271 13:43:16.295048 [ModeRegInit_LP4] CH1 RK0
6272 13:43:16.298152 [ModeRegInit_LP4] CH1 RK1
6273 13:43:16.298229 match AC timing 19
6274 13:43:16.304739 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6275 13:43:16.308308 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6276 13:43:16.311539 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6277 13:43:16.318181 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6278 13:43:16.321927 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6279 13:43:16.322077 ==
6280 13:43:16.324899 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 13:43:16.328618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 13:43:16.328700 ==
6283 13:43:16.335126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 13:43:16.341540 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 13:43:16.345140 [CA 0] Center 36 (8~64) winsize 57
6286 13:43:16.348314 [CA 1] Center 36 (8~64) winsize 57
6287 13:43:16.348486 [CA 2] Center 36 (8~64) winsize 57
6288 13:43:16.351679 [CA 3] Center 36 (8~64) winsize 57
6289 13:43:16.354966 [CA 4] Center 36 (8~64) winsize 57
6290 13:43:16.358371 [CA 5] Center 36 (8~64) winsize 57
6291 13:43:16.358474
6292 13:43:16.361543 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 13:43:16.365076
6294 13:43:16.368042 [CATrainingPosCal] consider 1 rank data
6295 13:43:16.368119 u2DelayCellTimex100 = 270/100 ps
6296 13:43:16.375014 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 13:43:16.378009 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 13:43:16.381474 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 13:43:16.384924 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 13:43:16.387866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 13:43:16.391445 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 13:43:16.391546
6303 13:43:16.394437 CA PerBit enable=1, Macro0, CA PI delay=36
6304 13:43:16.394517
6305 13:43:16.397998 [CBTSetCACLKResult] CA Dly = 36
6306 13:43:16.401085 CS Dly: 1 (0~32)
6307 13:43:16.401181 ==
6308 13:43:16.404686 Dram Type= 6, Freq= 0, CH_0, rank 1
6309 13:43:16.407843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 13:43:16.407939 ==
6311 13:43:16.414314 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6312 13:43:16.417845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6313 13:43:16.421039 [CA 0] Center 36 (8~64) winsize 57
6314 13:43:16.424601 [CA 1] Center 36 (8~64) winsize 57
6315 13:43:16.427710 [CA 2] Center 36 (8~64) winsize 57
6316 13:43:16.431285 [CA 3] Center 36 (8~64) winsize 57
6317 13:43:16.434381 [CA 4] Center 36 (8~64) winsize 57
6318 13:43:16.438010 [CA 5] Center 36 (8~64) winsize 57
6319 13:43:16.438084
6320 13:43:16.440991 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6321 13:43:16.441059
6322 13:43:16.444404 [CATrainingPosCal] consider 2 rank data
6323 13:43:16.447870 u2DelayCellTimex100 = 270/100 ps
6324 13:43:16.451230 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 13:43:16.454653 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 13:43:16.460897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 13:43:16.464465 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 13:43:16.467501 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 13:43:16.471091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 13:43:16.471159
6331 13:43:16.474068 CA PerBit enable=1, Macro0, CA PI delay=36
6332 13:43:16.474173
6333 13:43:16.477707 [CBTSetCACLKResult] CA Dly = 36
6334 13:43:16.477781 CS Dly: 1 (0~32)
6335 13:43:16.477844
6336 13:43:16.480716 ----->DramcWriteLeveling(PI) begin...
6337 13:43:16.484274 ==
6338 13:43:16.484421 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 13:43:16.490555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 13:43:16.490639 ==
6341 13:43:16.494129 Write leveling (Byte 0): 40 => 8
6342 13:43:16.497604 Write leveling (Byte 1): 32 => 0
6343 13:43:16.500733 DramcWriteLeveling(PI) end<-----
6344 13:43:16.500814
6345 13:43:16.500879 ==
6346 13:43:16.504149 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 13:43:16.507275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 13:43:16.507358 ==
6349 13:43:16.510476 [Gating] SW mode calibration
6350 13:43:16.517495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6351 13:43:16.520553 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6352 13:43:16.527194 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6353 13:43:16.530713 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 13:43:16.533728 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 13:43:16.540364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 13:43:16.543861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 13:43:16.546914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 13:43:16.553583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 13:43:16.556957 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 13:43:16.560318 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6361 13:43:16.563823 Total UI for P1: 0, mck2ui 16
6362 13:43:16.567009 best dqsien dly found for B0: ( 0, 14, 24)
6363 13:43:16.570496 Total UI for P1: 0, mck2ui 16
6364 13:43:16.574005 best dqsien dly found for B1: ( 0, 14, 24)
6365 13:43:16.576987 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6366 13:43:16.580383 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6367 13:43:16.580463
6368 13:43:16.587164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6369 13:43:16.590535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 13:43:16.593992 [Gating] SW calibration Done
6371 13:43:16.594073 ==
6372 13:43:16.597038 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 13:43:16.600442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 13:43:16.600523 ==
6375 13:43:16.600587 RX Vref Scan: 0
6376 13:43:16.600647
6377 13:43:16.603517 RX Vref 0 -> 0, step: 1
6378 13:43:16.603597
6379 13:43:16.607038 RX Delay -410 -> 252, step: 16
6380 13:43:16.610561 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6381 13:43:16.617060 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6382 13:43:16.620176 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6383 13:43:16.623726 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6384 13:43:16.627219 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6385 13:43:16.633459 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6386 13:43:16.637068 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6387 13:43:16.640067 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6388 13:43:16.643658 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6389 13:43:16.646838 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6390 13:43:16.653816 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6391 13:43:16.656679 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6392 13:43:16.660079 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6393 13:43:16.666846 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6394 13:43:16.670452 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6395 13:43:16.673353 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6396 13:43:16.673450 ==
6397 13:43:16.676770 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 13:43:16.680211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 13:43:16.680310 ==
6400 13:43:16.683572 DQS Delay:
6401 13:43:16.683653 DQS0 = 27, DQS1 = 43
6402 13:43:16.687104 DQM Delay:
6403 13:43:16.687186 DQM0 = 12, DQM1 = 12
6404 13:43:16.690071 DQ Delay:
6405 13:43:16.690152 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6406 13:43:16.693542 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6407 13:43:16.696905 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6408 13:43:16.700278 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6409 13:43:16.700359
6410 13:43:16.700424
6411 13:43:16.700500 ==
6412 13:43:16.703386 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 13:43:16.710193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 13:43:16.710301 ==
6415 13:43:16.710367
6416 13:43:16.710427
6417 13:43:16.710483 TX Vref Scan disable
6418 13:43:16.713223 == TX Byte 0 ==
6419 13:43:16.716564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 13:43:16.720095 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 13:43:16.723194 == TX Byte 1 ==
6422 13:43:16.726710 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6423 13:43:16.729785 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6424 13:43:16.733289 ==
6425 13:43:16.736914 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 13:43:16.739889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 13:43:16.740014 ==
6428 13:43:16.740107
6429 13:43:16.740204
6430 13:43:16.743405 TX Vref Scan disable
6431 13:43:16.743515 == TX Byte 0 ==
6432 13:43:16.746598 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 13:43:16.753209 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 13:43:16.753388 == TX Byte 1 ==
6435 13:43:16.756762 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6436 13:43:16.763097 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6437 13:43:16.763229
6438 13:43:16.763327 [DATLAT]
6439 13:43:16.763422 Freq=400, CH0 RK0
6440 13:43:16.763512
6441 13:43:16.766819 DATLAT Default: 0xf
6442 13:43:16.766921 0, 0xFFFF, sum = 0
6443 13:43:16.769708 1, 0xFFFF, sum = 0
6444 13:43:16.773246 2, 0xFFFF, sum = 0
6445 13:43:16.773380 3, 0xFFFF, sum = 0
6446 13:43:16.776710 4, 0xFFFF, sum = 0
6447 13:43:16.776827 5, 0xFFFF, sum = 0
6448 13:43:16.780075 6, 0xFFFF, sum = 0
6449 13:43:16.780187 7, 0xFFFF, sum = 0
6450 13:43:16.783156 8, 0xFFFF, sum = 0
6451 13:43:16.783277 9, 0xFFFF, sum = 0
6452 13:43:16.786576 10, 0xFFFF, sum = 0
6453 13:43:16.786694 11, 0xFFFF, sum = 0
6454 13:43:16.789957 12, 0xFFFF, sum = 0
6455 13:43:16.790040 13, 0x0, sum = 1
6456 13:43:16.793048 14, 0x0, sum = 2
6457 13:43:16.793153 15, 0x0, sum = 3
6458 13:43:16.796625 16, 0x0, sum = 4
6459 13:43:16.796734 best_step = 14
6460 13:43:16.796824
6461 13:43:16.796910 ==
6462 13:43:16.799996 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 13:43:16.803367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 13:43:16.806242 ==
6465 13:43:16.806344 RX Vref Scan: 1
6466 13:43:16.806435
6467 13:43:16.809882 RX Vref 0 -> 0, step: 1
6468 13:43:16.809955
6469 13:43:16.812926 RX Delay -327 -> 252, step: 8
6470 13:43:16.813025
6471 13:43:16.816507 Set Vref, RX VrefLevel [Byte0]: 60
6472 13:43:16.819529 [Byte1]: 51
6473 13:43:16.819636
6474 13:43:16.823136 Final RX Vref Byte 0 = 60 to rank0
6475 13:43:16.826296 Final RX Vref Byte 1 = 51 to rank0
6476 13:43:16.829485 Final RX Vref Byte 0 = 60 to rank1
6477 13:43:16.833037 Final RX Vref Byte 1 = 51 to rank1==
6478 13:43:16.836542 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 13:43:16.839580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 13:43:16.839732 ==
6481 13:43:16.842973 DQS Delay:
6482 13:43:16.843086 DQS0 = 28, DQS1 = 48
6483 13:43:16.846100 DQM Delay:
6484 13:43:16.846232 DQM0 = 11, DQM1 = 15
6485 13:43:16.846323 DQ Delay:
6486 13:43:16.849710 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6487 13:43:16.852761 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6488 13:43:16.856167 DQ8 =12, DQ9 =0, DQ10 =12, DQ11 =8
6489 13:43:16.859638 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6490 13:43:16.859786
6491 13:43:16.859881
6492 13:43:16.869479 [DQSOSCAuto] RK0, (LSB)MR18= 0xaea6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6493 13:43:16.872838 CH0 RK0: MR19=C0C, MR18=AEA6
6494 13:43:16.875932 CH0_RK0: MR19=0xC0C, MR18=0xAEA6, DQSOSC=388, MR23=63, INC=392, DEC=261
6495 13:43:16.879111 ==
6496 13:43:16.882499 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 13:43:16.885951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 13:43:16.886036 ==
6499 13:43:16.889275 [Gating] SW mode calibration
6500 13:43:16.895658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6501 13:43:16.899178 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6502 13:43:16.905798 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6503 13:43:16.909044 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 13:43:16.912574 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 13:43:16.919173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 13:43:16.922639 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 13:43:16.925716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 13:43:16.932396 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 13:43:16.935498 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 13:43:16.939050 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 13:43:16.942112 Total UI for P1: 0, mck2ui 16
6512 13:43:16.945604 best dqsien dly found for B0: ( 0, 14, 24)
6513 13:43:16.948681 Total UI for P1: 0, mck2ui 16
6514 13:43:16.952323 best dqsien dly found for B1: ( 0, 14, 24)
6515 13:43:16.955475 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6516 13:43:16.958952 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6517 13:43:16.959057
6518 13:43:16.965635 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6519 13:43:16.968709 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 13:43:16.968868 [Gating] SW calibration Done
6521 13:43:16.972186 ==
6522 13:43:16.975504 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 13:43:16.979098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 13:43:16.979261 ==
6525 13:43:16.979390 RX Vref Scan: 0
6526 13:43:16.979517
6527 13:43:16.982119 RX Vref 0 -> 0, step: 1
6528 13:43:16.982255
6529 13:43:16.985755 RX Delay -410 -> 252, step: 16
6530 13:43:16.988755 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6531 13:43:16.992067 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6532 13:43:16.998650 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6533 13:43:17.002173 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6534 13:43:17.005550 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6535 13:43:17.008516 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6536 13:43:17.015400 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6537 13:43:17.018939 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6538 13:43:17.021958 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6539 13:43:17.025487 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6540 13:43:17.032165 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6541 13:43:17.035671 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6542 13:43:17.038699 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6543 13:43:17.042315 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6544 13:43:17.048958 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6545 13:43:17.052127 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6546 13:43:17.052258 ==
6547 13:43:17.055611 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 13:43:17.058580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 13:43:17.058715 ==
6550 13:43:17.062009 DQS Delay:
6551 13:43:17.062144 DQS0 = 27, DQS1 = 43
6552 13:43:17.065078 DQM Delay:
6553 13:43:17.065219 DQM0 = 9, DQM1 = 13
6554 13:43:17.065385 DQ Delay:
6555 13:43:17.068613 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6556 13:43:17.072069 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6557 13:43:17.075009 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6558 13:43:17.078812 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6559 13:43:17.078918
6560 13:43:17.079013
6561 13:43:17.079105 ==
6562 13:43:17.082098 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 13:43:17.088157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 13:43:17.088263 ==
6565 13:43:17.088354
6566 13:43:17.088447
6567 13:43:17.088536 TX Vref Scan disable
6568 13:43:17.091847 == TX Byte 0 ==
6569 13:43:17.094834 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6570 13:43:17.098216 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6571 13:43:17.101496 == TX Byte 1 ==
6572 13:43:17.104929 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6573 13:43:17.108345 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6574 13:43:17.108453 ==
6575 13:43:17.111873 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 13:43:17.118175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 13:43:17.118284 ==
6578 13:43:17.118381
6579 13:43:17.118469
6580 13:43:17.118560 TX Vref Scan disable
6581 13:43:17.121821 == TX Byte 0 ==
6582 13:43:17.124906 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6583 13:43:17.128004 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6584 13:43:17.131563 == TX Byte 1 ==
6585 13:43:17.135134 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6586 13:43:17.138191 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6587 13:43:17.138300
6588 13:43:17.141648 [DATLAT]
6589 13:43:17.141733 Freq=400, CH0 RK1
6590 13:43:17.141799
6591 13:43:17.144828 DATLAT Default: 0xe
6592 13:43:17.144952 0, 0xFFFF, sum = 0
6593 13:43:17.148458 1, 0xFFFF, sum = 0
6594 13:43:17.148561 2, 0xFFFF, sum = 0
6595 13:43:17.151536 3, 0xFFFF, sum = 0
6596 13:43:17.151638 4, 0xFFFF, sum = 0
6597 13:43:17.154693 5, 0xFFFF, sum = 0
6598 13:43:17.154775 6, 0xFFFF, sum = 0
6599 13:43:17.158190 7, 0xFFFF, sum = 0
6600 13:43:17.158328 8, 0xFFFF, sum = 0
6601 13:43:17.161162 9, 0xFFFF, sum = 0
6602 13:43:17.161309 10, 0xFFFF, sum = 0
6603 13:43:17.164732 11, 0xFFFF, sum = 0
6604 13:43:17.168282 12, 0xFFFF, sum = 0
6605 13:43:17.168417 13, 0x0, sum = 1
6606 13:43:17.168536 14, 0x0, sum = 2
6607 13:43:17.171467 15, 0x0, sum = 3
6608 13:43:17.171603 16, 0x0, sum = 4
6609 13:43:17.174968 best_step = 14
6610 13:43:17.175102
6611 13:43:17.175225 ==
6612 13:43:17.177957 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 13:43:17.181517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 13:43:17.181672 ==
6615 13:43:17.184825 RX Vref Scan: 0
6616 13:43:17.184970
6617 13:43:17.185092 RX Vref 0 -> 0, step: 1
6618 13:43:17.185217
6619 13:43:17.187901 RX Delay -327 -> 252, step: 8
6620 13:43:17.196069 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6621 13:43:17.199690 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6622 13:43:17.203145 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6623 13:43:17.205911 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6624 13:43:17.213000 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6625 13:43:17.216270 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6626 13:43:17.219546 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6627 13:43:17.222996 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6628 13:43:17.229466 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6629 13:43:17.233049 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6630 13:43:17.236153 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6631 13:43:17.242647 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6632 13:43:17.246250 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6633 13:43:17.249274 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6634 13:43:17.252466 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6635 13:43:17.259184 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6636 13:43:17.259296 ==
6637 13:43:17.262722 Dram Type= 6, Freq= 0, CH_0, rank 1
6638 13:43:17.265808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 13:43:17.265916 ==
6640 13:43:17.266009 DQS Delay:
6641 13:43:17.269420 DQS0 = 28, DQS1 = 40
6642 13:43:17.269521 DQM Delay:
6643 13:43:17.272526 DQM0 = 10, DQM1 = 12
6644 13:43:17.272640 DQ Delay:
6645 13:43:17.276042 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6646 13:43:17.279461 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6647 13:43:17.282549 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6648 13:43:17.285903 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6649 13:43:17.286047
6650 13:43:17.286173
6651 13:43:17.292829 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6652 13:43:17.295835 CH0 RK1: MR19=C0C, MR18=BC6F
6653 13:43:17.302838 CH0_RK1: MR19=0xC0C, MR18=0xBC6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6654 13:43:17.305947 [RxdqsGatingPostProcess] freq 400
6655 13:43:17.312446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6656 13:43:17.312593 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 13:43:17.316253 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 13:43:17.319218 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 13:43:17.322964 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 13:43:17.326314 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 13:43:17.329505 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 13:43:17.332708 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 13:43:17.336106 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 13:43:17.339658 Pre-setting of DQS Precalculation
6665 13:43:17.342804 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6666 13:43:17.346254 ==
6667 13:43:17.346358 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 13:43:17.352473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 13:43:17.352583 ==
6670 13:43:17.356054 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 13:43:17.362763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6672 13:43:17.365699 [CA 0] Center 36 (8~64) winsize 57
6673 13:43:17.369272 [CA 1] Center 36 (8~64) winsize 57
6674 13:43:17.372547 [CA 2] Center 36 (8~64) winsize 57
6675 13:43:17.375701 [CA 3] Center 36 (8~64) winsize 57
6676 13:43:17.379189 [CA 4] Center 36 (8~64) winsize 57
6677 13:43:17.382193 [CA 5] Center 36 (8~64) winsize 57
6678 13:43:17.382297
6679 13:43:17.385892 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6680 13:43:17.385995
6681 13:43:17.388860 [CATrainingPosCal] consider 1 rank data
6682 13:43:17.392181 u2DelayCellTimex100 = 270/100 ps
6683 13:43:17.395687 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 13:43:17.398760 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 13:43:17.402482 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 13:43:17.405436 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 13:43:17.412127 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 13:43:17.415793 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 13:43:17.415898
6690 13:43:17.419212 CA PerBit enable=1, Macro0, CA PI delay=36
6691 13:43:17.419314
6692 13:43:17.422089 [CBTSetCACLKResult] CA Dly = 36
6693 13:43:17.422201 CS Dly: 1 (0~32)
6694 13:43:17.422294 ==
6695 13:43:17.425787 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 13:43:17.428833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 13:43:17.432125 ==
6698 13:43:17.435456 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6699 13:43:17.442595 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6700 13:43:17.445447 [CA 0] Center 36 (8~64) winsize 57
6701 13:43:17.448987 [CA 1] Center 36 (8~64) winsize 57
6702 13:43:17.452459 [CA 2] Center 36 (8~64) winsize 57
6703 13:43:17.455580 [CA 3] Center 36 (8~64) winsize 57
6704 13:43:17.459090 [CA 4] Center 36 (8~64) winsize 57
6705 13:43:17.462042 [CA 5] Center 36 (8~64) winsize 57
6706 13:43:17.462146
6707 13:43:17.465713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6708 13:43:17.465825
6709 13:43:17.469156 [CATrainingPosCal] consider 2 rank data
6710 13:43:17.472223 u2DelayCellTimex100 = 270/100 ps
6711 13:43:17.475784 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 13:43:17.478938 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 13:43:17.482332 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 13:43:17.485428 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 13:43:17.488936 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 13:43:17.492007 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 13:43:17.492110
6718 13:43:17.495339 CA PerBit enable=1, Macro0, CA PI delay=36
6719 13:43:17.498670
6720 13:43:17.498772 [CBTSetCACLKResult] CA Dly = 36
6721 13:43:17.502247 CS Dly: 1 (0~32)
6722 13:43:17.502360
6723 13:43:17.505262 ----->DramcWriteLeveling(PI) begin...
6724 13:43:17.505379 ==
6725 13:43:17.508844 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 13:43:17.511920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 13:43:17.512024 ==
6728 13:43:17.515527 Write leveling (Byte 0): 40 => 8
6729 13:43:17.518561 Write leveling (Byte 1): 32 => 0
6730 13:43:17.522143 DramcWriteLeveling(PI) end<-----
6731 13:43:17.522258
6732 13:43:17.522352 ==
6733 13:43:17.525140 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 13:43:17.528594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 13:43:17.528702 ==
6736 13:43:17.531875 [Gating] SW mode calibration
6737 13:43:17.538669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6738 13:43:17.545396 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6739 13:43:17.548937 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6740 13:43:17.555558 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 13:43:17.558539 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 13:43:17.562198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 13:43:17.568478 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 13:43:17.571920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 13:43:17.575267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 13:43:17.578816 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 13:43:17.585486 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6748 13:43:17.588492 Total UI for P1: 0, mck2ui 16
6749 13:43:17.592014 best dqsien dly found for B0: ( 0, 14, 24)
6750 13:43:17.595109 Total UI for P1: 0, mck2ui 16
6751 13:43:17.598543 best dqsien dly found for B1: ( 0, 14, 24)
6752 13:43:17.601971 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6753 13:43:17.605068 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6754 13:43:17.605172
6755 13:43:17.608668 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6756 13:43:17.611695 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 13:43:17.615246 [Gating] SW calibration Done
6758 13:43:17.615356 ==
6759 13:43:17.618695 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 13:43:17.621774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 13:43:17.621910 ==
6762 13:43:17.625193 RX Vref Scan: 0
6763 13:43:17.625325
6764 13:43:17.628256 RX Vref 0 -> 0, step: 1
6765 13:43:17.628367
6766 13:43:17.628467 RX Delay -410 -> 252, step: 16
6767 13:43:17.634902 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6768 13:43:17.638656 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6769 13:43:17.641975 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6770 13:43:17.645237 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6771 13:43:17.651582 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6772 13:43:17.654984 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6773 13:43:17.658466 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6774 13:43:17.661937 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6775 13:43:17.668190 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6776 13:43:17.671722 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6777 13:43:17.675145 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6778 13:43:17.678604 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6779 13:43:17.685320 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6780 13:43:17.688442 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6781 13:43:17.692017 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6782 13:43:17.695080 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6783 13:43:17.698562 ==
6784 13:43:17.702093 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 13:43:17.705038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 13:43:17.705139 ==
6787 13:43:17.705232 DQS Delay:
6788 13:43:17.708448 DQS0 = 27, DQS1 = 43
6789 13:43:17.708550 DQM Delay:
6790 13:43:17.711988 DQM0 = 9, DQM1 = 16
6791 13:43:17.712088 DQ Delay:
6792 13:43:17.714942 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6793 13:43:17.718427 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6794 13:43:17.721542 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6795 13:43:17.725150 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6796 13:43:17.725250
6797 13:43:17.725378
6798 13:43:17.725469 ==
6799 13:43:17.728715 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 13:43:17.731842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 13:43:17.731949 ==
6802 13:43:17.732042
6803 13:43:17.732131
6804 13:43:17.734971 TX Vref Scan disable
6805 13:43:17.735070 == TX Byte 0 ==
6806 13:43:17.741467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 13:43:17.744923 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 13:43:17.745023 == TX Byte 1 ==
6809 13:43:17.751679 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6810 13:43:17.754936 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6811 13:43:17.755037 ==
6812 13:43:17.758311 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 13:43:17.761515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 13:43:17.761616 ==
6815 13:43:17.761710
6816 13:43:17.761798
6817 13:43:17.764619 TX Vref Scan disable
6818 13:43:17.764719 == TX Byte 0 ==
6819 13:43:17.771607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 13:43:17.774644 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 13:43:17.774744 == TX Byte 1 ==
6822 13:43:17.781704 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6823 13:43:17.784835 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6824 13:43:17.784935
6825 13:43:17.785032 [DATLAT]
6826 13:43:17.787857 Freq=400, CH1 RK0
6827 13:43:17.787955
6828 13:43:17.788050 DATLAT Default: 0xf
6829 13:43:17.791521 0, 0xFFFF, sum = 0
6830 13:43:17.791622 1, 0xFFFF, sum = 0
6831 13:43:17.794560 2, 0xFFFF, sum = 0
6832 13:43:17.794661 3, 0xFFFF, sum = 0
6833 13:43:17.798050 4, 0xFFFF, sum = 0
6834 13:43:17.798150 5, 0xFFFF, sum = 0
6835 13:43:17.801550 6, 0xFFFF, sum = 0
6836 13:43:17.801652 7, 0xFFFF, sum = 0
6837 13:43:17.804646 8, 0xFFFF, sum = 0
6838 13:43:17.808090 9, 0xFFFF, sum = 0
6839 13:43:17.808193 10, 0xFFFF, sum = 0
6840 13:43:17.811560 11, 0xFFFF, sum = 0
6841 13:43:17.811664 12, 0xFFFF, sum = 0
6842 13:43:17.814534 13, 0x0, sum = 1
6843 13:43:17.814615 14, 0x0, sum = 2
6844 13:43:17.818081 15, 0x0, sum = 3
6845 13:43:17.818161 16, 0x0, sum = 4
6846 13:43:17.818225 best_step = 14
6847 13:43:17.818288
6848 13:43:17.821540 ==
6849 13:43:17.825007 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 13:43:17.827925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 13:43:17.828028 ==
6852 13:43:17.828121 RX Vref Scan: 1
6853 13:43:17.828213
6854 13:43:17.831473 RX Vref 0 -> 0, step: 1
6855 13:43:17.831575
6856 13:43:17.834395 RX Delay -327 -> 252, step: 8
6857 13:43:17.834495
6858 13:43:17.837979 Set Vref, RX VrefLevel [Byte0]: 52
6859 13:43:17.841521 [Byte1]: 53
6860 13:43:17.844613
6861 13:43:17.844718 Final RX Vref Byte 0 = 52 to rank0
6862 13:43:17.848113 Final RX Vref Byte 1 = 53 to rank0
6863 13:43:17.851544 Final RX Vref Byte 0 = 52 to rank1
6864 13:43:17.854828 Final RX Vref Byte 1 = 53 to rank1==
6865 13:43:17.857776 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 13:43:17.864886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 13:43:17.864994 ==
6868 13:43:17.865086 DQS Delay:
6869 13:43:17.868206 DQS0 = 32, DQS1 = 40
6870 13:43:17.868308 DQM Delay:
6871 13:43:17.868401 DQM0 = 11, DQM1 = 12
6872 13:43:17.871114 DQ Delay:
6873 13:43:17.874582 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6874 13:43:17.874688 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6875 13:43:17.878016 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6876 13:43:17.880978 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6877 13:43:17.884546
6878 13:43:17.884650
6879 13:43:17.891117 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6880 13:43:17.894692 CH1 RK0: MR19=C0C, MR18=93CF
6881 13:43:17.900991 CH1_RK0: MR19=0xC0C, MR18=0x93CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6882 13:43:17.901145 ==
6883 13:43:17.904470 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 13:43:17.907538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 13:43:17.907649 ==
6886 13:43:17.911006 [Gating] SW mode calibration
6887 13:43:17.917531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6888 13:43:17.924534 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6889 13:43:17.927733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6890 13:43:17.931252 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 13:43:17.937927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 13:43:17.940981 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 13:43:17.944523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 13:43:17.951073 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 13:43:17.954097 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 13:43:17.957583 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 13:43:17.960904 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6898 13:43:17.964239 Total UI for P1: 0, mck2ui 16
6899 13:43:17.967586 best dqsien dly found for B0: ( 0, 14, 24)
6900 13:43:17.970959 Total UI for P1: 0, mck2ui 16
6901 13:43:17.974351 best dqsien dly found for B1: ( 0, 14, 24)
6902 13:43:17.977241 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6903 13:43:17.983963 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6904 13:43:17.984072
6905 13:43:17.987591 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6906 13:43:17.990496 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 13:43:17.994111 [Gating] SW calibration Done
6908 13:43:17.994185 ==
6909 13:43:17.997215 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 13:43:18.000737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 13:43:18.000812 ==
6912 13:43:18.004189 RX Vref Scan: 0
6913 13:43:18.004285
6914 13:43:18.004381 RX Vref 0 -> 0, step: 1
6915 13:43:18.004469
6916 13:43:18.007275 RX Delay -410 -> 252, step: 16
6917 13:43:18.010815 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6918 13:43:18.017500 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6919 13:43:18.020455 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6920 13:43:18.024070 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6921 13:43:18.027176 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6922 13:43:18.033744 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6923 13:43:18.037248 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6924 13:43:18.040844 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6925 13:43:18.043726 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6926 13:43:18.050750 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6927 13:43:18.053859 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6928 13:43:18.057402 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6929 13:43:18.060351 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6930 13:43:18.067331 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6931 13:43:18.070649 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6932 13:43:18.073958 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6933 13:43:18.074043 ==
6934 13:43:18.077332 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 13:43:18.084062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 13:43:18.084158 ==
6937 13:43:18.084226 DQS Delay:
6938 13:43:18.086991 DQS0 = 35, DQS1 = 43
6939 13:43:18.087065 DQM Delay:
6940 13:43:18.087133 DQM0 = 16, DQM1 = 21
6941 13:43:18.090587 DQ Delay:
6942 13:43:18.094076 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6943 13:43:18.097083 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6944 13:43:18.097161 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6945 13:43:18.103716 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =32
6946 13:43:18.103799
6947 13:43:18.103867
6948 13:43:18.103928 ==
6949 13:43:18.107290 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 13:43:18.110349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 13:43:18.110422 ==
6952 13:43:18.110490
6953 13:43:18.110553
6954 13:43:18.113820 TX Vref Scan disable
6955 13:43:18.113889 == TX Byte 0 ==
6956 13:43:18.117400 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6957 13:43:18.124045 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6958 13:43:18.124127 == TX Byte 1 ==
6959 13:43:18.127055 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6960 13:43:18.133795 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6961 13:43:18.133873 ==
6962 13:43:18.137319 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 13:43:18.140491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 13:43:18.140568 ==
6965 13:43:18.140630
6966 13:43:18.140688
6967 13:43:18.143678 TX Vref Scan disable
6968 13:43:18.143756 == TX Byte 0 ==
6969 13:43:18.147044 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6970 13:43:18.153727 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6971 13:43:18.153803 == TX Byte 1 ==
6972 13:43:18.157206 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6973 13:43:18.163764 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6974 13:43:18.163836
6975 13:43:18.163899 [DATLAT]
6976 13:43:18.163957 Freq=400, CH1 RK1
6977 13:43:18.164023
6978 13:43:18.166894 DATLAT Default: 0xe
6979 13:43:18.170395 0, 0xFFFF, sum = 0
6980 13:43:18.170467 1, 0xFFFF, sum = 0
6981 13:43:18.173875 2, 0xFFFF, sum = 0
6982 13:43:18.173945 3, 0xFFFF, sum = 0
6983 13:43:18.176820 4, 0xFFFF, sum = 0
6984 13:43:18.176889 5, 0xFFFF, sum = 0
6985 13:43:18.180254 6, 0xFFFF, sum = 0
6986 13:43:18.180330 7, 0xFFFF, sum = 0
6987 13:43:18.183633 8, 0xFFFF, sum = 0
6988 13:43:18.183720 9, 0xFFFF, sum = 0
6989 13:43:18.187007 10, 0xFFFF, sum = 0
6990 13:43:18.187077 11, 0xFFFF, sum = 0
6991 13:43:18.190162 12, 0xFFFF, sum = 0
6992 13:43:18.190248 13, 0x0, sum = 1
6993 13:43:18.193686 14, 0x0, sum = 2
6994 13:43:18.193770 15, 0x0, sum = 3
6995 13:43:18.196782 16, 0x0, sum = 4
6996 13:43:18.196852 best_step = 14
6997 13:43:18.196911
6998 13:43:18.196973 ==
6999 13:43:18.199892 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 13:43:18.206555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 13:43:18.206628 ==
7002 13:43:18.206690 RX Vref Scan: 0
7003 13:43:18.206756
7004 13:43:18.209988 RX Vref 0 -> 0, step: 1
7005 13:43:18.210099
7006 13:43:18.213107 RX Delay -327 -> 252, step: 8
7007 13:43:18.220271 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7008 13:43:18.223352 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7009 13:43:18.226740 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7010 13:43:18.230148 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7011 13:43:18.236581 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7012 13:43:18.240089 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7013 13:43:18.243167 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7014 13:43:18.246631 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7015 13:43:18.250194 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7016 13:43:18.256827 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7017 13:43:18.259883 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7018 13:43:18.263495 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7019 13:43:18.270071 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7020 13:43:18.273097 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7021 13:43:18.276497 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7022 13:43:18.280201 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7023 13:43:18.280281 ==
7024 13:43:18.283067 Dram Type= 6, Freq= 0, CH_1, rank 1
7025 13:43:18.289664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7026 13:43:18.289748 ==
7027 13:43:18.289812 DQS Delay:
7028 13:43:18.292982 DQS0 = 32, DQS1 = 36
7029 13:43:18.293050 DQM Delay:
7030 13:43:18.296302 DQM0 = 12, DQM1 = 11
7031 13:43:18.296372 DQ Delay:
7032 13:43:18.299857 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7033 13:43:18.303411 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =12
7034 13:43:18.303488 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
7035 13:43:18.310105 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7036 13:43:18.310175
7037 13:43:18.310243
7038 13:43:18.316686 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 388 ps
7039 13:43:18.319758 CH1 RK1: MR19=C0C, MR18=AF59
7040 13:43:18.326333 CH1_RK1: MR19=0xC0C, MR18=0xAF59, DQSOSC=388, MR23=63, INC=392, DEC=261
7041 13:43:18.329957 [RxdqsGatingPostProcess] freq 400
7042 13:43:18.333014 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7043 13:43:18.336491 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 13:43:18.339918 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 13:43:18.343059 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 13:43:18.346646 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 13:43:18.350108 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 13:43:18.353123 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 13:43:18.356545 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 13:43:18.359610 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 13:43:18.363097 Pre-setting of DQS Precalculation
7052 13:43:18.366673 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7053 13:43:18.376521 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7054 13:43:18.383073 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7055 13:43:18.383158
7056 13:43:18.383223
7057 13:43:18.386566 [Calibration Summary] 800 Mbps
7058 13:43:18.386649 CH 0, Rank 0
7059 13:43:18.389897 SW Impedance : PASS
7060 13:43:18.389979 DUTY Scan : NO K
7061 13:43:18.393083 ZQ Calibration : PASS
7062 13:43:18.396360 Jitter Meter : NO K
7063 13:43:18.396443 CBT Training : PASS
7064 13:43:18.399522 Write leveling : PASS
7065 13:43:18.399604 RX DQS gating : PASS
7066 13:43:18.402861 RX DQ/DQS(RDDQC) : PASS
7067 13:43:18.406218 TX DQ/DQS : PASS
7068 13:43:18.406301 RX DATLAT : PASS
7069 13:43:18.409790 RX DQ/DQS(Engine): PASS
7070 13:43:18.412853 TX OE : NO K
7071 13:43:18.412936 All Pass.
7072 13:43:18.413002
7073 13:43:18.413063 CH 0, Rank 1
7074 13:43:18.416309 SW Impedance : PASS
7075 13:43:18.419533 DUTY Scan : NO K
7076 13:43:18.419615 ZQ Calibration : PASS
7077 13:43:18.423068 Jitter Meter : NO K
7078 13:43:18.426243 CBT Training : PASS
7079 13:43:18.426325 Write leveling : NO K
7080 13:43:18.429264 RX DQS gating : PASS
7081 13:43:18.432843 RX DQ/DQS(RDDQC) : PASS
7082 13:43:18.432926 TX DQ/DQS : PASS
7083 13:43:18.436385 RX DATLAT : PASS
7084 13:43:18.439774 RX DQ/DQS(Engine): PASS
7085 13:43:18.439857 TX OE : NO K
7086 13:43:18.439924 All Pass.
7087 13:43:18.442780
7088 13:43:18.442862 CH 1, Rank 0
7089 13:43:18.446351 SW Impedance : PASS
7090 13:43:18.446433 DUTY Scan : NO K
7091 13:43:18.449538 ZQ Calibration : PASS
7092 13:43:18.449620 Jitter Meter : NO K
7093 13:43:18.453003 CBT Training : PASS
7094 13:43:18.456078 Write leveling : PASS
7095 13:43:18.456161 RX DQS gating : PASS
7096 13:43:18.459617 RX DQ/DQS(RDDQC) : PASS
7097 13:43:18.463031 TX DQ/DQS : PASS
7098 13:43:18.463114 RX DATLAT : PASS
7099 13:43:18.466071 RX DQ/DQS(Engine): PASS
7100 13:43:18.469716 TX OE : NO K
7101 13:43:18.469800 All Pass.
7102 13:43:18.469865
7103 13:43:18.469925 CH 1, Rank 1
7104 13:43:18.472807 SW Impedance : PASS
7105 13:43:18.476342 DUTY Scan : NO K
7106 13:43:18.476425 ZQ Calibration : PASS
7107 13:43:18.479418 Jitter Meter : NO K
7108 13:43:18.482916 CBT Training : PASS
7109 13:43:18.483004 Write leveling : NO K
7110 13:43:18.485995 RX DQS gating : PASS
7111 13:43:18.489208 RX DQ/DQS(RDDQC) : PASS
7112 13:43:18.489291 TX DQ/DQS : PASS
7113 13:43:18.492784 RX DATLAT : PASS
7114 13:43:18.492867 RX DQ/DQS(Engine): PASS
7115 13:43:18.496291 TX OE : NO K
7116 13:43:18.496378 All Pass.
7117 13:43:18.496444
7118 13:43:18.499425 DramC Write-DBI off
7119 13:43:18.502701 PER_BANK_REFRESH: Hybrid Mode
7120 13:43:18.502784 TX_TRACKING: ON
7121 13:43:18.512699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7122 13:43:18.516225 [FAST_K] Save calibration result to emmc
7123 13:43:18.519270 dramc_set_vcore_voltage set vcore to 725000
7124 13:43:18.522864 Read voltage for 1600, 0
7125 13:43:18.522947 Vio18 = 0
7126 13:43:18.525916 Vcore = 725000
7127 13:43:18.525999 Vdram = 0
7128 13:43:18.526065 Vddq = 0
7129 13:43:18.526126 Vmddr = 0
7130 13:43:18.532973 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7131 13:43:18.536038 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7132 13:43:18.539540 MEM_TYPE=3, freq_sel=13
7133 13:43:18.542448 sv_algorithm_assistance_LP4_3733
7134 13:43:18.546189 ============ PULL DRAM RESETB DOWN ============
7135 13:43:18.552966 ========== PULL DRAM RESETB DOWN end =========
7136 13:43:18.555967 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7137 13:43:18.559582 ===================================
7138 13:43:18.562695 LPDDR4 DRAM CONFIGURATION
7139 13:43:18.566166 ===================================
7140 13:43:18.566249 EX_ROW_EN[0] = 0x0
7141 13:43:18.569208 EX_ROW_EN[1] = 0x0
7142 13:43:18.569290 LP4Y_EN = 0x0
7143 13:43:18.572853 WORK_FSP = 0x1
7144 13:43:18.572934 WL = 0x5
7145 13:43:18.575834 RL = 0x5
7146 13:43:18.575917 BL = 0x2
7147 13:43:18.579493 RPST = 0x0
7148 13:43:18.579620 RD_PRE = 0x0
7149 13:43:18.582429 WR_PRE = 0x1
7150 13:43:18.582512 WR_PST = 0x1
7151 13:43:18.585889 DBI_WR = 0x0
7152 13:43:18.585972 DBI_RD = 0x0
7153 13:43:18.589530 OTF = 0x1
7154 13:43:18.592557 ===================================
7155 13:43:18.596166 ===================================
7156 13:43:18.596249 ANA top config
7157 13:43:18.599134 ===================================
7158 13:43:18.602550 DLL_ASYNC_EN = 0
7159 13:43:18.605927 ALL_SLAVE_EN = 0
7160 13:43:18.609202 NEW_RANK_MODE = 1
7161 13:43:18.609286 DLL_IDLE_MODE = 1
7162 13:43:18.612684 LP45_APHY_COMB_EN = 1
7163 13:43:18.615950 TX_ODT_DIS = 0
7164 13:43:18.619172 NEW_8X_MODE = 1
7165 13:43:18.622659 ===================================
7166 13:43:18.626096 ===================================
7167 13:43:18.629260 data_rate = 3200
7168 13:43:18.632329 CKR = 1
7169 13:43:18.632412 DQ_P2S_RATIO = 8
7170 13:43:18.636017 ===================================
7171 13:43:18.639209 CA_P2S_RATIO = 8
7172 13:43:18.642692 DQ_CA_OPEN = 0
7173 13:43:18.645736 DQ_SEMI_OPEN = 0
7174 13:43:18.649161 CA_SEMI_OPEN = 0
7175 13:43:18.649270 CA_FULL_RATE = 0
7176 13:43:18.652590 DQ_CKDIV4_EN = 0
7177 13:43:18.655667 CA_CKDIV4_EN = 0
7178 13:43:18.659177 CA_PREDIV_EN = 0
7179 13:43:18.662654 PH8_DLY = 12
7180 13:43:18.665763 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7181 13:43:18.665847 DQ_AAMCK_DIV = 4
7182 13:43:18.669232 CA_AAMCK_DIV = 4
7183 13:43:18.672451 CA_ADMCK_DIV = 4
7184 13:43:18.675507 DQ_TRACK_CA_EN = 0
7185 13:43:18.678939 CA_PICK = 1600
7186 13:43:18.682077 CA_MCKIO = 1600
7187 13:43:18.685607 MCKIO_SEMI = 0
7188 13:43:18.689241 PLL_FREQ = 3068
7189 13:43:18.689328 DQ_UI_PI_RATIO = 32
7190 13:43:18.692335 CA_UI_PI_RATIO = 0
7191 13:43:18.695793 ===================================
7192 13:43:18.698742 ===================================
7193 13:43:18.702338 memory_type:LPDDR4
7194 13:43:18.705478 GP_NUM : 10
7195 13:43:18.705560 SRAM_EN : 1
7196 13:43:18.708990 MD32_EN : 0
7197 13:43:18.711905 ===================================
7198 13:43:18.715780 [ANA_INIT] >>>>>>>>>>>>>>
7199 13:43:18.715863 <<<<<< [CONFIGURE PHASE]: ANA_TX
7200 13:43:18.718665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7201 13:43:18.721941 ===================================
7202 13:43:18.725228 data_rate = 3200,PCW = 0X7600
7203 13:43:18.728984 ===================================
7204 13:43:18.732117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7205 13:43:18.738686 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7206 13:43:18.745363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 13:43:18.748937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7208 13:43:18.751961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7209 13:43:18.755468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7210 13:43:18.758483 [ANA_INIT] flow start
7211 13:43:18.758567 [ANA_INIT] PLL >>>>>>>>
7212 13:43:18.762117 [ANA_INIT] PLL <<<<<<<<
7213 13:43:18.765148 [ANA_INIT] MIDPI >>>>>>>>
7214 13:43:18.765231 [ANA_INIT] MIDPI <<<<<<<<
7215 13:43:18.768818 [ANA_INIT] DLL >>>>>>>>
7216 13:43:18.772240 [ANA_INIT] DLL <<<<<<<<
7217 13:43:18.772322 [ANA_INIT] flow end
7218 13:43:18.778610 ============ LP4 DIFF to SE enter ============
7219 13:43:18.782087 ============ LP4 DIFF to SE exit ============
7220 13:43:18.782171 [ANA_INIT] <<<<<<<<<<<<<
7221 13:43:18.785670 [Flow] Enable top DCM control >>>>>
7222 13:43:18.788675 [Flow] Enable top DCM control <<<<<
7223 13:43:18.792274 Enable DLL master slave shuffle
7224 13:43:18.798855 ==============================================================
7225 13:43:18.801943 Gating Mode config
7226 13:43:18.805348 ==============================================================
7227 13:43:18.809040 Config description:
7228 13:43:18.818955 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7229 13:43:18.825568 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7230 13:43:18.828459 SELPH_MODE 0: By rank 1: By Phase
7231 13:43:18.835476 ==============================================================
7232 13:43:18.838554 GAT_TRACK_EN = 1
7233 13:43:18.841984 RX_GATING_MODE = 2
7234 13:43:18.842068 RX_GATING_TRACK_MODE = 2
7235 13:43:18.845553 SELPH_MODE = 1
7236 13:43:18.848661 PICG_EARLY_EN = 1
7237 13:43:18.852207 VALID_LAT_VALUE = 1
7238 13:43:18.858709 ==============================================================
7239 13:43:18.862088 Enter into Gating configuration >>>>
7240 13:43:18.865626 Exit from Gating configuration <<<<
7241 13:43:18.868619 Enter into DVFS_PRE_config >>>>>
7242 13:43:18.878775 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7243 13:43:18.882133 Exit from DVFS_PRE_config <<<<<
7244 13:43:18.885712 Enter into PICG configuration >>>>
7245 13:43:18.888785 Exit from PICG configuration <<<<
7246 13:43:18.891968 [RX_INPUT] configuration >>>>>
7247 13:43:18.895709 [RX_INPUT] configuration <<<<<
7248 13:43:18.898719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7249 13:43:18.905276 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7250 13:43:18.912427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7251 13:43:18.915389 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7252 13:43:18.921997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 13:43:18.928635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 13:43:18.931879 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7255 13:43:18.935179 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7256 13:43:18.942026 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7257 13:43:18.945540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7258 13:43:18.948658 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7259 13:43:18.955163 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7260 13:43:18.958334 ===================================
7261 13:43:18.958461 LPDDR4 DRAM CONFIGURATION
7262 13:43:18.961885 ===================================
7263 13:43:18.965179 EX_ROW_EN[0] = 0x0
7264 13:43:18.968743 EX_ROW_EN[1] = 0x0
7265 13:43:18.968827 LP4Y_EN = 0x0
7266 13:43:18.971802 WORK_FSP = 0x1
7267 13:43:18.971885 WL = 0x5
7268 13:43:18.975296 RL = 0x5
7269 13:43:18.975379 BL = 0x2
7270 13:43:18.978569 RPST = 0x0
7271 13:43:18.978653 RD_PRE = 0x0
7272 13:43:18.981641 WR_PRE = 0x1
7273 13:43:18.981731 WR_PST = 0x1
7274 13:43:18.985118 DBI_WR = 0x0
7275 13:43:18.985201 DBI_RD = 0x0
7276 13:43:18.988247 OTF = 0x1
7277 13:43:18.991715 ===================================
7278 13:43:18.994807 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7279 13:43:18.998487 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7280 13:43:19.004970 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7281 13:43:19.008595 ===================================
7282 13:43:19.008679 LPDDR4 DRAM CONFIGURATION
7283 13:43:19.011593 ===================================
7284 13:43:19.015089 EX_ROW_EN[0] = 0x10
7285 13:43:19.015172 EX_ROW_EN[1] = 0x0
7286 13:43:19.018240 LP4Y_EN = 0x0
7287 13:43:19.021870 WORK_FSP = 0x1
7288 13:43:19.021954 WL = 0x5
7289 13:43:19.024869 RL = 0x5
7290 13:43:19.024957 BL = 0x2
7291 13:43:19.028334 RPST = 0x0
7292 13:43:19.028417 RD_PRE = 0x0
7293 13:43:19.031393 WR_PRE = 0x1
7294 13:43:19.031477 WR_PST = 0x1
7295 13:43:19.034911 DBI_WR = 0x0
7296 13:43:19.034995 DBI_RD = 0x0
7297 13:43:19.038315 OTF = 0x1
7298 13:43:19.041605 ===================================
7299 13:43:19.048289 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7300 13:43:19.048374 ==
7301 13:43:19.051353 Dram Type= 6, Freq= 0, CH_0, rank 0
7302 13:43:19.055013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 13:43:19.055105 ==
7304 13:43:19.058078 [Duty_Offset_Calibration]
7305 13:43:19.058177 B0:2 B1:0 CA:1
7306 13:43:19.058243
7307 13:43:19.061614 [DutyScan_Calibration_Flow] k_type=0
7308 13:43:19.071002
7309 13:43:19.071085 ==CLK 0==
7310 13:43:19.074106 Final CLK duty delay cell = -4
7311 13:43:19.077629 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7312 13:43:19.081097 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7313 13:43:19.084272 [-4] AVG Duty = 4906%(X100)
7314 13:43:19.084360
7315 13:43:19.087677 CH0 CLK Duty spec in!! Max-Min= 187%
7316 13:43:19.090726 [DutyScan_Calibration_Flow] ====Done====
7317 13:43:19.090810
7318 13:43:19.094107 [DutyScan_Calibration_Flow] k_type=1
7319 13:43:19.110248
7320 13:43:19.110331 ==DQS 0 ==
7321 13:43:19.113743 Final DQS duty delay cell = 0
7322 13:43:19.116832 [0] MAX Duty = 5218%(X100), DQS PI = 32
7323 13:43:19.120553 [0] MIN Duty = 4938%(X100), DQS PI = 62
7324 13:43:19.123561 [0] AVG Duty = 5078%(X100)
7325 13:43:19.123645
7326 13:43:19.123711 ==DQS 1 ==
7327 13:43:19.126747 Final DQS duty delay cell = -4
7328 13:43:19.130179 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7329 13:43:19.133682 [-4] MIN Duty = 4844%(X100), DQS PI = 22
7330 13:43:19.136822 [-4] AVG Duty = 4969%(X100)
7331 13:43:19.136905
7332 13:43:19.140311 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7333 13:43:19.140395
7334 13:43:19.143564 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7335 13:43:19.146901 [DutyScan_Calibration_Flow] ====Done====
7336 13:43:19.146984
7337 13:43:19.150128 [DutyScan_Calibration_Flow] k_type=3
7338 13:43:19.167646
7339 13:43:19.167730 ==DQM 0 ==
7340 13:43:19.171066 Final DQM duty delay cell = 0
7341 13:43:19.174487 [0] MAX Duty = 5093%(X100), DQS PI = 26
7342 13:43:19.178072 [0] MIN Duty = 4813%(X100), DQS PI = 50
7343 13:43:19.181015 [0] AVG Duty = 4953%(X100)
7344 13:43:19.181099
7345 13:43:19.181182 ==DQM 1 ==
7346 13:43:19.184645 Final DQM duty delay cell = 0
7347 13:43:19.187674 [0] MAX Duty = 5249%(X100), DQS PI = 30
7348 13:43:19.191091 [0] MIN Duty = 5000%(X100), DQS PI = 20
7349 13:43:19.194609 [0] AVG Duty = 5124%(X100)
7350 13:43:19.194693
7351 13:43:19.197625 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7352 13:43:19.197709
7353 13:43:19.201201 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7354 13:43:19.204268 [DutyScan_Calibration_Flow] ====Done====
7355 13:43:19.204352
7356 13:43:19.207776 [DutyScan_Calibration_Flow] k_type=2
7357 13:43:19.225093
7358 13:43:19.225176 ==DQ 0 ==
7359 13:43:19.228723 Final DQ duty delay cell = 0
7360 13:43:19.231632 [0] MAX Duty = 5124%(X100), DQS PI = 34
7361 13:43:19.235125 [0] MIN Duty = 5000%(X100), DQS PI = 0
7362 13:43:19.235210 [0] AVG Duty = 5062%(X100)
7363 13:43:19.238552
7364 13:43:19.238633 ==DQ 1 ==
7365 13:43:19.241601 Final DQ duty delay cell = 0
7366 13:43:19.244950 [0] MAX Duty = 4969%(X100), DQS PI = 42
7367 13:43:19.248460 [0] MIN Duty = 4875%(X100), DQS PI = 0
7368 13:43:19.248542 [0] AVG Duty = 4922%(X100)
7369 13:43:19.248606
7370 13:43:19.251410 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7371 13:43:19.255014
7372 13:43:19.258357 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7373 13:43:19.261387 [DutyScan_Calibration_Flow] ====Done====
7374 13:43:19.261484 ==
7375 13:43:19.264572 Dram Type= 6, Freq= 0, CH_1, rank 0
7376 13:43:19.268117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7377 13:43:19.268199 ==
7378 13:43:19.271191 [Duty_Offset_Calibration]
7379 13:43:19.271272 B0:0 B1:-1 CA:2
7380 13:43:19.271337
7381 13:43:19.274833 [DutyScan_Calibration_Flow] k_type=0
7382 13:43:19.285121
7383 13:43:19.285228 ==CLK 0==
7384 13:43:19.288683 Final CLK duty delay cell = 0
7385 13:43:19.291599 [0] MAX Duty = 5156%(X100), DQS PI = 42
7386 13:43:19.295074 [0] MIN Duty = 4906%(X100), DQS PI = 12
7387 13:43:19.295178 [0] AVG Duty = 5031%(X100)
7388 13:43:19.298534
7389 13:43:19.301747 CH1 CLK Duty spec in!! Max-Min= 250%
7390 13:43:19.304943 [DutyScan_Calibration_Flow] ====Done====
7391 13:43:19.305044
7392 13:43:19.308477 [DutyScan_Calibration_Flow] k_type=1
7393 13:43:19.325039
7394 13:43:19.325142 ==DQS 0 ==
7395 13:43:19.328179 Final DQS duty delay cell = 0
7396 13:43:19.331332 [0] MAX Duty = 5062%(X100), DQS PI = 10
7397 13:43:19.334912 [0] MIN Duty = 5000%(X100), DQS PI = 0
7398 13:43:19.335017 [0] AVG Duty = 5031%(X100)
7399 13:43:19.337935
7400 13:43:19.338041 ==DQS 1 ==
7401 13:43:19.341508 Final DQS duty delay cell = 0
7402 13:43:19.344528 [0] MAX Duty = 5187%(X100), DQS PI = 26
7403 13:43:19.348114 [0] MIN Duty = 4782%(X100), DQS PI = 2
7404 13:43:19.348217 [0] AVG Duty = 4984%(X100)
7405 13:43:19.351262
7406 13:43:19.354717 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7407 13:43:19.354800
7408 13:43:19.358016 CH1 DQS 1 Duty spec in!! Max-Min= 405%
7409 13:43:19.361424 [DutyScan_Calibration_Flow] ====Done====
7410 13:43:19.361505
7411 13:43:19.364680 [DutyScan_Calibration_Flow] k_type=3
7412 13:43:19.381767
7413 13:43:19.381849 ==DQM 0 ==
7414 13:43:19.384663 Final DQM duty delay cell = 4
7415 13:43:19.388470 [4] MAX Duty = 5125%(X100), DQS PI = 24
7416 13:43:19.391452 [4] MIN Duty = 4969%(X100), DQS PI = 0
7417 13:43:19.391533 [4] AVG Duty = 5047%(X100)
7418 13:43:19.394960
7419 13:43:19.395040 ==DQM 1 ==
7420 13:43:19.398050 Final DQM duty delay cell = -4
7421 13:43:19.401730 [-4] MAX Duty = 4938%(X100), DQS PI = 28
7422 13:43:19.404861 [-4] MIN Duty = 4719%(X100), DQS PI = 0
7423 13:43:19.407912 [-4] AVG Duty = 4828%(X100)
7424 13:43:19.407992
7425 13:43:19.411354 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7426 13:43:19.411435
7427 13:43:19.414909 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7428 13:43:19.417934 [DutyScan_Calibration_Flow] ====Done====
7429 13:43:19.418015
7430 13:43:19.421547 [DutyScan_Calibration_Flow] k_type=2
7431 13:43:19.438809
7432 13:43:19.438907 ==DQ 0 ==
7433 13:43:19.441897 Final DQ duty delay cell = 0
7434 13:43:19.445471 [0] MAX Duty = 5093%(X100), DQS PI = 24
7435 13:43:19.448478 [0] MIN Duty = 4938%(X100), DQS PI = 0
7436 13:43:19.448559 [0] AVG Duty = 5015%(X100)
7437 13:43:19.448624
7438 13:43:19.451835 ==DQ 1 ==
7439 13:43:19.455479 Final DQ duty delay cell = 0
7440 13:43:19.458475 [0] MAX Duty = 5094%(X100), DQS PI = 34
7441 13:43:19.462081 [0] MIN Duty = 4813%(X100), DQS PI = 0
7442 13:43:19.462162 [0] AVG Duty = 4953%(X100)
7443 13:43:19.462226
7444 13:43:19.465490 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7445 13:43:19.468279
7446 13:43:19.471703 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7447 13:43:19.474978 [DutyScan_Calibration_Flow] ====Done====
7448 13:43:19.478428 nWR fixed to 30
7449 13:43:19.478529 [ModeRegInit_LP4] CH0 RK0
7450 13:43:19.481696 [ModeRegInit_LP4] CH0 RK1
7451 13:43:19.485176 [ModeRegInit_LP4] CH1 RK0
7452 13:43:19.485293 [ModeRegInit_LP4] CH1 RK1
7453 13:43:19.488518 match AC timing 5
7454 13:43:19.491917 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7455 13:43:19.495354 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7456 13:43:19.502051 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7457 13:43:19.505174 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7458 13:43:19.512005 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7459 13:43:19.512083 [MiockJmeterHQA]
7460 13:43:19.512146
7461 13:43:19.515175 [DramcMiockJmeter] u1RxGatingPI = 0
7462 13:43:19.518225 0 : 4365, 4137
7463 13:43:19.518300 4 : 4252, 4027
7464 13:43:19.518363 8 : 4363, 4137
7465 13:43:19.521756 12 : 4363, 4138
7466 13:43:19.521830 16 : 4366, 4139
7467 13:43:19.524829 20 : 4255, 4029
7468 13:43:19.524901 24 : 4253, 4026
7469 13:43:19.528502 28 : 4253, 4027
7470 13:43:19.528577 32 : 4252, 4027
7471 13:43:19.531560 36 : 4366, 4140
7472 13:43:19.531635 40 : 4366, 4140
7473 13:43:19.531697 44 : 4250, 4027
7474 13:43:19.535026 48 : 4254, 4029
7475 13:43:19.535103 52 : 4361, 4138
7476 13:43:19.537979 56 : 4250, 4027
7477 13:43:19.538082 60 : 4360, 4138
7478 13:43:19.541439 64 : 4250, 4027
7479 13:43:19.541517 68 : 4250, 4027
7480 13:43:19.545125 72 : 4250, 4027
7481 13:43:19.545227 76 : 4250, 4026
7482 13:43:19.545340 80 : 4250, 4027
7483 13:43:19.548244 84 : 4250, 4027
7484 13:43:19.548342 88 : 4363, 3931
7485 13:43:19.551935 92 : 4364, 0
7486 13:43:19.552041 96 : 4253, 0
7487 13:43:19.552132 100 : 4363, 0
7488 13:43:19.555077 104 : 4252, 0
7489 13:43:19.555148 108 : 4360, 0
7490 13:43:19.558135 112 : 4250, 0
7491 13:43:19.558232 116 : 4250, 0
7492 13:43:19.558324 120 : 4252, 0
7493 13:43:19.561710 124 : 4250, 0
7494 13:43:19.561783 128 : 4250, 0
7495 13:43:19.561843 132 : 4363, 0
7496 13:43:19.564744 136 : 4253, 0
7497 13:43:19.564843 140 : 4250, 0
7498 13:43:19.568363 144 : 4253, 0
7499 13:43:19.568439 148 : 4252, 0
7500 13:43:19.568501 152 : 4363, 0
7501 13:43:19.571334 156 : 4258, 0
7502 13:43:19.571422 160 : 4252, 0
7503 13:43:19.575011 164 : 4361, 0
7504 13:43:19.575115 168 : 4250, 0
7505 13:43:19.575208 172 : 4250, 0
7506 13:43:19.578360 176 : 4250, 0
7507 13:43:19.578451 180 : 4253, 0
7508 13:43:19.581675 184 : 4363, 0
7509 13:43:19.581763 188 : 4252, 0
7510 13:43:19.581855 192 : 4250, 0
7511 13:43:19.585030 196 : 4255, 0
7512 13:43:19.585133 200 : 4361, 3
7513 13:43:19.587913 204 : 4250, 2455
7514 13:43:19.588015 208 : 4363, 4140
7515 13:43:19.591370 212 : 4250, 4027
7516 13:43:19.591474 216 : 4250, 4027
7517 13:43:19.591566 220 : 4250, 4027
7518 13:43:19.594769 224 : 4253, 4029
7519 13:43:19.594841 228 : 4250, 4027
7520 13:43:19.598180 232 : 4250, 4027
7521 13:43:19.598253 236 : 4252, 4029
7522 13:43:19.601256 240 : 4250, 4027
7523 13:43:19.601380 244 : 4363, 4140
7524 13:43:19.604758 248 : 4250, 4027
7525 13:43:19.604857 252 : 4250, 4026
7526 13:43:19.607816 256 : 4250, 4027
7527 13:43:19.607919 260 : 4364, 4140
7528 13:43:19.611452 264 : 4361, 4138
7529 13:43:19.611552 268 : 4248, 4024
7530 13:43:19.614453 272 : 4363, 4140
7531 13:43:19.614528 276 : 4253, 4029
7532 13:43:19.614590 280 : 4250, 4027
7533 13:43:19.617967 284 : 4250, 4026
7534 13:43:19.618067 288 : 4252, 4029
7535 13:43:19.621563 292 : 4253, 4029
7536 13:43:19.621665 296 : 4363, 4140
7537 13:43:19.624552 300 : 4252, 4027
7538 13:43:19.624628 304 : 4250, 4026
7539 13:43:19.627993 308 : 4250, 4027
7540 13:43:19.628092 312 : 4364, 4096
7541 13:43:19.631165 316 : 4361, 2322
7542 13:43:19.631271 320 : 4250, 7
7543 13:43:19.631365
7544 13:43:19.634819 MIOCK jitter meter ch=0
7545 13:43:19.634922
7546 13:43:19.637969 1T = (320-92) = 228 dly cells
7547 13:43:19.641554 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7548 13:43:19.641635 ==
7549 13:43:19.644560 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 13:43:19.651198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 13:43:19.651303 ==
7552 13:43:19.654619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 13:43:19.661093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 13:43:19.664559 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 13:43:19.671228 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 13:43:19.678858 [CA 0] Center 43 (13~73) winsize 61
7557 13:43:19.682216 [CA 1] Center 43 (13~73) winsize 61
7558 13:43:19.685543 [CA 2] Center 38 (8~68) winsize 61
7559 13:43:19.688891 [CA 3] Center 37 (8~67) winsize 60
7560 13:43:19.692052 [CA 4] Center 36 (6~66) winsize 61
7561 13:43:19.695371 [CA 5] Center 35 (5~65) winsize 61
7562 13:43:19.695472
7563 13:43:19.698603 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 13:43:19.698678
7565 13:43:19.701965 [CATrainingPosCal] consider 1 rank data
7566 13:43:19.705443 u2DelayCellTimex100 = 285/100 ps
7567 13:43:19.708405 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7568 13:43:19.715422 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7569 13:43:19.718422 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7570 13:43:19.721897 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7571 13:43:19.725009 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7572 13:43:19.728611 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7573 13:43:19.728709
7574 13:43:19.731716 CA PerBit enable=1, Macro0, CA PI delay=35
7575 13:43:19.731817
7576 13:43:19.735435 [CBTSetCACLKResult] CA Dly = 35
7577 13:43:19.738460 CS Dly: 9 (0~40)
7578 13:43:19.741941 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 13:43:19.745483 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 13:43:19.745560 ==
7581 13:43:19.748516 Dram Type= 6, Freq= 0, CH_0, rank 1
7582 13:43:19.751587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 13:43:19.755099 ==
7584 13:43:19.758679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7585 13:43:19.761790 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7586 13:43:19.768572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7587 13:43:19.771598 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7588 13:43:19.782098 [CA 0] Center 43 (13~74) winsize 62
7589 13:43:19.785510 [CA 1] Center 43 (13~73) winsize 61
7590 13:43:19.788760 [CA 2] Center 38 (9~68) winsize 60
7591 13:43:19.792098 [CA 3] Center 38 (9~68) winsize 60
7592 13:43:19.795507 [CA 4] Center 37 (7~67) winsize 61
7593 13:43:19.798810 [CA 5] Center 36 (6~66) winsize 61
7594 13:43:19.798913
7595 13:43:19.801853 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7596 13:43:19.801927
7597 13:43:19.805232 [CATrainingPosCal] consider 2 rank data
7598 13:43:19.808539 u2DelayCellTimex100 = 285/100 ps
7599 13:43:19.811918 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7600 13:43:19.818418 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7601 13:43:19.821949 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7602 13:43:19.825442 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7603 13:43:19.828557 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7604 13:43:19.831983 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7605 13:43:19.832088
7606 13:43:19.835131 CA PerBit enable=1, Macro0, CA PI delay=35
7607 13:43:19.835233
7608 13:43:19.838682 [CBTSetCACLKResult] CA Dly = 35
7609 13:43:19.841754 CS Dly: 10 (0~43)
7610 13:43:19.845178 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7611 13:43:19.848760 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7612 13:43:19.848843
7613 13:43:19.851823 ----->DramcWriteLeveling(PI) begin...
7614 13:43:19.851902 ==
7615 13:43:19.855412 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 13:43:19.861618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 13:43:19.861723 ==
7618 13:43:19.865001 Write leveling (Byte 0): 38 => 38
7619 13:43:19.865073 Write leveling (Byte 1): 32 => 32
7620 13:43:19.868163 DramcWriteLeveling(PI) end<-----
7621 13:43:19.868262
7622 13:43:19.871847 ==
7623 13:43:19.871923 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 13:43:19.878426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 13:43:19.878503 ==
7626 13:43:19.881434 [Gating] SW mode calibration
7627 13:43:19.888322 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7628 13:43:19.891545 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7629 13:43:19.898238 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 13:43:19.901443 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 13:43:19.904682 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7632 13:43:19.911323 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7633 13:43:19.914804 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7634 13:43:19.918121 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7635 13:43:19.924845 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 13:43:19.927884 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 13:43:19.931383 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 13:43:19.937991 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 13:43:19.941190 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
7640 13:43:19.944717 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7641 13:43:19.951178 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7642 13:43:19.954812 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
7643 13:43:19.957913 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 13:43:19.964520 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 13:43:19.968056 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 13:43:19.971065 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7647 13:43:19.974647 1 6 8 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
7648 13:43:19.981205 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7649 13:43:19.984422 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7650 13:43:19.987559 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7651 13:43:19.994459 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 13:43:19.997562 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 13:43:20.000935 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 13:43:20.007527 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 13:43:20.011181 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 13:43:20.014539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 13:43:20.021193 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7658 13:43:20.024498 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 13:43:20.027579 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 13:43:20.034080 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 13:43:20.037571 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 13:43:20.040690 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 13:43:20.047451 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 13:43:20.050964 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 13:43:20.054604 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 13:43:20.060607 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 13:43:20.064098 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 13:43:20.067324 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 13:43:20.074025 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 13:43:20.077645 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 13:43:20.081088 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 13:43:20.087806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7673 13:43:20.090930 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 13:43:20.094391 Total UI for P1: 0, mck2ui 16
7675 13:43:20.097484 best dqsien dly found for B0: ( 1, 9, 12)
7676 13:43:20.100614 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7677 13:43:20.104013 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 13:43:20.107599 Total UI for P1: 0, mck2ui 16
7679 13:43:20.110570 best dqsien dly found for B1: ( 1, 9, 18)
7680 13:43:20.114565 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7681 13:43:20.120524 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7682 13:43:20.120606
7683 13:43:20.123898 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7684 13:43:20.127214 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7685 13:43:20.130872 [Gating] SW calibration Done
7686 13:43:20.130951 ==
7687 13:43:20.133816 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 13:43:20.137424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 13:43:20.137497 ==
7690 13:43:20.140532 RX Vref Scan: 0
7691 13:43:20.140632
7692 13:43:20.140721 RX Vref 0 -> 0, step: 1
7693 13:43:20.140809
7694 13:43:20.143958 RX Delay 0 -> 252, step: 8
7695 13:43:20.147087 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7696 13:43:20.150611 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7697 13:43:20.157345 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7698 13:43:20.160478 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7699 13:43:20.164002 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7700 13:43:20.167055 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7701 13:43:20.170584 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7702 13:43:20.176948 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7703 13:43:20.180564 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7704 13:43:20.183644 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7705 13:43:20.187202 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7706 13:43:20.190782 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7707 13:43:20.197311 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7708 13:43:20.200524 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7709 13:43:20.203924 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7710 13:43:20.207578 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7711 13:43:20.207648 ==
7712 13:43:20.210642 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 13:43:20.214117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 13:43:20.217371 ==
7715 13:43:20.217470 DQS Delay:
7716 13:43:20.217561 DQS0 = 0, DQS1 = 0
7717 13:43:20.220854 DQM Delay:
7718 13:43:20.220925 DQM0 = 138, DQM1 = 126
7719 13:43:20.224088 DQ Delay:
7720 13:43:20.227531 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7721 13:43:20.230474 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7722 13:43:20.234072 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7723 13:43:20.237406 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7724 13:43:20.237494
7725 13:43:20.237567
7726 13:43:20.237628 ==
7727 13:43:20.240581 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 13:43:20.243648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 13:43:20.243748 ==
7730 13:43:20.243839
7731 13:43:20.247254
7732 13:43:20.247325 TX Vref Scan disable
7733 13:43:20.250308 == TX Byte 0 ==
7734 13:43:20.253876 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7735 13:43:20.257494 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7736 13:43:20.260590 == TX Byte 1 ==
7737 13:43:20.263734 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7738 13:43:20.267166 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7739 13:43:20.267241 ==
7740 13:43:20.270782 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 13:43:20.277408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 13:43:20.277482 ==
7743 13:43:20.289076
7744 13:43:20.292051 TX Vref early break, caculate TX vref
7745 13:43:20.295749 TX Vref=16, minBit 4, minWin=22, winSum=375
7746 13:43:20.298762 TX Vref=18, minBit 7, minWin=23, winSum=384
7747 13:43:20.302231 TX Vref=20, minBit 0, minWin=24, winSum=394
7748 13:43:20.305874 TX Vref=22, minBit 2, minWin=24, winSum=406
7749 13:43:20.308863 TX Vref=24, minBit 4, minWin=25, winSum=417
7750 13:43:20.315320 TX Vref=26, minBit 4, minWin=25, winSum=423
7751 13:43:20.318891 TX Vref=28, minBit 0, minWin=26, winSum=427
7752 13:43:20.321991 TX Vref=30, minBit 0, minWin=26, winSum=422
7753 13:43:20.325585 TX Vref=32, minBit 1, minWin=25, winSum=414
7754 13:43:20.328979 TX Vref=34, minBit 7, minWin=24, winSum=403
7755 13:43:20.335517 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
7756 13:43:20.335627
7757 13:43:20.338852 Final TX Range 0 Vref 28
7758 13:43:20.338958
7759 13:43:20.339049 ==
7760 13:43:20.342226 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 13:43:20.345444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 13:43:20.345549 ==
7763 13:43:20.345641
7764 13:43:20.345729
7765 13:43:20.348888 TX Vref Scan disable
7766 13:43:20.355653 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7767 13:43:20.355753 == TX Byte 0 ==
7768 13:43:20.358621 u2DelayCellOfst[0]=13 cells (4 PI)
7769 13:43:20.362256 u2DelayCellOfst[1]=20 cells (6 PI)
7770 13:43:20.365404 u2DelayCellOfst[2]=10 cells (3 PI)
7771 13:43:20.368870 u2DelayCellOfst[3]=13 cells (4 PI)
7772 13:43:20.371960 u2DelayCellOfst[4]=10 cells (3 PI)
7773 13:43:20.375448 u2DelayCellOfst[5]=0 cells (0 PI)
7774 13:43:20.378648 u2DelayCellOfst[6]=20 cells (6 PI)
7775 13:43:20.378721 u2DelayCellOfst[7]=17 cells (5 PI)
7776 13:43:20.385663 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7777 13:43:20.388781 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7778 13:43:20.388862 == TX Byte 1 ==
7779 13:43:20.391889 u2DelayCellOfst[8]=3 cells (1 PI)
7780 13:43:20.395559 u2DelayCellOfst[9]=0 cells (0 PI)
7781 13:43:20.398613 u2DelayCellOfst[10]=6 cells (2 PI)
7782 13:43:20.402131 u2DelayCellOfst[11]=3 cells (1 PI)
7783 13:43:20.405168 u2DelayCellOfst[12]=13 cells (4 PI)
7784 13:43:20.408688 u2DelayCellOfst[13]=10 cells (3 PI)
7785 13:43:20.412223 u2DelayCellOfst[14]=13 cells (4 PI)
7786 13:43:20.415205 u2DelayCellOfst[15]=10 cells (3 PI)
7787 13:43:20.418782 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7788 13:43:20.425486 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7789 13:43:20.425564 DramC Write-DBI on
7790 13:43:20.425631 ==
7791 13:43:20.428501 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 13:43:20.432041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 13:43:20.432141 ==
7794 13:43:20.435450
7795 13:43:20.435551
7796 13:43:20.435642 TX Vref Scan disable
7797 13:43:20.438664 == TX Byte 0 ==
7798 13:43:20.441813 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7799 13:43:20.445513 == TX Byte 1 ==
7800 13:43:20.448412 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7801 13:43:20.448486 DramC Write-DBI off
7802 13:43:20.451957
7803 13:43:20.452066 [DATLAT]
7804 13:43:20.452144 Freq=1600, CH0 RK0
7805 13:43:20.452207
7806 13:43:20.455334 DATLAT Default: 0xf
7807 13:43:20.455412 0, 0xFFFF, sum = 0
7808 13:43:20.458462 1, 0xFFFF, sum = 0
7809 13:43:20.458537 2, 0xFFFF, sum = 0
7810 13:43:20.462033 3, 0xFFFF, sum = 0
7811 13:43:20.462124 4, 0xFFFF, sum = 0
7812 13:43:20.465145 5, 0xFFFF, sum = 0
7813 13:43:20.468787 6, 0xFFFF, sum = 0
7814 13:43:20.468885 7, 0xFFFF, sum = 0
7815 13:43:20.471830 8, 0xFFFF, sum = 0
7816 13:43:20.471934 9, 0xFFFF, sum = 0
7817 13:43:20.475310 10, 0xFFFF, sum = 0
7818 13:43:20.475415 11, 0xFFFF, sum = 0
7819 13:43:20.478427 12, 0xFFFF, sum = 0
7820 13:43:20.478542 13, 0xFFFF, sum = 0
7821 13:43:20.481957 14, 0x0, sum = 1
7822 13:43:20.482091 15, 0x0, sum = 2
7823 13:43:20.484970 16, 0x0, sum = 3
7824 13:43:20.485113 17, 0x0, sum = 4
7825 13:43:20.488667 best_step = 15
7826 13:43:20.488825
7827 13:43:20.488933 ==
7828 13:43:20.491701 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 13:43:20.495232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 13:43:20.495386 ==
7831 13:43:20.498240 RX Vref Scan: 1
7832 13:43:20.498413
7833 13:43:20.498578 Set Vref Range= 24 -> 127
7834 13:43:20.498770
7835 13:43:20.501875 RX Vref 24 -> 127, step: 1
7836 13:43:20.502077
7837 13:43:20.504972 RX Delay 19 -> 252, step: 4
7838 13:43:20.505174
7839 13:43:20.508675 Set Vref, RX VrefLevel [Byte0]: 24
7840 13:43:20.511739 [Byte1]: 24
7841 13:43:20.512001
7842 13:43:20.515311 Set Vref, RX VrefLevel [Byte0]: 25
7843 13:43:20.518402 [Byte1]: 25
7844 13:43:20.518832
7845 13:43:20.521978 Set Vref, RX VrefLevel [Byte0]: 26
7846 13:43:20.524969 [Byte1]: 26
7847 13:43:20.529187
7848 13:43:20.529735 Set Vref, RX VrefLevel [Byte0]: 27
7849 13:43:20.532344 [Byte1]: 27
7850 13:43:20.536481
7851 13:43:20.537023 Set Vref, RX VrefLevel [Byte0]: 28
7852 13:43:20.540040 [Byte1]: 28
7853 13:43:20.544408
7854 13:43:20.544876 Set Vref, RX VrefLevel [Byte0]: 29
7855 13:43:20.547497 [Byte1]: 29
7856 13:43:20.551657
7857 13:43:20.552254 Set Vref, RX VrefLevel [Byte0]: 30
7858 13:43:20.554907 [Byte1]: 30
7859 13:43:20.559594
7860 13:43:20.560061 Set Vref, RX VrefLevel [Byte0]: 31
7861 13:43:20.562794 [Byte1]: 31
7862 13:43:20.567020
7863 13:43:20.567485 Set Vref, RX VrefLevel [Byte0]: 32
7864 13:43:20.570462 [Byte1]: 32
7865 13:43:20.574487
7866 13:43:20.575093 Set Vref, RX VrefLevel [Byte0]: 33
7867 13:43:20.578002 [Byte1]: 33
7868 13:43:20.582144
7869 13:43:20.582744 Set Vref, RX VrefLevel [Byte0]: 34
7870 13:43:20.585727 [Byte1]: 34
7871 13:43:20.589794
7872 13:43:20.590258 Set Vref, RX VrefLevel [Byte0]: 35
7873 13:43:20.592917 [Byte1]: 35
7874 13:43:20.597442
7875 13:43:20.597905 Set Vref, RX VrefLevel [Byte0]: 36
7876 13:43:20.600505 [Byte1]: 36
7877 13:43:20.605055
7878 13:43:20.605565 Set Vref, RX VrefLevel [Byte0]: 37
7879 13:43:20.608086 [Byte1]: 37
7880 13:43:20.612601
7881 13:43:20.613066 Set Vref, RX VrefLevel [Byte0]: 38
7882 13:43:20.615631 [Byte1]: 38
7883 13:43:20.620215
7884 13:43:20.620770 Set Vref, RX VrefLevel [Byte0]: 39
7885 13:43:20.623423 [Byte1]: 39
7886 13:43:20.627811
7887 13:43:20.628278 Set Vref, RX VrefLevel [Byte0]: 40
7888 13:43:20.630936 [Byte1]: 40
7889 13:43:20.635076
7890 13:43:20.635543 Set Vref, RX VrefLevel [Byte0]: 41
7891 13:43:20.638669 [Byte1]: 41
7892 13:43:20.642653
7893 13:43:20.643123 Set Vref, RX VrefLevel [Byte0]: 42
7894 13:43:20.646060 [Byte1]: 42
7895 13:43:20.650412
7896 13:43:20.650874 Set Vref, RX VrefLevel [Byte0]: 43
7897 13:43:20.653798 [Byte1]: 43
7898 13:43:20.657860
7899 13:43:20.658323 Set Vref, RX VrefLevel [Byte0]: 44
7900 13:43:20.661284 [Byte1]: 44
7901 13:43:20.665379
7902 13:43:20.665856 Set Vref, RX VrefLevel [Byte0]: 45
7903 13:43:20.668638 [Byte1]: 45
7904 13:43:20.673116
7905 13:43:20.673642 Set Vref, RX VrefLevel [Byte0]: 46
7906 13:43:20.676597 [Byte1]: 46
7907 13:43:20.680317
7908 13:43:20.680782 Set Vref, RX VrefLevel [Byte0]: 47
7909 13:43:20.683919 [Byte1]: 47
7910 13:43:20.688040
7911 13:43:20.688503 Set Vref, RX VrefLevel [Byte0]: 48
7912 13:43:20.691569 [Byte1]: 48
7913 13:43:20.695603
7914 13:43:20.696068 Set Vref, RX VrefLevel [Byte0]: 49
7915 13:43:20.699222 [Byte1]: 49
7916 13:43:20.703237
7917 13:43:20.703699 Set Vref, RX VrefLevel [Byte0]: 50
7918 13:43:20.706661 [Byte1]: 50
7919 13:43:20.710706
7920 13:43:20.711172 Set Vref, RX VrefLevel [Byte0]: 51
7921 13:43:20.714239 [Byte1]: 51
7922 13:43:20.718291
7923 13:43:20.718755 Set Vref, RX VrefLevel [Byte0]: 52
7924 13:43:20.721837 [Byte1]: 52
7925 13:43:20.725812
7926 13:43:20.726276 Set Vref, RX VrefLevel [Byte0]: 53
7927 13:43:20.729577 [Byte1]: 53
7928 13:43:20.733619
7929 13:43:20.734186 Set Vref, RX VrefLevel [Byte0]: 54
7930 13:43:20.736564 [Byte1]: 54
7931 13:43:20.741266
7932 13:43:20.741769 Set Vref, RX VrefLevel [Byte0]: 55
7933 13:43:20.744391 [Byte1]: 55
7934 13:43:20.748933
7935 13:43:20.749422 Set Vref, RX VrefLevel [Byte0]: 56
7936 13:43:20.751968 [Byte1]: 56
7937 13:43:20.756237
7938 13:43:20.756702 Set Vref, RX VrefLevel [Byte0]: 57
7939 13:43:20.759741 [Byte1]: 57
7940 13:43:20.763724
7941 13:43:20.764190 Set Vref, RX VrefLevel [Byte0]: 58
7942 13:43:20.767251 [Byte1]: 58
7943 13:43:20.771272
7944 13:43:20.771737 Set Vref, RX VrefLevel [Byte0]: 59
7945 13:43:20.775013 [Byte1]: 59
7946 13:43:20.779187
7947 13:43:20.779650 Set Vref, RX VrefLevel [Byte0]: 60
7948 13:43:20.782240 [Byte1]: 60
7949 13:43:20.786676
7950 13:43:20.787142 Set Vref, RX VrefLevel [Byte0]: 61
7951 13:43:20.789928 [Byte1]: 61
7952 13:43:20.794222
7953 13:43:20.794786 Set Vref, RX VrefLevel [Byte0]: 62
7954 13:43:20.797646 [Byte1]: 62
7955 13:43:20.801769
7956 13:43:20.802230 Set Vref, RX VrefLevel [Byte0]: 63
7957 13:43:20.804833 [Byte1]: 63
7958 13:43:20.809454
7959 13:43:20.809921 Set Vref, RX VrefLevel [Byte0]: 64
7960 13:43:20.812381 [Byte1]: 64
7961 13:43:20.816958
7962 13:43:20.817453 Set Vref, RX VrefLevel [Byte0]: 65
7963 13:43:20.820485 [Byte1]: 65
7964 13:43:20.824466
7965 13:43:20.824933 Set Vref, RX VrefLevel [Byte0]: 66
7966 13:43:20.827625 [Byte1]: 66
7967 13:43:20.832095
7968 13:43:20.832582 Set Vref, RX VrefLevel [Byte0]: 67
7969 13:43:20.835210 [Byte1]: 67
7970 13:43:20.839822
7971 13:43:20.840288 Set Vref, RX VrefLevel [Byte0]: 68
7972 13:43:20.842784 [Byte1]: 68
7973 13:43:20.847448
7974 13:43:20.847934 Set Vref, RX VrefLevel [Byte0]: 69
7975 13:43:20.850368 [Byte1]: 69
7976 13:43:20.854945
7977 13:43:20.855412 Set Vref, RX VrefLevel [Byte0]: 70
7978 13:43:20.858283 [Byte1]: 70
7979 13:43:20.862186
7980 13:43:20.862660 Set Vref, RX VrefLevel [Byte0]: 71
7981 13:43:20.865647 [Byte1]: 71
7982 13:43:20.869776
7983 13:43:20.870235 Set Vref, RX VrefLevel [Byte0]: 72
7984 13:43:20.873159 [Byte1]: 72
7985 13:43:20.877407
7986 13:43:20.877878 Set Vref, RX VrefLevel [Byte0]: 73
7987 13:43:20.880891 [Byte1]: 73
7988 13:43:20.885058
7989 13:43:20.885655 Set Vref, RX VrefLevel [Byte0]: 74
7990 13:43:20.888283 [Byte1]: 74
7991 13:43:20.892978
7992 13:43:20.893663 Set Vref, RX VrefLevel [Byte0]: 75
7993 13:43:20.895752 [Byte1]: 75
7994 13:43:20.900101
7995 13:43:20.900600 Set Vref, RX VrefLevel [Byte0]: 76
7996 13:43:20.903693 [Byte1]: 76
7997 13:43:20.907848
7998 13:43:20.908420 Set Vref, RX VrefLevel [Byte0]: 77
7999 13:43:20.911362 [Byte1]: 77
8000 13:43:20.915505
8001 13:43:20.916105 Set Vref, RX VrefLevel [Byte0]: 78
8002 13:43:20.918673 [Byte1]: 78
8003 13:43:20.923133
8004 13:43:20.923639 Final RX Vref Byte 0 = 61 to rank0
8005 13:43:20.926132 Final RX Vref Byte 1 = 63 to rank0
8006 13:43:20.929623 Final RX Vref Byte 0 = 61 to rank1
8007 13:43:20.932953 Final RX Vref Byte 1 = 63 to rank1==
8008 13:43:20.936183 Dram Type= 6, Freq= 0, CH_0, rank 0
8009 13:43:20.943094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8010 13:43:20.943582 ==
8011 13:43:20.944036 DQS Delay:
8012 13:43:20.944440 DQS0 = 0, DQS1 = 0
8013 13:43:20.946523 DQM Delay:
8014 13:43:20.946994 DQM0 = 136, DQM1 = 124
8015 13:43:20.949621 DQ Delay:
8016 13:43:20.952973 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
8017 13:43:20.956084 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =144
8018 13:43:20.959517 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8019 13:43:20.962956 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8020 13:43:20.963451
8021 13:43:20.963814
8022 13:43:20.964156
8023 13:43:20.965910 [DramC_TX_OE_Calibration] TA2
8024 13:43:20.969204 Original DQ_B0 (3 6) =30, OEN = 27
8025 13:43:20.972981 Original DQ_B1 (3 6) =30, OEN = 27
8026 13:43:20.975882 24, 0x0, End_B0=24 End_B1=24
8027 13:43:20.976351 25, 0x0, End_B0=25 End_B1=25
8028 13:43:20.979486 26, 0x0, End_B0=26 End_B1=26
8029 13:43:20.983149 27, 0x0, End_B0=27 End_B1=27
8030 13:43:20.986106 28, 0x0, End_B0=28 End_B1=28
8031 13:43:20.986585 29, 0x0, End_B0=29 End_B1=29
8032 13:43:20.989661 30, 0x0, End_B0=30 End_B1=30
8033 13:43:20.992463 31, 0x4545, End_B0=30 End_B1=30
8034 13:43:20.995923 Byte0 end_step=30 best_step=27
8035 13:43:20.999089 Byte1 end_step=30 best_step=27
8036 13:43:21.002756 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 13:43:21.005913 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 13:43:21.006394
8039 13:43:21.006759
8040 13:43:21.012355 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8041 13:43:21.015919 CH0 RK0: MR19=303, MR18=1F1D
8042 13:43:21.022349 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8043 13:43:21.022824
8044 13:43:21.025883 ----->DramcWriteLeveling(PI) begin...
8045 13:43:21.026377 ==
8046 13:43:21.028876 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 13:43:21.032403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 13:43:21.032882 ==
8049 13:43:21.035861 Write leveling (Byte 0): 37 => 37
8050 13:43:21.039016 Write leveling (Byte 1): 31 => 31
8051 13:43:21.042614 DramcWriteLeveling(PI) end<-----
8052 13:43:21.043326
8053 13:43:21.044016 ==
8054 13:43:21.045607 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 13:43:21.049270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 13:43:21.049789 ==
8057 13:43:21.052390 [Gating] SW mode calibration
8058 13:43:21.059002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8059 13:43:21.065470 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8060 13:43:21.069084 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 13:43:21.072414 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 13:43:21.079287 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 13:43:21.082477 1 4 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (1 1)
8064 13:43:21.085916 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 13:43:21.092352 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 13:43:21.095544 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 13:43:21.099456 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 13:43:21.105628 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 13:43:21.109042 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 13:43:21.112141 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8071 13:43:21.119015 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8072 13:43:21.122607 1 5 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
8073 13:43:21.125602 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 13:43:21.132175 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 13:43:21.135758 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 13:43:21.138803 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 13:43:21.145582 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 13:43:21.148953 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8079 13:43:21.152294 1 6 12 | B1->B0 | 2f2f 4444 | 0 1 | (0 0) (0 0)
8080 13:43:21.158836 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 13:43:21.162355 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 13:43:21.165209 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 13:43:21.171838 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 13:43:21.175267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 13:43:21.178702 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 13:43:21.182231 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 13:43:21.188892 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8088 13:43:21.192040 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 13:43:21.195078 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 13:43:21.201681 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 13:43:21.205155 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 13:43:21.208292 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 13:43:21.215134 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 13:43:21.218550 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 13:43:21.221757 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 13:43:21.228314 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 13:43:21.231591 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 13:43:21.235026 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 13:43:21.241769 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 13:43:21.244872 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 13:43:21.248065 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 13:43:21.254845 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 13:43:21.258482 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8104 13:43:21.261271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 13:43:21.265126 Total UI for P1: 0, mck2ui 16
8106 13:43:21.268018 best dqsien dly found for B0: ( 1, 9, 12)
8107 13:43:21.275121 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 13:43:21.275585 Total UI for P1: 0, mck2ui 16
8109 13:43:21.281556 best dqsien dly found for B1: ( 1, 9, 14)
8110 13:43:21.284967 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8111 13:43:21.288011 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8112 13:43:21.288493
8113 13:43:21.291605 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8114 13:43:21.294601 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8115 13:43:21.297911 [Gating] SW calibration Done
8116 13:43:21.298393 ==
8117 13:43:21.301282 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 13:43:21.304961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 13:43:21.305496 ==
8120 13:43:21.308107 RX Vref Scan: 0
8121 13:43:21.308590
8122 13:43:21.308956 RX Vref 0 -> 0, step: 1
8123 13:43:21.311152
8124 13:43:21.311611 RX Delay 0 -> 252, step: 8
8125 13:43:21.314694 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8126 13:43:21.321184 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8127 13:43:21.324835 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8128 13:43:21.327715 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8129 13:43:21.331140 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8130 13:43:21.334491 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8131 13:43:21.341065 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8132 13:43:21.344561 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8133 13:43:21.354835 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8134 13:43:21.355305 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8135 13:43:21.355718 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8136 13:43:21.360974 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8137 13:43:21.364619 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8138 13:43:21.367630 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8139 13:43:21.371202 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8140 13:43:21.374284 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8141 13:43:21.378029 ==
8142 13:43:21.378502 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 13:43:21.384537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 13:43:21.385055 ==
8145 13:43:21.385460 DQS Delay:
8146 13:43:21.387814 DQS0 = 0, DQS1 = 0
8147 13:43:21.388386 DQM Delay:
8148 13:43:21.391230 DQM0 = 136, DQM1 = 125
8149 13:43:21.391692 DQ Delay:
8150 13:43:21.394689 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8151 13:43:21.397751 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8152 13:43:21.401376 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8153 13:43:21.404359 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8154 13:43:21.404824
8155 13:43:21.405190
8156 13:43:21.405589 ==
8157 13:43:21.407945 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 13:43:21.414328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 13:43:21.414808 ==
8160 13:43:21.415282
8161 13:43:21.415727
8162 13:43:21.416159 TX Vref Scan disable
8163 13:43:21.418067 == TX Byte 0 ==
8164 13:43:21.421401 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8165 13:43:21.427984 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8166 13:43:21.428590 == TX Byte 1 ==
8167 13:43:21.431197 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8168 13:43:21.437812 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8169 13:43:21.438294 ==
8170 13:43:21.441349 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 13:43:21.444475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 13:43:21.444914 ==
8173 13:43:21.457183
8174 13:43:21.460700 TX Vref early break, caculate TX vref
8175 13:43:21.463858 TX Vref=16, minBit 3, minWin=23, winSum=392
8176 13:43:21.467369 TX Vref=18, minBit 0, minWin=24, winSum=398
8177 13:43:21.470444 TX Vref=20, minBit 1, minWin=24, winSum=401
8178 13:43:21.473959 TX Vref=22, minBit 0, minWin=25, winSum=417
8179 13:43:21.477166 TX Vref=24, minBit 0, minWin=25, winSum=420
8180 13:43:21.483883 TX Vref=26, minBit 0, minWin=26, winSum=429
8181 13:43:21.487468 TX Vref=28, minBit 0, minWin=26, winSum=431
8182 13:43:21.490905 TX Vref=30, minBit 0, minWin=26, winSum=427
8183 13:43:21.493807 TX Vref=32, minBit 0, minWin=25, winSum=417
8184 13:43:21.497410 TX Vref=34, minBit 2, minWin=24, winSum=408
8185 13:43:21.504044 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8186 13:43:21.504608
8187 13:43:21.507209 Final TX Range 0 Vref 28
8188 13:43:21.507680
8189 13:43:21.508053 ==
8190 13:43:21.510772 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 13:43:21.513846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 13:43:21.514319 ==
8193 13:43:21.514693
8194 13:43:21.515036
8195 13:43:21.517428 TX Vref Scan disable
8196 13:43:21.524280 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8197 13:43:21.525112 == TX Byte 0 ==
8198 13:43:21.527495 u2DelayCellOfst[0]=13 cells (4 PI)
8199 13:43:21.530484 u2DelayCellOfst[1]=20 cells (6 PI)
8200 13:43:21.534068 u2DelayCellOfst[2]=13 cells (4 PI)
8201 13:43:21.537084 u2DelayCellOfst[3]=13 cells (4 PI)
8202 13:43:21.540639 u2DelayCellOfst[4]=10 cells (3 PI)
8203 13:43:21.543913 u2DelayCellOfst[5]=0 cells (0 PI)
8204 13:43:21.547258 u2DelayCellOfst[6]=20 cells (6 PI)
8205 13:43:21.547908 u2DelayCellOfst[7]=20 cells (6 PI)
8206 13:43:21.554082 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8207 13:43:21.557409 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8208 13:43:21.560398 == TX Byte 1 ==
8209 13:43:21.560890 u2DelayCellOfst[8]=3 cells (1 PI)
8210 13:43:21.563934 u2DelayCellOfst[9]=0 cells (0 PI)
8211 13:43:21.567125 u2DelayCellOfst[10]=6 cells (2 PI)
8212 13:43:21.570443 u2DelayCellOfst[11]=3 cells (1 PI)
8213 13:43:21.574067 u2DelayCellOfst[12]=13 cells (4 PI)
8214 13:43:21.577062 u2DelayCellOfst[13]=10 cells (3 PI)
8215 13:43:21.580370 u2DelayCellOfst[14]=13 cells (4 PI)
8216 13:43:21.584032 u2DelayCellOfst[15]=10 cells (3 PI)
8217 13:43:21.587051 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8218 13:43:21.594083 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8219 13:43:21.594549 DramC Write-DBI on
8220 13:43:21.594914 ==
8221 13:43:21.597006 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 13:43:21.600354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 13:43:21.600822 ==
8224 13:43:21.603969
8225 13:43:21.604434
8226 13:43:21.604800 TX Vref Scan disable
8227 13:43:21.606844 == TX Byte 0 ==
8228 13:43:21.610485 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8229 13:43:21.613518 == TX Byte 1 ==
8230 13:43:21.617213 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8231 13:43:21.620274 DramC Write-DBI off
8232 13:43:21.620732
8233 13:43:21.621095 [DATLAT]
8234 13:43:21.621483 Freq=1600, CH0 RK1
8235 13:43:21.621820
8236 13:43:21.623391 DATLAT Default: 0xf
8237 13:43:21.623853 0, 0xFFFF, sum = 0
8238 13:43:21.627057 1, 0xFFFF, sum = 0
8239 13:43:21.630538 2, 0xFFFF, sum = 0
8240 13:43:21.631009 3, 0xFFFF, sum = 0
8241 13:43:21.633910 4, 0xFFFF, sum = 0
8242 13:43:21.634380 5, 0xFFFF, sum = 0
8243 13:43:21.636826 6, 0xFFFF, sum = 0
8244 13:43:21.637328 7, 0xFFFF, sum = 0
8245 13:43:21.640366 8, 0xFFFF, sum = 0
8246 13:43:21.640832 9, 0xFFFF, sum = 0
8247 13:43:21.643464 10, 0xFFFF, sum = 0
8248 13:43:21.643930 11, 0xFFFF, sum = 0
8249 13:43:21.646928 12, 0xFFFF, sum = 0
8250 13:43:21.647412 13, 0xFFFF, sum = 0
8251 13:43:21.650324 14, 0x0, sum = 1
8252 13:43:21.650809 15, 0x0, sum = 2
8253 13:43:21.653653 16, 0x0, sum = 3
8254 13:43:21.654141 17, 0x0, sum = 4
8255 13:43:21.657066 best_step = 15
8256 13:43:21.657587
8257 13:43:21.658060 ==
8258 13:43:21.660503 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 13:43:21.663755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 13:43:21.664238 ==
8261 13:43:21.664712 RX Vref Scan: 0
8262 13:43:21.667083
8263 13:43:21.667556 RX Vref 0 -> 0, step: 1
8264 13:43:21.668029
8265 13:43:21.670135 RX Delay 11 -> 252, step: 4
8266 13:43:21.673670 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8267 13:43:21.680280 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8268 13:43:21.683408 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8269 13:43:21.687045 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8270 13:43:21.690061 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8271 13:43:21.693535 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8272 13:43:21.699940 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8273 13:43:21.703311 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8274 13:43:21.706705 iDelay=191, Bit 8, Center 114 (67 ~ 162) 96
8275 13:43:21.710326 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8276 13:43:21.713387 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8277 13:43:21.716831 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8278 13:43:21.723630 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8279 13:43:21.726570 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8280 13:43:21.730115 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8281 13:43:21.733515 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8282 13:43:21.733936 ==
8283 13:43:21.736297 Dram Type= 6, Freq= 0, CH_0, rank 1
8284 13:43:21.743222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 13:43:21.743646 ==
8286 13:43:21.743978 DQS Delay:
8287 13:43:21.746720 DQS0 = 0, DQS1 = 0
8288 13:43:21.747139 DQM Delay:
8289 13:43:21.749765 DQM0 = 132, DQM1 = 123
8290 13:43:21.750185 DQ Delay:
8291 13:43:21.753323 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8292 13:43:21.756698 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
8293 13:43:21.759544 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8294 13:43:21.763205 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8295 13:43:21.763622
8296 13:43:21.763949
8297 13:43:21.764256
8298 13:43:21.766287 [DramC_TX_OE_Calibration] TA2
8299 13:43:21.769781 Original DQ_B0 (3 6) =30, OEN = 27
8300 13:43:21.773188 Original DQ_B1 (3 6) =30, OEN = 27
8301 13:43:21.776615 24, 0x0, End_B0=24 End_B1=24
8302 13:43:21.777038 25, 0x0, End_B0=25 End_B1=25
8303 13:43:21.779996 26, 0x0, End_B0=26 End_B1=26
8304 13:43:21.782986 27, 0x0, End_B0=27 End_B1=27
8305 13:43:21.786220 28, 0x0, End_B0=28 End_B1=28
8306 13:43:21.789691 29, 0x0, End_B0=29 End_B1=29
8307 13:43:21.790112 30, 0x0, End_B0=30 End_B1=30
8308 13:43:21.793147 31, 0x5151, End_B0=30 End_B1=30
8309 13:43:21.796645 Byte0 end_step=30 best_step=27
8310 13:43:21.799699 Byte1 end_step=30 best_step=27
8311 13:43:21.803278 Byte0 TX OE(2T, 0.5T) = (3, 3)
8312 13:43:21.806331 Byte1 TX OE(2T, 0.5T) = (3, 3)
8313 13:43:21.806749
8314 13:43:21.807078
8315 13:43:21.813250 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8316 13:43:21.816286 CH0 RK1: MR19=303, MR18=210E
8317 13:43:21.822802 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8318 13:43:21.826407 [RxdqsGatingPostProcess] freq 1600
8319 13:43:21.829887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8320 13:43:21.832949 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 13:43:21.836140 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 13:43:21.839622 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 13:43:21.843073 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 13:43:21.846306 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 13:43:21.849280 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 13:43:21.852687 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 13:43:21.856176 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 13:43:21.859658 Pre-setting of DQS Precalculation
8329 13:43:21.862706 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8330 13:43:21.863184 ==
8331 13:43:21.866115 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 13:43:21.869762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 13:43:21.872967 ==
8334 13:43:21.876256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 13:43:21.879045 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 13:43:21.885971 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 13:43:21.892516 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 13:43:21.899929 [CA 0] Center 40 (11~70) winsize 60
8339 13:43:21.902965 [CA 1] Center 41 (11~71) winsize 61
8340 13:43:21.906533 [CA 2] Center 37 (8~67) winsize 60
8341 13:43:21.910039 [CA 3] Center 36 (7~66) winsize 60
8342 13:43:21.912875 [CA 4] Center 37 (7~67) winsize 61
8343 13:43:21.916186 [CA 5] Center 36 (6~66) winsize 61
8344 13:43:21.916678
8345 13:43:21.919830 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8346 13:43:21.920254
8347 13:43:21.922899 [CATrainingPosCal] consider 1 rank data
8348 13:43:21.926444 u2DelayCellTimex100 = 285/100 ps
8349 13:43:21.929486 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8350 13:43:21.936372 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8351 13:43:21.939921 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8352 13:43:21.942859 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8353 13:43:21.946347 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8354 13:43:21.949830 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8355 13:43:21.950249
8356 13:43:21.952962 CA PerBit enable=1, Macro0, CA PI delay=36
8357 13:43:21.953417
8358 13:43:21.956500 [CBTSetCACLKResult] CA Dly = 36
8359 13:43:21.956916 CS Dly: 8 (0~39)
8360 13:43:21.963068 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 13:43:21.966500 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 13:43:21.966940 ==
8363 13:43:21.969831 Dram Type= 6, Freq= 0, CH_1, rank 1
8364 13:43:21.972934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 13:43:21.973424 ==
8366 13:43:21.979902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 13:43:21.982963 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 13:43:21.989401 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 13:43:21.992899 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 13:43:22.003114 [CA 0] Center 41 (12~71) winsize 60
8371 13:43:22.006162 [CA 1] Center 41 (12~71) winsize 60
8372 13:43:22.009653 [CA 2] Center 38 (8~68) winsize 61
8373 13:43:22.012846 [CA 3] Center 37 (8~67) winsize 60
8374 13:43:22.016240 [CA 4] Center 37 (8~67) winsize 60
8375 13:43:22.019581 [CA 5] Center 37 (7~67) winsize 61
8376 13:43:22.019953
8377 13:43:22.022682 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8378 13:43:22.023093
8379 13:43:22.026282 [CATrainingPosCal] consider 2 rank data
8380 13:43:22.029165 u2DelayCellTimex100 = 285/100 ps
8381 13:43:22.032752 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8382 13:43:22.039115 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8383 13:43:22.042635 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8384 13:43:22.046078 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8385 13:43:22.049272 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8386 13:43:22.052865 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8387 13:43:22.053364
8388 13:43:22.056189 CA PerBit enable=1, Macro0, CA PI delay=36
8389 13:43:22.056641
8390 13:43:22.059079 [CBTSetCACLKResult] CA Dly = 36
8391 13:43:22.062626 CS Dly: 10 (0~43)
8392 13:43:22.066148 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 13:43:22.069188 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 13:43:22.069596
8395 13:43:22.072626 ----->DramcWriteLeveling(PI) begin...
8396 13:43:22.073087 ==
8397 13:43:22.075746 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 13:43:22.079264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 13:43:22.082769 ==
8400 13:43:22.083445 Write leveling (Byte 0): 26 => 26
8401 13:43:22.085898 Write leveling (Byte 1): 28 => 28
8402 13:43:22.089007 DramcWriteLeveling(PI) end<-----
8403 13:43:22.089478
8404 13:43:22.089842 ==
8405 13:43:22.092546 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 13:43:22.099158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 13:43:22.099588 ==
8408 13:43:22.102723 [Gating] SW mode calibration
8409 13:43:22.109405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8410 13:43:22.112338 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8411 13:43:22.119160 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 13:43:22.122545 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 13:43:22.125857 1 4 8 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
8414 13:43:22.132618 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8415 13:43:22.135722 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 13:43:22.138953 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 13:43:22.142547 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 13:43:22.149107 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 13:43:22.152546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 13:43:22.155548 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8421 13:43:22.162401 1 5 8 | B1->B0 | 3232 2929 | 1 0 | (1 0) (1 0)
8422 13:43:22.165667 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8423 13:43:22.169194 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8424 13:43:22.175965 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 13:43:22.179247 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 13:43:22.182357 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 13:43:22.188946 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 13:43:22.192413 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8429 13:43:22.195590 1 6 8 | B1->B0 | 2a2a 3f3f | 0 0 | (0 0) (0 0)
8430 13:43:22.202289 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8431 13:43:22.205568 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 13:43:22.209101 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 13:43:22.215544 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 13:43:22.219053 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 13:43:22.222176 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 13:43:22.228633 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8437 13:43:22.232049 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8438 13:43:22.235468 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8439 13:43:22.242061 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 13:43:22.245628 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 13:43:22.248688 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 13:43:22.255319 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 13:43:22.258861 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 13:43:22.262386 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 13:43:22.265453 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 13:43:22.272163 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 13:43:22.275377 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 13:43:22.278968 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 13:43:22.285521 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 13:43:22.288954 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 13:43:22.292080 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 13:43:22.298526 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8453 13:43:22.302047 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8454 13:43:22.305224 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8455 13:43:22.308616 Total UI for P1: 0, mck2ui 16
8456 13:43:22.311908 best dqsien dly found for B0: ( 1, 9, 6)
8457 13:43:22.318771 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 13:43:22.319198 Total UI for P1: 0, mck2ui 16
8459 13:43:22.325388 best dqsien dly found for B1: ( 1, 9, 10)
8460 13:43:22.328419 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8461 13:43:22.331926 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8462 13:43:22.332401
8463 13:43:22.335147 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8464 13:43:22.338632 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8465 13:43:22.341906 [Gating] SW calibration Done
8466 13:43:22.342376 ==
8467 13:43:22.344842 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 13:43:22.348525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 13:43:22.348954 ==
8470 13:43:22.351536 RX Vref Scan: 0
8471 13:43:22.352046
8472 13:43:22.352395 RX Vref 0 -> 0, step: 1
8473 13:43:22.352760
8474 13:43:22.354881 RX Delay 0 -> 252, step: 8
8475 13:43:22.358563 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8476 13:43:22.365135 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8477 13:43:22.368544 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8478 13:43:22.371899 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8479 13:43:22.375255 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8480 13:43:22.378851 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8481 13:43:22.381830 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8482 13:43:22.388710 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8483 13:43:22.392198 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8484 13:43:22.395338 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8485 13:43:22.398778 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8486 13:43:22.401885 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8487 13:43:22.408443 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8488 13:43:22.411385 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8489 13:43:22.415022 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8490 13:43:22.418198 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8491 13:43:22.418619 ==
8492 13:43:22.421422 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 13:43:22.428360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 13:43:22.428850 ==
8495 13:43:22.429218 DQS Delay:
8496 13:43:22.431546 DQS0 = 0, DQS1 = 0
8497 13:43:22.432006 DQM Delay:
8498 13:43:22.434559 DQM0 = 137, DQM1 = 129
8499 13:43:22.435022 DQ Delay:
8500 13:43:22.437960 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8501 13:43:22.441606 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8502 13:43:22.444597 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8503 13:43:22.448212 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8504 13:43:22.448682
8505 13:43:22.449052
8506 13:43:22.449444 ==
8507 13:43:22.451237 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 13:43:22.457790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 13:43:22.458265 ==
8510 13:43:22.458639
8511 13:43:22.458983
8512 13:43:22.459316 TX Vref Scan disable
8513 13:43:22.461348 == TX Byte 0 ==
8514 13:43:22.464890 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8515 13:43:22.471478 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 13:43:22.471950 == TX Byte 1 ==
8517 13:43:22.474418 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8518 13:43:22.481435 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 13:43:22.481863 ==
8520 13:43:22.484530 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 13:43:22.487642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 13:43:22.488105 ==
8523 13:43:22.501062
8524 13:43:22.504083 TX Vref early break, caculate TX vref
8525 13:43:22.507578 TX Vref=16, minBit 10, minWin=22, winSum=374
8526 13:43:22.511181 TX Vref=18, minBit 12, minWin=23, winSum=385
8527 13:43:22.514287 TX Vref=20, minBit 9, minWin=24, winSum=398
8528 13:43:22.517828 TX Vref=22, minBit 9, minWin=24, winSum=405
8529 13:43:22.520849 TX Vref=24, minBit 15, minWin=25, winSum=419
8530 13:43:22.527682 TX Vref=26, minBit 15, minWin=25, winSum=422
8531 13:43:22.530770 TX Vref=28, minBit 10, minWin=25, winSum=425
8532 13:43:22.534309 TX Vref=30, minBit 10, minWin=25, winSum=422
8533 13:43:22.537407 TX Vref=32, minBit 10, minWin=24, winSum=412
8534 13:43:22.540964 TX Vref=34, minBit 10, minWin=24, winSum=404
8535 13:43:22.547716 TX Vref=36, minBit 10, minWin=22, winSum=394
8536 13:43:22.550940 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 28
8537 13:43:22.554014
8538 13:43:22.554435 Final TX Range 0 Vref 28
8539 13:43:22.554833
8540 13:43:22.555195 ==
8541 13:43:22.557508 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 13:43:22.564006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 13:43:22.564607 ==
8544 13:43:22.565075
8545 13:43:22.565580
8546 13:43:22.565942 TX Vref Scan disable
8547 13:43:22.570943 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8548 13:43:22.571385 == TX Byte 0 ==
8549 13:43:22.574419 u2DelayCellOfst[0]=17 cells (5 PI)
8550 13:43:22.577978 u2DelayCellOfst[1]=10 cells (3 PI)
8551 13:43:22.581001 u2DelayCellOfst[2]=0 cells (0 PI)
8552 13:43:22.584313 u2DelayCellOfst[3]=3 cells (1 PI)
8553 13:43:22.587760 u2DelayCellOfst[4]=6 cells (2 PI)
8554 13:43:22.591258 u2DelayCellOfst[5]=17 cells (5 PI)
8555 13:43:22.594433 u2DelayCellOfst[6]=17 cells (5 PI)
8556 13:43:22.597835 u2DelayCellOfst[7]=3 cells (1 PI)
8557 13:43:22.601446 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8558 13:43:22.604410 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8559 13:43:22.608029 == TX Byte 1 ==
8560 13:43:22.611079 u2DelayCellOfst[8]=0 cells (0 PI)
8561 13:43:22.614667 u2DelayCellOfst[9]=0 cells (0 PI)
8562 13:43:22.615182 u2DelayCellOfst[10]=6 cells (2 PI)
8563 13:43:22.617759 u2DelayCellOfst[11]=3 cells (1 PI)
8564 13:43:22.621407 u2DelayCellOfst[12]=13 cells (4 PI)
8565 13:43:22.624358 u2DelayCellOfst[13]=10 cells (3 PI)
8566 13:43:22.628069 u2DelayCellOfst[14]=13 cells (4 PI)
8567 13:43:22.630938 u2DelayCellOfst[15]=10 cells (3 PI)
8568 13:43:22.637567 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8569 13:43:22.641128 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8570 13:43:22.641670 DramC Write-DBI on
8571 13:43:22.642147 ==
8572 13:43:22.644642 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 13:43:22.650839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 13:43:22.651253 ==
8575 13:43:22.651678
8576 13:43:22.652063
8577 13:43:22.652392 TX Vref Scan disable
8578 13:43:22.655013 == TX Byte 0 ==
8579 13:43:22.658071 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8580 13:43:22.661402 == TX Byte 1 ==
8581 13:43:22.664582 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8582 13:43:22.668156 DramC Write-DBI off
8583 13:43:22.668723
8584 13:43:22.669217 [DATLAT]
8585 13:43:22.669747 Freq=1600, CH1 RK0
8586 13:43:22.670229
8587 13:43:22.671209 DATLAT Default: 0xf
8588 13:43:22.671783 0, 0xFFFF, sum = 0
8589 13:43:22.674710 1, 0xFFFF, sum = 0
8590 13:43:22.678259 2, 0xFFFF, sum = 0
8591 13:43:22.678707 3, 0xFFFF, sum = 0
8592 13:43:22.681384 4, 0xFFFF, sum = 0
8593 13:43:22.681854 5, 0xFFFF, sum = 0
8594 13:43:22.684565 6, 0xFFFF, sum = 0
8595 13:43:22.685019 7, 0xFFFF, sum = 0
8596 13:43:22.688109 8, 0xFFFF, sum = 0
8597 13:43:22.688600 9, 0xFFFF, sum = 0
8598 13:43:22.691205 10, 0xFFFF, sum = 0
8599 13:43:22.691661 11, 0xFFFF, sum = 0
8600 13:43:22.694776 12, 0xFFFF, sum = 0
8601 13:43:22.695229 13, 0xFFFF, sum = 0
8602 13:43:22.698386 14, 0x0, sum = 1
8603 13:43:22.698849 15, 0x0, sum = 2
8604 13:43:22.701173 16, 0x0, sum = 3
8605 13:43:22.701765 17, 0x0, sum = 4
8606 13:43:22.704520 best_step = 15
8607 13:43:22.704996
8608 13:43:22.705504 ==
8609 13:43:22.708149 Dram Type= 6, Freq= 0, CH_1, rank 0
8610 13:43:22.711087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8611 13:43:22.711513 ==
8612 13:43:22.714688 RX Vref Scan: 1
8613 13:43:22.715180
8614 13:43:22.715566 Set Vref Range= 24 -> 127
8615 13:43:22.715897
8616 13:43:22.717895 RX Vref 24 -> 127, step: 1
8617 13:43:22.718415
8618 13:43:22.721466 RX Delay 19 -> 252, step: 4
8619 13:43:22.721892
8620 13:43:22.724481 Set Vref, RX VrefLevel [Byte0]: 24
8621 13:43:22.727994 [Byte1]: 24
8622 13:43:22.728420
8623 13:43:22.731045 Set Vref, RX VrefLevel [Byte0]: 25
8624 13:43:22.734508 [Byte1]: 25
8625 13:43:22.734932
8626 13:43:22.737430 Set Vref, RX VrefLevel [Byte0]: 26
8627 13:43:22.740953 [Byte1]: 26
8628 13:43:22.745031
8629 13:43:22.745485 Set Vref, RX VrefLevel [Byte0]: 27
8630 13:43:22.748732 [Byte1]: 27
8631 13:43:22.752636
8632 13:43:22.753053 Set Vref, RX VrefLevel [Byte0]: 28
8633 13:43:22.755626 [Byte1]: 28
8634 13:43:22.759910
8635 13:43:22.759991 Set Vref, RX VrefLevel [Byte0]: 29
8636 13:43:22.763235 [Byte1]: 29
8637 13:43:22.767802
8638 13:43:22.767883 Set Vref, RX VrefLevel [Byte0]: 30
8639 13:43:22.770946 [Byte1]: 30
8640 13:43:22.774919
8641 13:43:22.775008 Set Vref, RX VrefLevel [Byte0]: 31
8642 13:43:22.778541 [Byte1]: 31
8643 13:43:22.782560
8644 13:43:22.782662 Set Vref, RX VrefLevel [Byte0]: 32
8645 13:43:22.786259 [Byte1]: 32
8646 13:43:22.790403
8647 13:43:22.790553 Set Vref, RX VrefLevel [Byte0]: 33
8648 13:43:22.793331 [Byte1]: 33
8649 13:43:22.798141
8650 13:43:22.798275 Set Vref, RX VrefLevel [Byte0]: 34
8651 13:43:22.801138 [Byte1]: 34
8652 13:43:22.805466
8653 13:43:22.805548 Set Vref, RX VrefLevel [Byte0]: 35
8654 13:43:22.808843 [Byte1]: 35
8655 13:43:22.812687
8656 13:43:22.812768 Set Vref, RX VrefLevel [Byte0]: 36
8657 13:43:22.816317 [Byte1]: 36
8658 13:43:22.820688
8659 13:43:22.820772 Set Vref, RX VrefLevel [Byte0]: 37
8660 13:43:22.823910 [Byte1]: 37
8661 13:43:22.827906
8662 13:43:22.828000 Set Vref, RX VrefLevel [Byte0]: 38
8663 13:43:22.831486 [Byte1]: 38
8664 13:43:22.835602
8665 13:43:22.835704 Set Vref, RX VrefLevel [Byte0]: 39
8666 13:43:22.839199 [Byte1]: 39
8667 13:43:22.843363
8668 13:43:22.843484 Set Vref, RX VrefLevel [Byte0]: 40
8669 13:43:22.846389 [Byte1]: 40
8670 13:43:22.851145
8671 13:43:22.851286 Set Vref, RX VrefLevel [Byte0]: 41
8672 13:43:22.854130 [Byte1]: 41
8673 13:43:22.858567
8674 13:43:22.858737 Set Vref, RX VrefLevel [Byte0]: 42
8675 13:43:22.861634 [Byte1]: 42
8676 13:43:22.866264
8677 13:43:22.866464 Set Vref, RX VrefLevel [Byte0]: 43
8678 13:43:22.869338 [Byte1]: 43
8679 13:43:22.873886
8680 13:43:22.874181 Set Vref, RX VrefLevel [Byte0]: 44
8681 13:43:22.876819 [Byte1]: 44
8682 13:43:22.881448
8683 13:43:22.881827 Set Vref, RX VrefLevel [Byte0]: 45
8684 13:43:22.884541 [Byte1]: 45
8685 13:43:22.889142
8686 13:43:22.889606 Set Vref, RX VrefLevel [Byte0]: 46
8687 13:43:22.892181 [Byte1]: 46
8688 13:43:22.896758
8689 13:43:22.897214 Set Vref, RX VrefLevel [Byte0]: 47
8690 13:43:22.899909 [Byte1]: 47
8691 13:43:22.904513
8692 13:43:22.905173 Set Vref, RX VrefLevel [Byte0]: 48
8693 13:43:22.907406 [Byte1]: 48
8694 13:43:22.911932
8695 13:43:22.912536 Set Vref, RX VrefLevel [Byte0]: 49
8696 13:43:22.914748 [Byte1]: 49
8697 13:43:22.919458
8698 13:43:22.919961 Set Vref, RX VrefLevel [Byte0]: 50
8699 13:43:22.922543 [Byte1]: 50
8700 13:43:22.927175
8701 13:43:22.927637 Set Vref, RX VrefLevel [Byte0]: 51
8702 13:43:22.930155 [Byte1]: 51
8703 13:43:22.934365
8704 13:43:22.934871 Set Vref, RX VrefLevel [Byte0]: 52
8705 13:43:22.937902 [Byte1]: 52
8706 13:43:22.942038
8707 13:43:22.942593 Set Vref, RX VrefLevel [Byte0]: 53
8708 13:43:22.945078 [Byte1]: 53
8709 13:43:22.949598
8710 13:43:22.950064 Set Vref, RX VrefLevel [Byte0]: 54
8711 13:43:22.952676 [Byte1]: 54
8712 13:43:22.957092
8713 13:43:22.957597 Set Vref, RX VrefLevel [Byte0]: 55
8714 13:43:22.960343 [Byte1]: 55
8715 13:43:22.964509
8716 13:43:22.964971 Set Vref, RX VrefLevel [Byte0]: 56
8717 13:43:22.968036 [Byte1]: 56
8718 13:43:22.972665
8719 13:43:22.973195 Set Vref, RX VrefLevel [Byte0]: 57
8720 13:43:22.975831 [Byte1]: 57
8721 13:43:22.979649
8722 13:43:22.980113 Set Vref, RX VrefLevel [Byte0]: 58
8723 13:43:22.983331 [Byte1]: 58
8724 13:43:22.987457
8725 13:43:22.987928 Set Vref, RX VrefLevel [Byte0]: 59
8726 13:43:22.990562 [Byte1]: 59
8727 13:43:22.995229
8728 13:43:22.995696 Set Vref, RX VrefLevel [Byte0]: 60
8729 13:43:22.998273 [Byte1]: 60
8730 13:43:23.002929
8731 13:43:23.003400 Set Vref, RX VrefLevel [Byte0]: 61
8732 13:43:23.005954 [Byte1]: 61
8733 13:43:23.009935
8734 13:43:23.010406 Set Vref, RX VrefLevel [Byte0]: 62
8735 13:43:23.013436 [Byte1]: 62
8736 13:43:23.017803
8737 13:43:23.018249 Set Vref, RX VrefLevel [Byte0]: 63
8738 13:43:23.020891 [Byte1]: 63
8739 13:43:23.025541
8740 13:43:23.025966 Set Vref, RX VrefLevel [Byte0]: 64
8741 13:43:23.028244 [Byte1]: 64
8742 13:43:23.032301
8743 13:43:23.032381 Set Vref, RX VrefLevel [Byte0]: 65
8744 13:43:23.035845 [Byte1]: 65
8745 13:43:23.039981
8746 13:43:23.040062 Set Vref, RX VrefLevel [Byte0]: 66
8747 13:43:23.043613 [Byte1]: 66
8748 13:43:23.047939
8749 13:43:23.048024 Set Vref, RX VrefLevel [Byte0]: 67
8750 13:43:23.051000 [Byte1]: 67
8751 13:43:23.055305
8752 13:43:23.055387 Set Vref, RX VrefLevel [Byte0]: 68
8753 13:43:23.058263 [Byte1]: 68
8754 13:43:23.062948
8755 13:43:23.063029 Set Vref, RX VrefLevel [Byte0]: 69
8756 13:43:23.066221 [Byte1]: 69
8757 13:43:23.070317
8758 13:43:23.070399 Set Vref, RX VrefLevel [Byte0]: 70
8759 13:43:23.073473 [Byte1]: 70
8760 13:43:23.077794
8761 13:43:23.077876 Set Vref, RX VrefLevel [Byte0]: 71
8762 13:43:23.081242 [Byte1]: 71
8763 13:43:23.085273
8764 13:43:23.085398 Set Vref, RX VrefLevel [Byte0]: 72
8765 13:43:23.088967 [Byte1]: 72
8766 13:43:23.092931
8767 13:43:23.093012 Final RX Vref Byte 0 = 51 to rank0
8768 13:43:23.096524 Final RX Vref Byte 1 = 64 to rank0
8769 13:43:23.099571 Final RX Vref Byte 0 = 51 to rank1
8770 13:43:23.103210 Final RX Vref Byte 1 = 64 to rank1==
8771 13:43:23.106385 Dram Type= 6, Freq= 0, CH_1, rank 0
8772 13:43:23.113159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 13:43:23.113267 ==
8774 13:43:23.113353 DQS Delay:
8775 13:43:23.113415 DQS0 = 0, DQS1 = 0
8776 13:43:23.116307 DQM Delay:
8777 13:43:23.116388 DQM0 = 133, DQM1 = 128
8778 13:43:23.119755 DQ Delay:
8779 13:43:23.123009 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8780 13:43:23.126628 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8781 13:43:23.129654 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8782 13:43:23.132905 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =136
8783 13:43:23.132986
8784 13:43:23.133050
8785 13:43:23.133109
8786 13:43:23.136297 [DramC_TX_OE_Calibration] TA2
8787 13:43:23.139504 Original DQ_B0 (3 6) =30, OEN = 27
8788 13:43:23.142990 Original DQ_B1 (3 6) =30, OEN = 27
8789 13:43:23.146028 24, 0x0, End_B0=24 End_B1=24
8790 13:43:23.146112 25, 0x0, End_B0=25 End_B1=25
8791 13:43:23.149590 26, 0x0, End_B0=26 End_B1=26
8792 13:43:23.152790 27, 0x0, End_B0=27 End_B1=27
8793 13:43:23.156211 28, 0x0, End_B0=28 End_B1=28
8794 13:43:23.156293 29, 0x0, End_B0=29 End_B1=29
8795 13:43:23.159642 30, 0x0, End_B0=30 End_B1=30
8796 13:43:23.162820 31, 0x5151, End_B0=30 End_B1=30
8797 13:43:23.166396 Byte0 end_step=30 best_step=27
8798 13:43:23.169561 Byte1 end_step=30 best_step=27
8799 13:43:23.172628 Byte0 TX OE(2T, 0.5T) = (3, 3)
8800 13:43:23.172736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8801 13:43:23.176382
8802 13:43:23.176505
8803 13:43:23.182752 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8804 13:43:23.186502 CH1 RK0: MR19=303, MR18=1927
8805 13:43:23.192875 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8806 13:43:23.192979
8807 13:43:23.196094 ----->DramcWriteLeveling(PI) begin...
8808 13:43:23.196171 ==
8809 13:43:23.199680 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 13:43:23.203135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 13:43:23.203234 ==
8812 13:43:23.206296 Write leveling (Byte 0): 24 => 24
8813 13:43:23.209872 Write leveling (Byte 1): 29 => 29
8814 13:43:23.212967 DramcWriteLeveling(PI) end<-----
8815 13:43:23.213054
8816 13:43:23.213126 ==
8817 13:43:23.216541 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 13:43:23.219657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 13:43:23.219750 ==
8820 13:43:23.223137 [Gating] SW mode calibration
8821 13:43:23.230049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8822 13:43:23.236557 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8823 13:43:23.239602 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 13:43:23.243071 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 13:43:23.249764 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8826 13:43:23.252839 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)
8827 13:43:23.256380 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 13:43:23.263144 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 13:43:23.266140 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 13:43:23.269263 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 13:43:23.276420 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 13:43:23.279560 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 13:43:23.283069 1 5 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
8834 13:43:23.289412 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (1 0) (0 1)
8835 13:43:23.292489 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8836 13:43:23.296141 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 13:43:23.302517 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 13:43:23.306096 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 13:43:23.309173 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 13:43:23.315888 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 13:43:23.319487 1 6 8 | B1->B0 | 3a3a 2323 | 0 0 | (1 1) (0 0)
8842 13:43:23.322604 1 6 12 | B1->B0 | 4646 3a3a | 0 0 | (0 0) (0 0)
8843 13:43:23.329067 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8844 13:43:23.332478 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 13:43:23.336142 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 13:43:23.339056 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 13:43:23.345560 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 13:43:23.349181 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 13:43:23.352265 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8850 13:43:23.359083 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8851 13:43:23.362036 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 13:43:23.365634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 13:43:23.372099 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 13:43:23.375670 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 13:43:23.378738 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 13:43:23.385815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 13:43:23.389092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 13:43:23.391905 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 13:43:23.398860 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 13:43:23.401814 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 13:43:23.405090 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 13:43:23.412019 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 13:43:23.414866 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 13:43:23.418504 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 13:43:23.425134 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8866 13:43:23.428205 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8867 13:43:23.431920 Total UI for P1: 0, mck2ui 16
8868 13:43:23.435323 best dqsien dly found for B1: ( 1, 9, 8)
8869 13:43:23.438622 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 13:43:23.441716 Total UI for P1: 0, mck2ui 16
8871 13:43:23.445107 best dqsien dly found for B0: ( 1, 9, 10)
8872 13:43:23.448640 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8873 13:43:23.451655 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8874 13:43:23.451739
8875 13:43:23.458409 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8876 13:43:23.461968 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8877 13:43:23.462051 [Gating] SW calibration Done
8878 13:43:23.465120 ==
8879 13:43:23.468678 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 13:43:23.471717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 13:43:23.471800 ==
8882 13:43:23.471866 RX Vref Scan: 0
8883 13:43:23.471926
8884 13:43:23.475288 RX Vref 0 -> 0, step: 1
8885 13:43:23.475371
8886 13:43:23.478323 RX Delay 0 -> 252, step: 8
8887 13:43:23.481816 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8888 13:43:23.484967 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8889 13:43:23.488625 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8890 13:43:23.495269 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8891 13:43:23.498252 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8892 13:43:23.501702 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8893 13:43:23.505407 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8894 13:43:23.508417 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8895 13:43:23.511950 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8896 13:43:23.518288 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8897 13:43:23.521608 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8898 13:43:23.524797 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8899 13:43:23.528479 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8900 13:43:23.535076 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8901 13:43:23.538087 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8902 13:43:23.541558 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8903 13:43:23.541641 ==
8904 13:43:23.545023 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 13:43:23.548132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 13:43:23.548215 ==
8907 13:43:23.551634 DQS Delay:
8908 13:43:23.551716 DQS0 = 0, DQS1 = 0
8909 13:43:23.554618 DQM Delay:
8910 13:43:23.554701 DQM0 = 138, DQM1 = 130
8911 13:43:23.554766 DQ Delay:
8912 13:43:23.558038 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8913 13:43:23.564859 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8914 13:43:23.568443 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8915 13:43:23.571356 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8916 13:43:23.571439
8917 13:43:23.571504
8918 13:43:23.571563 ==
8919 13:43:23.574623 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 13:43:23.578155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 13:43:23.578239 ==
8922 13:43:23.578304
8923 13:43:23.578363
8924 13:43:23.581620 TX Vref Scan disable
8925 13:43:23.584750 == TX Byte 0 ==
8926 13:43:23.588402 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8927 13:43:23.591381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8928 13:43:23.594457 == TX Byte 1 ==
8929 13:43:23.598060 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8930 13:43:23.601639 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8931 13:43:23.601722 ==
8932 13:43:23.604975 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 13:43:23.608126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 13:43:23.608210 ==
8935 13:43:23.623424
8936 13:43:23.626689 TX Vref early break, caculate TX vref
8937 13:43:23.630083 TX Vref=16, minBit 13, minWin=22, winSum=383
8938 13:43:23.633208 TX Vref=18, minBit 9, minWin=23, winSum=394
8939 13:43:23.636918 TX Vref=20, minBit 13, minWin=24, winSum=405
8940 13:43:23.639932 TX Vref=22, minBit 9, minWin=24, winSum=413
8941 13:43:23.643513 TX Vref=24, minBit 9, minWin=25, winSum=420
8942 13:43:23.650221 TX Vref=26, minBit 13, minWin=25, winSum=425
8943 13:43:23.653110 TX Vref=28, minBit 10, minWin=25, winSum=427
8944 13:43:23.656857 TX Vref=30, minBit 2, minWin=25, winSum=419
8945 13:43:23.660020 TX Vref=32, minBit 0, minWin=25, winSum=409
8946 13:43:23.663669 TX Vref=34, minBit 10, minWin=23, winSum=405
8947 13:43:23.669865 TX Vref=36, minBit 10, minWin=23, winSum=393
8948 13:43:23.673523 [TxChooseVref] Worse bit 10, Min win 25, Win sum 427, Final Vref 28
8949 13:43:23.673601
8950 13:43:23.676632 Final TX Range 0 Vref 28
8951 13:43:23.676731
8952 13:43:23.676822 ==
8953 13:43:23.680116 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 13:43:23.683161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 13:43:23.686786 ==
8956 13:43:23.686860
8957 13:43:23.686922
8958 13:43:23.686981 TX Vref Scan disable
8959 13:43:23.693647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8960 13:43:23.693750 == TX Byte 0 ==
8961 13:43:23.696829 u2DelayCellOfst[0]=13 cells (4 PI)
8962 13:43:23.700044 u2DelayCellOfst[1]=10 cells (3 PI)
8963 13:43:23.703623 u2DelayCellOfst[2]=0 cells (0 PI)
8964 13:43:23.706684 u2DelayCellOfst[3]=3 cells (1 PI)
8965 13:43:23.710271 u2DelayCellOfst[4]=6 cells (2 PI)
8966 13:43:23.713522 u2DelayCellOfst[5]=17 cells (5 PI)
8967 13:43:23.716607 u2DelayCellOfst[6]=13 cells (4 PI)
8968 13:43:23.720034 u2DelayCellOfst[7]=3 cells (1 PI)
8969 13:43:23.723092 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8970 13:43:23.726774 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8971 13:43:23.730211 == TX Byte 1 ==
8972 13:43:23.733430 u2DelayCellOfst[8]=0 cells (0 PI)
8973 13:43:23.736638 u2DelayCellOfst[9]=3 cells (1 PI)
8974 13:43:23.736727 u2DelayCellOfst[10]=10 cells (3 PI)
8975 13:43:23.739800 u2DelayCellOfst[11]=3 cells (1 PI)
8976 13:43:23.743488 u2DelayCellOfst[12]=13 cells (4 PI)
8977 13:43:23.746804 u2DelayCellOfst[13]=13 cells (4 PI)
8978 13:43:23.750078 u2DelayCellOfst[14]=17 cells (5 PI)
8979 13:43:23.753135 u2DelayCellOfst[15]=13 cells (4 PI)
8980 13:43:23.760118 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8981 13:43:23.763286 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8982 13:43:23.763362 DramC Write-DBI on
8983 13:43:23.763432 ==
8984 13:43:23.766550 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 13:43:23.772908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 13:43:23.773016 ==
8987 13:43:23.773112
8988 13:43:23.773205
8989 13:43:23.773321 TX Vref Scan disable
8990 13:43:23.776998 == TX Byte 0 ==
8991 13:43:23.780700 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8992 13:43:23.784152 == TX Byte 1 ==
8993 13:43:23.787208 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8994 13:43:23.790565 DramC Write-DBI off
8995 13:43:23.790637
8996 13:43:23.790701 [DATLAT]
8997 13:43:23.790764 Freq=1600, CH1 RK1
8998 13:43:23.790830
8999 13:43:23.793548 DATLAT Default: 0xf
9000 13:43:23.793619 0, 0xFFFF, sum = 0
9001 13:43:23.797175 1, 0xFFFF, sum = 0
9002 13:43:23.797275 2, 0xFFFF, sum = 0
9003 13:43:23.800501 3, 0xFFFF, sum = 0
9004 13:43:23.804017 4, 0xFFFF, sum = 0
9005 13:43:23.804118 5, 0xFFFF, sum = 0
9006 13:43:23.807081 6, 0xFFFF, sum = 0
9007 13:43:23.807181 7, 0xFFFF, sum = 0
9008 13:43:23.810769 8, 0xFFFF, sum = 0
9009 13:43:23.810868 9, 0xFFFF, sum = 0
9010 13:43:23.813723 10, 0xFFFF, sum = 0
9011 13:43:23.813799 11, 0xFFFF, sum = 0
9012 13:43:23.817430 12, 0xFFFF, sum = 0
9013 13:43:23.817502 13, 0xFFFF, sum = 0
9014 13:43:23.820539 14, 0x0, sum = 1
9015 13:43:23.820610 15, 0x0, sum = 2
9016 13:43:23.823597 16, 0x0, sum = 3
9017 13:43:23.823669 17, 0x0, sum = 4
9018 13:43:23.827079 best_step = 15
9019 13:43:23.827150
9020 13:43:23.827212 ==
9021 13:43:23.830710 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 13:43:23.833639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 13:43:23.833714 ==
9024 13:43:23.836962 RX Vref Scan: 0
9025 13:43:23.837033
9026 13:43:23.837094 RX Vref 0 -> 0, step: 1
9027 13:43:23.837152
9028 13:43:23.840363 RX Delay 19 -> 252, step: 4
9029 13:43:23.843578 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9030 13:43:23.850332 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9031 13:43:23.853503 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
9032 13:43:23.856843 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9033 13:43:23.860022 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9034 13:43:23.863309 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9035 13:43:23.866683 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9036 13:43:23.873277 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9037 13:43:23.877083 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9038 13:43:23.879913 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9039 13:43:23.883849 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9040 13:43:23.886597 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9041 13:43:23.893430 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9042 13:43:23.896506 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9043 13:43:23.900156 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9044 13:43:23.903190 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9045 13:43:23.903273 ==
9046 13:43:23.906332 Dram Type= 6, Freq= 0, CH_1, rank 1
9047 13:43:23.913675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9048 13:43:23.913758 ==
9049 13:43:23.913823 DQS Delay:
9050 13:43:23.916680 DQS0 = 0, DQS1 = 0
9051 13:43:23.916762 DQM Delay:
9052 13:43:23.916827 DQM0 = 133, DQM1 = 129
9053 13:43:23.920259 DQ Delay:
9054 13:43:23.923527 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9055 13:43:23.926976 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =130
9056 13:43:23.929812 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9057 13:43:23.933258 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =140
9058 13:43:23.933379
9059 13:43:23.933445
9060 13:43:23.933506
9061 13:43:23.936431 [DramC_TX_OE_Calibration] TA2
9062 13:43:23.940075 Original DQ_B0 (3 6) =30, OEN = 27
9063 13:43:23.943043 Original DQ_B1 (3 6) =30, OEN = 27
9064 13:43:23.946454 24, 0x0, End_B0=24 End_B1=24
9065 13:43:23.946537 25, 0x0, End_B0=25 End_B1=25
9066 13:43:23.949787 26, 0x0, End_B0=26 End_B1=26
9067 13:43:23.953168 27, 0x0, End_B0=27 End_B1=27
9068 13:43:23.956692 28, 0x0, End_B0=28 End_B1=28
9069 13:43:23.960032 29, 0x0, End_B0=29 End_B1=29
9070 13:43:23.960116 30, 0x0, End_B0=30 End_B1=30
9071 13:43:23.963018 31, 0x4141, End_B0=30 End_B1=30
9072 13:43:23.966481 Byte0 end_step=30 best_step=27
9073 13:43:23.969920 Byte1 end_step=30 best_step=27
9074 13:43:23.973424 Byte0 TX OE(2T, 0.5T) = (3, 3)
9075 13:43:23.976235 Byte1 TX OE(2T, 0.5T) = (3, 3)
9076 13:43:23.976316
9077 13:43:23.976381
9078 13:43:23.983100 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
9079 13:43:23.986787 CH1 RK1: MR19=303, MR18=1F0B
9080 13:43:23.993294 CH1_RK1: MR19=0x303, MR18=0x1F0B, DQSOSC=394, MR23=63, INC=23, DEC=15
9081 13:43:23.996340 [RxdqsGatingPostProcess] freq 1600
9082 13:43:23.999661 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9083 13:43:24.003097 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 13:43:24.006205 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 13:43:24.009695 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 13:43:24.013124 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 13:43:24.016178 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 13:43:24.019755 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 13:43:24.022905 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 13:43:24.025928 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 13:43:24.029659 Pre-setting of DQS Precalculation
9092 13:43:24.032993 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9093 13:43:24.039780 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9094 13:43:24.046410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 13:43:24.049411
9096 13:43:24.049494
9097 13:43:24.049561 [Calibration Summary] 3200 Mbps
9098 13:43:24.052753 CH 0, Rank 0
9099 13:43:24.052837 SW Impedance : PASS
9100 13:43:24.056352 DUTY Scan : NO K
9101 13:43:24.059267 ZQ Calibration : PASS
9102 13:43:24.059350 Jitter Meter : NO K
9103 13:43:24.062795 CBT Training : PASS
9104 13:43:24.066276 Write leveling : PASS
9105 13:43:24.066359 RX DQS gating : PASS
9106 13:43:24.069720 RX DQ/DQS(RDDQC) : PASS
9107 13:43:24.072812 TX DQ/DQS : PASS
9108 13:43:24.072896 RX DATLAT : PASS
9109 13:43:24.076146 RX DQ/DQS(Engine): PASS
9110 13:43:24.079449 TX OE : PASS
9111 13:43:24.079533 All Pass.
9112 13:43:24.079599
9113 13:43:24.079663 CH 0, Rank 1
9114 13:43:24.082893 SW Impedance : PASS
9115 13:43:24.086133 DUTY Scan : NO K
9116 13:43:24.086217 ZQ Calibration : PASS
9117 13:43:24.089174 Jitter Meter : NO K
9118 13:43:24.093015 CBT Training : PASS
9119 13:43:24.093100 Write leveling : PASS
9120 13:43:24.095998 RX DQS gating : PASS
9121 13:43:24.096083 RX DQ/DQS(RDDQC) : PASS
9122 13:43:24.099170 TX DQ/DQS : PASS
9123 13:43:24.102755 RX DATLAT : PASS
9124 13:43:24.102840 RX DQ/DQS(Engine): PASS
9125 13:43:24.105709 TX OE : PASS
9126 13:43:24.105794 All Pass.
9127 13:43:24.105879
9128 13:43:24.109273 CH 1, Rank 0
9129 13:43:24.109396 SW Impedance : PASS
9130 13:43:24.112311 DUTY Scan : NO K
9131 13:43:24.116169 ZQ Calibration : PASS
9132 13:43:24.116254 Jitter Meter : NO K
9133 13:43:24.119074 CBT Training : PASS
9134 13:43:24.122654 Write leveling : PASS
9135 13:43:24.122739 RX DQS gating : PASS
9136 13:43:24.125755 RX DQ/DQS(RDDQC) : PASS
9137 13:43:24.128849 TX DQ/DQS : PASS
9138 13:43:24.128934 RX DATLAT : PASS
9139 13:43:24.132401 RX DQ/DQS(Engine): PASS
9140 13:43:24.135963 TX OE : PASS
9141 13:43:24.136048 All Pass.
9142 13:43:24.136131
9143 13:43:24.136210 CH 1, Rank 1
9144 13:43:24.138903 SW Impedance : PASS
9145 13:43:24.142311 DUTY Scan : NO K
9146 13:43:24.142396 ZQ Calibration : PASS
9147 13:43:24.145956 Jitter Meter : NO K
9148 13:43:24.149245 CBT Training : PASS
9149 13:43:24.149348 Write leveling : PASS
9150 13:43:24.152131 RX DQS gating : PASS
9151 13:43:24.152213 RX DQ/DQS(RDDQC) : PASS
9152 13:43:24.155675 TX DQ/DQS : PASS
9153 13:43:24.159001 RX DATLAT : PASS
9154 13:43:24.159083 RX DQ/DQS(Engine): PASS
9155 13:43:24.162609 TX OE : PASS
9156 13:43:24.162691 All Pass.
9157 13:43:24.162755
9158 13:43:24.165627 DramC Write-DBI on
9159 13:43:24.169108 PER_BANK_REFRESH: Hybrid Mode
9160 13:43:24.169190 TX_TRACKING: ON
9161 13:43:24.179004 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9162 13:43:24.185664 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9163 13:43:24.192530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9164 13:43:24.198992 [FAST_K] Save calibration result to emmc
9165 13:43:24.199075 sync common calibartion params.
9166 13:43:24.202540 sync cbt_mode0:1, 1:1
9167 13:43:24.205661 dram_init: ddr_geometry: 2
9168 13:43:24.205744 dram_init: ddr_geometry: 2
9169 13:43:24.209255 dram_init: ddr_geometry: 2
9170 13:43:24.212394 0:dram_rank_size:100000000
9171 13:43:24.215943 1:dram_rank_size:100000000
9172 13:43:24.219004 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9173 13:43:24.222125 DFS_SHUFFLE_HW_MODE: ON
9174 13:43:24.225634 dramc_set_vcore_voltage set vcore to 725000
9175 13:43:24.229227 Read voltage for 1600, 0
9176 13:43:24.229334 Vio18 = 0
9177 13:43:24.229403 Vcore = 725000
9178 13:43:24.232327 Vdram = 0
9179 13:43:24.232410 Vddq = 0
9180 13:43:24.232473 Vmddr = 0
9181 13:43:24.235580 switch to 3200 Mbps bootup
9182 13:43:24.239015 [DramcRunTimeConfig]
9183 13:43:24.239117 PHYPLL
9184 13:43:24.239237 DPM_CONTROL_AFTERK: ON
9185 13:43:24.242414 PER_BANK_REFRESH: ON
9186 13:43:24.245797 REFRESH_OVERHEAD_REDUCTION: ON
9187 13:43:24.245884 CMD_PICG_NEW_MODE: OFF
9188 13:43:24.248882 XRTWTW_NEW_MODE: ON
9189 13:43:24.251991 XRTRTR_NEW_MODE: ON
9190 13:43:24.252075 TX_TRACKING: ON
9191 13:43:24.255577 RDSEL_TRACKING: OFF
9192 13:43:24.255662 DQS Precalculation for DVFS: ON
9193 13:43:24.258621 RX_TRACKING: OFF
9194 13:43:24.258704 HW_GATING DBG: ON
9195 13:43:24.262139 ZQCS_ENABLE_LP4: ON
9196 13:43:24.262257 RX_PICG_NEW_MODE: ON
9197 13:43:24.265179 TX_PICG_NEW_MODE: ON
9198 13:43:24.268408 ENABLE_RX_DCM_DPHY: ON
9199 13:43:24.271723 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9200 13:43:24.271813 DUMMY_READ_FOR_TRACKING: OFF
9201 13:43:24.275153 !!! SPM_CONTROL_AFTERK: OFF
9202 13:43:24.278770 !!! SPM could not control APHY
9203 13:43:24.281846 IMPEDANCE_TRACKING: ON
9204 13:43:24.281930 TEMP_SENSOR: ON
9205 13:43:24.285268 HW_SAVE_FOR_SR: OFF
9206 13:43:24.285505 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9207 13:43:24.292098 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9208 13:43:24.292204 Read ODT Tracking: ON
9209 13:43:24.295391 Refresh Rate DeBounce: ON
9210 13:43:24.295475 DFS_NO_QUEUE_FLUSH: ON
9211 13:43:24.299008 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9212 13:43:24.302147 ENABLE_DFS_RUNTIME_MRW: OFF
9213 13:43:24.305651 DDR_RESERVE_NEW_MODE: ON
9214 13:43:24.305741 MR_CBT_SWITCH_FREQ: ON
9215 13:43:24.308665 =========================
9216 13:43:24.328233 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9217 13:43:24.331368 dram_init: ddr_geometry: 2
9218 13:43:24.349778 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9219 13:43:24.353497 dram_init: dram init end (result: 0)
9220 13:43:24.360274 DRAM-K: Full calibration passed in 24521 msecs
9221 13:43:24.363494 MRC: failed to locate region type 0.
9222 13:43:24.363963 DRAM rank0 size:0x100000000,
9223 13:43:24.366485 DRAM rank1 size=0x100000000
9224 13:43:24.376854 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9225 13:43:24.383392 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9226 13:43:24.389639 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9227 13:43:24.396501 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9228 13:43:24.399641 DRAM rank0 size:0x100000000,
9229 13:43:24.403002 DRAM rank1 size=0x100000000
9230 13:43:24.403467 CBMEM:
9231 13:43:24.406511 IMD: root @ 0xfffff000 254 entries.
9232 13:43:24.410045 IMD: root @ 0xffffec00 62 entries.
9233 13:43:24.413208 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9234 13:43:24.416274 WARNING: RO_VPD is uninitialized or empty.
9235 13:43:24.422869 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9236 13:43:24.429989 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9237 13:43:24.443027 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9238 13:43:24.454121 BS: romstage times (exec / console): total (unknown) / 24018 ms
9239 13:43:24.454665
9240 13:43:24.455037
9241 13:43:24.464041 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9242 13:43:24.467646 ARM64: Exception handlers installed.
9243 13:43:24.471187 ARM64: Testing exception
9244 13:43:24.474121 ARM64: Done test exception
9245 13:43:24.474589 Enumerating buses...
9246 13:43:24.477511 Show all devs... Before device enumeration.
9247 13:43:24.480747 Root Device: enabled 1
9248 13:43:24.483954 CPU_CLUSTER: 0: enabled 1
9249 13:43:24.484416 CPU: 00: enabled 1
9250 13:43:24.487553 Compare with tree...
9251 13:43:24.488022 Root Device: enabled 1
9252 13:43:24.490713 CPU_CLUSTER: 0: enabled 1
9253 13:43:24.494249 CPU: 00: enabled 1
9254 13:43:24.494713 Root Device scanning...
9255 13:43:24.497366 scan_static_bus for Root Device
9256 13:43:24.500330 CPU_CLUSTER: 0 enabled
9257 13:43:24.503901 scan_static_bus for Root Device done
9258 13:43:24.507202 scan_bus: bus Root Device finished in 8 msecs
9259 13:43:24.507670 done
9260 13:43:24.513716 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9261 13:43:24.517225 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9262 13:43:24.523720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9263 13:43:24.526954 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9264 13:43:24.530561 Allocating resources...
9265 13:43:24.533671 Reading resources...
9266 13:43:24.537353 Root Device read_resources bus 0 link: 0
9267 13:43:24.537820 DRAM rank0 size:0x100000000,
9268 13:43:24.540527 DRAM rank1 size=0x100000000
9269 13:43:24.543576 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9270 13:43:24.546977 CPU: 00 missing read_resources
9271 13:43:24.553649 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9272 13:43:24.557220 Root Device read_resources bus 0 link: 0 done
9273 13:43:24.557687 Done reading resources.
9274 13:43:24.563579 Show resources in subtree (Root Device)...After reading.
9275 13:43:24.567051 Root Device child on link 0 CPU_CLUSTER: 0
9276 13:43:24.570100 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 13:43:24.580089 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 13:43:24.580784 CPU: 00
9279 13:43:24.583427 Root Device assign_resources, bus 0 link: 0
9280 13:43:24.586629 CPU_CLUSTER: 0 missing set_resources
9281 13:43:24.593496 Root Device assign_resources, bus 0 link: 0 done
9282 13:43:24.593929 Done setting resources.
9283 13:43:24.600146 Show resources in subtree (Root Device)...After assigning values.
9284 13:43:24.603344 Root Device child on link 0 CPU_CLUSTER: 0
9285 13:43:24.606931 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 13:43:24.616621 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 13:43:24.617099 CPU: 00
9288 13:43:24.620241 Done allocating resources.
9289 13:43:24.623346 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9290 13:43:24.626803 Enabling resources...
9291 13:43:24.627273 done.
9292 13:43:24.633380 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9293 13:43:24.633808 Initializing devices...
9294 13:43:24.637095 Root Device init
9295 13:43:24.637587 init hardware done!
9296 13:43:24.640086 0x00000018: ctrlr->caps
9297 13:43:24.643174 52.000 MHz: ctrlr->f_max
9298 13:43:24.643665 0.400 MHz: ctrlr->f_min
9299 13:43:24.646822 0x40ff8080: ctrlr->voltages
9300 13:43:24.647460 sclk: 390625
9301 13:43:24.649837 Bus Width = 1
9302 13:43:24.650264 sclk: 390625
9303 13:43:24.653405 Bus Width = 1
9304 13:43:24.653870 Early init status = 3
9305 13:43:24.660176 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9306 13:43:24.663563 in-header: 03 fc 00 00 01 00 00 00
9307 13:43:24.663993 in-data: 00
9308 13:43:24.669975 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9309 13:43:24.673399 in-header: 03 fd 00 00 00 00 00 00
9310 13:43:24.676852 in-data:
9311 13:43:24.679905 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9312 13:43:24.684308 in-header: 03 fc 00 00 01 00 00 00
9313 13:43:24.687432 in-data: 00
9314 13:43:24.690801 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9315 13:43:24.696589 in-header: 03 fd 00 00 00 00 00 00
9316 13:43:24.699649 in-data:
9317 13:43:24.702910 [SSUSB] Setting up USB HOST controller...
9318 13:43:24.706560 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 13:43:24.709557 [SSUSB] phy power-on done.
9320 13:43:24.713189 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 13:43:24.719743 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 13:43:24.722803 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 13:43:24.729400 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 13:43:24.736264 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 13:43:24.742690 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 13:43:24.749344 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 13:43:24.755979 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 13:43:24.759487 SPM: binary array size = 0x9dc
9329 13:43:24.762522 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 13:43:24.769266 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 13:43:24.776185 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 13:43:24.779254 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 13:43:24.785729 configure_display: Starting display init
9334 13:43:24.819414 anx7625_power_on_init: Init interface.
9335 13:43:24.823101 anx7625_disable_pd_protocol: Disabled PD feature.
9336 13:43:24.826102 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 13:43:24.853721 anx7625_start_dp_work: Secure OCM version=00
9338 13:43:24.857460 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 13:43:24.871959 sp_tx_get_edid_block: EDID Block = 1
9340 13:43:24.974879 Extracted contents:
9341 13:43:24.978353 header: 00 ff ff ff ff ff ff 00
9342 13:43:24.981221 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 13:43:24.984488 version: 01 04
9344 13:43:24.987875 basic params: 95 1f 11 78 0a
9345 13:43:24.991243 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 13:43:24.994263 established: 00 00 00
9347 13:43:25.000967 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 13:43:25.004460 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 13:43:25.010819 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 13:43:25.017617 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 13:43:25.024412 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 13:43:25.027552 extensions: 00
9353 13:43:25.027984 checksum: fb
9354 13:43:25.028343
9355 13:43:25.031130 Manufacturer: IVO Model 57d Serial Number 0
9356 13:43:25.034390 Made week 0 of 2020
9357 13:43:25.034789 EDID version: 1.4
9358 13:43:25.037662 Digital display
9359 13:43:25.040610 6 bits per primary color channel
9360 13:43:25.041038 DisplayPort interface
9361 13:43:25.043976 Maximum image size: 31 cm x 17 cm
9362 13:43:25.047664 Gamma: 220%
9363 13:43:25.048071 Check DPMS levels
9364 13:43:25.050673 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 13:43:25.057165 First detailed timing is preferred timing
9366 13:43:25.057754 Established timings supported:
9367 13:43:25.060851 Standard timings supported:
9368 13:43:25.063902 Detailed timings
9369 13:43:25.067509 Hex of detail: 383680a07038204018303c0035ae10000019
9370 13:43:25.070622 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 13:43:25.077460 0780 0798 07c8 0820 hborder 0
9372 13:43:25.080504 0438 043b 0447 0458 vborder 0
9373 13:43:25.083823 -hsync -vsync
9374 13:43:25.084351 Did detailed timing
9375 13:43:25.090451 Hex of detail: 000000000000000000000000000000000000
9376 13:43:25.090864 Manufacturer-specified data, tag 0
9377 13:43:25.097478 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 13:43:25.100547 ASCII string: InfoVision
9379 13:43:25.104055 Hex of detail: 000000fe00523134304e574635205248200a
9380 13:43:25.107208 ASCII string: R140NWF5 RH
9381 13:43:25.107666 Checksum
9382 13:43:25.108076 Checksum: 0xfb (valid)
9383 13:43:25.114237 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 13:43:25.117171 DSI data_rate: 832800000 bps
9385 13:43:25.120842 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 13:43:25.127588 anx7625_parse_edid: pixelclock(138800).
9387 13:43:25.130735 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 13:43:25.133918 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 13:43:25.137032 anx7625_dsi_config: config dsi.
9390 13:43:25.144036 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 13:43:25.156946 anx7625_dsi_config: success to config DSI
9392 13:43:25.160163 anx7625_dp_start: MIPI phy setup OK.
9393 13:43:25.163401 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 13:43:25.166325 mtk_ddp_mode_set invalid vrefresh 60
9395 13:43:25.169788 main_disp_path_setup
9396 13:43:25.170379 ovl_layer_smi_id_en
9397 13:43:25.172912 ovl_layer_smi_id_en
9398 13:43:25.173423 ccorr_config
9399 13:43:25.173750 aal_config
9400 13:43:25.176489 gamma_config
9401 13:43:25.176921 postmask_config
9402 13:43:25.180026 dither_config
9403 13:43:25.183130 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 13:43:25.189702 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 13:43:25.193140 Root Device init finished in 553 msecs
9406 13:43:25.196283 CPU_CLUSTER: 0 init
9407 13:43:25.203140 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 13:43:25.206307 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 13:43:25.209967 APU_MBOX 0x190000b0 = 0x10001
9410 13:43:25.213029 APU_MBOX 0x190001b0 = 0x10001
9411 13:43:25.216601 APU_MBOX 0x190005b0 = 0x10001
9412 13:43:25.219861 APU_MBOX 0x190006b0 = 0x10001
9413 13:43:25.223025 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 13:43:25.235701 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9415 13:43:25.248131 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 13:43:25.254788 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 13:43:25.266132 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9418 13:43:25.275180 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 13:43:25.278506 CPU_CLUSTER: 0 init finished in 81 msecs
9420 13:43:25.281983 Devices initialized
9421 13:43:25.285022 Show all devs... After init.
9422 13:43:25.285529 Root Device: enabled 1
9423 13:43:25.288790 CPU_CLUSTER: 0: enabled 1
9424 13:43:25.291743 CPU: 00: enabled 1
9425 13:43:25.295172 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9426 13:43:25.298578 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 13:43:25.301766 ELOG: NV offset 0x57f000 size 0x1000
9428 13:43:25.308536 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9429 13:43:25.315174 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 13:43:25.318687 ELOG: Event(17) added with size 13 at 2024-05-28 13:42:15 UTC
9431 13:43:25.321680 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 13:43:25.325511 in-header: 03 43 00 00 2c 00 00 00
9433 13:43:25.339138 in-data: fc 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 13:43:25.345261 ELOG: Event(A1) added with size 10 at 2024-05-28 13:42:15 UTC
9435 13:43:25.351880 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9436 13:43:25.358909 ELOG: Event(A0) added with size 9 at 2024-05-28 13:42:15 UTC
9437 13:43:25.362377 elog_add_boot_reason: Logged dev mode boot
9438 13:43:25.365481 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9439 13:43:25.368945 Finalize devices...
9440 13:43:25.369360 Devices finalized
9441 13:43:25.375521 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 13:43:25.378553 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9443 13:43:25.382059 in-header: 03 07 00 00 08 00 00 00
9444 13:43:25.385426 in-data: aa e4 47 04 13 02 00 00
9445 13:43:25.388587 Chrome EC: UHEPI supported
9446 13:43:25.395182 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9447 13:43:25.398772 in-header: 03 a9 00 00 08 00 00 00
9448 13:43:25.402348 in-data: 84 60 60 08 00 00 00 00
9449 13:43:25.405253 ELOG: Event(91) added with size 10 at 2024-05-28 13:42:15 UTC
9450 13:43:25.411829 Chrome EC: clear events_b mask to 0x0000000020004000
9451 13:43:25.418399 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9452 13:43:25.422268 in-header: 03 fd 00 00 00 00 00 00
9453 13:43:25.422723 in-data:
9454 13:43:25.428813 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9455 13:43:25.432096 Writing coreboot table at 0xffe64000
9456 13:43:25.435211 0. 000000000010a000-0000000000113fff: RAMSTAGE
9457 13:43:25.438676 1. 0000000040000000-00000000400fffff: RAM
9458 13:43:25.442191 2. 0000000040100000-000000004032afff: RAMSTAGE
9459 13:43:25.448842 3. 000000004032b000-00000000545fffff: RAM
9460 13:43:25.451924 4. 0000000054600000-000000005465ffff: BL31
9461 13:43:25.455019 5. 0000000054660000-00000000ffe63fff: RAM
9462 13:43:25.458552 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9463 13:43:25.465078 7. 0000000100000000-000000023fffffff: RAM
9464 13:43:25.465568 Passing 5 GPIOs to payload:
9465 13:43:25.471873 NAME | PORT | POLARITY | VALUE
9466 13:43:25.474969 EC in RW | 0x000000aa | low | undefined
9467 13:43:25.481581 EC interrupt | 0x00000005 | low | undefined
9468 13:43:25.485233 TPM interrupt | 0x000000ab | high | undefined
9469 13:43:25.488429 SD card detect | 0x00000011 | high | undefined
9470 13:43:25.494959 speaker enable | 0x00000093 | high | undefined
9471 13:43:25.498501 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9472 13:43:25.501577 in-header: 03 f9 00 00 02 00 00 00
9473 13:43:25.502031 in-data: 02 00
9474 13:43:25.505129 ADC[4]: Raw value=901032 ID=7
9475 13:43:25.508190 ADC[3]: Raw value=212810 ID=1
9476 13:43:25.508653 RAM Code: 0x71
9477 13:43:25.511586 ADC[6]: Raw value=74502 ID=0
9478 13:43:25.514917 ADC[5]: Raw value=212441 ID=1
9479 13:43:25.515384 SKU Code: 0x1
9480 13:43:25.521825 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ca9d
9481 13:43:25.524927 coreboot table: 964 bytes.
9482 13:43:25.528309 IMD ROOT 0. 0xfffff000 0x00001000
9483 13:43:25.531781 IMD SMALL 1. 0xffffe000 0x00001000
9484 13:43:25.534934 RO MCACHE 2. 0xffffc000 0x00001104
9485 13:43:25.538469 CONSOLE 3. 0xfff7c000 0x00080000
9486 13:43:25.541403 FMAP 4. 0xfff7b000 0x00000452
9487 13:43:25.545072 TIME STAMP 5. 0xfff7a000 0x00000910
9488 13:43:25.548101 VBOOT WORK 6. 0xfff66000 0x00014000
9489 13:43:25.551561 RAMOOPS 7. 0xffe66000 0x00100000
9490 13:43:25.554701 COREBOOT 8. 0xffe64000 0x00002000
9491 13:43:25.555169 IMD small region:
9492 13:43:25.558249 IMD ROOT 0. 0xffffec00 0x00000400
9493 13:43:25.561346 VPD 1. 0xffffeb80 0x0000006c
9494 13:43:25.564922 MMC STATUS 2. 0xffffeb60 0x00000004
9495 13:43:25.571319 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9496 13:43:25.577877 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9497 13:43:25.617412 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9498 13:43:25.620685 Checking segment from ROM address 0x40100000
9499 13:43:25.623987 Checking segment from ROM address 0x4010001c
9500 13:43:25.630481 Loading segment from ROM address 0x40100000
9501 13:43:25.630916 code (compression=0)
9502 13:43:25.640727 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9503 13:43:25.646970 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9504 13:43:25.647402 it's not compressed!
9505 13:43:25.653558 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9506 13:43:25.660298 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9507 13:43:25.677989 Loading segment from ROM address 0x4010001c
9508 13:43:25.678412 Entry Point 0x80000000
9509 13:43:25.680968 Loaded segments
9510 13:43:25.684304 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9511 13:43:25.691375 Jumping to boot code at 0x80000000(0xffe64000)
9512 13:43:25.697688 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9513 13:43:25.704352 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9514 13:43:25.711975 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9515 13:43:25.715284 Checking segment from ROM address 0x40100000
9516 13:43:25.719006 Checking segment from ROM address 0x4010001c
9517 13:43:25.725193 Loading segment from ROM address 0x40100000
9518 13:43:25.725653 code (compression=1)
9519 13:43:25.731924 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9520 13:43:25.741827 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9521 13:43:25.742256 using LZMA
9522 13:43:25.750207 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9523 13:43:25.756966 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9524 13:43:25.760512 Loading segment from ROM address 0x4010001c
9525 13:43:25.760942 Entry Point 0x54601000
9526 13:43:25.763627 Loaded segments
9527 13:43:25.767215 NOTICE: MT8192 bl31_setup
9528 13:43:25.774289 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9529 13:43:25.777394 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9530 13:43:25.780983 WARNING: region 0:
9531 13:43:25.784030 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 13:43:25.784455 WARNING: region 1:
9533 13:43:25.790641 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9534 13:43:25.794279 WARNING: region 2:
9535 13:43:25.797211 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9536 13:43:25.800682 WARNING: region 3:
9537 13:43:25.804132 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 13:43:25.807482 WARNING: region 4:
9539 13:43:25.813994 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 13:43:25.814583 WARNING: region 5:
9541 13:43:25.817439 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 13:43:25.820503 WARNING: region 6:
9543 13:43:25.823930 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 13:43:25.827392 WARNING: region 7:
9545 13:43:25.830752 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 13:43:25.837235 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9547 13:43:25.840801 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9548 13:43:25.843804 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9549 13:43:25.850627 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9550 13:43:25.853792 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9551 13:43:25.857358 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9552 13:43:25.863979 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9553 13:43:25.867400 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9554 13:43:25.874329 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9555 13:43:25.877419 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9556 13:43:25.880711 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9557 13:43:25.887219 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9558 13:43:25.890334 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9559 13:43:25.893969 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9560 13:43:25.900464 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9561 13:43:25.903596 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9562 13:43:25.910759 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9563 13:43:25.913630 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9564 13:43:25.917363 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9565 13:43:25.923889 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9566 13:43:25.926879 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9567 13:43:25.930477 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9568 13:43:25.937372 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9569 13:43:25.940496 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9570 13:43:25.947049 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9571 13:43:25.950559 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9572 13:43:25.953730 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9573 13:43:25.960469 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9574 13:43:25.963892 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9575 13:43:25.970648 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9576 13:43:25.973692 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9577 13:43:25.976948 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9578 13:43:25.983460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9579 13:43:25.987015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9580 13:43:25.990373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9581 13:43:25.993548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9582 13:43:26.000284 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9583 13:43:26.003842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9584 13:43:26.006995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9585 13:43:26.010529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9586 13:43:26.017182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9587 13:43:26.020459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9588 13:43:26.023829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9589 13:43:26.027072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9590 13:43:26.033561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9591 13:43:26.037125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9592 13:43:26.040531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9593 13:43:26.043853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9594 13:43:26.050317 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9595 13:43:26.053837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9596 13:43:26.060357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9597 13:43:26.063813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9598 13:43:26.070618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9599 13:43:26.073753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9600 13:43:26.076953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9601 13:43:26.084009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9602 13:43:26.086980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9603 13:43:26.093590 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9604 13:43:26.097043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9605 13:43:26.103444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9606 13:43:26.107025 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9607 13:43:26.110237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9608 13:43:26.116963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9609 13:43:26.120545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9610 13:43:26.126952 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9611 13:43:26.130406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9612 13:43:26.136743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9613 13:43:26.139855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9614 13:43:26.146761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9615 13:43:26.150065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9616 13:43:26.153499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9617 13:43:26.160135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9618 13:43:26.163670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9619 13:43:26.169915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9620 13:43:26.173461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9621 13:43:26.179776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9622 13:43:26.183171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9623 13:43:26.186835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9624 13:43:26.193203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9625 13:43:26.196565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9626 13:43:26.203019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9627 13:43:26.206511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9628 13:43:26.213172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9629 13:43:26.216776 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9630 13:43:26.219799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9631 13:43:26.226357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9632 13:43:26.230026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9633 13:43:26.236569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9634 13:43:26.240006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9635 13:43:26.246581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9636 13:43:26.250097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9637 13:43:26.253377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9638 13:43:26.259757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9639 13:43:26.262951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9640 13:43:26.269806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9641 13:43:26.273359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9642 13:43:26.280052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9643 13:43:26.283215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9644 13:43:26.286301 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9645 13:43:26.289877 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9646 13:43:26.293112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9647 13:43:26.299876 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9648 13:43:26.303340 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9649 13:43:26.309794 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9650 13:43:26.312959 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9651 13:43:26.316524 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9652 13:43:26.323056 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9653 13:43:26.326645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9654 13:43:26.333067 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9655 13:43:26.336591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9656 13:43:26.339563 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9657 13:43:26.346537 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9658 13:43:26.349883 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9659 13:43:26.356189 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9660 13:43:26.359525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9661 13:43:26.362964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9662 13:43:26.369463 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9663 13:43:26.372968 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9664 13:43:26.376288 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9665 13:43:26.383117 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9666 13:43:26.386405 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9667 13:43:26.389416 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9668 13:43:26.393061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9669 13:43:26.399293 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9670 13:43:26.402767 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9671 13:43:26.405944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9672 13:43:26.412939 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9673 13:43:26.416040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9674 13:43:26.422633 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9675 13:43:26.425913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9676 13:43:26.429437 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9677 13:43:26.435987 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9678 13:43:26.439545 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9679 13:43:26.446123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9680 13:43:26.449203 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9681 13:43:26.452789 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9682 13:43:26.459226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9683 13:43:26.462643 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9684 13:43:26.469504 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9685 13:43:26.472619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9686 13:43:26.475744 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9687 13:43:26.482784 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9688 13:43:26.485827 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9689 13:43:26.489094 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9690 13:43:26.495943 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9691 13:43:26.499051 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9692 13:43:26.505790 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9693 13:43:26.508975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9694 13:43:26.512397 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9695 13:43:26.518954 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9696 13:43:26.522425 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9697 13:43:26.529026 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9698 13:43:26.532110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9699 13:43:26.535579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9700 13:43:26.542607 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9701 13:43:26.545737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9702 13:43:26.552465 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9703 13:43:26.555922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9704 13:43:26.559155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9705 13:43:26.565642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9706 13:43:26.568990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9707 13:43:26.572250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9708 13:43:26.578851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9709 13:43:26.582378 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9710 13:43:26.589040 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9711 13:43:26.592417 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9712 13:43:26.595511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9713 13:43:26.602240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9714 13:43:26.605742 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9715 13:43:26.612312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9716 13:43:26.615558 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9717 13:43:26.618804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9718 13:43:26.625871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9719 13:43:26.628979 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9720 13:43:26.631883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9721 13:43:26.638820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9722 13:43:26.642343 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9723 13:43:26.649122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9724 13:43:26.652132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9725 13:43:26.655594 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9726 13:43:26.662107 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9727 13:43:26.665474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9728 13:43:26.672049 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9729 13:43:26.675651 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9730 13:43:26.679210 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9731 13:43:26.685920 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9732 13:43:26.689234 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9733 13:43:26.692350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9734 13:43:26.698970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9735 13:43:26.702693 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9736 13:43:26.709153 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9737 13:43:26.712298 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9738 13:43:26.719224 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9739 13:43:26.722510 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9740 13:43:26.725805 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9741 13:43:26.732418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9742 13:43:26.735370 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9743 13:43:26.742416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9744 13:43:26.745411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9745 13:43:26.748991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9746 13:43:26.755553 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9747 13:43:26.759035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9748 13:43:26.765435 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9749 13:43:26.768980 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9750 13:43:26.775604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9751 13:43:26.778704 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9752 13:43:26.781930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9753 13:43:26.788718 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9754 13:43:26.792316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9755 13:43:26.798823 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9756 13:43:26.801912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9757 13:43:26.805523 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9758 13:43:26.812124 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9759 13:43:26.815232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9760 13:43:26.821906 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9761 13:43:26.825234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9762 13:43:26.828658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9763 13:43:26.835238 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9764 13:43:26.838865 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9765 13:43:26.845402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9766 13:43:26.848499 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9767 13:43:26.855189 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9768 13:43:26.858207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9769 13:43:26.861865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9770 13:43:26.868599 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9771 13:43:26.871787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9772 13:43:26.878333 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9773 13:43:26.881955 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9774 13:43:26.884950 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9775 13:43:26.892018 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9776 13:43:26.895201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9777 13:43:26.898377 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9778 13:43:26.901637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9779 13:43:26.908172 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9780 13:43:26.911817 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9781 13:43:26.914760 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9782 13:43:26.921389 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9783 13:43:26.924975 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9784 13:43:26.928255 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9785 13:43:26.934552 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9786 13:43:26.938134 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9787 13:43:26.944610 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9788 13:43:26.948130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9789 13:43:26.951198 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9790 13:43:26.957989 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9791 13:43:26.961113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9792 13:43:26.964572 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9793 13:43:26.971201 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9794 13:43:26.974309 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9795 13:43:26.977851 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9796 13:43:26.984494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9797 13:43:26.987982 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9798 13:43:26.994366 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9799 13:43:26.997932 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9800 13:43:27.001283 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9801 13:43:27.007915 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9802 13:43:27.011125 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9803 13:43:27.014609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9804 13:43:27.021114 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9805 13:43:27.024206 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9806 13:43:27.030802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9807 13:43:27.034338 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9808 13:43:27.037372 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9809 13:43:27.044244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9810 13:43:27.047681 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9811 13:43:27.050696 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9812 13:43:27.057419 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9813 13:43:27.060912 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9814 13:43:27.063945 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9815 13:43:27.070515 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9816 13:43:27.074103 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9817 13:43:27.077259 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9818 13:43:27.080885 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9819 13:43:27.083964 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9820 13:43:27.090792 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9821 13:43:27.093933 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9822 13:43:27.097563 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9823 13:43:27.100591 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9824 13:43:27.107219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9825 13:43:27.110555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9826 13:43:27.113874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9827 13:43:27.120862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9828 13:43:27.124122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9829 13:43:27.127101 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9830 13:43:27.133728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9831 13:43:27.137281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9832 13:43:27.143775 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9833 13:43:27.147112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9834 13:43:27.153975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9835 13:43:27.157073 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9836 13:43:27.160143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9837 13:43:27.166857 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9838 13:43:27.170396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9839 13:43:27.176948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9840 13:43:27.179949 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9841 13:43:27.183541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9842 13:43:27.190199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9843 13:43:27.193707 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9844 13:43:27.200183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9845 13:43:27.203275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9846 13:43:27.206908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9847 13:43:27.213155 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9848 13:43:27.216765 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9849 13:43:27.223215 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9850 13:43:27.226740 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9851 13:43:27.229578 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9852 13:43:27.236274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9853 13:43:27.239856 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9854 13:43:27.246197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9855 13:43:27.249633 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9856 13:43:27.256297 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9857 13:43:27.259880 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9858 13:43:27.265920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9859 13:43:27.269429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9860 13:43:27.272869 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9861 13:43:27.279516 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9862 13:43:27.282746 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9863 13:43:27.286244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9864 13:43:27.292469 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9865 13:43:27.296012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9866 13:43:27.302594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9867 13:43:27.306161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9868 13:43:27.312390 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9869 13:43:27.315682 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9870 13:43:27.319420 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9871 13:43:27.325756 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9872 13:43:27.328966 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9873 13:43:27.335566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9874 13:43:27.338823 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9875 13:43:27.342430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9876 13:43:27.348938 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9877 13:43:27.352353 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9878 13:43:27.358634 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9879 13:43:27.362158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9880 13:43:27.368814 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9881 13:43:27.371842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9882 13:43:27.375416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9883 13:43:27.382022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9884 13:43:27.385055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9885 13:43:27.391706 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9886 13:43:27.395262 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9887 13:43:27.398146 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9888 13:43:27.404862 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9889 13:43:27.408567 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9890 13:43:27.415117 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9891 13:43:27.418105 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9892 13:43:27.421761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9893 13:43:27.428246 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9894 13:43:27.431399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9895 13:43:27.438387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9896 13:43:27.441364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9897 13:43:27.448231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9898 13:43:27.451254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9899 13:43:27.454803 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9900 13:43:27.461781 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9901 13:43:27.464726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9902 13:43:27.471796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9903 13:43:27.474898 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9904 13:43:27.481479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9905 13:43:27.484916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9906 13:43:27.488153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9907 13:43:27.494722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9908 13:43:27.497939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9909 13:43:27.504392 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9910 13:43:27.507983 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9911 13:43:27.514770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9912 13:43:27.517829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9913 13:43:27.521504 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9914 13:43:27.528016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9915 13:43:27.531550 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9916 13:43:27.537912 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9917 13:43:27.541418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9918 13:43:27.547862 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9919 13:43:27.550962 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9920 13:43:27.557848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9921 13:43:27.561049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9922 13:43:27.564518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9923 13:43:27.570961 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9924 13:43:27.574438 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9925 13:43:27.580999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9926 13:43:27.584456 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9927 13:43:27.591107 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9928 13:43:27.594266 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9929 13:43:27.597797 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9930 13:43:27.604358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9931 13:43:27.607458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9932 13:43:27.614148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9933 13:43:27.617796 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9934 13:43:27.624480 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9935 13:43:27.627405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9936 13:43:27.630997 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9937 13:43:27.637521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9938 13:43:27.640918 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9939 13:43:27.647653 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9940 13:43:27.651067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9941 13:43:27.657287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9942 13:43:27.660656 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9943 13:43:27.664148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9944 13:43:27.671098 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9945 13:43:27.674016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9946 13:43:27.681058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9947 13:43:27.684096 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9948 13:43:27.687623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9949 13:43:27.693974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9950 13:43:27.697515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9951 13:43:27.704242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9952 13:43:27.707429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9953 13:43:27.714053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9954 13:43:27.717559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9955 13:43:27.723977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9956 13:43:27.727540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9957 13:43:27.733937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9958 13:43:27.737347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9959 13:43:27.743918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9960 13:43:27.747345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9961 13:43:27.754210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9962 13:43:27.757262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9963 13:43:27.760808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9964 13:43:27.767206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9965 13:43:27.770966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9966 13:43:27.777237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9967 13:43:27.780639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9968 13:43:27.787325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9969 13:43:27.790730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9970 13:43:27.797502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9971 13:43:27.800668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9972 13:43:27.807139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9973 13:43:27.810819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9974 13:43:27.817528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9975 13:43:27.820511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9976 13:43:27.827078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9977 13:43:27.830582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9978 13:43:27.837121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9979 13:43:27.840472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9980 13:43:27.847371 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9981 13:43:27.847819 INFO: [APUAPC] vio 0
9982 13:43:27.853770 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9983 13:43:27.857705 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9984 13:43:27.860810 INFO: [APUAPC] D0_APC_0: 0x400510
9985 13:43:27.863850 INFO: [APUAPC] D0_APC_1: 0x0
9986 13:43:27.867217 INFO: [APUAPC] D0_APC_2: 0x1540
9987 13:43:27.870894 INFO: [APUAPC] D0_APC_3: 0x0
9988 13:43:27.873965 INFO: [APUAPC] D1_APC_0: 0xffffffff
9989 13:43:27.877527 INFO: [APUAPC] D1_APC_1: 0xffffffff
9990 13:43:27.880594 INFO: [APUAPC] D1_APC_2: 0x3fffff
9991 13:43:27.883863 INFO: [APUAPC] D1_APC_3: 0x0
9992 13:43:27.887350 INFO: [APUAPC] D2_APC_0: 0xffffffff
9993 13:43:27.891013 INFO: [APUAPC] D2_APC_1: 0xffffffff
9994 13:43:27.894058 INFO: [APUAPC] D2_APC_2: 0x3fffff
9995 13:43:27.897321 INFO: [APUAPC] D2_APC_3: 0x0
9996 13:43:27.900905 INFO: [APUAPC] D3_APC_0: 0xffffffff
9997 13:43:27.904042 INFO: [APUAPC] D3_APC_1: 0xffffffff
9998 13:43:27.907606 INFO: [APUAPC] D3_APC_2: 0x3fffff
9999 13:43:27.908031 INFO: [APUAPC] D3_APC_3: 0x0
10000 13:43:27.910639 INFO: [APUAPC] D4_APC_0: 0xffffffff
10001 13:43:27.917332 INFO: [APUAPC] D4_APC_1: 0xffffffff
10002 13:43:27.920899 INFO: [APUAPC] D4_APC_2: 0x3fffff
10003 13:43:27.921344 INFO: [APUAPC] D4_APC_3: 0x0
10004 13:43:27.923982 INFO: [APUAPC] D5_APC_0: 0xffffffff
10005 13:43:27.927160 INFO: [APUAPC] D5_APC_1: 0xffffffff
10006 13:43:27.930828 INFO: [APUAPC] D5_APC_2: 0x3fffff
10007 13:43:27.933982 INFO: [APUAPC] D5_APC_3: 0x0
10008 13:43:27.937104 INFO: [APUAPC] D6_APC_0: 0xffffffff
10009 13:43:27.940556 INFO: [APUAPC] D6_APC_1: 0xffffffff
10010 13:43:27.944064 INFO: [APUAPC] D6_APC_2: 0x3fffff
10011 13:43:27.947265 INFO: [APUAPC] D6_APC_3: 0x0
10012 13:43:27.950746 INFO: [APUAPC] D7_APC_0: 0xffffffff
10013 13:43:27.953782 INFO: [APUAPC] D7_APC_1: 0xffffffff
10014 13:43:27.957191 INFO: [APUAPC] D7_APC_2: 0x3fffff
10015 13:43:27.960574 INFO: [APUAPC] D7_APC_3: 0x0
10016 13:43:27.963844 INFO: [APUAPC] D8_APC_0: 0xffffffff
10017 13:43:27.966835 INFO: [APUAPC] D8_APC_1: 0xffffffff
10018 13:43:27.970459 INFO: [APUAPC] D8_APC_2: 0x3fffff
10019 13:43:27.974013 INFO: [APUAPC] D8_APC_3: 0x0
10020 13:43:27.976979 INFO: [APUAPC] D9_APC_0: 0xffffffff
10021 13:43:27.980631 INFO: [APUAPC] D9_APC_1: 0xffffffff
10022 13:43:27.983609 INFO: [APUAPC] D9_APC_2: 0x3fffff
10023 13:43:27.987210 INFO: [APUAPC] D9_APC_3: 0x0
10024 13:43:27.990262 INFO: [APUAPC] D10_APC_0: 0xffffffff
10025 13:43:27.993693 INFO: [APUAPC] D10_APC_1: 0xffffffff
10026 13:43:27.997129 INFO: [APUAPC] D10_APC_2: 0x3fffff
10027 13:43:28.000192 INFO: [APUAPC] D10_APC_3: 0x0
10028 13:43:28.003723 INFO: [APUAPC] D11_APC_0: 0xffffffff
10029 13:43:28.006924 INFO: [APUAPC] D11_APC_1: 0xffffffff
10030 13:43:28.010044 INFO: [APUAPC] D11_APC_2: 0x3fffff
10031 13:43:28.013511 INFO: [APUAPC] D11_APC_3: 0x0
10032 13:43:28.016522 INFO: [APUAPC] D12_APC_0: 0xffffffff
10033 13:43:28.020123 INFO: [APUAPC] D12_APC_1: 0xffffffff
10034 13:43:28.023839 INFO: [APUAPC] D12_APC_2: 0x3fffff
10035 13:43:28.026867 INFO: [APUAPC] D12_APC_3: 0x0
10036 13:43:28.030046 INFO: [APUAPC] D13_APC_0: 0xffffffff
10037 13:43:28.033514 INFO: [APUAPC] D13_APC_1: 0xffffffff
10038 13:43:28.036743 INFO: [APUAPC] D13_APC_2: 0x3fffff
10039 13:43:28.040391 INFO: [APUAPC] D13_APC_3: 0x0
10040 13:43:28.043494 INFO: [APUAPC] D14_APC_0: 0xffffffff
10041 13:43:28.046881 INFO: [APUAPC] D14_APC_1: 0xffffffff
10042 13:43:28.049948 INFO: [APUAPC] D14_APC_2: 0x3fffff
10043 13:43:28.053693 INFO: [APUAPC] D14_APC_3: 0x0
10044 13:43:28.056592 INFO: [APUAPC] D15_APC_0: 0xffffffff
10045 13:43:28.060188 INFO: [APUAPC] D15_APC_1: 0xffffffff
10046 13:43:28.063205 INFO: [APUAPC] D15_APC_2: 0x3fffff
10047 13:43:28.066555 INFO: [APUAPC] D15_APC_3: 0x0
10048 13:43:28.070225 INFO: [APUAPC] APC_CON: 0x4
10049 13:43:28.073186 INFO: [NOCDAPC] D0_APC_0: 0x0
10050 13:43:28.076804 INFO: [NOCDAPC] D0_APC_1: 0x0
10051 13:43:28.079795 INFO: [NOCDAPC] D1_APC_0: 0x0
10052 13:43:28.083379 INFO: [NOCDAPC] D1_APC_1: 0xfff
10053 13:43:28.083803 INFO: [NOCDAPC] D2_APC_0: 0x0
10054 13:43:28.086398 INFO: [NOCDAPC] D2_APC_1: 0xfff
10055 13:43:28.089897 INFO: [NOCDAPC] D3_APC_0: 0x0
10056 13:43:28.093463 INFO: [NOCDAPC] D3_APC_1: 0xfff
10057 13:43:28.096546 INFO: [NOCDAPC] D4_APC_0: 0x0
10058 13:43:28.100136 INFO: [NOCDAPC] D4_APC_1: 0xfff
10059 13:43:28.103046 INFO: [NOCDAPC] D5_APC_0: 0x0
10060 13:43:28.106303 INFO: [NOCDAPC] D5_APC_1: 0xfff
10061 13:43:28.109526 INFO: [NOCDAPC] D6_APC_0: 0x0
10062 13:43:28.113286 INFO: [NOCDAPC] D6_APC_1: 0xfff
10063 13:43:28.116416 INFO: [NOCDAPC] D7_APC_0: 0x0
10064 13:43:28.116982 INFO: [NOCDAPC] D7_APC_1: 0xfff
10065 13:43:28.119921 INFO: [NOCDAPC] D8_APC_0: 0x0
10066 13:43:28.123086 INFO: [NOCDAPC] D8_APC_1: 0xfff
10067 13:43:28.126779 INFO: [NOCDAPC] D9_APC_0: 0x0
10068 13:43:28.129880 INFO: [NOCDAPC] D9_APC_1: 0xfff
10069 13:43:28.133265 INFO: [NOCDAPC] D10_APC_0: 0x0
10070 13:43:28.136374 INFO: [NOCDAPC] D10_APC_1: 0xfff
10071 13:43:28.139633 INFO: [NOCDAPC] D11_APC_0: 0x0
10072 13:43:28.143243 INFO: [NOCDAPC] D11_APC_1: 0xfff
10073 13:43:28.146306 INFO: [NOCDAPC] D12_APC_0: 0x0
10074 13:43:28.149831 INFO: [NOCDAPC] D12_APC_1: 0xfff
10075 13:43:28.153351 INFO: [NOCDAPC] D13_APC_0: 0x0
10076 13:43:28.153773 INFO: [NOCDAPC] D13_APC_1: 0xfff
10077 13:43:28.156236 INFO: [NOCDAPC] D14_APC_0: 0x0
10078 13:43:28.159582 INFO: [NOCDAPC] D14_APC_1: 0xfff
10079 13:43:28.163240 INFO: [NOCDAPC] D15_APC_0: 0x0
10080 13:43:28.166205 INFO: [NOCDAPC] D15_APC_1: 0xfff
10081 13:43:28.169614 INFO: [NOCDAPC] APC_CON: 0x4
10082 13:43:28.172817 INFO: [APUAPC] set_apusys_apc done
10083 13:43:28.176145 INFO: [DEVAPC] devapc_init done
10084 13:43:28.179622 INFO: GICv3 without legacy support detected.
10085 13:43:28.186347 INFO: ARM GICv3 driver initialized in EL3
10086 13:43:28.189455 INFO: Maximum SPI INTID supported: 639
10087 13:43:28.193016 INFO: BL31: Initializing runtime services
10088 13:43:28.199705 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10089 13:43:28.200147 INFO: SPM: enable CPC mode
10090 13:43:28.206508 INFO: mcdi ready for mcusys-off-idle and system suspend
10091 13:43:28.209564 INFO: BL31: Preparing for EL3 exit to normal world
10092 13:43:28.212887 INFO: Entry point address = 0x80000000
10093 13:43:28.216215 INFO: SPSR = 0x8
10094 13:43:28.221903
10095 13:43:28.222379
10096 13:43:28.222769
10097 13:43:28.225389 Starting depthcharge on Spherion...
10098 13:43:28.225815
10099 13:43:28.226212 Wipe memory regions:
10100 13:43:28.226574
10101 13:43:28.228827 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10102 13:43:28.229442 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10103 13:43:28.229945 Setting prompt string to ['asurada:']
10104 13:43:28.230372 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10105 13:43:28.231024 [0x00000040000000, 0x00000054600000)
10106 13:43:28.350911
10107 13:43:28.351389 [0x00000054660000, 0x00000080000000)
10108 13:43:28.611964
10109 13:43:28.612557 [0x000000821a7280, 0x000000ffe64000)
10110 13:43:29.356369
10111 13:43:29.356860 [0x00000100000000, 0x00000240000000)
10112 13:43:31.246594
10113 13:43:31.250053 Initializing XHCI USB controller at 0x11200000.
10114 13:43:32.287985
10115 13:43:32.291183 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10116 13:43:32.291275
10117 13:43:32.291343
10118 13:43:32.291629 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 13:43:32.391956 asurada: tftpboot 192.168.201.1 14063105/tftp-deploy-o8z8wbql/kernel/image.itb 14063105/tftp-deploy-o8z8wbql/kernel/cmdline
10121 13:43:32.392108 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 13:43:32.392204 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10123 13:43:32.396605 tftpboot 192.168.201.1 14063105/tftp-deploy-o8z8wbql/kernel/image.itp-deploy-o8z8wbql/kernel/cmdline
10124 13:43:32.396689
10125 13:43:32.396753 Waiting for link
10126 13:43:32.554830
10127 13:43:32.554980 R8152: Initializing
10128 13:43:32.555049
10129 13:43:32.557877 Version 9 (ocp_data = 6010)
10130 13:43:32.557949
10131 13:43:32.561231 R8152: Done initializing
10132 13:43:32.561353
10133 13:43:32.561420 Adding net device
10134 13:43:34.436014
10135 13:43:34.436153 done.
10136 13:43:34.436220
10137 13:43:34.436280 MAC: 00:e0:4c:72:2d:d6
10138 13:43:34.436337
10139 13:43:34.439083 Sending DHCP discover... done.
10140 13:43:34.439195
10141 13:43:34.443047 Waiting for reply... done.
10142 13:43:34.443168
10143 13:43:34.445674 Sending DHCP request... done.
10144 13:43:34.445756
10145 13:43:34.445822 Waiting for reply... done.
10146 13:43:34.445900
10147 13:43:34.449116 My ip is 192.168.201.21
10148 13:43:34.449227
10149 13:43:34.452362 The DHCP server ip is 192.168.201.1
10150 13:43:34.452445
10151 13:43:34.455455 TFTP server IP predefined by user: 192.168.201.1
10152 13:43:34.455537
10153 13:43:34.462082 Bootfile predefined by user: 14063105/tftp-deploy-o8z8wbql/kernel/image.itb
10154 13:43:34.462164
10155 13:43:34.465629 Sending tftp read request... done.
10156 13:43:34.465711
10157 13:43:34.468679 Waiting for the transfer...
10158 13:43:34.468762
10159 13:43:34.724031 00000000 ################################################################
10160 13:43:34.724187
10161 13:43:34.975497 00080000 ################################################################
10162 13:43:34.975677
10163 13:43:35.227881 00100000 ################################################################
10164 13:43:35.228051
10165 13:43:35.490816 00180000 ################################################################
10166 13:43:35.490951
10167 13:43:35.742116 00200000 ################################################################
10168 13:43:35.742265
10169 13:43:35.995341 00280000 ################################################################
10170 13:43:35.995487
10171 13:43:36.278701 00300000 ################################################################
10172 13:43:36.278840
10173 13:43:36.543040 00380000 ################################################################
10174 13:43:36.543203
10175 13:43:36.798860 00400000 ################################################################
10176 13:43:36.799023
10177 13:43:37.061558 00480000 ################################################################
10178 13:43:37.061699
10179 13:43:37.347004 00500000 ################################################################
10180 13:43:37.347158
10181 13:43:37.625167 00580000 ################################################################
10182 13:43:37.625364
10183 13:43:37.906555 00600000 ################################################################
10184 13:43:37.906717
10185 13:43:38.189269 00680000 ################################################################
10186 13:43:38.189439
10187 13:43:38.476426 00700000 ################################################################
10188 13:43:38.476561
10189 13:43:38.745071 00780000 ################################################################
10190 13:43:38.745203
10191 13:43:39.007574 00800000 ################################################################
10192 13:43:39.007718
10193 13:43:39.262071 00880000 ################################################################
10194 13:43:39.262204
10195 13:43:39.526737 00900000 ################################################################
10196 13:43:39.526873
10197 13:43:39.791348 00980000 ################################################################
10198 13:43:39.791482
10199 13:43:40.073863 00a00000 ################################################################
10200 13:43:40.073997
10201 13:43:40.328673 00a80000 ################################################################
10202 13:43:40.328811
10203 13:43:40.604355 00b00000 ################################################################
10204 13:43:40.604488
10205 13:43:40.871309 00b80000 ################################################################
10206 13:43:40.871438
10207 13:43:41.133656 00c00000 ################################################################
10208 13:43:41.133791
10209 13:43:41.381389 00c80000 ################################################################
10210 13:43:41.381525
10211 13:43:41.628368 00d00000 ################################################################
10212 13:43:41.628502
10213 13:43:41.878131 00d80000 ################################################################
10214 13:43:41.878266
10215 13:43:42.126812 00e00000 ################################################################
10216 13:43:42.126951
10217 13:43:42.382397 00e80000 ################################################################
10218 13:43:42.382557
10219 13:43:42.634348 00f00000 ################################################################
10220 13:43:42.634480
10221 13:43:42.884123 00f80000 ################################################################
10222 13:43:42.884263
10223 13:43:43.134314 01000000 ################################################################
10224 13:43:43.134451
10225 13:43:43.421107 01080000 ################################################################
10226 13:43:43.421279
10227 13:43:43.707178 01100000 ################################################################
10228 13:43:43.707366
10229 13:43:43.989201 01180000 ################################################################
10230 13:43:43.989408
10231 13:43:44.252594 01200000 ################################################################
10232 13:43:44.252770
10233 13:43:44.502231 01280000 ################################################################
10234 13:43:44.502412
10235 13:43:44.775879 01300000 ################################################################
10236 13:43:44.776063
10237 13:43:45.061632 01380000 ################################################################
10238 13:43:45.061791
10239 13:43:45.328189 01400000 ################################################################
10240 13:43:45.328350
10241 13:43:45.577216 01480000 ################################################################
10242 13:43:45.577409
10243 13:43:45.826749 01500000 ################################################################
10244 13:43:45.826905
10245 13:43:46.078234 01580000 ################################################################
10246 13:43:46.078392
10247 13:43:46.346175 01600000 ################################################################
10248 13:43:46.346340
10249 13:43:46.631859 01680000 ################################################################
10250 13:43:46.632021
10251 13:43:46.902144 01700000 ################################################################
10252 13:43:46.902309
10253 13:43:47.177773 01780000 ################################################################
10254 13:43:47.177937
10255 13:43:47.450363 01800000 ################################################################
10256 13:43:47.450540
10257 13:43:47.735340 01880000 ################################################################
10258 13:43:47.735507
10259 13:43:47.994879 01900000 ################################################################
10260 13:43:47.995031
10261 13:43:48.246822 01980000 ################################################################
10262 13:43:48.246972
10263 13:43:48.497881 01a00000 ################################################################
10264 13:43:48.498027
10265 13:43:48.753287 01a80000 ################################################################
10266 13:43:48.753465
10267 13:43:49.022993 01b00000 ################################################################
10268 13:43:49.023164
10269 13:43:49.286051 01b80000 ################################################################
10270 13:43:49.286233
10271 13:43:49.571675 01c00000 ################################################################
10272 13:43:49.571826
10273 13:43:49.932303 01c80000 ################################################################
10274 13:43:49.932458
10275 13:43:50.279698 01d00000 ################################################################
10276 13:43:50.279853
10277 13:43:50.626889 01d80000 ################################################################
10278 13:43:50.627035
10279 13:43:50.889734 01e00000 ################################################ done.
10280 13:43:50.889869
10281 13:43:50.893181 The bootfile was 31846522 bytes long.
10282 13:43:50.893262
10283 13:43:50.893345 Sending tftp read request... done.
10284 13:43:50.896632
10285 13:43:50.896711 Waiting for the transfer...
10286 13:43:50.896782
10287 13:43:50.899393 00000000 # done.
10288 13:43:50.899477
10289 13:43:50.906115 Command line loaded dynamically from TFTP file: 14063105/tftp-deploy-o8z8wbql/kernel/cmdline
10290 13:43:50.906239
10291 13:43:50.929496 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10292 13:43:50.929646
10293 13:43:50.929716 Loading FIT.
10294 13:43:50.929779
10295 13:43:50.932475 Image ramdisk-1 has 18735926 bytes.
10296 13:43:50.932559
10297 13:43:50.935964 Image fdt-1 has 47258 bytes.
10298 13:43:50.936049
10299 13:43:50.939399 Image kernel-1 has 13061303 bytes.
10300 13:43:50.939485
10301 13:43:50.948856 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10302 13:43:50.948952
10303 13:43:50.965689 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10304 13:43:50.965826
10305 13:43:50.972098 Choosing best match conf-1 for compat google,spherion-rev2.
10306 13:43:50.972191
10307 13:43:50.979666 Connected to device vid:did:rid of 1ae0:0028:00
10308 13:43:50.988150
10309 13:43:50.991042 tpm_get_response: command 0x17b, return code 0x0
10310 13:43:50.991131
10311 13:43:50.994685 ec_init: CrosEC protocol v3 supported (256, 248)
10312 13:43:50.998744
10313 13:43:51.001676 tpm_cleanup: add release locality here.
10314 13:43:51.001773
10315 13:43:51.001841 Shutting down all USB controllers.
10316 13:43:51.001903
10317 13:43:51.004971 Removing current net device
10318 13:43:51.005065
10319 13:43:51.011731 Exiting depthcharge with code 4 at timestamp: 52119666
10320 13:43:51.011837
10321 13:43:51.015103 LZMA decompressing kernel-1 to 0x821a6718
10322 13:43:51.015192
10323 13:43:51.018609 LZMA decompressing kernel-1 to 0x40000000
10324 13:43:52.629892
10325 13:43:52.630081 jumping to kernel
10326 13:43:52.630565 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10327 13:43:52.630710 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10328 13:43:52.630824 Setting prompt string to ['Linux version [0-9]']
10329 13:43:52.630893 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10330 13:43:52.630961 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10331 13:43:52.712203
10332 13:43:52.715613 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10333 13:43:52.719310 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10334 13:43:52.719446 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10335 13:43:52.719535 Setting prompt string to []
10336 13:43:52.719616 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10337 13:43:52.719693 Using line separator: #'\n'#
10338 13:43:52.719755 No login prompt set.
10339 13:43:52.719831 Parsing kernel messages
10340 13:43:52.719891 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10341 13:43:52.719997 [login-action] Waiting for messages, (timeout 00:04:03)
10342 13:43:52.720068 Waiting using forced prompt support (timeout 00:02:01)
10343 13:43:52.738837 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10344 13:43:52.741760 [ 0.000000] random: crng init done
10345 13:43:52.748868 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 13:43:52.752040 [ 0.000000] efi: UEFI not found.
10347 13:43:52.758612 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 13:43:52.768673 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 13:43:52.775347 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 13:43:52.785353 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 13:43:52.791897 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 13:43:52.798676 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 13:43:52.804951 [ 0.000000] NUMA: No NUMA configuration found
10354 13:43:52.811721 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 13:43:52.815021 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10356 13:43:52.818447 [ 0.000000] Zone ranges:
10357 13:43:52.824984 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 13:43:52.828408 [ 0.000000] DMA32 empty
10359 13:43:52.834827 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 13:43:52.838315 [ 0.000000] Movable zone start for each node
10361 13:43:52.841265 [ 0.000000] Early memory node ranges
10362 13:43:52.848346 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 13:43:52.854828 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 13:43:52.861302 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 13:43:52.868172 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 13:43:52.871203 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 13:43:52.881334 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 13:43:52.937605 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 13:43:52.943851 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 13:43:52.950565 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 13:43:52.954013 [ 0.000000] psci: probing for conduit method from DT.
10372 13:43:52.960614 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 13:43:52.963995 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 13:43:52.970329 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 13:43:52.973953 [ 0.000000] psci: SMC Calling Convention v1.2
10376 13:43:52.980312 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10377 13:43:52.983825 [ 0.000000] Detected VIPT I-cache on CPU0
10378 13:43:52.990296 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 13:43:52.997055 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 13:43:53.003467 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 13:43:53.010115 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 13:43:53.016609 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 13:43:53.026917 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 13:43:53.029913 [ 0.000000] alternatives: applying boot alternatives
10385 13:43:53.036782 [ 0.000000] Fallback order for Node 0: 0
10386 13:43:53.043116 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 13:43:53.046653 [ 0.000000] Policy zone: Normal
10388 13:43:53.069801 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10389 13:43:53.079767 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 13:43:53.090252 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 13:43:53.100353 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 13:43:53.106884 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10393 13:43:53.110209 <6>[ 0.000000] software IO TLB: area num 8.
10394 13:43:53.167256 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 13:43:53.317257 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10396 13:43:53.323839 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 13:43:53.330383 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 13:43:53.333492 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 13:43:53.340093 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 13:43:53.346731 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 13:43:53.350138 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 13:43:53.360061 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 13:43:53.366917 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 13:43:53.373417 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 13:43:53.379649 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 13:43:53.383340 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 13:43:53.386784 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 13:43:53.393276 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 13:43:53.396737 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 13:43:53.403117 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 13:43:53.416179 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 13:43:53.429508 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 13:43:53.436163 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 13:43:53.443130 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 13:43:53.456680 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 13:43:53.462784 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 13:43:53.469722 <6>[ 0.009180] Console: colour dummy device 80x25
10418 13:43:53.480075 <6>[ 0.013926] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 13:43:53.486420 <6>[ 0.024367] pid_max: default: 32768 minimum: 301
10420 13:43:53.489730 <6>[ 0.029240] LSM: Security Framework initializing
10421 13:43:53.496277 <6>[ 0.034178] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 13:43:53.506497 <6>[ 0.041991] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 13:43:53.513195 <6>[ 0.051410] cblist_init_generic: Setting adjustable number of callback queues.
10424 13:43:53.519932 <6>[ 0.058854] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 13:43:53.529294 <6>[ 0.065233] cblist_init_generic: Setting adjustable number of callback queues.
10426 13:43:53.536300 <6>[ 0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 13:43:53.539245 <6>[ 0.079060] rcu: Hierarchical SRCU implementation.
10428 13:43:53.546021 <6>[ 0.084076] rcu: Max phase no-delay instances is 1000.
10429 13:43:53.552678 <6>[ 0.091110] EFI services will not be available.
10430 13:43:53.555931 <6>[ 0.096066] smp: Bringing up secondary CPUs ...
10431 13:43:53.564299 <6>[ 0.101115] Detected VIPT I-cache on CPU1
10432 13:43:53.570714 <6>[ 0.101188] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 13:43:53.577230 <6>[ 0.101217] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 13:43:53.580701 <6>[ 0.101553] Detected VIPT I-cache on CPU2
10435 13:43:53.587477 <6>[ 0.101604] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 13:43:53.594139 <6>[ 0.101621] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 13:43:53.600612 <6>[ 0.101880] Detected VIPT I-cache on CPU3
10438 13:43:53.607468 <6>[ 0.101928] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 13:43:53.613684 <6>[ 0.101942] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 13:43:53.617289 <6>[ 0.102246] CPU features: detected: Spectre-v4
10441 13:43:53.624101 <6>[ 0.102252] CPU features: detected: Spectre-BHB
10442 13:43:53.627214 <6>[ 0.102257] Detected PIPT I-cache on CPU4
10443 13:43:53.633713 <6>[ 0.102315] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 13:43:53.640188 <6>[ 0.102331] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 13:43:53.647165 <6>[ 0.102628] Detected PIPT I-cache on CPU5
10446 13:43:53.653668 <6>[ 0.102691] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 13:43:53.660411 <6>[ 0.102708] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 13:43:53.663775 <6>[ 0.102988] Detected PIPT I-cache on CPU6
10449 13:43:53.670251 <6>[ 0.103054] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 13:43:53.676850 <6>[ 0.103069] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 13:43:53.683390 <6>[ 0.103364] Detected PIPT I-cache on CPU7
10452 13:43:53.690342 <6>[ 0.103429] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 13:43:53.696881 <6>[ 0.103445] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 13:43:53.699948 <6>[ 0.103492] smp: Brought up 1 node, 8 CPUs
10455 13:43:53.706993 <6>[ 0.244900] SMP: Total of 8 processors activated.
10456 13:43:53.710044 <6>[ 0.249852] CPU features: detected: 32-bit EL0 Support
10457 13:43:53.720285 <6>[ 0.255247] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 13:43:53.726899 <6>[ 0.264047] CPU features: detected: Common not Private translations
10459 13:43:53.730222 <6>[ 0.270523] CPU features: detected: CRC32 instructions
10460 13:43:53.736589 <6>[ 0.275875] CPU features: detected: RCpc load-acquire (LDAPR)
10461 13:43:53.743279 <6>[ 0.281835] CPU features: detected: LSE atomic instructions
10462 13:43:53.750149 <6>[ 0.287652] CPU features: detected: Privileged Access Never
10463 13:43:53.753364 <6>[ 0.293432] CPU features: detected: RAS Extension Support
10464 13:43:53.763196 <6>[ 0.299040] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 13:43:53.767095 <6>[ 0.306259] CPU: All CPU(s) started at EL2
10466 13:43:53.773018 <6>[ 0.310602] alternatives: applying system-wide alternatives
10467 13:43:53.782433 <6>[ 0.321480] devtmpfs: initialized
10468 13:43:53.798426 <6>[ 0.330498] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 13:43:53.805080 <6>[ 0.340457] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 13:43:53.811243 <6>[ 0.348655] pinctrl core: initialized pinctrl subsystem
10471 13:43:53.814717 <6>[ 0.355328] DMI not present or invalid.
10472 13:43:53.821466 <6>[ 0.359737] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 13:43:53.831207 <6>[ 0.366571] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 13:43:53.837937 <6>[ 0.374157] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 13:43:53.847585 <6>[ 0.382381] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 13:43:53.850923 <6>[ 0.390618] audit: initializing netlink subsys (disabled)
10477 13:43:53.861044 <5>[ 0.396312] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10478 13:43:53.867304 <6>[ 0.397021] thermal_sys: Registered thermal governor 'step_wise'
10479 13:43:53.873935 <6>[ 0.404278] thermal_sys: Registered thermal governor 'power_allocator'
10480 13:43:53.877107 <6>[ 0.410532] cpuidle: using governor menu
10481 13:43:53.884053 <6>[ 0.421491] NET: Registered PF_QIPCRTR protocol family
10482 13:43:53.890410 <6>[ 0.426977] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 13:43:53.897250 <6>[ 0.434075] ASID allocator initialised with 32768 entries
10484 13:43:53.900276 <6>[ 0.440659] Serial: AMBA PL011 UART driver
10485 13:43:53.910709 <4>[ 0.449472] Trying to register duplicate clock ID: 134
10486 13:43:53.968832 <6>[ 0.511212] KASLR enabled
10487 13:43:53.983407 <6>[ 0.518983] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 13:43:53.989971 <6>[ 0.525997] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 13:43:53.996984 <6>[ 0.532489] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 13:43:54.003499 <6>[ 0.539493] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 13:43:54.009661 <6>[ 0.545982] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 13:43:54.016382 <6>[ 0.552988] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 13:43:54.022656 <6>[ 0.559475] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 13:43:54.029418 <6>[ 0.566479] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 13:43:54.032811 <6>[ 0.574015] ACPI: Interpreter disabled.
10496 13:43:54.041418 <6>[ 0.580451] iommu: Default domain type: Translated
10497 13:43:54.048190 <6>[ 0.585563] iommu: DMA domain TLB invalidation policy: strict mode
10498 13:43:54.051810 <5>[ 0.592219] SCSI subsystem initialized
10499 13:43:54.057916 <6>[ 0.596383] usbcore: registered new interface driver usbfs
10500 13:43:54.064857 <6>[ 0.602114] usbcore: registered new interface driver hub
10501 13:43:54.067565 <6>[ 0.607666] usbcore: registered new device driver usb
10502 13:43:54.074573 <6>[ 0.613770] pps_core: LinuxPPS API ver. 1 registered
10503 13:43:54.084496 <6>[ 0.618961] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 13:43:54.088363 <6>[ 0.628307] PTP clock support registered
10505 13:43:54.091311 <6>[ 0.632550] EDAC MC: Ver: 3.0.0
10506 13:43:54.098405 <6>[ 0.637701] FPGA manager framework
10507 13:43:54.105100 <6>[ 0.641387] Advanced Linux Sound Architecture Driver Initialized.
10508 13:43:54.108629 <6>[ 0.648157] vgaarb: loaded
10509 13:43:54.114904 <6>[ 0.651328] clocksource: Switched to clocksource arch_sys_counter
10510 13:43:54.118487 <5>[ 0.657771] VFS: Disk quotas dquot_6.6.0
10511 13:43:54.125000 <6>[ 0.661955] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 13:43:54.128361 <6>[ 0.669144] pnp: PnP ACPI: disabled
10513 13:43:54.136819 <6>[ 0.675851] NET: Registered PF_INET protocol family
10514 13:43:54.146411 <6>[ 0.681448] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 13:43:54.157853 <6>[ 0.693778] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 13:43:54.168068 <6>[ 0.702592] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 13:43:54.174801 <6>[ 0.710564] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 13:43:54.181253 <6>[ 0.719264] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 13:43:54.193731 <6>[ 0.729021] TCP: Hash tables configured (established 65536 bind 65536)
10520 13:43:54.200144 <6>[ 0.735890] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 13:43:54.206620 <6>[ 0.743091] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 13:43:54.213286 <6>[ 0.750795] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 13:43:54.220009 <6>[ 0.756947] RPC: Registered named UNIX socket transport module.
10524 13:43:54.223751 <6>[ 0.763098] RPC: Registered udp transport module.
10525 13:43:54.229806 <6>[ 0.768031] RPC: Registered tcp transport module.
10526 13:43:54.236871 <6>[ 0.772964] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 13:43:54.240112 <6>[ 0.779630] PCI: CLS 0 bytes, default 64
10528 13:43:54.243335 <6>[ 0.783969] Unpacking initramfs...
10529 13:43:54.268020 <6>[ 0.803419] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 13:43:54.277333 <6>[ 0.812075] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 13:43:54.281011 <6>[ 0.820915] kvm [1]: IPA Size Limit: 40 bits
10532 13:43:54.287502 <6>[ 0.825447] kvm [1]: GICv3: no GICV resource entry
10533 13:43:54.290821 <6>[ 0.830468] kvm [1]: disabling GICv2 emulation
10534 13:43:54.297271 <6>[ 0.835151] kvm [1]: GIC system register CPU interface enabled
10535 13:43:54.300829 <6>[ 0.841307] kvm [1]: vgic interrupt IRQ18
10536 13:43:54.307471 <6>[ 0.845658] kvm [1]: VHE mode initialized successfully
10537 13:43:54.313794 <5>[ 0.852019] Initialise system trusted keyrings
10538 13:43:54.320293 <6>[ 0.856859] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 13:43:54.327886 <6>[ 0.866893] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 13:43:54.334322 <5>[ 0.873290] NFS: Registering the id_resolver key type
10541 13:43:54.337806 <5>[ 0.878589] Key type id_resolver registered
10542 13:43:54.344562 <5>[ 0.883002] Key type id_legacy registered
10543 13:43:54.351378 <6>[ 0.887298] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 13:43:54.357758 <6>[ 0.894218] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 13:43:54.364208 <6>[ 0.901913] 9p: Installing v9fs 9p2000 file system support
10546 13:43:54.401871 <5>[ 0.940955] Key type asymmetric registered
10547 13:43:54.405087 <5>[ 0.945284] Asymmetric key parser 'x509' registered
10548 13:43:54.415045 <6>[ 0.950424] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 13:43:54.418007 <6>[ 0.958042] io scheduler mq-deadline registered
10550 13:43:54.421399 <6>[ 0.962817] io scheduler kyber registered
10551 13:43:54.440373 <6>[ 0.979855] EINJ: ACPI disabled.
10552 13:43:54.473174 <4>[ 1.005794] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 13:43:54.483036 <4>[ 1.016448] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 13:43:54.498713 <6>[ 1.037947] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 13:43:54.506549 <6>[ 1.046108] printk: console [ttyS0] disabled
10556 13:43:54.534737 <6>[ 1.070759] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 13:43:54.541033 <6>[ 1.080251] printk: console [ttyS0] enabled
10558 13:43:54.544441 <6>[ 1.080251] printk: console [ttyS0] enabled
10559 13:43:54.550926 <6>[ 1.089149] printk: bootconsole [mtk8250] disabled
10560 13:43:54.554432 <6>[ 1.089149] printk: bootconsole [mtk8250] disabled
10561 13:43:54.560848 <6>[ 1.100498] SuperH (H)SCI(F) driver initialized
10562 13:43:54.564292 <6>[ 1.105786] msm_serial: driver initialized
10563 13:43:54.578525 <6>[ 1.114805] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 13:43:54.588540 <6>[ 1.123356] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 13:43:54.595264 <6>[ 1.131899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 13:43:54.605750 <6>[ 1.140526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 13:43:54.615596 <6>[ 1.149233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 13:43:54.622171 <6>[ 1.157956] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 13:43:54.631972 <6>[ 1.166497] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 13:43:54.638846 <6>[ 1.175299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 13:43:54.648159 <6>[ 1.183845] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 13:43:54.660400 <6>[ 1.199703] loop: module loaded
10573 13:43:54.666984 <6>[ 1.205427] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 13:43:54.689750 <4>[ 1.229059] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 13:43:54.696672 <6>[ 1.235989] megasas: 07.719.03.00-rc1
10576 13:43:54.706507 <6>[ 1.245577] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 13:43:54.715519 <6>[ 1.254716] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 13:43:54.731903 <6>[ 1.271297] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 13:43:54.788303 <6>[ 1.321322] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10580 13:43:55.033102 <6>[ 1.572366] Freeing initrd memory: 18292K
10581 13:43:55.044971 <6>[ 1.584160] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 13:43:55.055795 <6>[ 1.595054] tun: Universal TUN/TAP device driver, 1.6
10583 13:43:55.059305 <6>[ 1.601117] thunder_xcv, ver 1.0
10584 13:43:55.062673 <6>[ 1.604624] thunder_bgx, ver 1.0
10585 13:43:55.066020 <6>[ 1.608118] nicpf, ver 1.0
10586 13:43:55.076508 <6>[ 1.612133] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 13:43:55.079735 <6>[ 1.619609] hns3: Copyright (c) 2017 Huawei Corporation.
10588 13:43:55.083104 <6>[ 1.625196] hclge is initializing
10589 13:43:55.090019 <6>[ 1.628777] e1000: Intel(R) PRO/1000 Network Driver
10590 13:43:55.096299 <6>[ 1.633906] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 13:43:55.099528 <6>[ 1.639921] e1000e: Intel(R) PRO/1000 Network Driver
10592 13:43:55.106157 <6>[ 1.645137] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 13:43:55.112841 <6>[ 1.651328] igb: Intel(R) Gigabit Ethernet Network Driver
10594 13:43:55.120181 <6>[ 1.656979] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 13:43:55.126131 <6>[ 1.662815] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 13:43:55.133072 <6>[ 1.669333] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 13:43:55.136029 <6>[ 1.675796] sky2: driver version 1.30
10598 13:43:55.143129 <6>[ 1.680714] usbcore: registered new device driver r8152-cfgselector
10599 13:43:55.149438 <6>[ 1.687248] usbcore: registered new interface driver r8152
10600 13:43:55.152984 <6>[ 1.693065] VFIO - User Level meta-driver version: 0.3
10601 13:43:55.162152 <6>[ 1.701303] usbcore: registered new interface driver usb-storage
10602 13:43:55.168771 <6>[ 1.707748] usbcore: registered new device driver onboard-usb-hub
10603 13:43:55.177630 <6>[ 1.716900] mt6397-rtc mt6359-rtc: registered as rtc0
10604 13:43:55.187674 <6>[ 1.722362] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:42:45 UTC (1716903765)
10605 13:43:55.191088 <6>[ 1.731929] i2c_dev: i2c /dev entries driver
10606 13:43:55.208165 <6>[ 1.743770] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10607 13:43:55.214625 <4>[ 1.752497] cpu cpu0: supply cpu not found, using dummy regulator
10608 13:43:55.221501 <4>[ 1.758917] cpu cpu1: supply cpu not found, using dummy regulator
10609 13:43:55.227712 <4>[ 1.765327] cpu cpu2: supply cpu not found, using dummy regulator
10610 13:43:55.234728 <4>[ 1.771747] cpu cpu3: supply cpu not found, using dummy regulator
10611 13:43:55.241164 <4>[ 1.778145] cpu cpu4: supply cpu not found, using dummy regulator
10612 13:43:55.248235 <4>[ 1.784543] cpu cpu5: supply cpu not found, using dummy regulator
10613 13:43:55.254165 <4>[ 1.790938] cpu cpu6: supply cpu not found, using dummy regulator
10614 13:43:55.261105 <4>[ 1.797333] cpu cpu7: supply cpu not found, using dummy regulator
10615 13:43:55.278543 <6>[ 1.817978] cpu cpu0: EM: created perf domain
10616 13:43:55.282049 <6>[ 1.822930] cpu cpu4: EM: created perf domain
10617 13:43:55.289341 <6>[ 1.828507] sdhci: Secure Digital Host Controller Interface driver
10618 13:43:55.295940 <6>[ 1.834940] sdhci: Copyright(c) Pierre Ossman
10619 13:43:55.302509 <6>[ 1.839904] Synopsys Designware Multimedia Card Interface Driver
10620 13:43:55.309363 <6>[ 1.846537] sdhci-pltfm: SDHCI platform and OF driver helper
10621 13:43:55.312820 <6>[ 1.846662] mmc0: CQHCI version 5.10
10622 13:43:55.319120 <6>[ 1.856629] ledtrig-cpu: registered to indicate activity on CPUs
10623 13:43:55.325710 <6>[ 1.863705] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10624 13:43:55.332353 <6>[ 1.870755] usbcore: registered new interface driver usbhid
10625 13:43:55.335847 <6>[ 1.876585] usbhid: USB HID core driver
10626 13:43:55.342086 <6>[ 1.880784] spi_master spi0: will run message pump with realtime priority
10627 13:43:55.386947 <6>[ 1.919628] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10628 13:43:55.405170 <6>[ 1.934566] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10629 13:43:55.409122 <6>[ 1.948174] mmc0: Command Queue Engine enabled
10630 13:43:55.415757 <6>[ 1.952950] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10631 13:43:55.422451 <6>[ 1.959883] cros-ec-spi spi0.0: Chrome EC device registered
10632 13:43:55.425363 <6>[ 1.960200] mmcblk0: mmc0:0001 DA4128 116 GiB
10633 13:43:55.438559 <6>[ 1.978124] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10634 13:43:55.445902 <6>[ 1.985604] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 13:43:55.456233 <6>[ 1.989142] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10636 13:43:55.459323 <6>[ 1.991456] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10637 13:43:55.466088 <6>[ 2.001302] NET: Registered PF_PACKET protocol family
10638 13:43:55.472858 <6>[ 2.006006] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 13:43:55.475833 <6>[ 2.010721] 9pnet: Installing 9P2000 support
10640 13:43:55.482686 <5>[ 2.021740] Key type dns_resolver registered
10641 13:43:55.486309 <6>[ 2.026680] registered taskstats version 1
10642 13:43:55.492733 <5>[ 2.031057] Loading compiled-in X.509 certificates
10643 13:43:55.520455 <4>[ 2.053633] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 13:43:55.530566 <4>[ 2.064400] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 13:43:55.545353 <6>[ 2.085234] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 13:43:55.552267 <6>[ 2.092157] xhci-mtk 11200000.usb: xHCI Host Controller
10647 13:43:55.559289 <6>[ 2.097729] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 13:43:55.569678 <6>[ 2.105587] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 13:43:55.576076 <6>[ 2.115018] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 13:43:55.582938 <6>[ 2.121199] xhci-mtk 11200000.usb: xHCI Host Controller
10651 13:43:55.589521 <6>[ 2.126701] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 13:43:55.596095 <6>[ 2.134357] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 13:43:55.603005 <6>[ 2.142097] hub 1-0:1.0: USB hub found
10654 13:43:55.606440 <6>[ 2.146118] hub 1-0:1.0: 1 port detected
10655 13:43:55.613042 <6>[ 2.150394] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 13:43:55.619599 <6>[ 2.159033] hub 2-0:1.0: USB hub found
10657 13:43:55.622912 <6>[ 2.163052] hub 2-0:1.0: 1 port detected
10658 13:43:55.630405 <6>[ 2.169979] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 13:43:55.641971 <6>[ 2.178096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10660 13:43:55.648799 <6>[ 2.186129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 13:43:55.659105 <4>[ 2.194022] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10662 13:43:55.668934 <6>[ 2.203546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10663 13:43:55.675419 <6>[ 2.211622] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 13:43:55.682165 <6>[ 2.219757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 13:43:55.691959 <6>[ 2.227687] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 13:43:55.698941 <6>[ 2.235504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10667 13:43:55.708714 <6>[ 2.243322] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 13:43:55.718745 <6>[ 2.253804] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 13:43:55.725435 <6>[ 2.262192] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 13:43:55.735345 <6>[ 2.270531] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 13:43:55.741852 <6>[ 2.278869] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 13:43:55.751785 <6>[ 2.287208] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 13:43:55.758547 <6>[ 2.295550] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 13:43:55.768510 <6>[ 2.303887] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 13:43:55.775210 <6>[ 2.312225] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 13:43:55.785158 <6>[ 2.320563] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 13:43:55.792060 <6>[ 2.328901] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 13:43:55.802044 <6>[ 2.337238] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 13:43:55.808393 <6>[ 2.345576] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 13:43:55.818461 <6>[ 2.353913] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 13:43:55.824618 <6>[ 2.362254] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 13:43:55.835453 <6>[ 2.370594] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 13:43:55.841816 <6>[ 2.379326] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 13:43:55.848356 <6>[ 2.386456] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 13:43:55.855395 <6>[ 2.393211] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 13:43:55.861724 <6>[ 2.399977] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 13:43:55.868187 <6>[ 2.406904] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 13:43:55.878083 <6>[ 2.413752] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 13:43:55.887982 <6>[ 2.422888] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 13:43:55.898052 <6>[ 2.432006] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 13:43:55.908044 <6>[ 2.441303] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 13:43:55.914378 <6>[ 2.450770] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 13:43:55.924292 <6>[ 2.460238] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 13:43:55.934086 <6>[ 2.469374] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 13:43:55.944260 <6>[ 2.478840] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 13:43:55.954413 <6>[ 2.487960] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 13:43:55.964210 <6>[ 2.497254] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 13:43:55.974111 <6>[ 2.507435] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 13:43:55.983890 <6>[ 2.519489] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 13:43:55.990636 <6>[ 2.529124] Trying to probe devices needed for running init ...
10701 13:43:56.011811 <6>[ 2.547854] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10702 13:43:56.040071 <6>[ 2.578992] hub 2-1:1.0: USB hub found
10703 13:43:56.043000 <6>[ 2.583444] hub 2-1:1.0: 3 ports detected
10704 13:43:56.051454 <6>[ 2.590919] hub 2-1:1.0: USB hub found
10705 13:43:56.054760 <6>[ 2.595222] hub 2-1:1.0: 3 ports detected
10706 13:43:56.163543 <6>[ 2.699600] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10707 13:43:56.318161 <6>[ 2.857667] hub 1-1:1.0: USB hub found
10708 13:43:56.321592 <6>[ 2.862126] hub 1-1:1.0: 4 ports detected
10709 13:43:56.331272 <6>[ 2.870728] hub 1-1:1.0: USB hub found
10710 13:43:56.334705 <6>[ 2.875061] hub 1-1:1.0: 4 ports detected
10711 13:43:56.403858 <6>[ 2.939893] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10712 13:43:56.511965 <6>[ 3.048283] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10713 13:43:56.547697 <4>[ 3.083908] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10714 13:43:56.557775 <4>[ 3.093046] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10715 13:43:56.597756 <6>[ 3.137086] r8152 2-1.3:1.0 eth0: v1.12.13
10716 13:43:56.655039 <6>[ 3.191648] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10717 13:43:56.788604 <6>[ 3.327644] hub 1-1.4:1.0: USB hub found
10718 13:43:56.791304 <6>[ 3.332314] hub 1-1.4:1.0: 2 ports detected
10719 13:43:56.801155 <6>[ 3.340676] hub 1-1.4:1.0: USB hub found
10720 13:43:56.804737 <6>[ 3.345267] hub 1-1.4:1.0: 2 ports detected
10721 13:43:57.107903 <6>[ 3.643679] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10722 13:43:57.299624 <6>[ 3.835666] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10723 13:43:58.214934 <6>[ 4.754501] r8152 2-1.3:1.0 eth0: carrier on
10724 13:44:00.687592 <5>[ 4.779440] Sending DHCP requests .., OK
10725 13:44:00.694384 <6>[ 7.231789] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10726 13:44:00.697812 <6>[ 7.240081] IP-Config: Complete:
10727 13:44:00.711104 <6>[ 7.243581] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10728 13:44:00.717499 <6>[ 7.254288] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10729 13:44:00.723984 <6>[ 7.262906] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10730 13:44:00.731123 <6>[ 7.262915] nameserver0=192.168.201.1
10731 13:44:00.734256 <6>[ 7.275067] clk: Disabling unused clocks
10732 13:44:00.737444 <6>[ 7.280565] ALSA device list:
10733 13:44:00.743723 <6>[ 7.283822] No soundcards found.
10734 13:44:00.751426 <6>[ 7.291194] Freeing unused kernel memory: 8512K
10735 13:44:00.754090 <6>[ 7.296194] Run /init as init process
10736 13:44:00.763894 Loading, please wait...
10737 13:44:00.790547 Starting systemd-udevd version 252.22-1~deb12u1
10738 13:44:01.046882 <6>[ 7.583701] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10739 13:44:01.069890 <6>[ 7.609809] remoteproc remoteproc0: scp is available
10740 13:44:01.076874 <6>[ 7.615357] remoteproc remoteproc0: powering up scp
10741 13:44:01.082834 <6>[ 7.620553] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10742 13:44:01.089685 <6>[ 7.629028] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10743 13:44:01.107989 <3>[ 7.644551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 13:44:01.114392 <3>[ 7.652746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 13:44:01.124743 <6>[ 7.660050] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10746 13:44:01.131003 <3>[ 7.660938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 13:44:01.141414 <6>[ 7.668467] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10748 13:44:01.144332 <6>[ 7.670321] mc: Linux media interface: v0.10
10749 13:44:01.151146 <4>[ 7.672526] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10750 13:44:01.157610 <6>[ 7.686008] videodev: Linux video capture interface: v2.00
10751 13:44:01.167928 <6>[ 7.689762] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10752 13:44:01.174497 <4>[ 7.692213] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10753 13:44:01.181099 <3>[ 7.694408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 13:44:01.190872 <3>[ 7.694424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 13:44:01.197667 <3>[ 7.694428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 13:44:01.207317 <3>[ 7.694435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 13:44:01.214073 <3>[ 7.694439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 13:44:01.223825 <3>[ 7.694476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 13:44:01.230565 <3>[ 7.694518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 13:44:01.240698 <3>[ 7.695205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 13:44:01.247095 <3>[ 7.695228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 13:44:01.254004 <3>[ 7.695421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 13:44:01.263849 <3>[ 7.695430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 13:44:01.270681 <3>[ 7.695437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 13:44:01.280603 <3>[ 7.695448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 13:44:01.287238 <3>[ 7.695456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 13:44:01.297141 <3>[ 7.700761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 13:44:01.303390 <6>[ 7.703992] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10769 13:44:01.310435 <6>[ 7.759981] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10770 13:44:01.320383 <6>[ 7.760024] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10771 13:44:01.326679 <6>[ 7.760033] remoteproc remoteproc0: remote processor scp is now up
10772 13:44:01.333754 <6>[ 7.824904] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10773 13:44:01.343409 <6>[ 7.835385] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10774 13:44:01.350620 <6>[ 7.835796] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10775 13:44:01.357032 <6>[ 7.840722] pci_bus 0000:00: root bus resource [bus 00-ff]
10776 13:44:01.367251 <6>[ 7.841067] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10777 13:44:01.374028 <4>[ 7.849481] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10778 13:44:01.380528 <4>[ 7.849481] Fallback method does not support PEC.
10779 13:44:01.387486 <6>[ 7.849889] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10780 13:44:01.397081 <6>[ 7.855540] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10781 13:44:01.403476 <6>[ 7.856888] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10782 13:44:01.413659 <3>[ 7.896065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 13:44:01.423677 <6>[ 7.896838] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10784 13:44:01.426967 <6>[ 7.925804] Bluetooth: Core ver 2.22
10785 13:44:01.433751 <6>[ 7.933468] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10786 13:44:01.436893 <6>[ 7.940602] NET: Registered PF_BLUETOOTH protocol family
10787 13:44:01.446498 <6>[ 7.941862] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10788 13:44:01.456343 <6>[ 7.943242] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10789 13:44:01.463360 <6>[ 7.943460] usbcore: registered new interface driver uvcvideo
10790 13:44:01.469688 <6>[ 7.948800] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10791 13:44:01.476902 <6>[ 7.957571] Bluetooth: HCI device and connection manager initialized
10792 13:44:01.483826 <6>[ 7.958181] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 13:44:01.487340 <6>[ 7.967527] pci 0000:00:00.0: supports D1 D2
10794 13:44:01.493998 <6>[ 7.971301] Bluetooth: HCI socket layer initialized
10795 13:44:01.500327 <6>[ 7.977586] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10796 13:44:01.507290 <6>[ 7.983108] Bluetooth: L2CAP socket layer initialized
10797 13:44:01.513766 <6>[ 7.991042] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10798 13:44:01.520438 <6>[ 8.002569] Bluetooth: SCO socket layer initialized
10799 13:44:01.527147 <6>[ 8.008653] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10800 13:44:01.533718 <3>[ 8.028303] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 13:44:01.543289 <6>[ 8.029185] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10802 13:44:01.546395 <6>[ 8.064810] usbcore: registered new interface driver btusb
10803 13:44:01.556387 <4>[ 8.065889] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10804 13:44:01.563110 <3>[ 8.065896] Bluetooth: hci0: Failed to load firmware file (-2)
10805 13:44:01.569548 <3>[ 8.065897] Bluetooth: hci0: Failed to set up firmware (-2)
10806 13:44:01.579503 <4>[ 8.065900] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10807 13:44:01.586309 <6>[ 8.070614] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10808 13:44:01.595848 <6>[ 8.132890] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10809 13:44:01.599252 <6>[ 8.140479] pci 0000:01:00.0: supports D1 D2
10810 13:44:01.606038 <6>[ 8.144999] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10811 13:44:01.626237 <6>[ 8.163517] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10812 13:44:01.633199 <6>[ 8.170422] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10813 13:44:01.640092 <6>[ 8.178503] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10814 13:44:01.649984 <6>[ 8.186501] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10815 13:44:01.656372 <6>[ 8.194505] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10816 13:44:01.666314 <6>[ 8.202506] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10817 13:44:01.669773 <6>[ 8.210505] pci 0000:00:00.0: PCI bridge to [bus 01]
10818 13:44:01.679795 <6>[ 8.215722] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10819 13:44:01.686103 <6>[ 8.223858] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10820 13:44:01.692854 <6>[ 8.230691] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10821 13:44:01.699268 <6>[ 8.237413] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10822 13:44:01.713956 <5>[ 8.251135] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10823 13:44:01.734173 <5>[ 8.271196] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10824 13:44:01.740796 <5>[ 8.278586] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10825 13:44:01.750870 <4>[ 8.287053] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10826 13:44:01.754184 <6>[ 8.295971] cfg80211: failed to load regulatory.db
10827 13:44:01.802750 <6>[ 8.339931] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10828 13:44:01.809257 <6>[ 8.347436] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10829 13:44:01.833623 <6>[ 8.374242] mt7921e 0000:01:00.0: ASIC revision: 79610010
10830 13:44:01.938433 <6>[ 8.475517] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10831 13:44:01.941916 <6>[ 8.475517]
10832 13:44:01.945229 Begin: Loading essential drivers ... done.
10833 13:44:01.948464 Begin: Running /scripts/init-premount ... done.
10834 13:44:01.954805 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10835 13:44:01.964667 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10836 13:44:01.968043 Device /sys/class/net/eth0 found
10837 13:44:01.968125 done.
10838 13:44:01.974506 Begin: Waiting up to 180 secs for any network device to become available ... done.
10839 13:44:02.019669 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10840 13:44:02.026083 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10841 13:44:02.032547 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10842 13:44:02.039348 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10843 13:44:02.046324 host : mt8192-asurada-spherion-r0-cbg-1
10844 13:44:02.052880 domain : lava-rack
10845 13:44:02.055667 rootserver: 192.168.201.1 rootpath:
10846 13:44:02.055819 filename :
10847 13:44:02.164641 done.
10848 13:44:02.171795 Begin: Running /scripts/nfs-bottom ... done.
10849 13:44:02.188624 Begin: Running /scripts/init-bottom ... done.
10850 13:44:02.205743 <6>[ 8.742804] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10851 13:44:03.496867 <6>[ 10.037059] NET: Registered PF_INET6 protocol family
10852 13:44:03.504072 <6>[ 10.044643] Segment Routing with IPv6
10853 13:44:03.507450 <6>[ 10.048641] In-situ OAM (IOAM) with IPv6
10854 13:44:03.674279 <30>[ 10.187847] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10855 13:44:03.680787 <30>[ 10.220940] systemd[1]: Detected architecture arm64.
10856 13:44:03.688304
10857 13:44:03.691615 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10858 13:44:03.692070
10859 13:44:03.717097 <30>[ 10.257097] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10860 13:44:04.780799 <30>[ 11.318049] systemd[1]: Queued start job for default target graphical.target.
10861 13:44:04.831860 <30>[ 11.368660] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10862 13:44:04.838167 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10863 13:44:04.860674 <30>[ 11.397424] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10864 13:44:04.870426 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10865 13:44:04.888602 <30>[ 11.425372] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10866 13:44:04.898217 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10867 13:44:04.916221 <30>[ 11.453035] systemd[1]: Created slice user.slice - User and Session Slice.
10868 13:44:04.922507 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10869 13:44:04.946638 <30>[ 11.479918] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10870 13:44:04.953118 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10871 13:44:04.974411 <30>[ 11.507864] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10872 13:44:04.980884 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10873 13:44:05.008594 <30>[ 11.535772] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10874 13:44:05.018885 <30>[ 11.555579] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10875 13:44:05.025262 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10876 13:44:05.043111 <30>[ 11.580044] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10877 13:44:05.052979 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10878 13:44:05.070880 <30>[ 11.607731] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10879 13:44:05.080366 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10880 13:44:05.095705 <30>[ 11.636163] systemd[1]: Reached target paths.target - Path Units.
10881 13:44:05.105997 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10882 13:44:05.122908 <30>[ 11.660082] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10883 13:44:05.129828 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10884 13:44:05.143458 <30>[ 11.683613] systemd[1]: Reached target slices.target - Slice Units.
10885 13:44:05.153890 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10886 13:44:05.167852 <30>[ 11.708114] systemd[1]: Reached target swap.target - Swaps.
10887 13:44:05.174830 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10888 13:44:05.195131 <30>[ 11.732170] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10889 13:44:05.204950 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10890 13:44:05.223719 <30>[ 11.760468] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10891 13:44:05.233705 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10892 13:44:05.253947 <30>[ 11.790724] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10893 13:44:05.263440 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10894 13:44:05.279716 <30>[ 11.817028] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10895 13:44:05.290087 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10896 13:44:05.307430 <30>[ 11.844389] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10897 13:44:05.314072 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10898 13:44:05.332190 <30>[ 11.869252] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10899 13:44:05.342200 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10900 13:44:05.361024 <30>[ 11.898469] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10901 13:44:05.370815 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10902 13:44:05.387690 <30>[ 11.924839] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10903 13:44:05.397672 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10904 13:44:05.438502 <30>[ 11.975666] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10905 13:44:05.444805 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10906 13:44:05.466402 <30>[ 12.003883] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10907 13:44:05.473284 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10908 13:44:05.534880 <30>[ 12.071836] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10909 13:44:05.541474 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10910 13:44:05.564794 <30>[ 12.095923] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10911 13:44:05.577252 <30>[ 12.114975] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10912 13:44:05.587198 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10913 13:44:05.626965 <30>[ 12.164326] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10914 13:44:05.633855 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10915 13:44:05.660288 <30>[ 12.197555] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10916 13:44:05.667344 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10917 13:44:05.692275 <30>[ 12.229445] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10918 13:44:05.702304 Startin<6>[ 12.238565] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10919 13:44:05.708632 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10920 13:44:05.762888 <30>[ 12.300413] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10921 13:44:05.772886 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10922 13:44:05.795318 <30>[ 12.332918] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10923 13:44:05.802061 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10924 13:44:05.826327 <30>[ 12.364093] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10925 13:44:05.833208 Starting [0;1;39mmodpr<6>[ 12.374394] fuse: init (API version 7.37)
10926 13:44:05.839477 obe@loop.ser…e[0m - Load Kernel Module loop...
10927 13:44:05.886231 <30>[ 12.424053] systemd[1]: Starting systemd-journald.service - Journal Service...
10928 13:44:05.892934 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10929 13:44:05.916724 <30>[ 12.454451] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10930 13:44:05.923616 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10931 13:44:05.974494 <30>[ 12.508639] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10932 13:44:05.981031 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10933 13:44:06.004545 <30>[ 12.542078] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10934 13:44:06.014380 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10935 13:44:06.034269 <30>[ 12.571849] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10936 13:44:06.041185 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10937 13:44:06.071349 <30>[ 12.608231] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10938 13:44:06.085016 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - H<3>[ 12.620813] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 13:44:06.085106 uge Pages File System.
10940 13:44:06.107183 <30>[ 12.644110] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10941 13:44:06.116803 [[0;32m OK [0m] Mounted [0;<3>[ 12.654346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 13:44:06.123596 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10943 13:44:06.142369 <30>[ 12.679842] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10944 13:44:06.149348 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10945 13:44:06.159113 <3>[ 12.696571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 13:44:06.174873 <30>[ 12.712179] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10947 13:44:06.188632 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate <3>[ 12.725637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 13:44:06.191572 List of Static Device Nodes.
10949 13:44:06.215592 <30>[ 12.752687] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10950 13:44:06.222374 <30>[ 12.761122] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10951 13:44:06.235440 [[0;32m OK [<3>[ 12.771256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 13:44:06.242102 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10953 13:44:06.259543 <30>[ 12.796727] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10954 13:44:06.265939 <3>[ 12.801756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 13:44:06.275742 <30>[ 12.804744] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10956 13:44:06.282430 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10957 13:44:06.295686 <3>[ 12.832913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 13:44:06.306574 <30>[ 12.844273] systemd[1]: modprobe@drm.service: Deactivated successfully.
10959 13:44:06.313480 <30>[ 12.852105] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10960 13:44:06.326665 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 12.865180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 13:44:06.330100 Load Kernel Module drm.
10962 13:44:06.351584 <30>[ 12.888780] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10963 13:44:06.361310 <30>[ 12.897555] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10964 13:44:06.367714 <3>[ 12.897563] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 13:44:06.384977 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module<3>[ 12.921231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 13:44:06.388359 efi_pstore.
10967 13:44:06.412611 <30>[ 12.950046] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10968 13:44:06.419582 <30>[ 12.958058] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10969 13:44:06.429506 <3>[ 12.966245] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 13:44:06.435923 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10971 13:44:06.454749 <30>[ 12.992535] systemd[1]: modprobe@loop.service: Deactivated successfully.
10972 13:44:06.462055 <30>[ 13.000168] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10973 13:44:06.472625 [[0;32m OK [0m] Finished [0<3>[ 13.010829] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 13:44:06.485670 ;1;39mmodprobe@l<3>[ 13.013289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10975 13:44:06.499109 <4>[ 13.019772] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10976 13:44:06.509146 oop.service[0m <3>[ 13.045535] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10977 13:44:06.519302 - Load Kernel Mo<3>[ 13.050324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:44:06.519388 dule loop.
10979 13:44:06.539525 <30>[ 13.076821] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10980 13:44:06.549764 [[0;32m OK [0m] Finished [0<3>[ 13.086967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 13:44:06.556488 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10982 13:44:06.578462 <30>[ 13.112153] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10983 13:44:06.585188 <3>[ 13.121237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 13:44:06.595397 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10985 13:44:06.611657 <30>[ 13.148841] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10986 13:44:06.621219 <3>[ 13.154978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 13:44:06.628296 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10988 13:44:06.647192 <30>[ 13.184008] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10989 13:44:06.654074 <3>[ 13.189851] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 13:44:06.663834 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10991 13:44:06.684006 <30>[ 13.221333] systemd[1]: Reached target network-pre.target - Preparation for Network.
10992 13:44:06.690496 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10993 13:44:06.754245 <30>[ 13.291731] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10994 13:44:06.760857 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10995 13:44:06.787305 <30>[ 13.324749] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10996 13:44:06.793654 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10997 13:44:06.817185 <30>[ 13.351805] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10998 13:44:06.834107 <30>[ 13.365443] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10999 13:44:06.848773 <30>[ 13.386657] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11000 13:44:06.855548 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11001 13:44:06.880513 <30>[ 13.414868] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11002 13:44:06.935130 <30>[ 13.472469] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11003 13:44:06.941507 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11004 13:44:06.966699 <30>[ 13.504369] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11005 13:44:06.976447 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11006 13:44:07.006777 <30>[ 13.544603] systemd[1]: Started systemd-journald.service - Journal Service.
11007 13:44:07.013515 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11008 13:44:07.035458 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11009 13:44:07.054608 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11010 13:44:07.079041 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11011 13:44:07.099299 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11012 13:44:07.119801 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11013 13:44:07.167219 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11014 13:44:07.190935 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11015 13:44:07.217693 <46>[ 13.755686] systemd-journald[311]: Received client request to flush runtime journal.
11016 13:44:07.985852 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11017 13:44:08.002736 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11018 13:44:08.022392 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11019 13:44:08.339226 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11020 13:44:08.620310 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11021 13:44:08.657219 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11022 13:44:08.806592 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11023 13:44:08.908545 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11024 13:44:08.932108 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11025 13:44:08.967827 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11026 13:44:09.135401 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11027 13:44:09.162181 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11028 13:44:09.248720 <6>[ 15.789864] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11029 13:44:09.269696 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11030 13:44:09.331804 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11031 13:44:09.392780 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11032 13:44:09.432976 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11033 13:44:09.451347 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11034 13:44:09.507129 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11035 13:44:09.528692 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11036 13:44:09.546233 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11037 13:44:09.564921 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11038 13:44:09.583272 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11039 13:44:09.616463 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11040 13:44:09.637730 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11041 13:44:09.654089 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11042 13:44:09.669917 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11043 13:44:09.691548 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11044 13:44:09.711910 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11045 13:44:09.728704 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11046 13:44:09.761724 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11047 13:44:09.781541 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11048 13:44:09.797597 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11049 13:44:09.814677 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11050 13:44:09.832503 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11051 13:44:09.848078 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11052 13:44:09.891989 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11053 13:44:09.957763 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11054 13:44:10.048797 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11055 13:44:10.083567 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11056 13:44:10.142460 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11057 13:44:10.181130 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11058 13:44:10.228043 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11059 13:44:10.279709 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11060 13:44:10.299203 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11061 13:44:10.322567 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11062 13:44:10.443216 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11063 13:44:10.467852 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11064 13:44:10.488447 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11065 13:44:10.546784 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11066 13:44:10.586771 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11067 13:44:10.679917
11068 13:44:10.683098 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11069 13:44:10.683576
11070 13:44:10.686675 debian-bookworm-arm64 login: root (automatic login)
11071 13:44:10.687148
11072 13:44:10.987073 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11073 13:44:10.987794
11074 13:44:10.993743 The programs included with the Debian GNU/Linux system are free software;
11075 13:44:11.000361 the exact distribution terms for each program are described in the
11076 13:44:11.003744 individual files in /usr/share/doc/*/copyright.
11077 13:44:11.004382
11078 13:44:11.010391 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11079 13:44:11.013155 permitted by applicable law.
11080 13:44:11.977915 Matched prompt #10: / #
11082 13:44:11.979292 Setting prompt string to ['/ #']
11083 13:44:11.979747 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11085 13:44:11.981043 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11086 13:44:11.981539 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
11087 13:44:11.981920 Setting prompt string to ['/ #']
11088 13:44:11.982241 Forcing a shell prompt, looking for ['/ #']
11090 13:44:12.032899 / #
11091 13:44:12.033231 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11092 13:44:12.033457 Waiting using forced prompt support (timeout 00:02:30)
11093 13:44:12.038718
11094 13:44:12.039316 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11095 13:44:12.039583 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
11097 13:44:12.140654 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha'
11098 13:44:12.147763 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14063105/extract-nfsrootfs-da5klrha'
11100 13:44:12.249834 / # export NFS_SERVER_IP='192.168.201.1'
11101 13:44:12.256081 export NFS_SERVER_IP='192.168.201.1'
11102 13:44:12.257029 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11103 13:44:12.257634 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
11104 13:44:12.258146 end: 2 depthcharge-action (duration 00:01:17) [common]
11105 13:44:12.258641 start: 3 lava-test-retry (timeout 00:08:04) [common]
11106 13:44:12.259133 start: 3.1 lava-test-shell (timeout 00:08:04) [common]
11107 13:44:12.259560 Using namespace: common
11109 13:44:12.360840 / # #
11110 13:44:12.361573 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11111 13:44:12.367203 #
11112 13:44:12.368068 Using /lava-14063105
11114 13:44:12.469475 / # export SHELL=/bin/bash
11115 13:44:12.476247 export SHELL=/bin/bash
11117 13:44:12.577932 / # . /lava-14063105/environment
11118 13:44:12.584449 . /lava-14063105/environment
11120 13:44:12.691880 / # /lava-14063105/bin/lava-test-runner /lava-14063105/0
11121 13:44:12.692531 Test shell timeout: 10s (minimum of the action and connection timeout)
11122 13:44:12.698132 /lava-14063105/bin/lava-test-runner /lava-14063105/0
11123 13:44:12.951712 + export TESTRUN_ID=0_timesync-off
11124 13:44:12.954574 + TESTRUN_ID=0_timesync-off
11125 13:44:12.957932 + cd /lava-14063105/0/tests/0_timesync-off
11126 13:44:12.961369 ++ cat uuid
11127 13:44:12.964842 + UUID=14063105_1.6.2.3.1
11128 13:44:12.965267 + set +x
11129 13:44:12.971097 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14063105_1.6.2.3.1>
11130 13:44:12.971684 Received signal: <STARTRUN> 0_timesync-off 14063105_1.6.2.3.1
11131 13:44:12.971758 Starting test lava.0_timesync-off (14063105_1.6.2.3.1)
11132 13:44:12.971844 Skipping test definition patterns.
11133 13:44:12.974038 + systemctl stop systemd-timesyncd
11134 13:44:13.028801 + set +x
11135 13:44:13.031759 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14063105_1.6.2.3.1>
11136 13:44:13.032497 Received signal: <ENDRUN> 0_timesync-off 14063105_1.6.2.3.1
11137 13:44:13.032984 Ending use of test pattern.
11138 13:44:13.033356 Ending test lava.0_timesync-off (14063105_1.6.2.3.1), duration 0.06
11140 13:44:13.095210 + export TESTRUN_ID=1_kselftest-tpm2
11141 13:44:13.098137 + TESTRUN_ID=1_kselftest-tpm2
11142 13:44:13.101640 + cd /lava-14063105/0/tests/1_kselftest-tpm2
11143 13:44:13.104881 ++ cat uuid
11144 13:44:13.108351 + UUID=14063105_1.6.2.3.5
11145 13:44:13.108436 + set +x
11146 13:44:13.115050 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14063105_1.6.2.3.5>
11147 13:44:13.115306 Received signal: <STARTRUN> 1_kselftest-tpm2 14063105_1.6.2.3.5
11148 13:44:13.115377 Starting test lava.1_kselftest-tpm2 (14063105_1.6.2.3.5)
11149 13:44:13.115459 Skipping test definition patterns.
11150 13:44:13.118228 + cd ./automated/linux/kselftest/
11151 13:44:13.141542 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11152 13:44:13.182338 INFO: install_deps skipped
11153 13:44:13.680320 --2024-05-28 13:43:04-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11154 13:44:13.694943 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11155 13:44:13.823773 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11156 13:44:13.952246 HTTP request sent, awaiting response... 200 OK
11157 13:44:13.955532 Length: 1642660 (1.6M) [application/octet-stream]
11158 13:44:13.958864 Saving to: 'kselftest_armhf.tar.gz'
11159 13:44:13.959361
11160 13:44:13.959832
11161 13:44:14.208929 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11162 13:44:14.465248 kselftest_armhf.tar 2%[ ] 46.39K 177KB/s
11163 13:44:14.721199 kselftest_armhf.tar 13%[=> ] 214.67K 409KB/s
11164 13:44:14.907935 kselftest_armhf.tar 55%[==========> ] 893.42K 1.11MB/s
11165 13:44:14.914903 kselftest_armhf.tar 100%[===================>] 1.57M 1.60MB/s in 1.0s
11166 13:44:14.915382
11167 13:44:15.065156 2024-05-28 13:43:05 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [1642660/1642660]
11168 13:44:15.065314
11169 13:44:19.114746 skiplist:
11170 13:44:19.118198 ========================================
11171 13:44:19.121102 ========================================
11172 13:44:19.165232 tpm2:test_smoke.sh
11173 13:44:19.168454 tpm2:test_space.sh
11174 13:44:19.184019 ============== Tests to run ===============
11175 13:44:19.184125 tpm2:test_smoke.sh
11176 13:44:19.187287 tpm2:test_space.sh
11177 13:44:19.190696 ===========End Tests to run ===============
11178 13:44:19.194227 shardfile-tpm2 pass
11179 13:44:19.301037 <12>[ 25.843325] kselftest: Running tests in tpm2
11180 13:44:19.309440 TAP version 13
11181 13:44:19.325457 1..2
11182 13:44:19.356309 # selftests: tpm2: test_smoke.sh
11183 13:44:21.238727 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11184 13:44:21.245358 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11185 13:44:21.252022 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11186 13:44:21.255242 # Traceback (most recent call last):
11187 13:44:21.265042 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11188 13:44:21.265583 # if self.tpm:
11189 13:44:21.268508 # ^^^^^^^^
11190 13:44:21.272060 # AttributeError: 'Client' object has no attribute 'tpm'
11191 13:44:21.278561 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11192 13:44:21.285154 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11193 13:44:21.288594 # Traceback (most recent call last):
11194 13:44:21.298823 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11195 13:44:21.299298 # if self.tpm:
11196 13:44:21.301768 # ^^^^^^^^
11197 13:44:21.305228 # AttributeError: 'Client' object has no attribute 'tpm'
11198 13:44:21.311979 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11199 13:44:21.318520 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11200 13:44:21.321952 # Traceback (most recent call last):
11201 13:44:21.331708 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11202 13:44:21.334916 # if self.tpm:
11203 13:44:21.335384 # ^^^^^^^^
11204 13:44:21.341849 # AttributeError: 'Client' object has no attribute 'tpm'
11205 13:44:21.348295 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11206 13:44:21.355046 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11207 13:44:21.358416 # Traceback (most recent call last):
11208 13:44:21.368552 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11209 13:44:21.369033 # if self.tpm:
11210 13:44:21.371935 # ^^^^^^^^
11211 13:44:21.375476 # AttributeError: 'Client' object has no attribute 'tpm'
11212 13:44:21.381809 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11213 13:44:21.389020 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11214 13:44:21.391839 # Traceback (most recent call last):
11215 13:44:21.402145 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11216 13:44:21.402647 # if self.tpm:
11217 13:44:21.405634 # ^^^^^^^^
11218 13:44:21.408543 # AttributeError: 'Client' object has no attribute 'tpm'
11219 13:44:21.415503 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11220 13:44:21.422302 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11221 13:44:21.425346 # Traceback (most recent call last):
11222 13:44:21.435181 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11223 13:44:21.438511 # if self.tpm:
11224 13:44:21.438985 # ^^^^^^^^
11225 13:44:21.445659 # AttributeError: 'Client' object has no attribute 'tpm'
11226 13:44:21.452013 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11227 13:44:21.458910 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11228 13:44:21.462188 # Traceback (most recent call last):
11229 13:44:21.472262 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11230 13:44:21.472697 # if self.tpm:
11231 13:44:21.475766 # ^^^^^^^^
11232 13:44:21.479106 # AttributeError: 'Client' object has no attribute 'tpm'
11233 13:44:21.489158 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11234 13:44:21.495759 # Exception ignored in: <function Client.__del__ at 0xffffa165ccc0>
11235 13:44:21.499146 # Traceback (most recent call last):
11236 13:44:21.508970 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11237 13:44:21.509514 # if self.tpm:
11238 13:44:21.511997 # ^^^^^^^^
11239 13:44:21.515540 # AttributeError: 'Client' object has no attribute 'tpm'
11240 13:44:21.516014 #
11241 13:44:21.521982 # ======================================================================
11242 13:44:21.528609 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11243 13:44:21.535235 # ----------------------------------------------------------------------
11244 13:44:21.538781 # Traceback (most recent call last):
11245 13:44:21.548805 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11246 13:44:21.555155 # self.root_key = self.client.create_root_key()
11247 13:44:21.558659 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11248 13:44:21.568587 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11249 13:44:21.575304 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11250 13:44:21.578964 # ^^^^^^^^^^^^^^^^^^
11251 13:44:21.589190 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11252 13:44:21.592541 # raise ProtocolError(cc, rc)
11253 13:44:21.598918 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11254 13:44:21.599164 #
11255 13:44:21.605243 # ======================================================================
11256 13:44:21.611814 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11257 13:44:21.618636 # ----------------------------------------------------------------------
11258 13:44:21.621726 # Traceback (most recent call last):
11259 13:44:21.631510 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11260 13:44:21.635035 # self.client = tpm2.Client()
11261 13:44:21.638572 # ^^^^^^^^^^^^^
11262 13:44:21.648773 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11263 13:44:21.651961 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11264 13:44:21.658582 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11265 13:44:21.661905 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11266 13:44:21.662059 #
11267 13:44:21.668310 # ======================================================================
11268 13:44:21.675148 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11269 13:44:21.681530 # ----------------------------------------------------------------------
11270 13:44:21.685068 # Traceback (most recent call last):
11271 13:44:21.695304 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11272 13:44:21.698201 # self.client = tpm2.Client()
11273 13:44:21.701586 # ^^^^^^^^^^^^^
11274 13:44:21.711672 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11275 13:44:21.714910 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11276 13:44:21.722031 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11277 13:44:21.724988 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11278 13:44:21.728561 #
11279 13:44:21.734818 # ======================================================================
11280 13:44:21.741676 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11281 13:44:21.745088 # ----------------------------------------------------------------------
11282 13:44:21.748764 # Traceback (most recent call last):
11283 13:44:21.758716 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11284 13:44:21.761720 # self.client = tpm2.Client()
11285 13:44:21.765414 # ^^^^^^^^^^^^^
11286 13:44:21.775147 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11287 13:44:21.782111 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11288 13:44:21.785149 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11289 13:44:21.792122 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11290 13:44:21.792637 #
11291 13:44:21.798560 # ======================================================================
11292 13:44:21.805176 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11293 13:44:21.811988 # ----------------------------------------------------------------------
11294 13:44:21.815579 # Traceback (most recent call last):
11295 13:44:21.825391 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11296 13:44:21.828933 # self.client = tpm2.Client()
11297 13:44:21.831961 # ^^^^^^^^^^^^^
11298 13:44:21.841865 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11299 13:44:21.845128 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11300 13:44:21.852193 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11301 13:44:21.854970 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11302 13:44:21.858414 #
11303 13:44:21.861734 # ======================================================================
11304 13:44:21.868708 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11305 13:44:21.875105 # ----------------------------------------------------------------------
11306 13:44:21.878664 # Traceback (most recent call last):
11307 13:44:21.888404 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11308 13:44:21.891708 # self.client = tpm2.Client()
11309 13:44:21.894963 # ^^^^^^^^^^^^^
11310 13:44:21.905265 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11311 13:44:21.908714 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11312 13:44:21.913193 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11313 13:44:21.920023 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11314 13:44:21.920148 #
11315 13:44:21.927287 # ======================================================================
11316 13:44:21.933778 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11317 13:44:21.937787 # ----------------------------------------------------------------------
11318 13:44:21.941228 # Traceback (most recent call last):
11319 13:44:21.951566 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11320 13:44:21.957378 # self.client = tpm2.Client()
11321 13:44:21.960762 # ^^^^^^^^^^^^^
11322 13:44:21.967930 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11323 13:44:21.974954 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11324 13:44:21.979881 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11325 13:44:21.983426 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11326 13:44:21.983536 #
11327 13:44:21.990070 # ======================================================================
11328 13:44:21.997009 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11329 13:44:22.003667 # ----------------------------------------------------------------------
11330 13:44:22.007053 # Traceback (most recent call last):
11331 13:44:22.016860 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11332 13:44:22.019959 # self.client = tpm2.Client()
11333 13:44:22.023392 # ^^^^^^^^^^^^^
11334 13:44:22.033439 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11335 13:44:22.040411 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11336 13:44:22.043437 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11337 13:44:22.050272 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11338 13:44:22.050719 #
11339 13:44:22.056918 # ======================================================================
11340 13:44:22.063835 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11341 13:44:22.070192 # ----------------------------------------------------------------------
11342 13:44:22.073779 # Traceback (most recent call last):
11343 13:44:22.083873 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11344 13:44:22.086855 # self.client = tpm2.Client()
11345 13:44:22.090468 # ^^^^^^^^^^^^^
11346 13:44:22.100662 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11347 13:44:22.104046 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11348 13:44:22.110165 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11349 13:44:22.113608 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11350 13:44:22.113838 #
11351 13:44:22.120213 # ----------------------------------------------------------------------
11352 13:44:22.124329 # Ran 9 tests in 0.060s
11353 13:44:22.124770 #
11354 13:44:22.126911 # FAILED (errors=9)
11355 13:44:22.130134 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11356 13:44:22.137087 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11357 13:44:22.137567 #
11358 13:44:22.143893 # ----------------------------------------------------------------------
11359 13:44:22.146948 # Ran 2 tests in 0.034s
11360 13:44:22.147299 #
11361 13:44:22.147560 # OK
11362 13:44:22.150319 ok 1 selftests: tpm2: test_smoke.sh
11363 13:44:22.154115 # selftests: tpm2: test_space.sh
11364 13:44:22.160821 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11365 13:44:22.167641 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11366 13:44:22.174016 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11367 13:44:22.180604 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11368 13:44:22.181161 #
11369 13:44:22.187319 # ======================================================================
11370 13:44:22.190662 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11371 13:44:22.197536 # ----------------------------------------------------------------------
11372 13:44:22.200624 # Traceback (most recent call last):
11373 13:44:22.213976 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11374 13:44:22.217342 # root1 = space1.create_root_key()
11375 13:44:22.220541 # ^^^^^^^^^^^^^^^^^^^^^^^^
11376 13:44:22.230337 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11377 13:44:22.237348 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11378 13:44:22.240697 # ^^^^^^^^^^^^^^^^^^
11379 13:44:22.250528 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11380 13:44:22.253862 # raise ProtocolError(cc, rc)
11381 13:44:22.260846 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11382 13:44:22.261398 #
11383 13:44:22.267124 # ======================================================================
11384 13:44:22.274084 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11385 13:44:22.277417 # ----------------------------------------------------------------------
11386 13:44:22.280560 # Traceback (most recent call last):
11387 13:44:22.293694 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11388 13:44:22.296750 # space1.create_root_key()
11389 13:44:22.307219 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11390 13:44:22.310042 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11391 13:44:22.316773 # ^^^^^^^^^^^^^^^^^^
11392 13:44:22.327252 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11393 13:44:22.330071 # raise ProtocolError(cc, rc)
11394 13:44:22.333734 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11395 13:44:22.336948 #
11396 13:44:22.340347 # ======================================================================
11397 13:44:22.346732 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11398 13:44:22.353548 # ----------------------------------------------------------------------
11399 13:44:22.357120 # Traceback (most recent call last):
11400 13:44:22.366953 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11401 13:44:22.370298 # root1 = space1.create_root_key()
11402 13:44:22.373445 # ^^^^^^^^^^^^^^^^^^^^^^^^
11403 13:44:22.386768 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11404 13:44:22.390037 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11405 13:44:22.397112 # ^^^^^^^^^^^^^^^^^^
11406 13:44:22.407462 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11407 13:44:22.410854 # raise ProtocolError(cc, rc)
11408 13:44:22.413981 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11409 13:44:22.414711 #
11410 13:44:22.420738 # ======================================================================
11411 13:44:22.427548 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11412 13:44:22.433911 # ----------------------------------------------------------------------
11413 13:44:22.437408 # Traceback (most recent call last):
11414 13:44:22.450301 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11415 13:44:22.453976 # root1 = space1.create_root_key()
11416 13:44:22.457268 # ^^^^^^^^^^^^^^^^^^^^^^^^
11417 13:44:22.467205 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11418 13:44:22.473966 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11419 13:44:22.477435 # ^^^^^^^^^^^^^^^^^^
11420 13:44:22.487541 # File "/lava-14063105/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11421 13:44:22.490833 # raise ProtocolError(cc, rc)
11422 13:44:22.497421 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11423 13:44:22.497896 #
11424 13:44:22.504024 # ----------------------------------------------------------------------
11425 13:44:22.504493 # Ran 4 tests in 0.093s
11426 13:44:22.504867 #
11427 13:44:22.507419 # FAILED (errors=4)
11428 13:44:22.510814 not ok 2 selftests: tpm2: test_space.sh # exit=1
11429 13:44:22.848791 tpm2_test_smoke_sh pass
11430 13:44:22.852156 tpm2_test_space_sh fail
11431 13:44:22.920014 + ../../utils/send-to-lava.sh ./output/result.txt
11432 13:44:22.977551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11433 13:44:22.977892 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11435 13:44:23.021125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11436 13:44:23.021916 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11438 13:44:23.061546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11439 13:44:23.062572 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11441 13:44:23.065058 + set +x
11442 13:44:23.068003 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14063105_1.6.2.3.5>
11443 13:44:23.068958 Received signal: <ENDRUN> 1_kselftest-tpm2 14063105_1.6.2.3.5
11444 13:44:23.069385 Ending use of test pattern.
11445 13:44:23.069714 Ending test lava.1_kselftest-tpm2 (14063105_1.6.2.3.5), duration 9.95
11447 13:44:23.071469 <LAVA_TEST_RUNNER EXIT>
11448 13:44:23.072204 ok: lava_test_shell seems to have completed
11449 13:44:23.073071 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11450 13:44:23.073701 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11451 13:44:23.074134 end: 3 lava-test-retry (duration 00:00:11) [common]
11452 13:44:23.074602 start: 4 finalize (timeout 00:07:53) [common]
11453 13:44:23.075316 start: 4.1 power-off (timeout 00:00:30) [common]
11454 13:44:23.076495 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11455 13:44:23.326240 >> Command sent successfully.
11456 13:44:23.337166 Returned 0 in 0 seconds
11457 13:44:23.438053 end: 4.1 power-off (duration 00:00:00) [common]
11459 13:44:23.438468 start: 4.2 read-feedback (timeout 00:07:53) [common]
11460 13:44:23.438748 Listened to connection for namespace 'common' for up to 1s
11461 13:44:24.439451 Finalising connection for namespace 'common'
11462 13:44:24.439662 Disconnecting from shell: Finalise
11463 13:44:24.439774 / #
11464 13:44:24.540126 end: 4.2 read-feedback (duration 00:00:01) [common]
11465 13:44:24.540297 end: 4 finalize (duration 00:00:01) [common]
11466 13:44:24.540409 Cleaning after the job
11467 13:44:24.540506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/ramdisk
11468 13:44:24.542734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/kernel
11469 13:44:24.553557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/dtb
11470 13:44:24.553797 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/nfsrootfs
11471 13:44:24.617202 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063105/tftp-deploy-o8z8wbql/modules
11472 13:44:24.623087 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063105
11473 13:44:25.155487 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063105
11474 13:44:25.155671 Job finished correctly