Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 13:39:45.103010 lava-dispatcher, installed at version: 2024.03
2 13:39:45.103220 start: 0 validate
3 13:39:45.103359 Start time: 2024-05-28 13:39:45.103351+00:00 (UTC)
4 13:39:45.103492 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:39:45.103625 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:39:45.372422 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:39:45.372593 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 13:39:45.629673 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:39:45.629851 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 13:39:45.878734 Using caching service: 'http://localhost/cache/?uri=%s'
11 13:39:45.878951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.91-cip21%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 13:39:46.140263 validate duration: 1.04
14 13:39:46.140646 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:39:46.140812 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:39:46.140953 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:39:46.141139 Not decompressing ramdisk as can be used compressed.
18 13:39:46.141263 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 13:39:46.141336 saving as /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/ramdisk/rootfs.cpio.gz
20 13:39:46.141402 total size: 28105535 (26 MB)
21 13:39:46.142662 progress 0 % (0 MB)
22 13:39:46.150624 progress 5 % (1 MB)
23 13:39:46.158531 progress 10 % (2 MB)
24 13:39:46.166452 progress 15 % (4 MB)
25 13:39:46.174336 progress 20 % (5 MB)
26 13:39:46.181769 progress 25 % (6 MB)
27 13:39:46.189567 progress 30 % (8 MB)
28 13:39:46.197517 progress 35 % (9 MB)
29 13:39:46.205500 progress 40 % (10 MB)
30 13:39:46.213231 progress 45 % (12 MB)
31 13:39:46.221162 progress 50 % (13 MB)
32 13:39:46.228799 progress 55 % (14 MB)
33 13:39:46.236104 progress 60 % (16 MB)
34 13:39:46.243467 progress 65 % (17 MB)
35 13:39:46.250772 progress 70 % (18 MB)
36 13:39:46.258092 progress 75 % (20 MB)
37 13:39:46.265577 progress 80 % (21 MB)
38 13:39:46.272922 progress 85 % (22 MB)
39 13:39:46.279974 progress 90 % (24 MB)
40 13:39:46.287447 progress 95 % (25 MB)
41 13:39:46.295226 progress 100 % (26 MB)
42 13:39:46.295497 26 MB downloaded in 0.15 s (173.94 MB/s)
43 13:39:46.295715 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:39:46.296121 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:39:46.296221 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:39:46.296327 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:39:46.296468 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 13:39:46.296557 saving as /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/kernel/Image
50 13:39:46.296624 total size: 54682112 (52 MB)
51 13:39:46.296686 No compression specified
52 13:39:46.297864 progress 0 % (0 MB)
53 13:39:46.313086 progress 5 % (2 MB)
54 13:39:46.328289 progress 10 % (5 MB)
55 13:39:46.343558 progress 15 % (7 MB)
56 13:39:46.359168 progress 20 % (10 MB)
57 13:39:46.374341 progress 25 % (13 MB)
58 13:39:46.388273 progress 30 % (15 MB)
59 13:39:46.402432 progress 35 % (18 MB)
60 13:39:46.416491 progress 40 % (20 MB)
61 13:39:46.430545 progress 45 % (23 MB)
62 13:39:46.444748 progress 50 % (26 MB)
63 13:39:46.458748 progress 55 % (28 MB)
64 13:39:46.473420 progress 60 % (31 MB)
65 13:39:46.487462 progress 65 % (33 MB)
66 13:39:46.501621 progress 70 % (36 MB)
67 13:39:46.515646 progress 75 % (39 MB)
68 13:39:46.529905 progress 80 % (41 MB)
69 13:39:46.543890 progress 85 % (44 MB)
70 13:39:46.557934 progress 90 % (46 MB)
71 13:39:46.572043 progress 95 % (49 MB)
72 13:39:46.585925 progress 100 % (52 MB)
73 13:39:46.586188 52 MB downloaded in 0.29 s (180.10 MB/s)
74 13:39:46.586346 end: 1.2.1 http-download (duration 00:00:00) [common]
76 13:39:46.586584 end: 1.2 download-retry (duration 00:00:00) [common]
77 13:39:46.586673 start: 1.3 download-retry (timeout 00:10:00) [common]
78 13:39:46.586772 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 13:39:46.586916 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 13:39:46.586987 saving as /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/dtb/mt8192-asurada-spherion-r0.dtb
81 13:39:46.587049 total size: 47258 (0 MB)
82 13:39:46.587112 No compression specified
83 13:39:46.588217 progress 69 % (0 MB)
84 13:39:46.588498 progress 100 % (0 MB)
85 13:39:46.588657 0 MB downloaded in 0.00 s (28.08 MB/s)
86 13:39:46.588783 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:39:46.589016 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:39:46.589105 start: 1.4 download-retry (timeout 00:10:00) [common]
90 13:39:46.589190 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 13:39:46.589304 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.91-cip21/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 13:39:46.589373 saving as /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/modules/modules.tar
93 13:39:46.589435 total size: 8607916 (8 MB)
94 13:39:46.589497 Using unxz to decompress xz
95 13:39:46.593562 progress 0 % (0 MB)
96 13:39:46.613765 progress 5 % (0 MB)
97 13:39:46.639007 progress 10 % (0 MB)
98 13:39:46.665802 progress 15 % (1 MB)
99 13:39:46.691296 progress 20 % (1 MB)
100 13:39:46.717322 progress 25 % (2 MB)
101 13:39:46.743089 progress 30 % (2 MB)
102 13:39:46.766972 progress 35 % (2 MB)
103 13:39:46.794759 progress 40 % (3 MB)
104 13:39:46.819986 progress 45 % (3 MB)
105 13:39:46.845121 progress 50 % (4 MB)
106 13:39:46.870507 progress 55 % (4 MB)
107 13:39:46.895365 progress 60 % (4 MB)
108 13:39:46.919589 progress 65 % (5 MB)
109 13:39:46.946211 progress 70 % (5 MB)
110 13:39:46.973745 progress 75 % (6 MB)
111 13:39:46.997690 progress 80 % (6 MB)
112 13:39:47.021811 progress 85 % (7 MB)
113 13:39:47.046202 progress 90 % (7 MB)
114 13:39:47.076227 progress 95 % (7 MB)
115 13:39:47.104907 progress 100 % (8 MB)
116 13:39:47.110722 8 MB downloaded in 0.52 s (15.75 MB/s)
117 13:39:47.110985 end: 1.4.1 http-download (duration 00:00:01) [common]
119 13:39:47.111260 end: 1.4 download-retry (duration 00:00:01) [common]
120 13:39:47.111411 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 13:39:47.111545 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 13:39:47.111678 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:39:47.111817 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 13:39:47.112105 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1
125 13:39:47.112280 makedir: /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin
126 13:39:47.112425 makedir: /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/tests
127 13:39:47.112567 makedir: /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/results
128 13:39:47.112718 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-add-keys
129 13:39:47.112904 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-add-sources
130 13:39:47.113082 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-background-process-start
131 13:39:47.113254 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-background-process-stop
132 13:39:47.113420 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-common-functions
133 13:39:47.113581 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-echo-ipv4
134 13:39:47.113741 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-install-packages
135 13:39:47.113902 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-installed-packages
136 13:39:47.114061 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-os-build
137 13:39:47.114222 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-probe-channel
138 13:39:47.114410 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-probe-ip
139 13:39:47.114541 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-target-ip
140 13:39:47.114670 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-target-mac
141 13:39:47.114794 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-target-storage
142 13:39:47.114928 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-case
143 13:39:47.115054 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-event
144 13:39:47.115194 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-feedback
145 13:39:47.115358 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-raise
146 13:39:47.115507 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-reference
147 13:39:47.115635 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-runner
148 13:39:47.115759 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-set
149 13:39:47.115888 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-test-shell
150 13:39:47.116016 Updating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-install-packages (oe)
151 13:39:47.116184 Updating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/bin/lava-installed-packages (oe)
152 13:39:47.116335 Creating /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/environment
153 13:39:47.116441 LAVA metadata
154 13:39:47.116514 - LAVA_JOB_ID=14063090
155 13:39:47.116587 - LAVA_DISPATCHER_IP=192.168.201.1
156 13:39:47.116696 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 13:39:47.116766 skipped lava-vland-overlay
158 13:39:47.116862 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 13:39:47.116985 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 13:39:47.117067 skipped lava-multinode-overlay
161 13:39:47.117143 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 13:39:47.117235 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 13:39:47.117349 Loading test definitions
164 13:39:47.117458 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 13:39:47.117537 Using /lava-14063090 at stage 0
166 13:39:47.117850 uuid=14063090_1.5.2.3.1 testdef=None
167 13:39:47.117943 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 13:39:47.118032 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 13:39:47.118559 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 13:39:47.118822 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 13:39:47.119449 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 13:39:47.119689 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 13:39:47.120288 runner path: /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/0/tests/0_v4l2-compliance-uvc test_uuid 14063090_1.5.2.3.1
176 13:39:47.120482 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 13:39:47.120710 Creating lava-test-runner.conf files
179 13:39:47.120774 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14063090/lava-overlay-38jdc3_1/lava-14063090/0 for stage 0
180 13:39:47.120893 - 0_v4l2-compliance-uvc
181 13:39:47.121044 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 13:39:47.121136 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 13:39:47.130061 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 13:39:47.130233 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 13:39:47.130363 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 13:39:47.130483 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 13:39:47.130601 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 13:39:48.048368 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 13:39:48.048774 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 13:39:48.048925 extracting modules file /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14063090/extract-overlay-ramdisk-om_aqg73/ramdisk
191 13:39:48.317628 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 13:39:48.317870 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 13:39:48.317998 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063090/compress-overlay-n98iilic/overlay-1.5.2.4.tar.gz to ramdisk
194 13:39:48.318081 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14063090/compress-overlay-n98iilic/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14063090/extract-overlay-ramdisk-om_aqg73/ramdisk
195 13:39:48.325367 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 13:39:48.325502 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 13:39:48.325597 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 13:39:48.325694 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 13:39:48.325777 Building ramdisk /var/lib/lava/dispatcher/tmp/14063090/extract-overlay-ramdisk-om_aqg73/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14063090/extract-overlay-ramdisk-om_aqg73/ramdisk
200 13:39:49.086583 >> 275882 blocks
201 13:39:53.422738 rename /var/lib/lava/dispatcher/tmp/14063090/extract-overlay-ramdisk-om_aqg73/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/ramdisk/ramdisk.cpio.gz
202 13:39:53.423195 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 13:39:53.423332 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 13:39:53.423434 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 13:39:53.423558 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/kernel/Image']
206 13:40:07.403014 Returned 0 in 13 seconds
207 13:40:07.503757 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/kernel/image.itb
208 13:40:08.150207 output: FIT description: Kernel Image image with one or more FDT blobs
209 13:40:08.150573 output: Created: Tue May 28 14:40:08 2024
210 13:40:08.150648 output: Image 0 (kernel-1)
211 13:40:08.150712 output: Description:
212 13:40:08.150772 output: Created: Tue May 28 14:40:08 2024
213 13:40:08.150831 output: Type: Kernel Image
214 13:40:08.150891 output: Compression: lzma compressed
215 13:40:08.150953 output: Data Size: 13061303 Bytes = 12755.18 KiB = 12.46 MiB
216 13:40:08.151021 output: Architecture: AArch64
217 13:40:08.151080 output: OS: Linux
218 13:40:08.151140 output: Load Address: 0x00000000
219 13:40:08.151196 output: Entry Point: 0x00000000
220 13:40:08.151254 output: Hash algo: crc32
221 13:40:08.151309 output: Hash value: 0578ee26
222 13:40:08.151362 output: Image 1 (fdt-1)
223 13:40:08.151420 output: Description: mt8192-asurada-spherion-r0
224 13:40:08.151475 output: Created: Tue May 28 14:40:08 2024
225 13:40:08.151528 output: Type: Flat Device Tree
226 13:40:08.151580 output: Compression: uncompressed
227 13:40:08.151632 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 13:40:08.151684 output: Architecture: AArch64
229 13:40:08.151736 output: Hash algo: crc32
230 13:40:08.151788 output: Hash value: 0f8e4d2e
231 13:40:08.151871 output: Image 2 (ramdisk-1)
232 13:40:08.151950 output: Description: unavailable
233 13:40:08.152025 output: Created: Tue May 28 14:40:08 2024
234 13:40:08.152086 output: Type: RAMDisk Image
235 13:40:08.152139 output: Compression: Unknown Compression
236 13:40:08.152191 output: Data Size: 41211104 Bytes = 40245.22 KiB = 39.30 MiB
237 13:40:08.152250 output: Architecture: AArch64
238 13:40:08.152303 output: OS: Linux
239 13:40:08.152355 output: Load Address: unavailable
240 13:40:08.152436 output: Entry Point: unavailable
241 13:40:08.152519 output: Hash algo: crc32
242 13:40:08.152570 output: Hash value: 3e5ef2de
243 13:40:08.152621 output: Default Configuration: 'conf-1'
244 13:40:08.152689 output: Configuration 0 (conf-1)
245 13:40:08.152764 output: Description: mt8192-asurada-spherion-r0
246 13:40:08.152816 output: Kernel: kernel-1
247 13:40:08.152885 output: Init Ramdisk: ramdisk-1
248 13:40:08.152938 output: FDT: fdt-1
249 13:40:08.153014 output: Loadables: kernel-1
250 13:40:08.153067 output:
251 13:40:08.153303 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 13:40:08.153403 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 13:40:08.153507 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 13:40:08.153604 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 13:40:08.153707 No LXC device requested
256 13:40:08.153819 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 13:40:08.153930 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 13:40:08.154007 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 13:40:08.154082 Checking files for TFTP limit of 4294967296 bytes.
260 13:40:08.154580 end: 1 tftp-deploy (duration 00:00:22) [common]
261 13:40:08.154683 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 13:40:08.154780 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 13:40:08.154906 substitutions:
264 13:40:08.154979 - {DTB}: 14063090/tftp-deploy-u_fffaoi/dtb/mt8192-asurada-spherion-r0.dtb
265 13:40:08.155043 - {INITRD}: 14063090/tftp-deploy-u_fffaoi/ramdisk/ramdisk.cpio.gz
266 13:40:08.155102 - {KERNEL}: 14063090/tftp-deploy-u_fffaoi/kernel/Image
267 13:40:08.155161 - {LAVA_MAC}: None
268 13:40:08.155218 - {PRESEED_CONFIG}: None
269 13:40:08.155273 - {PRESEED_LOCAL}: None
270 13:40:08.155328 - {RAMDISK}: 14063090/tftp-deploy-u_fffaoi/ramdisk/ramdisk.cpio.gz
271 13:40:08.155382 - {ROOT_PART}: None
272 13:40:08.155469 - {ROOT}: None
273 13:40:08.155551 - {SERVER_IP}: 192.168.201.1
274 13:40:08.155629 - {TEE}: None
275 13:40:08.155690 Parsed boot commands:
276 13:40:08.155744 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 13:40:08.155930 Parsed boot commands: tftpboot 192.168.201.1 14063090/tftp-deploy-u_fffaoi/kernel/image.itb 14063090/tftp-deploy-u_fffaoi/kernel/cmdline
278 13:40:08.156039 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 13:40:08.156146 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 13:40:08.156242 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 13:40:08.156335 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 13:40:08.156409 Not connected, no need to disconnect.
283 13:40:08.156482 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 13:40:08.156559 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 13:40:08.156626 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 13:40:08.160699 Setting prompt string to ['lava-test: # ']
287 13:40:08.161192 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 13:40:08.161325 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 13:40:08.161475 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 13:40:08.161605 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 13:40:08.161961 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 13:40:13.298350 >> Command sent successfully.
293 13:40:13.300796 Returned 0 in 5 seconds
294 13:40:13.401151 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 13:40:13.401537 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 13:40:13.401635 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 13:40:13.401722 Setting prompt string to 'Starting depthcharge on Spherion...'
299 13:40:13.401789 Changing prompt to 'Starting depthcharge on Spherion...'
300 13:40:13.401917 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 13:40:13.402310 [Enter `^Ec?' for help]
302 13:40:13.577601
303 13:40:13.577762
304 13:40:13.577833 F0: 102B 0000
305 13:40:13.577894
306 13:40:13.577956 F3: 1001 0000 [0200]
307 13:40:13.580879
308 13:40:13.580967 F3: 1001 0000
309 13:40:13.581049
310 13:40:13.581111 F7: 102D 0000
311 13:40:13.581169
312 13:40:13.584605 F1: 0000 0000
313 13:40:13.584687
314 13:40:13.584751 V0: 0000 0000 [0001]
315 13:40:13.584812
316 13:40:13.587645 00: 0007 8000
317 13:40:13.587730
318 13:40:13.587794 01: 0000 0000
319 13:40:13.587856
320 13:40:13.591480 BP: 0C00 0209 [0000]
321 13:40:13.591587
322 13:40:13.591659 G0: 1182 0000
323 13:40:13.591720
324 13:40:13.594996 EC: 0000 0021 [4000]
325 13:40:13.595084
326 13:40:13.595150 S7: 0000 0000 [0000]
327 13:40:13.595211
328 13:40:13.598239 CC: 0000 0000 [0001]
329 13:40:13.598320
330 13:40:13.598393 T0: 0000 0040 [010F]
331 13:40:13.598484
332 13:40:13.598540 Jump to BL
333 13:40:13.598628
334 13:40:13.625257
335 13:40:13.625400
336 13:40:13.632561 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 13:40:13.635708 ARM64: Exception handlers installed.
338 13:40:13.639384 ARM64: Testing exception
339 13:40:13.642974 ARM64: Done test exception
340 13:40:13.649514 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 13:40:13.659781 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 13:40:13.666213 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 13:40:13.676509 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 13:40:13.683160 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 13:40:13.689828 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 13:40:13.701531 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 13:40:13.708190 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 13:40:13.727953 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 13:40:13.730902 WDT: Last reset was cold boot
350 13:40:13.734037 SPI1(PAD0) initialized at 2873684 Hz
351 13:40:13.737624 SPI5(PAD0) initialized at 992727 Hz
352 13:40:13.740877 VBOOT: Loading verstage.
353 13:40:13.747435 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 13:40:13.751092 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 13:40:13.754089 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 13:40:13.757759 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 13:40:13.765141 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 13:40:13.771354 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 13:40:13.782611 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 13:40:13.782702
361 13:40:13.782790
362 13:40:13.792910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 13:40:13.795791 ARM64: Exception handlers installed.
364 13:40:13.799303 ARM64: Testing exception
365 13:40:13.799389 ARM64: Done test exception
366 13:40:13.805976 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 13:40:13.809770 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 13:40:13.824850 Probing TPM: . done!
369 13:40:13.824943 TPM ready after 0 ms
370 13:40:13.831517 Connected to device vid:did:rid of 1ae0:0028:00
371 13:40:13.838546 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 13:40:13.895850 Initialized TPM device CR50 revision 0
373 13:40:13.907770 tlcl_send_startup: Startup return code is 0
374 13:40:13.907872 TPM: setup succeeded
375 13:40:13.919205 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 13:40:13.927879 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 13:40:13.939988 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 13:40:13.949523 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 13:40:13.953284 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 13:40:13.959324 in-header: 03 07 00 00 08 00 00 00
381 13:40:13.963048 in-data: aa e4 47 04 13 02 00 00
382 13:40:13.966733 Chrome EC: UHEPI supported
383 13:40:13.974045 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 13:40:13.977769 in-header: 03 ad 00 00 08 00 00 00
385 13:40:13.977853 in-data: 00 20 20 08 00 00 00 00
386 13:40:13.981320 Phase 1
387 13:40:13.985276 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 13:40:13.989278 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 13:40:13.996266 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 13:40:14.000119 Recovery requested (1009000e)
391 13:40:14.008154 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 13:40:14.012873 tlcl_extend: response is 0
393 13:40:14.022694 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 13:40:14.028816 tlcl_extend: response is 0
395 13:40:14.035642 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 13:40:14.054739 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 13:40:14.061419 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 13:40:14.061511
399 13:40:14.061578
400 13:40:14.072426 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 13:40:14.076018 ARM64: Exception handlers installed.
402 13:40:14.076145 ARM64: Testing exception
403 13:40:14.079185 ARM64: Done test exception
404 13:40:14.100101 pmic_efuse_setting: Set efuses in 11 msecs
405 13:40:14.104156 pmwrap_interface_init: Select PMIF_VLD_RDY
406 13:40:14.110835 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 13:40:14.113912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 13:40:14.121041 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 13:40:14.124543 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 13:40:14.127992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 13:40:14.131778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 13:40:14.139722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 13:40:14.143340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 13:40:14.147014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 13:40:14.154508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 13:40:14.158547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 13:40:14.162774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 13:40:14.165812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 13:40:14.173176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 13:40:14.177313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 13:40:14.184136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 13:40:14.191587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 13:40:14.195299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 13:40:14.199534 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 13:40:14.206774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 13:40:14.210466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 13:40:14.217882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 13:40:14.224964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 13:40:14.229290 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 13:40:14.232619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 13:40:14.240106 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 13:40:14.243780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 13:40:14.251175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 13:40:14.255016 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 13:40:14.258717 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 13:40:14.265484 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 13:40:14.269664 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 13:40:14.272555 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 13:40:14.280670 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 13:40:14.284253 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 13:40:14.287986 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 13:40:14.295438 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 13:40:14.299234 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 13:40:14.302821 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 13:40:14.306448 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 13:40:14.313819 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 13:40:14.317263 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 13:40:14.320640 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 13:40:14.324431 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 13:40:14.328427 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 13:40:14.336357 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 13:40:14.339863 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 13:40:14.343625 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 13:40:14.347463 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 13:40:14.351079 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 13:40:14.354761 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 13:40:14.362464 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 13:40:14.373443 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 13:40:14.377299 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 13:40:14.384139 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 13:40:14.391948 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 13:40:14.398688 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 13:40:14.402494 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 13:40:14.406211 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 13:40:14.413466 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
466 13:40:14.417331 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 13:40:14.424954 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 13:40:14.428023 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 13:40:14.437629 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 13:40:14.447373 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 13:40:14.456705 [RTC]rtc_get_frequency_meter,154: input=19, output=885
472 13:40:14.466507 [RTC]rtc_get_frequency_meter,154: input=17, output=836
473 13:40:14.475820 [RTC]rtc_get_frequency_meter,154: input=16, output=812
474 13:40:14.485776 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 13:40:14.494922 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 13:40:14.498233 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 13:40:14.505833 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 13:40:14.509417 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 13:40:14.513170 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 13:40:14.517504 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 13:40:14.521075 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 13:40:14.524870 ADC[4]: Raw value=901328 ID=7
483 13:40:14.524997 ADC[3]: Raw value=213336 ID=1
484 13:40:14.528574 RAM Code: 0x71
485 13:40:14.531927 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 13:40:14.535654 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 13:40:14.547149 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 13:40:14.550448 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 13:40:14.554073 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 13:40:14.559587 in-header: 03 07 00 00 08 00 00 00
491 13:40:14.562950 in-data: aa e4 47 04 13 02 00 00
492 13:40:14.566412 Chrome EC: UHEPI supported
493 13:40:14.573726 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 13:40:14.577430 in-header: 03 ed 00 00 08 00 00 00
495 13:40:14.577574 in-data: 80 20 60 08 00 00 00 00
496 13:40:14.581793 MRC: failed to locate region type 0.
497 13:40:14.589249 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 13:40:14.592937 DRAM-K: Running full calibration
499 13:40:14.599661 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 13:40:14.599787 header.status = 0x0
501 13:40:14.603783 header.version = 0x6 (expected: 0x6)
502 13:40:14.607802 header.size = 0xd00 (expected: 0xd00)
503 13:40:14.607919 header.flags = 0x0
504 13:40:14.615244 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 13:40:14.632906 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 13:40:14.640289 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 13:40:14.643879 dram_init: ddr_geometry: 2
508 13:40:14.643967 [EMI] MDL number = 2
509 13:40:14.647690 [EMI] Get MDL freq = 0
510 13:40:14.647800 dram_init: ddr_type: 0
511 13:40:14.651188 is_discrete_lpddr4: 1
512 13:40:14.654827 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 13:40:14.654915
514 13:40:14.654981
515 13:40:14.655041 [Bian_co] ETT version 0.0.0.1
516 13:40:14.662330 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 13:40:14.662421
518 13:40:14.665950 dramc_set_vcore_voltage set vcore to 650000
519 13:40:14.666026 Read voltage for 800, 4
520 13:40:14.670246 Vio18 = 0
521 13:40:14.670321 Vcore = 650000
522 13:40:14.670384 Vdram = 0
523 13:40:14.670447 Vddq = 0
524 13:40:14.673538 Vmddr = 0
525 13:40:14.673623 dram_init: config_dvfs: 1
526 13:40:14.680841 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 13:40:14.684616 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 13:40:14.688342 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 13:40:14.691420 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 13:40:14.694664 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 13:40:14.701495 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 13:40:14.701614 MEM_TYPE=3, freq_sel=18
533 13:40:14.705145 sv_algorithm_assistance_LP4_1600
534 13:40:14.708243 ============ PULL DRAM RESETB DOWN ============
535 13:40:14.714789 ========== PULL DRAM RESETB DOWN end =========
536 13:40:14.718338 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 13:40:14.721671 ===================================
538 13:40:14.725404 LPDDR4 DRAM CONFIGURATION
539 13:40:14.728699 ===================================
540 13:40:14.728812 EX_ROW_EN[0] = 0x0
541 13:40:14.731805 EX_ROW_EN[1] = 0x0
542 13:40:14.731906 LP4Y_EN = 0x0
543 13:40:14.735490 WORK_FSP = 0x0
544 13:40:14.735579 WL = 0x2
545 13:40:14.738535 RL = 0x2
546 13:40:14.738619 BL = 0x2
547 13:40:14.742018 RPST = 0x0
548 13:40:14.742093 RD_PRE = 0x0
549 13:40:14.745402 WR_PRE = 0x1
550 13:40:14.745514 WR_PST = 0x0
551 13:40:14.748971 DBI_WR = 0x0
552 13:40:14.749053 DBI_RD = 0x0
553 13:40:14.751934 OTF = 0x1
554 13:40:14.755468 ===================================
555 13:40:14.759120 ===================================
556 13:40:14.759201 ANA top config
557 13:40:14.762151 ===================================
558 13:40:14.765663 DLL_ASYNC_EN = 0
559 13:40:14.768815 ALL_SLAVE_EN = 1
560 13:40:14.772555 NEW_RANK_MODE = 1
561 13:40:14.772637 DLL_IDLE_MODE = 1
562 13:40:14.775505 LP45_APHY_COMB_EN = 1
563 13:40:14.779191 TX_ODT_DIS = 1
564 13:40:14.782620 NEW_8X_MODE = 1
565 13:40:14.785633 ===================================
566 13:40:14.788641 ===================================
567 13:40:14.792388 data_rate = 1600
568 13:40:14.792464 CKR = 1
569 13:40:14.795460 DQ_P2S_RATIO = 8
570 13:40:14.799087 ===================================
571 13:40:14.802263 CA_P2S_RATIO = 8
572 13:40:14.805890 DQ_CA_OPEN = 0
573 13:40:14.809112 DQ_SEMI_OPEN = 0
574 13:40:14.809221 CA_SEMI_OPEN = 0
575 13:40:14.812103 CA_FULL_RATE = 0
576 13:40:14.815954 DQ_CKDIV4_EN = 1
577 13:40:14.818860 CA_CKDIV4_EN = 1
578 13:40:14.822459 CA_PREDIV_EN = 0
579 13:40:14.825605 PH8_DLY = 0
580 13:40:14.825683 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 13:40:14.829174 DQ_AAMCK_DIV = 4
582 13:40:14.832587 CA_AAMCK_DIV = 4
583 13:40:14.835909 CA_ADMCK_DIV = 4
584 13:40:14.839551 DQ_TRACK_CA_EN = 0
585 13:40:14.842678 CA_PICK = 800
586 13:40:14.842768 CA_MCKIO = 800
587 13:40:14.846475 MCKIO_SEMI = 0
588 13:40:14.849856 PLL_FREQ = 3068
589 13:40:14.852846 DQ_UI_PI_RATIO = 32
590 13:40:14.860986 CA_UI_PI_RATIO = 0
591 13:40:14.861313 ===================================
592 13:40:14.861390 ===================================
593 13:40:14.864327 memory_type:LPDDR4
594 13:40:14.867957 GP_NUM : 10
595 13:40:14.868094 SRAM_EN : 1
596 13:40:14.871650 MD32_EN : 0
597 13:40:14.875341 ===================================
598 13:40:14.875459 [ANA_INIT] >>>>>>>>>>>>>>
599 13:40:14.878978 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 13:40:14.882711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 13:40:14.886321 ===================================
602 13:40:14.889703 data_rate = 1600,PCW = 0X7600
603 13:40:14.893372 ===================================
604 13:40:14.896440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 13:40:14.899545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 13:40:14.906226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 13:40:14.910029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 13:40:14.913253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 13:40:14.916321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 13:40:14.920151 [ANA_INIT] flow start
611 13:40:14.923093 [ANA_INIT] PLL >>>>>>>>
612 13:40:14.923186 [ANA_INIT] PLL <<<<<<<<
613 13:40:14.926857 [ANA_INIT] MIDPI >>>>>>>>
614 13:40:14.929831 [ANA_INIT] MIDPI <<<<<<<<
615 13:40:14.929914 [ANA_INIT] DLL >>>>>>>>
616 13:40:14.933180 [ANA_INIT] flow end
617 13:40:14.936798 ============ LP4 DIFF to SE enter ============
618 13:40:14.940093 ============ LP4 DIFF to SE exit ============
619 13:40:14.943342 [ANA_INIT] <<<<<<<<<<<<<
620 13:40:14.946860 [Flow] Enable top DCM control >>>>>
621 13:40:14.950419 [Flow] Enable top DCM control <<<<<
622 13:40:14.953431 Enable DLL master slave shuffle
623 13:40:14.960345 ==============================================================
624 13:40:14.960520 Gating Mode config
625 13:40:14.966763 ==============================================================
626 13:40:14.966909 Config description:
627 13:40:14.977423 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 13:40:14.983549 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 13:40:14.990301 SELPH_MODE 0: By rank 1: By Phase
630 13:40:14.993935 ==============================================================
631 13:40:14.997551 GAT_TRACK_EN = 1
632 13:40:15.000557 RX_GATING_MODE = 2
633 13:40:15.003956 RX_GATING_TRACK_MODE = 2
634 13:40:15.007076 SELPH_MODE = 1
635 13:40:15.010726 PICG_EARLY_EN = 1
636 13:40:15.013860 VALID_LAT_VALUE = 1
637 13:40:15.017530 ==============================================================
638 13:40:15.020465 Enter into Gating configuration >>>>
639 13:40:15.024248 Exit from Gating configuration <<<<
640 13:40:15.027207 Enter into DVFS_PRE_config >>>>>
641 13:40:15.040712 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 13:40:15.040808 Exit from DVFS_PRE_config <<<<<
643 13:40:15.044337 Enter into PICG configuration >>>>
644 13:40:15.047522 Exit from PICG configuration <<<<
645 13:40:15.051013 [RX_INPUT] configuration >>>>>
646 13:40:15.054394 [RX_INPUT] configuration <<<<<
647 13:40:15.060874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 13:40:15.064211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 13:40:15.071275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 13:40:15.078453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 13:40:15.084798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 13:40:15.088015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 13:40:15.095019 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 13:40:15.098077 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 13:40:15.101619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 13:40:15.105136 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 13:40:15.108803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 13:40:15.115228 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 13:40:15.118780 ===================================
660 13:40:15.118873 LPDDR4 DRAM CONFIGURATION
661 13:40:15.121805 ===================================
662 13:40:15.125570 EX_ROW_EN[0] = 0x0
663 13:40:15.128513 EX_ROW_EN[1] = 0x0
664 13:40:15.128598 LP4Y_EN = 0x0
665 13:40:15.131966 WORK_FSP = 0x0
666 13:40:15.132053 WL = 0x2
667 13:40:15.135364 RL = 0x2
668 13:40:15.135449 BL = 0x2
669 13:40:15.138952 RPST = 0x0
670 13:40:15.139036 RD_PRE = 0x0
671 13:40:15.142068 WR_PRE = 0x1
672 13:40:15.142153 WR_PST = 0x0
673 13:40:15.145092 DBI_WR = 0x0
674 13:40:15.145177 DBI_RD = 0x0
675 13:40:15.148760 OTF = 0x1
676 13:40:15.152512 ===================================
677 13:40:15.155642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 13:40:15.159060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 13:40:15.165532 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 13:40:15.165630 ===================================
681 13:40:15.169009 LPDDR4 DRAM CONFIGURATION
682 13:40:15.172146 ===================================
683 13:40:15.175861 EX_ROW_EN[0] = 0x10
684 13:40:15.176001 EX_ROW_EN[1] = 0x0
685 13:40:15.178737 LP4Y_EN = 0x0
686 13:40:15.178843 WORK_FSP = 0x0
687 13:40:15.182010 WL = 0x2
688 13:40:15.182126 RL = 0x2
689 13:40:15.185680 BL = 0x2
690 13:40:15.185792 RPST = 0x0
691 13:40:15.188617 RD_PRE = 0x0
692 13:40:15.188736 WR_PRE = 0x1
693 13:40:15.192716 WR_PST = 0x0
694 13:40:15.192828 DBI_WR = 0x0
695 13:40:15.196002 DBI_RD = 0x0
696 13:40:15.199162 OTF = 0x1
697 13:40:15.199273 ===================================
698 13:40:15.205949 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 13:40:15.211012 nWR fixed to 40
700 13:40:15.214146 [ModeRegInit_LP4] CH0 RK0
701 13:40:15.214231 [ModeRegInit_LP4] CH0 RK1
702 13:40:15.217479 [ModeRegInit_LP4] CH1 RK0
703 13:40:15.220924 [ModeRegInit_LP4] CH1 RK1
704 13:40:15.221017 match AC timing 13
705 13:40:15.227755 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 13:40:15.230815 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 13:40:15.234318 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 13:40:15.240894 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 13:40:15.244214 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 13:40:15.244300 [EMI DOE] emi_dcm 0
711 13:40:15.250866 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 13:40:15.250950 ==
713 13:40:15.254603 Dram Type= 6, Freq= 0, CH_0, rank 0
714 13:40:15.257558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 13:40:15.257638 ==
716 13:40:15.264717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 13:40:15.268115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 13:40:15.278105 [CA 0] Center 37 (7~68) winsize 62
719 13:40:15.281639 [CA 1] Center 37 (6~68) winsize 63
720 13:40:15.285204 [CA 2] Center 35 (4~66) winsize 63
721 13:40:15.288207 [CA 3] Center 34 (4~65) winsize 62
722 13:40:15.291950 [CA 4] Center 34 (4~64) winsize 61
723 13:40:15.295253 [CA 5] Center 33 (3~64) winsize 62
724 13:40:15.295331
725 13:40:15.298250 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 13:40:15.298327
727 13:40:15.301788 [CATrainingPosCal] consider 1 rank data
728 13:40:15.304865 u2DelayCellTimex100 = 270/100 ps
729 13:40:15.308420 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 13:40:15.311791 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 13:40:15.315130 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
732 13:40:15.321910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 13:40:15.325374 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
734 13:40:15.328814 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 13:40:15.328901
736 13:40:15.331901 CA PerBit enable=1, Macro0, CA PI delay=33
737 13:40:15.331986
738 13:40:15.335702 [CBTSetCACLKResult] CA Dly = 33
739 13:40:15.335804 CS Dly: 5 (0~36)
740 13:40:15.335886 ==
741 13:40:15.338774 Dram Type= 6, Freq= 0, CH_0, rank 1
742 13:40:15.345509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 13:40:15.345595 ==
744 13:40:15.348550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 13:40:15.355412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 13:40:15.364572 [CA 0] Center 37 (6~68) winsize 63
747 13:40:15.367547 [CA 1] Center 37 (7~68) winsize 62
748 13:40:15.371407 [CA 2] Center 35 (5~66) winsize 62
749 13:40:15.374420 [CA 3] Center 34 (4~65) winsize 62
750 13:40:15.378145 [CA 4] Center 34 (3~65) winsize 63
751 13:40:15.381088 [CA 5] Center 33 (3~64) winsize 62
752 13:40:15.381172
753 13:40:15.384491 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 13:40:15.384575
755 13:40:15.387981 [CATrainingPosCal] consider 2 rank data
756 13:40:15.391008 u2DelayCellTimex100 = 270/100 ps
757 13:40:15.394683 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 13:40:15.397781 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 13:40:15.404549 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 13:40:15.408276 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 13:40:15.411243 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
762 13:40:15.414917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 13:40:15.415002
764 13:40:15.417997 CA PerBit enable=1, Macro0, CA PI delay=33
765 13:40:15.418087
766 13:40:15.421612 [CBTSetCACLKResult] CA Dly = 33
767 13:40:15.421696 CS Dly: 5 (0~37)
768 13:40:15.421762
769 13:40:15.424516 ----->DramcWriteLeveling(PI) begin...
770 13:40:15.424600 ==
771 13:40:15.428130 Dram Type= 6, Freq= 0, CH_0, rank 0
772 13:40:15.435763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 13:40:15.435849 ==
774 13:40:15.435917 Write leveling (Byte 0): 29 => 29
775 13:40:15.439305 Write leveling (Byte 1): 29 => 29
776 13:40:15.442633 DramcWriteLeveling(PI) end<-----
777 13:40:15.442741
778 13:40:15.442835 ==
779 13:40:15.446507 Dram Type= 6, Freq= 0, CH_0, rank 0
780 13:40:15.449395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 13:40:15.449481 ==
782 13:40:15.452800 [Gating] SW mode calibration
783 13:40:15.460352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 13:40:15.466944 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 13:40:15.470467 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 13:40:15.473619 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 13:40:15.480414 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 13:40:15.483969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 13:40:15.487019 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 13:40:15.494107 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 13:40:15.496924 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 13:40:15.500615 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 13:40:15.503814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 13:40:15.510564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 13:40:15.514343 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 13:40:15.517252 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 13:40:15.524092 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 13:40:15.527635 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 13:40:15.530542 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 13:40:15.537706 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 13:40:15.540577 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 13:40:15.544517 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 13:40:15.550733 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 13:40:15.554621 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 13:40:15.557464 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 13:40:15.564167 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 13:40:15.567331 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 13:40:15.570815 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 13:40:15.574272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 13:40:15.580842 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 13:40:15.584177 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
812 13:40:15.587972 0 9 12 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
813 13:40:15.594629 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 13:40:15.598160 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 13:40:15.600961 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 13:40:15.607876 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 13:40:15.611431 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 13:40:15.614592 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 13:40:15.621294 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
820 13:40:15.624939 0 10 12 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
821 13:40:15.628123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 13:40:15.631621 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 13:40:15.638382 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 13:40:15.641514 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 13:40:15.645114 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 13:40:15.651348 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 13:40:15.654502 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
828 13:40:15.658297 0 11 12 | B1->B0 | 3636 4242 | 1 0 | (1 1) (0 0)
829 13:40:15.665181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 13:40:15.668182 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 13:40:15.671795 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 13:40:15.678469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 13:40:15.681562 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 13:40:15.684870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 13:40:15.688210 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 13:40:15.695059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 13:40:15.698756 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 13:40:15.701660 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 13:40:15.708725 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 13:40:15.712096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 13:40:15.715346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 13:40:15.722100 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 13:40:15.725158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 13:40:15.728793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 13:40:15.735392 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 13:40:15.738921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 13:40:15.742134 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 13:40:15.748834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 13:40:15.751940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 13:40:15.755715 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 13:40:15.758809 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 13:40:15.765528 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 13:40:15.768729 Total UI for P1: 0, mck2ui 16
854 13:40:15.772437 best dqsien dly found for B0: ( 0, 14, 8)
855 13:40:15.775560 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 13:40:15.779140 Total UI for P1: 0, mck2ui 16
857 13:40:15.782438 best dqsien dly found for B1: ( 0, 14, 10)
858 13:40:15.785385 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 13:40:15.788435 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 13:40:15.788519
861 13:40:15.792256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 13:40:15.795254 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 13:40:15.799050 [Gating] SW calibration Done
864 13:40:15.799134 ==
865 13:40:15.802043 Dram Type= 6, Freq= 0, CH_0, rank 0
866 13:40:15.805952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 13:40:15.809070 ==
868 13:40:15.809173 RX Vref Scan: 0
869 13:40:15.809240
870 13:40:15.812426 RX Vref 0 -> 0, step: 1
871 13:40:15.812509
872 13:40:15.815447 RX Delay -130 -> 252, step: 16
873 13:40:15.818893 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 13:40:15.822428 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
875 13:40:15.825805 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 13:40:15.829249 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 13:40:15.835546 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
878 13:40:15.839387 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 13:40:15.842586 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 13:40:15.845871 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 13:40:15.849379 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
882 13:40:15.852551 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 13:40:15.859314 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 13:40:15.862707 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
885 13:40:15.866021 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
886 13:40:15.869581 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 13:40:15.872649 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
888 13:40:15.879334 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 13:40:15.879442 ==
890 13:40:15.883020 Dram Type= 6, Freq= 0, CH_0, rank 0
891 13:40:15.886279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 13:40:15.886370 ==
893 13:40:15.886436 DQS Delay:
894 13:40:15.889196 DQS0 = 0, DQS1 = 0
895 13:40:15.889280 DQM Delay:
896 13:40:15.892914 DQM0 = 86, DQM1 = 76
897 13:40:15.893062 DQ Delay:
898 13:40:15.896120 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 13:40:15.899715 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
900 13:40:15.902798 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
901 13:40:15.906405 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 13:40:15.906497
903 13:40:15.906563
904 13:40:15.906624 ==
905 13:40:15.909500 Dram Type= 6, Freq= 0, CH_0, rank 0
906 13:40:15.913241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 13:40:15.913324 ==
908 13:40:15.913389
909 13:40:15.913449
910 13:40:15.916109 TX Vref Scan disable
911 13:40:15.919804 == TX Byte 0 ==
912 13:40:15.922700 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 13:40:15.926277 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 13:40:15.929378 == TX Byte 1 ==
915 13:40:15.932961 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 13:40:15.936219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 13:40:15.936303 ==
918 13:40:15.939780 Dram Type= 6, Freq= 0, CH_0, rank 0
919 13:40:15.942924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 13:40:15.946526 ==
921 13:40:15.957620 TX Vref=22, minBit 5, minWin=26, winSum=440
922 13:40:15.961272 TX Vref=24, minBit 0, minWin=27, winSum=442
923 13:40:15.964821 TX Vref=26, minBit 7, minWin=27, winSum=446
924 13:40:15.967676 TX Vref=28, minBit 5, minWin=27, winSum=450
925 13:40:15.971483 TX Vref=30, minBit 2, minWin=28, winSum=454
926 13:40:15.974681 TX Vref=32, minBit 12, minWin=27, winSum=451
927 13:40:15.981243 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
928 13:40:15.981344
929 13:40:15.984836 Final TX Range 1 Vref 30
930 13:40:15.984918
931 13:40:15.985009 ==
932 13:40:15.988071 Dram Type= 6, Freq= 0, CH_0, rank 0
933 13:40:15.991389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 13:40:15.991465 ==
935 13:40:15.991527
936 13:40:15.994639
937 13:40:15.994718 TX Vref Scan disable
938 13:40:15.997619 == TX Byte 0 ==
939 13:40:16.001294 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 13:40:16.004363 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 13:40:16.008104 == TX Byte 1 ==
942 13:40:16.011339 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 13:40:16.014394 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 13:40:16.014479
945 13:40:16.017895 [DATLAT]
946 13:40:16.017968 Freq=800, CH0 RK0
947 13:40:16.018031
948 13:40:16.020840 DATLAT Default: 0xa
949 13:40:16.020922 0, 0xFFFF, sum = 0
950 13:40:16.024345 1, 0xFFFF, sum = 0
951 13:40:16.024421 2, 0xFFFF, sum = 0
952 13:40:16.027869 3, 0xFFFF, sum = 0
953 13:40:16.027954 4, 0xFFFF, sum = 0
954 13:40:16.030964 5, 0xFFFF, sum = 0
955 13:40:16.031061 6, 0xFFFF, sum = 0
956 13:40:16.034692 7, 0xFFFF, sum = 0
957 13:40:16.034768 8, 0xFFFF, sum = 0
958 13:40:16.037783 9, 0x0, sum = 1
959 13:40:16.037856 10, 0x0, sum = 2
960 13:40:16.041516 11, 0x0, sum = 3
961 13:40:16.041594 12, 0x0, sum = 4
962 13:40:16.044476 best_step = 10
963 13:40:16.044544
964 13:40:16.044603 ==
965 13:40:16.048144 Dram Type= 6, Freq= 0, CH_0, rank 0
966 13:40:16.051307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 13:40:16.051382 ==
968 13:40:16.054404 RX Vref Scan: 1
969 13:40:16.054474
970 13:40:16.054535 Set Vref Range= 32 -> 127
971 13:40:16.054592
972 13:40:16.058075 RX Vref 32 -> 127, step: 1
973 13:40:16.058145
974 13:40:16.061582 RX Delay -95 -> 252, step: 8
975 13:40:16.061669
976 13:40:16.064962 Set Vref, RX VrefLevel [Byte0]: 32
977 13:40:16.068095 [Byte1]: 32
978 13:40:16.068178
979 13:40:16.072524 Set Vref, RX VrefLevel [Byte0]: 33
980 13:40:16.075440 [Byte1]: 33
981 13:40:16.075526
982 13:40:16.078549 Set Vref, RX VrefLevel [Byte0]: 34
983 13:40:16.082237 [Byte1]: 34
984 13:40:16.085884
985 13:40:16.085994 Set Vref, RX VrefLevel [Byte0]: 35
986 13:40:16.088789 [Byte1]: 35
987 13:40:16.093557
988 13:40:16.093658 Set Vref, RX VrefLevel [Byte0]: 36
989 13:40:16.096372 [Byte1]: 36
990 13:40:16.101330
991 13:40:16.101431 Set Vref, RX VrefLevel [Byte0]: 37
992 13:40:16.104670 [Byte1]: 37
993 13:40:16.108863
994 13:40:16.109032 Set Vref, RX VrefLevel [Byte0]: 38
995 13:40:16.112266 [Byte1]: 38
996 13:40:16.116630
997 13:40:16.116717 Set Vref, RX VrefLevel [Byte0]: 39
998 13:40:16.120066 [Byte1]: 39
999 13:40:16.124243
1000 13:40:16.124329 Set Vref, RX VrefLevel [Byte0]: 40
1001 13:40:16.127245 [Byte1]: 40
1002 13:40:16.131591
1003 13:40:16.131682 Set Vref, RX VrefLevel [Byte0]: 41
1004 13:40:16.134645 [Byte1]: 41
1005 13:40:16.139162
1006 13:40:16.139249 Set Vref, RX VrefLevel [Byte0]: 42
1007 13:40:16.142197 [Byte1]: 42
1008 13:40:16.146598
1009 13:40:16.146672 Set Vref, RX VrefLevel [Byte0]: 43
1010 13:40:16.149565 [Byte1]: 43
1011 13:40:16.154391
1012 13:40:16.154475 Set Vref, RX VrefLevel [Byte0]: 44
1013 13:40:16.157596 [Byte1]: 44
1014 13:40:16.161685
1015 13:40:16.161785 Set Vref, RX VrefLevel [Byte0]: 45
1016 13:40:16.164661 [Byte1]: 45
1017 13:40:16.168931
1018 13:40:16.169081 Set Vref, RX VrefLevel [Byte0]: 46
1019 13:40:16.172283 [Byte1]: 46
1020 13:40:16.176923
1021 13:40:16.177063 Set Vref, RX VrefLevel [Byte0]: 47
1022 13:40:16.180023 [Byte1]: 47
1023 13:40:16.184283
1024 13:40:16.184375 Set Vref, RX VrefLevel [Byte0]: 48
1025 13:40:16.187455 [Byte1]: 48
1026 13:40:16.191984
1027 13:40:16.192083 Set Vref, RX VrefLevel [Byte0]: 49
1028 13:40:16.195172 [Byte1]: 49
1029 13:40:16.199331
1030 13:40:16.199421 Set Vref, RX VrefLevel [Byte0]: 50
1031 13:40:16.202704 [Byte1]: 50
1032 13:40:16.207318
1033 13:40:16.207411 Set Vref, RX VrefLevel [Byte0]: 51
1034 13:40:16.210866 [Byte1]: 51
1035 13:40:16.214936
1036 13:40:16.215029 Set Vref, RX VrefLevel [Byte0]: 52
1037 13:40:16.218483 [Byte1]: 52
1038 13:40:16.222225
1039 13:40:16.222328 Set Vref, RX VrefLevel [Byte0]: 53
1040 13:40:16.225411 [Byte1]: 53
1041 13:40:16.230103
1042 13:40:16.230196 Set Vref, RX VrefLevel [Byte0]: 54
1043 13:40:16.232889 [Byte1]: 54
1044 13:40:16.237946
1045 13:40:16.238041 Set Vref, RX VrefLevel [Byte0]: 55
1046 13:40:16.240844 [Byte1]: 55
1047 13:40:16.245123
1048 13:40:16.245204 Set Vref, RX VrefLevel [Byte0]: 56
1049 13:40:16.248248 [Byte1]: 56
1050 13:40:16.252660
1051 13:40:16.255701 Set Vref, RX VrefLevel [Byte0]: 57
1052 13:40:16.255785 [Byte1]: 57
1053 13:40:16.260243
1054 13:40:16.260344 Set Vref, RX VrefLevel [Byte0]: 58
1055 13:40:16.263665 [Byte1]: 58
1056 13:40:16.268142
1057 13:40:16.268228 Set Vref, RX VrefLevel [Byte0]: 59
1058 13:40:16.271239 [Byte1]: 59
1059 13:40:16.275468
1060 13:40:16.275583 Set Vref, RX VrefLevel [Byte0]: 60
1061 13:40:16.278958 [Byte1]: 60
1062 13:40:16.282857
1063 13:40:16.282948 Set Vref, RX VrefLevel [Byte0]: 61
1064 13:40:16.286442 [Byte1]: 61
1065 13:40:16.290459
1066 13:40:16.290546 Set Vref, RX VrefLevel [Byte0]: 62
1067 13:40:16.294158 [Byte1]: 62
1068 13:40:16.298301
1069 13:40:16.298391 Set Vref, RX VrefLevel [Byte0]: 63
1070 13:40:16.301326 [Byte1]: 63
1071 13:40:16.305734
1072 13:40:16.305820 Set Vref, RX VrefLevel [Byte0]: 64
1073 13:40:16.308851 [Byte1]: 64
1074 13:40:16.313710
1075 13:40:16.313799 Set Vref, RX VrefLevel [Byte0]: 65
1076 13:40:16.316677 [Byte1]: 65
1077 13:40:16.320929
1078 13:40:16.321107 Set Vref, RX VrefLevel [Byte0]: 66
1079 13:40:16.324388 [Byte1]: 66
1080 13:40:16.328640
1081 13:40:16.328753 Set Vref, RX VrefLevel [Byte0]: 67
1082 13:40:16.332117 [Byte1]: 67
1083 13:40:16.336260
1084 13:40:16.336341 Set Vref, RX VrefLevel [Byte0]: 68
1085 13:40:16.339459 [Byte1]: 68
1086 13:40:16.343770
1087 13:40:16.343855 Set Vref, RX VrefLevel [Byte0]: 69
1088 13:40:16.347216 [Byte1]: 69
1089 13:40:16.351354
1090 13:40:16.351434 Set Vref, RX VrefLevel [Byte0]: 70
1091 13:40:16.355245 [Byte1]: 70
1092 13:40:16.359403
1093 13:40:16.359481 Set Vref, RX VrefLevel [Byte0]: 71
1094 13:40:16.362509 [Byte1]: 71
1095 13:40:16.366965
1096 13:40:16.367048 Set Vref, RX VrefLevel [Byte0]: 72
1097 13:40:16.370134 [Byte1]: 72
1098 13:40:16.374363
1099 13:40:16.374442 Set Vref, RX VrefLevel [Byte0]: 73
1100 13:40:16.377881 [Byte1]: 73
1101 13:40:16.382126
1102 13:40:16.382208 Set Vref, RX VrefLevel [Byte0]: 74
1103 13:40:16.385236 [Byte1]: 74
1104 13:40:16.389415
1105 13:40:16.389492 Set Vref, RX VrefLevel [Byte0]: 75
1106 13:40:16.392700 [Byte1]: 75
1107 13:40:16.397155
1108 13:40:16.397267 Set Vref, RX VrefLevel [Byte0]: 76
1109 13:40:16.400356 [Byte1]: 76
1110 13:40:16.404832
1111 13:40:16.404948 Final RX Vref Byte 0 = 61 to rank0
1112 13:40:16.407877 Final RX Vref Byte 1 = 55 to rank0
1113 13:40:16.411501 Final RX Vref Byte 0 = 61 to rank1
1114 13:40:16.414629 Final RX Vref Byte 1 = 55 to rank1==
1115 13:40:16.417975 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 13:40:16.421170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 13:40:16.424777 ==
1118 13:40:16.424891 DQS Delay:
1119 13:40:16.424989 DQS0 = 0, DQS1 = 0
1120 13:40:16.427958 DQM Delay:
1121 13:40:16.428039 DQM0 = 88, DQM1 = 78
1122 13:40:16.431466 DQ Delay:
1123 13:40:16.431548 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 13:40:16.434574 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1125 13:40:16.438241 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1126 13:40:16.441366 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1127 13:40:16.441439
1128 13:40:16.445014
1129 13:40:16.451329 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1130 13:40:16.454578 CH0 RK0: MR19=606, MR18=2C13
1131 13:40:16.461707 CH0_RK0: MR19=0x606, MR18=0x2C13, DQSOSC=398, MR23=63, INC=93, DEC=62
1132 13:40:16.461820
1133 13:40:16.464690 ----->DramcWriteLeveling(PI) begin...
1134 13:40:16.464770 ==
1135 13:40:16.468294 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 13:40:16.471364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 13:40:16.471443 ==
1138 13:40:16.474466 Write leveling (Byte 0): 32 => 32
1139 13:40:16.478133 Write leveling (Byte 1): 30 => 30
1140 13:40:16.481753 DramcWriteLeveling(PI) end<-----
1141 13:40:16.481849
1142 13:40:16.481911 ==
1143 13:40:16.484811 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 13:40:16.488636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 13:40:16.488711 ==
1146 13:40:16.491538 [Gating] SW mode calibration
1147 13:40:16.498308 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 13:40:16.505332 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 13:40:16.508764 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 13:40:16.511810 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 13:40:16.556100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1152 13:40:16.556537 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 13:40:16.556641 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 13:40:16.556755 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 13:40:16.556892 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 13:40:16.557003 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 13:40:16.557102 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 13:40:16.557201 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 13:40:16.557301 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 13:40:16.557402 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 13:40:16.597495 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 13:40:16.597652 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 13:40:16.597944 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 13:40:16.598016 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 13:40:16.598094 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 13:40:16.598168 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 13:40:16.598256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1168 13:40:16.598368 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 13:40:16.598460 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 13:40:16.601289 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 13:40:16.604679 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 13:40:16.608388 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 13:40:16.615063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 13:40:16.618430 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 13:40:16.621723 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1176 13:40:16.625125 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1177 13:40:16.631673 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 13:40:16.635396 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 13:40:16.638470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 13:40:16.645283 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 13:40:16.648399 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 13:40:16.652092 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1183 13:40:16.658402 0 10 8 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
1184 13:40:16.662238 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1185 13:40:16.665213 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 13:40:16.671839 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 13:40:16.675354 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 13:40:16.678922 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 13:40:16.682627 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 13:40:16.689724 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1191 13:40:16.693835 0 11 8 | B1->B0 | 2727 3e3e | 0 0 | (0 0) (0 0)
1192 13:40:16.697594 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1193 13:40:16.700623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 13:40:16.703736 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 13:40:16.711002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 13:40:16.714637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 13:40:16.718290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 13:40:16.725218 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 13:40:16.727973 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1200 13:40:16.731489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 13:40:16.734641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 13:40:16.741580 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 13:40:16.744626 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 13:40:16.748318 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 13:40:16.755184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 13:40:16.758204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 13:40:16.761897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 13:40:16.768739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 13:40:16.771705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 13:40:16.775345 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 13:40:16.781640 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 13:40:16.785377 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 13:40:16.788414 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 13:40:16.791799 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 13:40:16.798625 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 13:40:16.801937 Total UI for P1: 0, mck2ui 16
1217 13:40:16.805594 best dqsien dly found for B0: ( 0, 14, 2)
1218 13:40:16.809123 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 13:40:16.812455 Total UI for P1: 0, mck2ui 16
1220 13:40:16.815400 best dqsien dly found for B1: ( 0, 14, 8)
1221 13:40:16.819070 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1222 13:40:16.822109 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 13:40:16.822212
1224 13:40:16.825676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1225 13:40:16.828728 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 13:40:16.832302 [Gating] SW calibration Done
1227 13:40:16.832397 ==
1228 13:40:16.835510 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 13:40:16.838922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 13:40:16.839027 ==
1231 13:40:16.842236 RX Vref Scan: 0
1232 13:40:16.842323
1233 13:40:16.845933 RX Vref 0 -> 0, step: 1
1234 13:40:16.846018
1235 13:40:16.846131 RX Delay -130 -> 252, step: 16
1236 13:40:16.852116 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1237 13:40:16.855794 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1238 13:40:16.858869 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 13:40:16.862573 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1240 13:40:16.865646 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1241 13:40:16.872599 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 13:40:16.876169 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 13:40:16.879185 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 13:40:16.882375 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 13:40:16.885953 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 13:40:16.892371 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 13:40:16.896215 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 13:40:16.899628 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1249 13:40:16.902897 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1250 13:40:16.906403 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1251 13:40:16.912603 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1252 13:40:16.912736 ==
1253 13:40:16.915898 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 13:40:16.919345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 13:40:16.919456 ==
1256 13:40:16.919547 DQS Delay:
1257 13:40:16.922531 DQS0 = 0, DQS1 = 0
1258 13:40:16.922643 DQM Delay:
1259 13:40:16.926705 DQM0 = 85, DQM1 = 73
1260 13:40:16.926812 DQ Delay:
1261 13:40:16.929518 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1262 13:40:16.933066 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1263 13:40:16.936022 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1264 13:40:16.939662 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
1265 13:40:16.939785
1266 13:40:16.939878
1267 13:40:16.939965 ==
1268 13:40:16.943301 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 13:40:16.946066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 13:40:16.946141 ==
1271 13:40:16.946203
1272 13:40:16.946264
1273 13:40:16.949527 TX Vref Scan disable
1274 13:40:16.953337 == TX Byte 0 ==
1275 13:40:16.956227 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1276 13:40:16.959763 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1277 13:40:16.963257 == TX Byte 1 ==
1278 13:40:16.966356 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 13:40:16.970029 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 13:40:16.970120 ==
1281 13:40:16.972971 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 13:40:16.976648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 13:40:16.979677 ==
1284 13:40:16.991478 TX Vref=22, minBit 5, minWin=27, winSum=448
1285 13:40:16.994159 TX Vref=24, minBit 9, minWin=27, winSum=449
1286 13:40:16.997917 TX Vref=26, minBit 9, minWin=27, winSum=448
1287 13:40:17.000971 TX Vref=28, minBit 5, minWin=28, winSum=457
1288 13:40:17.004597 TX Vref=30, minBit 4, minWin=28, winSum=458
1289 13:40:17.011339 TX Vref=32, minBit 4, minWin=28, winSum=455
1290 13:40:17.014432 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1291 13:40:17.014540
1292 13:40:17.017603 Final TX Range 1 Vref 30
1293 13:40:17.017734
1294 13:40:17.017804 ==
1295 13:40:17.021289 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 13:40:17.024303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 13:40:17.024411 ==
1298 13:40:17.027398
1299 13:40:17.027526
1300 13:40:17.027619 TX Vref Scan disable
1301 13:40:17.031059 == TX Byte 0 ==
1302 13:40:17.034687 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1303 13:40:17.038253 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1304 13:40:17.040912 == TX Byte 1 ==
1305 13:40:17.044405 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 13:40:17.048003 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 13:40:17.048098
1308 13:40:17.051486 [DATLAT]
1309 13:40:17.051559 Freq=800, CH0 RK1
1310 13:40:17.051617
1311 13:40:17.054605 DATLAT Default: 0xa
1312 13:40:17.054699 0, 0xFFFF, sum = 0
1313 13:40:17.058046 1, 0xFFFF, sum = 0
1314 13:40:17.058130 2, 0xFFFF, sum = 0
1315 13:40:17.061287 3, 0xFFFF, sum = 0
1316 13:40:17.061377 4, 0xFFFF, sum = 0
1317 13:40:17.064520 5, 0xFFFF, sum = 0
1318 13:40:17.064674 6, 0xFFFF, sum = 0
1319 13:40:17.067804 7, 0xFFFF, sum = 0
1320 13:40:17.067907 8, 0xFFFF, sum = 0
1321 13:40:17.071659 9, 0x0, sum = 1
1322 13:40:17.071770 10, 0x0, sum = 2
1323 13:40:17.075009 11, 0x0, sum = 3
1324 13:40:17.075120 12, 0x0, sum = 4
1325 13:40:17.077983 best_step = 10
1326 13:40:17.078089
1327 13:40:17.078157 ==
1328 13:40:17.081807 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 13:40:17.084859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 13:40:17.084997 ==
1331 13:40:17.087885 RX Vref Scan: 0
1332 13:40:17.087970
1333 13:40:17.088035 RX Vref 0 -> 0, step: 1
1334 13:40:17.088094
1335 13:40:17.091666 RX Delay -95 -> 252, step: 8
1336 13:40:17.098334 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 13:40:17.101432 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 13:40:17.105104 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 13:40:17.108540 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 13:40:17.111790 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1341 13:40:17.114789 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 13:40:17.121905 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 13:40:17.125381 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 13:40:17.128525 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 13:40:17.131697 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 13:40:17.135434 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 13:40:17.141947 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 13:40:17.145588 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 13:40:17.148631 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1350 13:40:17.151772 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 13:40:17.155441 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 13:40:17.158478 ==
1353 13:40:17.158570 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 13:40:17.165338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 13:40:17.165446 ==
1356 13:40:17.165511 DQS Delay:
1357 13:40:17.168798 DQS0 = 0, DQS1 = 0
1358 13:40:17.168884 DQM Delay:
1359 13:40:17.168948 DQM0 = 87, DQM1 = 78
1360 13:40:17.172331 DQ Delay:
1361 13:40:17.175559 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 13:40:17.178715 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1363 13:40:17.182218 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 13:40:17.185783 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1365 13:40:17.185886
1366 13:40:17.185953
1367 13:40:17.192120 [DQSOSCAuto] RK1, (LSB)MR18= 0x341f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1368 13:40:17.195752 CH0 RK1: MR19=606, MR18=341F
1369 13:40:17.202498 CH0_RK1: MR19=0x606, MR18=0x341F, DQSOSC=396, MR23=63, INC=94, DEC=62
1370 13:40:17.205590 [RxdqsGatingPostProcess] freq 800
1371 13:40:17.209163 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 13:40:17.212132 Pre-setting of DQS Precalculation
1373 13:40:17.218981 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 13:40:17.219091 ==
1375 13:40:17.222689 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 13:40:17.226014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 13:40:17.226116 ==
1378 13:40:17.232837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 13:40:17.235941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 13:40:17.246379 [CA 0] Center 36 (6~66) winsize 61
1381 13:40:17.249226 [CA 1] Center 36 (6~66) winsize 61
1382 13:40:17.252956 [CA 2] Center 34 (4~65) winsize 62
1383 13:40:17.256076 [CA 3] Center 33 (3~64) winsize 62
1384 13:40:17.259212 [CA 4] Center 34 (4~65) winsize 62
1385 13:40:17.262909 [CA 5] Center 33 (3~64) winsize 62
1386 13:40:17.263057
1387 13:40:17.266450 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 13:40:17.266545
1389 13:40:17.269330 [CATrainingPosCal] consider 1 rank data
1390 13:40:17.272574 u2DelayCellTimex100 = 270/100 ps
1391 13:40:17.276251 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 13:40:17.279239 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 13:40:17.283083 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1394 13:40:17.289667 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1395 13:40:17.292407 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 13:40:17.296031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 13:40:17.296177
1398 13:40:17.299466 CA PerBit enable=1, Macro0, CA PI delay=33
1399 13:40:17.299601
1400 13:40:17.303157 [CBTSetCACLKResult] CA Dly = 33
1401 13:40:17.303248 CS Dly: 5 (0~36)
1402 13:40:17.303342 ==
1403 13:40:17.305976 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 13:40:17.312967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 13:40:17.313165 ==
1406 13:40:17.315895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 13:40:17.322753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 13:40:17.332140 [CA 0] Center 36 (6~66) winsize 61
1409 13:40:17.335409 [CA 1] Center 36 (6~66) winsize 61
1410 13:40:17.339002 [CA 2] Center 34 (4~65) winsize 62
1411 13:40:17.342115 [CA 3] Center 34 (3~65) winsize 63
1412 13:40:17.345300 [CA 4] Center 34 (4~64) winsize 61
1413 13:40:17.349171 [CA 5] Center 33 (3~64) winsize 62
1414 13:40:17.349280
1415 13:40:17.352913 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 13:40:17.353028
1417 13:40:17.356627 [CATrainingPosCal] consider 2 rank data
1418 13:40:17.360366 u2DelayCellTimex100 = 270/100 ps
1419 13:40:17.363486 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 13:40:17.367326 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 13:40:17.370717 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1422 13:40:17.374062 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 13:40:17.378449 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1424 13:40:17.381544 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 13:40:17.381666
1426 13:40:17.385258 CA PerBit enable=1, Macro0, CA PI delay=33
1427 13:40:17.385352
1428 13:40:17.388927 [CBTSetCACLKResult] CA Dly = 33
1429 13:40:17.389030 CS Dly: 5 (0~36)
1430 13:40:17.389115
1431 13:40:17.392284 ----->DramcWriteLeveling(PI) begin...
1432 13:40:17.392373 ==
1433 13:40:17.395302 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 13:40:17.402393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 13:40:17.402513 ==
1436 13:40:17.405256 Write leveling (Byte 0): 28 => 28
1437 13:40:17.409290 Write leveling (Byte 1): 28 => 28
1438 13:40:17.409386 DramcWriteLeveling(PI) end<-----
1439 13:40:17.409474
1440 13:40:17.412205 ==
1441 13:40:17.415710 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 13:40:17.418869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 13:40:17.418992 ==
1444 13:40:17.422311 [Gating] SW mode calibration
1445 13:40:17.428950 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 13:40:17.432379 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 13:40:17.439415 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 13:40:17.442520 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 13:40:17.446212 0 6 8 | B1->B0 | 2323 2323 | 1 0 | (0 0) (1 0)
1450 13:40:17.449429 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 13:40:17.456106 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 13:40:17.459228 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 13:40:17.462858 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 13:40:17.469238 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 13:40:17.472935 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 13:40:17.475976 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 13:40:17.482927 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 13:40:17.486065 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 13:40:17.489877 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1460 13:40:17.495964 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 13:40:17.499628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 13:40:17.502681 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1463 13:40:17.509515 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 13:40:17.513096 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 13:40:17.516110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1466 13:40:17.522865 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 13:40:17.526561 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 13:40:17.529612 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1469 13:40:17.532737 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 13:40:17.539503 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 13:40:17.543053 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 13:40:17.546417 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 13:40:17.553083 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 13:40:17.556694 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 13:40:17.559782 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 13:40:17.566512 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 13:40:17.570235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 13:40:17.573328 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1479 13:40:17.576583 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 13:40:17.583448 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1481 13:40:17.586421 0 10 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 1)
1482 13:40:17.589939 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 13:40:17.596878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 13:40:17.599981 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 13:40:17.603737 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 13:40:17.609932 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1487 13:40:17.613747 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 13:40:17.616764 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1489 13:40:17.623601 0 11 8 | B1->B0 | 3636 3434 | 0 0 | (0 0) (1 1)
1490 13:40:17.627181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 13:40:17.630571 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 13:40:17.637418 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 13:40:17.640458 0 11 24 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1494 13:40:17.643554 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 13:40:17.646983 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 13:40:17.653795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 13:40:17.657216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 13:40:17.660279 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 13:40:17.667046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 13:40:17.670725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 13:40:17.673723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 13:40:17.680507 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 13:40:17.684252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 13:40:17.687168 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 13:40:17.694130 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 13:40:17.697435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 13:40:17.700893 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 13:40:17.704157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 13:40:17.711154 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 13:40:17.714294 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 13:40:17.717528 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 13:40:17.724374 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 13:40:17.727445 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 13:40:17.731100 Total UI for P1: 0, mck2ui 16
1515 13:40:17.734252 best dqsien dly found for B0: ( 0, 14, 6)
1516 13:40:17.737649 Total UI for P1: 0, mck2ui 16
1517 13:40:17.740958 best dqsien dly found for B1: ( 0, 14, 6)
1518 13:40:17.744522 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 13:40:17.747934 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1520 13:40:17.748032
1521 13:40:17.751478 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 13:40:17.754191 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 13:40:17.757709 [Gating] SW calibration Done
1524 13:40:17.757847 ==
1525 13:40:17.761143 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 13:40:17.764345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 13:40:17.764445 ==
1528 13:40:17.767684 RX Vref Scan: 0
1529 13:40:17.767818
1530 13:40:17.771153 RX Vref 0 -> 0, step: 1
1531 13:40:17.771267
1532 13:40:17.771361 RX Delay -130 -> 252, step: 16
1533 13:40:17.778229 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1534 13:40:17.781345 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1535 13:40:17.784396 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1536 13:40:17.788330 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1537 13:40:17.791384 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1538 13:40:17.798398 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1539 13:40:17.801452 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1540 13:40:17.804917 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1541 13:40:17.807954 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1542 13:40:17.811472 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1543 13:40:17.814582 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1544 13:40:17.821923 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1545 13:40:17.825093 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1546 13:40:17.828623 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1547 13:40:17.831744 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1548 13:40:17.834867 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1549 13:40:17.838600 ==
1550 13:40:17.841736 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 13:40:17.845332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 13:40:17.845419 ==
1553 13:40:17.845491 DQS Delay:
1554 13:40:17.848393 DQS0 = 0, DQS1 = 0
1555 13:40:17.848476 DQM Delay:
1556 13:40:17.851941 DQM0 = 83, DQM1 = 77
1557 13:40:17.852032 DQ Delay:
1558 13:40:17.855648 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1559 13:40:17.858719 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1560 13:40:17.862258 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1561 13:40:17.865593 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 13:40:17.865689
1563 13:40:17.865753
1564 13:40:17.865810 ==
1565 13:40:17.869012 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 13:40:17.871853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 13:40:17.871961 ==
1568 13:40:17.872050
1569 13:40:17.872134
1570 13:40:17.875307 TX Vref Scan disable
1571 13:40:17.875412 == TX Byte 0 ==
1572 13:40:17.882378 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1573 13:40:17.885616 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1574 13:40:17.885738 == TX Byte 1 ==
1575 13:40:17.892211 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 13:40:17.895389 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 13:40:17.895527 ==
1578 13:40:17.898565 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 13:40:17.902481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 13:40:17.902570 ==
1581 13:40:17.916391 TX Vref=22, minBit 1, minWin=27, winSum=437
1582 13:40:17.919306 TX Vref=24, minBit 0, minWin=27, winSum=439
1583 13:40:17.922941 TX Vref=26, minBit 7, minWin=27, winSum=445
1584 13:40:17.926256 TX Vref=28, minBit 11, minWin=27, winSum=449
1585 13:40:17.929339 TX Vref=30, minBit 0, minWin=28, winSum=452
1586 13:40:17.933963 TX Vref=32, minBit 0, minWin=28, winSum=455
1587 13:40:17.940840 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
1588 13:40:17.941056
1589 13:40:17.944010 Final TX Range 1 Vref 32
1590 13:40:17.944151
1591 13:40:17.944241 ==
1592 13:40:17.947171 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 13:40:17.950903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 13:40:17.950995 ==
1595 13:40:17.951058
1596 13:40:17.951165
1597 13:40:17.953930 TX Vref Scan disable
1598 13:40:17.957230 == TX Byte 0 ==
1599 13:40:17.960850 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 13:40:17.963960 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 13:40:17.967665 == TX Byte 1 ==
1602 13:40:17.970598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 13:40:17.974302 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 13:40:17.974399
1605 13:40:17.974464 [DATLAT]
1606 13:40:17.977761 Freq=800, CH1 RK0
1607 13:40:17.977883
1608 13:40:17.977997 DATLAT Default: 0xa
1609 13:40:17.981168 0, 0xFFFF, sum = 0
1610 13:40:17.981245 1, 0xFFFF, sum = 0
1611 13:40:17.984505 2, 0xFFFF, sum = 0
1612 13:40:17.984588 3, 0xFFFF, sum = 0
1613 13:40:17.987744 4, 0xFFFF, sum = 0
1614 13:40:17.987823 5, 0xFFFF, sum = 0
1615 13:40:17.991396 6, 0xFFFF, sum = 0
1616 13:40:17.994241 7, 0xFFFF, sum = 0
1617 13:40:17.994324 8, 0xFFFF, sum = 0
1618 13:40:17.994386 9, 0x0, sum = 1
1619 13:40:17.997960 10, 0x0, sum = 2
1620 13:40:17.998037 11, 0x0, sum = 3
1621 13:40:18.000839 12, 0x0, sum = 4
1622 13:40:18.000919 best_step = 10
1623 13:40:18.001005
1624 13:40:18.001112 ==
1625 13:40:18.004750 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 13:40:18.011663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 13:40:18.011782 ==
1628 13:40:18.011851 RX Vref Scan: 1
1629 13:40:18.011909
1630 13:40:18.014771 Set Vref Range= 32 -> 127
1631 13:40:18.014862
1632 13:40:18.017877 RX Vref 32 -> 127, step: 1
1633 13:40:18.018064
1634 13:40:18.018194 RX Delay -95 -> 252, step: 8
1635 13:40:18.021618
1636 13:40:18.021715 Set Vref, RX VrefLevel [Byte0]: 32
1637 13:40:18.024501 [Byte1]: 32
1638 13:40:18.028459
1639 13:40:18.028603 Set Vref, RX VrefLevel [Byte0]: 33
1640 13:40:18.032387 [Byte1]: 33
1641 13:40:18.036053
1642 13:40:18.036150 Set Vref, RX VrefLevel [Byte0]: 34
1643 13:40:18.039949 [Byte1]: 34
1644 13:40:18.044279
1645 13:40:18.044385 Set Vref, RX VrefLevel [Byte0]: 35
1646 13:40:18.047434 [Byte1]: 35
1647 13:40:18.051849
1648 13:40:18.051955 Set Vref, RX VrefLevel [Byte0]: 36
1649 13:40:18.054849 [Byte1]: 36
1650 13:40:18.059285
1651 13:40:18.059382 Set Vref, RX VrefLevel [Byte0]: 37
1652 13:40:18.062354 [Byte1]: 37
1653 13:40:18.066605
1654 13:40:18.066706 Set Vref, RX VrefLevel [Byte0]: 38
1655 13:40:18.070151 [Byte1]: 38
1656 13:40:18.074221
1657 13:40:18.074322 Set Vref, RX VrefLevel [Byte0]: 39
1658 13:40:18.077727 [Byte1]: 39
1659 13:40:18.082075
1660 13:40:18.082175 Set Vref, RX VrefLevel [Byte0]: 40
1661 13:40:18.085622 [Byte1]: 40
1662 13:40:18.089471
1663 13:40:18.089598 Set Vref, RX VrefLevel [Byte0]: 41
1664 13:40:18.092843 [Byte1]: 41
1665 13:40:18.097309
1666 13:40:18.097412 Set Vref, RX VrefLevel [Byte0]: 42
1667 13:40:18.100246 [Byte1]: 42
1668 13:40:18.104879
1669 13:40:18.105008 Set Vref, RX VrefLevel [Byte0]: 43
1670 13:40:18.108166 [Byte1]: 43
1671 13:40:18.112271
1672 13:40:18.112400 Set Vref, RX VrefLevel [Byte0]: 44
1673 13:40:18.115583 [Byte1]: 44
1674 13:40:18.120017
1675 13:40:18.120135 Set Vref, RX VrefLevel [Byte0]: 45
1676 13:40:18.122894 [Byte1]: 45
1677 13:40:18.127887
1678 13:40:18.128017 Set Vref, RX VrefLevel [Byte0]: 46
1679 13:40:18.130976 [Byte1]: 46
1680 13:40:18.135343
1681 13:40:18.135434 Set Vref, RX VrefLevel [Byte0]: 47
1682 13:40:18.138497 [Byte1]: 47
1683 13:40:18.142826
1684 13:40:18.142942 Set Vref, RX VrefLevel [Byte0]: 48
1685 13:40:18.146029 [Byte1]: 48
1686 13:40:18.150423
1687 13:40:18.150519 Set Vref, RX VrefLevel [Byte0]: 49
1688 13:40:18.153360 [Byte1]: 49
1689 13:40:18.157775
1690 13:40:18.157866 Set Vref, RX VrefLevel [Byte0]: 50
1691 13:40:18.161406 [Byte1]: 50
1692 13:40:18.165702
1693 13:40:18.165792 Set Vref, RX VrefLevel [Byte0]: 51
1694 13:40:18.168914 [Byte1]: 51
1695 13:40:18.173178
1696 13:40:18.173282 Set Vref, RX VrefLevel [Byte0]: 52
1697 13:40:18.176610 [Byte1]: 52
1698 13:40:18.180880
1699 13:40:18.181015 Set Vref, RX VrefLevel [Byte0]: 53
1700 13:40:18.185934 [Byte1]: 53
1701 13:40:18.188175
1702 13:40:18.188284 Set Vref, RX VrefLevel [Byte0]: 54
1703 13:40:18.191367 [Byte1]: 54
1704 13:40:18.195695
1705 13:40:18.195779 Set Vref, RX VrefLevel [Byte0]: 55
1706 13:40:18.199240 [Byte1]: 55
1707 13:40:18.203401
1708 13:40:18.203477 Set Vref, RX VrefLevel [Byte0]: 56
1709 13:40:18.207047 [Byte1]: 56
1710 13:40:18.211037
1711 13:40:18.211115 Set Vref, RX VrefLevel [Byte0]: 57
1712 13:40:18.214248 [Byte1]: 57
1713 13:40:18.218826
1714 13:40:18.218937 Set Vref, RX VrefLevel [Byte0]: 58
1715 13:40:18.222182 [Byte1]: 58
1716 13:40:18.226369
1717 13:40:18.226468 Set Vref, RX VrefLevel [Byte0]: 59
1718 13:40:18.229337 [Byte1]: 59
1719 13:40:18.234107
1720 13:40:18.234192 Set Vref, RX VrefLevel [Byte0]: 60
1721 13:40:18.237200 [Byte1]: 60
1722 13:40:18.241188
1723 13:40:18.241301 Set Vref, RX VrefLevel [Byte0]: 61
1724 13:40:18.245226 [Byte1]: 61
1725 13:40:18.249205
1726 13:40:18.249311 Set Vref, RX VrefLevel [Byte0]: 62
1727 13:40:18.252258 [Byte1]: 62
1728 13:40:18.256769
1729 13:40:18.256865 Set Vref, RX VrefLevel [Byte0]: 63
1730 13:40:18.260269 [Byte1]: 63
1731 13:40:18.264089
1732 13:40:18.264180 Set Vref, RX VrefLevel [Byte0]: 64
1733 13:40:18.267530 [Byte1]: 64
1734 13:40:18.272148
1735 13:40:18.272291 Set Vref, RX VrefLevel [Byte0]: 65
1736 13:40:18.275202 [Byte1]: 65
1737 13:40:18.279354
1738 13:40:18.279444 Set Vref, RX VrefLevel [Byte0]: 66
1739 13:40:18.282884 [Byte1]: 66
1740 13:40:18.287264
1741 13:40:18.287429 Set Vref, RX VrefLevel [Byte0]: 67
1742 13:40:18.290636 [Byte1]: 67
1743 13:40:18.294642
1744 13:40:18.294799 Set Vref, RX VrefLevel [Byte0]: 68
1745 13:40:18.298102 [Byte1]: 68
1746 13:40:18.302434
1747 13:40:18.302588 Set Vref, RX VrefLevel [Byte0]: 69
1748 13:40:18.305453 [Byte1]: 69
1749 13:40:18.310096
1750 13:40:18.310249 Set Vref, RX VrefLevel [Byte0]: 70
1751 13:40:18.313369 [Byte1]: 70
1752 13:40:18.317593
1753 13:40:18.317703 Set Vref, RX VrefLevel [Byte0]: 71
1754 13:40:18.321322 [Byte1]: 71
1755 13:40:18.325350
1756 13:40:18.325458 Set Vref, RX VrefLevel [Byte0]: 72
1757 13:40:18.328743 [Byte1]: 72
1758 13:40:18.332819
1759 13:40:18.332938 Set Vref, RX VrefLevel [Byte0]: 73
1760 13:40:18.335936 [Byte1]: 73
1761 13:40:18.340527
1762 13:40:18.340659 Set Vref, RX VrefLevel [Byte0]: 74
1763 13:40:18.343502 [Byte1]: 74
1764 13:40:18.348326
1765 13:40:18.348446 Set Vref, RX VrefLevel [Byte0]: 75
1766 13:40:18.351153 [Byte1]: 75
1767 13:40:18.355596
1768 13:40:18.355708 Set Vref, RX VrefLevel [Byte0]: 76
1769 13:40:18.358668 [Byte1]: 76
1770 13:40:18.363040
1771 13:40:18.363152 Set Vref, RX VrefLevel [Byte0]: 77
1772 13:40:18.366103 [Byte1]: 77
1773 13:40:18.370501
1774 13:40:18.370614 Set Vref, RX VrefLevel [Byte0]: 78
1775 13:40:18.374271 [Byte1]: 78
1776 13:40:18.378454
1777 13:40:18.378558 Set Vref, RX VrefLevel [Byte0]: 79
1778 13:40:18.381545 [Byte1]: 79
1779 13:40:18.385690
1780 13:40:18.389169 Final RX Vref Byte 0 = 67 to rank0
1781 13:40:18.389267 Final RX Vref Byte 1 = 60 to rank0
1782 13:40:18.392292 Final RX Vref Byte 0 = 67 to rank1
1783 13:40:18.395621 Final RX Vref Byte 1 = 60 to rank1==
1784 13:40:18.399233 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 13:40:18.405660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 13:40:18.405785 ==
1787 13:40:18.405856 DQS Delay:
1788 13:40:18.405916 DQS0 = 0, DQS1 = 0
1789 13:40:18.409339 DQM Delay:
1790 13:40:18.409417 DQM0 = 82, DQM1 = 74
1791 13:40:18.412375 DQ Delay:
1792 13:40:18.416019 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1793 13:40:18.416105 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1794 13:40:18.419202 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =72
1795 13:40:18.422658 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1796 13:40:18.425768
1797 13:40:18.425874
1798 13:40:18.432369 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1799 13:40:18.436321 CH1 RK0: MR19=605, MR18=27FC
1800 13:40:18.442670 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1801 13:40:18.442795
1802 13:40:18.446020 ----->DramcWriteLeveling(PI) begin...
1803 13:40:18.446107 ==
1804 13:40:18.449390 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 13:40:18.452625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 13:40:18.452715 ==
1807 13:40:18.456226 Write leveling (Byte 0): 29 => 29
1808 13:40:18.459357 Write leveling (Byte 1): 29 => 29
1809 13:40:18.462547 DramcWriteLeveling(PI) end<-----
1810 13:40:18.462645
1811 13:40:18.462711 ==
1812 13:40:18.466162 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 13:40:18.469701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 13:40:18.469793 ==
1815 13:40:18.473151 [Gating] SW mode calibration
1816 13:40:18.479456 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 13:40:18.486535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 13:40:18.489473 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1819 13:40:18.493072 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1820 13:40:18.496392 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 13:40:18.502926 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1822 13:40:18.506753 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 13:40:18.509524 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 13:40:18.516217 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 13:40:18.520009 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 13:40:18.523920 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 13:40:18.529876 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1828 13:40:18.533178 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 13:40:18.536636 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1830 13:40:18.543326 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1831 13:40:18.546483 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 13:40:18.549969 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 13:40:18.556473 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 13:40:18.559896 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1835 13:40:18.563141 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1836 13:40:18.566822 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 13:40:18.573130 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 13:40:18.576449 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 13:40:18.580082 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 13:40:18.586637 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 13:40:18.590187 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 13:40:18.593743 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 13:40:18.600449 0 9 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1844 13:40:18.603393 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
1845 13:40:18.607335 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1846 13:40:18.613800 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 13:40:18.616837 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 13:40:18.620484 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 13:40:18.623573 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 13:40:18.630344 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1851 13:40:18.633703 0 10 4 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
1852 13:40:18.637094 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 13:40:18.643924 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 13:40:18.647555 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 13:40:18.650574 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 13:40:18.657108 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 13:40:18.660602 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1858 13:40:18.664393 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1859 13:40:18.670900 0 11 4 | B1->B0 | 2929 3939 | 0 0 | (0 0) (0 0)
1860 13:40:18.674249 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1861 13:40:18.677514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 13:40:18.684003 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 13:40:18.687181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 13:40:18.690723 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 13:40:18.693974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 13:40:18.700902 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1867 13:40:18.704027 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1868 13:40:18.707840 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 13:40:18.714427 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 13:40:18.717213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 13:40:18.720685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 13:40:18.727376 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 13:40:18.731091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 13:40:18.734112 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 13:40:18.741442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 13:40:18.744761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 13:40:18.747953 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 13:40:18.754351 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 13:40:18.758120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 13:40:18.761554 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 13:40:18.764511 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 13:40:18.771270 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1883 13:40:18.774537 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 13:40:18.778135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 13:40:18.781151 Total UI for P1: 0, mck2ui 16
1886 13:40:18.784755 best dqsien dly found for B0: ( 0, 14, 2)
1887 13:40:18.788544 Total UI for P1: 0, mck2ui 16
1888 13:40:18.791442 best dqsien dly found for B1: ( 0, 14, 4)
1889 13:40:18.794798 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1890 13:40:18.798523 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1891 13:40:18.798687
1892 13:40:18.801591 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1893 13:40:18.808274 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 13:40:18.808414 [Gating] SW calibration Done
1895 13:40:18.808481 ==
1896 13:40:18.811389 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 13:40:18.818189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 13:40:18.818314 ==
1899 13:40:18.818380 RX Vref Scan: 0
1900 13:40:18.818440
1901 13:40:18.821766 RX Vref 0 -> 0, step: 1
1902 13:40:18.821850
1903 13:40:18.825176 RX Delay -130 -> 252, step: 16
1904 13:40:18.828485 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1905 13:40:18.831693 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1906 13:40:18.835407 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1907 13:40:18.838236 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1908 13:40:18.845398 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1909 13:40:18.848647 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1910 13:40:18.852263 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1911 13:40:18.855548 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1912 13:40:18.858754 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1913 13:40:18.865098 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1914 13:40:18.868675 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1915 13:40:18.871781 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1916 13:40:18.875458 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1917 13:40:18.878677 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1918 13:40:18.885266 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1919 13:40:18.888680 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1920 13:40:18.888791 ==
1921 13:40:18.892266 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 13:40:18.895730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 13:40:18.895821 ==
1924 13:40:18.898763 DQS Delay:
1925 13:40:18.898869 DQS0 = 0, DQS1 = 0
1926 13:40:18.898934 DQM Delay:
1927 13:40:18.902553 DQM0 = 81, DQM1 = 77
1928 13:40:18.902634 DQ Delay:
1929 13:40:18.905568 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1930 13:40:18.908922 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1931 13:40:18.912329 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1932 13:40:18.916225 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1933 13:40:18.916310
1934 13:40:18.916373
1935 13:40:18.916428 ==
1936 13:40:18.918857 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 13:40:18.922293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 13:40:18.922369 ==
1939 13:40:18.925841
1940 13:40:18.925958
1941 13:40:18.926048 TX Vref Scan disable
1942 13:40:18.929638 == TX Byte 0 ==
1943 13:40:18.932307 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1944 13:40:18.935817 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1945 13:40:18.939501 == TX Byte 1 ==
1946 13:40:18.942483 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1947 13:40:18.946098 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1948 13:40:18.946190 ==
1949 13:40:18.948923 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 13:40:18.955770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 13:40:18.955888 ==
1952 13:40:18.967678 TX Vref=22, minBit 0, minWin=27, winSum=441
1953 13:40:18.970981 TX Vref=24, minBit 5, minWin=27, winSum=445
1954 13:40:18.974370 TX Vref=26, minBit 3, minWin=27, winSum=447
1955 13:40:18.977900 TX Vref=28, minBit 0, minWin=28, winSum=449
1956 13:40:18.980849 TX Vref=30, minBit 0, minWin=28, winSum=452
1957 13:40:18.984606 TX Vref=32, minBit 3, minWin=27, winSum=450
1958 13:40:18.991235 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1959 13:40:18.991337
1960 13:40:18.994319 Final TX Range 1 Vref 30
1961 13:40:18.994394
1962 13:40:18.994460 ==
1963 13:40:18.997839 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 13:40:19.001214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 13:40:19.001291 ==
1966 13:40:19.001351
1967 13:40:19.001406
1968 13:40:19.004196 TX Vref Scan disable
1969 13:40:19.007759 == TX Byte 0 ==
1970 13:40:19.011444 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1971 13:40:19.014439 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1972 13:40:19.018018 == TX Byte 1 ==
1973 13:40:19.021106 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 13:40:19.024227 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 13:40:19.024313
1976 13:40:19.028511 [DATLAT]
1977 13:40:19.028606 Freq=800, CH1 RK1
1978 13:40:19.028672
1979 13:40:19.031605 DATLAT Default: 0xa
1980 13:40:19.031691 0, 0xFFFF, sum = 0
1981 13:40:19.034991 1, 0xFFFF, sum = 0
1982 13:40:19.035092 2, 0xFFFF, sum = 0
1983 13:40:19.038045 3, 0xFFFF, sum = 0
1984 13:40:19.038149 4, 0xFFFF, sum = 0
1985 13:40:19.041436 5, 0xFFFF, sum = 0
1986 13:40:19.041529 6, 0xFFFF, sum = 0
1987 13:40:19.044485 7, 0xFFFF, sum = 0
1988 13:40:19.044571 8, 0xFFFF, sum = 0
1989 13:40:19.047928 9, 0x0, sum = 1
1990 13:40:19.048022 10, 0x0, sum = 2
1991 13:40:19.051574 11, 0x0, sum = 3
1992 13:40:19.051662 12, 0x0, sum = 4
1993 13:40:19.054699 best_step = 10
1994 13:40:19.054782
1995 13:40:19.054845 ==
1996 13:40:19.058139 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 13:40:19.061739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 13:40:19.061828 ==
1999 13:40:19.061894 RX Vref Scan: 0
2000 13:40:19.061954
2001 13:40:19.064963 RX Vref 0 -> 0, step: 1
2002 13:40:19.065067
2003 13:40:19.068485 RX Delay -95 -> 252, step: 8
2004 13:40:19.071621 iDelay=201, Bit 0, Center 80 (-31 ~ 192) 224
2005 13:40:19.078680 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2006 13:40:19.081545 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2007 13:40:19.085485 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2008 13:40:19.088804 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2009 13:40:19.091665 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2010 13:40:19.094912 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2011 13:40:19.101991 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2012 13:40:19.105442 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2013 13:40:19.108387 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2014 13:40:19.111975 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2015 13:40:19.115747 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2016 13:40:19.122093 iDelay=201, Bit 12, Center 84 (-31 ~ 200) 232
2017 13:40:19.125746 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2018 13:40:19.128827 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2019 13:40:19.132032 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2020 13:40:19.132123 ==
2021 13:40:19.134991 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 13:40:19.142138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 13:40:19.142257 ==
2024 13:40:19.142323 DQS Delay:
2025 13:40:19.142381 DQS0 = 0, DQS1 = 0
2026 13:40:19.145143 DQM Delay:
2027 13:40:19.145222 DQM0 = 79, DQM1 = 76
2028 13:40:19.148914 DQ Delay:
2029 13:40:19.152309 DQ0 =80, DQ1 =76, DQ2 =68, DQ3 =80
2030 13:40:19.152389 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2031 13:40:19.155582 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2032 13:40:19.158759 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2033 13:40:19.162567
2034 13:40:19.162649
2035 13:40:19.169124 [DQSOSCAuto] RK1, (LSB)MR18= 0x232f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
2036 13:40:19.172200 CH1 RK1: MR19=606, MR18=232F
2037 13:40:19.178920 CH1_RK1: MR19=0x606, MR18=0x232F, DQSOSC=397, MR23=63, INC=93, DEC=62
2038 13:40:19.179033 [RxdqsGatingPostProcess] freq 800
2039 13:40:19.185705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 13:40:19.189411 Pre-setting of DQS Precalculation
2041 13:40:19.192418 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 13:40:19.202451 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 13:40:19.208851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 13:40:19.209021
2045 13:40:19.209103
2046 13:40:19.212339 [Calibration Summary] 1600 Mbps
2047 13:40:19.212426 CH 0, Rank 0
2048 13:40:19.215704 SW Impedance : PASS
2049 13:40:19.215818 DUTY Scan : NO K
2050 13:40:19.219236 ZQ Calibration : PASS
2051 13:40:19.222803 Jitter Meter : NO K
2052 13:40:19.222897 CBT Training : PASS
2053 13:40:19.225651 Write leveling : PASS
2054 13:40:19.229314 RX DQS gating : PASS
2055 13:40:19.229402 RX DQ/DQS(RDDQC) : PASS
2056 13:40:19.232803 TX DQ/DQS : PASS
2057 13:40:19.235919 RX DATLAT : PASS
2058 13:40:19.236033 RX DQ/DQS(Engine): PASS
2059 13:40:19.239492 TX OE : NO K
2060 13:40:19.239578 All Pass.
2061 13:40:19.239643
2062 13:40:19.242511 CH 0, Rank 1
2063 13:40:19.242584 SW Impedance : PASS
2064 13:40:19.246049 DUTY Scan : NO K
2065 13:40:19.246148 ZQ Calibration : PASS
2066 13:40:19.249119 Jitter Meter : NO K
2067 13:40:19.252749 CBT Training : PASS
2068 13:40:19.252832 Write leveling : PASS
2069 13:40:19.255855 RX DQS gating : PASS
2070 13:40:19.259161 RX DQ/DQS(RDDQC) : PASS
2071 13:40:19.259243 TX DQ/DQS : PASS
2072 13:40:19.262634 RX DATLAT : PASS
2073 13:40:19.266383 RX DQ/DQS(Engine): PASS
2074 13:40:19.266471 TX OE : NO K
2075 13:40:19.269396 All Pass.
2076 13:40:19.269499
2077 13:40:19.269567 CH 1, Rank 0
2078 13:40:19.273083 SW Impedance : PASS
2079 13:40:19.273181 DUTY Scan : NO K
2080 13:40:19.276204 ZQ Calibration : PASS
2081 13:40:19.276288 Jitter Meter : NO K
2082 13:40:19.279791 CBT Training : PASS
2083 13:40:19.283521 Write leveling : PASS
2084 13:40:19.283618 RX DQS gating : PASS
2085 13:40:19.286511 RX DQ/DQS(RDDQC) : PASS
2086 13:40:19.289893 TX DQ/DQS : PASS
2087 13:40:19.289978 RX DATLAT : PASS
2088 13:40:19.293102 RX DQ/DQS(Engine): PASS
2089 13:40:19.296727 TX OE : NO K
2090 13:40:19.296818 All Pass.
2091 13:40:19.296882
2092 13:40:19.296942 CH 1, Rank 1
2093 13:40:19.300206 SW Impedance : PASS
2094 13:40:19.303418 DUTY Scan : NO K
2095 13:40:19.303508 ZQ Calibration : PASS
2096 13:40:19.306924 Jitter Meter : NO K
2097 13:40:19.307013 CBT Training : PASS
2098 13:40:19.310151 Write leveling : PASS
2099 13:40:19.313316 RX DQS gating : PASS
2100 13:40:19.313407 RX DQ/DQS(RDDQC) : PASS
2101 13:40:19.316718 TX DQ/DQS : PASS
2102 13:40:19.320117 RX DATLAT : PASS
2103 13:40:19.320226 RX DQ/DQS(Engine): PASS
2104 13:40:19.323748 TX OE : NO K
2105 13:40:19.323836 All Pass.
2106 13:40:19.323901
2107 13:40:19.326749 DramC Write-DBI off
2108 13:40:19.330289 PER_BANK_REFRESH: Hybrid Mode
2109 13:40:19.330379 TX_TRACKING: ON
2110 13:40:19.333709 [GetDramInforAfterCalByMRR] Vendor 6.
2111 13:40:19.336629 [GetDramInforAfterCalByMRR] Revision 606.
2112 13:40:19.340218 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 13:40:19.343859 MR0 0x3b3b
2114 13:40:19.343967 MR8 0x5151
2115 13:40:19.346769 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 13:40:19.346853
2117 13:40:19.346918 MR0 0x3b3b
2118 13:40:19.350598 MR8 0x5151
2119 13:40:19.353493 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 13:40:19.353578
2121 13:40:19.360450 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 13:40:19.363594 [FAST_K] Save calibration result to emmc
2123 13:40:19.370475 [FAST_K] Save calibration result to emmc
2124 13:40:19.370593 dram_init: config_dvfs: 1
2125 13:40:19.373929 dramc_set_vcore_voltage set vcore to 662500
2126 13:40:19.377219 Read voltage for 1200, 2
2127 13:40:19.377310 Vio18 = 0
2128 13:40:19.380829 Vcore = 662500
2129 13:40:19.380943 Vdram = 0
2130 13:40:19.381030 Vddq = 0
2131 13:40:19.383804 Vmddr = 0
2132 13:40:19.387258 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 13:40:19.394017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 13:40:19.394133 MEM_TYPE=3, freq_sel=15
2135 13:40:19.397843 sv_algorithm_assistance_LP4_1600
2136 13:40:19.400835 ============ PULL DRAM RESETB DOWN ============
2137 13:40:19.407515 ========== PULL DRAM RESETB DOWN end =========
2138 13:40:19.410983 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 13:40:19.414172 ===================================
2140 13:40:19.417297 LPDDR4 DRAM CONFIGURATION
2141 13:40:19.420929 ===================================
2142 13:40:19.421089 EX_ROW_EN[0] = 0x0
2143 13:40:19.424251 EX_ROW_EN[1] = 0x0
2144 13:40:19.424329 LP4Y_EN = 0x0
2145 13:40:19.427336 WORK_FSP = 0x0
2146 13:40:19.427427 WL = 0x4
2147 13:40:19.430615 RL = 0x4
2148 13:40:19.434062 BL = 0x2
2149 13:40:19.434156 RPST = 0x0
2150 13:40:19.437265 RD_PRE = 0x0
2151 13:40:19.437353 WR_PRE = 0x1
2152 13:40:19.441079 WR_PST = 0x0
2153 13:40:19.441171 DBI_WR = 0x0
2154 13:40:19.444090 DBI_RD = 0x0
2155 13:40:19.444173 OTF = 0x1
2156 13:40:19.447612 ===================================
2157 13:40:19.450776 ===================================
2158 13:40:19.454592 ANA top config
2159 13:40:19.454686 ===================================
2160 13:40:19.457484 DLL_ASYNC_EN = 0
2161 13:40:19.461238 ALL_SLAVE_EN = 0
2162 13:40:19.464393 NEW_RANK_MODE = 1
2163 13:40:19.467739 DLL_IDLE_MODE = 1
2164 13:40:19.467833 LP45_APHY_COMB_EN = 1
2165 13:40:19.471563 TX_ODT_DIS = 1
2166 13:40:19.474526 NEW_8X_MODE = 1
2167 13:40:19.477633 ===================================
2168 13:40:19.481155 ===================================
2169 13:40:19.484632 data_rate = 2400
2170 13:40:19.487852 CKR = 1
2171 13:40:19.487937 DQ_P2S_RATIO = 8
2172 13:40:19.491150 ===================================
2173 13:40:19.494849 CA_P2S_RATIO = 8
2174 13:40:19.497896 DQ_CA_OPEN = 0
2175 13:40:19.501575 DQ_SEMI_OPEN = 0
2176 13:40:19.504539 CA_SEMI_OPEN = 0
2177 13:40:19.504626 CA_FULL_RATE = 0
2178 13:40:19.508456 DQ_CKDIV4_EN = 0
2179 13:40:19.511896 CA_CKDIV4_EN = 0
2180 13:40:19.514872 CA_PREDIV_EN = 0
2181 13:40:19.518438 PH8_DLY = 17
2182 13:40:19.521613 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 13:40:19.521706 DQ_AAMCK_DIV = 4
2184 13:40:19.524700 CA_AAMCK_DIV = 4
2185 13:40:19.528349 CA_ADMCK_DIV = 4
2186 13:40:19.531860 DQ_TRACK_CA_EN = 0
2187 13:40:19.534775 CA_PICK = 1200
2188 13:40:19.538502 CA_MCKIO = 1200
2189 13:40:19.538593 MCKIO_SEMI = 0
2190 13:40:19.541562 PLL_FREQ = 2366
2191 13:40:19.545104 DQ_UI_PI_RATIO = 32
2192 13:40:19.548186 CA_UI_PI_RATIO = 0
2193 13:40:19.551804 ===================================
2194 13:40:19.554968 ===================================
2195 13:40:19.558385 memory_type:LPDDR4
2196 13:40:19.558484 GP_NUM : 10
2197 13:40:19.561742 SRAM_EN : 1
2198 13:40:19.565336 MD32_EN : 0
2199 13:40:19.565420 ===================================
2200 13:40:19.568472 [ANA_INIT] >>>>>>>>>>>>>>
2201 13:40:19.571952 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 13:40:19.575175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 13:40:19.578667 ===================================
2204 13:40:19.581771 data_rate = 2400,PCW = 0X5b00
2205 13:40:19.585460 ===================================
2206 13:40:19.588432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 13:40:19.595079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 13:40:19.598356 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 13:40:19.605337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 13:40:19.609076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 13:40:19.612058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 13:40:19.612137 [ANA_INIT] flow start
2213 13:40:19.615595 [ANA_INIT] PLL >>>>>>>>
2214 13:40:19.618705 [ANA_INIT] PLL <<<<<<<<
2215 13:40:19.618781 [ANA_INIT] MIDPI >>>>>>>>
2216 13:40:19.622438 [ANA_INIT] MIDPI <<<<<<<<
2217 13:40:19.625471 [ANA_INIT] DLL >>>>>>>>
2218 13:40:19.625578 [ANA_INIT] DLL <<<<<<<<
2219 13:40:19.629052 [ANA_INIT] flow end
2220 13:40:19.632238 ============ LP4 DIFF to SE enter ============
2221 13:40:19.635819 ============ LP4 DIFF to SE exit ============
2222 13:40:19.638789 [ANA_INIT] <<<<<<<<<<<<<
2223 13:40:19.642470 [Flow] Enable top DCM control >>>>>
2224 13:40:19.645848 [Flow] Enable top DCM control <<<<<
2225 13:40:19.649183 Enable DLL master slave shuffle
2226 13:40:19.655774 ==============================================================
2227 13:40:19.655884 Gating Mode config
2228 13:40:19.662469 ==============================================================
2229 13:40:19.662575 Config description:
2230 13:40:19.672641 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 13:40:19.679227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 13:40:19.685678 SELPH_MODE 0: By rank 1: By Phase
2233 13:40:19.689314 ==============================================================
2234 13:40:19.692373 GAT_TRACK_EN = 1
2235 13:40:19.695936 RX_GATING_MODE = 2
2236 13:40:19.699104 RX_GATING_TRACK_MODE = 2
2237 13:40:19.702436 SELPH_MODE = 1
2238 13:40:19.706151 PICG_EARLY_EN = 1
2239 13:40:19.709452 VALID_LAT_VALUE = 1
2240 13:40:19.712907 ==============================================================
2241 13:40:19.716308 Enter into Gating configuration >>>>
2242 13:40:19.719337 Exit from Gating configuration <<<<
2243 13:40:19.722617 Enter into DVFS_PRE_config >>>>>
2244 13:40:19.732899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 13:40:19.736478 Exit from DVFS_PRE_config <<<<<
2246 13:40:19.739473 Enter into PICG configuration >>>>
2247 13:40:19.742660 Exit from PICG configuration <<<<
2248 13:40:19.746098 [RX_INPUT] configuration >>>>>
2249 13:40:19.749856 [RX_INPUT] configuration <<<<<
2250 13:40:19.753132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 13:40:19.759534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 13:40:19.766240 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 13:40:19.773326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 13:40:19.779881 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 13:40:19.783545 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 13:40:19.790155 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 13:40:19.793204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 13:40:19.796600 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 13:40:19.800057 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 13:40:19.803045 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 13:40:19.809741 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 13:40:19.813392 ===================================
2263 13:40:19.816842 LPDDR4 DRAM CONFIGURATION
2264 13:40:19.820219 ===================================
2265 13:40:19.820360 EX_ROW_EN[0] = 0x0
2266 13:40:19.823473 EX_ROW_EN[1] = 0x0
2267 13:40:19.823556 LP4Y_EN = 0x0
2268 13:40:19.826531 WORK_FSP = 0x0
2269 13:40:19.826612 WL = 0x4
2270 13:40:19.830481 RL = 0x4
2271 13:40:19.830563 BL = 0x2
2272 13:40:19.833316 RPST = 0x0
2273 13:40:19.833383 RD_PRE = 0x0
2274 13:40:19.836382 WR_PRE = 0x1
2275 13:40:19.836449 WR_PST = 0x0
2276 13:40:19.840042 DBI_WR = 0x0
2277 13:40:19.840114 DBI_RD = 0x0
2278 13:40:19.843144 OTF = 0x1
2279 13:40:19.846809 ===================================
2280 13:40:19.849763 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 13:40:19.853424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 13:40:19.860083 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 13:40:19.863462 ===================================
2284 13:40:19.863552 LPDDR4 DRAM CONFIGURATION
2285 13:40:19.867026 ===================================
2286 13:40:19.870222 EX_ROW_EN[0] = 0x10
2287 13:40:19.873524 EX_ROW_EN[1] = 0x0
2288 13:40:19.873611 LP4Y_EN = 0x0
2289 13:40:19.876918 WORK_FSP = 0x0
2290 13:40:19.877059 WL = 0x4
2291 13:40:19.880640 RL = 0x4
2292 13:40:19.880731 BL = 0x2
2293 13:40:19.883599 RPST = 0x0
2294 13:40:19.883718 RD_PRE = 0x0
2295 13:40:19.887239 WR_PRE = 0x1
2296 13:40:19.887330 WR_PST = 0x0
2297 13:40:19.890112 DBI_WR = 0x0
2298 13:40:19.890196 DBI_RD = 0x0
2299 13:40:19.893899 OTF = 0x1
2300 13:40:19.897271 ===================================
2301 13:40:19.900700 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 13:40:19.903511 ==
2303 13:40:19.907470 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 13:40:19.910788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 13:40:19.910884 ==
2306 13:40:19.913723 [Duty_Offset_Calibration]
2307 13:40:19.913808 B0:2 B1:-1 CA:1
2308 13:40:19.913870
2309 13:40:19.917305 [DutyScan_Calibration_Flow] k_type=0
2310 13:40:19.925848
2311 13:40:19.925963 ==CLK 0==
2312 13:40:19.928963 Final CLK duty delay cell = -4
2313 13:40:19.932937 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2314 13:40:19.936244 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2315 13:40:19.939160 [-4] AVG Duty = 4953%(X100)
2316 13:40:19.939252
2317 13:40:19.942416 CH0 CLK Duty spec in!! Max-Min= 156%
2318 13:40:19.945807 [DutyScan_Calibration_Flow] ====Done====
2319 13:40:19.945894
2320 13:40:19.949490 [DutyScan_Calibration_Flow] k_type=1
2321 13:40:19.964682
2322 13:40:19.964827 ==DQS 0 ==
2323 13:40:19.968323 Final DQS duty delay cell = 0
2324 13:40:19.971597 [0] MAX Duty = 5125%(X100), DQS PI = 48
2325 13:40:19.975171 [0] MIN Duty = 5000%(X100), DQS PI = 12
2326 13:40:19.975272 [0] AVG Duty = 5062%(X100)
2327 13:40:19.978132
2328 13:40:19.978231 ==DQS 1 ==
2329 13:40:19.981652 Final DQS duty delay cell = -4
2330 13:40:19.984658 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2331 13:40:19.988008 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2332 13:40:19.991628 [-4] AVG Duty = 5062%(X100)
2333 13:40:19.991724
2334 13:40:19.994779 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2335 13:40:19.994865
2336 13:40:19.998516 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2337 13:40:20.001519 [DutyScan_Calibration_Flow] ====Done====
2338 13:40:20.001608
2339 13:40:20.005115 [DutyScan_Calibration_Flow] k_type=3
2340 13:40:20.021698
2341 13:40:20.021846 ==DQM 0 ==
2342 13:40:20.025214 Final DQM duty delay cell = 0
2343 13:40:20.028302 [0] MAX Duty = 5000%(X100), DQS PI = 54
2344 13:40:20.032221 [0] MIN Duty = 4875%(X100), DQS PI = 4
2345 13:40:20.032326 [0] AVG Duty = 4937%(X100)
2346 13:40:20.035050
2347 13:40:20.035142 ==DQM 1 ==
2348 13:40:20.038094 Final DQM duty delay cell = 0
2349 13:40:20.041464 [0] MAX Duty = 5156%(X100), DQS PI = 62
2350 13:40:20.044651 [0] MIN Duty = 5000%(X100), DQS PI = 8
2351 13:40:20.044782 [0] AVG Duty = 5078%(X100)
2352 13:40:20.048575
2353 13:40:20.051467 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2354 13:40:20.051547
2355 13:40:20.055107 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2356 13:40:20.058273 [DutyScan_Calibration_Flow] ====Done====
2357 13:40:20.058439
2358 13:40:20.061365 [DutyScan_Calibration_Flow] k_type=2
2359 13:40:20.076999
2360 13:40:20.077158 ==DQ 0 ==
2361 13:40:20.080516 Final DQ duty delay cell = -4
2362 13:40:20.083756 [-4] MAX Duty = 5031%(X100), DQS PI = 46
2363 13:40:20.087308 [-4] MIN Duty = 4844%(X100), DQS PI = 12
2364 13:40:20.090548 [-4] AVG Duty = 4937%(X100)
2365 13:40:20.090665
2366 13:40:20.090768 ==DQ 1 ==
2367 13:40:20.094276 Final DQ duty delay cell = 0
2368 13:40:20.097267 [0] MAX Duty = 5031%(X100), DQS PI = 18
2369 13:40:20.100914 [0] MIN Duty = 4907%(X100), DQS PI = 44
2370 13:40:20.101061 [0] AVG Duty = 4969%(X100)
2371 13:40:20.103971
2372 13:40:20.107642 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2373 13:40:20.107736
2374 13:40:20.110645 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2375 13:40:20.114522 [DutyScan_Calibration_Flow] ====Done====
2376 13:40:20.114635 ==
2377 13:40:20.117315 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 13:40:20.120953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 13:40:20.121074 ==
2380 13:40:20.123989 [Duty_Offset_Calibration]
2381 13:40:20.124071 B0:1 B1:1 CA:2
2382 13:40:20.124135
2383 13:40:20.127339 [DutyScan_Calibration_Flow] k_type=0
2384 13:40:20.137843
2385 13:40:20.137985 ==CLK 0==
2386 13:40:20.140857 Final CLK duty delay cell = 0
2387 13:40:20.144396 [0] MAX Duty = 5156%(X100), DQS PI = 24
2388 13:40:20.147373 [0] MIN Duty = 4938%(X100), DQS PI = 42
2389 13:40:20.147461 [0] AVG Duty = 5047%(X100)
2390 13:40:20.150902
2391 13:40:20.154163 CH1 CLK Duty spec in!! Max-Min= 218%
2392 13:40:20.157453 [DutyScan_Calibration_Flow] ====Done====
2393 13:40:20.157556
2394 13:40:20.160986 [DutyScan_Calibration_Flow] k_type=1
2395 13:40:20.177031
2396 13:40:20.177179 ==DQS 0 ==
2397 13:40:20.180104 Final DQS duty delay cell = 0
2398 13:40:20.183571 [0] MAX Duty = 5031%(X100), DQS PI = 18
2399 13:40:20.187125 [0] MIN Duty = 4844%(X100), DQS PI = 48
2400 13:40:20.187223 [0] AVG Duty = 4937%(X100)
2401 13:40:20.190592
2402 13:40:20.190673 ==DQS 1 ==
2403 13:40:20.194184 Final DQS duty delay cell = 0
2404 13:40:20.196929 [0] MAX Duty = 5031%(X100), DQS PI = 20
2405 13:40:20.200225 [0] MIN Duty = 4875%(X100), DQS PI = 16
2406 13:40:20.200343 [0] AVG Duty = 4953%(X100)
2407 13:40:20.203708
2408 13:40:20.206808 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2409 13:40:20.206891
2410 13:40:20.210477 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2411 13:40:20.213614 [DutyScan_Calibration_Flow] ====Done====
2412 13:40:20.213701
2413 13:40:20.217181 [DutyScan_Calibration_Flow] k_type=3
2414 13:40:20.233656
2415 13:40:20.233807 ==DQM 0 ==
2416 13:40:20.237203 Final DQM duty delay cell = 0
2417 13:40:20.239949 [0] MAX Duty = 5093%(X100), DQS PI = 16
2418 13:40:20.243991 [0] MIN Duty = 4844%(X100), DQS PI = 48
2419 13:40:20.244087 [0] AVG Duty = 4968%(X100)
2420 13:40:20.246785
2421 13:40:20.246870 ==DQM 1 ==
2422 13:40:20.250241 Final DQM duty delay cell = 0
2423 13:40:20.253677 [0] MAX Duty = 5156%(X100), DQS PI = 62
2424 13:40:20.257321 [0] MIN Duty = 4938%(X100), DQS PI = 22
2425 13:40:20.257412 [0] AVG Duty = 5047%(X100)
2426 13:40:20.260144
2427 13:40:20.263570 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2428 13:40:20.263658
2429 13:40:20.267193 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2430 13:40:20.270432 [DutyScan_Calibration_Flow] ====Done====
2431 13:40:20.270521
2432 13:40:20.273336 [DutyScan_Calibration_Flow] k_type=2
2433 13:40:20.290433
2434 13:40:20.290582 ==DQ 0 ==
2435 13:40:20.293289 Final DQ duty delay cell = 0
2436 13:40:20.296732 [0] MAX Duty = 5093%(X100), DQS PI = 18
2437 13:40:20.299675 [0] MIN Duty = 4938%(X100), DQS PI = 50
2438 13:40:20.299796 [0] AVG Duty = 5015%(X100)
2439 13:40:20.303408
2440 13:40:20.303506 ==DQ 1 ==
2441 13:40:20.306664 Final DQ duty delay cell = 0
2442 13:40:20.309957 [0] MAX Duty = 5093%(X100), DQS PI = 10
2443 13:40:20.313559 [0] MIN Duty = 5000%(X100), DQS PI = 50
2444 13:40:20.313648 [0] AVG Duty = 5046%(X100)
2445 13:40:20.313713
2446 13:40:20.316616 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2447 13:40:20.316699
2448 13:40:20.320345 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2449 13:40:20.326899 [DutyScan_Calibration_Flow] ====Done====
2450 13:40:20.330046 nWR fixed to 30
2451 13:40:20.330151 [ModeRegInit_LP4] CH0 RK0
2452 13:40:20.333631 [ModeRegInit_LP4] CH0 RK1
2453 13:40:20.337290 [ModeRegInit_LP4] CH1 RK0
2454 13:40:20.337393 [ModeRegInit_LP4] CH1 RK1
2455 13:40:20.339972 match AC timing 7
2456 13:40:20.343623 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 13:40:20.347147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 13:40:20.353801 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 13:40:20.356960 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 13:40:20.363582 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 13:40:20.363700 ==
2462 13:40:20.367476 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 13:40:20.370345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 13:40:20.370435 ==
2465 13:40:20.373761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 13:40:20.380349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2467 13:40:20.389734 [CA 0] Center 40 (10~71) winsize 62
2468 13:40:20.393320 [CA 1] Center 39 (9~70) winsize 62
2469 13:40:20.396888 [CA 2] Center 36 (6~67) winsize 62
2470 13:40:20.399833 [CA 3] Center 36 (5~67) winsize 63
2471 13:40:20.403204 [CA 4] Center 35 (5~65) winsize 61
2472 13:40:20.406729 [CA 5] Center 34 (4~64) winsize 61
2473 13:40:20.406827
2474 13:40:20.410410 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2475 13:40:20.410503
2476 13:40:20.413408 [CATrainingPosCal] consider 1 rank data
2477 13:40:20.416708 u2DelayCellTimex100 = 270/100 ps
2478 13:40:20.420260 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2479 13:40:20.423724 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2480 13:40:20.430145 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2481 13:40:20.433579 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2482 13:40:20.437331 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2483 13:40:20.440451 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2484 13:40:20.440548
2485 13:40:20.443441 CA PerBit enable=1, Macro0, CA PI delay=34
2486 13:40:20.443524
2487 13:40:20.447161 [CBTSetCACLKResult] CA Dly = 34
2488 13:40:20.447248 CS Dly: 7 (0~38)
2489 13:40:20.447313 ==
2490 13:40:20.450793 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 13:40:20.457395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 13:40:20.457516 ==
2493 13:40:20.460353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 13:40:20.467269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 13:40:20.475652 [CA 0] Center 39 (9~70) winsize 62
2496 13:40:20.479337 [CA 1] Center 40 (10~70) winsize 61
2497 13:40:20.482772 [CA 2] Center 36 (6~67) winsize 62
2498 13:40:20.486328 [CA 3] Center 36 (5~67) winsize 63
2499 13:40:20.489140 [CA 4] Center 34 (4~65) winsize 62
2500 13:40:20.492890 [CA 5] Center 34 (4~64) winsize 61
2501 13:40:20.493031
2502 13:40:20.496107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 13:40:20.496194
2504 13:40:20.499037 [CATrainingPosCal] consider 2 rank data
2505 13:40:20.502665 u2DelayCellTimex100 = 270/100 ps
2506 13:40:20.506152 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 13:40:20.509130 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 13:40:20.516269 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2509 13:40:20.519258 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2510 13:40:20.522734 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2511 13:40:20.525959 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2512 13:40:20.526052
2513 13:40:20.529568 CA PerBit enable=1, Macro0, CA PI delay=34
2514 13:40:20.529666
2515 13:40:20.532600 [CBTSetCACLKResult] CA Dly = 34
2516 13:40:20.532684 CS Dly: 8 (0~41)
2517 13:40:20.532748
2518 13:40:20.536295 ----->DramcWriteLeveling(PI) begin...
2519 13:40:20.539339 ==
2520 13:40:20.539426 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 13:40:20.546028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 13:40:20.546140 ==
2523 13:40:20.549616 Write leveling (Byte 0): 31 => 31
2524 13:40:20.552712 Write leveling (Byte 1): 28 => 28
2525 13:40:20.556250 DramcWriteLeveling(PI) end<-----
2526 13:40:20.556345
2527 13:40:20.556410 ==
2528 13:40:20.559199 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 13:40:20.562874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 13:40:20.562959 ==
2531 13:40:20.566580 [Gating] SW mode calibration
2532 13:40:20.572844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 13:40:20.576107 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 13:40:20.582784 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 13:40:20.586493 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2536 13:40:20.589308 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2537 13:40:20.596420 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 13:40:20.599622 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 13:40:20.602910 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 13:40:20.609857 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 13:40:20.613336 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 13:40:20.616333 1 0 0 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (1 0)
2543 13:40:20.623273 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2544 13:40:20.626469 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 13:40:20.629485 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 13:40:20.633153 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 13:40:20.640159 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 13:40:20.643108 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 13:40:20.646625 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 13:40:20.653314 1 1 0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
2551 13:40:20.657139 1 1 4 | B1->B0 | 3a3a 4545 | 0 0 | (1 1) (0 0)
2552 13:40:20.660056 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 13:40:20.667042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 13:40:20.669771 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 13:40:20.673477 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 13:40:20.679852 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 13:40:20.683307 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 13:40:20.686961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2559 13:40:20.693795 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2560 13:40:20.696712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 13:40:20.700179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 13:40:20.703553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 13:40:20.710552 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 13:40:20.713745 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 13:40:20.717001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 13:40:20.723760 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 13:40:20.726961 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 13:40:20.730559 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 13:40:20.737317 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 13:40:20.740431 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 13:40:20.743924 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 13:40:20.750439 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 13:40:20.754037 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 13:40:20.757665 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2575 13:40:20.760501 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2576 13:40:20.764267 Total UI for P1: 0, mck2ui 16
2577 13:40:20.767270 best dqsien dly found for B0: ( 1, 4, 0)
2578 13:40:20.774099 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 13:40:20.774221 Total UI for P1: 0, mck2ui 16
2580 13:40:20.780612 best dqsien dly found for B1: ( 1, 4, 4)
2581 13:40:20.783956 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2582 13:40:20.787434 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2583 13:40:20.787531
2584 13:40:20.790956 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 13:40:20.794103 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2586 13:40:20.797693 [Gating] SW calibration Done
2587 13:40:20.797785 ==
2588 13:40:20.800693 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 13:40:20.804319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 13:40:20.804417 ==
2591 13:40:20.807954 RX Vref Scan: 0
2592 13:40:20.808042
2593 13:40:20.808131 RX Vref 0 -> 0, step: 1
2594 13:40:20.808211
2595 13:40:20.811191 RX Delay -40 -> 252, step: 8
2596 13:40:20.814696 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2597 13:40:20.817554 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2598 13:40:20.824375 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2599 13:40:20.827623 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2600 13:40:20.830826 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2601 13:40:20.834409 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2602 13:40:20.837939 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2603 13:40:20.844576 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2604 13:40:20.847675 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2605 13:40:20.851386 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2606 13:40:20.854371 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2607 13:40:20.858111 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2608 13:40:20.864835 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2609 13:40:20.867781 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2610 13:40:20.871547 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2611 13:40:20.874401 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2612 13:40:20.874487 ==
2613 13:40:20.878116 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 13:40:20.881170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 13:40:20.884601 ==
2616 13:40:20.884684 DQS Delay:
2617 13:40:20.884759 DQS0 = 0, DQS1 = 0
2618 13:40:20.888289 DQM Delay:
2619 13:40:20.888374 DQM0 = 116, DQM1 = 107
2620 13:40:20.891734 DQ Delay:
2621 13:40:20.894516 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2622 13:40:20.898251 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2623 13:40:20.901482 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2624 13:40:20.904882 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2625 13:40:20.904967
2626 13:40:20.905071
2627 13:40:20.905129 ==
2628 13:40:20.907984 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 13:40:20.911713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 13:40:20.911788 ==
2631 13:40:20.911846
2632 13:40:20.911901
2633 13:40:20.914914 TX Vref Scan disable
2634 13:40:20.918343 == TX Byte 0 ==
2635 13:40:20.921687 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2636 13:40:20.925210 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2637 13:40:20.925296 == TX Byte 1 ==
2638 13:40:20.932127 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2639 13:40:20.934875 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2640 13:40:20.934972 ==
2641 13:40:20.938235 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 13:40:20.941691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 13:40:20.941784 ==
2644 13:40:20.955241 TX Vref=22, minBit 1, minWin=24, winSum=419
2645 13:40:20.958014 TX Vref=24, minBit 1, minWin=25, winSum=423
2646 13:40:20.961731 TX Vref=26, minBit 4, minWin=25, winSum=427
2647 13:40:20.964877 TX Vref=28, minBit 1, minWin=26, winSum=433
2648 13:40:20.968115 TX Vref=30, minBit 1, minWin=27, winSum=438
2649 13:40:20.971482 TX Vref=32, minBit 4, minWin=26, winSum=434
2650 13:40:20.978288 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
2651 13:40:20.978414
2652 13:40:20.981984 Final TX Range 1 Vref 30
2653 13:40:20.982070
2654 13:40:20.982144 ==
2655 13:40:20.984897 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 13:40:20.988560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 13:40:20.988647 ==
2658 13:40:20.988711
2659 13:40:20.988769
2660 13:40:20.992012 TX Vref Scan disable
2661 13:40:20.995065 == TX Byte 0 ==
2662 13:40:20.998507 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2663 13:40:21.001491 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2664 13:40:21.005040 == TX Byte 1 ==
2665 13:40:21.008323 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2666 13:40:21.011907 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2667 13:40:21.012003
2668 13:40:21.014979 [DATLAT]
2669 13:40:21.015068 Freq=1200, CH0 RK0
2670 13:40:21.015133
2671 13:40:21.018794 DATLAT Default: 0xd
2672 13:40:21.018879 0, 0xFFFF, sum = 0
2673 13:40:21.021872 1, 0xFFFF, sum = 0
2674 13:40:21.021968 2, 0xFFFF, sum = 0
2675 13:40:21.025677 3, 0xFFFF, sum = 0
2676 13:40:21.025771 4, 0xFFFF, sum = 0
2677 13:40:21.028678 5, 0xFFFF, sum = 0
2678 13:40:21.028829 6, 0xFFFF, sum = 0
2679 13:40:21.032147 7, 0xFFFF, sum = 0
2680 13:40:21.032249 8, 0xFFFF, sum = 0
2681 13:40:21.035178 9, 0xFFFF, sum = 0
2682 13:40:21.035272 10, 0xFFFF, sum = 0
2683 13:40:21.038895 11, 0xFFFF, sum = 0
2684 13:40:21.038980 12, 0x0, sum = 1
2685 13:40:21.041847 13, 0x0, sum = 2
2686 13:40:21.041928 14, 0x0, sum = 3
2687 13:40:21.045612 15, 0x0, sum = 4
2688 13:40:21.045702 best_step = 13
2689 13:40:21.045765
2690 13:40:21.045822 ==
2691 13:40:21.048509 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 13:40:21.055434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 13:40:21.055547 ==
2694 13:40:21.055621 RX Vref Scan: 1
2695 13:40:21.055679
2696 13:40:21.058917 Set Vref Range= 32 -> 127
2697 13:40:21.059068
2698 13:40:21.062036 RX Vref 32 -> 127, step: 1
2699 13:40:21.062126
2700 13:40:21.062189 RX Delay -21 -> 252, step: 4
2701 13:40:21.062331
2702 13:40:21.065706 Set Vref, RX VrefLevel [Byte0]: 32
2703 13:40:21.068669 [Byte1]: 32
2704 13:40:21.073321
2705 13:40:21.073432 Set Vref, RX VrefLevel [Byte0]: 33
2706 13:40:21.076511 [Byte1]: 33
2707 13:40:21.080761
2708 13:40:21.080920 Set Vref, RX VrefLevel [Byte0]: 34
2709 13:40:21.084433 [Byte1]: 34
2710 13:40:21.088755
2711 13:40:21.088869 Set Vref, RX VrefLevel [Byte0]: 35
2712 13:40:21.092479 [Byte1]: 35
2713 13:40:21.096920
2714 13:40:21.097075 Set Vref, RX VrefLevel [Byte0]: 36
2715 13:40:21.100161 [Byte1]: 36
2716 13:40:21.104688
2717 13:40:21.104817 Set Vref, RX VrefLevel [Byte0]: 37
2718 13:40:21.108373 [Byte1]: 37
2719 13:40:21.112697
2720 13:40:21.112784 Set Vref, RX VrefLevel [Byte0]: 38
2721 13:40:21.116376 [Byte1]: 38
2722 13:40:21.120538
2723 13:40:21.120655 Set Vref, RX VrefLevel [Byte0]: 39
2724 13:40:21.124077 [Byte1]: 39
2725 13:40:21.128454
2726 13:40:21.128587 Set Vref, RX VrefLevel [Byte0]: 40
2727 13:40:21.132366 [Byte1]: 40
2728 13:40:21.136435
2729 13:40:21.136563 Set Vref, RX VrefLevel [Byte0]: 41
2730 13:40:21.139667 [Byte1]: 41
2731 13:40:21.144412
2732 13:40:21.144542 Set Vref, RX VrefLevel [Byte0]: 42
2733 13:40:21.148132 [Byte1]: 42
2734 13:40:21.152396
2735 13:40:21.152497 Set Vref, RX VrefLevel [Byte0]: 43
2736 13:40:21.155512 [Byte1]: 43
2737 13:40:21.160346
2738 13:40:21.160445 Set Vref, RX VrefLevel [Byte0]: 44
2739 13:40:21.163436 [Byte1]: 44
2740 13:40:21.168044
2741 13:40:21.168146 Set Vref, RX VrefLevel [Byte0]: 45
2742 13:40:21.171751 [Byte1]: 45
2743 13:40:21.175865
2744 13:40:21.175969 Set Vref, RX VrefLevel [Byte0]: 46
2745 13:40:21.179850 [Byte1]: 46
2746 13:40:21.183872
2747 13:40:21.183980 Set Vref, RX VrefLevel [Byte0]: 47
2748 13:40:21.187446 [Byte1]: 47
2749 13:40:21.192247
2750 13:40:21.192356 Set Vref, RX VrefLevel [Byte0]: 48
2751 13:40:21.195186 [Byte1]: 48
2752 13:40:21.200139
2753 13:40:21.200240 Set Vref, RX VrefLevel [Byte0]: 49
2754 13:40:21.203162 [Byte1]: 49
2755 13:40:21.207794
2756 13:40:21.207888 Set Vref, RX VrefLevel [Byte0]: 50
2757 13:40:21.211060 [Byte1]: 50
2758 13:40:21.215925
2759 13:40:21.216015 Set Vref, RX VrefLevel [Byte0]: 51
2760 13:40:21.219074 [Byte1]: 51
2761 13:40:21.224030
2762 13:40:21.224147 Set Vref, RX VrefLevel [Byte0]: 52
2763 13:40:21.226844 [Byte1]: 52
2764 13:40:21.231930
2765 13:40:21.232070 Set Vref, RX VrefLevel [Byte0]: 53
2766 13:40:21.235233 [Byte1]: 53
2767 13:40:21.239476
2768 13:40:21.239590 Set Vref, RX VrefLevel [Byte0]: 54
2769 13:40:21.242990 [Byte1]: 54
2770 13:40:21.247763
2771 13:40:21.247857 Set Vref, RX VrefLevel [Byte0]: 55
2772 13:40:21.251066 [Byte1]: 55
2773 13:40:21.255260
2774 13:40:21.255383 Set Vref, RX VrefLevel [Byte0]: 56
2775 13:40:21.259011 [Byte1]: 56
2776 13:40:21.263404
2777 13:40:21.263513 Set Vref, RX VrefLevel [Byte0]: 57
2778 13:40:21.266955 [Byte1]: 57
2779 13:40:21.271225
2780 13:40:21.271376 Set Vref, RX VrefLevel [Byte0]: 58
2781 13:40:21.274444 [Byte1]: 58
2782 13:40:21.279167
2783 13:40:21.279295 Set Vref, RX VrefLevel [Byte0]: 59
2784 13:40:21.282935 [Byte1]: 59
2785 13:40:21.287186
2786 13:40:21.287278 Set Vref, RX VrefLevel [Byte0]: 60
2787 13:40:21.290284 [Byte1]: 60
2788 13:40:21.294950
2789 13:40:21.295082 Set Vref, RX VrefLevel [Byte0]: 61
2790 13:40:21.298583 [Byte1]: 61
2791 13:40:21.303452
2792 13:40:21.303644 Set Vref, RX VrefLevel [Byte0]: 62
2793 13:40:21.306020 [Byte1]: 62
2794 13:40:21.311225
2795 13:40:21.311330 Set Vref, RX VrefLevel [Byte0]: 63
2796 13:40:21.314215 [Byte1]: 63
2797 13:40:21.318646
2798 13:40:21.318747 Set Vref, RX VrefLevel [Byte0]: 64
2799 13:40:21.322281 [Byte1]: 64
2800 13:40:21.326780
2801 13:40:21.326883 Set Vref, RX VrefLevel [Byte0]: 65
2802 13:40:21.330525 [Byte1]: 65
2803 13:40:21.334674
2804 13:40:21.334772 Set Vref, RX VrefLevel [Byte0]: 66
2805 13:40:21.338082 [Byte1]: 66
2806 13:40:21.342732
2807 13:40:21.342836 Set Vref, RX VrefLevel [Byte0]: 67
2808 13:40:21.345745 [Byte1]: 67
2809 13:40:21.350749
2810 13:40:21.350896 Set Vref, RX VrefLevel [Byte0]: 68
2811 13:40:21.353760 [Byte1]: 68
2812 13:40:21.358203
2813 13:40:21.358297 Final RX Vref Byte 0 = 55 to rank0
2814 13:40:21.361911 Final RX Vref Byte 1 = 51 to rank0
2815 13:40:21.365073 Final RX Vref Byte 0 = 55 to rank1
2816 13:40:21.368651 Final RX Vref Byte 1 = 51 to rank1==
2817 13:40:21.371605 Dram Type= 6, Freq= 0, CH_0, rank 0
2818 13:40:21.378240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 13:40:21.378385 ==
2820 13:40:21.378480 DQS Delay:
2821 13:40:21.378569 DQS0 = 0, DQS1 = 0
2822 13:40:21.381870 DQM Delay:
2823 13:40:21.381956 DQM0 = 114, DQM1 = 104
2824 13:40:21.384910 DQ Delay:
2825 13:40:21.388609 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112
2826 13:40:21.391843 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2827 13:40:21.394862 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2828 13:40:21.398113 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2829 13:40:21.398218
2830 13:40:21.398293
2831 13:40:21.405146 [DQSOSCAuto] RK0, (LSB)MR18= 0xef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2832 13:40:21.408441 CH0 RK0: MR19=403, MR18=EF
2833 13:40:21.415121 CH0_RK0: MR19=0x403, MR18=0xEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2834 13:40:21.415248
2835 13:40:21.418313 ----->DramcWriteLeveling(PI) begin...
2836 13:40:21.418421 ==
2837 13:40:21.421910 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 13:40:21.425478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 13:40:21.425607 ==
2840 13:40:21.428567 Write leveling (Byte 0): 34 => 34
2841 13:40:21.432125 Write leveling (Byte 1): 29 => 29
2842 13:40:21.435208 DramcWriteLeveling(PI) end<-----
2843 13:40:21.435307
2844 13:40:21.435370 ==
2845 13:40:21.438299 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 13:40:21.442144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 13:40:21.442230 ==
2848 13:40:21.445132 [Gating] SW mode calibration
2849 13:40:21.452284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2850 13:40:21.458527 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2851 13:40:21.461791 0 15 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2852 13:40:21.468932 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2853 13:40:21.472185 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 13:40:21.475256 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 13:40:21.478867 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 13:40:21.485478 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 13:40:21.489097 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2858 13:40:21.492555 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2859 13:40:21.499127 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2860 13:40:21.502238 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 13:40:21.505521 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 13:40:21.512419 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 13:40:21.515947 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 13:40:21.519385 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 13:40:21.526081 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2866 13:40:21.529379 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2867 13:40:21.532476 1 1 0 | B1->B0 | 2b2b 3c3c | 0 0 | (0 0) (0 0)
2868 13:40:21.536073 1 1 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2869 13:40:21.542764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 13:40:21.545886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 13:40:21.549582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 13:40:21.556264 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 13:40:21.559213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 13:40:21.563006 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 13:40:21.569443 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2876 13:40:21.572843 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 13:40:21.575941 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 13:40:21.582963 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 13:40:21.586166 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 13:40:21.589555 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 13:40:21.592834 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 13:40:21.599909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 13:40:21.603386 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 13:40:21.606236 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 13:40:21.613140 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 13:40:21.616797 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 13:40:21.619629 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 13:40:21.626648 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 13:40:21.629842 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 13:40:21.633468 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 13:40:21.639910 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2892 13:40:21.640027 Total UI for P1: 0, mck2ui 16
2893 13:40:21.643521 best dqsien dly found for B0: ( 1, 3, 28)
2894 13:40:21.649858 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 13:40:21.653403 Total UI for P1: 0, mck2ui 16
2896 13:40:21.656850 best dqsien dly found for B1: ( 1, 4, 0)
2897 13:40:21.659853 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2898 13:40:21.663645 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2899 13:40:21.663742
2900 13:40:21.666749 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2901 13:40:21.669698 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2902 13:40:21.673456 [Gating] SW calibration Done
2903 13:40:21.673567 ==
2904 13:40:21.676704 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 13:40:21.680139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 13:40:21.680273 ==
2907 13:40:21.683271 RX Vref Scan: 0
2908 13:40:21.683358
2909 13:40:21.683424 RX Vref 0 -> 0, step: 1
2910 13:40:21.683485
2911 13:40:21.686730 RX Delay -40 -> 252, step: 8
2912 13:40:21.690184 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2913 13:40:21.696765 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2914 13:40:21.700199 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2915 13:40:21.703335 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2916 13:40:21.706576 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2917 13:40:21.710202 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2918 13:40:21.716802 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2919 13:40:21.720558 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2920 13:40:21.723635 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2921 13:40:21.727215 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2922 13:40:21.730503 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2923 13:40:21.733956 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2924 13:40:21.740493 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 13:40:21.743624 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2926 13:40:21.746940 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2927 13:40:21.750193 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2928 13:40:21.750308 ==
2929 13:40:21.753915 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 13:40:21.760732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 13:40:21.760851 ==
2932 13:40:21.760918 DQS Delay:
2933 13:40:21.763693 DQS0 = 0, DQS1 = 0
2934 13:40:21.763792 DQM Delay:
2935 13:40:21.763858 DQM0 = 115, DQM1 = 105
2936 13:40:21.767356 DQ Delay:
2937 13:40:21.770673 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2938 13:40:21.773669 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2939 13:40:21.777483 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2940 13:40:21.780738 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2941 13:40:21.780828
2942 13:40:21.780891
2943 13:40:21.780951 ==
2944 13:40:21.784201 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 13:40:21.787215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 13:40:21.787309 ==
2947 13:40:21.787474
2948 13:40:21.790756
2949 13:40:21.790857 TX Vref Scan disable
2950 13:40:21.793957 == TX Byte 0 ==
2951 13:40:21.797468 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2952 13:40:21.800988 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2953 13:40:21.803911 == TX Byte 1 ==
2954 13:40:21.807423 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2955 13:40:21.810674 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2956 13:40:21.810789 ==
2957 13:40:21.814053 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 13:40:21.820792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 13:40:21.820904 ==
2960 13:40:21.831369 TX Vref=22, minBit 1, minWin=25, winSum=420
2961 13:40:21.834905 TX Vref=24, minBit 1, minWin=25, winSum=424
2962 13:40:21.837944 TX Vref=26, minBit 5, minWin=25, winSum=429
2963 13:40:21.841764 TX Vref=28, minBit 0, minWin=26, winSum=432
2964 13:40:21.844683 TX Vref=30, minBit 3, minWin=26, winSum=434
2965 13:40:21.848453 TX Vref=32, minBit 4, minWin=26, winSum=434
2966 13:40:21.855024 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 30
2967 13:40:21.855148
2968 13:40:21.858313 Final TX Range 1 Vref 30
2969 13:40:21.858422
2970 13:40:21.858516 ==
2971 13:40:21.861853 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 13:40:21.864806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 13:40:21.864945 ==
2974 13:40:21.865048
2975 13:40:21.865108
2976 13:40:21.868302 TX Vref Scan disable
2977 13:40:21.871568 == TX Byte 0 ==
2978 13:40:21.875406 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2979 13:40:21.878409 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2980 13:40:21.881982 == TX Byte 1 ==
2981 13:40:21.885298 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2982 13:40:21.888805 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2983 13:40:21.888943
2984 13:40:21.891746 [DATLAT]
2985 13:40:21.891850 Freq=1200, CH0 RK1
2986 13:40:21.891933
2987 13:40:21.895123 DATLAT Default: 0xd
2988 13:40:21.895216 0, 0xFFFF, sum = 0
2989 13:40:21.898100 1, 0xFFFF, sum = 0
2990 13:40:21.898191 2, 0xFFFF, sum = 0
2991 13:40:21.901695 3, 0xFFFF, sum = 0
2992 13:40:21.901790 4, 0xFFFF, sum = 0
2993 13:40:21.905201 5, 0xFFFF, sum = 0
2994 13:40:21.905295 6, 0xFFFF, sum = 0
2995 13:40:21.908423 7, 0xFFFF, sum = 0
2996 13:40:21.908505 8, 0xFFFF, sum = 0
2997 13:40:21.912148 9, 0xFFFF, sum = 0
2998 13:40:21.912257 10, 0xFFFF, sum = 0
2999 13:40:21.915464 11, 0xFFFF, sum = 0
3000 13:40:21.915582 12, 0x0, sum = 1
3001 13:40:21.918485 13, 0x0, sum = 2
3002 13:40:21.918571 14, 0x0, sum = 3
3003 13:40:21.922100 15, 0x0, sum = 4
3004 13:40:21.922214 best_step = 13
3005 13:40:21.922306
3006 13:40:21.922394 ==
3007 13:40:21.925158 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 13:40:21.932025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 13:40:21.932163 ==
3010 13:40:21.932231 RX Vref Scan: 0
3011 13:40:21.932290
3012 13:40:21.935607 RX Vref 0 -> 0, step: 1
3013 13:40:21.935693
3014 13:40:21.938703 RX Delay -21 -> 252, step: 4
3015 13:40:21.941847 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3016 13:40:21.945067 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3017 13:40:21.948577 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3018 13:40:21.955502 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3019 13:40:21.958468 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3020 13:40:21.962013 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3021 13:40:21.965532 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3022 13:40:21.968907 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3023 13:40:21.975900 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3024 13:40:21.978747 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3025 13:40:21.982202 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3026 13:40:21.985860 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3027 13:40:21.988938 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3028 13:40:21.992571 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3029 13:40:21.999226 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3030 13:40:22.002357 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3031 13:40:22.002469 ==
3032 13:40:22.006248 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 13:40:22.009192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 13:40:22.009316 ==
3035 13:40:22.012771 DQS Delay:
3036 13:40:22.012855 DQS0 = 0, DQS1 = 0
3037 13:40:22.012919 DQM Delay:
3038 13:40:22.015944 DQM0 = 113, DQM1 = 104
3039 13:40:22.016018 DQ Delay:
3040 13:40:22.019298 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3041 13:40:22.022346 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =122
3042 13:40:22.026049 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3043 13:40:22.032662 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3044 13:40:22.032811
3045 13:40:22.032906
3046 13:40:22.039433 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3047 13:40:22.042457 CH0 RK1: MR19=403, MR18=2F3
3048 13:40:22.049237 CH0_RK1: MR19=0x403, MR18=0x2F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3049 13:40:22.052466 [RxdqsGatingPostProcess] freq 1200
3050 13:40:22.056092 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 13:40:22.059175 best DQS0 dly(2T, 0.5T) = (0, 12)
3052 13:40:22.062825 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 13:40:22.065728 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3054 13:40:22.069404 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 13:40:22.072554 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 13:40:22.076168 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 13:40:22.079749 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 13:40:22.082654 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 13:40:22.086088 Pre-setting of DQS Precalculation
3060 13:40:22.089356 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 13:40:22.089441 ==
3062 13:40:22.092889 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 13:40:22.096027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 13:40:22.096111 ==
3065 13:40:22.103220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 13:40:22.109713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3067 13:40:22.116784 [CA 0] Center 38 (8~68) winsize 61
3068 13:40:22.120226 [CA 1] Center 38 (9~68) winsize 60
3069 13:40:22.123568 [CA 2] Center 35 (5~65) winsize 61
3070 13:40:22.126965 [CA 3] Center 34 (4~64) winsize 61
3071 13:40:22.130189 [CA 4] Center 34 (4~65) winsize 62
3072 13:40:22.133921 [CA 5] Center 33 (3~63) winsize 61
3073 13:40:22.134037
3074 13:40:22.137659 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3075 13:40:22.137781
3076 13:40:22.140595 [CATrainingPosCal] consider 1 rank data
3077 13:40:22.144208 u2DelayCellTimex100 = 270/100 ps
3078 13:40:22.147325 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3079 13:40:22.150453 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3080 13:40:22.154074 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 13:40:22.157308 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 13:40:22.164198 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3083 13:40:22.167138 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3084 13:40:22.167232
3085 13:40:22.170732 CA PerBit enable=1, Macro0, CA PI delay=33
3086 13:40:22.170824
3087 13:40:22.174283 [CBTSetCACLKResult] CA Dly = 33
3088 13:40:22.174381 CS Dly: 6 (0~37)
3089 13:40:22.174445 ==
3090 13:40:22.177691 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 13:40:22.181111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 13:40:22.184620 ==
3093 13:40:22.187881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 13:40:22.194276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3095 13:40:22.202698 [CA 0] Center 38 (8~68) winsize 61
3096 13:40:22.205842 [CA 1] Center 38 (8~68) winsize 61
3097 13:40:22.209617 [CA 2] Center 34 (4~65) winsize 62
3098 13:40:22.212592 [CA 3] Center 34 (4~65) winsize 62
3099 13:40:22.215734 [CA 4] Center 34 (4~65) winsize 62
3100 13:40:22.219258 [CA 5] Center 33 (3~63) winsize 61
3101 13:40:22.219383
3102 13:40:22.222409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3103 13:40:22.222488
3104 13:40:22.225837 [CATrainingPosCal] consider 2 rank data
3105 13:40:22.229650 u2DelayCellTimex100 = 270/100 ps
3106 13:40:22.232616 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3107 13:40:22.235708 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3108 13:40:22.239513 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 13:40:22.246258 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 13:40:22.249394 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3111 13:40:22.252860 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3112 13:40:22.252959
3113 13:40:22.255968 CA PerBit enable=1, Macro0, CA PI delay=33
3114 13:40:22.256059
3115 13:40:22.259632 [CBTSetCACLKResult] CA Dly = 33
3116 13:40:22.259726 CS Dly: 7 (0~40)
3117 13:40:22.259792
3118 13:40:22.262800 ----->DramcWriteLeveling(PI) begin...
3119 13:40:22.262887 ==
3120 13:40:22.266064 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 13:40:22.272929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 13:40:22.273083 ==
3123 13:40:22.276638 Write leveling (Byte 0): 27 => 27
3124 13:40:22.279517 Write leveling (Byte 1): 29 => 29
3125 13:40:22.279610 DramcWriteLeveling(PI) end<-----
3126 13:40:22.279675
3127 13:40:22.283019 ==
3128 13:40:22.283108 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 13:40:22.289903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 13:40:22.290019 ==
3131 13:40:22.293129 [Gating] SW mode calibration
3132 13:40:22.299600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 13:40:22.303302 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 13:40:22.309925 0 15 0 | B1->B0 | 2b2b 2323 | 1 1 | (0 0) (0 0)
3135 13:40:22.313273 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3136 13:40:22.316354 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 13:40:22.320090 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 13:40:22.326751 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 13:40:22.329809 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 13:40:22.333638 0 15 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3141 13:40:22.339846 0 15 28 | B1->B0 | 3232 3333 | 0 1 | (0 1) (1 0)
3142 13:40:22.343444 1 0 0 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
3143 13:40:22.347070 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 13:40:22.353826 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 13:40:22.356627 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 13:40:22.360309 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 13:40:22.367364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 13:40:22.370270 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 13:40:22.373405 1 0 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3150 13:40:22.377239 1 1 0 | B1->B0 | 4242 3434 | 0 0 | (0 0) (0 0)
3151 13:40:22.383553 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 13:40:22.386757 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 13:40:22.390326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 13:40:22.397283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 13:40:22.400647 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 13:40:22.404389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 13:40:22.410959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 13:40:22.414123 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3159 13:40:22.417362 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 13:40:22.424001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 13:40:22.427638 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 13:40:22.431000 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 13:40:22.434469 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 13:40:22.440685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 13:40:22.444313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 13:40:22.447299 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 13:40:22.454500 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 13:40:22.457453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 13:40:22.460828 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 13:40:22.467608 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 13:40:22.470692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 13:40:22.474491 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 13:40:22.481259 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3174 13:40:22.484192 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 13:40:22.487857 Total UI for P1: 0, mck2ui 16
3176 13:40:22.491149 best dqsien dly found for B0: ( 1, 3, 28)
3177 13:40:22.494499 Total UI for P1: 0, mck2ui 16
3178 13:40:22.498297 best dqsien dly found for B1: ( 1, 3, 28)
3179 13:40:22.501484 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3180 13:40:22.504504 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3181 13:40:22.504598
3182 13:40:22.507927 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3183 13:40:22.511502 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3184 13:40:22.514486 [Gating] SW calibration Done
3185 13:40:22.514584 ==
3186 13:40:22.518110 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 13:40:22.521298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 13:40:22.521390 ==
3189 13:40:22.524766 RX Vref Scan: 0
3190 13:40:22.524856
3191 13:40:22.524921 RX Vref 0 -> 0, step: 1
3192 13:40:22.525010
3193 13:40:22.528102 RX Delay -40 -> 252, step: 8
3194 13:40:22.534747 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3195 13:40:22.538254 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3196 13:40:22.541392 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3197 13:40:22.545143 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3198 13:40:22.548000 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3199 13:40:22.551620 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3200 13:40:22.558541 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3201 13:40:22.561850 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3202 13:40:22.564806 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3203 13:40:22.568468 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3204 13:40:22.571426 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3205 13:40:22.578591 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3206 13:40:22.581348 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3207 13:40:22.585079 iDelay=200, Bit 13, Center 119 (56 ~ 183) 128
3208 13:40:22.588659 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3209 13:40:22.591667 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3210 13:40:22.591761 ==
3211 13:40:22.595321 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 13:40:22.601649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 13:40:22.601784 ==
3214 13:40:22.601852 DQS Delay:
3215 13:40:22.605515 DQS0 = 0, DQS1 = 0
3216 13:40:22.605620 DQM Delay:
3217 13:40:22.605688 DQM0 = 115, DQM1 = 110
3218 13:40:22.608368 DQ Delay:
3219 13:40:22.611967 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3220 13:40:22.615319 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111
3221 13:40:22.618458 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3222 13:40:22.622257 DQ12 =123, DQ13 =119, DQ14 =111, DQ15 =115
3223 13:40:22.622368
3224 13:40:22.622435
3225 13:40:22.622495 ==
3226 13:40:22.625312 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 13:40:22.629067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 13:40:22.629170 ==
3229 13:40:22.629238
3230 13:40:22.632249
3231 13:40:22.632344 TX Vref Scan disable
3232 13:40:22.635644 == TX Byte 0 ==
3233 13:40:22.638584 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3234 13:40:22.642263 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3235 13:40:22.645677 == TX Byte 1 ==
3236 13:40:22.649387 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3237 13:40:22.652272 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3238 13:40:22.652368 ==
3239 13:40:22.655444 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 13:40:22.662156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 13:40:22.662277 ==
3242 13:40:22.672576 TX Vref=22, minBit 0, minWin=25, winSum=412
3243 13:40:22.676345 TX Vref=24, minBit 1, minWin=25, winSum=415
3244 13:40:22.679427 TX Vref=26, minBit 1, minWin=26, winSum=426
3245 13:40:22.682826 TX Vref=28, minBit 1, minWin=26, winSum=428
3246 13:40:22.686049 TX Vref=30, minBit 3, minWin=25, winSum=426
3247 13:40:22.689341 TX Vref=32, minBit 3, minWin=25, winSum=427
3248 13:40:22.696102 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3249 13:40:22.696232
3250 13:40:22.699730 Final TX Range 1 Vref 28
3251 13:40:22.699839
3252 13:40:22.699906 ==
3253 13:40:22.702912 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 13:40:22.706083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 13:40:22.706171 ==
3256 13:40:22.706235
3257 13:40:22.706294
3258 13:40:22.709989 TX Vref Scan disable
3259 13:40:22.712789 == TX Byte 0 ==
3260 13:40:22.716536 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3261 13:40:22.720120 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3262 13:40:22.723393 == TX Byte 1 ==
3263 13:40:22.726746 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3264 13:40:22.730083 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3265 13:40:22.730180
3266 13:40:22.730246 [DATLAT]
3267 13:40:22.733624 Freq=1200, CH1 RK0
3268 13:40:22.733722
3269 13:40:22.736567 DATLAT Default: 0xd
3270 13:40:22.736679 0, 0xFFFF, sum = 0
3271 13:40:22.740148 1, 0xFFFF, sum = 0
3272 13:40:22.740242 2, 0xFFFF, sum = 0
3273 13:40:22.743791 3, 0xFFFF, sum = 0
3274 13:40:22.743905 4, 0xFFFF, sum = 0
3275 13:40:22.746877 5, 0xFFFF, sum = 0
3276 13:40:22.746964 6, 0xFFFF, sum = 0
3277 13:40:22.750177 7, 0xFFFF, sum = 0
3278 13:40:22.750271 8, 0xFFFF, sum = 0
3279 13:40:22.753234 9, 0xFFFF, sum = 0
3280 13:40:22.753331 10, 0xFFFF, sum = 0
3281 13:40:22.756830 11, 0xFFFF, sum = 0
3282 13:40:22.756924 12, 0x0, sum = 1
3283 13:40:22.760310 13, 0x0, sum = 2
3284 13:40:22.760429 14, 0x0, sum = 3
3285 13:40:22.763371 15, 0x0, sum = 4
3286 13:40:22.763464 best_step = 13
3287 13:40:22.763547
3288 13:40:22.763626 ==
3289 13:40:22.767249 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 13:40:22.770367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 13:40:22.773295 ==
3292 13:40:22.773389 RX Vref Scan: 1
3293 13:40:22.773499
3294 13:40:22.777265 Set Vref Range= 32 -> 127
3295 13:40:22.777421
3296 13:40:22.777515 RX Vref 32 -> 127, step: 1
3297 13:40:22.780339
3298 13:40:22.780432 RX Delay -21 -> 252, step: 4
3299 13:40:22.780496
3300 13:40:22.783342 Set Vref, RX VrefLevel [Byte0]: 32
3301 13:40:22.786938 [Byte1]: 32
3302 13:40:22.790944
3303 13:40:22.791085 Set Vref, RX VrefLevel [Byte0]: 33
3304 13:40:22.793877 [Byte1]: 33
3305 13:40:22.799060
3306 13:40:22.799163 Set Vref, RX VrefLevel [Byte0]: 34
3307 13:40:22.802324 [Byte1]: 34
3308 13:40:22.806421
3309 13:40:22.806515 Set Vref, RX VrefLevel [Byte0]: 35
3310 13:40:22.810159 [Byte1]: 35
3311 13:40:22.814332
3312 13:40:22.814428 Set Vref, RX VrefLevel [Byte0]: 36
3313 13:40:22.818140 [Byte1]: 36
3314 13:40:22.822489
3315 13:40:22.822584 Set Vref, RX VrefLevel [Byte0]: 37
3316 13:40:22.825936 [Byte1]: 37
3317 13:40:22.830077
3318 13:40:22.830185 Set Vref, RX VrefLevel [Byte0]: 38
3319 13:40:22.833718 [Byte1]: 38
3320 13:40:22.838511
3321 13:40:22.838623 Set Vref, RX VrefLevel [Byte0]: 39
3322 13:40:22.841285 [Byte1]: 39
3323 13:40:22.845832
3324 13:40:22.845932 Set Vref, RX VrefLevel [Byte0]: 40
3325 13:40:22.849699 [Byte1]: 40
3326 13:40:22.854051
3327 13:40:22.857645 Set Vref, RX VrefLevel [Byte0]: 41
3328 13:40:22.860517 [Byte1]: 41
3329 13:40:22.860607
3330 13:40:22.864283 Set Vref, RX VrefLevel [Byte0]: 42
3331 13:40:22.867390 [Byte1]: 42
3332 13:40:22.867503
3333 13:40:22.870394 Set Vref, RX VrefLevel [Byte0]: 43
3334 13:40:22.874180 [Byte1]: 43
3335 13:40:22.877887
3336 13:40:22.877986 Set Vref, RX VrefLevel [Byte0]: 44
3337 13:40:22.880827 [Byte1]: 44
3338 13:40:22.885826
3339 13:40:22.885923 Set Vref, RX VrefLevel [Byte0]: 45
3340 13:40:22.889020 [Byte1]: 45
3341 13:40:22.893572
3342 13:40:22.893673 Set Vref, RX VrefLevel [Byte0]: 46
3343 13:40:22.896833 [Byte1]: 46
3344 13:40:22.901741
3345 13:40:22.901837 Set Vref, RX VrefLevel [Byte0]: 47
3346 13:40:22.904782 [Byte1]: 47
3347 13:40:22.909902
3348 13:40:22.910000 Set Vref, RX VrefLevel [Byte0]: 48
3349 13:40:22.913121 [Byte1]: 48
3350 13:40:22.917243
3351 13:40:22.917327 Set Vref, RX VrefLevel [Byte0]: 49
3352 13:40:22.920869 [Byte1]: 49
3353 13:40:22.925437
3354 13:40:22.925518 Set Vref, RX VrefLevel [Byte0]: 50
3355 13:40:22.928869 [Byte1]: 50
3356 13:40:22.933035
3357 13:40:22.933131 Set Vref, RX VrefLevel [Byte0]: 51
3358 13:40:22.936616 [Byte1]: 51
3359 13:40:22.941404
3360 13:40:22.941487 Set Vref, RX VrefLevel [Byte0]: 52
3361 13:40:22.944347 [Byte1]: 52
3362 13:40:22.949066
3363 13:40:22.949149 Set Vref, RX VrefLevel [Byte0]: 53
3364 13:40:22.952137 [Byte1]: 53
3365 13:40:22.957072
3366 13:40:22.957155 Set Vref, RX VrefLevel [Byte0]: 54
3367 13:40:22.960401 [Byte1]: 54
3368 13:40:22.964649
3369 13:40:22.964729 Set Vref, RX VrefLevel [Byte0]: 55
3370 13:40:22.968529 [Byte1]: 55
3371 13:40:22.972801
3372 13:40:22.972881 Set Vref, RX VrefLevel [Byte0]: 56
3373 13:40:22.976129 [Byte1]: 56
3374 13:40:22.980917
3375 13:40:22.981042 Set Vref, RX VrefLevel [Byte0]: 57
3376 13:40:22.983922 [Byte1]: 57
3377 13:40:22.988739
3378 13:40:22.988819 Set Vref, RX VrefLevel [Byte0]: 58
3379 13:40:22.991900 [Byte1]: 58
3380 13:40:22.996748
3381 13:40:22.996828 Set Vref, RX VrefLevel [Byte0]: 59
3382 13:40:23.000260 [Byte1]: 59
3383 13:40:23.004731
3384 13:40:23.004812 Set Vref, RX VrefLevel [Byte0]: 60
3385 13:40:23.007806 [Byte1]: 60
3386 13:40:23.012603
3387 13:40:23.012684 Set Vref, RX VrefLevel [Byte0]: 61
3388 13:40:23.015652 [Byte1]: 61
3389 13:40:23.020834
3390 13:40:23.020915 Set Vref, RX VrefLevel [Byte0]: 62
3391 13:40:23.023444 [Byte1]: 62
3392 13:40:23.028231
3393 13:40:23.028306 Set Vref, RX VrefLevel [Byte0]: 63
3394 13:40:23.031491 [Byte1]: 63
3395 13:40:23.036212
3396 13:40:23.036294 Set Vref, RX VrefLevel [Byte0]: 64
3397 13:40:23.039584 [Byte1]: 64
3398 13:40:23.044219
3399 13:40:23.044305 Set Vref, RX VrefLevel [Byte0]: 65
3400 13:40:23.047316 [Byte1]: 65
3401 13:40:23.052393
3402 13:40:23.052464 Set Vref, RX VrefLevel [Byte0]: 66
3403 13:40:23.055248 [Byte1]: 66
3404 13:40:23.059774
3405 13:40:23.059848 Set Vref, RX VrefLevel [Byte0]: 67
3406 13:40:23.063013 [Byte1]: 67
3407 13:40:23.067839
3408 13:40:23.067909 Set Vref, RX VrefLevel [Byte0]: 68
3409 13:40:23.071404 [Byte1]: 68
3410 13:40:23.075740
3411 13:40:23.075862 Set Vref, RX VrefLevel [Byte0]: 69
3412 13:40:23.079260 [Byte1]: 69
3413 13:40:23.083945
3414 13:40:23.084052 Set Vref, RX VrefLevel [Byte0]: 70
3415 13:40:23.087184 [Byte1]: 70
3416 13:40:23.091446
3417 13:40:23.091520 Set Vref, RX VrefLevel [Byte0]: 71
3418 13:40:23.094951 [Byte1]: 71
3419 13:40:23.099834
3420 13:40:23.099909 Set Vref, RX VrefLevel [Byte0]: 72
3421 13:40:23.102846 [Byte1]: 72
3422 13:40:23.107582
3423 13:40:23.107655 Final RX Vref Byte 0 = 56 to rank0
3424 13:40:23.110708 Final RX Vref Byte 1 = 51 to rank0
3425 13:40:23.114410 Final RX Vref Byte 0 = 56 to rank1
3426 13:40:23.117479 Final RX Vref Byte 1 = 51 to rank1==
3427 13:40:23.121044 Dram Type= 6, Freq= 0, CH_1, rank 0
3428 13:40:23.124335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 13:40:23.127884 ==
3430 13:40:23.127961 DQS Delay:
3431 13:40:23.128022 DQS0 = 0, DQS1 = 0
3432 13:40:23.131256 DQM Delay:
3433 13:40:23.131325 DQM0 = 116, DQM1 = 109
3434 13:40:23.134341 DQ Delay:
3435 13:40:23.137298 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3436 13:40:23.140967 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3437 13:40:23.144312 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3438 13:40:23.147687 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =114
3439 13:40:23.147758
3440 13:40:23.147817
3441 13:40:23.154228 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3442 13:40:23.158074 CH1 RK0: MR19=403, MR18=1E6
3443 13:40:23.164389 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3444 13:40:23.164483
3445 13:40:23.167995 ----->DramcWriteLeveling(PI) begin...
3446 13:40:23.168071 ==
3447 13:40:23.171379 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 13:40:23.174636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 13:40:23.174720 ==
3450 13:40:23.178313 Write leveling (Byte 0): 27 => 27
3451 13:40:23.181253 Write leveling (Byte 1): 28 => 28
3452 13:40:23.184881 DramcWriteLeveling(PI) end<-----
3453 13:40:23.184964
3454 13:40:23.185074 ==
3455 13:40:23.187756 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 13:40:23.191219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 13:40:23.191301 ==
3458 13:40:23.194707 [Gating] SW mode calibration
3459 13:40:23.201190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3460 13:40:23.208076 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3461 13:40:23.211081 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3462 13:40:23.218198 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3463 13:40:23.221183 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 13:40:23.224865 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3465 13:40:23.227735 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 13:40:23.234826 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 13:40:23.238377 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
3468 13:40:23.241336 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3469 13:40:23.248159 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3470 13:40:23.251637 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 13:40:23.254714 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 13:40:23.261311 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3473 13:40:23.264855 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 13:40:23.268289 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3475 13:40:23.275129 1 0 24 | B1->B0 | 2727 4040 | 0 1 | (0 0) (0 0)
3476 13:40:23.278099 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3477 13:40:23.281339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 13:40:23.288558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 13:40:23.291636 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 13:40:23.294893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 13:40:23.301606 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 13:40:23.305315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3483 13:40:23.308323 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3484 13:40:23.311761 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3485 13:40:23.318012 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 13:40:23.321607 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 13:40:23.324674 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 13:40:23.331411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 13:40:23.334629 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 13:40:23.338208 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 13:40:23.345164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 13:40:23.348623 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 13:40:23.351668 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 13:40:23.358412 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 13:40:23.361460 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 13:40:23.364680 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 13:40:23.371814 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 13:40:23.374943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 13:40:23.378364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3500 13:40:23.385129 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3501 13:40:23.385222 Total UI for P1: 0, mck2ui 16
3502 13:40:23.388748 best dqsien dly found for B0: ( 1, 3, 24)
3503 13:40:23.395486 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 13:40:23.398796 Total UI for P1: 0, mck2ui 16
3505 13:40:23.401873 best dqsien dly found for B1: ( 1, 3, 26)
3506 13:40:23.405250 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3507 13:40:23.408437 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3508 13:40:23.408509
3509 13:40:23.411627 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3510 13:40:23.415051 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3511 13:40:23.418022 [Gating] SW calibration Done
3512 13:40:23.418162 ==
3513 13:40:23.421458 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 13:40:23.424746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 13:40:23.424821 ==
3516 13:40:23.428465 RX Vref Scan: 0
3517 13:40:23.428535
3518 13:40:23.428601 RX Vref 0 -> 0, step: 1
3519 13:40:23.431496
3520 13:40:23.431593 RX Delay -40 -> 252, step: 8
3521 13:40:23.438065 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3522 13:40:23.441701 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3523 13:40:23.444759 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3524 13:40:23.448144 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3525 13:40:23.451326 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3526 13:40:23.458560 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3527 13:40:23.461615 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3528 13:40:23.464633 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3529 13:40:23.468315 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3530 13:40:23.471464 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3531 13:40:23.475028 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3532 13:40:23.481530 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3533 13:40:23.484734 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3534 13:40:23.487979 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3535 13:40:23.491465 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3536 13:40:23.498123 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3537 13:40:23.498212 ==
3538 13:40:23.501520 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 13:40:23.504560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 13:40:23.504645 ==
3541 13:40:23.504710 DQS Delay:
3542 13:40:23.508403 DQS0 = 0, DQS1 = 0
3543 13:40:23.508481 DQM Delay:
3544 13:40:23.511208 DQM0 = 113, DQM1 = 110
3545 13:40:23.511286 DQ Delay:
3546 13:40:23.514954 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3547 13:40:23.518027 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3548 13:40:23.521796 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3549 13:40:23.524466 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3550 13:40:23.524550
3551 13:40:23.524614
3552 13:40:23.527954 ==
3553 13:40:23.531153 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 13:40:23.534588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 13:40:23.534675 ==
3556 13:40:23.534740
3557 13:40:23.534800
3558 13:40:23.538140 TX Vref Scan disable
3559 13:40:23.538222 == TX Byte 0 ==
3560 13:40:23.541154 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 13:40:23.548137 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 13:40:23.548254 == TX Byte 1 ==
3563 13:40:23.550991 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 13:40:23.558324 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 13:40:23.558406 ==
3566 13:40:23.561234 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 13:40:23.564889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 13:40:23.565009 ==
3569 13:40:23.576482 TX Vref=22, minBit 1, minWin=25, winSum=419
3570 13:40:23.579527 TX Vref=24, minBit 3, minWin=25, winSum=423
3571 13:40:23.583058 TX Vref=26, minBit 9, minWin=25, winSum=429
3572 13:40:23.586175 TX Vref=28, minBit 4, minWin=26, winSum=433
3573 13:40:23.589891 TX Vref=30, minBit 2, minWin=26, winSum=432
3574 13:40:23.592916 TX Vref=32, minBit 2, minWin=26, winSum=431
3575 13:40:23.599555 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 28
3576 13:40:23.599650
3577 13:40:23.603130 Final TX Range 1 Vref 28
3578 13:40:23.603216
3579 13:40:23.603301 ==
3580 13:40:23.606313 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 13:40:23.609605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 13:40:23.609690 ==
3583 13:40:23.609775
3584 13:40:23.609855
3585 13:40:23.613253 TX Vref Scan disable
3586 13:40:23.616785 == TX Byte 0 ==
3587 13:40:23.619756 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3588 13:40:23.622848 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3589 13:40:23.626385 == TX Byte 1 ==
3590 13:40:23.630117 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 13:40:23.633270 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 13:40:23.633370
3593 13:40:23.637047 [DATLAT]
3594 13:40:23.637157 Freq=1200, CH1 RK1
3595 13:40:23.637244
3596 13:40:23.639912 DATLAT Default: 0xd
3597 13:40:23.639996 0, 0xFFFF, sum = 0
3598 13:40:23.642861 1, 0xFFFF, sum = 0
3599 13:40:23.642946 2, 0xFFFF, sum = 0
3600 13:40:23.646381 3, 0xFFFF, sum = 0
3601 13:40:23.646466 4, 0xFFFF, sum = 0
3602 13:40:23.650055 5, 0xFFFF, sum = 0
3603 13:40:23.650139 6, 0xFFFF, sum = 0
3604 13:40:23.653413 7, 0xFFFF, sum = 0
3605 13:40:23.653497 8, 0xFFFF, sum = 0
3606 13:40:23.656662 9, 0xFFFF, sum = 0
3607 13:40:23.656737 10, 0xFFFF, sum = 0
3608 13:40:23.659838 11, 0xFFFF, sum = 0
3609 13:40:23.659915 12, 0x0, sum = 1
3610 13:40:23.663277 13, 0x0, sum = 2
3611 13:40:23.663352 14, 0x0, sum = 3
3612 13:40:23.666941 15, 0x0, sum = 4
3613 13:40:23.667015 best_step = 13
3614 13:40:23.667093
3615 13:40:23.667169 ==
3616 13:40:23.669734 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 13:40:23.676849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 13:40:23.676940 ==
3619 13:40:23.677079 RX Vref Scan: 0
3620 13:40:23.677159
3621 13:40:23.679997 RX Vref 0 -> 0, step: 1
3622 13:40:23.680068
3623 13:40:23.683567 RX Delay -21 -> 252, step: 4
3624 13:40:23.686635 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3625 13:40:23.690273 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3626 13:40:23.696690 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3627 13:40:23.699841 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3628 13:40:23.703287 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3629 13:40:23.706324 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3630 13:40:23.709798 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3631 13:40:23.716402 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3632 13:40:23.719615 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3633 13:40:23.723129 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3634 13:40:23.726101 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3635 13:40:23.729757 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3636 13:40:23.736523 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3637 13:40:23.739655 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3638 13:40:23.742775 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3639 13:40:23.746383 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3640 13:40:23.746469 ==
3641 13:40:23.749311 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 13:40:23.756200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 13:40:23.756299 ==
3644 13:40:23.756363 DQS Delay:
3645 13:40:23.759278 DQS0 = 0, DQS1 = 0
3646 13:40:23.759361 DQM Delay:
3647 13:40:23.759424 DQM0 = 113, DQM1 = 109
3648 13:40:23.762958 DQ Delay:
3649 13:40:23.765819 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3650 13:40:23.769572 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3651 13:40:23.772672 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3652 13:40:23.776066 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3653 13:40:23.776150
3654 13:40:23.776213
3655 13:40:23.785724 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3656 13:40:23.785828 CH1 RK1: MR19=303, MR18=F8FF
3657 13:40:23.792550 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3658 13:40:23.796131 [RxdqsGatingPostProcess] freq 1200
3659 13:40:23.802744 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3660 13:40:23.805778 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 13:40:23.809314 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 13:40:23.812352 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 13:40:23.816068 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 13:40:23.818885 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 13:40:23.818978 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 13:40:23.822537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 13:40:23.825664 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 13:40:23.829374 Pre-setting of DQS Precalculation
3669 13:40:23.835663 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3670 13:40:23.842332 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3671 13:40:23.849018 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3672 13:40:23.849154
3673 13:40:23.849231
3674 13:40:23.852559 [Calibration Summary] 2400 Mbps
3675 13:40:23.852647 CH 0, Rank 0
3676 13:40:23.855586 SW Impedance : PASS
3677 13:40:23.858894 DUTY Scan : NO K
3678 13:40:23.858995 ZQ Calibration : PASS
3679 13:40:23.862341 Jitter Meter : NO K
3680 13:40:23.865899 CBT Training : PASS
3681 13:40:23.865994 Write leveling : PASS
3682 13:40:23.869331 RX DQS gating : PASS
3683 13:40:23.872265 RX DQ/DQS(RDDQC) : PASS
3684 13:40:23.872372 TX DQ/DQS : PASS
3685 13:40:23.875901 RX DATLAT : PASS
3686 13:40:23.878926 RX DQ/DQS(Engine): PASS
3687 13:40:23.879027 TX OE : NO K
3688 13:40:23.879094 All Pass.
3689 13:40:23.879154
3690 13:40:23.882056 CH 0, Rank 1
3691 13:40:23.885695 SW Impedance : PASS
3692 13:40:23.885795 DUTY Scan : NO K
3693 13:40:23.888752 ZQ Calibration : PASS
3694 13:40:23.892396 Jitter Meter : NO K
3695 13:40:23.892485 CBT Training : PASS
3696 13:40:23.895836 Write leveling : PASS
3697 13:40:23.895919 RX DQS gating : PASS
3698 13:40:23.899078 RX DQ/DQS(RDDQC) : PASS
3699 13:40:23.902151 TX DQ/DQS : PASS
3700 13:40:23.902233 RX DATLAT : PASS
3701 13:40:23.905682 RX DQ/DQS(Engine): PASS
3702 13:40:23.909100 TX OE : NO K
3703 13:40:23.909182 All Pass.
3704 13:40:23.909245
3705 13:40:23.909304 CH 1, Rank 0
3706 13:40:23.912415 SW Impedance : PASS
3707 13:40:23.915408 DUTY Scan : NO K
3708 13:40:23.915489 ZQ Calibration : PASS
3709 13:40:23.919072 Jitter Meter : NO K
3710 13:40:23.922377 CBT Training : PASS
3711 13:40:23.922458 Write leveling : PASS
3712 13:40:23.925890 RX DQS gating : PASS
3713 13:40:23.928894 RX DQ/DQS(RDDQC) : PASS
3714 13:40:23.928982 TX DQ/DQS : PASS
3715 13:40:23.932269 RX DATLAT : PASS
3716 13:40:23.932350 RX DQ/DQS(Engine): PASS
3717 13:40:23.935998 TX OE : NO K
3718 13:40:23.936080 All Pass.
3719 13:40:23.936144
3720 13:40:23.938936 CH 1, Rank 1
3721 13:40:23.939016 SW Impedance : PASS
3722 13:40:23.942088 DUTY Scan : NO K
3723 13:40:23.945807 ZQ Calibration : PASS
3724 13:40:23.945891 Jitter Meter : NO K
3725 13:40:23.948763 CBT Training : PASS
3726 13:40:23.952515 Write leveling : PASS
3727 13:40:23.952598 RX DQS gating : PASS
3728 13:40:23.955552 RX DQ/DQS(RDDQC) : PASS
3729 13:40:23.959087 TX DQ/DQS : PASS
3730 13:40:23.959170 RX DATLAT : PASS
3731 13:40:23.962101 RX DQ/DQS(Engine): PASS
3732 13:40:23.966056 TX OE : NO K
3733 13:40:23.966143 All Pass.
3734 13:40:23.966228
3735 13:40:23.966307 DramC Write-DBI off
3736 13:40:23.968774 PER_BANK_REFRESH: Hybrid Mode
3737 13:40:23.972195 TX_TRACKING: ON
3738 13:40:23.978885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3739 13:40:23.982370 [FAST_K] Save calibration result to emmc
3740 13:40:23.989210 dramc_set_vcore_voltage set vcore to 650000
3741 13:40:23.989304 Read voltage for 600, 5
3742 13:40:23.992196 Vio18 = 0
3743 13:40:23.992279 Vcore = 650000
3744 13:40:23.992363 Vdram = 0
3745 13:40:23.992442 Vddq = 0
3746 13:40:23.995730 Vmddr = 0
3747 13:40:23.998682 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3748 13:40:24.005859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3749 13:40:24.008962 MEM_TYPE=3, freq_sel=19
3750 13:40:24.009086 sv_algorithm_assistance_LP4_1600
3751 13:40:24.015309 ============ PULL DRAM RESETB DOWN ============
3752 13:40:24.018822 ========== PULL DRAM RESETB DOWN end =========
3753 13:40:24.022250 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 13:40:24.025635 ===================================
3755 13:40:24.028865 LPDDR4 DRAM CONFIGURATION
3756 13:40:24.032425 ===================================
3757 13:40:24.035306 EX_ROW_EN[0] = 0x0
3758 13:40:24.035397 EX_ROW_EN[1] = 0x0
3759 13:40:24.039097 LP4Y_EN = 0x0
3760 13:40:24.039184 WORK_FSP = 0x0
3761 13:40:24.042405 WL = 0x2
3762 13:40:24.042488 RL = 0x2
3763 13:40:24.045617 BL = 0x2
3764 13:40:24.045702 RPST = 0x0
3765 13:40:24.048654 RD_PRE = 0x0
3766 13:40:24.048737 WR_PRE = 0x1
3767 13:40:24.052487 WR_PST = 0x0
3768 13:40:24.052572 DBI_WR = 0x0
3769 13:40:24.055376 DBI_RD = 0x0
3770 13:40:24.055460 OTF = 0x1
3771 13:40:24.058612 ===================================
3772 13:40:24.062004 ===================================
3773 13:40:24.065771 ANA top config
3774 13:40:24.068848 ===================================
3775 13:40:24.072031 DLL_ASYNC_EN = 0
3776 13:40:24.072119 ALL_SLAVE_EN = 1
3777 13:40:24.075549 NEW_RANK_MODE = 1
3778 13:40:24.078611 DLL_IDLE_MODE = 1
3779 13:40:24.082160 LP45_APHY_COMB_EN = 1
3780 13:40:24.082248 TX_ODT_DIS = 1
3781 13:40:24.085695 NEW_8X_MODE = 1
3782 13:40:24.088730 ===================================
3783 13:40:24.092434 ===================================
3784 13:40:24.095490 data_rate = 1200
3785 13:40:24.099201 CKR = 1
3786 13:40:24.102154 DQ_P2S_RATIO = 8
3787 13:40:24.105303 ===================================
3788 13:40:24.108725 CA_P2S_RATIO = 8
3789 13:40:24.108809 DQ_CA_OPEN = 0
3790 13:40:24.111959 DQ_SEMI_OPEN = 0
3791 13:40:24.115258 CA_SEMI_OPEN = 0
3792 13:40:24.118604 CA_FULL_RATE = 0
3793 13:40:24.122139 DQ_CKDIV4_EN = 1
3794 13:40:24.125316 CA_CKDIV4_EN = 1
3795 13:40:24.125401 CA_PREDIV_EN = 0
3796 13:40:24.128805 PH8_DLY = 0
3797 13:40:24.131862 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3798 13:40:24.135650 DQ_AAMCK_DIV = 4
3799 13:40:24.138746 CA_AAMCK_DIV = 4
3800 13:40:24.138834 CA_ADMCK_DIV = 4
3801 13:40:24.142102 DQ_TRACK_CA_EN = 0
3802 13:40:24.145476 CA_PICK = 600
3803 13:40:24.148535 CA_MCKIO = 600
3804 13:40:24.152232 MCKIO_SEMI = 0
3805 13:40:24.155491 PLL_FREQ = 2288
3806 13:40:24.159022 DQ_UI_PI_RATIO = 32
3807 13:40:24.159107 CA_UI_PI_RATIO = 0
3808 13:40:24.162354 ===================================
3809 13:40:24.165244 ===================================
3810 13:40:24.169051 memory_type:LPDDR4
3811 13:40:24.172204 GP_NUM : 10
3812 13:40:24.172290 SRAM_EN : 1
3813 13:40:24.175458 MD32_EN : 0
3814 13:40:24.178837 ===================================
3815 13:40:24.182471 [ANA_INIT] >>>>>>>>>>>>>>
3816 13:40:24.185438 <<<<<< [CONFIGURE PHASE]: ANA_TX
3817 13:40:24.189028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3818 13:40:24.191843 ===================================
3819 13:40:24.191954 data_rate = 1200,PCW = 0X5800
3820 13:40:24.195537 ===================================
3821 13:40:24.198544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3822 13:40:24.205416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 13:40:24.212497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 13:40:24.215635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3825 13:40:24.219656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3826 13:40:24.222473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3827 13:40:24.225416 [ANA_INIT] flow start
3828 13:40:24.225529 [ANA_INIT] PLL >>>>>>>>
3829 13:40:24.228722 [ANA_INIT] PLL <<<<<<<<
3830 13:40:24.232268 [ANA_INIT] MIDPI >>>>>>>>
3831 13:40:24.235289 [ANA_INIT] MIDPI <<<<<<<<
3832 13:40:24.235382 [ANA_INIT] DLL >>>>>>>>
3833 13:40:24.238809 [ANA_INIT] flow end
3834 13:40:24.242096 ============ LP4 DIFF to SE enter ============
3835 13:40:24.245738 ============ LP4 DIFF to SE exit ============
3836 13:40:24.248882 [ANA_INIT] <<<<<<<<<<<<<
3837 13:40:24.252566 [Flow] Enable top DCM control >>>>>
3838 13:40:24.256121 [Flow] Enable top DCM control <<<<<
3839 13:40:24.258739 Enable DLL master slave shuffle
3840 13:40:24.265558 ==============================================================
3841 13:40:24.265652 Gating Mode config
3842 13:40:24.271962 ==============================================================
3843 13:40:24.272054 Config description:
3844 13:40:24.281929 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3845 13:40:24.288927 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3846 13:40:24.295663 SELPH_MODE 0: By rank 1: By Phase
3847 13:40:24.298785 ==============================================================
3848 13:40:24.302577 GAT_TRACK_EN = 1
3849 13:40:24.305318 RX_GATING_MODE = 2
3850 13:40:24.309015 RX_GATING_TRACK_MODE = 2
3851 13:40:24.312033 SELPH_MODE = 1
3852 13:40:24.315320 PICG_EARLY_EN = 1
3853 13:40:24.318811 VALID_LAT_VALUE = 1
3854 13:40:24.322465 ==============================================================
3855 13:40:24.325570 Enter into Gating configuration >>>>
3856 13:40:24.329189 Exit from Gating configuration <<<<
3857 13:40:24.332070 Enter into DVFS_PRE_config >>>>>
3858 13:40:24.345896 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3859 13:40:24.346021 Exit from DVFS_PRE_config <<<<<
3860 13:40:24.349008 Enter into PICG configuration >>>>
3861 13:40:24.352610 Exit from PICG configuration <<<<
3862 13:40:24.355674 [RX_INPUT] configuration >>>>>
3863 13:40:24.358927 [RX_INPUT] configuration <<<<<
3864 13:40:24.365718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3865 13:40:24.369252 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3866 13:40:24.375630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 13:40:24.382649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 13:40:24.388907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 13:40:24.395472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 13:40:24.399052 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3871 13:40:24.402430 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3872 13:40:24.405742 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3873 13:40:24.412362 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3874 13:40:24.415539 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3875 13:40:24.419298 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 13:40:24.422271 ===================================
3877 13:40:24.425443 LPDDR4 DRAM CONFIGURATION
3878 13:40:24.429250 ===================================
3879 13:40:24.429369 EX_ROW_EN[0] = 0x0
3880 13:40:24.432099 EX_ROW_EN[1] = 0x0
3881 13:40:24.432181 LP4Y_EN = 0x0
3882 13:40:24.435794 WORK_FSP = 0x0
3883 13:40:24.439212 WL = 0x2
3884 13:40:24.439297 RL = 0x2
3885 13:40:24.442095 BL = 0x2
3886 13:40:24.442177 RPST = 0x0
3887 13:40:24.445649 RD_PRE = 0x0
3888 13:40:24.445734 WR_PRE = 0x1
3889 13:40:24.448728 WR_PST = 0x0
3890 13:40:24.448810 DBI_WR = 0x0
3891 13:40:24.452305 DBI_RD = 0x0
3892 13:40:24.452386 OTF = 0x1
3893 13:40:24.456018 ===================================
3894 13:40:24.459054 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3895 13:40:24.465904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3896 13:40:24.468774 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 13:40:24.472082 ===================================
3898 13:40:24.475617 LPDDR4 DRAM CONFIGURATION
3899 13:40:24.479135 ===================================
3900 13:40:24.479235 EX_ROW_EN[0] = 0x10
3901 13:40:24.482021 EX_ROW_EN[1] = 0x0
3902 13:40:24.482118 LP4Y_EN = 0x0
3903 13:40:24.485549 WORK_FSP = 0x0
3904 13:40:24.485632 WL = 0x2
3905 13:40:24.488652 RL = 0x2
3906 13:40:24.488734 BL = 0x2
3907 13:40:24.492216 RPST = 0x0
3908 13:40:24.492298 RD_PRE = 0x0
3909 13:40:24.495320 WR_PRE = 0x1
3910 13:40:24.495402 WR_PST = 0x0
3911 13:40:24.498717 DBI_WR = 0x0
3912 13:40:24.502320 DBI_RD = 0x0
3913 13:40:24.502401 OTF = 0x1
3914 13:40:24.505823 ===================================
3915 13:40:24.512062 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3916 13:40:24.515526 nWR fixed to 30
3917 13:40:24.519225 [ModeRegInit_LP4] CH0 RK0
3918 13:40:24.519313 [ModeRegInit_LP4] CH0 RK1
3919 13:40:24.522228 [ModeRegInit_LP4] CH1 RK0
3920 13:40:24.525877 [ModeRegInit_LP4] CH1 RK1
3921 13:40:24.525960 match AC timing 17
3922 13:40:24.532672 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3923 13:40:24.535714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3924 13:40:24.538770 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3925 13:40:24.546166 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3926 13:40:24.548763 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3927 13:40:24.548855 ==
3928 13:40:24.552566 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 13:40:24.555441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 13:40:24.555524 ==
3931 13:40:24.562293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 13:40:24.569106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3933 13:40:24.572567 [CA 0] Center 36 (6~66) winsize 61
3934 13:40:24.575537 [CA 1] Center 36 (6~66) winsize 61
3935 13:40:24.578765 [CA 2] Center 34 (4~65) winsize 62
3936 13:40:24.582308 [CA 3] Center 34 (4~65) winsize 62
3937 13:40:24.585616 [CA 4] Center 33 (3~64) winsize 62
3938 13:40:24.588654 [CA 5] Center 33 (3~64) winsize 62
3939 13:40:24.588740
3940 13:40:24.592105 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3941 13:40:24.592190
3942 13:40:24.595844 [CATrainingPosCal] consider 1 rank data
3943 13:40:24.598747 u2DelayCellTimex100 = 270/100 ps
3944 13:40:24.602575 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 13:40:24.605281 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 13:40:24.609196 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 13:40:24.612328 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 13:40:24.615230 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 13:40:24.618493 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 13:40:24.621782
3951 13:40:24.625276 CA PerBit enable=1, Macro0, CA PI delay=33
3952 13:40:24.625366
3953 13:40:24.628760 [CBTSetCACLKResult] CA Dly = 33
3954 13:40:24.628844 CS Dly: 4 (0~35)
3955 13:40:24.628945 ==
3956 13:40:24.632071 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 13:40:24.635360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 13:40:24.635474 ==
3959 13:40:24.642364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 13:40:24.648699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3961 13:40:24.652262 [CA 0] Center 36 (6~67) winsize 62
3962 13:40:24.655448 [CA 1] Center 36 (6~66) winsize 61
3963 13:40:24.658732 [CA 2] Center 34 (4~65) winsize 62
3964 13:40:24.662231 [CA 3] Center 34 (4~65) winsize 62
3965 13:40:24.665300 [CA 4] Center 33 (3~64) winsize 62
3966 13:40:24.669160 [CA 5] Center 33 (3~64) winsize 62
3967 13:40:24.669247
3968 13:40:24.672165 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3969 13:40:24.672249
3970 13:40:24.675735 [CATrainingPosCal] consider 2 rank data
3971 13:40:24.678773 u2DelayCellTimex100 = 270/100 ps
3972 13:40:24.682454 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 13:40:24.685740 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 13:40:24.689140 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 13:40:24.692449 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 13:40:24.696038 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 13:40:24.699172 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 13:40:24.699259
3979 13:40:24.705888 CA PerBit enable=1, Macro0, CA PI delay=33
3980 13:40:24.706018
3981 13:40:24.706121 [CBTSetCACLKResult] CA Dly = 33
3982 13:40:24.709407 CS Dly: 4 (0~36)
3983 13:40:24.709485
3984 13:40:24.712477 ----->DramcWriteLeveling(PI) begin...
3985 13:40:24.712554 ==
3986 13:40:24.716020 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 13:40:24.719315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 13:40:24.719414 ==
3989 13:40:24.722195 Write leveling (Byte 0): 31 => 31
3990 13:40:24.725663 Write leveling (Byte 1): 30 => 30
3991 13:40:24.729187 DramcWriteLeveling(PI) end<-----
3992 13:40:24.729274
3993 13:40:24.729359 ==
3994 13:40:24.732257 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 13:40:24.735840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 13:40:24.739129 ==
3997 13:40:24.739245 [Gating] SW mode calibration
3998 13:40:24.749379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3999 13:40:24.752440 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4000 13:40:24.756117 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 13:40:24.762329 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 13:40:24.765957 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 13:40:24.769117 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4004 13:40:24.775426 0 9 16 | B1->B0 | 3434 3030 | 1 1 | (0 1) (1 1)
4005 13:40:24.779405 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 13:40:24.782499 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 13:40:24.789136 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 13:40:24.792040 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 13:40:24.795902 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 13:40:24.802184 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 13:40:24.805708 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 13:40:24.808764 0 10 16 | B1->B0 | 3131 3939 | 0 0 | (1 1) (0 0)
4013 13:40:24.815435 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 13:40:24.818637 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 13:40:24.822358 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 13:40:24.825304 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 13:40:24.832002 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 13:40:24.835717 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 13:40:24.838560 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 13:40:24.845465 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4021 13:40:24.849000 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 13:40:24.852289 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 13:40:24.858936 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 13:40:24.862502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 13:40:24.865576 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 13:40:24.872263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 13:40:24.875713 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 13:40:24.878575 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 13:40:24.885556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 13:40:24.888894 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 13:40:24.892042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 13:40:24.898533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 13:40:24.902061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 13:40:24.905618 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 13:40:24.912057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 13:40:24.915697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 13:40:24.918851 Total UI for P1: 0, mck2ui 16
4038 13:40:24.922493 best dqsien dly found for B0: ( 0, 13, 14)
4039 13:40:24.925442 Total UI for P1: 0, mck2ui 16
4040 13:40:24.929045 best dqsien dly found for B1: ( 0, 13, 14)
4041 13:40:24.932627 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4042 13:40:24.935537 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4043 13:40:24.935617
4044 13:40:24.939195 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4045 13:40:24.942255 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4046 13:40:24.945415 [Gating] SW calibration Done
4047 13:40:24.945496 ==
4048 13:40:24.949133 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 13:40:24.952191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 13:40:24.952280 ==
4051 13:40:24.955907 RX Vref Scan: 0
4052 13:40:24.955991
4053 13:40:24.958757 RX Vref 0 -> 0, step: 1
4054 13:40:24.958848
4055 13:40:24.958912 RX Delay -230 -> 252, step: 16
4056 13:40:24.965398 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4057 13:40:24.968910 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 13:40:24.972463 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 13:40:24.975894 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4060 13:40:24.982405 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 13:40:24.985500 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4062 13:40:24.988912 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4063 13:40:24.992537 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4064 13:40:24.995517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4065 13:40:25.002033 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4066 13:40:25.005582 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 13:40:25.008778 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 13:40:25.012080 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 13:40:25.018914 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4070 13:40:25.022395 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 13:40:25.025823 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4072 13:40:25.025929 ==
4073 13:40:25.028998 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 13:40:25.032024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 13:40:25.032105 ==
4076 13:40:25.035648 DQS Delay:
4077 13:40:25.035728 DQS0 = 0, DQS1 = 0
4078 13:40:25.039282 DQM Delay:
4079 13:40:25.039365 DQM0 = 40, DQM1 = 33
4080 13:40:25.039429 DQ Delay:
4081 13:40:25.042298 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4082 13:40:25.045479 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4083 13:40:25.048899 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4084 13:40:25.052130 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4085 13:40:25.052210
4086 13:40:25.052273
4087 13:40:25.055609 ==
4088 13:40:25.055689 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 13:40:25.062393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 13:40:25.062474 ==
4091 13:40:25.062538
4092 13:40:25.062598
4093 13:40:25.065392 TX Vref Scan disable
4094 13:40:25.065472 == TX Byte 0 ==
4095 13:40:25.068862 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4096 13:40:25.075527 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4097 13:40:25.075610 == TX Byte 1 ==
4098 13:40:25.078664 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4099 13:40:25.085550 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4100 13:40:25.085664 ==
4101 13:40:25.088811 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 13:40:25.092082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 13:40:25.092183 ==
4104 13:40:25.092270
4105 13:40:25.092352
4106 13:40:25.095603 TX Vref Scan disable
4107 13:40:25.099077 == TX Byte 0 ==
4108 13:40:25.102147 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4109 13:40:25.105676 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4110 13:40:25.108624 == TX Byte 1 ==
4111 13:40:25.112034 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4112 13:40:25.115745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4113 13:40:25.115847
4114 13:40:25.118781 [DATLAT]
4115 13:40:25.118881 Freq=600, CH0 RK0
4116 13:40:25.118968
4117 13:40:25.122091 DATLAT Default: 0x9
4118 13:40:25.122188 0, 0xFFFF, sum = 0
4119 13:40:25.125225 1, 0xFFFF, sum = 0
4120 13:40:25.125327 2, 0xFFFF, sum = 0
4121 13:40:25.128625 3, 0xFFFF, sum = 0
4122 13:40:25.128728 4, 0xFFFF, sum = 0
4123 13:40:25.131834 5, 0xFFFF, sum = 0
4124 13:40:25.131934 6, 0xFFFF, sum = 0
4125 13:40:25.135212 7, 0xFFFF, sum = 0
4126 13:40:25.135313 8, 0x0, sum = 1
4127 13:40:25.138713 9, 0x0, sum = 2
4128 13:40:25.138820 10, 0x0, sum = 3
4129 13:40:25.142234 11, 0x0, sum = 4
4130 13:40:25.142342 best_step = 9
4131 13:40:25.142482
4132 13:40:25.142566 ==
4133 13:40:25.145535 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 13:40:25.148577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 13:40:25.148677 ==
4136 13:40:25.152168 RX Vref Scan: 1
4137 13:40:25.152269
4138 13:40:25.155304 RX Vref 0 -> 0, step: 1
4139 13:40:25.155391
4140 13:40:25.155455 RX Delay -179 -> 252, step: 8
4141 13:40:25.155515
4142 13:40:25.159153 Set Vref, RX VrefLevel [Byte0]: 55
4143 13:40:25.162062 [Byte1]: 51
4144 13:40:25.166907
4145 13:40:25.166989 Final RX Vref Byte 0 = 55 to rank0
4146 13:40:25.170049 Final RX Vref Byte 1 = 51 to rank0
4147 13:40:25.173621 Final RX Vref Byte 0 = 55 to rank1
4148 13:40:25.176654 Final RX Vref Byte 1 = 51 to rank1==
4149 13:40:25.180413 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 13:40:25.183674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 13:40:25.187363 ==
4152 13:40:25.187449 DQS Delay:
4153 13:40:25.187516 DQS0 = 0, DQS1 = 0
4154 13:40:25.190792 DQM Delay:
4155 13:40:25.190909 DQM0 = 43, DQM1 = 33
4156 13:40:25.193582 DQ Delay:
4157 13:40:25.193682 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4158 13:40:25.197301 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4159 13:40:25.200337 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4160 13:40:25.203718 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4161 13:40:25.203801
4162 13:40:25.207084
4163 13:40:25.213442 [DQSOSCAuto] RK0, (LSB)MR18= 0x4726, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4164 13:40:25.216892 CH0 RK0: MR19=808, MR18=4726
4165 13:40:25.223894 CH0_RK0: MR19=0x808, MR18=0x4726, DQSOSC=396, MR23=63, INC=167, DEC=111
4166 13:40:25.223983
4167 13:40:25.227103 ----->DramcWriteLeveling(PI) begin...
4168 13:40:25.227211 ==
4169 13:40:25.230048 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 13:40:25.233746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 13:40:25.233853 ==
4172 13:40:25.236806 Write leveling (Byte 0): 34 => 34
4173 13:40:25.240081 Write leveling (Byte 1): 30 => 30
4174 13:40:25.243487 DramcWriteLeveling(PI) end<-----
4175 13:40:25.243568
4176 13:40:25.243631 ==
4177 13:40:25.246890 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 13:40:25.250526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 13:40:25.250676 ==
4180 13:40:25.254098 [Gating] SW mode calibration
4181 13:40:25.260455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 13:40:25.266848 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 13:40:25.270095 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 13:40:25.273717 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 13:40:25.280332 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 13:40:25.283391 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4187 13:40:25.286872 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4188 13:40:25.293413 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4189 13:40:25.297066 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 13:40:25.300089 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 13:40:25.306734 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 13:40:25.310295 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 13:40:25.313405 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 13:40:25.320027 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4195 13:40:25.323477 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4196 13:40:25.326890 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 13:40:25.330613 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 13:40:25.336663 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 13:40:25.340312 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 13:40:25.343455 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 13:40:25.350064 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 13:40:25.353762 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4203 13:40:25.357222 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 13:40:25.363921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 13:40:25.366821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 13:40:25.370432 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 13:40:25.377265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 13:40:25.380862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 13:40:25.383928 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 13:40:25.390426 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 13:40:25.393440 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 13:40:25.397152 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 13:40:25.404056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 13:40:25.407686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 13:40:25.410404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 13:40:25.413769 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 13:40:25.420629 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 13:40:25.423654 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4219 13:40:25.427330 Total UI for P1: 0, mck2ui 16
4220 13:40:25.430747 best dqsien dly found for B0: ( 0, 13, 10)
4221 13:40:25.434136 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4222 13:40:25.437055 Total UI for P1: 0, mck2ui 16
4223 13:40:25.440688 best dqsien dly found for B1: ( 0, 13, 12)
4224 13:40:25.443623 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4225 13:40:25.447361 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4226 13:40:25.450265
4227 13:40:25.453802 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4228 13:40:25.457355 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4229 13:40:25.460380 [Gating] SW calibration Done
4230 13:40:25.460479 ==
4231 13:40:25.463489 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 13:40:25.467177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 13:40:25.467256 ==
4234 13:40:25.467318 RX Vref Scan: 0
4235 13:40:25.467376
4236 13:40:25.470646 RX Vref 0 -> 0, step: 1
4237 13:40:25.470746
4238 13:40:25.473780 RX Delay -230 -> 252, step: 16
4239 13:40:25.477066 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4240 13:40:25.480395 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4241 13:40:25.487181 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4242 13:40:25.490648 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4243 13:40:25.493582 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4244 13:40:25.497163 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4245 13:40:25.503766 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4246 13:40:25.506978 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 13:40:25.510658 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4248 13:40:25.513703 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4249 13:40:25.516892 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4250 13:40:25.523588 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4251 13:40:25.527071 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4252 13:40:25.530481 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4253 13:40:25.534144 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4254 13:40:25.540474 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4255 13:40:25.540581 ==
4256 13:40:25.543835 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 13:40:25.546867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 13:40:25.546951 ==
4259 13:40:25.547015 DQS Delay:
4260 13:40:25.550608 DQS0 = 0, DQS1 = 0
4261 13:40:25.550690 DQM Delay:
4262 13:40:25.553733 DQM0 = 37, DQM1 = 31
4263 13:40:25.553814 DQ Delay:
4264 13:40:25.557244 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4265 13:40:25.560218 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4266 13:40:25.563810 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4267 13:40:25.567063 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4268 13:40:25.567149
4269 13:40:25.567215
4270 13:40:25.567307 ==
4271 13:40:25.570545 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 13:40:25.573431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 13:40:25.573512 ==
4274 13:40:25.576944
4275 13:40:25.577068
4276 13:40:25.577133 TX Vref Scan disable
4277 13:40:25.580537 == TX Byte 0 ==
4278 13:40:25.583452 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4279 13:40:25.587048 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4280 13:40:25.590266 == TX Byte 1 ==
4281 13:40:25.593377 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 13:40:25.597113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 13:40:25.597201 ==
4284 13:40:25.600126 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 13:40:25.606817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 13:40:25.606909 ==
4287 13:40:25.606975
4288 13:40:25.607035
4289 13:40:25.607092 TX Vref Scan disable
4290 13:40:25.611497 == TX Byte 0 ==
4291 13:40:25.615098 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4292 13:40:25.618178 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4293 13:40:25.621720 == TX Byte 1 ==
4294 13:40:25.624785 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4295 13:40:25.628161 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4296 13:40:25.631522
4297 13:40:25.631604 [DATLAT]
4298 13:40:25.631668 Freq=600, CH0 RK1
4299 13:40:25.631727
4300 13:40:25.634649 DATLAT Default: 0x9
4301 13:40:25.634730 0, 0xFFFF, sum = 0
4302 13:40:25.638527 1, 0xFFFF, sum = 0
4303 13:40:25.638617 2, 0xFFFF, sum = 0
4304 13:40:25.641533 3, 0xFFFF, sum = 0
4305 13:40:25.641632 4, 0xFFFF, sum = 0
4306 13:40:25.645039 5, 0xFFFF, sum = 0
4307 13:40:25.648251 6, 0xFFFF, sum = 0
4308 13:40:25.648336 7, 0xFFFF, sum = 0
4309 13:40:25.648400 8, 0x0, sum = 1
4310 13:40:25.651695 9, 0x0, sum = 2
4311 13:40:25.651777 10, 0x0, sum = 3
4312 13:40:25.655062 11, 0x0, sum = 4
4313 13:40:25.655143 best_step = 9
4314 13:40:25.655206
4315 13:40:25.655265 ==
4316 13:40:25.658322 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 13:40:25.664677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 13:40:25.664764 ==
4319 13:40:25.664828 RX Vref Scan: 0
4320 13:40:25.664887
4321 13:40:25.668401 RX Vref 0 -> 0, step: 1
4322 13:40:25.668484
4323 13:40:25.671388 RX Delay -195 -> 252, step: 8
4324 13:40:25.675077 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4325 13:40:25.681304 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4326 13:40:25.684799 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4327 13:40:25.687878 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4328 13:40:25.691346 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4329 13:40:25.694962 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4330 13:40:25.701501 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4331 13:40:25.704601 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4332 13:40:25.708120 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4333 13:40:25.711314 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4334 13:40:25.718383 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4335 13:40:25.721466 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4336 13:40:25.724960 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4337 13:40:25.728387 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4338 13:40:25.731474 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4339 13:40:25.738090 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4340 13:40:25.738181 ==
4341 13:40:25.741900 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 13:40:25.744789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 13:40:25.744886 ==
4344 13:40:25.744985 DQS Delay:
4345 13:40:25.748027 DQS0 = 0, DQS1 = 0
4346 13:40:25.748095 DQM Delay:
4347 13:40:25.751817 DQM0 = 39, DQM1 = 32
4348 13:40:25.751897 DQ Delay:
4349 13:40:25.755194 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4350 13:40:25.758385 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4351 13:40:25.761421 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4352 13:40:25.765127 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4353 13:40:25.765216
4354 13:40:25.765276
4355 13:40:25.771661 [DQSOSCAuto] RK1, (LSB)MR18= 0x472a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4356 13:40:25.775233 CH0 RK1: MR19=808, MR18=472A
4357 13:40:25.781408 CH0_RK1: MR19=0x808, MR18=0x472A, DQSOSC=396, MR23=63, INC=167, DEC=111
4358 13:40:25.785212 [RxdqsGatingPostProcess] freq 600
4359 13:40:25.791689 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 13:40:25.795273 Pre-setting of DQS Precalculation
4361 13:40:25.798377 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 13:40:25.798450 ==
4363 13:40:25.801878 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 13:40:25.805187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 13:40:25.805260 ==
4366 13:40:25.811541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 13:40:25.818464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4368 13:40:25.821926 [CA 0] Center 35 (5~66) winsize 62
4369 13:40:25.825085 [CA 1] Center 35 (5~65) winsize 61
4370 13:40:25.828484 [CA 2] Center 34 (4~65) winsize 62
4371 13:40:25.832143 [CA 3] Center 33 (3~64) winsize 62
4372 13:40:25.834884 [CA 4] Center 34 (3~65) winsize 63
4373 13:40:25.838695 [CA 5] Center 33 (3~64) winsize 62
4374 13:40:25.838786
4375 13:40:25.842303 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4376 13:40:25.842376
4377 13:40:25.845288 [CATrainingPosCal] consider 1 rank data
4378 13:40:25.848480 u2DelayCellTimex100 = 270/100 ps
4379 13:40:25.851826 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 13:40:25.855533 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4381 13:40:25.858579 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 13:40:25.862324 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 13:40:25.865308 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4384 13:40:25.868642 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 13:40:25.868724
4386 13:40:25.875060 CA PerBit enable=1, Macro0, CA PI delay=33
4387 13:40:25.875163
4388 13:40:25.878466 [CBTSetCACLKResult] CA Dly = 33
4389 13:40:25.878607 CS Dly: 4 (0~35)
4390 13:40:25.878672 ==
4391 13:40:25.881659 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 13:40:25.885244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 13:40:25.885329 ==
4394 13:40:25.891599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 13:40:25.898586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4396 13:40:25.901548 [CA 0] Center 35 (5~66) winsize 62
4397 13:40:25.905225 [CA 1] Center 35 (5~66) winsize 62
4398 13:40:25.908200 [CA 2] Center 34 (4~65) winsize 62
4399 13:40:25.911887 [CA 3] Center 34 (3~65) winsize 63
4400 13:40:25.915222 [CA 4] Center 34 (3~65) winsize 63
4401 13:40:25.918539 [CA 5] Center 33 (3~64) winsize 62
4402 13:40:25.918628
4403 13:40:25.922178 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4404 13:40:25.922277
4405 13:40:25.925279 [CATrainingPosCal] consider 2 rank data
4406 13:40:25.928866 u2DelayCellTimex100 = 270/100 ps
4407 13:40:25.931802 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 13:40:25.935501 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4409 13:40:25.938902 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 13:40:25.941951 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 13:40:25.945334 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4412 13:40:25.948555 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 13:40:25.948637
4414 13:40:25.955348 CA PerBit enable=1, Macro0, CA PI delay=33
4415 13:40:25.955430
4416 13:40:25.955493 [CBTSetCACLKResult] CA Dly = 33
4417 13:40:25.958803 CS Dly: 5 (0~38)
4418 13:40:25.958882
4419 13:40:25.962043 ----->DramcWriteLeveling(PI) begin...
4420 13:40:25.962126 ==
4421 13:40:25.965531 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 13:40:25.968399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 13:40:25.968480 ==
4424 13:40:25.972174 Write leveling (Byte 0): 29 => 29
4425 13:40:25.975576 Write leveling (Byte 1): 31 => 31
4426 13:40:25.978552 DramcWriteLeveling(PI) end<-----
4427 13:40:25.978635
4428 13:40:25.978699 ==
4429 13:40:25.982227 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 13:40:25.985778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 13:40:25.988535 ==
4432 13:40:25.988610 [Gating] SW mode calibration
4433 13:40:25.998819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 13:40:26.002001 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 13:40:26.005349 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4436 13:40:26.012279 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 13:40:26.015343 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 13:40:26.018991 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
4439 13:40:26.025322 0 9 16 | B1->B0 | 2727 2323 | 1 1 | (1 0) (1 0)
4440 13:40:26.028937 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 13:40:26.032626 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 13:40:26.038788 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4443 13:40:26.042082 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 13:40:26.045628 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 13:40:26.048741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 13:40:26.055258 0 10 12 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
4447 13:40:26.058808 0 10 16 | B1->B0 | 3c3c 4141 | 1 0 | (0 0) (0 0)
4448 13:40:26.061893 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 13:40:26.069087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 13:40:26.072105 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 13:40:26.075739 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 13:40:26.082320 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 13:40:26.085713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 13:40:26.088748 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 13:40:26.095306 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4456 13:40:26.099094 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 13:40:26.102475 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 13:40:26.108661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 13:40:26.112075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 13:40:26.115491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 13:40:26.122117 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 13:40:26.125328 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 13:40:26.128843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 13:40:26.135409 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 13:40:26.138549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 13:40:26.142348 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 13:40:26.145434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 13:40:26.151906 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 13:40:26.155353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 13:40:26.158958 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 13:40:26.165711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 13:40:26.168677 Total UI for P1: 0, mck2ui 16
4473 13:40:26.172246 best dqsien dly found for B0: ( 0, 13, 14)
4474 13:40:26.172346 Total UI for P1: 0, mck2ui 16
4475 13:40:26.178925 best dqsien dly found for B1: ( 0, 13, 14)
4476 13:40:26.182017 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4477 13:40:26.185500 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4478 13:40:26.185585
4479 13:40:26.189131 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4480 13:40:26.192185 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4481 13:40:26.195320 [Gating] SW calibration Done
4482 13:40:26.195412 ==
4483 13:40:26.199228 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 13:40:26.202474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 13:40:26.202565 ==
4486 13:40:26.206131 RX Vref Scan: 0
4487 13:40:26.206216
4488 13:40:26.206280 RX Vref 0 -> 0, step: 1
4489 13:40:26.206341
4490 13:40:26.208835 RX Delay -230 -> 252, step: 16
4491 13:40:26.215625 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4492 13:40:26.219489 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4493 13:40:26.222534 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4494 13:40:26.225821 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4495 13:40:26.229299 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4496 13:40:26.235930 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4497 13:40:26.238884 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4498 13:40:26.242397 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4499 13:40:26.245988 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4500 13:40:26.248868 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4501 13:40:26.255474 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4502 13:40:26.259168 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4503 13:40:26.262544 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4504 13:40:26.265823 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4505 13:40:26.272371 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4506 13:40:26.275388 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4507 13:40:26.275480 ==
4508 13:40:26.278764 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 13:40:26.282428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 13:40:26.282516 ==
4511 13:40:26.285539 DQS Delay:
4512 13:40:26.285630 DQS0 = 0, DQS1 = 0
4513 13:40:26.285751 DQM Delay:
4514 13:40:26.289178 DQM0 = 43, DQM1 = 35
4515 13:40:26.289263 DQ Delay:
4516 13:40:26.292315 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4517 13:40:26.295191 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4518 13:40:26.298937 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4519 13:40:26.302390 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4520 13:40:26.302477
4521 13:40:26.302541
4522 13:40:26.302600 ==
4523 13:40:26.305508 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 13:40:26.311993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 13:40:26.312090 ==
4526 13:40:26.312155
4527 13:40:26.312249
4528 13:40:26.312309 TX Vref Scan disable
4529 13:40:26.316210 == TX Byte 0 ==
4530 13:40:26.319288 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4531 13:40:26.322657 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4532 13:40:26.325677 == TX Byte 1 ==
4533 13:40:26.329258 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 13:40:26.332297 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 13:40:26.335996 ==
4536 13:40:26.339611 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 13:40:26.342672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 13:40:26.342758 ==
4539 13:40:26.342822
4540 13:40:26.342881
4541 13:40:26.346036 TX Vref Scan disable
4542 13:40:26.346129 == TX Byte 0 ==
4543 13:40:26.352404 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4544 13:40:26.356240 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4545 13:40:26.356329 == TX Byte 1 ==
4546 13:40:26.362804 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 13:40:26.366208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 13:40:26.366294
4549 13:40:26.366358 [DATLAT]
4550 13:40:26.369088 Freq=600, CH1 RK0
4551 13:40:26.369175
4552 13:40:26.369280 DATLAT Default: 0x9
4553 13:40:26.372495 0, 0xFFFF, sum = 0
4554 13:40:26.372605 1, 0xFFFF, sum = 0
4555 13:40:26.376043 2, 0xFFFF, sum = 0
4556 13:40:26.376134 3, 0xFFFF, sum = 0
4557 13:40:26.379129 4, 0xFFFF, sum = 0
4558 13:40:26.379212 5, 0xFFFF, sum = 0
4559 13:40:26.382659 6, 0xFFFF, sum = 0
4560 13:40:26.386118 7, 0xFFFF, sum = 0
4561 13:40:26.386205 8, 0x0, sum = 1
4562 13:40:26.386271 9, 0x0, sum = 2
4563 13:40:26.389340 10, 0x0, sum = 3
4564 13:40:26.389422 11, 0x0, sum = 4
4565 13:40:26.392296 best_step = 9
4566 13:40:26.392377
4567 13:40:26.392441 ==
4568 13:40:26.395921 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 13:40:26.399691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 13:40:26.399778 ==
4571 13:40:26.402457 RX Vref Scan: 1
4572 13:40:26.402540
4573 13:40:26.402603 RX Vref 0 -> 0, step: 1
4574 13:40:26.402662
4575 13:40:26.405858 RX Delay -195 -> 252, step: 8
4576 13:40:26.405945
4577 13:40:26.409557 Set Vref, RX VrefLevel [Byte0]: 56
4578 13:40:26.412530 [Byte1]: 51
4579 13:40:26.416253
4580 13:40:26.416334 Final RX Vref Byte 0 = 56 to rank0
4581 13:40:26.419581 Final RX Vref Byte 1 = 51 to rank0
4582 13:40:26.423029 Final RX Vref Byte 0 = 56 to rank1
4583 13:40:26.426353 Final RX Vref Byte 1 = 51 to rank1==
4584 13:40:26.429651 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 13:40:26.436795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 13:40:26.436887 ==
4587 13:40:26.436952 DQS Delay:
4588 13:40:26.437054 DQS0 = 0, DQS1 = 0
4589 13:40:26.439999 DQM Delay:
4590 13:40:26.440083 DQM0 = 40, DQM1 = 33
4591 13:40:26.443463 DQ Delay:
4592 13:40:26.446496 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4593 13:40:26.446581 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4594 13:40:26.449517 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4595 13:40:26.456726 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4596 13:40:26.456850
4597 13:40:26.456942
4598 13:40:26.463036 [DQSOSCAuto] RK0, (LSB)MR18= 0x470c, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4599 13:40:26.466522 CH1 RK0: MR19=808, MR18=470C
4600 13:40:26.473393 CH1_RK0: MR19=0x808, MR18=0x470C, DQSOSC=396, MR23=63, INC=167, DEC=111
4601 13:40:26.473488
4602 13:40:26.476652 ----->DramcWriteLeveling(PI) begin...
4603 13:40:26.476735 ==
4604 13:40:26.479621 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 13:40:26.483248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 13:40:26.483339 ==
4607 13:40:26.486126 Write leveling (Byte 0): 30 => 30
4608 13:40:26.489912 Write leveling (Byte 1): 31 => 31
4609 13:40:26.493003 DramcWriteLeveling(PI) end<-----
4610 13:40:26.493100
4611 13:40:26.493164 ==
4612 13:40:26.496425 Dram Type= 6, Freq= 0, CH_1, rank 1
4613 13:40:26.499695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 13:40:26.499780 ==
4615 13:40:26.503296 [Gating] SW mode calibration
4616 13:40:26.509848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4617 13:40:26.516574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4618 13:40:26.519520 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 13:40:26.523273 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 13:40:26.530073 0 9 8 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)
4621 13:40:26.532896 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (1 1) (1 1)
4622 13:40:26.536260 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
4623 13:40:26.543117 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4624 13:40:26.546399 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 13:40:26.550102 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 13:40:26.556676 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 13:40:26.560280 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 13:40:26.563009 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4629 13:40:26.569573 0 10 12 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
4630 13:40:26.573355 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4631 13:40:26.576703 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 13:40:26.579629 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 13:40:26.586398 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 13:40:26.590095 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 13:40:26.593295 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 13:40:26.599992 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 13:40:26.603449 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 13:40:26.606449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4639 13:40:26.613122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 13:40:26.616642 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 13:40:26.620155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 13:40:26.626488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 13:40:26.630377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 13:40:26.633168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 13:40:26.640059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 13:40:26.643431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 13:40:26.646870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 13:40:26.653394 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 13:40:26.656482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 13:40:26.659702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 13:40:26.663055 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 13:40:26.669734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 13:40:26.673167 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4654 13:40:26.676679 Total UI for P1: 0, mck2ui 16
4655 13:40:26.680413 best dqsien dly found for B0: ( 0, 13, 10)
4656 13:40:26.683229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 13:40:26.686363 Total UI for P1: 0, mck2ui 16
4658 13:40:26.690410 best dqsien dly found for B1: ( 0, 13, 12)
4659 13:40:26.693121 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4660 13:40:26.696712 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4661 13:40:26.699731
4662 13:40:26.703409 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4663 13:40:26.706547 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4664 13:40:26.709751 [Gating] SW calibration Done
4665 13:40:26.709832 ==
4666 13:40:26.713236 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 13:40:26.716863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 13:40:26.716943 ==
4669 13:40:26.717042 RX Vref Scan: 0
4670 13:40:26.719954
4671 13:40:26.720034 RX Vref 0 -> 0, step: 1
4672 13:40:26.720096
4673 13:40:26.723523 RX Delay -230 -> 252, step: 16
4674 13:40:26.726409 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4675 13:40:26.733416 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4676 13:40:26.736859 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4677 13:40:26.740078 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4678 13:40:26.743071 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4679 13:40:26.746278 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4680 13:40:26.752967 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4681 13:40:26.756379 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4682 13:40:26.760099 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4683 13:40:26.763627 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4684 13:40:26.766794 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4685 13:40:26.773212 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4686 13:40:26.776659 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4687 13:40:26.779918 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4688 13:40:26.783109 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4689 13:40:26.790085 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4690 13:40:26.790175 ==
4691 13:40:26.793277 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 13:40:26.796663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 13:40:26.796747 ==
4694 13:40:26.796811 DQS Delay:
4695 13:40:26.799935 DQS0 = 0, DQS1 = 0
4696 13:40:26.800017 DQM Delay:
4697 13:40:26.803223 DQM0 = 43, DQM1 = 36
4698 13:40:26.803303 DQ Delay:
4699 13:40:26.806499 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4700 13:40:26.809953 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4701 13:40:26.813598 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4702 13:40:26.816707 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4703 13:40:26.816787
4704 13:40:26.816851
4705 13:40:26.816911 ==
4706 13:40:26.820483 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 13:40:26.823510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 13:40:26.823591 ==
4709 13:40:26.823655
4710 13:40:26.823715
4711 13:40:26.826678 TX Vref Scan disable
4712 13:40:26.830316 == TX Byte 0 ==
4713 13:40:26.833723 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4714 13:40:26.836863 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4715 13:40:26.840158 == TX Byte 1 ==
4716 13:40:26.843790 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4717 13:40:26.847208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4718 13:40:26.847291 ==
4719 13:40:26.849934 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 13:40:26.856739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 13:40:26.856846 ==
4722 13:40:26.856938
4723 13:40:26.857047
4724 13:40:26.857105 TX Vref Scan disable
4725 13:40:26.861343 == TX Byte 0 ==
4726 13:40:26.864452 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4727 13:40:26.867647 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4728 13:40:26.870884 == TX Byte 1 ==
4729 13:40:26.874427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4730 13:40:26.878079 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4731 13:40:26.880951
4732 13:40:26.881069 [DATLAT]
4733 13:40:26.881134 Freq=600, CH1 RK1
4734 13:40:26.881195
4735 13:40:26.884471 DATLAT Default: 0x9
4736 13:40:26.884553 0, 0xFFFF, sum = 0
4737 13:40:26.887566 1, 0xFFFF, sum = 0
4738 13:40:26.887648 2, 0xFFFF, sum = 0
4739 13:40:26.890890 3, 0xFFFF, sum = 0
4740 13:40:26.890973 4, 0xFFFF, sum = 0
4741 13:40:26.894278 5, 0xFFFF, sum = 0
4742 13:40:26.894361 6, 0xFFFF, sum = 0
4743 13:40:26.898290 7, 0xFFFF, sum = 0
4744 13:40:26.898373 8, 0x0, sum = 1
4745 13:40:26.900942 9, 0x0, sum = 2
4746 13:40:26.901047 10, 0x0, sum = 3
4747 13:40:26.904833 11, 0x0, sum = 4
4748 13:40:26.904916 best_step = 9
4749 13:40:26.904986
4750 13:40:26.905078 ==
4751 13:40:26.907682 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 13:40:26.914372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 13:40:26.914457 ==
4754 13:40:26.914521 RX Vref Scan: 0
4755 13:40:26.914581
4756 13:40:26.917943 RX Vref 0 -> 0, step: 1
4757 13:40:26.918025
4758 13:40:26.920892 RX Delay -179 -> 252, step: 8
4759 13:40:26.924662 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4760 13:40:26.931419 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4761 13:40:26.934253 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4762 13:40:26.937851 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4763 13:40:26.941398 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4764 13:40:26.944560 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4765 13:40:26.951475 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4766 13:40:26.954600 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4767 13:40:26.958319 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4768 13:40:26.961351 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4769 13:40:26.964659 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4770 13:40:26.971656 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4771 13:40:26.974441 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4772 13:40:26.978156 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4773 13:40:26.981474 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4774 13:40:26.988280 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4775 13:40:26.988368 ==
4776 13:40:26.991605 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 13:40:26.994699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 13:40:26.994782 ==
4779 13:40:26.994845 DQS Delay:
4780 13:40:26.998131 DQS0 = 0, DQS1 = 0
4781 13:40:26.998212 DQM Delay:
4782 13:40:27.001795 DQM0 = 38, DQM1 = 32
4783 13:40:27.001917 DQ Delay:
4784 13:40:27.004575 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4785 13:40:27.007998 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4786 13:40:27.011745 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4787 13:40:27.014921 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4788 13:40:27.015060
4789 13:40:27.015130
4790 13:40:27.021439 [DQSOSCAuto] RK1, (LSB)MR18= 0x3947, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4791 13:40:27.024865 CH1 RK1: MR19=808, MR18=3947
4792 13:40:27.031671 CH1_RK1: MR19=0x808, MR18=0x3947, DQSOSC=396, MR23=63, INC=167, DEC=111
4793 13:40:27.034636 [RxdqsGatingPostProcess] freq 600
4794 13:40:27.041778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4795 13:40:27.044906 Pre-setting of DQS Precalculation
4796 13:40:27.048458 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4797 13:40:27.054794 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4798 13:40:27.061430 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4799 13:40:27.061576
4800 13:40:27.061648
4801 13:40:27.065149 [Calibration Summary] 1200 Mbps
4802 13:40:27.068042 CH 0, Rank 0
4803 13:40:27.068276 SW Impedance : PASS
4804 13:40:27.071603 DUTY Scan : NO K
4805 13:40:27.071756 ZQ Calibration : PASS
4806 13:40:27.074670 Jitter Meter : NO K
4807 13:40:27.078315 CBT Training : PASS
4808 13:40:27.078403 Write leveling : PASS
4809 13:40:27.081373 RX DQS gating : PASS
4810 13:40:27.084899 RX DQ/DQS(RDDQC) : PASS
4811 13:40:27.085027 TX DQ/DQS : PASS
4812 13:40:27.088507 RX DATLAT : PASS
4813 13:40:27.091400 RX DQ/DQS(Engine): PASS
4814 13:40:27.091482 TX OE : NO K
4815 13:40:27.095066 All Pass.
4816 13:40:27.095147
4817 13:40:27.095211 CH 0, Rank 1
4818 13:40:27.098067 SW Impedance : PASS
4819 13:40:27.098147 DUTY Scan : NO K
4820 13:40:27.101645 ZQ Calibration : PASS
4821 13:40:27.104753 Jitter Meter : NO K
4822 13:40:27.104859 CBT Training : PASS
4823 13:40:27.108150 Write leveling : PASS
4824 13:40:27.111775 RX DQS gating : PASS
4825 13:40:27.111862 RX DQ/DQS(RDDQC) : PASS
4826 13:40:27.114841 TX DQ/DQS : PASS
4827 13:40:27.114922 RX DATLAT : PASS
4828 13:40:27.118591 RX DQ/DQS(Engine): PASS
4829 13:40:27.121680 TX OE : NO K
4830 13:40:27.121765 All Pass.
4831 13:40:27.121829
4832 13:40:27.121888 CH 1, Rank 0
4833 13:40:27.125279 SW Impedance : PASS
4834 13:40:27.128322 DUTY Scan : NO K
4835 13:40:27.128402 ZQ Calibration : PASS
4836 13:40:27.131488 Jitter Meter : NO K
4837 13:40:27.134962 CBT Training : PASS
4838 13:40:27.135044 Write leveling : PASS
4839 13:40:27.138395 RX DQS gating : PASS
4840 13:40:27.141911 RX DQ/DQS(RDDQC) : PASS
4841 13:40:27.141997 TX DQ/DQS : PASS
4842 13:40:27.144965 RX DATLAT : PASS
4843 13:40:27.148285 RX DQ/DQS(Engine): PASS
4844 13:40:27.148366 TX OE : NO K
4845 13:40:27.148431 All Pass.
4846 13:40:27.148491
4847 13:40:27.151794 CH 1, Rank 1
4848 13:40:27.154971 SW Impedance : PASS
4849 13:40:27.155051 DUTY Scan : NO K
4850 13:40:27.158403 ZQ Calibration : PASS
4851 13:40:27.158485 Jitter Meter : NO K
4852 13:40:27.161935 CBT Training : PASS
4853 13:40:27.164890 Write leveling : PASS
4854 13:40:27.165029 RX DQS gating : PASS
4855 13:40:27.168525 RX DQ/DQS(RDDQC) : PASS
4856 13:40:27.171550 TX DQ/DQS : PASS
4857 13:40:27.171656 RX DATLAT : PASS
4858 13:40:27.174972 RX DQ/DQS(Engine): PASS
4859 13:40:27.178588 TX OE : NO K
4860 13:40:27.178671 All Pass.
4861 13:40:27.178735
4862 13:40:27.178795 DramC Write-DBI off
4863 13:40:27.181613 PER_BANK_REFRESH: Hybrid Mode
4864 13:40:27.185175 TX_TRACKING: ON
4865 13:40:27.192107 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4866 13:40:27.194836 [FAST_K] Save calibration result to emmc
4867 13:40:27.202277 dramc_set_vcore_voltage set vcore to 662500
4868 13:40:27.202367 Read voltage for 933, 3
4869 13:40:27.205161 Vio18 = 0
4870 13:40:27.205242 Vcore = 662500
4871 13:40:27.205306 Vdram = 0
4872 13:40:27.205366 Vddq = 0
4873 13:40:27.208658 Vmddr = 0
4874 13:40:27.211971 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4875 13:40:27.218598 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4876 13:40:27.221591 MEM_TYPE=3, freq_sel=17
4877 13:40:27.221682 sv_algorithm_assistance_LP4_1600
4878 13:40:27.228796 ============ PULL DRAM RESETB DOWN ============
4879 13:40:27.231996 ========== PULL DRAM RESETB DOWN end =========
4880 13:40:27.235474 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4881 13:40:27.239126 ===================================
4882 13:40:27.242382 LPDDR4 DRAM CONFIGURATION
4883 13:40:27.245414 ===================================
4884 13:40:27.248777 EX_ROW_EN[0] = 0x0
4885 13:40:27.248920 EX_ROW_EN[1] = 0x0
4886 13:40:27.251989 LP4Y_EN = 0x0
4887 13:40:27.252120 WORK_FSP = 0x0
4888 13:40:27.255633 WL = 0x3
4889 13:40:27.255776 RL = 0x3
4890 13:40:27.258619 BL = 0x2
4891 13:40:27.258739 RPST = 0x0
4892 13:40:27.261664 RD_PRE = 0x0
4893 13:40:27.261763 WR_PRE = 0x1
4894 13:40:27.265258 WR_PST = 0x0
4895 13:40:27.265375 DBI_WR = 0x0
4896 13:40:27.268765 DBI_RD = 0x0
4897 13:40:27.268872 OTF = 0x1
4898 13:40:27.271809 ===================================
4899 13:40:27.275614 ===================================
4900 13:40:27.278387 ANA top config
4901 13:40:27.281905 ===================================
4902 13:40:27.284938 DLL_ASYNC_EN = 0
4903 13:40:27.285056 ALL_SLAVE_EN = 1
4904 13:40:27.288380 NEW_RANK_MODE = 1
4905 13:40:27.291633 DLL_IDLE_MODE = 1
4906 13:40:27.295183 LP45_APHY_COMB_EN = 1
4907 13:40:27.295264 TX_ODT_DIS = 1
4908 13:40:27.298691 NEW_8X_MODE = 1
4909 13:40:27.301793 ===================================
4910 13:40:27.305216 ===================================
4911 13:40:27.308354 data_rate = 1866
4912 13:40:27.311876 CKR = 1
4913 13:40:27.315170 DQ_P2S_RATIO = 8
4914 13:40:27.318724 ===================================
4915 13:40:27.321716 CA_P2S_RATIO = 8
4916 13:40:27.321798 DQ_CA_OPEN = 0
4917 13:40:27.325074 DQ_SEMI_OPEN = 0
4918 13:40:27.328482 CA_SEMI_OPEN = 0
4919 13:40:27.331559 CA_FULL_RATE = 0
4920 13:40:27.335328 DQ_CKDIV4_EN = 1
4921 13:40:27.335409 CA_CKDIV4_EN = 1
4922 13:40:27.338403 CA_PREDIV_EN = 0
4923 13:40:27.342154 PH8_DLY = 0
4924 13:40:27.345537 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4925 13:40:27.348558 DQ_AAMCK_DIV = 4
4926 13:40:27.352033 CA_AAMCK_DIV = 4
4927 13:40:27.352114 CA_ADMCK_DIV = 4
4928 13:40:27.355085 DQ_TRACK_CA_EN = 0
4929 13:40:27.358481 CA_PICK = 933
4930 13:40:27.361687 CA_MCKIO = 933
4931 13:40:27.365223 MCKIO_SEMI = 0
4932 13:40:27.368404 PLL_FREQ = 3732
4933 13:40:27.371653 DQ_UI_PI_RATIO = 32
4934 13:40:27.371734 CA_UI_PI_RATIO = 0
4935 13:40:27.375116 ===================================
4936 13:40:27.378689 ===================================
4937 13:40:27.382004 memory_type:LPDDR4
4938 13:40:27.385289 GP_NUM : 10
4939 13:40:27.385371 SRAM_EN : 1
4940 13:40:27.388322 MD32_EN : 0
4941 13:40:27.391790 ===================================
4942 13:40:27.394996 [ANA_INIT] >>>>>>>>>>>>>>
4943 13:40:27.398401 <<<<<< [CONFIGURE PHASE]: ANA_TX
4944 13:40:27.402037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4945 13:40:27.404894 ===================================
4946 13:40:27.405038 data_rate = 1866,PCW = 0X8f00
4947 13:40:27.408332 ===================================
4948 13:40:27.412087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4949 13:40:27.418713 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 13:40:27.425474 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 13:40:27.428408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4952 13:40:27.432054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4953 13:40:27.434844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4954 13:40:27.438347 [ANA_INIT] flow start
4955 13:40:27.438428 [ANA_INIT] PLL >>>>>>>>
4956 13:40:27.441534 [ANA_INIT] PLL <<<<<<<<
4957 13:40:27.444926 [ANA_INIT] MIDPI >>>>>>>>
4958 13:40:27.448575 [ANA_INIT] MIDPI <<<<<<<<
4959 13:40:27.448656 [ANA_INIT] DLL >>>>>>>>
4960 13:40:27.451615 [ANA_INIT] flow end
4961 13:40:27.454843 ============ LP4 DIFF to SE enter ============
4962 13:40:27.458156 ============ LP4 DIFF to SE exit ============
4963 13:40:27.461849 [ANA_INIT] <<<<<<<<<<<<<
4964 13:40:27.465399 [Flow] Enable top DCM control >>>>>
4965 13:40:27.468125 [Flow] Enable top DCM control <<<<<
4966 13:40:27.471417 Enable DLL master slave shuffle
4967 13:40:27.478199 ==============================================================
4968 13:40:27.478282 Gating Mode config
4969 13:40:27.485135 ==============================================================
4970 13:40:27.485222 Config description:
4971 13:40:27.495138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4972 13:40:27.501768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4973 13:40:27.508369 SELPH_MODE 0: By rank 1: By Phase
4974 13:40:27.511764 ==============================================================
4975 13:40:27.515304 GAT_TRACK_EN = 1
4976 13:40:27.518290 RX_GATING_MODE = 2
4977 13:40:27.522007 RX_GATING_TRACK_MODE = 2
4978 13:40:27.524892 SELPH_MODE = 1
4979 13:40:27.528713 PICG_EARLY_EN = 1
4980 13:40:27.531812 VALID_LAT_VALUE = 1
4981 13:40:27.535218 ==============================================================
4982 13:40:27.538197 Enter into Gating configuration >>>>
4983 13:40:27.541932 Exit from Gating configuration <<<<
4984 13:40:27.545271 Enter into DVFS_PRE_config >>>>>
4985 13:40:27.558285 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4986 13:40:27.558390 Exit from DVFS_PRE_config <<<<<
4987 13:40:27.561430 Enter into PICG configuration >>>>
4988 13:40:27.564893 Exit from PICG configuration <<<<
4989 13:40:27.568364 [RX_INPUT] configuration >>>>>
4990 13:40:27.571489 [RX_INPUT] configuration <<<<<
4991 13:40:27.578114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4992 13:40:27.581975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4993 13:40:27.588226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4994 13:40:27.595187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4995 13:40:27.601630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 13:40:27.608345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 13:40:27.611461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4998 13:40:27.614918 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4999 13:40:27.618558 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5000 13:40:27.624732 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5001 13:40:27.628314 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5002 13:40:27.631490 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5003 13:40:27.635130 ===================================
5004 13:40:27.638295 LPDDR4 DRAM CONFIGURATION
5005 13:40:27.641742 ===================================
5006 13:40:27.641827 EX_ROW_EN[0] = 0x0
5007 13:40:27.644968 EX_ROW_EN[1] = 0x0
5008 13:40:27.648550 LP4Y_EN = 0x0
5009 13:40:27.648620 WORK_FSP = 0x0
5010 13:40:27.651620 WL = 0x3
5011 13:40:27.651692 RL = 0x3
5012 13:40:27.654999 BL = 0x2
5013 13:40:27.655072 RPST = 0x0
5014 13:40:27.658046 RD_PRE = 0x0
5015 13:40:27.658117 WR_PRE = 0x1
5016 13:40:27.661672 WR_PST = 0x0
5017 13:40:27.661747 DBI_WR = 0x0
5018 13:40:27.665269 DBI_RD = 0x0
5019 13:40:27.665338 OTF = 0x1
5020 13:40:27.668163 ===================================
5021 13:40:27.671550 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5022 13:40:27.678476 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5023 13:40:27.681869 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 13:40:27.684766 ===================================
5025 13:40:27.688301 LPDDR4 DRAM CONFIGURATION
5026 13:40:27.691518 ===================================
5027 13:40:27.691598 EX_ROW_EN[0] = 0x10
5028 13:40:27.694858 EX_ROW_EN[1] = 0x0
5029 13:40:27.694932 LP4Y_EN = 0x0
5030 13:40:27.698394 WORK_FSP = 0x0
5031 13:40:27.698494 WL = 0x3
5032 13:40:27.701596 RL = 0x3
5033 13:40:27.701667 BL = 0x2
5034 13:40:27.704978 RPST = 0x0
5035 13:40:27.705054 RD_PRE = 0x0
5036 13:40:27.708282 WR_PRE = 0x1
5037 13:40:27.711862 WR_PST = 0x0
5038 13:40:27.711936 DBI_WR = 0x0
5039 13:40:27.714854 DBI_RD = 0x0
5040 13:40:27.714927 OTF = 0x1
5041 13:40:27.718506 ===================================
5042 13:40:27.725001 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5043 13:40:27.728486 nWR fixed to 30
5044 13:40:27.731508 [ModeRegInit_LP4] CH0 RK0
5045 13:40:27.731642 [ModeRegInit_LP4] CH0 RK1
5046 13:40:27.735187 [ModeRegInit_LP4] CH1 RK0
5047 13:40:27.738246 [ModeRegInit_LP4] CH1 RK1
5048 13:40:27.738332 match AC timing 9
5049 13:40:27.744799 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5050 13:40:27.748418 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5051 13:40:27.752078 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5052 13:40:27.758720 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5053 13:40:27.762047 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5054 13:40:27.762197 ==
5055 13:40:27.764896 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 13:40:27.768630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 13:40:27.768718 ==
5058 13:40:27.775281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 13:40:27.782341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5060 13:40:27.785563 [CA 0] Center 38 (7~69) winsize 63
5061 13:40:27.788634 [CA 1] Center 38 (7~69) winsize 63
5062 13:40:27.792042 [CA 2] Center 35 (5~66) winsize 62
5063 13:40:27.795509 [CA 3] Center 35 (5~66) winsize 62
5064 13:40:27.798625 [CA 4] Center 33 (3~64) winsize 62
5065 13:40:27.802340 [CA 5] Center 33 (3~64) winsize 62
5066 13:40:27.802433
5067 13:40:27.805216 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5068 13:40:27.805300
5069 13:40:27.808301 [CATrainingPosCal] consider 1 rank data
5070 13:40:27.811943 u2DelayCellTimex100 = 270/100 ps
5071 13:40:27.815119 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 13:40:27.818562 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5073 13:40:27.821485 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5074 13:40:27.824891 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5075 13:40:27.828704 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 13:40:27.831585 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5077 13:40:27.831663
5078 13:40:27.838209 CA PerBit enable=1, Macro0, CA PI delay=33
5079 13:40:27.838280
5080 13:40:27.838341 [CBTSetCACLKResult] CA Dly = 33
5081 13:40:27.841849 CS Dly: 6 (0~37)
5082 13:40:27.841925 ==
5083 13:40:27.844868 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 13:40:27.848464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 13:40:27.848534 ==
5086 13:40:27.855202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 13:40:27.861780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5088 13:40:27.865339 [CA 0] Center 38 (8~69) winsize 62
5089 13:40:27.868593 [CA 1] Center 38 (7~69) winsize 63
5090 13:40:27.871748 [CA 2] Center 35 (5~66) winsize 62
5091 13:40:27.874947 [CA 3] Center 35 (4~66) winsize 63
5092 13:40:27.878498 [CA 4] Center 33 (3~64) winsize 62
5093 13:40:27.882012 [CA 5] Center 33 (3~64) winsize 62
5094 13:40:27.882083
5095 13:40:27.885238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5096 13:40:27.885308
5097 13:40:27.888381 [CATrainingPosCal] consider 2 rank data
5098 13:40:27.891926 u2DelayCellTimex100 = 270/100 ps
5099 13:40:27.895025 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5100 13:40:27.898625 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5101 13:40:27.901797 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5102 13:40:27.904871 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5103 13:40:27.908637 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 13:40:27.911707 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5105 13:40:27.911814
5106 13:40:27.918226 CA PerBit enable=1, Macro0, CA PI delay=33
5107 13:40:27.918311
5108 13:40:27.921966 [CBTSetCACLKResult] CA Dly = 33
5109 13:40:27.922037 CS Dly: 7 (0~39)
5110 13:40:27.922096
5111 13:40:27.925161 ----->DramcWriteLeveling(PI) begin...
5112 13:40:27.925231 ==
5113 13:40:27.928336 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 13:40:27.931693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 13:40:27.931766 ==
5116 13:40:27.935185 Write leveling (Byte 0): 33 => 33
5117 13:40:27.938313 Write leveling (Byte 1): 26 => 26
5118 13:40:27.941343 DramcWriteLeveling(PI) end<-----
5119 13:40:27.941479
5120 13:40:27.941548 ==
5121 13:40:27.945117 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 13:40:27.948658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 13:40:27.951859 ==
5124 13:40:27.951933 [Gating] SW mode calibration
5125 13:40:27.962160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5126 13:40:27.965196 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5127 13:40:27.968895 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5128 13:40:27.975257 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5129 13:40:27.978870 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 13:40:27.981740 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 13:40:27.988733 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 13:40:27.991831 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 13:40:27.995319 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 13:40:28.002268 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 1)
5135 13:40:28.005521 0 15 0 | B1->B0 | 3131 2a2a | 0 1 | (0 1) (1 0)
5136 13:40:28.008508 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5137 13:40:28.015231 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 13:40:28.018954 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 13:40:28.022429 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 13:40:28.025365 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 13:40:28.032084 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 13:40:28.035077 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 13:40:28.038846 1 0 0 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)
5144 13:40:28.045436 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5145 13:40:28.048533 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 13:40:28.051902 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 13:40:28.058536 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 13:40:28.061967 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 13:40:28.065679 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 13:40:28.072443 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 13:40:28.075440 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5152 13:40:28.078682 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5153 13:40:28.085337 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 13:40:28.088612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 13:40:28.091975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 13:40:28.095494 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 13:40:28.102661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 13:40:28.105435 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 13:40:28.108821 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 13:40:28.115617 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 13:40:28.118852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 13:40:28.122482 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 13:40:28.129010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 13:40:28.132157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 13:40:28.135546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 13:40:28.142289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 13:40:28.145437 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5168 13:40:28.148919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 13:40:28.152436 Total UI for P1: 0, mck2ui 16
5170 13:40:28.155397 best dqsien dly found for B0: ( 1, 3, 0)
5171 13:40:28.159272 Total UI for P1: 0, mck2ui 16
5172 13:40:28.162639 best dqsien dly found for B1: ( 1, 3, 2)
5173 13:40:28.165338 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5174 13:40:28.169116 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5175 13:40:28.169198
5176 13:40:28.172110 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5177 13:40:28.175561 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5178 13:40:28.179264 [Gating] SW calibration Done
5179 13:40:28.179347 ==
5180 13:40:28.182557 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 13:40:28.188562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 13:40:28.188647 ==
5183 13:40:28.188712 RX Vref Scan: 0
5184 13:40:28.188771
5185 13:40:28.192006 RX Vref 0 -> 0, step: 1
5186 13:40:28.192089
5187 13:40:28.195602 RX Delay -80 -> 252, step: 8
5188 13:40:28.199140 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5189 13:40:28.202239 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5190 13:40:28.205224 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5191 13:40:28.208752 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5192 13:40:28.215104 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5193 13:40:28.218530 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5194 13:40:28.221787 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5195 13:40:28.225344 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5196 13:40:28.228468 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5197 13:40:28.232040 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5198 13:40:28.238592 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5199 13:40:28.242006 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5200 13:40:28.245262 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5201 13:40:28.248859 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5202 13:40:28.251580 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5203 13:40:28.255355 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5204 13:40:28.258497 ==
5205 13:40:28.261585 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 13:40:28.265243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 13:40:28.265324 ==
5208 13:40:28.265386 DQS Delay:
5209 13:40:28.268658 DQS0 = 0, DQS1 = 0
5210 13:40:28.268758 DQM Delay:
5211 13:40:28.272196 DQM0 = 99, DQM1 = 86
5212 13:40:28.272280 DQ Delay:
5213 13:40:28.275465 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5214 13:40:28.278555 DQ4 =103, DQ5 =91, DQ6 =103, DQ7 =103
5215 13:40:28.281802 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5216 13:40:28.285279 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5217 13:40:28.285361
5218 13:40:28.285424
5219 13:40:28.285482 ==
5220 13:40:28.288401 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 13:40:28.292033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 13:40:28.292106 ==
5223 13:40:28.292166
5224 13:40:28.292222
5225 13:40:28.295084 TX Vref Scan disable
5226 13:40:28.298806 == TX Byte 0 ==
5227 13:40:28.301729 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5228 13:40:28.305315 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5229 13:40:28.308880 == TX Byte 1 ==
5230 13:40:28.312092 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5231 13:40:28.315104 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5232 13:40:28.315183 ==
5233 13:40:28.318497 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 13:40:28.325135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 13:40:28.325214 ==
5236 13:40:28.325275
5237 13:40:28.325332
5238 13:40:28.325387 TX Vref Scan disable
5239 13:40:28.328837 == TX Byte 0 ==
5240 13:40:28.332498 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5241 13:40:28.339021 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5242 13:40:28.339120 == TX Byte 1 ==
5243 13:40:28.342206 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5244 13:40:28.345704 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5245 13:40:28.349368
5246 13:40:28.349446 [DATLAT]
5247 13:40:28.349508 Freq=933, CH0 RK0
5248 13:40:28.349570
5249 13:40:28.352517 DATLAT Default: 0xd
5250 13:40:28.352616 0, 0xFFFF, sum = 0
5251 13:40:28.355919 1, 0xFFFF, sum = 0
5252 13:40:28.356018 2, 0xFFFF, sum = 0
5253 13:40:28.359572 3, 0xFFFF, sum = 0
5254 13:40:28.359672 4, 0xFFFF, sum = 0
5255 13:40:28.362458 5, 0xFFFF, sum = 0
5256 13:40:28.362528 6, 0xFFFF, sum = 0
5257 13:40:28.366291 7, 0xFFFF, sum = 0
5258 13:40:28.368957 8, 0xFFFF, sum = 0
5259 13:40:28.369098 9, 0xFFFF, sum = 0
5260 13:40:28.369175 10, 0x0, sum = 1
5261 13:40:28.372728 11, 0x0, sum = 2
5262 13:40:28.372834 12, 0x0, sum = 3
5263 13:40:28.375770 13, 0x0, sum = 4
5264 13:40:28.375876 best_step = 11
5265 13:40:28.376001
5266 13:40:28.376087 ==
5267 13:40:28.379129 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 13:40:28.385751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 13:40:28.385834 ==
5270 13:40:28.385897 RX Vref Scan: 1
5271 13:40:28.385974
5272 13:40:28.389237 RX Vref 0 -> 0, step: 1
5273 13:40:28.389325
5274 13:40:28.392453 RX Delay -69 -> 252, step: 4
5275 13:40:28.392530
5276 13:40:28.396034 Set Vref, RX VrefLevel [Byte0]: 55
5277 13:40:28.398939 [Byte1]: 51
5278 13:40:28.399010
5279 13:40:28.402829 Final RX Vref Byte 0 = 55 to rank0
5280 13:40:28.406155 Final RX Vref Byte 1 = 51 to rank0
5281 13:40:28.409107 Final RX Vref Byte 0 = 55 to rank1
5282 13:40:28.412845 Final RX Vref Byte 1 = 51 to rank1==
5283 13:40:28.415844 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 13:40:28.419248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 13:40:28.419332 ==
5286 13:40:28.422314 DQS Delay:
5287 13:40:28.422391 DQS0 = 0, DQS1 = 0
5288 13:40:28.422460 DQM Delay:
5289 13:40:28.426038 DQM0 = 96, DQM1 = 88
5290 13:40:28.426115 DQ Delay:
5291 13:40:28.429084 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5292 13:40:28.432484 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5293 13:40:28.435857 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5294 13:40:28.439157 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =98
5295 13:40:28.439237
5296 13:40:28.439298
5297 13:40:28.449377 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5298 13:40:28.452961 CH0 RK0: MR19=504, MR18=14FF
5299 13:40:28.456258 CH0_RK0: MR19=0x504, MR18=0x14FF, DQSOSC=415, MR23=63, INC=62, DEC=41
5300 13:40:28.456339
5301 13:40:28.459014 ----->DramcWriteLeveling(PI) begin...
5302 13:40:28.462629 ==
5303 13:40:28.465644 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 13:40:28.469278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 13:40:28.469351 ==
5306 13:40:28.472927 Write leveling (Byte 0): 33 => 33
5307 13:40:28.475753 Write leveling (Byte 1): 33 => 33
5308 13:40:28.479390 DramcWriteLeveling(PI) end<-----
5309 13:40:28.479461
5310 13:40:28.479520 ==
5311 13:40:28.482373 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 13:40:28.485879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 13:40:28.485955 ==
5314 13:40:28.489241 [Gating] SW mode calibration
5315 13:40:28.496142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 13:40:28.499493 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 13:40:28.506249 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5318 13:40:28.509471 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5319 13:40:28.512346 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 13:40:28.519449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 13:40:28.522393 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 13:40:28.526090 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 13:40:28.532378 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5324 13:40:28.535835 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5325 13:40:28.539626 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5326 13:40:28.546109 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 13:40:28.549440 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 13:40:28.552429 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 13:40:28.559719 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 13:40:28.562612 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 13:40:28.566173 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 13:40:28.572692 0 15 28 | B1->B0 | 2929 3737 | 0 0 | (0 0) (1 1)
5333 13:40:28.576392 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5334 13:40:28.579139 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 13:40:28.582740 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 13:40:28.589483 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 13:40:28.592894 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 13:40:28.596510 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 13:40:28.602673 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 13:40:28.605883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 13:40:28.609661 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 13:40:28.616135 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 13:40:28.619127 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 13:40:28.622418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 13:40:28.629773 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 13:40:28.632584 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 13:40:28.636100 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 13:40:28.642500 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 13:40:28.646368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 13:40:28.649130 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 13:40:28.655986 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 13:40:28.659304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 13:40:28.662583 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 13:40:28.669235 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 13:40:28.672618 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 13:40:28.676246 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 13:40:28.679375 Total UI for P1: 0, mck2ui 16
5358 13:40:28.682517 best dqsien dly found for B0: ( 1, 2, 24)
5359 13:40:28.686131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 13:40:28.692954 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 13:40:28.695790 Total UI for P1: 0, mck2ui 16
5362 13:40:28.699475 best dqsien dly found for B1: ( 1, 2, 30)
5363 13:40:28.702907 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5364 13:40:28.705956 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 13:40:28.706041
5366 13:40:28.709614 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5367 13:40:28.712753 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 13:40:28.716268 [Gating] SW calibration Done
5369 13:40:28.716359 ==
5370 13:40:28.719303 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 13:40:28.722694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 13:40:28.722780 ==
5373 13:40:28.726408 RX Vref Scan: 0
5374 13:40:28.726490
5375 13:40:28.726554 RX Vref 0 -> 0, step: 1
5376 13:40:28.726614
5377 13:40:28.729605 RX Delay -80 -> 252, step: 8
5378 13:40:28.736055 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5379 13:40:28.739288 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5380 13:40:28.742811 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 13:40:28.746417 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5382 13:40:28.749656 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5383 13:40:28.752585 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 13:40:28.756228 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 13:40:28.763160 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5386 13:40:28.766187 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5387 13:40:28.769509 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5388 13:40:28.772936 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 13:40:28.776474 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5390 13:40:28.779772 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5391 13:40:28.786130 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5392 13:40:28.789667 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5393 13:40:28.792981 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 13:40:28.793089 ==
5395 13:40:28.796400 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 13:40:28.799467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 13:40:28.799541 ==
5398 13:40:28.802618 DQS Delay:
5399 13:40:28.802690 DQS0 = 0, DQS1 = 0
5400 13:40:28.802749 DQM Delay:
5401 13:40:28.806139 DQM0 = 98, DQM1 = 87
5402 13:40:28.806206 DQ Delay:
5403 13:40:28.809632 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5404 13:40:28.812852 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5405 13:40:28.815904 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5406 13:40:28.819557 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5407 13:40:28.819630
5408 13:40:28.819691
5409 13:40:28.819747 ==
5410 13:40:28.823006 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 13:40:28.829637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 13:40:28.829742 ==
5413 13:40:28.829829
5414 13:40:28.829913
5415 13:40:28.829999 TX Vref Scan disable
5416 13:40:28.832744 == TX Byte 0 ==
5417 13:40:28.836440 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5418 13:40:28.843266 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5419 13:40:28.843357 == TX Byte 1 ==
5420 13:40:28.846588 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5421 13:40:28.849731 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5422 13:40:28.853390 ==
5423 13:40:28.856635 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 13:40:28.859557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 13:40:28.859633 ==
5426 13:40:28.859696
5427 13:40:28.859753
5428 13:40:28.863024 TX Vref Scan disable
5429 13:40:28.863102 == TX Byte 0 ==
5430 13:40:28.869570 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5431 13:40:28.873226 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5432 13:40:28.873306 == TX Byte 1 ==
5433 13:40:28.879539 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5434 13:40:28.883020 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5435 13:40:28.883094
5436 13:40:28.883154 [DATLAT]
5437 13:40:28.886405 Freq=933, CH0 RK1
5438 13:40:28.886473
5439 13:40:28.886530 DATLAT Default: 0xb
5440 13:40:28.889668 0, 0xFFFF, sum = 0
5441 13:40:28.889738 1, 0xFFFF, sum = 0
5442 13:40:28.892878 2, 0xFFFF, sum = 0
5443 13:40:28.892964 3, 0xFFFF, sum = 0
5444 13:40:28.896588 4, 0xFFFF, sum = 0
5445 13:40:28.896655 5, 0xFFFF, sum = 0
5446 13:40:28.899531 6, 0xFFFF, sum = 0
5447 13:40:28.899599 7, 0xFFFF, sum = 0
5448 13:40:28.903120 8, 0xFFFF, sum = 0
5449 13:40:28.903194 9, 0xFFFF, sum = 0
5450 13:40:28.906262 10, 0x0, sum = 1
5451 13:40:28.906330 11, 0x0, sum = 2
5452 13:40:28.909704 12, 0x0, sum = 3
5453 13:40:28.909777 13, 0x0, sum = 4
5454 13:40:28.913388 best_step = 11
5455 13:40:28.913455
5456 13:40:28.913515 ==
5457 13:40:28.916284 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 13:40:28.919807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 13:40:28.919880 ==
5460 13:40:28.923091 RX Vref Scan: 0
5461 13:40:28.923157
5462 13:40:28.923214 RX Vref 0 -> 0, step: 1
5463 13:40:28.923271
5464 13:40:28.926451 RX Delay -61 -> 252, step: 4
5465 13:40:28.933676 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5466 13:40:28.936622 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 13:40:28.940369 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 13:40:28.943376 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 13:40:28.947181 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5470 13:40:28.950040 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5471 13:40:28.956624 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 13:40:28.960457 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5473 13:40:28.964011 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5474 13:40:28.966787 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5475 13:40:28.970024 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 13:40:28.973679 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5477 13:40:28.980582 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5478 13:40:28.983489 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5479 13:40:28.987095 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5480 13:40:28.990214 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5481 13:40:28.990298 ==
5482 13:40:28.993674 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 13:40:28.996937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 13:40:28.997075 ==
5485 13:40:29.000488 DQS Delay:
5486 13:40:29.000564 DQS0 = 0, DQS1 = 0
5487 13:40:29.003451 DQM Delay:
5488 13:40:29.003549 DQM0 = 95, DQM1 = 87
5489 13:40:29.003611 DQ Delay:
5490 13:40:29.007215 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5491 13:40:29.010060 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =104
5492 13:40:29.013246 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =80
5493 13:40:29.017004 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5494 13:40:29.017073
5495 13:40:29.020185
5496 13:40:29.026803 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5497 13:40:29.030667 CH0 RK1: MR19=505, MR18=1B09
5498 13:40:29.036562 CH0_RK1: MR19=0x505, MR18=0x1B09, DQSOSC=413, MR23=63, INC=63, DEC=42
5499 13:40:29.036638 [RxdqsGatingPostProcess] freq 933
5500 13:40:29.043727 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 13:40:29.046979 best DQS0 dly(2T, 0.5T) = (0, 11)
5502 13:40:29.049974 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 13:40:29.053711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5504 13:40:29.056641 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 13:40:29.060264 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 13:40:29.063391 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 13:40:29.066629 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 13:40:29.070189 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 13:40:29.073233 Pre-setting of DQS Precalculation
5510 13:40:29.076739 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 13:40:29.076820 ==
5512 13:40:29.080040 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 13:40:29.083304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 13:40:29.086430 ==
5515 13:40:29.089946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 13:40:29.096491 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5517 13:40:29.100163 [CA 0] Center 36 (6~67) winsize 62
5518 13:40:29.103191 [CA 1] Center 36 (6~67) winsize 62
5519 13:40:29.106581 [CA 2] Center 34 (4~64) winsize 61
5520 13:40:29.109971 [CA 3] Center 33 (3~64) winsize 62
5521 13:40:29.112961 [CA 4] Center 34 (4~64) winsize 61
5522 13:40:29.116561 [CA 5] Center 33 (3~63) winsize 61
5523 13:40:29.116652
5524 13:40:29.119785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5525 13:40:29.119866
5526 13:40:29.123284 [CATrainingPosCal] consider 1 rank data
5527 13:40:29.126858 u2DelayCellTimex100 = 270/100 ps
5528 13:40:29.129966 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 13:40:29.133526 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 13:40:29.136556 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 13:40:29.140046 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 13:40:29.143031 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 13:40:29.149700 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5534 13:40:29.149786
5535 13:40:29.153332 CA PerBit enable=1, Macro0, CA PI delay=33
5536 13:40:29.153412
5537 13:40:29.156439 [CBTSetCACLKResult] CA Dly = 33
5538 13:40:29.156548 CS Dly: 4 (0~35)
5539 13:40:29.156640 ==
5540 13:40:29.160100 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 13:40:29.163123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 13:40:29.166353 ==
5543 13:40:29.169958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 13:40:29.176520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 13:40:29.179678 [CA 0] Center 36 (6~67) winsize 62
5546 13:40:29.183272 [CA 1] Center 36 (6~67) winsize 62
5547 13:40:29.186735 [CA 2] Center 33 (3~64) winsize 62
5548 13:40:29.190070 [CA 3] Center 33 (3~64) winsize 62
5549 13:40:29.193052 [CA 4] Center 34 (4~64) winsize 61
5550 13:40:29.196566 [CA 5] Center 32 (2~63) winsize 62
5551 13:40:29.196652
5552 13:40:29.200217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 13:40:29.200311
5554 13:40:29.203021 [CATrainingPosCal] consider 2 rank data
5555 13:40:29.206549 u2DelayCellTimex100 = 270/100 ps
5556 13:40:29.209708 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 13:40:29.213127 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 13:40:29.216827 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 13:40:29.220206 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 13:40:29.223533 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 13:40:29.230127 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 13:40:29.230212
5563 13:40:29.233124 CA PerBit enable=1, Macro0, CA PI delay=33
5564 13:40:29.233208
5565 13:40:29.236421 [CBTSetCACLKResult] CA Dly = 33
5566 13:40:29.236505 CS Dly: 5 (0~38)
5567 13:40:29.236590
5568 13:40:29.239688 ----->DramcWriteLeveling(PI) begin...
5569 13:40:29.239772 ==
5570 13:40:29.243341 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 13:40:29.249862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 13:40:29.249952 ==
5573 13:40:29.253539 Write leveling (Byte 0): 26 => 26
5574 13:40:29.253623 Write leveling (Byte 1): 26 => 26
5575 13:40:29.256337 DramcWriteLeveling(PI) end<-----
5576 13:40:29.256422
5577 13:40:29.256507 ==
5578 13:40:29.259928 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 13:40:29.266654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 13:40:29.266738 ==
5581 13:40:29.269730 [Gating] SW mode calibration
5582 13:40:29.276440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 13:40:29.280225 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 13:40:29.286266 0 14 0 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
5585 13:40:29.289935 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 13:40:29.293004 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 13:40:29.300117 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 13:40:29.303322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 13:40:29.306591 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 13:40:29.309973 0 14 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 0)
5591 13:40:29.316178 0 14 28 | B1->B0 | 2e2e 3131 | 0 1 | (0 1) (0 1)
5592 13:40:29.319499 0 15 0 | B1->B0 | 2727 2a2a | 0 0 | (0 0) (1 1)
5593 13:40:29.322982 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 13:40:29.329529 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 13:40:29.333335 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 13:40:29.336424 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 13:40:29.342811 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 13:40:29.346687 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 13:40:29.349967 0 15 28 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (0 0)
5600 13:40:29.356285 1 0 0 | B1->B0 | 4545 4343 | 0 1 | (0 0) (0 0)
5601 13:40:29.359692 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 13:40:29.363403 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 13:40:29.369669 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 13:40:29.372716 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 13:40:29.376377 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 13:40:29.383101 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 13:40:29.386072 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 13:40:29.389699 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 13:40:29.396645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 13:40:29.399527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 13:40:29.402675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 13:40:29.409395 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 13:40:29.413097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 13:40:29.416580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 13:40:29.419961 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 13:40:29.426250 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 13:40:29.429509 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 13:40:29.433087 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 13:40:29.439865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 13:40:29.443337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 13:40:29.446603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 13:40:29.452899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 13:40:29.456324 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 13:40:29.459779 Total UI for P1: 0, mck2ui 16
5625 13:40:29.463197 best dqsien dly found for B0: ( 1, 2, 26)
5626 13:40:29.466330 Total UI for P1: 0, mck2ui 16
5627 13:40:29.470414 best dqsien dly found for B1: ( 1, 2, 26)
5628 13:40:29.473318 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5629 13:40:29.476916 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5630 13:40:29.477282
5631 13:40:29.479939 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5632 13:40:29.483766 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5633 13:40:29.486931 [Gating] SW calibration Done
5634 13:40:29.487252 ==
5635 13:40:29.490465 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 13:40:29.493539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 13:40:29.493939 ==
5638 13:40:29.496768 RX Vref Scan: 0
5639 13:40:29.497277
5640 13:40:29.500558 RX Vref 0 -> 0, step: 1
5641 13:40:29.500890
5642 13:40:29.501263 RX Delay -80 -> 252, step: 8
5643 13:40:29.507000 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5644 13:40:29.510233 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5645 13:40:29.513572 iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184
5646 13:40:29.516842 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5647 13:40:29.520259 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5648 13:40:29.523315 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5649 13:40:29.530482 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5650 13:40:29.533765 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5651 13:40:29.536821 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5652 13:40:29.540222 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5653 13:40:29.543783 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5654 13:40:29.550619 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5655 13:40:29.553926 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5656 13:40:29.557116 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5657 13:40:29.559918 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5658 13:40:29.563643 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5659 13:40:29.564053 ==
5660 13:40:29.566689 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 13:40:29.569987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 13:40:29.573172 ==
5663 13:40:29.573384 DQS Delay:
5664 13:40:29.573544 DQS0 = 0, DQS1 = 0
5665 13:40:29.576730 DQM Delay:
5666 13:40:29.576934 DQM0 = 96, DQM1 = 89
5667 13:40:29.579481 DQ Delay:
5668 13:40:29.583214 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5669 13:40:29.586443 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5670 13:40:29.589801 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5671 13:40:29.592957 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5672 13:40:29.593138
5673 13:40:29.593257
5674 13:40:29.593338 ==
5675 13:40:29.596555 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 13:40:29.599588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 13:40:29.599695 ==
5678 13:40:29.599773
5679 13:40:29.599843
5680 13:40:29.602844 TX Vref Scan disable
5681 13:40:29.602942 == TX Byte 0 ==
5682 13:40:29.609370 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5683 13:40:29.613106 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5684 13:40:29.613214 == TX Byte 1 ==
5685 13:40:29.619373 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5686 13:40:29.623218 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5687 13:40:29.623350 ==
5688 13:40:29.626723 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 13:40:29.629710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 13:40:29.629793 ==
5691 13:40:29.629857
5692 13:40:29.629917
5693 13:40:29.632761 TX Vref Scan disable
5694 13:40:29.636443 == TX Byte 0 ==
5695 13:40:29.639510 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 13:40:29.642763 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 13:40:29.646075 == TX Byte 1 ==
5698 13:40:29.649678 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5699 13:40:29.652899 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5700 13:40:29.653036
5701 13:40:29.656224 [DATLAT]
5702 13:40:29.656305 Freq=933, CH1 RK0
5703 13:40:29.656370
5704 13:40:29.659780 DATLAT Default: 0xd
5705 13:40:29.659861 0, 0xFFFF, sum = 0
5706 13:40:29.663267 1, 0xFFFF, sum = 0
5707 13:40:29.663349 2, 0xFFFF, sum = 0
5708 13:40:29.666147 3, 0xFFFF, sum = 0
5709 13:40:29.666230 4, 0xFFFF, sum = 0
5710 13:40:29.669522 5, 0xFFFF, sum = 0
5711 13:40:29.669604 6, 0xFFFF, sum = 0
5712 13:40:29.672791 7, 0xFFFF, sum = 0
5713 13:40:29.672873 8, 0xFFFF, sum = 0
5714 13:40:29.676345 9, 0xFFFF, sum = 0
5715 13:40:29.676430 10, 0x0, sum = 1
5716 13:40:29.679228 11, 0x0, sum = 2
5717 13:40:29.679310 12, 0x0, sum = 3
5718 13:40:29.682664 13, 0x0, sum = 4
5719 13:40:29.682761 best_step = 11
5720 13:40:29.682826
5721 13:40:29.682887 ==
5722 13:40:29.686196 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 13:40:29.692849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 13:40:29.692935 ==
5725 13:40:29.693060 RX Vref Scan: 1
5726 13:40:29.693151
5727 13:40:29.695848 RX Vref 0 -> 0, step: 1
5728 13:40:29.695931
5729 13:40:29.699151 RX Delay -61 -> 252, step: 4
5730 13:40:29.699248
5731 13:40:29.702649 Set Vref, RX VrefLevel [Byte0]: 56
5732 13:40:29.706115 [Byte1]: 51
5733 13:40:29.706196
5734 13:40:29.709366 Final RX Vref Byte 0 = 56 to rank0
5735 13:40:29.712360 Final RX Vref Byte 1 = 51 to rank0
5736 13:40:29.715923 Final RX Vref Byte 0 = 56 to rank1
5737 13:40:29.719604 Final RX Vref Byte 1 = 51 to rank1==
5738 13:40:29.722506 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 13:40:29.726106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 13:40:29.726193 ==
5741 13:40:29.729112 DQS Delay:
5742 13:40:29.729193 DQS0 = 0, DQS1 = 0
5743 13:40:29.729257 DQM Delay:
5744 13:40:29.732763 DQM0 = 97, DQM1 = 89
5745 13:40:29.732862 DQ Delay:
5746 13:40:29.735763 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5747 13:40:29.739360 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =96
5748 13:40:29.742430 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5749 13:40:29.745685 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5750 13:40:29.745777
5751 13:40:29.745842
5752 13:40:29.755695 [DQSOSCAuto] RK0, (LSB)MR18= 0x12ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5753 13:40:29.759191 CH1 RK0: MR19=504, MR18=12EE
5754 13:40:29.762429 CH1_RK0: MR19=0x504, MR18=0x12EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5755 13:40:29.762511
5756 13:40:29.765900 ----->DramcWriteLeveling(PI) begin...
5757 13:40:29.769132 ==
5758 13:40:29.772614 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 13:40:29.775844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 13:40:29.775926 ==
5761 13:40:29.779430 Write leveling (Byte 0): 25 => 25
5762 13:40:29.782469 Write leveling (Byte 1): 25 => 25
5763 13:40:29.785899 DramcWriteLeveling(PI) end<-----
5764 13:40:29.785995
5765 13:40:29.786060 ==
5766 13:40:29.789300 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 13:40:29.792824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 13:40:29.792905 ==
5769 13:40:29.795939 [Gating] SW mode calibration
5770 13:40:29.802924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 13:40:29.805909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 13:40:29.813301 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5773 13:40:29.816124 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 13:40:29.819322 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 13:40:29.826541 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 13:40:29.829489 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5777 13:40:29.832995 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 13:40:29.839251 0 14 24 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 1)
5779 13:40:29.842860 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
5780 13:40:29.846506 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 13:40:29.853284 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 13:40:29.856088 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 13:40:29.859853 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 13:40:29.866575 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 13:40:29.869475 0 15 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5786 13:40:29.872871 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5787 13:40:29.876471 0 15 28 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
5788 13:40:29.883046 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 13:40:29.886308 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 13:40:29.889803 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 13:40:29.896035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 13:40:29.899664 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 13:40:29.902700 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 13:40:29.909553 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5795 13:40:29.912634 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 13:40:29.916567 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5797 13:40:29.923232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 13:40:29.926223 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 13:40:29.929211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 13:40:29.936270 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 13:40:29.939871 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 13:40:29.942737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 13:40:29.949445 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 13:40:29.952594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 13:40:29.956434 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 13:40:29.962844 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 13:40:29.966450 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 13:40:29.969504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 13:40:29.973071 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 13:40:29.979573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 13:40:29.982745 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5812 13:40:29.986178 Total UI for P1: 0, mck2ui 16
5813 13:40:29.989423 best dqsien dly found for B0: ( 1, 2, 24)
5814 13:40:29.993128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5815 13:40:29.999806 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 13:40:30.002834 Total UI for P1: 0, mck2ui 16
5817 13:40:30.006460 best dqsien dly found for B1: ( 1, 2, 30)
5818 13:40:30.010217 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5819 13:40:30.013027 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5820 13:40:30.013163
5821 13:40:30.016334 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 13:40:30.019684 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5823 13:40:30.023065 [Gating] SW calibration Done
5824 13:40:30.023251 ==
5825 13:40:30.026817 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 13:40:30.029779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 13:40:30.029930 ==
5828 13:40:30.033303 RX Vref Scan: 0
5829 13:40:30.033473
5830 13:40:30.033639 RX Vref 0 -> 0, step: 1
5831 13:40:30.033772
5832 13:40:30.036198 RX Delay -80 -> 252, step: 8
5833 13:40:30.039514 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5834 13:40:30.046410 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5835 13:40:30.050179 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5836 13:40:30.053109 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5837 13:40:30.056950 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5838 13:40:30.060003 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5839 13:40:30.063720 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5840 13:40:30.070024 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5841 13:40:30.073165 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5842 13:40:30.076346 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5843 13:40:30.079980 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5844 13:40:30.083522 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5845 13:40:30.086526 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5846 13:40:30.093101 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5847 13:40:30.096842 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5848 13:40:30.100142 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5849 13:40:30.100445 ==
5850 13:40:30.103344 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 13:40:30.107051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 13:40:30.107375 ==
5853 13:40:30.110386 DQS Delay:
5854 13:40:30.110744 DQS0 = 0, DQS1 = 0
5855 13:40:30.111101 DQM Delay:
5856 13:40:30.113251 DQM0 = 94, DQM1 = 88
5857 13:40:30.113650 DQ Delay:
5858 13:40:30.116908 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5859 13:40:30.119878 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5860 13:40:30.123064 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5861 13:40:30.126766 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5862 13:40:30.127230
5863 13:40:30.127600
5864 13:40:30.127963 ==
5865 13:40:30.130262 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 13:40:30.136620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 13:40:30.137004 ==
5868 13:40:30.137299
5869 13:40:30.137561
5870 13:40:30.137812 TX Vref Scan disable
5871 13:40:30.140386 == TX Byte 0 ==
5872 13:40:30.143569 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5873 13:40:30.146694 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5874 13:40:30.150175 == TX Byte 1 ==
5875 13:40:30.153879 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5876 13:40:30.156970 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5877 13:40:30.159969 ==
5878 13:40:30.163763 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 13:40:30.166635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 13:40:30.166946 ==
5881 13:40:30.167208
5882 13:40:30.167477
5883 13:40:30.170191 TX Vref Scan disable
5884 13:40:30.170484 == TX Byte 0 ==
5885 13:40:30.176936 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5886 13:40:30.180041 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5887 13:40:30.180343 == TX Byte 1 ==
5888 13:40:30.186935 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5889 13:40:30.190460 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5890 13:40:30.190893
5891 13:40:30.191163 [DATLAT]
5892 13:40:30.193439 Freq=933, CH1 RK1
5893 13:40:30.193752
5894 13:40:30.194005 DATLAT Default: 0xb
5895 13:40:30.197231 0, 0xFFFF, sum = 0
5896 13:40:30.197542 1, 0xFFFF, sum = 0
5897 13:40:30.200123 2, 0xFFFF, sum = 0
5898 13:40:30.200432 3, 0xFFFF, sum = 0
5899 13:40:30.203648 4, 0xFFFF, sum = 0
5900 13:40:30.203943 5, 0xFFFF, sum = 0
5901 13:40:30.206825 6, 0xFFFF, sum = 0
5902 13:40:30.207197 7, 0xFFFF, sum = 0
5903 13:40:30.210024 8, 0xFFFF, sum = 0
5904 13:40:30.210374 9, 0xFFFF, sum = 0
5905 13:40:30.213820 10, 0x0, sum = 1
5906 13:40:30.214190 11, 0x0, sum = 2
5907 13:40:30.217119 12, 0x0, sum = 3
5908 13:40:30.217491 13, 0x0, sum = 4
5909 13:40:30.220048 best_step = 11
5910 13:40:30.220391
5911 13:40:30.220680 ==
5912 13:40:30.223464 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 13:40:30.226859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 13:40:30.227331 ==
5915 13:40:30.230194 RX Vref Scan: 0
5916 13:40:30.230673
5917 13:40:30.230976 RX Vref 0 -> 0, step: 1
5918 13:40:30.231246
5919 13:40:30.233482 RX Delay -61 -> 252, step: 4
5920 13:40:30.240862 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5921 13:40:30.243910 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5922 13:40:30.247472 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5923 13:40:30.250622 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5924 13:40:30.253612 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5925 13:40:30.257288 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5926 13:40:30.263955 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5927 13:40:30.267622 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5928 13:40:30.270657 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5929 13:40:30.273605 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5930 13:40:30.277459 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5931 13:40:30.283509 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5932 13:40:30.287365 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5933 13:40:30.290353 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5934 13:40:30.293654 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5935 13:40:30.297392 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5936 13:40:30.297753 ==
5937 13:40:30.300236 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 13:40:30.306987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 13:40:30.307430 ==
5940 13:40:30.307716 DQS Delay:
5941 13:40:30.307975 DQS0 = 0, DQS1 = 0
5942 13:40:30.310675 DQM Delay:
5943 13:40:30.311155 DQM0 = 95, DQM1 = 89
5944 13:40:30.313751 DQ Delay:
5945 13:40:30.317016 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =92
5946 13:40:30.320684 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5947 13:40:30.321079 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =82
5948 13:40:30.327524 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5949 13:40:30.327870
5950 13:40:30.328201
5951 13:40:30.334050 [DQSOSCAuto] RK1, (LSB)MR18= 0xc15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5952 13:40:30.337114 CH1 RK1: MR19=505, MR18=C15
5953 13:40:30.343583 CH1_RK1: MR19=0x505, MR18=0xC15, DQSOSC=415, MR23=63, INC=62, DEC=41
5954 13:40:30.343794 [RxdqsGatingPostProcess] freq 933
5955 13:40:30.350641 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5956 13:40:30.353667 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 13:40:30.357313 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 13:40:30.360311 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 13:40:30.364017 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 13:40:30.367184 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 13:40:30.370532 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 13:40:30.373934 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 13:40:30.377395 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 13:40:30.381105 Pre-setting of DQS Precalculation
5965 13:40:30.383948 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5966 13:40:30.391061 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5967 13:40:30.397421 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5968 13:40:30.397796
5969 13:40:30.398110
5970 13:40:30.400933 [Calibration Summary] 1866 Mbps
5971 13:40:30.404027 CH 0, Rank 0
5972 13:40:30.404396 SW Impedance : PASS
5973 13:40:30.407790 DUTY Scan : NO K
5974 13:40:30.410759 ZQ Calibration : PASS
5975 13:40:30.411179 Jitter Meter : NO K
5976 13:40:30.414650 CBT Training : PASS
5977 13:40:30.417540 Write leveling : PASS
5978 13:40:30.417884 RX DQS gating : PASS
5979 13:40:30.421202 RX DQ/DQS(RDDQC) : PASS
5980 13:40:30.421570 TX DQ/DQS : PASS
5981 13:40:30.424515 RX DATLAT : PASS
5982 13:40:30.428122 RX DQ/DQS(Engine): PASS
5983 13:40:30.428501 TX OE : NO K
5984 13:40:30.431015 All Pass.
5985 13:40:30.431509
5986 13:40:30.431907 CH 0, Rank 1
5987 13:40:30.434412 SW Impedance : PASS
5988 13:40:30.434757 DUTY Scan : NO K
5989 13:40:30.437557 ZQ Calibration : PASS
5990 13:40:30.440928 Jitter Meter : NO K
5991 13:40:30.441333 CBT Training : PASS
5992 13:40:30.444130 Write leveling : PASS
5993 13:40:30.447750 RX DQS gating : PASS
5994 13:40:30.448125 RX DQ/DQS(RDDQC) : PASS
5995 13:40:30.451094 TX DQ/DQS : PASS
5996 13:40:30.454164 RX DATLAT : PASS
5997 13:40:30.454561 RX DQ/DQS(Engine): PASS
5998 13:40:30.457787 TX OE : NO K
5999 13:40:30.458163 All Pass.
6000 13:40:30.458458
6001 13:40:30.460855 CH 1, Rank 0
6002 13:40:30.461276 SW Impedance : PASS
6003 13:40:30.464457 DUTY Scan : NO K
6004 13:40:30.467496 ZQ Calibration : PASS
6005 13:40:30.467841 Jitter Meter : NO K
6006 13:40:30.470655 CBT Training : PASS
6007 13:40:30.471071 Write leveling : PASS
6008 13:40:30.474403 RX DQS gating : PASS
6009 13:40:30.477378 RX DQ/DQS(RDDQC) : PASS
6010 13:40:30.477744 TX DQ/DQS : PASS
6011 13:40:30.481252 RX DATLAT : PASS
6012 13:40:30.484416 RX DQ/DQS(Engine): PASS
6013 13:40:30.484757 TX OE : NO K
6014 13:40:30.487360 All Pass.
6015 13:40:30.487849
6016 13:40:30.488152 CH 1, Rank 1
6017 13:40:30.490932 SW Impedance : PASS
6018 13:40:30.491313 DUTY Scan : NO K
6019 13:40:30.494094 ZQ Calibration : PASS
6020 13:40:30.497539 Jitter Meter : NO K
6021 13:40:30.497988 CBT Training : PASS
6022 13:40:30.501064 Write leveling : PASS
6023 13:40:30.504420 RX DQS gating : PASS
6024 13:40:30.504809 RX DQ/DQS(RDDQC) : PASS
6025 13:40:30.507225 TX DQ/DQS : PASS
6026 13:40:30.507681 RX DATLAT : PASS
6027 13:40:30.511179 RX DQ/DQS(Engine): PASS
6028 13:40:30.514623 TX OE : NO K
6029 13:40:30.515024 All Pass.
6030 13:40:30.515371
6031 13:40:30.517723 DramC Write-DBI off
6032 13:40:30.518094 PER_BANK_REFRESH: Hybrid Mode
6033 13:40:30.520801 TX_TRACKING: ON
6034 13:40:30.531313 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6035 13:40:30.534489 [FAST_K] Save calibration result to emmc
6036 13:40:30.537715 dramc_set_vcore_voltage set vcore to 650000
6037 13:40:30.538188 Read voltage for 400, 6
6038 13:40:30.541153 Vio18 = 0
6039 13:40:30.541535 Vcore = 650000
6040 13:40:30.541937 Vdram = 0
6041 13:40:30.544110 Vddq = 0
6042 13:40:30.544554 Vmddr = 0
6043 13:40:30.547510 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6044 13:40:30.554295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6045 13:40:30.557576 MEM_TYPE=3, freq_sel=20
6046 13:40:30.561355 sv_algorithm_assistance_LP4_800
6047 13:40:30.564361 ============ PULL DRAM RESETB DOWN ============
6048 13:40:30.567648 ========== PULL DRAM RESETB DOWN end =========
6049 13:40:30.571378 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6050 13:40:30.574229 ===================================
6051 13:40:30.577506 LPDDR4 DRAM CONFIGURATION
6052 13:40:30.580953 ===================================
6053 13:40:30.584067 EX_ROW_EN[0] = 0x0
6054 13:40:30.584490 EX_ROW_EN[1] = 0x0
6055 13:40:30.587760 LP4Y_EN = 0x0
6056 13:40:30.588446 WORK_FSP = 0x0
6057 13:40:30.591072 WL = 0x2
6058 13:40:30.591594 RL = 0x2
6059 13:40:30.594555 BL = 0x2
6060 13:40:30.594899 RPST = 0x0
6061 13:40:30.598169 RD_PRE = 0x0
6062 13:40:30.598548 WR_PRE = 0x1
6063 13:40:30.601258 WR_PST = 0x0
6064 13:40:30.601662 DBI_WR = 0x0
6065 13:40:30.604592 DBI_RD = 0x0
6066 13:40:30.607619 OTF = 0x1
6067 13:40:30.611160 ===================================
6068 13:40:30.611568 ===================================
6069 13:40:30.614190 ANA top config
6070 13:40:30.617528 ===================================
6071 13:40:30.621497 DLL_ASYNC_EN = 0
6072 13:40:30.622041 ALL_SLAVE_EN = 1
6073 13:40:30.624253 NEW_RANK_MODE = 1
6074 13:40:30.627940 DLL_IDLE_MODE = 1
6075 13:40:30.631230 LP45_APHY_COMB_EN = 1
6076 13:40:30.634274 TX_ODT_DIS = 1
6077 13:40:30.634731 NEW_8X_MODE = 1
6078 13:40:30.638006 ===================================
6079 13:40:30.641546 ===================================
6080 13:40:30.644902 data_rate = 800
6081 13:40:30.647956 CKR = 1
6082 13:40:30.651553 DQ_P2S_RATIO = 4
6083 13:40:30.654802 ===================================
6084 13:40:30.657973 CA_P2S_RATIO = 4
6085 13:40:30.658432 DQ_CA_OPEN = 0
6086 13:40:30.661551 DQ_SEMI_OPEN = 1
6087 13:40:30.664791 CA_SEMI_OPEN = 1
6088 13:40:30.668339 CA_FULL_RATE = 0
6089 13:40:30.671253 DQ_CKDIV4_EN = 0
6090 13:40:30.674364 CA_CKDIV4_EN = 1
6091 13:40:30.674743 CA_PREDIV_EN = 0
6092 13:40:30.677993 PH8_DLY = 0
6093 13:40:30.681080 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6094 13:40:30.684847 DQ_AAMCK_DIV = 0
6095 13:40:30.687776 CA_AAMCK_DIV = 0
6096 13:40:30.691668 CA_ADMCK_DIV = 4
6097 13:40:30.692050 DQ_TRACK_CA_EN = 0
6098 13:40:30.694672 CA_PICK = 800
6099 13:40:30.697827 CA_MCKIO = 400
6100 13:40:30.701183 MCKIO_SEMI = 400
6101 13:40:30.704886 PLL_FREQ = 3016
6102 13:40:30.708149 DQ_UI_PI_RATIO = 32
6103 13:40:30.711210 CA_UI_PI_RATIO = 32
6104 13:40:30.714675 ===================================
6105 13:40:30.718252 ===================================
6106 13:40:30.718637 memory_type:LPDDR4
6107 13:40:30.721351 GP_NUM : 10
6108 13:40:30.721732 SRAM_EN : 1
6109 13:40:30.724852 MD32_EN : 0
6110 13:40:30.727868 ===================================
6111 13:40:30.731388 [ANA_INIT] >>>>>>>>>>>>>>
6112 13:40:30.735098 <<<<<< [CONFIGURE PHASE]: ANA_TX
6113 13:40:30.737883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6114 13:40:30.741073 ===================================
6115 13:40:30.741457 data_rate = 800,PCW = 0X7400
6116 13:40:30.744905 ===================================
6117 13:40:30.748754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6118 13:40:30.755049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 13:40:30.768462 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 13:40:30.771820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6121 13:40:30.775259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6122 13:40:30.778304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6123 13:40:30.781546 [ANA_INIT] flow start
6124 13:40:30.781927 [ANA_INIT] PLL >>>>>>>>
6125 13:40:30.785329 [ANA_INIT] PLL <<<<<<<<
6126 13:40:30.788267 [ANA_INIT] MIDPI >>>>>>>>
6127 13:40:30.788647 [ANA_INIT] MIDPI <<<<<<<<
6128 13:40:30.791932 [ANA_INIT] DLL >>>>>>>>
6129 13:40:30.795086 [ANA_INIT] flow end
6130 13:40:30.798157 ============ LP4 DIFF to SE enter ============
6131 13:40:30.802004 ============ LP4 DIFF to SE exit ============
6132 13:40:30.805005 [ANA_INIT] <<<<<<<<<<<<<
6133 13:40:30.808771 [Flow] Enable top DCM control >>>>>
6134 13:40:30.811691 [Flow] Enable top DCM control <<<<<
6135 13:40:30.814826 Enable DLL master slave shuffle
6136 13:40:30.818743 ==============================================================
6137 13:40:30.821729 Gating Mode config
6138 13:40:30.824491 ==============================================================
6139 13:40:30.828200 Config description:
6140 13:40:30.838064 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6141 13:40:30.844537 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6142 13:40:30.848166 SELPH_MODE 0: By rank 1: By Phase
6143 13:40:30.854336 ==============================================================
6144 13:40:30.858218 GAT_TRACK_EN = 0
6145 13:40:30.861431 RX_GATING_MODE = 2
6146 13:40:30.864433 RX_GATING_TRACK_MODE = 2
6147 13:40:30.868224 SELPH_MODE = 1
6148 13:40:30.870926 PICG_EARLY_EN = 1
6149 13:40:30.871011 VALID_LAT_VALUE = 1
6150 13:40:30.877949 ==============================================================
6151 13:40:30.881041 Enter into Gating configuration >>>>
6152 13:40:30.884729 Exit from Gating configuration <<<<
6153 13:40:30.887678 Enter into DVFS_PRE_config >>>>>
6154 13:40:30.897595 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6155 13:40:30.900807 Exit from DVFS_PRE_config <<<<<
6156 13:40:30.904442 Enter into PICG configuration >>>>
6157 13:40:30.907697 Exit from PICG configuration <<<<
6158 13:40:30.911304 [RX_INPUT] configuration >>>>>
6159 13:40:30.914514 [RX_INPUT] configuration <<<<<
6160 13:40:30.921351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6161 13:40:30.924154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6162 13:40:30.931162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 13:40:30.937440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 13:40:30.944305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 13:40:30.951137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 13:40:30.954296 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6167 13:40:30.957603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6168 13:40:30.961162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6169 13:40:30.967311 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6170 13:40:30.971047 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6171 13:40:30.974130 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 13:40:30.977794 ===================================
6173 13:40:30.980707 LPDDR4 DRAM CONFIGURATION
6174 13:40:30.984710 ===================================
6175 13:40:30.984791 EX_ROW_EN[0] = 0x0
6176 13:40:30.987609 EX_ROW_EN[1] = 0x0
6177 13:40:30.987689 LP4Y_EN = 0x0
6178 13:40:30.990925 WORK_FSP = 0x0
6179 13:40:30.991021 WL = 0x2
6180 13:40:30.994175 RL = 0x2
6181 13:40:30.994281 BL = 0x2
6182 13:40:30.997726 RPST = 0x0
6183 13:40:30.997806 RD_PRE = 0x0
6184 13:40:31.000701 WR_PRE = 0x1
6185 13:40:31.000807 WR_PST = 0x0
6186 13:40:31.004453 DBI_WR = 0x0
6187 13:40:31.007650 DBI_RD = 0x0
6188 13:40:31.007743 OTF = 0x1
6189 13:40:31.011413 ===================================
6190 13:40:31.014462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6191 13:40:31.018007 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6192 13:40:31.024115 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 13:40:31.028089 ===================================
6194 13:40:31.028170 LPDDR4 DRAM CONFIGURATION
6195 13:40:31.030830 ===================================
6196 13:40:31.034502 EX_ROW_EN[0] = 0x10
6197 13:40:31.037558 EX_ROW_EN[1] = 0x0
6198 13:40:31.037638 LP4Y_EN = 0x0
6199 13:40:31.041217 WORK_FSP = 0x0
6200 13:40:31.041298 WL = 0x2
6201 13:40:31.044307 RL = 0x2
6202 13:40:31.044387 BL = 0x2
6203 13:40:31.047984 RPST = 0x0
6204 13:40:31.048064 RD_PRE = 0x0
6205 13:40:31.051315 WR_PRE = 0x1
6206 13:40:31.051397 WR_PST = 0x0
6207 13:40:31.054511 DBI_WR = 0x0
6208 13:40:31.054591 DBI_RD = 0x0
6209 13:40:31.058127 OTF = 0x1
6210 13:40:31.061189 ===================================
6211 13:40:31.068029 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6212 13:40:31.071234 nWR fixed to 30
6213 13:40:31.074494 [ModeRegInit_LP4] CH0 RK0
6214 13:40:31.074575 [ModeRegInit_LP4] CH0 RK1
6215 13:40:31.077473 [ModeRegInit_LP4] CH1 RK0
6216 13:40:31.080811 [ModeRegInit_LP4] CH1 RK1
6217 13:40:31.080917 match AC timing 19
6218 13:40:31.087609 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6219 13:40:31.091234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6220 13:40:31.094472 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6221 13:40:31.101287 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6222 13:40:31.104179 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6223 13:40:31.104259 ==
6224 13:40:31.107514 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 13:40:31.111191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 13:40:31.111273 ==
6227 13:40:31.117525 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 13:40:31.124614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6229 13:40:31.127739 [CA 0] Center 36 (8~64) winsize 57
6230 13:40:31.127821 [CA 1] Center 36 (8~64) winsize 57
6231 13:40:31.130864 [CA 2] Center 36 (8~64) winsize 57
6232 13:40:31.134505 [CA 3] Center 36 (8~64) winsize 57
6233 13:40:31.137533 [CA 4] Center 36 (8~64) winsize 57
6234 13:40:31.141296 [CA 5] Center 36 (8~64) winsize 57
6235 13:40:31.141377
6236 13:40:31.144342 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6237 13:40:31.144423
6238 13:40:31.147781 [CATrainingPosCal] consider 1 rank data
6239 13:40:31.150942 u2DelayCellTimex100 = 270/100 ps
6240 13:40:31.154490 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 13:40:31.158133 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 13:40:31.164562 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 13:40:31.167824 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 13:40:31.171294 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 13:40:31.174411 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 13:40:31.174492
6247 13:40:31.178063 CA PerBit enable=1, Macro0, CA PI delay=36
6248 13:40:31.178144
6249 13:40:31.180980 [CBTSetCACLKResult] CA Dly = 36
6250 13:40:31.181091 CS Dly: 1 (0~32)
6251 13:40:31.181155 ==
6252 13:40:31.184425 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 13:40:31.191371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 13:40:31.191453 ==
6255 13:40:31.194396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 13:40:31.200850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6257 13:40:31.204801 [CA 0] Center 36 (8~64) winsize 57
6258 13:40:31.207712 [CA 1] Center 36 (8~64) winsize 57
6259 13:40:31.211639 [CA 2] Center 36 (8~64) winsize 57
6260 13:40:31.214275 [CA 3] Center 36 (8~64) winsize 57
6261 13:40:31.218065 [CA 4] Center 36 (8~64) winsize 57
6262 13:40:31.221071 [CA 5] Center 36 (8~64) winsize 57
6263 13:40:31.221152
6264 13:40:31.224771 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6265 13:40:31.224852
6266 13:40:31.227853 [CATrainingPosCal] consider 2 rank data
6267 13:40:31.231136 u2DelayCellTimex100 = 270/100 ps
6268 13:40:31.234577 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 13:40:31.238526 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 13:40:31.241372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 13:40:31.244893 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 13:40:31.247928 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 13:40:31.251581 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 13:40:31.251663
6275 13:40:31.258417 CA PerBit enable=1, Macro0, CA PI delay=36
6276 13:40:31.258499
6277 13:40:31.258563 [CBTSetCACLKResult] CA Dly = 36
6278 13:40:31.261714 CS Dly: 1 (0~32)
6279 13:40:31.261795
6280 13:40:31.264878 ----->DramcWriteLeveling(PI) begin...
6281 13:40:31.264960 ==
6282 13:40:31.268639 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 13:40:31.271671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 13:40:31.271752 ==
6285 13:40:31.274720 Write leveling (Byte 0): 40 => 8
6286 13:40:31.278389 Write leveling (Byte 1): 32 => 0
6287 13:40:31.281335 DramcWriteLeveling(PI) end<-----
6288 13:40:31.281416
6289 13:40:31.281480 ==
6290 13:40:31.285032 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 13:40:31.288531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 13:40:31.288887 ==
6293 13:40:31.292189 [Gating] SW mode calibration
6294 13:40:31.297966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6295 13:40:31.304970 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6296 13:40:31.308233 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 13:40:31.314949 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 13:40:31.317705 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 13:40:31.321523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 13:40:31.328019 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 13:40:31.331353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 13:40:31.334966 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 13:40:31.338034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 13:40:31.344934 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 13:40:31.348036 Total UI for P1: 0, mck2ui 16
6306 13:40:31.351757 best dqsien dly found for B0: ( 0, 14, 24)
6307 13:40:31.355264 Total UI for P1: 0, mck2ui 16
6308 13:40:31.358502 best dqsien dly found for B1: ( 0, 14, 24)
6309 13:40:31.361532 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6310 13:40:31.365078 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6311 13:40:31.365456
6312 13:40:31.368788 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 13:40:31.371682 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 13:40:31.374817 [Gating] SW calibration Done
6315 13:40:31.375197 ==
6316 13:40:31.378273 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 13:40:31.381896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 13:40:31.382277 ==
6319 13:40:31.385037 RX Vref Scan: 0
6320 13:40:31.385417
6321 13:40:31.385719 RX Vref 0 -> 0, step: 1
6322 13:40:31.388738
6323 13:40:31.389245 RX Delay -410 -> 252, step: 16
6324 13:40:31.395357 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6325 13:40:31.398503 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6326 13:40:31.402045 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6327 13:40:31.405298 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6328 13:40:31.411832 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6329 13:40:31.415369 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6330 13:40:31.418404 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6331 13:40:31.422088 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6332 13:40:31.428438 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6333 13:40:31.431818 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6334 13:40:31.435098 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6335 13:40:31.438337 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6336 13:40:31.445175 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6337 13:40:31.448611 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6338 13:40:31.451901 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6339 13:40:31.455241 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6340 13:40:31.455817 ==
6341 13:40:31.458926 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 13:40:31.465415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 13:40:31.465708 ==
6344 13:40:31.465965 DQS Delay:
6345 13:40:31.468310 DQS0 = 35, DQS1 = 51
6346 13:40:31.468530 DQM Delay:
6347 13:40:31.472008 DQM0 = 7, DQM1 = 11
6348 13:40:31.472225 DQ Delay:
6349 13:40:31.475202 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6350 13:40:31.478766 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6351 13:40:31.478981 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6352 13:40:31.481697 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6353 13:40:31.485486
6354 13:40:31.485758
6355 13:40:31.485929 ==
6356 13:40:31.488567 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 13:40:31.491656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 13:40:31.491882 ==
6359 13:40:31.492054
6360 13:40:31.492226
6361 13:40:31.495112 TX Vref Scan disable
6362 13:40:31.495481 == TX Byte 0 ==
6363 13:40:31.498467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 13:40:31.505331 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 13:40:31.505550 == TX Byte 1 ==
6366 13:40:31.508323 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 13:40:31.515004 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 13:40:31.515361 ==
6369 13:40:31.518864 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 13:40:31.521948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 13:40:31.522293 ==
6372 13:40:31.522593
6373 13:40:31.522852
6374 13:40:31.525494 TX Vref Scan disable
6375 13:40:31.525854 == TX Byte 0 ==
6376 13:40:31.531661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 13:40:31.535470 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 13:40:31.535830 == TX Byte 1 ==
6379 13:40:31.538320 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6380 13:40:31.545354 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6381 13:40:31.545803
6382 13:40:31.546129 [DATLAT]
6383 13:40:31.548748 Freq=400, CH0 RK0
6384 13:40:31.549353
6385 13:40:31.549793 DATLAT Default: 0xf
6386 13:40:31.552210 0, 0xFFFF, sum = 0
6387 13:40:31.552650 1, 0xFFFF, sum = 0
6388 13:40:31.555533 2, 0xFFFF, sum = 0
6389 13:40:31.555969 3, 0xFFFF, sum = 0
6390 13:40:31.558748 4, 0xFFFF, sum = 0
6391 13:40:31.559353 5, 0xFFFF, sum = 0
6392 13:40:31.561624 6, 0xFFFF, sum = 0
6393 13:40:31.562000 7, 0xFFFF, sum = 0
6394 13:40:31.565375 8, 0xFFFF, sum = 0
6395 13:40:31.565805 9, 0xFFFF, sum = 0
6396 13:40:31.568925 10, 0xFFFF, sum = 0
6397 13:40:31.569411 11, 0xFFFF, sum = 0
6398 13:40:31.571731 12, 0xFFFF, sum = 0
6399 13:40:31.572168 13, 0x0, sum = 1
6400 13:40:31.575273 14, 0x0, sum = 2
6401 13:40:31.575725 15, 0x0, sum = 3
6402 13:40:31.578400 16, 0x0, sum = 4
6403 13:40:31.578876 best_step = 14
6404 13:40:31.579371
6405 13:40:31.579701 ==
6406 13:40:31.581574 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 13:40:31.588780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 13:40:31.589239 ==
6409 13:40:31.589571 RX Vref Scan: 1
6410 13:40:31.589879
6411 13:40:31.591782 RX Vref 0 -> 0, step: 1
6412 13:40:31.592193
6413 13:40:31.595062 RX Delay -343 -> 252, step: 8
6414 13:40:31.595503
6415 13:40:31.598660 Set Vref, RX VrefLevel [Byte0]: 55
6416 13:40:31.601768 [Byte1]: 51
6417 13:40:31.602278
6418 13:40:31.604966 Final RX Vref Byte 0 = 55 to rank0
6419 13:40:31.608803 Final RX Vref Byte 1 = 51 to rank0
6420 13:40:31.611839 Final RX Vref Byte 0 = 55 to rank1
6421 13:40:31.614789 Final RX Vref Byte 1 = 51 to rank1==
6422 13:40:31.618493 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 13:40:31.621945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 13:40:31.625062 ==
6425 13:40:31.625547 DQS Delay:
6426 13:40:31.625955 DQS0 = 44, DQS1 = 56
6427 13:40:31.628728 DQM Delay:
6428 13:40:31.629393 DQM0 = 11, DQM1 = 12
6429 13:40:31.631800 DQ Delay:
6430 13:40:31.632217 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6431 13:40:31.634935 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6432 13:40:31.638663 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6433 13:40:31.641833 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6434 13:40:31.642287
6435 13:40:31.642745
6436 13:40:31.652253 [DQSOSCAuto] RK0, (LSB)MR18= 0x824f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6437 13:40:31.655155 CH0 RK0: MR19=C0C, MR18=824F
6438 13:40:31.658216 CH0_RK0: MR19=0xC0C, MR18=0x824F, DQSOSC=393, MR23=63, INC=382, DEC=254
6439 13:40:31.661597 ==
6440 13:40:31.664868 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 13:40:31.668575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 13:40:31.669124 ==
6443 13:40:31.671856 [Gating] SW mode calibration
6444 13:40:31.678461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6445 13:40:31.681501 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6446 13:40:31.688437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 13:40:31.691605 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 13:40:31.695017 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 13:40:31.701622 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 13:40:31.705235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 13:40:31.708132 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 13:40:31.715653 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 13:40:31.718735 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 13:40:31.721973 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 13:40:31.725300 Total UI for P1: 0, mck2ui 16
6456 13:40:31.728271 best dqsien dly found for B0: ( 0, 14, 24)
6457 13:40:31.731503 Total UI for P1: 0, mck2ui 16
6458 13:40:31.735200 best dqsien dly found for B1: ( 0, 14, 24)
6459 13:40:31.738488 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6460 13:40:31.742333 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6461 13:40:31.742750
6462 13:40:31.745146 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 13:40:31.751962 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 13:40:31.752547 [Gating] SW calibration Done
6465 13:40:31.753134 ==
6466 13:40:31.755053 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 13:40:31.761687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 13:40:31.762173 ==
6469 13:40:31.762521 RX Vref Scan: 0
6470 13:40:31.762908
6471 13:40:31.764886 RX Vref 0 -> 0, step: 1
6472 13:40:31.765371
6473 13:40:31.768187 RX Delay -410 -> 252, step: 16
6474 13:40:31.771843 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6475 13:40:31.775105 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6476 13:40:31.781861 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6477 13:40:31.785368 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6478 13:40:31.788254 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6479 13:40:31.792092 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6480 13:40:31.798320 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6481 13:40:31.801948 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6482 13:40:31.805161 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6483 13:40:31.808533 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6484 13:40:31.815001 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6485 13:40:31.818146 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6486 13:40:31.821813 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6487 13:40:31.825073 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6488 13:40:31.831569 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6489 13:40:31.834981 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6490 13:40:31.835409 ==
6491 13:40:31.838173 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 13:40:31.841842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 13:40:31.842266 ==
6494 13:40:31.844957 DQS Delay:
6495 13:40:31.845415 DQS0 = 35, DQS1 = 51
6496 13:40:31.845846 DQM Delay:
6497 13:40:31.848876 DQM0 = 4, DQM1 = 10
6498 13:40:31.849345 DQ Delay:
6499 13:40:31.851781 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6500 13:40:31.854894 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6501 13:40:31.858494 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6502 13:40:31.861597 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6503 13:40:31.862024
6504 13:40:31.862450
6505 13:40:31.862854 ==
6506 13:40:31.865041 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 13:40:31.868611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 13:40:31.869176 ==
6509 13:40:31.869533
6510 13:40:31.871647
6511 13:40:31.872051 TX Vref Scan disable
6512 13:40:31.875213 == TX Byte 0 ==
6513 13:40:31.878270 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6514 13:40:31.882100 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6515 13:40:31.885043 == TX Byte 1 ==
6516 13:40:31.888592 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6517 13:40:31.891584 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6518 13:40:31.891992 ==
6519 13:40:31.895214 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 13:40:31.898430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 13:40:31.898840 ==
6522 13:40:31.899178
6523 13:40:31.902130
6524 13:40:31.902553 TX Vref Scan disable
6525 13:40:31.905256 == TX Byte 0 ==
6526 13:40:31.908519 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6527 13:40:31.911952 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6528 13:40:31.912499 == TX Byte 1 ==
6529 13:40:31.918877 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6530 13:40:31.921654 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6531 13:40:31.922065
6532 13:40:31.922407 [DATLAT]
6533 13:40:31.925278 Freq=400, CH0 RK1
6534 13:40:31.925702
6535 13:40:31.926026 DATLAT Default: 0xe
6536 13:40:31.928890 0, 0xFFFF, sum = 0
6537 13:40:31.929362 1, 0xFFFF, sum = 0
6538 13:40:31.931764 2, 0xFFFF, sum = 0
6539 13:40:31.932219 3, 0xFFFF, sum = 0
6540 13:40:31.935204 4, 0xFFFF, sum = 0
6541 13:40:31.935634 5, 0xFFFF, sum = 0
6542 13:40:31.938690 6, 0xFFFF, sum = 0
6543 13:40:31.941552 7, 0xFFFF, sum = 0
6544 13:40:31.942035 8, 0xFFFF, sum = 0
6545 13:40:31.945367 9, 0xFFFF, sum = 0
6546 13:40:31.945802 10, 0xFFFF, sum = 0
6547 13:40:31.948617 11, 0xFFFF, sum = 0
6548 13:40:31.949093 12, 0xFFFF, sum = 0
6549 13:40:31.952136 13, 0x0, sum = 1
6550 13:40:31.952704 14, 0x0, sum = 2
6551 13:40:31.955148 15, 0x0, sum = 3
6552 13:40:31.955576 16, 0x0, sum = 4
6553 13:40:31.955914 best_step = 14
6554 13:40:31.958442
6555 13:40:31.958867 ==
6556 13:40:31.961488 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 13:40:31.965224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 13:40:31.965672 ==
6559 13:40:31.966002 RX Vref Scan: 0
6560 13:40:31.966379
6561 13:40:31.968917 RX Vref 0 -> 0, step: 1
6562 13:40:31.969390
6563 13:40:31.971880 RX Delay -343 -> 252, step: 8
6564 13:40:31.979236 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6565 13:40:31.982140 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6566 13:40:31.985371 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6567 13:40:31.988919 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6568 13:40:31.995610 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6569 13:40:31.999237 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6570 13:40:32.002306 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6571 13:40:32.005438 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6572 13:40:32.012362 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6573 13:40:32.016055 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6574 13:40:32.018959 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6575 13:40:32.022348 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6576 13:40:32.028938 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6577 13:40:32.032501 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6578 13:40:32.036216 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6579 13:40:32.039007 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6580 13:40:32.042772 ==
6581 13:40:32.045957 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 13:40:32.049461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 13:40:32.049897 ==
6584 13:40:32.050237 DQS Delay:
6585 13:40:32.052485 DQS0 = 48, DQS1 = 60
6586 13:40:32.052938 DQM Delay:
6587 13:40:32.055969 DQM0 = 13, DQM1 = 12
6588 13:40:32.056394 DQ Delay:
6589 13:40:32.059053 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6590 13:40:32.062573 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6591 13:40:32.065422 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6592 13:40:32.069150 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6593 13:40:32.069672
6594 13:40:32.070066
6595 13:40:32.075632 [DQSOSCAuto] RK1, (LSB)MR18= 0x9165, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6596 13:40:32.079355 CH0 RK1: MR19=C0C, MR18=9165
6597 13:40:32.085961 CH0_RK1: MR19=0xC0C, MR18=0x9165, DQSOSC=391, MR23=63, INC=386, DEC=257
6598 13:40:32.089146 [RxdqsGatingPostProcess] freq 400
6599 13:40:32.092094 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6600 13:40:32.096134 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 13:40:32.099296 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 13:40:32.102103 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 13:40:32.105732 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 13:40:32.108618 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 13:40:32.112624 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 13:40:32.115598 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 13:40:32.119377 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 13:40:32.122243 Pre-setting of DQS Precalculation
6609 13:40:32.125284 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6610 13:40:32.128962 ==
6611 13:40:32.129462 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 13:40:32.135390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 13:40:32.135847 ==
6614 13:40:32.138971 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 13:40:32.145662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6616 13:40:32.148891 [CA 0] Center 36 (8~64) winsize 57
6617 13:40:32.152609 [CA 1] Center 36 (8~64) winsize 57
6618 13:40:32.155746 [CA 2] Center 36 (8~64) winsize 57
6619 13:40:32.158795 [CA 3] Center 36 (8~64) winsize 57
6620 13:40:32.162540 [CA 4] Center 36 (8~64) winsize 57
6621 13:40:32.165560 [CA 5] Center 36 (8~64) winsize 57
6622 13:40:32.165990
6623 13:40:32.169252 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6624 13:40:32.169689
6625 13:40:32.171954 [CATrainingPosCal] consider 1 rank data
6626 13:40:32.175487 u2DelayCellTimex100 = 270/100 ps
6627 13:40:32.179255 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 13:40:32.182443 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 13:40:32.185573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 13:40:32.189461 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 13:40:32.192081 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 13:40:32.195737 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 13:40:32.196143
6634 13:40:32.202809 CA PerBit enable=1, Macro0, CA PI delay=36
6635 13:40:32.203519
6636 13:40:32.205954 [CBTSetCACLKResult] CA Dly = 36
6637 13:40:32.206398 CS Dly: 1 (0~32)
6638 13:40:32.206752 ==
6639 13:40:32.209372 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 13:40:32.212233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 13:40:32.212644 ==
6642 13:40:32.219071 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 13:40:32.225896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6644 13:40:32.229173 [CA 0] Center 36 (8~64) winsize 57
6645 13:40:32.232347 [CA 1] Center 36 (8~64) winsize 57
6646 13:40:32.235910 [CA 2] Center 36 (8~64) winsize 57
6647 13:40:32.236342 [CA 3] Center 36 (8~64) winsize 57
6648 13:40:32.239463 [CA 4] Center 36 (8~64) winsize 57
6649 13:40:32.242801 [CA 5] Center 36 (8~64) winsize 57
6650 13:40:32.243213
6651 13:40:32.245607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6652 13:40:32.249371
6653 13:40:32.252478 [CATrainingPosCal] consider 2 rank data
6654 13:40:32.252888 u2DelayCellTimex100 = 270/100 ps
6655 13:40:32.259434 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 13:40:32.262544 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 13:40:32.266095 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 13:40:32.269445 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 13:40:32.272945 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 13:40:32.276064 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 13:40:32.276476
6662 13:40:32.279528 CA PerBit enable=1, Macro0, CA PI delay=36
6663 13:40:32.279941
6664 13:40:32.282496 [CBTSetCACLKResult] CA Dly = 36
6665 13:40:32.286288 CS Dly: 1 (0~32)
6666 13:40:32.286712
6667 13:40:32.289230 ----->DramcWriteLeveling(PI) begin...
6668 13:40:32.289647 ==
6669 13:40:32.292594 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 13:40:32.295916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 13:40:32.296332 ==
6672 13:40:32.299298 Write leveling (Byte 0): 40 => 8
6673 13:40:32.302680 Write leveling (Byte 1): 40 => 8
6674 13:40:32.306236 DramcWriteLeveling(PI) end<-----
6675 13:40:32.306754
6676 13:40:32.307182 ==
6677 13:40:32.309423 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 13:40:32.312872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 13:40:32.313373 ==
6680 13:40:32.316405 [Gating] SW mode calibration
6681 13:40:32.322635 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6682 13:40:32.329160 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6683 13:40:32.332766 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 13:40:32.336023 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 13:40:32.339656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 13:40:32.346204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 13:40:32.349147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 13:40:32.352611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 13:40:32.359564 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 13:40:32.363178 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 13:40:32.366369 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 13:40:32.369426 Total UI for P1: 0, mck2ui 16
6693 13:40:32.373137 best dqsien dly found for B0: ( 0, 14, 24)
6694 13:40:32.376273 Total UI for P1: 0, mck2ui 16
6695 13:40:32.379103 best dqsien dly found for B1: ( 0, 14, 24)
6696 13:40:32.382829 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6697 13:40:32.385972 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6698 13:40:32.386445
6699 13:40:32.392777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 13:40:32.396370 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 13:40:32.399515 [Gating] SW calibration Done
6702 13:40:32.399923 ==
6703 13:40:32.402563 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 13:40:32.406263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 13:40:32.406811 ==
6706 13:40:32.407230 RX Vref Scan: 0
6707 13:40:32.407542
6708 13:40:32.409740 RX Vref 0 -> 0, step: 1
6709 13:40:32.410149
6710 13:40:32.412611 RX Delay -410 -> 252, step: 16
6711 13:40:32.415925 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6712 13:40:32.422701 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6713 13:40:32.426095 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6714 13:40:32.429172 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6715 13:40:32.433077 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6716 13:40:32.436296 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6717 13:40:32.442788 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6718 13:40:32.446416 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6719 13:40:32.449653 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6720 13:40:32.452690 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6721 13:40:32.459543 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6722 13:40:32.463137 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6723 13:40:32.466022 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6724 13:40:32.469732 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6725 13:40:32.476726 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6726 13:40:32.479664 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6727 13:40:32.480076 ==
6728 13:40:32.482958 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 13:40:32.486005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 13:40:32.486451 ==
6731 13:40:32.489402 DQS Delay:
6732 13:40:32.489807 DQS0 = 51, DQS1 = 59
6733 13:40:32.493086 DQM Delay:
6734 13:40:32.493629 DQM0 = 19, DQM1 = 17
6735 13:40:32.493965 DQ Delay:
6736 13:40:32.496223 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6737 13:40:32.499438 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6738 13:40:32.502961 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6739 13:40:32.506051 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6740 13:40:32.506468
6741 13:40:32.506833
6742 13:40:32.507137 ==
6743 13:40:32.509764 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 13:40:32.516375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 13:40:32.516788 ==
6746 13:40:32.517161
6747 13:40:32.517465
6748 13:40:32.517752 TX Vref Scan disable
6749 13:40:32.519383 == TX Byte 0 ==
6750 13:40:32.523210 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 13:40:32.526378 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 13:40:32.530217 == TX Byte 1 ==
6753 13:40:32.533030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 13:40:32.536292 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 13:40:32.536705 ==
6756 13:40:32.539604 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 13:40:32.546548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 13:40:32.546962 ==
6759 13:40:32.547331
6760 13:40:32.547642
6761 13:40:32.547931 TX Vref Scan disable
6762 13:40:32.549794 == TX Byte 0 ==
6763 13:40:32.553045 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 13:40:32.556320 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 13:40:32.559689 == TX Byte 1 ==
6766 13:40:32.563214 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 13:40:32.566382 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 13:40:32.566806
6769 13:40:32.569503 [DATLAT]
6770 13:40:32.569911 Freq=400, CH1 RK0
6771 13:40:32.570236
6772 13:40:32.572900 DATLAT Default: 0xf
6773 13:40:32.573350 0, 0xFFFF, sum = 0
6774 13:40:32.576596 1, 0xFFFF, sum = 0
6775 13:40:32.577052 2, 0xFFFF, sum = 0
6776 13:40:32.579747 3, 0xFFFF, sum = 0
6777 13:40:32.580163 4, 0xFFFF, sum = 0
6778 13:40:32.583307 5, 0xFFFF, sum = 0
6779 13:40:32.583726 6, 0xFFFF, sum = 0
6780 13:40:32.586455 7, 0xFFFF, sum = 0
6781 13:40:32.586986 8, 0xFFFF, sum = 0
6782 13:40:32.590017 9, 0xFFFF, sum = 0
6783 13:40:32.590433 10, 0xFFFF, sum = 0
6784 13:40:32.593205 11, 0xFFFF, sum = 0
6785 13:40:32.596691 12, 0xFFFF, sum = 0
6786 13:40:32.597162 13, 0x0, sum = 1
6787 13:40:32.597511 14, 0x0, sum = 2
6788 13:40:32.599801 15, 0x0, sum = 3
6789 13:40:32.600221 16, 0x0, sum = 4
6790 13:40:32.603677 best_step = 14
6791 13:40:32.604098
6792 13:40:32.604423 ==
6793 13:40:32.606687 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 13:40:32.609658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 13:40:32.610128 ==
6796 13:40:32.613310 RX Vref Scan: 1
6797 13:40:32.613732
6798 13:40:32.614060 RX Vref 0 -> 0, step: 1
6799 13:40:32.614369
6800 13:40:32.616565 RX Delay -359 -> 252, step: 8
6801 13:40:32.617026
6802 13:40:32.619631 Set Vref, RX VrefLevel [Byte0]: 56
6803 13:40:32.623127 [Byte1]: 51
6804 13:40:32.628069
6805 13:40:32.628478 Final RX Vref Byte 0 = 56 to rank0
6806 13:40:32.631333 Final RX Vref Byte 1 = 51 to rank0
6807 13:40:32.635053 Final RX Vref Byte 0 = 56 to rank1
6808 13:40:32.637932 Final RX Vref Byte 1 = 51 to rank1==
6809 13:40:32.641694 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 13:40:32.647948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 13:40:32.648362 ==
6812 13:40:32.648690 DQS Delay:
6813 13:40:32.649029 DQS0 = 48, DQS1 = 60
6814 13:40:32.651618 DQM Delay:
6815 13:40:32.652026 DQM0 = 12, DQM1 = 13
6816 13:40:32.654866 DQ Delay:
6817 13:40:32.655279 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6818 13:40:32.658266 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6819 13:40:32.661336 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6820 13:40:32.664656 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6821 13:40:32.665242
6822 13:40:32.665701
6823 13:40:32.674873 [DQSOSCAuto] RK0, (LSB)MR18= 0x842b, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6824 13:40:32.678224 CH1 RK0: MR19=C0C, MR18=842B
6825 13:40:32.681588 CH1_RK0: MR19=0xC0C, MR18=0x842B, DQSOSC=393, MR23=63, INC=382, DEC=254
6826 13:40:32.684903 ==
6827 13:40:32.688286 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 13:40:32.691610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 13:40:32.692026 ==
6830 13:40:32.695064 [Gating] SW mode calibration
6831 13:40:32.701637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6832 13:40:32.704930 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6833 13:40:32.711660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 13:40:32.714886 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 13:40:32.718406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 13:40:32.725199 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 13:40:32.728217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 13:40:32.731439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 13:40:32.738294 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 13:40:32.741955 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 13:40:32.744922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 13:40:32.748584 Total UI for P1: 0, mck2ui 16
6843 13:40:32.751642 best dqsien dly found for B0: ( 0, 14, 24)
6844 13:40:32.755315 Total UI for P1: 0, mck2ui 16
6845 13:40:32.758630 best dqsien dly found for B1: ( 0, 14, 24)
6846 13:40:32.761504 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6847 13:40:32.765140 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6848 13:40:32.765563
6849 13:40:32.768873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 13:40:32.775344 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 13:40:32.775757 [Gating] SW calibration Done
6852 13:40:32.776084 ==
6853 13:40:32.778759 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 13:40:32.784954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 13:40:32.785075 ==
6856 13:40:32.785139 RX Vref Scan: 0
6857 13:40:32.785198
6858 13:40:32.787886 RX Vref 0 -> 0, step: 1
6859 13:40:32.787966
6860 13:40:32.791636 RX Delay -410 -> 252, step: 16
6861 13:40:32.794643 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6862 13:40:32.798395 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6863 13:40:32.804884 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6864 13:40:32.807744 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6865 13:40:32.811429 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6866 13:40:32.814737 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6867 13:40:32.821518 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6868 13:40:32.825113 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6869 13:40:32.828224 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6870 13:40:32.831623 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6871 13:40:32.834759 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6872 13:40:32.841636 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6873 13:40:32.844766 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6874 13:40:32.847718 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6875 13:40:32.855219 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6876 13:40:32.858058 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6877 13:40:32.858154 ==
6878 13:40:32.861386 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 13:40:32.864941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 13:40:32.865052 ==
6881 13:40:32.868219 DQS Delay:
6882 13:40:32.868351 DQS0 = 43, DQS1 = 59
6883 13:40:32.868464 DQM Delay:
6884 13:40:32.871258 DQM0 = 9, DQM1 = 18
6885 13:40:32.871358 DQ Delay:
6886 13:40:32.874909 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6887 13:40:32.878019 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6888 13:40:32.881699 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6889 13:40:32.884687 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =24
6890 13:40:32.884819
6891 13:40:32.884924
6892 13:40:32.885044 ==
6893 13:40:32.888372 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 13:40:32.891286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 13:40:32.891435 ==
6896 13:40:32.891554
6897 13:40:32.895015
6898 13:40:32.895183 TX Vref Scan disable
6899 13:40:32.898188 == TX Byte 0 ==
6900 13:40:32.901291 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6901 13:40:32.904957 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6902 13:40:32.908704 == TX Byte 1 ==
6903 13:40:32.911487 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6904 13:40:32.914736 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6905 13:40:32.915116 ==
6906 13:40:32.918504 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 13:40:32.921421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 13:40:32.921835 ==
6909 13:40:32.922245
6910 13:40:32.924765
6911 13:40:32.925255 TX Vref Scan disable
6912 13:40:32.928202 == TX Byte 0 ==
6913 13:40:32.931284 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6914 13:40:32.934757 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6915 13:40:32.938385 == TX Byte 1 ==
6916 13:40:32.941795 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6917 13:40:32.945158 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6918 13:40:32.945592
6919 13:40:32.945997 [DATLAT]
6920 13:40:32.948201 Freq=400, CH1 RK1
6921 13:40:32.948691
6922 13:40:32.949089 DATLAT Default: 0xe
6923 13:40:32.951669 0, 0xFFFF, sum = 0
6924 13:40:32.952113 1, 0xFFFF, sum = 0
6925 13:40:32.955279 2, 0xFFFF, sum = 0
6926 13:40:32.955786 3, 0xFFFF, sum = 0
6927 13:40:32.958194 4, 0xFFFF, sum = 0
6928 13:40:32.961670 5, 0xFFFF, sum = 0
6929 13:40:32.962096 6, 0xFFFF, sum = 0
6930 13:40:32.964695 7, 0xFFFF, sum = 0
6931 13:40:32.965137 8, 0xFFFF, sum = 0
6932 13:40:32.968623 9, 0xFFFF, sum = 0
6933 13:40:32.969074 10, 0xFFFF, sum = 0
6934 13:40:32.971667 11, 0xFFFF, sum = 0
6935 13:40:32.972087 12, 0xFFFF, sum = 0
6936 13:40:32.975319 13, 0x0, sum = 1
6937 13:40:32.975739 14, 0x0, sum = 2
6938 13:40:32.978304 15, 0x0, sum = 3
6939 13:40:32.978829 16, 0x0, sum = 4
6940 13:40:32.979195 best_step = 14
6941 13:40:32.981329
6942 13:40:32.981772 ==
6943 13:40:32.984956 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 13:40:32.987985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 13:40:32.988496 ==
6946 13:40:32.988871 RX Vref Scan: 0
6947 13:40:32.989274
6948 13:40:32.991858 RX Vref 0 -> 0, step: 1
6949 13:40:32.992407
6950 13:40:32.995079 RX Delay -359 -> 252, step: 8
6951 13:40:33.001852 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6952 13:40:33.005663 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6953 13:40:33.008543 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6954 13:40:33.012221 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6955 13:40:33.018773 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6956 13:40:33.021818 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6957 13:40:33.025545 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6958 13:40:33.028588 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6959 13:40:33.035544 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6960 13:40:33.038843 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6961 13:40:33.042129 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6962 13:40:33.045183 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6963 13:40:33.052065 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6964 13:40:33.055610 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6965 13:40:33.058491 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6966 13:40:33.065537 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6967 13:40:33.065955 ==
6968 13:40:33.068760 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 13:40:33.072044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 13:40:33.072457 ==
6971 13:40:33.072780 DQS Delay:
6972 13:40:33.075252 DQS0 = 52, DQS1 = 56
6973 13:40:33.075662 DQM Delay:
6974 13:40:33.079127 DQM0 = 13, DQM1 = 9
6975 13:40:33.079537 DQ Delay:
6976 13:40:33.082726 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6977 13:40:33.085709 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6978 13:40:33.088630 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6979 13:40:33.091887 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6980 13:40:33.092296
6981 13:40:33.092618
6982 13:40:33.098458 [DQSOSCAuto] RK1, (LSB)MR18= 0x7288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6983 13:40:33.101893 CH1 RK1: MR19=C0C, MR18=7288
6984 13:40:33.108658 CH1_RK1: MR19=0xC0C, MR18=0x7288, DQSOSC=392, MR23=63, INC=384, DEC=256
6985 13:40:33.111835 [RxdqsGatingPostProcess] freq 400
6986 13:40:33.115555 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6987 13:40:33.118526 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 13:40:33.121843 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 13:40:33.124915 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 13:40:33.128597 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 13:40:33.131570 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 13:40:33.135318 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 13:40:33.138537 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 13:40:33.141925 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 13:40:33.145466 Pre-setting of DQS Precalculation
6996 13:40:33.148360 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6997 13:40:33.158917 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6998 13:40:33.165298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6999 13:40:33.165715
7000 13:40:33.166041
7001 13:40:33.168484 [Calibration Summary] 800 Mbps
7002 13:40:33.168895 CH 0, Rank 0
7003 13:40:33.172092 SW Impedance : PASS
7004 13:40:33.172515 DUTY Scan : NO K
7005 13:40:33.174978 ZQ Calibration : PASS
7006 13:40:33.178560 Jitter Meter : NO K
7007 13:40:33.179066 CBT Training : PASS
7008 13:40:33.182222 Write leveling : PASS
7009 13:40:33.184958 RX DQS gating : PASS
7010 13:40:33.185389 RX DQ/DQS(RDDQC) : PASS
7011 13:40:33.188716 TX DQ/DQS : PASS
7012 13:40:33.191769 RX DATLAT : PASS
7013 13:40:33.192179 RX DQ/DQS(Engine): PASS
7014 13:40:33.195293 TX OE : NO K
7015 13:40:33.195705 All Pass.
7016 13:40:33.196031
7017 13:40:33.198704 CH 0, Rank 1
7018 13:40:33.199180 SW Impedance : PASS
7019 13:40:33.201802 DUTY Scan : NO K
7020 13:40:33.202217 ZQ Calibration : PASS
7021 13:40:33.205320 Jitter Meter : NO K
7022 13:40:33.208260 CBT Training : PASS
7023 13:40:33.208672 Write leveling : NO K
7024 13:40:33.211774 RX DQS gating : PASS
7025 13:40:33.215573 RX DQ/DQS(RDDQC) : PASS
7026 13:40:33.216026 TX DQ/DQS : PASS
7027 13:40:33.218856 RX DATLAT : PASS
7028 13:40:33.221801 RX DQ/DQS(Engine): PASS
7029 13:40:33.222215 TX OE : NO K
7030 13:40:33.224796 All Pass.
7031 13:40:33.225235
7032 13:40:33.225563 CH 1, Rank 0
7033 13:40:33.228383 SW Impedance : PASS
7034 13:40:33.228810 DUTY Scan : NO K
7035 13:40:33.232092 ZQ Calibration : PASS
7036 13:40:33.235305 Jitter Meter : NO K
7037 13:40:33.235716 CBT Training : PASS
7038 13:40:33.238219 Write leveling : PASS
7039 13:40:33.241861 RX DQS gating : PASS
7040 13:40:33.242273 RX DQ/DQS(RDDQC) : PASS
7041 13:40:33.245020 TX DQ/DQS : PASS
7042 13:40:33.245435 RX DATLAT : PASS
7043 13:40:33.248363 RX DQ/DQS(Engine): PASS
7044 13:40:33.251943 TX OE : NO K
7045 13:40:33.252502 All Pass.
7046 13:40:33.253009
7047 13:40:33.253476 CH 1, Rank 1
7048 13:40:33.254908 SW Impedance : PASS
7049 13:40:33.258711 DUTY Scan : NO K
7050 13:40:33.259243 ZQ Calibration : PASS
7051 13:40:33.261798 Jitter Meter : NO K
7052 13:40:33.264848 CBT Training : PASS
7053 13:40:33.265313 Write leveling : NO K
7054 13:40:33.268541 RX DQS gating : PASS
7055 13:40:33.271918 RX DQ/DQS(RDDQC) : PASS
7056 13:40:33.272336 TX DQ/DQS : PASS
7057 13:40:33.275123 RX DATLAT : PASS
7058 13:40:33.278670 RX DQ/DQS(Engine): PASS
7059 13:40:33.279136 TX OE : NO K
7060 13:40:33.279468 All Pass.
7061 13:40:33.279774
7062 13:40:33.281683 DramC Write-DBI off
7063 13:40:33.285253 PER_BANK_REFRESH: Hybrid Mode
7064 13:40:33.285667 TX_TRACKING: ON
7065 13:40:33.294927 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7066 13:40:33.298339 [FAST_K] Save calibration result to emmc
7067 13:40:33.301567 dramc_set_vcore_voltage set vcore to 725000
7068 13:40:33.305399 Read voltage for 1600, 0
7069 13:40:33.305813 Vio18 = 0
7070 13:40:33.308417 Vcore = 725000
7071 13:40:33.308830 Vdram = 0
7072 13:40:33.309258 Vddq = 0
7073 13:40:33.309721 Vmddr = 0
7074 13:40:33.315405 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7075 13:40:33.322207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7076 13:40:33.322640 MEM_TYPE=3, freq_sel=13
7077 13:40:33.325431 sv_algorithm_assistance_LP4_3733
7078 13:40:33.328696 ============ PULL DRAM RESETB DOWN ============
7079 13:40:33.335576 ========== PULL DRAM RESETB DOWN end =========
7080 13:40:33.338607 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7081 13:40:33.342282 ===================================
7082 13:40:33.345370 LPDDR4 DRAM CONFIGURATION
7083 13:40:33.348623 ===================================
7084 13:40:33.349099 EX_ROW_EN[0] = 0x0
7085 13:40:33.351965 EX_ROW_EN[1] = 0x0
7086 13:40:33.352394 LP4Y_EN = 0x0
7087 13:40:33.355729 WORK_FSP = 0x1
7088 13:40:33.356156 WL = 0x5
7089 13:40:33.358556 RL = 0x5
7090 13:40:33.358988 BL = 0x2
7091 13:40:33.362129 RPST = 0x0
7092 13:40:33.362542 RD_PRE = 0x0
7093 13:40:33.365215 WR_PRE = 0x1
7094 13:40:33.365648 WR_PST = 0x1
7095 13:40:33.368742 DBI_WR = 0x0
7096 13:40:33.369214 DBI_RD = 0x0
7097 13:40:33.372195 OTF = 0x1
7098 13:40:33.375367 ===================================
7099 13:40:33.378588 ===================================
7100 13:40:33.379021 ANA top config
7101 13:40:33.382191 ===================================
7102 13:40:33.385162 DLL_ASYNC_EN = 0
7103 13:40:33.388943 ALL_SLAVE_EN = 0
7104 13:40:33.391867 NEW_RANK_MODE = 1
7105 13:40:33.392290 DLL_IDLE_MODE = 1
7106 13:40:33.395405 LP45_APHY_COMB_EN = 1
7107 13:40:33.398529 TX_ODT_DIS = 0
7108 13:40:33.401824 NEW_8X_MODE = 1
7109 13:40:33.405348 ===================================
7110 13:40:33.408538 ===================================
7111 13:40:33.412070 data_rate = 3200
7112 13:40:33.412576 CKR = 1
7113 13:40:33.415495 DQ_P2S_RATIO = 8
7114 13:40:33.418258 ===================================
7115 13:40:33.421858 CA_P2S_RATIO = 8
7116 13:40:33.425487 DQ_CA_OPEN = 0
7117 13:40:33.428411 DQ_SEMI_OPEN = 0
7118 13:40:33.432150 CA_SEMI_OPEN = 0
7119 13:40:33.432569 CA_FULL_RATE = 0
7120 13:40:33.435228 DQ_CKDIV4_EN = 0
7121 13:40:33.438729 CA_CKDIV4_EN = 0
7122 13:40:33.441977 CA_PREDIV_EN = 0
7123 13:40:33.445400 PH8_DLY = 12
7124 13:40:33.448434 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7125 13:40:33.448852 DQ_AAMCK_DIV = 4
7126 13:40:33.451832 CA_AAMCK_DIV = 4
7127 13:40:33.455642 CA_ADMCK_DIV = 4
7128 13:40:33.458625 DQ_TRACK_CA_EN = 0
7129 13:40:33.462256 CA_PICK = 1600
7130 13:40:33.465119 CA_MCKIO = 1600
7131 13:40:33.468756 MCKIO_SEMI = 0
7132 13:40:33.469239 PLL_FREQ = 3068
7133 13:40:33.471768 DQ_UI_PI_RATIO = 32
7134 13:40:33.475460 CA_UI_PI_RATIO = 0
7135 13:40:33.478463 ===================================
7136 13:40:33.482294 ===================================
7137 13:40:33.485310 memory_type:LPDDR4
7138 13:40:33.485802 GP_NUM : 10
7139 13:40:33.489010 SRAM_EN : 1
7140 13:40:33.492171 MD32_EN : 0
7141 13:40:33.495714 ===================================
7142 13:40:33.496152 [ANA_INIT] >>>>>>>>>>>>>>
7143 13:40:33.498732 <<<<<< [CONFIGURE PHASE]: ANA_TX
7144 13:40:33.501804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7145 13:40:33.505041 ===================================
7146 13:40:33.508670 data_rate = 3200,PCW = 0X7600
7147 13:40:33.511783 ===================================
7148 13:40:33.515370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7149 13:40:33.522658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 13:40:33.525314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 13:40:33.532318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7152 13:40:33.535769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7153 13:40:33.538748 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7154 13:40:33.539173 [ANA_INIT] flow start
7155 13:40:33.542337 [ANA_INIT] PLL >>>>>>>>
7156 13:40:33.545374 [ANA_INIT] PLL <<<<<<<<
7157 13:40:33.545790 [ANA_INIT] MIDPI >>>>>>>>
7158 13:40:33.548941 [ANA_INIT] MIDPI <<<<<<<<
7159 13:40:33.551976 [ANA_INIT] DLL >>>>>>>>
7160 13:40:33.552397 [ANA_INIT] DLL <<<<<<<<
7161 13:40:33.555520 [ANA_INIT] flow end
7162 13:40:33.558753 ============ LP4 DIFF to SE enter ============
7163 13:40:33.565574 ============ LP4 DIFF to SE exit ============
7164 13:40:33.566005 [ANA_INIT] <<<<<<<<<<<<<
7165 13:40:33.568529 [Flow] Enable top DCM control >>>>>
7166 13:40:33.572123 [Flow] Enable top DCM control <<<<<
7167 13:40:33.575850 Enable DLL master slave shuffle
7168 13:40:33.582473 ==============================================================
7169 13:40:33.582902 Gating Mode config
7170 13:40:33.589049 ==============================================================
7171 13:40:33.592029 Config description:
7172 13:40:33.598671 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7173 13:40:33.605624 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7174 13:40:33.612430 SELPH_MODE 0: By rank 1: By Phase
7175 13:40:33.618607 ==============================================================
7176 13:40:33.619107 GAT_TRACK_EN = 1
7177 13:40:33.621781 RX_GATING_MODE = 2
7178 13:40:33.625827 RX_GATING_TRACK_MODE = 2
7179 13:40:33.628803 SELPH_MODE = 1
7180 13:40:33.631726 PICG_EARLY_EN = 1
7181 13:40:33.635286 VALID_LAT_VALUE = 1
7182 13:40:33.641865 ==============================================================
7183 13:40:33.645291 Enter into Gating configuration >>>>
7184 13:40:33.648278 Exit from Gating configuration <<<<
7185 13:40:33.651483 Enter into DVFS_PRE_config >>>>>
7186 13:40:33.661840 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7187 13:40:33.665153 Exit from DVFS_PRE_config <<<<<
7188 13:40:33.668092 Enter into PICG configuration >>>>
7189 13:40:33.671647 Exit from PICG configuration <<<<
7190 13:40:33.674793 [RX_INPUT] configuration >>>>>
7191 13:40:33.675228 [RX_INPUT] configuration <<<<<
7192 13:40:33.681419 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7193 13:40:33.688688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7194 13:40:33.691716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 13:40:33.698374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 13:40:33.705059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 13:40:33.711991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 13:40:33.715054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7199 13:40:33.718048 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7200 13:40:33.724958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7201 13:40:33.728658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7202 13:40:33.731857 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7203 13:40:33.738827 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 13:40:33.739237 ===================================
7205 13:40:33.741555 LPDDR4 DRAM CONFIGURATION
7206 13:40:33.745207 ===================================
7207 13:40:33.748143 EX_ROW_EN[0] = 0x0
7208 13:40:33.748568 EX_ROW_EN[1] = 0x0
7209 13:40:33.751722 LP4Y_EN = 0x0
7210 13:40:33.752232 WORK_FSP = 0x1
7211 13:40:33.755143 WL = 0x5
7212 13:40:33.755584 RL = 0x5
7213 13:40:33.758269 BL = 0x2
7214 13:40:33.758722 RPST = 0x0
7215 13:40:33.761790 RD_PRE = 0x0
7216 13:40:33.764721 WR_PRE = 0x1
7217 13:40:33.765200 WR_PST = 0x1
7218 13:40:33.768463 DBI_WR = 0x0
7219 13:40:33.768871 DBI_RD = 0x0
7220 13:40:33.771909 OTF = 0x1
7221 13:40:33.775145 ===================================
7222 13:40:33.778380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7223 13:40:33.781913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7224 13:40:33.784820 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 13:40:33.788393 ===================================
7226 13:40:33.791973 LPDDR4 DRAM CONFIGURATION
7227 13:40:33.794749 ===================================
7228 13:40:33.798640 EX_ROW_EN[0] = 0x10
7229 13:40:33.799056 EX_ROW_EN[1] = 0x0
7230 13:40:33.801855 LP4Y_EN = 0x0
7231 13:40:33.802266 WORK_FSP = 0x1
7232 13:40:33.805373 WL = 0x5
7233 13:40:33.805782 RL = 0x5
7234 13:40:33.808383 BL = 0x2
7235 13:40:33.808794 RPST = 0x0
7236 13:40:33.812019 RD_PRE = 0x0
7237 13:40:33.812443 WR_PRE = 0x1
7238 13:40:33.815027 WR_PST = 0x1
7239 13:40:33.815436 DBI_WR = 0x0
7240 13:40:33.818724 DBI_RD = 0x0
7241 13:40:33.819135 OTF = 0x1
7242 13:40:33.821463 ===================================
7243 13:40:33.828345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7244 13:40:33.828760 ==
7245 13:40:33.832066 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 13:40:33.838475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7247 13:40:33.838975 ==
7248 13:40:33.839404 [Duty_Offset_Calibration]
7249 13:40:33.842078 B0:2 B1:-1 CA:1
7250 13:40:33.842512
7251 13:40:33.845046 [DutyScan_Calibration_Flow] k_type=0
7252 13:40:33.853898
7253 13:40:33.854325 ==CLK 0==
7254 13:40:33.856637 Final CLK duty delay cell = -4
7255 13:40:33.860045 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7256 13:40:33.863473 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7257 13:40:33.867198 [-4] AVG Duty = 4937%(X100)
7258 13:40:33.867629
7259 13:40:33.870363 CH0 CLK Duty spec in!! Max-Min= 187%
7260 13:40:33.873961 [DutyScan_Calibration_Flow] ====Done====
7261 13:40:33.874378
7262 13:40:33.877183 [DutyScan_Calibration_Flow] k_type=1
7263 13:40:33.893277
7264 13:40:33.893833 ==DQS 0 ==
7265 13:40:33.896348 Final DQS duty delay cell = 0
7266 13:40:33.899506 [0] MAX Duty = 5125%(X100), DQS PI = 20
7267 13:40:33.903147 [0] MIN Duty = 5000%(X100), DQS PI = 16
7268 13:40:33.903566 [0] AVG Duty = 5062%(X100)
7269 13:40:33.906394
7270 13:40:33.906890 ==DQS 1 ==
7271 13:40:33.909909 Final DQS duty delay cell = -4
7272 13:40:33.913061 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7273 13:40:33.916676 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7274 13:40:33.919588 [-4] AVG Duty = 5046%(X100)
7275 13:40:33.920247
7276 13:40:33.922869 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7277 13:40:33.923375
7278 13:40:33.926700 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7279 13:40:33.929601 [DutyScan_Calibration_Flow] ====Done====
7280 13:40:33.930011
7281 13:40:33.933099 [DutyScan_Calibration_Flow] k_type=3
7282 13:40:33.950186
7283 13:40:33.950594 ==DQM 0 ==
7284 13:40:33.953901 Final DQM duty delay cell = 0
7285 13:40:33.957056 [0] MAX Duty = 5000%(X100), DQS PI = 18
7286 13:40:33.960462 [0] MIN Duty = 4875%(X100), DQS PI = 4
7287 13:40:33.960879 [0] AVG Duty = 4937%(X100)
7288 13:40:33.963994
7289 13:40:33.964449 ==DQM 1 ==
7290 13:40:33.967035 Final DQM duty delay cell = 0
7291 13:40:33.970563 [0] MAX Duty = 5187%(X100), DQS PI = 58
7292 13:40:33.973730 [0] MIN Duty = 4938%(X100), DQS PI = 20
7293 13:40:33.974215 [0] AVG Duty = 5062%(X100)
7294 13:40:33.977313
7295 13:40:33.980380 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7296 13:40:33.980820
7297 13:40:33.984143 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7298 13:40:33.987375 [DutyScan_Calibration_Flow] ====Done====
7299 13:40:33.987812
7300 13:40:33.990392 [DutyScan_Calibration_Flow] k_type=2
7301 13:40:34.006757
7302 13:40:34.007328 ==DQ 0 ==
7303 13:40:34.010083 Final DQ duty delay cell = -4
7304 13:40:34.013383 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7305 13:40:34.016630 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7306 13:40:34.020018 [-4] AVG Duty = 4922%(X100)
7307 13:40:34.020430
7308 13:40:34.020752 ==DQ 1 ==
7309 13:40:34.023270 Final DQ duty delay cell = 0
7310 13:40:34.026430 [0] MAX Duty = 5031%(X100), DQS PI = 30
7311 13:40:34.030131 [0] MIN Duty = 4907%(X100), DQS PI = 18
7312 13:40:34.033112 [0] AVG Duty = 4969%(X100)
7313 13:40:34.033553
7314 13:40:34.036502 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7315 13:40:34.036945
7316 13:40:34.040033 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7317 13:40:34.043638 [DutyScan_Calibration_Flow] ====Done====
7318 13:40:34.044077 ==
7319 13:40:34.046831 Dram Type= 6, Freq= 0, CH_1, rank 0
7320 13:40:34.049835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7321 13:40:34.050320 ==
7322 13:40:34.053789 [Duty_Offset_Calibration]
7323 13:40:34.054230 B0:1 B1:1 CA:2
7324 13:40:34.054554
7325 13:40:34.056624 [DutyScan_Calibration_Flow] k_type=0
7326 13:40:34.067492
7327 13:40:34.067931 ==CLK 0==
7328 13:40:34.070588 Final CLK duty delay cell = 0
7329 13:40:34.074070 [0] MAX Duty = 5187%(X100), DQS PI = 24
7330 13:40:34.077267 [0] MIN Duty = 4938%(X100), DQS PI = 50
7331 13:40:34.077708 [0] AVG Duty = 5062%(X100)
7332 13:40:34.078031
7333 13:40:34.080926 CH1 CLK Duty spec in!! Max-Min= 249%
7334 13:40:34.087769 [DutyScan_Calibration_Flow] ====Done====
7335 13:40:34.088344
7336 13:40:34.090602 [DutyScan_Calibration_Flow] k_type=1
7337 13:40:34.107621
7338 13:40:34.108069 ==DQS 0 ==
7339 13:40:34.110376 Final DQS duty delay cell = 0
7340 13:40:34.113821 [0] MAX Duty = 5062%(X100), DQS PI = 22
7341 13:40:34.116773 [0] MIN Duty = 4813%(X100), DQS PI = 44
7342 13:40:34.120651 [0] AVG Duty = 4937%(X100)
7343 13:40:34.121149
7344 13:40:34.121481 ==DQS 1 ==
7345 13:40:34.123636 Final DQS duty delay cell = 0
7346 13:40:34.127431 [0] MAX Duty = 5031%(X100), DQS PI = 58
7347 13:40:34.130463 [0] MIN Duty = 4938%(X100), DQS PI = 0
7348 13:40:34.133760 [0] AVG Duty = 4984%(X100)
7349 13:40:34.134432
7350 13:40:34.137227 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7351 13:40:34.137637
7352 13:40:34.140208 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7353 13:40:34.143920 [DutyScan_Calibration_Flow] ====Done====
7354 13:40:34.144333
7355 13:40:34.147029 [DutyScan_Calibration_Flow] k_type=3
7356 13:40:34.163645
7357 13:40:34.164331 ==DQM 0 ==
7358 13:40:34.167348 Final DQM duty delay cell = 0
7359 13:40:34.170220 [0] MAX Duty = 5156%(X100), DQS PI = 20
7360 13:40:34.173605 [0] MIN Duty = 4813%(X100), DQS PI = 50
7361 13:40:34.177496 [0] AVG Duty = 4984%(X100)
7362 13:40:34.177900
7363 13:40:34.178369 ==DQM 1 ==
7364 13:40:34.180528 Final DQM duty delay cell = 0
7365 13:40:34.183691 [0] MAX Duty = 5156%(X100), DQS PI = 60
7366 13:40:34.187415 [0] MIN Duty = 4907%(X100), DQS PI = 18
7367 13:40:34.187879 [0] AVG Duty = 5031%(X100)
7368 13:40:34.190891
7369 13:40:34.193771 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7370 13:40:34.194214
7371 13:40:34.197371 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7372 13:40:34.200969 [DutyScan_Calibration_Flow] ====Done====
7373 13:40:34.201450
7374 13:40:34.203799 [DutyScan_Calibration_Flow] k_type=2
7375 13:40:34.221033
7376 13:40:34.221444 ==DQ 0 ==
7377 13:40:34.224447 Final DQ duty delay cell = 0
7378 13:40:34.227867 [0] MAX Duty = 5156%(X100), DQS PI = 20
7379 13:40:34.231318 [0] MIN Duty = 4907%(X100), DQS PI = 50
7380 13:40:34.231738 [0] AVG Duty = 5031%(X100)
7381 13:40:34.234144
7382 13:40:34.234554 ==DQ 1 ==
7383 13:40:34.237706 Final DQ duty delay cell = 0
7384 13:40:34.240613 [0] MAX Duty = 5093%(X100), DQS PI = 6
7385 13:40:34.243910 [0] MIN Duty = 5031%(X100), DQS PI = 0
7386 13:40:34.244390 [0] AVG Duty = 5062%(X100)
7387 13:40:34.244809
7388 13:40:34.247283 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7389 13:40:34.247759
7390 13:40:34.250762 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7391 13:40:34.257174 [DutyScan_Calibration_Flow] ====Done====
7392 13:40:34.260880 nWR fixed to 30
7393 13:40:34.261355 [ModeRegInit_LP4] CH0 RK0
7394 13:40:34.263981 [ModeRegInit_LP4] CH0 RK1
7395 13:40:34.267751 [ModeRegInit_LP4] CH1 RK0
7396 13:40:34.268216 [ModeRegInit_LP4] CH1 RK1
7397 13:40:34.270844 match AC timing 5
7398 13:40:34.274502 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7399 13:40:34.277252 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7400 13:40:34.283936 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7401 13:40:34.287702 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7402 13:40:34.294270 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7403 13:40:34.294683 [MiockJmeterHQA]
7404 13:40:34.295008
7405 13:40:34.297517 [DramcMiockJmeter] u1RxGatingPI = 0
7406 13:40:34.297953 0 : 4255, 4029
7407 13:40:34.301057 4 : 4368, 4140
7408 13:40:34.301504 8 : 4252, 4027
7409 13:40:34.304387 12 : 4252, 4027
7410 13:40:34.304803 16 : 4252, 4027
7411 13:40:34.307377 20 : 4252, 4027
7412 13:40:34.307809 24 : 4255, 4029
7413 13:40:34.308144 28 : 4253, 4027
7414 13:40:34.311018 32 : 4252, 4027
7415 13:40:34.311441 36 : 4366, 4140
7416 13:40:34.314220 40 : 4252, 4027
7417 13:40:34.314641 44 : 4255, 4029
7418 13:40:34.317685 48 : 4252, 4027
7419 13:40:34.318107 52 : 4361, 4138
7420 13:40:34.320735 56 : 4250, 4027
7421 13:40:34.321219 60 : 4361, 4138
7422 13:40:34.321561 64 : 4250, 4027
7423 13:40:34.324289 68 : 4250, 4027
7424 13:40:34.324734 72 : 4250, 4026
7425 13:40:34.327632 76 : 4253, 4029
7426 13:40:34.328054 80 : 4361, 4138
7427 13:40:34.331095 84 : 4250, 4027
7428 13:40:34.331517 88 : 4361, 4137
7429 13:40:34.331850 92 : 4250, 4026
7430 13:40:34.334492 96 : 4250, 3360
7431 13:40:34.335115 100 : 4250, 0
7432 13:40:34.337609 104 : 4252, 0
7433 13:40:34.338110 108 : 4252, 0
7434 13:40:34.338453 112 : 4252, 0
7435 13:40:34.340829 116 : 4253, 0
7436 13:40:34.341375 120 : 4250, 0
7437 13:40:34.344527 124 : 4361, 0
7438 13:40:34.345027 128 : 4361, 0
7439 13:40:34.345387 132 : 4250, 0
7440 13:40:34.348124 136 : 4250, 0
7441 13:40:34.348604 140 : 4250, 0
7442 13:40:34.350977 144 : 4252, 0
7443 13:40:34.351449 148 : 4250, 0
7444 13:40:34.351871 152 : 4250, 0
7445 13:40:34.354228 156 : 4252, 0
7446 13:40:34.354731 160 : 4363, 0
7447 13:40:34.357527 164 : 4250, 0
7448 13:40:34.358034 168 : 4250, 0
7449 13:40:34.358380 172 : 4360, 0
7450 13:40:34.361395 176 : 4361, 0
7451 13:40:34.361816 180 : 4363, 0
7452 13:40:34.362150 184 : 4250, 0
7453 13:40:34.364319 188 : 4250, 0
7454 13:40:34.364989 192 : 4250, 0
7455 13:40:34.367397 196 : 4252, 0
7456 13:40:34.367849 200 : 4250, 0
7457 13:40:34.368840 204 : 4250, 0
7458 13:40:34.371021 208 : 4253, 0
7459 13:40:34.371441 212 : 4361, 44
7460 13:40:34.374044 216 : 4250, 3543
7461 13:40:34.374638 220 : 4361, 4137
7462 13:40:34.377899 224 : 4361, 4138
7463 13:40:34.378508 228 : 4247, 4024
7464 13:40:34.380822 232 : 4363, 4140
7465 13:40:34.381274 236 : 4361, 4138
7466 13:40:34.381613 240 : 4250, 4026
7467 13:40:34.384242 244 : 4250, 4027
7468 13:40:34.384743 248 : 4252, 4029
7469 13:40:34.387550 252 : 4250, 4027
7470 13:40:34.387970 256 : 4250, 4027
7471 13:40:34.390652 260 : 4250, 4027
7472 13:40:34.391073 264 : 4252, 4029
7473 13:40:34.394314 268 : 4249, 4027
7474 13:40:34.394737 272 : 4361, 4137
7475 13:40:34.397987 276 : 4361, 4138
7476 13:40:34.398470 280 : 4250, 4027
7477 13:40:34.400957 284 : 4363, 4140
7478 13:40:34.401422 288 : 4361, 4138
7479 13:40:34.404500 292 : 4250, 4027
7480 13:40:34.404922 296 : 4250, 4027
7481 13:40:34.405305 300 : 4252, 4029
7482 13:40:34.407855 304 : 4250, 4027
7483 13:40:34.408348 308 : 4250, 4027
7484 13:40:34.410715 312 : 4250, 4027
7485 13:40:34.411136 316 : 4252, 4029
7486 13:40:34.414149 320 : 4250, 4027
7487 13:40:34.414572 324 : 4360, 4138
7488 13:40:34.417974 328 : 4361, 4138
7489 13:40:34.418395 332 : 4248, 2885
7490 13:40:34.421033 336 : 4360, 41
7491 13:40:34.421457
7492 13:40:34.421784 MIOCK jitter meter ch=0
7493 13:40:34.422091
7494 13:40:34.424009 1T = (336-100) = 236 dly cells
7495 13:40:34.430870 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7496 13:40:34.431290 ==
7497 13:40:34.434194 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 13:40:34.437339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 13:40:34.437757 ==
7500 13:40:34.444530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 13:40:34.447573 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 13:40:34.451284 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 13:40:34.457703 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 13:40:34.467472 [CA 0] Center 44 (14~75) winsize 62
7505 13:40:34.470543 [CA 1] Center 44 (13~75) winsize 63
7506 13:40:34.473557 [CA 2] Center 40 (11~69) winsize 59
7507 13:40:34.477033 [CA 3] Center 39 (10~69) winsize 60
7508 13:40:34.480202 [CA 4] Center 38 (8~68) winsize 61
7509 13:40:34.483842 [CA 5] Center 37 (7~67) winsize 61
7510 13:40:34.484260
7511 13:40:34.487164 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 13:40:34.487581
7513 13:40:34.490503 [CATrainingPosCal] consider 1 rank data
7514 13:40:34.493617 u2DelayCellTimex100 = 275/100 ps
7515 13:40:34.497371 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7516 13:40:34.503923 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7517 13:40:34.507382 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7518 13:40:34.510696 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7519 13:40:34.513842 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7520 13:40:34.517326 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 13:40:34.517745
7522 13:40:34.520297 CA PerBit enable=1, Macro0, CA PI delay=37
7523 13:40:34.520713
7524 13:40:34.524246 [CBTSetCACLKResult] CA Dly = 37
7525 13:40:34.527215 CS Dly: 10 (0~41)
7526 13:40:34.530772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 13:40:34.533846 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 13:40:34.534243 ==
7529 13:40:34.536959 Dram Type= 6, Freq= 0, CH_0, rank 1
7530 13:40:34.540622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 13:40:34.544288 ==
7532 13:40:34.547087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 13:40:34.550292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 13:40:34.557294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 13:40:34.560727 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 13:40:34.571233 [CA 0] Center 44 (14~75) winsize 62
7537 13:40:34.574278 [CA 1] Center 44 (14~75) winsize 62
7538 13:40:34.577806 [CA 2] Center 40 (11~69) winsize 59
7539 13:40:34.581023 [CA 3] Center 39 (10~69) winsize 60
7540 13:40:34.584751 [CA 4] Center 38 (8~68) winsize 61
7541 13:40:34.587836 [CA 5] Center 37 (7~67) winsize 61
7542 13:40:34.588280
7543 13:40:34.590848 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 13:40:34.591315
7545 13:40:34.594472 [CATrainingPosCal] consider 2 rank data
7546 13:40:34.597828 u2DelayCellTimex100 = 275/100 ps
7547 13:40:34.601092 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7548 13:40:34.607505 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7549 13:40:34.611349 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7550 13:40:34.614296 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7551 13:40:34.618040 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7552 13:40:34.621079 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7553 13:40:34.621495
7554 13:40:34.624599 CA PerBit enable=1, Macro0, CA PI delay=37
7555 13:40:34.625115
7556 13:40:34.627453 [CBTSetCACLKResult] CA Dly = 37
7557 13:40:34.631077 CS Dly: 11 (0~44)
7558 13:40:34.634580 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 13:40:34.637643 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 13:40:34.638062
7561 13:40:34.641589 ----->DramcWriteLeveling(PI) begin...
7562 13:40:34.642031 ==
7563 13:40:34.644429 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 13:40:34.647546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 13:40:34.651311 ==
7566 13:40:34.651726 Write leveling (Byte 0): 32 => 32
7567 13:40:34.654333 Write leveling (Byte 1): 28 => 28
7568 13:40:34.657961 DramcWriteLeveling(PI) end<-----
7569 13:40:34.658377
7570 13:40:34.658704 ==
7571 13:40:34.661263 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 13:40:34.667864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 13:40:34.668278 ==
7574 13:40:34.668706 [Gating] SW mode calibration
7575 13:40:34.677629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7576 13:40:34.681259 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7577 13:40:34.687800 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 13:40:34.691636 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 13:40:34.694574 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 13:40:34.697633 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 13:40:34.704227 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7582 13:40:34.707923 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7583 13:40:34.711589 1 4 24 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
7584 13:40:34.718232 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 13:40:34.721519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 13:40:34.724432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 13:40:34.731306 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 13:40:34.734352 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7589 13:40:34.737550 1 5 16 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7590 13:40:34.744888 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7591 13:40:34.747621 1 5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7592 13:40:34.751416 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 13:40:34.757888 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 13:40:34.761444 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 13:40:34.764510 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 13:40:34.771179 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 13:40:34.774619 1 6 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7598 13:40:34.778275 1 6 20 | B1->B0 | 2525 4242 | 0 1 | (0 0) (0 0)
7599 13:40:34.781061 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7600 13:40:34.788016 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 13:40:34.791431 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 13:40:34.794735 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 13:40:34.801574 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 13:40:34.804644 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 13:40:34.808200 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 13:40:34.814753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7607 13:40:34.818429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7608 13:40:34.821469 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 13:40:34.827784 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 13:40:34.831565 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 13:40:34.834602 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 13:40:34.841459 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 13:40:34.844447 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 13:40:34.847869 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 13:40:34.854923 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 13:40:34.858046 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 13:40:34.861763 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 13:40:34.864851 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 13:40:34.871437 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 13:40:34.875164 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 13:40:34.878620 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 13:40:34.884578 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7623 13:40:34.888232 Total UI for P1: 0, mck2ui 16
7624 13:40:34.891871 best dqsien dly found for B0: ( 1, 9, 16)
7625 13:40:34.895067 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 13:40:34.898471 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 13:40:34.901626 Total UI for P1: 0, mck2ui 16
7628 13:40:34.904568 best dqsien dly found for B1: ( 1, 9, 22)
7629 13:40:34.908094 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7630 13:40:34.912018 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7631 13:40:34.912433
7632 13:40:34.918121 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7633 13:40:34.921758 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7634 13:40:34.924574 [Gating] SW calibration Done
7635 13:40:34.925134 ==
7636 13:40:34.927743 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 13:40:34.931186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 13:40:34.931624 ==
7639 13:40:34.931957 RX Vref Scan: 0
7640 13:40:34.932269
7641 13:40:34.935028 RX Vref 0 -> 0, step: 1
7642 13:40:34.935441
7643 13:40:34.938186 RX Delay 0 -> 252, step: 8
7644 13:40:34.941862 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7645 13:40:34.944868 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7646 13:40:34.947889 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7647 13:40:34.954577 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
7648 13:40:34.957877 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7649 13:40:34.961387 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7650 13:40:34.964823 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7651 13:40:34.968002 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7652 13:40:34.974655 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7653 13:40:34.978438 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7654 13:40:34.981349 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7655 13:40:34.984916 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7656 13:40:34.988000 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7657 13:40:34.994901 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7658 13:40:34.998537 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7659 13:40:35.001552 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7660 13:40:35.002180 ==
7661 13:40:35.004904 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 13:40:35.008062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 13:40:35.008515 ==
7664 13:40:35.011413 DQS Delay:
7665 13:40:35.011890 DQS0 = 0, DQS1 = 0
7666 13:40:35.014702 DQM Delay:
7667 13:40:35.015121 DQM0 = 132, DQM1 = 124
7668 13:40:35.015595 DQ Delay:
7669 13:40:35.018257 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7670 13:40:35.024481 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7671 13:40:35.028263 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7672 13:40:35.031016 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7673 13:40:35.031095
7674 13:40:35.031158
7675 13:40:35.031216 ==
7676 13:40:35.034454 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 13:40:35.037493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 13:40:35.037574 ==
7679 13:40:35.037670
7680 13:40:35.037729
7681 13:40:35.040911 TX Vref Scan disable
7682 13:40:35.044638 == TX Byte 0 ==
7683 13:40:35.047661 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7684 13:40:35.051341 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7685 13:40:35.054675 == TX Byte 1 ==
7686 13:40:35.057540 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7687 13:40:35.061388 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7688 13:40:35.061469 ==
7689 13:40:35.064263 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 13:40:35.068098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 13:40:35.068180 ==
7692 13:40:35.082527
7693 13:40:35.085342 TX Vref early break, caculate TX vref
7694 13:40:35.089102 TX Vref=16, minBit 1, minWin=21, winSum=356
7695 13:40:35.092074 TX Vref=18, minBit 4, minWin=21, winSum=367
7696 13:40:35.095708 TX Vref=20, minBit 7, minWin=21, winSum=378
7697 13:40:35.098883 TX Vref=22, minBit 1, minWin=22, winSum=385
7698 13:40:35.102592 TX Vref=24, minBit 1, minWin=23, winSum=394
7699 13:40:35.109193 TX Vref=26, minBit 4, minWin=23, winSum=410
7700 13:40:35.112293 TX Vref=28, minBit 4, minWin=24, winSum=418
7701 13:40:35.115483 TX Vref=30, minBit 4, minWin=24, winSum=414
7702 13:40:35.119170 TX Vref=32, minBit 4, minWin=24, winSum=413
7703 13:40:35.122239 TX Vref=34, minBit 4, minWin=23, winSum=396
7704 13:40:35.129340 [TxChooseVref] Worse bit 4, Min win 24, Win sum 418, Final Vref 28
7705 13:40:35.129423
7706 13:40:35.132405 Final TX Range 0 Vref 28
7707 13:40:35.132486
7708 13:40:35.132550 ==
7709 13:40:35.135891 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 13:40:35.139022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 13:40:35.139104 ==
7712 13:40:35.139168
7713 13:40:35.139227
7714 13:40:35.142626 TX Vref Scan disable
7715 13:40:35.149192 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7716 13:40:35.149275 == TX Byte 0 ==
7717 13:40:35.152592 u2DelayCellOfst[0]=17 cells (5 PI)
7718 13:40:35.155668 u2DelayCellOfst[1]=21 cells (6 PI)
7719 13:40:35.159524 u2DelayCellOfst[2]=14 cells (4 PI)
7720 13:40:35.162331 u2DelayCellOfst[3]=17 cells (5 PI)
7721 13:40:35.165967 u2DelayCellOfst[4]=10 cells (3 PI)
7722 13:40:35.169242 u2DelayCellOfst[5]=0 cells (0 PI)
7723 13:40:35.169323 u2DelayCellOfst[6]=21 cells (6 PI)
7724 13:40:35.172211 u2DelayCellOfst[7]=21 cells (6 PI)
7725 13:40:35.179283 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7726 13:40:35.182779 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7727 13:40:35.182860 == TX Byte 1 ==
7728 13:40:35.185768 u2DelayCellOfst[8]=0 cells (0 PI)
7729 13:40:35.189130 u2DelayCellOfst[9]=0 cells (0 PI)
7730 13:40:35.192329 u2DelayCellOfst[10]=10 cells (3 PI)
7731 13:40:35.195998 u2DelayCellOfst[11]=0 cells (0 PI)
7732 13:40:35.199054 u2DelayCellOfst[12]=14 cells (4 PI)
7733 13:40:35.202763 u2DelayCellOfst[13]=10 cells (3 PI)
7734 13:40:35.205742 u2DelayCellOfst[14]=14 cells (4 PI)
7735 13:40:35.209090 u2DelayCellOfst[15]=10 cells (3 PI)
7736 13:40:35.212696 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7737 13:40:35.216262 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7738 13:40:35.219355 DramC Write-DBI on
7739 13:40:35.219435 ==
7740 13:40:35.222516 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 13:40:35.226080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 13:40:35.226161 ==
7743 13:40:35.226224
7744 13:40:35.226283
7745 13:40:35.229631 TX Vref Scan disable
7746 13:40:35.232639 == TX Byte 0 ==
7747 13:40:35.235707 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7748 13:40:35.239496 == TX Byte 1 ==
7749 13:40:35.242345 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7750 13:40:35.242427 DramC Write-DBI off
7751 13:40:35.242491
7752 13:40:35.245668 [DATLAT]
7753 13:40:35.245749 Freq=1600, CH0 RK0
7754 13:40:35.245816
7755 13:40:35.249577 DATLAT Default: 0xf
7756 13:40:35.249659 0, 0xFFFF, sum = 0
7757 13:40:35.252622 1, 0xFFFF, sum = 0
7758 13:40:35.252715 2, 0xFFFF, sum = 0
7759 13:40:35.255846 3, 0xFFFF, sum = 0
7760 13:40:35.255928 4, 0xFFFF, sum = 0
7761 13:40:35.259367 5, 0xFFFF, sum = 0
7762 13:40:35.259449 6, 0xFFFF, sum = 0
7763 13:40:35.262560 7, 0xFFFF, sum = 0
7764 13:40:35.262642 8, 0xFFFF, sum = 0
7765 13:40:35.265709 9, 0xFFFF, sum = 0
7766 13:40:35.265804 10, 0xFFFF, sum = 0
7767 13:40:35.269262 11, 0xFFFF, sum = 0
7768 13:40:35.272231 12, 0xFFFF, sum = 0
7769 13:40:35.272313 13, 0xFFFF, sum = 0
7770 13:40:35.275854 14, 0x0, sum = 1
7771 13:40:35.275935 15, 0x0, sum = 2
7772 13:40:35.276000 16, 0x0, sum = 3
7773 13:40:35.279108 17, 0x0, sum = 4
7774 13:40:35.279190 best_step = 15
7775 13:40:35.279254
7776 13:40:35.282329 ==
7777 13:40:35.282411 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 13:40:35.289297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 13:40:35.289380 ==
7780 13:40:35.289444 RX Vref Scan: 1
7781 13:40:35.289504
7782 13:40:35.292450 Set Vref Range= 24 -> 127
7783 13:40:35.292530
7784 13:40:35.295913 RX Vref 24 -> 127, step: 1
7785 13:40:35.295994
7786 13:40:35.299191 RX Delay 11 -> 252, step: 4
7787 13:40:35.299272
7788 13:40:35.302302 Set Vref, RX VrefLevel [Byte0]: 24
7789 13:40:35.305914 [Byte1]: 24
7790 13:40:35.305990
7791 13:40:35.308961 Set Vref, RX VrefLevel [Byte0]: 25
7792 13:40:35.312664 [Byte1]: 25
7793 13:40:35.312735
7794 13:40:35.315680 Set Vref, RX VrefLevel [Byte0]: 26
7795 13:40:35.318708 [Byte1]: 26
7796 13:40:35.322543
7797 13:40:35.322639 Set Vref, RX VrefLevel [Byte0]: 27
7798 13:40:35.325432 [Byte1]: 27
7799 13:40:35.329626
7800 13:40:35.329702 Set Vref, RX VrefLevel [Byte0]: 28
7801 13:40:35.333272 [Byte1]: 28
7802 13:40:35.337660
7803 13:40:35.337731 Set Vref, RX VrefLevel [Byte0]: 29
7804 13:40:35.340703 [Byte1]: 29
7805 13:40:35.345162
7806 13:40:35.345234 Set Vref, RX VrefLevel [Byte0]: 30
7807 13:40:35.348542 [Byte1]: 30
7808 13:40:35.352531
7809 13:40:35.352608 Set Vref, RX VrefLevel [Byte0]: 31
7810 13:40:35.356234 [Byte1]: 31
7811 13:40:35.360243
7812 13:40:35.360319 Set Vref, RX VrefLevel [Byte0]: 32
7813 13:40:35.363656 [Byte1]: 32
7814 13:40:35.368313
7815 13:40:35.368391 Set Vref, RX VrefLevel [Byte0]: 33
7816 13:40:35.371342 [Byte1]: 33
7817 13:40:35.375448
7818 13:40:35.375520 Set Vref, RX VrefLevel [Byte0]: 34
7819 13:40:35.379250 [Byte1]: 34
7820 13:40:35.382995
7821 13:40:35.383068 Set Vref, RX VrefLevel [Byte0]: 35
7822 13:40:35.386521 [Byte1]: 35
7823 13:40:35.390749
7824 13:40:35.390818 Set Vref, RX VrefLevel [Byte0]: 36
7825 13:40:35.394293 [Byte1]: 36
7826 13:40:35.398580
7827 13:40:35.398655 Set Vref, RX VrefLevel [Byte0]: 37
7828 13:40:35.401868 [Byte1]: 37
7829 13:40:35.406343
7830 13:40:35.406419 Set Vref, RX VrefLevel [Byte0]: 38
7831 13:40:35.409589 [Byte1]: 38
7832 13:40:35.413770
7833 13:40:35.413849 Set Vref, RX VrefLevel [Byte0]: 39
7834 13:40:35.416791 [Byte1]: 39
7835 13:40:35.421683
7836 13:40:35.422141 Set Vref, RX VrefLevel [Byte0]: 40
7837 13:40:35.425121 [Byte1]: 40
7838 13:40:35.429390
7839 13:40:35.429886 Set Vref, RX VrefLevel [Byte0]: 41
7840 13:40:35.432381 [Byte1]: 41
7841 13:40:35.436722
7842 13:40:35.437198 Set Vref, RX VrefLevel [Byte0]: 42
7843 13:40:35.439835 [Byte1]: 42
7844 13:40:35.444813
7845 13:40:35.445276 Set Vref, RX VrefLevel [Byte0]: 43
7846 13:40:35.447843 [Byte1]: 43
7847 13:40:35.452270
7848 13:40:35.452689 Set Vref, RX VrefLevel [Byte0]: 44
7849 13:40:35.455150 [Byte1]: 44
7850 13:40:35.459957
7851 13:40:35.460375 Set Vref, RX VrefLevel [Byte0]: 45
7852 13:40:35.463156 [Byte1]: 45
7853 13:40:35.467296
7854 13:40:35.467711 Set Vref, RX VrefLevel [Byte0]: 46
7855 13:40:35.470892 [Byte1]: 46
7856 13:40:35.475111
7857 13:40:35.475525 Set Vref, RX VrefLevel [Byte0]: 47
7858 13:40:35.478280 [Byte1]: 47
7859 13:40:35.482414
7860 13:40:35.482830 Set Vref, RX VrefLevel [Byte0]: 48
7861 13:40:35.485986 [Byte1]: 48
7862 13:40:35.490435
7863 13:40:35.491136 Set Vref, RX VrefLevel [Byte0]: 49
7864 13:40:35.493713 [Byte1]: 49
7865 13:40:35.498039
7866 13:40:35.498456 Set Vref, RX VrefLevel [Byte0]: 50
7867 13:40:35.501181 [Byte1]: 50
7868 13:40:35.505560
7869 13:40:35.505971 Set Vref, RX VrefLevel [Byte0]: 51
7870 13:40:35.508773 [Byte1]: 51
7871 13:40:35.512823
7872 13:40:35.513304 Set Vref, RX VrefLevel [Byte0]: 52
7873 13:40:35.516202 [Byte1]: 52
7874 13:40:35.520864
7875 13:40:35.521361 Set Vref, RX VrefLevel [Byte0]: 53
7876 13:40:35.523908 [Byte1]: 53
7877 13:40:35.528571
7878 13:40:35.529013 Set Vref, RX VrefLevel [Byte0]: 54
7879 13:40:35.531439 [Byte1]: 54
7880 13:40:35.535773
7881 13:40:35.536184 Set Vref, RX VrefLevel [Byte0]: 55
7882 13:40:35.538818 [Byte1]: 55
7883 13:40:35.543791
7884 13:40:35.544345 Set Vref, RX VrefLevel [Byte0]: 56
7885 13:40:35.546869 [Byte1]: 56
7886 13:40:35.551127
7887 13:40:35.551540 Set Vref, RX VrefLevel [Byte0]: 57
7888 13:40:35.554265 [Byte1]: 57
7889 13:40:35.558482
7890 13:40:35.558889 Set Vref, RX VrefLevel [Byte0]: 58
7891 13:40:35.561884 [Byte1]: 58
7892 13:40:35.566145
7893 13:40:35.566553 Set Vref, RX VrefLevel [Byte0]: 59
7894 13:40:35.569754 [Byte1]: 59
7895 13:40:35.574112
7896 13:40:35.574540 Set Vref, RX VrefLevel [Byte0]: 60
7897 13:40:35.577102 [Byte1]: 60
7898 13:40:35.581362
7899 13:40:35.581779 Set Vref, RX VrefLevel [Byte0]: 61
7900 13:40:35.584911 [Byte1]: 61
7901 13:40:35.589583
7902 13:40:35.590076 Set Vref, RX VrefLevel [Byte0]: 62
7903 13:40:35.592137 [Byte1]: 62
7904 13:40:35.596854
7905 13:40:35.597331 Set Vref, RX VrefLevel [Byte0]: 63
7906 13:40:35.599913 [Byte1]: 63
7907 13:40:35.604388
7908 13:40:35.604951 Set Vref, RX VrefLevel [Byte0]: 64
7909 13:40:35.607378 [Byte1]: 64
7910 13:40:35.612130
7911 13:40:35.612626 Set Vref, RX VrefLevel [Byte0]: 65
7912 13:40:35.615314 [Byte1]: 65
7913 13:40:35.619537
7914 13:40:35.620010 Set Vref, RX VrefLevel [Byte0]: 66
7915 13:40:35.623051 [Byte1]: 66
7916 13:40:35.627077
7917 13:40:35.627602 Set Vref, RX VrefLevel [Byte0]: 67
7918 13:40:35.630588 [Byte1]: 67
7919 13:40:35.634690
7920 13:40:35.635106 Set Vref, RX VrefLevel [Byte0]: 68
7921 13:40:35.638637 [Byte1]: 68
7922 13:40:35.642879
7923 13:40:35.643291 Set Vref, RX VrefLevel [Byte0]: 69
7924 13:40:35.645931 [Byte1]: 69
7925 13:40:35.649928
7926 13:40:35.650343 Set Vref, RX VrefLevel [Byte0]: 70
7927 13:40:35.653533 [Byte1]: 70
7928 13:40:35.657856
7929 13:40:35.658269 Set Vref, RX VrefLevel [Byte0]: 71
7930 13:40:35.660866 [Byte1]: 71
7931 13:40:35.665053
7932 13:40:35.665469 Set Vref, RX VrefLevel [Byte0]: 72
7933 13:40:35.668804 [Byte1]: 72
7934 13:40:35.673089
7935 13:40:35.673502 Set Vref, RX VrefLevel [Byte0]: 73
7936 13:40:35.676208 [Byte1]: 73
7937 13:40:35.680601
7938 13:40:35.681115 Set Vref, RX VrefLevel [Byte0]: 74
7939 13:40:35.683944 [Byte1]: 74
7940 13:40:35.687894
7941 13:40:35.688392 Set Vref, RX VrefLevel [Byte0]: 75
7942 13:40:35.691633 [Byte1]: 75
7943 13:40:35.696052
7944 13:40:35.696468 Set Vref, RX VrefLevel [Byte0]: 76
7945 13:40:35.699464 [Byte1]: 76
7946 13:40:35.703382
7947 13:40:35.703856 Final RX Vref Byte 0 = 56 to rank0
7948 13:40:35.706622 Final RX Vref Byte 1 = 62 to rank0
7949 13:40:35.710022 Final RX Vref Byte 0 = 56 to rank1
7950 13:40:35.713173 Final RX Vref Byte 1 = 62 to rank1==
7951 13:40:35.716783 Dram Type= 6, Freq= 0, CH_0, rank 0
7952 13:40:35.723311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 13:40:35.723870 ==
7954 13:40:35.724204 DQS Delay:
7955 13:40:35.724576 DQS0 = 0, DQS1 = 0
7956 13:40:35.726643 DQM Delay:
7957 13:40:35.727052 DQM0 = 129, DQM1 = 122
7958 13:40:35.729718 DQ Delay:
7959 13:40:35.733293 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7960 13:40:35.736689 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7961 13:40:35.739774 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7962 13:40:35.743270 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =134
7963 13:40:35.743706
7964 13:40:35.744035
7965 13:40:35.744340
7966 13:40:35.746335 [DramC_TX_OE_Calibration] TA2
7967 13:40:35.749878 Original DQ_B0 (3 6) =30, OEN = 27
7968 13:40:35.753010 Original DQ_B1 (3 6) =30, OEN = 27
7969 13:40:35.756740 24, 0x0, End_B0=24 End_B1=24
7970 13:40:35.757341 25, 0x0, End_B0=25 End_B1=25
7971 13:40:35.759944 26, 0x0, End_B0=26 End_B1=26
7972 13:40:35.763715 27, 0x0, End_B0=27 End_B1=27
7973 13:40:35.766554 28, 0x0, End_B0=28 End_B1=28
7974 13:40:35.767223 29, 0x0, End_B0=29 End_B1=29
7975 13:40:35.769958 30, 0x0, End_B0=30 End_B1=30
7976 13:40:35.773048 31, 0x4141, End_B0=30 End_B1=30
7977 13:40:35.776875 Byte0 end_step=30 best_step=27
7978 13:40:35.780081 Byte1 end_step=30 best_step=27
7979 13:40:35.783251 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 13:40:35.783668 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 13:40:35.783999
7982 13:40:35.786845
7983 13:40:35.793746 [DQSOSCAuto] RK0, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
7984 13:40:35.796941 CH0 RK0: MR19=303, MR18=170B
7985 13:40:35.803121 CH0_RK0: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
7986 13:40:35.803540
7987 13:40:35.807091 ----->DramcWriteLeveling(PI) begin...
7988 13:40:35.807510 ==
7989 13:40:35.809902 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 13:40:35.813437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 13:40:35.813870 ==
7992 13:40:35.817179 Write leveling (Byte 0): 33 => 33
7993 13:40:35.820404 Write leveling (Byte 1): 27 => 27
7994 13:40:35.823717 DramcWriteLeveling(PI) end<-----
7995 13:40:35.824413
7996 13:40:35.824927 ==
7997 13:40:35.826779 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 13:40:35.830471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 13:40:35.830892 ==
8000 13:40:35.833539 [Gating] SW mode calibration
8001 13:40:35.840581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8002 13:40:35.846926 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8003 13:40:35.850259 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 13:40:35.853418 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 13:40:35.857193 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 13:40:35.864106 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8007 13:40:35.867126 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8008 13:40:35.870142 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8009 13:40:35.876881 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 13:40:35.880584 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 13:40:35.883604 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 13:40:35.890569 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 13:40:35.893718 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8014 13:40:35.897240 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8015 13:40:35.903632 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8016 13:40:35.907111 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
8017 13:40:35.910165 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 13:40:35.916937 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 13:40:35.920579 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 13:40:35.923872 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 13:40:35.930265 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8022 13:40:35.933912 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 13:40:35.937535 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8024 13:40:35.940659 1 6 20 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8025 13:40:35.947452 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 13:40:35.950305 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 13:40:35.953879 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 13:40:35.960363 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 13:40:35.963986 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 13:40:35.967020 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8031 13:40:35.973835 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8032 13:40:35.977381 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 13:40:35.980346 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 13:40:35.987128 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 13:40:35.990333 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 13:40:35.993857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 13:40:36.000726 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 13:40:36.004277 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 13:40:36.007301 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 13:40:36.013991 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 13:40:36.017128 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 13:40:36.020958 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 13:40:36.023964 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 13:40:36.030877 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 13:40:36.034329 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 13:40:36.037245 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8047 13:40:36.040591 Total UI for P1: 0, mck2ui 16
8048 13:40:36.044108 best dqsien dly found for B0: ( 1, 9, 8)
8049 13:40:36.050596 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 13:40:36.053999 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 13:40:36.057208 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 13:40:36.060772 Total UI for P1: 0, mck2ui 16
8053 13:40:36.063825 best dqsien dly found for B1: ( 1, 9, 18)
8054 13:40:36.067373 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8055 13:40:36.070448 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8056 13:40:36.070872
8057 13:40:36.077421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8058 13:40:36.080330 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8059 13:40:36.083930 [Gating] SW calibration Done
8060 13:40:36.084374 ==
8061 13:40:36.087478 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 13:40:36.090766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 13:40:36.091257 ==
8064 13:40:36.091619 RX Vref Scan: 0
8065 13:40:36.091923
8066 13:40:36.093837 RX Vref 0 -> 0, step: 1
8067 13:40:36.094277
8068 13:40:36.096963 RX Delay 0 -> 252, step: 8
8069 13:40:36.100521 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8070 13:40:36.103986 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8071 13:40:36.107162 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8072 13:40:36.113737 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8073 13:40:36.117248 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8074 13:40:36.120473 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8075 13:40:36.123742 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 13:40:36.127434 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 13:40:36.134155 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8078 13:40:36.137037 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8079 13:40:36.140627 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 13:40:36.143728 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8081 13:40:36.146854 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8082 13:40:36.153996 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8083 13:40:36.156919 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8084 13:40:36.160371 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8085 13:40:36.161013 ==
8086 13:40:36.163767 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 13:40:36.166892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 13:40:36.170169 ==
8089 13:40:36.170250 DQS Delay:
8090 13:40:36.170314 DQS0 = 0, DQS1 = 0
8091 13:40:36.172992 DQM Delay:
8092 13:40:36.173079 DQM0 = 130, DQM1 = 126
8093 13:40:36.176596 DQ Delay:
8094 13:40:36.179791 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8095 13:40:36.183054 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8096 13:40:36.186558 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8097 13:40:36.189760 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
8098 13:40:36.189842
8099 13:40:36.189905
8100 13:40:36.189965 ==
8101 13:40:36.193358 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 13:40:36.196486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 13:40:36.196561 ==
8104 13:40:36.196624
8105 13:40:36.196682
8106 13:40:36.199761 TX Vref Scan disable
8107 13:40:36.203422 == TX Byte 0 ==
8108 13:40:36.206560 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8109 13:40:36.210386 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8110 13:40:36.213461 == TX Byte 1 ==
8111 13:40:36.216598 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 13:40:36.220287 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8113 13:40:36.220366 ==
8114 13:40:36.223257 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 13:40:36.227071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 13:40:36.230102 ==
8117 13:40:36.242766
8118 13:40:36.246476 TX Vref early break, caculate TX vref
8119 13:40:36.249484 TX Vref=16, minBit 4, minWin=22, winSum=366
8120 13:40:36.252852 TX Vref=18, minBit 1, minWin=23, winSum=380
8121 13:40:36.256356 TX Vref=20, minBit 1, minWin=23, winSum=386
8122 13:40:36.259519 TX Vref=22, minBit 1, minWin=24, winSum=395
8123 13:40:36.263268 TX Vref=24, minBit 1, minWin=24, winSum=404
8124 13:40:36.266233 TX Vref=26, minBit 4, minWin=24, winSum=410
8125 13:40:36.273299 TX Vref=28, minBit 0, minWin=25, winSum=417
8126 13:40:36.276268 TX Vref=30, minBit 0, minWin=25, winSum=415
8127 13:40:36.279827 TX Vref=32, minBit 0, minWin=25, winSum=412
8128 13:40:36.283532 TX Vref=34, minBit 0, minWin=24, winSum=401
8129 13:40:36.286708 TX Vref=36, minBit 0, minWin=23, winSum=392
8130 13:40:36.293098 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8131 13:40:36.293260
8132 13:40:36.296817 Final TX Range 0 Vref 28
8133 13:40:36.296930
8134 13:40:36.297033 ==
8135 13:40:36.299874 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 13:40:36.303664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 13:40:36.303808 ==
8138 13:40:36.303915
8139 13:40:36.304016
8140 13:40:36.306601 TX Vref Scan disable
8141 13:40:36.313371 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8142 13:40:36.313552 == TX Byte 0 ==
8143 13:40:36.316612 u2DelayCellOfst[0]=14 cells (4 PI)
8144 13:40:36.320380 u2DelayCellOfst[1]=17 cells (5 PI)
8145 13:40:36.323429 u2DelayCellOfst[2]=10 cells (3 PI)
8146 13:40:36.326249 u2DelayCellOfst[3]=10 cells (3 PI)
8147 13:40:36.330021 u2DelayCellOfst[4]=7 cells (2 PI)
8148 13:40:36.333534 u2DelayCellOfst[5]=0 cells (0 PI)
8149 13:40:36.336686 u2DelayCellOfst[6]=17 cells (5 PI)
8150 13:40:36.340169 u2DelayCellOfst[7]=17 cells (5 PI)
8151 13:40:36.343270 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8152 13:40:36.346936 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8153 13:40:36.350002 == TX Byte 1 ==
8154 13:40:36.350631 u2DelayCellOfst[8]=0 cells (0 PI)
8155 13:40:36.353816 u2DelayCellOfst[9]=0 cells (0 PI)
8156 13:40:36.356899 u2DelayCellOfst[10]=7 cells (2 PI)
8157 13:40:36.360270 u2DelayCellOfst[11]=0 cells (0 PI)
8158 13:40:36.363893 u2DelayCellOfst[12]=14 cells (4 PI)
8159 13:40:36.366944 u2DelayCellOfst[13]=10 cells (3 PI)
8160 13:40:36.370632 u2DelayCellOfst[14]=14 cells (4 PI)
8161 13:40:36.373541 u2DelayCellOfst[15]=10 cells (3 PI)
8162 13:40:36.376913 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8163 13:40:36.383709 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8164 13:40:36.384137 DramC Write-DBI on
8165 13:40:36.384469 ==
8166 13:40:36.386905 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 13:40:36.390399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 13:40:36.390952 ==
8169 13:40:36.391446
8170 13:40:36.393529
8171 13:40:36.393968 TX Vref Scan disable
8172 13:40:36.396801 == TX Byte 0 ==
8173 13:40:36.400498 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8174 13:40:36.404045 == TX Byte 1 ==
8175 13:40:36.407332 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8176 13:40:36.407743 DramC Write-DBI off
8177 13:40:36.408097
8178 13:40:36.410491 [DATLAT]
8179 13:40:36.410945 Freq=1600, CH0 RK1
8180 13:40:36.411307
8181 13:40:36.413507 DATLAT Default: 0xf
8182 13:40:36.413953 0, 0xFFFF, sum = 0
8183 13:40:36.417411 1, 0xFFFF, sum = 0
8184 13:40:36.417975 2, 0xFFFF, sum = 0
8185 13:40:36.420345 3, 0xFFFF, sum = 0
8186 13:40:36.420817 4, 0xFFFF, sum = 0
8187 13:40:36.423728 5, 0xFFFF, sum = 0
8188 13:40:36.424325 6, 0xFFFF, sum = 0
8189 13:40:36.427444 7, 0xFFFF, sum = 0
8190 13:40:36.428041 8, 0xFFFF, sum = 0
8191 13:40:36.430399 9, 0xFFFF, sum = 0
8192 13:40:36.430834 10, 0xFFFF, sum = 0
8193 13:40:36.434019 11, 0xFFFF, sum = 0
8194 13:40:36.437247 12, 0xFFFF, sum = 0
8195 13:40:36.437737 13, 0xFFFF, sum = 0
8196 13:40:36.440587 14, 0x0, sum = 1
8197 13:40:36.441029 15, 0x0, sum = 2
8198 13:40:36.443882 16, 0x0, sum = 3
8199 13:40:36.444296 17, 0x0, sum = 4
8200 13:40:36.444654 best_step = 15
8201 13:40:36.444960
8202 13:40:36.446925 ==
8203 13:40:36.450118 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 13:40:36.453857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 13:40:36.454300 ==
8206 13:40:36.454721 RX Vref Scan: 0
8207 13:40:36.455065
8208 13:40:36.457542 RX Vref 0 -> 0, step: 1
8209 13:40:36.458072
8210 13:40:36.461374 RX Delay 11 -> 252, step: 4
8211 13:40:36.463773 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8212 13:40:36.467425 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8213 13:40:36.474132 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8214 13:40:36.477383 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8215 13:40:36.480667 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8216 13:40:36.484190 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8217 13:40:36.486853 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8218 13:40:36.493956 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8219 13:40:36.497580 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8220 13:40:36.500778 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8221 13:40:36.503733 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8222 13:40:36.507432 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8223 13:40:36.514049 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8224 13:40:36.517469 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8225 13:40:36.520432 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8226 13:40:36.524389 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8227 13:40:36.525053 ==
8228 13:40:36.527325 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 13:40:36.530587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 13:40:36.534462 ==
8231 13:40:36.534953 DQS Delay:
8232 13:40:36.535316 DQS0 = 0, DQS1 = 0
8233 13:40:36.537655 DQM Delay:
8234 13:40:36.538061 DQM0 = 126, DQM1 = 122
8235 13:40:36.540675 DQ Delay:
8236 13:40:36.543917 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8237 13:40:36.547746 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =134
8238 13:40:36.551083 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8239 13:40:36.554136 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8240 13:40:36.554863
8241 13:40:36.555202
8242 13:40:36.555536
8243 13:40:36.557376 [DramC_TX_OE_Calibration] TA2
8244 13:40:36.560483 Original DQ_B0 (3 6) =30, OEN = 27
8245 13:40:36.564135 Original DQ_B1 (3 6) =30, OEN = 27
8246 13:40:36.564651 24, 0x0, End_B0=24 End_B1=24
8247 13:40:36.567249 25, 0x0, End_B0=25 End_B1=25
8248 13:40:36.570485 26, 0x0, End_B0=26 End_B1=26
8249 13:40:36.574221 27, 0x0, End_B0=27 End_B1=27
8250 13:40:36.577324 28, 0x0, End_B0=28 End_B1=28
8251 13:40:36.577758 29, 0x0, End_B0=29 End_B1=29
8252 13:40:36.580576 30, 0x0, End_B0=30 End_B1=30
8253 13:40:36.583979 31, 0x4141, End_B0=30 End_B1=30
8254 13:40:36.587196 Byte0 end_step=30 best_step=27
8255 13:40:36.590913 Byte1 end_step=30 best_step=27
8256 13:40:36.593750 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 13:40:36.594182 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 13:40:36.594511
8259 13:40:36.594818
8260 13:40:36.603934 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8261 13:40:36.607270 CH0 RK1: MR19=303, MR18=150A
8262 13:40:36.614265 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8263 13:40:36.614598 [RxdqsGatingPostProcess] freq 1600
8264 13:40:36.620731 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 13:40:36.623565 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 13:40:36.627257 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 13:40:36.630012 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 13:40:36.633796 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 13:40:36.637042 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 13:40:36.640305 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 13:40:36.643383 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 13:40:36.643499 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 13:40:36.646996 Pre-setting of DQS Precalculation
8274 13:40:36.653290 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 13:40:36.653437 ==
8276 13:40:36.657121 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 13:40:36.660363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 13:40:36.660507 ==
8279 13:40:36.667010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 13:40:36.670265 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 13:40:36.673641 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 13:40:36.680082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 13:40:36.689476 [CA 0] Center 43 (15~72) winsize 58
8284 13:40:36.693194 [CA 1] Center 43 (14~72) winsize 59
8285 13:40:36.696331 [CA 2] Center 38 (10~67) winsize 58
8286 13:40:36.699443 [CA 3] Center 36 (7~66) winsize 60
8287 13:40:36.703153 [CA 4] Center 38 (8~68) winsize 61
8288 13:40:36.706328 [CA 5] Center 37 (8~66) winsize 59
8289 13:40:36.706437
8290 13:40:36.709902 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 13:40:36.710023
8292 13:40:36.712744 [CATrainingPosCal] consider 1 rank data
8293 13:40:36.716540 u2DelayCellTimex100 = 275/100 ps
8294 13:40:36.719824 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8295 13:40:36.726490 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8296 13:40:36.729350 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8297 13:40:36.732839 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8298 13:40:36.736200 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8299 13:40:36.739604 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8300 13:40:36.739841
8301 13:40:36.742897 CA PerBit enable=1, Macro0, CA PI delay=36
8302 13:40:36.743190
8303 13:40:36.746202 [CBTSetCACLKResult] CA Dly = 36
8304 13:40:36.746492 CS Dly: 8 (0~39)
8305 13:40:36.753040 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 13:40:36.756601 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 13:40:36.757053 ==
8308 13:40:36.759834 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 13:40:36.763258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 13:40:36.763666 ==
8311 13:40:36.770061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 13:40:36.773065 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 13:40:36.780014 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 13:40:36.783103 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 13:40:36.793017 [CA 0] Center 42 (13~72) winsize 60
8316 13:40:36.796736 [CA 1] Center 42 (14~71) winsize 58
8317 13:40:36.799596 [CA 2] Center 37 (8~66) winsize 59
8318 13:40:36.803018 [CA 3] Center 36 (7~66) winsize 60
8319 13:40:36.806177 [CA 4] Center 37 (8~67) winsize 60
8320 13:40:36.809567 [CA 5] Center 36 (6~66) winsize 61
8321 13:40:36.810051
8322 13:40:36.813140 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8323 13:40:36.813567
8324 13:40:36.816281 [CATrainingPosCal] consider 2 rank data
8325 13:40:36.819456 u2DelayCellTimex100 = 275/100 ps
8326 13:40:36.823294 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8327 13:40:36.829791 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8328 13:40:36.832736 CA2 delay=38 (10~66),Diff = 2 PI (7 cell)
8329 13:40:36.836337 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 13:40:36.839978 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8331 13:40:36.842883 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8332 13:40:36.843507
8333 13:40:36.846531 CA PerBit enable=1, Macro0, CA PI delay=36
8334 13:40:36.846971
8335 13:40:36.849974 [CBTSetCACLKResult] CA Dly = 36
8336 13:40:36.853368 CS Dly: 10 (0~44)
8337 13:40:36.856318 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 13:40:36.859565 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 13:40:36.860028
8340 13:40:36.863527 ----->DramcWriteLeveling(PI) begin...
8341 13:40:36.864099 ==
8342 13:40:36.866244 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 13:40:36.869898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 13:40:36.873145 ==
8345 13:40:36.873687 Write leveling (Byte 0): 25 => 25
8346 13:40:36.876402 Write leveling (Byte 1): 29 => 29
8347 13:40:36.879650 DramcWriteLeveling(PI) end<-----
8348 13:40:36.880063
8349 13:40:36.880385 ==
8350 13:40:36.883407 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 13:40:36.889440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 13:40:36.889952 ==
8353 13:40:36.890300 [Gating] SW mode calibration
8354 13:40:36.900084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 13:40:36.903230 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 13:40:36.906726 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 13:40:36.913206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 13:40:36.917126 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 13:40:36.920057 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 13:40:36.926724 1 4 16 | B1->B0 | 3131 2a2a | 1 1 | (1 1) (1 1)
8361 13:40:36.930071 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 13:40:36.933616 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 13:40:36.940192 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 13:40:36.943126 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 13:40:36.946682 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 13:40:36.953467 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 13:40:36.956786 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 13:40:36.959830 1 5 16 | B1->B0 | 2f2f 3333 | 0 1 | (1 0) (1 0)
8369 13:40:36.966594 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8370 13:40:36.970330 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 13:40:36.973110 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 13:40:36.976816 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 13:40:36.983752 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 13:40:36.987020 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 13:40:36.989986 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 13:40:36.996558 1 6 16 | B1->B0 | 3e3e 2e2e | 0 0 | (0 0) (0 0)
8377 13:40:37.000264 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 13:40:37.003506 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 13:40:37.010198 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 13:40:37.013709 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 13:40:37.016627 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 13:40:37.023533 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 13:40:37.026754 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 13:40:37.030340 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 13:40:37.037190 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8386 13:40:37.040216 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 13:40:37.043537 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 13:40:37.046724 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 13:40:37.053440 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 13:40:37.056738 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 13:40:37.059751 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 13:40:37.066579 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 13:40:37.069794 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 13:40:37.073417 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 13:40:37.079843 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 13:40:37.082944 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 13:40:37.086634 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 13:40:37.092873 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 13:40:37.096578 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 13:40:37.099757 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 13:40:37.106241 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 13:40:37.106378 Total UI for P1: 0, mck2ui 16
8403 13:40:37.113070 best dqsien dly found for B0: ( 1, 9, 14)
8404 13:40:37.113187 Total UI for P1: 0, mck2ui 16
8405 13:40:37.119772 best dqsien dly found for B1: ( 1, 9, 14)
8406 13:40:37.123338 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8407 13:40:37.126636 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8408 13:40:37.126710
8409 13:40:37.130057 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8410 13:40:37.133129 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8411 13:40:37.136441 [Gating] SW calibration Done
8412 13:40:37.136512 ==
8413 13:40:37.140207 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 13:40:37.143266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 13:40:37.143346 ==
8416 13:40:37.146726 RX Vref Scan: 0
8417 13:40:37.146805
8418 13:40:37.146869 RX Vref 0 -> 0, step: 1
8419 13:40:37.146927
8420 13:40:37.149475 RX Delay 0 -> 252, step: 8
8421 13:40:37.153319 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8422 13:40:37.159630 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8423 13:40:37.162932 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8424 13:40:37.166053 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8425 13:40:37.169731 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8426 13:40:37.172950 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8427 13:40:37.176441 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8428 13:40:37.182938 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8429 13:40:37.186022 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8430 13:40:37.190035 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8431 13:40:37.193068 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8432 13:40:37.196048 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8433 13:40:37.202598 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8434 13:40:37.206339 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8435 13:40:37.209580 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8436 13:40:37.212714 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8437 13:40:37.212816 ==
8438 13:40:37.216639 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 13:40:37.222789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 13:40:37.222870 ==
8441 13:40:37.222933 DQS Delay:
8442 13:40:37.226484 DQS0 = 0, DQS1 = 0
8443 13:40:37.226565 DQM Delay:
8444 13:40:37.229970 DQM0 = 133, DQM1 = 127
8445 13:40:37.230055 DQ Delay:
8446 13:40:37.232835 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8447 13:40:37.236446 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8448 13:40:37.239767 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8449 13:40:37.242864 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8450 13:40:37.242966
8451 13:40:37.243083
8452 13:40:37.243166 ==
8453 13:40:37.246196 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 13:40:37.252884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 13:40:37.253012 ==
8456 13:40:37.253093
8457 13:40:37.253153
8458 13:40:37.253209 TX Vref Scan disable
8459 13:40:37.256093 == TX Byte 0 ==
8460 13:40:37.259404 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8461 13:40:37.262864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8462 13:40:37.266031 == TX Byte 1 ==
8463 13:40:37.269494 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8464 13:40:37.272916 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8465 13:40:37.276744 ==
8466 13:40:37.276829 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 13:40:37.282750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 13:40:37.282843 ==
8469 13:40:37.295176
8470 13:40:37.298133 TX Vref early break, caculate TX vref
8471 13:40:37.301969 TX Vref=16, minBit 8, minWin=20, winSum=358
8472 13:40:37.304914 TX Vref=18, minBit 8, minWin=21, winSum=369
8473 13:40:37.308461 TX Vref=20, minBit 8, minWin=22, winSum=383
8474 13:40:37.311942 TX Vref=22, minBit 8, minWin=22, winSum=388
8475 13:40:37.314968 TX Vref=24, minBit 8, minWin=23, winSum=402
8476 13:40:37.321758 TX Vref=26, minBit 8, minWin=24, winSum=411
8477 13:40:37.325224 TX Vref=28, minBit 5, minWin=25, winSum=416
8478 13:40:37.328400 TX Vref=30, minBit 11, minWin=24, winSum=415
8479 13:40:37.331543 TX Vref=32, minBit 8, minWin=24, winSum=406
8480 13:40:37.335358 TX Vref=34, minBit 8, minWin=23, winSum=393
8481 13:40:37.342028 [TxChooseVref] Worse bit 5, Min win 25, Win sum 416, Final Vref 28
8482 13:40:37.342104
8483 13:40:37.345352 Final TX Range 0 Vref 28
8484 13:40:37.345425
8485 13:40:37.345495 ==
8486 13:40:37.348471 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 13:40:37.351628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 13:40:37.351702 ==
8489 13:40:37.351762
8490 13:40:37.351819
8491 13:40:37.354852 TX Vref Scan disable
8492 13:40:37.361920 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8493 13:40:37.361998 == TX Byte 0 ==
8494 13:40:37.365113 u2DelayCellOfst[0]=14 cells (4 PI)
8495 13:40:37.368598 u2DelayCellOfst[1]=10 cells (3 PI)
8496 13:40:37.371790 u2DelayCellOfst[2]=0 cells (0 PI)
8497 13:40:37.375242 u2DelayCellOfst[3]=7 cells (2 PI)
8498 13:40:37.378222 u2DelayCellOfst[4]=7 cells (2 PI)
8499 13:40:37.381550 u2DelayCellOfst[5]=21 cells (6 PI)
8500 13:40:37.381661 u2DelayCellOfst[6]=17 cells (5 PI)
8501 13:40:37.385297 u2DelayCellOfst[7]=7 cells (2 PI)
8502 13:40:37.391750 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8503 13:40:37.395003 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8504 13:40:37.395085 == TX Byte 1 ==
8505 13:40:37.398446 u2DelayCellOfst[8]=0 cells (0 PI)
8506 13:40:37.401834 u2DelayCellOfst[9]=3 cells (1 PI)
8507 13:40:37.405519 u2DelayCellOfst[10]=7 cells (2 PI)
8508 13:40:37.408401 u2DelayCellOfst[11]=3 cells (1 PI)
8509 13:40:37.411887 u2DelayCellOfst[12]=10 cells (3 PI)
8510 13:40:37.415083 u2DelayCellOfst[13]=14 cells (4 PI)
8511 13:40:37.418553 u2DelayCellOfst[14]=14 cells (4 PI)
8512 13:40:37.422043 u2DelayCellOfst[15]=14 cells (4 PI)
8513 13:40:37.425257 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8514 13:40:37.428426 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8515 13:40:37.431555 DramC Write-DBI on
8516 13:40:37.431650 ==
8517 13:40:37.434938 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 13:40:37.438597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 13:40:37.438669 ==
8520 13:40:37.438731
8521 13:40:37.438787
8522 13:40:37.441526 TX Vref Scan disable
8523 13:40:37.445168 == TX Byte 0 ==
8524 13:40:37.448555 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8525 13:40:37.448627 == TX Byte 1 ==
8526 13:40:37.455325 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8527 13:40:37.455394 DramC Write-DBI off
8528 13:40:37.455456
8529 13:40:37.458401 [DATLAT]
8530 13:40:37.458486 Freq=1600, CH1 RK0
8531 13:40:37.458556
8532 13:40:37.462226 DATLAT Default: 0xf
8533 13:40:37.462389 0, 0xFFFF, sum = 0
8534 13:40:37.465388 1, 0xFFFF, sum = 0
8535 13:40:37.465566 2, 0xFFFF, sum = 0
8536 13:40:37.468706 3, 0xFFFF, sum = 0
8537 13:40:37.468854 4, 0xFFFF, sum = 0
8538 13:40:37.472270 5, 0xFFFF, sum = 0
8539 13:40:37.472435 6, 0xFFFF, sum = 0
8540 13:40:37.475384 7, 0xFFFF, sum = 0
8541 13:40:37.475520 8, 0xFFFF, sum = 0
8542 13:40:37.478395 9, 0xFFFF, sum = 0
8543 13:40:37.478514 10, 0xFFFF, sum = 0
8544 13:40:37.481920 11, 0xFFFF, sum = 0
8545 13:40:37.482041 12, 0xFFFF, sum = 0
8546 13:40:37.485276 13, 0xFFFF, sum = 0
8547 13:40:37.485401 14, 0x0, sum = 1
8548 13:40:37.488867 15, 0x0, sum = 2
8549 13:40:37.489043 16, 0x0, sum = 3
8550 13:40:37.491978 17, 0x0, sum = 4
8551 13:40:37.492152 best_step = 15
8552 13:40:37.492323
8553 13:40:37.492469 ==
8554 13:40:37.495246 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 13:40:37.501860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 13:40:37.502052 ==
8557 13:40:37.502229 RX Vref Scan: 1
8558 13:40:37.502438
8559 13:40:37.505059 Set Vref Range= 24 -> 127
8560 13:40:37.505252
8561 13:40:37.508497 RX Vref 24 -> 127, step: 1
8562 13:40:37.508843
8563 13:40:37.512164 RX Delay 11 -> 252, step: 4
8564 13:40:37.512518
8565 13:40:37.512839 Set Vref, RX VrefLevel [Byte0]: 24
8566 13:40:37.515465 [Byte1]: 24
8567 13:40:37.519781
8568 13:40:37.520244 Set Vref, RX VrefLevel [Byte0]: 25
8569 13:40:37.523326 [Byte1]: 25
8570 13:40:37.527550
8571 13:40:37.527959 Set Vref, RX VrefLevel [Byte0]: 26
8572 13:40:37.530602 [Byte1]: 26
8573 13:40:37.534880
8574 13:40:37.535290 Set Vref, RX VrefLevel [Byte0]: 27
8575 13:40:37.538422 [Byte1]: 27
8576 13:40:37.542560
8577 13:40:37.542967 Set Vref, RX VrefLevel [Byte0]: 28
8578 13:40:37.546308 [Byte1]: 28
8579 13:40:37.550652
8580 13:40:37.551061 Set Vref, RX VrefLevel [Byte0]: 29
8581 13:40:37.553666 [Byte1]: 29
8582 13:40:37.557830
8583 13:40:37.558337 Set Vref, RX VrefLevel [Byte0]: 30
8584 13:40:37.561468 [Byte1]: 30
8585 13:40:37.565501
8586 13:40:37.565913 Set Vref, RX VrefLevel [Byte0]: 31
8587 13:40:37.568789 [Byte1]: 31
8588 13:40:37.573156
8589 13:40:37.573753 Set Vref, RX VrefLevel [Byte0]: 32
8590 13:40:37.576435 [Byte1]: 32
8591 13:40:37.580916
8592 13:40:37.581379 Set Vref, RX VrefLevel [Byte0]: 33
8593 13:40:37.583901 [Byte1]: 33
8594 13:40:37.588394
8595 13:40:37.588817 Set Vref, RX VrefLevel [Byte0]: 34
8596 13:40:37.591804 [Byte1]: 34
8597 13:40:37.595844
8598 13:40:37.596255 Set Vref, RX VrefLevel [Byte0]: 35
8599 13:40:37.599430 [Byte1]: 35
8600 13:40:37.603812
8601 13:40:37.604220 Set Vref, RX VrefLevel [Byte0]: 36
8602 13:40:37.607005 [Byte1]: 36
8603 13:40:37.611170
8604 13:40:37.611629 Set Vref, RX VrefLevel [Byte0]: 37
8605 13:40:37.614813 [Byte1]: 37
8606 13:40:37.619064
8607 13:40:37.619474 Set Vref, RX VrefLevel [Byte0]: 38
8608 13:40:37.622328 [Byte1]: 38
8609 13:40:37.626258
8610 13:40:37.626718 Set Vref, RX VrefLevel [Byte0]: 39
8611 13:40:37.629953 [Byte1]: 39
8612 13:40:37.634165
8613 13:40:37.634576 Set Vref, RX VrefLevel [Byte0]: 40
8614 13:40:37.637522 [Byte1]: 40
8615 13:40:37.642052
8616 13:40:37.642467 Set Vref, RX VrefLevel [Byte0]: 41
8617 13:40:37.644740 [Byte1]: 41
8618 13:40:37.649487
8619 13:40:37.649901 Set Vref, RX VrefLevel [Byte0]: 42
8620 13:40:37.652774 [Byte1]: 42
8621 13:40:37.656602
8622 13:40:37.657044 Set Vref, RX VrefLevel [Byte0]: 43
8623 13:40:37.660264 [Byte1]: 43
8624 13:40:37.664448
8625 13:40:37.664866 Set Vref, RX VrefLevel [Byte0]: 44
8626 13:40:37.668118 [Byte1]: 44
8627 13:40:37.672351
8628 13:40:37.672766 Set Vref, RX VrefLevel [Byte0]: 45
8629 13:40:37.675373 [Byte1]: 45
8630 13:40:37.679770
8631 13:40:37.680184 Set Vref, RX VrefLevel [Byte0]: 46
8632 13:40:37.682999 [Byte1]: 46
8633 13:40:37.687157
8634 13:40:37.687615 Set Vref, RX VrefLevel [Byte0]: 47
8635 13:40:37.690903 [Byte1]: 47
8636 13:40:37.695023
8637 13:40:37.695436 Set Vref, RX VrefLevel [Byte0]: 48
8638 13:40:37.698730 [Byte1]: 48
8639 13:40:37.702335
8640 13:40:37.702753 Set Vref, RX VrefLevel [Byte0]: 49
8641 13:40:37.706110 [Byte1]: 49
8642 13:40:37.710467
8643 13:40:37.710880 Set Vref, RX VrefLevel [Byte0]: 50
8644 13:40:37.713542 [Byte1]: 50
8645 13:40:37.717921
8646 13:40:37.718335 Set Vref, RX VrefLevel [Byte0]: 51
8647 13:40:37.720933 [Byte1]: 51
8648 13:40:37.725283
8649 13:40:37.725695 Set Vref, RX VrefLevel [Byte0]: 52
8650 13:40:37.728962 [Byte1]: 52
8651 13:40:37.733272
8652 13:40:37.733687 Set Vref, RX VrefLevel [Byte0]: 53
8653 13:40:37.736613 [Byte1]: 53
8654 13:40:37.740476
8655 13:40:37.740889 Set Vref, RX VrefLevel [Byte0]: 54
8656 13:40:37.744139 [Byte1]: 54
8657 13:40:37.748588
8658 13:40:37.749020 Set Vref, RX VrefLevel [Byte0]: 55
8659 13:40:37.751583 [Byte1]: 55
8660 13:40:37.756144
8661 13:40:37.756565 Set Vref, RX VrefLevel [Byte0]: 56
8662 13:40:37.759080 [Byte1]: 56
8663 13:40:37.763640
8664 13:40:37.764079 Set Vref, RX VrefLevel [Byte0]: 57
8665 13:40:37.766799 [Byte1]: 57
8666 13:40:37.771239
8667 13:40:37.771686 Set Vref, RX VrefLevel [Byte0]: 58
8668 13:40:37.774158 [Byte1]: 58
8669 13:40:37.778596
8670 13:40:37.779016 Set Vref, RX VrefLevel [Byte0]: 59
8671 13:40:37.781946 [Byte1]: 59
8672 13:40:37.786440
8673 13:40:37.786854 Set Vref, RX VrefLevel [Byte0]: 60
8674 13:40:37.789877 [Byte1]: 60
8675 13:40:37.793612
8676 13:40:37.794037 Set Vref, RX VrefLevel [Byte0]: 61
8677 13:40:37.797029 [Byte1]: 61
8678 13:40:37.801908
8679 13:40:37.802325 Set Vref, RX VrefLevel [Byte0]: 62
8680 13:40:37.804889 [Byte1]: 62
8681 13:40:37.809373
8682 13:40:37.809928 Set Vref, RX VrefLevel [Byte0]: 63
8683 13:40:37.812349 [Byte1]: 63
8684 13:40:37.816878
8685 13:40:37.817411 Set Vref, RX VrefLevel [Byte0]: 64
8686 13:40:37.820064 [Byte1]: 64
8687 13:40:37.824628
8688 13:40:37.825223 Set Vref, RX VrefLevel [Byte0]: 65
8689 13:40:37.827672 [Byte1]: 65
8690 13:40:37.832115
8691 13:40:37.832659 Set Vref, RX VrefLevel [Byte0]: 66
8692 13:40:37.835178 [Byte1]: 66
8693 13:40:37.839560
8694 13:40:37.840138 Set Vref, RX VrefLevel [Byte0]: 67
8695 13:40:37.842622 [Byte1]: 67
8696 13:40:37.846931
8697 13:40:37.847010 Set Vref, RX VrefLevel [Byte0]: 68
8698 13:40:37.849930 [Byte1]: 68
8699 13:40:37.854770
8700 13:40:37.854855 Set Vref, RX VrefLevel [Byte0]: 69
8701 13:40:37.857750 [Byte1]: 69
8702 13:40:37.861808
8703 13:40:37.861891 Set Vref, RX VrefLevel [Byte0]: 70
8704 13:40:37.865525 [Byte1]: 70
8705 13:40:37.869370
8706 13:40:37.869451 Set Vref, RX VrefLevel [Byte0]: 71
8707 13:40:37.873024 [Byte1]: 71
8708 13:40:37.877185
8709 13:40:37.877309 Set Vref, RX VrefLevel [Byte0]: 72
8710 13:40:37.880298 [Byte1]: 72
8711 13:40:37.884742
8712 13:40:37.884822 Final RX Vref Byte 0 = 60 to rank0
8713 13:40:37.888277 Final RX Vref Byte 1 = 52 to rank0
8714 13:40:37.891450 Final RX Vref Byte 0 = 60 to rank1
8715 13:40:37.895051 Final RX Vref Byte 1 = 52 to rank1==
8716 13:40:37.897978 Dram Type= 6, Freq= 0, CH_1, rank 0
8717 13:40:37.905090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 13:40:37.905173 ==
8719 13:40:37.905237 DQS Delay:
8720 13:40:37.905297 DQS0 = 0, DQS1 = 0
8721 13:40:37.908313 DQM Delay:
8722 13:40:37.908408 DQM0 = 131, DQM1 = 124
8723 13:40:37.911648 DQ Delay:
8724 13:40:37.915221 DQ0 =136, DQ1 =124, DQ2 =120, DQ3 =130
8725 13:40:37.917922 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8726 13:40:37.921467 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8727 13:40:37.924893 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8728 13:40:37.924999
8729 13:40:37.925088
8730 13:40:37.925178
8731 13:40:37.928503 [DramC_TX_OE_Calibration] TA2
8732 13:40:37.931333 Original DQ_B0 (3 6) =30, OEN = 27
8733 13:40:37.934912 Original DQ_B1 (3 6) =30, OEN = 27
8734 13:40:37.938213 24, 0x0, End_B0=24 End_B1=24
8735 13:40:37.938321 25, 0x0, End_B0=25 End_B1=25
8736 13:40:37.941531 26, 0x0, End_B0=26 End_B1=26
8737 13:40:37.945373 27, 0x0, End_B0=27 End_B1=27
8738 13:40:37.948484 28, 0x0, End_B0=28 End_B1=28
8739 13:40:37.948565 29, 0x0, End_B0=29 End_B1=29
8740 13:40:37.951628 30, 0x0, End_B0=30 End_B1=30
8741 13:40:37.955302 31, 0x4141, End_B0=30 End_B1=30
8742 13:40:37.958232 Byte0 end_step=30 best_step=27
8743 13:40:37.961677 Byte1 end_step=30 best_step=27
8744 13:40:37.964896 Byte0 TX OE(2T, 0.5T) = (3, 3)
8745 13:40:37.964984 Byte1 TX OE(2T, 0.5T) = (3, 3)
8746 13:40:37.965078
8747 13:40:37.965137
8748 13:40:37.974981 [DQSOSCAuto] RK0, (LSB)MR18= 0x13ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 400 ps
8749 13:40:37.978314 CH1 RK0: MR19=302, MR18=13FF
8750 13:40:37.981949 CH1_RK0: MR19=0x302, MR18=0x13FF, DQSOSC=400, MR23=63, INC=23, DEC=15
8751 13:40:37.985261
8752 13:40:37.988450 ----->DramcWriteLeveling(PI) begin...
8753 13:40:37.988561 ==
8754 13:40:37.992030 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 13:40:37.994931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 13:40:37.995031 ==
8757 13:40:37.998218 Write leveling (Byte 0): 26 => 26
8758 13:40:38.001617 Write leveling (Byte 1): 26 => 26
8759 13:40:38.005010 DramcWriteLeveling(PI) end<-----
8760 13:40:38.005130
8761 13:40:38.005221 ==
8762 13:40:38.008284 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 13:40:38.011564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 13:40:38.011645 ==
8765 13:40:38.015300 [Gating] SW mode calibration
8766 13:40:38.022083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8767 13:40:38.028492 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8768 13:40:38.031690 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 13:40:38.035410 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 13:40:38.038421 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8771 13:40:38.045360 1 4 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8772 13:40:38.048469 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 13:40:38.051778 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 13:40:38.058168 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 13:40:38.061735 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 13:40:38.065402 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 13:40:38.071619 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8778 13:40:38.075397 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
8779 13:40:38.078274 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8780 13:40:38.084911 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8781 13:40:38.088509 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 13:40:38.091603 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 13:40:38.098610 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 13:40:38.101901 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 13:40:38.104863 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8786 13:40:38.111978 1 6 8 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
8787 13:40:38.115023 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8788 13:40:38.118563 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 13:40:38.125286 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 13:40:38.128448 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 13:40:38.131747 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 13:40:38.138730 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 13:40:38.141858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 13:40:38.145669 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 13:40:38.148803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8796 13:40:38.155557 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 13:40:38.158845 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 13:40:38.161960 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 13:40:38.168729 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 13:40:38.171862 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 13:40:38.175139 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 13:40:38.182119 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 13:40:38.185826 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 13:40:38.189068 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 13:40:38.196088 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 13:40:38.198732 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 13:40:38.202443 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 13:40:38.209394 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 13:40:38.212354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8810 13:40:38.215271 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 13:40:38.222201 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8812 13:40:38.222630 Total UI for P1: 0, mck2ui 16
8813 13:40:38.225454 best dqsien dly found for B0: ( 1, 9, 6)
8814 13:40:38.232391 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 13:40:38.235601 Total UI for P1: 0, mck2ui 16
8816 13:40:38.239268 best dqsien dly found for B1: ( 1, 9, 10)
8817 13:40:38.242635 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8818 13:40:38.245708 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8819 13:40:38.246258
8820 13:40:38.248815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8821 13:40:38.252063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8822 13:40:38.255751 [Gating] SW calibration Done
8823 13:40:38.256165 ==
8824 13:40:38.258911 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 13:40:38.262208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 13:40:38.262629 ==
8827 13:40:38.266012 RX Vref Scan: 0
8828 13:40:38.266424
8829 13:40:38.266754 RX Vref 0 -> 0, step: 1
8830 13:40:38.267062
8831 13:40:38.269250 RX Delay 0 -> 252, step: 8
8832 13:40:38.272198 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8833 13:40:38.278926 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8834 13:40:38.282602 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8835 13:40:38.285879 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8836 13:40:38.288818 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8837 13:40:38.292244 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8838 13:40:38.299230 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8839 13:40:38.302366 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8840 13:40:38.306048 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8841 13:40:38.309189 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8842 13:40:38.312349 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8843 13:40:38.319195 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8844 13:40:38.322753 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8845 13:40:38.325829 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8846 13:40:38.329001 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8847 13:40:38.332379 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8848 13:40:38.335927 ==
8849 13:40:38.336340 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 13:40:38.342449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 13:40:38.342936 ==
8852 13:40:38.343375 DQS Delay:
8853 13:40:38.345812 DQS0 = 0, DQS1 = 0
8854 13:40:38.346261 DQM Delay:
8855 13:40:38.348855 DQM0 = 132, DQM1 = 128
8856 13:40:38.349349 DQ Delay:
8857 13:40:38.352164 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8858 13:40:38.355523 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8859 13:40:38.359036 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8860 13:40:38.361998 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8861 13:40:38.362409
8862 13:40:38.362729
8863 13:40:38.363031 ==
8864 13:40:38.365816 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 13:40:38.372623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 13:40:38.373069 ==
8867 13:40:38.373398
8868 13:40:38.373702
8869 13:40:38.373994 TX Vref Scan disable
8870 13:40:38.375707 == TX Byte 0 ==
8871 13:40:38.378985 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8872 13:40:38.382717 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8873 13:40:38.385634 == TX Byte 1 ==
8874 13:40:38.389339 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8875 13:40:38.395485 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8876 13:40:38.395911 ==
8877 13:40:38.399181 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 13:40:38.402265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 13:40:38.402690 ==
8880 13:40:38.415518
8881 13:40:38.418861 TX Vref early break, caculate TX vref
8882 13:40:38.422325 TX Vref=16, minBit 5, minWin=22, winSum=377
8883 13:40:38.425326 TX Vref=18, minBit 9, minWin=23, winSum=390
8884 13:40:38.428631 TX Vref=20, minBit 0, minWin=24, winSum=401
8885 13:40:38.432159 TX Vref=22, minBit 9, minWin=24, winSum=404
8886 13:40:38.435551 TX Vref=24, minBit 0, minWin=25, winSum=414
8887 13:40:38.442110 TX Vref=26, minBit 0, minWin=26, winSum=425
8888 13:40:38.445818 TX Vref=28, minBit 5, minWin=25, winSum=423
8889 13:40:38.448750 TX Vref=30, minBit 5, minWin=25, winSum=424
8890 13:40:38.451936 TX Vref=32, minBit 0, minWin=25, winSum=417
8891 13:40:38.455813 TX Vref=34, minBit 3, minWin=24, winSum=406
8892 13:40:38.459181 TX Vref=36, minBit 0, minWin=24, winSum=400
8893 13:40:38.465534 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8894 13:40:38.465983
8895 13:40:38.469016 Final TX Range 0 Vref 26
8896 13:40:38.469498
8897 13:40:38.469987 ==
8898 13:40:38.472481 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 13:40:38.475677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 13:40:38.476234 ==
8901 13:40:38.476735
8902 13:40:38.477280
8903 13:40:38.478516 TX Vref Scan disable
8904 13:40:38.485336 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8905 13:40:38.485752 == TX Byte 0 ==
8906 13:40:38.488941 u2DelayCellOfst[0]=14 cells (4 PI)
8907 13:40:38.491895 u2DelayCellOfst[1]=10 cells (3 PI)
8908 13:40:38.495591 u2DelayCellOfst[2]=0 cells (0 PI)
8909 13:40:38.498621 u2DelayCellOfst[3]=7 cells (2 PI)
8910 13:40:38.501862 u2DelayCellOfst[4]=7 cells (2 PI)
8911 13:40:38.505372 u2DelayCellOfst[5]=17 cells (5 PI)
8912 13:40:38.508424 u2DelayCellOfst[6]=17 cells (5 PI)
8913 13:40:38.512290 u2DelayCellOfst[7]=3 cells (1 PI)
8914 13:40:38.515234 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8915 13:40:38.518376 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8916 13:40:38.521911 == TX Byte 1 ==
8917 13:40:38.522317 u2DelayCellOfst[8]=0 cells (0 PI)
8918 13:40:38.525079 u2DelayCellOfst[9]=3 cells (1 PI)
8919 13:40:38.528562 u2DelayCellOfst[10]=10 cells (3 PI)
8920 13:40:38.531933 u2DelayCellOfst[11]=3 cells (1 PI)
8921 13:40:38.535597 u2DelayCellOfst[12]=14 cells (4 PI)
8922 13:40:38.538665 u2DelayCellOfst[13]=14 cells (4 PI)
8923 13:40:38.541754 u2DelayCellOfst[14]=17 cells (5 PI)
8924 13:40:38.545550 u2DelayCellOfst[15]=14 cells (4 PI)
8925 13:40:38.548474 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 13:40:38.555269 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 13:40:38.555870 DramC Write-DBI on
8928 13:40:38.556279 ==
8929 13:40:38.558951 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 13:40:38.561837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 13:40:38.565221 ==
8932 13:40:38.565659
8933 13:40:38.565983
8934 13:40:38.566325 TX Vref Scan disable
8935 13:40:38.568397 == TX Byte 0 ==
8936 13:40:38.572232 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 13:40:38.575647 == TX Byte 1 ==
8938 13:40:38.578803 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 13:40:38.579356 DramC Write-DBI off
8940 13:40:38.581957
8941 13:40:38.582512 [DATLAT]
8942 13:40:38.582955 Freq=1600, CH1 RK1
8943 13:40:38.583360
8944 13:40:38.585676 DATLAT Default: 0xf
8945 13:40:38.586109 0, 0xFFFF, sum = 0
8946 13:40:38.588399 1, 0xFFFF, sum = 0
8947 13:40:38.589032 2, 0xFFFF, sum = 0
8948 13:40:38.592157 3, 0xFFFF, sum = 0
8949 13:40:38.592590 4, 0xFFFF, sum = 0
8950 13:40:38.595213 5, 0xFFFF, sum = 0
8951 13:40:38.598904 6, 0xFFFF, sum = 0
8952 13:40:38.599470 7, 0xFFFF, sum = 0
8953 13:40:38.601892 8, 0xFFFF, sum = 0
8954 13:40:38.602611 9, 0xFFFF, sum = 0
8955 13:40:38.605641 10, 0xFFFF, sum = 0
8956 13:40:38.606146 11, 0xFFFF, sum = 0
8957 13:40:38.608570 12, 0xFFFF, sum = 0
8958 13:40:38.609215 13, 0xFFFF, sum = 0
8959 13:40:38.611676 14, 0x0, sum = 1
8960 13:40:38.612135 15, 0x0, sum = 2
8961 13:40:38.615481 16, 0x0, sum = 3
8962 13:40:38.615908 17, 0x0, sum = 4
8963 13:40:38.618455 best_step = 15
8964 13:40:38.618878
8965 13:40:38.619204 ==
8966 13:40:38.622102 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 13:40:38.625413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 13:40:38.625834 ==
8969 13:40:38.626228 RX Vref Scan: 0
8970 13:40:38.626548
8971 13:40:38.628405 RX Vref 0 -> 0, step: 1
8972 13:40:38.628821
8973 13:40:38.632163 RX Delay 11 -> 252, step: 4
8974 13:40:38.635255 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8975 13:40:38.641878 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8976 13:40:38.645408 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8977 13:40:38.648545 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8978 13:40:38.652054 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8979 13:40:38.655274 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8980 13:40:38.659100 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8981 13:40:38.665185 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8982 13:40:38.668803 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8983 13:40:38.671822 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
8984 13:40:38.675370 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8985 13:40:38.678745 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8986 13:40:38.685403 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8987 13:40:38.688937 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8988 13:40:38.692320 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8989 13:40:38.695388 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8990 13:40:38.695958 ==
8991 13:40:38.698994 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 13:40:38.705111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 13:40:38.705568 ==
8994 13:40:38.705932 DQS Delay:
8995 13:40:38.708695 DQS0 = 0, DQS1 = 0
8996 13:40:38.709145 DQM Delay:
8997 13:40:38.709480 DQM0 = 129, DQM1 = 126
8998 13:40:38.712114 DQ Delay:
8999 13:40:38.715746 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9000 13:40:38.719650 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9001 13:40:38.721950 DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =118
9002 13:40:38.725708 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9003 13:40:38.726389
9004 13:40:38.726857
9005 13:40:38.727176
9006 13:40:38.728821 [DramC_TX_OE_Calibration] TA2
9007 13:40:38.732696 Original DQ_B0 (3 6) =30, OEN = 27
9008 13:40:38.735624 Original DQ_B1 (3 6) =30, OEN = 27
9009 13:40:38.738760 24, 0x0, End_B0=24 End_B1=24
9010 13:40:38.739221 25, 0x0, End_B0=25 End_B1=25
9011 13:40:38.742412 26, 0x0, End_B0=26 End_B1=26
9012 13:40:38.745456 27, 0x0, End_B0=27 End_B1=27
9013 13:40:38.748798 28, 0x0, End_B0=28 End_B1=28
9014 13:40:38.749346 29, 0x0, End_B0=29 End_B1=29
9015 13:40:38.752101 30, 0x0, End_B0=30 End_B1=30
9016 13:40:38.755608 31, 0x4141, End_B0=30 End_B1=30
9017 13:40:38.759181 Byte0 end_step=30 best_step=27
9018 13:40:38.762243 Byte1 end_step=30 best_step=27
9019 13:40:38.765711 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 13:40:38.766218 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 13:40:38.766582
9022 13:40:38.766884
9023 13:40:38.775794 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9024 13:40:38.779337 CH1 RK1: MR19=303, MR18=1117
9025 13:40:38.785679 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9026 13:40:38.786093 [RxdqsGatingPostProcess] freq 1600
9027 13:40:38.792490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 13:40:38.795497 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 13:40:38.798966 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 13:40:38.802648 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 13:40:38.805454 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 13:40:38.808878 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 13:40:38.812265 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 13:40:38.815599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 13:40:38.816108 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 13:40:38.819123 Pre-setting of DQS Precalculation
9037 13:40:38.826157 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 13:40:38.832705 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 13:40:38.838803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 13:40:38.839237
9041 13:40:38.839583
9042 13:40:38.842554 [Calibration Summary] 3200 Mbps
9043 13:40:38.845681 CH 0, Rank 0
9044 13:40:38.846134 SW Impedance : PASS
9045 13:40:38.849669 DUTY Scan : NO K
9046 13:40:38.850192 ZQ Calibration : PASS
9047 13:40:38.852712 Jitter Meter : NO K
9048 13:40:38.855798 CBT Training : PASS
9049 13:40:38.856339 Write leveling : PASS
9050 13:40:38.859253 RX DQS gating : PASS
9051 13:40:38.862727 RX DQ/DQS(RDDQC) : PASS
9052 13:40:38.863135 TX DQ/DQS : PASS
9053 13:40:38.865691 RX DATLAT : PASS
9054 13:40:38.869513 RX DQ/DQS(Engine): PASS
9055 13:40:38.869963 TX OE : PASS
9056 13:40:38.872241 All Pass.
9057 13:40:38.872753
9058 13:40:38.873121 CH 0, Rank 1
9059 13:40:38.876000 SW Impedance : PASS
9060 13:40:38.876409 DUTY Scan : NO K
9061 13:40:38.879019 ZQ Calibration : PASS
9062 13:40:38.882857 Jitter Meter : NO K
9063 13:40:38.883270 CBT Training : PASS
9064 13:40:38.885615 Write leveling : PASS
9065 13:40:38.886025 RX DQS gating : PASS
9066 13:40:38.889218 RX DQ/DQS(RDDQC) : PASS
9067 13:40:38.892899 TX DQ/DQS : PASS
9068 13:40:38.893345 RX DATLAT : PASS
9069 13:40:38.896138 RX DQ/DQS(Engine): PASS
9070 13:40:38.899053 TX OE : PASS
9071 13:40:38.899468 All Pass.
9072 13:40:38.899789
9073 13:40:38.900088 CH 1, Rank 0
9074 13:40:38.902687 SW Impedance : PASS
9075 13:40:38.906129 DUTY Scan : NO K
9076 13:40:38.906543 ZQ Calibration : PASS
9077 13:40:38.909035 Jitter Meter : NO K
9078 13:40:38.912890 CBT Training : PASS
9079 13:40:38.913340 Write leveling : PASS
9080 13:40:38.915899 RX DQS gating : PASS
9081 13:40:38.919259 RX DQ/DQS(RDDQC) : PASS
9082 13:40:38.919679 TX DQ/DQS : PASS
9083 13:40:38.922626 RX DATLAT : PASS
9084 13:40:38.926051 RX DQ/DQS(Engine): PASS
9085 13:40:38.926550 TX OE : PASS
9086 13:40:38.926894 All Pass.
9087 13:40:38.927276
9088 13:40:38.929454 CH 1, Rank 1
9089 13:40:38.930043 SW Impedance : PASS
9090 13:40:38.932644 DUTY Scan : NO K
9091 13:40:38.935875 ZQ Calibration : PASS
9092 13:40:38.936293 Jitter Meter : NO K
9093 13:40:38.939642 CBT Training : PASS
9094 13:40:38.942553 Write leveling : PASS
9095 13:40:38.942979 RX DQS gating : PASS
9096 13:40:38.946290 RX DQ/DQS(RDDQC) : PASS
9097 13:40:38.949406 TX DQ/DQS : PASS
9098 13:40:38.949824 RX DATLAT : PASS
9099 13:40:38.952528 RX DQ/DQS(Engine): PASS
9100 13:40:38.956150 TX OE : PASS
9101 13:40:38.956566 All Pass.
9102 13:40:38.956892
9103 13:40:38.957236 DramC Write-DBI on
9104 13:40:38.959331 PER_BANK_REFRESH: Hybrid Mode
9105 13:40:38.962762 TX_TRACKING: ON
9106 13:40:38.969462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 13:40:38.979244 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 13:40:38.986000 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 13:40:38.988915 [FAST_K] Save calibration result to emmc
9110 13:40:38.992753 sync common calibartion params.
9111 13:40:38.993310 sync cbt_mode0:1, 1:1
9112 13:40:38.995859 dram_init: ddr_geometry: 2
9113 13:40:38.999402 dram_init: ddr_geometry: 2
9114 13:40:39.002407 dram_init: ddr_geometry: 2
9115 13:40:39.002821 0:dram_rank_size:100000000
9116 13:40:39.005567 1:dram_rank_size:100000000
9117 13:40:39.012651 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 13:40:39.013115 DFS_SHUFFLE_HW_MODE: ON
9119 13:40:39.019399 dramc_set_vcore_voltage set vcore to 725000
9120 13:40:39.019814 Read voltage for 1600, 0
9121 13:40:39.022469 Vio18 = 0
9122 13:40:39.022882 Vcore = 725000
9123 13:40:39.023210 Vdram = 0
9124 13:40:39.023517 Vddq = 0
9125 13:40:39.025693 Vmddr = 0
9126 13:40:39.029403 switch to 3200 Mbps bootup
9127 13:40:39.029821 [DramcRunTimeConfig]
9128 13:40:39.030151 PHYPLL
9129 13:40:39.032301 DPM_CONTROL_AFTERK: ON
9130 13:40:39.032712 PER_BANK_REFRESH: ON
9131 13:40:39.035682 REFRESH_OVERHEAD_REDUCTION: ON
9132 13:40:39.039006 CMD_PICG_NEW_MODE: OFF
9133 13:40:39.039420 XRTWTW_NEW_MODE: ON
9134 13:40:39.042434 XRTRTR_NEW_MODE: ON
9135 13:40:39.042846 TX_TRACKING: ON
9136 13:40:39.046033 RDSEL_TRACKING: OFF
9137 13:40:39.049218 DQS Precalculation for DVFS: ON
9138 13:40:39.049634 RX_TRACKING: OFF
9139 13:40:39.052838 HW_GATING DBG: ON
9140 13:40:39.053272 ZQCS_ENABLE_LP4: ON
9141 13:40:39.055991 RX_PICG_NEW_MODE: ON
9142 13:40:39.056400 TX_PICG_NEW_MODE: ON
9143 13:40:39.059049 ENABLE_RX_DCM_DPHY: ON
9144 13:40:39.062730 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 13:40:39.065784 DUMMY_READ_FOR_TRACKING: OFF
9146 13:40:39.069432 !!! SPM_CONTROL_AFTERK: OFF
9147 13:40:39.070092 !!! SPM could not control APHY
9148 13:40:39.072342 IMPEDANCE_TRACKING: ON
9149 13:40:39.072923 TEMP_SENSOR: ON
9150 13:40:39.076061 HW_SAVE_FOR_SR: OFF
9151 13:40:39.079763 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 13:40:39.082563 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 13:40:39.086338 Read ODT Tracking: ON
9154 13:40:39.086758 Refresh Rate DeBounce: ON
9155 13:40:39.089491 DFS_NO_QUEUE_FLUSH: ON
9156 13:40:39.092822 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 13:40:39.096321 ENABLE_DFS_RUNTIME_MRW: OFF
9158 13:40:39.096735 DDR_RESERVE_NEW_MODE: ON
9159 13:40:39.099674 MR_CBT_SWITCH_FREQ: ON
9160 13:40:39.102398 =========================
9161 13:40:39.119572 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 13:40:39.123316 dram_init: ddr_geometry: 2
9163 13:40:39.141916 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 13:40:39.144632 dram_init: dram init end (result: 0)
9165 13:40:39.151379 DRAM-K: Full calibration passed in 24547 msecs
9166 13:40:39.154633 MRC: failed to locate region type 0.
9167 13:40:39.154762 DRAM rank0 size:0x100000000,
9168 13:40:39.158429 DRAM rank1 size=0x100000000
9169 13:40:39.168224 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 13:40:39.175157 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 13:40:39.181613 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 13:40:39.188611 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 13:40:39.191527 DRAM rank0 size:0x100000000,
9174 13:40:39.195147 DRAM rank1 size=0x100000000
9175 13:40:39.195560 CBMEM:
9176 13:40:39.198715 IMD: root @ 0xfffff000 254 entries.
9177 13:40:39.202173 IMD: root @ 0xffffec00 62 entries.
9178 13:40:39.205537 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 13:40:39.208510 WARNING: RO_VPD is uninitialized or empty.
9180 13:40:39.215245 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 13:40:39.221685 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 13:40:39.234436 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9183 13:40:39.245754 BS: romstage times (exec / console): total (unknown) / 24054 ms
9184 13:40:39.246173
9185 13:40:39.246500
9186 13:40:39.255718 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 13:40:39.259373 ARM64: Exception handlers installed.
9188 13:40:39.262305 ARM64: Testing exception
9189 13:40:39.266048 ARM64: Done test exception
9190 13:40:39.266464 Enumerating buses...
9191 13:40:39.269191 Show all devs... Before device enumeration.
9192 13:40:39.273117 Root Device: enabled 1
9193 13:40:39.276036 CPU_CLUSTER: 0: enabled 1
9194 13:40:39.276452 CPU: 00: enabled 1
9195 13:40:39.279181 Compare with tree...
9196 13:40:39.279598 Root Device: enabled 1
9197 13:40:39.282575 CPU_CLUSTER: 0: enabled 1
9198 13:40:39.286224 CPU: 00: enabled 1
9199 13:40:39.286642 Root Device scanning...
9200 13:40:39.289463 scan_static_bus for Root Device
9201 13:40:39.292405 CPU_CLUSTER: 0 enabled
9202 13:40:39.296202 scan_static_bus for Root Device done
9203 13:40:39.298977 scan_bus: bus Root Device finished in 8 msecs
9204 13:40:39.299492 done
9205 13:40:39.305719 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 13:40:39.309127 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 13:40:39.315976 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 13:40:39.319439 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 13:40:39.322860 Allocating resources...
9210 13:40:39.323276 Reading resources...
9211 13:40:39.325853 Root Device read_resources bus 0 link: 0
9212 13:40:39.329331 DRAM rank0 size:0x100000000,
9213 13:40:39.333008 DRAM rank1 size=0x100000000
9214 13:40:39.336195 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 13:40:39.339341 CPU: 00 missing read_resources
9216 13:40:39.342806 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 13:40:39.346206 Root Device read_resources bus 0 link: 0 done
9218 13:40:39.349518 Done reading resources.
9219 13:40:39.356170 Show resources in subtree (Root Device)...After reading.
9220 13:40:39.359577 Root Device child on link 0 CPU_CLUSTER: 0
9221 13:40:39.362962 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 13:40:39.372937 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 13:40:39.373563 CPU: 00
9224 13:40:39.375870 Root Device assign_resources, bus 0 link: 0
9225 13:40:39.379553 CPU_CLUSTER: 0 missing set_resources
9226 13:40:39.382858 Root Device assign_resources, bus 0 link: 0 done
9227 13:40:39.386174 Done setting resources.
9228 13:40:39.393047 Show resources in subtree (Root Device)...After assigning values.
9229 13:40:39.395985 Root Device child on link 0 CPU_CLUSTER: 0
9230 13:40:39.399588 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 13:40:39.409472 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 13:40:39.409907 CPU: 00
9233 13:40:39.413029 Done allocating resources.
9234 13:40:39.416286 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 13:40:39.419746 Enabling resources...
9236 13:40:39.420179 done.
9237 13:40:39.423139 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 13:40:39.425809 Initializing devices...
9239 13:40:39.426235 Root Device init
9240 13:40:39.429295 init hardware done!
9241 13:40:39.432782 0x00000018: ctrlr->caps
9242 13:40:39.433292 52.000 MHz: ctrlr->f_max
9243 13:40:39.435918 0.400 MHz: ctrlr->f_min
9244 13:40:39.439992 0x40ff8080: ctrlr->voltages
9245 13:40:39.440524 sclk: 390625
9246 13:40:39.440859 Bus Width = 1
9247 13:40:39.442833 sclk: 390625
9248 13:40:39.443244 Bus Width = 1
9249 13:40:39.445770 Early init status = 3
9250 13:40:39.449220 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 13:40:39.453672 in-header: 03 fc 00 00 01 00 00 00
9252 13:40:39.456678 in-data: 00
9253 13:40:39.459757 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 13:40:39.464557 in-header: 03 fd 00 00 00 00 00 00
9255 13:40:39.467993 in-data:
9256 13:40:39.471514 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 13:40:39.474749 in-header: 03 fc 00 00 01 00 00 00
9258 13:40:39.478211 in-data: 00
9259 13:40:39.481854 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 13:40:39.486851 in-header: 03 fd 00 00 00 00 00 00
9261 13:40:39.490033 in-data:
9262 13:40:39.493244 [SSUSB] Setting up USB HOST controller...
9263 13:40:39.496998 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 13:40:39.500610 [SSUSB] phy power-on done.
9265 13:40:39.503538 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 13:40:39.510345 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 13:40:39.513404 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 13:40:39.520106 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 13:40:39.526933 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 13:40:39.533963 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 13:40:39.540211 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 13:40:39.546758 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9273 13:40:39.547219 SPM: binary array size = 0x9dc
9274 13:40:39.553460 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 13:40:39.560438 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 13:40:39.567219 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 13:40:39.570204 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 13:40:39.573280 configure_display: Starting display init
9279 13:40:39.610248 anx7625_power_on_init: Init interface.
9280 13:40:39.613420 anx7625_disable_pd_protocol: Disabled PD feature.
9281 13:40:39.616872 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 13:40:39.644931 anx7625_start_dp_work: Secure OCM version=00
9283 13:40:39.647998 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 13:40:39.662561 sp_tx_get_edid_block: EDID Block = 1
9285 13:40:39.765545 Extracted contents:
9286 13:40:39.768482 header: 00 ff ff ff ff ff ff 00
9287 13:40:39.771906 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 13:40:39.775325 version: 01 04
9289 13:40:39.778903 basic params: 95 1f 11 78 0a
9290 13:40:39.782118 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 13:40:39.785200 established: 00 00 00
9292 13:40:39.791761 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 13:40:39.795477 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 13:40:39.801567 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 13:40:39.808438 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 13:40:39.814890 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 13:40:39.818300 extensions: 00
9298 13:40:39.818677 checksum: fb
9299 13:40:39.819008
9300 13:40:39.821379 Manufacturer: IVO Model 57d Serial Number 0
9301 13:40:39.824915 Made week 0 of 2020
9302 13:40:39.825379 EDID version: 1.4
9303 13:40:39.828819 Digital display
9304 13:40:39.831692 6 bits per primary color channel
9305 13:40:39.832142 DisplayPort interface
9306 13:40:39.834854 Maximum image size: 31 cm x 17 cm
9307 13:40:39.838514 Gamma: 220%
9308 13:40:39.838915 Check DPMS levels
9309 13:40:39.841700 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 13:40:39.844849 First detailed timing is preferred timing
9311 13:40:39.848403 Established timings supported:
9312 13:40:39.851847 Standard timings supported:
9313 13:40:39.852142 Detailed timings
9314 13:40:39.858422 Hex of detail: 383680a07038204018303c0035ae10000019
9315 13:40:39.861995 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 13:40:39.864992 0780 0798 07c8 0820 hborder 0
9317 13:40:39.871740 0438 043b 0447 0458 vborder 0
9318 13:40:39.872081 -hsync -vsync
9319 13:40:39.875290 Did detailed timing
9320 13:40:39.878836 Hex of detail: 000000000000000000000000000000000000
9321 13:40:39.881802 Manufacturer-specified data, tag 0
9322 13:40:39.888509 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 13:40:39.888886 ASCII string: InfoVision
9324 13:40:39.895464 Hex of detail: 000000fe00523134304e574635205248200a
9325 13:40:39.895972 ASCII string: R140NWF5 RH
9326 13:40:39.898908 Checksum
9327 13:40:39.899275 Checksum: 0xfb (valid)
9328 13:40:39.905280 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 13:40:39.905756 DSI data_rate: 832800000 bps
9330 13:40:39.912790 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 13:40:39.916056 anx7625_parse_edid: pixelclock(138800).
9332 13:40:39.919738 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 13:40:39.923008 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 13:40:39.926072 anx7625_dsi_config: config dsi.
9335 13:40:39.933289 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 13:40:39.947569 anx7625_dsi_config: success to config DSI
9337 13:40:39.950472 anx7625_dp_start: MIPI phy setup OK.
9338 13:40:39.954109 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 13:40:39.957525 mtk_ddp_mode_set invalid vrefresh 60
9340 13:40:39.960646 main_disp_path_setup
9341 13:40:39.961150 ovl_layer_smi_id_en
9342 13:40:39.963729 ovl_layer_smi_id_en
9343 13:40:39.964138 ccorr_config
9344 13:40:39.964487 aal_config
9345 13:40:39.967550 gamma_config
9346 13:40:39.967982 postmask_config
9347 13:40:39.970398 dither_config
9348 13:40:39.974033 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 13:40:39.980680 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 13:40:39.983805 Root Device init finished in 552 msecs
9351 13:40:39.984219 CPU_CLUSTER: 0 init
9352 13:40:39.993992 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 13:40:39.997242 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 13:40:40.000649 APU_MBOX 0x190000b0 = 0x10001
9355 13:40:40.003649 APU_MBOX 0x190001b0 = 0x10001
9356 13:40:40.007103 APU_MBOX 0x190005b0 = 0x10001
9357 13:40:40.010531 APU_MBOX 0x190006b0 = 0x10001
9358 13:40:40.014039 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 13:40:40.026437 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9360 13:40:40.038998 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 13:40:40.045655 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 13:40:40.057310 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9363 13:40:40.066334 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 13:40:40.069365 CPU_CLUSTER: 0 init finished in 81 msecs
9365 13:40:40.072829 Devices initialized
9366 13:40:40.075992 Show all devs... After init.
9367 13:40:40.076646 Root Device: enabled 1
9368 13:40:40.079500 CPU_CLUSTER: 0: enabled 1
9369 13:40:40.082905 CPU: 00: enabled 1
9370 13:40:40.085981 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9371 13:40:40.089789 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 13:40:40.092771 ELOG: NV offset 0x57f000 size 0x1000
9373 13:40:40.099599 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9374 13:40:40.106391 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 13:40:40.109620 ELOG: Event(17) added with size 13 at 2024-05-28 13:40:40 UTC
9376 13:40:40.112549 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 13:40:40.117425 in-header: 03 f9 00 00 2c 00 00 00
9378 13:40:40.130379 in-data: 66 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 13:40:40.137101 ELOG: Event(A1) added with size 10 at 2024-05-28 13:40:40 UTC
9380 13:40:40.144305 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 13:40:40.150334 ELOG: Event(A0) added with size 9 at 2024-05-28 13:40:40 UTC
9382 13:40:40.154188 elog_add_boot_reason: Logged dev mode boot
9383 13:40:40.157439 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9384 13:40:40.160597 Finalize devices...
9385 13:40:40.161144 Devices finalized
9386 13:40:40.167323 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 13:40:40.170168 Writing coreboot table at 0xffe64000
9388 13:40:40.174378 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 13:40:40.177277 1. 0000000040000000-00000000400fffff: RAM
9390 13:40:40.180834 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 13:40:40.187521 3. 000000004032b000-00000000545fffff: RAM
9392 13:40:40.190692 4. 0000000054600000-000000005465ffff: BL31
9393 13:40:40.194318 5. 0000000054660000-00000000ffe63fff: RAM
9394 13:40:40.197492 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 13:40:40.203728 7. 0000000100000000-000000023fffffff: RAM
9396 13:40:40.204326 Passing 5 GPIOs to payload:
9397 13:40:40.210659 NAME | PORT | POLARITY | VALUE
9398 13:40:40.213685 EC in RW | 0x000000aa | low | undefined
9399 13:40:40.220928 EC interrupt | 0x00000005 | low | undefined
9400 13:40:40.223920 TPM interrupt | 0x000000ab | high | undefined
9401 13:40:40.227036 SD card detect | 0x00000011 | high | undefined
9402 13:40:40.233820 speaker enable | 0x00000093 | high | undefined
9403 13:40:40.237448 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 13:40:40.240322 in-header: 03 f9 00 00 02 00 00 00
9405 13:40:40.240734 in-data: 02 00
9406 13:40:40.243621 ADC[4]: Raw value=899852 ID=7
9407 13:40:40.247522 ADC[3]: Raw value=213336 ID=1
9408 13:40:40.248010 RAM Code: 0x71
9409 13:40:40.250724 ADC[6]: Raw value=74557 ID=0
9410 13:40:40.253866 ADC[5]: Raw value=211860 ID=1
9411 13:40:40.254315 SKU Code: 0x1
9412 13:40:40.261059 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a3a8
9413 13:40:40.263962 coreboot table: 964 bytes.
9414 13:40:40.267015 IMD ROOT 0. 0xfffff000 0x00001000
9415 13:40:40.270814 IMD SMALL 1. 0xffffe000 0x00001000
9416 13:40:40.273938 RO MCACHE 2. 0xffffc000 0x00001104
9417 13:40:40.277443 CONSOLE 3. 0xfff7c000 0x00080000
9418 13:40:40.280870 FMAP 4. 0xfff7b000 0x00000452
9419 13:40:40.283466 TIME STAMP 5. 0xfff7a000 0x00000910
9420 13:40:40.287300 VBOOT WORK 6. 0xfff66000 0x00014000
9421 13:40:40.290268 RAMOOPS 7. 0xffe66000 0x00100000
9422 13:40:40.293905 COREBOOT 8. 0xffe64000 0x00002000
9423 13:40:40.293984 IMD small region:
9424 13:40:40.297185 IMD ROOT 0. 0xffffec00 0x00000400
9425 13:40:40.300266 VPD 1. 0xffffeb80 0x0000006c
9426 13:40:40.303315 MMC STATUS 2. 0xffffeb60 0x00000004
9427 13:40:40.309938 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 13:40:40.310018 Probing TPM: done!
9429 13:40:40.316815 Connected to device vid:did:rid of 1ae0:0028:00
9430 13:40:40.323318 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 13:40:40.326633 Initialized TPM device CR50 revision 0
9432 13:40:40.330825 Checking cr50 for pending updates
9433 13:40:40.336483 Reading cr50 TPM mode
9434 13:40:40.345118 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 13:40:40.351493 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 13:40:40.391743 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9437 13:40:40.395278 Checking segment from ROM address 0x40100000
9438 13:40:40.398343 Checking segment from ROM address 0x4010001c
9439 13:40:40.405111 Loading segment from ROM address 0x40100000
9440 13:40:40.405210 code (compression=0)
9441 13:40:40.411713 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 13:40:40.422131 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 13:40:40.422212 it's not compressed!
9444 13:40:40.428381 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 13:40:40.431522 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 13:40:40.451961 Loading segment from ROM address 0x4010001c
9447 13:40:40.452049 Entry Point 0x80000000
9448 13:40:40.455406 Loaded segments
9449 13:40:40.458783 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 13:40:40.466111 Jumping to boot code at 0x80000000(0xffe64000)
9451 13:40:40.472298 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 13:40:40.479148 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 13:40:40.486689 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 13:40:40.489716 Checking segment from ROM address 0x40100000
9455 13:40:40.493154 Checking segment from ROM address 0x4010001c
9456 13:40:40.496948 Loading segment from ROM address 0x40100000
9457 13:40:40.499924 code (compression=1)
9458 13:40:40.506514 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 13:40:40.516451 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 13:40:40.516536 using LZMA
9461 13:40:40.524895 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 13:40:40.532203 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 13:40:40.535304 Loading segment from ROM address 0x4010001c
9464 13:40:40.535388 Entry Point 0x54601000
9465 13:40:40.538740 Loaded segments
9466 13:40:40.541747 NOTICE: MT8192 bl31_setup
9467 13:40:40.548463 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 13:40:40.551635 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 13:40:40.555425 WARNING: region 0:
9470 13:40:40.558312 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 13:40:40.558410 WARNING: region 1:
9472 13:40:40.565318 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 13:40:40.568329 WARNING: region 2:
9474 13:40:40.572060 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 13:40:40.575313 WARNING: region 3:
9476 13:40:40.578999 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 13:40:40.581974 WARNING: region 4:
9478 13:40:40.585539 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 13:40:40.588397 WARNING: region 5:
9480 13:40:40.592068 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 13:40:40.595299 WARNING: region 6:
9482 13:40:40.599017 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 13:40:40.599100 WARNING: region 7:
9484 13:40:40.605599 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 13:40:40.612306 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 13:40:40.615457 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 13:40:40.618716 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 13:40:40.625879 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 13:40:40.628743 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 13:40:40.632515 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 13:40:40.639040 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 13:40:40.642015 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 13:40:40.645765 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 13:40:40.652437 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 13:40:40.655517 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 13:40:40.659403 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 13:40:40.666130 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 13:40:40.668870 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 13:40:40.675600 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 13:40:40.679417 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 13:40:40.682290 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 13:40:40.688988 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 13:40:40.693011 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 13:40:40.695806 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 13:40:40.702863 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 13:40:40.706300 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 13:40:40.712919 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 13:40:40.716471 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 13:40:40.719253 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 13:40:40.726062 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 13:40:40.729738 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 13:40:40.733401 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 13:40:40.739623 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 13:40:40.742779 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 13:40:40.749600 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 13:40:40.752875 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 13:40:40.756672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 13:40:40.759528 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 13:40:40.766424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 13:40:40.769600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 13:40:40.773264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 13:40:40.776899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 13:40:40.783366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 13:40:40.786536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 13:40:40.790161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 13:40:40.793230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 13:40:40.796946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 13:40:40.803196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 13:40:40.807046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 13:40:40.810012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 13:40:40.816937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 13:40:40.820306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 13:40:40.823773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 13:40:40.830127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 13:40:40.833557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 13:40:40.837226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 13:40:40.843838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 13:40:40.847117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 13:40:40.854097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 13:40:40.857136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 13:40:40.863768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 13:40:40.866942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 13:40:40.870195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 13:40:40.876937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 13:40:40.880302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 13:40:40.887547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 13:40:40.890390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 13:40:40.896961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 13:40:40.900784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 13:40:40.903882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 13:40:40.910815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 13:40:40.914351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 13:40:40.920942 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 13:40:40.923890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 13:40:40.927453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 13:40:40.934429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 13:40:40.937643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 13:40:40.943924 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 13:40:40.947784 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 13:40:40.954339 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 13:40:40.957678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 13:40:40.960983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 13:40:40.967853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 13:40:40.970965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 13:40:40.977781 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 13:40:40.980979 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 13:40:40.987342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 13:40:40.990973 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 13:40:40.994650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 13:40:41.000756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 13:40:41.004244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 13:40:41.011262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 13:40:41.014256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 13:40:41.020965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 13:40:41.024865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 13:40:41.028030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 13:40:41.034511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 13:40:41.038258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 13:40:41.044726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 13:40:41.048233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 13:40:41.051447 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 13:40:41.058185 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 13:40:41.061766 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 13:40:41.064749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 13:40:41.068264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 13:40:41.075262 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 13:40:41.078139 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 13:40:41.081756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 13:40:41.088503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 13:40:41.091646 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 13:40:41.098275 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 13:40:41.101917 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 13:40:41.105135 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 13:40:41.112061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 13:40:41.115646 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 13:40:41.122562 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 13:40:41.125404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 13:40:41.128520 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 13:40:41.135363 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 13:40:41.139181 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 13:40:41.142082 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 13:40:41.148641 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 13:40:41.152370 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 13:40:41.155406 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 13:40:41.159004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 13:40:41.165423 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 13:40:41.169180 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 13:40:41.172272 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 13:40:41.178954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 13:40:41.182537 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 13:40:41.185604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 13:40:41.192785 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 13:40:41.196014 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 13:40:41.199115 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 13:40:41.206019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 13:40:41.208911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 13:40:41.212709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 13:40:41.219364 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 13:40:41.223011 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 13:40:41.229715 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 13:40:41.232853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 13:40:41.236175 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 13:40:41.242652 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 13:40:41.246356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 13:40:41.252592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 13:40:41.256182 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 13:40:41.260019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 13:40:41.266320 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 13:40:41.269703 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 13:40:41.273225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 13:40:41.279646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 13:40:41.283216 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 13:40:41.286380 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 13:40:41.293348 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 13:40:41.297172 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 13:40:41.303691 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 13:40:41.306519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 13:40:41.310036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 13:40:41.317174 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 13:40:41.320112 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 13:40:41.323844 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 13:40:41.330073 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 13:40:41.333866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 13:40:41.339965 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 13:40:41.343400 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 13:40:41.347150 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 13:40:41.353424 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 13:40:41.356916 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 13:40:41.363100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 13:40:41.366924 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 13:40:41.370236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 13:40:41.376712 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 13:40:41.379997 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 13:40:41.386695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 13:40:41.390194 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 13:40:41.393225 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 13:40:41.399893 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 13:40:41.403336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 13:40:41.406591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 13:40:41.413491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 13:40:41.416645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 13:40:41.423450 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 13:40:41.426741 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 13:40:41.430340 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 13:40:41.436437 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 13:40:41.440143 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 13:40:41.443374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 13:40:41.449838 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 13:40:41.453162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 13:40:41.459744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 13:40:41.463544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 13:40:41.467237 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 13:40:41.473451 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 13:40:41.476812 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 13:40:41.483568 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 13:40:41.487162 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 13:40:41.493617 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 13:40:41.497109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 13:40:41.500347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 13:40:41.506733 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 13:40:41.510114 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 13:40:41.516850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 13:40:41.520462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 13:40:41.523393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 13:40:41.530354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 13:40:41.533538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 13:40:41.539995 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 13:40:41.543417 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 13:40:41.547026 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 13:40:41.553668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 13:40:41.556893 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 13:40:41.563570 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 13:40:41.567098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 13:40:41.570139 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 13:40:41.576836 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 13:40:41.580076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 13:40:41.587169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 13:40:41.590243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 13:40:41.593421 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 13:40:41.600544 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 13:40:41.603542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 13:40:41.610397 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 13:40:41.613586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 13:40:41.620677 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 13:40:41.623604 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 13:40:41.627239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 13:40:41.633429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 13:40:41.637191 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 13:40:41.644043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 13:40:41.647510 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 13:40:41.650792 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 13:40:41.657218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 13:40:41.660361 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 13:40:41.664043 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 13:40:41.670762 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 13:40:41.673837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 13:40:41.677370 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 13:40:41.680438 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 13:40:41.687183 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 13:40:41.690617 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 13:40:41.694245 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 13:40:41.700519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 13:40:41.704288 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 13:40:41.707342 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 13:40:41.714096 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 13:40:41.717391 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 13:40:41.723991 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 13:40:41.727120 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 13:40:41.730619 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 13:40:41.737306 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 13:40:41.740372 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 13:40:41.744263 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 13:40:41.750875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 13:40:41.753905 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 13:40:41.757162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 13:40:41.763690 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 13:40:41.767569 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 13:40:41.770855 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 13:40:41.777315 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 13:40:41.780997 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 13:40:41.787248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 13:40:41.790229 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 13:40:41.793790 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 13:40:41.800733 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 13:40:41.803684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 13:40:41.806921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 13:40:41.813612 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 13:40:41.817151 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 13:40:41.820664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 13:40:41.827268 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 13:40:41.830981 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 13:40:41.837385 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 13:40:41.840418 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 13:40:41.844182 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 13:40:41.847187 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 13:40:41.850218 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 13:40:41.857247 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 13:40:41.860759 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 13:40:41.863972 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 13:40:41.867325 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 13:40:41.874245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 13:40:41.877044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 13:40:41.880890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 13:40:41.883798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 13:40:41.890394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 13:40:41.894233 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 13:40:41.897201 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 13:40:41.903995 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 13:40:41.907232 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 13:40:41.914061 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 13:40:41.917108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 13:40:41.920967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 13:40:41.927590 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 13:40:41.930418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 13:40:41.937112 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 13:40:41.940544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 13:40:41.943817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 13:40:41.950496 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 13:40:41.953636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 13:40:41.960337 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 13:40:41.963941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 13:40:41.967144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 13:40:41.973930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 13:40:41.977422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 13:40:41.983600 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 13:40:41.987010 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 13:40:41.990566 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 13:40:41.997205 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 13:40:42.000457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 13:40:42.007219 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 13:40:42.010705 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 13:40:42.013916 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 13:40:42.020758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 13:40:42.024258 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 13:40:42.030610 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 13:40:42.034108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 13:40:42.037462 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 13:40:42.044133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 13:40:42.047214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 13:40:42.054058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 13:40:42.057725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 13:40:42.060859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 13:40:42.067434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 13:40:42.070500 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 13:40:42.077548 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 13:40:42.080575 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 13:40:42.084264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 13:40:42.090661 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 13:40:42.094206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 13:40:42.101087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 13:40:42.104539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 13:40:42.107412 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 13:40:42.114022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 13:40:42.117194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 13:40:42.124457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 13:40:42.127210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 13:40:42.130413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 13:40:42.137370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 13:40:42.140810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 13:40:42.147645 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 13:40:42.150617 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 13:40:42.154380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 13:40:42.161046 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 13:40:42.163997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 13:40:42.170664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 13:40:42.174328 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 13:40:42.177631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 13:40:42.184473 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 13:40:42.187410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 13:40:42.194100 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 13:40:42.197388 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 13:40:42.200919 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 13:40:42.207380 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 13:40:42.210912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 13:40:42.217382 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 13:40:42.220347 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 13:40:42.227344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 13:40:42.230404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 13:40:42.233860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 13:40:42.240727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 13:40:42.243955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 13:40:42.250838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 13:40:42.253939 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 13:40:42.260737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 13:40:42.263903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 13:40:42.267326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 13:40:42.273873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 13:40:42.277122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 13:40:42.284342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 13:40:42.287437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 13:40:42.294071 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 13:40:42.297269 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 13:40:42.300461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 13:40:42.307537 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 13:40:42.310687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 13:40:42.317891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 13:40:42.320581 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 13:40:42.324066 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 13:40:42.331185 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 13:40:42.334167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 13:40:42.340838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 13:40:42.343885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 13:40:42.350789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 13:40:42.354106 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 13:40:42.357426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 13:40:42.363930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 13:40:42.367150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 13:40:42.374255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 13:40:42.377540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 13:40:42.384192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 13:40:42.387239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 13:40:42.391115 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 13:40:42.397328 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 13:40:42.401093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 13:40:42.407259 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 13:40:42.411068 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 13:40:42.417545 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 13:40:42.420780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 13:40:42.424043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 13:40:42.430502 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 13:40:42.433994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 13:40:42.441099 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 13:40:42.444091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 13:40:42.450970 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 13:40:42.453953 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 13:40:42.457628 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 13:40:42.464237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 13:40:42.467669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 13:40:42.473996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 13:40:42.477610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 13:40:42.484062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 13:40:42.487197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 13:40:42.490881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 13:40:42.497210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 13:40:42.500756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 13:40:42.507531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 13:40:42.510437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 13:40:42.517279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 13:40:42.520408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 13:40:42.527622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 13:40:42.530580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 13:40:42.537503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 13:40:42.540571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 13:40:42.547447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 13:40:42.550863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 13:40:42.557291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 13:40:42.561213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 13:40:42.567392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 13:40:42.571034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 13:40:42.577487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 13:40:42.580789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 13:40:42.587338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 13:40:42.591120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 13:40:42.597504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 13:40:42.601325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 13:40:42.607457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 13:40:42.611193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 13:40:42.618166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 13:40:42.621125 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 13:40:42.621218 INFO: [APUAPC] vio 0
9921 13:40:42.628466 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 13:40:42.631786 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 13:40:42.634715 INFO: [APUAPC] D0_APC_0: 0x400510
9924 13:40:42.638306 INFO: [APUAPC] D0_APC_1: 0x0
9925 13:40:42.641860 INFO: [APUAPC] D0_APC_2: 0x1540
9926 13:40:42.644932 INFO: [APUAPC] D0_APC_3: 0x0
9927 13:40:42.648152 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 13:40:42.651668 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 13:40:42.654580 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 13:40:42.657963 INFO: [APUAPC] D1_APC_3: 0x0
9931 13:40:42.661460 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 13:40:42.665192 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 13:40:42.668281 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 13:40:42.671976 INFO: [APUAPC] D2_APC_3: 0x0
9935 13:40:42.675018 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 13:40:42.678099 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 13:40:42.681686 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 13:40:42.681766 INFO: [APUAPC] D3_APC_3: 0x0
9939 13:40:42.685098 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 13:40:42.691899 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 13:40:42.692012 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 13:40:42.694930 INFO: [APUAPC] D4_APC_3: 0x0
9943 13:40:42.698987 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 13:40:42.701514 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 13:40:42.705195 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 13:40:42.708658 INFO: [APUAPC] D5_APC_3: 0x0
9947 13:40:42.711921 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 13:40:42.714895 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 13:40:42.718754 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 13:40:42.721685 INFO: [APUAPC] D6_APC_3: 0x0
9951 13:40:42.725378 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 13:40:42.728526 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 13:40:42.731514 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 13:40:42.735295 INFO: [APUAPC] D7_APC_3: 0x0
9955 13:40:42.738351 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 13:40:42.741586 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 13:40:42.745282 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 13:40:42.748867 INFO: [APUAPC] D8_APC_3: 0x0
9959 13:40:42.751912 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 13:40:42.755213 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 13:40:42.758094 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 13:40:42.761893 INFO: [APUAPC] D9_APC_3: 0x0
9963 13:40:42.765099 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 13:40:42.768196 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 13:40:42.771580 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 13:40:42.775198 INFO: [APUAPC] D10_APC_3: 0x0
9967 13:40:42.778741 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 13:40:42.781764 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 13:40:42.784887 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 13:40:42.788628 INFO: [APUAPC] D11_APC_3: 0x0
9971 13:40:42.791585 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 13:40:42.795252 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 13:40:42.798494 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 13:40:42.801904 INFO: [APUAPC] D12_APC_3: 0x0
9975 13:40:42.805390 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 13:40:42.808609 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 13:40:42.811968 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 13:40:42.815096 INFO: [APUAPC] D13_APC_3: 0x0
9979 13:40:42.818799 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 13:40:42.821993 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 13:40:42.825117 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 13:40:42.828198 INFO: [APUAPC] D14_APC_3: 0x0
9983 13:40:42.831806 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 13:40:42.835525 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 13:40:42.838408 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 13:40:42.842191 INFO: [APUAPC] D15_APC_3: 0x0
9987 13:40:42.845369 INFO: [APUAPC] APC_CON: 0x4
9988 13:40:42.848389 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 13:40:42.848470 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 13:40:42.852124 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 13:40:42.855077 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 13:40:42.858725 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 13:40:42.861817 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 13:40:42.865058 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 13:40:42.868574 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 13:40:42.872213 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 13:40:42.875552 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 13:40:42.878461 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 13:40:42.878541 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 13:40:42.881606 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 13:40:42.884986 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 13:40:42.888698 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 13:40:42.891513 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 13:40:42.895199 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 13:40:42.898406 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 13:40:42.901982 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 13:40:42.905584 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 13:40:42.908224 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 13:40:42.912142 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 13:40:42.912222 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 13:40:42.914966 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 13:40:42.918508 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 13:40:42.922194 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 13:40:42.925083 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 13:40:42.928602 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 13:40:42.931884 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 13:40:42.934972 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 13:40:42.938633 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 13:40:42.941764 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 13:40:42.945505 INFO: [NOCDAPC] APC_CON: 0x4
10021 13:40:42.948741 INFO: [APUAPC] set_apusys_apc done
10022 13:40:42.951780 INFO: [DEVAPC] devapc_init done
10023 13:40:42.955263 INFO: GICv3 without legacy support detected.
10024 13:40:42.958506 INFO: ARM GICv3 driver initialized in EL3
10025 13:40:42.962017 INFO: Maximum SPI INTID supported: 639
10026 13:40:42.965269 INFO: BL31: Initializing runtime services
10027 13:40:42.971912 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 13:40:42.974941 INFO: SPM: enable CPC mode
10029 13:40:42.981936 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 13:40:42.985187 INFO: BL31: Preparing for EL3 exit to normal world
10031 13:40:42.988594 INFO: Entry point address = 0x80000000
10032 13:40:42.991879 INFO: SPSR = 0x8
10033 13:40:42.996291
10034 13:40:42.996382
10035 13:40:42.996448
10036 13:40:43.000074 Starting depthcharge on Spherion...
10037 13:40:43.000211
10038 13:40:43.000291 Wipe memory regions:
10039 13:40:43.000351
10040 13:40:43.001076 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 13:40:43.001176 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 13:40:43.001291 Setting prompt string to ['asurada:']
10043 13:40:43.001369 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 13:40:43.003191 [0x00000040000000, 0x00000054600000)
10045 13:40:43.125249
10046 13:40:43.125397 [0x00000054660000, 0x00000080000000)
10047 13:40:43.386093
10048 13:40:43.386258 [0x000000821a7280, 0x000000ffe64000)
10049 13:40:44.130682
10050 13:40:44.130832 [0x00000100000000, 0x00000240000000)
10051 13:40:46.021323
10052 13:40:46.024591 Initializing XHCI USB controller at 0x11200000.
10053 13:40:47.062134
10054 13:40:47.065314 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 13:40:47.065408
10056 13:40:47.065473
10057 13:40:47.065752 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 13:40:47.166112 asurada: tftpboot 192.168.201.1 14063090/tftp-deploy-u_fffaoi/kernel/image.itb 14063090/tftp-deploy-u_fffaoi/kernel/cmdline
10060 13:40:47.166274 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 13:40:47.166390 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 13:40:47.170475 tftpboot 192.168.201.1 14063090/tftp-deploy-u_fffaoi/kernel/image.itp-deploy-u_fffaoi/kernel/cmdline
10063 13:40:47.170590
10064 13:40:47.170655 Waiting for link
10065 13:40:47.330639
10066 13:40:47.330787 R8152: Initializing
10067 13:40:47.330864
10068 13:40:47.334436 Version 6 (ocp_data = 5c30)
10069 13:40:47.334522
10070 13:40:47.337365 R8152: Done initializing
10071 13:40:47.337436
10072 13:40:47.337496 Adding net device
10073 13:40:49.240685
10074 13:40:49.240851 done.
10075 13:40:49.240966
10076 13:40:49.241075 MAC: 00:24:32:30:78:52
10077 13:40:49.241138
10078 13:40:49.243930 Sending DHCP discover... done.
10079 13:40:49.244012
10080 13:40:58.197930 Waiting for reply... done.
10081 13:40:58.198074
10082 13:40:58.198145 Sending DHCP request... done.
10083 13:40:58.201735
10084 13:40:58.213738 Waiting for reply... done.
10085 13:40:58.213851
10086 13:40:58.213918 My ip is 192.168.201.14
10087 13:40:58.213979
10088 13:40:58.216901 The DHCP server ip is 192.168.201.1
10089 13:40:58.216990
10090 13:40:58.223718 TFTP server IP predefined by user: 192.168.201.1
10091 13:40:58.223803
10092 13:40:58.230179 Bootfile predefined by user: 14063090/tftp-deploy-u_fffaoi/kernel/image.itb
10093 13:40:58.230262
10094 13:40:58.230327 Sending tftp read request... done.
10095 13:40:58.233850
10096 13:40:58.237615 Waiting for the transfer...
10097 13:40:58.237699
10098 13:40:58.823521 00000000 ################################################################
10099 13:40:58.823668
10100 13:40:59.448689 00080000 ################################################################
10101 13:40:59.448824
10102 13:40:59.994390 00100000 ################################################################
10103 13:40:59.994529
10104 13:41:00.540796 00180000 ################################################################
10105 13:41:00.540959
10106 13:41:01.093142 00200000 ################################################################
10107 13:41:01.093296
10108 13:41:01.662311 00280000 ################################################################
10109 13:41:01.662474
10110 13:41:02.218495 00300000 ################################################################
10111 13:41:02.218648
10112 13:41:02.771912 00380000 ################################################################
10113 13:41:02.772053
10114 13:41:03.317274 00400000 ################################################################
10115 13:41:03.317482
10116 13:41:03.849146 00480000 ################################################################
10117 13:41:03.849364
10118 13:41:04.381738 00500000 ################################################################
10119 13:41:04.381924
10120 13:41:04.922409 00580000 ################################################################
10121 13:41:04.922633
10122 13:41:05.476021 00600000 ################################################################
10123 13:41:05.476164
10124 13:41:06.031031 00680000 ################################################################
10125 13:41:06.031209
10126 13:41:06.581531 00700000 ################################################################
10127 13:41:06.581709
10128 13:41:07.140788 00780000 ################################################################
10129 13:41:07.140935
10130 13:41:07.749839 00800000 ################################################################
10131 13:41:07.750029
10132 13:41:08.291848 00880000 ################################################################
10133 13:41:08.291990
10134 13:41:08.833861 00900000 ################################################################
10135 13:41:08.834033
10136 13:41:09.387543 00980000 ################################################################
10137 13:41:09.387689
10138 13:41:09.942357 00a00000 ################################################################
10139 13:41:09.942503
10140 13:41:10.517642 00a80000 ################################################################
10141 13:41:10.517784
10142 13:41:11.072792 00b00000 ################################################################
10143 13:41:11.072936
10144 13:41:11.656701 00b80000 ################################################################
10145 13:41:11.656848
10146 13:41:12.237839 00c00000 ################################################################
10147 13:41:12.237989
10148 13:41:12.825370 00c80000 ################################################################
10149 13:41:12.825516
10150 13:41:13.377685 00d00000 ################################################################
10151 13:41:13.377839
10152 13:41:13.932702 00d80000 ################################################################
10153 13:41:13.932878
10154 13:41:14.486372 00e00000 ################################################################
10155 13:41:14.486515
10156 13:41:15.048264 00e80000 ################################################################
10157 13:41:15.048419
10158 13:41:15.617754 00f00000 ################################################################
10159 13:41:15.617889
10160 13:41:16.183371 00f80000 ################################################################
10161 13:41:16.183522
10162 13:41:16.744867 01000000 ################################################################
10163 13:41:16.745057
10164 13:41:17.271270 01080000 ################################################################
10165 13:41:17.271447
10166 13:41:17.810092 01100000 ################################################################
10167 13:41:17.810276
10168 13:41:18.367118 01180000 ################################################################
10169 13:41:18.367256
10170 13:41:18.918832 01200000 ################################################################
10171 13:41:18.918965
10172 13:41:19.463160 01280000 ################################################################
10173 13:41:19.463316
10174 13:41:19.996660 01300000 ################################################################
10175 13:41:19.996815
10176 13:41:20.529179 01380000 ################################################################
10177 13:41:20.529338
10178 13:41:21.059983 01400000 ################################################################
10179 13:41:21.060123
10180 13:41:21.602234 01480000 ################################################################
10181 13:41:21.602371
10182 13:41:22.148906 01500000 ################################################################
10183 13:41:22.149083
10184 13:41:22.693923 01580000 ################################################################
10185 13:41:22.694061
10186 13:41:23.217311 01600000 ################################################################
10187 13:41:23.217446
10188 13:41:23.775078 01680000 ################################################################
10189 13:41:23.775215
10190 13:41:24.338416 01700000 ################################################################
10191 13:41:24.338556
10192 13:41:24.877032 01780000 ################################################################
10193 13:41:24.877168
10194 13:41:25.518205 01800000 ################################################################
10195 13:41:25.518714
10196 13:41:26.234192 01880000 ################################################################
10197 13:41:26.234709
10198 13:41:26.930161 01900000 ################################################################
10199 13:41:26.930666
10200 13:41:27.631790 01980000 ################################################################
10201 13:41:27.632312
10202 13:41:28.336367 01a00000 ################################################################
10203 13:41:28.336864
10204 13:41:29.035186 01a80000 ################################################################
10205 13:41:29.035721
10206 13:41:29.743450 01b00000 ################################################################
10207 13:41:29.743938
10208 13:41:30.433088 01b80000 ################################################################
10209 13:41:30.433611
10210 13:41:31.157218 01c00000 ################################################################
10211 13:41:31.157738
10212 13:41:31.873938 01c80000 ################################################################
10213 13:41:31.874464
10214 13:41:32.573116 01d00000 ################################################################
10215 13:41:32.573629
10216 13:41:33.240760 01d80000 ################################################################
10217 13:41:33.241360
10218 13:41:33.841779 01e00000 ################################################################
10219 13:41:33.842318
10220 13:41:34.456911 01e80000 ################################################################
10221 13:41:34.457084
10222 13:41:35.051325 01f00000 ################################################################
10223 13:41:35.051487
10224 13:41:35.626094 01f80000 ################################################################
10225 13:41:35.626257
10226 13:41:36.254175 02000000 ################################################################
10227 13:41:36.254676
10228 13:41:36.887157 02080000 ################################################################
10229 13:41:36.887288
10230 13:41:37.438394 02100000 ################################################################
10231 13:41:37.438990
10232 13:41:38.109799 02180000 ################################################################
10233 13:41:38.109987
10234 13:41:38.790191 02200000 ################################################################
10235 13:41:38.790323
10236 13:41:39.478835 02280000 ################################################################
10237 13:41:39.479388
10238 13:41:40.049262 02300000 ################################################################
10239 13:41:40.049399
10240 13:41:40.596848 02380000 ################################################################
10241 13:41:40.596995
10242 13:41:41.144456 02400000 ################################################################
10243 13:41:41.144599
10244 13:41:41.705726 02480000 ################################################################
10245 13:41:41.705856
10246 13:41:42.249491 02500000 ################################################################
10247 13:41:42.249635
10248 13:41:42.796928 02580000 ################################################################
10249 13:41:42.797102
10250 13:41:43.347047 02600000 ################################################################
10251 13:41:43.347205
10252 13:41:43.882589 02680000 ################################################################
10253 13:41:43.882720
10254 13:41:44.402916 02700000 ################################################################
10255 13:41:44.403046
10256 13:41:44.937424 02780000 ################################################################
10257 13:41:44.937564
10258 13:41:45.468528 02800000 ################################################################
10259 13:41:45.468660
10260 13:41:45.996522 02880000 ################################################################
10261 13:41:45.996650
10262 13:41:46.520639 02900000 ################################################################
10263 13:41:46.520776
10264 13:41:47.097273 02980000 ################################################################
10265 13:41:47.097410
10266 13:41:47.626180 02a00000 ################################################################
10267 13:41:47.626326
10268 13:41:48.175629 02a80000 ################################################################
10269 13:41:48.175775
10270 13:41:48.715084 02b00000 ################################################################
10271 13:41:48.715239
10272 13:41:49.261507 02b80000 ################################################################
10273 13:41:49.261659
10274 13:41:49.793791 02c00000 ################################################################
10275 13:41:49.793941
10276 13:41:50.318834 02c80000 ################################################################
10277 13:41:50.318985
10278 13:41:50.864970 02d00000 ################################################################
10279 13:41:50.865162
10280 13:41:51.400609 02d80000 ################################################################
10281 13:41:51.400790
10282 13:41:51.926298 02e00000 ################################################################
10283 13:41:51.926453
10284 13:41:52.457430 02e80000 ################################################################
10285 13:41:52.457583
10286 13:41:52.982192 02f00000 ################################################################
10287 13:41:52.982338
10288 13:41:53.500865 02f80000 ################################################################
10289 13:41:53.501045
10290 13:41:54.034490 03000000 ################################################################
10291 13:41:54.034651
10292 13:41:54.573852 03080000 ################################################################
10293 13:41:54.574009
10294 13:41:55.141151 03100000 ################################################################
10295 13:41:55.141328
10296 13:41:55.681876 03180000 ################################################################
10297 13:41:55.682017
10298 13:41:56.222772 03200000 ################################################################
10299 13:41:56.222909
10300 13:41:56.761266 03280000 ################################################################
10301 13:41:56.761428
10302 13:41:57.324570 03300000 ################################################################
10303 13:41:57.324707
10304 13:41:57.698415 03380000 ######################################## done.
10305 13:41:57.698655
10306 13:41:57.701553 The bootfile was 54321698 bytes long.
10307 13:41:57.701743
10308 13:41:57.704702 Sending tftp read request... done.
10309 13:41:57.704871
10310 13:41:57.708140 Waiting for the transfer...
10311 13:41:57.708305
10312 13:41:57.708442 00000000 # done.
10313 13:41:57.708578
10314 13:41:57.714853 Command line loaded dynamically from TFTP file: 14063090/tftp-deploy-u_fffaoi/kernel/cmdline
10315 13:41:57.718455
10316 13:41:57.728279 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10317 13:41:57.731456
10318 13:41:57.731635 Loading FIT.
10319 13:41:57.731777
10320 13:41:57.734662 Image ramdisk-1 has 41211104 bytes.
10321 13:41:57.734840
10322 13:41:57.738049 Image fdt-1 has 47258 bytes.
10323 13:41:57.738484
10324 13:41:57.741983 Image kernel-1 has 13061303 bytes.
10325 13:41:57.742334
10326 13:41:57.748100 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10327 13:41:57.748457
10328 13:41:57.767823 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10329 13:41:57.768330
10330 13:41:57.771182 Choosing best match conf-1 for compat google,spherion-rev2.
10331 13:41:57.776076
10332 13:41:57.780719 Connected to device vid:did:rid of 1ae0:0028:00
10333 13:41:57.789261
10334 13:41:57.792316 tpm_get_response: command 0x17b, return code 0x0
10335 13:41:57.792753
10336 13:41:57.798747 ec_init: CrosEC protocol v3 supported (256, 248)
10337 13:41:57.799101
10338 13:41:57.802623 tpm_cleanup: add release locality here.
10339 13:41:57.802978
10340 13:41:57.805903 Shutting down all USB controllers.
10341 13:41:57.806256
10342 13:41:57.808903 Removing current net device
10343 13:41:57.809297
10344 13:41:57.812623 Exiting depthcharge with code 4 at timestamp: 104186051
10345 13:41:57.813064
10346 13:41:57.815622 LZMA decompressing kernel-1 to 0x821a6718
10347 13:41:57.815975
10348 13:41:57.822285 LZMA decompressing kernel-1 to 0x40000000
10349 13:41:59.433116
10350 13:41:59.433636 jumping to kernel
10351 13:41:59.435499 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10352 13:41:59.435981 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10353 13:41:59.436353 Setting prompt string to ['Linux version [0-9]']
10354 13:41:59.436692 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10355 13:41:59.437073 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10356 13:41:59.515958
10357 13:41:59.519023 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10358 13:41:59.522647 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10359 13:41:59.523225 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10360 13:41:59.523586 Setting prompt string to []
10361 13:41:59.523964 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10362 13:41:59.524330 Using line separator: #'\n'#
10363 13:41:59.524629 No login prompt set.
10364 13:41:59.524939 Parsing kernel messages
10365 13:41:59.525256 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10366 13:41:59.525752 [login-action] Waiting for messages, (timeout 00:03:09)
10367 13:41:59.526086 Waiting using forced prompt support (timeout 00:01:34)
10368 13:41:59.542693 [ 0.000000] Linux version 6.1.91-cip21 (KernelCI@build-j208563-arm64-gcc-10-defconfig-arm64-chromebook-j5dkg) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024
10369 13:41:59.545810 [ 0.000000] random: crng init done
10370 13:41:59.552261 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10371 13:41:59.552765 [ 0.000000] efi: UEFI not found.
10372 13:41:59.562559 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10373 13:41:59.568934 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10374 13:41:59.579004 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10375 13:41:59.589154 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10376 13:41:59.595814 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10377 13:41:59.599169 [ 0.000000] printk: bootconsole [mtk8250] enabled
10378 13:41:59.608030 [ 0.000000] NUMA: No NUMA configuration found
10379 13:41:59.614119 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10380 13:41:59.621132 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10381 13:41:59.621656 [ 0.000000] Zone ranges:
10382 13:41:59.627858 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10383 13:41:59.631029 [ 0.000000] DMA32 empty
10384 13:41:59.637594 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10385 13:41:59.641038 [ 0.000000] Movable zone start for each node
10386 13:41:59.644117 [ 0.000000] Early memory node ranges
10387 13:41:59.650869 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10388 13:41:59.657360 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10389 13:41:59.664075 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10390 13:41:59.670588 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10391 13:41:59.677251 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10392 13:41:59.684207 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10393 13:41:59.740256 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10394 13:41:59.746930 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10395 13:41:59.753295 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10396 13:41:59.756792 [ 0.000000] psci: probing for conduit method from DT.
10397 13:41:59.763148 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10398 13:41:59.766760 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10399 13:41:59.773543 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10400 13:41:59.777145 [ 0.000000] psci: SMC Calling Convention v1.2
10401 13:41:59.784197 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10402 13:41:59.786915 [ 0.000000] Detected VIPT I-cache on CPU0
10403 13:41:59.793399 [ 0.000000] CPU features: detected: GIC system register CPU interface
10404 13:41:59.799944 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10405 13:41:59.806641 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10406 13:41:59.813799 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10407 13:41:59.820907 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10408 13:41:59.826756 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10409 13:41:59.833713 [ 0.000000] alternatives: applying boot alternatives
10410 13:41:59.837423 [ 0.000000] Fallback order for Node 0: 0
10411 13:41:59.843971 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10412 13:41:59.847218 [ 0.000000] Policy zone: Normal
10413 13:41:59.863541 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10414 13:41:59.873539 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10415 13:41:59.884875 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10416 13:41:59.894764 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10417 13:41:59.901271 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10418 13:41:59.904830 <6>[ 0.000000] software IO TLB: area num 8.
10419 13:41:59.961830 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10420 13:42:00.110957 <6>[ 0.000000] Memory: 7923944K/8385536K available (18112K kernel code, 4120K rwdata, 22500K rodata, 8512K init, 616K bss, 428824K reserved, 32768K cma-reserved)
10421 13:42:00.117856 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10422 13:42:00.124159 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10423 13:42:00.127732 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10424 13:42:00.133952 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10425 13:42:00.140722 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10426 13:42:00.143911 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10427 13:42:00.154139 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10428 13:42:00.161028 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10429 13:42:00.163931 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10430 13:42:00.172034 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10431 13:42:00.174873 <6>[ 0.000000] GICv3: 608 SPIs implemented
10432 13:42:00.181373 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10433 13:42:00.185153 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10434 13:42:00.188267 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10435 13:42:00.198186 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10436 13:42:00.208095 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10437 13:42:00.221128 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10438 13:42:00.227841 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10439 13:42:00.237044 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10440 13:42:00.250302 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10441 13:42:00.257305 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10442 13:42:00.263754 <6>[ 0.009177] Console: colour dummy device 80x25
10443 13:42:00.273614 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10444 13:42:00.277115 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10445 13:42:00.283620 <6>[ 0.029214] LSM: Security Framework initializing
10446 13:42:00.290388 <6>[ 0.034152] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 13:42:00.300495 <6>[ 0.041965] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 13:42:00.307055 <6>[ 0.051389] cblist_init_generic: Setting adjustable number of callback queues.
10449 13:42:00.313586 <6>[ 0.058834] cblist_init_generic: Setting shift to 3 and lim to 1.
10450 13:42:00.320719 <6>[ 0.065173] cblist_init_generic: Setting adjustable number of callback queues.
10451 13:42:00.327079 <6>[ 0.072600] cblist_init_generic: Setting shift to 3 and lim to 1.
10452 13:42:00.334053 <6>[ 0.078999] rcu: Hierarchical SRCU implementation.
10453 13:42:00.340906 <6>[ 0.084015] rcu: Max phase no-delay instances is 1000.
10454 13:42:00.343614 <6>[ 0.091035] EFI services will not be available.
10455 13:42:00.350354 <6>[ 0.095992] smp: Bringing up secondary CPUs ...
10456 13:42:00.357542 <6>[ 0.101041] Detected VIPT I-cache on CPU1
10457 13:42:00.364557 <6>[ 0.101110] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10458 13:42:00.371266 <6>[ 0.101140] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10459 13:42:00.375090 <6>[ 0.101475] Detected VIPT I-cache on CPU2
10460 13:42:00.381180 <6>[ 0.101524] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10461 13:42:00.391070 <6>[ 0.101540] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10462 13:42:00.394238 <6>[ 0.101794] Detected VIPT I-cache on CPU3
10463 13:42:00.401412 <6>[ 0.101841] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10464 13:42:00.408086 <6>[ 0.101854] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10465 13:42:00.410907 <6>[ 0.102159] CPU features: detected: Spectre-v4
10466 13:42:00.417657 <6>[ 0.102165] CPU features: detected: Spectre-BHB
10467 13:42:00.420674 <6>[ 0.102170] Detected PIPT I-cache on CPU4
10468 13:42:00.427488 <6>[ 0.102227] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10469 13:42:00.434472 <6>[ 0.102243] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10470 13:42:00.441283 <6>[ 0.102537] Detected PIPT I-cache on CPU5
10471 13:42:00.447251 <6>[ 0.102601] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10472 13:42:00.454001 <6>[ 0.102617] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10473 13:42:00.457694 <6>[ 0.102897] Detected PIPT I-cache on CPU6
10474 13:42:00.463924 <6>[ 0.102965] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10475 13:42:00.470772 <6>[ 0.102981] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10476 13:42:00.473944 <6>[ 0.103279] Detected PIPT I-cache on CPU7
10477 13:42:00.484499 <6>[ 0.103345] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10478 13:42:00.490547 <6>[ 0.103361] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10479 13:42:00.494141 <6>[ 0.103408] smp: Brought up 1 node, 8 CPUs
10480 13:42:00.497586 <6>[ 0.244676] SMP: Total of 8 processors activated.
10481 13:42:00.504697 <6>[ 0.249597] CPU features: detected: 32-bit EL0 Support
10482 13:42:00.514067 <6>[ 0.254959] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10483 13:42:00.520619 <6>[ 0.263814] CPU features: detected: Common not Private translations
10484 13:42:00.523881 <6>[ 0.270290] CPU features: detected: CRC32 instructions
10485 13:42:00.531152 <6>[ 0.275675] CPU features: detected: RCpc load-acquire (LDAPR)
10486 13:42:00.537497 <6>[ 0.281635] CPU features: detected: LSE atomic instructions
10487 13:42:00.543658 <6>[ 0.287452] CPU features: detected: Privileged Access Never
10488 13:42:00.547362 <6>[ 0.293231] CPU features: detected: RAS Extension Support
10489 13:42:00.553697 <6>[ 0.298875] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10490 13:42:00.560906 <6>[ 0.306139] CPU: All CPU(s) started at EL2
10491 13:42:00.567354 <6>[ 0.310483] alternatives: applying system-wide alternatives
10492 13:42:00.575802 <6>[ 0.321330] devtmpfs: initialized
10493 13:42:00.587541 <6>[ 0.330097] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10494 13:42:00.597735 <6>[ 0.340059] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10495 13:42:00.604697 <6>[ 0.348069] pinctrl core: initialized pinctrl subsystem
10496 13:42:00.607774 <6>[ 0.354729] DMI not present or invalid.
10497 13:42:00.614120 <6>[ 0.359085] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10498 13:42:00.621099 <6>[ 0.365931] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10499 13:42:00.631290 <6>[ 0.373514] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10500 13:42:00.638000 <6>[ 0.381731] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10501 13:42:00.644609 <6>[ 0.389971] audit: initializing netlink subsys (disabled)
10502 13:42:00.654537 <5>[ 0.395664] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10503 13:42:00.657718 <6>[ 0.396365] thermal_sys: Registered thermal governor 'step_wise'
10504 13:42:00.664646 <6>[ 0.403627] thermal_sys: Registered thermal governor 'power_allocator'
10505 13:42:00.671084 <6>[ 0.409884] cpuidle: using governor menu
10506 13:42:00.674294 <6>[ 0.420846] NET: Registered PF_QIPCRTR protocol family
10507 13:42:00.681194 <6>[ 0.426294] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10508 13:42:00.687817 <6>[ 0.433396] ASID allocator initialised with 32768 entries
10509 13:42:00.694168 <6>[ 0.439970] Serial: AMBA PL011 UART driver
10510 13:42:00.702889 <4>[ 0.448785] Trying to register duplicate clock ID: 134
10511 13:42:00.760895 <6>[ 0.510066] KASLR enabled
10512 13:42:00.775520 <6>[ 0.517787] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10513 13:42:00.781863 <6>[ 0.524803] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10514 13:42:00.788706 <6>[ 0.531292] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10515 13:42:00.795199 <6>[ 0.538295] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10516 13:42:00.801829 <6>[ 0.544782] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10517 13:42:00.808550 <6>[ 0.551787] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10518 13:42:00.815142 <6>[ 0.558274] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10519 13:42:00.822154 <6>[ 0.565278] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10520 13:42:00.825311 <6>[ 0.572786] ACPI: Interpreter disabled.
10521 13:42:00.833551 <6>[ 0.579198] iommu: Default domain type: Translated
10522 13:42:00.840270 <6>[ 0.584311] iommu: DMA domain TLB invalidation policy: strict mode
10523 13:42:00.843732 <5>[ 0.590967] SCSI subsystem initialized
10524 13:42:00.850011 <6>[ 0.595135] usbcore: registered new interface driver usbfs
10525 13:42:00.856813 <6>[ 0.600866] usbcore: registered new interface driver hub
10526 13:42:00.859929 <6>[ 0.606414] usbcore: registered new device driver usb
10527 13:42:00.866714 <6>[ 0.612510] pps_core: LinuxPPS API ver. 1 registered
10528 13:42:00.876497 <6>[ 0.617703] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10529 13:42:00.879958 <6>[ 0.627046] PTP clock support registered
10530 13:42:00.883232 <6>[ 0.631286] EDAC MC: Ver: 3.0.0
10531 13:42:00.890694 <6>[ 0.636437] FPGA manager framework
10532 13:42:00.897062 <6>[ 0.640124] Advanced Linux Sound Architecture Driver Initialized.
10533 13:42:00.900736 <6>[ 0.646898] vgaarb: loaded
10534 13:42:00.904224 <6>[ 0.650051] clocksource: Switched to clocksource arch_sys_counter
10535 13:42:00.910763 <5>[ 0.656490] VFS: Disk quotas dquot_6.6.0
10536 13:42:00.917556 <6>[ 0.660670] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10537 13:42:00.920450 <6>[ 0.667858] pnp: PnP ACPI: disabled
10538 13:42:00.928902 <6>[ 0.674523] NET: Registered PF_INET protocol family
10539 13:42:00.935742 <6>[ 0.680116] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10540 13:42:00.950203 <6>[ 0.692446] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10541 13:42:00.960240 <6>[ 0.701260] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10542 13:42:00.967143 <6>[ 0.709233] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10543 13:42:00.973285 <6>[ 0.717934] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10544 13:42:00.985420 <6>[ 0.727677] TCP: Hash tables configured (established 65536 bind 65536)
10545 13:42:00.992246 <6>[ 0.734543] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 13:42:00.998953 <6>[ 0.741741] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10547 13:42:01.005615 <6>[ 0.749443] NET: Registered PF_UNIX/PF_LOCAL protocol family
10548 13:42:01.011888 <6>[ 0.755595] RPC: Registered named UNIX socket transport module.
10549 13:42:01.015546 <6>[ 0.761747] RPC: Registered udp transport module.
10550 13:42:01.022356 <6>[ 0.766678] RPC: Registered tcp transport module.
10551 13:42:01.028196 <6>[ 0.771610] RPC: Registered tcp NFSv4.1 backchannel transport module.
10552 13:42:01.032084 <6>[ 0.778272] PCI: CLS 0 bytes, default 64
10553 13:42:01.035182 <6>[ 0.782611] Unpacking initramfs...
10554 13:42:01.059728 <6>[ 0.802161] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10555 13:42:01.069805 <6>[ 0.810816] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10556 13:42:01.072808 <6>[ 0.819660] kvm [1]: IPA Size Limit: 40 bits
10557 13:42:01.079467 <6>[ 0.824186] kvm [1]: GICv3: no GICV resource entry
10558 13:42:01.083349 <6>[ 0.829206] kvm [1]: disabling GICv2 emulation
10559 13:42:01.090015 <6>[ 0.833894] kvm [1]: GIC system register CPU interface enabled
10560 13:42:01.093270 <6>[ 0.840054] kvm [1]: vgic interrupt IRQ18
10561 13:42:01.099804 <6>[ 0.844410] kvm [1]: VHE mode initialized successfully
10562 13:42:01.106556 <5>[ 0.850845] Initialise system trusted keyrings
10563 13:42:01.113035 <6>[ 0.855704] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10564 13:42:01.119809 <6>[ 0.865713] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10565 13:42:01.126969 <5>[ 0.872104] NFS: Registering the id_resolver key type
10566 13:42:01.129587 <5>[ 0.877408] Key type id_resolver registered
10567 13:42:01.137026 <5>[ 0.881821] Key type id_legacy registered
10568 13:42:01.143501 <6>[ 0.886113] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10569 13:42:01.150372 <6>[ 0.893037] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10570 13:42:01.156772 <6>[ 0.900774] 9p: Installing v9fs 9p2000 file system support
10571 13:42:01.192767 <5>[ 0.938447] Key type asymmetric registered
10572 13:42:01.195799 <5>[ 0.942777] Asymmetric key parser 'x509' registered
10573 13:42:01.206155 <6>[ 0.947922] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10574 13:42:01.209558 <6>[ 0.955539] io scheduler mq-deadline registered
10575 13:42:01.213218 <6>[ 0.960328] io scheduler kyber registered
10576 13:42:01.231640 <6>[ 0.977299] EINJ: ACPI disabled.
10577 13:42:01.264469 <4>[ 1.003423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 13:42:01.274025 <4>[ 1.014063] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 13:42:01.289788 <6>[ 1.035241] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10580 13:42:01.297540 <6>[ 1.043328] printk: console [ttyS0] disabled
10581 13:42:01.325668 <6>[ 1.067955] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10582 13:42:01.332411 <6>[ 1.077429] printk: console [ttyS0] enabled
10583 13:42:01.335792 <6>[ 1.077429] printk: console [ttyS0] enabled
10584 13:42:01.338961 <6>[ 1.086322] printk: bootconsole [mtk8250] disabled
10585 13:42:01.345865 <6>[ 1.086322] printk: bootconsole [mtk8250] disabled
10586 13:42:01.352555 <6>[ 1.097393] SuperH (H)SCI(F) driver initialized
10587 13:42:01.355634 <6>[ 1.102663] msm_serial: driver initialized
10588 13:42:01.369076 <6>[ 1.111639] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10589 13:42:01.379730 <6>[ 1.120185] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10590 13:42:01.386162 <6>[ 1.128727] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10591 13:42:01.395994 <6>[ 1.137354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10592 13:42:01.402055 <6>[ 1.146067] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10593 13:42:01.412422 <6>[ 1.154790] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10594 13:42:01.422635 <6>[ 1.163334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10595 13:42:01.428946 <6>[ 1.172141] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10596 13:42:01.439428 <6>[ 1.180689] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10597 13:42:01.450198 <6>[ 1.196331] loop: module loaded
10598 13:42:01.457534 <6>[ 1.202442] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10599 13:42:01.480645 <4>[ 1.225896] mtk-pmic-keys: Failed to locate of_node [id: -1]
10600 13:42:01.487467 <6>[ 1.232689] megasas: 07.719.03.00-rc1
10601 13:42:01.496426 <6>[ 1.242352] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10602 13:42:01.503761 <6>[ 1.249435] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10603 13:42:01.520717 <6>[ 1.266259] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10604 13:42:01.577245 <6>[ 1.316388] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10605 13:42:02.767836 <6>[ 2.513834] Freeing initrd memory: 40240K
10606 13:42:02.779760 <6>[ 2.525532] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10607 13:42:02.790349 <6>[ 2.536661] tun: Universal TUN/TAP device driver, 1.6
10608 13:42:02.793609 <6>[ 2.542741] thunder_xcv, ver 1.0
10609 13:42:02.797290 <6>[ 2.546249] thunder_bgx, ver 1.0
10610 13:42:02.800639 <6>[ 2.549738] nicpf, ver 1.0
10611 13:42:02.811135 <6>[ 2.553774] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10612 13:42:02.814483 <6>[ 2.561250] hns3: Copyright (c) 2017 Huawei Corporation.
10613 13:42:02.821291 <6>[ 2.566844] hclge is initializing
10614 13:42:02.824328 <6>[ 2.570424] e1000: Intel(R) PRO/1000 Network Driver
10615 13:42:02.831264 <6>[ 2.575554] e1000: Copyright (c) 1999-2006 Intel Corporation.
10616 13:42:02.834120 <6>[ 2.581567] e1000e: Intel(R) PRO/1000 Network Driver
10617 13:42:02.840639 <6>[ 2.586782] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10618 13:42:02.847564 <6>[ 2.592966] igb: Intel(R) Gigabit Ethernet Network Driver
10619 13:42:02.854418 <6>[ 2.598616] igb: Copyright (c) 2007-2014 Intel Corporation.
10620 13:42:02.860775 <6>[ 2.604453] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10621 13:42:02.867450 <6>[ 2.610971] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10622 13:42:02.870607 <6>[ 2.617433] sky2: driver version 1.30
10623 13:42:02.877394 <6>[ 2.622356] usbcore: registered new device driver r8152-cfgselector
10624 13:42:02.883818 <6>[ 2.628889] usbcore: registered new interface driver r8152
10625 13:42:02.890755 <6>[ 2.634711] VFIO - User Level meta-driver version: 0.3
10626 13:42:02.897397 <6>[ 2.642971] usbcore: registered new interface driver usb-storage
10627 13:42:02.903950 <6>[ 2.649412] usbcore: registered new device driver onboard-usb-hub
10628 13:42:02.912852 <6>[ 2.658579] mt6397-rtc mt6359-rtc: registered as rtc0
10629 13:42:02.922551 <6>[ 2.664038] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-28T13:42:03 UTC (1716903723)
10630 13:42:02.926024 <6>[ 2.673602] i2c_dev: i2c /dev entries driver
10631 13:42:02.942508 <6>[ 2.685398] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10632 13:42:02.949310 <4>[ 2.694128] cpu cpu0: supply cpu not found, using dummy regulator
10633 13:42:02.955848 <4>[ 2.700551] cpu cpu1: supply cpu not found, using dummy regulator
10634 13:42:02.962909 <4>[ 2.706952] cpu cpu2: supply cpu not found, using dummy regulator
10635 13:42:02.969640 <4>[ 2.713352] cpu cpu3: supply cpu not found, using dummy regulator
10636 13:42:02.975877 <4>[ 2.719769] cpu cpu4: supply cpu not found, using dummy regulator
10637 13:42:02.982828 <4>[ 2.726170] cpu cpu5: supply cpu not found, using dummy regulator
10638 13:42:02.989140 <4>[ 2.732567] cpu cpu6: supply cpu not found, using dummy regulator
10639 13:42:02.995764 <4>[ 2.738958] cpu cpu7: supply cpu not found, using dummy regulator
10640 13:42:03.014729 <6>[ 2.760616] cpu cpu0: EM: created perf domain
10641 13:42:03.017854 <6>[ 2.765559] cpu cpu4: EM: created perf domain
10642 13:42:03.025229 <6>[ 2.771174] sdhci: Secure Digital Host Controller Interface driver
10643 13:42:03.031898 <6>[ 2.777608] sdhci: Copyright(c) Pierre Ossman
10644 13:42:03.038900 <6>[ 2.782563] Synopsys Designware Multimedia Card Interface Driver
10645 13:42:03.045058 <6>[ 2.789182] sdhci-pltfm: SDHCI platform and OF driver helper
10646 13:42:03.048547 <6>[ 2.789276] mmc0: CQHCI version 5.10
10647 13:42:03.054892 <6>[ 2.799245] ledtrig-cpu: registered to indicate activity on CPUs
10648 13:42:03.061410 <6>[ 2.806058] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10649 13:42:03.068437 <6>[ 2.813114] usbcore: registered new interface driver usbhid
10650 13:42:03.071382 <6>[ 2.818935] usbhid: USB HID core driver
10651 13:42:03.077873 <6>[ 2.823130] spi_master spi0: will run message pump with realtime priority
10652 13:42:03.120821 <6>[ 2.860018] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10653 13:42:03.139364 <6>[ 2.874821] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10654 13:42:03.142276 <6>[ 2.889479] mmc0: Command Queue Engine enabled
10655 13:42:03.149104 <6>[ 2.894226] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10656 13:42:03.155553 <6>[ 2.900941] cros-ec-spi spi0.0: Chrome EC device registered
10657 13:42:03.159336 <6>[ 2.901498] mmcblk0: mmc0:0001 DA4128 116 GiB
10658 13:42:03.171203 <6>[ 2.917126] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10659 13:42:03.178135 <6>[ 2.924230] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10660 13:42:03.184866 <6>[ 2.930129] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10661 13:42:03.191698 <6>[ 2.936181] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 13:42:03.206054 <6>[ 2.948907] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10663 13:42:03.213766 <6>[ 2.959493] NET: Registered PF_PACKET protocol family
10664 13:42:03.217192 <6>[ 2.964888] 9pnet: Installing 9P2000 support
10665 13:42:03.223934 <5>[ 2.969455] Key type dns_resolver registered
10666 13:42:03.226995 <6>[ 2.974442] registered taskstats version 1
10667 13:42:03.233881 <5>[ 2.978828] Loading compiled-in X.509 certificates
10668 13:42:03.264936 <4>[ 3.003970] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 13:42:03.274735 <4>[ 3.014753] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 13:42:03.289738 <6>[ 3.035620] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10671 13:42:03.296474 <6>[ 3.042599] xhci-mtk 11200000.usb: xHCI Host Controller
10672 13:42:03.303175 <6>[ 3.048129] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10673 13:42:03.313630 <6>[ 3.055999] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10674 13:42:03.319729 <6>[ 3.065452] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10675 13:42:03.326920 <6>[ 3.071629] xhci-mtk 11200000.usb: xHCI Host Controller
10676 13:42:03.333087 <6>[ 3.077132] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10677 13:42:03.340111 <6>[ 3.084789] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10678 13:42:03.346456 <6>[ 3.092583] hub 1-0:1.0: USB hub found
10679 13:42:03.349635 <6>[ 3.096606] hub 1-0:1.0: 1 port detected
10680 13:42:03.360123 <6>[ 3.100887] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10681 13:42:03.363310 <6>[ 3.109608] hub 2-0:1.0: USB hub found
10682 13:42:03.366327 <6>[ 3.113630] hub 2-0:1.0: 1 port detected
10683 13:42:03.374071 <6>[ 3.120332] mtk-msdc 11f70000.mmc: Got CD GPIO
10684 13:42:03.387010 <6>[ 3.129821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10685 13:42:03.394063 <6>[ 3.137858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10686 13:42:03.403497 <4>[ 3.145763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10687 13:42:03.413311 <6>[ 3.155297] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10688 13:42:03.420003 <6>[ 3.163374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10689 13:42:03.426642 <6>[ 3.171415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10690 13:42:03.436640 <6>[ 3.179334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10691 13:42:03.443926 <6>[ 3.187151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10692 13:42:03.453698 <6>[ 3.194971] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10693 13:42:03.463585 <6>[ 3.205366] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10694 13:42:03.469882 <6>[ 3.213723] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10695 13:42:03.479799 <6>[ 3.222069] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10696 13:42:03.487090 <6>[ 3.230407] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10697 13:42:03.497016 <6>[ 3.238744] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10698 13:42:03.503424 <6>[ 3.247083] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10699 13:42:03.513085 <6>[ 3.255420] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10700 13:42:03.519992 <6>[ 3.263758] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10701 13:42:03.529670 <6>[ 3.272097] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10702 13:42:03.536291 <6>[ 3.280434] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10703 13:42:03.546528 <6>[ 3.288771] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10704 13:42:03.552932 <6>[ 3.297109] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10705 13:42:03.563247 <6>[ 3.305446] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10706 13:42:03.569518 <6>[ 3.313784] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10707 13:42:03.580118 <6>[ 3.322121] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10708 13:42:03.586233 <6>[ 3.330836] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10709 13:42:03.592969 <6>[ 3.337978] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10710 13:42:03.600045 <6>[ 3.344736] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10711 13:42:03.606180 <6>[ 3.351497] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10712 13:42:03.613186 <6>[ 3.358476] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10713 13:42:03.622932 <6>[ 3.365320] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10714 13:42:03.633075 <6>[ 3.374453] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10715 13:42:03.642946 <6>[ 3.383572] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10716 13:42:03.652863 <6>[ 3.392866] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10717 13:42:03.659482 <6>[ 3.402334] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10718 13:42:03.669535 <6>[ 3.411800] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10719 13:42:03.679882 <6>[ 3.420922] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10720 13:42:03.689490 <6>[ 3.430388] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10721 13:42:03.699229 <6>[ 3.439508] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10722 13:42:03.709379 <6>[ 3.448806] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10723 13:42:03.719462 <6>[ 3.458967] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10724 13:42:03.729219 <6>[ 3.470634] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10725 13:42:03.767619 <6>[ 3.510331] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10726 13:42:03.921281 <6>[ 3.667425] hub 1-1:1.0: USB hub found
10727 13:42:03.924727 <6>[ 3.671876] hub 1-1:1.0: 4 ports detected
10728 13:42:03.933790 <6>[ 3.679885] hub 1-1:1.0: USB hub found
10729 13:42:03.937295 <6>[ 3.684197] hub 1-1:1.0: 4 ports detected
10730 13:42:04.047744 <6>[ 3.790756] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10731 13:42:04.075904 <6>[ 3.821858] hub 2-1:1.0: USB hub found
10732 13:42:04.079152 <6>[ 3.826433] hub 2-1:1.0: 3 ports detected
10733 13:42:04.089316 <6>[ 3.835315] hub 2-1:1.0: USB hub found
10734 13:42:04.092907 <6>[ 3.839784] hub 2-1:1.0: 3 ports detected
10735 13:42:04.259723 <6>[ 4.002368] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10736 13:42:04.391984 <6>[ 4.138200] hub 1-1.4:1.0: USB hub found
10737 13:42:04.395104 <6>[ 4.142862] hub 1-1.4:1.0: 2 ports detected
10738 13:42:04.405392 <6>[ 4.151386] hub 1-1.4:1.0: USB hub found
10739 13:42:04.408681 <6>[ 4.156017] hub 1-1.4:1.0: 2 ports detected
10740 13:42:04.475611 <6>[ 4.218578] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10741 13:42:04.583675 <6>[ 4.326995] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10742 13:42:04.620307 <4>[ 4.363560] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10743 13:42:04.630624 <4>[ 4.372647] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10744 13:42:04.665470 <6>[ 4.411821] r8152 2-1.3:1.0 eth0: v1.12.13
10745 13:42:04.707311 <6>[ 4.450369] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10746 13:42:04.898914 <6>[ 4.642348] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10747 13:42:06.260149 <6>[ 6.006804] r8152 2-1.3:1.0 eth0: carrier on
10748 13:42:06.303606 <5>[ 6.034144] Sending DHCP requests ., OK
10749 13:42:06.310105 <6>[ 6.054391] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10750 13:42:06.313411 <6>[ 6.062676] IP-Config: Complete:
10751 13:42:06.326741 <6>[ 6.066174] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10752 13:42:06.333445 <6>[ 6.076896] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10753 13:42:06.340039 <6>[ 6.085514] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10754 13:42:06.346825 <6>[ 6.085523] nameserver0=192.168.201.1
10755 13:42:06.350154 <6>[ 6.097671] clk: Disabling unused clocks
10756 13:42:06.353584 <6>[ 6.103167] ALSA device list:
10757 13:42:06.356595 <6>[ 6.106432] No soundcards found.
10758 13:42:06.367609 <6>[ 6.114142] Freeing unused kernel memory: 8512K
10759 13:42:06.370604 <6>[ 6.119015] Run /init as init process
10760 13:42:06.400915 <6>[ 6.147712] NET: Registered PF_INET6 protocol family
10761 13:42:06.407985 <6>[ 6.154581] Segment Routing with IPv6
10762 13:42:06.411061 <6>[ 6.158536] In-situ OAM (IOAM) with IPv6
10763 13:42:06.451726 <30>[ 6.171775] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10764 13:42:06.458440 <30>[ 6.204839] systemd[1]: Detected architecture arm64.
10765 13:42:06.458536
10766 13:42:06.464556 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10767 13:42:06.464638
10768 13:42:06.479407 <30>[ 6.226428] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10769 13:42:06.605307 <30>[ 6.348735] systemd[1]: Queued start job for default target graphical.target.
10770 13:42:06.652271 <30>[ 6.395773] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10771 13:42:06.659040 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10772 13:42:06.679433 <30>[ 6.422791] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10773 13:42:06.689021 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10774 13:42:06.708300 <30>[ 6.451973] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10775 13:42:06.718196 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10776 13:42:06.736474 <30>[ 6.479766] systemd[1]: Created slice user.slice - User and Session Slice.
10777 13:42:06.742826 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10778 13:42:06.766991 <30>[ 6.507050] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10779 13:42:06.773663 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10780 13:42:06.794068 <30>[ 6.534510] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10781 13:42:06.801108 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10782 13:42:06.829387 <30>[ 6.562909] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10783 13:42:06.839198 <30>[ 6.582801] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10784 13:42:06.845754 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10785 13:42:06.862947 <30>[ 6.606740] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10786 13:42:06.869676 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10787 13:42:06.891218 <30>[ 6.634856] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10788 13:42:06.901372 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10789 13:42:06.915841 <30>[ 6.662858] systemd[1]: Reached target paths.target - Path Units.
10790 13:42:06.925857 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10791 13:42:06.943036 <30>[ 6.686809] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10792 13:42:06.949784 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10793 13:42:06.963862 <30>[ 6.710335] systemd[1]: Reached target slices.target - Slice Units.
10794 13:42:06.973636 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10795 13:42:06.987814 <30>[ 6.734828] systemd[1]: Reached target swap.target - Swaps.
10796 13:42:06.994941 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10797 13:42:07.015663 <30>[ 6.758824] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10798 13:42:07.025698 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10799 13:42:07.043484 <30>[ 6.786804] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10800 13:42:07.053306 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10801 13:42:07.073111 <30>[ 6.816266] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10802 13:42:07.082967 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10803 13:42:07.099377 <30>[ 6.843042] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10804 13:42:07.109828 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10805 13:42:07.127612 <30>[ 6.870978] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10806 13:42:07.134299 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10807 13:42:07.151663 <30>[ 6.895019] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10808 13:42:07.161469 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10809 13:42:07.180381 <30>[ 6.923729] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10810 13:42:07.189955 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10811 13:42:07.208300 <30>[ 6.951489] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10812 13:42:07.217595 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10813 13:42:07.271220 <30>[ 7.014671] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10814 13:42:07.277465 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10815 13:42:07.299170 <30>[ 7.042461] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10816 13:42:07.305276 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10817 13:42:07.325109 <30>[ 7.068442] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10818 13:42:07.331662 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10819 13:42:07.357406 <30>[ 7.094510] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10820 13:42:07.371097 <30>[ 7.114295] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10821 13:42:07.380330 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10822 13:42:07.403972 <30>[ 7.147827] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10823 13:42:07.410595 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10824 13:42:07.459721 <30>[ 7.203107] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10825 13:42:07.469661 Startin<6>[ 7.212556] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10826 13:42:07.475847 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10827 13:42:07.500789 <30>[ 7.243968] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10828 13:42:07.507258 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10829 13:42:07.532221 <30>[ 7.275862] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10830 13:42:07.542104 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10831 13:42:07.563974 <30>[ 7.307803] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10832 13:42:07.571034 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10833 13:42:07.615261 <30>[ 7.358693] systemd[1]: Starting systemd-journald.service - Journal Service...
10834 13:42:07.621555 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10835 13:42:07.641657 <30>[ 7.385483] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10836 13:42:07.648385 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10837 13:42:07.672891 <30>[ 7.413321] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10838 13:42:07.679601 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10839 13:42:07.703238 <30>[ 7.446709] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10840 13:42:07.712880 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10841 13:42:07.755546 <30>[ 7.499246] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10842 13:42:07.762122 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10843 13:42:07.786892 <30>[ 7.530210] systemd[1]: Started systemd-journald.service - Journal Service.
10844 13:42:07.793069 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10845 13:42:07.813123 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10846 13:42:07.831275 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10847 13:42:07.847177 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10848 13:42:07.863970 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10849 13:42:07.884851 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10850 13:42:07.904511 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10851 13:42:07.925031 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10852 13:42:07.945090 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10853 13:42:07.964837 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10854 13:42:07.984400 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10855 13:42:08.008790 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10856 13:42:08.033188 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10857 13:42:08.040466 See 'systemctl status systemd-remount-fs.service' for details.
10858 13:42:08.050130 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10859 13:42:08.073758 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10860 13:42:08.128022 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10861 13:42:08.152450 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10862 13:42:08.163645 <46>[ 7.907413] systemd-journald[192]: Received client request to flush runtime journal.
10863 13:42:08.180420 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10864 13:42:08.204636 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10865 13:42:08.228128 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10866 13:42:08.257062 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10867 13:42:08.275159 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10868 13:42:08.292075 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10869 13:42:08.312087 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10870 13:42:08.331792 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10871 13:42:08.380080 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10872 13:42:08.401433 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10873 13:42:08.418856 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10874 13:42:08.438519 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10875 13:42:08.487386 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10876 13:42:08.513215 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10877 13:42:08.542524 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10878 13:42:08.583518 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10879 13:42:08.605473 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10880 13:42:08.625173 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10881 13:42:08.671226 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10882 13:42:08.685948 <46>[ 8.432815] systemd-journald[192]: Time jumped backwards, rotating.
10883 13:42:08.701972 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10884 13:42:08.746195 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10885 13:42:08.846176 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10886 13:42:08.863538 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10887 13:42:08.883347 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10888 13:42:08.900403 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10889 13:42:08.919847 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10890 13:42:08.937017 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10891 13:42:08.958813 [[0;32m OK [0m] Reached targ<6>[ 8.700588] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10892 13:42:08.968588 et [0;1;39msock<6>[ 8.709947] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10893 13:42:08.975219 ets.target[0m -<3>[ 8.712519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 13:42:08.985287 <6>[ 8.720034] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10895 13:42:08.988743 Socket Units.
10896 13:42:08.995935 <3>[ 8.729430] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 13:42:08.996017
10898 13:42:09.001890 <3>[ 8.747449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 13:42:09.019224 <3>[ 8.762881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 13:42:09.025542 <6>[ 8.762916] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10901 13:42:09.035755 <3>[ 8.771036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 13:42:09.042402 <3>[ 8.786483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 13:42:09.048882 <6>[ 8.790201] remoteproc remoteproc0: scp is available
10904 13:42:09.055546 <3>[ 8.794577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 13:42:09.062247 <3>[ 8.794581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 13:42:09.069122 <6>[ 8.799876] remoteproc remoteproc0: powering up scp
10907 13:42:09.075904 <3>[ 8.810296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 13:42:09.082693 <6>[ 8.810496] mc: Linux media interface: v0.10
10909 13:42:09.089012 <6>[ 8.816016] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10910 13:42:09.099221 <3>[ 8.826450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 13:42:09.105989 <4>[ 8.828031] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10912 13:42:09.112391 <6>[ 8.829198] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10913 13:42:09.118979 <3>[ 8.833701] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 13:42:09.126035 <6>[ 8.846070] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10915 13:42:09.136011 <4>[ 8.846111] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10916 13:42:09.142645 <3>[ 8.850259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 13:42:09.152325 <3>[ 8.852404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 13:42:09.158798 <6>[ 8.868686] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10919 13:42:09.162429 <6>[ 8.869523] videodev: Linux video capture interface: v2.00
10920 13:42:09.172227 <3>[ 8.871429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 13:42:09.178728 <3>[ 8.871436] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 13:42:09.185655 <6>[ 8.879187] pci_bus 0000:00: root bus resource [bus 00-ff]
10923 13:42:09.192324 <3>[ 8.886412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 13:42:09.202337 <3>[ 8.886421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 13:42:09.209160 <4>[ 8.887633] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10926 13:42:09.215556 <4>[ 8.887633] Fallback method does not support PEC.
10927 13:42:09.222324 <3>[ 8.891695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 13:42:09.229457 <6>[ 8.896956] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10929 13:42:09.239372 <6>[ 8.926711] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10930 13:42:09.249621 <6>[ 8.931905] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10931 13:42:09.259410 <6>[ 8.938621] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10932 13:42:09.266278 <6>[ 8.945833] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10933 13:42:09.275972 <6>[ 8.958258] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10934 13:42:09.283027 <6>[ 8.963562] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10935 13:42:09.289291 <6>[ 8.967466] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10936 13:42:09.299584 <6>[ 8.970340] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10937 13:42:09.302582 <6>[ 8.970406] pci 0000:00:00.0: supports D1 D2
10938 13:42:09.309635 <6>[ 8.970408] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10939 13:42:09.319443 <6>[ 8.971309] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10940 13:42:09.322851 <6>[ 8.971390] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10941 13:42:09.332410 <6>[ 8.971415] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10942 13:42:09.339367 <6>[ 8.971432] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10943 13:42:09.346039 <6>[ 8.971447] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10944 13:42:09.352390 <6>[ 8.971550] pci 0000:01:00.0: supports D1 D2
10945 13:42:09.359537 <6>[ 8.971552] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10946 13:42:09.365921 <6>[ 8.982151] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10947 13:42:09.369749 <6>[ 8.982685] remoteproc remoteproc0: remote processor scp is now up
10948 13:42:09.380676 <3>[ 8.984887] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 13:42:09.387126 <6>[ 8.992781] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10950 13:42:09.397551 <6>[ 9.017131] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10951 13:42:09.404524 <6>[ 9.017949] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10952 13:42:09.407486 <6>[ 9.018823] Bluetooth: Core ver 2.22
10953 13:42:09.415264 <6>[ 9.018895] NET: Registered PF_BLUETOOTH protocol family
10954 13:42:09.422012 <6>[ 9.018898] Bluetooth: HCI device and connection manager initialized
10955 13:42:09.425215 <6>[ 9.018914] Bluetooth: HCI socket layer initialized
10956 13:42:09.431935 <6>[ 9.018921] Bluetooth: L2CAP socket layer initialized
10957 13:42:09.434997 <6>[ 9.018935] Bluetooth: SCO socket layer initialized
10958 13:42:09.445505 <6>[ 9.032145] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10959 13:42:09.452258 <6>[ 9.034305] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10960 13:42:09.459024 <6>[ 9.055746] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10961 13:42:09.465471 <6>[ 9.061675] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10962 13:42:09.475459 <6>[ 9.061688] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10963 13:42:09.486060 <6>[ 9.071374] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10964 13:42:09.493477 <6>[ 9.076201] pci 0000:00:00.0: PCI bridge to [bus 01]
10965 13:42:09.499552 <6>[ 9.077118] usbcore: registered new interface driver btusb
10966 13:42:09.506231 <6>[ 9.077249] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10967 13:42:09.516367 <4>[ 9.077812] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10968 13:42:09.522955 <3>[ 9.077828] Bluetooth: hci0: Failed to load firmware file (-2)
10969 13:42:09.526500 <3>[ 9.077833] Bluetooth: hci0: Failed to set up firmware (-2)
10970 13:42:09.537052 <4>[ 9.077842] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10971 13:42:09.543570 <6>[ 9.084526] usbcore: registered new interface driver uvcvideo
10972 13:42:09.553295 <6>[ 9.091143] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10973 13:42:09.557040 <6>[ 9.091330] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10974 13:42:09.567300 <3>[ 9.136469] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 13:42:09.573687 <3>[ 9.137177] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10976 13:42:09.580569 <6>[ 9.140715] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10977 13:42:09.590635 <3>[ 9.143534] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 13:42:09.597818 <3>[ 9.144423] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10979 13:42:09.607484 <3>[ 9.167025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 13:42:09.611668 <6>[ 9.172934] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10981 13:42:09.622002 <3>[ 9.197600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 13:42:09.628859 <5>[ 9.214801] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10983 13:42:09.638947 <3>[ 9.241010] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 13:42:09.645303 <5>[ 9.264335] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10985 13:42:09.655615 <3>[ 9.288013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 13:42:09.662479 <5>[ 9.290516] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10987 13:42:09.672692 <3>[ 9.317219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 13:42:09.679740 <4>[ 9.319351] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10989 13:42:09.686004 <6>[ 9.432282] cfg80211: failed to load regulatory.db
10990 13:42:09.692571 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10991 13:42:09.715345 [[0;32m OK [<6>[ 9.459461] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10992 13:42:09.722113 0m] Reached targ<6>[ 9.468218] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10993 13:42:09.728489 et [0;1;39mbasic.target[0m - Basic System.
10994 13:42:09.748988 <6>[ 9.496232] mt7921e 0000:01:00.0: ASIC revision: 79610010
10995 13:42:09.779873 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10996 13:42:09.808273 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10997 13:42:09.827902 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10998 13:42:09.849908 [[0;32m OK [<6>[ 9.594455] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10999 13:42:09.853536 <6>[ 9.594455]
11000 13:42:09.859630 0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11001 13:42:09.930995 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11002 13:42:09.954794 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11003 13:42:09.975261 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11004 13:42:09.995905 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11005 13:42:10.020027 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11006 13:42:10.068581 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11007 13:42:10.093033 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11008 13:42:10.122970 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness <6>[ 9.864620] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11009 13:42:10.125885 of leds:white:kbd_backlight.
11010 13:42:10.145721 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11011 13:42:10.200455 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11012 13:42:10.225882 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11013 13:42:10.243797 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11014 13:42:10.259176 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11015 13:42:10.279601 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11016 13:42:10.336848 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11017 13:42:10.360688 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11018 13:42:10.381171 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11019 13:42:10.415779 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11020 13:42:10.467946
11021 13:42:10.471357 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11022 13:42:10.471466
11023 13:42:10.474643 debian-bookworm-arm64 login: root (automatic login)
11024 13:42:10.474747
11025 13:42:10.487048 Linux debian-bookworm-arm64 6.1.91-cip21 #1 SMP PREEMPT Tue May 28 13:24:21 UTC 2024 aarch64
11026 13:42:10.487178
11027 13:42:10.493721 The programs included with the Debian GNU/Linux system are free software;
11028 13:42:10.500305 the exact distribution terms for each program are described in the
11029 13:42:10.503619 individual files in /usr/share/doc/*/copyright.
11030 13:42:10.503725
11031 13:42:10.510369 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11032 13:42:10.513355 permitted by applicable law.
11033 13:42:10.513866 Matched prompt #10: / #
11035 13:42:10.514196 Setting prompt string to ['/ #']
11036 13:42:10.514326 end: 2.2.5.1 login-action (duration 00:00:11) [common]
11038 13:42:10.514644 end: 2.2.5 auto-login-action (duration 00:00:11) [common]
11039 13:42:10.514779 start: 2.2.6 expect-shell-connection (timeout 00:02:58) [common]
11040 13:42:10.514887 Setting prompt string to ['/ #']
11041 13:42:10.514987 Forcing a shell prompt, looking for ['/ #']
11043 13:42:10.565266 / #
11044 13:42:10.565444 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11045 13:42:10.565553 Waiting using forced prompt support (timeout 00:02:30)
11046 13:42:10.570151
11047 13:42:10.570467 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11048 13:42:10.570614 start: 2.2.7 export-device-env (timeout 00:02:58) [common]
11049 13:42:10.570739 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11050 13:42:10.570835 end: 2.2 depthcharge-retry (duration 00:02:02) [common]
11051 13:42:10.570919 end: 2 depthcharge-action (duration 00:02:02) [common]
11052 13:42:10.571013 start: 3 lava-test-retry (timeout 00:07:36) [common]
11053 13:42:10.571098 start: 3.1 lava-test-shell (timeout 00:07:36) [common]
11054 13:42:10.571172 Using namespace: common
11056 13:42:10.671488 / # #
11057 13:42:10.671636 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11058 13:42:10.676264 #
11059 13:42:10.676519 Using /lava-14063090
11061 13:42:10.776881 / # export SHELL=/bin/sh
11062 13:42:10.782716 export SHELL=/bin/sh
11064 13:42:10.883206 / # . /lava-14063090/environment
11065 13:42:10.888527 . /lava-14063090/environment
11067 13:42:10.989036 / # /lava-14063090/bin/lava-test-runner /lava-14063090/0
11068 13:42:10.989362 Test shell timeout: 10s (minimum of the action and connection timeout)
11069 13:42:10.989954 /lava-14063090/bin/lava-test-runner /lava-14063090/0<6>[ 10.734356] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11070 13:42:10.994325
11071 13:42:11.037111 + export TESTRUN_ID=0_v4l2-compliance-uvc
11072 13:42:11.037229 + cd /lava-14063090/0/tests/0_v4l2-compliance-uvc
11073 13:42:11.037296 + cat uuid
11074 13:42:11.037357 + UUID=14063090_1.5.2.3.1
11075 13:42:11.037415 + set +x
11076 13:42:11.037474 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14063090_1.5.2.3.1>
11077 13:42:11.037532 + /usr/bin/v4l2-parser.sh -d uvcvideo
11078 13:42:11.037778 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14063090_1.5.2.3.1
11079 13:42:11.037846 Starting test lava.0_v4l2-compliance-uvc (14063090_1.5.2.3.1)
11080 13:42:11.037922 Skipping test definition patterns.
11081 13:42:11.040939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11082 13:42:11.041040 device: /dev/video0
11083 13:42:11.041267 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11085 13:42:17.542047 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11086 13:42:17.552841 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11087 13:42:17.560984
11088 13:42:17.573613 Compliance test for uvcvideo device /dev/video0:
11089 13:42:17.581966
11090 13:42:17.596837 Driver Info:
11091 13:42:17.608421 Driver name : uvcvideo
11092 13:42:17.621559 Card type : HD User Facing: HD User Facing
11093 13:42:17.632619 Bus info : usb-11200000.usb-1.4.1
11094 13:42:17.640028 Driver version : 6.1.91
11095 13:42:17.651393 Capabilities : 0x84a00001
11096 13:42:17.665119 Metadata Capture
11097 13:42:17.676988 Streaming
11098 13:42:17.690215 Extended Pix Format
11099 13:42:17.701759 Device Capabilities
11100 13:42:17.713417 Device Caps : 0x04200001
11101 13:42:17.726392 Streaming
11102 13:42:17.740217 Extended Pix Format
11103 13:42:17.751169 Media Driver Info:
11104 13:42:17.760904 Driver name : uvcvideo
11105 13:42:17.776375 Model : HD User Facing: HD User Facing
11106 13:42:17.784527 Serial : 200901010001
11107 13:42:17.799114 Bus info : usb-11200000.usb-1.4.1
11108 13:42:17.808906 Media version : 6.1.91
11109 13:42:17.824963 Hardware revision: 0x00009758 (38744)
11110 13:42:17.832502 Driver version : 6.1.91
11111 13:42:17.842242 Interface Info:
11112 13:42:17.858067 <LAVA_SIGNAL_TESTSET START Interface-Info>
11113 13:42:17.858201 ID : 0x03000002
11114 13:42:17.858537 Received signal: <TESTSET> START Interface-Info
11115 13:42:17.858634 Starting test_set Interface-Info
11116 13:42:17.868217 Type : V4L Video
11117 13:42:17.878258 Entity Info:
11118 13:42:17.888720 <LAVA_SIGNAL_TESTSET STOP>
11119 13:42:17.889015 Received signal: <TESTSET> STOP
11120 13:42:17.889131 Closing test_set Interface-Info
11121 13:42:17.898650 <LAVA_SIGNAL_TESTSET START Entity-Info>
11122 13:42:17.898945 Received signal: <TESTSET> START Entity-Info
11123 13:42:17.899055 Starting test_set Entity-Info
11124 13:42:17.901560 ID : 0x00000001 (1)
11125 13:42:17.915623 Name : HD User Facing: HD User Facing
11126 13:42:17.923481 Function : V4L2 I/O
11127 13:42:17.933244 Flags : default
11128 13:42:17.943571 Pad 0x01000007 : 0: Sink
11129 13:42:17.964382 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11130 13:42:17.968690
11131 13:42:17.979345 Required ioctls:
11132 13:42:17.990660 <LAVA_SIGNAL_TESTSET STOP>
11133 13:42:17.990913 Received signal: <TESTSET> STOP
11134 13:42:17.990981 Closing test_set Entity-Info
11135 13:42:17.999926 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11136 13:42:18.000170 Received signal: <TESTSET> START Required-ioctls
11137 13:42:18.000239 Starting test_set Required-ioctls
11138 13:42:18.003131 test MC information (see 'Media Driver Info' above): OK
11139 13:42:18.029380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11140 13:42:18.029633 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11142 13:42:18.032427 test VIDIOC_QUERYCAP: OK
11143 13:42:18.050912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11144 13:42:18.051162 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11146 13:42:18.054615 test invalid ioctls: OK
11147 13:42:18.075562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11148 13:42:18.075644
11149 13:42:18.075883 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11151 13:42:18.085968 Allow for multiple opens:
11152 13:42:18.093147 <LAVA_SIGNAL_TESTSET STOP>
11153 13:42:18.093427 Received signal: <TESTSET> STOP
11154 13:42:18.093521 Closing test_set Required-ioctls
11155 13:42:18.102245 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11156 13:42:18.102496 Received signal: <TESTSET> START Allow-for-multiple-opens
11157 13:42:18.102567 Starting test_set Allow-for-multiple-opens
11158 13:42:18.105241 test second /dev/video0 open: OK
11159 13:42:18.130416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11160 13:42:18.130667 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11162 13:42:18.133819 test VIDIOC_QUERYCAP: OK
11163 13:42:18.153377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11164 13:42:18.153627 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11166 13:42:18.156517 test VIDIOC_G/S_PRIORITY: OK
11167 13:42:18.177850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11168 13:42:18.178130 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11170 13:42:18.180895 test for unlimited opens: OK
11171 13:42:18.202991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11172 13:42:18.203087
11173 13:42:18.203325 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11175 13:42:18.216597 Debug ioctls:
11176 13:42:18.223860 <LAVA_SIGNAL_TESTSET STOP>
11177 13:42:18.224128 Received signal: <TESTSET> STOP
11178 13:42:18.224205 Closing test_set Allow-for-multiple-opens
11179 13:42:18.233903 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11180 13:42:18.234158 Received signal: <TESTSET> START Debug-ioctls
11181 13:42:18.234233 Starting test_set Debug-ioctls
11182 13:42:18.237183 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11183 13:42:18.264558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11184 13:42:18.264813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11186 13:42:18.270905 test VIDIOC_LOG_STATUS: OK (Not Supported)
11187 13:42:18.291187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11188 13:42:18.291271
11189 13:42:18.291525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11191 13:42:18.300759 Input ioctls:
11192 13:42:18.307874 <LAVA_SIGNAL_TESTSET STOP>
11193 13:42:18.308129 Received signal: <TESTSET> STOP
11194 13:42:18.308202 Closing test_set Debug-ioctls
11195 13:42:18.317619 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11196 13:42:18.317872 Received signal: <TESTSET> START Input-ioctls
11197 13:42:18.317945 Starting test_set Input-ioctls
11198 13:42:18.321112 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11199 13:42:18.346030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11200 13:42:18.346282 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11202 13:42:18.349376 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11203 13:42:18.367389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11204 13:42:18.367640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11206 13:42:18.373883 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11207 13:42:18.393624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11208 13:42:18.393880 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11210 13:42:18.400006 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11211 13:42:18.418754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11212 13:42:18.419028 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11214 13:42:18.421669 test VIDIOC_G/S/ENUMINPUT: OK
11215 13:42:18.442697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11216 13:42:18.442977 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11218 13:42:18.446045 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11219 13:42:18.469755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11220 13:42:18.470042 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11222 13:42:18.473245 Inputs: 1 Audio Inputs: 0 Tuners: 0
11223 13:42:18.480869
11224 13:42:18.501933 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11225 13:42:18.524389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11226 13:42:18.524679 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11228 13:42:18.531123 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11229 13:42:18.550827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11230 13:42:18.551092 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11232 13:42:18.557377 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11233 13:42:18.576909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11234 13:42:18.577218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11236 13:42:18.583306 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11237 13:42:18.602456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11238 13:42:18.602756 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11240 13:42:18.609253 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11241 13:42:18.629933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11242 13:42:18.630035
11243 13:42:18.630310 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11245 13:42:18.649315 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11246 13:42:18.670948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11247 13:42:18.671254 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11249 13:42:18.677715 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11250 13:42:18.703271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11251 13:42:18.703575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11253 13:42:18.706220 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11254 13:42:18.724683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11255 13:42:18.724950 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11257 13:42:18.727636 test VIDIOC_G/S_EDID: OK (Not Supported)
11258 13:42:18.750047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11259 13:42:18.750143
11260 13:42:18.750382 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11262 13:42:18.761788 Control ioctls (Input 0):
11263 13:42:18.773175 <LAVA_SIGNAL_TESTSET STOP>
11264 13:42:18.773434 Received signal: <TESTSET> STOP
11265 13:42:18.773507 Closing test_set Input-ioctls
11266 13:42:18.783175 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11267 13:42:18.783431 Received signal: <TESTSET> START Control-ioctls-Input-0
11268 13:42:18.783500 Starting test_set Control-ioctls-Input-0
11269 13:42:18.786013 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11270 13:42:18.816227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11271 13:42:18.816374 test VIDIOC_QUERYCTRL: OK
11272 13:42:18.816648 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11274 13:42:18.841888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11275 13:42:18.842192 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11277 13:42:18.844961 test VIDIOC_G/S_CTRL: OK
11278 13:42:18.866894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11279 13:42:18.867196 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11281 13:42:18.869894 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11282 13:42:18.892607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11283 13:42:18.892918 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11285 13:42:18.899096 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11286 13:42:18.922277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11287 13:42:18.922592 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11289 13:42:18.925473 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11290 13:42:18.944443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11291 13:42:18.944765 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11293 13:42:18.948086 Standard Controls: 16 Private Controls: 0
11294 13:42:18.955378
11295 13:42:18.967767 Format ioctls (Input 0):
11296 13:42:18.974969 <LAVA_SIGNAL_TESTSET STOP>
11297 13:42:18.975278 Received signal: <TESTSET> STOP
11298 13:42:18.975360 Closing test_set Control-ioctls-Input-0
11299 13:42:18.984538 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11300 13:42:18.984829 Received signal: <TESTSET> START Format-ioctls-Input-0
11301 13:42:18.984932 Starting test_set Format-ioctls-Input-0
11302 13:42:18.987461 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11303 13:42:19.015306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11304 13:42:19.015641 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11306 13:42:19.018951 test VIDIOC_G/S_PARM: OK
11307 13:42:19.034625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11308 13:42:19.034949 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11310 13:42:19.038060 test VIDIOC_G_FBUF: OK (Not Supported)
11311 13:42:19.063448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11312 13:42:19.063774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11314 13:42:19.066627 test VIDIOC_G_FMT: OK
11315 13:42:19.087567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11316 13:42:19.087889 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11318 13:42:19.090549 test VIDIOC_TRY_FMT: OK
11319 13:42:19.113314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11320 13:42:19.113644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11322 13:42:19.120232 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11323 13:42:19.123855 test VIDIOC_S_FMT: OK
11324 13:42:19.147580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11325 13:42:19.147895 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11327 13:42:19.151173 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11328 13:42:19.175494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11329 13:42:19.175816 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11331 13:42:19.178821 test Cropping: OK (Not Supported)
11332 13:42:19.205268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11333 13:42:19.205595 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11335 13:42:19.208281 test Composing: OK (Not Supported)
11336 13:42:19.232130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11337 13:42:19.232453 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11339 13:42:19.235233 test Scaling: OK (Not Supported)
11340 13:42:19.256179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11341 13:42:19.256322
11342 13:42:19.256563 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11344 13:42:19.268461 Codec ioctls (Input 0):
11345 13:42:19.280250 <LAVA_SIGNAL_TESTSET STOP>
11346 13:42:19.280510 Received signal: <TESTSET> STOP
11347 13:42:19.280581 Closing test_set Format-ioctls-Input-0
11348 13:42:19.289928 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11349 13:42:19.290183 Received signal: <TESTSET> START Codec-ioctls-Input-0
11350 13:42:19.290251 Starting test_set Codec-ioctls-Input-0
11351 13:42:19.293136 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11352 13:42:19.319803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11353 13:42:19.320128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11355 13:42:19.326320 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11356 13:42:19.348666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11357 13:42:19.348983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11359 13:42:19.355403 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11360 13:42:19.373384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11361 13:42:19.373511
11362 13:42:19.373752 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11364 13:42:19.387748 Buffer ioctls (Input 0):
11365 13:42:19.394867 <LAVA_SIGNAL_TESTSET STOP>
11366 13:42:19.395155 Received signal: <TESTSET> STOP
11367 13:42:19.395228 Closing test_set Codec-ioctls-Input-0
11368 13:42:19.404431 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11369 13:42:19.404747 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11370 13:42:19.404823 Starting test_set Buffer-ioctls-Input-0
11371 13:42:19.407892 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11372 13:42:19.431655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11373 13:42:19.431982 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11375 13:42:19.434825 test CREATE_BUFS maximum buffers: OK
11376 13:42:19.456685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11377 13:42:19.457038 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11379 13:42:19.459864 test VIDIOC_EXPBUF: OK
11380 13:42:19.481773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11381 13:42:19.482102 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11383 13:42:19.484759 test Requests: OK (Not Supported)
11384 13:42:19.507318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11385 13:42:19.507471
11386 13:42:19.507713 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11388 13:42:19.520321 Test input 0:
11389 13:42:19.536156
11390 13:42:19.545914 Streaming ioctls:
11391 13:42:19.552867 <LAVA_SIGNAL_TESTSET STOP>
11392 13:42:19.553142 Received signal: <TESTSET> STOP
11393 13:42:19.553219 Closing test_set Buffer-ioctls-Input-0
11394 13:42:19.562094 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11395 13:42:19.562349 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11396 13:42:19.562424 Starting test_set Streaming-ioctls_Test-input-0
11397 13:42:19.565382 test read/write: OK (Not Supported)
11398 13:42:19.585563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11399 13:42:19.585851 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11401 13:42:19.588482 test blocking wait: OK
11402 13:42:19.608705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11403 13:42:19.609044 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11405 13:42:19.615142 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11406 13:42:19.620879 test MMAP (no poll): FAIL
11407 13:42:19.645749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11408 13:42:19.646075 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11410 13:42:19.652316 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11411 13:42:19.655806 test MMAP (select): FAIL
11412 13:42:19.679967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11413 13:42:19.680229 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11415 13:42:19.686402 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11416 13:42:19.691985 test MMAP (epoll): FAIL
11417 13:42:19.716854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11418 13:42:19.717007
11419 13:42:19.717265 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11421 13:42:19.730216
11422 13:42:19.918861
11423 13:42:19.927704 test USERPTR (no poll): OK
11424 13:42:19.955091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11425 13:42:19.955237
11426 13:42:19.955478 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11428 13:42:19.969706
11429 13:42:20.158200
11430 13:42:20.168701 test USERPTR (select): OK
11431 13:42:20.195867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11432 13:42:20.196180 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11434 13:42:20.202766 test DMABUF: Cannot test, specify --expbuf-device
11435 13:42:20.206109
11436 13:42:20.226972 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11437 13:42:20.233673 <LAVA_TEST_RUNNER EXIT>
11438 13:42:20.233943 ok: lava_test_shell seems to have completed
11439 13:42:20.234021 Marking unfinished test run as failed
11441 13:42:20.234965 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11442 13:42:20.235092 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11443 13:42:20.235181 end: 3 lava-test-retry (duration 00:00:10) [common]
11444 13:42:20.235289 start: 4 finalize (timeout 00:07:26) [common]
11445 13:42:20.235381 start: 4.1 power-off (timeout 00:00:30) [common]
11446 13:42:20.235564 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11447 13:42:20.314918 >> Command sent successfully.
11448 13:42:20.317475 Returned 0 in 0 seconds
11449 13:42:20.417884 end: 4.1 power-off (duration 00:00:00) [common]
11451 13:42:20.418219 start: 4.2 read-feedback (timeout 00:07:26) [common]
11452 13:42:20.418496 Listened to connection for namespace 'common' for up to 1s
11453 13:42:21.419452 Finalising connection for namespace 'common'
11454 13:42:21.419634 Disconnecting from shell: Finalise
11455 13:42:21.419720 / #
11456 13:42:21.520049 end: 4.2 read-feedback (duration 00:00:01) [common]
11457 13:42:21.520220 end: 4 finalize (duration 00:00:01) [common]
11458 13:42:21.520333 Cleaning after the job
11459 13:42:21.520432 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/ramdisk
11460 13:42:21.524814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/kernel
11461 13:42:21.537619 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/dtb
11462 13:42:21.537807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14063090/tftp-deploy-u_fffaoi/modules
11463 13:42:21.543435 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14063090
11464 13:42:21.605302 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14063090
11465 13:42:21.605473 Job finished correctly