Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:04:42.618600 lava-dispatcher, installed at version: 2024.03
2 18:04:42.618838 start: 0 validate
3 18:04:42.618986 Start time: 2024-06-11 18:04:42.618979+00:00 (UTC)
4 18:04:42.619117 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:04:42.619248 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 18:04:42.887587 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:04:42.887825 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:04:42.889329 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:04:42.889492 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:04:43.156269 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:04:43.156484 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:04:43.422049 validate duration: 0.80
14 18:04:43.422430 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:04:43.422591 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:04:43.422726 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:04:43.422904 Not decompressing ramdisk as can be used compressed.
18 18:04:43.423022 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 18:04:43.423123 saving as /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/ramdisk/rootfs.cpio.gz
20 18:04:43.423216 total size: 8181887 (7 MB)
21 18:04:43.424754 progress 0 % (0 MB)
22 18:04:43.428292 progress 5 % (0 MB)
23 18:04:43.431497 progress 10 % (0 MB)
24 18:04:43.434970 progress 15 % (1 MB)
25 18:04:43.438212 progress 20 % (1 MB)
26 18:04:43.441824 progress 25 % (1 MB)
27 18:04:43.445018 progress 30 % (2 MB)
28 18:04:43.448522 progress 35 % (2 MB)
29 18:04:43.451752 progress 40 % (3 MB)
30 18:04:43.455303 progress 45 % (3 MB)
31 18:04:43.458571 progress 50 % (3 MB)
32 18:04:43.462027 progress 55 % (4 MB)
33 18:04:43.465186 progress 60 % (4 MB)
34 18:04:43.468634 progress 65 % (5 MB)
35 18:04:43.471939 progress 70 % (5 MB)
36 18:04:43.474285 progress 75 % (5 MB)
37 18:04:43.476284 progress 80 % (6 MB)
38 18:04:43.478497 progress 85 % (6 MB)
39 18:04:43.480663 progress 90 % (7 MB)
40 18:04:43.482844 progress 95 % (7 MB)
41 18:04:43.484933 progress 100 % (7 MB)
42 18:04:43.485131 7 MB downloaded in 0.06 s (126.03 MB/s)
43 18:04:43.485283 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:04:43.485557 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:04:43.485676 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:04:43.485759 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:04:43.485942 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:04:43.486048 saving as /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/kernel/Image
50 18:04:43.486113 total size: 54813184 (52 MB)
51 18:04:43.486204 No compression specified
52 18:04:43.487350 progress 0 % (0 MB)
53 18:04:43.501364 progress 5 % (2 MB)
54 18:04:43.515782 progress 10 % (5 MB)
55 18:04:43.530186 progress 15 % (7 MB)
56 18:04:43.544420 progress 20 % (10 MB)
57 18:04:43.558588 progress 25 % (13 MB)
58 18:04:43.572927 progress 30 % (15 MB)
59 18:04:43.586947 progress 35 % (18 MB)
60 18:04:43.600978 progress 40 % (20 MB)
61 18:04:43.615488 progress 45 % (23 MB)
62 18:04:43.629860 progress 50 % (26 MB)
63 18:04:43.644542 progress 55 % (28 MB)
64 18:04:43.659725 progress 60 % (31 MB)
65 18:04:43.674824 progress 65 % (34 MB)
66 18:04:43.690482 progress 70 % (36 MB)
67 18:04:43.704564 progress 75 % (39 MB)
68 18:04:43.718818 progress 80 % (41 MB)
69 18:04:43.732708 progress 85 % (44 MB)
70 18:04:43.747007 progress 90 % (47 MB)
71 18:04:43.760941 progress 95 % (49 MB)
72 18:04:43.774723 progress 100 % (52 MB)
73 18:04:43.774996 52 MB downloaded in 0.29 s (180.95 MB/s)
74 18:04:43.775170 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:04:43.775405 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:04:43.775496 start: 1.3 download-retry (timeout 00:10:00) [common]
78 18:04:43.775580 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 18:04:43.775726 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:04:43.775798 saving as /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/dtb/mt8192-asurada-spherion-r0.dtb
81 18:04:43.775858 total size: 47258 (0 MB)
82 18:04:43.775920 No compression specified
83 18:04:43.777033 progress 69 % (0 MB)
84 18:04:43.777307 progress 100 % (0 MB)
85 18:04:43.777462 0 MB downloaded in 0.00 s (28.15 MB/s)
86 18:04:43.777596 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:04:43.777852 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:04:43.777939 start: 1.4 download-retry (timeout 00:10:00) [common]
90 18:04:43.778022 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 18:04:43.778136 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:04:43.778204 saving as /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/modules/modules.tar
93 18:04:43.778265 total size: 8618176 (8 MB)
94 18:04:43.778327 Using unxz to decompress xz
95 18:04:43.782327 progress 0 % (0 MB)
96 18:04:43.802545 progress 5 % (0 MB)
97 18:04:43.831471 progress 10 % (0 MB)
98 18:04:43.863305 progress 15 % (1 MB)
99 18:04:43.889232 progress 20 % (1 MB)
100 18:04:43.914238 progress 25 % (2 MB)
101 18:04:43.939449 progress 30 % (2 MB)
102 18:04:43.967396 progress 35 % (2 MB)
103 18:04:43.993971 progress 40 % (3 MB)
104 18:04:44.018934 progress 45 % (3 MB)
105 18:04:44.045076 progress 50 % (4 MB)
106 18:04:44.072249 progress 55 % (4 MB)
107 18:04:44.097850 progress 60 % (4 MB)
108 18:04:44.122738 progress 65 % (5 MB)
109 18:04:44.150499 progress 70 % (5 MB)
110 18:04:44.176522 progress 75 % (6 MB)
111 18:04:44.204780 progress 80 % (6 MB)
112 18:04:44.231361 progress 85 % (7 MB)
113 18:04:44.259150 progress 90 % (7 MB)
114 18:04:44.286321 progress 95 % (7 MB)
115 18:04:44.314660 progress 100 % (8 MB)
116 18:04:44.319428 8 MB downloaded in 0.54 s (15.19 MB/s)
117 18:04:44.319793 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:04:44.320223 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:04:44.320382 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:04:44.320524 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:04:44.320660 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:04:44.320808 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:04:44.321144 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy
125 18:04:44.321371 makedir: /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin
126 18:04:44.321546 makedir: /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/tests
127 18:04:44.321703 makedir: /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/results
128 18:04:44.321896 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-add-keys
129 18:04:44.322098 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-add-sources
130 18:04:44.322302 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-background-process-start
131 18:04:44.322503 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-background-process-stop
132 18:04:44.322682 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-common-functions
133 18:04:44.322879 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-echo-ipv4
134 18:04:44.323077 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-install-packages
135 18:04:44.323256 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-installed-packages
136 18:04:44.323467 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-os-build
137 18:04:44.323647 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-probe-channel
138 18:04:44.323818 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-probe-ip
139 18:04:44.324023 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-target-ip
140 18:04:44.324205 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-target-mac
141 18:04:44.324424 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-target-storage
142 18:04:44.324641 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-case
143 18:04:44.324855 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-event
144 18:04:44.325053 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-feedback
145 18:04:44.325256 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-raise
146 18:04:44.325438 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-reference
147 18:04:44.325682 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-runner
148 18:04:44.325859 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-set
149 18:04:44.326071 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-test-shell
150 18:04:44.326256 Updating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-install-packages (oe)
151 18:04:44.326466 Updating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/bin/lava-installed-packages (oe)
152 18:04:44.326678 Creating /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/environment
153 18:04:44.326835 LAVA metadata
154 18:04:44.326947 - LAVA_JOB_ID=14291414
155 18:04:44.327068 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:04:44.327226 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:04:44.327346 skipped lava-vland-overlay
158 18:04:44.327476 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:04:44.327654 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:04:44.327756 skipped lava-multinode-overlay
161 18:04:44.327869 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:04:44.327998 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:04:44.328112 Loading test definitions
164 18:04:44.328250 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:04:44.328385 Using /lava-14291414 at stage 0
166 18:04:44.328865 uuid=14291414_1.5.2.3.1 testdef=None
167 18:04:44.328992 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:04:44.329119 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:04:44.329914 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:04:44.330285 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:04:44.331276 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:04:44.331691 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:04:44.332739 runner path: /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/0/tests/0_dmesg test_uuid 14291414_1.5.2.3.1
176 18:04:44.332953 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:04:44.333296 Creating lava-test-runner.conf files
179 18:04:44.333407 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291414/lava-overlay-_7sxqqgy/lava-14291414/0 for stage 0
180 18:04:44.333529 - 0_dmesg
181 18:04:44.333695 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:04:44.333828 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:04:44.344312 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:04:44.344554 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:04:44.344729 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:04:44.344856 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:04:44.344979 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:04:44.611879 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 18:04:44.612278 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 18:04:44.612435 extracting modules file /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291414/extract-overlay-ramdisk-7mxfefcz/ramdisk
191 18:04:44.852124 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:04:44.852307 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 18:04:44.852417 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291414/compress-overlay-zz4qjbq_/overlay-1.5.2.4.tar.gz to ramdisk
194 18:04:44.852490 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291414/compress-overlay-zz4qjbq_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291414/extract-overlay-ramdisk-7mxfefcz/ramdisk
195 18:04:44.860197 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:04:44.860457 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 18:04:44.860590 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:04:44.860688 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 18:04:44.860778 Building ramdisk /var/lib/lava/dispatcher/tmp/14291414/extract-overlay-ramdisk-7mxfefcz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291414/extract-overlay-ramdisk-7mxfefcz/ramdisk
200 18:04:45.215861 >> 145182 blocks
201 18:04:47.648133 rename /var/lib/lava/dispatcher/tmp/14291414/extract-overlay-ramdisk-7mxfefcz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/ramdisk/ramdisk.cpio.gz
202 18:04:47.648753 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 18:04:47.648962 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 18:04:47.649146 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 18:04:47.649325 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/kernel/Image']
206 18:05:02.249646 Returned 0 in 14 seconds
207 18:05:02.350333 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/kernel/image.itb
208 18:05:02.747013 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:05:02.747402 output: Created: Tue Jun 11 19:05:02 2024
210 18:05:02.747483 output: Image 0 (kernel-1)
211 18:05:02.747550 output: Description:
212 18:05:02.747612 output: Created: Tue Jun 11 19:05:02 2024
213 18:05:02.747674 output: Type: Kernel Image
214 18:05:02.747736 output: Compression: lzma compressed
215 18:05:02.747795 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:05:02.747855 output: Architecture: AArch64
217 18:05:02.747934 output: OS: Linux
218 18:05:02.747996 output: Load Address: 0x00000000
219 18:05:02.748058 output: Entry Point: 0x00000000
220 18:05:02.748119 output: Hash algo: crc32
221 18:05:02.748179 output: Hash value: 7a9e9d3e
222 18:05:02.748238 output: Image 1 (fdt-1)
223 18:05:02.748325 output: Description: mt8192-asurada-spherion-r0
224 18:05:02.748405 output: Created: Tue Jun 11 19:05:02 2024
225 18:05:02.748465 output: Type: Flat Device Tree
226 18:05:02.748520 output: Compression: uncompressed
227 18:05:02.748575 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:05:02.748630 output: Architecture: AArch64
229 18:05:02.748683 output: Hash algo: crc32
230 18:05:02.748747 output: Hash value: 0f8e4d2e
231 18:05:02.748836 output: Image 2 (ramdisk-1)
232 18:05:02.748924 output: Description: unavailable
233 18:05:02.749012 output: Created: Tue Jun 11 19:05:02 2024
234 18:05:02.749099 output: Type: RAMDisk Image
235 18:05:02.749191 output: Compression: Unknown Compression
236 18:05:02.749291 output: Data Size: 21376335 Bytes = 20875.33 KiB = 20.39 MiB
237 18:05:02.749395 output: Architecture: AArch64
238 18:05:02.749458 output: OS: Linux
239 18:05:02.749516 output: Load Address: unavailable
240 18:05:02.749573 output: Entry Point: unavailable
241 18:05:02.749629 output: Hash algo: crc32
242 18:05:02.749684 output: Hash value: 14418371
243 18:05:02.749739 output: Default Configuration: 'conf-1'
244 18:05:02.749794 output: Configuration 0 (conf-1)
245 18:05:02.749848 output: Description: mt8192-asurada-spherion-r0
246 18:05:02.749903 output: Kernel: kernel-1
247 18:05:02.749957 output: Init Ramdisk: ramdisk-1
248 18:05:02.750012 output: FDT: fdt-1
249 18:05:02.750066 output: Loadables: kernel-1
250 18:05:02.750119 output:
251 18:05:02.750331 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 18:05:02.750429 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 18:05:02.750539 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 18:05:02.750636 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 18:05:02.750712 No LXC device requested
256 18:05:02.750794 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:05:02.750877 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 18:05:02.750954 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:05:02.751025 Checking files for TFTP limit of 4294967296 bytes.
260 18:05:02.751531 end: 1 tftp-deploy (duration 00:00:19) [common]
261 18:05:02.751642 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:05:02.751736 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:05:02.751864 substitutions:
264 18:05:02.751958 - {DTB}: 14291414/tftp-deploy-nsk2g2v5/dtb/mt8192-asurada-spherion-r0.dtb
265 18:05:02.752028 - {INITRD}: 14291414/tftp-deploy-nsk2g2v5/ramdisk/ramdisk.cpio.gz
266 18:05:02.752090 - {KERNEL}: 14291414/tftp-deploy-nsk2g2v5/kernel/Image
267 18:05:02.752149 - {LAVA_MAC}: None
268 18:05:02.752208 - {PRESEED_CONFIG}: None
269 18:05:02.752265 - {PRESEED_LOCAL}: None
270 18:05:02.752321 - {RAMDISK}: 14291414/tftp-deploy-nsk2g2v5/ramdisk/ramdisk.cpio.gz
271 18:05:02.752396 - {ROOT_PART}: None
272 18:05:02.752453 - {ROOT}: None
273 18:05:02.752511 - {SERVER_IP}: 192.168.201.1
274 18:05:02.752567 - {TEE}: None
275 18:05:02.752623 Parsed boot commands:
276 18:05:02.752679 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:05:02.752868 Parsed boot commands: tftpboot 192.168.201.1 14291414/tftp-deploy-nsk2g2v5/kernel/image.itb 14291414/tftp-deploy-nsk2g2v5/kernel/cmdline
278 18:05:02.752962 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:05:02.753050 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:05:02.753143 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:05:02.753231 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:05:02.753303 Not connected, no need to disconnect.
283 18:05:02.753378 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:05:02.753461 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:05:02.753527 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 18:05:02.757448 Setting prompt string to ['lava-test: # ']
287 18:05:02.757885 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:05:02.758021 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:05:02.758127 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:05:02.758218 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:05:02.758420 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 18:05:07.893198 >> Command sent successfully.
293 18:05:07.895706 Returned 0 in 5 seconds
294 18:05:07.996133 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 18:05:07.996572 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 18:05:07.996712 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 18:05:07.996839 Setting prompt string to 'Starting depthcharge on Spherion...'
299 18:05:07.996941 Changing prompt to 'Starting depthcharge on Spherion...'
300 18:05:07.997045 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 18:05:07.997594 [Enter `^Ec?' for help]
302 18:05:08.397967
303 18:05:08.398115
304 18:05:08.398185 F0: 102B 0000
305 18:05:08.398248
306 18:05:08.398328 F3: 1001 0000 [0200]
307 18:05:08.401476
308 18:05:08.401568 F3: 1001 0000
309 18:05:08.401637
310 18:05:08.401721 F7: 102D 0000
311 18:05:08.401783
312 18:05:08.404265 F1: 0000 0000
313 18:05:08.404386
314 18:05:08.404496 V0: 0000 0000 [0001]
315 18:05:08.404596
316 18:05:08.407919 00: 0007 8000
317 18:05:08.408039
318 18:05:08.408130 01: 0000 0000
319 18:05:08.408220
320 18:05:08.410956 BP: 0C00 0209 [0000]
321 18:05:08.411033
322 18:05:08.411094 G0: 1182 0000
323 18:05:08.411151
324 18:05:08.414562 EC: 0000 0021 [4000]
325 18:05:08.414634
326 18:05:08.414701 S7: 0000 0000 [0000]
327 18:05:08.414758
328 18:05:08.417439 CC: 0000 0000 [0001]
329 18:05:08.417522
330 18:05:08.417586 T0: 0000 0040 [010F]
331 18:05:08.417646
332 18:05:08.420833 Jump to BL
333 18:05:08.420910
334 18:05:08.444770
335 18:05:08.444927
336 18:05:08.454470 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 18:05:08.458069 ARM64: Exception handlers installed.
338 18:05:08.458182 ARM64: Testing exception
339 18:05:08.461009 ARM64: Done test exception
340 18:05:08.467720 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 18:05:08.478721 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 18:05:08.485449 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 18:05:08.495720 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 18:05:08.502404 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 18:05:08.512561 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 18:05:08.522806 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 18:05:08.529223 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 18:05:08.547867 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 18:05:08.551169 WDT: Last reset was cold boot
350 18:05:08.554530 SPI1(PAD0) initialized at 2873684 Hz
351 18:05:08.557544 SPI5(PAD0) initialized at 992727 Hz
352 18:05:08.561355 VBOOT: Loading verstage.
353 18:05:08.567984 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 18:05:08.570904 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 18:05:08.574608 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 18:05:08.577597 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 18:05:08.585418 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 18:05:08.592068 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 18:05:08.603110 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 18:05:08.603245
361 18:05:08.603347
362 18:05:08.612940 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 18:05:08.616280 ARM64: Exception handlers installed.
364 18:05:08.619475 ARM64: Testing exception
365 18:05:08.619570 ARM64: Done test exception
366 18:05:08.626151 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 18:05:08.629611 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 18:05:08.643602 Probing TPM: . done!
369 18:05:08.643730 TPM ready after 0 ms
370 18:05:08.650628 Connected to device vid:did:rid of 1ae0:0028:00
371 18:05:08.657125 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 18:05:08.728958 Initialized TPM device CR50 revision 0
373 18:05:08.757831 tlcl_send_startup: Startup return code is 0
374 18:05:08.758029 TPM: setup succeeded
375 18:05:08.769314 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 18:05:08.778246 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 18:05:08.791778 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 18:05:08.799864 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 18:05:08.802911 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 18:05:08.806693 in-header: 03 07 00 00 08 00 00 00
381 18:05:08.810496 in-data: aa e4 47 04 13 02 00 00
382 18:05:08.814813 Chrome EC: UHEPI supported
383 18:05:08.817794 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 18:05:08.821703 in-header: 03 ad 00 00 08 00 00 00
385 18:05:08.824688 in-data: 00 20 20 08 00 00 00 00
386 18:05:08.828352 Phase 1
387 18:05:08.831365 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 18:05:08.838363 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 18:05:08.841284 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 18:05:08.845021 Recovery requested (1009000e)
391 18:05:08.852815 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:05:08.858040 tlcl_extend: response is 0
393 18:05:08.868347 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:05:08.871844 tlcl_extend: response is 0
395 18:05:08.879006 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:05:08.899605 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 18:05:08.906059 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:05:08.906194
399 18:05:08.906286
400 18:05:08.916264 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:05:08.920020 ARM64: Exception handlers installed.
402 18:05:08.922924 ARM64: Testing exception
403 18:05:08.923011 ARM64: Done test exception
404 18:05:08.944857 pmic_efuse_setting: Set efuses in 11 msecs
405 18:05:08.947883 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:05:08.954608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:05:08.958388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:05:08.964476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:05:08.968134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:05:08.974606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:05:08.978497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:05:08.981394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:05:08.988146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:05:08.991744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:05:08.998271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:05:09.001355 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:05:09.004718 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:05:09.011535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:05:09.018131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:05:09.021492 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:05:09.028331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:05:09.034537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:05:09.041280 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:05:09.044922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:05:09.051512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:05:09.055162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:05:09.061788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:05:09.067818 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:05:09.071520 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:05:09.078316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:05:09.084807 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:05:09.087694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:05:09.094615 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:05:09.098305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:05:09.104620 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:05:09.108120 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:05:09.114496 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:05:09.118184 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:05:09.124948 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:05:09.127980 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:05:09.134583 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:05:09.138074 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:05:09.145000 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:05:09.147898 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:05:09.151157 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:05:09.157949 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:05:09.161556 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:05:09.164628 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:05:09.171395 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:05:09.174834 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:05:09.177964 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:05:09.181543 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:05:09.188045 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:05:09.191759 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:05:09.194659 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:05:09.198359 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:05:09.208296 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 18:05:09.214626 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:05:09.221586 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:05:09.227959 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:05:09.237663 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:05:09.241413 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:05:09.244378 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:05:09.251223 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:05:09.258626 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0xd
466 18:05:09.265028 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
467 18:05:09.268479 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 18:05:09.271211 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:05:09.281666 [RTC]rtc_get_frequency_meter,154: input=15, output=759
470 18:05:09.291708 [RTC]rtc_get_frequency_meter,154: input=23, output=942
471 18:05:09.301182 [RTC]rtc_get_frequency_meter,154: input=19, output=850
472 18:05:09.310725 [RTC]rtc_get_frequency_meter,154: input=17, output=804
473 18:05:09.319892 [RTC]rtc_get_frequency_meter,154: input=16, output=782
474 18:05:09.329611 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 18:05:09.338824 [RTC]rtc_get_frequency_meter,154: input=17, output=803
476 18:05:09.342278 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 18:05:09.349703 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
478 18:05:09.352827 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 18:05:09.355786 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 18:05:09.362533 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 18:05:09.366360 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 18:05:09.369382 ADC[4]: Raw value=905834 ID=7
483 18:05:09.369483 ADC[3]: Raw value=213810 ID=1
484 18:05:09.373114 RAM Code: 0x71
485 18:05:09.376075 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 18:05:09.382603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 18:05:09.389631 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 18:05:09.396655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 18:05:09.399662 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 18:05:09.402935 in-header: 03 07 00 00 08 00 00 00
491 18:05:09.406573 in-data: aa e4 47 04 13 02 00 00
492 18:05:09.409670 Chrome EC: UHEPI supported
493 18:05:09.416136 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 18:05:09.419511 in-header: 03 ed 00 00 08 00 00 00
495 18:05:09.423307 in-data: 80 20 60 08 00 00 00 00
496 18:05:09.426546 MRC: failed to locate region type 0.
497 18:05:09.432716 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 18:05:09.436382 DRAM-K: Running full calibration
499 18:05:09.443894 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 18:05:09.444013 header.status = 0x0
501 18:05:09.447489 header.version = 0x6 (expected: 0x6)
502 18:05:09.451272 header.size = 0xd00 (expected: 0xd00)
503 18:05:09.451401 header.flags = 0x0
504 18:05:09.458245 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 18:05:09.476778 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 18:05:09.483697 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 18:05:09.486563 dram_init: ddr_geometry: 2
508 18:05:09.486665 [EMI] MDL number = 2
509 18:05:09.490246 [EMI] Get MDL freq = 0
510 18:05:09.493327 dram_init: ddr_type: 0
511 18:05:09.493441 is_discrete_lpddr4: 1
512 18:05:09.496995 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 18:05:09.497085
514 18:05:09.497171
515 18:05:09.500130 [Bian_co] ETT version 0.0.0.1
516 18:05:09.503389 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 18:05:09.503488
518 18:05:09.510220 dramc_set_vcore_voltage set vcore to 650000
519 18:05:09.510330 Read voltage for 800, 4
520 18:05:09.510421 Vio18 = 0
521 18:05:09.513260 Vcore = 650000
522 18:05:09.513346 Vdram = 0
523 18:05:09.513439 Vddq = 0
524 18:05:09.516999 Vmddr = 0
525 18:05:09.517092 dram_init: config_dvfs: 1
526 18:05:09.523754 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 18:05:09.530504 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 18:05:09.533419 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 18:05:09.537270 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 18:05:09.540195 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 18:05:09.543748 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 18:05:09.547242 MEM_TYPE=3, freq_sel=18
533 18:05:09.549944 sv_algorithm_assistance_LP4_1600
534 18:05:09.553778 ============ PULL DRAM RESETB DOWN ============
535 18:05:09.557054 ========== PULL DRAM RESETB DOWN end =========
536 18:05:09.563467 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 18:05:09.567163 ===================================
538 18:05:09.567299 LPDDR4 DRAM CONFIGURATION
539 18:05:09.570642 ===================================
540 18:05:09.573718 EX_ROW_EN[0] = 0x0
541 18:05:09.573816 EX_ROW_EN[1] = 0x0
542 18:05:09.576959 LP4Y_EN = 0x0
543 18:05:09.577086 WORK_FSP = 0x0
544 18:05:09.580358 WL = 0x2
545 18:05:09.580451 RL = 0x2
546 18:05:09.583749 BL = 0x2
547 18:05:09.583870 RPST = 0x0
548 18:05:09.587373 RD_PRE = 0x0
549 18:05:09.590595 WR_PRE = 0x1
550 18:05:09.590690 WR_PST = 0x0
551 18:05:09.593609 DBI_WR = 0x0
552 18:05:09.593720 DBI_RD = 0x0
553 18:05:09.597098 OTF = 0x1
554 18:05:09.600665 ===================================
555 18:05:09.603695 ===================================
556 18:05:09.603810 ANA top config
557 18:05:09.607569 ===================================
558 18:05:09.610610 DLL_ASYNC_EN = 0
559 18:05:09.610703 ALL_SLAVE_EN = 1
560 18:05:09.613709 NEW_RANK_MODE = 1
561 18:05:09.617686 DLL_IDLE_MODE = 1
562 18:05:09.620721 LP45_APHY_COMB_EN = 1
563 18:05:09.623662 TX_ODT_DIS = 1
564 18:05:09.623753 NEW_8X_MODE = 1
565 18:05:09.627658 ===================================
566 18:05:09.630344 ===================================
567 18:05:09.634560 data_rate = 1600
568 18:05:09.637618 CKR = 1
569 18:05:09.641606 DQ_P2S_RATIO = 8
570 18:05:09.645457 ===================================
571 18:05:09.645559 CA_P2S_RATIO = 8
572 18:05:09.648645 DQ_CA_OPEN = 0
573 18:05:09.652469 DQ_SEMI_OPEN = 0
574 18:05:09.656200 CA_SEMI_OPEN = 0
575 18:05:09.656305 CA_FULL_RATE = 0
576 18:05:09.660022 DQ_CKDIV4_EN = 1
577 18:05:09.663745 CA_CKDIV4_EN = 1
578 18:05:09.667302 CA_PREDIV_EN = 0
579 18:05:09.667405 PH8_DLY = 0
580 18:05:09.671032 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 18:05:09.674691 DQ_AAMCK_DIV = 4
582 18:05:09.678440 CA_AAMCK_DIV = 4
583 18:05:09.678561 CA_ADMCK_DIV = 4
584 18:05:09.681761 DQ_TRACK_CA_EN = 0
585 18:05:09.685066 CA_PICK = 800
586 18:05:09.688286 CA_MCKIO = 800
587 18:05:09.691507 MCKIO_SEMI = 0
588 18:05:09.695118 PLL_FREQ = 3068
589 18:05:09.695241 DQ_UI_PI_RATIO = 32
590 18:05:09.698177 CA_UI_PI_RATIO = 0
591 18:05:09.701731 ===================================
592 18:05:09.704861 ===================================
593 18:05:09.708675 memory_type:LPDDR4
594 18:05:09.712066 GP_NUM : 10
595 18:05:09.712195 SRAM_EN : 1
596 18:05:09.715294 MD32_EN : 0
597 18:05:09.718534 ===================================
598 18:05:09.718659 [ANA_INIT] >>>>>>>>>>>>>>
599 18:05:09.722021 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 18:05:09.724862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 18:05:09.728721 ===================================
602 18:05:09.731804 data_rate = 1600,PCW = 0X7600
603 18:05:09.734923 ===================================
604 18:05:09.738609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 18:05:09.745472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 18:05:09.749302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 18:05:09.756349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 18:05:09.760172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 18:05:09.760303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 18:05:09.763288 [ANA_INIT] flow start
611 18:05:09.767127 [ANA_INIT] PLL >>>>>>>>
612 18:05:09.767229 [ANA_INIT] PLL <<<<<<<<
613 18:05:09.770799 [ANA_INIT] MIDPI >>>>>>>>
614 18:05:09.774497 [ANA_INIT] MIDPI <<<<<<<<
615 18:05:09.774592 [ANA_INIT] DLL >>>>>>>>
616 18:05:09.778078 [ANA_INIT] flow end
617 18:05:09.781884 ============ LP4 DIFF to SE enter ============
618 18:05:09.785686 ============ LP4 DIFF to SE exit ============
619 18:05:09.789381 [ANA_INIT] <<<<<<<<<<<<<
620 18:05:09.789474 [Flow] Enable top DCM control >>>>>
621 18:05:09.793304 [Flow] Enable top DCM control <<<<<
622 18:05:09.796321 Enable DLL master slave shuffle
623 18:05:09.803809 ==============================================================
624 18:05:09.803921 Gating Mode config
625 18:05:09.811091 ==============================================================
626 18:05:09.811194 Config description:
627 18:05:09.822416 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 18:05:09.830212 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 18:05:09.833862 SELPH_MODE 0: By rank 1: By Phase
630 18:05:09.837730 ==============================================================
631 18:05:09.840898 GAT_TRACK_EN = 1
632 18:05:09.844682 RX_GATING_MODE = 2
633 18:05:09.848468 RX_GATING_TRACK_MODE = 2
634 18:05:09.852016 SELPH_MODE = 1
635 18:05:09.852146 PICG_EARLY_EN = 1
636 18:05:09.855313 VALID_LAT_VALUE = 1
637 18:05:09.862064 ==============================================================
638 18:05:09.865929 Enter into Gating configuration >>>>
639 18:05:09.868988 Exit from Gating configuration <<<<
640 18:05:09.872902 Enter into DVFS_PRE_config >>>>>
641 18:05:09.883331 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 18:05:09.886335 Exit from DVFS_PRE_config <<<<<
643 18:05:09.889469 Enter into PICG configuration >>>>
644 18:05:09.893276 Exit from PICG configuration <<<<
645 18:05:09.896484 [RX_INPUT] configuration >>>>>
646 18:05:09.899370 [RX_INPUT] configuration <<<<<
647 18:05:09.903181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 18:05:09.909388 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 18:05:09.916246 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 18:05:09.919243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 18:05:09.926459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 18:05:09.933833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 18:05:09.937466 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 18:05:09.941276 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 18:05:09.944980 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 18:05:09.948979 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 18:05:09.952778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 18:05:09.959951 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 18:05:09.960127 ===================================
660 18:05:09.963720 LPDDR4 DRAM CONFIGURATION
661 18:05:09.967289 ===================================
662 18:05:09.967422 EX_ROW_EN[0] = 0x0
663 18:05:09.971631 EX_ROW_EN[1] = 0x0
664 18:05:09.971743 LP4Y_EN = 0x0
665 18:05:09.974948 WORK_FSP = 0x0
666 18:05:09.975074 WL = 0x2
667 18:05:09.979043 RL = 0x2
668 18:05:09.979170 BL = 0x2
669 18:05:09.982498 RPST = 0x0
670 18:05:09.982638 RD_PRE = 0x0
671 18:05:09.986135 WR_PRE = 0x1
672 18:05:09.986225 WR_PST = 0x0
673 18:05:09.989698 DBI_WR = 0x0
674 18:05:09.989803 DBI_RD = 0x0
675 18:05:09.993527 OTF = 0x1
676 18:05:09.993625 ===================================
677 18:05:09.997363 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 18:05:10.005336 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 18:05:10.008335 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 18:05:10.012184 ===================================
681 18:05:10.012296 LPDDR4 DRAM CONFIGURATION
682 18:05:10.015966 ===================================
683 18:05:10.019897 EX_ROW_EN[0] = 0x10
684 18:05:10.020029 EX_ROW_EN[1] = 0x0
685 18:05:10.023743 LP4Y_EN = 0x0
686 18:05:10.023850 WORK_FSP = 0x0
687 18:05:10.026889 WL = 0x2
688 18:05:10.026984 RL = 0x2
689 18:05:10.030654 BL = 0x2
690 18:05:10.030758 RPST = 0x0
691 18:05:10.030829 RD_PRE = 0x0
692 18:05:10.034362 WR_PRE = 0x1
693 18:05:10.034468 WR_PST = 0x0
694 18:05:10.038016 DBI_WR = 0x0
695 18:05:10.038139 DBI_RD = 0x0
696 18:05:10.041632 OTF = 0x1
697 18:05:10.045431 ===================================
698 18:05:10.049241 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 18:05:10.055177 nWR fixed to 40
700 18:05:10.058867 [ModeRegInit_LP4] CH0 RK0
701 18:05:10.059002 [ModeRegInit_LP4] CH0 RK1
702 18:05:10.061891 [ModeRegInit_LP4] CH1 RK0
703 18:05:10.062016 [ModeRegInit_LP4] CH1 RK1
704 18:05:10.065641 match AC timing 13
705 18:05:10.069437 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 18:05:10.073126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 18:05:10.076942 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 18:05:10.084221 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 18:05:10.087947 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 18:05:10.088060 [EMI DOE] emi_dcm 0
711 18:05:10.095110 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 18:05:10.095233 ==
713 18:05:10.099319 Dram Type= 6, Freq= 0, CH_0, rank 0
714 18:05:10.102790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 18:05:10.102916 ==
716 18:05:10.106849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 18:05:10.113655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 18:05:10.122091 [CA 0] Center 36 (6~67) winsize 62
719 18:05:10.125895 [CA 1] Center 36 (6~67) winsize 62
720 18:05:10.129672 [CA 2] Center 34 (4~65) winsize 62
721 18:05:10.133489 [CA 3] Center 33 (3~64) winsize 62
722 18:05:10.137051 [CA 4] Center 33 (3~63) winsize 61
723 18:05:10.140621 [CA 5] Center 32 (3~62) winsize 60
724 18:05:10.140760
725 18:05:10.144105 [CmdBusTrainingLP45] Vref(ca) range 1: 32
726 18:05:10.144230
727 18:05:10.147984 [CATrainingPosCal] consider 1 rank data
728 18:05:10.148115 u2DelayCellTimex100 = 270/100 ps
729 18:05:10.151833 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 18:05:10.155592 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 18:05:10.159406 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 18:05:10.162979 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 18:05:10.166824 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
734 18:05:10.170186 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
735 18:05:10.170307
736 18:05:10.174457 CA PerBit enable=1, Macro0, CA PI delay=32
737 18:05:10.174601
738 18:05:10.178190 [CBTSetCACLKResult] CA Dly = 32
739 18:05:10.181990 CS Dly: 4 (0~35)
740 18:05:10.182132 ==
741 18:05:10.182232 Dram Type= 6, Freq= 0, CH_0, rank 1
742 18:05:10.189411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 18:05:10.189536 ==
744 18:05:10.193323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 18:05:10.200114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 18:05:10.208408 [CA 0] Center 36 (6~67) winsize 62
747 18:05:10.211979 [CA 1] Center 36 (6~67) winsize 62
748 18:05:10.215424 [CA 2] Center 34 (3~65) winsize 63
749 18:05:10.219657 [CA 3] Center 33 (3~64) winsize 62
750 18:05:10.222453 [CA 4] Center 32 (2~63) winsize 62
751 18:05:10.226639 [CA 5] Center 32 (2~63) winsize 62
752 18:05:10.226792
753 18:05:10.230388 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 18:05:10.230518
755 18:05:10.233370 [CATrainingPosCal] consider 2 rank data
756 18:05:10.237117 u2DelayCellTimex100 = 270/100 ps
757 18:05:10.240901 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 18:05:10.244649 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 18:05:10.248272 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
760 18:05:10.248421 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
761 18:05:10.256034 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
762 18:05:10.256194 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
763 18:05:10.256305
764 18:05:10.263576 CA PerBit enable=1, Macro0, CA PI delay=32
765 18:05:10.263710
766 18:05:10.263781 [CBTSetCACLKResult] CA Dly = 32
767 18:05:10.267313 CS Dly: 4 (0~36)
768 18:05:10.267428
769 18:05:10.271211 ----->DramcWriteLeveling(PI) begin...
770 18:05:10.271327 ==
771 18:05:10.274268 Dram Type= 6, Freq= 0, CH_0, rank 0
772 18:05:10.278499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 18:05:10.278649 ==
774 18:05:10.282097 Write leveling (Byte 0): 33 => 33
775 18:05:10.285673 Write leveling (Byte 1): 30 => 30
776 18:05:10.285811 DramcWriteLeveling(PI) end<-----
777 18:05:10.285912
778 18:05:10.286007 ==
779 18:05:10.289549 Dram Type= 6, Freq= 0, CH_0, rank 0
780 18:05:10.293216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 18:05:10.293325 ==
782 18:05:10.296975 [Gating] SW mode calibration
783 18:05:10.304717 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 18:05:10.308477 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 18:05:10.315529 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 18:05:10.319323 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 18:05:10.323191 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 18:05:10.326969 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 18:05:10.330722 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:05:10.337842 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:05:10.341299 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:05:10.345295 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:05:10.349124 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:05:10.352835 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:05:10.356724 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:05:10.363700 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:05:10.368106 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:05:10.371365 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 18:05:10.374967 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 18:05:10.378723 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:05:10.382589 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:05:10.390352 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 18:05:10.394010 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
804 18:05:10.397500 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 18:05:10.401273 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:05:10.405152 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:05:10.412624 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:05:10.416513 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 18:05:10.419666 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 18:05:10.423419 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 18:05:10.427353 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
812 18:05:10.431157 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
813 18:05:10.438008 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:05:10.441763 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:05:10.445655 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 18:05:10.449461 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 18:05:10.453118 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 18:05:10.460615 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
819 18:05:10.464811 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
820 18:05:10.468458 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
821 18:05:10.472322 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:05:10.475707 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:05:10.479332 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 18:05:10.486961 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 18:05:10.490731 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 18:05:10.494316 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:05:10.497702 0 11 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
828 18:05:10.501073 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
829 18:05:10.508383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:05:10.511198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:05:10.514464 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 18:05:10.521198 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 18:05:10.524438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 18:05:10.528295 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 18:05:10.534436 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
836 18:05:10.538266 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 18:05:10.541229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:05:10.547981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:05:10.551024 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:05:10.554242 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:05:10.561231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:05:10.564977 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:05:10.568322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:05:10.574780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:05:10.578170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:05:10.581277 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:05:10.584495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 18:05:10.591635 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 18:05:10.594496 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 18:05:10.598337 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 18:05:10.605032 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 18:05:10.608523 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 18:05:10.611423 Total UI for P1: 0, mck2ui 16
854 18:05:10.615013 best dqsien dly found for B0: ( 0, 14, 6)
855 18:05:10.617924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 18:05:10.621446 Total UI for P1: 0, mck2ui 16
857 18:05:10.624850 best dqsien dly found for B1: ( 0, 14, 10)
858 18:05:10.628615 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 18:05:10.631545 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 18:05:10.631692
861 18:05:10.638426 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 18:05:10.641407 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 18:05:10.641530 [Gating] SW calibration Done
864 18:05:10.641604 ==
865 18:05:10.645340 Dram Type= 6, Freq= 0, CH_0, rank 0
866 18:05:10.651996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 18:05:10.652159 ==
868 18:05:10.652268 RX Vref Scan: 0
869 18:05:10.652371
870 18:05:10.654890 RX Vref 0 -> 0, step: 1
871 18:05:10.655012
872 18:05:10.658839 RX Delay -130 -> 252, step: 16
873 18:05:10.661731 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 18:05:10.664863 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 18:05:10.668653 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 18:05:10.674989 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 18:05:10.678832 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 18:05:10.681774 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 18:05:10.685579 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 18:05:10.689340 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 18:05:10.693455 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 18:05:10.696851 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 18:05:10.700598 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 18:05:10.704529 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 18:05:10.711248 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 18:05:10.715683 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 18:05:10.719497 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 18:05:10.723111 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 18:05:10.723273 ==
890 18:05:10.726048 Dram Type= 6, Freq= 0, CH_0, rank 0
891 18:05:10.729978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 18:05:10.730113 ==
893 18:05:10.730213 DQS Delay:
894 18:05:10.732780 DQS0 = 0, DQS1 = 0
895 18:05:10.732875 DQM Delay:
896 18:05:10.735779 DQM0 = 89, DQM1 = 81
897 18:05:10.735908 DQ Delay:
898 18:05:10.739563 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 18:05:10.742470 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 18:05:10.746190 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 18:05:10.749184 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 18:05:10.749317
903 18:05:10.749386
904 18:05:10.749455 ==
905 18:05:10.752947 Dram Type= 6, Freq= 0, CH_0, rank 0
906 18:05:10.755858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 18:05:10.759490 ==
908 18:05:10.759610
909 18:05:10.759678
910 18:05:10.759741 TX Vref Scan disable
911 18:05:10.762665 == TX Byte 0 ==
912 18:05:10.766462 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 18:05:10.769660 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 18:05:10.772711 == TX Byte 1 ==
915 18:05:10.775751 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 18:05:10.779695 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 18:05:10.779817 ==
918 18:05:10.782794 Dram Type= 6, Freq= 0, CH_0, rank 0
919 18:05:10.789711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 18:05:10.789838 ==
921 18:05:10.802055 TX Vref=22, minBit 7, minWin=27, winSum=447
922 18:05:10.805057 TX Vref=24, minBit 5, minWin=27, winSum=448
923 18:05:10.808657 TX Vref=26, minBit 10, minWin=27, winSum=454
924 18:05:10.811568 TX Vref=28, minBit 0, minWin=28, winSum=456
925 18:05:10.815108 TX Vref=30, minBit 5, minWin=28, winSum=457
926 18:05:10.821488 TX Vref=32, minBit 10, minWin=27, winSum=452
927 18:05:10.824812 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
928 18:05:10.824930
929 18:05:10.828252 Final TX Range 1 Vref 30
930 18:05:10.828389
931 18:05:10.828461 ==
932 18:05:10.831409 Dram Type= 6, Freq= 0, CH_0, rank 0
933 18:05:10.834802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 18:05:10.834934 ==
935 18:05:10.838506
936 18:05:10.838645
937 18:05:10.838752 TX Vref Scan disable
938 18:05:10.841513 == TX Byte 0 ==
939 18:05:10.844978 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 18:05:10.848837 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 18:05:10.851992 == TX Byte 1 ==
942 18:05:10.855323 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 18:05:10.858383 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 18:05:10.862096
945 18:05:10.862242 [DATLAT]
946 18:05:10.862347 Freq=800, CH0 RK0
947 18:05:10.862439
948 18:05:10.865061 DATLAT Default: 0xa
949 18:05:10.865170 0, 0xFFFF, sum = 0
950 18:05:10.869440 1, 0xFFFF, sum = 0
951 18:05:10.869555 2, 0xFFFF, sum = 0
952 18:05:10.872694 3, 0xFFFF, sum = 0
953 18:05:10.872809 4, 0xFFFF, sum = 0
954 18:05:10.876716 5, 0xFFFF, sum = 0
955 18:05:10.876835 6, 0xFFFF, sum = 0
956 18:05:10.879762 7, 0xFFFF, sum = 0
957 18:05:10.879867 8, 0xFFFF, sum = 0
958 18:05:10.882839 9, 0x0, sum = 1
959 18:05:10.882952 10, 0x0, sum = 2
960 18:05:10.886642 11, 0x0, sum = 3
961 18:05:10.886752 12, 0x0, sum = 4
962 18:05:10.886851 best_step = 10
963 18:05:10.886935
964 18:05:10.890084 ==
965 18:05:10.892905 Dram Type= 6, Freq= 0, CH_0, rank 0
966 18:05:10.896845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 18:05:10.896963 ==
968 18:05:10.897062 RX Vref Scan: 1
969 18:05:10.897136
970 18:05:10.899877 Set Vref Range= 32 -> 127
971 18:05:10.900002
972 18:05:10.903776 RX Vref 32 -> 127, step: 1
973 18:05:10.903896
974 18:05:10.906897 RX Delay -95 -> 252, step: 8
975 18:05:10.907010
976 18:05:10.910094 Set Vref, RX VrefLevel [Byte0]: 32
977 18:05:10.913141 [Byte1]: 32
978 18:05:10.913265
979 18:05:10.916310 Set Vref, RX VrefLevel [Byte0]: 33
980 18:05:10.920030 [Byte1]: 33
981 18:05:10.920142
982 18:05:10.923125 Set Vref, RX VrefLevel [Byte0]: 34
983 18:05:10.926761 [Byte1]: 34
984 18:05:10.929743
985 18:05:10.929857 Set Vref, RX VrefLevel [Byte0]: 35
986 18:05:10.932783 [Byte1]: 35
987 18:05:10.937288
988 18:05:10.937442 Set Vref, RX VrefLevel [Byte0]: 36
989 18:05:10.940831 [Byte1]: 36
990 18:05:10.945012
991 18:05:10.945140 Set Vref, RX VrefLevel [Byte0]: 37
992 18:05:10.948507 [Byte1]: 37
993 18:05:10.952536
994 18:05:10.952714 Set Vref, RX VrefLevel [Byte0]: 38
995 18:05:10.956158 [Byte1]: 38
996 18:05:10.959922
997 18:05:10.960060 Set Vref, RX VrefLevel [Byte0]: 39
998 18:05:10.963439 [Byte1]: 39
999 18:05:10.967526
1000 18:05:10.967664 Set Vref, RX VrefLevel [Byte0]: 40
1001 18:05:10.970878 [Byte1]: 40
1002 18:05:10.975502
1003 18:05:10.975658 Set Vref, RX VrefLevel [Byte0]: 41
1004 18:05:10.978225 [Byte1]: 41
1005 18:05:10.983091
1006 18:05:10.983287 Set Vref, RX VrefLevel [Byte0]: 42
1007 18:05:10.986655 [Byte1]: 42
1008 18:05:10.990247
1009 18:05:10.990378 Set Vref, RX VrefLevel [Byte0]: 43
1010 18:05:10.994100 [Byte1]: 43
1011 18:05:10.997929
1012 18:05:10.998046 Set Vref, RX VrefLevel [Byte0]: 44
1013 18:05:11.001822 [Byte1]: 44
1014 18:05:11.005545
1015 18:05:11.005692 Set Vref, RX VrefLevel [Byte0]: 45
1016 18:05:11.009276 [Byte1]: 45
1017 18:05:11.013102
1018 18:05:11.013221 Set Vref, RX VrefLevel [Byte0]: 46
1019 18:05:11.016852 [Byte1]: 46
1020 18:05:11.021250
1021 18:05:11.021370 Set Vref, RX VrefLevel [Byte0]: 47
1022 18:05:11.024034 [Byte1]: 47
1023 18:05:11.028656
1024 18:05:11.028777 Set Vref, RX VrefLevel [Byte0]: 48
1025 18:05:11.031493 [Byte1]: 48
1026 18:05:11.036086
1027 18:05:11.036196 Set Vref, RX VrefLevel [Byte0]: 49
1028 18:05:11.039287 [Byte1]: 49
1029 18:05:11.043952
1030 18:05:11.044088 Set Vref, RX VrefLevel [Byte0]: 50
1031 18:05:11.046985 [Byte1]: 50
1032 18:05:11.051418
1033 18:05:11.051562 Set Vref, RX VrefLevel [Byte0]: 51
1034 18:05:11.054358 [Byte1]: 51
1035 18:05:11.059435
1036 18:05:11.059618 Set Vref, RX VrefLevel [Byte0]: 52
1037 18:05:11.061935 [Byte1]: 52
1038 18:05:11.066227
1039 18:05:11.066343 Set Vref, RX VrefLevel [Byte0]: 53
1040 18:05:11.069850 [Byte1]: 53
1041 18:05:11.074658
1042 18:05:11.074804 Set Vref, RX VrefLevel [Byte0]: 54
1043 18:05:11.080423 [Byte1]: 54
1044 18:05:11.080563
1045 18:05:11.084195 Set Vref, RX VrefLevel [Byte0]: 55
1046 18:05:11.087102 [Byte1]: 55
1047 18:05:11.087220
1048 18:05:11.090637 Set Vref, RX VrefLevel [Byte0]: 56
1049 18:05:11.093615 [Byte1]: 56
1050 18:05:11.093764
1051 18:05:11.097329 Set Vref, RX VrefLevel [Byte0]: 57
1052 18:05:11.100576 [Byte1]: 57
1053 18:05:11.104457
1054 18:05:11.104617 Set Vref, RX VrefLevel [Byte0]: 58
1055 18:05:11.107468 [Byte1]: 58
1056 18:05:11.112352
1057 18:05:11.112468 Set Vref, RX VrefLevel [Byte0]: 59
1058 18:05:11.115224 [Byte1]: 59
1059 18:05:11.120139
1060 18:05:11.120285 Set Vref, RX VrefLevel [Byte0]: 60
1061 18:05:11.123449 [Byte1]: 60
1062 18:05:11.126949
1063 18:05:11.127058 Set Vref, RX VrefLevel [Byte0]: 61
1064 18:05:11.130643 [Byte1]: 61
1065 18:05:11.135066
1066 18:05:11.135180 Set Vref, RX VrefLevel [Byte0]: 62
1067 18:05:11.138136 [Byte1]: 62
1068 18:05:11.142734
1069 18:05:11.142851 Set Vref, RX VrefLevel [Byte0]: 63
1070 18:05:11.145763 [Byte1]: 63
1071 18:05:11.150483
1072 18:05:11.150597 Set Vref, RX VrefLevel [Byte0]: 64
1073 18:05:11.153516 [Byte1]: 64
1074 18:05:11.157456
1075 18:05:11.157584 Set Vref, RX VrefLevel [Byte0]: 65
1076 18:05:11.161297 [Byte1]: 65
1077 18:05:11.165667
1078 18:05:11.165786 Set Vref, RX VrefLevel [Byte0]: 66
1079 18:05:11.168430 [Byte1]: 66
1080 18:05:11.173391
1081 18:05:11.173544 Set Vref, RX VrefLevel [Byte0]: 67
1082 18:05:11.176402 [Byte1]: 67
1083 18:05:11.180826
1084 18:05:11.180999 Set Vref, RX VrefLevel [Byte0]: 68
1085 18:05:11.184084 [Byte1]: 68
1086 18:05:11.187925
1087 18:05:11.188040 Set Vref, RX VrefLevel [Byte0]: 69
1088 18:05:11.191712 [Byte1]: 69
1089 18:05:11.196084
1090 18:05:11.196238 Set Vref, RX VrefLevel [Byte0]: 70
1091 18:05:11.199288 [Byte1]: 70
1092 18:05:11.203041
1093 18:05:11.203157 Set Vref, RX VrefLevel [Byte0]: 71
1094 18:05:11.206822 [Byte1]: 71
1095 18:05:11.211056
1096 18:05:11.211209 Set Vref, RX VrefLevel [Byte0]: 72
1097 18:05:11.213952 [Byte1]: 72
1098 18:05:11.218731
1099 18:05:11.218897 Set Vref, RX VrefLevel [Byte0]: 73
1100 18:05:11.221750 [Byte1]: 73
1101 18:05:11.225758
1102 18:05:11.225924 Set Vref, RX VrefLevel [Byte0]: 74
1103 18:05:11.229532 [Byte1]: 74
1104 18:05:11.233360
1105 18:05:11.233506 Set Vref, RX VrefLevel [Byte0]: 75
1106 18:05:11.236862 [Byte1]: 75
1107 18:05:11.241240
1108 18:05:11.241396 Set Vref, RX VrefLevel [Byte0]: 76
1109 18:05:11.244850 [Byte1]: 76
1110 18:05:11.248771
1111 18:05:11.248924 Final RX Vref Byte 0 = 59 to rank0
1112 18:05:11.252591 Final RX Vref Byte 1 = 54 to rank0
1113 18:05:11.255659 Final RX Vref Byte 0 = 59 to rank1
1114 18:05:11.258676 Final RX Vref Byte 1 = 54 to rank1==
1115 18:05:11.262624 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 18:05:11.266482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 18:05:11.266647 ==
1118 18:05:11.270286 DQS Delay:
1119 18:05:11.270437 DQS0 = 0, DQS1 = 0
1120 18:05:11.270515 DQM Delay:
1121 18:05:11.273976 DQM0 = 92, DQM1 = 84
1122 18:05:11.274091 DQ Delay:
1123 18:05:11.277420 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1124 18:05:11.281631 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1125 18:05:11.284723 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1126 18:05:11.287731 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1127 18:05:11.287853
1128 18:05:11.287920
1129 18:05:11.295407 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1130 18:05:11.299002 CH0 RK0: MR19=606, MR18=4E45
1131 18:05:11.305296 CH0_RK0: MR19=0x606, MR18=0x4E45, DQSOSC=390, MR23=63, INC=97, DEC=64
1132 18:05:11.305456
1133 18:05:11.308555 ----->DramcWriteLeveling(PI) begin...
1134 18:05:11.308694 ==
1135 18:05:11.312310 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 18:05:11.315855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 18:05:11.316004 ==
1138 18:05:11.318880 Write leveling (Byte 0): 35 => 35
1139 18:05:11.322453 Write leveling (Byte 1): 30 => 30
1140 18:05:11.325385 DramcWriteLeveling(PI) end<-----
1141 18:05:11.325502
1142 18:05:11.325572 ==
1143 18:05:11.329097 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 18:05:11.332146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 18:05:11.332288 ==
1146 18:05:11.335250 [Gating] SW mode calibration
1147 18:05:11.342710 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 18:05:11.349376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 18:05:11.352048 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 18:05:11.355775 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 18:05:11.362544 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 18:05:11.365665 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 18:05:11.368834 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 18:05:11.375394 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 18:05:11.379104 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 18:05:11.382096 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 18:05:11.388800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:05:11.392361 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:05:11.395614 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:05:11.402393 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:05:11.405392 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:05:11.408719 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:05:11.412324 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:05:11.419427 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:05:11.422725 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:05:11.425665 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 18:05:11.432365 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1168 18:05:11.436051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 18:05:11.438958 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 18:05:11.445932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:05:11.449083 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:05:11.452881 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:05:11.459252 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:05:11.462957 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:05:11.465847 0 9 8 | B1->B0 | 2929 2a2a | 1 0 | (0 0) (0 0)
1176 18:05:11.472826 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 18:05:11.476046 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 18:05:11.479093 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 18:05:11.482938 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 18:05:11.489261 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 18:05:11.492258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:05:11.495924 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 18:05:11.502608 0 10 8 | B1->B0 | 2828 2929 | 0 0 | (1 0) (0 0)
1184 18:05:11.506641 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 18:05:11.509487 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 18:05:11.516168 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 18:05:11.519851 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 18:05:11.522911 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 18:05:11.529862 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:05:11.532723 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1191 18:05:11.536160 0 11 8 | B1->B0 | 3939 3c3c | 0 0 | (0 0) (0 0)
1192 18:05:11.542655 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 18:05:11.546333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 18:05:11.549225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 18:05:11.555835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 18:05:11.559667 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 18:05:11.562679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:05:11.566371 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 18:05:11.572824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 18:05:11.576594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1201 18:05:11.579475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 18:05:11.586434 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 18:05:11.589682 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 18:05:11.592611 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 18:05:11.599670 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:05:11.602618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:05:11.606398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:05:11.612867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:05:11.616650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:05:11.619599 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:05:11.626226 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:05:11.630102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:05:11.633295 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:05:11.636361 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 18:05:11.643195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 18:05:11.646194 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 18:05:11.649671 Total UI for P1: 0, mck2ui 16
1218 18:05:11.653168 best dqsien dly found for B0: ( 0, 14, 8)
1219 18:05:11.656601 Total UI for P1: 0, mck2ui 16
1220 18:05:11.659557 best dqsien dly found for B1: ( 0, 14, 8)
1221 18:05:11.663230 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 18:05:11.666224 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1223 18:05:11.666340
1224 18:05:11.670081 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 18:05:11.672824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 18:05:11.676474 [Gating] SW calibration Done
1227 18:05:11.676597 ==
1228 18:05:11.680353 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 18:05:11.683148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 18:05:11.686839 ==
1231 18:05:11.686966 RX Vref Scan: 0
1232 18:05:11.687038
1233 18:05:11.689746 RX Vref 0 -> 0, step: 1
1234 18:05:11.689847
1235 18:05:11.693665 RX Delay -130 -> 252, step: 16
1236 18:05:11.696732 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 18:05:11.699670 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 18:05:11.703479 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1239 18:05:11.706952 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 18:05:11.713658 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 18:05:11.716637 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1242 18:05:11.720269 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1243 18:05:11.723277 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1244 18:05:11.727044 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 18:05:11.729844 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 18:05:11.736722 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 18:05:11.740568 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1248 18:05:11.743595 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1249 18:05:11.746732 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1250 18:05:11.753649 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 18:05:11.756636 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 18:05:11.756783 ==
1253 18:05:11.760415 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 18:05:11.763337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 18:05:11.763491 ==
1256 18:05:11.763591 DQS Delay:
1257 18:05:11.766944 DQS0 = 0, DQS1 = 0
1258 18:05:11.767082 DQM Delay:
1259 18:05:11.769978 DQM0 = 91, DQM1 = 81
1260 18:05:11.770102 DQ Delay:
1261 18:05:11.773125 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1262 18:05:11.776811 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1263 18:05:11.780298 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1264 18:05:11.783674 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1265 18:05:11.783820
1266 18:05:11.783936
1267 18:05:11.784038 ==
1268 18:05:11.786624 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 18:05:11.790145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 18:05:11.793709 ==
1271 18:05:11.793859
1272 18:05:11.793963
1273 18:05:11.794054 TX Vref Scan disable
1274 18:05:11.796927 == TX Byte 0 ==
1275 18:05:11.800509 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1276 18:05:11.803646 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1277 18:05:11.806696 == TX Byte 1 ==
1278 18:05:11.810481 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1279 18:05:11.813424 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1280 18:05:11.813562 ==
1281 18:05:11.816580 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 18:05:11.823355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 18:05:11.823511 ==
1284 18:05:11.835694 TX Vref=22, minBit 8, minWin=27, winSum=447
1285 18:05:11.839733 TX Vref=24, minBit 1, minWin=28, winSum=453
1286 18:05:11.842837 TX Vref=26, minBit 1, minWin=28, winSum=456
1287 18:05:11.846060 TX Vref=28, minBit 9, minWin=28, winSum=460
1288 18:05:11.849112 TX Vref=30, minBit 6, minWin=28, winSum=455
1289 18:05:11.852951 TX Vref=32, minBit 2, minWin=28, winSum=452
1290 18:05:11.859078 [TxChooseVref] Worse bit 9, Min win 28, Win sum 460, Final Vref 28
1291 18:05:11.859209
1292 18:05:11.862840 Final TX Range 1 Vref 28
1293 18:05:11.862993
1294 18:05:11.863103 ==
1295 18:05:11.865901 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 18:05:11.869254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 18:05:11.869386 ==
1298 18:05:11.869489
1299 18:05:11.872792
1300 18:05:11.872920 TX Vref Scan disable
1301 18:05:11.875730 == TX Byte 0 ==
1302 18:05:11.879344 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1303 18:05:11.882926 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1304 18:05:11.886007 == TX Byte 1 ==
1305 18:05:11.889119 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1306 18:05:11.892721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1307 18:05:11.895754
1308 18:05:11.895876 [DATLAT]
1309 18:05:11.895945 Freq=800, CH0 RK1
1310 18:05:11.896016
1311 18:05:11.899476 DATLAT Default: 0xa
1312 18:05:11.899572 0, 0xFFFF, sum = 0
1313 18:05:11.902403 1, 0xFFFF, sum = 0
1314 18:05:11.902496 2, 0xFFFF, sum = 0
1315 18:05:11.905986 3, 0xFFFF, sum = 0
1316 18:05:11.906127 4, 0xFFFF, sum = 0
1317 18:05:11.909609 5, 0xFFFF, sum = 0
1318 18:05:11.912494 6, 0xFFFF, sum = 0
1319 18:05:11.912621 7, 0xFFFF, sum = 0
1320 18:05:11.915914 8, 0xFFFF, sum = 0
1321 18:05:11.916020 9, 0x0, sum = 1
1322 18:05:11.916088 10, 0x0, sum = 2
1323 18:05:11.918820 11, 0x0, sum = 3
1324 18:05:11.918962 12, 0x0, sum = 4
1325 18:05:11.922449 best_step = 10
1326 18:05:11.922586
1327 18:05:11.922681 ==
1328 18:05:11.926248 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 18:05:11.929691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 18:05:11.929802 ==
1331 18:05:11.933572 RX Vref Scan: 0
1332 18:05:11.933680
1333 18:05:11.933748 RX Vref 0 -> 0, step: 1
1334 18:05:11.933809
1335 18:05:11.937428 RX Delay -95 -> 252, step: 8
1336 18:05:11.941029 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1337 18:05:11.944931 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1338 18:05:11.948912 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1339 18:05:11.952805 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1340 18:05:11.955939 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1341 18:05:11.963617 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1342 18:05:11.966732 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1343 18:05:11.969875 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1344 18:05:11.973626 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1345 18:05:11.976699 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1346 18:05:11.979801 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1347 18:05:11.987201 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1348 18:05:11.989949 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1349 18:05:11.993822 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1350 18:05:11.997215 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1351 18:05:12.000177 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1352 18:05:12.000312 ==
1353 18:05:12.003657 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 18:05:12.010370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 18:05:12.010500 ==
1356 18:05:12.010578 DQS Delay:
1357 18:05:12.013316 DQS0 = 0, DQS1 = 0
1358 18:05:12.013407 DQM Delay:
1359 18:05:12.013489 DQM0 = 93, DQM1 = 83
1360 18:05:12.017029 DQ Delay:
1361 18:05:12.019969 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1362 18:05:12.023572 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1363 18:05:12.026550 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1364 18:05:12.029947 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1365 18:05:12.030076
1366 18:05:12.030171
1367 18:05:12.036846 [DQSOSCAuto] RK1, (LSB)MR18= 0x4416, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1368 18:05:12.040395 CH0 RK1: MR19=606, MR18=4416
1369 18:05:12.046562 CH0_RK1: MR19=0x606, MR18=0x4416, DQSOSC=392, MR23=63, INC=96, DEC=64
1370 18:05:12.050431 [RxdqsGatingPostProcess] freq 800
1371 18:05:12.053147 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 18:05:12.056934 Pre-setting of DQS Precalculation
1373 18:05:12.063080 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 18:05:12.063206 ==
1375 18:05:12.066989 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 18:05:12.069871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 18:05:12.069980 ==
1378 18:05:12.076718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 18:05:12.082942 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 18:05:12.091499 [CA 0] Center 36 (6~67) winsize 62
1381 18:05:12.094662 [CA 1] Center 37 (6~68) winsize 63
1382 18:05:12.097648 [CA 2] Center 35 (4~66) winsize 63
1383 18:05:12.101201 [CA 3] Center 34 (4~65) winsize 62
1384 18:05:12.104608 [CA 4] Center 35 (5~65) winsize 61
1385 18:05:12.107986 [CA 5] Center 34 (4~64) winsize 61
1386 18:05:12.108123
1387 18:05:12.111388 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 18:05:12.111506
1389 18:05:12.114689 [CATrainingPosCal] consider 1 rank data
1390 18:05:12.117913 u2DelayCellTimex100 = 270/100 ps
1391 18:05:12.121386 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 18:05:12.124808 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1393 18:05:12.128237 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1394 18:05:12.134852 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 18:05:12.137751 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1396 18:05:12.141329 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 18:05:12.141450
1398 18:05:12.144795 CA PerBit enable=1, Macro0, CA PI delay=34
1399 18:05:12.144897
1400 18:05:12.147664 [CBTSetCACLKResult] CA Dly = 34
1401 18:05:12.147796 CS Dly: 5 (0~36)
1402 18:05:12.147869 ==
1403 18:05:12.151288 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 18:05:12.157892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 18:05:12.158069 ==
1406 18:05:12.161439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 18:05:12.167597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 18:05:12.177429 [CA 0] Center 36 (6~67) winsize 62
1409 18:05:12.180481 [CA 1] Center 37 (6~68) winsize 63
1410 18:05:12.184209 [CA 2] Center 35 (4~66) winsize 63
1411 18:05:12.187202 [CA 3] Center 34 (4~65) winsize 62
1412 18:05:12.190482 [CA 4] Center 35 (4~66) winsize 63
1413 18:05:12.193552 [CA 5] Center 34 (4~65) winsize 62
1414 18:05:12.193654
1415 18:05:12.197467 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 18:05:12.197574
1417 18:05:12.200466 [CATrainingPosCal] consider 2 rank data
1418 18:05:12.203505 u2DelayCellTimex100 = 270/100 ps
1419 18:05:12.207480 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 18:05:12.210530 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1421 18:05:12.214424 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1422 18:05:12.220685 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 18:05:12.224230 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1424 18:05:12.227085 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 18:05:12.227206
1426 18:05:12.231228 CA PerBit enable=1, Macro0, CA PI delay=34
1427 18:05:12.231363
1428 18:05:12.233914 [CBTSetCACLKResult] CA Dly = 34
1429 18:05:12.234038 CS Dly: 6 (0~39)
1430 18:05:12.234139
1431 18:05:12.237508 ----->DramcWriteLeveling(PI) begin...
1432 18:05:12.237643 ==
1433 18:05:12.240959 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 18:05:12.247137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 18:05:12.247286 ==
1436 18:05:12.250525 Write leveling (Byte 0): 28 => 28
1437 18:05:12.254339 Write leveling (Byte 1): 27 => 27
1438 18:05:12.254449 DramcWriteLeveling(PI) end<-----
1439 18:05:12.254520
1440 18:05:12.257666 ==
1441 18:05:12.260573 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 18:05:12.263854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 18:05:12.263980 ==
1444 18:05:12.267194 [Gating] SW mode calibration
1445 18:05:12.273898 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 18:05:12.277367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 18:05:12.283623 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 18:05:12.287483 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1449 18:05:12.290509 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 18:05:12.297106 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 18:05:12.301020 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 18:05:12.303994 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 18:05:12.310945 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 18:05:12.314069 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:05:12.317712 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:05:12.324553 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:05:12.327350 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:05:12.330549 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:05:12.334567 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:05:12.341104 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 18:05:12.344060 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 18:05:12.347647 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:05:12.354562 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:05:12.357565 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 18:05:12.361098 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 18:05:12.367445 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 18:05:12.371045 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 18:05:12.373941 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 18:05:12.381162 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 18:05:12.383856 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 18:05:12.387508 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:05:12.395330 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1473 18:05:12.397800 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1474 18:05:12.400774 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 18:05:12.407865 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 18:05:12.411017 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 18:05:12.413973 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 18:05:12.417923 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 18:05:12.424189 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1480 18:05:12.427544 0 10 4 | B1->B0 | 3434 2929 | 0 0 | (1 1) (0 0)
1481 18:05:12.430978 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1482 18:05:12.437890 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 18:05:12.440823 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 18:05:12.444359 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 18:05:12.450502 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 18:05:12.454388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 18:05:12.457342 0 11 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1488 18:05:12.464083 0 11 4 | B1->B0 | 2c2c 3737 | 0 1 | (1 1) (0 0)
1489 18:05:12.467219 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1490 18:05:12.470873 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 18:05:12.477649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 18:05:12.480494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 18:05:12.484132 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 18:05:12.490475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 18:05:12.494225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:05:12.497374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1497 18:05:12.503770 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 18:05:12.507736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 18:05:12.510590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 18:05:12.517872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 18:05:12.520571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 18:05:12.524191 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:05:12.527390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:05:12.534349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:05:12.538200 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:05:12.540876 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:05:12.547665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:05:12.550794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:05:12.554427 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:05:12.561403 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:05:12.564493 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 18:05:12.568225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 18:05:12.574385 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 18:05:12.574543 Total UI for P1: 0, mck2ui 16
1515 18:05:12.581429 best dqsien dly found for B0: ( 0, 14, 2)
1516 18:05:12.581567 Total UI for P1: 0, mck2ui 16
1517 18:05:12.584484 best dqsien dly found for B1: ( 0, 14, 2)
1518 18:05:12.588068 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1519 18:05:12.594727 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1520 18:05:12.594879
1521 18:05:12.597752 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1522 18:05:12.601561 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1523 18:05:12.604760 [Gating] SW calibration Done
1524 18:05:12.604920 ==
1525 18:05:12.607902 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 18:05:12.610911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 18:05:12.611027 ==
1528 18:05:12.611098 RX Vref Scan: 0
1529 18:05:12.611161
1530 18:05:12.614663 RX Vref 0 -> 0, step: 1
1531 18:05:12.614787
1532 18:05:12.617734 RX Delay -130 -> 252, step: 16
1533 18:05:12.621324 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1534 18:05:12.624330 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1535 18:05:12.631390 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1536 18:05:12.634354 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1537 18:05:12.637990 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1538 18:05:12.641198 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1539 18:05:12.644722 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1540 18:05:12.651304 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1541 18:05:12.654322 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1542 18:05:12.658116 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1543 18:05:12.661214 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1544 18:05:12.664314 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1545 18:05:12.671196 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1546 18:05:12.674820 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1547 18:05:12.677920 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1548 18:05:12.681614 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1549 18:05:12.681780 ==
1550 18:05:12.684593 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 18:05:12.688253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 18:05:12.691356 ==
1553 18:05:12.691496 DQS Delay:
1554 18:05:12.691603 DQS0 = 0, DQS1 = 0
1555 18:05:12.694412 DQM Delay:
1556 18:05:12.694547 DQM0 = 94, DQM1 = 91
1557 18:05:12.698123 DQ Delay:
1558 18:05:12.698283 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1559 18:05:12.701722 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1560 18:05:12.704771 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1561 18:05:12.711751 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1562 18:05:12.711929
1563 18:05:12.712053
1564 18:05:12.712144 ==
1565 18:05:12.714755 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 18:05:12.717831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 18:05:12.717950 ==
1568 18:05:12.718045
1569 18:05:12.718134
1570 18:05:12.721783 TX Vref Scan disable
1571 18:05:12.721898 == TX Byte 0 ==
1572 18:05:12.728665 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1573 18:05:12.731802 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1574 18:05:12.731962 == TX Byte 1 ==
1575 18:05:12.738500 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1576 18:05:12.741627 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1577 18:05:12.741767 ==
1578 18:05:12.745276 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 18:05:12.748180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 18:05:12.748330 ==
1581 18:05:12.761953 TX Vref=22, minBit 3, minWin=25, winSum=436
1582 18:05:12.765375 TX Vref=24, minBit 1, minWin=27, winSum=445
1583 18:05:12.768316 TX Vref=26, minBit 2, minWin=27, winSum=448
1584 18:05:12.772233 TX Vref=28, minBit 1, minWin=27, winSum=452
1585 18:05:12.775245 TX Vref=30, minBit 1, minWin=27, winSum=453
1586 18:05:12.778157 TX Vref=32, minBit 1, minWin=27, winSum=448
1587 18:05:12.784779 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 30
1588 18:05:12.784912
1589 18:05:12.788546 Final TX Range 1 Vref 30
1590 18:05:12.788696
1591 18:05:12.788796 ==
1592 18:05:12.791605 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 18:05:12.795581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 18:05:12.795684 ==
1595 18:05:12.795753
1596 18:05:12.795813
1597 18:05:12.798661 TX Vref Scan disable
1598 18:05:12.801677 == TX Byte 0 ==
1599 18:05:12.805470 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 18:05:12.808283 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1601 18:05:12.811829 == TX Byte 1 ==
1602 18:05:12.815489 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1603 18:05:12.818489 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1604 18:05:12.818625
1605 18:05:12.821629 [DATLAT]
1606 18:05:12.821732 Freq=800, CH1 RK0
1607 18:05:12.821801
1608 18:05:12.825372 DATLAT Default: 0xa
1609 18:05:12.825502 0, 0xFFFF, sum = 0
1610 18:05:12.828651 1, 0xFFFF, sum = 0
1611 18:05:12.828753 2, 0xFFFF, sum = 0
1612 18:05:12.832440 3, 0xFFFF, sum = 0
1613 18:05:12.832556 4, 0xFFFF, sum = 0
1614 18:05:12.835329 5, 0xFFFF, sum = 0
1615 18:05:12.835453 6, 0xFFFF, sum = 0
1616 18:05:12.838985 7, 0xFFFF, sum = 0
1617 18:05:12.839118 8, 0xFFFF, sum = 0
1618 18:05:12.842227 9, 0x0, sum = 1
1619 18:05:12.842364 10, 0x0, sum = 2
1620 18:05:12.845064 11, 0x0, sum = 3
1621 18:05:12.845158 12, 0x0, sum = 4
1622 18:05:12.848877 best_step = 10
1623 18:05:12.848980
1624 18:05:12.849049 ==
1625 18:05:12.851717 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 18:05:12.855566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 18:05:12.855689 ==
1628 18:05:12.858638 RX Vref Scan: 1
1629 18:05:12.858755
1630 18:05:12.858850 Set Vref Range= 32 -> 127
1631 18:05:12.858959
1632 18:05:12.862251 RX Vref 32 -> 127, step: 1
1633 18:05:12.862389
1634 18:05:12.865265 RX Delay -63 -> 252, step: 8
1635 18:05:12.865380
1636 18:05:12.868949 Set Vref, RX VrefLevel [Byte0]: 32
1637 18:05:12.871775 [Byte1]: 32
1638 18:05:12.871896
1639 18:05:12.875637 Set Vref, RX VrefLevel [Byte0]: 33
1640 18:05:12.878817 [Byte1]: 33
1641 18:05:12.878956
1642 18:05:12.882275 Set Vref, RX VrefLevel [Byte0]: 34
1643 18:05:12.885076 [Byte1]: 34
1644 18:05:12.889277
1645 18:05:12.889445 Set Vref, RX VrefLevel [Byte0]: 35
1646 18:05:12.892751 [Byte1]: 35
1647 18:05:12.896552
1648 18:05:12.896666 Set Vref, RX VrefLevel [Byte0]: 36
1649 18:05:12.900440 [Byte1]: 36
1650 18:05:12.904270
1651 18:05:12.904424 Set Vref, RX VrefLevel [Byte0]: 37
1652 18:05:12.907329 [Byte1]: 37
1653 18:05:12.911638
1654 18:05:12.911756 Set Vref, RX VrefLevel [Byte0]: 38
1655 18:05:12.915533 [Byte1]: 38
1656 18:05:12.919101
1657 18:05:12.919244 Set Vref, RX VrefLevel [Byte0]: 39
1658 18:05:12.922710 [Byte1]: 39
1659 18:05:12.927071
1660 18:05:12.927214 Set Vref, RX VrefLevel [Byte0]: 40
1661 18:05:12.930024 [Byte1]: 40
1662 18:05:12.934420
1663 18:05:12.934566 Set Vref, RX VrefLevel [Byte0]: 41
1664 18:05:12.937520 [Byte1]: 41
1665 18:05:12.941994
1666 18:05:12.942147 Set Vref, RX VrefLevel [Byte0]: 42
1667 18:05:12.944926 [Byte1]: 42
1668 18:05:12.949503
1669 18:05:12.949622 Set Vref, RX VrefLevel [Byte0]: 43
1670 18:05:12.952530 [Byte1]: 43
1671 18:05:12.957065
1672 18:05:12.957193 Set Vref, RX VrefLevel [Byte0]: 44
1673 18:05:12.960081 [Byte1]: 44
1674 18:05:12.964037
1675 18:05:12.964180 Set Vref, RX VrefLevel [Byte0]: 45
1676 18:05:12.968015 [Byte1]: 45
1677 18:05:12.971823
1678 18:05:12.971945 Set Vref, RX VrefLevel [Byte0]: 46
1679 18:05:12.974971 [Byte1]: 46
1680 18:05:12.979477
1681 18:05:12.979600 Set Vref, RX VrefLevel [Byte0]: 47
1682 18:05:12.982482 [Byte1]: 47
1683 18:05:12.986623
1684 18:05:12.986745 Set Vref, RX VrefLevel [Byte0]: 48
1685 18:05:12.990061 [Byte1]: 48
1686 18:05:12.994842
1687 18:05:12.994990 Set Vref, RX VrefLevel [Byte0]: 49
1688 18:05:12.997336 [Byte1]: 49
1689 18:05:13.001637
1690 18:05:13.001786 Set Vref, RX VrefLevel [Byte0]: 50
1691 18:05:13.004999 [Byte1]: 50
1692 18:05:13.009200
1693 18:05:13.009368 Set Vref, RX VrefLevel [Byte0]: 51
1694 18:05:13.012701 [Byte1]: 51
1695 18:05:13.016780
1696 18:05:13.016920 Set Vref, RX VrefLevel [Byte0]: 52
1697 18:05:13.019900 [Byte1]: 52
1698 18:05:13.024448
1699 18:05:13.024599 Set Vref, RX VrefLevel [Byte0]: 53
1700 18:05:13.027472 [Byte1]: 53
1701 18:05:13.032080
1702 18:05:13.032231 Set Vref, RX VrefLevel [Byte0]: 54
1703 18:05:13.034959 [Byte1]: 54
1704 18:05:13.039124
1705 18:05:13.039290 Set Vref, RX VrefLevel [Byte0]: 55
1706 18:05:13.042582 [Byte1]: 55
1707 18:05:13.046571
1708 18:05:13.046738 Set Vref, RX VrefLevel [Byte0]: 56
1709 18:05:13.050371 [Byte1]: 56
1710 18:05:13.054138
1711 18:05:13.054303 Set Vref, RX VrefLevel [Byte0]: 57
1712 18:05:13.057651 [Byte1]: 57
1713 18:05:13.061794
1714 18:05:13.061913 Set Vref, RX VrefLevel [Byte0]: 58
1715 18:05:13.065468 [Byte1]: 58
1716 18:05:13.069285
1717 18:05:13.069400 Set Vref, RX VrefLevel [Byte0]: 59
1718 18:05:13.072368 [Byte1]: 59
1719 18:05:13.076972
1720 18:05:13.077094 Set Vref, RX VrefLevel [Byte0]: 60
1721 18:05:13.080180 [Byte1]: 60
1722 18:05:13.083969
1723 18:05:13.084082 Set Vref, RX VrefLevel [Byte0]: 61
1724 18:05:13.087092 [Byte1]: 61
1725 18:05:13.091699
1726 18:05:13.091815 Set Vref, RX VrefLevel [Byte0]: 62
1727 18:05:13.094797 [Byte1]: 62
1728 18:05:13.099340
1729 18:05:13.099485 Set Vref, RX VrefLevel [Byte0]: 63
1730 18:05:13.102293 [Byte1]: 63
1731 18:05:13.106504
1732 18:05:13.106658 Set Vref, RX VrefLevel [Byte0]: 64
1733 18:05:13.109988 [Byte1]: 64
1734 18:05:13.114432
1735 18:05:13.114582 Set Vref, RX VrefLevel [Byte0]: 65
1736 18:05:13.117285 [Byte1]: 65
1737 18:05:13.121902
1738 18:05:13.122070 Set Vref, RX VrefLevel [Byte0]: 66
1739 18:05:13.125498 [Byte1]: 66
1740 18:05:13.129416
1741 18:05:13.129586 Set Vref, RX VrefLevel [Byte0]: 67
1742 18:05:13.132860 [Byte1]: 67
1743 18:05:13.137178
1744 18:05:13.137341 Set Vref, RX VrefLevel [Byte0]: 68
1745 18:05:13.140290 [Byte1]: 68
1746 18:05:13.144186
1747 18:05:13.144365 Set Vref, RX VrefLevel [Byte0]: 69
1748 18:05:13.147776 [Byte1]: 69
1749 18:05:13.151472
1750 18:05:13.151609 Set Vref, RX VrefLevel [Byte0]: 70
1751 18:05:13.154931 [Byte1]: 70
1752 18:05:13.159191
1753 18:05:13.159329 Set Vref, RX VrefLevel [Byte0]: 71
1754 18:05:13.162396 [Byte1]: 71
1755 18:05:13.166547
1756 18:05:13.166687 Final RX Vref Byte 0 = 60 to rank0
1757 18:05:13.169748 Final RX Vref Byte 1 = 54 to rank0
1758 18:05:13.173773 Final RX Vref Byte 0 = 60 to rank1
1759 18:05:13.176718 Final RX Vref Byte 1 = 54 to rank1==
1760 18:05:13.179849 Dram Type= 6, Freq= 0, CH_1, rank 0
1761 18:05:13.186806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1762 18:05:13.186934 ==
1763 18:05:13.187009 DQS Delay:
1764 18:05:13.187072 DQS0 = 0, DQS1 = 0
1765 18:05:13.189802 DQM Delay:
1766 18:05:13.189896 DQM0 = 95, DQM1 = 90
1767 18:05:13.193698 DQ Delay:
1768 18:05:13.196803 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1769 18:05:13.199946 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
1770 18:05:13.203723 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1771 18:05:13.206719 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1772 18:05:13.206854
1773 18:05:13.206950
1774 18:05:13.213084 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1775 18:05:13.216769 CH1 RK0: MR19=606, MR18=2D49
1776 18:05:13.223829 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1777 18:05:13.223997
1778 18:05:13.226807 ----->DramcWriteLeveling(PI) begin...
1779 18:05:13.226955 ==
1780 18:05:13.229952 Dram Type= 6, Freq= 0, CH_1, rank 1
1781 18:05:13.233637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 18:05:13.233751 ==
1783 18:05:13.236587 Write leveling (Byte 0): 29 => 29
1784 18:05:13.240231 Write leveling (Byte 1): 30 => 30
1785 18:05:13.243816 DramcWriteLeveling(PI) end<-----
1786 18:05:13.243959
1787 18:05:13.244071 ==
1788 18:05:13.246630 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 18:05:13.249997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 18:05:13.250140 ==
1791 18:05:13.253059 [Gating] SW mode calibration
1792 18:05:13.259860 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1793 18:05:13.266652 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1794 18:05:13.269708 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1795 18:05:13.273612 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1796 18:05:13.280331 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 18:05:13.283779 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 18:05:13.286461 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 18:05:13.293328 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 18:05:13.296803 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 18:05:13.299745 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 18:05:13.306574 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 18:05:13.309678 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 18:05:13.313510 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 18:05:13.320011 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 18:05:13.323520 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 18:05:13.326373 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 18:05:13.333522 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 18:05:13.336347 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 18:05:13.340029 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1811 18:05:13.343750 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1812 18:05:13.350233 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 18:05:13.353735 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 18:05:13.356534 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 18:05:13.363525 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 18:05:13.366655 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 18:05:13.370237 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 18:05:13.376470 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 18:05:13.380435 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1820 18:05:13.383522 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1821 18:05:13.390479 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 18:05:13.393569 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 18:05:13.396595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 18:05:13.403235 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 18:05:13.406753 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 18:05:13.410172 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1827 18:05:13.417002 0 10 4 | B1->B0 | 2a2a 3131 | 0 0 | (1 0) (1 0)
1828 18:05:13.419869 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1829 18:05:13.423752 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 18:05:13.426679 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:05:13.434122 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 18:05:13.437022 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 18:05:13.439999 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 18:05:13.447293 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1835 18:05:13.450106 0 11 4 | B1->B0 | 3c3c 2929 | 0 0 | (1 1) (0 0)
1836 18:05:13.453853 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1837 18:05:13.460048 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 18:05:13.463973 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 18:05:13.466725 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 18:05:13.473878 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 18:05:13.476756 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 18:05:13.480301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1843 18:05:13.487221 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1844 18:05:13.490366 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 18:05:13.493548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 18:05:13.500889 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 18:05:13.503828 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 18:05:13.507092 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 18:05:13.510074 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 18:05:13.516866 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 18:05:13.520177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 18:05:13.523369 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 18:05:13.530155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 18:05:13.533418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 18:05:13.536797 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 18:05:13.543730 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 18:05:13.547396 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 18:05:13.550283 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 18:05:13.557438 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1860 18:05:13.560733 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 18:05:13.563715 Total UI for P1: 0, mck2ui 16
1862 18:05:13.567372 best dqsien dly found for B0: ( 0, 14, 4)
1863 18:05:13.570449 Total UI for P1: 0, mck2ui 16
1864 18:05:13.573453 best dqsien dly found for B1: ( 0, 14, 4)
1865 18:05:13.576954 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1866 18:05:13.580489 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1867 18:05:13.580640
1868 18:05:13.583405 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1869 18:05:13.586902 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1870 18:05:13.590517 [Gating] SW calibration Done
1871 18:05:13.590670 ==
1872 18:05:13.593389 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 18:05:13.597349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 18:05:13.597493 ==
1875 18:05:13.600366 RX Vref Scan: 0
1876 18:05:13.600486
1877 18:05:13.604049 RX Vref 0 -> 0, step: 1
1878 18:05:13.604179
1879 18:05:13.604279 RX Delay -130 -> 252, step: 16
1880 18:05:13.610421 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1881 18:05:13.613335 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1882 18:05:13.617518 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1883 18:05:13.620590 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1884 18:05:13.623569 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1885 18:05:13.630610 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1886 18:05:13.633579 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1887 18:05:13.637226 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1888 18:05:13.640174 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1889 18:05:13.643910 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1890 18:05:13.650364 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1891 18:05:13.653861 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1892 18:05:13.657400 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1893 18:05:13.660181 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1894 18:05:13.663831 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1895 18:05:13.670357 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1896 18:05:13.670512 ==
1897 18:05:13.674165 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 18:05:13.676855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 18:05:13.677020 ==
1900 18:05:13.677128 DQS Delay:
1901 18:05:13.680299 DQS0 = 0, DQS1 = 0
1902 18:05:13.680433 DQM Delay:
1903 18:05:13.684243 DQM0 = 93, DQM1 = 90
1904 18:05:13.684383 DQ Delay:
1905 18:05:13.687168 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1906 18:05:13.690385 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1907 18:05:13.693892 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1908 18:05:13.696866 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1909 18:05:13.697011
1910 18:05:13.697112
1911 18:05:13.697209 ==
1912 18:05:13.700521 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 18:05:13.704249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 18:05:13.704404 ==
1915 18:05:13.707424
1916 18:05:13.707549
1917 18:05:13.707649 TX Vref Scan disable
1918 18:05:13.710372 == TX Byte 0 ==
1919 18:05:13.713497 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1920 18:05:13.717367 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1921 18:05:13.720399 == TX Byte 1 ==
1922 18:05:13.723414 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1923 18:05:13.727067 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1924 18:05:13.727169 ==
1925 18:05:13.730140 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 18:05:13.737116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 18:05:13.737263 ==
1928 18:05:13.748914 TX Vref=22, minBit 1, minWin=27, winSum=444
1929 18:05:13.752522 TX Vref=24, minBit 0, minWin=27, winSum=446
1930 18:05:13.756139 TX Vref=26, minBit 2, minWin=27, winSum=449
1931 18:05:13.759042 TX Vref=28, minBit 2, minWin=27, winSum=454
1932 18:05:13.762729 TX Vref=30, minBit 2, minWin=27, winSum=451
1933 18:05:13.766143 TX Vref=32, minBit 0, minWin=27, winSum=446
1934 18:05:13.772737 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1935 18:05:13.772902
1936 18:05:13.775839 Final TX Range 1 Vref 28
1937 18:05:13.775977
1938 18:05:13.776084 ==
1939 18:05:13.779572 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 18:05:13.782423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 18:05:13.782561 ==
1942 18:05:13.782662
1943 18:05:13.782755
1944 18:05:13.785982 TX Vref Scan disable
1945 18:05:13.789354 == TX Byte 0 ==
1946 18:05:13.792505 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1947 18:05:13.795877 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1948 18:05:13.799478 == TX Byte 1 ==
1949 18:05:13.802625 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 18:05:13.806211 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 18:05:13.806378
1952 18:05:13.809677 [DATLAT]
1953 18:05:13.809815 Freq=800, CH1 RK1
1954 18:05:13.809915
1955 18:05:13.812411 DATLAT Default: 0xa
1956 18:05:13.812534 0, 0xFFFF, sum = 0
1957 18:05:13.815861 1, 0xFFFF, sum = 0
1958 18:05:13.815999 2, 0xFFFF, sum = 0
1959 18:05:13.819951 3, 0xFFFF, sum = 0
1960 18:05:13.820096 4, 0xFFFF, sum = 0
1961 18:05:13.822840 5, 0xFFFF, sum = 0
1962 18:05:13.822976 6, 0xFFFF, sum = 0
1963 18:05:13.826017 7, 0xFFFF, sum = 0
1964 18:05:13.826138 8, 0xFFFF, sum = 0
1965 18:05:13.829017 9, 0x0, sum = 1
1966 18:05:13.829144 10, 0x0, sum = 2
1967 18:05:13.832986 11, 0x0, sum = 3
1968 18:05:13.833114 12, 0x0, sum = 4
1969 18:05:13.835923 best_step = 10
1970 18:05:13.836040
1971 18:05:13.836137 ==
1972 18:05:13.839746 Dram Type= 6, Freq= 0, CH_1, rank 1
1973 18:05:13.842857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1974 18:05:13.842987 ==
1975 18:05:13.845794 RX Vref Scan: 0
1976 18:05:13.845918
1977 18:05:13.846013 RX Vref 0 -> 0, step: 1
1978 18:05:13.846106
1979 18:05:13.849543 RX Delay -63 -> 252, step: 8
1980 18:05:13.852594 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1981 18:05:13.859791 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1982 18:05:13.862837 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1983 18:05:13.865923 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1984 18:05:13.869729 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1985 18:05:13.873277 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1986 18:05:13.876359 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1987 18:05:13.883083 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1988 18:05:13.886153 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1989 18:05:13.889442 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1990 18:05:13.893250 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1991 18:05:13.896219 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1992 18:05:13.903418 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1993 18:05:13.906303 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1994 18:05:13.909862 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1995 18:05:13.913372 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1996 18:05:13.913515 ==
1997 18:05:13.916639 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 18:05:13.920000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 18:05:13.920137 ==
2000 18:05:13.922811 DQS Delay:
2001 18:05:13.922938 DQS0 = 0, DQS1 = 0
2002 18:05:13.926336 DQM Delay:
2003 18:05:13.926461 DQM0 = 96, DQM1 = 90
2004 18:05:13.926564 DQ Delay:
2005 18:05:13.929690 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2006 18:05:13.933351 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2007 18:05:13.936094 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2008 18:05:13.940069 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2009 18:05:13.943051
2010 18:05:13.943162
2011 18:05:13.950029 [DQSOSCAuto] RK1, (LSB)MR18= 0x4811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2012 18:05:13.953133 CH1 RK1: MR19=606, MR18=4811
2013 18:05:13.959903 CH1_RK1: MR19=0x606, MR18=0x4811, DQSOSC=391, MR23=63, INC=96, DEC=64
2014 18:05:13.960051 [RxdqsGatingPostProcess] freq 800
2015 18:05:13.966638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2016 18:05:13.970126 Pre-setting of DQS Precalculation
2017 18:05:13.973313 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2018 18:05:13.983742 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2019 18:05:13.990179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2020 18:05:13.990311
2021 18:05:13.990383
2022 18:05:13.993751 [Calibration Summary] 1600 Mbps
2023 18:05:13.993854 CH 0, Rank 0
2024 18:05:13.996678 SW Impedance : PASS
2025 18:05:13.996790 DUTY Scan : NO K
2026 18:05:14.000739 ZQ Calibration : PASS
2027 18:05:14.003573 Jitter Meter : NO K
2028 18:05:14.003671 CBT Training : PASS
2029 18:05:14.007267 Write leveling : PASS
2030 18:05:14.010136 RX DQS gating : PASS
2031 18:05:14.010249 RX DQ/DQS(RDDQC) : PASS
2032 18:05:14.013804 TX DQ/DQS : PASS
2033 18:05:14.016900 RX DATLAT : PASS
2034 18:05:14.017013 RX DQ/DQS(Engine): PASS
2035 18:05:14.020928 TX OE : NO K
2036 18:05:14.021032 All Pass.
2037 18:05:14.021099
2038 18:05:14.021161 CH 0, Rank 1
2039 18:05:14.023650 SW Impedance : PASS
2040 18:05:14.027393 DUTY Scan : NO K
2041 18:05:14.027494 ZQ Calibration : PASS
2042 18:05:14.030111 Jitter Meter : NO K
2043 18:05:14.033941 CBT Training : PASS
2044 18:05:14.034048 Write leveling : PASS
2045 18:05:14.036806 RX DQS gating : PASS
2046 18:05:14.040542 RX DQ/DQS(RDDQC) : PASS
2047 18:05:14.040649 TX DQ/DQS : PASS
2048 18:05:14.043997 RX DATLAT : PASS
2049 18:05:14.046993 RX DQ/DQS(Engine): PASS
2050 18:05:14.047102 TX OE : NO K
2051 18:05:14.050652 All Pass.
2052 18:05:14.050758
2053 18:05:14.050826 CH 1, Rank 0
2054 18:05:14.053713 SW Impedance : PASS
2055 18:05:14.053801 DUTY Scan : NO K
2056 18:05:14.056778 ZQ Calibration : PASS
2057 18:05:14.060707 Jitter Meter : NO K
2058 18:05:14.060811 CBT Training : PASS
2059 18:05:14.063682 Write leveling : PASS
2060 18:05:14.063785 RX DQS gating : PASS
2061 18:05:14.067405 RX DQ/DQS(RDDQC) : PASS
2062 18:05:14.070320 TX DQ/DQS : PASS
2063 18:05:14.070459 RX DATLAT : PASS
2064 18:05:14.074233 RX DQ/DQS(Engine): PASS
2065 18:05:14.077039 TX OE : NO K
2066 18:05:14.077177 All Pass.
2067 18:05:14.077248
2068 18:05:14.077312 CH 1, Rank 1
2069 18:05:14.080859 SW Impedance : PASS
2070 18:05:14.084018 DUTY Scan : NO K
2071 18:05:14.084151 ZQ Calibration : PASS
2072 18:05:14.087087 Jitter Meter : NO K
2073 18:05:14.090228 CBT Training : PASS
2074 18:05:14.090377 Write leveling : PASS
2075 18:05:14.093864 RX DQS gating : PASS
2076 18:05:14.097449 RX DQ/DQS(RDDQC) : PASS
2077 18:05:14.097595 TX DQ/DQS : PASS
2078 18:05:14.100330 RX DATLAT : PASS
2079 18:05:14.100466 RX DQ/DQS(Engine): PASS
2080 18:05:14.103690 TX OE : NO K
2081 18:05:14.103821 All Pass.
2082 18:05:14.103891
2083 18:05:14.107106 DramC Write-DBI off
2084 18:05:14.110185 PER_BANK_REFRESH: Hybrid Mode
2085 18:05:14.110318 TX_TRACKING: ON
2086 18:05:14.113984 [GetDramInforAfterCalByMRR] Vendor 6.
2087 18:05:14.117428 [GetDramInforAfterCalByMRR] Revision 606.
2088 18:05:14.120324 [GetDramInforAfterCalByMRR] Revision 2 0.
2089 18:05:14.123519 MR0 0x3b3b
2090 18:05:14.123628 MR8 0x5151
2091 18:05:14.127394 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2092 18:05:14.127519
2093 18:05:14.130359 MR0 0x3b3b
2094 18:05:14.130480 MR8 0x5151
2095 18:05:14.134008 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 18:05:14.134116
2097 18:05:14.144373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2098 18:05:14.147286 [FAST_K] Save calibration result to emmc
2099 18:05:14.150816 [FAST_K] Save calibration result to emmc
2100 18:05:14.150956 dram_init: config_dvfs: 1
2101 18:05:14.157452 dramc_set_vcore_voltage set vcore to 662500
2102 18:05:14.157614 Read voltage for 1200, 2
2103 18:05:14.160487 Vio18 = 0
2104 18:05:14.160592 Vcore = 662500
2105 18:05:14.160660 Vdram = 0
2106 18:05:14.163812 Vddq = 0
2107 18:05:14.163914 Vmddr = 0
2108 18:05:14.167543 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2109 18:05:14.174475 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2110 18:05:14.177504 MEM_TYPE=3, freq_sel=15
2111 18:05:14.180594 sv_algorithm_assistance_LP4_1600
2112 18:05:14.183765 ============ PULL DRAM RESETB DOWN ============
2113 18:05:14.187381 ========== PULL DRAM RESETB DOWN end =========
2114 18:05:14.190567 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2115 18:05:14.194419 ===================================
2116 18:05:14.197573 LPDDR4 DRAM CONFIGURATION
2117 18:05:14.200488 ===================================
2118 18:05:14.204259 EX_ROW_EN[0] = 0x0
2119 18:05:14.204381 EX_ROW_EN[1] = 0x0
2120 18:05:14.207493 LP4Y_EN = 0x0
2121 18:05:14.207612 WORK_FSP = 0x0
2122 18:05:14.210899 WL = 0x4
2123 18:05:14.211056 RL = 0x4
2124 18:05:14.213831 BL = 0x2
2125 18:05:14.213937 RPST = 0x0
2126 18:05:14.217205 RD_PRE = 0x0
2127 18:05:14.217309 WR_PRE = 0x1
2128 18:05:14.221176 WR_PST = 0x0
2129 18:05:14.221285 DBI_WR = 0x0
2130 18:05:14.224030 DBI_RD = 0x0
2131 18:05:14.227454 OTF = 0x1
2132 18:05:14.227560 ===================================
2133 18:05:14.230463 ===================================
2134 18:05:14.234131 ANA top config
2135 18:05:14.237094 ===================================
2136 18:05:14.240773 DLL_ASYNC_EN = 0
2137 18:05:14.240883 ALL_SLAVE_EN = 0
2138 18:05:14.243839 NEW_RANK_MODE = 1
2139 18:05:14.247302 DLL_IDLE_MODE = 1
2140 18:05:14.250926 LP45_APHY_COMB_EN = 1
2141 18:05:14.251068 TX_ODT_DIS = 1
2142 18:05:14.254160 NEW_8X_MODE = 1
2143 18:05:14.257705 ===================================
2144 18:05:14.260656 ===================================
2145 18:05:14.264422 data_rate = 2400
2146 18:05:14.267382 CKR = 1
2147 18:05:14.270408 DQ_P2S_RATIO = 8
2148 18:05:14.274299 ===================================
2149 18:05:14.277126 CA_P2S_RATIO = 8
2150 18:05:14.277244 DQ_CA_OPEN = 0
2151 18:05:14.280882 DQ_SEMI_OPEN = 0
2152 18:05:14.284005 CA_SEMI_OPEN = 0
2153 18:05:14.287101 CA_FULL_RATE = 0
2154 18:05:14.291176 DQ_CKDIV4_EN = 0
2155 18:05:14.293944 CA_CKDIV4_EN = 0
2156 18:05:14.294037 CA_PREDIV_EN = 0
2157 18:05:14.297810 PH8_DLY = 17
2158 18:05:14.300834 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2159 18:05:14.303964 DQ_AAMCK_DIV = 4
2160 18:05:14.307647 CA_AAMCK_DIV = 4
2161 18:05:14.310475 CA_ADMCK_DIV = 4
2162 18:05:14.310619 DQ_TRACK_CA_EN = 0
2163 18:05:14.314299 CA_PICK = 1200
2164 18:05:14.317332 CA_MCKIO = 1200
2165 18:05:14.321016 MCKIO_SEMI = 0
2166 18:05:14.323888 PLL_FREQ = 2366
2167 18:05:14.327734 DQ_UI_PI_RATIO = 32
2168 18:05:14.330760 CA_UI_PI_RATIO = 0
2169 18:05:14.334335 ===================================
2170 18:05:14.337281 ===================================
2171 18:05:14.337386 memory_type:LPDDR4
2172 18:05:14.340797 GP_NUM : 10
2173 18:05:14.344307 SRAM_EN : 1
2174 18:05:14.344461 MD32_EN : 0
2175 18:05:14.347571 ===================================
2176 18:05:14.351377 [ANA_INIT] >>>>>>>>>>>>>>
2177 18:05:14.354099 <<<<<< [CONFIGURE PHASE]: ANA_TX
2178 18:05:14.357135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2179 18:05:14.360725 ===================================
2180 18:05:14.360838 data_rate = 2400,PCW = 0X5b00
2181 18:05:14.364209 ===================================
2182 18:05:14.370905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2183 18:05:14.373892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2184 18:05:14.380642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 18:05:14.384440 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2186 18:05:14.387463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2187 18:05:14.391362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2188 18:05:14.394388 [ANA_INIT] flow start
2189 18:05:14.394525 [ANA_INIT] PLL >>>>>>>>
2190 18:05:14.397543 [ANA_INIT] PLL <<<<<<<<
2191 18:05:14.401243 [ANA_INIT] MIDPI >>>>>>>>
2192 18:05:14.404065 [ANA_INIT] MIDPI <<<<<<<<
2193 18:05:14.404206 [ANA_INIT] DLL >>>>>>>>
2194 18:05:14.407928 [ANA_INIT] DLL <<<<<<<<
2195 18:05:14.410974 [ANA_INIT] flow end
2196 18:05:14.414635 ============ LP4 DIFF to SE enter ============
2197 18:05:14.417528 ============ LP4 DIFF to SE exit ============
2198 18:05:14.420728 [ANA_INIT] <<<<<<<<<<<<<
2199 18:05:14.424449 [Flow] Enable top DCM control >>>>>
2200 18:05:14.427566 [Flow] Enable top DCM control <<<<<
2201 18:05:14.431200 Enable DLL master slave shuffle
2202 18:05:14.434273 ==============================================================
2203 18:05:14.437273 Gating Mode config
2204 18:05:14.441099 ==============================================================
2205 18:05:14.444139 Config description:
2206 18:05:14.454299 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2207 18:05:14.461165 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2208 18:05:14.464142 SELPH_MODE 0: By rank 1: By Phase
2209 18:05:14.471331 ==============================================================
2210 18:05:14.474020 GAT_TRACK_EN = 1
2211 18:05:14.477727 RX_GATING_MODE = 2
2212 18:05:14.481526 RX_GATING_TRACK_MODE = 2
2213 18:05:14.484395 SELPH_MODE = 1
2214 18:05:14.484531 PICG_EARLY_EN = 1
2215 18:05:14.487940 VALID_LAT_VALUE = 1
2216 18:05:14.494258 ==============================================================
2217 18:05:14.497312 Enter into Gating configuration >>>>
2218 18:05:14.501384 Exit from Gating configuration <<<<
2219 18:05:14.504412 Enter into DVFS_PRE_config >>>>>
2220 18:05:14.514197 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2221 18:05:14.517864 Exit from DVFS_PRE_config <<<<<
2222 18:05:14.520757 Enter into PICG configuration >>>>
2223 18:05:14.524609 Exit from PICG configuration <<<<
2224 18:05:14.527686 [RX_INPUT] configuration >>>>>
2225 18:05:14.531323 [RX_INPUT] configuration <<<<<
2226 18:05:14.534231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2227 18:05:14.540928 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2228 18:05:14.547817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2229 18:05:14.554140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2230 18:05:14.557703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 18:05:14.564913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 18:05:14.571035 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2233 18:05:14.574636 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2234 18:05:14.577525 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2235 18:05:14.581126 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2236 18:05:14.584433 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2237 18:05:14.591305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2238 18:05:14.594455 ===================================
2239 18:05:14.597478 LPDDR4 DRAM CONFIGURATION
2240 18:05:14.600986 ===================================
2241 18:05:14.601147 EX_ROW_EN[0] = 0x0
2242 18:05:14.604186 EX_ROW_EN[1] = 0x0
2243 18:05:14.604312 LP4Y_EN = 0x0
2244 18:05:14.607765 WORK_FSP = 0x0
2245 18:05:14.607908 WL = 0x4
2246 18:05:14.610836 RL = 0x4
2247 18:05:14.611026 BL = 0x2
2248 18:05:14.614688 RPST = 0x0
2249 18:05:14.614824 RD_PRE = 0x0
2250 18:05:14.617608 WR_PRE = 0x1
2251 18:05:14.617736 WR_PST = 0x0
2252 18:05:14.621412 DBI_WR = 0x0
2253 18:05:14.621536 DBI_RD = 0x0
2254 18:05:14.624500 OTF = 0x1
2255 18:05:14.627928 ===================================
2256 18:05:14.630984 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2257 18:05:14.634009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2258 18:05:14.640735 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 18:05:14.644424 ===================================
2260 18:05:14.644580 LPDDR4 DRAM CONFIGURATION
2261 18:05:14.647496 ===================================
2262 18:05:14.651311 EX_ROW_EN[0] = 0x10
2263 18:05:14.654459 EX_ROW_EN[1] = 0x0
2264 18:05:14.654563 LP4Y_EN = 0x0
2265 18:05:14.657359 WORK_FSP = 0x0
2266 18:05:14.657456 WL = 0x4
2267 18:05:14.661017 RL = 0x4
2268 18:05:14.661108 BL = 0x2
2269 18:05:14.664067 RPST = 0x0
2270 18:05:14.664159 RD_PRE = 0x0
2271 18:05:14.667769 WR_PRE = 0x1
2272 18:05:14.667889 WR_PST = 0x0
2273 18:05:14.671452 DBI_WR = 0x0
2274 18:05:14.671570 DBI_RD = 0x0
2275 18:05:14.674148 OTF = 0x1
2276 18:05:14.677281 ===================================
2277 18:05:14.684464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2278 18:05:14.684588 ==
2279 18:05:14.687979 Dram Type= 6, Freq= 0, CH_0, rank 0
2280 18:05:14.690890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2281 18:05:14.690984 ==
2282 18:05:14.693966 [Duty_Offset_Calibration]
2283 18:05:14.694052 B0:2 B1:1 CA:1
2284 18:05:14.694118
2285 18:05:14.697709 [DutyScan_Calibration_Flow] k_type=0
2286 18:05:14.707743
2287 18:05:14.707865 ==CLK 0==
2288 18:05:14.710969 Final CLK duty delay cell = 0
2289 18:05:14.714506 [0] MAX Duty = 5187%(X100), DQS PI = 24
2290 18:05:14.717625 [0] MIN Duty = 4844%(X100), DQS PI = 48
2291 18:05:14.717736 [0] AVG Duty = 5015%(X100)
2292 18:05:14.720657
2293 18:05:14.724300 CH0 CLK Duty spec in!! Max-Min= 343%
2294 18:05:14.727903 [DutyScan_Calibration_Flow] ====Done====
2295 18:05:14.728016
2296 18:05:14.730811 [DutyScan_Calibration_Flow] k_type=1
2297 18:05:14.746029
2298 18:05:14.746174 ==DQS 0 ==
2299 18:05:14.749582 Final DQS duty delay cell = -4
2300 18:05:14.752882 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2301 18:05:14.756352 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2302 18:05:14.759311 [-4] AVG Duty = 4937%(X100)
2303 18:05:14.759399
2304 18:05:14.759469 ==DQS 1 ==
2305 18:05:14.762858 Final DQS duty delay cell = 0
2306 18:05:14.766472 [0] MAX Duty = 5156%(X100), DQS PI = 62
2307 18:05:14.769588 [0] MIN Duty = 5000%(X100), DQS PI = 32
2308 18:05:14.773365 [0] AVG Duty = 5078%(X100)
2309 18:05:14.773467
2310 18:05:14.776164 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2311 18:05:14.776249
2312 18:05:14.779697 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2313 18:05:14.783214 [DutyScan_Calibration_Flow] ====Done====
2314 18:05:14.783342
2315 18:05:14.786127 [DutyScan_Calibration_Flow] k_type=3
2316 18:05:14.802857
2317 18:05:14.803002 ==DQM 0 ==
2318 18:05:14.806306 Final DQM duty delay cell = 0
2319 18:05:14.809355 [0] MAX Duty = 5156%(X100), DQS PI = 30
2320 18:05:14.813148 [0] MIN Duty = 4906%(X100), DQS PI = 52
2321 18:05:14.816581 [0] AVG Duty = 5031%(X100)
2322 18:05:14.816683
2323 18:05:14.816749 ==DQM 1 ==
2324 18:05:14.819442 Final DQM duty delay cell = 0
2325 18:05:14.822713 [0] MAX Duty = 5093%(X100), DQS PI = 0
2326 18:05:14.826449 [0] MIN Duty = 5031%(X100), DQS PI = 2
2327 18:05:14.826568 [0] AVG Duty = 5062%(X100)
2328 18:05:14.829358
2329 18:05:14.833012 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2330 18:05:14.833110
2331 18:05:14.836529 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2332 18:05:14.839925 [DutyScan_Calibration_Flow] ====Done====
2333 18:05:14.840047
2334 18:05:14.842745 [DutyScan_Calibration_Flow] k_type=2
2335 18:05:14.859449
2336 18:05:14.859587 ==DQ 0 ==
2337 18:05:14.863184 Final DQ duty delay cell = 0
2338 18:05:14.866110 [0] MAX Duty = 5062%(X100), DQS PI = 32
2339 18:05:14.869182 [0] MIN Duty = 4844%(X100), DQS PI = 62
2340 18:05:14.869272 [0] AVG Duty = 4953%(X100)
2341 18:05:14.872640
2342 18:05:14.872721 ==DQ 1 ==
2343 18:05:14.876048 Final DQ duty delay cell = 0
2344 18:05:14.879120 [0] MAX Duty = 5093%(X100), DQS PI = 26
2345 18:05:14.882381 [0] MIN Duty = 4907%(X100), DQS PI = 36
2346 18:05:14.882473 [0] AVG Duty = 5000%(X100)
2347 18:05:14.882538
2348 18:05:14.889629 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2349 18:05:14.889742
2350 18:05:14.892539 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2351 18:05:14.896072 [DutyScan_Calibration_Flow] ====Done====
2352 18:05:14.896171 ==
2353 18:05:14.899229 Dram Type= 6, Freq= 0, CH_1, rank 0
2354 18:05:14.902852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 18:05:14.902938 ==
2356 18:05:14.906097 [Duty_Offset_Calibration]
2357 18:05:14.906187 B0:1 B1:0 CA:0
2358 18:05:14.906253
2359 18:05:14.909559 [DutyScan_Calibration_Flow] k_type=0
2360 18:05:14.918523
2361 18:05:14.918665 ==CLK 0==
2362 18:05:14.922086 Final CLK duty delay cell = -4
2363 18:05:14.925151 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2364 18:05:14.928846 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2365 18:05:14.931786 [-4] AVG Duty = 4953%(X100)
2366 18:05:14.931910
2367 18:05:14.935297 CH1 CLK Duty spec in!! Max-Min= 93%
2368 18:05:14.938836 [DutyScan_Calibration_Flow] ====Done====
2369 18:05:14.938960
2370 18:05:14.942180 [DutyScan_Calibration_Flow] k_type=1
2371 18:05:14.958683
2372 18:05:14.958854 ==DQS 0 ==
2373 18:05:14.961624 Final DQS duty delay cell = 0
2374 18:05:14.964996 [0] MAX Duty = 5062%(X100), DQS PI = 12
2375 18:05:14.968667 [0] MIN Duty = 4844%(X100), DQS PI = 0
2376 18:05:14.968795 [0] AVG Duty = 4953%(X100)
2377 18:05:14.971712
2378 18:05:14.971816 ==DQS 1 ==
2379 18:05:14.974839 Final DQS duty delay cell = 0
2380 18:05:14.978434 [0] MAX Duty = 5187%(X100), DQS PI = 18
2381 18:05:14.981810 [0] MIN Duty = 4938%(X100), DQS PI = 10
2382 18:05:14.981933 [0] AVG Duty = 5062%(X100)
2383 18:05:14.985342
2384 18:05:14.988301 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2385 18:05:14.988432
2386 18:05:14.992078 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2387 18:05:14.995276 [DutyScan_Calibration_Flow] ====Done====
2388 18:05:14.995376
2389 18:05:14.997993 [DutyScan_Calibration_Flow] k_type=3
2390 18:05:15.014787
2391 18:05:15.014923 ==DQM 0 ==
2392 18:05:15.018586 Final DQM duty delay cell = 0
2393 18:05:15.021546 [0] MAX Duty = 5156%(X100), DQS PI = 6
2394 18:05:15.024668 [0] MIN Duty = 5031%(X100), DQS PI = 0
2395 18:05:15.024764 [0] AVG Duty = 5093%(X100)
2396 18:05:15.028496
2397 18:05:15.028589 ==DQM 1 ==
2398 18:05:15.031601 Final DQM duty delay cell = 0
2399 18:05:15.035394 [0] MAX Duty = 5031%(X100), DQS PI = 26
2400 18:05:15.038446 [0] MIN Duty = 4875%(X100), DQS PI = 36
2401 18:05:15.038544 [0] AVG Duty = 4953%(X100)
2402 18:05:15.038611
2403 18:05:15.045270 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2404 18:05:15.045385
2405 18:05:15.048176 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2406 18:05:15.051728 [DutyScan_Calibration_Flow] ====Done====
2407 18:05:15.051837
2408 18:05:15.054905 [DutyScan_Calibration_Flow] k_type=2
2409 18:05:15.070865
2410 18:05:15.071036 ==DQ 0 ==
2411 18:05:15.074411 Final DQ duty delay cell = -4
2412 18:05:15.077182 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2413 18:05:15.080658 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2414 18:05:15.084361 [-4] AVG Duty = 5000%(X100)
2415 18:05:15.084454
2416 18:05:15.084521 ==DQ 1 ==
2417 18:05:15.087266 Final DQ duty delay cell = 0
2418 18:05:15.090833 [0] MAX Duty = 5125%(X100), DQS PI = 20
2419 18:05:15.094608 [0] MIN Duty = 4969%(X100), DQS PI = 12
2420 18:05:15.094702 [0] AVG Duty = 5047%(X100)
2421 18:05:15.097406
2422 18:05:15.101090 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2423 18:05:15.101184
2424 18:05:15.103955 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2425 18:05:15.107757 [DutyScan_Calibration_Flow] ====Done====
2426 18:05:15.110737 nWR fixed to 30
2427 18:05:15.110866 [ModeRegInit_LP4] CH0 RK0
2428 18:05:15.114308 [ModeRegInit_LP4] CH0 RK1
2429 18:05:15.117684 [ModeRegInit_LP4] CH1 RK0
2430 18:05:15.121037 [ModeRegInit_LP4] CH1 RK1
2431 18:05:15.121174 match AC timing 7
2432 18:05:15.124206 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2433 18:05:15.131042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2434 18:05:15.133985 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2435 18:05:15.137742 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2436 18:05:15.144295 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2437 18:05:15.144436 ==
2438 18:05:15.147310 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 18:05:15.151144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 18:05:15.151247 ==
2441 18:05:15.158126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2442 18:05:15.164061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2443 18:05:15.170944 [CA 0] Center 39 (8~70) winsize 63
2444 18:05:15.174620 [CA 1] Center 39 (8~70) winsize 63
2445 18:05:15.177567 [CA 2] Center 35 (5~66) winsize 62
2446 18:05:15.181128 [CA 3] Center 34 (4~65) winsize 62
2447 18:05:15.184419 [CA 4] Center 33 (3~64) winsize 62
2448 18:05:15.188017 [CA 5] Center 32 (3~62) winsize 60
2449 18:05:15.188310
2450 18:05:15.191321 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2451 18:05:15.191597
2452 18:05:15.194108 [CATrainingPosCal] consider 1 rank data
2453 18:05:15.197536 u2DelayCellTimex100 = 270/100 ps
2454 18:05:15.201541 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2455 18:05:15.204131 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2456 18:05:15.211305 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2457 18:05:15.214266 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2458 18:05:15.217929 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2459 18:05:15.221651 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2460 18:05:15.221783
2461 18:05:15.224428 CA PerBit enable=1, Macro0, CA PI delay=32
2462 18:05:15.224547
2463 18:05:15.227909 [CBTSetCACLKResult] CA Dly = 32
2464 18:05:15.228072 CS Dly: 6 (0~37)
2465 18:05:15.228174 ==
2466 18:05:15.231578 Dram Type= 6, Freq= 0, CH_0, rank 1
2467 18:05:15.238201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 18:05:15.238436 ==
2469 18:05:15.241223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 18:05:15.248079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 18:05:15.256571 [CA 0] Center 38 (8~69) winsize 62
2472 18:05:15.260215 [CA 1] Center 38 (8~69) winsize 62
2473 18:05:15.263301 [CA 2] Center 35 (4~66) winsize 63
2474 18:05:15.266986 [CA 3] Center 34 (4~65) winsize 62
2475 18:05:15.270238 [CA 4] Center 33 (3~64) winsize 62
2476 18:05:15.273850 [CA 5] Center 32 (2~62) winsize 61
2477 18:05:15.274056
2478 18:05:15.276726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 18:05:15.276915
2480 18:05:15.280255 [CATrainingPosCal] consider 2 rank data
2481 18:05:15.283680 u2DelayCellTimex100 = 270/100 ps
2482 18:05:15.287159 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2483 18:05:15.290288 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2484 18:05:15.297146 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2485 18:05:15.299990 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2486 18:05:15.303604 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2487 18:05:15.307070 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2488 18:05:15.307228
2489 18:05:15.309979 CA PerBit enable=1, Macro0, CA PI delay=32
2490 18:05:15.310140
2491 18:05:15.313481 [CBTSetCACLKResult] CA Dly = 32
2492 18:05:15.313686 CS Dly: 6 (0~38)
2493 18:05:15.313828
2494 18:05:15.316795 ----->DramcWriteLeveling(PI) begin...
2495 18:05:15.320151 ==
2496 18:05:15.320367 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 18:05:15.327198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 18:05:15.327417 ==
2499 18:05:15.330217 Write leveling (Byte 0): 35 => 35
2500 18:05:15.333674 Write leveling (Byte 1): 32 => 32
2501 18:05:15.333882 DramcWriteLeveling(PI) end<-----
2502 18:05:15.337368
2503 18:05:15.337568 ==
2504 18:05:15.340122 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 18:05:15.343854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 18:05:15.344056 ==
2507 18:05:15.346972 [Gating] SW mode calibration
2508 18:05:15.353609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2509 18:05:15.357386 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2510 18:05:15.363329 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2511 18:05:15.367178 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2512 18:05:15.370162 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 18:05:15.377124 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 18:05:15.380164 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 18:05:15.383338 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 18:05:15.390253 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2517 18:05:15.393107 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2518 18:05:15.396566 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2519 18:05:15.403576 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 18:05:15.406730 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 18:05:15.410185 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 18:05:15.417015 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 18:05:15.420619 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 18:05:15.423339 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2525 18:05:15.430147 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2526 18:05:15.433604 1 1 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2527 18:05:15.437007 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 18:05:15.440383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 18:05:15.447044 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 18:05:15.450290 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 18:05:15.453567 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 18:05:15.460036 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 18:05:15.463872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2534 18:05:15.466914 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2535 18:05:15.473777 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 18:05:15.477001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 18:05:15.480670 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 18:05:15.486826 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 18:05:15.490508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 18:05:15.493535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 18:05:15.500466 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 18:05:15.503425 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 18:05:15.507038 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 18:05:15.513474 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 18:05:15.517290 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 18:05:15.520600 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 18:05:15.523950 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 18:05:15.530508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 18:05:15.533962 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2550 18:05:15.536764 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2551 18:05:15.543925 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 18:05:15.546960 Total UI for P1: 0, mck2ui 16
2553 18:05:15.550400 best dqsien dly found for B0: ( 1, 3, 30)
2554 18:05:15.550555 Total UI for P1: 0, mck2ui 16
2555 18:05:15.556809 best dqsien dly found for B1: ( 1, 4, 0)
2556 18:05:15.560327 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2557 18:05:15.563781 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2558 18:05:15.563912
2559 18:05:15.567173 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2560 18:05:15.570455 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2561 18:05:15.573992 [Gating] SW calibration Done
2562 18:05:15.574118 ==
2563 18:05:15.576973 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 18:05:15.580917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 18:05:15.581015 ==
2566 18:05:15.583714 RX Vref Scan: 0
2567 18:05:15.583823
2568 18:05:15.583916 RX Vref 0 -> 0, step: 1
2569 18:05:15.584003
2570 18:05:15.586944 RX Delay -40 -> 252, step: 8
2571 18:05:15.590851 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2572 18:05:15.597012 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2573 18:05:15.600956 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2574 18:05:15.603940 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2575 18:05:15.606950 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2576 18:05:15.610796 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2577 18:05:15.613782 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2578 18:05:15.620508 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2579 18:05:15.623707 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2580 18:05:15.626688 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2581 18:05:15.630640 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2582 18:05:15.637376 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2583 18:05:15.640786 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2584 18:05:15.643339 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2585 18:05:15.647066 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2586 18:05:15.650416 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2587 18:05:15.653317 ==
2588 18:05:15.653426 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 18:05:15.660250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 18:05:15.660373 ==
2591 18:05:15.660469 DQS Delay:
2592 18:05:15.663706 DQS0 = 0, DQS1 = 0
2593 18:05:15.663805 DQM Delay:
2594 18:05:15.666932 DQM0 = 121, DQM1 = 113
2595 18:05:15.667064 DQ Delay:
2596 18:05:15.670596 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2597 18:05:15.673338 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2598 18:05:15.676921 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2599 18:05:15.680481 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2600 18:05:15.680604
2601 18:05:15.680708
2602 18:05:15.680818 ==
2603 18:05:15.683833 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 18:05:15.687233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 18:05:15.690839 ==
2606 18:05:15.690976
2607 18:05:15.691079
2608 18:05:15.691169 TX Vref Scan disable
2609 18:05:15.693904 == TX Byte 0 ==
2610 18:05:15.696832 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2611 18:05:15.700081 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2612 18:05:15.703753 == TX Byte 1 ==
2613 18:05:15.706742 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2614 18:05:15.710575 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2615 18:05:15.713653 ==
2616 18:05:15.717365 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 18:05:15.720247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 18:05:15.720358 ==
2619 18:05:15.731602 TX Vref=22, minBit 0, minWin=24, winSum=400
2620 18:05:15.734856 TX Vref=24, minBit 4, minWin=24, winSum=406
2621 18:05:15.738422 TX Vref=26, minBit 7, minWin=25, winSum=414
2622 18:05:15.741707 TX Vref=28, minBit 12, minWin=25, winSum=418
2623 18:05:15.744883 TX Vref=30, minBit 0, minWin=26, winSum=419
2624 18:05:15.748284 TX Vref=32, minBit 0, minWin=26, winSum=419
2625 18:05:15.754710 [TxChooseVref] Worse bit 0, Min win 26, Win sum 419, Final Vref 30
2626 18:05:15.754831
2627 18:05:15.758081 Final TX Range 1 Vref 30
2628 18:05:15.758177
2629 18:05:15.758264 ==
2630 18:05:15.761490 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 18:05:15.765275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 18:05:15.765385 ==
2633 18:05:15.765482
2634 18:05:15.768086
2635 18:05:15.768198 TX Vref Scan disable
2636 18:05:15.771635 == TX Byte 0 ==
2637 18:05:15.774583 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2638 18:05:15.778170 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2639 18:05:15.781437 == TX Byte 1 ==
2640 18:05:15.784754 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2641 18:05:15.788374 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2642 18:05:15.788486
2643 18:05:15.791204 [DATLAT]
2644 18:05:15.791304 Freq=1200, CH0 RK0
2645 18:05:15.791372
2646 18:05:15.794726 DATLAT Default: 0xd
2647 18:05:15.794817 0, 0xFFFF, sum = 0
2648 18:05:15.798218 1, 0xFFFF, sum = 0
2649 18:05:15.798331 2, 0xFFFF, sum = 0
2650 18:05:15.801871 3, 0xFFFF, sum = 0
2651 18:05:15.801966 4, 0xFFFF, sum = 0
2652 18:05:15.804491 5, 0xFFFF, sum = 0
2653 18:05:15.804585 6, 0xFFFF, sum = 0
2654 18:05:15.808280 7, 0xFFFF, sum = 0
2655 18:05:15.808409 8, 0xFFFF, sum = 0
2656 18:05:15.811253 9, 0xFFFF, sum = 0
2657 18:05:15.815123 10, 0xFFFF, sum = 0
2658 18:05:15.815262 11, 0xFFFF, sum = 0
2659 18:05:15.818078 12, 0x0, sum = 1
2660 18:05:15.818169 13, 0x0, sum = 2
2661 18:05:15.818257 14, 0x0, sum = 3
2662 18:05:15.821808 15, 0x0, sum = 4
2663 18:05:15.821899 best_step = 13
2664 18:05:15.821983
2665 18:05:15.822061 ==
2666 18:05:15.824955 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 18:05:15.831619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 18:05:15.831736 ==
2669 18:05:15.831826 RX Vref Scan: 1
2670 18:05:15.831905
2671 18:05:15.834586 Set Vref Range= 32 -> 127
2672 18:05:15.834678
2673 18:05:15.838364 RX Vref 32 -> 127, step: 1
2674 18:05:15.838456
2675 18:05:15.841287 RX Delay -13 -> 252, step: 4
2676 18:05:15.841372
2677 18:05:15.844915 Set Vref, RX VrefLevel [Byte0]: 32
2678 18:05:15.848573 [Byte1]: 32
2679 18:05:15.848688
2680 18:05:15.851435 Set Vref, RX VrefLevel [Byte0]: 33
2681 18:05:15.854951 [Byte1]: 33
2682 18:05:15.855086
2683 18:05:15.858549 Set Vref, RX VrefLevel [Byte0]: 34
2684 18:05:15.861655 [Byte1]: 34
2685 18:05:15.865744
2686 18:05:15.865848 Set Vref, RX VrefLevel [Byte0]: 35
2687 18:05:15.868585 [Byte1]: 35
2688 18:05:15.873684
2689 18:05:15.873801 Set Vref, RX VrefLevel [Byte0]: 36
2690 18:05:15.876590 [Byte1]: 36
2691 18:05:15.881021
2692 18:05:15.881127 Set Vref, RX VrefLevel [Byte0]: 37
2693 18:05:15.884929 [Byte1]: 37
2694 18:05:15.889275
2695 18:05:15.889382 Set Vref, RX VrefLevel [Byte0]: 38
2696 18:05:15.892078 [Byte1]: 38
2697 18:05:15.897094
2698 18:05:15.897205 Set Vref, RX VrefLevel [Byte0]: 39
2699 18:05:15.900375 [Byte1]: 39
2700 18:05:15.905139
2701 18:05:15.905282 Set Vref, RX VrefLevel [Byte0]: 40
2702 18:05:15.908019 [Byte1]: 40
2703 18:05:15.912982
2704 18:05:15.913113 Set Vref, RX VrefLevel [Byte0]: 41
2705 18:05:15.916283 [Byte1]: 41
2706 18:05:15.921009
2707 18:05:15.921125 Set Vref, RX VrefLevel [Byte0]: 42
2708 18:05:15.924093 [Byte1]: 42
2709 18:05:15.928626
2710 18:05:15.928762 Set Vref, RX VrefLevel [Byte0]: 43
2711 18:05:15.931820 [Byte1]: 43
2712 18:05:15.936394
2713 18:05:15.936498 Set Vref, RX VrefLevel [Byte0]: 44
2714 18:05:15.939493 [Byte1]: 44
2715 18:05:15.944840
2716 18:05:15.944978 Set Vref, RX VrefLevel [Byte0]: 45
2717 18:05:15.947857 [Byte1]: 45
2718 18:05:15.952240
2719 18:05:15.952387 Set Vref, RX VrefLevel [Byte0]: 46
2720 18:05:15.955853 [Byte1]: 46
2721 18:05:15.960253
2722 18:05:15.960372 Set Vref, RX VrefLevel [Byte0]: 47
2723 18:05:15.963800 [Byte1]: 47
2724 18:05:15.967859
2725 18:05:15.967965 Set Vref, RX VrefLevel [Byte0]: 48
2726 18:05:15.971325 [Byte1]: 48
2727 18:05:15.976285
2728 18:05:15.976441 Set Vref, RX VrefLevel [Byte0]: 49
2729 18:05:15.979131 [Byte1]: 49
2730 18:05:15.984145
2731 18:05:15.984282 Set Vref, RX VrefLevel [Byte0]: 50
2732 18:05:15.987217 [Byte1]: 50
2733 18:05:15.991815
2734 18:05:15.991917 Set Vref, RX VrefLevel [Byte0]: 51
2735 18:05:15.994953 [Byte1]: 51
2736 18:05:16.000101
2737 18:05:16.000201 Set Vref, RX VrefLevel [Byte0]: 52
2738 18:05:16.003028 [Byte1]: 52
2739 18:05:16.007373
2740 18:05:16.007507 Set Vref, RX VrefLevel [Byte0]: 53
2741 18:05:16.010794 [Byte1]: 53
2742 18:05:16.015466
2743 18:05:16.015586 Set Vref, RX VrefLevel [Byte0]: 54
2744 18:05:16.018733 [Byte1]: 54
2745 18:05:16.023407
2746 18:05:16.023541 Set Vref, RX VrefLevel [Byte0]: 55
2747 18:05:16.026696 [Byte1]: 55
2748 18:05:16.030909
2749 18:05:16.031016 Set Vref, RX VrefLevel [Byte0]: 56
2750 18:05:16.034710 [Byte1]: 56
2751 18:05:16.039363
2752 18:05:16.039497 Set Vref, RX VrefLevel [Byte0]: 57
2753 18:05:16.042415 [Byte1]: 57
2754 18:05:16.046957
2755 18:05:16.047087 Set Vref, RX VrefLevel [Byte0]: 58
2756 18:05:16.049898 [Byte1]: 58
2757 18:05:16.055163
2758 18:05:16.055279 Set Vref, RX VrefLevel [Byte0]: 59
2759 18:05:16.058258 [Byte1]: 59
2760 18:05:16.063352
2761 18:05:16.063496 Set Vref, RX VrefLevel [Byte0]: 60
2762 18:05:16.066266 [Byte1]: 60
2763 18:05:16.070665
2764 18:05:16.070802 Set Vref, RX VrefLevel [Byte0]: 61
2765 18:05:16.074159 [Byte1]: 61
2766 18:05:16.078377
2767 18:05:16.078512 Set Vref, RX VrefLevel [Byte0]: 62
2768 18:05:16.081743 [Byte1]: 62
2769 18:05:16.086377
2770 18:05:16.086487 Set Vref, RX VrefLevel [Byte0]: 63
2771 18:05:16.089951 [Byte1]: 63
2772 18:05:16.093996
2773 18:05:16.094123 Set Vref, RX VrefLevel [Byte0]: 64
2774 18:05:16.097735 [Byte1]: 64
2775 18:05:16.102332
2776 18:05:16.102468 Set Vref, RX VrefLevel [Byte0]: 65
2777 18:05:16.105970 [Byte1]: 65
2778 18:05:16.110583
2779 18:05:16.110695 Set Vref, RX VrefLevel [Byte0]: 66
2780 18:05:16.113566 [Byte1]: 66
2781 18:05:16.117936
2782 18:05:16.118047 Set Vref, RX VrefLevel [Byte0]: 67
2783 18:05:16.121447 [Byte1]: 67
2784 18:05:16.125617
2785 18:05:16.125729 Set Vref, RX VrefLevel [Byte0]: 68
2786 18:05:16.129443 [Byte1]: 68
2787 18:05:16.133825
2788 18:05:16.133963 Set Vref, RX VrefLevel [Byte0]: 69
2789 18:05:16.136775 [Byte1]: 69
2790 18:05:16.141627
2791 18:05:16.141742 Final RX Vref Byte 0 = 55 to rank0
2792 18:05:16.145398 Final RX Vref Byte 1 = 49 to rank0
2793 18:05:16.148475 Final RX Vref Byte 0 = 55 to rank1
2794 18:05:16.151594 Final RX Vref Byte 1 = 49 to rank1==
2795 18:05:16.154796 Dram Type= 6, Freq= 0, CH_0, rank 0
2796 18:05:16.161708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2797 18:05:16.161869 ==
2798 18:05:16.161974 DQS Delay:
2799 18:05:16.162071 DQS0 = 0, DQS1 = 0
2800 18:05:16.164867 DQM Delay:
2801 18:05:16.164955 DQM0 = 120, DQM1 = 112
2802 18:05:16.168613 DQ Delay:
2803 18:05:16.171410 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2804 18:05:16.174511 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2805 18:05:16.178330 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2806 18:05:16.181437 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2807 18:05:16.181578
2808 18:05:16.181677
2809 18:05:16.191400 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2810 18:05:16.191563 CH0 RK0: MR19=404, MR18=1610
2811 18:05:16.197982 CH0_RK0: MR19=0x404, MR18=0x1610, DQSOSC=401, MR23=63, INC=40, DEC=27
2812 18:05:16.198108
2813 18:05:16.201517 ----->DramcWriteLeveling(PI) begin...
2814 18:05:16.201646 ==
2815 18:05:16.205069 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 18:05:16.208273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 18:05:16.211571 ==
2818 18:05:16.211698 Write leveling (Byte 0): 33 => 33
2819 18:05:16.215012 Write leveling (Byte 1): 29 => 29
2820 18:05:16.218638 DramcWriteLeveling(PI) end<-----
2821 18:05:16.218770
2822 18:05:16.218870 ==
2823 18:05:16.221671 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 18:05:16.228308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 18:05:16.228440 ==
2826 18:05:16.231893 [Gating] SW mode calibration
2827 18:05:16.238420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2828 18:05:16.241369 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2829 18:05:16.247882 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
2830 18:05:16.251192 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2831 18:05:16.254501 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 18:05:16.258125 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 18:05:16.264903 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 18:05:16.267968 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 18:05:16.271835 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 18:05:16.278472 0 15 28 | B1->B0 | 2e2e 2e2e | 1 0 | (1 0) (0 0)
2837 18:05:16.281495 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2838 18:05:16.285516 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2839 18:05:16.291436 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 18:05:16.295462 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 18:05:16.298490 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 18:05:16.304784 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 18:05:16.308160 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2844 18:05:16.311562 1 0 28 | B1->B0 | 3b3b 3a3a | 0 0 | (0 0) (0 0)
2845 18:05:16.318002 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 18:05:16.321662 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2847 18:05:16.325007 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 18:05:16.331722 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 18:05:16.335097 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 18:05:16.338021 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 18:05:16.341589 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 18:05:16.348158 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2853 18:05:16.351914 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2854 18:05:16.354938 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 18:05:16.361383 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 18:05:16.364857 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 18:05:16.368520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 18:05:16.374671 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 18:05:16.378560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 18:05:16.381606 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 18:05:16.387947 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 18:05:16.391677 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 18:05:16.394825 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 18:05:16.401601 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 18:05:16.404735 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 18:05:16.408520 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 18:05:16.414756 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 18:05:16.418103 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2869 18:05:16.421407 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 18:05:16.424985 Total UI for P1: 0, mck2ui 16
2871 18:05:16.427794 best dqsien dly found for B0: ( 1, 3, 28)
2872 18:05:16.431524 Total UI for P1: 0, mck2ui 16
2873 18:05:16.435097 best dqsien dly found for B1: ( 1, 3, 28)
2874 18:05:16.438188 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2875 18:05:16.441339 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2876 18:05:16.441432
2877 18:05:16.444954 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2878 18:05:16.451907 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2879 18:05:16.452050 [Gating] SW calibration Done
2880 18:05:16.452148 ==
2881 18:05:16.455354 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 18:05:16.461928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 18:05:16.462075 ==
2884 18:05:16.462189 RX Vref Scan: 0
2885 18:05:16.462289
2886 18:05:16.464945 RX Vref 0 -> 0, step: 1
2887 18:05:16.465071
2888 18:05:16.467978 RX Delay -40 -> 252, step: 8
2889 18:05:16.471653 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2890 18:05:16.475084 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2891 18:05:16.478459 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2892 18:05:16.485199 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2893 18:05:16.488187 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2894 18:05:16.491861 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2895 18:05:16.494761 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2896 18:05:16.498663 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2897 18:05:16.501530 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2898 18:05:16.508405 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2899 18:05:16.511344 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2900 18:05:16.515127 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2901 18:05:16.518138 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2902 18:05:16.522013 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2903 18:05:16.528589 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2904 18:05:16.531961 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2905 18:05:16.532098 ==
2906 18:05:16.535334 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 18:05:16.538063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 18:05:16.538191 ==
2909 18:05:16.541490 DQS Delay:
2910 18:05:16.541610 DQS0 = 0, DQS1 = 0
2911 18:05:16.541709 DQM Delay:
2912 18:05:16.545034 DQM0 = 122, DQM1 = 112
2913 18:05:16.545126 DQ Delay:
2914 18:05:16.548036 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2915 18:05:16.551470 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2916 18:05:16.554986 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
2917 18:05:16.561509 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2918 18:05:16.561684
2919 18:05:16.561804
2920 18:05:16.561895 ==
2921 18:05:16.565056 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 18:05:16.568418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 18:05:16.568565 ==
2924 18:05:16.568664
2925 18:05:16.568754
2926 18:05:16.571825 TX Vref Scan disable
2927 18:05:16.571965 == TX Byte 0 ==
2928 18:05:16.578760 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2929 18:05:16.581969 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2930 18:05:16.582131 == TX Byte 1 ==
2931 18:05:16.588531 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2932 18:05:16.591598 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2933 18:05:16.591745 ==
2934 18:05:16.595494 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 18:05:16.598404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 18:05:16.598531 ==
2937 18:05:16.611129 TX Vref=22, minBit 3, minWin=25, winSum=412
2938 18:05:16.615162 TX Vref=24, minBit 1, minWin=25, winSum=417
2939 18:05:16.618067 TX Vref=26, minBit 3, minWin=25, winSum=420
2940 18:05:16.621338 TX Vref=28, minBit 1, minWin=26, winSum=423
2941 18:05:16.625034 TX Vref=30, minBit 12, minWin=25, winSum=428
2942 18:05:16.631197 TX Vref=32, minBit 12, minWin=25, winSum=423
2943 18:05:16.634851 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 28
2944 18:05:16.634985
2945 18:05:16.638458 Final TX Range 1 Vref 28
2946 18:05:16.638582
2947 18:05:16.638690 ==
2948 18:05:16.641403 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 18:05:16.644464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 18:05:16.644591 ==
2951 18:05:16.648008
2952 18:05:16.648131
2953 18:05:16.648228 TX Vref Scan disable
2954 18:05:16.651766 == TX Byte 0 ==
2955 18:05:16.654710 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2956 18:05:16.658233 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2957 18:05:16.661696 == TX Byte 1 ==
2958 18:05:16.664739 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2959 18:05:16.667853 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2960 18:05:16.667982
2961 18:05:16.671799 [DATLAT]
2962 18:05:16.671918 Freq=1200, CH0 RK1
2963 18:05:16.672018
2964 18:05:16.674501 DATLAT Default: 0xd
2965 18:05:16.674613 0, 0xFFFF, sum = 0
2966 18:05:16.677944 1, 0xFFFF, sum = 0
2967 18:05:16.678062 2, 0xFFFF, sum = 0
2968 18:05:16.681565 3, 0xFFFF, sum = 0
2969 18:05:16.681692 4, 0xFFFF, sum = 0
2970 18:05:16.685106 5, 0xFFFF, sum = 0
2971 18:05:16.685227 6, 0xFFFF, sum = 0
2972 18:05:16.688098 7, 0xFFFF, sum = 0
2973 18:05:16.688228 8, 0xFFFF, sum = 0
2974 18:05:16.691237 9, 0xFFFF, sum = 0
2975 18:05:16.694953 10, 0xFFFF, sum = 0
2976 18:05:16.695078 11, 0xFFFF, sum = 0
2977 18:05:16.697916 12, 0x0, sum = 1
2978 18:05:16.698036 13, 0x0, sum = 2
2979 18:05:16.698134 14, 0x0, sum = 3
2980 18:05:16.701503 15, 0x0, sum = 4
2981 18:05:16.701619 best_step = 13
2982 18:05:16.701723
2983 18:05:16.705034 ==
2984 18:05:16.705163 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 18:05:16.711728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 18:05:16.711880 ==
2987 18:05:16.711984 RX Vref Scan: 0
2988 18:05:16.712087
2989 18:05:16.714618 RX Vref 0 -> 0, step: 1
2990 18:05:16.714727
2991 18:05:16.718371 RX Delay -13 -> 252, step: 4
2992 18:05:16.721551 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2993 18:05:16.725411 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2994 18:05:16.731477 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2995 18:05:16.735360 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2996 18:05:16.738463 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2997 18:05:16.742012 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
2998 18:05:16.745016 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
2999 18:05:16.751770 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3000 18:05:16.755348 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3001 18:05:16.758363 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3002 18:05:16.762140 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3003 18:05:16.765176 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3004 18:05:16.768654 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3005 18:05:16.775521 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3006 18:05:16.778484 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3007 18:05:16.782326 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3008 18:05:16.782464 ==
3009 18:05:16.785359 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 18:05:16.788999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 18:05:16.791958 ==
3012 18:05:16.792082 DQS Delay:
3013 18:05:16.792191 DQS0 = 0, DQS1 = 0
3014 18:05:16.795576 DQM Delay:
3015 18:05:16.795699 DQM0 = 120, DQM1 = 110
3016 18:05:16.798447 DQ Delay:
3017 18:05:16.802299 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3018 18:05:16.805652 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3019 18:05:16.808554 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3020 18:05:16.812061 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =120
3021 18:05:16.812196
3022 18:05:16.812297
3023 18:05:16.818903 [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps
3024 18:05:16.821771 CH0 RK1: MR19=403, MR18=FF0
3025 18:05:16.828588 CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26
3026 18:05:16.831750 [RxdqsGatingPostProcess] freq 1200
3027 18:05:16.838649 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3028 18:05:16.838797 best DQS0 dly(2T, 0.5T) = (0, 11)
3029 18:05:16.842398 best DQS1 dly(2T, 0.5T) = (0, 12)
3030 18:05:16.845375 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3031 18:05:16.848512 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3032 18:05:16.852362 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 18:05:16.855375 best DQS1 dly(2T, 0.5T) = (0, 11)
3034 18:05:16.859094 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 18:05:16.862092 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3036 18:05:16.865171 Pre-setting of DQS Precalculation
3037 18:05:16.869209 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3038 18:05:16.869347 ==
3039 18:05:16.872133 Dram Type= 6, Freq= 0, CH_1, rank 0
3040 18:05:16.878895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 18:05:16.879044 ==
3042 18:05:16.881728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3043 18:05:16.888719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3044 18:05:16.897458 [CA 0] Center 37 (7~68) winsize 62
3045 18:05:16.901087 [CA 1] Center 37 (7~68) winsize 62
3046 18:05:16.904642 [CA 2] Center 35 (5~65) winsize 61
3047 18:05:16.907306 [CA 3] Center 34 (4~64) winsize 61
3048 18:05:16.911079 [CA 4] Center 34 (4~64) winsize 61
3049 18:05:16.914256 [CA 5] Center 33 (3~63) winsize 61
3050 18:05:16.914387
3051 18:05:16.917395 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3052 18:05:16.917519
3053 18:05:16.921112 [CATrainingPosCal] consider 1 rank data
3054 18:05:16.924138 u2DelayCellTimex100 = 270/100 ps
3055 18:05:16.927810 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3056 18:05:16.930618 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3057 18:05:16.937446 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3058 18:05:16.940813 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3059 18:05:16.944162 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3060 18:05:16.947824 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3061 18:05:16.947957
3062 18:05:16.950769 CA PerBit enable=1, Macro0, CA PI delay=33
3063 18:05:16.950900
3064 18:05:16.954605 [CBTSetCACLKResult] CA Dly = 33
3065 18:05:16.954725 CS Dly: 8 (0~39)
3066 18:05:16.954834 ==
3067 18:05:16.957737 Dram Type= 6, Freq= 0, CH_1, rank 1
3068 18:05:16.964331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 18:05:16.964477 ==
3070 18:05:16.967361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 18:05:16.974144 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3072 18:05:16.983137 [CA 0] Center 37 (7~68) winsize 62
3073 18:05:16.986992 [CA 1] Center 38 (7~69) winsize 63
3074 18:05:16.990012 [CA 2] Center 35 (5~65) winsize 61
3075 18:05:16.993145 [CA 3] Center 34 (4~65) winsize 62
3076 18:05:16.996688 [CA 4] Center 34 (4~65) winsize 62
3077 18:05:16.999743 [CA 5] Center 34 (4~64) winsize 61
3078 18:05:16.999841
3079 18:05:17.003298 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3080 18:05:17.003387
3081 18:05:17.006671 [CATrainingPosCal] consider 2 rank data
3082 18:05:17.010278 u2DelayCellTimex100 = 270/100 ps
3083 18:05:17.013664 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 18:05:17.017042 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 18:05:17.020374 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3086 18:05:17.027434 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3087 18:05:17.030504 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 18:05:17.033488 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3089 18:05:17.033620
3090 18:05:17.036532 CA PerBit enable=1, Macro0, CA PI delay=33
3091 18:05:17.036658
3092 18:05:17.040247 [CBTSetCACLKResult] CA Dly = 33
3093 18:05:17.040385 CS Dly: 8 (0~40)
3094 18:05:17.040483
3095 18:05:17.043304 ----->DramcWriteLeveling(PI) begin...
3096 18:05:17.043419 ==
3097 18:05:17.047084 Dram Type= 6, Freq= 0, CH_1, rank 0
3098 18:05:17.053498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 18:05:17.053647 ==
3100 18:05:17.056982 Write leveling (Byte 0): 26 => 26
3101 18:05:17.060290 Write leveling (Byte 1): 27 => 27
3102 18:05:17.060431 DramcWriteLeveling(PI) end<-----
3103 18:05:17.063824
3104 18:05:17.063943 ==
3105 18:05:17.066832 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 18:05:17.070036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 18:05:17.070166 ==
3108 18:05:17.073608 [Gating] SW mode calibration
3109 18:05:17.080002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3110 18:05:17.083902 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3111 18:05:17.089956 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 18:05:17.093829 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3113 18:05:17.096835 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 18:05:17.103748 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 18:05:17.106957 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 18:05:17.109855 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 18:05:17.116515 0 15 24 | B1->B0 | 3232 2929 | 1 0 | (1 0) (0 0)
3118 18:05:17.120199 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3119 18:05:17.123266 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3120 18:05:17.129842 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3121 18:05:17.133539 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 18:05:17.136735 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 18:05:17.143808 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 18:05:17.146858 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 18:05:17.149834 1 0 24 | B1->B0 | 3030 3b3b | 0 1 | (1 1) (0 0)
3126 18:05:17.153587 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 18:05:17.159860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 18:05:17.163874 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 18:05:17.166826 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 18:05:17.173343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 18:05:17.177063 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 18:05:17.179956 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 18:05:17.186607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3134 18:05:17.190228 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3135 18:05:17.193387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 18:05:17.200602 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 18:05:17.203977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 18:05:17.206750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 18:05:17.213411 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 18:05:17.217138 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 18:05:17.220285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 18:05:17.226938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 18:05:17.230080 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 18:05:17.233732 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 18:05:17.236816 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 18:05:17.243568 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 18:05:17.247089 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 18:05:17.250609 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 18:05:17.257110 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3150 18:05:17.260163 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 18:05:17.264025 Total UI for P1: 0, mck2ui 16
3152 18:05:17.267040 best dqsien dly found for B0: ( 1, 3, 24)
3153 18:05:17.270094 Total UI for P1: 0, mck2ui 16
3154 18:05:17.273823 best dqsien dly found for B1: ( 1, 3, 24)
3155 18:05:17.276961 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3156 18:05:17.280131 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3157 18:05:17.280267
3158 18:05:17.283996 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3159 18:05:17.287280 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3160 18:05:17.290300 [Gating] SW calibration Done
3161 18:05:17.290421 ==
3162 18:05:17.293360 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 18:05:17.297015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 18:05:17.300140 ==
3165 18:05:17.300265 RX Vref Scan: 0
3166 18:05:17.300374
3167 18:05:17.303600 RX Vref 0 -> 0, step: 1
3168 18:05:17.303718
3169 18:05:17.307001 RX Delay -40 -> 252, step: 8
3170 18:05:17.310202 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3171 18:05:17.313859 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3172 18:05:17.317282 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3173 18:05:17.320269 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3174 18:05:17.323773 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3175 18:05:17.330953 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3176 18:05:17.333978 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3177 18:05:17.337045 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3178 18:05:17.340779 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3179 18:05:17.343971 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3180 18:05:17.350936 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3181 18:05:17.353857 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3182 18:05:17.357424 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3183 18:05:17.360591 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3184 18:05:17.364300 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3185 18:05:17.370588 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3186 18:05:17.370739 ==
3187 18:05:17.374445 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 18:05:17.377274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 18:05:17.377403 ==
3190 18:05:17.377501 DQS Delay:
3191 18:05:17.380379 DQS0 = 0, DQS1 = 0
3192 18:05:17.380493 DQM Delay:
3193 18:05:17.384111 DQM0 = 119, DQM1 = 116
3194 18:05:17.384227 DQ Delay:
3195 18:05:17.387242 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3196 18:05:17.390426 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3197 18:05:17.394306 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3198 18:05:17.397439 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3199 18:05:17.397557
3200 18:05:17.397656
3201 18:05:17.400564 ==
3202 18:05:17.403678 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 18:05:17.407488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 18:05:17.407614 ==
3205 18:05:17.407724
3206 18:05:17.407817
3207 18:05:17.410526 TX Vref Scan disable
3208 18:05:17.410635 == TX Byte 0 ==
3209 18:05:17.413607 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3210 18:05:17.420851 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3211 18:05:17.421010 == TX Byte 1 ==
3212 18:05:17.423859 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3213 18:05:17.430464 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3214 18:05:17.430607 ==
3215 18:05:17.433907 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 18:05:17.437224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 18:05:17.437350 ==
3218 18:05:17.449242 TX Vref=22, minBit 1, minWin=25, winSum=412
3219 18:05:17.452546 TX Vref=24, minBit 11, minWin=24, winSum=417
3220 18:05:17.455940 TX Vref=26, minBit 9, minWin=25, winSum=422
3221 18:05:17.458827 TX Vref=28, minBit 1, minWin=26, winSum=427
3222 18:05:17.462386 TX Vref=30, minBit 9, minWin=26, winSum=430
3223 18:05:17.469288 TX Vref=32, minBit 10, minWin=26, winSum=429
3224 18:05:17.472325 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3225 18:05:17.472478
3226 18:05:17.476082 Final TX Range 1 Vref 30
3227 18:05:17.476204
3228 18:05:17.476301 ==
3229 18:05:17.479044 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 18:05:17.482654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 18:05:17.482785 ==
3232 18:05:17.482885
3233 18:05:17.486106
3234 18:05:17.486223 TX Vref Scan disable
3235 18:05:17.489298 == TX Byte 0 ==
3236 18:05:17.493038 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3237 18:05:17.495961 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3238 18:05:17.499010 == TX Byte 1 ==
3239 18:05:17.502674 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3240 18:05:17.505883 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3241 18:05:17.506010
3242 18:05:17.508930 [DATLAT]
3243 18:05:17.509043 Freq=1200, CH1 RK0
3244 18:05:17.509138
3245 18:05:17.512911 DATLAT Default: 0xd
3246 18:05:17.513029 0, 0xFFFF, sum = 0
3247 18:05:17.516191 1, 0xFFFF, sum = 0
3248 18:05:17.516308 2, 0xFFFF, sum = 0
3249 18:05:17.519255 3, 0xFFFF, sum = 0
3250 18:05:17.519382 4, 0xFFFF, sum = 0
3251 18:05:17.523011 5, 0xFFFF, sum = 0
3252 18:05:17.523131 6, 0xFFFF, sum = 0
3253 18:05:17.525960 7, 0xFFFF, sum = 0
3254 18:05:17.526077 8, 0xFFFF, sum = 0
3255 18:05:17.529177 9, 0xFFFF, sum = 0
3256 18:05:17.529276 10, 0xFFFF, sum = 0
3257 18:05:17.532303 11, 0xFFFF, sum = 0
3258 18:05:17.532402 12, 0x0, sum = 1
3259 18:05:17.536064 13, 0x0, sum = 2
3260 18:05:17.536187 14, 0x0, sum = 3
3261 18:05:17.539224 15, 0x0, sum = 4
3262 18:05:17.539340 best_step = 13
3263 18:05:17.539435
3264 18:05:17.539527 ==
3265 18:05:17.543204 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 18:05:17.549725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 18:05:17.549873 ==
3268 18:05:17.549975 RX Vref Scan: 1
3269 18:05:17.550067
3270 18:05:17.552348 Set Vref Range= 32 -> 127
3271 18:05:17.552464
3272 18:05:17.555914 RX Vref 32 -> 127, step: 1
3273 18:05:17.556031
3274 18:05:17.559461 RX Delay -5 -> 252, step: 4
3275 18:05:17.559580
3276 18:05:17.559677 Set Vref, RX VrefLevel [Byte0]: 32
3277 18:05:17.562425 [Byte1]: 32
3278 18:05:17.567266
3279 18:05:17.567400 Set Vref, RX VrefLevel [Byte0]: 33
3280 18:05:17.570620 [Byte1]: 33
3281 18:05:17.575255
3282 18:05:17.575387 Set Vref, RX VrefLevel [Byte0]: 34
3283 18:05:17.578445 [Byte1]: 34
3284 18:05:17.582683
3285 18:05:17.582817 Set Vref, RX VrefLevel [Byte0]: 35
3286 18:05:17.586407 [Byte1]: 35
3287 18:05:17.590690
3288 18:05:17.590824 Set Vref, RX VrefLevel [Byte0]: 36
3289 18:05:17.594319 [Byte1]: 36
3290 18:05:17.598401
3291 18:05:17.598527 Set Vref, RX VrefLevel [Byte0]: 37
3292 18:05:17.602074 [Byte1]: 37
3293 18:05:17.606503
3294 18:05:17.606644 Set Vref, RX VrefLevel [Byte0]: 38
3295 18:05:17.610037 [Byte1]: 38
3296 18:05:17.614678
3297 18:05:17.614806 Set Vref, RX VrefLevel [Byte0]: 39
3298 18:05:17.617710 [Byte1]: 39
3299 18:05:17.622363
3300 18:05:17.622491 Set Vref, RX VrefLevel [Byte0]: 40
3301 18:05:17.625433 [Byte1]: 40
3302 18:05:17.629930
3303 18:05:17.630054 Set Vref, RX VrefLevel [Byte0]: 41
3304 18:05:17.636636 [Byte1]: 41
3305 18:05:17.636771
3306 18:05:17.639654 Set Vref, RX VrefLevel [Byte0]: 42
3307 18:05:17.643455 [Byte1]: 42
3308 18:05:17.643572
3309 18:05:17.646487 Set Vref, RX VrefLevel [Byte0]: 43
3310 18:05:17.649529 [Byte1]: 43
3311 18:05:17.653966
3312 18:05:17.654087 Set Vref, RX VrefLevel [Byte0]: 44
3313 18:05:17.656829 [Byte1]: 44
3314 18:05:17.661810
3315 18:05:17.661935 Set Vref, RX VrefLevel [Byte0]: 45
3316 18:05:17.664598 [Byte1]: 45
3317 18:05:17.669297
3318 18:05:17.669422 Set Vref, RX VrefLevel [Byte0]: 46
3319 18:05:17.672313 [Byte1]: 46
3320 18:05:17.676977
3321 18:05:17.677097 Set Vref, RX VrefLevel [Byte0]: 47
3322 18:05:17.680717 [Byte1]: 47
3323 18:05:17.684805
3324 18:05:17.684925 Set Vref, RX VrefLevel [Byte0]: 48
3325 18:05:17.688269 [Byte1]: 48
3326 18:05:17.693153
3327 18:05:17.693284 Set Vref, RX VrefLevel [Byte0]: 49
3328 18:05:17.696047 [Byte1]: 49
3329 18:05:17.700588
3330 18:05:17.700712 Set Vref, RX VrefLevel [Byte0]: 50
3331 18:05:17.703869 [Byte1]: 50
3332 18:05:17.708996
3333 18:05:17.709133 Set Vref, RX VrefLevel [Byte0]: 51
3334 18:05:17.712393 [Byte1]: 51
3335 18:05:17.716451
3336 18:05:17.716581 Set Vref, RX VrefLevel [Byte0]: 52
3337 18:05:17.719830 [Byte1]: 52
3338 18:05:17.724470
3339 18:05:17.724609 Set Vref, RX VrefLevel [Byte0]: 53
3340 18:05:17.727276 [Byte1]: 53
3341 18:05:17.732370
3342 18:05:17.732512 Set Vref, RX VrefLevel [Byte0]: 54
3343 18:05:17.735233 [Byte1]: 54
3344 18:05:17.740050
3345 18:05:17.740190 Set Vref, RX VrefLevel [Byte0]: 55
3346 18:05:17.743193 [Byte1]: 55
3347 18:05:17.747987
3348 18:05:17.748122 Set Vref, RX VrefLevel [Byte0]: 56
3349 18:05:17.750971 [Byte1]: 56
3350 18:05:17.755708
3351 18:05:17.755843 Set Vref, RX VrefLevel [Byte0]: 57
3352 18:05:17.758834 [Byte1]: 57
3353 18:05:17.763647
3354 18:05:17.763781 Set Vref, RX VrefLevel [Byte0]: 58
3355 18:05:17.767105 [Byte1]: 58
3356 18:05:17.771477
3357 18:05:17.771612 Set Vref, RX VrefLevel [Byte0]: 59
3358 18:05:17.774404 [Byte1]: 59
3359 18:05:17.779262
3360 18:05:17.779391 Set Vref, RX VrefLevel [Byte0]: 60
3361 18:05:17.782381 [Byte1]: 60
3362 18:05:17.787008
3363 18:05:17.787136 Set Vref, RX VrefLevel [Byte0]: 61
3364 18:05:17.789957 [Byte1]: 61
3365 18:05:17.794916
3366 18:05:17.795049 Set Vref, RX VrefLevel [Byte0]: 62
3367 18:05:17.797839 [Byte1]: 62
3368 18:05:17.802626
3369 18:05:17.802754 Set Vref, RX VrefLevel [Byte0]: 63
3370 18:05:17.806348 [Byte1]: 63
3371 18:05:17.810746
3372 18:05:17.810875 Set Vref, RX VrefLevel [Byte0]: 64
3373 18:05:17.813780 [Byte1]: 64
3374 18:05:17.818697
3375 18:05:17.818832 Set Vref, RX VrefLevel [Byte0]: 65
3376 18:05:17.821412 [Byte1]: 65
3377 18:05:17.826296
3378 18:05:17.826426 Set Vref, RX VrefLevel [Byte0]: 66
3379 18:05:17.829799 [Byte1]: 66
3380 18:05:17.834091
3381 18:05:17.834220 Set Vref, RX VrefLevel [Byte0]: 67
3382 18:05:17.837635 [Byte1]: 67
3383 18:05:17.842395
3384 18:05:17.842518 Set Vref, RX VrefLevel [Byte0]: 68
3385 18:05:17.845721 [Byte1]: 68
3386 18:05:17.849530
3387 18:05:17.849652 Final RX Vref Byte 0 = 54 to rank0
3388 18:05:17.853277 Final RX Vref Byte 1 = 53 to rank0
3389 18:05:17.856435 Final RX Vref Byte 0 = 54 to rank1
3390 18:05:17.859444 Final RX Vref Byte 1 = 53 to rank1==
3391 18:05:17.863359 Dram Type= 6, Freq= 0, CH_1, rank 0
3392 18:05:17.869448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3393 18:05:17.869584 ==
3394 18:05:17.869683 DQS Delay:
3395 18:05:17.869774 DQS0 = 0, DQS1 = 0
3396 18:05:17.873073 DQM Delay:
3397 18:05:17.873186 DQM0 = 120, DQM1 = 117
3398 18:05:17.876428 DQ Delay:
3399 18:05:17.879925 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3400 18:05:17.882695 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3401 18:05:17.886625 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3402 18:05:17.889570 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3403 18:05:17.889678
3404 18:05:17.889772
3405 18:05:17.899343 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3406 18:05:17.899451 CH1 RK0: MR19=304, MR18=FF12
3407 18:05:17.905928 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3408 18:05:17.906035
3409 18:05:17.909123 ----->DramcWriteLeveling(PI) begin...
3410 18:05:17.909226 ==
3411 18:05:17.912982 Dram Type= 6, Freq= 0, CH_1, rank 1
3412 18:05:17.919384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 18:05:17.919508 ==
3414 18:05:17.922461 Write leveling (Byte 0): 27 => 27
3415 18:05:17.922568 Write leveling (Byte 1): 30 => 30
3416 18:05:17.926240 DramcWriteLeveling(PI) end<-----
3417 18:05:17.926345
3418 18:05:17.929220 ==
3419 18:05:17.929328 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 18:05:17.936337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 18:05:17.936451 ==
3422 18:05:17.939177 [Gating] SW mode calibration
3423 18:05:17.946062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3424 18:05:17.949734 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3425 18:05:17.956232 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 18:05:17.959751 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 18:05:17.962622 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 18:05:17.969615 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 18:05:17.972689 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 18:05:17.975785 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3431 18:05:17.982607 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 1)
3432 18:05:17.986237 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3433 18:05:17.989035 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 18:05:17.996102 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 18:05:17.999161 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 18:05:18.002279 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 18:05:18.009025 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 18:05:18.012526 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3439 18:05:18.015571 1 0 24 | B1->B0 | 4040 2424 | 0 0 | (0 0) (0 0)
3440 18:05:18.019410 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 18:05:18.025626 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 18:05:18.029458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 18:05:18.032839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 18:05:18.039612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 18:05:18.042431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 18:05:18.046156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3447 18:05:18.052713 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3448 18:05:18.056104 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3449 18:05:18.059428 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 18:05:18.065907 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 18:05:18.069614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 18:05:18.072435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 18:05:18.079311 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 18:05:18.082750 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 18:05:18.085849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 18:05:18.092690 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 18:05:18.095935 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 18:05:18.099273 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 18:05:18.106024 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 18:05:18.109143 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 18:05:18.112116 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 18:05:18.119323 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3463 18:05:18.122286 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3464 18:05:18.125834 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3465 18:05:18.128634 Total UI for P1: 0, mck2ui 16
3466 18:05:18.132572 best dqsien dly found for B1: ( 1, 3, 22)
3467 18:05:18.135669 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 18:05:18.138759 Total UI for P1: 0, mck2ui 16
3469 18:05:18.141799 best dqsien dly found for B0: ( 1, 3, 26)
3470 18:05:18.145390 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3471 18:05:18.152322 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3472 18:05:18.152470
3473 18:05:18.155400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3474 18:05:18.158464 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3475 18:05:18.162188 [Gating] SW calibration Done
3476 18:05:18.162295 ==
3477 18:05:18.165628 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 18:05:18.168461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 18:05:18.168561 ==
3480 18:05:18.171781 RX Vref Scan: 0
3481 18:05:18.171884
3482 18:05:18.171975 RX Vref 0 -> 0, step: 1
3483 18:05:18.172063
3484 18:05:18.175340 RX Delay -40 -> 252, step: 8
3485 18:05:18.178710 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3486 18:05:18.181642 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3487 18:05:18.188743 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3488 18:05:18.191614 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3489 18:05:18.194921 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3490 18:05:18.198681 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3491 18:05:18.201573 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3492 18:05:18.208799 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3493 18:05:18.211553 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3494 18:05:18.215112 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3495 18:05:18.218375 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3496 18:05:18.221754 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3497 18:05:18.228218 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3498 18:05:18.231929 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3499 18:05:18.234814 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3500 18:05:18.238435 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3501 18:05:18.238518 ==
3502 18:05:18.241521 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 18:05:18.248464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 18:05:18.248553 ==
3505 18:05:18.248617 DQS Delay:
3506 18:05:18.251422 DQS0 = 0, DQS1 = 0
3507 18:05:18.251525 DQM Delay:
3508 18:05:18.255213 DQM0 = 121, DQM1 = 117
3509 18:05:18.255285 DQ Delay:
3510 18:05:18.258305 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3511 18:05:18.261391 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3512 18:05:18.265146 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3513 18:05:18.268079 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3514 18:05:18.268178
3515 18:05:18.268245
3516 18:05:18.268306 ==
3517 18:05:18.271940 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 18:05:18.278495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 18:05:18.278580 ==
3520 18:05:18.278645
3521 18:05:18.278705
3522 18:05:18.278783 TX Vref Scan disable
3523 18:05:18.281483 == TX Byte 0 ==
3524 18:05:18.284913 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3525 18:05:18.291512 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3526 18:05:18.291623 == TX Byte 1 ==
3527 18:05:18.294988 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3528 18:05:18.301526 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3529 18:05:18.301613 ==
3530 18:05:18.304374 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 18:05:18.307987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 18:05:18.308109 ==
3533 18:05:18.319038 TX Vref=22, minBit 0, minWin=25, winSum=420
3534 18:05:18.322630 TX Vref=24, minBit 1, minWin=26, winSum=424
3535 18:05:18.325666 TX Vref=26, minBit 1, minWin=25, winSum=426
3536 18:05:18.329465 TX Vref=28, minBit 8, minWin=26, winSum=432
3537 18:05:18.332511 TX Vref=30, minBit 9, minWin=26, winSum=435
3538 18:05:18.339413 TX Vref=32, minBit 6, minWin=26, winSum=434
3539 18:05:18.342387 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3540 18:05:18.342472
3541 18:05:18.346293 Final TX Range 1 Vref 30
3542 18:05:18.346393
3543 18:05:18.346491 ==
3544 18:05:18.349464 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 18:05:18.352325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 18:05:18.352448 ==
3547 18:05:18.356158
3548 18:05:18.356240
3549 18:05:18.356304 TX Vref Scan disable
3550 18:05:18.359157 == TX Byte 0 ==
3551 18:05:18.362228 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3552 18:05:18.365930 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3553 18:05:18.368925 == TX Byte 1 ==
3554 18:05:18.372673 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3555 18:05:18.378717 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3556 18:05:18.378802
3557 18:05:18.378868 [DATLAT]
3558 18:05:18.378928 Freq=1200, CH1 RK1
3559 18:05:18.378987
3560 18:05:18.382379 DATLAT Default: 0xd
3561 18:05:18.382463 0, 0xFFFF, sum = 0
3562 18:05:18.385322 1, 0xFFFF, sum = 0
3563 18:05:18.385407 2, 0xFFFF, sum = 0
3564 18:05:18.389096 3, 0xFFFF, sum = 0
3565 18:05:18.392255 4, 0xFFFF, sum = 0
3566 18:05:18.392400 5, 0xFFFF, sum = 0
3567 18:05:18.395332 6, 0xFFFF, sum = 0
3568 18:05:18.395417 7, 0xFFFF, sum = 0
3569 18:05:18.398846 8, 0xFFFF, sum = 0
3570 18:05:18.398931 9, 0xFFFF, sum = 0
3571 18:05:18.402360 10, 0xFFFF, sum = 0
3572 18:05:18.402445 11, 0xFFFF, sum = 0
3573 18:05:18.405050 12, 0x0, sum = 1
3574 18:05:18.405134 13, 0x0, sum = 2
3575 18:05:18.408475 14, 0x0, sum = 3
3576 18:05:18.408560 15, 0x0, sum = 4
3577 18:05:18.411953 best_step = 13
3578 18:05:18.412039
3579 18:05:18.412105 ==
3580 18:05:18.415388 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 18:05:18.418499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 18:05:18.418618 ==
3583 18:05:18.418687 RX Vref Scan: 0
3584 18:05:18.421820
3585 18:05:18.421905 RX Vref 0 -> 0, step: 1
3586 18:05:18.421971
3587 18:05:18.425412 RX Delay -5 -> 252, step: 4
3588 18:05:18.428544 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3589 18:05:18.435123 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3590 18:05:18.438129 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3591 18:05:18.441967 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3592 18:05:18.444844 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3593 18:05:18.448441 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3594 18:05:18.455256 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3595 18:05:18.458295 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3596 18:05:18.461316 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3597 18:05:18.465191 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3598 18:05:18.468336 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3599 18:05:18.475040 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3600 18:05:18.478174 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3601 18:05:18.481264 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3602 18:05:18.484958 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3603 18:05:18.491614 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3604 18:05:18.491726 ==
3605 18:05:18.494781 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 18:05:18.498548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 18:05:18.498633 ==
3608 18:05:18.498698 DQS Delay:
3609 18:05:18.501619 DQS0 = 0, DQS1 = 0
3610 18:05:18.501703 DQM Delay:
3611 18:05:18.504622 DQM0 = 120, DQM1 = 118
3612 18:05:18.504721 DQ Delay:
3613 18:05:18.508372 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3614 18:05:18.511586 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3615 18:05:18.514406 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3616 18:05:18.518039 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3617 18:05:18.518123
3618 18:05:18.518189
3619 18:05:18.528046 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3620 18:05:18.531325 CH1 RK1: MR19=403, MR18=10ED
3621 18:05:18.538006 CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3622 18:05:18.538097 [RxdqsGatingPostProcess] freq 1200
3623 18:05:18.544196 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3624 18:05:18.548233 best DQS0 dly(2T, 0.5T) = (0, 11)
3625 18:05:18.551444 best DQS1 dly(2T, 0.5T) = (0, 11)
3626 18:05:18.554424 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3627 18:05:18.557901 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3628 18:05:18.579632 best DQS0 dly(2T, 0.5T) = (0, 11)
3629 18:05:18.579810 best DQS1 dly(2T, 0.5T) = (0, 11)
3630 18:05:18.579965 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3631 18:05:18.580056 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3632 18:05:18.580168 Pre-setting of DQS Precalculation
3633 18:05:18.580249 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3634 18:05:18.584411 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3635 18:05:18.593975 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3636 18:05:18.594077
3637 18:05:18.594147
3638 18:05:18.597892 [Calibration Summary] 2400 Mbps
3639 18:05:18.597968 CH 0, Rank 0
3640 18:05:18.600982 SW Impedance : PASS
3641 18:05:18.601067 DUTY Scan : NO K
3642 18:05:18.604007 ZQ Calibration : PASS
3643 18:05:18.604117 Jitter Meter : NO K
3644 18:05:18.607836 CBT Training : PASS
3645 18:05:18.610880 Write leveling : PASS
3646 18:05:18.610966 RX DQS gating : PASS
3647 18:05:18.613976 RX DQ/DQS(RDDQC) : PASS
3648 18:05:18.617169 TX DQ/DQS : PASS
3649 18:05:18.617255 RX DATLAT : PASS
3650 18:05:18.620638 RX DQ/DQS(Engine): PASS
3651 18:05:18.623765 TX OE : NO K
3652 18:05:18.623851 All Pass.
3653 18:05:18.623918
3654 18:05:18.623979 CH 0, Rank 1
3655 18:05:18.627306 SW Impedance : PASS
3656 18:05:18.630861 DUTY Scan : NO K
3657 18:05:18.630946 ZQ Calibration : PASS
3658 18:05:18.633791 Jitter Meter : NO K
3659 18:05:18.637658 CBT Training : PASS
3660 18:05:18.637745 Write leveling : PASS
3661 18:05:18.640766 RX DQS gating : PASS
3662 18:05:18.643728 RX DQ/DQS(RDDQC) : PASS
3663 18:05:18.643812 TX DQ/DQS : PASS
3664 18:05:18.647483 RX DATLAT : PASS
3665 18:05:18.650657 RX DQ/DQS(Engine): PASS
3666 18:05:18.650742 TX OE : NO K
3667 18:05:18.650810 All Pass.
3668 18:05:18.653689
3669 18:05:18.653773 CH 1, Rank 0
3670 18:05:18.656818 SW Impedance : PASS
3671 18:05:18.656903 DUTY Scan : NO K
3672 18:05:18.660316 ZQ Calibration : PASS
3673 18:05:18.663470 Jitter Meter : NO K
3674 18:05:18.663556 CBT Training : PASS
3675 18:05:18.667148 Write leveling : PASS
3676 18:05:18.670084 RX DQS gating : PASS
3677 18:05:18.670171 RX DQ/DQS(RDDQC) : PASS
3678 18:05:18.673421 TX DQ/DQS : PASS
3679 18:05:18.673508 RX DATLAT : PASS
3680 18:05:18.676720 RX DQ/DQS(Engine): PASS
3681 18:05:18.679798 TX OE : NO K
3682 18:05:18.679886 All Pass.
3683 18:05:18.679952
3684 18:05:18.680013 CH 1, Rank 1
3685 18:05:18.683199 SW Impedance : PASS
3686 18:05:18.686573 DUTY Scan : NO K
3687 18:05:18.686662 ZQ Calibration : PASS
3688 18:05:18.689771 Jitter Meter : NO K
3689 18:05:18.693655 CBT Training : PASS
3690 18:05:18.693757 Write leveling : PASS
3691 18:05:18.696629 RX DQS gating : PASS
3692 18:05:18.700097 RX DQ/DQS(RDDQC) : PASS
3693 18:05:18.700213 TX DQ/DQS : PASS
3694 18:05:18.703480 RX DATLAT : PASS
3695 18:05:18.706255 RX DQ/DQS(Engine): PASS
3696 18:05:18.706375 TX OE : NO K
3697 18:05:18.709744 All Pass.
3698 18:05:18.709863
3699 18:05:18.709972 DramC Write-DBI off
3700 18:05:18.713180 PER_BANK_REFRESH: Hybrid Mode
3701 18:05:18.713273 TX_TRACKING: ON
3702 18:05:18.722833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3703 18:05:18.726659 [FAST_K] Save calibration result to emmc
3704 18:05:18.729674 dramc_set_vcore_voltage set vcore to 650000
3705 18:05:18.733463 Read voltage for 600, 5
3706 18:05:18.733567 Vio18 = 0
3707 18:05:18.736254 Vcore = 650000
3708 18:05:18.736375 Vdram = 0
3709 18:05:18.736453 Vddq = 0
3710 18:05:18.736511 Vmddr = 0
3711 18:05:18.743401 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3712 18:05:18.749571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3713 18:05:18.749676 MEM_TYPE=3, freq_sel=19
3714 18:05:18.753467 sv_algorithm_assistance_LP4_1600
3715 18:05:18.756715 ============ PULL DRAM RESETB DOWN ============
3716 18:05:18.762973 ========== PULL DRAM RESETB DOWN end =========
3717 18:05:18.766911 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3718 18:05:18.769826 ===================================
3719 18:05:18.772926 LPDDR4 DRAM CONFIGURATION
3720 18:05:18.776730 ===================================
3721 18:05:18.776819 EX_ROW_EN[0] = 0x0
3722 18:05:18.779902 EX_ROW_EN[1] = 0x0
3723 18:05:18.782844 LP4Y_EN = 0x0
3724 18:05:18.782928 WORK_FSP = 0x0
3725 18:05:18.786435 WL = 0x2
3726 18:05:18.786511 RL = 0x2
3727 18:05:18.789315 BL = 0x2
3728 18:05:18.789394 RPST = 0x0
3729 18:05:18.793145 RD_PRE = 0x0
3730 18:05:18.793225 WR_PRE = 0x1
3731 18:05:18.796140 WR_PST = 0x0
3732 18:05:18.796240 DBI_WR = 0x0
3733 18:05:18.799245 DBI_RD = 0x0
3734 18:05:18.799323 OTF = 0x1
3735 18:05:18.802985 ===================================
3736 18:05:18.805965 ===================================
3737 18:05:18.809541 ANA top config
3738 18:05:18.812223 ===================================
3739 18:05:18.812361 DLL_ASYNC_EN = 0
3740 18:05:18.816157 ALL_SLAVE_EN = 1
3741 18:05:18.819607 NEW_RANK_MODE = 1
3742 18:05:18.822721 DLL_IDLE_MODE = 1
3743 18:05:18.825870 LP45_APHY_COMB_EN = 1
3744 18:05:18.825987 TX_ODT_DIS = 1
3745 18:05:18.829172 NEW_8X_MODE = 1
3746 18:05:18.832173 ===================================
3747 18:05:18.836015 ===================================
3748 18:05:18.839237 data_rate = 1200
3749 18:05:18.842513 CKR = 1
3750 18:05:18.845570 DQ_P2S_RATIO = 8
3751 18:05:18.849618 ===================================
3752 18:05:18.849736 CA_P2S_RATIO = 8
3753 18:05:18.852229 DQ_CA_OPEN = 0
3754 18:05:18.855661 DQ_SEMI_OPEN = 0
3755 18:05:18.859459 CA_SEMI_OPEN = 0
3756 18:05:18.862612 CA_FULL_RATE = 0
3757 18:05:18.865732 DQ_CKDIV4_EN = 1
3758 18:05:18.865829 CA_CKDIV4_EN = 1
3759 18:05:18.869426 CA_PREDIV_EN = 0
3760 18:05:18.872447 PH8_DLY = 0
3761 18:05:18.875543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3762 18:05:18.878726 DQ_AAMCK_DIV = 4
3763 18:05:18.882792 CA_AAMCK_DIV = 4
3764 18:05:18.882898 CA_ADMCK_DIV = 4
3765 18:05:18.885673 DQ_TRACK_CA_EN = 0
3766 18:05:18.888694 CA_PICK = 600
3767 18:05:18.892409 CA_MCKIO = 600
3768 18:05:18.895292 MCKIO_SEMI = 0
3769 18:05:18.898899 PLL_FREQ = 2288
3770 18:05:18.902050 DQ_UI_PI_RATIO = 32
3771 18:05:18.902140 CA_UI_PI_RATIO = 0
3772 18:05:18.905992 ===================================
3773 18:05:18.908996 ===================================
3774 18:05:18.911925 memory_type:LPDDR4
3775 18:05:18.915733 GP_NUM : 10
3776 18:05:18.915816 SRAM_EN : 1
3777 18:05:18.918667 MD32_EN : 0
3778 18:05:18.922404 ===================================
3779 18:05:18.925456 [ANA_INIT] >>>>>>>>>>>>>>
3780 18:05:18.929218 <<<<<< [CONFIGURE PHASE]: ANA_TX
3781 18:05:18.932232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3782 18:05:18.935862 ===================================
3783 18:05:18.935947 data_rate = 1200,PCW = 0X5800
3784 18:05:18.938643 ===================================
3785 18:05:18.942154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3786 18:05:18.948443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3787 18:05:18.955397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 18:05:18.958536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3789 18:05:18.962027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3790 18:05:18.965216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3791 18:05:18.968494 [ANA_INIT] flow start
3792 18:05:18.971961 [ANA_INIT] PLL >>>>>>>>
3793 18:05:18.972046 [ANA_INIT] PLL <<<<<<<<
3794 18:05:18.975110 [ANA_INIT] MIDPI >>>>>>>>
3795 18:05:18.978664 [ANA_INIT] MIDPI <<<<<<<<
3796 18:05:18.978751 [ANA_INIT] DLL >>>>>>>>
3797 18:05:18.982023 [ANA_INIT] flow end
3798 18:05:18.985121 ============ LP4 DIFF to SE enter ============
3799 18:05:18.988881 ============ LP4 DIFF to SE exit ============
3800 18:05:18.991896 [ANA_INIT] <<<<<<<<<<<<<
3801 18:05:18.995015 [Flow] Enable top DCM control >>>>>
3802 18:05:18.998889 [Flow] Enable top DCM control <<<<<
3803 18:05:19.001744 Enable DLL master slave shuffle
3804 18:05:19.008500 ==============================================================
3805 18:05:19.008603 Gating Mode config
3806 18:05:19.014808 ==============================================================
3807 18:05:19.014909 Config description:
3808 18:05:19.025258 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3809 18:05:19.031457 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3810 18:05:19.038159 SELPH_MODE 0: By rank 1: By Phase
3811 18:05:19.041348 ==============================================================
3812 18:05:19.045270 GAT_TRACK_EN = 1
3813 18:05:19.048140 RX_GATING_MODE = 2
3814 18:05:19.051617 RX_GATING_TRACK_MODE = 2
3815 18:05:19.054638 SELPH_MODE = 1
3816 18:05:19.057817 PICG_EARLY_EN = 1
3817 18:05:19.061568 VALID_LAT_VALUE = 1
3818 18:05:19.067660 ==============================================================
3819 18:05:19.071273 Enter into Gating configuration >>>>
3820 18:05:19.074304 Exit from Gating configuration <<<<
3821 18:05:19.078138 Enter into DVFS_PRE_config >>>>>
3822 18:05:19.088013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3823 18:05:19.090833 Exit from DVFS_PRE_config <<<<<
3824 18:05:19.094663 Enter into PICG configuration >>>>
3825 18:05:19.097911 Exit from PICG configuration <<<<
3826 18:05:19.101040 [RX_INPUT] configuration >>>>>
3827 18:05:19.101129 [RX_INPUT] configuration <<<<<
3828 18:05:19.107930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3829 18:05:19.114410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3830 18:05:19.117978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3831 18:05:19.123983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3832 18:05:19.130687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3833 18:05:19.137381 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3834 18:05:19.141064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3835 18:05:19.143979 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3836 18:05:19.150890 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3837 18:05:19.154608 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3838 18:05:19.157414 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3839 18:05:19.161165 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 18:05:19.164183 ===================================
3841 18:05:19.167841 LPDDR4 DRAM CONFIGURATION
3842 18:05:19.170816 ===================================
3843 18:05:19.174479 EX_ROW_EN[0] = 0x0
3844 18:05:19.174568 EX_ROW_EN[1] = 0x0
3845 18:05:19.177448 LP4Y_EN = 0x0
3846 18:05:19.177534 WORK_FSP = 0x0
3847 18:05:19.181241 WL = 0x2
3848 18:05:19.181327 RL = 0x2
3849 18:05:19.184385 BL = 0x2
3850 18:05:19.184470 RPST = 0x0
3851 18:05:19.187427 RD_PRE = 0x0
3852 18:05:19.187511 WR_PRE = 0x1
3853 18:05:19.191097 WR_PST = 0x0
3854 18:05:19.194158 DBI_WR = 0x0
3855 18:05:19.194243 DBI_RD = 0x0
3856 18:05:19.198023 OTF = 0x1
3857 18:05:19.200864 ===================================
3858 18:05:19.204269 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3859 18:05:19.207768 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3860 18:05:19.210531 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 18:05:19.213739 ===================================
3862 18:05:19.217234 LPDDR4 DRAM CONFIGURATION
3863 18:05:19.220395 ===================================
3864 18:05:19.224085 EX_ROW_EN[0] = 0x10
3865 18:05:19.224207 EX_ROW_EN[1] = 0x0
3866 18:05:19.227345 LP4Y_EN = 0x0
3867 18:05:19.227431 WORK_FSP = 0x0
3868 18:05:19.230669 WL = 0x2
3869 18:05:19.230754 RL = 0x2
3870 18:05:19.233822 BL = 0x2
3871 18:05:19.233907 RPST = 0x0
3872 18:05:19.237477 RD_PRE = 0x0
3873 18:05:19.237564 WR_PRE = 0x1
3874 18:05:19.240943 WR_PST = 0x0
3875 18:05:19.241034 DBI_WR = 0x0
3876 18:05:19.243955 DBI_RD = 0x0
3877 18:05:19.247050 OTF = 0x1
3878 18:05:19.250652 ===================================
3879 18:05:19.253745 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3880 18:05:19.259092 nWR fixed to 30
3881 18:05:19.262128 [ModeRegInit_LP4] CH0 RK0
3882 18:05:19.262217 [ModeRegInit_LP4] CH0 RK1
3883 18:05:19.265619 [ModeRegInit_LP4] CH1 RK0
3884 18:05:19.268682 [ModeRegInit_LP4] CH1 RK1
3885 18:05:19.268770 match AC timing 17
3886 18:05:19.275398 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3887 18:05:19.279083 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3888 18:05:19.282444 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3889 18:05:19.289022 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3890 18:05:19.292078 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3891 18:05:19.292205 ==
3892 18:05:19.295820 Dram Type= 6, Freq= 0, CH_0, rank 0
3893 18:05:19.298948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3894 18:05:19.299059 ==
3895 18:05:19.305770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3896 18:05:19.312559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3897 18:05:19.315521 [CA 0] Center 35 (5~66) winsize 62
3898 18:05:19.318663 [CA 1] Center 35 (5~66) winsize 62
3899 18:05:19.322415 [CA 2] Center 33 (3~64) winsize 62
3900 18:05:19.325484 [CA 3] Center 33 (2~64) winsize 63
3901 18:05:19.329309 [CA 4] Center 33 (2~64) winsize 63
3902 18:05:19.332227 [CA 5] Center 32 (2~63) winsize 62
3903 18:05:19.332331
3904 18:05:19.335796 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3905 18:05:19.335911
3906 18:05:19.338690 [CATrainingPosCal] consider 1 rank data
3907 18:05:19.342086 u2DelayCellTimex100 = 270/100 ps
3908 18:05:19.345392 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3909 18:05:19.348385 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3910 18:05:19.352297 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3911 18:05:19.355367 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3912 18:05:19.358518 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3913 18:05:19.365001 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3914 18:05:19.365126
3915 18:05:19.368208 CA PerBit enable=1, Macro0, CA PI delay=32
3916 18:05:19.368323
3917 18:05:19.371589 [CBTSetCACLKResult] CA Dly = 32
3918 18:05:19.371710 CS Dly: 5 (0~36)
3919 18:05:19.371816 ==
3920 18:05:19.375146 Dram Type= 6, Freq= 0, CH_0, rank 1
3921 18:05:19.378300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 18:05:19.381378 ==
3923 18:05:19.385031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 18:05:19.391307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3925 18:05:19.394799 [CA 0] Center 35 (5~66) winsize 62
3926 18:05:19.397980 [CA 1] Center 35 (5~66) winsize 62
3927 18:05:19.401740 [CA 2] Center 34 (3~65) winsize 63
3928 18:05:19.404769 [CA 3] Center 33 (3~64) winsize 62
3929 18:05:19.408499 [CA 4] Center 32 (2~63) winsize 62
3930 18:05:19.411646 [CA 5] Center 32 (2~63) winsize 62
3931 18:05:19.411732
3932 18:05:19.414466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3933 18:05:19.414550
3934 18:05:19.418206 [CATrainingPosCal] consider 2 rank data
3935 18:05:19.421285 u2DelayCellTimex100 = 270/100 ps
3936 18:05:19.424467 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3937 18:05:19.427990 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 18:05:19.430980 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3939 18:05:19.437758 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3940 18:05:19.441554 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3941 18:05:19.444630 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3942 18:05:19.444718
3943 18:05:19.447771 CA PerBit enable=1, Macro0, CA PI delay=32
3944 18:05:19.447856
3945 18:05:19.450768 [CBTSetCACLKResult] CA Dly = 32
3946 18:05:19.450854 CS Dly: 5 (0~36)
3947 18:05:19.450920
3948 18:05:19.454503 ----->DramcWriteLeveling(PI) begin...
3949 18:05:19.458034 ==
3950 18:05:19.458121 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 18:05:19.464222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 18:05:19.464348 ==
3953 18:05:19.467873 Write leveling (Byte 0): 33 => 33
3954 18:05:19.470751 Write leveling (Byte 1): 31 => 31
3955 18:05:19.470837 DramcWriteLeveling(PI) end<-----
3956 18:05:19.474231
3957 18:05:19.474316 ==
3958 18:05:19.477737 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 18:05:19.481038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 18:05:19.481123 ==
3961 18:05:19.484437 [Gating] SW mode calibration
3962 18:05:19.490922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3963 18:05:19.493996 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3964 18:05:19.500940 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3965 18:05:19.503914 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 18:05:19.507851 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 18:05:19.513813 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
3968 18:05:19.517611 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3969 18:05:19.520643 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 18:05:19.527492 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 18:05:19.530468 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 18:05:19.534159 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 18:05:19.540927 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 18:05:19.544034 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 18:05:19.547013 0 10 12 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
3976 18:05:19.554014 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
3977 18:05:19.557206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 18:05:19.560223 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 18:05:19.566761 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 18:05:19.570550 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 18:05:19.573685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 18:05:19.580366 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 18:05:19.583425 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3984 18:05:19.587252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3985 18:05:19.593587 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 18:05:19.596588 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 18:05:19.600200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 18:05:19.607110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 18:05:19.610009 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 18:05:19.613472 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 18:05:19.620203 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 18:05:19.623239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 18:05:19.626512 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 18:05:19.633246 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 18:05:19.636319 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 18:05:19.639597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 18:05:19.646560 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 18:05:19.649776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 18:05:19.653622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4000 18:05:19.659863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 18:05:19.659987 Total UI for P1: 0, mck2ui 16
4002 18:05:19.662828 best dqsien dly found for B0: ( 0, 13, 12)
4003 18:05:19.666583 Total UI for P1: 0, mck2ui 16
4004 18:05:19.670080 best dqsien dly found for B1: ( 0, 13, 14)
4005 18:05:19.672926 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4006 18:05:19.679834 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4007 18:05:19.679957
4008 18:05:19.682833 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4009 18:05:19.685973 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4010 18:05:19.689786 [Gating] SW calibration Done
4011 18:05:19.689869 ==
4012 18:05:19.692867 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 18:05:19.696599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 18:05:19.696717 ==
4015 18:05:19.699561 RX Vref Scan: 0
4016 18:05:19.699650
4017 18:05:19.699717 RX Vref 0 -> 0, step: 1
4018 18:05:19.699779
4019 18:05:19.703274 RX Delay -230 -> 252, step: 16
4020 18:05:19.706056 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4021 18:05:19.712682 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4022 18:05:19.716398 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4023 18:05:19.719422 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4024 18:05:19.723152 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4025 18:05:19.726094 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4026 18:05:19.732779 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4027 18:05:19.736719 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4028 18:05:19.739490 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4029 18:05:19.742730 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4030 18:05:19.749535 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4031 18:05:19.752727 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4032 18:05:19.755982 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4033 18:05:19.759505 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4034 18:05:19.765844 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4035 18:05:19.769048 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4036 18:05:19.769165 ==
4037 18:05:19.772378 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 18:05:19.775931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 18:05:19.776016 ==
4040 18:05:19.779663 DQS Delay:
4041 18:05:19.779774 DQS0 = 0, DQS1 = 0
4042 18:05:19.779868 DQM Delay:
4043 18:05:19.782369 DQM0 = 53, DQM1 = 46
4044 18:05:19.782470 DQ Delay:
4045 18:05:19.786172 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4046 18:05:19.789127 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =65
4047 18:05:19.793030 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4048 18:05:19.796190 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4049 18:05:19.796281
4050 18:05:19.796377
4051 18:05:19.796440 ==
4052 18:05:19.799395 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 18:05:19.805512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 18:05:19.805595 ==
4055 18:05:19.805665
4056 18:05:19.805726
4057 18:05:19.805784 TX Vref Scan disable
4058 18:05:19.809151 == TX Byte 0 ==
4059 18:05:19.812942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4060 18:05:19.819299 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4061 18:05:19.819412 == TX Byte 1 ==
4062 18:05:19.822353 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4063 18:05:19.829235 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4064 18:05:19.829361 ==
4065 18:05:19.832906 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 18:05:19.835962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 18:05:19.836067 ==
4068 18:05:19.836167
4069 18:05:19.836258
4070 18:05:19.839737 TX Vref Scan disable
4071 18:05:19.839841 == TX Byte 0 ==
4072 18:05:19.845734 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4073 18:05:19.849326 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4074 18:05:19.852316 == TX Byte 1 ==
4075 18:05:19.856270 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4076 18:05:19.859147 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4077 18:05:19.859232
4078 18:05:19.859298 [DATLAT]
4079 18:05:19.862874 Freq=600, CH0 RK0
4080 18:05:19.862951
4081 18:05:19.863014 DATLAT Default: 0x9
4082 18:05:19.865555 0, 0xFFFF, sum = 0
4083 18:05:19.865673 1, 0xFFFF, sum = 0
4084 18:05:19.869298 2, 0xFFFF, sum = 0
4085 18:05:19.872237 3, 0xFFFF, sum = 0
4086 18:05:19.872347 4, 0xFFFF, sum = 0
4087 18:05:19.875785 5, 0xFFFF, sum = 0
4088 18:05:19.875889 6, 0xFFFF, sum = 0
4089 18:05:19.879478 7, 0xFFFF, sum = 0
4090 18:05:19.879585 8, 0x0, sum = 1
4091 18:05:19.879690 9, 0x0, sum = 2
4092 18:05:19.882680 10, 0x0, sum = 3
4093 18:05:19.882785 11, 0x0, sum = 4
4094 18:05:19.886011 best_step = 9
4095 18:05:19.886099
4096 18:05:19.886170 ==
4097 18:05:19.889398 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 18:05:19.892715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 18:05:19.892825 ==
4100 18:05:19.895401 RX Vref Scan: 1
4101 18:05:19.895512
4102 18:05:19.895608 RX Vref 0 -> 0, step: 1
4103 18:05:19.895701
4104 18:05:19.898958 RX Delay -163 -> 252, step: 8
4105 18:05:19.899062
4106 18:05:19.902670 Set Vref, RX VrefLevel [Byte0]: 55
4107 18:05:19.905790 [Byte1]: 49
4108 18:05:19.909760
4109 18:05:19.909872 Final RX Vref Byte 0 = 55 to rank0
4110 18:05:19.913434 Final RX Vref Byte 1 = 49 to rank0
4111 18:05:19.916480 Final RX Vref Byte 0 = 55 to rank1
4112 18:05:19.919385 Final RX Vref Byte 1 = 49 to rank1==
4113 18:05:19.923146 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 18:05:19.929712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 18:05:19.929840 ==
4116 18:05:19.929940 DQS Delay:
4117 18:05:19.930034 DQS0 = 0, DQS1 = 0
4118 18:05:19.932787 DQM Delay:
4119 18:05:19.932896 DQM0 = 53, DQM1 = 46
4120 18:05:19.936448 DQ Delay:
4121 18:05:19.939517 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4122 18:05:19.942659 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4123 18:05:19.946610 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4124 18:05:19.949624 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4125 18:05:19.949732
4126 18:05:19.949826
4127 18:05:19.956034 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4128 18:05:19.959289 CH0 RK0: MR19=808, MR18=6D60
4129 18:05:19.966114 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4130 18:05:19.966224
4131 18:05:19.969686 ----->DramcWriteLeveling(PI) begin...
4132 18:05:19.969797 ==
4133 18:05:19.972517 Dram Type= 6, Freq= 0, CH_0, rank 1
4134 18:05:19.976121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 18:05:19.976222 ==
4136 18:05:19.978956 Write leveling (Byte 0): 34 => 34
4137 18:05:19.982673 Write leveling (Byte 1): 30 => 30
4138 18:05:19.985734 DramcWriteLeveling(PI) end<-----
4139 18:05:19.985818
4140 18:05:19.985885 ==
4141 18:05:19.989572 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 18:05:19.992328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 18:05:19.992421 ==
4144 18:05:19.995932 [Gating] SW mode calibration
4145 18:05:20.002340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4146 18:05:20.009262 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4147 18:05:20.012574 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4148 18:05:20.019119 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 18:05:20.022003 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 18:05:20.025598 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4151 18:05:20.032017 0 9 16 | B1->B0 | 2626 2828 | 0 0 | (0 0) (1 1)
4152 18:05:20.035644 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 18:05:20.038690 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 18:05:20.045442 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 18:05:20.048529 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 18:05:20.052418 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 18:05:20.059050 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 18:05:20.062059 0 10 12 | B1->B0 | 2525 2626 | 1 0 | (0 0) (0 0)
4159 18:05:20.065202 0 10 16 | B1->B0 | 4444 4242 | 0 0 | (0 0) (0 0)
4160 18:05:20.069121 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 18:05:20.075244 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 18:05:20.079041 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 18:05:20.082398 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 18:05:20.088921 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 18:05:20.091826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 18:05:20.095615 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4167 18:05:20.102186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 18:05:20.105185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 18:05:20.108353 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 18:05:20.115186 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 18:05:20.118789 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 18:05:20.122468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 18:05:20.128549 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 18:05:20.131845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 18:05:20.135094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 18:05:20.141715 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 18:05:20.145540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 18:05:20.148277 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 18:05:20.155184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 18:05:20.158254 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 18:05:20.161970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 18:05:20.168672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4183 18:05:20.171689 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4184 18:05:20.175516 Total UI for P1: 0, mck2ui 16
4185 18:05:20.178411 best dqsien dly found for B0: ( 0, 13, 12)
4186 18:05:20.181471 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 18:05:20.185084 Total UI for P1: 0, mck2ui 16
4188 18:05:20.188199 best dqsien dly found for B1: ( 0, 13, 14)
4189 18:05:20.191998 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4190 18:05:20.195337 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4191 18:05:20.195450
4192 18:05:20.198188 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4193 18:05:20.205150 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4194 18:05:20.205231 [Gating] SW calibration Done
4195 18:05:20.208074 ==
4196 18:05:20.208178 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 18:05:20.214775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 18:05:20.214880 ==
4199 18:05:20.214973 RX Vref Scan: 0
4200 18:05:20.215074
4201 18:05:20.218711 RX Vref 0 -> 0, step: 1
4202 18:05:20.218812
4203 18:05:20.221854 RX Delay -230 -> 252, step: 16
4204 18:05:20.224877 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4205 18:05:20.228700 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4206 18:05:20.234741 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4207 18:05:20.238627 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4208 18:05:20.241323 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4209 18:05:20.244781 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4210 18:05:20.248118 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4211 18:05:20.254694 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4212 18:05:20.258373 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4213 18:05:20.261465 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4214 18:05:20.264770 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4215 18:05:20.271080 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4216 18:05:20.274996 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4217 18:05:20.277822 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4218 18:05:20.281402 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4219 18:05:20.288095 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4220 18:05:20.288224 ==
4221 18:05:20.291168 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 18:05:20.294767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 18:05:20.294856 ==
4224 18:05:20.294924 DQS Delay:
4225 18:05:20.297967 DQS0 = 0, DQS1 = 0
4226 18:05:20.298043 DQM Delay:
4227 18:05:20.301347 DQM0 = 52, DQM1 = 44
4228 18:05:20.301422 DQ Delay:
4229 18:05:20.304762 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4230 18:05:20.307592 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4231 18:05:20.311523 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4232 18:05:20.314302 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4233 18:05:20.314383
4234 18:05:20.314450
4235 18:05:20.314510 ==
4236 18:05:20.318096 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 18:05:20.321058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 18:05:20.321139 ==
4239 18:05:20.321205
4240 18:05:20.324214
4241 18:05:20.324322 TX Vref Scan disable
4242 18:05:20.327413 == TX Byte 0 ==
4243 18:05:20.331142 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4244 18:05:20.334038 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4245 18:05:20.337626 == TX Byte 1 ==
4246 18:05:20.340727 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4247 18:05:20.343938 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4248 18:05:20.344039 ==
4249 18:05:20.347794 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 18:05:20.354510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 18:05:20.354629 ==
4252 18:05:20.354729
4253 18:05:20.354824
4254 18:05:20.354913 TX Vref Scan disable
4255 18:05:20.358817 == TX Byte 0 ==
4256 18:05:20.362567 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4257 18:05:20.365542 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4258 18:05:20.368952 == TX Byte 1 ==
4259 18:05:20.372454 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4260 18:05:20.375637 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4261 18:05:20.378801
4262 18:05:20.378910 [DATLAT]
4263 18:05:20.378980 Freq=600, CH0 RK1
4264 18:05:20.379048
4265 18:05:20.382275 DATLAT Default: 0x9
4266 18:05:20.382379 0, 0xFFFF, sum = 0
4267 18:05:20.385388 1, 0xFFFF, sum = 0
4268 18:05:20.385502 2, 0xFFFF, sum = 0
4269 18:05:20.389220 3, 0xFFFF, sum = 0
4270 18:05:20.389343 4, 0xFFFF, sum = 0
4271 18:05:20.391965 5, 0xFFFF, sum = 0
4272 18:05:20.395620 6, 0xFFFF, sum = 0
4273 18:05:20.395738 7, 0xFFFF, sum = 0
4274 18:05:20.395841 8, 0x0, sum = 1
4275 18:05:20.399001 9, 0x0, sum = 2
4276 18:05:20.399117 10, 0x0, sum = 3
4277 18:05:20.402776 11, 0x0, sum = 4
4278 18:05:20.402892 best_step = 9
4279 18:05:20.402987
4280 18:05:20.403076 ==
4281 18:05:20.405855 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 18:05:20.412360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 18:05:20.412456 ==
4284 18:05:20.412539 RX Vref Scan: 0
4285 18:05:20.412604
4286 18:05:20.415847 RX Vref 0 -> 0, step: 1
4287 18:05:20.415966
4288 18:05:20.419400 RX Delay -163 -> 252, step: 8
4289 18:05:20.422209 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4290 18:05:20.425698 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4291 18:05:20.432487 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4292 18:05:20.435605 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4293 18:05:20.438491 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4294 18:05:20.442191 iDelay=197, Bit 5, Center 48 (-91 ~ 188) 280
4295 18:05:20.445098 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4296 18:05:20.451986 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4297 18:05:20.455818 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4298 18:05:20.458900 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4299 18:05:20.461900 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4300 18:05:20.468725 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4301 18:05:20.471702 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4302 18:05:20.475357 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4303 18:05:20.478427 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4304 18:05:20.482191 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4305 18:05:20.485095 ==
4306 18:05:20.488504 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 18:05:20.491342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 18:05:20.491449 ==
4309 18:05:20.491543 DQS Delay:
4310 18:05:20.494936 DQS0 = 0, DQS1 = 0
4311 18:05:20.495049 DQM Delay:
4312 18:05:20.498082 DQM0 = 54, DQM1 = 47
4313 18:05:20.498191 DQ Delay:
4314 18:05:20.501503 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4315 18:05:20.504526 DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =60
4316 18:05:20.508049 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4317 18:05:20.511709 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4318 18:05:20.511824
4319 18:05:20.511920
4320 18:05:20.518149 [DQSOSCAuto] RK1, (LSB)MR18= 0x6525, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4321 18:05:20.521572 CH0 RK1: MR19=808, MR18=6525
4322 18:05:20.528430 CH0_RK1: MR19=0x808, MR18=0x6525, DQSOSC=390, MR23=63, INC=172, DEC=114
4323 18:05:20.531035 [RxdqsGatingPostProcess] freq 600
4324 18:05:20.537878 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4325 18:05:20.540953 Pre-setting of DQS Precalculation
4326 18:05:20.544661 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4327 18:05:20.544784 ==
4328 18:05:20.547534 Dram Type= 6, Freq= 0, CH_1, rank 0
4329 18:05:20.551486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 18:05:20.551605 ==
4331 18:05:20.557674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4332 18:05:20.564448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4333 18:05:20.568196 [CA 0] Center 35 (5~66) winsize 62
4334 18:05:20.571233 [CA 1] Center 36 (6~67) winsize 62
4335 18:05:20.574235 [CA 2] Center 34 (4~65) winsize 62
4336 18:05:20.578063 [CA 3] Center 34 (4~65) winsize 62
4337 18:05:20.581138 [CA 4] Center 34 (4~65) winsize 62
4338 18:05:20.584118 [CA 5] Center 34 (3~65) winsize 63
4339 18:05:20.584203
4340 18:05:20.588141 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4341 18:05:20.588245
4342 18:05:20.591069 [CATrainingPosCal] consider 1 rank data
4343 18:05:20.594135 u2DelayCellTimex100 = 270/100 ps
4344 18:05:20.597333 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4345 18:05:20.600898 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4346 18:05:20.604003 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4347 18:05:20.607798 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4348 18:05:20.611096 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4349 18:05:20.614442 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4350 18:05:20.617346
4351 18:05:20.620865 CA PerBit enable=1, Macro0, CA PI delay=34
4352 18:05:20.620974
4353 18:05:20.624308 [CBTSetCACLKResult] CA Dly = 34
4354 18:05:20.624415 CS Dly: 5 (0~36)
4355 18:05:20.624484 ==
4356 18:05:20.627273 Dram Type= 6, Freq= 0, CH_1, rank 1
4357 18:05:20.631114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 18:05:20.631224 ==
4359 18:05:20.637641 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 18:05:20.644335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4361 18:05:20.647846 [CA 0] Center 36 (6~67) winsize 62
4362 18:05:20.650521 [CA 1] Center 36 (6~67) winsize 62
4363 18:05:20.653868 [CA 2] Center 35 (4~66) winsize 63
4364 18:05:20.657219 [CA 3] Center 35 (4~66) winsize 63
4365 18:05:20.661034 [CA 4] Center 34 (4~65) winsize 62
4366 18:05:20.664125 [CA 5] Center 34 (4~65) winsize 62
4367 18:05:20.664206
4368 18:05:20.667344 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4369 18:05:20.667423
4370 18:05:20.670619 [CATrainingPosCal] consider 2 rank data
4371 18:05:20.673965 u2DelayCellTimex100 = 270/100 ps
4372 18:05:20.677023 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4373 18:05:20.680731 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4374 18:05:20.683832 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4375 18:05:20.687696 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4376 18:05:20.693766 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4377 18:05:20.696831 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 18:05:20.696939
4379 18:05:20.700573 CA PerBit enable=1, Macro0, CA PI delay=34
4380 18:05:20.700652
4381 18:05:20.703741 [CBTSetCACLKResult] CA Dly = 34
4382 18:05:20.703820 CS Dly: 6 (0~38)
4383 18:05:20.703894
4384 18:05:20.707722 ----->DramcWriteLeveling(PI) begin...
4385 18:05:20.707844 ==
4386 18:05:20.710559 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 18:05:20.717433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 18:05:20.717557 ==
4389 18:05:20.720542 Write leveling (Byte 0): 30 => 30
4390 18:05:20.720621 Write leveling (Byte 1): 30 => 30
4391 18:05:20.723729 DramcWriteLeveling(PI) end<-----
4392 18:05:20.723842
4393 18:05:20.727533 ==
4394 18:05:20.727631 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 18:05:20.733671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 18:05:20.733760 ==
4397 18:05:20.737244 [Gating] SW mode calibration
4398 18:05:20.743480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 18:05:20.746780 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4400 18:05:20.753553 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 18:05:20.756657 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 18:05:20.760488 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4403 18:05:20.766860 0 9 12 | B1->B0 | 2e2e 2e2e | 1 0 | (1 0) (0 0)
4404 18:05:20.770526 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 18:05:20.773295 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 18:05:20.779975 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 18:05:20.783420 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 18:05:20.786675 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 18:05:20.793545 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 18:05:20.796922 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
4411 18:05:20.800494 0 10 12 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4412 18:05:20.803536 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 18:05:20.810467 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 18:05:20.813578 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 18:05:20.816589 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 18:05:20.823444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 18:05:20.826607 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 18:05:20.830504 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 18:05:20.836590 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4420 18:05:20.840242 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 18:05:20.843318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 18:05:20.850562 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 18:05:20.853503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 18:05:20.856477 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 18:05:20.863457 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 18:05:20.866527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 18:05:20.870094 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 18:05:20.876665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 18:05:20.879443 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 18:05:20.883368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 18:05:20.889975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 18:05:20.893014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 18:05:20.895973 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 18:05:20.903084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4435 18:05:20.905916 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 18:05:20.909283 Total UI for P1: 0, mck2ui 16
4437 18:05:20.912670 best dqsien dly found for B0: ( 0, 13, 8)
4438 18:05:20.916175 Total UI for P1: 0, mck2ui 16
4439 18:05:20.919267 best dqsien dly found for B1: ( 0, 13, 10)
4440 18:05:20.922789 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4441 18:05:20.926105 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4442 18:05:20.926231
4443 18:05:20.928987 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4444 18:05:20.932760 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4445 18:05:20.935857 [Gating] SW calibration Done
4446 18:05:20.935965 ==
4447 18:05:20.938958 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 18:05:20.942793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 18:05:20.945750 ==
4450 18:05:20.945858 RX Vref Scan: 0
4451 18:05:20.945951
4452 18:05:20.948848 RX Vref 0 -> 0, step: 1
4453 18:05:20.948950
4454 18:05:20.952713 RX Delay -230 -> 252, step: 16
4455 18:05:20.955731 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4456 18:05:20.959040 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4457 18:05:20.962597 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4458 18:05:20.968667 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4459 18:05:20.972560 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4460 18:05:20.975646 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4461 18:05:20.978644 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4462 18:05:20.982154 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4463 18:05:20.988862 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4464 18:05:20.992156 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4465 18:05:20.995494 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4466 18:05:20.998795 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4467 18:05:21.005331 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4468 18:05:21.009069 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4469 18:05:21.012182 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4470 18:05:21.015288 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4471 18:05:21.015399 ==
4472 18:05:21.019076 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 18:05:21.025913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 18:05:21.026040 ==
4475 18:05:21.026139 DQS Delay:
4476 18:05:21.028992 DQS0 = 0, DQS1 = 0
4477 18:05:21.029101 DQM Delay:
4478 18:05:21.029197 DQM0 = 47, DQM1 = 45
4479 18:05:21.031852 DQ Delay:
4480 18:05:21.035524 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4481 18:05:21.038821 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4482 18:05:21.042004 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4483 18:05:21.045062 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4484 18:05:21.045172
4485 18:05:21.045267
4486 18:05:21.045359 ==
4487 18:05:21.048276 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 18:05:21.051896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 18:05:21.052010 ==
4490 18:05:21.052108
4491 18:05:21.052201
4492 18:05:21.055569 TX Vref Scan disable
4493 18:05:21.058446 == TX Byte 0 ==
4494 18:05:21.062199 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4495 18:05:21.065395 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4496 18:05:21.068310 == TX Byte 1 ==
4497 18:05:21.071441 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4498 18:05:21.075356 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4499 18:05:21.075466 ==
4500 18:05:21.078373 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 18:05:21.081520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 18:05:21.085217 ==
4503 18:05:21.085328
4504 18:05:21.085423
4505 18:05:21.085514 TX Vref Scan disable
4506 18:05:21.088969 == TX Byte 0 ==
4507 18:05:21.092087 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 18:05:21.098850 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 18:05:21.098968 == TX Byte 1 ==
4510 18:05:21.102884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 18:05:21.109140 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 18:05:21.109260
4513 18:05:21.109357 [DATLAT]
4514 18:05:21.109449 Freq=600, CH1 RK0
4515 18:05:21.109541
4516 18:05:21.111763 DATLAT Default: 0x9
4517 18:05:21.111870 0, 0xFFFF, sum = 0
4518 18:05:21.115351 1, 0xFFFF, sum = 0
4519 18:05:21.115466 2, 0xFFFF, sum = 0
4520 18:05:21.118642 3, 0xFFFF, sum = 0
4521 18:05:21.122393 4, 0xFFFF, sum = 0
4522 18:05:21.122517 5, 0xFFFF, sum = 0
4523 18:05:21.125397 6, 0xFFFF, sum = 0
4524 18:05:21.125515 7, 0xFFFF, sum = 0
4525 18:05:21.128488 8, 0x0, sum = 1
4526 18:05:21.128576 9, 0x0, sum = 2
4527 18:05:21.128649 10, 0x0, sum = 3
4528 18:05:21.132233 11, 0x0, sum = 4
4529 18:05:21.132355 best_step = 9
4530 18:05:21.132423
4531 18:05:21.132484 ==
4532 18:05:21.135350 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 18:05:21.141862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 18:05:21.141989 ==
4535 18:05:21.142085 RX Vref Scan: 1
4536 18:05:21.142185
4537 18:05:21.145466 RX Vref 0 -> 0, step: 1
4538 18:05:21.145582
4539 18:05:21.148482 RX Delay -163 -> 252, step: 8
4540 18:05:21.148588
4541 18:05:21.152136 Set Vref, RX VrefLevel [Byte0]: 54
4542 18:05:21.154906 [Byte1]: 53
4543 18:05:21.155024
4544 18:05:21.158457 Final RX Vref Byte 0 = 54 to rank0
4545 18:05:21.161872 Final RX Vref Byte 1 = 53 to rank0
4546 18:05:21.165500 Final RX Vref Byte 0 = 54 to rank1
4547 18:05:21.168324 Final RX Vref Byte 1 = 53 to rank1==
4548 18:05:21.171407 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 18:05:21.175066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 18:05:21.175184 ==
4551 18:05:21.178128 DQS Delay:
4552 18:05:21.178208 DQS0 = 0, DQS1 = 0
4553 18:05:21.181479 DQM Delay:
4554 18:05:21.181594 DQM0 = 49, DQM1 = 44
4555 18:05:21.181691 DQ Delay:
4556 18:05:21.185109 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4557 18:05:21.188091 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4558 18:05:21.191747 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4559 18:05:21.194619 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4560 18:05:21.194733
4561 18:05:21.194831
4562 18:05:21.205454 [DQSOSCAuto] RK0, (LSB)MR18= 0x4269, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4563 18:05:21.208216 CH1 RK0: MR19=808, MR18=4269
4564 18:05:21.215025 CH1_RK0: MR19=0x808, MR18=0x4269, DQSOSC=390, MR23=63, INC=172, DEC=114
4565 18:05:21.215155
4566 18:05:21.217989 ----->DramcWriteLeveling(PI) begin...
4567 18:05:21.218103 ==
4568 18:05:21.221826 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 18:05:21.224462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 18:05:21.224579 ==
4571 18:05:21.227795 Write leveling (Byte 0): 29 => 29
4572 18:05:21.231486 Write leveling (Byte 1): 31 => 31
4573 18:05:21.234566 DramcWriteLeveling(PI) end<-----
4574 18:05:21.234684
4575 18:05:21.234779 ==
4576 18:05:21.238436 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 18:05:21.241475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 18:05:21.241595 ==
4579 18:05:21.244670 [Gating] SW mode calibration
4580 18:05:21.251411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4581 18:05:21.258094 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4582 18:05:21.261200 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 18:05:21.264279 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4584 18:05:21.271228 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 18:05:21.274886 0 9 12 | B1->B0 | 2525 2e2e | 0 0 | (1 0) (1 0)
4586 18:05:21.277719 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 18:05:21.284151 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 18:05:21.287948 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 18:05:21.291251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 18:05:21.298134 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 18:05:21.301082 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 18:05:21.304164 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 18:05:21.307512 0 10 12 | B1->B0 | 3535 3232 | 0 0 | (0 0) (0 0)
4594 18:05:21.314482 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 18:05:21.317343 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 18:05:21.324291 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 18:05:21.327358 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 18:05:21.330921 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 18:05:21.334374 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 18:05:21.340571 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 18:05:21.344059 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4602 18:05:21.347278 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 18:05:21.354048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 18:05:21.357492 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 18:05:21.360419 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 18:05:21.367185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 18:05:21.370370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 18:05:21.373969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 18:05:21.380830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 18:05:21.383867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 18:05:21.386842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 18:05:21.393569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 18:05:21.397401 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 18:05:21.400415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 18:05:21.407000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 18:05:21.410350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4617 18:05:21.413669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4618 18:05:21.420302 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 18:05:21.423537 Total UI for P1: 0, mck2ui 16
4620 18:05:21.426800 best dqsien dly found for B0: ( 0, 13, 10)
4621 18:05:21.426940 Total UI for P1: 0, mck2ui 16
4622 18:05:21.433341 best dqsien dly found for B1: ( 0, 13, 10)
4623 18:05:21.436921 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4624 18:05:21.440427 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4625 18:05:21.440529
4626 18:05:21.443612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4627 18:05:21.446942 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4628 18:05:21.450418 [Gating] SW calibration Done
4629 18:05:21.450517 ==
4630 18:05:21.453076 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 18:05:21.456660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 18:05:21.456767 ==
4633 18:05:21.460076 RX Vref Scan: 0
4634 18:05:21.460207
4635 18:05:21.460312 RX Vref 0 -> 0, step: 1
4636 18:05:21.460435
4637 18:05:21.463695 RX Delay -230 -> 252, step: 16
4638 18:05:21.470388 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4639 18:05:21.473360 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4640 18:05:21.477067 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4641 18:05:21.480069 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4642 18:05:21.483180 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4643 18:05:21.489835 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4644 18:05:21.493606 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4645 18:05:21.496706 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4646 18:05:21.499731 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4647 18:05:21.506703 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4648 18:05:21.509656 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4649 18:05:21.513429 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4650 18:05:21.516416 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4651 18:05:21.522916 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4652 18:05:21.526869 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4653 18:05:21.529893 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4654 18:05:21.530015 ==
4655 18:05:21.533522 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 18:05:21.536571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 18:05:21.536681 ==
4658 18:05:21.539534 DQS Delay:
4659 18:05:21.539638 DQS0 = 0, DQS1 = 0
4660 18:05:21.543049 DQM Delay:
4661 18:05:21.543156 DQM0 = 51, DQM1 = 49
4662 18:05:21.543247 DQ Delay:
4663 18:05:21.546733 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4664 18:05:21.549960 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4665 18:05:21.553536 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4666 18:05:21.556503 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4667 18:05:21.556610
4668 18:05:21.556702
4669 18:05:21.559761 ==
4670 18:05:21.559866 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 18:05:21.566103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 18:05:21.566225 ==
4673 18:05:21.566321
4674 18:05:21.566410
4675 18:05:21.569795 TX Vref Scan disable
4676 18:05:21.569900 == TX Byte 0 ==
4677 18:05:21.573324 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4678 18:05:21.579543 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4679 18:05:21.579676 == TX Byte 1 ==
4680 18:05:21.582675 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4681 18:05:21.589701 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4682 18:05:21.589837 ==
4683 18:05:21.592676 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 18:05:21.596508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 18:05:21.596627 ==
4686 18:05:21.596725
4687 18:05:21.596816
4688 18:05:21.599707 TX Vref Scan disable
4689 18:05:21.602666 == TX Byte 0 ==
4690 18:05:21.606428 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 18:05:21.609478 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 18:05:21.612488 == TX Byte 1 ==
4693 18:05:21.616278 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4694 18:05:21.619494 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4695 18:05:21.619607
4696 18:05:21.622424 [DATLAT]
4697 18:05:21.622535 Freq=600, CH1 RK1
4698 18:05:21.622630
4699 18:05:21.626060 DATLAT Default: 0x9
4700 18:05:21.626182 0, 0xFFFF, sum = 0
4701 18:05:21.628957 1, 0xFFFF, sum = 0
4702 18:05:21.629068 2, 0xFFFF, sum = 0
4703 18:05:21.632725 3, 0xFFFF, sum = 0
4704 18:05:21.632823 4, 0xFFFF, sum = 0
4705 18:05:21.635853 5, 0xFFFF, sum = 0
4706 18:05:21.635971 6, 0xFFFF, sum = 0
4707 18:05:21.639476 7, 0xFFFF, sum = 0
4708 18:05:21.639560 8, 0x0, sum = 1
4709 18:05:21.642349 9, 0x0, sum = 2
4710 18:05:21.642466 10, 0x0, sum = 3
4711 18:05:21.645492 11, 0x0, sum = 4
4712 18:05:21.645607 best_step = 9
4713 18:05:21.645699
4714 18:05:21.645793 ==
4715 18:05:21.649489 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 18:05:21.652694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 18:05:21.655649 ==
4718 18:05:21.655759 RX Vref Scan: 0
4719 18:05:21.655852
4720 18:05:21.658765 RX Vref 0 -> 0, step: 1
4721 18:05:21.658873
4722 18:05:21.662771 RX Delay -163 -> 252, step: 8
4723 18:05:21.665844 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4724 18:05:21.669260 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4725 18:05:21.675771 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4726 18:05:21.679618 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4727 18:05:21.682586 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4728 18:05:21.685620 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4729 18:05:21.689073 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4730 18:05:21.695678 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4731 18:05:21.699059 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4732 18:05:21.701960 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4733 18:05:21.705658 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4734 18:05:21.708627 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4735 18:05:21.715284 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4736 18:05:21.719140 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4737 18:05:21.722148 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4738 18:05:21.725180 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4739 18:05:21.725300 ==
4740 18:05:21.728832 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 18:05:21.735649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 18:05:21.735777 ==
4743 18:05:21.735875 DQS Delay:
4744 18:05:21.738416 DQS0 = 0, DQS1 = 0
4745 18:05:21.738526 DQM Delay:
4746 18:05:21.738622 DQM0 = 49, DQM1 = 46
4747 18:05:21.741923 DQ Delay:
4748 18:05:21.745407 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4749 18:05:21.749095 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4750 18:05:21.752018 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4751 18:05:21.755885 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4752 18:05:21.755985
4753 18:05:21.756077
4754 18:05:21.762529 [DQSOSCAuto] RK1, (LSB)MR18= 0x651c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4755 18:05:21.765464 CH1 RK1: MR19=808, MR18=651C
4756 18:05:21.772292 CH1_RK1: MR19=0x808, MR18=0x651C, DQSOSC=390, MR23=63, INC=172, DEC=114
4757 18:05:21.775138 [RxdqsGatingPostProcess] freq 600
4758 18:05:21.778621 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4759 18:05:21.782352 Pre-setting of DQS Precalculation
4760 18:05:21.788634 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4761 18:05:21.794895 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4762 18:05:21.801685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4763 18:05:21.801816
4764 18:05:21.801915
4765 18:05:21.804765 [Calibration Summary] 1200 Mbps
4766 18:05:21.804876 CH 0, Rank 0
4767 18:05:21.808319 SW Impedance : PASS
4768 18:05:21.811640 DUTY Scan : NO K
4769 18:05:21.811752 ZQ Calibration : PASS
4770 18:05:21.815118 Jitter Meter : NO K
4771 18:05:21.817997 CBT Training : PASS
4772 18:05:21.818112 Write leveling : PASS
4773 18:05:21.821819 RX DQS gating : PASS
4774 18:05:21.825039 RX DQ/DQS(RDDQC) : PASS
4775 18:05:21.825154 TX DQ/DQS : PASS
4776 18:05:21.827981 RX DATLAT : PASS
4777 18:05:21.832041 RX DQ/DQS(Engine): PASS
4778 18:05:21.832159 TX OE : NO K
4779 18:05:21.834985 All Pass.
4780 18:05:21.835085
4781 18:05:21.835177 CH 0, Rank 1
4782 18:05:21.838044 SW Impedance : PASS
4783 18:05:21.838143 DUTY Scan : NO K
4784 18:05:21.841173 ZQ Calibration : PASS
4785 18:05:21.844724 Jitter Meter : NO K
4786 18:05:21.844820 CBT Training : PASS
4787 18:05:21.848539 Write leveling : PASS
4788 18:05:21.851382 RX DQS gating : PASS
4789 18:05:21.851460 RX DQ/DQS(RDDQC) : PASS
4790 18:05:21.854920 TX DQ/DQS : PASS
4791 18:05:21.855042 RX DATLAT : PASS
4792 18:05:21.857805 RX DQ/DQS(Engine): PASS
4793 18:05:21.861059 TX OE : NO K
4794 18:05:21.861174 All Pass.
4795 18:05:21.861268
4796 18:05:21.861359 CH 1, Rank 0
4797 18:05:21.864909 SW Impedance : PASS
4798 18:05:21.867971 DUTY Scan : NO K
4799 18:05:21.868081 ZQ Calibration : PASS
4800 18:05:21.870991 Jitter Meter : NO K
4801 18:05:21.874799 CBT Training : PASS
4802 18:05:21.874910 Write leveling : PASS
4803 18:05:21.877953 RX DQS gating : PASS
4804 18:05:21.880918 RX DQ/DQS(RDDQC) : PASS
4805 18:05:21.881023 TX DQ/DQS : PASS
4806 18:05:21.884713 RX DATLAT : PASS
4807 18:05:21.887347 RX DQ/DQS(Engine): PASS
4808 18:05:21.887453 TX OE : NO K
4809 18:05:21.890799 All Pass.
4810 18:05:21.890906
4811 18:05:21.891000 CH 1, Rank 1
4812 18:05:21.894325 SW Impedance : PASS
4813 18:05:21.894430 DUTY Scan : NO K
4814 18:05:21.897349 ZQ Calibration : PASS
4815 18:05:21.901222 Jitter Meter : NO K
4816 18:05:21.901327 CBT Training : PASS
4817 18:05:21.904168 Write leveling : PASS
4818 18:05:21.907322 RX DQS gating : PASS
4819 18:05:21.907428 RX DQ/DQS(RDDQC) : PASS
4820 18:05:21.911019 TX DQ/DQS : PASS
4821 18:05:21.914201 RX DATLAT : PASS
4822 18:05:21.914307 RX DQ/DQS(Engine): PASS
4823 18:05:21.917112 TX OE : NO K
4824 18:05:21.917226 All Pass.
4825 18:05:21.917320
4826 18:05:21.920843 DramC Write-DBI off
4827 18:05:21.923863 PER_BANK_REFRESH: Hybrid Mode
4828 18:05:21.923946 TX_TRACKING: ON
4829 18:05:21.933575 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4830 18:05:21.937144 [FAST_K] Save calibration result to emmc
4831 18:05:21.940631 dramc_set_vcore_voltage set vcore to 662500
4832 18:05:21.943857 Read voltage for 933, 3
4833 18:05:21.943971 Vio18 = 0
4834 18:05:21.944078 Vcore = 662500
4835 18:05:21.947440 Vdram = 0
4836 18:05:21.947551 Vddq = 0
4837 18:05:21.947643 Vmddr = 0
4838 18:05:21.953416 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4839 18:05:21.957024 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4840 18:05:21.960732 MEM_TYPE=3, freq_sel=17
4841 18:05:21.963531 sv_algorithm_assistance_LP4_1600
4842 18:05:21.966918 ============ PULL DRAM RESETB DOWN ============
4843 18:05:21.970452 ========== PULL DRAM RESETB DOWN end =========
4844 18:05:21.976940 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4845 18:05:21.980664 ===================================
4846 18:05:21.980771 LPDDR4 DRAM CONFIGURATION
4847 18:05:21.983853 ===================================
4848 18:05:21.987133 EX_ROW_EN[0] = 0x0
4849 18:05:21.990776 EX_ROW_EN[1] = 0x0
4850 18:05:21.990861 LP4Y_EN = 0x0
4851 18:05:21.993602 WORK_FSP = 0x0
4852 18:05:21.993676 WL = 0x3
4853 18:05:21.997363 RL = 0x3
4854 18:05:21.997437 BL = 0x2
4855 18:05:22.000790 RPST = 0x0
4856 18:05:22.000864 RD_PRE = 0x0
4857 18:05:22.003570 WR_PRE = 0x1
4858 18:05:22.003670 WR_PST = 0x0
4859 18:05:22.007219 DBI_WR = 0x0
4860 18:05:22.007319 DBI_RD = 0x0
4861 18:05:22.010116 OTF = 0x1
4862 18:05:22.013456 ===================================
4863 18:05:22.017347 ===================================
4864 18:05:22.017456 ANA top config
4865 18:05:22.020487 ===================================
4866 18:05:22.023606 DLL_ASYNC_EN = 0
4867 18:05:22.026785 ALL_SLAVE_EN = 1
4868 18:05:22.030463 NEW_RANK_MODE = 1
4869 18:05:22.030585 DLL_IDLE_MODE = 1
4870 18:05:22.033453 LP45_APHY_COMB_EN = 1
4871 18:05:22.037260 TX_ODT_DIS = 1
4872 18:05:22.040175 NEW_8X_MODE = 1
4873 18:05:22.043805 ===================================
4874 18:05:22.046764 ===================================
4875 18:05:22.050299 data_rate = 1866
4876 18:05:22.050415 CKR = 1
4877 18:05:22.053809 DQ_P2S_RATIO = 8
4878 18:05:22.056663 ===================================
4879 18:05:22.060369 CA_P2S_RATIO = 8
4880 18:05:22.063483 DQ_CA_OPEN = 0
4881 18:05:22.066469 DQ_SEMI_OPEN = 0
4882 18:05:22.066575 CA_SEMI_OPEN = 0
4883 18:05:22.070252 CA_FULL_RATE = 0
4884 18:05:22.073255 DQ_CKDIV4_EN = 1
4885 18:05:22.076795 CA_CKDIV4_EN = 1
4886 18:05:22.079759 CA_PREDIV_EN = 0
4887 18:05:22.083529 PH8_DLY = 0
4888 18:05:22.083633 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4889 18:05:22.086552 DQ_AAMCK_DIV = 4
4890 18:05:22.089699 CA_AAMCK_DIV = 4
4891 18:05:22.093611 CA_ADMCK_DIV = 4
4892 18:05:22.096705 DQ_TRACK_CA_EN = 0
4893 18:05:22.099602 CA_PICK = 933
4894 18:05:22.103460 CA_MCKIO = 933
4895 18:05:22.103543 MCKIO_SEMI = 0
4896 18:05:22.106398 PLL_FREQ = 3732
4897 18:05:22.110082 DQ_UI_PI_RATIO = 32
4898 18:05:22.112904 CA_UI_PI_RATIO = 0
4899 18:05:22.116414 ===================================
4900 18:05:22.119998 ===================================
4901 18:05:22.122713 memory_type:LPDDR4
4902 18:05:22.122821 GP_NUM : 10
4903 18:05:22.127277 SRAM_EN : 1
4904 18:05:22.129652 MD32_EN : 0
4905 18:05:22.132801 ===================================
4906 18:05:22.132913 [ANA_INIT] >>>>>>>>>>>>>>
4907 18:05:22.136758 <<<<<< [CONFIGURE PHASE]: ANA_TX
4908 18:05:22.139394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4909 18:05:22.143094 ===================================
4910 18:05:22.145998 data_rate = 1866,PCW = 0X8f00
4911 18:05:22.149532 ===================================
4912 18:05:22.152688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4913 18:05:22.159505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4914 18:05:22.163026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4915 18:05:22.169940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4916 18:05:22.172698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4917 18:05:22.176046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4918 18:05:22.176186 [ANA_INIT] flow start
4919 18:05:22.179082 [ANA_INIT] PLL >>>>>>>>
4920 18:05:22.182831 [ANA_INIT] PLL <<<<<<<<
4921 18:05:22.182961 [ANA_INIT] MIDPI >>>>>>>>
4922 18:05:22.185849 [ANA_INIT] MIDPI <<<<<<<<
4923 18:05:22.189571 [ANA_INIT] DLL >>>>>>>>
4924 18:05:22.189705 [ANA_INIT] flow end
4925 18:05:22.196579 ============ LP4 DIFF to SE enter ============
4926 18:05:22.199711 ============ LP4 DIFF to SE exit ============
4927 18:05:22.202639 [ANA_INIT] <<<<<<<<<<<<<
4928 18:05:22.205775 [Flow] Enable top DCM control >>>>>
4929 18:05:22.209694 [Flow] Enable top DCM control <<<<<
4930 18:05:22.209811 Enable DLL master slave shuffle
4931 18:05:22.215800 ==============================================================
4932 18:05:22.219502 Gating Mode config
4933 18:05:22.223028 ==============================================================
4934 18:05:22.225823 Config description:
4935 18:05:22.236197 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4936 18:05:22.242335 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4937 18:05:22.246207 SELPH_MODE 0: By rank 1: By Phase
4938 18:05:22.252374 ==============================================================
4939 18:05:22.256145 GAT_TRACK_EN = 1
4940 18:05:22.259051 RX_GATING_MODE = 2
4941 18:05:22.262334 RX_GATING_TRACK_MODE = 2
4942 18:05:22.266086 SELPH_MODE = 1
4943 18:05:22.266171 PICG_EARLY_EN = 1
4944 18:05:22.269237 VALID_LAT_VALUE = 1
4945 18:05:22.276005 ==============================================================
4946 18:05:22.279515 Enter into Gating configuration >>>>
4947 18:05:22.282370 Exit from Gating configuration <<<<
4948 18:05:22.285643 Enter into DVFS_PRE_config >>>>>
4949 18:05:22.295651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4950 18:05:22.298854 Exit from DVFS_PRE_config <<<<<
4951 18:05:22.302468 Enter into PICG configuration >>>>
4952 18:05:22.305471 Exit from PICG configuration <<<<
4953 18:05:22.309333 [RX_INPUT] configuration >>>>>
4954 18:05:22.312386 [RX_INPUT] configuration <<<<<
4955 18:05:22.315469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4956 18:05:22.322372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4957 18:05:22.329201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 18:05:22.335577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 18:05:22.342451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 18:05:22.345392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 18:05:22.352115 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4962 18:05:22.355964 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4963 18:05:22.358880 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4964 18:05:22.362557 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4965 18:05:22.369272 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4966 18:05:22.372333 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 18:05:22.375331 ===================================
4968 18:05:22.379348 LPDDR4 DRAM CONFIGURATION
4969 18:05:22.382210 ===================================
4970 18:05:22.382304 EX_ROW_EN[0] = 0x0
4971 18:05:22.385502 EX_ROW_EN[1] = 0x0
4972 18:05:22.385602 LP4Y_EN = 0x0
4973 18:05:22.389178 WORK_FSP = 0x0
4974 18:05:22.389275 WL = 0x3
4975 18:05:22.392077 RL = 0x3
4976 18:05:22.392182 BL = 0x2
4977 18:05:22.395569 RPST = 0x0
4978 18:05:22.395675 RD_PRE = 0x0
4979 18:05:22.399083 WR_PRE = 0x1
4980 18:05:22.399191 WR_PST = 0x0
4981 18:05:22.402467 DBI_WR = 0x0
4982 18:05:22.402571 DBI_RD = 0x0
4983 18:05:22.405813 OTF = 0x1
4984 18:05:22.409099 ===================================
4985 18:05:22.412708 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4986 18:05:22.415961 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4987 18:05:22.422374 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 18:05:22.425899 ===================================
4989 18:05:22.426031 LPDDR4 DRAM CONFIGURATION
4990 18:05:22.428904 ===================================
4991 18:05:22.431991 EX_ROW_EN[0] = 0x10
4992 18:05:22.435673 EX_ROW_EN[1] = 0x0
4993 18:05:22.435786 LP4Y_EN = 0x0
4994 18:05:22.438733 WORK_FSP = 0x0
4995 18:05:22.438843 WL = 0x3
4996 18:05:22.442243 RL = 0x3
4997 18:05:22.442323 BL = 0x2
4998 18:05:22.445959 RPST = 0x0
4999 18:05:22.446044 RD_PRE = 0x0
5000 18:05:22.448769 WR_PRE = 0x1
5001 18:05:22.448854 WR_PST = 0x0
5002 18:05:22.451961 DBI_WR = 0x0
5003 18:05:22.452042 DBI_RD = 0x0
5004 18:05:22.455615 OTF = 0x1
5005 18:05:22.459133 ===================================
5006 18:05:22.465499 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5007 18:05:22.468697 nWR fixed to 30
5008 18:05:22.472401 [ModeRegInit_LP4] CH0 RK0
5009 18:05:22.472524 [ModeRegInit_LP4] CH0 RK1
5010 18:05:22.475342 [ModeRegInit_LP4] CH1 RK0
5011 18:05:22.478576 [ModeRegInit_LP4] CH1 RK1
5012 18:05:22.478691 match AC timing 9
5013 18:05:22.485471 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5014 18:05:22.488482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5015 18:05:22.492326 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5016 18:05:22.498946 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5017 18:05:22.502051 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5018 18:05:22.502145 ==
5019 18:05:22.505116 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 18:05:22.508892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5021 18:05:22.508980 ==
5022 18:05:22.515354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5023 18:05:22.522373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5024 18:05:22.525087 [CA 0] Center 37 (7~68) winsize 62
5025 18:05:22.528761 [CA 1] Center 37 (7~68) winsize 62
5026 18:05:22.531672 [CA 2] Center 34 (4~65) winsize 62
5027 18:05:22.535296 [CA 3] Center 34 (3~65) winsize 63
5028 18:05:22.538043 [CA 4] Center 33 (3~64) winsize 62
5029 18:05:22.541656 [CA 5] Center 32 (2~62) winsize 61
5030 18:05:22.541769
5031 18:05:22.545302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5032 18:05:22.545414
5033 18:05:22.548232 [CATrainingPosCal] consider 1 rank data
5034 18:05:22.551849 u2DelayCellTimex100 = 270/100 ps
5035 18:05:22.554637 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5036 18:05:22.558092 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5037 18:05:22.561645 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5038 18:05:22.564623 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5039 18:05:22.568447 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5040 18:05:22.571568 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5041 18:05:22.571694
5042 18:05:22.578447 CA PerBit enable=1, Macro0, CA PI delay=32
5043 18:05:22.578574
5044 18:05:22.581508 [CBTSetCACLKResult] CA Dly = 32
5045 18:05:22.581625 CS Dly: 5 (0~36)
5046 18:05:22.581721 ==
5047 18:05:22.584611 Dram Type= 6, Freq= 0, CH_0, rank 1
5048 18:05:22.588422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 18:05:22.588516 ==
5050 18:05:22.595215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 18:05:22.601338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 18:05:22.604988 [CA 0] Center 37 (7~68) winsize 62
5053 18:05:22.607870 [CA 1] Center 37 (7~68) winsize 62
5054 18:05:22.611627 [CA 2] Center 34 (4~65) winsize 62
5055 18:05:22.614754 [CA 3] Center 34 (3~65) winsize 63
5056 18:05:22.617911 [CA 4] Center 33 (3~63) winsize 61
5057 18:05:22.621564 [CA 5] Center 32 (2~62) winsize 61
5058 18:05:22.621652
5059 18:05:22.624389 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 18:05:22.624495
5061 18:05:22.627819 [CATrainingPosCal] consider 2 rank data
5062 18:05:22.631109 u2DelayCellTimex100 = 270/100 ps
5063 18:05:22.634565 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5064 18:05:22.637672 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5065 18:05:22.640835 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5066 18:05:22.644563 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5067 18:05:22.647610 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5068 18:05:22.654250 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5069 18:05:22.654381
5070 18:05:22.657986 CA PerBit enable=1, Macro0, CA PI delay=32
5071 18:05:22.658080
5072 18:05:22.660729 [CBTSetCACLKResult] CA Dly = 32
5073 18:05:22.660853 CS Dly: 5 (0~37)
5074 18:05:22.660953
5075 18:05:22.664287 ----->DramcWriteLeveling(PI) begin...
5076 18:05:22.664387 ==
5077 18:05:22.667765 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 18:05:22.674536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 18:05:22.674651 ==
5080 18:05:22.677943 Write leveling (Byte 0): 33 => 33
5081 18:05:22.678032 Write leveling (Byte 1): 29 => 29
5082 18:05:22.680816 DramcWriteLeveling(PI) end<-----
5083 18:05:22.680897
5084 18:05:22.680978 ==
5085 18:05:22.684551 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 18:05:22.691332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 18:05:22.691426 ==
5088 18:05:22.694479 [Gating] SW mode calibration
5089 18:05:22.701299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5090 18:05:22.704286 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5091 18:05:22.711219 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5092 18:05:22.714376 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5093 18:05:22.717363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 18:05:22.724494 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 18:05:22.727683 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 18:05:22.730842 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 18:05:22.737617 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5098 18:05:22.740497 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (0 0)
5099 18:05:22.744114 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5100 18:05:22.750591 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 18:05:22.753585 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 18:05:22.757317 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 18:05:22.763938 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 18:05:22.767014 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 18:05:22.770654 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5106 18:05:22.777194 0 15 28 | B1->B0 | 2525 4141 | 0 1 | (0 0) (0 0)
5107 18:05:22.780040 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5108 18:05:22.783571 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 18:05:22.790477 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 18:05:22.793255 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 18:05:22.797112 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 18:05:22.800502 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 18:05:22.807062 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5114 18:05:22.810038 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5115 18:05:22.813880 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 18:05:22.819961 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 18:05:22.823868 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 18:05:22.826995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 18:05:22.833234 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 18:05:22.837217 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 18:05:22.840201 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 18:05:22.847095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 18:05:22.850208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 18:05:22.853950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 18:05:22.859618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 18:05:22.863421 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 18:05:22.866464 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 18:05:22.873415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 18:05:22.876579 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5130 18:05:22.880267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5131 18:05:22.886279 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5132 18:05:22.886372 Total UI for P1: 0, mck2ui 16
5133 18:05:22.893440 best dqsien dly found for B0: ( 1, 2, 26)
5134 18:05:22.896216 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 18:05:22.900121 Total UI for P1: 0, mck2ui 16
5136 18:05:22.903073 best dqsien dly found for B1: ( 1, 3, 0)
5137 18:05:22.906609 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5138 18:05:22.909411 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5139 18:05:22.909498
5140 18:05:22.912764 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5141 18:05:22.916581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5142 18:05:22.920028 [Gating] SW calibration Done
5143 18:05:22.920119 ==
5144 18:05:22.922814 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 18:05:22.926834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 18:05:22.926962 ==
5147 18:05:22.929830 RX Vref Scan: 0
5148 18:05:22.929942
5149 18:05:22.932842 RX Vref 0 -> 0, step: 1
5150 18:05:22.932929
5151 18:05:22.933019 RX Delay -80 -> 252, step: 8
5152 18:05:22.939893 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5153 18:05:22.942924 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5154 18:05:22.946746 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5155 18:05:22.950034 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5156 18:05:22.953046 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5157 18:05:22.959677 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5158 18:05:22.962685 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5159 18:05:22.966243 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5160 18:05:22.969348 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5161 18:05:22.973060 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5162 18:05:22.976287 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5163 18:05:22.982593 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5164 18:05:22.986436 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5165 18:05:22.989494 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5166 18:05:22.992654 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5167 18:05:22.996354 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5168 18:05:22.996442 ==
5169 18:05:22.999411 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 18:05:23.005745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 18:05:23.005865 ==
5172 18:05:23.005935 DQS Delay:
5173 18:05:23.009174 DQS0 = 0, DQS1 = 0
5174 18:05:23.009268 DQM Delay:
5175 18:05:23.009335 DQM0 = 103, DQM1 = 95
5176 18:05:23.012446 DQ Delay:
5177 18:05:23.016401 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5178 18:05:23.019235 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =111
5179 18:05:23.022917 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5180 18:05:23.026338 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5181 18:05:23.026427
5182 18:05:23.026493
5183 18:05:23.026553 ==
5184 18:05:23.029503 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 18:05:23.032666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 18:05:23.032755 ==
5187 18:05:23.032820
5188 18:05:23.032885
5189 18:05:23.036155 TX Vref Scan disable
5190 18:05:23.039082 == TX Byte 0 ==
5191 18:05:23.042724 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5192 18:05:23.045972 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5193 18:05:23.049664 == TX Byte 1 ==
5194 18:05:23.052743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5195 18:05:23.055743 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5196 18:05:23.055834 ==
5197 18:05:23.059649 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 18:05:23.062897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 18:05:23.065833 ==
5200 18:05:23.065918
5201 18:05:23.065985
5202 18:05:23.066048 TX Vref Scan disable
5203 18:05:23.069609 == TX Byte 0 ==
5204 18:05:23.073348 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5205 18:05:23.079857 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5206 18:05:23.079948 == TX Byte 1 ==
5207 18:05:23.083031 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 18:05:23.089997 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 18:05:23.090086
5210 18:05:23.090153 [DATLAT]
5211 18:05:23.090217 Freq=933, CH0 RK0
5212 18:05:23.090277
5213 18:05:23.093080 DATLAT Default: 0xd
5214 18:05:23.093159 0, 0xFFFF, sum = 0
5215 18:05:23.096166 1, 0xFFFF, sum = 0
5216 18:05:23.096248 2, 0xFFFF, sum = 0
5217 18:05:23.099296 3, 0xFFFF, sum = 0
5218 18:05:23.102400 4, 0xFFFF, sum = 0
5219 18:05:23.102477 5, 0xFFFF, sum = 0
5220 18:05:23.106432 6, 0xFFFF, sum = 0
5221 18:05:23.106516 7, 0xFFFF, sum = 0
5222 18:05:23.109452 8, 0xFFFF, sum = 0
5223 18:05:23.109531 9, 0xFFFF, sum = 0
5224 18:05:23.112425 10, 0x0, sum = 1
5225 18:05:23.112506 11, 0x0, sum = 2
5226 18:05:23.115991 12, 0x0, sum = 3
5227 18:05:23.116102 13, 0x0, sum = 4
5228 18:05:23.116204 best_step = 11
5229 18:05:23.118942
5230 18:05:23.119025 ==
5231 18:05:23.122629 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 18:05:23.125570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 18:05:23.125689 ==
5234 18:05:23.125783 RX Vref Scan: 1
5235 18:05:23.125886
5236 18:05:23.129427 RX Vref 0 -> 0, step: 1
5237 18:05:23.129514
5238 18:05:23.132704 RX Delay -45 -> 252, step: 4
5239 18:05:23.132787
5240 18:05:23.135665 Set Vref, RX VrefLevel [Byte0]: 55
5241 18:05:23.139377 [Byte1]: 49
5242 18:05:23.139488
5243 18:05:23.142086 Final RX Vref Byte 0 = 55 to rank0
5244 18:05:23.145399 Final RX Vref Byte 1 = 49 to rank0
5245 18:05:23.148797 Final RX Vref Byte 0 = 55 to rank1
5246 18:05:23.152050 Final RX Vref Byte 1 = 49 to rank1==
5247 18:05:23.155345 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 18:05:23.159299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 18:05:23.162358 ==
5250 18:05:23.162445 DQS Delay:
5251 18:05:23.162534 DQS0 = 0, DQS1 = 0
5252 18:05:23.165589 DQM Delay:
5253 18:05:23.165678 DQM0 = 104, DQM1 = 96
5254 18:05:23.169028 DQ Delay:
5255 18:05:23.172506 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5256 18:05:23.175294 DQ4 =104, DQ5 =94, DQ6 =114, DQ7 =110
5257 18:05:23.178969 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =90
5258 18:05:23.181962 DQ12 =100, DQ13 =100, DQ14 =108, DQ15 =102
5259 18:05:23.182056
5260 18:05:23.182122
5261 18:05:23.188674 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5262 18:05:23.191835 CH0 RK0: MR19=505, MR18=3028
5263 18:05:23.198849 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5264 18:05:23.198977
5265 18:05:23.202048 ----->DramcWriteLeveling(PI) begin...
5266 18:05:23.202154 ==
5267 18:05:23.205144 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 18:05:23.208401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 18:05:23.208482 ==
5270 18:05:23.212227 Write leveling (Byte 0): 31 => 31
5271 18:05:23.215328 Write leveling (Byte 1): 31 => 31
5272 18:05:23.218482 DramcWriteLeveling(PI) end<-----
5273 18:05:23.218597
5274 18:05:23.218692 ==
5275 18:05:23.222271 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 18:05:23.228356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 18:05:23.228477 ==
5278 18:05:23.228576 [Gating] SW mode calibration
5279 18:05:23.238631 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5280 18:05:23.241742 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5281 18:05:23.245601 0 14 0 | B1->B0 | 3333 3231 | 1 1 | (1 1) (1 1)
5282 18:05:23.251685 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 18:05:23.254859 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 18:05:23.258799 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 18:05:23.265364 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 18:05:23.268404 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 18:05:23.271994 0 14 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5288 18:05:23.278612 0 14 28 | B1->B0 | 2929 2828 | 0 0 | (1 0) (0 0)
5289 18:05:23.281976 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5290 18:05:23.285108 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 18:05:23.291680 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 18:05:23.295022 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 18:05:23.298508 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 18:05:23.305029 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 18:05:23.308148 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5296 18:05:23.311943 0 15 28 | B1->B0 | 3b3b 3737 | 0 0 | (0 0) (0 0)
5297 18:05:23.318236 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5298 18:05:23.321301 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 18:05:23.325068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 18:05:23.331496 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 18:05:23.334409 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 18:05:23.338271 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 18:05:23.345089 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 18:05:23.348028 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5305 18:05:23.351495 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 18:05:23.357781 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 18:05:23.360926 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 18:05:23.364572 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 18:05:23.371055 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 18:05:23.374530 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 18:05:23.377473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 18:05:23.384511 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 18:05:23.387436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 18:05:23.391247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 18:05:23.397580 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 18:05:23.400757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 18:05:23.404288 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 18:05:23.410406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 18:05:23.413795 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5320 18:05:23.417233 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5321 18:05:23.420732 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5322 18:05:23.423686 Total UI for P1: 0, mck2ui 16
5323 18:05:23.427555 best dqsien dly found for B1: ( 1, 2, 30)
5324 18:05:23.434367 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 18:05:23.437167 Total UI for P1: 0, mck2ui 16
5326 18:05:23.441067 best dqsien dly found for B0: ( 1, 2, 28)
5327 18:05:23.443787 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5328 18:05:23.447519 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5329 18:05:23.447606
5330 18:05:23.450591 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5331 18:05:23.453538 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5332 18:05:23.457299 [Gating] SW calibration Done
5333 18:05:23.457402 ==
5334 18:05:23.460295 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 18:05:23.463707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 18:05:23.463829 ==
5337 18:05:23.467412 RX Vref Scan: 0
5338 18:05:23.467530
5339 18:05:23.470123 RX Vref 0 -> 0, step: 1
5340 18:05:23.470239
5341 18:05:23.470319 RX Delay -80 -> 252, step: 8
5342 18:05:23.476818 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5343 18:05:23.480468 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5344 18:05:23.483885 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5345 18:05:23.486809 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5346 18:05:23.490647 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5347 18:05:23.493832 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5348 18:05:23.500498 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5349 18:05:23.503360 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5350 18:05:23.506691 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5351 18:05:23.510185 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5352 18:05:23.513677 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5353 18:05:23.516683 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5354 18:05:23.523757 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5355 18:05:23.526573 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5356 18:05:23.530135 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5357 18:05:23.533333 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5358 18:05:23.533447 ==
5359 18:05:23.536875 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 18:05:23.543204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 18:05:23.543346 ==
5362 18:05:23.543447 DQS Delay:
5363 18:05:23.543540 DQS0 = 0, DQS1 = 0
5364 18:05:23.546880 DQM Delay:
5365 18:05:23.546990 DQM0 = 105, DQM1 = 95
5366 18:05:23.550578 DQ Delay:
5367 18:05:23.553598 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5368 18:05:23.556555 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5369 18:05:23.560281 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5370 18:05:23.563390 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5371 18:05:23.563479
5372 18:05:23.563574
5373 18:05:23.563676 ==
5374 18:05:23.567004 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 18:05:23.570223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 18:05:23.570341 ==
5377 18:05:23.570437
5378 18:05:23.570529
5379 18:05:23.573890 TX Vref Scan disable
5380 18:05:23.576616 == TX Byte 0 ==
5381 18:05:23.579989 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5382 18:05:23.583678 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5383 18:05:23.586365 == TX Byte 1 ==
5384 18:05:23.589829 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5385 18:05:23.593540 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5386 18:05:23.593678 ==
5387 18:05:23.596455 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 18:05:23.600244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 18:05:23.603226 ==
5390 18:05:23.603317
5391 18:05:23.603384
5392 18:05:23.603446 TX Vref Scan disable
5393 18:05:23.607010 == TX Byte 0 ==
5394 18:05:23.610066 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5395 18:05:23.613697 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5396 18:05:23.617073 == TX Byte 1 ==
5397 18:05:23.619858 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5398 18:05:23.626716 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5399 18:05:23.626854
5400 18:05:23.626955 [DATLAT]
5401 18:05:23.627049 Freq=933, CH0 RK1
5402 18:05:23.627145
5403 18:05:23.629954 DATLAT Default: 0xb
5404 18:05:23.630068 0, 0xFFFF, sum = 0
5405 18:05:23.633446 1, 0xFFFF, sum = 0
5406 18:05:23.633560 2, 0xFFFF, sum = 0
5407 18:05:23.637020 3, 0xFFFF, sum = 0
5408 18:05:23.640155 4, 0xFFFF, sum = 0
5409 18:05:23.640270 5, 0xFFFF, sum = 0
5410 18:05:23.643532 6, 0xFFFF, sum = 0
5411 18:05:23.643620 7, 0xFFFF, sum = 0
5412 18:05:23.646983 8, 0xFFFF, sum = 0
5413 18:05:23.647098 9, 0xFFFF, sum = 0
5414 18:05:23.650236 10, 0x0, sum = 1
5415 18:05:23.650359 11, 0x0, sum = 2
5416 18:05:23.652798 12, 0x0, sum = 3
5417 18:05:23.652911 13, 0x0, sum = 4
5418 18:05:23.653010 best_step = 11
5419 18:05:23.653104
5420 18:05:23.656734 ==
5421 18:05:23.659727 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 18:05:23.662808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 18:05:23.662912 ==
5424 18:05:23.663008 RX Vref Scan: 0
5425 18:05:23.663100
5426 18:05:23.666680 RX Vref 0 -> 0, step: 1
5427 18:05:23.666789
5428 18:05:23.669934 RX Delay -45 -> 252, step: 4
5429 18:05:23.676618 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5430 18:05:23.679667 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5431 18:05:23.682631 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5432 18:05:23.686297 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5433 18:05:23.689651 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5434 18:05:23.692549 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5435 18:05:23.699460 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5436 18:05:23.702687 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5437 18:05:23.705890 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5438 18:05:23.709603 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5439 18:05:23.713126 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5440 18:05:23.719135 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5441 18:05:23.722834 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5442 18:05:23.725920 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5443 18:05:23.729557 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5444 18:05:23.733148 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5445 18:05:23.733277 ==
5446 18:05:23.736440 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 18:05:23.742817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 18:05:23.742955 ==
5449 18:05:23.743055 DQS Delay:
5450 18:05:23.745942 DQS0 = 0, DQS1 = 0
5451 18:05:23.746058 DQM Delay:
5452 18:05:23.749676 DQM0 = 105, DQM1 = 94
5453 18:05:23.749794 DQ Delay:
5454 18:05:23.752672 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =102
5455 18:05:23.756497 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5456 18:05:23.759849 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90
5457 18:05:23.762983 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5458 18:05:23.763097
5459 18:05:23.763195
5460 18:05:23.772857 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5461 18:05:23.773002 CH0 RK1: MR19=505, MR18=2801
5462 18:05:23.779575 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5463 18:05:23.782745 [RxdqsGatingPostProcess] freq 933
5464 18:05:23.789591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 18:05:23.792556 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 18:05:23.796360 best DQS1 dly(2T, 0.5T) = (0, 11)
5467 18:05:23.799385 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 18:05:23.802671 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5469 18:05:23.802793 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 18:05:23.806112 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 18:05:23.809122 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 18:05:23.812795 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 18:05:23.815805 Pre-setting of DQS Precalculation
5474 18:05:23.822809 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 18:05:23.822936 ==
5476 18:05:23.826158 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 18:05:23.829225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 18:05:23.829341 ==
5479 18:05:23.835797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 18:05:23.839590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5481 18:05:23.843315 [CA 0] Center 36 (6~67) winsize 62
5482 18:05:23.846761 [CA 1] Center 36 (6~67) winsize 62
5483 18:05:23.850334 [CA 2] Center 34 (4~65) winsize 62
5484 18:05:23.853213 [CA 3] Center 34 (3~65) winsize 63
5485 18:05:23.856769 [CA 4] Center 34 (4~64) winsize 61
5486 18:05:23.859936 [CA 5] Center 33 (3~64) winsize 62
5487 18:05:23.860023
5488 18:05:23.863670 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5489 18:05:23.863756
5490 18:05:23.866536 [CATrainingPosCal] consider 1 rank data
5491 18:05:23.870212 u2DelayCellTimex100 = 270/100 ps
5492 18:05:23.873866 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 18:05:23.876663 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 18:05:23.883719 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 18:05:23.886647 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5496 18:05:23.889898 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5497 18:05:23.893614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 18:05:23.893693
5499 18:05:23.896517 CA PerBit enable=1, Macro0, CA PI delay=33
5500 18:05:23.896595
5501 18:05:23.900212 [CBTSetCACLKResult] CA Dly = 33
5502 18:05:23.900313 CS Dly: 7 (0~38)
5503 18:05:23.903400 ==
5504 18:05:23.903486 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 18:05:23.910060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 18:05:23.910152 ==
5507 18:05:23.913049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 18:05:23.919766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5509 18:05:23.923537 [CA 0] Center 37 (7~67) winsize 61
5510 18:05:23.926566 [CA 1] Center 37 (7~68) winsize 62
5511 18:05:23.930251 [CA 2] Center 35 (5~65) winsize 61
5512 18:05:23.933228 [CA 3] Center 34 (4~65) winsize 62
5513 18:05:23.936800 [CA 4] Center 34 (4~65) winsize 62
5514 18:05:23.939556 [CA 5] Center 33 (3~64) winsize 62
5515 18:05:23.939667
5516 18:05:23.942959 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5517 18:05:23.943060
5518 18:05:23.946293 [CATrainingPosCal] consider 2 rank data
5519 18:05:23.949815 u2DelayCellTimex100 = 270/100 ps
5520 18:05:23.952861 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5521 18:05:23.959839 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5522 18:05:23.963432 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5523 18:05:23.966569 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5524 18:05:23.969959 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 18:05:23.973410 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 18:05:23.973522
5527 18:05:23.976879 CA PerBit enable=1, Macro0, CA PI delay=33
5528 18:05:23.976964
5529 18:05:23.979806 [CBTSetCACLKResult] CA Dly = 33
5530 18:05:23.979917 CS Dly: 8 (0~40)
5531 18:05:23.982937
5532 18:05:23.986384 ----->DramcWriteLeveling(PI) begin...
5533 18:05:23.986470 ==
5534 18:05:23.989823 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 18:05:23.993229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 18:05:23.993315 ==
5537 18:05:23.996871 Write leveling (Byte 0): 29 => 29
5538 18:05:23.999723 Write leveling (Byte 1): 28 => 28
5539 18:05:24.003412 DramcWriteLeveling(PI) end<-----
5540 18:05:24.003531
5541 18:05:24.003639 ==
5542 18:05:24.006406 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 18:05:24.010185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 18:05:24.010293 ==
5545 18:05:24.013120 [Gating] SW mode calibration
5546 18:05:24.019909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 18:05:24.026551 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 18:05:24.029481 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 18:05:24.033409 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 18:05:24.039945 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 18:05:24.042908 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 18:05:24.046609 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 18:05:24.053318 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 18:05:24.056350 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5555 18:05:24.059269 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (1 0)
5556 18:05:24.062833 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 18:05:24.069460 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 18:05:24.072703 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 18:05:24.076080 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 18:05:24.083074 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 18:05:24.085842 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 18:05:24.089251 0 15 24 | B1->B0 | 2727 3333 | 1 0 | (0 0) (0 0)
5563 18:05:24.095678 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5564 18:05:24.099210 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 18:05:24.102601 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 18:05:24.109242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 18:05:24.112725 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 18:05:24.115930 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 18:05:24.122390 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 18:05:24.126132 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5571 18:05:24.129270 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 18:05:24.135813 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 18:05:24.138835 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 18:05:24.142417 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 18:05:24.149245 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 18:05:24.152079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 18:05:24.155735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 18:05:24.162309 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 18:05:24.165869 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 18:05:24.168903 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 18:05:24.175394 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 18:05:24.179083 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 18:05:24.182046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 18:05:24.188449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 18:05:24.191865 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 18:05:24.195413 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5587 18:05:24.202277 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 18:05:24.202377 Total UI for P1: 0, mck2ui 16
5589 18:05:24.208397 best dqsien dly found for B0: ( 1, 2, 24)
5590 18:05:24.208513 Total UI for P1: 0, mck2ui 16
5591 18:05:24.215081 best dqsien dly found for B1: ( 1, 2, 24)
5592 18:05:24.218518 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5593 18:05:24.222027 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5594 18:05:24.222139
5595 18:05:24.225609 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5596 18:05:24.228767 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5597 18:05:24.232035 [Gating] SW calibration Done
5598 18:05:24.232155 ==
5599 18:05:24.235090 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 18:05:24.238578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 18:05:24.238688 ==
5602 18:05:24.242203 RX Vref Scan: 0
5603 18:05:24.242316
5604 18:05:24.242420 RX Vref 0 -> 0, step: 1
5605 18:05:24.242525
5606 18:05:24.245193 RX Delay -80 -> 252, step: 8
5607 18:05:24.248462 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5608 18:05:24.254904 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5609 18:05:24.257887 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5610 18:05:24.261744 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5611 18:05:24.264557 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5612 18:05:24.268261 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5613 18:05:24.271868 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5614 18:05:24.277829 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5615 18:05:24.281595 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5616 18:05:24.284407 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5617 18:05:24.288004 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5618 18:05:24.291170 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5619 18:05:24.298046 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5620 18:05:24.301464 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5621 18:05:24.304361 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5622 18:05:24.308071 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5623 18:05:24.308180 ==
5624 18:05:24.311073 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 18:05:24.314418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 18:05:24.318187 ==
5627 18:05:24.318270 DQS Delay:
5628 18:05:24.318337 DQS0 = 0, DQS1 = 0
5629 18:05:24.321164 DQM Delay:
5630 18:05:24.321241 DQM0 = 102, DQM1 = 97
5631 18:05:24.324183 DQ Delay:
5632 18:05:24.327725 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5633 18:05:24.331428 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5634 18:05:24.334360 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5635 18:05:24.338027 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5636 18:05:24.338135
5637 18:05:24.338230
5638 18:05:24.338319 ==
5639 18:05:24.341034 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 18:05:24.344652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 18:05:24.344761 ==
5642 18:05:24.344869
5643 18:05:24.344971
5644 18:05:24.347353 TX Vref Scan disable
5645 18:05:24.350912 == TX Byte 0 ==
5646 18:05:24.354253 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5647 18:05:24.357990 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5648 18:05:24.360843 == TX Byte 1 ==
5649 18:05:24.363959 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5650 18:05:24.367274 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5651 18:05:24.367385 ==
5652 18:05:24.370526 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 18:05:24.373851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 18:05:24.377120 ==
5655 18:05:24.377202
5656 18:05:24.377305
5657 18:05:24.377406 TX Vref Scan disable
5658 18:05:24.380841 == TX Byte 0 ==
5659 18:05:24.384008 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 18:05:24.390500 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 18:05:24.390610 == TX Byte 1 ==
5662 18:05:24.394197 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5663 18:05:24.400754 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5664 18:05:24.400835
5665 18:05:24.400917 [DATLAT]
5666 18:05:24.400983 Freq=933, CH1 RK0
5667 18:05:24.401043
5668 18:05:24.404346 DATLAT Default: 0xd
5669 18:05:24.404441 0, 0xFFFF, sum = 0
5670 18:05:24.407066 1, 0xFFFF, sum = 0
5671 18:05:24.407177 2, 0xFFFF, sum = 0
5672 18:05:24.410668 3, 0xFFFF, sum = 0
5673 18:05:24.413705 4, 0xFFFF, sum = 0
5674 18:05:24.413821 5, 0xFFFF, sum = 0
5675 18:05:24.417485 6, 0xFFFF, sum = 0
5676 18:05:24.417594 7, 0xFFFF, sum = 0
5677 18:05:24.420360 8, 0xFFFF, sum = 0
5678 18:05:24.420471 9, 0xFFFF, sum = 0
5679 18:05:24.423957 10, 0x0, sum = 1
5680 18:05:24.424069 11, 0x0, sum = 2
5681 18:05:24.427436 12, 0x0, sum = 3
5682 18:05:24.427543 13, 0x0, sum = 4
5683 18:05:24.427650 best_step = 11
5684 18:05:24.427751
5685 18:05:24.430868 ==
5686 18:05:24.433724 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 18:05:24.437397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 18:05:24.437505 ==
5689 18:05:24.437599 RX Vref Scan: 1
5690 18:05:24.437695
5691 18:05:24.440451 RX Vref 0 -> 0, step: 1
5692 18:05:24.440552
5693 18:05:24.444008 RX Delay -45 -> 252, step: 4
5694 18:05:24.444112
5695 18:05:24.447231 Set Vref, RX VrefLevel [Byte0]: 54
5696 18:05:24.450724 [Byte1]: 53
5697 18:05:24.450828
5698 18:05:24.453748 Final RX Vref Byte 0 = 54 to rank0
5699 18:05:24.456720 Final RX Vref Byte 1 = 53 to rank0
5700 18:05:24.460369 Final RX Vref Byte 0 = 54 to rank1
5701 18:05:24.463437 Final RX Vref Byte 1 = 53 to rank1==
5702 18:05:24.467016 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 18:05:24.470065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 18:05:24.473552 ==
5705 18:05:24.473651 DQS Delay:
5706 18:05:24.473746 DQS0 = 0, DQS1 = 0
5707 18:05:24.477250 DQM Delay:
5708 18:05:24.477350 DQM0 = 103, DQM1 = 101
5709 18:05:24.479988 DQ Delay:
5710 18:05:24.483450 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5711 18:05:24.487280 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5712 18:05:24.490737 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5713 18:05:24.493720 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5714 18:05:24.493819
5715 18:05:24.493912
5716 18:05:24.500042 [DQSOSCAuto] RK0, (LSB)MR18= 0x142c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5717 18:05:24.503652 CH1 RK0: MR19=505, MR18=142C
5718 18:05:24.510386 CH1_RK0: MR19=0x505, MR18=0x142C, DQSOSC=408, MR23=63, INC=65, DEC=43
5719 18:05:24.510499
5720 18:05:24.513510 ----->DramcWriteLeveling(PI) begin...
5721 18:05:24.513613 ==
5722 18:05:24.516651 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 18:05:24.519819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 18:05:24.519924 ==
5725 18:05:24.523138 Write leveling (Byte 0): 27 => 27
5726 18:05:24.526492 Write leveling (Byte 1): 27 => 27
5727 18:05:24.529996 DramcWriteLeveling(PI) end<-----
5728 18:05:24.530107
5729 18:05:24.530202 ==
5730 18:05:24.533369 Dram Type= 6, Freq= 0, CH_1, rank 1
5731 18:05:24.536314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 18:05:24.540174 ==
5733 18:05:24.540281 [Gating] SW mode calibration
5734 18:05:24.549710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5735 18:05:24.553330 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5736 18:05:24.556256 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 18:05:24.562955 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 18:05:24.566840 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 18:05:24.569879 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 18:05:24.576483 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 18:05:24.580210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 18:05:24.583144 0 14 24 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
5743 18:05:24.589714 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5744 18:05:24.593472 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 18:05:24.596426 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 18:05:24.602936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 18:05:24.606631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 18:05:24.609999 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 18:05:24.616626 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 18:05:24.619569 0 15 24 | B1->B0 | 3a3a 2a2a | 0 0 | (0 0) (0 0)
5751 18:05:24.623390 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5752 18:05:24.629484 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 18:05:24.633350 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 18:05:24.636404 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 18:05:24.642953 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 18:05:24.646901 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 18:05:24.649766 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 18:05:24.653195 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5759 18:05:24.660087 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5760 18:05:24.663171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 18:05:24.666812 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 18:05:24.673536 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 18:05:24.676521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 18:05:24.680136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 18:05:24.686744 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 18:05:24.689792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 18:05:24.693451 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 18:05:24.699967 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 18:05:24.702919 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 18:05:24.706586 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 18:05:24.713388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 18:05:24.716208 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 18:05:24.719674 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 18:05:24.726492 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 18:05:24.729816 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 18:05:24.733286 Total UI for P1: 0, mck2ui 16
5777 18:05:24.736268 best dqsien dly found for B0: ( 1, 2, 26)
5778 18:05:24.739971 Total UI for P1: 0, mck2ui 16
5779 18:05:24.742944 best dqsien dly found for B1: ( 1, 2, 26)
5780 18:05:24.746622 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5781 18:05:24.749571 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5782 18:05:24.749655
5783 18:05:24.753595 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5784 18:05:24.756699 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5785 18:05:24.760130 [Gating] SW calibration Done
5786 18:05:24.760236 ==
5787 18:05:24.763462 Dram Type= 6, Freq= 0, CH_1, rank 1
5788 18:05:24.766523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 18:05:24.766623 ==
5790 18:05:24.769685 RX Vref Scan: 0
5791 18:05:24.769792
5792 18:05:24.769887 RX Vref 0 -> 0, step: 1
5793 18:05:24.772727
5794 18:05:24.772804 RX Delay -80 -> 252, step: 8
5795 18:05:24.779627 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5796 18:05:24.783356 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5797 18:05:24.786641 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5798 18:05:24.789597 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5799 18:05:24.793509 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5800 18:05:24.796434 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5801 18:05:24.802774 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5802 18:05:24.806518 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5803 18:05:24.809551 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5804 18:05:24.813080 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5805 18:05:24.816059 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5806 18:05:24.819699 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5807 18:05:24.826480 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5808 18:05:24.829436 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5809 18:05:24.833038 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5810 18:05:24.835894 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5811 18:05:24.835978 ==
5812 18:05:24.839159 Dram Type= 6, Freq= 0, CH_1, rank 1
5813 18:05:24.845864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 18:05:24.845978 ==
5815 18:05:24.846064 DQS Delay:
5816 18:05:24.846128 DQS0 = 0, DQS1 = 0
5817 18:05:24.849414 DQM Delay:
5818 18:05:24.849526 DQM0 = 102, DQM1 = 99
5819 18:05:24.852348 DQ Delay:
5820 18:05:24.856050 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95
5821 18:05:24.859003 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5822 18:05:24.862516 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5823 18:05:24.866194 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =107
5824 18:05:24.866278
5825 18:05:24.866344
5826 18:05:24.866413 ==
5827 18:05:24.869315 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 18:05:24.872949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 18:05:24.873034 ==
5830 18:05:24.873100
5831 18:05:24.873197
5832 18:05:24.875825 TX Vref Scan disable
5833 18:05:24.879330 == TX Byte 0 ==
5834 18:05:24.882828 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5835 18:05:24.885892 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5836 18:05:24.889024 == TX Byte 1 ==
5837 18:05:24.892283 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5838 18:05:24.895626 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5839 18:05:24.895799 ==
5840 18:05:24.899039 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 18:05:24.902482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 18:05:24.905742 ==
5843 18:05:24.905896
5844 18:05:24.906000
5845 18:05:24.906095 TX Vref Scan disable
5846 18:05:24.909090 == TX Byte 0 ==
5847 18:05:24.912447 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5848 18:05:24.919039 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5849 18:05:24.919215 == TX Byte 1 ==
5850 18:05:24.922686 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5851 18:05:24.929252 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5852 18:05:24.929382
5853 18:05:24.929491 [DATLAT]
5854 18:05:24.929605 Freq=933, CH1 RK1
5855 18:05:24.929672
5856 18:05:24.932501 DATLAT Default: 0xb
5857 18:05:24.932620 0, 0xFFFF, sum = 0
5858 18:05:24.936131 1, 0xFFFF, sum = 0
5859 18:05:24.936286 2, 0xFFFF, sum = 0
5860 18:05:24.939083 3, 0xFFFF, sum = 0
5861 18:05:24.942075 4, 0xFFFF, sum = 0
5862 18:05:24.942210 5, 0xFFFF, sum = 0
5863 18:05:24.945694 6, 0xFFFF, sum = 0
5864 18:05:24.945818 7, 0xFFFF, sum = 0
5865 18:05:24.949129 8, 0xFFFF, sum = 0
5866 18:05:24.949241 9, 0xFFFF, sum = 0
5867 18:05:24.952466 10, 0x0, sum = 1
5868 18:05:24.952576 11, 0x0, sum = 2
5869 18:05:24.955740 12, 0x0, sum = 3
5870 18:05:24.955850 13, 0x0, sum = 4
5871 18:05:24.955945 best_step = 11
5872 18:05:24.956032
5873 18:05:24.959347 ==
5874 18:05:24.962214 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 18:05:24.965790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 18:05:24.965898 ==
5877 18:05:24.965990 RX Vref Scan: 0
5878 18:05:24.966078
5879 18:05:24.969431 RX Vref 0 -> 0, step: 1
5880 18:05:24.969536
5881 18:05:24.972620 RX Delay -45 -> 252, step: 4
5882 18:05:24.975417 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5883 18:05:24.982696 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5884 18:05:24.985484 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5885 18:05:24.989084 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5886 18:05:24.992076 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5887 18:05:24.995731 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5888 18:05:25.002455 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5889 18:05:25.005577 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5890 18:05:25.008970 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5891 18:05:25.012288 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5892 18:05:25.015548 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5893 18:05:25.022005 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5894 18:05:25.025175 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5895 18:05:25.028522 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5896 18:05:25.032048 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5897 18:05:25.035377 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5898 18:05:25.035469 ==
5899 18:05:25.038393 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 18:05:25.045064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 18:05:25.045160 ==
5902 18:05:25.045279 DQS Delay:
5903 18:05:25.048188 DQS0 = 0, DQS1 = 0
5904 18:05:25.048295 DQM Delay:
5905 18:05:25.051763 DQM0 = 104, DQM1 = 101
5906 18:05:25.051863 DQ Delay:
5907 18:05:25.055211 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100
5908 18:05:25.058882 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5909 18:05:25.061496 DQ8 =92, DQ9 =92, DQ10 =102, DQ11 =94
5910 18:05:25.064887 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5911 18:05:25.064973
5912 18:05:25.065039
5913 18:05:25.075061 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5914 18:05:25.075160 CH1 RK1: MR19=504, MR18=2AFD
5915 18:05:25.081789 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5916 18:05:25.084904 [RxdqsGatingPostProcess] freq 933
5917 18:05:25.091531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5918 18:05:25.095178 best DQS0 dly(2T, 0.5T) = (0, 10)
5919 18:05:25.098025 best DQS1 dly(2T, 0.5T) = (0, 10)
5920 18:05:25.101636 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5921 18:05:25.104638 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5922 18:05:25.104729 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 18:05:25.108431 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 18:05:25.111268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 18:05:25.115024 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 18:05:25.118072 Pre-setting of DQS Precalculation
5927 18:05:25.124702 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5928 18:05:25.131686 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5929 18:05:25.138088 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5930 18:05:25.138195
5931 18:05:25.138264
5932 18:05:25.141368 [Calibration Summary] 1866 Mbps
5933 18:05:25.141455 CH 0, Rank 0
5934 18:05:25.145007 SW Impedance : PASS
5935 18:05:25.148414 DUTY Scan : NO K
5936 18:05:25.148494 ZQ Calibration : PASS
5937 18:05:25.151244 Jitter Meter : NO K
5938 18:05:25.154746 CBT Training : PASS
5939 18:05:25.154832 Write leveling : PASS
5940 18:05:25.158343 RX DQS gating : PASS
5941 18:05:25.161706 RX DQ/DQS(RDDQC) : PASS
5942 18:05:25.161792 TX DQ/DQS : PASS
5943 18:05:25.164852 RX DATLAT : PASS
5944 18:05:25.168184 RX DQ/DQS(Engine): PASS
5945 18:05:25.168266 TX OE : NO K
5946 18:05:25.171573 All Pass.
5947 18:05:25.171654
5948 18:05:25.171726 CH 0, Rank 1
5949 18:05:25.174512 SW Impedance : PASS
5950 18:05:25.174588 DUTY Scan : NO K
5951 18:05:25.177863 ZQ Calibration : PASS
5952 18:05:25.181230 Jitter Meter : NO K
5953 18:05:25.181315 CBT Training : PASS
5954 18:05:25.184534 Write leveling : PASS
5955 18:05:25.184655 RX DQS gating : PASS
5956 18:05:25.188301 RX DQ/DQS(RDDQC) : PASS
5957 18:05:25.191203 TX DQ/DQS : PASS
5958 18:05:25.191309 RX DATLAT : PASS
5959 18:05:25.194569 RX DQ/DQS(Engine): PASS
5960 18:05:25.198237 TX OE : NO K
5961 18:05:25.198343 All Pass.
5962 18:05:25.198424
5963 18:05:25.198486 CH 1, Rank 0
5964 18:05:25.201370 SW Impedance : PASS
5965 18:05:25.204352 DUTY Scan : NO K
5966 18:05:25.204430 ZQ Calibration : PASS
5967 18:05:25.208090 Jitter Meter : NO K
5968 18:05:25.211144 CBT Training : PASS
5969 18:05:25.211252 Write leveling : PASS
5970 18:05:25.214789 RX DQS gating : PASS
5971 18:05:25.217719 RX DQ/DQS(RDDQC) : PASS
5972 18:05:25.217823 TX DQ/DQS : PASS
5973 18:05:25.221679 RX DATLAT : PASS
5974 18:05:25.224560 RX DQ/DQS(Engine): PASS
5975 18:05:25.224670 TX OE : NO K
5976 18:05:25.227716 All Pass.
5977 18:05:25.227821
5978 18:05:25.227896 CH 1, Rank 1
5979 18:05:25.231339 SW Impedance : PASS
5980 18:05:25.231455 DUTY Scan : NO K
5981 18:05:25.234480 ZQ Calibration : PASS
5982 18:05:25.237401 Jitter Meter : NO K
5983 18:05:25.237510 CBT Training : PASS
5984 18:05:25.240957 Write leveling : PASS
5985 18:05:25.241069 RX DQS gating : PASS
5986 18:05:25.244516 RX DQ/DQS(RDDQC) : PASS
5987 18:05:25.247958 TX DQ/DQS : PASS
5988 18:05:25.248042 RX DATLAT : PASS
5989 18:05:25.251273 RX DQ/DQS(Engine): PASS
5990 18:05:25.254581 TX OE : NO K
5991 18:05:25.254692 All Pass.
5992 18:05:25.254788
5993 18:05:25.257395 DramC Write-DBI off
5994 18:05:25.257518 PER_BANK_REFRESH: Hybrid Mode
5995 18:05:25.261244 TX_TRACKING: ON
5996 18:05:25.271058 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5997 18:05:25.274078 [FAST_K] Save calibration result to emmc
5998 18:05:25.277576 dramc_set_vcore_voltage set vcore to 650000
5999 18:05:25.277673 Read voltage for 400, 6
6000 18:05:25.280991 Vio18 = 0
6001 18:05:25.281093 Vcore = 650000
6002 18:05:25.281160 Vdram = 0
6003 18:05:25.284349 Vddq = 0
6004 18:05:25.284441 Vmddr = 0
6005 18:05:25.287063 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6006 18:05:25.294302 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6007 18:05:25.297549 MEM_TYPE=3, freq_sel=20
6008 18:05:25.300660 sv_algorithm_assistance_LP4_800
6009 18:05:25.303866 ============ PULL DRAM RESETB DOWN ============
6010 18:05:25.307267 ========== PULL DRAM RESETB DOWN end =========
6011 18:05:25.313991 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6012 18:05:25.316939 ===================================
6013 18:05:25.317026 LPDDR4 DRAM CONFIGURATION
6014 18:05:25.320741 ===================================
6015 18:05:25.323785 EX_ROW_EN[0] = 0x0
6016 18:05:25.323871 EX_ROW_EN[1] = 0x0
6017 18:05:25.327522 LP4Y_EN = 0x0
6018 18:05:25.327607 WORK_FSP = 0x0
6019 18:05:25.330574 WL = 0x2
6020 18:05:25.333862 RL = 0x2
6021 18:05:25.333951 BL = 0x2
6022 18:05:25.337501 RPST = 0x0
6023 18:05:25.337613 RD_PRE = 0x0
6024 18:05:25.340634 WR_PRE = 0x1
6025 18:05:25.340709 WR_PST = 0x0
6026 18:05:25.343615 DBI_WR = 0x0
6027 18:05:25.343704 DBI_RD = 0x0
6028 18:05:25.347377 OTF = 0x1
6029 18:05:25.350276 ===================================
6030 18:05:25.353548 ===================================
6031 18:05:25.353653 ANA top config
6032 18:05:25.357104 ===================================
6033 18:05:25.360168 DLL_ASYNC_EN = 0
6034 18:05:25.363653 ALL_SLAVE_EN = 1
6035 18:05:25.363735 NEW_RANK_MODE = 1
6036 18:05:25.367370 DLL_IDLE_MODE = 1
6037 18:05:25.370451 LP45_APHY_COMB_EN = 1
6038 18:05:25.373493 TX_ODT_DIS = 1
6039 18:05:25.377131 NEW_8X_MODE = 1
6040 18:05:25.377218 ===================================
6041 18:05:25.380023 ===================================
6042 18:05:25.383905 data_rate = 800
6043 18:05:25.386655 CKR = 1
6044 18:05:25.390214 DQ_P2S_RATIO = 4
6045 18:05:25.394125 ===================================
6046 18:05:25.397106 CA_P2S_RATIO = 4
6047 18:05:25.400069 DQ_CA_OPEN = 0
6048 18:05:25.403621 DQ_SEMI_OPEN = 1
6049 18:05:25.403736 CA_SEMI_OPEN = 1
6050 18:05:25.406515 CA_FULL_RATE = 0
6051 18:05:25.409917 DQ_CKDIV4_EN = 0
6052 18:05:25.413221 CA_CKDIV4_EN = 1
6053 18:05:25.416612 CA_PREDIV_EN = 0
6054 18:05:25.420285 PH8_DLY = 0
6055 18:05:25.420403 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6056 18:05:25.423409 DQ_AAMCK_DIV = 0
6057 18:05:25.426546 CA_AAMCK_DIV = 0
6058 18:05:25.430039 CA_ADMCK_DIV = 4
6059 18:05:25.433761 DQ_TRACK_CA_EN = 0
6060 18:05:25.436863 CA_PICK = 800
6061 18:05:25.436937 CA_MCKIO = 400
6062 18:05:25.440643 MCKIO_SEMI = 400
6063 18:05:25.443641 PLL_FREQ = 3016
6064 18:05:25.446819 DQ_UI_PI_RATIO = 32
6065 18:05:25.450344 CA_UI_PI_RATIO = 32
6066 18:05:25.453391 ===================================
6067 18:05:25.457280 ===================================
6068 18:05:25.460363 memory_type:LPDDR4
6069 18:05:25.460447 GP_NUM : 10
6070 18:05:25.463613 SRAM_EN : 1
6071 18:05:25.463710 MD32_EN : 0
6072 18:05:25.467285 ===================================
6073 18:05:25.470339 [ANA_INIT] >>>>>>>>>>>>>>
6074 18:05:25.473313 <<<<<< [CONFIGURE PHASE]: ANA_TX
6075 18:05:25.477095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6076 18:05:25.479815 ===================================
6077 18:05:25.483047 data_rate = 800,PCW = 0X7400
6078 18:05:25.486333 ===================================
6079 18:05:25.489711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6080 18:05:25.496787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 18:05:25.506568 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 18:05:25.509576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6083 18:05:25.513495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6084 18:05:25.516442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6085 18:05:25.519438 [ANA_INIT] flow start
6086 18:05:25.522992 [ANA_INIT] PLL >>>>>>>>
6087 18:05:25.523096 [ANA_INIT] PLL <<<<<<<<
6088 18:05:25.525882 [ANA_INIT] MIDPI >>>>>>>>
6089 18:05:25.529615 [ANA_INIT] MIDPI <<<<<<<<
6090 18:05:25.533108 [ANA_INIT] DLL >>>>>>>>
6091 18:05:25.533194 [ANA_INIT] flow end
6092 18:05:25.535986 ============ LP4 DIFF to SE enter ============
6093 18:05:25.542769 ============ LP4 DIFF to SE exit ============
6094 18:05:25.542863 [ANA_INIT] <<<<<<<<<<<<<
6095 18:05:25.546026 [Flow] Enable top DCM control >>>>>
6096 18:05:25.549762 [Flow] Enable top DCM control <<<<<
6097 18:05:25.552833 Enable DLL master slave shuffle
6098 18:05:25.559808 ==============================================================
6099 18:05:25.559891 Gating Mode config
6100 18:05:25.566389 ==============================================================
6101 18:05:25.569345 Config description:
6102 18:05:25.579242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6103 18:05:25.586070 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6104 18:05:25.588877 SELPH_MODE 0: By rank 1: By Phase
6105 18:05:25.596139 ==============================================================
6106 18:05:25.598931 GAT_TRACK_EN = 0
6107 18:05:25.602479 RX_GATING_MODE = 2
6108 18:05:25.602579 RX_GATING_TRACK_MODE = 2
6109 18:05:25.605844 SELPH_MODE = 1
6110 18:05:25.609471 PICG_EARLY_EN = 1
6111 18:05:25.612229 VALID_LAT_VALUE = 1
6112 18:05:25.619070 ==============================================================
6113 18:05:25.621845 Enter into Gating configuration >>>>
6114 18:05:25.625431 Exit from Gating configuration <<<<
6115 18:05:25.628950 Enter into DVFS_PRE_config >>>>>
6116 18:05:25.638809 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6117 18:05:25.641892 Exit from DVFS_PRE_config <<<<<
6118 18:05:25.645546 Enter into PICG configuration >>>>
6119 18:05:25.649077 Exit from PICG configuration <<<<
6120 18:05:25.651750 [RX_INPUT] configuration >>>>>
6121 18:05:25.655097 [RX_INPUT] configuration <<<<<
6122 18:05:25.658967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6123 18:05:25.665738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6124 18:05:25.671824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6125 18:05:25.678584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6126 18:05:25.681689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 18:05:25.688412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 18:05:25.691916 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6129 18:05:25.698675 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6130 18:05:25.701724 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6131 18:05:25.705317 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6132 18:05:25.708217 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6133 18:05:25.715103 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 18:05:25.718696 ===================================
6135 18:05:25.718783 LPDDR4 DRAM CONFIGURATION
6136 18:05:25.721579 ===================================
6137 18:05:25.725122 EX_ROW_EN[0] = 0x0
6138 18:05:25.728539 EX_ROW_EN[1] = 0x0
6139 18:05:25.728625 LP4Y_EN = 0x0
6140 18:05:25.732299 WORK_FSP = 0x0
6141 18:05:25.732405 WL = 0x2
6142 18:05:25.735076 RL = 0x2
6143 18:05:25.735162 BL = 0x2
6144 18:05:25.738210 RPST = 0x0
6145 18:05:25.738295 RD_PRE = 0x0
6146 18:05:25.741594 WR_PRE = 0x1
6147 18:05:25.741679 WR_PST = 0x0
6148 18:05:25.745338 DBI_WR = 0x0
6149 18:05:25.745424 DBI_RD = 0x0
6150 18:05:25.748249 OTF = 0x1
6151 18:05:25.752062 ===================================
6152 18:05:25.755116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6153 18:05:25.758072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6154 18:05:25.765484 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 18:05:25.768211 ===================================
6156 18:05:25.768289 LPDDR4 DRAM CONFIGURATION
6157 18:05:25.771706 ===================================
6158 18:05:25.775113 EX_ROW_EN[0] = 0x10
6159 18:05:25.778327 EX_ROW_EN[1] = 0x0
6160 18:05:25.778411 LP4Y_EN = 0x0
6161 18:05:25.781324 WORK_FSP = 0x0
6162 18:05:25.781412 WL = 0x2
6163 18:05:25.784747 RL = 0x2
6164 18:05:25.784847 BL = 0x2
6165 18:05:25.787834 RPST = 0x0
6166 18:05:25.787914 RD_PRE = 0x0
6167 18:05:25.791775 WR_PRE = 0x1
6168 18:05:25.791852 WR_PST = 0x0
6169 18:05:25.794696 DBI_WR = 0x0
6170 18:05:25.794774 DBI_RD = 0x0
6171 18:05:25.798234 OTF = 0x1
6172 18:05:25.801391 ===================================
6173 18:05:25.808194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6174 18:05:25.811034 nWR fixed to 30
6175 18:05:25.811119 [ModeRegInit_LP4] CH0 RK0
6176 18:05:25.814711 [ModeRegInit_LP4] CH0 RK1
6177 18:05:25.818511 [ModeRegInit_LP4] CH1 RK0
6178 18:05:25.821398 [ModeRegInit_LP4] CH1 RK1
6179 18:05:25.821482 match AC timing 19
6180 18:05:25.828249 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6181 18:05:25.831341 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6182 18:05:25.834397 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6183 18:05:25.841268 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6184 18:05:25.844199 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6185 18:05:25.844308 ==
6186 18:05:25.847697 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 18:05:25.851175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6188 18:05:25.851259 ==
6189 18:05:25.857980 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6190 18:05:25.864771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6191 18:05:25.867491 [CA 0] Center 36 (8~64) winsize 57
6192 18:05:25.870713 [CA 1] Center 36 (8~64) winsize 57
6193 18:05:25.870825 [CA 2] Center 36 (8~64) winsize 57
6194 18:05:25.874202 [CA 3] Center 36 (8~64) winsize 57
6195 18:05:25.878001 [CA 4] Center 36 (8~64) winsize 57
6196 18:05:25.881039 [CA 5] Center 36 (8~64) winsize 57
6197 18:05:25.881149
6198 18:05:25.884465 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6199 18:05:25.884571
6200 18:05:25.890800 [CATrainingPosCal] consider 1 rank data
6201 18:05:25.890905 u2DelayCellTimex100 = 270/100 ps
6202 18:05:25.894211 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 18:05:25.900611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 18:05:25.904438 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 18:05:25.907522 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 18:05:25.910612 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 18:05:25.914415 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 18:05:25.914502
6209 18:05:25.917383 CA PerBit enable=1, Macro0, CA PI delay=36
6210 18:05:25.917494
6211 18:05:25.920974 [CBTSetCACLKResult] CA Dly = 36
6212 18:05:25.924008 CS Dly: 1 (0~32)
6213 18:05:25.924115 ==
6214 18:05:25.927069 Dram Type= 6, Freq= 0, CH_0, rank 1
6215 18:05:25.930888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 18:05:25.931002 ==
6217 18:05:25.937734 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 18:05:25.940740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 18:05:25.943869 [CA 0] Center 36 (8~64) winsize 57
6220 18:05:25.947591 [CA 1] Center 36 (8~64) winsize 57
6221 18:05:25.950751 [CA 2] Center 36 (8~64) winsize 57
6222 18:05:25.954443 [CA 3] Center 36 (8~64) winsize 57
6223 18:05:25.957389 [CA 4] Center 36 (8~64) winsize 57
6224 18:05:25.960379 [CA 5] Center 36 (8~64) winsize 57
6225 18:05:25.960470
6226 18:05:25.964058 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 18:05:25.964142
6228 18:05:25.967087 [CATrainingPosCal] consider 2 rank data
6229 18:05:25.970721 u2DelayCellTimex100 = 270/100 ps
6230 18:05:25.973505 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 18:05:25.976888 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 18:05:25.980166 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 18:05:25.986783 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 18:05:25.990232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 18:05:25.993541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 18:05:25.993647
6237 18:05:25.997091 CA PerBit enable=1, Macro0, CA PI delay=36
6238 18:05:25.997198
6239 18:05:26.000266 [CBTSetCACLKResult] CA Dly = 36
6240 18:05:26.000395 CS Dly: 1 (0~32)
6241 18:05:26.000491
6242 18:05:26.003735 ----->DramcWriteLeveling(PI) begin...
6243 18:05:26.006502 ==
6244 18:05:26.006585 Dram Type= 6, Freq= 0, CH_0, rank 0
6245 18:05:26.013467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 18:05:26.013574 ==
6247 18:05:26.016953 Write leveling (Byte 0): 40 => 8
6248 18:05:26.020388 Write leveling (Byte 1): 40 => 8
6249 18:05:26.023822 DramcWriteLeveling(PI) end<-----
6250 18:05:26.023920
6251 18:05:26.023993 ==
6252 18:05:26.026760 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 18:05:26.030095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 18:05:26.030177 ==
6255 18:05:26.033373 [Gating] SW mode calibration
6256 18:05:26.040089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6257 18:05:26.042982 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6258 18:05:26.049806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 18:05:26.052945 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 18:05:26.056798 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 18:05:26.063333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 18:05:26.066448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 18:05:26.070072 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 18:05:26.076195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 18:05:26.079839 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 18:05:26.082949 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 18:05:26.086733 Total UI for P1: 0, mck2ui 16
6268 18:05:26.089498 best dqsien dly found for B0: ( 0, 14, 24)
6269 18:05:26.093116 Total UI for P1: 0, mck2ui 16
6270 18:05:26.096364 best dqsien dly found for B1: ( 0, 14, 24)
6271 18:05:26.100044 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6272 18:05:26.103202 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6273 18:05:26.103288
6274 18:05:26.109601 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 18:05:26.112989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 18:05:26.116302 [Gating] SW calibration Done
6277 18:05:26.116405 ==
6278 18:05:26.119633 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 18:05:26.122864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 18:05:26.122948 ==
6281 18:05:26.123015 RX Vref Scan: 0
6282 18:05:26.123077
6283 18:05:26.126399 RX Vref 0 -> 0, step: 1
6284 18:05:26.126483
6285 18:05:26.129359 RX Delay -410 -> 252, step: 16
6286 18:05:26.132808 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6287 18:05:26.139227 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6288 18:05:26.142675 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6289 18:05:26.145994 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6290 18:05:26.149336 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6291 18:05:26.155857 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6292 18:05:26.159047 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6293 18:05:26.163006 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6294 18:05:26.165990 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6295 18:05:26.172794 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6296 18:05:26.175676 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6297 18:05:26.178798 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6298 18:05:26.182679 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6299 18:05:26.188639 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6300 18:05:26.192433 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6301 18:05:26.196030 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6302 18:05:26.196141 ==
6303 18:05:26.198834 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 18:05:26.202384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 18:05:26.205450 ==
6306 18:05:26.205536 DQS Delay:
6307 18:05:26.205613 DQS0 = 27, DQS1 = 35
6308 18:05:26.209541 DQM Delay:
6309 18:05:26.209620 DQM0 = 11, DQM1 = 11
6310 18:05:26.212713 DQ Delay:
6311 18:05:26.212795 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6312 18:05:26.215728 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6313 18:05:26.218768 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6314 18:05:26.222303 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6315 18:05:26.222388
6316 18:05:26.222453
6317 18:05:26.225681 ==
6318 18:05:26.225764 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 18:05:26.231895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 18:05:26.232005 ==
6321 18:05:26.232100
6322 18:05:26.232189
6323 18:05:26.235475 TX Vref Scan disable
6324 18:05:26.235583 == TX Byte 0 ==
6325 18:05:26.239130 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6326 18:05:26.245205 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6327 18:05:26.245314 == TX Byte 1 ==
6328 18:05:26.248738 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6329 18:05:26.255129 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6330 18:05:26.255235 ==
6331 18:05:26.258503 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 18:05:26.261854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 18:05:26.261941 ==
6334 18:05:26.262022
6335 18:05:26.262086
6336 18:05:26.264983 TX Vref Scan disable
6337 18:05:26.265077 == TX Byte 0 ==
6338 18:05:26.268500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 18:05:26.275424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 18:05:26.275572 == TX Byte 1 ==
6341 18:05:26.278465 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 18:05:26.285692 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 18:05:26.285817
6344 18:05:26.285900 [DATLAT]
6345 18:05:26.285962 Freq=400, CH0 RK0
6346 18:05:26.286028
6347 18:05:26.288925 DATLAT Default: 0xf
6348 18:05:26.289016 0, 0xFFFF, sum = 0
6349 18:05:26.291887 1, 0xFFFF, sum = 0
6350 18:05:26.295472 2, 0xFFFF, sum = 0
6351 18:05:26.295566 3, 0xFFFF, sum = 0
6352 18:05:26.298595 4, 0xFFFF, sum = 0
6353 18:05:26.298678 5, 0xFFFF, sum = 0
6354 18:05:26.301558 6, 0xFFFF, sum = 0
6355 18:05:26.301639 7, 0xFFFF, sum = 0
6356 18:05:26.305018 8, 0xFFFF, sum = 0
6357 18:05:26.305102 9, 0xFFFF, sum = 0
6358 18:05:26.308583 10, 0xFFFF, sum = 0
6359 18:05:26.308669 11, 0xFFFF, sum = 0
6360 18:05:26.312200 12, 0xFFFF, sum = 0
6361 18:05:26.312279 13, 0x0, sum = 1
6362 18:05:26.315178 14, 0x0, sum = 2
6363 18:05:26.315263 15, 0x0, sum = 3
6364 18:05:26.318839 16, 0x0, sum = 4
6365 18:05:26.318924 best_step = 14
6366 18:05:26.318994
6367 18:05:26.319056 ==
6368 18:05:26.321700 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 18:05:26.325690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 18:05:26.328502 ==
6371 18:05:26.328583 RX Vref Scan: 1
6372 18:05:26.328662
6373 18:05:26.331483 RX Vref 0 -> 0, step: 1
6374 18:05:26.331559
6375 18:05:26.335025 RX Delay -311 -> 252, step: 8
6376 18:05:26.335112
6377 18:05:26.338799 Set Vref, RX VrefLevel [Byte0]: 55
6378 18:05:26.338929 [Byte1]: 49
6379 18:05:26.344019
6380 18:05:26.344126 Final RX Vref Byte 0 = 55 to rank0
6381 18:05:26.347062 Final RX Vref Byte 1 = 49 to rank0
6382 18:05:26.350666 Final RX Vref Byte 0 = 55 to rank1
6383 18:05:26.354179 Final RX Vref Byte 1 = 49 to rank1==
6384 18:05:26.356961 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 18:05:26.364310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 18:05:26.364448 ==
6387 18:05:26.364539 DQS Delay:
6388 18:05:26.367225 DQS0 = 28, DQS1 = 36
6389 18:05:26.367336 DQM Delay:
6390 18:05:26.367440 DQM0 = 11, DQM1 = 12
6391 18:05:26.370315 DQ Delay:
6392 18:05:26.373682 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6393 18:05:26.373766 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6394 18:05:26.376962 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6395 18:05:26.380238 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6396 18:05:26.380367
6397 18:05:26.383490
6398 18:05:26.390854 [DQSOSCAuto] RK0, (LSB)MR18= 0xc7b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6399 18:05:26.393653 CH0 RK0: MR19=C0C, MR18=C7B5
6400 18:05:26.400457 CH0_RK0: MR19=0xC0C, MR18=0xC7B5, DQSOSC=385, MR23=63, INC=398, DEC=265
6401 18:05:26.400573 ==
6402 18:05:26.403477 Dram Type= 6, Freq= 0, CH_0, rank 1
6403 18:05:26.407251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 18:05:26.407344 ==
6405 18:05:26.409959 [Gating] SW mode calibration
6406 18:05:26.417191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6407 18:05:26.423619 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6408 18:05:26.426744 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 18:05:26.430472 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 18:05:26.437111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 18:05:26.439994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 18:05:26.443694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 18:05:26.450437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 18:05:26.453568 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 18:05:26.456606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 18:05:26.463264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 18:05:26.463382 Total UI for P1: 0, mck2ui 16
6418 18:05:26.466849 best dqsien dly found for B0: ( 0, 14, 24)
6419 18:05:26.469691 Total UI for P1: 0, mck2ui 16
6420 18:05:26.473275 best dqsien dly found for B1: ( 0, 14, 24)
6421 18:05:26.476640 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6422 18:05:26.483307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6423 18:05:26.483437
6424 18:05:26.486871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 18:05:26.490135 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 18:05:26.492923 [Gating] SW calibration Done
6427 18:05:26.493013 ==
6428 18:05:26.496333 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 18:05:26.499543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 18:05:26.499624 ==
6431 18:05:26.503100 RX Vref Scan: 0
6432 18:05:26.503212
6433 18:05:26.503307 RX Vref 0 -> 0, step: 1
6434 18:05:26.503397
6435 18:05:26.506451 RX Delay -410 -> 252, step: 16
6436 18:05:26.509967 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6437 18:05:26.516520 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6438 18:05:26.519984 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6439 18:05:26.523042 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6440 18:05:26.526503 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6441 18:05:26.533045 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6442 18:05:26.536188 iDelay=230, Bit 6, Center -11 (-234 ~ 213) 448
6443 18:05:26.539766 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6444 18:05:26.542753 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6445 18:05:26.549506 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6446 18:05:26.553472 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6447 18:05:26.556307 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6448 18:05:26.559988 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6449 18:05:26.565965 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6450 18:05:26.569855 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6451 18:05:26.572674 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6452 18:05:26.572784 ==
6453 18:05:26.576510 Dram Type= 6, Freq= 0, CH_0, rank 1
6454 18:05:26.582998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 18:05:26.583118 ==
6456 18:05:26.583234 DQS Delay:
6457 18:05:26.585872 DQS0 = 27, DQS1 = 35
6458 18:05:26.585964 DQM Delay:
6459 18:05:26.586054 DQM0 = 11, DQM1 = 12
6460 18:05:26.589446 DQ Delay:
6461 18:05:26.593239 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6462 18:05:26.593364 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6463 18:05:26.596137 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6464 18:05:26.599332 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6465 18:05:26.599456
6466 18:05:26.602826
6467 18:05:26.602930 ==
6468 18:05:26.606087 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 18:05:26.609668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 18:05:26.609804 ==
6471 18:05:26.609905
6472 18:05:26.610008
6473 18:05:26.612933 TX Vref Scan disable
6474 18:05:26.613046 == TX Byte 0 ==
6475 18:05:26.616267 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6476 18:05:26.622140 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6477 18:05:26.622239 == TX Byte 1 ==
6478 18:05:26.625999 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6479 18:05:26.632678 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6480 18:05:26.632769 ==
6481 18:05:26.635569 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 18:05:26.638885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 18:05:26.638974 ==
6484 18:05:26.639041
6485 18:05:26.639103
6486 18:05:26.642540 TX Vref Scan disable
6487 18:05:26.642631 == TX Byte 0 ==
6488 18:05:26.649171 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 18:05:26.652526 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 18:05:26.652627 == TX Byte 1 ==
6491 18:05:26.658739 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6492 18:05:26.661854 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6493 18:05:26.661973
6494 18:05:26.662042 [DATLAT]
6495 18:05:26.665646 Freq=400, CH0 RK1
6496 18:05:26.665729
6497 18:05:26.665795 DATLAT Default: 0xe
6498 18:05:26.668685 0, 0xFFFF, sum = 0
6499 18:05:26.668812 1, 0xFFFF, sum = 0
6500 18:05:26.671638 2, 0xFFFF, sum = 0
6501 18:05:26.671725 3, 0xFFFF, sum = 0
6502 18:05:26.675290 4, 0xFFFF, sum = 0
6503 18:05:26.675405 5, 0xFFFF, sum = 0
6504 18:05:26.678325 6, 0xFFFF, sum = 0
6505 18:05:26.678415 7, 0xFFFF, sum = 0
6506 18:05:26.682059 8, 0xFFFF, sum = 0
6507 18:05:26.682163 9, 0xFFFF, sum = 0
6508 18:05:26.685058 10, 0xFFFF, sum = 0
6509 18:05:26.685152 11, 0xFFFF, sum = 0
6510 18:05:26.688166 12, 0xFFFF, sum = 0
6511 18:05:26.691852 13, 0x0, sum = 1
6512 18:05:26.691969 14, 0x0, sum = 2
6513 18:05:26.692094 15, 0x0, sum = 3
6514 18:05:26.694961 16, 0x0, sum = 4
6515 18:05:26.695078 best_step = 14
6516 18:05:26.695171
6517 18:05:26.698540 ==
6518 18:05:26.701080 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 18:05:26.704927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 18:05:26.705043 ==
6521 18:05:26.705150 RX Vref Scan: 0
6522 18:05:26.705247
6523 18:05:26.707955 RX Vref 0 -> 0, step: 1
6524 18:05:26.708062
6525 18:05:26.711047 RX Delay -311 -> 252, step: 8
6526 18:05:26.718406 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6527 18:05:26.721575 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6528 18:05:26.725002 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6529 18:05:26.731789 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6530 18:05:26.735219 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6531 18:05:26.738193 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6532 18:05:26.740977 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6533 18:05:26.744487 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6534 18:05:26.751261 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6535 18:05:26.754394 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6536 18:05:26.757424 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6537 18:05:26.764723 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6538 18:05:26.767558 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6539 18:05:26.770997 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6540 18:05:26.774255 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6541 18:05:26.781262 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6542 18:05:26.781380 ==
6543 18:05:26.784105 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 18:05:26.787441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 18:05:26.787549 ==
6546 18:05:26.787677 DQS Delay:
6547 18:05:26.791169 DQS0 = 24, DQS1 = 32
6548 18:05:26.791285 DQM Delay:
6549 18:05:26.794132 DQM0 = 7, DQM1 = 9
6550 18:05:26.794217 DQ Delay:
6551 18:05:26.798009 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6552 18:05:26.800942 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6553 18:05:26.803854 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6554 18:05:26.807469 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6555 18:05:26.807555
6556 18:05:26.807634
6557 18:05:26.814517 [DQSOSCAuto] RK1, (LSB)MR18= 0xb656, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6558 18:05:26.817507 CH0 RK1: MR19=C0C, MR18=B656
6559 18:05:26.824049 CH0_RK1: MR19=0xC0C, MR18=0xB656, DQSOSC=387, MR23=63, INC=394, DEC=262
6560 18:05:26.827826 [RxdqsGatingPostProcess] freq 400
6561 18:05:26.833722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6562 18:05:26.833839 best DQS0 dly(2T, 0.5T) = (0, 10)
6563 18:05:26.837631 best DQS1 dly(2T, 0.5T) = (0, 10)
6564 18:05:26.840594 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6565 18:05:26.844381 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6566 18:05:26.847332 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 18:05:26.850330 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 18:05:26.854009 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 18:05:26.857612 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 18:05:26.860448 Pre-setting of DQS Precalculation
6571 18:05:26.867124 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6572 18:05:26.867212 ==
6573 18:05:26.870760 Dram Type= 6, Freq= 0, CH_1, rank 0
6574 18:05:26.873706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 18:05:26.873790 ==
6576 18:05:26.880445 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6577 18:05:26.883541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6578 18:05:26.886979 [CA 0] Center 36 (8~64) winsize 57
6579 18:05:26.890057 [CA 1] Center 36 (8~64) winsize 57
6580 18:05:26.895833 [CA 2] Center 36 (8~64) winsize 57
6581 18:05:26.896791 [CA 3] Center 36 (8~64) winsize 57
6582 18:05:26.900301 [CA 4] Center 36 (8~64) winsize 57
6583 18:05:26.903253 [CA 5] Center 36 (8~64) winsize 57
6584 18:05:26.903365
6585 18:05:26.906769 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6586 18:05:26.906891
6587 18:05:26.910199 [CATrainingPosCal] consider 1 rank data
6588 18:05:26.913293 u2DelayCellTimex100 = 270/100 ps
6589 18:05:26.916967 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 18:05:26.920531 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 18:05:26.923225 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 18:05:26.929998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 18:05:26.933567 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 18:05:26.936506 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 18:05:26.936622
6596 18:05:26.940302 CA PerBit enable=1, Macro0, CA PI delay=36
6597 18:05:26.940412
6598 18:05:26.943279 [CBTSetCACLKResult] CA Dly = 36
6599 18:05:26.943355 CS Dly: 1 (0~32)
6600 18:05:26.943423 ==
6601 18:05:26.946341 Dram Type= 6, Freq= 0, CH_1, rank 1
6602 18:05:26.953071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 18:05:26.953159 ==
6604 18:05:26.956899 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 18:05:26.963652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6606 18:05:26.966574 [CA 0] Center 36 (8~64) winsize 57
6607 18:05:26.970275 [CA 1] Center 36 (8~64) winsize 57
6608 18:05:26.973120 [CA 2] Center 36 (8~64) winsize 57
6609 18:05:26.976495 [CA 3] Center 36 (8~64) winsize 57
6610 18:05:26.980050 [CA 4] Center 36 (8~64) winsize 57
6611 18:05:26.983291 [CA 5] Center 36 (8~64) winsize 57
6612 18:05:26.983392
6613 18:05:26.986320 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6614 18:05:26.986410
6615 18:05:26.990145 [CATrainingPosCal] consider 2 rank data
6616 18:05:26.993332 u2DelayCellTimex100 = 270/100 ps
6617 18:05:26.996335 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 18:05:27.000084 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 18:05:27.002899 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 18:05:27.006000 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 18:05:27.009753 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 18:05:27.012780 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 18:05:27.016137
6624 18:05:27.019740 CA PerBit enable=1, Macro0, CA PI delay=36
6625 18:05:27.019905
6626 18:05:27.023063 [CBTSetCACLKResult] CA Dly = 36
6627 18:05:27.023181 CS Dly: 1 (0~32)
6628 18:05:27.023276
6629 18:05:27.025790 ----->DramcWriteLeveling(PI) begin...
6630 18:05:27.025874 ==
6631 18:05:27.029755 Dram Type= 6, Freq= 0, CH_1, rank 0
6632 18:05:27.032495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 18:05:27.036075 ==
6634 18:05:27.036195 Write leveling (Byte 0): 40 => 8
6635 18:05:27.039250 Write leveling (Byte 1): 40 => 8
6636 18:05:27.042351 DramcWriteLeveling(PI) end<-----
6637 18:05:27.042471
6638 18:05:27.042565 ==
6639 18:05:27.045999 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 18:05:27.052481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 18:05:27.052574 ==
6642 18:05:27.052646 [Gating] SW mode calibration
6643 18:05:27.062753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6644 18:05:27.065785 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6645 18:05:27.072677 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 18:05:27.075526 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 18:05:27.079022 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 18:05:27.082041 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 18:05:27.088782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 18:05:27.092644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 18:05:27.095512 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 18:05:27.102495 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 18:05:27.105460 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 18:05:27.109054 Total UI for P1: 0, mck2ui 16
6655 18:05:27.112175 best dqsien dly found for B0: ( 0, 14, 24)
6656 18:05:27.115778 Total UI for P1: 0, mck2ui 16
6657 18:05:27.118738 best dqsien dly found for B1: ( 0, 14, 24)
6658 18:05:27.122302 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6659 18:05:27.125327 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6660 18:05:27.125454
6661 18:05:27.128968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 18:05:27.132594 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 18:05:27.135703 [Gating] SW calibration Done
6664 18:05:27.135813 ==
6665 18:05:27.138768 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 18:05:27.145280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 18:05:27.145370 ==
6668 18:05:27.145442 RX Vref Scan: 0
6669 18:05:27.145517
6670 18:05:27.148931 RX Vref 0 -> 0, step: 1
6671 18:05:27.149052
6672 18:05:27.152096 RX Delay -410 -> 252, step: 16
6673 18:05:27.155480 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6674 18:05:27.158996 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6675 18:05:27.165551 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6676 18:05:27.168970 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6677 18:05:27.172249 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6678 18:05:27.175337 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6679 18:05:27.178847 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6680 18:05:27.185618 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6681 18:05:27.188726 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6682 18:05:27.191746 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6683 18:05:27.195033 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6684 18:05:27.202415 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6685 18:05:27.205323 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6686 18:05:27.209196 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6687 18:05:27.215689 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6688 18:05:27.218806 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6689 18:05:27.218893 ==
6690 18:05:27.221824 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 18:05:27.225576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 18:05:27.225671 ==
6693 18:05:27.228663 DQS Delay:
6694 18:05:27.228756 DQS0 = 27, DQS1 = 35
6695 18:05:27.228834 DQM Delay:
6696 18:05:27.231703 DQM0 = 10, DQM1 = 13
6697 18:05:27.231787 DQ Delay:
6698 18:05:27.235440 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6699 18:05:27.238399 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6700 18:05:27.242437 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6701 18:05:27.245031 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6702 18:05:27.245124
6703 18:05:27.245197
6704 18:05:27.245267 ==
6705 18:05:27.248343 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 18:05:27.251384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 18:05:27.255052 ==
6708 18:05:27.255134
6709 18:05:27.255210
6710 18:05:27.255272 TX Vref Scan disable
6711 18:05:27.258054 == TX Byte 0 ==
6712 18:05:27.261808 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6713 18:05:27.265019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6714 18:05:27.273417 == TX Byte 1 ==
6715 18:05:27.273601 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6716 18:05:27.275305 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6717 18:05:27.275417 ==
6718 18:05:27.278104 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 18:05:27.284648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 18:05:27.284747 ==
6721 18:05:27.284821
6722 18:05:27.284886
6723 18:05:27.284949 TX Vref Scan disable
6724 18:05:27.288279 == TX Byte 0 ==
6725 18:05:27.291725 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 18:05:27.294372 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 18:05:27.297932 == TX Byte 1 ==
6728 18:05:27.301745 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 18:05:27.304482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 18:05:27.304569
6731 18:05:27.307835 [DATLAT]
6732 18:05:27.307915 Freq=400, CH1 RK0
6733 18:05:27.307988
6734 18:05:27.311395 DATLAT Default: 0xf
6735 18:05:27.311479 0, 0xFFFF, sum = 0
6736 18:05:27.314576 1, 0xFFFF, sum = 0
6737 18:05:27.314659 2, 0xFFFF, sum = 0
6738 18:05:27.317776 3, 0xFFFF, sum = 0
6739 18:05:27.317893 4, 0xFFFF, sum = 0
6740 18:05:27.320926 5, 0xFFFF, sum = 0
6741 18:05:27.321031 6, 0xFFFF, sum = 0
6742 18:05:27.324211 7, 0xFFFF, sum = 0
6743 18:05:27.324325 8, 0xFFFF, sum = 0
6744 18:05:27.327678 9, 0xFFFF, sum = 0
6745 18:05:27.327762 10, 0xFFFF, sum = 0
6746 18:05:27.331206 11, 0xFFFF, sum = 0
6747 18:05:27.334173 12, 0xFFFF, sum = 0
6748 18:05:27.334258 13, 0x0, sum = 1
6749 18:05:27.334324 14, 0x0, sum = 2
6750 18:05:27.337923 15, 0x0, sum = 3
6751 18:05:27.338008 16, 0x0, sum = 4
6752 18:05:27.340951 best_step = 14
6753 18:05:27.341030
6754 18:05:27.341103 ==
6755 18:05:27.344643 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 18:05:27.347598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 18:05:27.347677 ==
6758 18:05:27.351168 RX Vref Scan: 1
6759 18:05:27.351251
6760 18:05:27.351317 RX Vref 0 -> 0, step: 1
6761 18:05:27.351379
6762 18:05:27.354041 RX Delay -311 -> 252, step: 8
6763 18:05:27.354121
6764 18:05:27.357703 Set Vref, RX VrefLevel [Byte0]: 54
6765 18:05:27.360735 [Byte1]: 53
6766 18:05:27.366168
6767 18:05:27.366248 Final RX Vref Byte 0 = 54 to rank0
6768 18:05:27.369074 Final RX Vref Byte 1 = 53 to rank0
6769 18:05:27.372967 Final RX Vref Byte 0 = 54 to rank1
6770 18:05:27.375829 Final RX Vref Byte 1 = 53 to rank1==
6771 18:05:27.378737 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 18:05:27.386152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 18:05:27.386275 ==
6774 18:05:27.386377 DQS Delay:
6775 18:05:27.389118 DQS0 = 32, DQS1 = 32
6776 18:05:27.389193 DQM Delay:
6777 18:05:27.389271 DQM0 = 13, DQM1 = 10
6778 18:05:27.392098 DQ Delay:
6779 18:05:27.395617 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6780 18:05:27.399265 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6781 18:05:27.399365 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6782 18:05:27.402065 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6783 18:05:27.402149
6784 18:05:27.405651
6785 18:05:27.412544 [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6786 18:05:27.415758 CH1 RK0: MR19=C0C, MR18=8BC3
6787 18:05:27.422364 CH1_RK0: MR19=0xC0C, MR18=0x8BC3, DQSOSC=385, MR23=63, INC=398, DEC=265
6788 18:05:27.422448 ==
6789 18:05:27.425249 Dram Type= 6, Freq= 0, CH_1, rank 1
6790 18:05:27.428787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 18:05:27.428872 ==
6792 18:05:27.432382 [Gating] SW mode calibration
6793 18:05:27.438888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6794 18:05:27.445245 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6795 18:05:27.449010 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 18:05:27.452204 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 18:05:27.455268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 18:05:27.462268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 18:05:27.465537 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 18:05:27.469056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 18:05:27.475132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 18:05:27.478903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 18:05:27.482025 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 18:05:27.485726 Total UI for P1: 0, mck2ui 16
6805 18:05:27.488334 best dqsien dly found for B0: ( 0, 14, 24)
6806 18:05:27.492085 Total UI for P1: 0, mck2ui 16
6807 18:05:27.495056 best dqsien dly found for B1: ( 0, 14, 24)
6808 18:05:27.498886 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6809 18:05:27.505339 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6810 18:05:27.505423
6811 18:05:27.508904 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 18:05:27.511668 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 18:05:27.515348 [Gating] SW calibration Done
6814 18:05:27.515446 ==
6815 18:05:27.518351 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 18:05:27.522169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 18:05:27.522253 ==
6818 18:05:27.522318 RX Vref Scan: 0
6819 18:05:27.525048
6820 18:05:27.525143 RX Vref 0 -> 0, step: 1
6821 18:05:27.525208
6822 18:05:27.528995 RX Delay -410 -> 252, step: 16
6823 18:05:27.531983 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6824 18:05:27.538750 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6825 18:05:27.541770 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6826 18:05:27.545465 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6827 18:05:27.548462 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6828 18:05:27.554925 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6829 18:05:27.558635 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6830 18:05:27.562143 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6831 18:05:27.565114 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6832 18:05:27.571838 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6833 18:05:27.574925 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6834 18:05:27.578434 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6835 18:05:27.581617 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6836 18:05:27.588907 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6837 18:05:27.592011 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6838 18:05:27.594946 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6839 18:05:27.595033 ==
6840 18:05:27.598504 Dram Type= 6, Freq= 0, CH_1, rank 1
6841 18:05:27.601521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 18:05:27.605104 ==
6843 18:05:27.605181 DQS Delay:
6844 18:05:27.605262 DQS0 = 35, DQS1 = 35
6845 18:05:27.608003 DQM Delay:
6846 18:05:27.608075 DQM0 = 18, DQM1 = 14
6847 18:05:27.611695 DQ Delay:
6848 18:05:27.614698 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6849 18:05:27.614783 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6850 18:05:27.618327 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6851 18:05:27.621779 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6852 18:05:27.621858
6853 18:05:27.624725
6854 18:05:27.624808 ==
6855 18:05:27.627917 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 18:05:27.631707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 18:05:27.631779 ==
6858 18:05:27.631842
6859 18:05:27.631900
6860 18:05:27.634537 TX Vref Scan disable
6861 18:05:27.634608 == TX Byte 0 ==
6862 18:05:27.638362 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6863 18:05:27.645190 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6864 18:05:27.645290 == TX Byte 1 ==
6865 18:05:27.648197 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6866 18:05:27.655083 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6867 18:05:27.655168 ==
6868 18:05:27.658033 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 18:05:27.661691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 18:05:27.661767 ==
6871 18:05:27.661831
6872 18:05:27.661891
6873 18:05:27.664383 TX Vref Scan disable
6874 18:05:27.664459 == TX Byte 0 ==
6875 18:05:27.667958 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 18:05:27.674642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 18:05:27.674748 == TX Byte 1 ==
6878 18:05:27.677467 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6879 18:05:27.684965 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6880 18:05:27.685044
6881 18:05:27.685109 [DATLAT]
6882 18:05:27.685169 Freq=400, CH1 RK1
6883 18:05:27.685229
6884 18:05:27.688118 DATLAT Default: 0xe
6885 18:05:27.690987 0, 0xFFFF, sum = 0
6886 18:05:27.691072 1, 0xFFFF, sum = 0
6887 18:05:27.694369 2, 0xFFFF, sum = 0
6888 18:05:27.694458 3, 0xFFFF, sum = 0
6889 18:05:27.697808 4, 0xFFFF, sum = 0
6890 18:05:27.697894 5, 0xFFFF, sum = 0
6891 18:05:27.701137 6, 0xFFFF, sum = 0
6892 18:05:27.701259 7, 0xFFFF, sum = 0
6893 18:05:27.704471 8, 0xFFFF, sum = 0
6894 18:05:27.704555 9, 0xFFFF, sum = 0
6895 18:05:27.707888 10, 0xFFFF, sum = 0
6896 18:05:27.707975 11, 0xFFFF, sum = 0
6897 18:05:27.711255 12, 0xFFFF, sum = 0
6898 18:05:27.711341 13, 0x0, sum = 1
6899 18:05:27.714515 14, 0x0, sum = 2
6900 18:05:27.714601 15, 0x0, sum = 3
6901 18:05:27.717840 16, 0x0, sum = 4
6902 18:05:27.717926 best_step = 14
6903 18:05:27.717991
6904 18:05:27.718054 ==
6905 18:05:27.721316 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 18:05:27.724491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 18:05:27.727743 ==
6908 18:05:27.727856 RX Vref Scan: 0
6909 18:05:27.727953
6910 18:05:27.731105 RX Vref 0 -> 0, step: 1
6911 18:05:27.731216
6912 18:05:27.734501 RX Delay -311 -> 252, step: 8
6913 18:05:27.737508 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6914 18:05:27.744237 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6915 18:05:27.747376 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6916 18:05:27.750983 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6917 18:05:27.754051 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6918 18:05:27.760571 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6919 18:05:27.764347 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6920 18:05:27.767337 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6921 18:05:27.770622 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6922 18:05:27.777137 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6923 18:05:27.780803 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6924 18:05:27.784280 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6925 18:05:27.790339 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6926 18:05:27.794083 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6927 18:05:27.797130 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6928 18:05:27.800858 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6929 18:05:27.800934 ==
6930 18:05:27.803877 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 18:05:27.810347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 18:05:27.810450 ==
6933 18:05:27.810538 DQS Delay:
6934 18:05:27.813722 DQS0 = 28, DQS1 = 36
6935 18:05:27.813804 DQM Delay:
6936 18:05:27.817412 DQM0 = 11, DQM1 = 15
6937 18:05:27.817519 DQ Delay:
6938 18:05:27.820628 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6939 18:05:27.824047 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6940 18:05:27.824165 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6941 18:05:27.830704 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6942 18:05:27.830785
6943 18:05:27.830848
6944 18:05:27.837086 [DQSOSCAuto] RK1, (LSB)MR18= 0xc555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6945 18:05:27.840616 CH1 RK1: MR19=C0C, MR18=C555
6946 18:05:27.846868 CH1_RK1: MR19=0xC0C, MR18=0xC555, DQSOSC=385, MR23=63, INC=398, DEC=265
6947 18:05:27.850726 [RxdqsGatingPostProcess] freq 400
6948 18:05:27.853934 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6949 18:05:27.857499 best DQS0 dly(2T, 0.5T) = (0, 10)
6950 18:05:27.860532 best DQS1 dly(2T, 0.5T) = (0, 10)
6951 18:05:27.864127 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6952 18:05:27.867086 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6953 18:05:27.870252 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 18:05:27.873859 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 18:05:27.876878 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 18:05:27.880466 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 18:05:27.884189 Pre-setting of DQS Precalculation
6958 18:05:27.886886 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6959 18:05:27.893779 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6960 18:05:27.903438 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6961 18:05:27.903550
6962 18:05:27.903644
6963 18:05:27.907383 [Calibration Summary] 800 Mbps
6964 18:05:27.907488 CH 0, Rank 0
6965 18:05:27.910232 SW Impedance : PASS
6966 18:05:27.910312 DUTY Scan : NO K
6967 18:05:27.913377 ZQ Calibration : PASS
6968 18:05:27.913455 Jitter Meter : NO K
6969 18:05:27.916924 CBT Training : PASS
6970 18:05:27.919917 Write leveling : PASS
6971 18:05:27.920021 RX DQS gating : PASS
6972 18:05:27.923483 RX DQ/DQS(RDDQC) : PASS
6973 18:05:27.926796 TX DQ/DQS : PASS
6974 18:05:27.926905 RX DATLAT : PASS
6975 18:05:27.930548 RX DQ/DQS(Engine): PASS
6976 18:05:27.933362 TX OE : NO K
6977 18:05:27.933460 All Pass.
6978 18:05:27.933530
6979 18:05:27.933592 CH 0, Rank 1
6980 18:05:27.937048 SW Impedance : PASS
6981 18:05:27.940178 DUTY Scan : NO K
6982 18:05:27.940289 ZQ Calibration : PASS
6983 18:05:27.943174 Jitter Meter : NO K
6984 18:05:27.947067 CBT Training : PASS
6985 18:05:27.947174 Write leveling : NO K
6986 18:05:27.949943 RX DQS gating : PASS
6987 18:05:27.953384 RX DQ/DQS(RDDQC) : PASS
6988 18:05:27.953492 TX DQ/DQS : PASS
6989 18:05:27.956859 RX DATLAT : PASS
6990 18:05:27.959773 RX DQ/DQS(Engine): PASS
6991 18:05:27.959884 TX OE : NO K
6992 18:05:27.963250 All Pass.
6993 18:05:27.963329
6994 18:05:27.963392 CH 1, Rank 0
6995 18:05:27.966564 SW Impedance : PASS
6996 18:05:27.966670 DUTY Scan : NO K
6997 18:05:27.969944 ZQ Calibration : PASS
6998 18:05:27.973087 Jitter Meter : NO K
6999 18:05:27.973191 CBT Training : PASS
7000 18:05:27.976277 Write leveling : PASS
7001 18:05:27.976394 RX DQS gating : PASS
7002 18:05:27.979980 RX DQ/DQS(RDDQC) : PASS
7003 18:05:27.983004 TX DQ/DQS : PASS
7004 18:05:27.983111 RX DATLAT : PASS
7005 18:05:27.986330 RX DQ/DQS(Engine): PASS
7006 18:05:27.989631 TX OE : NO K
7007 18:05:27.989738 All Pass.
7008 18:05:27.989832
7009 18:05:27.989926 CH 1, Rank 1
7010 18:05:27.993174 SW Impedance : PASS
7011 18:05:27.996587 DUTY Scan : NO K
7012 18:05:27.996680 ZQ Calibration : PASS
7013 18:05:27.999379 Jitter Meter : NO K
7014 18:05:28.003129 CBT Training : PASS
7015 18:05:28.003209 Write leveling : NO K
7016 18:05:28.005998 RX DQS gating : PASS
7017 18:05:28.009844 RX DQ/DQS(RDDQC) : PASS
7018 18:05:28.009918 TX DQ/DQS : PASS
7019 18:05:28.012771 RX DATLAT : PASS
7020 18:05:28.016777 RX DQ/DQS(Engine): PASS
7021 18:05:28.016890 TX OE : NO K
7022 18:05:28.019611 All Pass.
7023 18:05:28.019686
7024 18:05:28.019759 DramC Write-DBI off
7025 18:05:28.022710 PER_BANK_REFRESH: Hybrid Mode
7026 18:05:28.022791 TX_TRACKING: ON
7027 18:05:28.032768 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7028 18:05:28.036461 [FAST_K] Save calibration result to emmc
7029 18:05:28.039765 dramc_set_vcore_voltage set vcore to 725000
7030 18:05:28.042544 Read voltage for 1600, 0
7031 18:05:28.042635 Vio18 = 0
7032 18:05:28.046250 Vcore = 725000
7033 18:05:28.046327 Vdram = 0
7034 18:05:28.046405 Vddq = 0
7035 18:05:28.046465 Vmddr = 0
7036 18:05:28.053077 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7037 18:05:28.059810 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7038 18:05:28.059917 MEM_TYPE=3, freq_sel=13
7039 18:05:28.062719 sv_algorithm_assistance_LP4_3733
7040 18:05:28.066481 ============ PULL DRAM RESETB DOWN ============
7041 18:05:28.073309 ========== PULL DRAM RESETB DOWN end =========
7042 18:05:28.076209 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7043 18:05:28.079425 ===================================
7044 18:05:28.082845 LPDDR4 DRAM CONFIGURATION
7045 18:05:28.086300 ===================================
7046 18:05:28.086376 EX_ROW_EN[0] = 0x0
7047 18:05:28.089140 EX_ROW_EN[1] = 0x0
7048 18:05:28.089214 LP4Y_EN = 0x0
7049 18:05:28.093061 WORK_FSP = 0x1
7050 18:05:28.093135 WL = 0x5
7051 18:05:28.095825 RL = 0x5
7052 18:05:28.099063 BL = 0x2
7053 18:05:28.099178 RPST = 0x0
7054 18:05:28.102800 RD_PRE = 0x0
7055 18:05:28.102915 WR_PRE = 0x1
7056 18:05:28.105759 WR_PST = 0x1
7057 18:05:28.105841 DBI_WR = 0x0
7058 18:05:28.109462 DBI_RD = 0x0
7059 18:05:28.109540 OTF = 0x1
7060 18:05:28.112436 ===================================
7061 18:05:28.115792 ===================================
7062 18:05:28.119493 ANA top config
7063 18:05:28.122326 ===================================
7064 18:05:28.122436 DLL_ASYNC_EN = 0
7065 18:05:28.125977 ALL_SLAVE_EN = 0
7066 18:05:28.128977 NEW_RANK_MODE = 1
7067 18:05:28.132083 DLL_IDLE_MODE = 1
7068 18:05:28.132165 LP45_APHY_COMB_EN = 1
7069 18:05:28.135737 TX_ODT_DIS = 0
7070 18:05:28.138798 NEW_8X_MODE = 1
7071 18:05:28.142434 ===================================
7072 18:05:28.145304 ===================================
7073 18:05:28.148680 data_rate = 3200
7074 18:05:28.152312 CKR = 1
7075 18:05:28.155890 DQ_P2S_RATIO = 8
7076 18:05:28.158886 ===================================
7077 18:05:28.158987 CA_P2S_RATIO = 8
7078 18:05:28.161981 DQ_CA_OPEN = 0
7079 18:05:28.165676 DQ_SEMI_OPEN = 0
7080 18:05:28.169325 CA_SEMI_OPEN = 0
7081 18:05:28.172293 CA_FULL_RATE = 0
7082 18:05:28.176007 DQ_CKDIV4_EN = 0
7083 18:05:28.176114 CA_CKDIV4_EN = 0
7084 18:05:28.178822 CA_PREDIV_EN = 0
7085 18:05:28.181794 PH8_DLY = 12
7086 18:05:28.185561 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7087 18:05:28.188758 DQ_AAMCK_DIV = 4
7088 18:05:28.191704 CA_AAMCK_DIV = 4
7089 18:05:28.191777 CA_ADMCK_DIV = 4
7090 18:05:28.195437 DQ_TRACK_CA_EN = 0
7091 18:05:28.198360 CA_PICK = 1600
7092 18:05:28.202188 CA_MCKIO = 1600
7093 18:05:28.205143 MCKIO_SEMI = 0
7094 18:05:28.209003 PLL_FREQ = 3068
7095 18:05:28.212117 DQ_UI_PI_RATIO = 32
7096 18:05:28.212199 CA_UI_PI_RATIO = 0
7097 18:05:28.215592 ===================================
7098 18:05:28.218406 ===================================
7099 18:05:28.221628 memory_type:LPDDR4
7100 18:05:28.225265 GP_NUM : 10
7101 18:05:28.225348 SRAM_EN : 1
7102 18:05:28.228429 MD32_EN : 0
7103 18:05:28.231593 ===================================
7104 18:05:28.235052 [ANA_INIT] >>>>>>>>>>>>>>
7105 18:05:28.238576 <<<<<< [CONFIGURE PHASE]: ANA_TX
7106 18:05:28.241487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7107 18:05:28.244684 ===================================
7108 18:05:28.248167 data_rate = 3200,PCW = 0X7600
7109 18:05:28.248256 ===================================
7110 18:05:28.254969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7111 18:05:28.258422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 18:05:28.264723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 18:05:28.268536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7114 18:05:28.271520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7115 18:05:28.275436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7116 18:05:28.278221 [ANA_INIT] flow start
7117 18:05:28.281231 [ANA_INIT] PLL >>>>>>>>
7118 18:05:28.281309 [ANA_INIT] PLL <<<<<<<<
7119 18:05:28.284953 [ANA_INIT] MIDPI >>>>>>>>
7120 18:05:28.288173 [ANA_INIT] MIDPI <<<<<<<<
7121 18:05:28.288255 [ANA_INIT] DLL >>>>>>>>
7122 18:05:28.291808 [ANA_INIT] DLL <<<<<<<<
7123 18:05:28.294787 [ANA_INIT] flow end
7124 18:05:28.297777 ============ LP4 DIFF to SE enter ============
7125 18:05:28.301522 ============ LP4 DIFF to SE exit ============
7126 18:05:28.304521 [ANA_INIT] <<<<<<<<<<<<<
7127 18:05:28.308191 [Flow] Enable top DCM control >>>>>
7128 18:05:28.311254 [Flow] Enable top DCM control <<<<<
7129 18:05:28.315017 Enable DLL master slave shuffle
7130 18:05:28.318024 ==============================================================
7131 18:05:28.321062 Gating Mode config
7132 18:05:28.327931 ==============================================================
7133 18:05:28.328013 Config description:
7134 18:05:28.337917 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7135 18:05:28.344460 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7136 18:05:28.351134 SELPH_MODE 0: By rank 1: By Phase
7137 18:05:28.354464 ==============================================================
7138 18:05:28.357470 GAT_TRACK_EN = 1
7139 18:05:28.360722 RX_GATING_MODE = 2
7140 18:05:28.364492 RX_GATING_TRACK_MODE = 2
7141 18:05:28.367654 SELPH_MODE = 1
7142 18:05:28.371030 PICG_EARLY_EN = 1
7143 18:05:28.374331 VALID_LAT_VALUE = 1
7144 18:05:28.377668 ==============================================================
7145 18:05:28.381061 Enter into Gating configuration >>>>
7146 18:05:28.384384 Exit from Gating configuration <<<<
7147 18:05:28.387285 Enter into DVFS_PRE_config >>>>>
7148 18:05:28.400317 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7149 18:05:28.404018 Exit from DVFS_PRE_config <<<<<
7150 18:05:28.407015 Enter into PICG configuration >>>>
7151 18:05:28.407132 Exit from PICG configuration <<<<
7152 18:05:28.410728 [RX_INPUT] configuration >>>>>
7153 18:05:28.413687 [RX_INPUT] configuration <<<<<
7154 18:05:28.420603 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7155 18:05:28.424301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7156 18:05:28.430542 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7157 18:05:28.437065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7158 18:05:28.443684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 18:05:28.450633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 18:05:28.453454 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7161 18:05:28.457118 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7162 18:05:28.460256 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7163 18:05:28.466918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7164 18:05:28.470478 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7165 18:05:28.473991 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 18:05:28.477114 ===================================
7167 18:05:28.480176 LPDDR4 DRAM CONFIGURATION
7168 18:05:28.484089 ===================================
7169 18:05:28.486852 EX_ROW_EN[0] = 0x0
7170 18:05:28.486936 EX_ROW_EN[1] = 0x0
7171 18:05:28.490517 LP4Y_EN = 0x0
7172 18:05:28.490598 WORK_FSP = 0x1
7173 18:05:28.493559 WL = 0x5
7174 18:05:28.493645 RL = 0x5
7175 18:05:28.497114 BL = 0x2
7176 18:05:28.497195 RPST = 0x0
7177 18:05:28.500665 RD_PRE = 0x0
7178 18:05:28.500745 WR_PRE = 0x1
7179 18:05:28.503892 WR_PST = 0x1
7180 18:05:28.503994 DBI_WR = 0x0
7181 18:05:28.506540 DBI_RD = 0x0
7182 18:05:28.506614 OTF = 0x1
7183 18:05:28.510229 ===================================
7184 18:05:28.516720 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7185 18:05:28.520056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7186 18:05:28.523286 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 18:05:28.526759 ===================================
7188 18:05:28.530012 LPDDR4 DRAM CONFIGURATION
7189 18:05:28.533673 ===================================
7190 18:05:28.536520 EX_ROW_EN[0] = 0x10
7191 18:05:28.536628 EX_ROW_EN[1] = 0x0
7192 18:05:28.540115 LP4Y_EN = 0x0
7193 18:05:28.540222 WORK_FSP = 0x1
7194 18:05:28.543026 WL = 0x5
7195 18:05:28.543136 RL = 0x5
7196 18:05:28.546885 BL = 0x2
7197 18:05:28.547009 RPST = 0x0
7198 18:05:28.549975 RD_PRE = 0x0
7199 18:05:28.550084 WR_PRE = 0x1
7200 18:05:28.553163 WR_PST = 0x1
7201 18:05:28.553268 DBI_WR = 0x0
7202 18:05:28.556075 DBI_RD = 0x0
7203 18:05:28.556178 OTF = 0x1
7204 18:05:28.559716 ===================================
7205 18:05:28.566404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7206 18:05:28.566515 ==
7207 18:05:28.569533 Dram Type= 6, Freq= 0, CH_0, rank 0
7208 18:05:28.576026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7209 18:05:28.576133 ==
7210 18:05:28.576229 [Duty_Offset_Calibration]
7211 18:05:28.579489 B0:2 B1:1 CA:1
7212 18:05:28.579593
7213 18:05:28.582565 [DutyScan_Calibration_Flow] k_type=0
7214 18:05:28.592263
7215 18:05:28.592378 ==CLK 0==
7216 18:05:28.595215 Final CLK duty delay cell = 0
7217 18:05:28.599173 [0] MAX Duty = 5156%(X100), DQS PI = 22
7218 18:05:28.602069 [0] MIN Duty = 4876%(X100), DQS PI = 46
7219 18:05:28.602179 [0] AVG Duty = 5016%(X100)
7220 18:05:28.605851
7221 18:05:28.608842 CH0 CLK Duty spec in!! Max-Min= 280%
7222 18:05:28.611878 [DutyScan_Calibration_Flow] ====Done====
7223 18:05:28.611980
7224 18:05:28.615501 [DutyScan_Calibration_Flow] k_type=1
7225 18:05:28.631366
7226 18:05:28.631482 ==DQS 0 ==
7227 18:05:28.635082 Final DQS duty delay cell = -4
7228 18:05:28.638142 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7229 18:05:28.641453 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7230 18:05:28.644807 [-4] AVG Duty = 4891%(X100)
7231 18:05:28.644914
7232 18:05:28.645011 ==DQS 1 ==
7233 18:05:28.648012 Final DQS duty delay cell = 0
7234 18:05:28.651629 [0] MAX Duty = 5187%(X100), DQS PI = 20
7235 18:05:28.654762 [0] MIN Duty = 5031%(X100), DQS PI = 52
7236 18:05:28.657695 [0] AVG Duty = 5109%(X100)
7237 18:05:28.657800
7238 18:05:28.661826 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7239 18:05:28.661935
7240 18:05:28.664903 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7241 18:05:28.668024 [DutyScan_Calibration_Flow] ====Done====
7242 18:05:28.668124
7243 18:05:28.671426 [DutyScan_Calibration_Flow] k_type=3
7244 18:05:28.689092
7245 18:05:28.689186 ==DQM 0 ==
7246 18:05:28.692193 Final DQM duty delay cell = 0
7247 18:05:28.695880 [0] MAX Duty = 5187%(X100), DQS PI = 26
7248 18:05:28.698652 [0] MIN Duty = 4907%(X100), DQS PI = 54
7249 18:05:28.702419 [0] AVG Duty = 5047%(X100)
7250 18:05:28.702527
7251 18:05:28.702621 ==DQM 1 ==
7252 18:05:28.705474 Final DQM duty delay cell = 0
7253 18:05:28.708532 [0] MAX Duty = 5187%(X100), DQS PI = 20
7254 18:05:28.712283 [0] MIN Duty = 5031%(X100), DQS PI = 50
7255 18:05:28.715190 [0] AVG Duty = 5109%(X100)
7256 18:05:28.715296
7257 18:05:28.718924 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7258 18:05:28.719030
7259 18:05:28.721949 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7260 18:05:28.725684 [DutyScan_Calibration_Flow] ====Done====
7261 18:05:28.725790
7262 18:05:28.728618 [DutyScan_Calibration_Flow] k_type=2
7263 18:05:28.745708
7264 18:05:28.745837 ==DQ 0 ==
7265 18:05:28.749529 Final DQ duty delay cell = 0
7266 18:05:28.752664 [0] MAX Duty = 5062%(X100), DQS PI = 26
7267 18:05:28.756328 [0] MIN Duty = 4907%(X100), DQS PI = 0
7268 18:05:28.756448 [0] AVG Duty = 4984%(X100)
7269 18:05:28.759187
7270 18:05:28.759300 ==DQ 1 ==
7271 18:05:28.762620 Final DQ duty delay cell = 0
7272 18:05:28.766000 [0] MAX Duty = 5125%(X100), DQS PI = 20
7273 18:05:28.769178 [0] MIN Duty = 4938%(X100), DQS PI = 14
7274 18:05:28.769293 [0] AVG Duty = 5031%(X100)
7275 18:05:28.772744
7276 18:05:28.775699 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7277 18:05:28.775810
7278 18:05:28.779271 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7279 18:05:28.782081 [DutyScan_Calibration_Flow] ====Done====
7280 18:05:28.782187 ==
7281 18:05:28.785477 Dram Type= 6, Freq= 0, CH_1, rank 0
7282 18:05:28.789235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 18:05:28.789346 ==
7284 18:05:28.792360 [Duty_Offset_Calibration]
7285 18:05:28.792462 B0:1 B1:0 CA:1
7286 18:05:28.792552
7287 18:05:28.795456 [DutyScan_Calibration_Flow] k_type=0
7288 18:05:28.805672
7289 18:05:28.805765 ==CLK 0==
7290 18:05:28.808765 Final CLK duty delay cell = -4
7291 18:05:28.812358 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7292 18:05:28.815075 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7293 18:05:28.818487 [-4] AVG Duty = 4922%(X100)
7294 18:05:28.818597
7295 18:05:28.822288 CH1 CLK Duty spec in!! Max-Min= 156%
7296 18:05:28.825356 [DutyScan_Calibration_Flow] ====Done====
7297 18:05:28.825438
7298 18:05:28.828343 [DutyScan_Calibration_Flow] k_type=1
7299 18:05:28.845741
7300 18:05:28.845855 ==DQS 0 ==
7301 18:05:28.848815 Final DQS duty delay cell = 0
7302 18:05:28.852241 [0] MAX Duty = 5094%(X100), DQS PI = 32
7303 18:05:28.855344 [0] MIN Duty = 4844%(X100), DQS PI = 0
7304 18:05:28.858386 [0] AVG Duty = 4969%(X100)
7305 18:05:28.858492
7306 18:05:28.858585 ==DQS 1 ==
7307 18:05:28.862324 Final DQS duty delay cell = 0
7308 18:05:28.865126 [0] MAX Duty = 5249%(X100), DQS PI = 16
7309 18:05:28.868857 [0] MIN Duty = 4938%(X100), DQS PI = 8
7310 18:05:28.868960 [0] AVG Duty = 5093%(X100)
7311 18:05:28.871690
7312 18:05:28.875300 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7313 18:05:28.875407
7314 18:05:28.878904 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7315 18:05:28.881969 [DutyScan_Calibration_Flow] ====Done====
7316 18:05:28.882052
7317 18:05:28.885021 [DutyScan_Calibration_Flow] k_type=3
7318 18:05:28.902267
7319 18:05:28.902351 ==DQM 0 ==
7320 18:05:28.905729 Final DQM duty delay cell = 0
7321 18:05:28.908879 [0] MAX Duty = 5187%(X100), DQS PI = 8
7322 18:05:28.912173 [0] MIN Duty = 4969%(X100), DQS PI = 48
7323 18:05:28.912286 [0] AVG Duty = 5078%(X100)
7324 18:05:28.915501
7325 18:05:28.915585 ==DQM 1 ==
7326 18:05:28.918962 Final DQM duty delay cell = 0
7327 18:05:28.922418 [0] MAX Duty = 5062%(X100), DQS PI = 16
7328 18:05:28.925357 [0] MIN Duty = 4907%(X100), DQS PI = 32
7329 18:05:28.928547 [0] AVG Duty = 4984%(X100)
7330 18:05:28.928629
7331 18:05:28.931731 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7332 18:05:28.931813
7333 18:05:28.935604 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7334 18:05:28.938729 [DutyScan_Calibration_Flow] ====Done====
7335 18:05:28.938818
7336 18:05:28.942184 [DutyScan_Calibration_Flow] k_type=2
7337 18:05:28.958609
7338 18:05:28.958704 ==DQ 0 ==
7339 18:05:28.961802 Final DQ duty delay cell = -4
7340 18:05:28.964735 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7341 18:05:28.968521 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7342 18:05:28.971495 [-4] AVG Duty = 4953%(X100)
7343 18:05:28.971569
7344 18:05:28.971633 ==DQ 1 ==
7345 18:05:28.974688 Final DQ duty delay cell = 0
7346 18:05:28.978292 [0] MAX Duty = 5093%(X100), DQS PI = 16
7347 18:05:28.981201 [0] MIN Duty = 4938%(X100), DQS PI = 8
7348 18:05:28.984657 [0] AVG Duty = 5015%(X100)
7349 18:05:28.984764
7350 18:05:28.988310 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7351 18:05:28.988404
7352 18:05:28.991136 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7353 18:05:28.994894 [DutyScan_Calibration_Flow] ====Done====
7354 18:05:28.997962 nWR fixed to 30
7355 18:05:29.001735 [ModeRegInit_LP4] CH0 RK0
7356 18:05:29.001840 [ModeRegInit_LP4] CH0 RK1
7357 18:05:29.004511 [ModeRegInit_LP4] CH1 RK0
7358 18:05:29.008101 [ModeRegInit_LP4] CH1 RK1
7359 18:05:29.008209 match AC timing 5
7360 18:05:29.014213 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7361 18:05:29.017923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7362 18:05:29.021059 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7363 18:05:29.027625 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7364 18:05:29.031193 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7365 18:05:29.031298 [MiockJmeterHQA]
7366 18:05:29.031393
7367 18:05:29.034239 [DramcMiockJmeter] u1RxGatingPI = 0
7368 18:05:29.037858 0 : 4363, 4137
7369 18:05:29.037968 4 : 4252, 4027
7370 18:05:29.040789 8 : 4252, 4027
7371 18:05:29.040895 12 : 4361, 4137
7372 18:05:29.044571 16 : 4255, 4029
7373 18:05:29.044676 20 : 4253, 4026
7374 18:05:29.044772 24 : 4363, 4140
7375 18:05:29.047388 28 : 4255, 4029
7376 18:05:29.047497 32 : 4361, 4137
7377 18:05:29.050796 36 : 4250, 4027
7378 18:05:29.050904 40 : 4363, 4140
7379 18:05:29.054130 44 : 4252, 4027
7380 18:05:29.054237 48 : 4250, 4027
7381 18:05:29.054336 52 : 4255, 4029
7382 18:05:29.057457 56 : 4250, 4027
7383 18:05:29.057563 60 : 4252, 4027
7384 18:05:29.061013 64 : 4250, 4027
7385 18:05:29.061119 68 : 4249, 4027
7386 18:05:29.063908 72 : 4250, 4027
7387 18:05:29.064010 76 : 4363, 4140
7388 18:05:29.067700 80 : 4250, 4026
7389 18:05:29.067805 84 : 4252, 4030
7390 18:05:29.067910 88 : 4250, 141
7391 18:05:29.070652 92 : 4250, 0
7392 18:05:29.070761 96 : 4252, 0
7393 18:05:29.074494 100 : 4361, 0
7394 18:05:29.074603 104 : 4250, 0
7395 18:05:29.074702 108 : 4250, 0
7396 18:05:29.077518 112 : 4361, 0
7397 18:05:29.077625 116 : 4250, 0
7398 18:05:29.080453 120 : 4250, 0
7399 18:05:29.080561 124 : 4250, 0
7400 18:05:29.080656 128 : 4249, 0
7401 18:05:29.084092 132 : 4250, 0
7402 18:05:29.084199 136 : 4250, 0
7403 18:05:29.084303 140 : 4249, 0
7404 18:05:29.087234 144 : 4250, 0
7405 18:05:29.087340 148 : 4250, 0
7406 18:05:29.090915 152 : 4363, 0
7407 18:05:29.091033 156 : 4250, 0
7408 18:05:29.091132 160 : 4361, 0
7409 18:05:29.093741 164 : 4250, 0
7410 18:05:29.093851 168 : 4250, 0
7411 18:05:29.097211 172 : 4250, 0
7412 18:05:29.097322 176 : 4250, 0
7413 18:05:29.097429 180 : 4250, 0
7414 18:05:29.100810 184 : 4250, 0
7415 18:05:29.100919 188 : 4253, 0
7416 18:05:29.103974 192 : 4249, 0
7417 18:05:29.104085 196 : 4250, 0
7418 18:05:29.104180 200 : 4250, 0
7419 18:05:29.107749 204 : 4360, 1315
7420 18:05:29.107859 208 : 4250, 3973
7421 18:05:29.110536 212 : 4253, 4029
7422 18:05:29.110643 216 : 4250, 4027
7423 18:05:29.114402 220 : 4250, 4027
7424 18:05:29.114513 224 : 4361, 4137
7425 18:05:29.117580 228 : 4250, 4027
7426 18:05:29.117695 232 : 4361, 4137
7427 18:05:29.117793 236 : 4250, 4027
7428 18:05:29.120473 240 : 4250, 4026
7429 18:05:29.120584 244 : 4250, 4027
7430 18:05:29.124305 248 : 4250, 4027
7431 18:05:29.124430 252 : 4255, 4029
7432 18:05:29.127199 256 : 4360, 4137
7433 18:05:29.127308 260 : 4250, 4026
7434 18:05:29.130929 264 : 4250, 4027
7435 18:05:29.131039 268 : 4252, 4027
7436 18:05:29.133815 272 : 4250, 4027
7437 18:05:29.133921 276 : 4361, 4137
7438 18:05:29.137637 280 : 4250, 4026
7439 18:05:29.137745 284 : 4361, 4138
7440 18:05:29.140763 288 : 4250, 4027
7441 18:05:29.140872 292 : 4250, 4026
7442 18:05:29.140973 296 : 4250, 4027
7443 18:05:29.144399 300 : 4250, 4027
7444 18:05:29.144507 304 : 4250, 4027
7445 18:05:29.147419 308 : 4361, 4116
7446 18:05:29.147521 312 : 4250, 2196
7447 18:05:29.150409 316 : 4361, 14
7448 18:05:29.150522
7449 18:05:29.150619 MIOCK jitter meter ch=0
7450 18:05:29.154151
7451 18:05:29.154268 1T = (316-88) = 228 dly cells
7452 18:05:29.160963 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7453 18:05:29.161069 ==
7454 18:05:29.163741 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 18:05:29.167512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7456 18:05:29.167627 ==
7457 18:05:29.173485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7458 18:05:29.177148 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7459 18:05:29.183546 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7460 18:05:29.186868 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7461 18:05:29.197375 [CA 0] Center 42 (12~73) winsize 62
7462 18:05:29.200473 [CA 1] Center 42 (12~73) winsize 62
7463 18:05:29.203673 [CA 2] Center 38 (8~68) winsize 61
7464 18:05:29.207556 [CA 3] Center 37 (8~67) winsize 60
7465 18:05:29.210531 [CA 4] Center 36 (6~66) winsize 61
7466 18:05:29.213951 [CA 5] Center 35 (6~64) winsize 59
7467 18:05:29.214034
7468 18:05:29.216938 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7469 18:05:29.217030
7470 18:05:29.220329 [CATrainingPosCal] consider 1 rank data
7471 18:05:29.223961 u2DelayCellTimex100 = 285/100 ps
7472 18:05:29.227286 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7473 18:05:29.233483 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7474 18:05:29.236887 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7475 18:05:29.240488 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7476 18:05:29.243399 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7477 18:05:29.247227 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7478 18:05:29.247338
7479 18:05:29.250372 CA PerBit enable=1, Macro0, CA PI delay=35
7480 18:05:29.250482
7481 18:05:29.254010 [CBTSetCACLKResult] CA Dly = 35
7482 18:05:29.257227 CS Dly: 9 (0~40)
7483 18:05:29.260202 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7484 18:05:29.264008 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7485 18:05:29.264116 ==
7486 18:05:29.267053 Dram Type= 6, Freq= 0, CH_0, rank 1
7487 18:05:29.270044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7488 18:05:29.273952 ==
7489 18:05:29.276958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7490 18:05:29.279980 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7491 18:05:29.286907 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7492 18:05:29.289801 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7493 18:05:29.300662 [CA 0] Center 43 (13~73) winsize 61
7494 18:05:29.304324 [CA 1] Center 43 (13~73) winsize 61
7495 18:05:29.307329 [CA 2] Center 38 (8~68) winsize 61
7496 18:05:29.310532 [CA 3] Center 38 (8~68) winsize 61
7497 18:05:29.314122 [CA 4] Center 36 (6~66) winsize 61
7498 18:05:29.317056 [CA 5] Center 35 (6~65) winsize 60
7499 18:05:29.317164
7500 18:05:29.320578 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7501 18:05:29.320658
7502 18:05:29.324003 [CATrainingPosCal] consider 2 rank data
7503 18:05:29.326949 u2DelayCellTimex100 = 285/100 ps
7504 18:05:29.330342 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7505 18:05:29.337101 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7506 18:05:29.340128 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7507 18:05:29.343864 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7508 18:05:29.346722 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7509 18:05:29.350273 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7510 18:05:29.350379
7511 18:05:29.353717 CA PerBit enable=1, Macro0, CA PI delay=35
7512 18:05:29.353830
7513 18:05:29.356951 [CBTSetCACLKResult] CA Dly = 35
7514 18:05:29.360031 CS Dly: 10 (0~42)
7515 18:05:29.363858 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7516 18:05:29.367014 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7517 18:05:29.367130
7518 18:05:29.370543 ----->DramcWriteLeveling(PI) begin...
7519 18:05:29.370652 ==
7520 18:05:29.373794 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 18:05:29.380002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 18:05:29.380116 ==
7523 18:05:29.383868 Write leveling (Byte 0): 38 => 38
7524 18:05:29.383975 Write leveling (Byte 1): 28 => 28
7525 18:05:29.386705 DramcWriteLeveling(PI) end<-----
7526 18:05:29.386788
7527 18:05:29.390417 ==
7528 18:05:29.390521 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 18:05:29.397092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 18:05:29.397206 ==
7531 18:05:29.400066 [Gating] SW mode calibration
7532 18:05:29.406860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7533 18:05:29.410321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7534 18:05:29.416442 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7535 18:05:29.420082 1 4 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7536 18:05:29.423208 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7537 18:05:29.429729 1 4 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
7538 18:05:29.433493 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7539 18:05:29.436510 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 18:05:29.443386 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7541 18:05:29.446493 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7542 18:05:29.450303 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7543 18:05:29.456382 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7544 18:05:29.459992 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7545 18:05:29.462912 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7546 18:05:29.469533 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 1)
7547 18:05:29.472909 1 5 20 | B1->B0 | 2525 2928 | 0 1 | (0 0) (0 0)
7548 18:05:29.476234 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (1 0) (0 0)
7549 18:05:29.479455 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7550 18:05:29.486485 1 6 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7551 18:05:29.489831 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7552 18:05:29.493087 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7553 18:05:29.499751 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7554 18:05:29.503023 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7555 18:05:29.506417 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7556 18:05:29.512797 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 18:05:29.516582 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 18:05:29.519260 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 18:05:29.526011 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 18:05:29.529748 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7561 18:05:29.532654 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7562 18:05:29.539590 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7563 18:05:29.542483 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 18:05:29.546165 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 18:05:29.552196 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 18:05:29.555889 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 18:05:29.559178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 18:05:29.565740 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 18:05:29.568675 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 18:05:29.572204 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 18:05:29.578576 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 18:05:29.582311 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 18:05:29.585309 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 18:05:29.592302 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 18:05:29.595691 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 18:05:29.598722 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7577 18:05:29.605357 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7578 18:05:29.609002 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7579 18:05:29.611761 Total UI for P1: 0, mck2ui 16
7580 18:05:29.615328 best dqsien dly found for B0: ( 1, 9, 10)
7581 18:05:29.651547 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 18:05:29.651688 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 18:05:29.651788 Total UI for P1: 0, mck2ui 16
7584 18:05:29.651883 best dqsien dly found for B1: ( 1, 9, 18)
7585 18:05:29.651973 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7586 18:05:29.652063 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7587 18:05:29.652149
7588 18:05:29.652235 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7589 18:05:29.652324 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7590 18:05:29.652397 [Gating] SW calibration Done
7591 18:05:29.652455 ==
7592 18:05:29.652741 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 18:05:29.655265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 18:05:29.655376 ==
7595 18:05:29.658201 RX Vref Scan: 0
7596 18:05:29.658307
7597 18:05:29.658399 RX Vref 0 -> 0, step: 1
7598 18:05:29.661622
7599 18:05:29.661737 RX Delay 0 -> 252, step: 8
7600 18:05:29.664542 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7601 18:05:29.671307 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7602 18:05:29.675119 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7603 18:05:29.678463 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7604 18:05:29.681389 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7605 18:05:29.684877 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7606 18:05:29.691621 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7607 18:05:29.694558 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7608 18:05:29.698181 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7609 18:05:29.701626 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7610 18:05:29.704564 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7611 18:05:29.711144 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7612 18:05:29.714709 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7613 18:05:29.717654 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7614 18:05:29.721292 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7615 18:05:29.727883 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7616 18:05:29.728002 ==
7617 18:05:29.731409 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 18:05:29.734300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 18:05:29.734404 ==
7620 18:05:29.734495 DQS Delay:
7621 18:05:29.737906 DQS0 = 0, DQS1 = 0
7622 18:05:29.738006 DQM Delay:
7623 18:05:29.741210 DQM0 = 137, DQM1 = 129
7624 18:05:29.741319 DQ Delay:
7625 18:05:29.744580 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7626 18:05:29.747369 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7627 18:05:29.751024 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7628 18:05:29.754804 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7629 18:05:29.754916
7630 18:05:29.755009
7631 18:05:29.757673 ==
7632 18:05:29.761035 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 18:05:29.764204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 18:05:29.764307 ==
7635 18:05:29.764410
7636 18:05:29.764497
7637 18:05:29.767177 TX Vref Scan disable
7638 18:05:29.767274 == TX Byte 0 ==
7639 18:05:29.773999 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7640 18:05:29.777613 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7641 18:05:29.777703 == TX Byte 1 ==
7642 18:05:29.784239 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7643 18:05:29.787416 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7644 18:05:29.787509 ==
7645 18:05:29.790965 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 18:05:29.794211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 18:05:29.794296 ==
7648 18:05:29.808297
7649 18:05:29.811437 TX Vref early break, caculate TX vref
7650 18:05:29.814807 TX Vref=16, minBit 3, minWin=22, winSum=377
7651 18:05:29.818465 TX Vref=18, minBit 0, minWin=23, winSum=387
7652 18:05:29.821782 TX Vref=20, minBit 0, minWin=23, winSum=395
7653 18:05:29.824781 TX Vref=22, minBit 4, minWin=24, winSum=406
7654 18:05:29.828415 TX Vref=24, minBit 2, minWin=24, winSum=414
7655 18:05:29.834954 TX Vref=26, minBit 0, minWin=25, winSum=417
7656 18:05:29.837810 TX Vref=28, minBit 0, minWin=25, winSum=422
7657 18:05:29.841550 TX Vref=30, minBit 6, minWin=24, winSum=411
7658 18:05:29.844646 TX Vref=32, minBit 6, minWin=24, winSum=405
7659 18:05:29.848024 TX Vref=34, minBit 1, minWin=23, winSum=390
7660 18:05:29.855094 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
7661 18:05:29.855186
7662 18:05:29.857865 Final TX Range 0 Vref 28
7663 18:05:29.857947
7664 18:05:29.858032 ==
7665 18:05:29.861751 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 18:05:29.864501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 18:05:29.864587 ==
7668 18:05:29.864673
7669 18:05:29.864753
7670 18:05:29.868135 TX Vref Scan disable
7671 18:05:29.874611 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7672 18:05:29.874701 == TX Byte 0 ==
7673 18:05:29.878319 u2DelayCellOfst[0]=13 cells (4 PI)
7674 18:05:29.882046 u2DelayCellOfst[1]=17 cells (5 PI)
7675 18:05:29.884969 u2DelayCellOfst[2]=13 cells (4 PI)
7676 18:05:29.888511 u2DelayCellOfst[3]=10 cells (3 PI)
7677 18:05:29.891145 u2DelayCellOfst[4]=10 cells (3 PI)
7678 18:05:29.894972 u2DelayCellOfst[5]=0 cells (0 PI)
7679 18:05:29.898315 u2DelayCellOfst[6]=17 cells (5 PI)
7680 18:05:29.901090 u2DelayCellOfst[7]=17 cells (5 PI)
7681 18:05:29.904663 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7682 18:05:29.907950 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7683 18:05:29.911276 == TX Byte 1 ==
7684 18:05:29.911384 u2DelayCellOfst[8]=0 cells (0 PI)
7685 18:05:29.914667 u2DelayCellOfst[9]=3 cells (1 PI)
7686 18:05:29.917775 u2DelayCellOfst[10]=10 cells (3 PI)
7687 18:05:29.921229 u2DelayCellOfst[11]=6 cells (2 PI)
7688 18:05:29.924015 u2DelayCellOfst[12]=13 cells (4 PI)
7689 18:05:29.927431 u2DelayCellOfst[13]=13 cells (4 PI)
7690 18:05:29.931013 u2DelayCellOfst[14]=13 cells (4 PI)
7691 18:05:29.934109 u2DelayCellOfst[15]=10 cells (3 PI)
7692 18:05:29.937536 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7693 18:05:29.944545 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7694 18:05:29.944646 DramC Write-DBI on
7695 18:05:29.944730 ==
7696 18:05:29.947843 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 18:05:29.954426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 18:05:29.954506 ==
7699 18:05:29.954575
7700 18:05:29.954657
7701 18:05:29.954736 TX Vref Scan disable
7702 18:05:29.958088 == TX Byte 0 ==
7703 18:05:29.961028 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7704 18:05:29.964529 == TX Byte 1 ==
7705 18:05:29.968121 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7706 18:05:29.971056 DramC Write-DBI off
7707 18:05:29.971138
7708 18:05:29.971203 [DATLAT]
7709 18:05:29.971263 Freq=1600, CH0 RK0
7710 18:05:29.971340
7711 18:05:29.974685 DATLAT Default: 0xf
7712 18:05:29.974767 0, 0xFFFF, sum = 0
7713 18:05:29.977531 1, 0xFFFF, sum = 0
7714 18:05:29.981002 2, 0xFFFF, sum = 0
7715 18:05:29.981088 3, 0xFFFF, sum = 0
7716 18:05:29.984634 4, 0xFFFF, sum = 0
7717 18:05:29.984727 5, 0xFFFF, sum = 0
7718 18:05:29.987532 6, 0xFFFF, sum = 0
7719 18:05:29.987616 7, 0xFFFF, sum = 0
7720 18:05:29.991003 8, 0xFFFF, sum = 0
7721 18:05:29.991087 9, 0xFFFF, sum = 0
7722 18:05:29.994544 10, 0xFFFF, sum = 0
7723 18:05:29.994629 11, 0xFFFF, sum = 0
7724 18:05:29.997347 12, 0xFFFF, sum = 0
7725 18:05:29.997430 13, 0xFFFF, sum = 0
7726 18:05:30.001054 14, 0x0, sum = 1
7727 18:05:30.001137 15, 0x0, sum = 2
7728 18:05:30.004575 16, 0x0, sum = 3
7729 18:05:30.004658 17, 0x0, sum = 4
7730 18:05:30.007506 best_step = 15
7731 18:05:30.007578
7732 18:05:30.007649 ==
7733 18:05:30.011217 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 18:05:30.014171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 18:05:30.014258 ==
7736 18:05:30.017890 RX Vref Scan: 1
7737 18:05:30.017969
7738 18:05:30.018052 Set Vref Range= 24 -> 127
7739 18:05:30.018132
7740 18:05:30.020659 RX Vref 24 -> 127, step: 1
7741 18:05:30.020742
7742 18:05:30.024292 RX Delay 19 -> 252, step: 4
7743 18:05:30.024394
7744 18:05:30.027479 Set Vref, RX VrefLevel [Byte0]: 24
7745 18:05:30.031009 [Byte1]: 24
7746 18:05:30.031094
7747 18:05:30.034001 Set Vref, RX VrefLevel [Byte0]: 25
7748 18:05:30.037514 [Byte1]: 25
7749 18:05:30.037629
7750 18:05:30.040676 Set Vref, RX VrefLevel [Byte0]: 26
7751 18:05:30.044084 [Byte1]: 26
7752 18:05:30.047959
7753 18:05:30.048042 Set Vref, RX VrefLevel [Byte0]: 27
7754 18:05:30.051650 [Byte1]: 27
7755 18:05:30.056026
7756 18:05:30.056135 Set Vref, RX VrefLevel [Byte0]: 28
7757 18:05:30.059429 [Byte1]: 28
7758 18:05:30.063282
7759 18:05:30.063417 Set Vref, RX VrefLevel [Byte0]: 29
7760 18:05:30.066641 [Byte1]: 29
7761 18:05:30.071046
7762 18:05:30.071216 Set Vref, RX VrefLevel [Byte0]: 30
7763 18:05:30.074078 [Byte1]: 30
7764 18:05:30.078777
7765 18:05:30.078901 Set Vref, RX VrefLevel [Byte0]: 31
7766 18:05:30.081866 [Byte1]: 31
7767 18:05:30.086364
7768 18:05:30.086487 Set Vref, RX VrefLevel [Byte0]: 32
7769 18:05:30.089192 [Byte1]: 32
7770 18:05:30.093360
7771 18:05:30.093466 Set Vref, RX VrefLevel [Byte0]: 33
7772 18:05:30.096922 [Byte1]: 33
7773 18:05:30.101016
7774 18:05:30.101114 Set Vref, RX VrefLevel [Byte0]: 34
7775 18:05:30.104526 [Byte1]: 34
7776 18:05:30.108849
7777 18:05:30.108950 Set Vref, RX VrefLevel [Byte0]: 35
7778 18:05:30.112300 [Byte1]: 35
7779 18:05:30.116086
7780 18:05:30.116185 Set Vref, RX VrefLevel [Byte0]: 36
7781 18:05:30.119858 [Byte1]: 36
7782 18:05:30.123958
7783 18:05:30.124059 Set Vref, RX VrefLevel [Byte0]: 37
7784 18:05:30.126911 [Byte1]: 37
7785 18:05:30.131408
7786 18:05:30.131497 Set Vref, RX VrefLevel [Byte0]: 38
7787 18:05:30.135075 [Byte1]: 38
7788 18:05:30.139292
7789 18:05:30.139409 Set Vref, RX VrefLevel [Byte0]: 39
7790 18:05:30.142141 [Byte1]: 39
7791 18:05:30.146485
7792 18:05:30.146569 Set Vref, RX VrefLevel [Byte0]: 40
7793 18:05:30.150219 [Byte1]: 40
7794 18:05:30.154509
7795 18:05:30.154609 Set Vref, RX VrefLevel [Byte0]: 41
7796 18:05:30.157977 [Byte1]: 41
7797 18:05:30.161538
7798 18:05:30.161665 Set Vref, RX VrefLevel [Byte0]: 42
7799 18:05:30.165099 [Byte1]: 42
7800 18:05:30.169422
7801 18:05:30.169528 Set Vref, RX VrefLevel [Byte0]: 43
7802 18:05:30.172763 [Byte1]: 43
7803 18:05:30.176866
7804 18:05:30.176970 Set Vref, RX VrefLevel [Byte0]: 44
7805 18:05:30.180228 [Byte1]: 44
7806 18:05:30.184321
7807 18:05:30.184447 Set Vref, RX VrefLevel [Byte0]: 45
7808 18:05:30.187492 [Byte1]: 45
7809 18:05:30.192207
7810 18:05:30.192317 Set Vref, RX VrefLevel [Byte0]: 46
7811 18:05:30.195108 [Byte1]: 46
7812 18:05:30.199676
7813 18:05:30.199760 Set Vref, RX VrefLevel [Byte0]: 47
7814 18:05:30.202693 [Byte1]: 47
7815 18:05:30.207083
7816 18:05:30.207206 Set Vref, RX VrefLevel [Byte0]: 48
7817 18:05:30.210443 [Byte1]: 48
7818 18:05:30.214592
7819 18:05:30.214677 Set Vref, RX VrefLevel [Byte0]: 49
7820 18:05:30.218079 [Byte1]: 49
7821 18:05:30.222487
7822 18:05:30.222572 Set Vref, RX VrefLevel [Byte0]: 50
7823 18:05:30.225810 [Byte1]: 50
7824 18:05:30.230206
7825 18:05:30.230291 Set Vref, RX VrefLevel [Byte0]: 51
7826 18:05:30.233182 [Byte1]: 51
7827 18:05:30.237456
7828 18:05:30.237542 Set Vref, RX VrefLevel [Byte0]: 52
7829 18:05:30.241050 [Byte1]: 52
7830 18:05:30.245370
7831 18:05:30.245457 Set Vref, RX VrefLevel [Byte0]: 53
7832 18:05:30.248282 [Byte1]: 53
7833 18:05:30.252484
7834 18:05:30.252624 Set Vref, RX VrefLevel [Byte0]: 54
7835 18:05:30.256100 [Byte1]: 54
7836 18:05:30.260329
7837 18:05:30.260474 Set Vref, RX VrefLevel [Byte0]: 55
7838 18:05:30.263455 [Byte1]: 55
7839 18:05:30.267825
7840 18:05:30.267929 Set Vref, RX VrefLevel [Byte0]: 56
7841 18:05:30.271368 [Byte1]: 56
7842 18:05:30.275038
7843 18:05:30.275137 Set Vref, RX VrefLevel [Byte0]: 57
7844 18:05:30.278594 [Byte1]: 57
7845 18:05:30.282740
7846 18:05:30.282869 Set Vref, RX VrefLevel [Byte0]: 58
7847 18:05:30.285992 [Byte1]: 58
7848 18:05:30.290255
7849 18:05:30.290334 Set Vref, RX VrefLevel [Byte0]: 59
7850 18:05:30.293991 [Byte1]: 59
7851 18:05:30.298078
7852 18:05:30.298190 Set Vref, RX VrefLevel [Byte0]: 60
7853 18:05:30.300979 [Byte1]: 60
7854 18:05:30.305510
7855 18:05:30.305637 Set Vref, RX VrefLevel [Byte0]: 61
7856 18:05:30.309221 [Byte1]: 61
7857 18:05:30.313787
7858 18:05:30.313903 Set Vref, RX VrefLevel [Byte0]: 62
7859 18:05:30.316755 [Byte1]: 62
7860 18:05:30.321050
7861 18:05:30.321158 Set Vref, RX VrefLevel [Byte0]: 63
7862 18:05:30.323819 [Byte1]: 63
7863 18:05:30.328651
7864 18:05:30.328763 Set Vref, RX VrefLevel [Byte0]: 64
7865 18:05:30.331858 [Byte1]: 64
7866 18:05:30.335878
7867 18:05:30.335963 Set Vref, RX VrefLevel [Byte0]: 65
7868 18:05:30.339009 [Byte1]: 65
7869 18:05:30.343751
7870 18:05:30.343838 Set Vref, RX VrefLevel [Byte0]: 66
7871 18:05:30.346829 [Byte1]: 66
7872 18:05:30.350976
7873 18:05:30.351060 Set Vref, RX VrefLevel [Byte0]: 67
7874 18:05:30.354370 [Byte1]: 67
7875 18:05:30.358957
7876 18:05:30.359069 Set Vref, RX VrefLevel [Byte0]: 68
7877 18:05:30.361700 [Byte1]: 68
7878 18:05:30.366665
7879 18:05:30.366783 Set Vref, RX VrefLevel [Byte0]: 69
7880 18:05:30.369603 [Byte1]: 69
7881 18:05:30.374098
7882 18:05:30.374182 Set Vref, RX VrefLevel [Byte0]: 70
7883 18:05:30.377035 [Byte1]: 70
7884 18:05:30.381524
7885 18:05:30.381632 Set Vref, RX VrefLevel [Byte0]: 71
7886 18:05:30.384553 [Byte1]: 71
7887 18:05:30.388975
7888 18:05:30.389062 Set Vref, RX VrefLevel [Byte0]: 72
7889 18:05:30.392677 [Byte1]: 72
7890 18:05:30.396895
7891 18:05:30.397001 Set Vref, RX VrefLevel [Byte0]: 73
7892 18:05:30.399628 [Byte1]: 73
7893 18:05:30.404402
7894 18:05:30.404492 Set Vref, RX VrefLevel [Byte0]: 74
7895 18:05:30.407501 [Byte1]: 74
7896 18:05:30.411971
7897 18:05:30.412058 Set Vref, RX VrefLevel [Byte0]: 75
7898 18:05:30.415244 [Byte1]: 75
7899 18:05:30.419548
7900 18:05:30.419638 Set Vref, RX VrefLevel [Byte0]: 76
7901 18:05:30.422407 [Byte1]: 76
7902 18:05:30.427003
7903 18:05:30.427087 Final RX Vref Byte 0 = 58 to rank0
7904 18:05:30.429974 Final RX Vref Byte 1 = 59 to rank0
7905 18:05:30.433244 Final RX Vref Byte 0 = 58 to rank1
7906 18:05:30.436719 Final RX Vref Byte 1 = 59 to rank1==
7907 18:05:30.440597 Dram Type= 6, Freq= 0, CH_0, rank 0
7908 18:05:30.446804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7909 18:05:30.446902 ==
7910 18:05:30.446970 DQS Delay:
7911 18:05:30.447033 DQS0 = 0, DQS1 = 0
7912 18:05:30.450402 DQM Delay:
7913 18:05:30.450486 DQM0 = 134, DQM1 = 127
7914 18:05:30.453019 DQ Delay:
7915 18:05:30.456915 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7916 18:05:30.460111 DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =140
7917 18:05:30.463051 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7918 18:05:30.466487 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =134
7919 18:05:30.466562
7920 18:05:30.466624
7921 18:05:30.466690
7922 18:05:30.469968 [DramC_TX_OE_Calibration] TA2
7923 18:05:30.473383 Original DQ_B0 (3 6) =30, OEN = 27
7924 18:05:30.476838 Original DQ_B1 (3 6) =30, OEN = 27
7925 18:05:30.479672 24, 0x0, End_B0=24 End_B1=24
7926 18:05:30.479759 25, 0x0, End_B0=25 End_B1=25
7927 18:05:30.483287 26, 0x0, End_B0=26 End_B1=26
7928 18:05:30.486833 27, 0x0, End_B0=27 End_B1=27
7929 18:05:30.489634 28, 0x0, End_B0=28 End_B1=28
7930 18:05:30.493347 29, 0x0, End_B0=29 End_B1=29
7931 18:05:30.493422 30, 0x0, End_B0=30 End_B1=30
7932 18:05:30.496195 31, 0x4141, End_B0=30 End_B1=30
7933 18:05:30.499819 Byte0 end_step=30 best_step=27
7934 18:05:30.503484 Byte1 end_step=30 best_step=27
7935 18:05:30.506646 Byte0 TX OE(2T, 0.5T) = (3, 3)
7936 18:05:30.506720 Byte1 TX OE(2T, 0.5T) = (3, 3)
7937 18:05:30.510100
7938 18:05:30.510176
7939 18:05:30.516708 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7940 18:05:30.519600 CH0 RK0: MR19=303, MR18=221E
7941 18:05:30.526793 CH0_RK0: MR19=0x303, MR18=0x221E, DQSOSC=392, MR23=63, INC=24, DEC=16
7942 18:05:30.526874
7943 18:05:30.529660 ----->DramcWriteLeveling(PI) begin...
7944 18:05:30.529736 ==
7945 18:05:30.533315 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 18:05:30.536196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 18:05:30.536298 ==
7948 18:05:30.540148 Write leveling (Byte 0): 37 => 37
7949 18:05:30.543089 Write leveling (Byte 1): 29 => 29
7950 18:05:30.546100 DramcWriteLeveling(PI) end<-----
7951 18:05:30.546220
7952 18:05:30.546316 ==
7953 18:05:30.549753 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 18:05:30.552731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 18:05:30.552858 ==
7956 18:05:30.556331 [Gating] SW mode calibration
7957 18:05:30.562712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7958 18:05:30.569813 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7959 18:05:30.572643 1 4 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7960 18:05:30.576132 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7961 18:05:30.582390 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7962 18:05:30.585848 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7963 18:05:30.589689 1 4 16 | B1->B0 | 2e2e 3837 | 1 1 | (1 1) (1 1)
7964 18:05:30.596012 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7965 18:05:30.599253 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7966 18:05:30.602821 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7967 18:05:30.609442 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7968 18:05:30.612917 1 5 4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7969 18:05:30.615896 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7970 18:05:30.622783 1 5 12 | B1->B0 | 3434 3635 | 1 1 | (1 0) (1 0)
7971 18:05:30.625773 1 5 16 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
7972 18:05:30.629189 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7973 18:05:30.635626 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7974 18:05:30.639418 1 5 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7975 18:05:30.642333 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7976 18:05:30.649344 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7977 18:05:30.652469 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7978 18:05:30.655505 1 6 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7979 18:05:30.662900 1 6 16 | B1->B0 | 3838 4544 | 0 1 | (0 0) (0 0)
7980 18:05:30.665967 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 18:05:30.669328 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7982 18:05:30.675711 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 18:05:30.679027 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 18:05:30.682552 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 18:05:30.688957 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 18:05:30.692404 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7987 18:05:30.695453 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
7988 18:05:30.702140 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
7989 18:05:30.705467 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 18:05:30.709181 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 18:05:30.712542 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 18:05:30.718597 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 18:05:30.722078 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 18:05:30.725532 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 18:05:30.732007 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 18:05:30.735492 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 18:05:30.739012 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 18:05:30.745781 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 18:05:30.748627 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 18:05:30.751902 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 18:05:30.759253 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8002 18:05:30.762452 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8003 18:05:30.765132 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8004 18:05:30.771762 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 18:05:30.775440 Total UI for P1: 0, mck2ui 16
8006 18:05:30.779006 best dqsien dly found for B0: ( 1, 9, 12)
8007 18:05:30.779090 Total UI for P1: 0, mck2ui 16
8008 18:05:30.785025 best dqsien dly found for B1: ( 1, 9, 14)
8009 18:05:30.788670 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8010 18:05:30.792095 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8011 18:05:30.792172
8012 18:05:30.795742 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8013 18:05:30.798532 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8014 18:05:30.802154 [Gating] SW calibration Done
8015 18:05:30.802237 ==
8016 18:05:30.805146 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 18:05:30.808894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 18:05:30.808999 ==
8019 18:05:30.811777 RX Vref Scan: 0
8020 18:05:30.811892
8021 18:05:30.812009 RX Vref 0 -> 0, step: 1
8022 18:05:30.812124
8023 18:05:30.815343 RX Delay 0 -> 252, step: 8
8024 18:05:30.818684 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8025 18:05:30.824809 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8026 18:05:30.828803 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8027 18:05:30.831693 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8028 18:05:30.835047 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8029 18:05:30.838217 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8030 18:05:30.844946 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8031 18:05:30.848336 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8032 18:05:30.851670 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8033 18:05:30.855086 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8034 18:05:30.858222 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8035 18:05:30.864887 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8036 18:05:30.868565 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8037 18:05:30.871594 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8038 18:05:30.875237 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8039 18:05:30.878235 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8040 18:05:30.881965 ==
8041 18:05:30.882049 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 18:05:30.888612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 18:05:30.888695 ==
8044 18:05:30.888758 DQS Delay:
8045 18:05:30.892278 DQS0 = 0, DQS1 = 0
8046 18:05:30.892411 DQM Delay:
8047 18:05:30.894992 DQM0 = 136, DQM1 = 128
8048 18:05:30.895065 DQ Delay:
8049 18:05:30.898614 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8050 18:05:30.902312 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8051 18:05:30.905092 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8052 18:05:30.908976 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8053 18:05:30.909084
8054 18:05:30.909181
8055 18:05:30.909269 ==
8056 18:05:30.911729 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 18:05:30.918324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 18:05:30.918438 ==
8059 18:05:30.918513
8060 18:05:30.918574
8061 18:05:30.918637 TX Vref Scan disable
8062 18:05:30.921982 == TX Byte 0 ==
8063 18:05:30.925720 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8064 18:05:30.928690 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8065 18:05:30.932230 == TX Byte 1 ==
8066 18:05:30.935168 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8067 18:05:30.941767 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8068 18:05:30.941876 ==
8069 18:05:30.945459 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 18:05:30.948923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 18:05:30.949011 ==
8072 18:05:30.961647
8073 18:05:30.964941 TX Vref early break, caculate TX vref
8074 18:05:30.968241 TX Vref=16, minBit 1, minWin=23, winSum=390
8075 18:05:30.971709 TX Vref=18, minBit 1, minWin=23, winSum=395
8076 18:05:30.974801 TX Vref=20, minBit 1, minWin=23, winSum=404
8077 18:05:30.978257 TX Vref=22, minBit 1, minWin=24, winSum=410
8078 18:05:30.981599 TX Vref=24, minBit 1, minWin=25, winSum=415
8079 18:05:30.988113 TX Vref=26, minBit 1, minWin=25, winSum=427
8080 18:05:30.991694 TX Vref=28, minBit 4, minWin=25, winSum=423
8081 18:05:30.994616 TX Vref=30, minBit 4, minWin=24, winSum=418
8082 18:05:30.998457 TX Vref=32, minBit 4, minWin=24, winSum=413
8083 18:05:31.001311 TX Vref=34, minBit 0, minWin=24, winSum=404
8084 18:05:31.008321 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
8085 18:05:31.008412
8086 18:05:31.011961 Final TX Range 0 Vref 26
8087 18:05:31.012065
8088 18:05:31.012161 ==
8089 18:05:31.014769 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 18:05:31.018532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 18:05:31.018645 ==
8092 18:05:31.018756
8093 18:05:31.018850
8094 18:05:31.021499 TX Vref Scan disable
8095 18:05:31.027997 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8096 18:05:31.028128 == TX Byte 0 ==
8097 18:05:31.031645 u2DelayCellOfst[0]=13 cells (4 PI)
8098 18:05:31.034627 u2DelayCellOfst[1]=17 cells (5 PI)
8099 18:05:31.038495 u2DelayCellOfst[2]=13 cells (4 PI)
8100 18:05:31.041271 u2DelayCellOfst[3]=10 cells (3 PI)
8101 18:05:31.045100 u2DelayCellOfst[4]=10 cells (3 PI)
8102 18:05:31.048097 u2DelayCellOfst[5]=0 cells (0 PI)
8103 18:05:31.051803 u2DelayCellOfst[6]=17 cells (5 PI)
8104 18:05:31.054741 u2DelayCellOfst[7]=17 cells (5 PI)
8105 18:05:31.058448 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8106 18:05:31.061062 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8107 18:05:31.064653 == TX Byte 1 ==
8108 18:05:31.064730 u2DelayCellOfst[8]=0 cells (0 PI)
8109 18:05:31.068248 u2DelayCellOfst[9]=0 cells (0 PI)
8110 18:05:31.071268 u2DelayCellOfst[10]=3 cells (1 PI)
8111 18:05:31.074840 u2DelayCellOfst[11]=0 cells (0 PI)
8112 18:05:31.078269 u2DelayCellOfst[12]=6 cells (2 PI)
8113 18:05:31.081012 u2DelayCellOfst[13]=6 cells (2 PI)
8114 18:05:31.084318 u2DelayCellOfst[14]=13 cells (4 PI)
8115 18:05:31.087665 u2DelayCellOfst[15]=6 cells (2 PI)
8116 18:05:31.091041 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8117 18:05:31.097775 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8118 18:05:31.097860 DramC Write-DBI on
8119 18:05:31.097931 ==
8120 18:05:31.101052 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 18:05:31.104770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 18:05:31.104851 ==
8123 18:05:31.107775
8124 18:05:31.107877
8125 18:05:31.107972 TX Vref Scan disable
8126 18:05:31.110864 == TX Byte 0 ==
8127 18:05:31.114517 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8128 18:05:31.117442 == TX Byte 1 ==
8129 18:05:31.121007 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8130 18:05:31.124874 DramC Write-DBI off
8131 18:05:31.124951
8132 18:05:31.125017 [DATLAT]
8133 18:05:31.125076 Freq=1600, CH0 RK1
8134 18:05:31.125136
8135 18:05:31.127694 DATLAT Default: 0xf
8136 18:05:31.127765 0, 0xFFFF, sum = 0
8137 18:05:31.131179 1, 0xFFFF, sum = 0
8138 18:05:31.134102 2, 0xFFFF, sum = 0
8139 18:05:31.134185 3, 0xFFFF, sum = 0
8140 18:05:31.137397 4, 0xFFFF, sum = 0
8141 18:05:31.137476 5, 0xFFFF, sum = 0
8142 18:05:31.141272 6, 0xFFFF, sum = 0
8143 18:05:31.141358 7, 0xFFFF, sum = 0
8144 18:05:31.144068 8, 0xFFFF, sum = 0
8145 18:05:31.144178 9, 0xFFFF, sum = 0
8146 18:05:31.147626 10, 0xFFFF, sum = 0
8147 18:05:31.147732 11, 0xFFFF, sum = 0
8148 18:05:31.150592 12, 0xFFFF, sum = 0
8149 18:05:31.150699 13, 0xFFFF, sum = 0
8150 18:05:31.154261 14, 0x0, sum = 1
8151 18:05:31.154338 15, 0x0, sum = 2
8152 18:05:31.157211 16, 0x0, sum = 3
8153 18:05:31.157287 17, 0x0, sum = 4
8154 18:05:31.160923 best_step = 15
8155 18:05:31.160997
8156 18:05:31.161064 ==
8157 18:05:31.163802 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 18:05:31.167374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 18:05:31.167458 ==
8160 18:05:31.170812 RX Vref Scan: 0
8161 18:05:31.170891
8162 18:05:31.170954 RX Vref 0 -> 0, step: 1
8163 18:05:31.171015
8164 18:05:31.173801 RX Delay 19 -> 252, step: 4
8165 18:05:31.180593 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8166 18:05:31.183609 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8167 18:05:31.187213 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8168 18:05:31.190871 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8169 18:05:31.193473 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8170 18:05:31.197350 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8171 18:05:31.203859 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8172 18:05:31.207330 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8173 18:05:31.210082 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8174 18:05:31.213216 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8175 18:05:31.217042 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8176 18:05:31.223620 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 18:05:31.226578 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8178 18:05:31.230279 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8179 18:05:31.233322 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8180 18:05:31.240167 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8181 18:05:31.240294 ==
8182 18:05:31.243770 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 18:05:31.246649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 18:05:31.246760 ==
8185 18:05:31.246867 DQS Delay:
8186 18:05:31.250040 DQS0 = 0, DQS1 = 0
8187 18:05:31.250146 DQM Delay:
8188 18:05:31.253719 DQM0 = 134, DQM1 = 127
8189 18:05:31.253820 DQ Delay:
8190 18:05:31.256695 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8191 18:05:31.260670 DQ4 =134, DQ5 =126, DQ6 =140, DQ7 =140
8192 18:05:31.263544 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8193 18:05:31.266496 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8194 18:05:31.266609
8195 18:05:31.266688
8196 18:05:31.270244
8197 18:05:31.270352 [DramC_TX_OE_Calibration] TA2
8198 18:05:31.273289 Original DQ_B0 (3 6) =30, OEN = 27
8199 18:05:31.276326 Original DQ_B1 (3 6) =30, OEN = 27
8200 18:05:31.280213 24, 0x0, End_B0=24 End_B1=24
8201 18:05:31.283111 25, 0x0, End_B0=25 End_B1=25
8202 18:05:31.286901 26, 0x0, End_B0=26 End_B1=26
8203 18:05:31.286986 27, 0x0, End_B0=27 End_B1=27
8204 18:05:31.290050 28, 0x0, End_B0=28 End_B1=28
8205 18:05:31.293612 29, 0x0, End_B0=29 End_B1=29
8206 18:05:31.296716 30, 0x0, End_B0=30 End_B1=30
8207 18:05:31.296802 31, 0x5151, End_B0=30 End_B1=30
8208 18:05:31.300306 Byte0 end_step=30 best_step=27
8209 18:05:31.303389 Byte1 end_step=30 best_step=27
8210 18:05:31.307187 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 18:05:31.310005 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 18:05:31.310080
8213 18:05:31.310142
8214 18:05:31.316938 [DQSOSCAuto] RK1, (LSB)MR18= 0x220b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8215 18:05:31.319903 CH0 RK1: MR19=303, MR18=220B
8216 18:05:31.326851 CH0_RK1: MR19=0x303, MR18=0x220B, DQSOSC=392, MR23=63, INC=24, DEC=16
8217 18:05:31.329417 [RxdqsGatingPostProcess] freq 1600
8218 18:05:31.336149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 18:05:31.339560 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 18:05:31.339639 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 18:05:31.343037 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 18:05:31.346098 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 18:05:31.349654 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 18:05:31.353062 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 18:05:31.356686 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 18:05:31.359834 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 18:05:31.362967 Pre-setting of DQS Precalculation
8228 18:05:31.365981 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 18:05:31.369980 ==
8230 18:05:31.370058 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 18:05:31.376532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 18:05:31.376611 ==
8233 18:05:31.380013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 18:05:31.386602 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 18:05:31.389598 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 18:05:31.396268 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 18:05:31.404322 [CA 0] Center 42 (13~72) winsize 60
8238 18:05:31.407366 [CA 1] Center 42 (12~72) winsize 61
8239 18:05:31.411039 [CA 2] Center 38 (9~68) winsize 60
8240 18:05:31.413974 [CA 3] Center 38 (9~67) winsize 59
8241 18:05:31.417601 [CA 4] Center 38 (9~68) winsize 60
8242 18:05:31.420572 [CA 5] Center 37 (8~67) winsize 60
8243 18:05:31.420655
8244 18:05:31.423660 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 18:05:31.423772
8246 18:05:31.427274 [CATrainingPosCal] consider 1 rank data
8247 18:05:31.430300 u2DelayCellTimex100 = 285/100 ps
8248 18:05:31.437123 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8249 18:05:31.440129 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8250 18:05:31.443863 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8251 18:05:31.446836 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8252 18:05:31.450505 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 18:05:31.453685 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8254 18:05:31.453790
8255 18:05:31.457385 CA PerBit enable=1, Macro0, CA PI delay=37
8256 18:05:31.457488
8257 18:05:31.460375 [CBTSetCACLKResult] CA Dly = 37
8258 18:05:31.463863 CS Dly: 12 (0~43)
8259 18:05:31.467297 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 18:05:31.470364 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 18:05:31.470470 ==
8262 18:05:31.474179 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 18:05:31.477332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 18:05:31.480684 ==
8265 18:05:31.483468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 18:05:31.486598 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 18:05:31.493748 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 18:05:31.500183 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 18:05:31.507690 [CA 0] Center 42 (13~72) winsize 60
8270 18:05:31.510662 [CA 1] Center 43 (13~73) winsize 61
8271 18:05:31.513877 [CA 2] Center 39 (10~69) winsize 60
8272 18:05:31.517365 [CA 3] Center 38 (9~68) winsize 60
8273 18:05:31.520438 [CA 4] Center 39 (9~69) winsize 61
8274 18:05:31.524115 [CA 5] Center 37 (8~67) winsize 60
8275 18:05:31.524198
8276 18:05:31.527015 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 18:05:31.527116
8278 18:05:31.530700 [CATrainingPosCal] consider 2 rank data
8279 18:05:31.533769 u2DelayCellTimex100 = 285/100 ps
8280 18:05:31.540415 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8281 18:05:31.543499 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8282 18:05:31.547075 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8283 18:05:31.550247 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8284 18:05:31.553865 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 18:05:31.556905 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 18:05:31.557011
8287 18:05:31.559851 CA PerBit enable=1, Macro0, CA PI delay=37
8288 18:05:31.559952
8289 18:05:31.563641 [CBTSetCACLKResult] CA Dly = 37
8290 18:05:31.566619 CS Dly: 12 (0~44)
8291 18:05:31.570467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 18:05:31.573570 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 18:05:31.573672
8294 18:05:31.576501 ----->DramcWriteLeveling(PI) begin...
8295 18:05:31.576575 ==
8296 18:05:31.580274 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 18:05:31.587164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 18:05:31.587268 ==
8299 18:05:31.590114 Write leveling (Byte 0): 26 => 26
8300 18:05:31.590190 Write leveling (Byte 1): 27 => 27
8301 18:05:31.593337 DramcWriteLeveling(PI) end<-----
8302 18:05:31.593447
8303 18:05:31.596694 ==
8304 18:05:31.600243 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 18:05:31.603609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 18:05:31.603697 ==
8307 18:05:31.606416 [Gating] SW mode calibration
8308 18:05:31.613288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 18:05:31.616678 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 18:05:31.623281 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 18:05:31.626696 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 18:05:31.630035 1 4 8 | B1->B0 | 2424 2929 | 0 1 | (0 0) (1 1)
8313 18:05:31.636577 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8314 18:05:31.640091 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 18:05:31.643078 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 18:05:31.649803 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 18:05:31.653532 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 18:05:31.656570 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 18:05:31.663363 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 18:05:31.666326 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8321 18:05:31.670358 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8322 18:05:31.676277 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 18:05:31.680199 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 18:05:31.683101 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 18:05:31.689814 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 18:05:31.692946 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 18:05:31.696763 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 18:05:31.703276 1 6 8 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
8329 18:05:31.706610 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8330 18:05:31.710134 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 18:05:31.712867 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 18:05:31.719396 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 18:05:31.723035 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 18:05:31.726600 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 18:05:31.732979 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 18:05:31.736592 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8337 18:05:31.739547 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 18:05:31.745930 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 18:05:31.749534 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 18:05:31.752780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 18:05:31.760013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 18:05:31.762946 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 18:05:31.766526 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 18:05:31.772513 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 18:05:31.776416 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 18:05:31.779548 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 18:05:31.786310 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 18:05:31.789327 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 18:05:31.793262 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 18:05:31.799745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 18:05:31.802654 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 18:05:31.806515 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 18:05:31.813180 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 18:05:31.816101 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 18:05:31.819081 Total UI for P1: 0, mck2ui 16
8356 18:05:31.822861 best dqsien dly found for B0: ( 1, 9, 10)
8357 18:05:31.826196 Total UI for P1: 0, mck2ui 16
8358 18:05:31.829472 best dqsien dly found for B1: ( 1, 9, 10)
8359 18:05:31.832958 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8360 18:05:31.835703 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8361 18:05:31.835811
8362 18:05:31.839266 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8363 18:05:31.842515 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8364 18:05:31.845898 [Gating] SW calibration Done
8365 18:05:31.846013 ==
8366 18:05:31.849500 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 18:05:31.852532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 18:05:31.852610 ==
8369 18:05:31.856274 RX Vref Scan: 0
8370 18:05:31.856381
8371 18:05:31.859097 RX Vref 0 -> 0, step: 1
8372 18:05:31.859168
8373 18:05:31.859237 RX Delay 0 -> 252, step: 8
8374 18:05:31.865496 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8375 18:05:31.869129 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8376 18:05:31.872650 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8377 18:05:31.875363 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8378 18:05:31.878694 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8379 18:05:31.885854 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8380 18:05:31.888722 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8381 18:05:31.892226 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8382 18:05:31.895269 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8383 18:05:31.899101 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8384 18:05:31.905874 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8385 18:05:31.908894 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8386 18:05:31.912518 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8387 18:05:31.915504 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8388 18:05:31.919127 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8389 18:05:31.925760 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8390 18:05:31.925839 ==
8391 18:05:31.928680 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 18:05:31.932262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 18:05:31.932348 ==
8394 18:05:31.932415 DQS Delay:
8395 18:05:31.935719 DQS0 = 0, DQS1 = 0
8396 18:05:31.935792 DQM Delay:
8397 18:05:31.939117 DQM0 = 136, DQM1 = 133
8398 18:05:31.939233 DQ Delay:
8399 18:05:31.942321 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8400 18:05:31.945547 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8401 18:05:31.948919 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8402 18:05:31.951870 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8403 18:05:31.951972
8404 18:05:31.952072
8405 18:05:31.955318 ==
8406 18:05:31.958553 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 18:05:31.961725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 18:05:31.961831 ==
8409 18:05:31.961925
8410 18:05:31.962012
8411 18:05:31.965084 TX Vref Scan disable
8412 18:05:31.965192 == TX Byte 0 ==
8413 18:05:31.971708 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8414 18:05:31.975423 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8415 18:05:31.975530 == TX Byte 1 ==
8416 18:05:31.978443 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8417 18:05:31.984964 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8418 18:05:31.985070 ==
8419 18:05:31.988444 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 18:05:31.991779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 18:05:31.991884 ==
8422 18:05:32.006022
8423 18:05:32.009468 TX Vref early break, caculate TX vref
8424 18:05:32.012412 TX Vref=16, minBit 1, minWin=22, winSum=376
8425 18:05:32.016056 TX Vref=18, minBit 1, minWin=23, winSum=381
8426 18:05:32.019082 TX Vref=20, minBit 1, minWin=23, winSum=395
8427 18:05:32.022655 TX Vref=22, minBit 0, minWin=24, winSum=404
8428 18:05:32.025716 TX Vref=24, minBit 0, minWin=25, winSum=417
8429 18:05:32.032395 TX Vref=26, minBit 1, minWin=25, winSum=424
8430 18:05:32.035942 TX Vref=28, minBit 0, minWin=25, winSum=426
8431 18:05:32.038814 TX Vref=30, minBit 6, minWin=24, winSum=421
8432 18:05:32.042483 TX Vref=32, minBit 0, minWin=24, winSum=414
8433 18:05:32.045380 TX Vref=34, minBit 0, minWin=24, winSum=406
8434 18:05:32.049000 TX Vref=36, minBit 0, minWin=23, winSum=391
8435 18:05:32.055730 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8436 18:05:32.055808
8437 18:05:32.058908 Final TX Range 0 Vref 28
8438 18:05:32.059010
8439 18:05:32.059100 ==
8440 18:05:32.062257 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 18:05:32.065587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 18:05:32.065688 ==
8443 18:05:32.065780
8444 18:05:32.068802
8445 18:05:32.068880 TX Vref Scan disable
8446 18:05:32.075043 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8447 18:05:32.075145 == TX Byte 0 ==
8448 18:05:32.078343 u2DelayCellOfst[0]=13 cells (4 PI)
8449 18:05:32.082344 u2DelayCellOfst[1]=10 cells (3 PI)
8450 18:05:32.085341 u2DelayCellOfst[2]=0 cells (0 PI)
8451 18:05:32.088421 u2DelayCellOfst[3]=6 cells (2 PI)
8452 18:05:32.091958 u2DelayCellOfst[4]=6 cells (2 PI)
8453 18:05:32.095088 u2DelayCellOfst[5]=17 cells (5 PI)
8454 18:05:32.099007 u2DelayCellOfst[6]=17 cells (5 PI)
8455 18:05:32.101947 u2DelayCellOfst[7]=3 cells (1 PI)
8456 18:05:32.105635 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8457 18:05:32.108449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8458 18:05:32.112035 == TX Byte 1 ==
8459 18:05:32.115237 u2DelayCellOfst[8]=0 cells (0 PI)
8460 18:05:32.115368 u2DelayCellOfst[9]=6 cells (2 PI)
8461 18:05:32.118894 u2DelayCellOfst[10]=10 cells (3 PI)
8462 18:05:32.121701 u2DelayCellOfst[11]=3 cells (1 PI)
8463 18:05:32.124980 u2DelayCellOfst[12]=17 cells (5 PI)
8464 18:05:32.129084 u2DelayCellOfst[13]=17 cells (5 PI)
8465 18:05:32.132082 u2DelayCellOfst[14]=17 cells (5 PI)
8466 18:05:32.135122 u2DelayCellOfst[15]=17 cells (5 PI)
8467 18:05:32.138596 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8468 18:05:32.145185 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 18:05:32.145299 DramC Write-DBI on
8470 18:05:32.145405 ==
8471 18:05:32.148290 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 18:05:32.154950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 18:05:32.155058 ==
8474 18:05:32.155151
8475 18:05:32.155247
8476 18:05:32.155335 TX Vref Scan disable
8477 18:05:32.158593 == TX Byte 0 ==
8478 18:05:32.162296 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8479 18:05:32.165238 == TX Byte 1 ==
8480 18:05:32.168822 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8481 18:05:32.172056 DramC Write-DBI off
8482 18:05:32.172172
8483 18:05:32.172264 [DATLAT]
8484 18:05:32.172360 Freq=1600, CH1 RK0
8485 18:05:32.172428
8486 18:05:32.175339 DATLAT Default: 0xf
8487 18:05:32.175436 0, 0xFFFF, sum = 0
8488 18:05:32.178993 1, 0xFFFF, sum = 0
8489 18:05:32.181752 2, 0xFFFF, sum = 0
8490 18:05:32.181829 3, 0xFFFF, sum = 0
8491 18:05:32.185337 4, 0xFFFF, sum = 0
8492 18:05:32.185443 5, 0xFFFF, sum = 0
8493 18:05:32.188700 6, 0xFFFF, sum = 0
8494 18:05:32.188805 7, 0xFFFF, sum = 0
8495 18:05:32.192024 8, 0xFFFF, sum = 0
8496 18:05:32.192125 9, 0xFFFF, sum = 0
8497 18:05:32.195381 10, 0xFFFF, sum = 0
8498 18:05:32.195489 11, 0xFFFF, sum = 0
8499 18:05:32.198794 12, 0xFFFF, sum = 0
8500 18:05:32.198904 13, 0xFFFF, sum = 0
8501 18:05:32.201931 14, 0x0, sum = 1
8502 18:05:32.202040 15, 0x0, sum = 2
8503 18:05:32.205624 16, 0x0, sum = 3
8504 18:05:32.205733 17, 0x0, sum = 4
8505 18:05:32.208644 best_step = 15
8506 18:05:32.208717
8507 18:05:32.208789 ==
8508 18:05:32.211765 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 18:05:32.215408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 18:05:32.215509 ==
8511 18:05:32.218612 RX Vref Scan: 1
8512 18:05:32.218716
8513 18:05:32.218806 Set Vref Range= 24 -> 127
8514 18:05:32.218895
8515 18:05:32.221762 RX Vref 24 -> 127, step: 1
8516 18:05:32.221858
8517 18:05:32.225309 RX Delay 27 -> 252, step: 4
8518 18:05:32.225417
8519 18:05:32.228584 Set Vref, RX VrefLevel [Byte0]: 24
8520 18:05:32.231560 [Byte1]: 24
8521 18:05:32.231671
8522 18:05:32.235054 Set Vref, RX VrefLevel [Byte0]: 25
8523 18:05:32.238594 [Byte1]: 25
8524 18:05:32.238699
8525 18:05:32.242042 Set Vref, RX VrefLevel [Byte0]: 26
8526 18:05:32.245357 [Byte1]: 26
8527 18:05:32.248874
8528 18:05:32.249004 Set Vref, RX VrefLevel [Byte0]: 27
8529 18:05:32.252438 [Byte1]: 27
8530 18:05:32.256375
8531 18:05:32.256504 Set Vref, RX VrefLevel [Byte0]: 28
8532 18:05:32.259905 [Byte1]: 28
8533 18:05:32.263767
8534 18:05:32.263874 Set Vref, RX VrefLevel [Byte0]: 29
8535 18:05:32.267421 [Byte1]: 29
8536 18:05:32.271917
8537 18:05:32.272027 Set Vref, RX VrefLevel [Byte0]: 30
8538 18:05:32.274923 [Byte1]: 30
8539 18:05:32.279632
8540 18:05:32.279736 Set Vref, RX VrefLevel [Byte0]: 31
8541 18:05:32.282287 [Byte1]: 31
8542 18:05:32.286588
8543 18:05:32.286694 Set Vref, RX VrefLevel [Byte0]: 32
8544 18:05:32.289623 [Byte1]: 32
8545 18:05:32.293974
8546 18:05:32.294052 Set Vref, RX VrefLevel [Byte0]: 33
8547 18:05:32.297664 [Byte1]: 33
8548 18:05:32.301868
8549 18:05:32.301971 Set Vref, RX VrefLevel [Byte0]: 34
8550 18:05:32.305296 [Byte1]: 34
8551 18:05:32.308959
8552 18:05:32.309062 Set Vref, RX VrefLevel [Byte0]: 35
8553 18:05:32.312496 [Byte1]: 35
8554 18:05:32.316601
8555 18:05:32.316681 Set Vref, RX VrefLevel [Byte0]: 36
8556 18:05:32.320154 [Byte1]: 36
8557 18:05:32.324471
8558 18:05:32.324549 Set Vref, RX VrefLevel [Byte0]: 37
8559 18:05:32.327415 [Byte1]: 37
8560 18:05:32.331991
8561 18:05:32.332100 Set Vref, RX VrefLevel [Byte0]: 38
8562 18:05:32.335590 [Byte1]: 38
8563 18:05:32.339528
8564 18:05:32.339605 Set Vref, RX VrefLevel [Byte0]: 39
8565 18:05:32.342475 [Byte1]: 39
8566 18:05:32.347298
8567 18:05:32.347410 Set Vref, RX VrefLevel [Byte0]: 40
8568 18:05:32.350241 [Byte1]: 40
8569 18:05:32.354576
8570 18:05:32.354689 Set Vref, RX VrefLevel [Byte0]: 41
8571 18:05:32.358025 [Byte1]: 41
8572 18:05:32.361944
8573 18:05:32.362068 Set Vref, RX VrefLevel [Byte0]: 42
8574 18:05:32.365438 [Byte1]: 42
8575 18:05:32.369286
8576 18:05:32.369365 Set Vref, RX VrefLevel [Byte0]: 43
8577 18:05:32.373002 [Byte1]: 43
8578 18:05:32.376718
8579 18:05:32.376794 Set Vref, RX VrefLevel [Byte0]: 44
8580 18:05:32.380554 [Byte1]: 44
8581 18:05:32.384501
8582 18:05:32.384616 Set Vref, RX VrefLevel [Byte0]: 45
8583 18:05:32.388210 [Byte1]: 45
8584 18:05:32.391751
8585 18:05:32.391829 Set Vref, RX VrefLevel [Byte0]: 46
8586 18:05:32.395416 [Byte1]: 46
8587 18:05:32.399783
8588 18:05:32.399858 Set Vref, RX VrefLevel [Byte0]: 47
8589 18:05:32.402762 [Byte1]: 47
8590 18:05:32.407270
8591 18:05:32.407374 Set Vref, RX VrefLevel [Byte0]: 48
8592 18:05:32.410333 [Byte1]: 48
8593 18:05:32.414861
8594 18:05:32.414936 Set Vref, RX VrefLevel [Byte0]: 49
8595 18:05:32.418343 [Byte1]: 49
8596 18:05:32.422332
8597 18:05:32.422440 Set Vref, RX VrefLevel [Byte0]: 50
8598 18:05:32.425588 [Byte1]: 50
8599 18:05:32.430018
8600 18:05:32.430125 Set Vref, RX VrefLevel [Byte0]: 51
8601 18:05:32.432713 [Byte1]: 51
8602 18:05:32.437186
8603 18:05:32.437270 Set Vref, RX VrefLevel [Byte0]: 52
8604 18:05:32.440592 [Byte1]: 52
8605 18:05:32.445087
8606 18:05:32.445204 Set Vref, RX VrefLevel [Byte0]: 53
8607 18:05:32.448028 [Byte1]: 53
8608 18:05:32.452249
8609 18:05:32.452391 Set Vref, RX VrefLevel [Byte0]: 54
8610 18:05:32.456062 [Byte1]: 54
8611 18:05:32.459929
8612 18:05:32.460009 Set Vref, RX VrefLevel [Byte0]: 55
8613 18:05:32.463463 [Byte1]: 55
8614 18:05:32.467194
8615 18:05:32.467308 Set Vref, RX VrefLevel [Byte0]: 56
8616 18:05:32.470793 [Byte1]: 56
8617 18:05:32.474753
8618 18:05:32.474863 Set Vref, RX VrefLevel [Byte0]: 57
8619 18:05:32.478130 [Byte1]: 57
8620 18:05:32.482463
8621 18:05:32.482558 Set Vref, RX VrefLevel [Byte0]: 58
8622 18:05:32.485553 [Byte1]: 58
8623 18:05:32.490039
8624 18:05:32.490131 Set Vref, RX VrefLevel [Byte0]: 59
8625 18:05:32.493627 [Byte1]: 59
8626 18:05:32.497528
8627 18:05:32.497607 Set Vref, RX VrefLevel [Byte0]: 60
8628 18:05:32.500854 [Byte1]: 60
8629 18:05:32.505639
8630 18:05:32.505753 Set Vref, RX VrefLevel [Byte0]: 61
8631 18:05:32.508415 [Byte1]: 61
8632 18:05:32.512375
8633 18:05:32.512482 Set Vref, RX VrefLevel [Byte0]: 62
8634 18:05:32.516065 [Byte1]: 62
8635 18:05:32.519777
8636 18:05:32.519876 Set Vref, RX VrefLevel [Byte0]: 63
8637 18:05:32.523715 [Byte1]: 63
8638 18:05:32.527397
8639 18:05:32.527500 Set Vref, RX VrefLevel [Byte0]: 64
8640 18:05:32.531188 [Byte1]: 64
8641 18:05:32.535660
8642 18:05:32.535736 Set Vref, RX VrefLevel [Byte0]: 65
8643 18:05:32.538322 [Byte1]: 65
8644 18:05:32.542494
8645 18:05:32.542571 Set Vref, RX VrefLevel [Byte0]: 66
8646 18:05:32.545939 [Byte1]: 66
8647 18:05:32.550033
8648 18:05:32.550116 Set Vref, RX VrefLevel [Byte0]: 67
8649 18:05:32.553571 [Byte1]: 67
8650 18:05:32.557556
8651 18:05:32.557669 Set Vref, RX VrefLevel [Byte0]: 68
8652 18:05:32.561262 [Byte1]: 68
8653 18:05:32.565099
8654 18:05:32.565183 Set Vref, RX VrefLevel [Byte0]: 69
8655 18:05:32.568883 [Byte1]: 69
8656 18:05:32.572585
8657 18:05:32.572685 Set Vref, RX VrefLevel [Byte0]: 70
8658 18:05:32.576372 [Byte1]: 70
8659 18:05:32.580947
8660 18:05:32.581024 Set Vref, RX VrefLevel [Byte0]: 71
8661 18:05:32.583694 [Byte1]: 71
8662 18:05:32.587916
8663 18:05:32.587995 Set Vref, RX VrefLevel [Byte0]: 72
8664 18:05:32.591603 [Byte1]: 72
8665 18:05:32.595491
8666 18:05:32.595568 Set Vref, RX VrefLevel [Byte0]: 73
8667 18:05:32.598816 [Byte1]: 73
8668 18:05:32.603084
8669 18:05:32.603164 Set Vref, RX VrefLevel [Byte0]: 74
8670 18:05:32.606905 [Byte1]: 74
8671 18:05:32.610315
8672 18:05:32.610396 Set Vref, RX VrefLevel [Byte0]: 75
8673 18:05:32.616999 [Byte1]: 75
8674 18:05:32.617079
8675 18:05:32.620043 Set Vref, RX VrefLevel [Byte0]: 76
8676 18:05:32.623738 [Byte1]: 76
8677 18:05:32.623818
8678 18:05:32.626784 Set Vref, RX VrefLevel [Byte0]: 77
8679 18:05:32.630391 [Byte1]: 77
8680 18:05:32.630466
8681 18:05:32.633397 Set Vref, RX VrefLevel [Byte0]: 78
8682 18:05:32.637011 [Byte1]: 78
8683 18:05:32.640884
8684 18:05:32.640994 Final RX Vref Byte 0 = 57 to rank0
8685 18:05:32.643851 Final RX Vref Byte 1 = 58 to rank0
8686 18:05:32.647580 Final RX Vref Byte 0 = 57 to rank1
8687 18:05:32.650408 Final RX Vref Byte 1 = 58 to rank1==
8688 18:05:32.654089 Dram Type= 6, Freq= 0, CH_1, rank 0
8689 18:05:32.660897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8690 18:05:32.660992 ==
8691 18:05:32.661058 DQS Delay:
8692 18:05:32.661118 DQS0 = 0, DQS1 = 0
8693 18:05:32.663865 DQM Delay:
8694 18:05:32.663938 DQM0 = 134, DQM1 = 131
8695 18:05:32.667652 DQ Delay:
8696 18:05:32.670462 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8697 18:05:32.674142 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8698 18:05:32.676963 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8699 18:05:32.680177 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8700 18:05:32.680288
8701 18:05:32.680390
8702 18:05:32.680478
8703 18:05:32.683596 [DramC_TX_OE_Calibration] TA2
8704 18:05:32.686998 Original DQ_B0 (3 6) =30, OEN = 27
8705 18:05:32.690883 Original DQ_B1 (3 6) =30, OEN = 27
8706 18:05:32.694044 24, 0x0, End_B0=24 End_B1=24
8707 18:05:32.694131 25, 0x0, End_B0=25 End_B1=25
8708 18:05:32.697117 26, 0x0, End_B0=26 End_B1=26
8709 18:05:32.700664 27, 0x0, End_B0=27 End_B1=27
8710 18:05:32.704190 28, 0x0, End_B0=28 End_B1=28
8711 18:05:32.704319 29, 0x0, End_B0=29 End_B1=29
8712 18:05:32.707738 30, 0x0, End_B0=30 End_B1=30
8713 18:05:32.710541 31, 0x4141, End_B0=30 End_B1=30
8714 18:05:32.714184 Byte0 end_step=30 best_step=27
8715 18:05:32.717838 Byte1 end_step=30 best_step=27
8716 18:05:32.720739 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 18:05:32.720854 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 18:05:32.720927
8719 18:05:32.724049
8720 18:05:32.730174 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8721 18:05:32.733741 CH1 RK0: MR19=303, MR18=1523
8722 18:05:32.740396 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8723 18:05:32.740481
8724 18:05:32.744070 ----->DramcWriteLeveling(PI) begin...
8725 18:05:32.744156 ==
8726 18:05:32.746917 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 18:05:32.750496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 18:05:32.750599 ==
8729 18:05:32.754012 Write leveling (Byte 0): 24 => 24
8730 18:05:32.757003 Write leveling (Byte 1): 28 => 28
8731 18:05:32.760869 DramcWriteLeveling(PI) end<-----
8732 18:05:32.760948
8733 18:05:32.761025 ==
8734 18:05:32.763841 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 18:05:32.766781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 18:05:32.766885 ==
8737 18:05:32.770700 [Gating] SW mode calibration
8738 18:05:32.776632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8739 18:05:32.783634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8740 18:05:32.787180 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 18:05:32.790253 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 18:05:32.796866 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8743 18:05:32.800403 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8744 18:05:32.803809 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 18:05:32.810153 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 18:05:32.813111 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 18:05:32.816541 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 18:05:32.823402 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 18:05:32.826568 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 18:05:32.830176 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
8751 18:05:32.836819 1 5 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 0)
8752 18:05:32.840169 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 18:05:32.843808 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 18:05:32.850182 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 18:05:32.853374 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 18:05:32.856946 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 18:05:32.863269 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 18:05:32.866932 1 6 8 | B1->B0 | 3b3b 2323 | 1 0 | (0 0) (0 0)
8759 18:05:32.869857 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8760 18:05:32.876690 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 18:05:32.880021 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 18:05:32.883042 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 18:05:32.886769 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 18:05:32.893430 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 18:05:32.896261 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8766 18:05:32.900416 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8767 18:05:32.906253 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8768 18:05:32.909948 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8769 18:05:32.913873 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 18:05:32.919587 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 18:05:32.923032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 18:05:32.926621 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 18:05:32.933094 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 18:05:32.936537 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 18:05:32.939712 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 18:05:32.946549 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 18:05:32.949741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 18:05:32.952994 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 18:05:32.959558 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 18:05:32.962847 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 18:05:32.966020 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 18:05:32.972980 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8783 18:05:32.976043 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8784 18:05:32.979696 Total UI for P1: 0, mck2ui 16
8785 18:05:32.982462 best dqsien dly found for B1: ( 1, 9, 6)
8786 18:05:32.985977 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 18:05:32.989005 Total UI for P1: 0, mck2ui 16
8788 18:05:32.992667 best dqsien dly found for B0: ( 1, 9, 10)
8789 18:05:32.995731 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8790 18:05:32.999280 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8791 18:05:32.999363
8792 18:05:33.006125 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8793 18:05:33.009164 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8794 18:05:33.012797 [Gating] SW calibration Done
8795 18:05:33.012880 ==
8796 18:05:33.015723 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 18:05:33.018697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 18:05:33.018781 ==
8799 18:05:33.018846 RX Vref Scan: 0
8800 18:05:33.018906
8801 18:05:33.022483 RX Vref 0 -> 0, step: 1
8802 18:05:33.022566
8803 18:05:33.025425 RX Delay 0 -> 252, step: 8
8804 18:05:33.029056 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8805 18:05:33.032507 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8806 18:05:33.035425 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8807 18:05:33.042026 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8808 18:05:33.045896 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8809 18:05:33.049247 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8810 18:05:33.052088 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8811 18:05:33.055721 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8812 18:05:33.062275 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8813 18:05:33.065648 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8814 18:05:33.068961 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8815 18:05:33.072470 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8816 18:05:33.076182 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8817 18:05:33.082551 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8818 18:05:33.085980 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8819 18:05:33.089386 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8820 18:05:33.089471 ==
8821 18:05:33.092114 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 18:05:33.095648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 18:05:33.098573 ==
8824 18:05:33.098677 DQS Delay:
8825 18:05:33.098770 DQS0 = 0, DQS1 = 0
8826 18:05:33.102421 DQM Delay:
8827 18:05:33.102527 DQM0 = 135, DQM1 = 133
8828 18:05:33.105220 DQ Delay:
8829 18:05:33.108906 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8830 18:05:33.111905 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8831 18:05:33.115609 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8832 18:05:33.118628 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8833 18:05:33.118711
8834 18:05:33.118776
8835 18:05:33.118837 ==
8836 18:05:33.122373 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 18:05:33.125364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 18:05:33.125447 ==
8839 18:05:33.125512
8840 18:05:33.128458
8841 18:05:33.128541 TX Vref Scan disable
8842 18:05:33.132189 == TX Byte 0 ==
8843 18:05:33.135488 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8844 18:05:33.138381 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8845 18:05:33.142095 == TX Byte 1 ==
8846 18:05:33.145181 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8847 18:05:33.148635 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8848 18:05:33.148727 ==
8849 18:05:33.152030 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 18:05:33.158432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 18:05:33.158542 ==
8852 18:05:33.169885
8853 18:05:33.173579 TX Vref early break, caculate TX vref
8854 18:05:33.177124 TX Vref=16, minBit 0, minWin=23, winSum=382
8855 18:05:33.180300 TX Vref=18, minBit 0, minWin=23, winSum=395
8856 18:05:33.183679 TX Vref=20, minBit 0, minWin=24, winSum=400
8857 18:05:33.187065 TX Vref=22, minBit 0, minWin=25, winSum=410
8858 18:05:33.190132 TX Vref=24, minBit 0, minWin=25, winSum=420
8859 18:05:33.196752 TX Vref=26, minBit 0, minWin=26, winSum=425
8860 18:05:33.199754 TX Vref=28, minBit 0, minWin=26, winSum=431
8861 18:05:33.203347 TX Vref=30, minBit 0, minWin=25, winSum=424
8862 18:05:33.206666 TX Vref=32, minBit 0, minWin=25, winSum=414
8863 18:05:33.209954 TX Vref=34, minBit 0, minWin=24, winSum=407
8864 18:05:33.216221 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8865 18:05:33.216344
8866 18:05:33.220189 Final TX Range 0 Vref 28
8867 18:05:33.220294
8868 18:05:33.220400 ==
8869 18:05:33.223468 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 18:05:33.226340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 18:05:33.226423 ==
8872 18:05:33.226489
8873 18:05:33.226549
8874 18:05:33.230176 TX Vref Scan disable
8875 18:05:33.236718 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8876 18:05:33.236794 == TX Byte 0 ==
8877 18:05:33.239799 u2DelayCellOfst[0]=17 cells (5 PI)
8878 18:05:33.243473 u2DelayCellOfst[1]=13 cells (4 PI)
8879 18:05:33.246045 u2DelayCellOfst[2]=0 cells (0 PI)
8880 18:05:33.249693 u2DelayCellOfst[3]=6 cells (2 PI)
8881 18:05:33.252806 u2DelayCellOfst[4]=10 cells (3 PI)
8882 18:05:33.256327 u2DelayCellOfst[5]=17 cells (5 PI)
8883 18:05:33.259295 u2DelayCellOfst[6]=20 cells (6 PI)
8884 18:05:33.263120 u2DelayCellOfst[7]=6 cells (2 PI)
8885 18:05:33.266235 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8886 18:05:33.269861 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8887 18:05:33.272587 == TX Byte 1 ==
8888 18:05:33.278669 u2DelayCellOfst[8]=0 cells (0 PI)
8889 18:05:33.278791 u2DelayCellOfst[9]=3 cells (1 PI)
8890 18:05:33.279564 u2DelayCellOfst[10]=10 cells (3 PI)
8891 18:05:33.282531 u2DelayCellOfst[11]=6 cells (2 PI)
8892 18:05:33.286048 u2DelayCellOfst[12]=13 cells (4 PI)
8893 18:05:33.289594 u2DelayCellOfst[13]=13 cells (4 PI)
8894 18:05:33.292525 u2DelayCellOfst[14]=17 cells (5 PI)
8895 18:05:33.295730 u2DelayCellOfst[15]=17 cells (5 PI)
8896 18:05:33.299025 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8897 18:05:33.306168 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8898 18:05:33.306283 DramC Write-DBI on
8899 18:05:33.306384 ==
8900 18:05:33.308874 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 18:05:33.315393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 18:05:33.315474 ==
8903 18:05:33.315545
8904 18:05:33.315635
8905 18:05:33.315722 TX Vref Scan disable
8906 18:05:33.319563 == TX Byte 0 ==
8907 18:05:33.323000 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8908 18:05:33.326290 == TX Byte 1 ==
8909 18:05:33.329482 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8910 18:05:33.332727 DramC Write-DBI off
8911 18:05:33.332829
8912 18:05:33.332906 [DATLAT]
8913 18:05:33.332967 Freq=1600, CH1 RK1
8914 18:05:33.333027
8915 18:05:33.336302 DATLAT Default: 0xf
8916 18:05:33.336396 0, 0xFFFF, sum = 0
8917 18:05:33.339524 1, 0xFFFF, sum = 0
8918 18:05:33.339630 2, 0xFFFF, sum = 0
8919 18:05:33.342849 3, 0xFFFF, sum = 0
8920 18:05:33.345863 4, 0xFFFF, sum = 0
8921 18:05:33.345982 5, 0xFFFF, sum = 0
8922 18:05:33.349529 6, 0xFFFF, sum = 0
8923 18:05:33.349643 7, 0xFFFF, sum = 0
8924 18:05:33.352659 8, 0xFFFF, sum = 0
8925 18:05:33.352776 9, 0xFFFF, sum = 0
8926 18:05:33.356294 10, 0xFFFF, sum = 0
8927 18:05:33.356420 11, 0xFFFF, sum = 0
8928 18:05:33.359203 12, 0xFFFF, sum = 0
8929 18:05:33.359320 13, 0xFFFF, sum = 0
8930 18:05:33.362930 14, 0x0, sum = 1
8931 18:05:33.363043 15, 0x0, sum = 2
8932 18:05:33.365865 16, 0x0, sum = 3
8933 18:05:33.365991 17, 0x0, sum = 4
8934 18:05:33.369508 best_step = 15
8935 18:05:33.369648
8936 18:05:33.369754 ==
8937 18:05:33.372521 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 18:05:33.375606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 18:05:33.375752 ==
8940 18:05:33.378983 RX Vref Scan: 0
8941 18:05:33.379098
8942 18:05:33.379209 RX Vref 0 -> 0, step: 1
8943 18:05:33.379287
8944 18:05:33.382649 RX Delay 19 -> 252, step: 4
8945 18:05:33.385808 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8946 18:05:33.392136 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8947 18:05:33.395844 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8948 18:05:33.398738 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8949 18:05:33.402247 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8950 18:05:33.405800 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8951 18:05:33.412328 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8952 18:05:33.415806 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8953 18:05:33.418575 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8954 18:05:33.422212 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8955 18:05:33.425752 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8956 18:05:33.432225 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8957 18:05:33.435682 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8958 18:05:33.438657 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8959 18:05:33.441956 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8960 18:05:33.445444 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8961 18:05:33.448800 ==
8962 18:05:33.452116 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 18:05:33.455580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 18:05:33.455694 ==
8965 18:05:33.455790 DQS Delay:
8966 18:05:33.458320 DQS0 = 0, DQS1 = 0
8967 18:05:33.458423 DQM Delay:
8968 18:05:33.462177 DQM0 = 134, DQM1 = 130
8969 18:05:33.462281 DQ Delay:
8970 18:05:33.465352 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8971 18:05:33.468662 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8972 18:05:33.472422 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8973 18:05:33.475231 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8974 18:05:33.475338
8975 18:05:33.475430
8976 18:05:33.475507
8977 18:05:33.478274 [DramC_TX_OE_Calibration] TA2
8978 18:05:33.481952 Original DQ_B0 (3 6) =30, OEN = 27
8979 18:05:33.485475 Original DQ_B1 (3 6) =30, OEN = 27
8980 18:05:33.488328 24, 0x0, End_B0=24 End_B1=24
8981 18:05:33.491797 25, 0x0, End_B0=25 End_B1=25
8982 18:05:33.491904 26, 0x0, End_B0=26 End_B1=26
8983 18:05:33.495484 27, 0x0, End_B0=27 End_B1=27
8984 18:05:33.498314 28, 0x0, End_B0=28 End_B1=28
8985 18:05:33.501661 29, 0x0, End_B0=29 End_B1=29
8986 18:05:33.505224 30, 0x0, End_B0=30 End_B1=30
8987 18:05:33.505339 31, 0x4141, End_B0=30 End_B1=30
8988 18:05:33.508834 Byte0 end_step=30 best_step=27
8989 18:05:33.511997 Byte1 end_step=30 best_step=27
8990 18:05:33.515343 Byte0 TX OE(2T, 0.5T) = (3, 3)
8991 18:05:33.518884 Byte1 TX OE(2T, 0.5T) = (3, 3)
8992 18:05:33.518998
8993 18:05:33.519092
8994 18:05:33.525450 [DQSOSCAuto] RK1, (LSB)MR18= 0x2005, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
8995 18:05:33.528669 CH1 RK1: MR19=303, MR18=2005
8996 18:05:33.535221 CH1_RK1: MR19=0x303, MR18=0x2005, DQSOSC=393, MR23=63, INC=23, DEC=15
8997 18:05:33.538880 [RxdqsGatingPostProcess] freq 1600
8998 18:05:33.541794 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8999 18:05:33.545486 best DQS0 dly(2T, 0.5T) = (1, 1)
9000 18:05:33.548305 best DQS1 dly(2T, 0.5T) = (1, 1)
9001 18:05:33.551988 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9002 18:05:33.554745 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9003 18:05:33.558293 best DQS0 dly(2T, 0.5T) = (1, 1)
9004 18:05:33.561803 best DQS1 dly(2T, 0.5T) = (1, 1)
9005 18:05:33.564828 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9006 18:05:33.568505 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9007 18:05:33.571460 Pre-setting of DQS Precalculation
9008 18:05:33.574774 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9009 18:05:33.585090 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9010 18:05:33.591745 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9011 18:05:33.591870
9012 18:05:33.591975
9013 18:05:33.594701 [Calibration Summary] 3200 Mbps
9014 18:05:33.594817 CH 0, Rank 0
9015 18:05:33.598270 SW Impedance : PASS
9016 18:05:33.598374 DUTY Scan : NO K
9017 18:05:33.601814 ZQ Calibration : PASS
9018 18:05:33.604826 Jitter Meter : NO K
9019 18:05:33.604904 CBT Training : PASS
9020 18:05:33.608317 Write leveling : PASS
9021 18:05:33.611634 RX DQS gating : PASS
9022 18:05:33.611747 RX DQ/DQS(RDDQC) : PASS
9023 18:05:33.614615 TX DQ/DQS : PASS
9024 18:05:33.614731 RX DATLAT : PASS
9025 18:05:33.618181 RX DQ/DQS(Engine): PASS
9026 18:05:33.621305 TX OE : PASS
9027 18:05:33.621388 All Pass.
9028 18:05:33.621453
9029 18:05:33.621537 CH 0, Rank 1
9030 18:05:33.624841 SW Impedance : PASS
9031 18:05:33.628200 DUTY Scan : NO K
9032 18:05:33.628304 ZQ Calibration : PASS
9033 18:05:33.631885 Jitter Meter : NO K
9034 18:05:33.635045 CBT Training : PASS
9035 18:05:33.635149 Write leveling : PASS
9036 18:05:33.638444 RX DQS gating : PASS
9037 18:05:33.641114 RX DQ/DQS(RDDQC) : PASS
9038 18:05:33.641219 TX DQ/DQS : PASS
9039 18:05:33.644696 RX DATLAT : PASS
9040 18:05:33.647693 RX DQ/DQS(Engine): PASS
9041 18:05:33.647776 TX OE : PASS
9042 18:05:33.651247 All Pass.
9043 18:05:33.651332
9044 18:05:33.651398 CH 1, Rank 0
9045 18:05:33.654855 SW Impedance : PASS
9046 18:05:33.654930 DUTY Scan : NO K
9047 18:05:33.657719 ZQ Calibration : PASS
9048 18:05:33.661194 Jitter Meter : NO K
9049 18:05:33.661280 CBT Training : PASS
9050 18:05:33.664824 Write leveling : PASS
9051 18:05:33.667517 RX DQS gating : PASS
9052 18:05:33.667628 RX DQ/DQS(RDDQC) : PASS
9053 18:05:33.671364 TX DQ/DQS : PASS
9054 18:05:33.671452 RX DATLAT : PASS
9055 18:05:33.674345 RX DQ/DQS(Engine): PASS
9056 18:05:33.677926 TX OE : PASS
9057 18:05:33.678011 All Pass.
9058 18:05:33.678077
9059 18:05:33.678138 CH 1, Rank 1
9060 18:05:33.680881 SW Impedance : PASS
9061 18:05:33.684188 DUTY Scan : NO K
9062 18:05:33.684273 ZQ Calibration : PASS
9063 18:05:33.687619 Jitter Meter : NO K
9064 18:05:33.691012 CBT Training : PASS
9065 18:05:33.691097 Write leveling : PASS
9066 18:05:33.694229 RX DQS gating : PASS
9067 18:05:33.697645 RX DQ/DQS(RDDQC) : PASS
9068 18:05:33.697731 TX DQ/DQS : PASS
9069 18:05:33.700640 RX DATLAT : PASS
9070 18:05:33.704511 RX DQ/DQS(Engine): PASS
9071 18:05:33.704594 TX OE : PASS
9072 18:05:33.707703 All Pass.
9073 18:05:33.707785
9074 18:05:33.707849 DramC Write-DBI on
9075 18:05:33.711089 PER_BANK_REFRESH: Hybrid Mode
9076 18:05:33.711169 TX_TRACKING: ON
9077 18:05:33.720474 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9078 18:05:33.730469 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9079 18:05:33.737246 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 18:05:33.740210 [FAST_K] Save calibration result to emmc
9081 18:05:33.743775 sync common calibartion params.
9082 18:05:33.743892 sync cbt_mode0:1, 1:1
9083 18:05:33.747235 dram_init: ddr_geometry: 2
9084 18:05:33.750105 dram_init: ddr_geometry: 2
9085 18:05:33.750221 dram_init: ddr_geometry: 2
9086 18:05:33.753598 0:dram_rank_size:100000000
9087 18:05:33.757306 1:dram_rank_size:100000000
9088 18:05:33.763411 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9089 18:05:33.763534 DFS_SHUFFLE_HW_MODE: ON
9090 18:05:33.767155 dramc_set_vcore_voltage set vcore to 725000
9091 18:05:33.770620 Read voltage for 1600, 0
9092 18:05:33.770711 Vio18 = 0
9093 18:05:33.774056 Vcore = 725000
9094 18:05:33.774140 Vdram = 0
9095 18:05:33.774205 Vddq = 0
9096 18:05:33.777033 Vmddr = 0
9097 18:05:33.777108 switch to 3200 Mbps bootup
9098 18:05:33.780745 [DramcRunTimeConfig]
9099 18:05:33.780829 PHYPLL
9100 18:05:33.783772 DPM_CONTROL_AFTERK: ON
9101 18:05:33.783855 PER_BANK_REFRESH: ON
9102 18:05:33.787341 REFRESH_OVERHEAD_REDUCTION: ON
9103 18:05:33.790166 CMD_PICG_NEW_MODE: OFF
9104 18:05:33.790279 XRTWTW_NEW_MODE: ON
9105 18:05:33.793757 XRTRTR_NEW_MODE: ON
9106 18:05:33.793843 TX_TRACKING: ON
9107 18:05:33.797057 RDSEL_TRACKING: OFF
9108 18:05:33.801598 DQS Precalculation for DVFS: ON
9109 18:05:33.801688 RX_TRACKING: OFF
9110 18:05:33.803801 HW_GATING DBG: ON
9111 18:05:33.803888 ZQCS_ENABLE_LP4: ON
9112 18:05:33.807339 RX_PICG_NEW_MODE: ON
9113 18:05:33.807423 TX_PICG_NEW_MODE: ON
9114 18:05:33.810226 ENABLE_RX_DCM_DPHY: ON
9115 18:05:33.813696 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9116 18:05:33.817467 DUMMY_READ_FOR_TRACKING: OFF
9117 18:05:33.817560 !!! SPM_CONTROL_AFTERK: OFF
9118 18:05:33.820384 !!! SPM could not control APHY
9119 18:05:33.824135 IMPEDANCE_TRACKING: ON
9120 18:05:33.824236 TEMP_SENSOR: ON
9121 18:05:33.827161 HW_SAVE_FOR_SR: OFF
9122 18:05:33.830514 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9123 18:05:33.833844 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9124 18:05:33.833955 Read ODT Tracking: ON
9125 18:05:33.836924 Refresh Rate DeBounce: ON
9126 18:05:33.840575 DFS_NO_QUEUE_FLUSH: ON
9127 18:05:33.844004 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9128 18:05:33.844114 ENABLE_DFS_RUNTIME_MRW: OFF
9129 18:05:33.847016 DDR_RESERVE_NEW_MODE: ON
9130 18:05:33.850600 MR_CBT_SWITCH_FREQ: ON
9131 18:05:33.850713 =========================
9132 18:05:33.870589 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9133 18:05:33.874176 dram_init: ddr_geometry: 2
9134 18:05:33.892756 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9135 18:05:33.895558 dram_init: dram init end (result: 0)
9136 18:05:33.902198 DRAM-K: Full calibration passed in 24454 msecs
9137 18:05:33.906102 MRC: failed to locate region type 0.
9138 18:05:33.906224 DRAM rank0 size:0x100000000,
9139 18:05:33.908792 DRAM rank1 size=0x100000000
9140 18:05:33.919062 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9141 18:05:33.925639 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9142 18:05:33.932107 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9143 18:05:33.938868 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9144 18:05:33.942287 DRAM rank0 size:0x100000000,
9145 18:05:33.945678 DRAM rank1 size=0x100000000
9146 18:05:33.945826 CBMEM:
9147 18:05:33.949239 IMD: root @ 0xfffff000 254 entries.
9148 18:05:33.951972 IMD: root @ 0xffffec00 62 entries.
9149 18:05:33.955731 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9150 18:05:33.958611 WARNING: RO_VPD is uninitialized or empty.
9151 18:05:33.965573 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9152 18:05:33.972491 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9153 18:05:33.985594 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9154 18:05:33.996542 BS: romstage times (exec / console): total (unknown) / 23984 ms
9155 18:05:33.996670
9156 18:05:33.996742
9157 18:05:34.006751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9158 18:05:34.009646 ARM64: Exception handlers installed.
9159 18:05:34.013538 ARM64: Testing exception
9160 18:05:34.016355 ARM64: Done test exception
9161 18:05:34.016478 Enumerating buses...
9162 18:05:34.019673 Show all devs... Before device enumeration.
9163 18:05:34.023148 Root Device: enabled 1
9164 18:05:34.026699 CPU_CLUSTER: 0: enabled 1
9165 18:05:34.026807 CPU: 00: enabled 1
9166 18:05:34.029496 Compare with tree...
9167 18:05:34.029601 Root Device: enabled 1
9168 18:05:34.033145 CPU_CLUSTER: 0: enabled 1
9169 18:05:34.036027 CPU: 00: enabled 1
9170 18:05:34.036129 Root Device scanning...
9171 18:05:34.039642 scan_static_bus for Root Device
9172 18:05:34.042758 CPU_CLUSTER: 0 enabled
9173 18:05:34.046249 scan_static_bus for Root Device done
9174 18:05:34.049780 scan_bus: bus Root Device finished in 8 msecs
9175 18:05:34.049891 done
9176 18:05:34.056417 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9177 18:05:34.059313 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9178 18:05:34.065711 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9179 18:05:34.069315 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9180 18:05:34.072998 Allocating resources...
9181 18:05:34.075741 Reading resources...
9182 18:05:34.079480 Root Device read_resources bus 0 link: 0
9183 18:05:34.079564 DRAM rank0 size:0x100000000,
9184 18:05:34.082719 DRAM rank1 size=0x100000000
9185 18:05:34.085530 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9186 18:05:34.089070 CPU: 00 missing read_resources
9187 18:05:34.095938 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9188 18:05:34.099442 Root Device read_resources bus 0 link: 0 done
9189 18:05:34.099522 Done reading resources.
9190 18:05:34.105618 Show resources in subtree (Root Device)...After reading.
9191 18:05:34.109374 Root Device child on link 0 CPU_CLUSTER: 0
9192 18:05:34.112335 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 18:05:34.122495 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 18:05:34.122579 CPU: 00
9195 18:05:34.126177 Root Device assign_resources, bus 0 link: 0
9196 18:05:34.129015 CPU_CLUSTER: 0 missing set_resources
9197 18:05:34.135389 Root Device assign_resources, bus 0 link: 0 done
9198 18:05:34.135474 Done setting resources.
9199 18:05:34.141958 Show resources in subtree (Root Device)...After assigning values.
9200 18:05:34.145439 Root Device child on link 0 CPU_CLUSTER: 0
9201 18:05:34.149114 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 18:05:34.159119 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 18:05:34.159223 CPU: 00
9204 18:05:34.161907 Done allocating resources.
9205 18:05:34.165244 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9206 18:05:34.168698 Enabling resources...
9207 18:05:34.168788 done.
9208 18:05:34.175581 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9209 18:05:34.175662 Initializing devices...
9210 18:05:34.178341 Root Device init
9211 18:05:34.178418 init hardware done!
9212 18:05:34.181847 0x00000018: ctrlr->caps
9213 18:05:34.185282 52.000 MHz: ctrlr->f_max
9214 18:05:34.185390 0.400 MHz: ctrlr->f_min
9215 18:05:34.188769 0x40ff8080: ctrlr->voltages
9216 18:05:34.191672 sclk: 390625
9217 18:05:34.191756 Bus Width = 1
9218 18:05:34.191822 sclk: 390625
9219 18:05:34.195473 Bus Width = 1
9220 18:05:34.195565 Early init status = 3
9221 18:05:34.201662 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9222 18:05:34.204946 in-header: 03 fc 00 00 01 00 00 00
9223 18:05:34.205027 in-data: 00
9224 18:05:34.211709 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9225 18:05:34.215302 in-header: 03 fd 00 00 00 00 00 00
9226 18:05:34.218328 in-data:
9227 18:05:34.221895 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9228 18:05:34.225502 in-header: 03 fc 00 00 01 00 00 00
9229 18:05:34.228408 in-data: 00
9230 18:05:34.231881 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9231 18:05:34.236104 in-header: 03 fd 00 00 00 00 00 00
9232 18:05:34.239631 in-data:
9233 18:05:34.243332 [SSUSB] Setting up USB HOST controller...
9234 18:05:34.246250 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9235 18:05:34.249901 [SSUSB] phy power-on done.
9236 18:05:34.252954 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9237 18:05:34.259340 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9238 18:05:34.263307 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9239 18:05:34.269298 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9240 18:05:34.276432 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9241 18:05:34.282723 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9242 18:05:34.289216 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9243 18:05:34.296373 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9244 18:05:34.299362 SPM: binary array size = 0x9dc
9245 18:05:34.303024 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9246 18:05:34.309715 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9247 18:05:34.315806 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9248 18:05:34.319188 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9249 18:05:34.325923 configure_display: Starting display init
9250 18:05:34.359641 anx7625_power_on_init: Init interface.
9251 18:05:34.363278 anx7625_disable_pd_protocol: Disabled PD feature.
9252 18:05:34.366272 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9253 18:05:34.394416 anx7625_start_dp_work: Secure OCM version=00
9254 18:05:34.397265 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9255 18:05:34.412309 sp_tx_get_edid_block: EDID Block = 1
9256 18:05:34.514633 Extracted contents:
9257 18:05:34.518147 header: 00 ff ff ff ff ff ff 00
9258 18:05:34.521732 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9259 18:05:34.524591 version: 01 04
9260 18:05:34.528366 basic params: 95 1f 11 78 0a
9261 18:05:34.531235 chroma info: 76 90 94 55 54 90 27 21 50 54
9262 18:05:34.535049 established: 00 00 00
9263 18:05:34.541252 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9264 18:05:34.544922 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9265 18:05:34.551335 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9266 18:05:34.557775 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9267 18:05:34.564955 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9268 18:05:34.567790 extensions: 00
9269 18:05:34.567877 checksum: fb
9270 18:05:34.567943
9271 18:05:34.571337 Manufacturer: IVO Model 57d Serial Number 0
9272 18:05:34.574295 Made week 0 of 2020
9273 18:05:34.574379 EDID version: 1.4
9274 18:05:34.577994 Digital display
9275 18:05:34.581070 6 bits per primary color channel
9276 18:05:34.581156 DisplayPort interface
9277 18:05:34.584730 Maximum image size: 31 cm x 17 cm
9278 18:05:34.588186 Gamma: 220%
9279 18:05:34.588276 Check DPMS levels
9280 18:05:34.590933 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9281 18:05:34.594621 First detailed timing is preferred timing
9282 18:05:34.597650 Established timings supported:
9283 18:05:34.601310 Standard timings supported:
9284 18:05:34.601420 Detailed timings
9285 18:05:34.607829 Hex of detail: 383680a07038204018303c0035ae10000019
9286 18:05:34.611359 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9287 18:05:34.618024 0780 0798 07c8 0820 hborder 0
9288 18:05:34.621381 0438 043b 0447 0458 vborder 0
9289 18:05:34.621466 -hsync -vsync
9290 18:05:34.624736 Did detailed timing
9291 18:05:34.628077 Hex of detail: 000000000000000000000000000000000000
9292 18:05:34.631490 Manufacturer-specified data, tag 0
9293 18:05:34.637864 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9294 18:05:34.637956 ASCII string: InfoVision
9295 18:05:34.644599 Hex of detail: 000000fe00523134304e574635205248200a
9296 18:05:34.647497 ASCII string: R140NWF5 RH
9297 18:05:34.647582 Checksum
9298 18:05:34.647647 Checksum: 0xfb (valid)
9299 18:05:34.654707 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9300 18:05:34.657515 DSI data_rate: 832800000 bps
9301 18:05:34.661143 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9302 18:05:34.664187 anx7625_parse_edid: pixelclock(138800).
9303 18:05:34.671276 hactive(1920), hsync(48), hfp(24), hbp(88)
9304 18:05:34.674128 vactive(1080), vsync(12), vfp(3), vbp(17)
9305 18:05:34.677395 anx7625_dsi_config: config dsi.
9306 18:05:34.683751 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9307 18:05:34.696619 anx7625_dsi_config: success to config DSI
9308 18:05:34.700519 anx7625_dp_start: MIPI phy setup OK.
9309 18:05:34.703154 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9310 18:05:34.706818 mtk_ddp_mode_set invalid vrefresh 60
9311 18:05:34.709700 main_disp_path_setup
9312 18:05:34.709785 ovl_layer_smi_id_en
9313 18:05:34.713117 ovl_layer_smi_id_en
9314 18:05:34.713221 ccorr_config
9315 18:05:34.713315 aal_config
9316 18:05:34.716802 gamma_config
9317 18:05:34.716885 postmask_config
9318 18:05:34.720243 dither_config
9319 18:05:34.722990 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9320 18:05:34.730388 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9321 18:05:34.733274 Root Device init finished in 551 msecs
9322 18:05:34.736707 CPU_CLUSTER: 0 init
9323 18:05:34.743620 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9324 18:05:34.747004 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9325 18:05:34.749956 APU_MBOX 0x190000b0 = 0x10001
9326 18:05:34.753429 APU_MBOX 0x190001b0 = 0x10001
9327 18:05:34.756764 APU_MBOX 0x190005b0 = 0x10001
9328 18:05:34.759687 APU_MBOX 0x190006b0 = 0x10001
9329 18:05:34.763403 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9330 18:05:34.776062 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9331 18:05:34.788036 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9332 18:05:34.794542 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9333 18:05:34.806393 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9334 18:05:34.815678 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9335 18:05:34.819335 CPU_CLUSTER: 0 init finished in 81 msecs
9336 18:05:34.822400 Devices initialized
9337 18:05:34.825834 Show all devs... After init.
9338 18:05:34.825928 Root Device: enabled 1
9339 18:05:34.829216 CPU_CLUSTER: 0: enabled 1
9340 18:05:34.832704 CPU: 00: enabled 1
9341 18:05:34.835700 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9342 18:05:34.839122 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9343 18:05:34.842778 ELOG: NV offset 0x57f000 size 0x1000
9344 18:05:34.849022 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9345 18:05:34.855835 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9346 18:05:34.859209 ELOG: Event(17) added with size 13 at 2024-06-11 18:00:51 UTC
9347 18:05:34.862477 out: cmd=0x121: 03 db 21 01 00 00 00 00
9348 18:05:34.865930 in-header: 03 e5 00 00 2c 00 00 00
9349 18:05:34.878903 in-data: 79 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 18:05:34.885339 ELOG: Event(A1) added with size 10 at 2024-06-11 18:00:51 UTC
9351 18:05:34.892315 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9352 18:05:34.898919 ELOG: Event(A0) added with size 9 at 2024-06-11 18:00:51 UTC
9353 18:05:34.902389 elog_add_boot_reason: Logged dev mode boot
9354 18:05:34.905448 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9355 18:05:34.908449 Finalize devices...
9356 18:05:34.908561 Devices finalized
9357 18:05:34.915483 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9358 18:05:34.919116 Writing coreboot table at 0xffe64000
9359 18:05:34.921848 0. 000000000010a000-0000000000113fff: RAMSTAGE
9360 18:05:34.925498 1. 0000000040000000-00000000400fffff: RAM
9361 18:05:34.932163 2. 0000000040100000-000000004032afff: RAMSTAGE
9362 18:05:34.935366 3. 000000004032b000-00000000545fffff: RAM
9363 18:05:34.938931 4. 0000000054600000-000000005465ffff: BL31
9364 18:05:34.941717 5. 0000000054660000-00000000ffe63fff: RAM
9365 18:05:34.948770 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9366 18:05:34.952050 7. 0000000100000000-000000023fffffff: RAM
9367 18:05:34.952163 Passing 5 GPIOs to payload:
9368 18:05:34.958529 NAME | PORT | POLARITY | VALUE
9369 18:05:34.962184 EC in RW | 0x000000aa | low | undefined
9370 18:05:34.968501 EC interrupt | 0x00000005 | low | undefined
9371 18:05:34.971870 TPM interrupt | 0x000000ab | high | undefined
9372 18:05:34.975312 SD card detect | 0x00000011 | high | undefined
9373 18:05:34.981726 speaker enable | 0x00000093 | high | undefined
9374 18:05:34.985395 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9375 18:05:34.988685 in-header: 03 f9 00 00 02 00 00 00
9376 18:05:34.988765 in-data: 02 00
9377 18:05:34.991681 ADC[4]: Raw value=903988 ID=7
9378 18:05:34.995362 ADC[3]: Raw value=213810 ID=1
9379 18:05:34.995478 RAM Code: 0x71
9380 18:05:34.998305 ADC[6]: Raw value=75701 ID=0
9381 18:05:35.001766 ADC[5]: Raw value=213072 ID=1
9382 18:05:35.001854 SKU Code: 0x1
9383 18:05:35.008271 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f641
9384 18:05:35.011568 coreboot table: 964 bytes.
9385 18:05:35.015054 IMD ROOT 0. 0xfffff000 0x00001000
9386 18:05:35.018623 IMD SMALL 1. 0xffffe000 0x00001000
9387 18:05:35.021903 RO MCACHE 2. 0xffffc000 0x00001104
9388 18:05:35.025248 CONSOLE 3. 0xfff7c000 0x00080000
9389 18:05:35.028880 FMAP 4. 0xfff7b000 0x00000452
9390 18:05:35.031736 TIME STAMP 5. 0xfff7a000 0x00000910
9391 18:05:35.035287 VBOOT WORK 6. 0xfff66000 0x00014000
9392 18:05:35.038119 RAMOOPS 7. 0xffe66000 0x00100000
9393 18:05:35.041670 COREBOOT 8. 0xffe64000 0x00002000
9394 18:05:35.041770 IMD small region:
9395 18:05:35.044868 IMD ROOT 0. 0xffffec00 0x00000400
9396 18:05:35.048061 VPD 1. 0xffffeb80 0x0000006c
9397 18:05:35.051689 MMC STATUS 2. 0xffffeb60 0x00000004
9398 18:05:35.058025 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9399 18:05:35.061651 Probing TPM: done!
9400 18:05:35.065232 Connected to device vid:did:rid of 1ae0:0028:00
9401 18:05:35.074803 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9402 18:05:35.078477 Initialized TPM device CR50 revision 0
9403 18:05:35.082452 Checking cr50 for pending updates
9404 18:05:35.085331 Reading cr50 TPM mode
9405 18:05:35.093707 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9406 18:05:35.100146 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9407 18:05:35.140883 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9408 18:05:35.143812 Checking segment from ROM address 0x40100000
9409 18:05:35.147423 Checking segment from ROM address 0x4010001c
9410 18:05:35.153644 Loading segment from ROM address 0x40100000
9411 18:05:35.153737 code (compression=0)
9412 18:05:35.163849 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9413 18:05:35.170870 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9414 18:05:35.170997 it's not compressed!
9415 18:05:35.177301 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9416 18:05:35.181124 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9417 18:05:35.200771 Loading segment from ROM address 0x4010001c
9418 18:05:35.200883 Entry Point 0x80000000
9419 18:05:35.204324 Loaded segments
9420 18:05:35.207866 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9421 18:05:35.214488 Jumping to boot code at 0x80000000(0xffe64000)
9422 18:05:35.220771 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9423 18:05:35.227994 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9424 18:05:35.235058 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9425 18:05:35.238444 Checking segment from ROM address 0x40100000
9426 18:05:35.241994 Checking segment from ROM address 0x4010001c
9427 18:05:35.248781 Loading segment from ROM address 0x40100000
9428 18:05:35.248866 code (compression=1)
9429 18:05:35.255239 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9430 18:05:35.265430 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9431 18:05:35.265540 using LZMA
9432 18:05:35.273692 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9433 18:05:35.280718 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9434 18:05:35.283536 Loading segment from ROM address 0x4010001c
9435 18:05:35.283614 Entry Point 0x54601000
9436 18:05:35.287140 Loaded segments
9437 18:05:35.290479 NOTICE: MT8192 bl31_setup
9438 18:05:35.297411 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9439 18:05:35.300817 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9440 18:05:35.304161 WARNING: region 0:
9441 18:05:35.307671 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 18:05:35.307748 WARNING: region 1:
9443 18:05:35.314016 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9444 18:05:35.317517 WARNING: region 2:
9445 18:05:35.321045 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9446 18:05:35.323997 WARNING: region 3:
9447 18:05:35.327777 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 18:05:35.331079 WARNING: region 4:
9449 18:05:35.337587 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9450 18:05:35.337667 WARNING: region 5:
9451 18:05:35.340910 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 18:05:35.344259 WARNING: region 6:
9453 18:05:35.347311 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 18:05:35.347384 WARNING: region 7:
9455 18:05:35.354566 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 18:05:35.360571 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9457 18:05:35.364426 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9458 18:05:35.367981 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9459 18:05:35.374429 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9460 18:05:35.377661 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9461 18:05:35.380788 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9462 18:05:35.387910 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9463 18:05:35.391378 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9464 18:05:35.394768 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9465 18:05:35.401114 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9466 18:05:35.404663 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9467 18:05:35.408076 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9468 18:05:35.414692 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9469 18:05:35.418180 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9470 18:05:35.424828 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9471 18:05:35.427891 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9472 18:05:35.431305 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9473 18:05:35.437626 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9474 18:05:35.441193 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9475 18:05:35.444793 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9476 18:05:35.450989 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9477 18:05:35.454512 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9478 18:05:35.461738 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9479 18:05:35.464446 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9480 18:05:35.467934 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9481 18:05:35.474906 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9482 18:05:35.478416 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9483 18:05:35.481236 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9484 18:05:35.488017 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9485 18:05:35.491489 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9486 18:05:35.498153 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9487 18:05:35.501837 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9488 18:05:35.505372 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9489 18:05:35.511489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9490 18:05:35.515222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9491 18:05:35.518505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9492 18:05:35.521912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9493 18:05:35.525182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9494 18:05:35.531706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9495 18:05:35.535353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9496 18:05:35.538153 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9497 18:05:35.541715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9498 18:05:35.548216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9499 18:05:35.551768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9500 18:05:35.555254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9501 18:05:35.558501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9502 18:05:35.565136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9503 18:05:35.568409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9504 18:05:35.572175 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9505 18:05:35.578265 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9506 18:05:35.581705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9507 18:05:35.588344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9508 18:05:35.591774 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9509 18:05:35.598598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9510 18:05:35.602174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9511 18:05:35.605351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9512 18:05:35.612039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9513 18:05:35.614883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9514 18:05:35.621758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9515 18:05:35.625229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9516 18:05:35.632102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9517 18:05:35.634950 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9518 18:05:35.638554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9519 18:05:35.644894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9520 18:05:35.648345 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9521 18:05:35.655359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9522 18:05:35.658323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9523 18:05:35.665061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9524 18:05:35.668361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9525 18:05:35.672046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9526 18:05:35.678853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9527 18:05:35.681711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9528 18:05:35.688911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9529 18:05:35.691709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9530 18:05:35.698908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9531 18:05:35.701926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9532 18:05:35.705114 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9533 18:05:35.712031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9534 18:05:35.715452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9535 18:05:35.721883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9536 18:05:35.725182 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9537 18:05:35.732105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9538 18:05:35.735591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9539 18:05:35.738452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9540 18:05:35.745103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9541 18:05:35.748813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9542 18:05:35.755338 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9543 18:05:35.758883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9544 18:05:35.761819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9545 18:05:35.769370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9546 18:05:35.772037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9547 18:05:35.778581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9548 18:05:35.782240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9549 18:05:35.788938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9550 18:05:35.792196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9551 18:05:35.799362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9552 18:05:35.802300 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9553 18:05:35.805949 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9554 18:05:35.809463 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9555 18:05:35.812392 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9556 18:05:35.819425 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9557 18:05:35.822131 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9558 18:05:35.829322 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9559 18:05:35.832936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9560 18:05:35.835657 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9561 18:05:35.842234 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9562 18:05:35.846431 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9563 18:05:35.852249 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9564 18:05:35.855739 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9565 18:05:35.859289 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9566 18:05:35.865881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9567 18:05:35.869690 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9568 18:05:35.872322 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9569 18:05:35.879566 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9570 18:05:35.882495 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9571 18:05:35.889222 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9572 18:05:35.892562 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9573 18:05:35.895815 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9574 18:05:35.902927 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9575 18:05:35.906310 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9576 18:05:35.909381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9577 18:05:35.913081 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9578 18:05:35.916022 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9579 18:05:35.922706 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9580 18:05:35.925944 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9581 18:05:35.929433 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9582 18:05:35.936780 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9583 18:05:35.939413 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9584 18:05:35.946183 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9585 18:05:35.949523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9586 18:05:35.952782 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9587 18:05:35.959442 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9588 18:05:35.963064 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9589 18:05:35.965967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9590 18:05:35.973338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9591 18:05:35.976145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9592 18:05:35.982756 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9593 18:05:35.986259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9594 18:05:35.989862 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9595 18:05:35.996277 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9596 18:05:35.999706 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9597 18:05:36.006336 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9598 18:05:36.009788 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9599 18:05:36.013384 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9600 18:05:36.019929 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9601 18:05:36.023090 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9602 18:05:36.026676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9603 18:05:36.032760 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9604 18:05:36.036419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9605 18:05:36.043196 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9606 18:05:36.046523 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9607 18:05:36.049862 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9608 18:05:36.056243 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9609 18:05:36.059720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9610 18:05:36.063089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9611 18:05:36.069817 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9612 18:05:36.073138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9613 18:05:36.080233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9614 18:05:36.082960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9615 18:05:36.086530 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9616 18:05:36.093189 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9617 18:05:36.096635 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9618 18:05:36.102980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9619 18:05:36.106558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9620 18:05:36.110099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9621 18:05:36.116289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9622 18:05:36.119854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9623 18:05:36.126869 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9624 18:05:36.129935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9625 18:05:36.133042 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9626 18:05:36.139856 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9627 18:05:36.143275 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9628 18:05:36.146001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9629 18:05:36.152642 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9630 18:05:36.156533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9631 18:05:36.163025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9632 18:05:36.165903 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9633 18:05:36.169365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9634 18:05:36.176324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9635 18:05:36.179419 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9636 18:05:36.185944 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9637 18:05:36.189412 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9638 18:05:36.192734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9639 18:05:36.199307 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9640 18:05:36.202856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9641 18:05:36.209003 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9642 18:05:36.212922 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9643 18:05:36.216269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9644 18:05:36.222772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9645 18:05:36.225664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9646 18:05:36.232723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9647 18:05:36.236234 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9648 18:05:36.239272 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9649 18:05:36.246244 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9650 18:05:36.249054 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9651 18:05:36.255692 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9652 18:05:36.259278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9653 18:05:36.265697 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9654 18:05:36.269205 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9655 18:05:36.272733 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9656 18:05:36.279204 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9657 18:05:36.282191 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9658 18:05:36.288855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9659 18:05:36.292324 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9660 18:05:36.295438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9661 18:05:36.302602 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9662 18:05:36.305604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9663 18:05:36.312604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9664 18:05:36.315625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9665 18:05:36.322550 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9666 18:05:36.325273 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9667 18:05:36.328917 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9668 18:05:36.335540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9669 18:05:36.338575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9670 18:05:36.345874 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9671 18:05:36.349078 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9672 18:05:36.352036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9673 18:05:36.358914 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9674 18:05:36.362420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9675 18:05:36.368869 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9676 18:05:36.372474 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9677 18:05:36.375314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9678 18:05:36.382633 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9679 18:05:36.385671 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9680 18:05:36.392051 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9681 18:05:36.395453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9682 18:05:36.401670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9683 18:05:36.405370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9684 18:05:36.408611 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9685 18:05:36.415254 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9686 18:05:36.418554 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9687 18:05:36.422074 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9688 18:05:36.425225 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9689 18:05:36.428328 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9690 18:05:36.435213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9691 18:05:36.438357 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9692 18:05:36.445047 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9693 18:05:36.448877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9694 18:05:36.451685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9695 18:05:36.458742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9696 18:05:36.461479 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9697 18:05:36.468234 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9698 18:05:36.471577 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9699 18:05:36.475256 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9700 18:05:36.481285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9701 18:05:36.484853 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9702 18:05:36.488393 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9703 18:05:36.495095 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9704 18:05:36.497999 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9705 18:05:36.501162 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9706 18:05:36.508057 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9707 18:05:36.511168 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9708 18:05:36.517543 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9709 18:05:36.521321 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9710 18:05:36.524542 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9711 18:05:36.531596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9712 18:05:36.534297 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9713 18:05:36.537927 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9714 18:05:36.544917 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9715 18:05:36.548186 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9716 18:05:36.551473 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9717 18:05:36.557967 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9718 18:05:36.561436 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9719 18:05:36.564641 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9720 18:05:36.571346 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9721 18:05:36.574751 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9722 18:05:36.581350 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9723 18:05:36.584463 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9724 18:05:36.587544 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9725 18:05:36.594027 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9726 18:05:36.597608 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9727 18:05:36.601192 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9728 18:05:36.604265 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9729 18:05:36.607798 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9730 18:05:36.613969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9731 18:05:36.617562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9732 18:05:36.621046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9733 18:05:36.624106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9734 18:05:36.630590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9735 18:05:36.633957 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9736 18:05:36.637346 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9737 18:05:36.644558 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9738 18:05:36.647360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9739 18:05:36.651126 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9740 18:05:36.657573 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9741 18:05:36.660926 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9742 18:05:36.667056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9743 18:05:36.670783 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9744 18:05:36.677569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9745 18:05:36.680801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9746 18:05:36.684240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9747 18:05:36.690930 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9748 18:05:36.693774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9749 18:05:36.697577 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9750 18:05:36.704087 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9751 18:05:36.707788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9752 18:05:36.714183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9753 18:05:36.717575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9754 18:05:36.721239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9755 18:05:36.727178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9756 18:05:36.730679 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9757 18:05:36.737470 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9758 18:05:36.740789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9759 18:05:36.747612 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9760 18:05:36.750551 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9761 18:05:36.754390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9762 18:05:36.760961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9763 18:05:36.763868 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9764 18:05:36.767406 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9765 18:05:36.773614 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9766 18:05:36.777183 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9767 18:05:36.783829 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9768 18:05:36.787317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9769 18:05:36.791242 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9770 18:05:36.797497 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9771 18:05:36.801052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9772 18:05:36.807093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9773 18:05:36.810771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9774 18:05:36.817411 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9775 18:05:36.820716 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9776 18:05:36.823812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9777 18:05:36.830663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9778 18:05:36.833609 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9779 18:05:36.840122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9780 18:05:36.843693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9781 18:05:36.847046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9782 18:05:36.853968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9783 18:05:36.856830 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9784 18:05:36.863332 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9785 18:05:36.866934 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9786 18:05:36.870542 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9787 18:05:36.876998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9788 18:05:36.880826 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9789 18:05:36.887351 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9790 18:05:36.890326 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9791 18:05:36.897344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9792 18:05:36.899989 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9793 18:05:36.903781 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9794 18:05:36.910387 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9795 18:05:36.913863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9796 18:05:36.920400 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9797 18:05:36.923638 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9798 18:05:36.926833 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9799 18:05:36.933704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9800 18:05:36.936976 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9801 18:05:36.940041 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9802 18:05:36.946740 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9803 18:05:36.950439 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9804 18:05:36.957254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9805 18:05:36.959969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9806 18:05:36.966938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9807 18:05:36.969865 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9808 18:05:36.973283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9809 18:05:36.979721 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9810 18:05:36.983306 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9811 18:05:36.989701 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9812 18:05:36.993588 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9813 18:05:37.000023 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9814 18:05:37.002996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9815 18:05:37.006562 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9816 18:05:37.013188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9817 18:05:37.016170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9818 18:05:37.023290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9819 18:05:37.026129 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9820 18:05:37.033366 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9821 18:05:37.036003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9822 18:05:37.042911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9823 18:05:37.046695 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9824 18:05:37.049319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9825 18:05:37.055968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9826 18:05:37.060067 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9827 18:05:37.066449 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9828 18:05:37.069439 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9829 18:05:37.076091 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9830 18:05:37.079678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9831 18:05:37.082736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9832 18:05:37.089167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9833 18:05:37.092751 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9834 18:05:37.099343 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9835 18:05:37.102924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9836 18:05:37.109842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9837 18:05:37.112433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9838 18:05:37.115958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9839 18:05:37.122476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9840 18:05:37.126026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9841 18:05:37.132955 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9842 18:05:37.135601 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9843 18:05:37.142659 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9844 18:05:37.146528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9845 18:05:37.149370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9846 18:05:37.155791 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9847 18:05:37.159445 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9848 18:05:37.165839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9849 18:05:37.169504 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9850 18:05:37.175668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9851 18:05:37.179090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9852 18:05:37.186184 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9853 18:05:37.189170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9854 18:05:37.192506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9855 18:05:37.199370 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9856 18:05:37.202319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9857 18:05:37.209189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9858 18:05:37.212654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9859 18:05:37.216211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9860 18:05:37.222331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9861 18:05:37.225824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9862 18:05:37.232365 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9863 18:05:37.235967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9864 18:05:37.242645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9865 18:05:37.245502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9866 18:05:37.252570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9867 18:05:37.255446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9868 18:05:37.262583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9869 18:05:37.265476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9870 18:05:37.272161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9871 18:05:37.275572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9872 18:05:37.282536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9873 18:05:37.285370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9874 18:05:37.292065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9875 18:05:37.295756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9876 18:05:37.298538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9877 18:05:37.305744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9878 18:05:37.308450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9879 18:05:37.315391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9880 18:05:37.318926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9881 18:05:37.325232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9882 18:05:37.328915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9883 18:05:37.335360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9884 18:05:37.338745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9885 18:05:37.345635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9886 18:05:37.352187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9887 18:05:37.355202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9888 18:05:37.367533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9889 18:05:37.367701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9890 18:05:37.368493 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9891 18:05:37.371583 INFO: [APUAPC] vio 0
9892 18:05:37.374984 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9893 18:05:37.382075 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9894 18:05:37.384932 INFO: [APUAPC] D0_APC_0: 0x400510
9895 18:05:37.388297 INFO: [APUAPC] D0_APC_1: 0x0
9896 18:05:37.392059 INFO: [APUAPC] D0_APC_2: 0x1540
9897 18:05:37.392150 INFO: [APUAPC] D0_APC_3: 0x0
9898 18:05:37.394878 INFO: [APUAPC] D1_APC_0: 0xffffffff
9899 18:05:37.398444 INFO: [APUAPC] D1_APC_1: 0xffffffff
9900 18:05:37.402096 INFO: [APUAPC] D1_APC_2: 0x3fffff
9901 18:05:37.405599 INFO: [APUAPC] D1_APC_3: 0x0
9902 18:05:37.408310 INFO: [APUAPC] D2_APC_0: 0xffffffff
9903 18:05:37.411924 INFO: [APUAPC] D2_APC_1: 0xffffffff
9904 18:05:37.414712 INFO: [APUAPC] D2_APC_2: 0x3fffff
9905 18:05:37.418280 INFO: [APUAPC] D2_APC_3: 0x0
9906 18:05:37.421238 INFO: [APUAPC] D3_APC_0: 0xffffffff
9907 18:05:37.424898 INFO: [APUAPC] D3_APC_1: 0xffffffff
9908 18:05:37.428562 INFO: [APUAPC] D3_APC_2: 0x3fffff
9909 18:05:37.431539 INFO: [APUAPC] D3_APC_3: 0x0
9910 18:05:37.435158 INFO: [APUAPC] D4_APC_0: 0xffffffff
9911 18:05:37.438025 INFO: [APUAPC] D4_APC_1: 0xffffffff
9912 18:05:37.441378 INFO: [APUAPC] D4_APC_2: 0x3fffff
9913 18:05:37.444700 INFO: [APUAPC] D4_APC_3: 0x0
9914 18:05:37.448303 INFO: [APUAPC] D5_APC_0: 0xffffffff
9915 18:05:37.451319 INFO: [APUAPC] D5_APC_1: 0xffffffff
9916 18:05:37.454547 INFO: [APUAPC] D5_APC_2: 0x3fffff
9917 18:05:37.458344 INFO: [APUAPC] D5_APC_3: 0x0
9918 18:05:37.461519 INFO: [APUAPC] D6_APC_0: 0xffffffff
9919 18:05:37.464648 INFO: [APUAPC] D6_APC_1: 0xffffffff
9920 18:05:37.468216 INFO: [APUAPC] D6_APC_2: 0x3fffff
9921 18:05:37.471041 INFO: [APUAPC] D6_APC_3: 0x0
9922 18:05:37.474745 INFO: [APUAPC] D7_APC_0: 0xffffffff
9923 18:05:37.478530 INFO: [APUAPC] D7_APC_1: 0xffffffff
9924 18:05:37.481605 INFO: [APUAPC] D7_APC_2: 0x3fffff
9925 18:05:37.484668 INFO: [APUAPC] D7_APC_3: 0x0
9926 18:05:37.488283 INFO: [APUAPC] D8_APC_0: 0xffffffff
9927 18:05:37.491027 INFO: [APUAPC] D8_APC_1: 0xffffffff
9928 18:05:37.494749 INFO: [APUAPC] D8_APC_2: 0x3fffff
9929 18:05:37.497722 INFO: [APUAPC] D8_APC_3: 0x0
9930 18:05:37.500989 INFO: [APUAPC] D9_APC_0: 0xffffffff
9931 18:05:37.504617 INFO: [APUAPC] D9_APC_1: 0xffffffff
9932 18:05:37.507926 INFO: [APUAPC] D9_APC_2: 0x3fffff
9933 18:05:37.511518 INFO: [APUAPC] D9_APC_3: 0x0
9934 18:05:37.514376 INFO: [APUAPC] D10_APC_0: 0xffffffff
9935 18:05:37.517918 INFO: [APUAPC] D10_APC_1: 0xffffffff
9936 18:05:37.521366 INFO: [APUAPC] D10_APC_2: 0x3fffff
9937 18:05:37.524346 INFO: [APUAPC] D10_APC_3: 0x0
9938 18:05:37.528059 INFO: [APUAPC] D11_APC_0: 0xffffffff
9939 18:05:37.531419 INFO: [APUAPC] D11_APC_1: 0xffffffff
9940 18:05:37.534310 INFO: [APUAPC] D11_APC_2: 0x3fffff
9941 18:05:37.537966 INFO: [APUAPC] D11_APC_3: 0x0
9942 18:05:37.540918 INFO: [APUAPC] D12_APC_0: 0xffffffff
9943 18:05:37.544460 INFO: [APUAPC] D12_APC_1: 0xffffffff
9944 18:05:37.547931 INFO: [APUAPC] D12_APC_2: 0x3fffff
9945 18:05:37.551409 INFO: [APUAPC] D12_APC_3: 0x0
9946 18:05:37.554300 INFO: [APUAPC] D13_APC_0: 0xffffffff
9947 18:05:37.558021 INFO: [APUAPC] D13_APC_1: 0xffffffff
9948 18:05:37.561589 INFO: [APUAPC] D13_APC_2: 0x3fffff
9949 18:05:37.564664 INFO: [APUAPC] D13_APC_3: 0x0
9950 18:05:37.567946 INFO: [APUAPC] D14_APC_0: 0xffffffff
9951 18:05:37.571413 INFO: [APUAPC] D14_APC_1: 0xffffffff
9952 18:05:37.574554 INFO: [APUAPC] D14_APC_2: 0x3fffff
9953 18:05:37.577911 INFO: [APUAPC] D14_APC_3: 0x0
9954 18:05:37.581408 INFO: [APUAPC] D15_APC_0: 0xffffffff
9955 18:05:37.584359 INFO: [APUAPC] D15_APC_1: 0xffffffff
9956 18:05:37.587780 INFO: [APUAPC] D15_APC_2: 0x3fffff
9957 18:05:37.590711 INFO: [APUAPC] D15_APC_3: 0x0
9958 18:05:37.594525 INFO: [APUAPC] APC_CON: 0x4
9959 18:05:37.597354 INFO: [NOCDAPC] D0_APC_0: 0x0
9960 18:05:37.597438 INFO: [NOCDAPC] D0_APC_1: 0x0
9961 18:05:37.601076 INFO: [NOCDAPC] D1_APC_0: 0x0
9962 18:05:37.604175 INFO: [NOCDAPC] D1_APC_1: 0xfff
9963 18:05:37.607612 INFO: [NOCDAPC] D2_APC_0: 0x0
9964 18:05:37.610573 INFO: [NOCDAPC] D2_APC_1: 0xfff
9965 18:05:37.613991 INFO: [NOCDAPC] D3_APC_0: 0x0
9966 18:05:37.617665 INFO: [NOCDAPC] D3_APC_1: 0xfff
9967 18:05:37.620744 INFO: [NOCDAPC] D4_APC_0: 0x0
9968 18:05:37.624199 INFO: [NOCDAPC] D4_APC_1: 0xfff
9969 18:05:37.627221 INFO: [NOCDAPC] D5_APC_0: 0x0
9970 18:05:37.630538 INFO: [NOCDAPC] D5_APC_1: 0xfff
9971 18:05:37.630648 INFO: [NOCDAPC] D6_APC_0: 0x0
9972 18:05:37.634045 INFO: [NOCDAPC] D6_APC_1: 0xfff
9973 18:05:37.637588 INFO: [NOCDAPC] D7_APC_0: 0x0
9974 18:05:37.640426 INFO: [NOCDAPC] D7_APC_1: 0xfff
9975 18:05:37.644252 INFO: [NOCDAPC] D8_APC_0: 0x0
9976 18:05:37.646992 INFO: [NOCDAPC] D8_APC_1: 0xfff
9977 18:05:37.650727 INFO: [NOCDAPC] D9_APC_0: 0x0
9978 18:05:37.654494 INFO: [NOCDAPC] D9_APC_1: 0xfff
9979 18:05:37.657409 INFO: [NOCDAPC] D10_APC_0: 0x0
9980 18:05:37.660323 INFO: [NOCDAPC] D10_APC_1: 0xfff
9981 18:05:37.663759 INFO: [NOCDAPC] D11_APC_0: 0x0
9982 18:05:37.667560 INFO: [NOCDAPC] D11_APC_1: 0xfff
9983 18:05:37.667672 INFO: [NOCDAPC] D12_APC_0: 0x0
9984 18:05:37.670427 INFO: [NOCDAPC] D12_APC_1: 0xfff
9985 18:05:37.674047 INFO: [NOCDAPC] D13_APC_0: 0x0
9986 18:05:37.677716 INFO: [NOCDAPC] D13_APC_1: 0xfff
9987 18:05:37.680530 INFO: [NOCDAPC] D14_APC_0: 0x0
9988 18:05:37.684154 INFO: [NOCDAPC] D14_APC_1: 0xfff
9989 18:05:37.687007 INFO: [NOCDAPC] D15_APC_0: 0x0
9990 18:05:37.690149 INFO: [NOCDAPC] D15_APC_1: 0xfff
9991 18:05:37.693512 INFO: [NOCDAPC] APC_CON: 0x4
9992 18:05:37.697165 INFO: [APUAPC] set_apusys_apc done
9993 18:05:37.701030 INFO: [DEVAPC] devapc_init done
9994 18:05:37.703528 INFO: GICv3 without legacy support detected.
9995 18:05:37.707153 INFO: ARM GICv3 driver initialized in EL3
9996 18:05:37.710083 INFO: Maximum SPI INTID supported: 639
9997 18:05:37.716813 INFO: BL31: Initializing runtime services
9998 18:05:37.720316 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9999 18:05:37.723916 INFO: SPM: enable CPC mode
10000 18:05:37.730776 INFO: mcdi ready for mcusys-off-idle and system suspend
10001 18:05:37.733823 INFO: BL31: Preparing for EL3 exit to normal world
10002 18:05:37.736773 INFO: Entry point address = 0x80000000
10003 18:05:37.740234 INFO: SPSR = 0x8
10004 18:05:37.745600
10005 18:05:37.745709
10006 18:05:37.745802
10007 18:05:37.748648 Starting depthcharge on Spherion...
10008 18:05:37.748754
10009 18:05:37.748844 Wipe memory regions:
10010 18:05:37.748940
10011 18:05:37.749807 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10012 18:05:37.749945 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10013 18:05:37.750055 Setting prompt string to ['asurada:']
10014 18:05:37.750159 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10015 18:05:37.752012 [0x00000040000000, 0x00000054600000)
10016 18:05:37.874377
10017 18:05:37.874518 [0x00000054660000, 0x00000080000000)
10018 18:05:38.134920
10019 18:05:38.135056 [0x000000821a7280, 0x000000ffe64000)
10020 18:05:38.878969
10021 18:05:38.879142 [0x00000100000000, 0x00000240000000)
10022 18:05:40.767022
10023 18:05:40.770379 Initializing XHCI USB controller at 0x11200000.
10024 18:05:41.808945
10025 18:05:41.811499 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10026 18:05:41.811586
10027 18:05:41.811652
10028 18:05:41.811929 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 18:05:41.912246 asurada: tftpboot 192.168.201.1 14291414/tftp-deploy-nsk2g2v5/kernel/image.itb 14291414/tftp-deploy-nsk2g2v5/kernel/cmdline
10031 18:05:41.912438 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 18:05:41.912561 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 18:05:41.916800 tftpboot 192.168.201.1 14291414/tftp-deploy-nsk2g2v5/kernel/image.ittp-deploy-nsk2g2v5/kernel/cmdline
10034 18:05:41.916912
10035 18:05:41.917016 Waiting for link
10036 18:05:42.074723
10037 18:05:42.074860 R8152: Initializing
10038 18:05:42.074932
10039 18:05:42.078268 Version 9 (ocp_data = 6010)
10040 18:05:42.078350
10041 18:05:42.081351 R8152: Done initializing
10042 18:05:42.081423
10043 18:05:42.081484 Adding net device
10044 18:05:43.956907
10045 18:05:43.957068 done.
10046 18:05:43.957140
10047 18:05:43.957204 MAC: 00:e0:4c:78:7a:aa
10048 18:05:43.957266
10049 18:05:43.960431 Sending DHCP discover... done.
10050 18:05:43.960541
10051 18:05:45.934069 Waiting for reply... done.
10052 18:05:45.934204
10053 18:05:45.934275 Sending DHCP request... done.
10054 18:05:45.937414
10055 18:05:45.937507 Waiting for reply... done.
10056 18:05:45.937574
10057 18:05:45.940909 My ip is 192.168.201.12
10058 18:05:45.940993
10059 18:05:45.944307 The DHCP server ip is 192.168.201.1
10060 18:05:45.944401
10061 18:05:45.947549 TFTP server IP predefined by user: 192.168.201.1
10062 18:05:45.947629
10063 18:05:45.954369 Bootfile predefined by user: 14291414/tftp-deploy-nsk2g2v5/kernel/image.itb
10064 18:05:45.954456
10065 18:05:45.957461 Sending tftp read request... done.
10066 18:05:45.957543
10067 18:05:45.960627 Waiting for the transfer...
10068 18:05:45.960723
10069 18:05:46.216863 00000000 ################################################################
10070 18:05:46.217020
10071 18:05:46.466060 00080000 ################################################################
10072 18:05:46.466225
10073 18:05:46.710840 00100000 ################################################################
10074 18:05:46.710979
10075 18:05:46.957458 00180000 ################################################################
10076 18:05:46.957628
10077 18:05:47.206940 00200000 ################################################################
10078 18:05:47.207074
10079 18:05:47.460082 00280000 ################################################################
10080 18:05:47.460251
10081 18:05:47.715153 00300000 ################################################################
10082 18:05:47.715285
10083 18:05:47.978136 00380000 ################################################################
10084 18:05:47.978302
10085 18:05:48.230451 00400000 ################################################################
10086 18:05:48.230591
10087 18:05:48.484039 00480000 ################################################################
10088 18:05:48.484210
10089 18:05:48.760790 00500000 ################################################################
10090 18:05:48.760931
10091 18:05:49.009177 00580000 ################################################################
10092 18:05:49.009315
10093 18:05:49.258021 00600000 ################################################################
10094 18:05:49.258168
10095 18:05:49.502345 00680000 ################################################################
10096 18:05:49.502488
10097 18:05:49.750399 00700000 ################################################################
10098 18:05:49.750534
10099 18:05:49.997453 00780000 ################################################################
10100 18:05:49.997615
10101 18:05:50.242915 00800000 ################################################################
10102 18:05:50.243050
10103 18:05:50.485278 00880000 ################################################################
10104 18:05:50.485409
10105 18:05:50.734906 00900000 ################################################################
10106 18:05:50.735083
10107 18:05:50.995139 00980000 ################################################################
10108 18:05:50.995278
10109 18:05:51.249988 00a00000 ################################################################
10110 18:05:51.250152
10111 18:05:51.495248 00a80000 ################################################################
10112 18:05:51.495396
10113 18:05:51.742569 00b00000 ################################################################
10114 18:05:51.742702
10115 18:05:51.997132 00b80000 ################################################################
10116 18:05:51.997269
10117 18:05:52.242575 00c00000 ################################################################
10118 18:05:52.242712
10119 18:05:52.492948 00c80000 ################################################################
10120 18:05:52.493083
10121 18:05:52.750043 00d00000 ################################################################
10122 18:05:52.750188
10123 18:05:53.007348 00d80000 ################################################################
10124 18:05:53.007525
10125 18:05:53.283704 00e00000 ################################################################
10126 18:05:53.283842
10127 18:05:53.551749 00e80000 ################################################################
10128 18:05:53.551910
10129 18:05:53.812977 00f00000 ################################################################
10130 18:05:53.813153
10131 18:05:54.075508 00f80000 ################################################################
10132 18:05:54.075677
10133 18:05:54.329587 01000000 ################################################################
10134 18:05:54.329766
10135 18:05:54.577006 01080000 ################################################################
10136 18:05:54.577180
10137 18:05:54.828154 01100000 ################################################################
10138 18:05:54.828330
10139 18:05:55.076512 01180000 ################################################################
10140 18:05:55.076675
10141 18:05:55.317727 01200000 ################################################################
10142 18:05:55.317861
10143 18:05:55.565047 01280000 ################################################################
10144 18:05:55.565190
10145 18:05:55.815649 01300000 ################################################################
10146 18:05:55.815786
10147 18:05:56.059889 01380000 ################################################################
10148 18:05:56.060027
10149 18:05:56.306681 01400000 ################################################################
10150 18:05:56.306856
10151 18:05:56.550320 01480000 ################################################################
10152 18:05:56.550525
10153 18:05:56.794049 01500000 ################################################################
10154 18:05:56.794201
10155 18:05:57.038833 01580000 ################################################################
10156 18:05:57.039035
10157 18:05:57.284437 01600000 ################################################################
10158 18:05:57.284598
10159 18:05:57.528965 01680000 ################################################################
10160 18:05:57.529124
10161 18:05:57.783868 01700000 ################################################################
10162 18:05:57.784039
10163 18:05:58.042514 01780000 ################################################################
10164 18:05:58.042682
10165 18:05:58.298305 01800000 ################################################################
10166 18:05:58.298457
10167 18:05:58.540348 01880000 ################################################################
10168 18:05:58.540483
10169 18:05:58.794168 01900000 ################################################################
10170 18:05:58.794332
10171 18:05:59.067290 01980000 ################################################################
10172 18:05:59.067454
10173 18:05:59.326088 01a00000 ################################################################
10174 18:05:59.326254
10175 18:05:59.584493 01a80000 ################################################################
10176 18:05:59.584660
10177 18:05:59.843216 01b00000 ################################################################
10178 18:05:59.843362
10179 18:06:00.109214 01b80000 ################################################################
10180 18:06:00.109350
10181 18:06:00.368377 01c00000 ################################################################
10182 18:06:00.368566
10183 18:06:00.623418 01c80000 ################################################################
10184 18:06:00.623553
10185 18:06:00.890312 01d00000 ################################################################
10186 18:06:00.890458
10187 18:06:01.147667 01d80000 ################################################################
10188 18:06:01.147817
10189 18:06:01.403443 01e00000 ################################################################
10190 18:06:01.403572
10191 18:06:01.661425 01e80000 ################################################################
10192 18:06:01.661559
10193 18:06:01.920319 01f00000 ################################################################
10194 18:06:01.920463
10195 18:06:02.172438 01f80000 ################################################################
10196 18:06:02.172578
10197 18:06:02.428668 02000000 ################################################################
10198 18:06:02.428847
10199 18:06:02.648958 02080000 ########################################################## done.
10200 18:06:02.649089
10201 18:06:02.651762 The bootfile was 34550730 bytes long.
10202 18:06:02.651839
10203 18:06:02.655409 Sending tftp read request... done.
10204 18:06:02.655496
10205 18:06:02.658299 Waiting for the transfer...
10206 18:06:02.658387
10207 18:06:02.661993 00000000 # done.
10208 18:06:02.662080
10209 18:06:02.668285 Command line loaded dynamically from TFTP file: 14291414/tftp-deploy-nsk2g2v5/kernel/cmdline
10210 18:06:02.668392
10211 18:06:02.681583 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10212 18:06:02.681685
10213 18:06:02.681751 Loading FIT.
10214 18:06:02.681813
10215 18:06:02.685022 Image ramdisk-1 has 21376335 bytes.
10216 18:06:02.685111
10217 18:06:02.688289 Image fdt-1 has 47258 bytes.
10218 18:06:02.688390
10219 18:06:02.691696 Image kernel-1 has 13125101 bytes.
10220 18:06:02.691782
10221 18:06:02.701573 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10222 18:06:02.701661
10223 18:06:02.718507 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10224 18:06:02.718639
10225 18:06:02.725035 Choosing best match conf-1 for compat google,spherion-rev2.
10226 18:06:02.725131
10227 18:06:02.732985 Connected to device vid:did:rid of 1ae0:0028:00
10228 18:06:02.740903
10229 18:06:02.744474 tpm_get_response: command 0x17b, return code 0x0
10230 18:06:02.744563
10231 18:06:02.747080 ec_init: CrosEC protocol v3 supported (256, 248)
10232 18:06:02.751114
10233 18:06:02.754673 tpm_cleanup: add release locality here.
10234 18:06:02.754753
10235 18:06:02.754818 Shutting down all USB controllers.
10236 18:06:02.758298
10237 18:06:02.758383 Removing current net device
10238 18:06:02.758470
10239 18:06:02.764778 Exiting depthcharge with code 4 at timestamp: 54315742
10240 18:06:02.764865
10241 18:06:02.768451 LZMA decompressing kernel-1 to 0x821a6718
10242 18:06:02.768538
10243 18:06:02.771222 LZMA decompressing kernel-1 to 0x40000000
10244 18:06:04.388840
10245 18:06:04.389026 jumping to kernel
10246 18:06:04.389827 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10247 18:06:04.390143 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10248 18:06:04.390281 Setting prompt string to ['Linux version [0-9]']
10249 18:06:04.390456 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10250 18:06:04.390583 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10251 18:06:04.470667
10252 18:06:04.473879 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10253 18:06:04.477275 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10254 18:06:04.477385 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10255 18:06:04.477460 Setting prompt string to []
10256 18:06:04.477543 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10257 18:06:04.477619 Using line separator: #'\n'#
10258 18:06:04.477680 No login prompt set.
10259 18:06:04.477757 Parsing kernel messages
10260 18:06:04.477815 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10261 18:06:04.477926 [login-action] Waiting for messages, (timeout 00:03:58)
10262 18:06:04.477994 Waiting using forced prompt support (timeout 00:01:59)
10263 18:06:04.497252 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10264 18:06:04.500097 [ 0.000000] random: crng init done
10265 18:06:04.507129 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10266 18:06:04.510825 [ 0.000000] efi: UEFI not found.
10267 18:06:04.516921 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10268 18:06:04.523252 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10269 18:06:04.533774 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10270 18:06:04.543721 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10271 18:06:04.549699 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10272 18:06:04.556209 [ 0.000000] printk: bootconsole [mtk8250] enabled
10273 18:06:04.563416 [ 0.000000] NUMA: No NUMA configuration found
10274 18:06:04.569570 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10275 18:06:04.573124 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10276 18:06:04.576031 [ 0.000000] Zone ranges:
10277 18:06:04.583327 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10278 18:06:04.586075 [ 0.000000] DMA32 empty
10279 18:06:04.592715 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10280 18:06:04.596133 [ 0.000000] Movable zone start for each node
10281 18:06:04.599743 [ 0.000000] Early memory node ranges
10282 18:06:04.606033 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10283 18:06:04.613102 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10284 18:06:04.619584 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10285 18:06:04.625879 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10286 18:06:04.632361 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10287 18:06:04.639236 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10288 18:06:04.695294 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10289 18:06:04.701633 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10290 18:06:04.708283 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10291 18:06:04.711709 [ 0.000000] psci: probing for conduit method from DT.
10292 18:06:04.718412 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10293 18:06:04.721511 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10294 18:06:04.728359 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10295 18:06:04.731894 [ 0.000000] psci: SMC Calling Convention v1.2
10296 18:06:04.738149 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10297 18:06:04.741654 [ 0.000000] Detected VIPT I-cache on CPU0
10298 18:06:04.747956 [ 0.000000] CPU features: detected: GIC system register CPU interface
10299 18:06:04.755003 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10300 18:06:04.761240 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10301 18:06:04.768288 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10302 18:06:04.774938 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10303 18:06:04.784846 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10304 18:06:04.787934 [ 0.000000] alternatives: applying boot alternatives
10305 18:06:04.794218 [ 0.000000] Fallback order for Node 0: 0
10306 18:06:04.800903 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10307 18:06:04.804639 [ 0.000000] Policy zone: Normal
10308 18:06:04.817298 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10309 18:06:04.827697 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10310 18:06:04.839633 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10311 18:06:04.849595 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10312 18:06:04.855890 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10313 18:06:04.859353 <6>[ 0.000000] software IO TLB: area num 8.
10314 18:06:04.916280 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10315 18:06:05.066048 <6>[ 0.000000] Memory: 7943188K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 409580K reserved, 32768K cma-reserved)
10316 18:06:05.072227 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10317 18:06:05.079155 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10318 18:06:05.082025 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10319 18:06:05.088603 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10320 18:06:05.095706 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10321 18:06:05.098515 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10322 18:06:05.108485 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10323 18:06:05.115576 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10324 18:06:05.121868 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10325 18:06:05.128245 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10326 18:06:05.131648 <6>[ 0.000000] GICv3: 608 SPIs implemented
10327 18:06:05.135630 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10328 18:06:05.142002 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10329 18:06:05.145474 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10330 18:06:05.151816 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10331 18:06:05.164683 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10332 18:06:05.177902 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10333 18:06:05.184872 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10334 18:06:05.192010 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10335 18:06:05.205323 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10336 18:06:05.211625 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10337 18:06:05.218626 <6>[ 0.009183] Console: colour dummy device 80x25
10338 18:06:05.228663 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10339 18:06:05.234967 <6>[ 0.024447] pid_max: default: 32768 minimum: 301
10340 18:06:05.238376 <6>[ 0.029320] LSM: Security Framework initializing
10341 18:06:05.245178 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10342 18:06:05.255333 <6>[ 0.042034] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10343 18:06:05.265232 <6>[ 0.051451] cblist_init_generic: Setting adjustable number of callback queues.
10344 18:06:05.267960 <6>[ 0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.
10345 18:06:05.277876 <6>[ 0.065272] cblist_init_generic: Setting adjustable number of callback queues.
10346 18:06:05.284899 <6>[ 0.072699] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 18:06:05.288219 <6>[ 0.079097] rcu: Hierarchical SRCU implementation.
10348 18:06:05.294387 <6>[ 0.084112] rcu: Max phase no-delay instances is 1000.
10349 18:06:05.301347 <6>[ 0.091134] EFI services will not be available.
10350 18:06:05.304663 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10351 18:06:05.313346 <6>[ 0.101171] Detected VIPT I-cache on CPU1
10352 18:06:05.319705 <6>[ 0.101232] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10353 18:06:05.326507 <6>[ 0.101258] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10354 18:06:05.329570 <6>[ 0.101567] Detected VIPT I-cache on CPU2
10355 18:06:05.336022 <6>[ 0.101613] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10356 18:06:05.345688 <6>[ 0.101630] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10357 18:06:05.349760 <6>[ 0.101882] Detected VIPT I-cache on CPU3
10358 18:06:05.355856 <6>[ 0.101929] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10359 18:06:05.363001 <6>[ 0.101943] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10360 18:06:05.365851 <6>[ 0.102246] CPU features: detected: Spectre-v4
10361 18:06:05.372425 <6>[ 0.102252] CPU features: detected: Spectre-BHB
10362 18:06:05.375924 <6>[ 0.102256] Detected PIPT I-cache on CPU4
10363 18:06:05.382077 <6>[ 0.102315] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10364 18:06:05.389325 <6>[ 0.102331] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10365 18:06:05.395201 <6>[ 0.102622] Detected PIPT I-cache on CPU5
10366 18:06:05.402247 <6>[ 0.102685] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10367 18:06:05.408885 <6>[ 0.102701] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10368 18:06:05.412446 <6>[ 0.102981] Detected PIPT I-cache on CPU6
10369 18:06:05.418798 <6>[ 0.103044] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10370 18:06:05.425064 <6>[ 0.103060] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10371 18:06:05.432317 <6>[ 0.103355] Detected PIPT I-cache on CPU7
10372 18:06:05.438278 <6>[ 0.103419] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10373 18:06:05.445370 <6>[ 0.103435] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10374 18:06:05.448198 <6>[ 0.103482] smp: Brought up 1 node, 8 CPUs
10375 18:06:05.455383 <6>[ 0.244833] SMP: Total of 8 processors activated.
10376 18:06:05.458140 <6>[ 0.249784] CPU features: detected: 32-bit EL0 Support
10377 18:06:05.468476 <6>[ 0.255148] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10378 18:06:05.474929 <6>[ 0.263948] CPU features: detected: Common not Private translations
10379 18:06:05.481369 <6>[ 0.270464] CPU features: detected: CRC32 instructions
10380 18:06:05.484697 <6>[ 0.275849] CPU features: detected: RCpc load-acquire (LDAPR)
10381 18:06:05.491692 <6>[ 0.281809] CPU features: detected: LSE atomic instructions
10382 18:06:05.497995 <6>[ 0.287591] CPU features: detected: Privileged Access Never
10383 18:06:05.505008 <6>[ 0.293406] CPU features: detected: RAS Extension Support
10384 18:06:05.511448 <6>[ 0.299015] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10385 18:06:05.514995 <6>[ 0.306236] CPU: All CPU(s) started at EL2
10386 18:06:05.521037 <6>[ 0.310580] alternatives: applying system-wide alternatives
10387 18:06:05.530425 <6>[ 0.321414] devtmpfs: initialized
10388 18:06:05.545983 <6>[ 0.330334] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10389 18:06:05.553282 <6>[ 0.340294] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10390 18:06:05.559382 <6>[ 0.348310] pinctrl core: initialized pinctrl subsystem
10391 18:06:05.562873 <6>[ 0.354993] DMI not present or invalid.
10392 18:06:05.569734 <6>[ 0.359409] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10393 18:06:05.579598 <6>[ 0.366265] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10394 18:06:05.586105 <6>[ 0.373858] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10395 18:06:05.596456 <6>[ 0.382078] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10396 18:06:05.599361 <6>[ 0.390320] audit: initializing netlink subsys (disabled)
10397 18:06:05.609340 <5>[ 0.396016] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10398 18:06:05.615609 <6>[ 0.396737] thermal_sys: Registered thermal governor 'step_wise'
10399 18:06:05.622832 <6>[ 0.403981] thermal_sys: Registered thermal governor 'power_allocator'
10400 18:06:05.625646 <6>[ 0.410235] cpuidle: using governor menu
10401 18:06:05.632004 <6>[ 0.421198] NET: Registered PF_QIPCRTR protocol family
10402 18:06:05.638595 <6>[ 0.426676] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10403 18:06:05.645628 <6>[ 0.433779] ASID allocator initialised with 32768 entries
10404 18:06:05.648717 <6>[ 0.440366] Serial: AMBA PL011 UART driver
10405 18:06:05.658687 <4>[ 0.449240] Trying to register duplicate clock ID: 134
10406 18:06:05.718436 <6>[ 0.512496] KASLR enabled
10407 18:06:05.732901 <6>[ 0.520191] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10408 18:06:05.739392 <6>[ 0.527203] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10409 18:06:05.746229 <6>[ 0.533691] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10410 18:06:05.752874 <6>[ 0.540696] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10411 18:06:05.759686 <6>[ 0.547181] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10412 18:06:05.765678 <6>[ 0.554187] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10413 18:06:05.772768 <6>[ 0.560675] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10414 18:06:05.779129 <6>[ 0.567680] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10415 18:06:05.782408 <6>[ 0.575152] ACPI: Interpreter disabled.
10416 18:06:05.791116 <6>[ 0.581586] iommu: Default domain type: Translated
10417 18:06:05.797568 <6>[ 0.586738] iommu: DMA domain TLB invalidation policy: strict mode
10418 18:06:05.801235 <5>[ 0.593397] SCSI subsystem initialized
10419 18:06:05.807980 <6>[ 0.597645] usbcore: registered new interface driver usbfs
10420 18:06:05.814579 <6>[ 0.603377] usbcore: registered new interface driver hub
10421 18:06:05.817409 <6>[ 0.608929] usbcore: registered new device driver usb
10422 18:06:05.824721 <6>[ 0.615046] pps_core: LinuxPPS API ver. 1 registered
10423 18:06:05.834021 <6>[ 0.620238] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10424 18:06:05.837528 <6>[ 0.629583] PTP clock support registered
10425 18:06:05.841095 <6>[ 0.633824] EDAC MC: Ver: 3.0.0
10426 18:06:05.848369 <6>[ 0.638984] FPGA manager framework
10427 18:06:05.851776 <6>[ 0.642660] Advanced Linux Sound Architecture Driver Initialized.
10428 18:06:05.855181 <6>[ 0.649444] vgaarb: loaded
10429 18:06:05.862261 <6>[ 0.652582] clocksource: Switched to clocksource arch_sys_counter
10430 18:06:05.868915 <5>[ 0.659027] VFS: Disk quotas dquot_6.6.0
10431 18:06:05.875508 <6>[ 0.663216] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10432 18:06:05.879031 <6>[ 0.670405] pnp: PnP ACPI: disabled
10433 18:06:05.886874 <6>[ 0.677147] NET: Registered PF_INET protocol family
10434 18:06:05.896546 <6>[ 0.682736] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10435 18:06:05.907933 <6>[ 0.695057] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10436 18:06:05.917561 <6>[ 0.703873] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10437 18:06:05.924672 <6>[ 0.711843] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10438 18:06:05.931024 <6>[ 0.720543] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10439 18:06:05.943127 <6>[ 0.730294] TCP: Hash tables configured (established 65536 bind 65536)
10440 18:06:05.949486 <6>[ 0.737164] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10441 18:06:05.955885 <6>[ 0.744361] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10442 18:06:05.962703 <6>[ 0.752069] NET: Registered PF_UNIX/PF_LOCAL protocol family
10443 18:06:05.969209 <6>[ 0.758215] RPC: Registered named UNIX socket transport module.
10444 18:06:05.972625 <6>[ 0.764369] RPC: Registered udp transport module.
10445 18:06:05.979040 <6>[ 0.769302] RPC: Registered tcp transport module.
10446 18:06:05.985660 <6>[ 0.774233] RPC: Registered tcp NFSv4.1 backchannel transport module.
10447 18:06:05.988988 <6>[ 0.780900] PCI: CLS 0 bytes, default 64
10448 18:06:05.992449 <6>[ 0.785270] Unpacking initramfs...
10449 18:06:06.002332 <6>[ 0.788992] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10450 18:06:06.008994 <6>[ 0.797621] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10451 18:06:06.016049 <6>[ 0.806414] kvm [1]: IPA Size Limit: 40 bits
10452 18:06:06.019215 <6>[ 0.810942] kvm [1]: GICv3: no GICV resource entry
10453 18:06:06.025931 <6>[ 0.815962] kvm [1]: disabling GICv2 emulation
10454 18:06:06.032061 <6>[ 0.820650] kvm [1]: GIC system register CPU interface enabled
10455 18:06:06.035556 <6>[ 0.826816] kvm [1]: vgic interrupt IRQ18
10456 18:06:06.041986 <6>[ 0.831191] kvm [1]: VHE mode initialized successfully
10457 18:06:06.045748 <5>[ 0.837647] Initialise system trusted keyrings
10458 18:06:06.051923 <6>[ 0.842416] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10459 18:06:06.061696 <6>[ 0.852408] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10460 18:06:06.068291 <5>[ 0.858775] NFS: Registering the id_resolver key type
10461 18:06:06.071894 <5>[ 0.864081] Key type id_resolver registered
10462 18:06:06.078365 <5>[ 0.868497] Key type id_legacy registered
10463 18:06:06.085263 <6>[ 0.872775] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10464 18:06:06.091318 <6>[ 0.879699] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10465 18:06:06.097835 <6>[ 0.887414] 9p: Installing v9fs 9p2000 file system support
10466 18:06:06.135440 <5>[ 0.925817] Key type asymmetric registered
10467 18:06:06.138541 <5>[ 0.930152] Asymmetric key parser 'x509' registered
10468 18:06:06.148267 <6>[ 0.935287] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10469 18:06:06.151684 <6>[ 0.942903] io scheduler mq-deadline registered
10470 18:06:06.155265 <6>[ 0.947665] io scheduler kyber registered
10471 18:06:06.174140 <6>[ 0.964605] EINJ: ACPI disabled.
10472 18:06:06.206169 <4>[ 0.990470] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10473 18:06:06.216095 <4>[ 1.001088] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10474 18:06:06.230979 <6>[ 1.021926] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10475 18:06:06.238867 <6>[ 1.029890] printk: console [ttyS0] disabled
10476 18:06:06.266994 <6>[ 1.054518] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10477 18:06:06.274204 <6>[ 1.064001] printk: console [ttyS0] enabled
10478 18:06:06.277168 <6>[ 1.064001] printk: console [ttyS0] enabled
10479 18:06:06.283889 <6>[ 1.072893] printk: bootconsole [mtk8250] disabled
10480 18:06:06.286792 <6>[ 1.072893] printk: bootconsole [mtk8250] disabled
10481 18:06:06.294045 <6>[ 1.083889] SuperH (H)SCI(F) driver initialized
10482 18:06:06.296960 <6>[ 1.089175] msm_serial: driver initialized
10483 18:06:06.310424 <6>[ 1.098062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10484 18:06:06.320625 <6>[ 1.106606] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10485 18:06:06.326991 <6>[ 1.115148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10486 18:06:06.337102 <6>[ 1.123776] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10487 18:06:06.346972 <6>[ 1.132482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10488 18:06:06.354158 <6>[ 1.141198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10489 18:06:06.363652 <6>[ 1.149746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10490 18:06:06.370675 <6>[ 1.158542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10491 18:06:06.380498 <6>[ 1.167086] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10492 18:06:06.392451 <6>[ 1.182751] loop: module loaded
10493 18:06:06.399141 <6>[ 1.188646] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10494 18:06:06.420928 <4>[ 1.211879] mtk-pmic-keys: Failed to locate of_node [id: -1]
10495 18:06:06.427982 <6>[ 1.218708] megasas: 07.719.03.00-rc1
10496 18:06:06.437563 <6>[ 1.228263] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10497 18:06:06.445632 <6>[ 1.235957] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10498 18:06:06.462037 <6>[ 1.252408] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10499 18:06:06.517523 <6>[ 1.301874] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10500 18:06:06.896204 <6>[ 1.687259] Freeing initrd memory: 20868K
10501 18:06:06.912776 <6>[ 1.703166] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10502 18:06:06.923793 <6>[ 1.714335] tun: Universal TUN/TAP device driver, 1.6
10503 18:06:06.927080 <6>[ 1.720413] thunder_xcv, ver 1.0
10504 18:06:06.930321 <6>[ 1.723916] thunder_bgx, ver 1.0
10505 18:06:06.933624 <6>[ 1.727416] nicpf, ver 1.0
10506 18:06:06.944275 <6>[ 1.731448] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10507 18:06:06.947246 <6>[ 1.738924] hns3: Copyright (c) 2017 Huawei Corporation.
10508 18:06:06.950929 <6>[ 1.744513] hclge is initializing
10509 18:06:06.957340 <6>[ 1.748094] e1000: Intel(R) PRO/1000 Network Driver
10510 18:06:06.964317 <6>[ 1.753223] e1000: Copyright (c) 1999-2006 Intel Corporation.
10511 18:06:06.967181 <6>[ 1.759239] e1000e: Intel(R) PRO/1000 Network Driver
10512 18:06:06.974218 <6>[ 1.764455] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10513 18:06:06.980701 <6>[ 1.770640] igb: Intel(R) Gigabit Ethernet Network Driver
10514 18:06:06.987629 <6>[ 1.776289] igb: Copyright (c) 2007-2014 Intel Corporation.
10515 18:06:06.993897 <6>[ 1.782126] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10516 18:06:06.997355 <6>[ 1.788643] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10517 18:06:07.004168 <6>[ 1.795107] sky2: driver version 1.30
10518 18:06:07.011000 <6>[ 1.800037] usbcore: registered new device driver r8152-cfgselector
10519 18:06:07.017639 <6>[ 1.806575] usbcore: registered new interface driver r8152
10520 18:06:07.021225 <6>[ 1.812394] VFIO - User Level meta-driver version: 0.3
10521 18:06:07.029978 <6>[ 1.820645] usbcore: registered new interface driver usb-storage
10522 18:06:07.036317 <6>[ 1.827091] usbcore: registered new device driver onboard-usb-hub
10523 18:06:07.045480 <6>[ 1.836270] mt6397-rtc mt6359-rtc: registered as rtc0
10524 18:06:07.055106 <6>[ 1.841738] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:01:23 UTC (1718128883)
10525 18:06:07.058471 <6>[ 1.851305] i2c_dev: i2c /dev entries driver
10526 18:06:07.072899 <4>[ 1.863461] cpu cpu0: supply cpu not found, using dummy regulator
10527 18:06:07.079266 <4>[ 1.869888] cpu cpu1: supply cpu not found, using dummy regulator
10528 18:06:07.085835 <4>[ 1.876311] cpu cpu2: supply cpu not found, using dummy regulator
10529 18:06:07.092974 <4>[ 1.882715] cpu cpu3: supply cpu not found, using dummy regulator
10530 18:06:07.099468 <4>[ 1.889112] cpu cpu4: supply cpu not found, using dummy regulator
10531 18:06:07.106575 <4>[ 1.895513] cpu cpu5: supply cpu not found, using dummy regulator
10532 18:06:07.112726 <4>[ 1.901932] cpu cpu6: supply cpu not found, using dummy regulator
10533 18:06:07.119142 <4>[ 1.908334] cpu cpu7: supply cpu not found, using dummy regulator
10534 18:06:07.138477 <6>[ 1.928987] cpu cpu0: EM: created perf domain
10535 18:06:07.141813 <6>[ 1.933925] cpu cpu4: EM: created perf domain
10536 18:06:07.148852 <6>[ 1.939554] sdhci: Secure Digital Host Controller Interface driver
10537 18:06:07.155388 <6>[ 1.945988] sdhci: Copyright(c) Pierre Ossman
10538 18:06:07.162249 <6>[ 1.950945] Synopsys Designware Multimedia Card Interface Driver
10539 18:06:07.169159 <6>[ 1.957587] sdhci-pltfm: SDHCI platform and OF driver helper
10540 18:06:07.172213 <6>[ 1.957645] mmc0: CQHCI version 5.10
10541 18:06:07.178901 <6>[ 1.967610] ledtrig-cpu: registered to indicate activity on CPUs
10542 18:06:07.185289 <6>[ 1.974742] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10543 18:06:07.192233 <6>[ 1.981800] usbcore: registered new interface driver usbhid
10544 18:06:07.195841 <6>[ 1.987621] usbhid: USB HID core driver
10545 18:06:07.202400 <6>[ 1.991809] spi_master spi0: will run message pump with realtime priority
10546 18:06:07.248671 <6>[ 2.032736] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10547 18:06:07.267816 <6>[ 2.048357] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10548 18:06:07.274228 <6>[ 2.062896] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10549 18:06:07.277739 <6>[ 2.063292] cros-ec-spi spi0.0: Chrome EC device registered
10550 18:06:07.285165 <6>[ 2.074997] mmc0: Command Queue Engine enabled
10551 18:06:07.291676 <6>[ 2.079745] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10552 18:06:07.298415 <6>[ 2.087770] mmcblk0: mmc0:0001 DA4128 116 GiB
10553 18:06:07.304633 <6>[ 2.087953] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10554 18:06:07.311364 <6>[ 2.096810] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10555 18:06:07.318351 <6>[ 2.102860] NET: Registered PF_PACKET protocol family
10556 18:06:07.321209 <6>[ 2.108887] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 18:06:07.328336 <6>[ 2.113112] 9pnet: Installing 9P2000 support
10558 18:06:07.331301 <6>[ 2.118912] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10559 18:06:07.337960 <5>[ 2.122807] Key type dns_resolver registered
10560 18:06:07.344404 <6>[ 2.128711] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10561 18:06:07.348130 <6>[ 2.133068] registered taskstats version 1
10562 18:06:07.351596 <5>[ 2.143397] Loading compiled-in X.509 certificates
10563 18:06:07.381225 <4>[ 2.165378] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 18:06:07.391048 <4>[ 2.176084] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 18:06:07.404850 <6>[ 2.195849] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10566 18:06:07.412249 <6>[ 2.202658] xhci-mtk 11200000.usb: xHCI Host Controller
10567 18:06:07.418291 <6>[ 2.208161] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10568 18:06:07.428277 <6>[ 2.216019] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10569 18:06:07.435285 <6>[ 2.225453] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10570 18:06:07.442019 <6>[ 2.231663] xhci-mtk 11200000.usb: xHCI Host Controller
10571 18:06:07.448662 <6>[ 2.237163] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10572 18:06:07.455107 <6>[ 2.244821] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10573 18:06:07.462083 <6>[ 2.252711] hub 1-0:1.0: USB hub found
10574 18:06:07.465000 <6>[ 2.256733] hub 1-0:1.0: 1 port detected
10575 18:06:07.472378 <6>[ 2.261007] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10576 18:06:07.479278 <6>[ 2.269757] hub 2-0:1.0: USB hub found
10577 18:06:07.481914 <6>[ 2.273777] hub 2-0:1.0: 1 port detected
10578 18:06:07.491063 <6>[ 2.281563] mtk-msdc 11f70000.mmc: Got CD GPIO
10579 18:06:07.508470 <6>[ 2.295941] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10580 18:06:07.518395 <6>[ 2.304313] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10581 18:06:07.525331 <6>[ 2.312658] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10582 18:06:07.535057 <6>[ 2.320996] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10583 18:06:07.541766 <6>[ 2.329334] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10584 18:06:07.551694 <6>[ 2.337672] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10585 18:06:07.558094 <6>[ 2.346013] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10586 18:06:07.567747 <6>[ 2.354353] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10587 18:06:07.574908 <6>[ 2.362690] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10588 18:06:07.584764 <6>[ 2.371030] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10589 18:06:07.591274 <6>[ 2.379368] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10590 18:06:07.601473 <6>[ 2.387714] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10591 18:06:07.607553 <6>[ 2.396052] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10592 18:06:07.617914 <6>[ 2.404390] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10593 18:06:07.624424 <6>[ 2.412729] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10594 18:06:07.630765 <6>[ 2.421417] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10595 18:06:07.637793 <6>[ 2.428583] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10596 18:06:07.644536 <6>[ 2.435370] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10597 18:06:07.654423 <6>[ 2.442133] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10598 18:06:07.661439 <6>[ 2.449108] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10599 18:06:07.667991 <6>[ 2.455964] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10600 18:06:07.678421 <6>[ 2.465096] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10601 18:06:07.687461 <6>[ 2.474215] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10602 18:06:07.697323 <6>[ 2.483509] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10603 18:06:07.707144 <6>[ 2.492976] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10604 18:06:07.717407 <6>[ 2.502446] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10605 18:06:07.723578 <6>[ 2.511566] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10606 18:06:07.734244 <6>[ 2.521031] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10607 18:06:07.743871 <6>[ 2.530152] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10608 18:06:07.754035 <6>[ 2.539450] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10609 18:06:07.763635 <6>[ 2.549611] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10610 18:06:07.773870 <6>[ 2.561305] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10611 18:06:07.896966 <6>[ 2.684879] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10612 18:06:08.051996 <6>[ 2.842862] hub 1-1:1.0: USB hub found
10613 18:06:08.055618 <6>[ 2.847397] hub 1-1:1.0: 4 ports detected
10614 18:06:08.067441 <6>[ 2.858346] hub 1-1:1.0: USB hub found
10615 18:06:08.070722 <6>[ 2.862648] hub 1-1:1.0: 4 ports detected
10616 18:06:08.177697 <6>[ 2.965039] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10617 18:06:08.202607 <6>[ 2.993237] hub 2-1:1.0: USB hub found
10618 18:06:08.205614 <6>[ 2.997667] hub 2-1:1.0: 3 ports detected
10619 18:06:08.215963 <6>[ 3.006935] hub 2-1:1.0: USB hub found
10620 18:06:08.219279 <6>[ 3.011326] hub 2-1:1.0: 3 ports detected
10621 18:06:08.393135 <6>[ 3.180898] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10622 18:06:08.525291 <6>[ 3.316251] hub 1-1.4:1.0: USB hub found
10623 18:06:08.528371 <6>[ 3.320871] hub 1-1.4:1.0: 2 ports detected
10624 18:06:08.540400 <6>[ 3.331545] hub 1-1.4:1.0: USB hub found
10625 18:06:08.543574 <6>[ 3.336096] hub 1-1.4:1.0: 2 ports detected
10626 18:06:08.609050 <6>[ 3.397016] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10627 18:06:08.717626 <6>[ 3.505274] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10628 18:06:08.749779 <4>[ 3.537379] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10629 18:06:08.759763 <4>[ 3.546548] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10630 18:06:08.798508 <6>[ 3.589875] r8152 2-1.3:1.0 eth0: v1.12.13
10631 18:06:08.844846 <6>[ 3.632662] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10632 18:06:09.037255 <6>[ 3.824712] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10633 18:06:10.473637 <6>[ 5.264861] r8152 2-1.3:1.0 eth0: carrier on
10634 18:06:12.561411 <5>[ 5.292675] Sending DHCP requests .., OK
10635 18:06:12.568244 <6>[ 7.356974] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10636 18:06:12.571805 <6>[ 7.365269] IP-Config: Complete:
10637 18:06:12.584685 <6>[ 7.368766] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10638 18:06:12.590995 <6>[ 7.379488] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10639 18:06:12.597984 <6>[ 7.388108] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10640 18:06:12.604489 <6>[ 7.388118] nameserver0=192.168.201.1
10641 18:06:12.607813 <6>[ 7.400293] clk: Disabling unused clocks
10642 18:06:12.611335 <6>[ 7.405852] ALSA device list:
10643 18:06:12.617656 <6>[ 7.409105] No soundcards found.
10644 18:06:12.625187 <6>[ 7.416386] Freeing unused kernel memory: 8512K
10645 18:06:12.628436 <6>[ 7.421336] Run /init as init process
10646 18:06:12.651560 Starting syslogd: OK
10647 18:06:12.656515 Starting klogd: OK
10648 18:06:12.665828 Running sysctl: OK
10649 18:06:12.676118 Populating /dev using udev: <30>[ 7.466420] udevd[190]: starting version 3.2.9
10650 18:06:12.682645 <27>[ 7.474309] udevd[190]: specified user 'tss' unknown
10651 18:06:12.689712 <27>[ 7.479685] udevd[190]: specified group 'tss' unknown
10652 18:06:12.692964 <30>[ 7.486151] udevd[191]: starting eudev-3.2.9
10653 18:06:12.814139 <6>[ 7.602243] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10654 18:06:12.832495 <6>[ 7.623826] mc: Linux media interface: v0.10
10655 18:06:12.848114 <6>[ 7.636154] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10656 18:06:12.854867 <6>[ 7.645834] videodev: Linux video capture interface: v2.00
10657 18:06:12.864575 <6>[ 7.653074] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10658 18:06:12.871454 <6>[ 7.653954] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10659 18:06:12.882161 <6>[ 7.669941] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10660 18:06:12.885107 <6>[ 7.672026] remoteproc remoteproc0: scp is available
10661 18:06:12.891997 <6>[ 7.683446] remoteproc remoteproc0: powering up scp
10662 18:06:12.902330 <6>[ 7.683756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10663 18:06:12.908507 <6>[ 7.688607] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10664 18:06:12.915415 <6>[ 7.688654] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10665 18:06:12.922237 <3>[ 7.697923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 18:06:12.931372 <6>[ 7.705552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10667 18:06:12.938624 <3>[ 7.710883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 18:06:12.948236 <3>[ 7.710890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 18:06:12.955096 <3>[ 7.711057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 18:06:12.964922 <4>[ 7.719356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10671 18:06:12.971231 <3>[ 7.726967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 18:06:12.981589 <6>[ 7.735780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10673 18:06:12.988303 <3>[ 7.743148] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 18:06:12.994648 <4>[ 7.743984] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10675 18:06:13.001283 <4>[ 7.744116] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10676 18:06:13.011754 <6>[ 7.751214] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 18:06:13.018130 <3>[ 7.760256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 18:06:13.028456 <6>[ 7.769224] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10679 18:06:13.034580 <6>[ 7.777999] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10680 18:06:13.044753 <3>[ 7.778372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 18:06:13.051092 <3>[ 7.778446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 18:06:13.057818 <3>[ 7.778487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 18:06:13.067675 <3>[ 7.778490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 18:06:13.074636 <3>[ 7.778494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 18:06:13.084255 <3>[ 7.778532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 18:06:13.091128 <3>[ 7.778535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 18:06:13.100916 <3>[ 7.778538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 18:06:13.107673 <3>[ 7.778542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 18:06:13.117450 <3>[ 7.778545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 18:06:13.123942 <3>[ 7.778562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 18:06:13.131011 <6>[ 7.782214] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10692 18:06:13.137192 <6>[ 7.782247] pci_bus 0000:00: root bus resource [bus 00-ff]
10693 18:06:13.143864 <6>[ 7.782263] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10694 18:06:13.153841 <6>[ 7.782270] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10695 18:06:13.160246 <6>[ 7.782356] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10696 18:06:13.167371 <6>[ 7.782387] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10697 18:06:13.173845 <6>[ 7.782543] pci 0000:00:00.0: supports D1 D2
10698 18:06:13.180668 <6>[ 7.782545] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10699 18:06:13.187123 <6>[ 7.783708] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10700 18:06:13.193918 <6>[ 7.783838] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10701 18:06:13.200469 <6>[ 7.783862] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10702 18:06:13.210679 <6>[ 7.783880] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10703 18:06:13.217676 <6>[ 7.783895] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10704 18:06:13.220765 <6>[ 7.784008] pci 0000:01:00.0: supports D1 D2
10705 18:06:13.227611 <6>[ 7.784010] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10706 18:06:13.237573 <6>[ 7.786926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10707 18:06:13.244019 <6>[ 7.800068] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10708 18:06:13.250522 <6>[ 7.807663] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10709 18:06:13.257083 <6>[ 7.815807] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10710 18:06:13.266807 <6>[ 7.823530] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10711 18:06:13.273690 <6>[ 7.823538] remoteproc remoteproc0: remote processor scp is now up
10712 18:06:13.280292 <6>[ 7.823560] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 18:06:13.290804 <6>[ 7.823685] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10714 18:06:13.297105 <6>[ 7.823695] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10715 18:06:13.307122 <6>[ 7.823711] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10716 18:06:13.313560 <6>[ 7.823727] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10717 18:06:13.320465 <6>[ 7.823741] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10718 18:06:13.326883 <6>[ 7.823753] pci 0000:00:00.0: PCI bridge to [bus 01]
10719 18:06:13.333266 <6>[ 7.823762] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10720 18:06:13.339908 <6>[ 7.824039] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10721 18:06:13.349710 <6>[ 7.831892] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10722 18:06:13.357259 <6>[ 7.840202] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10723 18:06:13.367711 <6>[ 7.848264] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10724 18:06:13.373843 <6>[ 7.856240] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10725 18:06:13.380671 <6>[ 7.868500] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10726 18:06:13.390365 <4>[ 7.927933] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10727 18:06:13.396620 <4>[ 7.927933] Fallback method does not support PEC.
10728 18:06:13.400269 <6>[ 7.959112] Bluetooth: Core ver 2.22
10729 18:06:13.407294 <6>[ 7.960603] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10730 18:06:13.419849 <6>[ 7.972883] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10731 18:06:13.423222 <6>[ 7.976073] NET: Registered PF_BLUETOOTH protocol family
10732 18:06:13.430042 <6>[ 7.984975] usbcore: registered new interface driver uvcvideo
10733 18:06:13.436225 <5>[ 7.986728] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10734 18:06:13.443544 <6>[ 7.990531] Bluetooth: HCI device and connection manager initialized
10735 18:06:13.449952 <6>[ 7.990558] Bluetooth: HCI socket layer initialized
10736 18:06:13.456743 <6>[ 7.991604] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10737 18:06:13.462907 <6>[ 8.001239] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10738 18:06:13.472821 <5>[ 8.004963] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10739 18:06:13.479652 <5>[ 8.005354] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10740 18:06:13.489283 <4>[ 8.005589] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10741 18:06:13.492862 <6>[ 8.005652] Bluetooth: L2CAP socket layer initialized
10742 18:06:13.499412 <6>[ 8.005681] Bluetooth: SCO socket layer initialized
10743 18:06:13.506300 <6>[ 8.015924] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10744 18:06:13.512684 <6>[ 8.017650] cfg80211: failed to load regulatory.db
10745 18:06:13.518932 <6>[ 8.047550] usbcore: registered new interface driver btusb
10746 18:06:13.529420 <4>[ 8.048143] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10747 18:06:13.535982 <3>[ 8.048148] Bluetooth: hci0: Failed to load firmware file (-2)
10748 18:06:13.539152 <3>[ 8.048151] Bluetooth: hci0: Failed to set up firmware (-2)
10749 18:06:13.552293 <4>[ 8.048152] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10750 18:06:13.559346 <3>[ 8.102237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10751 18:06:13.565349 <6>[ 8.129654] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10752 18:06:13.575541 <3>[ 8.154118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10753 18:06:13.581856 <6>[ 8.163103] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10754 18:06:13.605548 <6>[ 8.396826] mt7921e 0000:01:00.0: ASIC revision: 79610010
10755 18:06:13.707637 <6>[ 8.496129] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10756 18:06:13.710865 <6>[ 8.496129]
10757 18:06:13.723210 done
10758 18:06:13.735074 Saving random seed: OK
10759 18:06:13.746849 Starting network: ip: RTNETLINK answers: File exists
10760 18:06:13.749752 FAIL
10761 18:06:13.783150 Starting dropbear sshd: <6>[ 8.574600] NET: Registered PF_INET6 protocol family
10762 18:06:13.789850 <6>[ 8.580828] Segment Routing with IPv6
10763 18:06:13.793257 <6>[ 8.584773] In-situ OAM (IOAM) with IPv6
10764 18:06:13.796431 OK
10765 18:06:13.807080 /bin/sh: can't access tty; job control turned off
10766 18:06:13.807544 Matched prompt #10: / #
10768 18:06:13.807762 Setting prompt string to ['/ #']
10769 18:06:13.807853 end: 2.2.5.1 login-action (duration 00:00:09) [common]
10771 18:06:13.808094 end: 2.2.5 auto-login-action (duration 00:00:09) [common]
10772 18:06:13.808185 start: 2.2.6 expect-shell-connection (timeout 00:03:49) [common]
10773 18:06:13.808256 Setting prompt string to ['/ #']
10774 18:06:13.808333 Forcing a shell prompt, looking for ['/ #']
10776 18:06:13.858581 / #
10777 18:06:13.858723 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10778 18:06:13.858830 Waiting using forced prompt support (timeout 00:02:30)
10779 18:06:13.863248
10780 18:06:13.863536 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10781 18:06:13.863634 start: 2.2.7 export-device-env (timeout 00:03:49) [common]
10782 18:06:13.863766 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10783 18:06:13.863870 end: 2.2 depthcharge-retry (duration 00:01:11) [common]
10784 18:06:13.863956 end: 2 depthcharge-action (duration 00:01:11) [common]
10785 18:06:13.864043 start: 3 lava-test-retry (timeout 00:01:00) [common]
10786 18:06:13.864127 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10787 18:06:13.864202 Using namespace: common
10789 18:06:13.964510 / # #
10790 18:06:13.964666 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10791 18:06:13.969443 #
10792 18:06:13.969715 Using /lava-14291414
10794 18:06:14.070085 / # <6>[ 8.766066] mtexport SHELL=/bin/sh
10795 18:06:14.070299 7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10796 18:06:14.075069 export SHELL=/bin/sh
10798 18:06:14.175606 / # . /lava-14291414/environment
10799 18:06:14.181392 . /lava-14291414/environment
10801 18:06:14.281910 / # /lava-14291414/bin/lava-test-runner /lava-14291414/0
10802 18:06:14.282070 Test shell timeout: 10s (minimum of the action and connection timeout)
10803 18:06:14.287554 /lava-14291414/bin/lava-test-runner /lava-14291414/0
10804 18:06:14.308265 + export 'TESTRUN_ID=0_dmesg'
10805 18:06:14.315078 +<8>[ 9.105300] <LAVA_SIGNAL_STARTRUN 0_dmesg 14291414_1.5.2.3.1>
10806 18:06:14.315351 Received signal: <STARTRUN> 0_dmesg 14291414_1.5.2.3.1
10807 18:06:14.315428 Starting test lava.0_dmesg (14291414_1.5.2.3.1)
10808 18:06:14.315545 Skipping test definition patterns.
10809 18:06:14.318250 cd /lava-14291414/0/tests/0_dmesg
10810 18:06:14.318348 + cat uuid
10811 18:06:14.321362 + UUID=14291414_1.5.2.3.1
10812 18:06:14.321449 + set +x
10813 18:06:14.327762 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10814 18:06:14.338284 <8>[ 9.125429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10815 18:06:14.338561 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10817 18:06:14.356835 <8>[ 9.145013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10818 18:06:14.357098 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10820 18:06:14.379006 <8>[ 9.167097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10821 18:06:14.379270 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10823 18:06:14.382426 + set +x
10824 18:06:14.385348 <8>[ 9.176979] <LAVA_SIGNAL_ENDRUN 0_dmesg 14291414_1.5.2.3.1>
10825 18:06:14.385603 Received signal: <ENDRUN> 0_dmesg 14291414_1.5.2.3.1
10826 18:06:14.385690 Ending use of test pattern.
10827 18:06:14.385755 Ending test lava.0_dmesg (14291414_1.5.2.3.1), duration 0.07
10829 18:06:14.389410 <LAVA_TEST_RUNNER EXIT>
10830 18:06:14.389662 ok: lava_test_shell seems to have completed
10831 18:06:14.389788 alert: pass
crit: pass
emerg: pass
10832 18:06:14.389889 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10833 18:06:14.389993 end: 3 lava-test-retry (duration 00:00:01) [common]
10834 18:06:14.390094 start: 4 finalize (timeout 00:08:29) [common]
10835 18:06:14.390181 start: 4.1 power-off (timeout 00:00:30) [common]
10836 18:06:14.390333 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
10837 18:06:14.466296 >> Command sent successfully.
10838 18:06:14.468626 Returned 0 in 0 seconds
10839 18:06:14.569021 end: 4.1 power-off (duration 00:00:00) [common]
10841 18:06:14.569367 start: 4.2 read-feedback (timeout 00:08:29) [common]
10842 18:06:14.569640 Listened to connection for namespace 'common' for up to 1s
10843 18:06:15.570586 Finalising connection for namespace 'common'
10844 18:06:15.570751 Disconnecting from shell: Finalise
10845 18:06:15.570844 / #
10846 18:06:15.671157 end: 4.2 read-feedback (duration 00:00:01) [common]
10847 18:06:15.671349 end: 4 finalize (duration 00:00:01) [common]
10848 18:06:15.671478 Cleaning after the job
10849 18:06:15.671581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/ramdisk
10850 18:06:15.674165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/kernel
10851 18:06:15.681469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/dtb
10852 18:06:15.681655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291414/tftp-deploy-nsk2g2v5/modules
10853 18:06:15.687419 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291414
10854 18:06:15.727700 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291414
10855 18:06:15.727863 Job finished correctly