Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 29
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 18:10:02.203809 lava-dispatcher, installed at version: 2024.03
2 18:10:02.204014 start: 0 validate
3 18:10:02.204166 Start time: 2024-06-11 18:10:02.204158+00:00 (UTC)
4 18:10:02.204304 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:10:02.204502 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 18:10:02.487201 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:10:02.488149 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:10:02.759407 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:10:02.760521 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:10:03.029020 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:10:03.029183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:10:03.296452 validate duration: 1.09
14 18:10:03.296745 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:10:03.296865 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:10:03.296977 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:10:03.297110 Not decompressing ramdisk as can be used compressed.
18 18:10:03.297196 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 18:10:03.297263 saving as /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/ramdisk/rootfs.cpio.gz
20 18:10:03.297337 total size: 39026414 (37 MB)
21 18:10:03.298486 progress 0 % (0 MB)
22 18:10:03.309983 progress 5 % (1 MB)
23 18:10:03.321782 progress 10 % (3 MB)
24 18:10:03.332948 progress 15 % (5 MB)
25 18:10:03.344151 progress 20 % (7 MB)
26 18:10:03.355023 progress 25 % (9 MB)
27 18:10:03.366116 progress 30 % (11 MB)
28 18:10:03.376285 progress 35 % (13 MB)
29 18:10:03.387022 progress 40 % (14 MB)
30 18:10:03.397514 progress 45 % (16 MB)
31 18:10:03.408846 progress 50 % (18 MB)
32 18:10:03.419144 progress 55 % (20 MB)
33 18:10:03.429569 progress 60 % (22 MB)
34 18:10:03.439838 progress 65 % (24 MB)
35 18:10:03.449715 progress 70 % (26 MB)
36 18:10:03.459913 progress 75 % (27 MB)
37 18:10:03.470147 progress 80 % (29 MB)
38 18:10:03.480539 progress 85 % (31 MB)
39 18:10:03.491802 progress 90 % (33 MB)
40 18:10:03.502106 progress 95 % (35 MB)
41 18:10:03.511750 progress 100 % (37 MB)
42 18:10:03.512007 37 MB downloaded in 0.21 s (173.38 MB/s)
43 18:10:03.512165 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:10:03.512487 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:10:03.512577 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:10:03.512662 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:10:03.512792 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:10:03.512865 saving as /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/kernel/Image
50 18:10:03.512955 total size: 54813184 (52 MB)
51 18:10:03.513042 No compression specified
52 18:10:03.514117 progress 0 % (0 MB)
53 18:10:03.527935 progress 5 % (2 MB)
54 18:10:03.542015 progress 10 % (5 MB)
55 18:10:03.555937 progress 15 % (7 MB)
56 18:10:03.570421 progress 20 % (10 MB)
57 18:10:03.584695 progress 25 % (13 MB)
58 18:10:03.599029 progress 30 % (15 MB)
59 18:10:03.613961 progress 35 % (18 MB)
60 18:10:03.629412 progress 40 % (20 MB)
61 18:10:03.643452 progress 45 % (23 MB)
62 18:10:03.657475 progress 50 % (26 MB)
63 18:10:03.671708 progress 55 % (28 MB)
64 18:10:03.685693 progress 60 % (31 MB)
65 18:10:03.699813 progress 65 % (34 MB)
66 18:10:03.713651 progress 70 % (36 MB)
67 18:10:03.728242 progress 75 % (39 MB)
68 18:10:03.743539 progress 80 % (41 MB)
69 18:10:03.758955 progress 85 % (44 MB)
70 18:10:03.773352 progress 90 % (47 MB)
71 18:10:03.787340 progress 95 % (49 MB)
72 18:10:03.800875 progress 100 % (52 MB)
73 18:10:03.801107 52 MB downloaded in 0.29 s (181.41 MB/s)
74 18:10:03.801262 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:10:03.801499 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:10:03.801588 start: 1.3 download-retry (timeout 00:09:59) [common]
78 18:10:03.801675 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 18:10:03.801815 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:10:03.801887 saving as /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/dtb/mt8192-asurada-spherion-r0.dtb
81 18:10:03.801989 total size: 47258 (0 MB)
82 18:10:03.802052 No compression specified
83 18:10:03.803190 progress 69 % (0 MB)
84 18:10:03.803457 progress 100 % (0 MB)
85 18:10:03.803650 0 MB downloaded in 0.00 s (27.16 MB/s)
86 18:10:03.803773 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:10:03.803998 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:10:03.804083 start: 1.4 download-retry (timeout 00:09:59) [common]
90 18:10:03.804166 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 18:10:03.804275 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:10:03.804367 saving as /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/modules/modules.tar
93 18:10:03.804443 total size: 8618176 (8 MB)
94 18:10:03.804505 Using unxz to decompress xz
95 18:10:03.808406 progress 0 % (0 MB)
96 18:10:03.827168 progress 5 % (0 MB)
97 18:10:03.854477 progress 10 % (0 MB)
98 18:10:03.884623 progress 15 % (1 MB)
99 18:10:03.909725 progress 20 % (1 MB)
100 18:10:03.933276 progress 25 % (2 MB)
101 18:10:03.957564 progress 30 % (2 MB)
102 18:10:03.984057 progress 35 % (2 MB)
103 18:10:04.010051 progress 40 % (3 MB)
104 18:10:04.034280 progress 45 % (3 MB)
105 18:10:04.058472 progress 50 % (4 MB)
106 18:10:04.083489 progress 55 % (4 MB)
107 18:10:04.107780 progress 60 % (4 MB)
108 18:10:04.132030 progress 65 % (5 MB)
109 18:10:04.159648 progress 70 % (5 MB)
110 18:10:04.184047 progress 75 % (6 MB)
111 18:10:04.209799 progress 80 % (6 MB)
112 18:10:04.234072 progress 85 % (7 MB)
113 18:10:04.260119 progress 90 % (7 MB)
114 18:10:04.285948 progress 95 % (7 MB)
115 18:10:04.312967 progress 100 % (8 MB)
116 18:10:04.317301 8 MB downloaded in 0.51 s (16.03 MB/s)
117 18:10:04.317526 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:10:04.317796 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:10:04.317892 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:10:04.317988 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:10:04.318071 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:10:04.318155 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:10:04.318389 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs
125 18:10:04.318522 makedir: /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin
126 18:10:04.318630 makedir: /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/tests
127 18:10:04.318736 makedir: /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/results
128 18:10:04.318852 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-add-keys
129 18:10:04.318997 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-add-sources
130 18:10:04.319136 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-background-process-start
131 18:10:04.319270 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-background-process-stop
132 18:10:04.319398 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-common-functions
133 18:10:04.319526 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-echo-ipv4
134 18:10:04.319654 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-install-packages
135 18:10:04.319781 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-installed-packages
136 18:10:04.319917 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-os-build
137 18:10:04.320048 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-probe-channel
138 18:10:04.320173 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-probe-ip
139 18:10:04.320298 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-target-ip
140 18:10:04.320484 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-target-mac
141 18:10:04.320643 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-target-storage
142 18:10:04.320803 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-case
143 18:10:04.320932 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-event
144 18:10:04.321063 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-feedback
145 18:10:04.321190 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-raise
146 18:10:04.321317 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-reference
147 18:10:04.321443 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-runner
148 18:10:04.321569 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-set
149 18:10:04.321698 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-test-shell
150 18:10:04.321831 Updating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-install-packages (oe)
151 18:10:04.321984 Updating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/bin/lava-installed-packages (oe)
152 18:10:04.322110 Creating /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/environment
153 18:10:04.322213 LAVA metadata
154 18:10:04.322288 - LAVA_JOB_ID=14291441
155 18:10:04.322356 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:10:04.322456 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:10:04.322525 skipped lava-vland-overlay
158 18:10:04.322601 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:10:04.322691 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:10:04.322766 skipped lava-multinode-overlay
161 18:10:04.322841 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:10:04.322925 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:10:04.323001 Loading test definitions
164 18:10:04.323095 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:10:04.323171 Using /lava-14291441 at stage 0
166 18:10:04.323506 uuid=14291441_1.5.2.3.1 testdef=None
167 18:10:04.323596 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:10:04.323682 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:10:04.324193 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:10:04.324465 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:10:04.325108 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:10:04.325339 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:10:04.325951 runner path: /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/0/tests/0_cros-ec test_uuid 14291441_1.5.2.3.1
176 18:10:04.326112 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:10:04.326335 Creating lava-test-runner.conf files
179 18:10:04.326401 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291441/lava-overlay-_11xb4zs/lava-14291441/0 for stage 0
180 18:10:04.326494 - 0_cros-ec
181 18:10:04.326595 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:10:04.326684 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:10:04.333950 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:10:04.334060 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:10:04.334148 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:10:04.334236 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:10:04.334325 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:10:05.542508 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 18:10:05.542926 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 18:10:05.543044 extracting modules file /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291441/extract-overlay-ramdisk-_g785ju9/ramdisk
191 18:10:05.793900 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:10:05.794070 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 18:10:05.794193 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291441/compress-overlay-tj5rgilt/overlay-1.5.2.4.tar.gz to ramdisk
194 18:10:05.794292 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291441/compress-overlay-tj5rgilt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291441/extract-overlay-ramdisk-_g785ju9/ramdisk
195 18:10:05.801524 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:10:05.801647 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 18:10:05.801742 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:10:05.801859 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 18:10:05.801941 Building ramdisk /var/lib/lava/dispatcher/tmp/14291441/extract-overlay-ramdisk-_g785ju9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291441/extract-overlay-ramdisk-_g785ju9/ramdisk
200 18:10:06.705550 >> 335936 blocks
201 18:10:11.893471 rename /var/lib/lava/dispatcher/tmp/14291441/extract-overlay-ramdisk-_g785ju9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/ramdisk/ramdisk.cpio.gz
202 18:10:11.893920 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 18:10:11.894046 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 18:10:11.894146 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 18:10:11.894254 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/kernel/Image']
206 18:10:25.265959 Returned 0 in 13 seconds
207 18:10:25.366605 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/kernel/image.itb
208 18:10:26.092362 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:10:26.092794 output: Created: Tue Jun 11 19:10:25 2024
210 18:10:26.092867 output: Image 0 (kernel-1)
211 18:10:26.092978 output: Description:
212 18:10:26.093043 output: Created: Tue Jun 11 19:10:25 2024
213 18:10:26.093137 output: Type: Kernel Image
214 18:10:26.093210 output: Compression: lzma compressed
215 18:10:26.093306 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:10:26.093379 output: Architecture: AArch64
217 18:10:26.093440 output: OS: Linux
218 18:10:26.093503 output: Load Address: 0x00000000
219 18:10:26.093641 output: Entry Point: 0x00000000
220 18:10:26.093702 output: Hash algo: crc32
221 18:10:26.093772 output: Hash value: 7a9e9d3e
222 18:10:26.093877 output: Image 1 (fdt-1)
223 18:10:26.094020 output: Description: mt8192-asurada-spherion-r0
224 18:10:26.094077 output: Created: Tue Jun 11 19:10:25 2024
225 18:10:26.094134 output: Type: Flat Device Tree
226 18:10:26.094201 output: Compression: uncompressed
227 18:10:26.094255 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:10:26.094309 output: Architecture: AArch64
229 18:10:26.094362 output: Hash algo: crc32
230 18:10:26.094415 output: Hash value: 0f8e4d2e
231 18:10:26.094468 output: Image 2 (ramdisk-1)
232 18:10:26.094521 output: Description: unavailable
233 18:10:26.094573 output: Created: Tue Jun 11 19:10:25 2024
234 18:10:26.094625 output: Type: RAMDisk Image
235 18:10:26.094678 output: Compression: Unknown Compression
236 18:10:26.094731 output: Data Size: 52137722 Bytes = 50915.74 KiB = 49.72 MiB
237 18:10:26.094785 output: Architecture: AArch64
238 18:10:26.094837 output: OS: Linux
239 18:10:26.094890 output: Load Address: unavailable
240 18:10:26.094942 output: Entry Point: unavailable
241 18:10:26.094994 output: Hash algo: crc32
242 18:10:26.095061 output: Hash value: badd8a61
243 18:10:26.095155 output: Default Configuration: 'conf-1'
244 18:10:26.095208 output: Configuration 0 (conf-1)
245 18:10:26.095260 output: Description: mt8192-asurada-spherion-r0
246 18:10:26.095327 output: Kernel: kernel-1
247 18:10:26.095382 output: Init Ramdisk: ramdisk-1
248 18:10:26.095435 output: FDT: fdt-1
249 18:10:26.095487 output: Loadables: kernel-1
250 18:10:26.095539 output:
251 18:10:26.095739 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 18:10:26.095834 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 18:10:26.095934 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 18:10:26.096028 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 18:10:26.096107 No LXC device requested
256 18:10:26.096186 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:10:26.096269 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 18:10:26.096351 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:10:26.096477 Checking files for TFTP limit of 4294967296 bytes.
260 18:10:26.096995 end: 1 tftp-deploy (duration 00:00:23) [common]
261 18:10:26.097098 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:10:26.097192 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:10:26.097310 substitutions:
264 18:10:26.097375 - {DTB}: 14291441/tftp-deploy-_9_2ntuc/dtb/mt8192-asurada-spherion-r0.dtb
265 18:10:26.097441 - {INITRD}: 14291441/tftp-deploy-_9_2ntuc/ramdisk/ramdisk.cpio.gz
266 18:10:26.097500 - {KERNEL}: 14291441/tftp-deploy-_9_2ntuc/kernel/Image
267 18:10:26.097557 - {LAVA_MAC}: None
268 18:10:26.097613 - {PRESEED_CONFIG}: None
269 18:10:26.097668 - {PRESEED_LOCAL}: None
270 18:10:26.097723 - {RAMDISK}: 14291441/tftp-deploy-_9_2ntuc/ramdisk/ramdisk.cpio.gz
271 18:10:26.097778 - {ROOT_PART}: None
272 18:10:26.097831 - {ROOT}: None
273 18:10:26.097885 - {SERVER_IP}: 192.168.201.1
274 18:10:26.097939 - {TEE}: None
275 18:10:26.097992 Parsed boot commands:
276 18:10:26.098056 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:10:26.098274 Parsed boot commands: tftpboot 192.168.201.1 14291441/tftp-deploy-_9_2ntuc/kernel/image.itb 14291441/tftp-deploy-_9_2ntuc/kernel/cmdline
278 18:10:26.098365 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:10:26.098457 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:10:26.098551 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:10:26.098636 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:10:26.098708 Not connected, no need to disconnect.
283 18:10:26.098783 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:10:26.098863 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:10:26.098931 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 18:10:26.102528 Setting prompt string to ['lava-test: # ']
287 18:10:26.102889 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:10:26.102993 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:10:26.103097 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:10:26.103188 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:10:26.103382 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 18:10:31.232930 >> Command sent successfully.
293 18:10:31.236278 Returned 0 in 5 seconds
294 18:10:31.336674 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 18:10:31.337096 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 18:10:31.337223 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 18:10:31.337334 Setting prompt string to 'Starting depthcharge on Spherion...'
299 18:10:31.337429 Changing prompt to 'Starting depthcharge on Spherion...'
300 18:10:31.337531 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 18:10:31.338183 [Enter `^Ec?' for help]
302 18:10:31.509526
303 18:10:31.509766
304 18:10:31.509912 F0: 102B 0000
305 18:10:31.510158
306 18:10:31.510371 F3: 1001 0000 [0200]
307 18:10:31.512833
308 18:10:31.513017 F3: 1001 0000
309 18:10:31.513170
310 18:10:31.513322 F7: 102D 0000
311 18:10:31.513534
312 18:10:31.516253 F1: 0000 0000
313 18:10:31.516530
314 18:10:31.516700 V0: 0000 0000 [0001]
315 18:10:31.516898
316 18:10:31.519982 00: 0007 8000
317 18:10:31.520242
318 18:10:31.520561 01: 0000 0000
319 18:10:31.520874
320 18:10:31.522839 BP: 0C00 0209 [0000]
321 18:10:31.523085
322 18:10:31.523329 G0: 1182 0000
323 18:10:31.523546
324 18:10:31.527045 EC: 0000 0021 [4000]
325 18:10:31.527352
326 18:10:31.527597 S7: 0000 0000 [0000]
327 18:10:31.527828
328 18:10:31.530753 CC: 0000 0000 [0001]
329 18:10:31.531148
330 18:10:31.531464 T0: 0000 0040 [010F]
331 18:10:31.531764
332 18:10:31.532046 Jump to BL
333 18:10:31.532485
334 18:10:31.556793
335 18:10:31.557491
336 18:10:31.563799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 18:10:31.566694 ARM64: Exception handlers installed.
338 18:10:31.571035 ARM64: Testing exception
339 18:10:31.573997 ARM64: Done test exception
340 18:10:31.580517 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 18:10:31.590794 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 18:10:31.598128 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 18:10:31.607606 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 18:10:31.614870 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 18:10:31.620965 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 18:10:31.633086 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 18:10:31.639828 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 18:10:31.659213 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 18:10:31.662761 WDT: Last reset was cold boot
350 18:10:31.665819 SPI1(PAD0) initialized at 2873684 Hz
351 18:10:31.669362 SPI5(PAD0) initialized at 992727 Hz
352 18:10:31.672300 VBOOT: Loading verstage.
353 18:10:31.679280 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 18:10:31.682270 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 18:10:31.685931 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 18:10:31.689579 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 18:10:31.697013 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 18:10:31.703494 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 18:10:31.714598 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 18:10:31.714686
361 18:10:31.714752
362 18:10:31.725025 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 18:10:31.728564 ARM64: Exception handlers installed.
364 18:10:31.731229 ARM64: Testing exception
365 18:10:31.731313 ARM64: Done test exception
366 18:10:31.738142 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 18:10:31.741756 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 18:10:31.755037 Probing TPM: . done!
369 18:10:31.755125 TPM ready after 0 ms
370 18:10:31.762275 Connected to device vid:did:rid of 1ae0:0028:00
371 18:10:31.769264 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 18:10:31.829584 Initialized TPM device CR50 revision 0
373 18:10:31.839174 tlcl_send_startup: Startup return code is 0
374 18:10:31.839690 TPM: setup succeeded
375 18:10:31.850734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 18:10:31.859583 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 18:10:31.871800 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 18:10:31.881710 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 18:10:31.885248 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 18:10:31.889308 in-header: 03 07 00 00 08 00 00 00
381 18:10:31.893420 in-data: aa e4 47 04 13 02 00 00
382 18:10:31.897178 Chrome EC: UHEPI supported
383 18:10:31.904590 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 18:10:31.908643 in-header: 03 95 00 00 08 00 00 00
385 18:10:31.909231 in-data: 18 20 20 08 00 00 00 00
386 18:10:31.911515 Phase 1
387 18:10:31.915653 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 18:10:31.918982 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 18:10:31.926572 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 18:10:31.930215 Recovery requested (1009000e)
391 18:10:31.940088 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:10:31.943758 tlcl_extend: response is 0
393 18:10:31.952606 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:10:31.957844 tlcl_extend: response is 0
395 18:10:31.964593 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:10:31.984364 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 18:10:31.991281 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:10:31.991469
399 18:10:31.991620
400 18:10:32.001265 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:10:32.005039 ARM64: Exception handlers installed.
402 18:10:32.007802 ARM64: Testing exception
403 18:10:32.008135 ARM64: Done test exception
404 18:10:32.030770 pmic_efuse_setting: Set efuses in 11 msecs
405 18:10:32.034243 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:10:32.040809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:10:32.043612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:10:32.051483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:10:32.055095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:10:32.058698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:10:32.065714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:10:32.069841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:10:32.073607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:10:32.077108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:10:32.084479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:10:32.088922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:10:32.092512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:10:32.096182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:10:32.103377 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:10:32.107660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:10:32.114949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:10:32.118365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:10:32.126567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:10:32.130136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:10:32.138000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:10:32.141849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:10:32.149434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:10:32.152497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:10:32.159888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:10:32.164064 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:10:32.171551 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:10:32.175248 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:10:32.178789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:10:32.186197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:10:32.189921 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:10:32.193546 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:10:32.200616 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:10:32.204078 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:10:32.211438 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:10:32.215052 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:10:32.218804 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:10:32.226336 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:10:32.229866 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:10:32.233585 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:10:32.237139 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:10:32.244705 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:10:32.248292 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:10:32.251850 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:10:32.255359 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:10:32.259033 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:10:32.266849 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:10:32.270247 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:10:32.274054 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:10:32.278085 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:10:32.281653 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:10:32.285140 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:10:32.292336 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 18:10:32.304234 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:10:32.307877 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:10:32.315063 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:10:32.322520 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:10:32.326339 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:10:32.333275 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:10:32.336200 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:10:32.344098 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xd
466 18:10:32.347754 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 18:10:32.355996 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 18:10:32.358808 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:10:32.368491 [RTC]rtc_get_frequency_meter,154: input=15, output=757
470 18:10:32.377560 [RTC]rtc_get_frequency_meter,154: input=23, output=942
471 18:10:32.387551 [RTC]rtc_get_frequency_meter,154: input=19, output=850
472 18:10:32.396046 [RTC]rtc_get_frequency_meter,154: input=17, output=804
473 18:10:32.405936 [RTC]rtc_get_frequency_meter,154: input=16, output=780
474 18:10:32.415050 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 18:10:32.425525 [RTC]rtc_get_frequency_meter,154: input=17, output=805
476 18:10:32.429641 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 18:10:32.434039 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 18:10:32.437641 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 18:10:32.441341 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 18:10:32.448635 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 18:10:32.452282 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 18:10:32.452496 ADC[4]: Raw value=906573 ID=7
483 18:10:32.455907 ADC[3]: Raw value=213441 ID=1
484 18:10:32.456164 RAM Code: 0x71
485 18:10:32.464122 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 18:10:32.468046 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 18:10:32.475124 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 18:10:32.483056 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 18:10:32.487115 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 18:10:32.490467 in-header: 03 07 00 00 08 00 00 00
491 18:10:32.494257 in-data: aa e4 47 04 13 02 00 00
492 18:10:32.494700 Chrome EC: UHEPI supported
493 18:10:32.501322 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 18:10:32.505059 in-header: 03 95 00 00 08 00 00 00
495 18:10:32.508593 in-data: 18 20 20 08 00 00 00 00
496 18:10:32.512434 MRC: failed to locate region type 0.
497 18:10:32.519598 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 18:10:32.520240 DRAM-K: Running full calibration
499 18:10:32.527309 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 18:10:32.531559 header.status = 0x0
501 18:10:32.531986 header.version = 0x6 (expected: 0x6)
502 18:10:32.534586 header.size = 0xd00 (expected: 0xd00)
503 18:10:32.538496 header.flags = 0x0
504 18:10:32.545728 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 18:10:32.562799 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 18:10:32.569948 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 18:10:32.570388 dram_init: ddr_geometry: 2
508 18:10:32.573579 [EMI] MDL number = 2
509 18:10:32.574004 [EMI] Get MDL freq = 0
510 18:10:32.577705 dram_init: ddr_type: 0
511 18:10:32.581035 is_discrete_lpddr4: 1
512 18:10:32.581464 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 18:10:32.581811
514 18:10:32.582130
515 18:10:32.585357 [Bian_co] ETT version 0.0.0.1
516 18:10:32.589035 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 18:10:32.589463
518 18:10:32.596568 dramc_set_vcore_voltage set vcore to 650000
519 18:10:32.596996 Read voltage for 800, 4
520 18:10:32.597344 Vio18 = 0
521 18:10:32.600006 Vcore = 650000
522 18:10:32.600474 Vdram = 0
523 18:10:32.600824 Vddq = 0
524 18:10:32.601146 Vmddr = 0
525 18:10:32.603341 dram_init: config_dvfs: 1
526 18:10:32.607618 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 18:10:32.614723 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 18:10:32.618489 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 18:10:32.622274 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 18:10:32.625839 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 18:10:32.629504 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 18:10:32.633842 MEM_TYPE=3, freq_sel=18
533 18:10:32.634416 sv_algorithm_assistance_LP4_1600
534 18:10:32.640323 ============ PULL DRAM RESETB DOWN ============
535 18:10:32.643936 ========== PULL DRAM RESETB DOWN end =========
536 18:10:32.646810 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 18:10:32.650415 ===================================
538 18:10:32.653683 LPDDR4 DRAM CONFIGURATION
539 18:10:32.657519 ===================================
540 18:10:32.657941 EX_ROW_EN[0] = 0x0
541 18:10:32.660616 EX_ROW_EN[1] = 0x0
542 18:10:32.661218 LP4Y_EN = 0x0
543 18:10:32.664611 WORK_FSP = 0x0
544 18:10:32.665140 WL = 0x2
545 18:10:32.668516 RL = 0x2
546 18:10:32.668944 BL = 0x2
547 18:10:32.671714 RPST = 0x0
548 18:10:32.672132 RD_PRE = 0x0
549 18:10:32.675442 WR_PRE = 0x1
550 18:10:32.675861 WR_PST = 0x0
551 18:10:32.678880 DBI_WR = 0x0
552 18:10:32.679302 DBI_RD = 0x0
553 18:10:32.682482 OTF = 0x1
554 18:10:32.685833 ===================================
555 18:10:32.689485 ===================================
556 18:10:32.689981 ANA top config
557 18:10:32.692455 ===================================
558 18:10:32.696250 DLL_ASYNC_EN = 0
559 18:10:32.699290 ALL_SLAVE_EN = 1
560 18:10:32.699842 NEW_RANK_MODE = 1
561 18:10:32.702548 DLL_IDLE_MODE = 1
562 18:10:32.706043 LP45_APHY_COMB_EN = 1
563 18:10:32.708750 TX_ODT_DIS = 1
564 18:10:32.709184 NEW_8X_MODE = 1
565 18:10:32.713156 ===================================
566 18:10:32.716405 ===================================
567 18:10:32.719871 data_rate = 1600
568 18:10:32.722961 CKR = 1
569 18:10:32.726496 DQ_P2S_RATIO = 8
570 18:10:32.730128 ===================================
571 18:10:32.733037 CA_P2S_RATIO = 8
572 18:10:32.733475 DQ_CA_OPEN = 0
573 18:10:32.736561 DQ_SEMI_OPEN = 0
574 18:10:32.740125 CA_SEMI_OPEN = 0
575 18:10:32.743054 CA_FULL_RATE = 0
576 18:10:32.746631 DQ_CKDIV4_EN = 1
577 18:10:32.749455 CA_CKDIV4_EN = 1
578 18:10:32.749893 CA_PREDIV_EN = 0
579 18:10:32.753008 PH8_DLY = 0
580 18:10:32.756881 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 18:10:32.759590 DQ_AAMCK_DIV = 4
582 18:10:32.763200 CA_AAMCK_DIV = 4
583 18:10:32.763641 CA_ADMCK_DIV = 4
584 18:10:32.766645 DQ_TRACK_CA_EN = 0
585 18:10:32.770228 CA_PICK = 800
586 18:10:32.773518 CA_MCKIO = 800
587 18:10:32.776723 MCKIO_SEMI = 0
588 18:10:32.780935 PLL_FREQ = 3068
589 18:10:32.781252 DQ_UI_PI_RATIO = 32
590 18:10:32.784205 CA_UI_PI_RATIO = 0
591 18:10:32.788104 ===================================
592 18:10:32.792247 ===================================
593 18:10:32.792603 memory_type:LPDDR4
594 18:10:32.795982 GP_NUM : 10
595 18:10:32.799783 SRAM_EN : 1
596 18:10:32.800148 MD32_EN : 0
597 18:10:32.803147 ===================================
598 18:10:32.807135 [ANA_INIT] >>>>>>>>>>>>>>
599 18:10:32.807462 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 18:10:32.811269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 18:10:32.814228 ===================================
602 18:10:32.817862 data_rate = 1600,PCW = 0X7600
603 18:10:32.821371 ===================================
604 18:10:32.824224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 18:10:32.831462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 18:10:32.834318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 18:10:32.841494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 18:10:32.844408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 18:10:32.847846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 18:10:32.848265 [ANA_INIT] flow start
611 18:10:32.851386 [ANA_INIT] PLL >>>>>>>>
612 18:10:32.854332 [ANA_INIT] PLL <<<<<<<<
613 18:10:32.854636 [ANA_INIT] MIDPI >>>>>>>>
614 18:10:32.857822 [ANA_INIT] MIDPI <<<<<<<<
615 18:10:32.861558 [ANA_INIT] DLL >>>>>>>>
616 18:10:32.861953 [ANA_INIT] flow end
617 18:10:32.868152 ============ LP4 DIFF to SE enter ============
618 18:10:32.870925 ============ LP4 DIFF to SE exit ============
619 18:10:32.874634 [ANA_INIT] <<<<<<<<<<<<<
620 18:10:32.878534 [Flow] Enable top DCM control >>>>>
621 18:10:32.881133 [Flow] Enable top DCM control <<<<<
622 18:10:32.881587 Enable DLL master slave shuffle
623 18:10:32.888067 ==============================================================
624 18:10:32.891055 Gating Mode config
625 18:10:32.894576 ==============================================================
626 18:10:32.897996 Config description:
627 18:10:32.907966 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 18:10:32.914379 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 18:10:32.917890 SELPH_MODE 0: By rank 1: By Phase
630 18:10:32.924264 ==============================================================
631 18:10:32.928083 GAT_TRACK_EN = 1
632 18:10:32.931355 RX_GATING_MODE = 2
633 18:10:32.934039 RX_GATING_TRACK_MODE = 2
634 18:10:32.934655 SELPH_MODE = 1
635 18:10:32.937457 PICG_EARLY_EN = 1
636 18:10:32.941060 VALID_LAT_VALUE = 1
637 18:10:32.947423 ==============================================================
638 18:10:32.951343 Enter into Gating configuration >>>>
639 18:10:32.954682 Exit from Gating configuration <<<<
640 18:10:32.957495 Enter into DVFS_PRE_config >>>>>
641 18:10:32.967679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 18:10:32.971386 Exit from DVFS_PRE_config <<<<<
643 18:10:32.974307 Enter into PICG configuration >>>>
644 18:10:32.977741 Exit from PICG configuration <<<<
645 18:10:32.981437 [RX_INPUT] configuration >>>>>
646 18:10:32.984420 [RX_INPUT] configuration <<<<<
647 18:10:32.988009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 18:10:32.994343 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 18:10:33.001533 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 18:10:33.008009 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 18:10:33.010782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 18:10:33.017834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 18:10:33.021134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 18:10:33.027687 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 18:10:33.031264 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 18:10:33.034762 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 18:10:33.038059 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 18:10:33.044490 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 18:10:33.047744 ===================================
660 18:10:33.048196 LPDDR4 DRAM CONFIGURATION
661 18:10:33.051053 ===================================
662 18:10:33.054568 EX_ROW_EN[0] = 0x0
663 18:10:33.057819 EX_ROW_EN[1] = 0x0
664 18:10:33.058249 LP4Y_EN = 0x0
665 18:10:33.061459 WORK_FSP = 0x0
666 18:10:33.061885 WL = 0x2
667 18:10:33.064786 RL = 0x2
668 18:10:33.065215 BL = 0x2
669 18:10:33.067843 RPST = 0x0
670 18:10:33.068270 RD_PRE = 0x0
671 18:10:33.071314 WR_PRE = 0x1
672 18:10:33.071827 WR_PST = 0x0
673 18:10:33.074384 DBI_WR = 0x0
674 18:10:33.074814 DBI_RD = 0x0
675 18:10:33.077784 OTF = 0x1
676 18:10:33.081429 ===================================
677 18:10:33.084422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 18:10:33.087719 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 18:10:33.094393 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 18:10:33.097922 ===================================
681 18:10:33.098352 LPDDR4 DRAM CONFIGURATION
682 18:10:33.101306 ===================================
683 18:10:33.104755 EX_ROW_EN[0] = 0x10
684 18:10:33.105185 EX_ROW_EN[1] = 0x0
685 18:10:33.107763 LP4Y_EN = 0x0
686 18:10:33.108190 WORK_FSP = 0x0
687 18:10:33.111538 WL = 0x2
688 18:10:33.114895 RL = 0x2
689 18:10:33.115443 BL = 0x2
690 18:10:33.117833 RPST = 0x0
691 18:10:33.118264 RD_PRE = 0x0
692 18:10:33.121567 WR_PRE = 0x1
693 18:10:33.121995 WR_PST = 0x0
694 18:10:33.124413 DBI_WR = 0x0
695 18:10:33.124846 DBI_RD = 0x0
696 18:10:33.127774 OTF = 0x1
697 18:10:33.131097 ===================================
698 18:10:33.134788 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 18:10:33.140435 nWR fixed to 40
700 18:10:33.143299 [ModeRegInit_LP4] CH0 RK0
701 18:10:33.143729 [ModeRegInit_LP4] CH0 RK1
702 18:10:33.146704 [ModeRegInit_LP4] CH1 RK0
703 18:10:33.150046 [ModeRegInit_LP4] CH1 RK1
704 18:10:33.150472 match AC timing 13
705 18:10:33.156892 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 18:10:33.159734 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 18:10:33.163101 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 18:10:33.170152 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 18:10:33.173357 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 18:10:33.173790 [EMI DOE] emi_dcm 0
711 18:10:33.179669 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 18:10:33.180099 ==
713 18:10:33.183112 Dram Type= 6, Freq= 0, CH_0, rank 0
714 18:10:33.186673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 18:10:33.187127 ==
716 18:10:33.193033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 18:10:33.199665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 18:10:33.207278 [CA 0] Center 36 (6~67) winsize 62
719 18:10:33.210893 [CA 1] Center 36 (6~67) winsize 62
720 18:10:33.213916 [CA 2] Center 34 (4~65) winsize 62
721 18:10:33.217464 [CA 3] Center 34 (4~64) winsize 61
722 18:10:33.220368 [CA 4] Center 33 (2~64) winsize 63
723 18:10:33.223943 [CA 5] Center 32 (2~62) winsize 61
724 18:10:33.224408
725 18:10:33.227557 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 18:10:33.227986
727 18:10:33.230633 [CATrainingPosCal] consider 1 rank data
728 18:10:33.234483 u2DelayCellTimex100 = 270/100 ps
729 18:10:33.237020 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 18:10:33.240540 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 18:10:33.247528 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 18:10:33.250894 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
733 18:10:33.254095 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
734 18:10:33.256930 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
735 18:10:33.257478
736 18:10:33.260511 CA PerBit enable=1, Macro0, CA PI delay=32
737 18:10:33.260942
738 18:10:33.263919 [CBTSetCACLKResult] CA Dly = 32
739 18:10:33.264387 CS Dly: 4 (0~35)
740 18:10:33.267538 ==
741 18:10:33.267965 Dram Type= 6, Freq= 0, CH_0, rank 1
742 18:10:33.274025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 18:10:33.274455 ==
744 18:10:33.277387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 18:10:33.284510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 18:10:33.293481 [CA 0] Center 36 (6~67) winsize 62
747 18:10:33.296860 [CA 1] Center 36 (6~67) winsize 62
748 18:10:33.300321 [CA 2] Center 34 (4~65) winsize 62
749 18:10:33.303292 [CA 3] Center 34 (4~65) winsize 62
750 18:10:33.306841 [CA 4] Center 33 (2~64) winsize 63
751 18:10:33.310450 [CA 5] Center 32 (2~63) winsize 62
752 18:10:33.310893
753 18:10:33.313866 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 18:10:33.314315
755 18:10:33.316705 [CATrainingPosCal] consider 2 rank data
756 18:10:33.320055 u2DelayCellTimex100 = 270/100 ps
757 18:10:33.323500 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 18:10:33.327101 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 18:10:33.333563 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
760 18:10:33.337167 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
761 18:10:33.340045 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
762 18:10:33.343557 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
763 18:10:33.343984
764 18:10:33.347154 CA PerBit enable=1, Macro0, CA PI delay=32
765 18:10:33.347599
766 18:10:33.350272 [CBTSetCACLKResult] CA Dly = 32
767 18:10:33.350710 CS Dly: 5 (0~37)
768 18:10:33.351054
769 18:10:33.353601 ----->DramcWriteLeveling(PI) begin...
770 18:10:33.357465 ==
771 18:10:33.357923 Dram Type= 6, Freq= 0, CH_0, rank 0
772 18:10:33.364946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 18:10:33.365441 ==
774 18:10:33.365903 Write leveling (Byte 0): 33 => 33
775 18:10:33.368335 Write leveling (Byte 1): 31 => 31
776 18:10:33.372452 DramcWriteLeveling(PI) end<-----
777 18:10:33.372899
778 18:10:33.373353 ==
779 18:10:33.375920 Dram Type= 6, Freq= 0, CH_0, rank 0
780 18:10:33.378856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 18:10:33.379291 ==
782 18:10:33.382473 [Gating] SW mode calibration
783 18:10:33.389705 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 18:10:33.396453 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 18:10:33.399793 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 18:10:33.403112 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 18:10:33.409924 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 18:10:33.412807 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 18:10:33.416519 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:10:33.423272 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:10:33.426163 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:10:33.429536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:10:33.432774 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:10:33.440075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:10:33.442804 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:10:33.446575 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:10:33.453028 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:10:33.456728 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 18:10:33.460002 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 18:10:33.466434 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:10:33.469972 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:10:33.473581 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 18:10:33.479742 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
804 18:10:33.483009 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 18:10:33.486290 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:10:33.492945 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:10:33.496558 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:10:33.500305 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 18:10:33.506363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 18:10:33.510141 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 18:10:33.513591 0 9 8 | B1->B0 | 2323 2f2f | 1 1 | (1 1) (1 1)
812 18:10:33.519710 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
813 18:10:33.523346 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:10:33.526956 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:10:33.529824 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 18:10:33.536723 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 18:10:33.540117 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 18:10:33.542890 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
819 18:10:33.550107 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
820 18:10:33.552819 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
821 18:10:33.556457 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:10:33.563042 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:10:33.566669 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 18:10:33.570136 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 18:10:33.576318 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 18:10:33.580050 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
827 18:10:33.583632 0 11 8 | B1->B0 | 2929 3b3b | 1 1 | (0 0) (0 0)
828 18:10:33.590096 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
829 18:10:33.593479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:10:33.596902 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:10:33.600504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 18:10:33.607016 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 18:10:33.610830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 18:10:33.615823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 18:10:33.620053 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 18:10:33.623332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 18:10:33.626804 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:10:33.633364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:10:33.637110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:10:33.639961 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:10:33.647144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:10:33.650337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:10:33.653897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:10:33.660143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:10:33.663775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:10:33.666716 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:10:33.673366 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 18:10:33.676662 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 18:10:33.680038 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 18:10:33.686539 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 18:10:33.690287 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
852 18:10:33.693914 Total UI for P1: 0, mck2ui 16
853 18:10:33.696890 best dqsien dly found for B0: ( 0, 14, 4)
854 18:10:33.700272 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 18:10:33.703089 Total UI for P1: 0, mck2ui 16
856 18:10:33.706502 best dqsien dly found for B1: ( 0, 14, 10)
857 18:10:33.710622 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 18:10:33.714382 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
859 18:10:33.714809
860 18:10:33.717405 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 18:10:33.720988 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
862 18:10:33.724413 [Gating] SW calibration Done
863 18:10:33.724876 ==
864 18:10:33.727712 Dram Type= 6, Freq= 0, CH_0, rank 0
865 18:10:33.731001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 18:10:33.731497 ==
867 18:10:33.734594 RX Vref Scan: 0
868 18:10:33.735008
869 18:10:33.737748 RX Vref 0 -> 0, step: 1
870 18:10:33.738176
871 18:10:33.738516 RX Delay -130 -> 252, step: 16
872 18:10:33.743934 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 18:10:33.747410 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
874 18:10:33.751071 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 18:10:33.754445 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 18:10:33.757404 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 18:10:33.764425 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 18:10:33.767267 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
879 18:10:33.770826 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
880 18:10:33.774478 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
881 18:10:33.777300 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
882 18:10:33.783982 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 18:10:33.787248 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
884 18:10:33.790891 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 18:10:33.794010 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 18:10:33.797494 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
887 18:10:33.804064 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 18:10:33.804401 ==
889 18:10:33.807167 Dram Type= 6, Freq= 0, CH_0, rank 0
890 18:10:33.810609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 18:10:33.810845 ==
892 18:10:33.811031 DQS Delay:
893 18:10:33.814024 DQS0 = 0, DQS1 = 0
894 18:10:33.814254 DQM Delay:
895 18:10:33.817504 DQM0 = 91, DQM1 = 82
896 18:10:33.817734 DQ Delay:
897 18:10:33.820954 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 18:10:33.823998 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =109
899 18:10:33.827706 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
900 18:10:33.831521 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
901 18:10:33.831962
902 18:10:33.832303
903 18:10:33.832696 ==
904 18:10:33.834491 Dram Type= 6, Freq= 0, CH_0, rank 0
905 18:10:33.837990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 18:10:33.838444 ==
907 18:10:33.838785
908 18:10:33.841443
909 18:10:33.841883 TX Vref Scan disable
910 18:10:33.844730 == TX Byte 0 ==
911 18:10:33.847460 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
912 18:10:33.851019 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
913 18:10:33.854487 == TX Byte 1 ==
914 18:10:33.858165 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 18:10:33.860916 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 18:10:33.861341 ==
917 18:10:33.864098 Dram Type= 6, Freq= 0, CH_0, rank 0
918 18:10:33.871069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 18:10:33.871512 ==
920 18:10:33.882657 TX Vref=22, minBit 9, minWin=27, winSum=449
921 18:10:33.886306 TX Vref=24, minBit 10, minWin=27, winSum=452
922 18:10:33.889711 TX Vref=26, minBit 0, minWin=28, winSum=457
923 18:10:33.893166 TX Vref=28, minBit 0, minWin=28, winSum=457
924 18:10:33.896388 TX Vref=30, minBit 8, minWin=28, winSum=456
925 18:10:33.899900 TX Vref=32, minBit 10, minWin=27, winSum=454
926 18:10:33.906438 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 26
927 18:10:33.906949
928 18:10:33.910105 Final TX Range 1 Vref 26
929 18:10:33.910531
930 18:10:33.910949 ==
931 18:10:33.913046 Dram Type= 6, Freq= 0, CH_0, rank 0
932 18:10:33.916591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 18:10:33.917103 ==
934 18:10:33.917494
935 18:10:33.919680
936 18:10:33.920101 TX Vref Scan disable
937 18:10:33.923273 == TX Byte 0 ==
938 18:10:33.926301 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 18:10:33.929628 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 18:10:33.932920 == TX Byte 1 ==
941 18:10:33.936511 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 18:10:33.939546 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 18:10:33.943108
944 18:10:33.943533 [DATLAT]
945 18:10:33.943889 Freq=800, CH0 RK0
946 18:10:33.944212
947 18:10:33.946537 DATLAT Default: 0xa
948 18:10:33.946959 0, 0xFFFF, sum = 0
949 18:10:33.949257 1, 0xFFFF, sum = 0
950 18:10:33.949837 2, 0xFFFF, sum = 0
951 18:10:33.953336 3, 0xFFFF, sum = 0
952 18:10:33.953796 4, 0xFFFF, sum = 0
953 18:10:33.956000 5, 0xFFFF, sum = 0
954 18:10:33.959374 6, 0xFFFF, sum = 0
955 18:10:33.959802 7, 0xFFFF, sum = 0
956 18:10:33.963137 8, 0xFFFF, sum = 0
957 18:10:33.963569 9, 0x0, sum = 1
958 18:10:33.963915 10, 0x0, sum = 2
959 18:10:33.966012 11, 0x0, sum = 3
960 18:10:33.966442 12, 0x0, sum = 4
961 18:10:33.969541 best_step = 10
962 18:10:33.969964
963 18:10:33.970308 ==
964 18:10:33.973114 Dram Type= 6, Freq= 0, CH_0, rank 0
965 18:10:33.976451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 18:10:33.977001 ==
967 18:10:33.979263 RX Vref Scan: 1
968 18:10:33.979740
969 18:10:33.982562 Set Vref Range= 32 -> 127
970 18:10:33.983193
971 18:10:33.983566 RX Vref 32 -> 127, step: 1
972 18:10:33.983898
973 18:10:33.986152 RX Delay -79 -> 252, step: 8
974 18:10:33.986757
975 18:10:33.989465 Set Vref, RX VrefLevel [Byte0]: 32
976 18:10:33.993153 [Byte1]: 32
977 18:10:33.993618
978 18:10:33.995979 Set Vref, RX VrefLevel [Byte0]: 33
979 18:10:33.999627 [Byte1]: 33
980 18:10:34.003676
981 18:10:34.004100 Set Vref, RX VrefLevel [Byte0]: 34
982 18:10:34.006395 [Byte1]: 34
983 18:10:34.010740
984 18:10:34.011164 Set Vref, RX VrefLevel [Byte0]: 35
985 18:10:34.014447 [Byte1]: 35
986 18:10:34.018848
987 18:10:34.019528 Set Vref, RX VrefLevel [Byte0]: 36
988 18:10:34.021673 [Byte1]: 36
989 18:10:34.026724
990 18:10:34.027156 Set Vref, RX VrefLevel [Byte0]: 37
991 18:10:34.029493 [Byte1]: 37
992 18:10:34.033896
993 18:10:34.034318 Set Vref, RX VrefLevel [Byte0]: 38
994 18:10:34.036763 [Byte1]: 38
995 18:10:34.041058
996 18:10:34.041485 Set Vref, RX VrefLevel [Byte0]: 39
997 18:10:34.044462 [Byte1]: 39
998 18:10:34.049000
999 18:10:34.049430 Set Vref, RX VrefLevel [Byte0]: 40
1000 18:10:34.051697 [Byte1]: 40
1001 18:10:34.056659
1002 18:10:34.057217 Set Vref, RX VrefLevel [Byte0]: 41
1003 18:10:34.059331 [Byte1]: 41
1004 18:10:34.063351
1005 18:10:34.063895 Set Vref, RX VrefLevel [Byte0]: 42
1006 18:10:34.066720 [Byte1]: 42
1007 18:10:34.071200
1008 18:10:34.071624 Set Vref, RX VrefLevel [Byte0]: 43
1009 18:10:34.074929 [Byte1]: 43
1010 18:10:34.078655
1011 18:10:34.079078 Set Vref, RX VrefLevel [Byte0]: 44
1012 18:10:34.082139 [Byte1]: 44
1013 18:10:34.086330
1014 18:10:34.086746 Set Vref, RX VrefLevel [Byte0]: 45
1015 18:10:34.089930 [Byte1]: 45
1016 18:10:34.093933
1017 18:10:34.094352 Set Vref, RX VrefLevel [Byte0]: 46
1018 18:10:34.097552 [Byte1]: 46
1019 18:10:34.101133
1020 18:10:34.101560 Set Vref, RX VrefLevel [Byte0]: 47
1021 18:10:34.104509 [Byte1]: 47
1022 18:10:34.108784
1023 18:10:34.109197 Set Vref, RX VrefLevel [Byte0]: 48
1024 18:10:34.112187 [Byte1]: 48
1025 18:10:34.116414
1026 18:10:34.116834 Set Vref, RX VrefLevel [Byte0]: 49
1027 18:10:34.120059 [Byte1]: 49
1028 18:10:34.124169
1029 18:10:34.124634 Set Vref, RX VrefLevel [Byte0]: 50
1030 18:10:34.127171 [Byte1]: 50
1031 18:10:34.131482
1032 18:10:34.131993 Set Vref, RX VrefLevel [Byte0]: 51
1033 18:10:34.135181 [Byte1]: 51
1034 18:10:34.138785
1035 18:10:34.139292 Set Vref, RX VrefLevel [Byte0]: 52
1036 18:10:34.142426 [Byte1]: 52
1037 18:10:34.146570
1038 18:10:34.146996 Set Vref, RX VrefLevel [Byte0]: 53
1039 18:10:34.150065 [Byte1]: 53
1040 18:10:34.154358
1041 18:10:34.154776 Set Vref, RX VrefLevel [Byte0]: 54
1042 18:10:34.157243 [Byte1]: 54
1043 18:10:34.161694
1044 18:10:34.162116 Set Vref, RX VrefLevel [Byte0]: 55
1045 18:10:34.165026 [Byte1]: 55
1046 18:10:34.168962
1047 18:10:34.169381 Set Vref, RX VrefLevel [Byte0]: 56
1048 18:10:34.172267 [Byte1]: 56
1049 18:10:34.177027
1050 18:10:34.177529 Set Vref, RX VrefLevel [Byte0]: 57
1051 18:10:34.180029 [Byte1]: 57
1052 18:10:34.184250
1053 18:10:34.184852 Set Vref, RX VrefLevel [Byte0]: 58
1054 18:10:34.187781 [Byte1]: 58
1055 18:10:34.192019
1056 18:10:34.192480 Set Vref, RX VrefLevel [Byte0]: 59
1057 18:10:34.194889 [Byte1]: 59
1058 18:10:34.199475
1059 18:10:34.199892 Set Vref, RX VrefLevel [Byte0]: 60
1060 18:10:34.203093 [Byte1]: 60
1061 18:10:34.207239
1062 18:10:34.207658 Set Vref, RX VrefLevel [Byte0]: 61
1063 18:10:34.210545 [Byte1]: 61
1064 18:10:34.214519
1065 18:10:34.214936 Set Vref, RX VrefLevel [Byte0]: 62
1066 18:10:34.217712 [Byte1]: 62
1067 18:10:34.221937
1068 18:10:34.222424 Set Vref, RX VrefLevel [Byte0]: 63
1069 18:10:34.225212 [Byte1]: 63
1070 18:10:34.230074
1071 18:10:34.230528 Set Vref, RX VrefLevel [Byte0]: 64
1072 18:10:34.232909 [Byte1]: 64
1073 18:10:34.237021
1074 18:10:34.237443 Set Vref, RX VrefLevel [Byte0]: 65
1075 18:10:34.240737 [Byte1]: 65
1076 18:10:34.245146
1077 18:10:34.245564 Set Vref, RX VrefLevel [Byte0]: 66
1078 18:10:34.247899 [Byte1]: 66
1079 18:10:34.252049
1080 18:10:34.252676 Set Vref, RX VrefLevel [Byte0]: 67
1081 18:10:34.255621 [Byte1]: 67
1082 18:10:34.259755
1083 18:10:34.260296 Set Vref, RX VrefLevel [Byte0]: 68
1084 18:10:34.263318 [Byte1]: 68
1085 18:10:34.267570
1086 18:10:34.267987 Set Vref, RX VrefLevel [Byte0]: 69
1087 18:10:34.271148 [Byte1]: 69
1088 18:10:34.275551
1089 18:10:34.276002 Set Vref, RX VrefLevel [Byte0]: 70
1090 18:10:34.278380 [Byte1]: 70
1091 18:10:34.282373
1092 18:10:34.282792 Set Vref, RX VrefLevel [Byte0]: 71
1093 18:10:34.285656 [Byte1]: 71
1094 18:10:34.290372
1095 18:10:34.290811 Set Vref, RX VrefLevel [Byte0]: 72
1096 18:10:34.293271 [Byte1]: 72
1097 18:10:34.297473
1098 18:10:34.297886 Set Vref, RX VrefLevel [Byte0]: 73
1099 18:10:34.301292 [Byte1]: 73
1100 18:10:34.304730
1101 18:10:34.305150 Set Vref, RX VrefLevel [Byte0]: 74
1102 18:10:34.308418 [Byte1]: 74
1103 18:10:34.312785
1104 18:10:34.313266 Set Vref, RX VrefLevel [Byte0]: 75
1105 18:10:34.316407 [Byte1]: 75
1106 18:10:34.320486
1107 18:10:34.320907 Set Vref, RX VrefLevel [Byte0]: 76
1108 18:10:34.323697 [Byte1]: 76
1109 18:10:34.327606
1110 18:10:34.328039 Set Vref, RX VrefLevel [Byte0]: 77
1111 18:10:34.330866 [Byte1]: 77
1112 18:10:34.335298
1113 18:10:34.335713 Final RX Vref Byte 0 = 57 to rank0
1114 18:10:34.338890 Final RX Vref Byte 1 = 57 to rank0
1115 18:10:34.342259 Final RX Vref Byte 0 = 57 to rank1
1116 18:10:34.345785 Final RX Vref Byte 1 = 57 to rank1==
1117 18:10:34.348692 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 18:10:34.352297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 18:10:34.355702 ==
1120 18:10:34.356206 DQS Delay:
1121 18:10:34.356670 DQS0 = 0, DQS1 = 0
1122 18:10:34.358846 DQM Delay:
1123 18:10:34.359333 DQM0 = 91, DQM1 = 84
1124 18:10:34.362386 DQ Delay:
1125 18:10:34.365280 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1126 18:10:34.365702 DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100
1127 18:10:34.369029 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1128 18:10:34.372473 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1129 18:10:34.375380
1130 18:10:34.375798
1131 18:10:34.382377 [DQSOSCAuto] RK0, (LSB)MR18= 0x473e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1132 18:10:34.385946 CH0 RK0: MR19=606, MR18=473E
1133 18:10:34.392267 CH0_RK0: MR19=0x606, MR18=0x473E, DQSOSC=392, MR23=63, INC=96, DEC=64
1134 18:10:34.392801
1135 18:10:34.395590 ----->DramcWriteLeveling(PI) begin...
1136 18:10:34.396015 ==
1137 18:10:34.399081 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 18:10:34.402688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 18:10:34.403123 ==
1140 18:10:34.405546 Write leveling (Byte 0): 36 => 36
1141 18:10:34.409151 Write leveling (Byte 1): 30 => 30
1142 18:10:34.412246 DramcWriteLeveling(PI) end<-----
1143 18:10:34.412706
1144 18:10:34.413042 ==
1145 18:10:34.415876 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 18:10:34.418952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 18:10:34.419420 ==
1148 18:10:34.422739 [Gating] SW mode calibration
1149 18:10:34.469885 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 18:10:34.470344 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 18:10:34.470681 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 18:10:34.470995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1153 18:10:34.471644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 18:10:34.471968 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 18:10:34.472387 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 18:10:34.472710 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 18:10:34.473048 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:10:34.473339 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:10:34.490515 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:10:34.491264 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:10:34.491633 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:10:34.491951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:10:34.494639 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:10:34.497956 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:10:34.500641 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:10:34.503812 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 18:10:34.507374 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 18:10:34.513992 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 18:10:34.517429 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 18:10:34.521060 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:10:34.527616 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:10:34.531195 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:10:34.534151 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:10:34.540697 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:10:34.544425 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 18:10:34.548065 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 18:10:34.554463 0 9 8 | B1->B0 | 2827 2626 | 1 1 | (1 1) (1 1)
1178 18:10:34.557480 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 18:10:34.560847 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 18:10:34.567850 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 18:10:34.571613 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:10:34.574576 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 18:10:34.581268 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 18:10:34.584838 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (0 0) (0 0)
1185 18:10:34.587377 0 10 8 | B1->B0 | 2525 2828 | 0 0 | (0 1) (0 0)
1186 18:10:34.594345 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 18:10:34.597843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 18:10:34.601252 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 18:10:34.605350 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:10:34.608543 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 18:10:34.616242 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 18:10:34.619439 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1193 18:10:34.622568 0 11 8 | B1->B0 | 3c3c 3f3f | 0 0 | (0 0) (0 0)
1194 18:10:34.625928 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 18:10:34.633210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 18:10:34.636887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 18:10:34.639810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:10:34.647029 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 18:10:34.649938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 18:10:34.653689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 18:10:34.656715 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1202 18:10:34.663799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 18:10:34.666732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 18:10:34.670475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 18:10:34.677120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:10:34.680850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:10:34.684038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:10:34.690194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:10:34.693704 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:10:34.696854 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:10:34.703968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:10:34.707187 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:10:34.710819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:10:34.717027 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 18:10:34.720560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 18:10:34.723603 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1217 18:10:34.730104 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 18:10:34.733406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 18:10:34.737099 Total UI for P1: 0, mck2ui 16
1220 18:10:34.740254 best dqsien dly found for B0: ( 0, 14, 8)
1221 18:10:34.743945 Total UI for P1: 0, mck2ui 16
1222 18:10:34.746887 best dqsien dly found for B1: ( 0, 14, 6)
1223 18:10:34.750550 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1224 18:10:34.753451 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1225 18:10:34.753673
1226 18:10:34.757115 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 18:10:34.760726 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 18:10:34.763658 [Gating] SW calibration Done
1229 18:10:34.763942 ==
1230 18:10:34.767200 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 18:10:34.770788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 18:10:34.771246 ==
1233 18:10:34.773865 RX Vref Scan: 0
1234 18:10:34.774275
1235 18:10:34.774638 RX Vref 0 -> 0, step: 1
1236 18:10:34.774953
1237 18:10:34.777442 RX Delay -130 -> 252, step: 16
1238 18:10:34.780422 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1239 18:10:34.786990 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1240 18:10:34.790524 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 18:10:34.793961 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1242 18:10:34.796885 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1243 18:10:34.800399 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1244 18:10:34.807438 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1245 18:10:34.810880 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1246 18:10:34.813676 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1247 18:10:34.817020 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1248 18:10:34.820382 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1249 18:10:34.827560 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1250 18:10:34.830586 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1251 18:10:34.833986 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1252 18:10:34.837582 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1253 18:10:34.840368 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 18:10:34.843700 ==
1255 18:10:34.847283 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 18:10:34.850851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 18:10:34.851403 ==
1258 18:10:34.851884 DQS Delay:
1259 18:10:34.853750 DQS0 = 0, DQS1 = 0
1260 18:10:34.854441 DQM Delay:
1261 18:10:34.857221 DQM0 = 91, DQM1 = 82
1262 18:10:34.857638 DQ Delay:
1263 18:10:34.860920 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1264 18:10:34.863966 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1265 18:10:34.867502 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1266 18:10:34.870181 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1267 18:10:34.870680
1268 18:10:34.871178
1269 18:10:34.871660 ==
1270 18:10:34.873722 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 18:10:34.877409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 18:10:34.877830 ==
1273 18:10:34.878165
1274 18:10:34.878479
1275 18:10:34.880314 TX Vref Scan disable
1276 18:10:34.883906 == TX Byte 0 ==
1277 18:10:34.887608 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1278 18:10:34.890488 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1279 18:10:34.894181 == TX Byte 1 ==
1280 18:10:34.897858 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1281 18:10:34.900450 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1282 18:10:34.900874 ==
1283 18:10:34.903852 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 18:10:34.907418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 18:10:34.910117 ==
1286 18:10:34.922460 TX Vref=22, minBit 13, minWin=27, winSum=448
1287 18:10:34.925891 TX Vref=24, minBit 1, minWin=28, winSum=451
1288 18:10:34.929450 TX Vref=26, minBit 1, minWin=28, winSum=456
1289 18:10:34.932105 TX Vref=28, minBit 1, minWin=28, winSum=456
1290 18:10:34.935433 TX Vref=30, minBit 1, minWin=28, winSum=455
1291 18:10:34.942490 TX Vref=32, minBit 1, minWin=28, winSum=456
1292 18:10:34.946285 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 26
1293 18:10:34.946799
1294 18:10:34.949172 Final TX Range 1 Vref 26
1295 18:10:34.949792
1296 18:10:34.950347 ==
1297 18:10:34.952457 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 18:10:34.955877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 18:10:34.956479 ==
1300 18:10:34.956851
1301 18:10:34.958859
1302 18:10:34.959283 TX Vref Scan disable
1303 18:10:34.962297 == TX Byte 0 ==
1304 18:10:34.965477 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
1305 18:10:34.972377 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
1306 18:10:34.972675 == TX Byte 1 ==
1307 18:10:34.975669 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1308 18:10:34.978659 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1309 18:10:34.982092
1310 18:10:34.982273 [DATLAT]
1311 18:10:34.982381 Freq=800, CH0 RK1
1312 18:10:34.982480
1313 18:10:34.985456 DATLAT Default: 0xa
1314 18:10:34.985652 0, 0xFFFF, sum = 0
1315 18:10:34.989133 1, 0xFFFF, sum = 0
1316 18:10:34.989272 2, 0xFFFF, sum = 0
1317 18:10:34.992071 3, 0xFFFF, sum = 0
1318 18:10:34.992271 4, 0xFFFF, sum = 0
1319 18:10:34.995683 5, 0xFFFF, sum = 0
1320 18:10:34.998702 6, 0xFFFF, sum = 0
1321 18:10:34.998839 7, 0xFFFF, sum = 0
1322 18:10:35.002287 8, 0xFFFF, sum = 0
1323 18:10:35.002478 9, 0x0, sum = 1
1324 18:10:35.002652 10, 0x0, sum = 2
1325 18:10:35.005780 11, 0x0, sum = 3
1326 18:10:35.005962 12, 0x0, sum = 4
1327 18:10:35.009370 best_step = 10
1328 18:10:35.009593
1329 18:10:35.009744 ==
1330 18:10:35.012155 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 18:10:35.016100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 18:10:35.016273 ==
1333 18:10:35.018873 RX Vref Scan: 0
1334 18:10:35.019040
1335 18:10:35.019201 RX Vref 0 -> 0, step: 1
1336 18:10:35.019343
1337 18:10:35.022554 RX Delay -79 -> 252, step: 8
1338 18:10:35.028918 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1339 18:10:35.032565 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1340 18:10:35.035490 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1341 18:10:35.038879 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1342 18:10:35.042356 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1343 18:10:35.048890 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1344 18:10:35.052522 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1345 18:10:35.056177 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1346 18:10:35.059709 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1347 18:10:35.062642 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1348 18:10:35.069432 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1349 18:10:35.072401 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1350 18:10:35.075905 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1351 18:10:35.079563 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1352 18:10:35.082949 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1353 18:10:35.089723 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1354 18:10:35.090150 ==
1355 18:10:35.092893 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 18:10:35.096089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 18:10:35.096625 ==
1358 18:10:35.096968 DQS Delay:
1359 18:10:35.099339 DQS0 = 0, DQS1 = 0
1360 18:10:35.099887 DQM Delay:
1361 18:10:35.102995 DQM0 = 92, DQM1 = 82
1362 18:10:35.103432 DQ Delay:
1363 18:10:35.106573 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1364 18:10:35.109588 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1365 18:10:35.112623 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1366 18:10:35.116445 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1367 18:10:35.116957
1368 18:10:35.117289
1369 18:10:35.122586 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e0e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
1370 18:10:35.126536 CH0 RK1: MR19=606, MR18=3E0E
1371 18:10:35.132600 CH0_RK1: MR19=0x606, MR18=0x3E0E, DQSOSC=394, MR23=63, INC=95, DEC=63
1372 18:10:35.136236 [RxdqsGatingPostProcess] freq 800
1373 18:10:35.143118 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 18:10:35.143659 Pre-setting of DQS Precalculation
1375 18:10:35.150080 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 18:10:35.150599 ==
1377 18:10:35.152636 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 18:10:35.156330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 18:10:35.156825 ==
1380 18:10:35.162670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 18:10:35.169847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 18:10:35.177974 [CA 0] Center 36 (6~67) winsize 62
1383 18:10:35.180998 [CA 1] Center 36 (6~67) winsize 62
1384 18:10:35.184725 [CA 2] Center 34 (4~65) winsize 62
1385 18:10:35.187714 [CA 3] Center 34 (4~65) winsize 62
1386 18:10:35.191366 [CA 4] Center 34 (4~65) winsize 62
1387 18:10:35.194847 [CA 5] Center 34 (4~64) winsize 61
1388 18:10:35.195290
1389 18:10:35.197705 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1390 18:10:35.198159
1391 18:10:35.201309 [CATrainingPosCal] consider 1 rank data
1392 18:10:35.204639 u2DelayCellTimex100 = 270/100 ps
1393 18:10:35.207959 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 18:10:35.211548 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 18:10:35.217851 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 18:10:35.221483 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 18:10:35.224437 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 18:10:35.227890 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 18:10:35.228310
1400 18:10:35.231516 CA PerBit enable=1, Macro0, CA PI delay=34
1401 18:10:35.231953
1402 18:10:35.234920 [CBTSetCACLKResult] CA Dly = 34
1403 18:10:35.235341 CS Dly: 6 (0~37)
1404 18:10:35.235694 ==
1405 18:10:35.237607 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 18:10:35.244170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 18:10:35.244641 ==
1408 18:10:35.247683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 18:10:35.254860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 18:10:35.264996 [CA 0] Center 37 (6~68) winsize 63
1411 18:10:35.267839 [CA 1] Center 36 (6~67) winsize 62
1412 18:10:35.271920 [CA 2] Center 35 (4~66) winsize 63
1413 18:10:35.275511 [CA 3] Center 35 (5~65) winsize 61
1414 18:10:35.278924 [CA 4] Center 35 (5~66) winsize 62
1415 18:10:35.279348 [CA 5] Center 34 (4~65) winsize 62
1416 18:10:35.283439
1417 18:10:35.286896 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 18:10:35.287316
1419 18:10:35.290785 [CATrainingPosCal] consider 2 rank data
1420 18:10:35.291234 u2DelayCellTimex100 = 270/100 ps
1421 18:10:35.293498 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 18:10:35.297913 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 18:10:35.300810 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 18:10:35.307313 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 18:10:35.310804 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 18:10:35.313979 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 18:10:35.314411
1428 18:10:35.317380 CA PerBit enable=1, Macro0, CA PI delay=34
1429 18:10:35.317796
1430 18:10:35.320828 [CBTSetCACLKResult] CA Dly = 34
1431 18:10:35.321344 CS Dly: 6 (0~38)
1432 18:10:35.321687
1433 18:10:35.324146 ----->DramcWriteLeveling(PI) begin...
1434 18:10:35.324754 ==
1435 18:10:35.327769 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 18:10:35.334413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 18:10:35.334993 ==
1438 18:10:35.337355 Write leveling (Byte 0): 28 => 28
1439 18:10:35.340794 Write leveling (Byte 1): 26 => 26
1440 18:10:35.341196 DramcWriteLeveling(PI) end<-----
1441 18:10:35.341553
1442 18:10:35.344463 ==
1443 18:10:35.347307 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 18:10:35.350690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 18:10:35.351128 ==
1446 18:10:35.354261 [Gating] SW mode calibration
1447 18:10:35.360790 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 18:10:35.364406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 18:10:35.370798 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 18:10:35.373866 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 18:10:35.377337 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 18:10:35.384324 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 18:10:35.387411 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 18:10:35.390476 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:10:35.397561 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:10:35.400986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:10:35.403903 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:10:35.411309 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:10:35.414161 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:10:35.417925 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 18:10:35.420786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 18:10:35.427727 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:10:35.431087 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:10:35.434520 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 18:10:35.440597 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 18:10:35.444407 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 18:10:35.447741 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 18:10:35.454162 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 18:10:35.457815 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 18:10:35.461430 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 18:10:35.467373 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:10:35.471115 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 18:10:35.474522 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 18:10:35.480907 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1475 18:10:35.484420 0 9 8 | B1->B0 | 3131 3433 | 1 1 | (1 1) (0 0)
1476 18:10:35.487812 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 18:10:35.491543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 18:10:35.497975 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 18:10:35.501112 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 18:10:35.504313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 18:10:35.510860 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 18:10:35.514500 0 10 4 | B1->B0 | 3232 2f2f | 0 1 | (1 1) (1 1)
1483 18:10:35.517596 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1484 18:10:35.524719 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 18:10:35.527765 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 18:10:35.531374 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 18:10:35.537585 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 18:10:35.541545 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 18:10:35.544928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 18:10:35.551383 0 11 4 | B1->B0 | 2a2a 3636 | 0 1 | (0 0) (0 0)
1491 18:10:35.554857 0 11 8 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
1492 18:10:35.558366 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 18:10:35.564474 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 18:10:35.568026 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 18:10:35.571663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:10:35.574566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 18:10:35.581082 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 18:10:35.584714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1499 18:10:35.588226 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 18:10:35.594871 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 18:10:35.597813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 18:10:35.601592 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:10:35.608074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:10:35.611589 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:10:35.614419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:10:35.621417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:10:35.624613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:10:35.627765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:10:35.634694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:10:35.637961 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:10:35.641587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 18:10:35.648136 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 18:10:35.651681 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1514 18:10:35.655086 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 18:10:35.657896 Total UI for P1: 0, mck2ui 16
1516 18:10:35.661397 best dqsien dly found for B0: ( 0, 14, 2)
1517 18:10:35.664634 Total UI for P1: 0, mck2ui 16
1518 18:10:35.668116 best dqsien dly found for B1: ( 0, 14, 0)
1519 18:10:35.671408 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1520 18:10:35.674804 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1521 18:10:35.675277
1522 18:10:35.678158 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1523 18:10:35.681882 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1524 18:10:35.684759 [Gating] SW calibration Done
1525 18:10:35.685179 ==
1526 18:10:35.688261 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 18:10:35.695054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 18:10:35.695588 ==
1529 18:10:35.695946 RX Vref Scan: 0
1530 18:10:35.696514
1531 18:10:35.698604 RX Vref 0 -> 0, step: 1
1532 18:10:35.699031
1533 18:10:35.701529 RX Delay -130 -> 252, step: 16
1534 18:10:35.704504 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 18:10:35.708022 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1536 18:10:35.711614 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 18:10:35.714558 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 18:10:35.720967 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 18:10:35.724674 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1540 18:10:35.728457 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1541 18:10:35.731263 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 18:10:35.734647 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1543 18:10:35.741525 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1544 18:10:35.744795 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1545 18:10:35.748052 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1546 18:10:35.751389 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 18:10:35.754847 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1548 18:10:35.761368 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1549 18:10:35.764846 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1550 18:10:35.765281 ==
1551 18:10:35.767717 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 18:10:35.771310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 18:10:35.771791 ==
1554 18:10:35.774603 DQS Delay:
1555 18:10:35.775062 DQS0 = 0, DQS1 = 0
1556 18:10:35.775444 DQM Delay:
1557 18:10:35.778271 DQM0 = 93, DQM1 = 89
1558 18:10:35.778718 DQ Delay:
1559 18:10:35.781700 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1560 18:10:35.785021 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1561 18:10:35.788396 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1562 18:10:35.791119 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1563 18:10:35.791561
1564 18:10:35.791902
1565 18:10:35.792209 ==
1566 18:10:35.794584 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 18:10:35.801093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 18:10:35.801576 ==
1569 18:10:35.801934
1570 18:10:35.802245
1571 18:10:35.802543 TX Vref Scan disable
1572 18:10:35.804925 == TX Byte 0 ==
1573 18:10:35.808593 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 18:10:35.814849 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 18:10:35.815296 == TX Byte 1 ==
1576 18:10:35.818709 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1577 18:10:35.824928 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1578 18:10:35.825378 ==
1579 18:10:35.828632 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 18:10:35.831524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 18:10:35.831973 ==
1582 18:10:35.844983 TX Vref=22, minBit 1, minWin=26, winSum=436
1583 18:10:35.848459 TX Vref=24, minBit 0, minWin=27, winSum=441
1584 18:10:35.851941 TX Vref=26, minBit 1, minWin=27, winSum=443
1585 18:10:35.854898 TX Vref=28, minBit 1, minWin=27, winSum=447
1586 18:10:35.858546 TX Vref=30, minBit 1, minWin=27, winSum=449
1587 18:10:35.862138 TX Vref=32, minBit 1, minWin=27, winSum=446
1588 18:10:35.868697 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1589 18:10:35.869169
1590 18:10:35.871818 Final TX Range 1 Vref 30
1591 18:10:35.872422
1592 18:10:35.872908 ==
1593 18:10:35.875049 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 18:10:35.878741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 18:10:35.879409 ==
1596 18:10:35.880000
1597 18:10:35.880375
1598 18:10:35.881727 TX Vref Scan disable
1599 18:10:35.885022 == TX Byte 0 ==
1600 18:10:35.888297 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 18:10:35.891728 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 18:10:35.895213 == TX Byte 1 ==
1603 18:10:35.898798 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1604 18:10:35.902060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1605 18:10:35.902610
1606 18:10:35.905407 [DATLAT]
1607 18:10:35.905867 Freq=800, CH1 RK0
1608 18:10:35.906222
1609 18:10:35.908816 DATLAT Default: 0xa
1610 18:10:35.909264 0, 0xFFFF, sum = 0
1611 18:10:35.911612 1, 0xFFFF, sum = 0
1612 18:10:35.912029 2, 0xFFFF, sum = 0
1613 18:10:35.915244 3, 0xFFFF, sum = 0
1614 18:10:35.915736 4, 0xFFFF, sum = 0
1615 18:10:35.918885 5, 0xFFFF, sum = 0
1616 18:10:35.919424 6, 0xFFFF, sum = 0
1617 18:10:35.921951 7, 0xFFFF, sum = 0
1618 18:10:35.922452 8, 0xFFFF, sum = 0
1619 18:10:35.925566 9, 0x0, sum = 1
1620 18:10:35.926032 10, 0x0, sum = 2
1621 18:10:35.929115 11, 0x0, sum = 3
1622 18:10:35.929677 12, 0x0, sum = 4
1623 18:10:35.930109 best_step = 10
1624 18:10:35.931892
1625 18:10:35.932324 ==
1626 18:10:35.935535 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 18:10:35.938886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 18:10:35.939305 ==
1629 18:10:35.939645 RX Vref Scan: 1
1630 18:10:35.940456
1631 18:10:35.941920 Set Vref Range= 32 -> 127
1632 18:10:35.942299
1633 18:10:35.945760 RX Vref 32 -> 127, step: 1
1634 18:10:35.946193
1635 18:10:35.949218 RX Delay -79 -> 252, step: 8
1636 18:10:35.949654
1637 18:10:35.952450 Set Vref, RX VrefLevel [Byte0]: 32
1638 18:10:35.955418 [Byte1]: 32
1639 18:10:35.955878
1640 18:10:35.958604 Set Vref, RX VrefLevel [Byte0]: 33
1641 18:10:35.962406 [Byte1]: 33
1642 18:10:35.962856
1643 18:10:35.965209 Set Vref, RX VrefLevel [Byte0]: 34
1644 18:10:35.968759 [Byte1]: 34
1645 18:10:35.972475
1646 18:10:35.972902 Set Vref, RX VrefLevel [Byte0]: 35
1647 18:10:35.975267 [Byte1]: 35
1648 18:10:35.979360
1649 18:10:35.979799 Set Vref, RX VrefLevel [Byte0]: 36
1650 18:10:35.983061 [Byte1]: 36
1651 18:10:35.987300
1652 18:10:35.987715 Set Vref, RX VrefLevel [Byte0]: 37
1653 18:10:35.990539 [Byte1]: 37
1654 18:10:35.994371
1655 18:10:35.994783 Set Vref, RX VrefLevel [Byte0]: 38
1656 18:10:35.997784 [Byte1]: 38
1657 18:10:36.002306
1658 18:10:36.002720 Set Vref, RX VrefLevel [Byte0]: 39
1659 18:10:36.005426 [Byte1]: 39
1660 18:10:36.009461
1661 18:10:36.009916 Set Vref, RX VrefLevel [Byte0]: 40
1662 18:10:36.013237 [Byte1]: 40
1663 18:10:36.017209
1664 18:10:36.017623 Set Vref, RX VrefLevel [Byte0]: 41
1665 18:10:36.020300 [Byte1]: 41
1666 18:10:36.024984
1667 18:10:36.025392 Set Vref, RX VrefLevel [Byte0]: 42
1668 18:10:36.028666 [Byte1]: 42
1669 18:10:36.032065
1670 18:10:36.032526 Set Vref, RX VrefLevel [Byte0]: 43
1671 18:10:36.035807 [Byte1]: 43
1672 18:10:36.040291
1673 18:10:36.040771 Set Vref, RX VrefLevel [Byte0]: 44
1674 18:10:36.043290 [Byte1]: 44
1675 18:10:36.047720
1676 18:10:36.048155 Set Vref, RX VrefLevel [Byte0]: 45
1677 18:10:36.051335 [Byte1]: 45
1678 18:10:36.055305
1679 18:10:36.055750 Set Vref, RX VrefLevel [Byte0]: 46
1680 18:10:36.058303 [Byte1]: 46
1681 18:10:36.062432
1682 18:10:36.062943 Set Vref, RX VrefLevel [Byte0]: 47
1683 18:10:36.065813 [Byte1]: 47
1684 18:10:36.069932
1685 18:10:36.070474 Set Vref, RX VrefLevel [Byte0]: 48
1686 18:10:36.073580 [Byte1]: 48
1687 18:10:36.077921
1688 18:10:36.078335 Set Vref, RX VrefLevel [Byte0]: 49
1689 18:10:36.081014 [Byte1]: 49
1690 18:10:36.085187
1691 18:10:36.085603 Set Vref, RX VrefLevel [Byte0]: 50
1692 18:10:36.088783 [Byte1]: 50
1693 18:10:36.092599
1694 18:10:36.093032 Set Vref, RX VrefLevel [Byte0]: 51
1695 18:10:36.095968 [Byte1]: 51
1696 18:10:36.100314
1697 18:10:36.100763 Set Vref, RX VrefLevel [Byte0]: 52
1698 18:10:36.104016 [Byte1]: 52
1699 18:10:36.107739
1700 18:10:36.108163 Set Vref, RX VrefLevel [Byte0]: 53
1701 18:10:36.111125 [Byte1]: 53
1702 18:10:36.115561
1703 18:10:36.116091 Set Vref, RX VrefLevel [Byte0]: 54
1704 18:10:36.118999 [Byte1]: 54
1705 18:10:36.122812
1706 18:10:36.123232 Set Vref, RX VrefLevel [Byte0]: 55
1707 18:10:36.126012 [Byte1]: 55
1708 18:10:36.130562
1709 18:10:36.130973 Set Vref, RX VrefLevel [Byte0]: 56
1710 18:10:36.133612 [Byte1]: 56
1711 18:10:36.137872
1712 18:10:36.138321 Set Vref, RX VrefLevel [Byte0]: 57
1713 18:10:36.141162 [Byte1]: 57
1714 18:10:36.145488
1715 18:10:36.145899 Set Vref, RX VrefLevel [Byte0]: 58
1716 18:10:36.149162 [Byte1]: 58
1717 18:10:36.153526
1718 18:10:36.153950 Set Vref, RX VrefLevel [Byte0]: 59
1719 18:10:36.156448 [Byte1]: 59
1720 18:10:36.160502
1721 18:10:36.160930 Set Vref, RX VrefLevel [Byte0]: 60
1722 18:10:36.164162 [Byte1]: 60
1723 18:10:36.168520
1724 18:10:36.168949 Set Vref, RX VrefLevel [Byte0]: 61
1725 18:10:36.171364 [Byte1]: 61
1726 18:10:36.175983
1727 18:10:36.176436 Set Vref, RX VrefLevel [Byte0]: 62
1728 18:10:36.179118 [Byte1]: 62
1729 18:10:36.183107
1730 18:10:36.183521 Set Vref, RX VrefLevel [Byte0]: 63
1731 18:10:36.186744 [Byte1]: 63
1732 18:10:36.191072
1733 18:10:36.191549 Set Vref, RX VrefLevel [Byte0]: 64
1734 18:10:36.194490 [Byte1]: 64
1735 18:10:36.198118
1736 18:10:36.198527 Set Vref, RX VrefLevel [Byte0]: 65
1737 18:10:36.201708 [Byte1]: 65
1738 18:10:36.205903
1739 18:10:36.206313 Set Vref, RX VrefLevel [Byte0]: 66
1740 18:10:36.209607 [Byte1]: 66
1741 18:10:36.213320
1742 18:10:36.213733 Set Vref, RX VrefLevel [Byte0]: 67
1743 18:10:36.216770 [Byte1]: 67
1744 18:10:36.221214
1745 18:10:36.221624 Set Vref, RX VrefLevel [Byte0]: 68
1746 18:10:36.224148 [Byte1]: 68
1747 18:10:36.228506
1748 18:10:36.228921 Set Vref, RX VrefLevel [Byte0]: 69
1749 18:10:36.232223 [Byte1]: 69
1750 18:10:36.236536
1751 18:10:36.237150 Set Vref, RX VrefLevel [Byte0]: 70
1752 18:10:36.239218 [Byte1]: 70
1753 18:10:36.243493
1754 18:10:36.243903 Set Vref, RX VrefLevel [Byte0]: 71
1755 18:10:36.247375 [Byte1]: 71
1756 18:10:36.251498
1757 18:10:36.251913 Final RX Vref Byte 0 = 57 to rank0
1758 18:10:36.254712 Final RX Vref Byte 1 = 56 to rank0
1759 18:10:36.257871 Final RX Vref Byte 0 = 57 to rank1
1760 18:10:36.261514 Final RX Vref Byte 1 = 56 to rank1==
1761 18:10:36.265044 Dram Type= 6, Freq= 0, CH_1, rank 0
1762 18:10:36.271197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1763 18:10:36.271615 ==
1764 18:10:36.271947 DQS Delay:
1765 18:10:36.272324 DQS0 = 0, DQS1 = 0
1766 18:10:36.274790 DQM Delay:
1767 18:10:36.275283 DQM0 = 95, DQM1 = 90
1768 18:10:36.278071 DQ Delay:
1769 18:10:36.281474 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1770 18:10:36.281903 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1771 18:10:36.284883 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1772 18:10:36.291726 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1773 18:10:36.292178
1774 18:10:36.292660
1775 18:10:36.298094 [DQSOSCAuto] RK0, (LSB)MR18= 0x2946, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1776 18:10:36.301613 CH1 RK0: MR19=606, MR18=2946
1777 18:10:36.307945 CH1_RK0: MR19=0x606, MR18=0x2946, DQSOSC=392, MR23=63, INC=96, DEC=64
1778 18:10:36.308396
1779 18:10:36.311669 ----->DramcWriteLeveling(PI) begin...
1780 18:10:36.312116 ==
1781 18:10:36.314453 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 18:10:36.318168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 18:10:36.318585 ==
1784 18:10:36.321674 Write leveling (Byte 0): 29 => 29
1785 18:10:36.324699 Write leveling (Byte 1): 27 => 27
1786 18:10:36.328291 DramcWriteLeveling(PI) end<-----
1787 18:10:36.328834
1788 18:10:36.329228 ==
1789 18:10:36.331363 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 18:10:36.334758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 18:10:36.335191 ==
1792 18:10:36.338348 [Gating] SW mode calibration
1793 18:10:36.344609 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1794 18:10:36.351683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1795 18:10:36.354507 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1796 18:10:36.358143 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1797 18:10:36.364988 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 18:10:36.367623 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 18:10:36.371003 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 18:10:36.377702 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 18:10:36.381156 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 18:10:36.384302 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 18:10:36.391272 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 18:10:36.394763 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 18:10:36.397710 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 18:10:36.404207 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 18:10:36.407955 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 18:10:36.411327 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 18:10:36.417987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 18:10:36.420863 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 18:10:36.424527 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1812 18:10:36.431052 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1813 18:10:36.434096 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 18:10:36.437592 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 18:10:36.444683 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 18:10:36.447655 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 18:10:36.451093 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 18:10:36.454579 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 18:10:36.460879 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 18:10:36.464687 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1821 18:10:36.467638 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1822 18:10:36.474146 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 18:10:36.477501 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 18:10:36.480853 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 18:10:36.487439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 18:10:36.491108 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 18:10:36.494033 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1828 18:10:36.501060 0 10 4 | B1->B0 | 2b2b 3030 | 0 1 | (0 0) (0 0)
1829 18:10:36.504440 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 18:10:36.507314 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:10:36.514154 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 18:10:36.518000 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 18:10:36.520779 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 18:10:36.527560 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 18:10:36.531034 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 18:10:36.533958 0 11 4 | B1->B0 | 3a3a 2f2f | 0 0 | (0 0) (0 0)
1837 18:10:36.540876 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 18:10:36.544421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 18:10:36.547255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 18:10:36.554518 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 18:10:36.557478 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 18:10:36.560822 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 18:10:36.564397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 18:10:36.570642 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1845 18:10:36.574374 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 18:10:36.577250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 18:10:36.583943 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 18:10:36.587387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 18:10:36.590687 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 18:10:36.597367 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 18:10:36.600875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 18:10:36.604387 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 18:10:36.610932 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 18:10:36.614493 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 18:10:36.617441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 18:10:36.623960 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 18:10:36.627636 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 18:10:36.630605 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 18:10:36.637367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1860 18:10:36.640909 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1861 18:10:36.644499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 18:10:36.647900 Total UI for P1: 0, mck2ui 16
1863 18:10:36.651064 best dqsien dly found for B0: ( 0, 14, 4)
1864 18:10:36.654410 Total UI for P1: 0, mck2ui 16
1865 18:10:36.657667 best dqsien dly found for B1: ( 0, 14, 2)
1866 18:10:36.660591 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1867 18:10:36.663989 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1868 18:10:36.664599
1869 18:10:36.667583 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1870 18:10:36.670782 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1871 18:10:36.674448 [Gating] SW calibration Done
1872 18:10:36.674937 ==
1873 18:10:36.677515 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 18:10:36.681387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 18:10:36.684846 ==
1876 18:10:36.685279 RX Vref Scan: 0
1877 18:10:36.685613
1878 18:10:36.687797 RX Vref 0 -> 0, step: 1
1879 18:10:36.688215
1880 18:10:36.690846 RX Delay -130 -> 252, step: 16
1881 18:10:36.694378 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1882 18:10:36.697735 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1883 18:10:36.700734 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1884 18:10:36.704153 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1885 18:10:36.710694 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1886 18:10:36.714367 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1887 18:10:36.717913 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1888 18:10:36.720908 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1889 18:10:36.724538 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1890 18:10:36.731167 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1891 18:10:36.734101 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1892 18:10:36.737643 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1893 18:10:36.740953 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1894 18:10:36.744361 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1895 18:10:36.750824 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1896 18:10:36.754470 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1897 18:10:36.754892 ==
1898 18:10:36.757445 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 18:10:36.761016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 18:10:36.761438 ==
1901 18:10:36.763781 DQS Delay:
1902 18:10:36.764212 DQS0 = 0, DQS1 = 0
1903 18:10:36.764597 DQM Delay:
1904 18:10:36.767565 DQM0 = 92, DQM1 = 88
1905 18:10:36.767985 DQ Delay:
1906 18:10:36.771001 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1907 18:10:36.774374 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1908 18:10:36.777066 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1909 18:10:36.780594 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1910 18:10:36.781014
1911 18:10:36.781351
1912 18:10:36.781664 ==
1913 18:10:36.784333 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 18:10:36.790977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 18:10:36.791424 ==
1916 18:10:36.791762
1917 18:10:36.792074
1918 18:10:36.792422 TX Vref Scan disable
1919 18:10:36.794839 == TX Byte 0 ==
1920 18:10:36.797831 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1921 18:10:36.801257 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1922 18:10:36.805406 == TX Byte 1 ==
1923 18:10:36.807729 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1924 18:10:36.811205 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1925 18:10:36.814296 ==
1926 18:10:36.817766 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 18:10:36.821243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 18:10:36.821358 ==
1929 18:10:36.833828 TX Vref=22, minBit 0, minWin=27, winSum=443
1930 18:10:36.836692 TX Vref=24, minBit 2, minWin=27, winSum=444
1931 18:10:36.840487 TX Vref=26, minBit 2, minWin=27, winSum=449
1932 18:10:36.844015 TX Vref=28, minBit 2, minWin=27, winSum=449
1933 18:10:36.847010 TX Vref=30, minBit 2, minWin=27, winSum=450
1934 18:10:36.850287 TX Vref=32, minBit 2, minWin=27, winSum=446
1935 18:10:36.857142 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30
1936 18:10:36.857227
1937 18:10:36.860090 Final TX Range 1 Vref 30
1938 18:10:36.860175
1939 18:10:36.860277 ==
1940 18:10:36.863579 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 18:10:36.867040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 18:10:36.867125 ==
1943 18:10:36.867211
1944 18:10:36.867291
1945 18:10:36.870592 TX Vref Scan disable
1946 18:10:36.873636 == TX Byte 0 ==
1947 18:10:36.877200 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1948 18:10:36.880531 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1949 18:10:36.883412 == TX Byte 1 ==
1950 18:10:36.886929 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1951 18:10:36.890567 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1952 18:10:36.890652
1953 18:10:36.894166 [DATLAT]
1954 18:10:36.894263 Freq=800, CH1 RK1
1955 18:10:36.894349
1956 18:10:36.897068 DATLAT Default: 0xa
1957 18:10:36.897166 0, 0xFFFF, sum = 0
1958 18:10:36.900755 1, 0xFFFF, sum = 0
1959 18:10:36.900841 2, 0xFFFF, sum = 0
1960 18:10:36.903670 3, 0xFFFF, sum = 0
1961 18:10:36.903755 4, 0xFFFF, sum = 0
1962 18:10:36.907367 5, 0xFFFF, sum = 0
1963 18:10:36.907452 6, 0xFFFF, sum = 0
1964 18:10:36.910591 7, 0xFFFF, sum = 0
1965 18:10:36.910677 8, 0xFFFF, sum = 0
1966 18:10:36.914140 9, 0x0, sum = 1
1967 18:10:36.914225 10, 0x0, sum = 2
1968 18:10:36.917129 11, 0x0, sum = 3
1969 18:10:36.917215 12, 0x0, sum = 4
1970 18:10:36.920690 best_step = 10
1971 18:10:36.920774
1972 18:10:36.920859 ==
1973 18:10:36.923510 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 18:10:36.927051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 18:10:36.927136 ==
1976 18:10:36.930310 RX Vref Scan: 0
1977 18:10:36.930394
1978 18:10:36.930478 RX Vref 0 -> 0, step: 1
1979 18:10:36.930559
1980 18:10:36.934307 RX Delay -79 -> 252, step: 8
1981 18:10:36.940459 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1982 18:10:36.944044 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1983 18:10:36.947442 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1984 18:10:36.950608 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1985 18:10:36.954138 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1986 18:10:36.957426 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1987 18:10:36.964272 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1988 18:10:36.967313 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1989 18:10:36.970730 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1990 18:10:36.974410 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1991 18:10:36.977310 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1992 18:10:36.980890 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1993 18:10:36.987312 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1994 18:10:36.990789 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1995 18:10:36.994602 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1996 18:10:36.997461 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1997 18:10:36.997548 ==
1998 18:10:37.001038 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 18:10:37.008008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 18:10:37.008109 ==
2001 18:10:37.008189 DQS Delay:
2002 18:10:37.008264 DQS0 = 0, DQS1 = 0
2003 18:10:37.010872 DQM Delay:
2004 18:10:37.010981 DQM0 = 97, DQM1 = 91
2005 18:10:37.014320 DQ Delay:
2006 18:10:37.017793 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2007 18:10:37.021060 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2008 18:10:37.024571 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2009 18:10:37.027554 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2010 18:10:37.027703
2011 18:10:37.027822
2012 18:10:37.034070 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2013 18:10:37.037902 CH1 RK1: MR19=606, MR18=4610
2014 18:10:37.044231 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2015 18:10:37.047940 [RxdqsGatingPostProcess] freq 800
2016 18:10:37.051454 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2017 18:10:37.054743 Pre-setting of DQS Precalculation
2018 18:10:37.061285 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2019 18:10:37.067799 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2020 18:10:37.074522 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2021 18:10:37.074956
2022 18:10:37.075400
2023 18:10:37.078119 [Calibration Summary] 1600 Mbps
2024 18:10:37.078552 CH 0, Rank 0
2025 18:10:37.081024 SW Impedance : PASS
2026 18:10:37.084989 DUTY Scan : NO K
2027 18:10:37.085423 ZQ Calibration : PASS
2028 18:10:37.087820 Jitter Meter : NO K
2029 18:10:37.088267 CBT Training : PASS
2030 18:10:37.091512 Write leveling : PASS
2031 18:10:37.094913 RX DQS gating : PASS
2032 18:10:37.095350 RX DQ/DQS(RDDQC) : PASS
2033 18:10:37.097910 TX DQ/DQS : PASS
2034 18:10:37.101306 RX DATLAT : PASS
2035 18:10:37.101740 RX DQ/DQS(Engine): PASS
2036 18:10:37.104883 TX OE : NO K
2037 18:10:37.105320 All Pass.
2038 18:10:37.105766
2039 18:10:37.107846 CH 0, Rank 1
2040 18:10:37.108277 SW Impedance : PASS
2041 18:10:37.111378 DUTY Scan : NO K
2042 18:10:37.115036 ZQ Calibration : PASS
2043 18:10:37.115468 Jitter Meter : NO K
2044 18:10:37.117990 CBT Training : PASS
2045 18:10:37.121665 Write leveling : PASS
2046 18:10:37.122099 RX DQS gating : PASS
2047 18:10:37.124457 RX DQ/DQS(RDDQC) : PASS
2048 18:10:37.128033 TX DQ/DQS : PASS
2049 18:10:37.128511 RX DATLAT : PASS
2050 18:10:37.131509 RX DQ/DQS(Engine): PASS
2051 18:10:37.131942 TX OE : NO K
2052 18:10:37.134874 All Pass.
2053 18:10:37.135306
2054 18:10:37.135742 CH 1, Rank 0
2055 18:10:37.137836 SW Impedance : PASS
2056 18:10:37.138267 DUTY Scan : NO K
2057 18:10:37.141476 ZQ Calibration : PASS
2058 18:10:37.144935 Jitter Meter : NO K
2059 18:10:37.145368 CBT Training : PASS
2060 18:10:37.147678 Write leveling : PASS
2061 18:10:37.151165 RX DQS gating : PASS
2062 18:10:37.151583 RX DQ/DQS(RDDQC) : PASS
2063 18:10:37.155016 TX DQ/DQS : PASS
2064 18:10:37.157932 RX DATLAT : PASS
2065 18:10:37.158351 RX DQ/DQS(Engine): PASS
2066 18:10:37.161387 TX OE : NO K
2067 18:10:37.161806 All Pass.
2068 18:10:37.162141
2069 18:10:37.164726 CH 1, Rank 1
2070 18:10:37.165143 SW Impedance : PASS
2071 18:10:37.168261 DUTY Scan : NO K
2072 18:10:37.171294 ZQ Calibration : PASS
2073 18:10:37.171710 Jitter Meter : NO K
2074 18:10:37.174606 CBT Training : PASS
2075 18:10:37.175025 Write leveling : PASS
2076 18:10:37.178157 RX DQS gating : PASS
2077 18:10:37.181695 RX DQ/DQS(RDDQC) : PASS
2078 18:10:37.182127 TX DQ/DQS : PASS
2079 18:10:37.184792 RX DATLAT : PASS
2080 18:10:37.188296 RX DQ/DQS(Engine): PASS
2081 18:10:37.188764 TX OE : NO K
2082 18:10:37.191534 All Pass.
2083 18:10:37.191967
2084 18:10:37.192440 DramC Write-DBI off
2085 18:10:37.194566 PER_BANK_REFRESH: Hybrid Mode
2086 18:10:37.195000 TX_TRACKING: ON
2087 18:10:37.198251 [GetDramInforAfterCalByMRR] Vendor 6.
2088 18:10:37.204948 [GetDramInforAfterCalByMRR] Revision 606.
2089 18:10:37.208128 [GetDramInforAfterCalByMRR] Revision 2 0.
2090 18:10:37.208599 MR0 0x3b3b
2091 18:10:37.209049 MR8 0x5151
2092 18:10:37.211735 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2093 18:10:37.212167
2094 18:10:37.215151 MR0 0x3b3b
2095 18:10:37.215584 MR8 0x5151
2096 18:10:37.218030 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 18:10:37.218467
2098 18:10:37.228268 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2099 18:10:37.231174 [FAST_K] Save calibration result to emmc
2100 18:10:37.234719 [FAST_K] Save calibration result to emmc
2101 18:10:37.238138 dram_init: config_dvfs: 1
2102 18:10:37.241733 dramc_set_vcore_voltage set vcore to 662500
2103 18:10:37.244675 Read voltage for 1200, 2
2104 18:10:37.245132 Vio18 = 0
2105 18:10:37.245571 Vcore = 662500
2106 18:10:37.248448 Vdram = 0
2107 18:10:37.248988 Vddq = 0
2108 18:10:37.249429 Vmddr = 0
2109 18:10:37.254690 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2110 18:10:37.258351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2111 18:10:37.261295 MEM_TYPE=3, freq_sel=15
2112 18:10:37.264733 sv_algorithm_assistance_LP4_1600
2113 18:10:37.268314 ============ PULL DRAM RESETB DOWN ============
2114 18:10:37.271736 ========== PULL DRAM RESETB DOWN end =========
2115 18:10:37.278042 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 18:10:37.281499 ===================================
2117 18:10:37.281933 LPDDR4 DRAM CONFIGURATION
2118 18:10:37.284409 ===================================
2119 18:10:37.288018 EX_ROW_EN[0] = 0x0
2120 18:10:37.291570 EX_ROW_EN[1] = 0x0
2121 18:10:37.292003 LP4Y_EN = 0x0
2122 18:10:37.294596 WORK_FSP = 0x0
2123 18:10:37.295028 WL = 0x4
2124 18:10:37.298159 RL = 0x4
2125 18:10:37.298594 BL = 0x2
2126 18:10:37.301758 RPST = 0x0
2127 18:10:37.302211 RD_PRE = 0x0
2128 18:10:37.304791 WR_PRE = 0x1
2129 18:10:37.305206 WR_PST = 0x0
2130 18:10:37.308087 DBI_WR = 0x0
2131 18:10:37.308544 DBI_RD = 0x0
2132 18:10:37.311374 OTF = 0x1
2133 18:10:37.315086 ===================================
2134 18:10:37.318087 ===================================
2135 18:10:37.318524 ANA top config
2136 18:10:37.321315 ===================================
2137 18:10:37.325355 DLL_ASYNC_EN = 0
2138 18:10:37.328087 ALL_SLAVE_EN = 0
2139 18:10:37.328559 NEW_RANK_MODE = 1
2140 18:10:37.331668 DLL_IDLE_MODE = 1
2141 18:10:37.334952 LP45_APHY_COMB_EN = 1
2142 18:10:37.337973 TX_ODT_DIS = 1
2143 18:10:37.341437 NEW_8X_MODE = 1
2144 18:10:37.345217 ===================================
2145 18:10:37.348454 ===================================
2146 18:10:37.348893 data_rate = 2400
2147 18:10:37.351288 CKR = 1
2148 18:10:37.354782 DQ_P2S_RATIO = 8
2149 18:10:37.358197 ===================================
2150 18:10:37.361151 CA_P2S_RATIO = 8
2151 18:10:37.364490 DQ_CA_OPEN = 0
2152 18:10:37.368242 DQ_SEMI_OPEN = 0
2153 18:10:37.368716 CA_SEMI_OPEN = 0
2154 18:10:37.371867 CA_FULL_RATE = 0
2155 18:10:37.374655 DQ_CKDIV4_EN = 0
2156 18:10:37.377930 CA_CKDIV4_EN = 0
2157 18:10:37.381462 CA_PREDIV_EN = 0
2158 18:10:37.381894 PH8_DLY = 17
2159 18:10:37.385296 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2160 18:10:37.388166 DQ_AAMCK_DIV = 4
2161 18:10:37.391931 CA_AAMCK_DIV = 4
2162 18:10:37.395311 CA_ADMCK_DIV = 4
2163 18:10:37.398114 DQ_TRACK_CA_EN = 0
2164 18:10:37.398547 CA_PICK = 1200
2165 18:10:37.401735 CA_MCKIO = 1200
2166 18:10:37.405409 MCKIO_SEMI = 0
2167 18:10:37.408390 PLL_FREQ = 2366
2168 18:10:37.412001 DQ_UI_PI_RATIO = 32
2169 18:10:37.415043 CA_UI_PI_RATIO = 0
2170 18:10:37.418754 ===================================
2171 18:10:37.421615 ===================================
2172 18:10:37.425002 memory_type:LPDDR4
2173 18:10:37.425438 GP_NUM : 10
2174 18:10:37.428544 SRAM_EN : 1
2175 18:10:37.428978 MD32_EN : 0
2176 18:10:37.431471 ===================================
2177 18:10:37.434907 [ANA_INIT] >>>>>>>>>>>>>>
2178 18:10:37.438321 <<<<<< [CONFIGURE PHASE]: ANA_TX
2179 18:10:37.441654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2180 18:10:37.444817 ===================================
2181 18:10:37.447933 data_rate = 2400,PCW = 0X5b00
2182 18:10:37.451553 ===================================
2183 18:10:37.455000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2184 18:10:37.458613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2185 18:10:37.465061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 18:10:37.468393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2187 18:10:37.471670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2188 18:10:37.475434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2189 18:10:37.478649 [ANA_INIT] flow start
2190 18:10:37.482066 [ANA_INIT] PLL >>>>>>>>
2191 18:10:37.482499 [ANA_INIT] PLL <<<<<<<<
2192 18:10:37.484935 [ANA_INIT] MIDPI >>>>>>>>
2193 18:10:37.488294 [ANA_INIT] MIDPI <<<<<<<<
2194 18:10:37.491707 [ANA_INIT] DLL >>>>>>>>
2195 18:10:37.492144 [ANA_INIT] DLL <<<<<<<<
2196 18:10:37.494607 [ANA_INIT] flow end
2197 18:10:37.498086 ============ LP4 DIFF to SE enter ============
2198 18:10:37.501549 ============ LP4 DIFF to SE exit ============
2199 18:10:37.505040 [ANA_INIT] <<<<<<<<<<<<<
2200 18:10:37.507892 [Flow] Enable top DCM control >>>>>
2201 18:10:37.511685 [Flow] Enable top DCM control <<<<<
2202 18:10:37.514464 Enable DLL master slave shuffle
2203 18:10:37.521779 ==============================================================
2204 18:10:37.522213 Gating Mode config
2205 18:10:37.528095 ==============================================================
2206 18:10:37.528580 Config description:
2207 18:10:37.538214 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2208 18:10:37.544719 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2209 18:10:37.551421 SELPH_MODE 0: By rank 1: By Phase
2210 18:10:37.555021 ==============================================================
2211 18:10:37.557912 GAT_TRACK_EN = 1
2212 18:10:37.561511 RX_GATING_MODE = 2
2213 18:10:37.565111 RX_GATING_TRACK_MODE = 2
2214 18:10:37.568128 SELPH_MODE = 1
2215 18:10:37.571492 PICG_EARLY_EN = 1
2216 18:10:37.574764 VALID_LAT_VALUE = 1
2217 18:10:37.578223 ==============================================================
2218 18:10:37.581388 Enter into Gating configuration >>>>
2219 18:10:37.585110 Exit from Gating configuration <<<<
2220 18:10:37.588408 Enter into DVFS_PRE_config >>>>>
2221 18:10:37.601292 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2222 18:10:37.604916 Exit from DVFS_PRE_config <<<<<
2223 18:10:37.608252 Enter into PICG configuration >>>>
2224 18:10:37.608761 Exit from PICG configuration <<<<
2225 18:10:37.611875 [RX_INPUT] configuration >>>>>
2226 18:10:37.614838 [RX_INPUT] configuration <<<<<
2227 18:10:37.621415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2228 18:10:37.625159 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2229 18:10:37.631648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2230 18:10:37.637902 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2231 18:10:37.644962 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 18:10:37.651430 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 18:10:37.654482 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2234 18:10:37.658075 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2235 18:10:37.662032 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2236 18:10:37.668399 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2237 18:10:37.671089 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2238 18:10:37.674605 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2239 18:10:37.678001 ===================================
2240 18:10:37.681617 LPDDR4 DRAM CONFIGURATION
2241 18:10:37.684515 ===================================
2242 18:10:37.688125 EX_ROW_EN[0] = 0x0
2243 18:10:37.688612 EX_ROW_EN[1] = 0x0
2244 18:10:37.691578 LP4Y_EN = 0x0
2245 18:10:37.692016 WORK_FSP = 0x0
2246 18:10:37.694577 WL = 0x4
2247 18:10:37.695066 RL = 0x4
2248 18:10:37.698021 BL = 0x2
2249 18:10:37.698438 RPST = 0x0
2250 18:10:37.701669 RD_PRE = 0x0
2251 18:10:37.702263 WR_PRE = 0x1
2252 18:10:37.704532 WR_PST = 0x0
2253 18:10:37.704997 DBI_WR = 0x0
2254 18:10:37.708124 DBI_RD = 0x0
2255 18:10:37.708615 OTF = 0x1
2256 18:10:37.711572 ===================================
2257 18:10:37.714737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2258 18:10:37.721089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2259 18:10:37.724775 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 18:10:37.727769 ===================================
2261 18:10:37.731242 LPDDR4 DRAM CONFIGURATION
2262 18:10:37.734882 ===================================
2263 18:10:37.735474 EX_ROW_EN[0] = 0x10
2264 18:10:37.737977 EX_ROW_EN[1] = 0x0
2265 18:10:37.738414 LP4Y_EN = 0x0
2266 18:10:37.741057 WORK_FSP = 0x0
2267 18:10:37.744601 WL = 0x4
2268 18:10:37.745042 RL = 0x4
2269 18:10:37.747932 BL = 0x2
2270 18:10:37.748403 RPST = 0x0
2271 18:10:37.751525 RD_PRE = 0x0
2272 18:10:37.751942 WR_PRE = 0x1
2273 18:10:37.755237 WR_PST = 0x0
2274 18:10:37.755672 DBI_WR = 0x0
2275 18:10:37.758051 DBI_RD = 0x0
2276 18:10:37.758600 OTF = 0x1
2277 18:10:37.761750 ===================================
2278 18:10:37.768297 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2279 18:10:37.768971 ==
2280 18:10:37.771190 Dram Type= 6, Freq= 0, CH_0, rank 0
2281 18:10:37.774942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2282 18:10:37.775364 ==
2283 18:10:37.778577 [Duty_Offset_Calibration]
2284 18:10:37.779009 B0:2 B1:1 CA:1
2285 18:10:37.781398
2286 18:10:37.784786 [DutyScan_Calibration_Flow] k_type=0
2287 18:10:37.792903
2288 18:10:37.793338 ==CLK 0==
2289 18:10:37.795812 Final CLK duty delay cell = 0
2290 18:10:37.799308 [0] MAX Duty = 5218%(X100), DQS PI = 24
2291 18:10:37.802595 [0] MIN Duty = 4875%(X100), DQS PI = 0
2292 18:10:37.803036 [0] AVG Duty = 5046%(X100)
2293 18:10:37.806341
2294 18:10:37.806775 CH0 CLK Duty spec in!! Max-Min= 343%
2295 18:10:37.812853 [DutyScan_Calibration_Flow] ====Done====
2296 18:10:37.813347
2297 18:10:37.815759 [DutyScan_Calibration_Flow] k_type=1
2298 18:10:37.831427
2299 18:10:37.831842 ==DQS 0 ==
2300 18:10:37.834170 Final DQS duty delay cell = -4
2301 18:10:37.837822 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2302 18:10:37.841343 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2303 18:10:37.844781 [-4] AVG Duty = 4937%(X100)
2304 18:10:37.845339
2305 18:10:37.845686 ==DQS 1 ==
2306 18:10:37.847649 Final DQS duty delay cell = 0
2307 18:10:37.850773 [0] MAX Duty = 5156%(X100), DQS PI = 14
2308 18:10:37.854549 [0] MIN Duty = 5000%(X100), DQS PI = 32
2309 18:10:37.857776 [0] AVG Duty = 5078%(X100)
2310 18:10:37.858212
2311 18:10:37.861081 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2312 18:10:37.861523
2313 18:10:37.864183 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2314 18:10:37.867763 [DutyScan_Calibration_Flow] ====Done====
2315 18:10:37.868191
2316 18:10:37.870906 [DutyScan_Calibration_Flow] k_type=3
2317 18:10:37.888120
2318 18:10:37.888575 ==DQM 0 ==
2319 18:10:37.891671 Final DQM duty delay cell = 0
2320 18:10:37.895381 [0] MAX Duty = 5156%(X100), DQS PI = 30
2321 18:10:37.897916 [0] MIN Duty = 4906%(X100), DQS PI = 58
2322 18:10:37.901327 [0] AVG Duty = 5031%(X100)
2323 18:10:37.901868
2324 18:10:37.902342 ==DQM 1 ==
2325 18:10:37.904991 Final DQM duty delay cell = 0
2326 18:10:37.907754 [0] MAX Duty = 5093%(X100), DQS PI = 0
2327 18:10:37.911197 [0] MIN Duty = 5031%(X100), DQS PI = 2
2328 18:10:37.911608 [0] AVG Duty = 5062%(X100)
2329 18:10:37.911939
2330 18:10:37.918426 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2331 18:10:37.918865
2332 18:10:37.921491 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2333 18:10:37.925077 [DutyScan_Calibration_Flow] ====Done====
2334 18:10:37.925372
2335 18:10:37.927847 [DutyScan_Calibration_Flow] k_type=2
2336 18:10:37.944032
2337 18:10:37.944229 ==DQ 0 ==
2338 18:10:37.947680 Final DQ duty delay cell = 0
2339 18:10:37.951030 [0] MAX Duty = 5062%(X100), DQS PI = 32
2340 18:10:37.954608 [0] MIN Duty = 4844%(X100), DQS PI = 62
2341 18:10:37.955027 [0] AVG Duty = 4953%(X100)
2342 18:10:37.957661
2343 18:10:37.958132 ==DQ 1 ==
2344 18:10:37.961170 Final DQ duty delay cell = 0
2345 18:10:37.964576 [0] MAX Duty = 5093%(X100), DQS PI = 26
2346 18:10:37.968006 [0] MIN Duty = 4907%(X100), DQS PI = 36
2347 18:10:37.968519 [0] AVG Duty = 5000%(X100)
2348 18:10:37.968887
2349 18:10:37.971440 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2350 18:10:37.971848
2351 18:10:37.977776 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2352 18:10:37.980952 [DutyScan_Calibration_Flow] ====Done====
2353 18:10:37.981372 ==
2354 18:10:37.984749 Dram Type= 6, Freq= 0, CH_1, rank 0
2355 18:10:37.987909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2356 18:10:37.988515 ==
2357 18:10:37.991249 [Duty_Offset_Calibration]
2358 18:10:37.991809 B0:1 B1:0 CA:1
2359 18:10:37.992303
2360 18:10:37.994112 [DutyScan_Calibration_Flow] k_type=0
2361 18:10:38.004043
2362 18:10:38.004734 ==CLK 0==
2363 18:10:38.006660 Final CLK duty delay cell = -4
2364 18:10:38.010447 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2365 18:10:38.013607 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2366 18:10:38.017023 [-4] AVG Duty = 4969%(X100)
2367 18:10:38.017512
2368 18:10:38.020322 CH1 CLK Duty spec in!! Max-Min= 124%
2369 18:10:38.023834 [DutyScan_Calibration_Flow] ====Done====
2370 18:10:38.024510
2371 18:10:38.026672 [DutyScan_Calibration_Flow] k_type=1
2372 18:10:38.043152
2373 18:10:38.043684 ==DQS 0 ==
2374 18:10:38.046533 Final DQS duty delay cell = 0
2375 18:10:38.049995 [0] MAX Duty = 5062%(X100), DQS PI = 22
2376 18:10:38.053733 [0] MIN Duty = 4844%(X100), DQS PI = 0
2377 18:10:38.054244 [0] AVG Duty = 4953%(X100)
2378 18:10:38.056620
2379 18:10:38.057127 ==DQS 1 ==
2380 18:10:38.060166 Final DQS duty delay cell = 0
2381 18:10:38.063710 [0] MAX Duty = 5187%(X100), DQS PI = 20
2382 18:10:38.066623 [0] MIN Duty = 4969%(X100), DQS PI = 8
2383 18:10:38.067232 [0] AVG Duty = 5078%(X100)
2384 18:10:38.070229
2385 18:10:38.073606 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2386 18:10:38.074066
2387 18:10:38.076470 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2388 18:10:38.080102 [DutyScan_Calibration_Flow] ====Done====
2389 18:10:38.080718
2390 18:10:38.083040 [DutyScan_Calibration_Flow] k_type=3
2391 18:10:38.099720
2392 18:10:38.100233 ==DQM 0 ==
2393 18:10:38.102982 Final DQM duty delay cell = 0
2394 18:10:38.106473 [0] MAX Duty = 5156%(X100), DQS PI = 6
2395 18:10:38.110019 [0] MIN Duty = 5000%(X100), DQS PI = 62
2396 18:10:38.110430 [0] AVG Duty = 5078%(X100)
2397 18:10:38.113385
2398 18:10:38.113790 ==DQM 1 ==
2399 18:10:38.116859 Final DQM duty delay cell = 0
2400 18:10:38.119351 [0] MAX Duty = 5031%(X100), DQS PI = 16
2401 18:10:38.122703 [0] MIN Duty = 4875%(X100), DQS PI = 52
2402 18:10:38.122785 [0] AVG Duty = 4953%(X100)
2403 18:10:38.126120
2404 18:10:38.129155 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2405 18:10:38.129235
2406 18:10:38.132591 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2407 18:10:38.136282 [DutyScan_Calibration_Flow] ====Done====
2408 18:10:38.136390
2409 18:10:38.139254 [DutyScan_Calibration_Flow] k_type=2
2410 18:10:38.154989
2411 18:10:38.155076 ==DQ 0 ==
2412 18:10:38.158678 Final DQ duty delay cell = -4
2413 18:10:38.162442 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2414 18:10:38.165322 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2415 18:10:38.169159 [-4] AVG Duty = 4984%(X100)
2416 18:10:38.169240
2417 18:10:38.169306 ==DQ 1 ==
2418 18:10:38.171868 Final DQ duty delay cell = 0
2419 18:10:38.175331 [0] MAX Duty = 5125%(X100), DQS PI = 20
2420 18:10:38.178861 [0] MIN Duty = 4969%(X100), DQS PI = 12
2421 18:10:38.178943 [0] AVG Duty = 5047%(X100)
2422 18:10:38.181757
2423 18:10:38.185230 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2424 18:10:38.185310
2425 18:10:38.188825 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2426 18:10:38.192210 [DutyScan_Calibration_Flow] ====Done====
2427 18:10:38.195569 nWR fixed to 30
2428 18:10:38.195651 [ModeRegInit_LP4] CH0 RK0
2429 18:10:38.198531 [ModeRegInit_LP4] CH0 RK1
2430 18:10:38.201981 [ModeRegInit_LP4] CH1 RK0
2431 18:10:38.205511 [ModeRegInit_LP4] CH1 RK1
2432 18:10:38.205591 match AC timing 7
2433 18:10:38.208267 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2434 18:10:38.215353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2435 18:10:38.218680 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2436 18:10:38.224957 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2437 18:10:38.228567 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2438 18:10:38.228648 ==
2439 18:10:38.232256 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 18:10:38.235099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 18:10:38.235180 ==
2442 18:10:38.241724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2443 18:10:38.248758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2444 18:10:38.255663 [CA 0] Center 39 (8~70) winsize 63
2445 18:10:38.259115 [CA 1] Center 39 (8~70) winsize 63
2446 18:10:38.261976 [CA 2] Center 35 (5~66) winsize 62
2447 18:10:38.265262 [CA 3] Center 34 (4~65) winsize 62
2448 18:10:38.268886 [CA 4] Center 33 (3~64) winsize 62
2449 18:10:38.272476 [CA 5] Center 32 (3~62) winsize 60
2450 18:10:38.272556
2451 18:10:38.275900 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2452 18:10:38.275980
2453 18:10:38.278687 [CATrainingPosCal] consider 1 rank data
2454 18:10:38.282292 u2DelayCellTimex100 = 270/100 ps
2455 18:10:38.285921 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2456 18:10:38.288932 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 18:10:38.296004 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2458 18:10:38.299000 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2459 18:10:38.302217 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2460 18:10:38.305897 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2461 18:10:38.305978
2462 18:10:38.309371 CA PerBit enable=1, Macro0, CA PI delay=32
2463 18:10:38.309452
2464 18:10:38.312367 [CBTSetCACLKResult] CA Dly = 32
2465 18:10:38.312462 CS Dly: 6 (0~37)
2466 18:10:38.312532 ==
2467 18:10:38.315748 Dram Type= 6, Freq= 0, CH_0, rank 1
2468 18:10:38.322632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 18:10:38.322713 ==
2470 18:10:38.326140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 18:10:38.332478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 18:10:38.340948 [CA 0] Center 39 (9~69) winsize 61
2473 18:10:38.344598 [CA 1] Center 38 (8~69) winsize 62
2474 18:10:38.347995 [CA 2] Center 35 (4~66) winsize 63
2475 18:10:38.351404 [CA 3] Center 34 (4~65) winsize 62
2476 18:10:38.354780 [CA 4] Center 33 (3~63) winsize 61
2477 18:10:38.358043 [CA 5] Center 32 (3~62) winsize 60
2478 18:10:38.358116
2479 18:10:38.361306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2480 18:10:38.361382
2481 18:10:38.364616 [CATrainingPosCal] consider 2 rank data
2482 18:10:38.368201 u2DelayCellTimex100 = 270/100 ps
2483 18:10:38.371421 CA0 delay=39 (9~69),Diff = 7 PI (33 cell)
2484 18:10:38.374149 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 18:10:38.381432 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2486 18:10:38.384334 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2487 18:10:38.387865 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2488 18:10:38.391447 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2489 18:10:38.391532
2490 18:10:38.394371 CA PerBit enable=1, Macro0, CA PI delay=32
2491 18:10:38.394451
2492 18:10:38.397955 [CBTSetCACLKResult] CA Dly = 32
2493 18:10:38.398036 CS Dly: 6 (0~38)
2494 18:10:38.398100
2495 18:10:38.401616 ----->DramcWriteLeveling(PI) begin...
2496 18:10:38.404299 ==
2497 18:10:38.407867 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 18:10:38.411462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 18:10:38.411543 ==
2500 18:10:38.414479 Write leveling (Byte 0): 36 => 36
2501 18:10:38.418211 Write leveling (Byte 1): 29 => 29
2502 18:10:38.421112 DramcWriteLeveling(PI) end<-----
2503 18:10:38.421205
2504 18:10:38.421269 ==
2505 18:10:38.424630 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 18:10:38.428040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 18:10:38.428120 ==
2508 18:10:38.430996 [Gating] SW mode calibration
2509 18:10:38.438203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2510 18:10:38.440992 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2511 18:10:38.448179 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (0 0)
2512 18:10:38.451092 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2513 18:10:38.454701 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 18:10:38.460986 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 18:10:38.464524 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 18:10:38.467930 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 18:10:38.474712 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 18:10:38.477646 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
2519 18:10:38.481553 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2520 18:10:38.488195 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2521 18:10:38.491054 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 18:10:38.494664 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 18:10:38.501166 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 18:10:38.504703 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 18:10:38.508428 1 0 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
2526 18:10:38.511205 1 0 28 | B1->B0 | 2525 4545 | 0 1 | (1 1) (0 0)
2527 18:10:38.518485 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2528 18:10:38.521390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 18:10:38.525044 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 18:10:38.531939 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 18:10:38.535414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 18:10:38.538303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 18:10:38.545063 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2534 18:10:38.548600 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2535 18:10:38.551349 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2536 18:10:38.558114 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 18:10:38.561423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 18:10:38.564968 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 18:10:38.571936 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 18:10:38.574768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 18:10:38.578404 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 18:10:38.584738 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 18:10:38.588307 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 18:10:38.591525 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 18:10:38.595244 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 18:10:38.601654 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 18:10:38.604974 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 18:10:38.608281 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 18:10:38.615314 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 18:10:38.618223 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2551 18:10:38.621778 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2552 18:10:38.625412 Total UI for P1: 0, mck2ui 16
2553 18:10:38.628215 best dqsien dly found for B0: ( 1, 3, 28)
2554 18:10:38.635347 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 18:10:38.635423 Total UI for P1: 0, mck2ui 16
2556 18:10:38.641562 best dqsien dly found for B1: ( 1, 4, 0)
2557 18:10:38.645200 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2558 18:10:38.648735 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2559 18:10:38.648817
2560 18:10:38.651678 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2561 18:10:38.655249 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2562 18:10:38.658498 [Gating] SW calibration Done
2563 18:10:38.658571 ==
2564 18:10:38.662144 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 18:10:38.664949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 18:10:38.665029 ==
2567 18:10:38.668365 RX Vref Scan: 0
2568 18:10:38.668437
2569 18:10:38.668500 RX Vref 0 -> 0, step: 1
2570 18:10:38.668560
2571 18:10:38.671735 RX Delay -40 -> 252, step: 8
2572 18:10:38.674889 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2573 18:10:38.678635 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2574 18:10:38.685248 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2575 18:10:38.688766 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2576 18:10:38.691546 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2577 18:10:38.695149 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2578 18:10:38.698194 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2579 18:10:38.705225 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2580 18:10:38.708661 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2581 18:10:38.712185 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2582 18:10:38.715234 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2583 18:10:38.718578 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2584 18:10:38.724887 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2585 18:10:38.728513 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2586 18:10:38.732046 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2587 18:10:38.735574 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2588 18:10:38.735648 ==
2589 18:10:38.738356 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 18:10:38.745359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 18:10:38.745442 ==
2592 18:10:38.745524 DQS Delay:
2593 18:10:38.745603 DQS0 = 0, DQS1 = 0
2594 18:10:38.748943 DQM Delay:
2595 18:10:38.749014 DQM0 = 121, DQM1 = 113
2596 18:10:38.751888 DQ Delay:
2597 18:10:38.755568 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2598 18:10:38.759224 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2599 18:10:38.762279 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2600 18:10:38.765857 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2601 18:10:38.765935
2602 18:10:38.765999
2603 18:10:38.766057 ==
2604 18:10:38.768847 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 18:10:38.772429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2606 18:10:38.772506 ==
2607 18:10:38.772567
2608 18:10:38.775098
2609 18:10:38.775167 TX Vref Scan disable
2610 18:10:38.778678 == TX Byte 0 ==
2611 18:10:38.782294 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2612 18:10:38.785393 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2613 18:10:38.788715 == TX Byte 1 ==
2614 18:10:38.792116 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2615 18:10:38.795602 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2616 18:10:38.795675 ==
2617 18:10:38.798750 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 18:10:38.805581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 18:10:38.805659 ==
2620 18:10:38.816085 TX Vref=22, minBit 0, minWin=25, winSum=403
2621 18:10:38.819783 TX Vref=24, minBit 3, minWin=25, winSum=410
2622 18:10:38.822892 TX Vref=26, minBit 11, minWin=25, winSum=418
2623 18:10:38.826617 TX Vref=28, minBit 13, minWin=25, winSum=419
2624 18:10:38.829725 TX Vref=30, minBit 5, minWin=25, winSum=422
2625 18:10:38.833094 TX Vref=32, minBit 2, minWin=26, winSum=424
2626 18:10:38.840061 [TxChooseVref] Worse bit 2, Min win 26, Win sum 424, Final Vref 32
2627 18:10:38.840153
2628 18:10:38.843055 Final TX Range 1 Vref 32
2629 18:10:38.843130
2630 18:10:38.843192 ==
2631 18:10:38.846545 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 18:10:38.849840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 18:10:38.849922 ==
2634 18:10:38.849988
2635 18:10:38.850050
2636 18:10:38.853208 TX Vref Scan disable
2637 18:10:38.856796 == TX Byte 0 ==
2638 18:10:38.859812 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2639 18:10:38.863350 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2640 18:10:38.866335 == TX Byte 1 ==
2641 18:10:38.869982 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2642 18:10:38.873705 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2643 18:10:38.873782
2644 18:10:38.876545 [DATLAT]
2645 18:10:38.876620 Freq=1200, CH0 RK0
2646 18:10:38.876682
2647 18:10:38.880107 DATLAT Default: 0xd
2648 18:10:38.880204 0, 0xFFFF, sum = 0
2649 18:10:38.883675 1, 0xFFFF, sum = 0
2650 18:10:38.883751 2, 0xFFFF, sum = 0
2651 18:10:38.886558 3, 0xFFFF, sum = 0
2652 18:10:38.886632 4, 0xFFFF, sum = 0
2653 18:10:38.890357 5, 0xFFFF, sum = 0
2654 18:10:38.890433 6, 0xFFFF, sum = 0
2655 18:10:38.893337 7, 0xFFFF, sum = 0
2656 18:10:38.893411 8, 0xFFFF, sum = 0
2657 18:10:38.896832 9, 0xFFFF, sum = 0
2658 18:10:38.896908 10, 0xFFFF, sum = 0
2659 18:10:38.900475 11, 0xFFFF, sum = 0
2660 18:10:38.900558 12, 0x0, sum = 1
2661 18:10:38.903390 13, 0x0, sum = 2
2662 18:10:38.903466 14, 0x0, sum = 3
2663 18:10:38.906926 15, 0x0, sum = 4
2664 18:10:38.907014 best_step = 13
2665 18:10:38.907080
2666 18:10:38.907229 ==
2667 18:10:38.910662 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 18:10:38.916908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 18:10:38.916990 ==
2670 18:10:38.917056 RX Vref Scan: 1
2671 18:10:38.917118
2672 18:10:38.920228 Set Vref Range= 32 -> 127
2673 18:10:38.920307
2674 18:10:38.923623 RX Vref 32 -> 127, step: 1
2675 18:10:38.923778
2676 18:10:38.923873 RX Delay -13 -> 252, step: 4
2677 18:10:38.927221
2678 18:10:38.927326 Set Vref, RX VrefLevel [Byte0]: 32
2679 18:10:38.929994 [Byte1]: 32
2680 18:10:38.934958
2681 18:10:38.935037 Set Vref, RX VrefLevel [Byte0]: 33
2682 18:10:38.937797 [Byte1]: 33
2683 18:10:38.942587
2684 18:10:38.942660 Set Vref, RX VrefLevel [Byte0]: 34
2685 18:10:38.946065 [Byte1]: 34
2686 18:10:38.950816
2687 18:10:38.950893 Set Vref, RX VrefLevel [Byte0]: 35
2688 18:10:38.953848 [Byte1]: 35
2689 18:10:38.958470
2690 18:10:38.958543 Set Vref, RX VrefLevel [Byte0]: 36
2691 18:10:38.961716 [Byte1]: 36
2692 18:10:38.966605
2693 18:10:38.966681 Set Vref, RX VrefLevel [Byte0]: 37
2694 18:10:38.969598 [Byte1]: 37
2695 18:10:38.974201
2696 18:10:38.974276 Set Vref, RX VrefLevel [Byte0]: 38
2697 18:10:38.977856 [Byte1]: 38
2698 18:10:38.982262
2699 18:10:38.982334 Set Vref, RX VrefLevel [Byte0]: 39
2700 18:10:38.985202 [Byte1]: 39
2701 18:10:38.990328
2702 18:10:38.990400 Set Vref, RX VrefLevel [Byte0]: 40
2703 18:10:38.993217 [Byte1]: 40
2704 18:10:38.998220
2705 18:10:38.998294 Set Vref, RX VrefLevel [Byte0]: 41
2706 18:10:39.001182 [Byte1]: 41
2707 18:10:39.006267
2708 18:10:39.006341 Set Vref, RX VrefLevel [Byte0]: 42
2709 18:10:39.009259 [Byte1]: 42
2710 18:10:39.013545
2711 18:10:39.013621 Set Vref, RX VrefLevel [Byte0]: 43
2712 18:10:39.016990 [Byte1]: 43
2713 18:10:39.021796
2714 18:10:39.021870 Set Vref, RX VrefLevel [Byte0]: 44
2715 18:10:39.024630 [Byte1]: 44
2716 18:10:39.029443
2717 18:10:39.029524 Set Vref, RX VrefLevel [Byte0]: 45
2718 18:10:39.033038 [Byte1]: 45
2719 18:10:39.037603
2720 18:10:39.037679 Set Vref, RX VrefLevel [Byte0]: 46
2721 18:10:39.040494 [Byte1]: 46
2722 18:10:39.045571
2723 18:10:39.045650 Set Vref, RX VrefLevel [Byte0]: 47
2724 18:10:39.048488 [Byte1]: 47
2725 18:10:39.052852
2726 18:10:39.052930 Set Vref, RX VrefLevel [Byte0]: 48
2727 18:10:39.056300 [Byte1]: 48
2728 18:10:39.061216
2729 18:10:39.061292 Set Vref, RX VrefLevel [Byte0]: 49
2730 18:10:39.064582 [Byte1]: 49
2731 18:10:39.069106
2732 18:10:39.069187 Set Vref, RX VrefLevel [Byte0]: 50
2733 18:10:39.072234 [Byte1]: 50
2734 18:10:39.076701
2735 18:10:39.076820 Set Vref, RX VrefLevel [Byte0]: 51
2736 18:10:39.080114 [Byte1]: 51
2737 18:10:39.084634
2738 18:10:39.084710 Set Vref, RX VrefLevel [Byte0]: 52
2739 18:10:39.087840 [Byte1]: 52
2740 18:10:39.092823
2741 18:10:39.092895 Set Vref, RX VrefLevel [Byte0]: 53
2742 18:10:39.096257 [Byte1]: 53
2743 18:10:39.100565
2744 18:10:39.100639 Set Vref, RX VrefLevel [Byte0]: 54
2745 18:10:39.103411 [Byte1]: 54
2746 18:10:39.108001
2747 18:10:39.108077 Set Vref, RX VrefLevel [Byte0]: 55
2748 18:10:39.111694 [Byte1]: 55
2749 18:10:39.116109
2750 18:10:39.116178 Set Vref, RX VrefLevel [Byte0]: 56
2751 18:10:39.119829 [Byte1]: 56
2752 18:10:39.124539
2753 18:10:39.124613 Set Vref, RX VrefLevel [Byte0]: 57
2754 18:10:39.127307 [Byte1]: 57
2755 18:10:39.132076
2756 18:10:39.132150 Set Vref, RX VrefLevel [Byte0]: 58
2757 18:10:39.135698 [Byte1]: 58
2758 18:10:39.140049
2759 18:10:39.140121 Set Vref, RX VrefLevel [Byte0]: 59
2760 18:10:39.143361 [Byte1]: 59
2761 18:10:39.148057
2762 18:10:39.148138 Set Vref, RX VrefLevel [Byte0]: 60
2763 18:10:39.151507 [Byte1]: 60
2764 18:10:39.155843
2765 18:10:39.155919 Set Vref, RX VrefLevel [Byte0]: 61
2766 18:10:39.158690 [Byte1]: 61
2767 18:10:39.163884
2768 18:10:39.163959 Set Vref, RX VrefLevel [Byte0]: 62
2769 18:10:39.166832 [Byte1]: 62
2770 18:10:39.171217
2771 18:10:39.171292 Set Vref, RX VrefLevel [Byte0]: 63
2772 18:10:39.174753 [Byte1]: 63
2773 18:10:39.179613
2774 18:10:39.179688 Set Vref, RX VrefLevel [Byte0]: 64
2775 18:10:39.182895 [Byte1]: 64
2776 18:10:39.186954
2777 18:10:39.187030 Set Vref, RX VrefLevel [Byte0]: 65
2778 18:10:39.190677 [Byte1]: 65
2779 18:10:39.194979
2780 18:10:39.195055 Set Vref, RX VrefLevel [Byte0]: 66
2781 18:10:39.198384 [Byte1]: 66
2782 18:10:39.203125
2783 18:10:39.203196 Set Vref, RX VrefLevel [Byte0]: 67
2784 18:10:39.206377 [Byte1]: 67
2785 18:10:39.211240
2786 18:10:39.211309 Set Vref, RX VrefLevel [Byte0]: 68
2787 18:10:39.214036 [Byte1]: 68
2788 18:10:39.219017
2789 18:10:39.219099 Set Vref, RX VrefLevel [Byte0]: 69
2790 18:10:39.221997 [Byte1]: 69
2791 18:10:39.226765
2792 18:10:39.226847 Final RX Vref Byte 0 = 53 to rank0
2793 18:10:39.230306 Final RX Vref Byte 1 = 48 to rank0
2794 18:10:39.233658 Final RX Vref Byte 0 = 53 to rank1
2795 18:10:39.236447 Final RX Vref Byte 1 = 48 to rank1==
2796 18:10:39.240011 Dram Type= 6, Freq= 0, CH_0, rank 0
2797 18:10:39.246409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2798 18:10:39.246492 ==
2799 18:10:39.246559 DQS Delay:
2800 18:10:39.246621 DQS0 = 0, DQS1 = 0
2801 18:10:39.250070 DQM Delay:
2802 18:10:39.250182 DQM0 = 120, DQM1 = 111
2803 18:10:39.253596 DQ Delay:
2804 18:10:39.256918 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2805 18:10:39.259576 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2806 18:10:39.263109 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
2807 18:10:39.266911 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2808 18:10:39.267010
2809 18:10:39.267100
2810 18:10:39.276267 [DQSOSCAuto] RK0, (LSB)MR18= 0x110a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2811 18:10:39.276397 CH0 RK0: MR19=404, MR18=110A
2812 18:10:39.283137 CH0_RK0: MR19=0x404, MR18=0x110A, DQSOSC=403, MR23=63, INC=40, DEC=26
2813 18:10:39.283216
2814 18:10:39.286749 ----->DramcWriteLeveling(PI) begin...
2815 18:10:39.286832 ==
2816 18:10:39.290378 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 18:10:39.293603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 18:10:39.296446 ==
2819 18:10:39.296526 Write leveling (Byte 0): 35 => 35
2820 18:10:39.300228 Write leveling (Byte 1): 29 => 29
2821 18:10:39.303076 DramcWriteLeveling(PI) end<-----
2822 18:10:39.303152
2823 18:10:39.303239 ==
2824 18:10:39.306773 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 18:10:39.313353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 18:10:39.313431 ==
2827 18:10:39.316309 [Gating] SW mode calibration
2828 18:10:39.322961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2829 18:10:39.326713 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2830 18:10:39.333344 0 15 0 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
2831 18:10:39.336543 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2832 18:10:39.340222 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 18:10:39.343682 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 18:10:39.350182 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 18:10:39.353154 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 18:10:39.356803 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 18:10:39.363201 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 1)
2838 18:10:39.366583 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2839 18:10:39.369933 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2840 18:10:39.376649 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 18:10:39.380228 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 18:10:39.382971 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 18:10:39.390346 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 18:10:39.393184 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2845 18:10:39.396682 1 0 28 | B1->B0 | 3838 3a3a | 1 1 | (0 0) (0 0)
2846 18:10:39.403515 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2847 18:10:39.407006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 18:10:39.409980 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 18:10:39.416563 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 18:10:39.420257 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 18:10:39.423750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 18:10:39.426773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 18:10:39.433914 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2854 18:10:39.436667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 18:10:39.440288 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 18:10:39.447180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 18:10:39.450270 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 18:10:39.453885 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 18:10:39.460366 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 18:10:39.463664 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 18:10:39.467336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 18:10:39.473767 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 18:10:39.477058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 18:10:39.480296 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 18:10:39.483593 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 18:10:39.490456 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 18:10:39.493929 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 18:10:39.496915 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 18:10:39.503462 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2870 18:10:39.507195 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2871 18:10:39.510595 Total UI for P1: 0, mck2ui 16
2872 18:10:39.514129 best dqsien dly found for B1: ( 1, 3, 28)
2873 18:10:39.516896 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 18:10:39.520599 Total UI for P1: 0, mck2ui 16
2875 18:10:39.523485 best dqsien dly found for B0: ( 1, 3, 30)
2876 18:10:39.527157 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2877 18:10:39.530695 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2878 18:10:39.530776
2879 18:10:39.537358 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2880 18:10:39.540245 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2881 18:10:39.543908 [Gating] SW calibration Done
2882 18:10:39.543989 ==
2883 18:10:39.546826 Dram Type= 6, Freq= 0, CH_0, rank 1
2884 18:10:39.550571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2885 18:10:39.550685 ==
2886 18:10:39.550781 RX Vref Scan: 0
2887 18:10:39.550881
2888 18:10:39.553410 RX Vref 0 -> 0, step: 1
2889 18:10:39.553507
2890 18:10:39.556962 RX Delay -40 -> 252, step: 8
2891 18:10:39.560214 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2892 18:10:39.563402 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2893 18:10:39.566841 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2894 18:10:39.574157 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2895 18:10:39.576933 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2896 18:10:39.580204 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2897 18:10:39.583710 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
2898 18:10:39.586870 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2899 18:10:39.593595 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2900 18:10:39.597497 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2901 18:10:39.600735 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2902 18:10:39.603772 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2903 18:10:39.607584 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2904 18:10:39.614017 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2905 18:10:39.617401 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2906 18:10:39.620939 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2907 18:10:39.621021 ==
2908 18:10:39.623697 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 18:10:39.627253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 18:10:39.627335 ==
2911 18:10:39.630953 DQS Delay:
2912 18:10:39.631035 DQS0 = 0, DQS1 = 0
2913 18:10:39.633873 DQM Delay:
2914 18:10:39.633954 DQM0 = 121, DQM1 = 112
2915 18:10:39.634019 DQ Delay:
2916 18:10:39.637371 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2917 18:10:39.643874 DQ4 =127, DQ5 =119, DQ6 =123, DQ7 =127
2918 18:10:39.647563 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2919 18:10:39.650457 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2920 18:10:39.650565
2921 18:10:39.650656
2922 18:10:39.650754 ==
2923 18:10:39.654116 Dram Type= 6, Freq= 0, CH_0, rank 1
2924 18:10:39.657086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2925 18:10:39.657186 ==
2926 18:10:39.657268
2927 18:10:39.657345
2928 18:10:39.660618 TX Vref Scan disable
2929 18:10:39.664251 == TX Byte 0 ==
2930 18:10:39.667136 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2931 18:10:39.670477 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2932 18:10:39.670595 == TX Byte 1 ==
2933 18:10:39.677607 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2934 18:10:39.680409 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2935 18:10:39.680508 ==
2936 18:10:39.683877 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 18:10:39.687215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 18:10:39.687322 ==
2939 18:10:39.701209 TX Vref=22, minBit 1, minWin=24, winSum=412
2940 18:10:39.704290 TX Vref=24, minBit 3, minWin=25, winSum=419
2941 18:10:39.707648 TX Vref=26, minBit 1, minWin=25, winSum=416
2942 18:10:39.711298 TX Vref=28, minBit 5, minWin=25, winSum=421
2943 18:10:39.714745 TX Vref=30, minBit 5, minWin=25, winSum=425
2944 18:10:39.717408 TX Vref=32, minBit 5, minWin=25, winSum=424
2945 18:10:39.724594 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 30
2946 18:10:39.724677
2947 18:10:39.727885 Final TX Range 1 Vref 30
2948 18:10:39.727966
2949 18:10:39.728032 ==
2950 18:10:39.731012 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 18:10:39.734697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 18:10:39.734780 ==
2953 18:10:39.734846
2954 18:10:39.737598
2955 18:10:39.737680 TX Vref Scan disable
2956 18:10:39.740746 == TX Byte 0 ==
2957 18:10:39.744477 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2958 18:10:39.747363 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2959 18:10:39.751019 == TX Byte 1 ==
2960 18:10:39.754508 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2961 18:10:39.758193 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2962 18:10:39.758275
2963 18:10:39.761163 [DATLAT]
2964 18:10:39.761244 Freq=1200, CH0 RK1
2965 18:10:39.761310
2966 18:10:39.764672 DATLAT Default: 0xd
2967 18:10:39.764753 0, 0xFFFF, sum = 0
2968 18:10:39.767588 1, 0xFFFF, sum = 0
2969 18:10:39.767671 2, 0xFFFF, sum = 0
2970 18:10:39.771245 3, 0xFFFF, sum = 0
2971 18:10:39.771328 4, 0xFFFF, sum = 0
2972 18:10:39.774709 5, 0xFFFF, sum = 0
2973 18:10:39.774793 6, 0xFFFF, sum = 0
2974 18:10:39.777889 7, 0xFFFF, sum = 0
2975 18:10:39.777972 8, 0xFFFF, sum = 0
2976 18:10:39.781234 9, 0xFFFF, sum = 0
2977 18:10:39.784591 10, 0xFFFF, sum = 0
2978 18:10:39.784673 11, 0xFFFF, sum = 0
2979 18:10:39.788220 12, 0x0, sum = 1
2980 18:10:39.788302 13, 0x0, sum = 2
2981 18:10:39.788410 14, 0x0, sum = 3
2982 18:10:39.790838 15, 0x0, sum = 4
2983 18:10:39.790921 best_step = 13
2984 18:10:39.790985
2985 18:10:39.791046 ==
2986 18:10:39.794554 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 18:10:39.801033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 18:10:39.801115 ==
2989 18:10:39.801181 RX Vref Scan: 0
2990 18:10:39.801243
2991 18:10:39.804577 RX Vref 0 -> 0, step: 1
2992 18:10:39.804658
2993 18:10:39.808131 RX Delay -13 -> 252, step: 4
2994 18:10:39.811149 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2995 18:10:39.814471 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2996 18:10:39.821424 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2997 18:10:39.825039 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2998 18:10:39.827921 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
2999 18:10:39.831263 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3000 18:10:39.834892 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3001 18:10:39.841176 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3002 18:10:39.844590 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3003 18:10:39.847856 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3004 18:10:39.851035 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3005 18:10:39.854307 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3006 18:10:39.861005 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3007 18:10:39.864673 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3008 18:10:39.867509 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3009 18:10:39.871154 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3010 18:10:39.871266 ==
3011 18:10:39.874652 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 18:10:39.881027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 18:10:39.881111 ==
3014 18:10:39.881213 DQS Delay:
3015 18:10:39.881321 DQS0 = 0, DQS1 = 0
3016 18:10:39.884416 DQM Delay:
3017 18:10:39.884530 DQM0 = 120, DQM1 = 110
3018 18:10:39.888015 DQ Delay:
3019 18:10:39.891300 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3020 18:10:39.894137 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3021 18:10:39.897831 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3022 18:10:39.900887 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3023 18:10:39.900969
3024 18:10:39.901034
3025 18:10:39.907868 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3026 18:10:39.910939 CH0 RK1: MR19=403, MR18=CED
3027 18:10:39.918065 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3028 18:10:39.920777 [RxdqsGatingPostProcess] freq 1200
3029 18:10:39.927567 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3030 18:10:39.930933 best DQS0 dly(2T, 0.5T) = (0, 11)
3031 18:10:39.931054 best DQS1 dly(2T, 0.5T) = (0, 12)
3032 18:10:39.934144 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3033 18:10:39.937618 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3034 18:10:39.941241 best DQS0 dly(2T, 0.5T) = (0, 11)
3035 18:10:39.944260 best DQS1 dly(2T, 0.5T) = (0, 11)
3036 18:10:39.947838 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3037 18:10:39.951393 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3038 18:10:39.954323 Pre-setting of DQS Precalculation
3039 18:10:39.961139 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3040 18:10:39.961293 ==
3041 18:10:39.964324 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 18:10:39.967673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 18:10:39.967837 ==
3044 18:10:39.974503 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3045 18:10:39.977372 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3046 18:10:39.987415 [CA 0] Center 37 (7~68) winsize 62
3047 18:10:39.990138 [CA 1] Center 37 (7~68) winsize 62
3048 18:10:39.994940 [CA 2] Center 35 (5~65) winsize 61
3049 18:10:39.997264 [CA 3] Center 35 (5~65) winsize 61
3050 18:10:40.000021 [CA 4] Center 35 (5~65) winsize 61
3051 18:10:40.004077 [CA 5] Center 33 (3~63) winsize 61
3052 18:10:40.004189
3053 18:10:40.007026 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3054 18:10:40.007132
3055 18:10:40.010741 [CATrainingPosCal] consider 1 rank data
3056 18:10:40.013635 u2DelayCellTimex100 = 270/100 ps
3057 18:10:40.017145 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3058 18:10:40.020704 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 18:10:40.024412 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3060 18:10:40.030679 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3061 18:10:40.034213 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 18:10:40.037400 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3063 18:10:40.037480
3064 18:10:40.040845 CA PerBit enable=1, Macro0, CA PI delay=33
3065 18:10:40.040948
3066 18:10:40.044130 [CBTSetCACLKResult] CA Dly = 33
3067 18:10:40.044230 CS Dly: 7 (0~38)
3068 18:10:40.044322 ==
3069 18:10:40.047465 Dram Type= 6, Freq= 0, CH_1, rank 1
3070 18:10:40.054448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 18:10:40.054557 ==
3072 18:10:40.057438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 18:10:40.063897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3074 18:10:40.072462 [CA 0] Center 37 (7~68) winsize 62
3075 18:10:40.076103 [CA 1] Center 38 (7~69) winsize 63
3076 18:10:40.079237 [CA 2] Center 35 (5~65) winsize 61
3077 18:10:40.082566 [CA 3] Center 34 (4~65) winsize 62
3078 18:10:40.086415 [CA 4] Center 34 (4~65) winsize 62
3079 18:10:40.089522 [CA 5] Center 33 (4~63) winsize 60
3080 18:10:40.089607
3081 18:10:40.092556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3082 18:10:40.092669
3083 18:10:40.096155 [CATrainingPosCal] consider 2 rank data
3084 18:10:40.099402 u2DelayCellTimex100 = 270/100 ps
3085 18:10:40.102778 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 18:10:40.106255 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 18:10:40.109643 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 18:10:40.115995 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 18:10:40.119538 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 18:10:40.123244 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3091 18:10:40.123350
3092 18:10:40.126182 CA PerBit enable=1, Macro0, CA PI delay=33
3093 18:10:40.126278
3094 18:10:40.129846 [CBTSetCACLKResult] CA Dly = 33
3095 18:10:40.129951 CS Dly: 8 (0~41)
3096 18:10:40.130041
3097 18:10:40.132712 ----->DramcWriteLeveling(PI) begin...
3098 18:10:40.132790 ==
3099 18:10:40.136307 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 18:10:40.143230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 18:10:40.143338 ==
3102 18:10:40.146079 Write leveling (Byte 0): 26 => 26
3103 18:10:40.149597 Write leveling (Byte 1): 28 => 28
3104 18:10:40.149705 DramcWriteLeveling(PI) end<-----
3105 18:10:40.149798
3106 18:10:40.152951 ==
3107 18:10:40.156639 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 18:10:40.160076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 18:10:40.160192 ==
3110 18:10:40.162941 [Gating] SW mode calibration
3111 18:10:40.169295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3112 18:10:40.172946 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3113 18:10:40.179415 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3114 18:10:40.183120 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 18:10:40.185982 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 18:10:40.193172 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 18:10:40.196053 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 18:10:40.199383 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 18:10:40.205869 0 15 24 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
3120 18:10:40.209527 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3121 18:10:40.212547 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3122 18:10:40.219886 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 18:10:40.222718 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 18:10:40.226289 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 18:10:40.232978 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 18:10:40.236409 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 18:10:40.239412 1 0 24 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
3128 18:10:40.242976 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3129 18:10:40.249324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 18:10:40.253418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 18:10:40.256299 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 18:10:40.263168 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 18:10:40.266545 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 18:10:40.269970 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 18:10:40.276314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3136 18:10:40.280036 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 18:10:40.283002 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 18:10:40.289621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 18:10:40.293378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 18:10:40.296946 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 18:10:40.303548 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 18:10:40.307082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 18:10:40.309737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 18:10:40.313273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 18:10:40.319970 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 18:10:40.323285 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 18:10:40.326768 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 18:10:40.333191 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 18:10:40.336602 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 18:10:40.339964 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 18:10:40.346722 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3152 18:10:40.350371 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 18:10:40.353803 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 18:10:40.356480 Total UI for P1: 0, mck2ui 16
3155 18:10:40.360327 best dqsien dly found for B0: ( 1, 3, 26)
3156 18:10:40.363783 Total UI for P1: 0, mck2ui 16
3157 18:10:40.367009 best dqsien dly found for B1: ( 1, 3, 26)
3158 18:10:40.370403 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3159 18:10:40.373547 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3160 18:10:40.373641
3161 18:10:40.377163 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3162 18:10:40.383787 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3163 18:10:40.383871 [Gating] SW calibration Done
3164 18:10:40.383937 ==
3165 18:10:40.386519 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 18:10:40.393619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 18:10:40.393703 ==
3168 18:10:40.393769 RX Vref Scan: 0
3169 18:10:40.393831
3170 18:10:40.396732 RX Vref 0 -> 0, step: 1
3171 18:10:40.396856
3172 18:10:40.400210 RX Delay -40 -> 252, step: 8
3173 18:10:40.403746 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3174 18:10:40.406730 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 18:10:40.410359 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 18:10:40.417055 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 18:10:40.419899 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 18:10:40.423560 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 18:10:40.427121 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3180 18:10:40.429896 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3181 18:10:40.436388 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3182 18:10:40.440061 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3183 18:10:40.443681 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 18:10:40.446564 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 18:10:40.450319 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 18:10:40.456628 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 18:10:40.459840 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 18:10:40.463128 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 18:10:40.463231 ==
3190 18:10:40.466841 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 18:10:40.469812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 18:10:40.469916 ==
3193 18:10:40.473196 DQS Delay:
3194 18:10:40.473294 DQS0 = 0, DQS1 = 0
3195 18:10:40.476755 DQM Delay:
3196 18:10:40.476830 DQM0 = 120, DQM1 = 116
3197 18:10:40.476910 DQ Delay:
3198 18:10:40.480024 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3199 18:10:40.483397 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3200 18:10:40.489965 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3201 18:10:40.493122 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 18:10:40.493198
3203 18:10:40.493279
3204 18:10:40.493372 ==
3205 18:10:40.496875 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 18:10:40.500062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 18:10:40.500160 ==
3208 18:10:40.500259
3209 18:10:40.500392
3210 18:10:40.503478 TX Vref Scan disable
3211 18:10:40.507095 == TX Byte 0 ==
3212 18:10:40.509876 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 18:10:40.513506 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 18:10:40.517099 == TX Byte 1 ==
3215 18:10:40.519934 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3216 18:10:40.523608 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3217 18:10:40.523690 ==
3218 18:10:40.527021 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 18:10:40.529960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 18:10:40.530035 ==
3221 18:10:40.543205 TX Vref=22, minBit 9, minWin=24, winSum=411
3222 18:10:40.546110 TX Vref=24, minBit 9, minWin=24, winSum=417
3223 18:10:40.549620 TX Vref=26, minBit 9, minWin=25, winSum=420
3224 18:10:40.553265 TX Vref=28, minBit 1, minWin=26, winSum=428
3225 18:10:40.556151 TX Vref=30, minBit 2, minWin=26, winSum=430
3226 18:10:40.559934 TX Vref=32, minBit 9, minWin=26, winSum=435
3227 18:10:40.566406 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32
3228 18:10:40.566509
3229 18:10:40.569927 Final TX Range 1 Vref 32
3230 18:10:40.570027
3231 18:10:40.570157 ==
3232 18:10:40.573435 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 18:10:40.576949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 18:10:40.577028 ==
3235 18:10:40.577128
3236 18:10:40.577228
3237 18:10:40.580143 TX Vref Scan disable
3238 18:10:40.583171 == TX Byte 0 ==
3239 18:10:40.586436 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 18:10:40.590082 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 18:10:40.593508 == TX Byte 1 ==
3242 18:10:40.596209 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3243 18:10:40.599792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3244 18:10:40.599897
3245 18:10:40.603384 [DATLAT]
3246 18:10:40.603486 Freq=1200, CH1 RK0
3247 18:10:40.603590
3248 18:10:40.606634 DATLAT Default: 0xd
3249 18:10:40.606714 0, 0xFFFF, sum = 0
3250 18:10:40.610041 1, 0xFFFF, sum = 0
3251 18:10:40.610119 2, 0xFFFF, sum = 0
3252 18:10:40.613228 3, 0xFFFF, sum = 0
3253 18:10:40.613331 4, 0xFFFF, sum = 0
3254 18:10:40.616506 5, 0xFFFF, sum = 0
3255 18:10:40.616588 6, 0xFFFF, sum = 0
3256 18:10:40.619829 7, 0xFFFF, sum = 0
3257 18:10:40.619935 8, 0xFFFF, sum = 0
3258 18:10:40.623002 9, 0xFFFF, sum = 0
3259 18:10:40.623077 10, 0xFFFF, sum = 0
3260 18:10:40.626337 11, 0xFFFF, sum = 0
3261 18:10:40.626442 12, 0x0, sum = 1
3262 18:10:40.629734 13, 0x0, sum = 2
3263 18:10:40.629831 14, 0x0, sum = 3
3264 18:10:40.633309 15, 0x0, sum = 4
3265 18:10:40.633381 best_step = 13
3266 18:10:40.633445
3267 18:10:40.633504 ==
3268 18:10:40.636228 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 18:10:40.642918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 18:10:40.642998 ==
3271 18:10:40.643066 RX Vref Scan: 1
3272 18:10:40.643130
3273 18:10:40.646746 Set Vref Range= 32 -> 127
3274 18:10:40.646844
3275 18:10:40.649552 RX Vref 32 -> 127, step: 1
3276 18:10:40.649621
3277 18:10:40.649685 RX Delay -5 -> 252, step: 4
3278 18:10:40.653203
3279 18:10:40.653298 Set Vref, RX VrefLevel [Byte0]: 32
3280 18:10:40.656826 [Byte1]: 32
3281 18:10:40.661106
3282 18:10:40.661181 Set Vref, RX VrefLevel [Byte0]: 33
3283 18:10:40.664070 [Byte1]: 33
3284 18:10:40.668665
3285 18:10:40.668740 Set Vref, RX VrefLevel [Byte0]: 34
3286 18:10:40.672316 [Byte1]: 34
3287 18:10:40.676668
3288 18:10:40.676741 Set Vref, RX VrefLevel [Byte0]: 35
3289 18:10:40.680188 [Byte1]: 35
3290 18:10:40.684544
3291 18:10:40.684621 Set Vref, RX VrefLevel [Byte0]: 36
3292 18:10:40.688082 [Byte1]: 36
3293 18:10:40.692201
3294 18:10:40.692304 Set Vref, RX VrefLevel [Byte0]: 37
3295 18:10:40.695669 [Byte1]: 37
3296 18:10:40.700159
3297 18:10:40.700257 Set Vref, RX VrefLevel [Byte0]: 38
3298 18:10:40.703663 [Byte1]: 38
3299 18:10:40.708194
3300 18:10:40.708295 Set Vref, RX VrefLevel [Byte0]: 39
3301 18:10:40.711374 [Byte1]: 39
3302 18:10:40.716187
3303 18:10:40.716292 Set Vref, RX VrefLevel [Byte0]: 40
3304 18:10:40.718962 [Byte1]: 40
3305 18:10:40.723641
3306 18:10:40.723749 Set Vref, RX VrefLevel [Byte0]: 41
3307 18:10:40.726976 [Byte1]: 41
3308 18:10:40.731858
3309 18:10:40.731962 Set Vref, RX VrefLevel [Byte0]: 42
3310 18:10:40.735250 [Byte1]: 42
3311 18:10:40.739425
3312 18:10:40.739536 Set Vref, RX VrefLevel [Byte0]: 43
3313 18:10:40.742986 [Byte1]: 43
3314 18:10:40.747077
3315 18:10:40.747178 Set Vref, RX VrefLevel [Byte0]: 44
3316 18:10:40.750341 [Byte1]: 44
3317 18:10:40.754819
3318 18:10:40.754927 Set Vref, RX VrefLevel [Byte0]: 45
3319 18:10:40.758550 [Byte1]: 45
3320 18:10:40.762750
3321 18:10:40.762849 Set Vref, RX VrefLevel [Byte0]: 46
3322 18:10:40.766450 [Byte1]: 46
3323 18:10:40.770942
3324 18:10:40.771041 Set Vref, RX VrefLevel [Byte0]: 47
3325 18:10:40.774379 [Byte1]: 47
3326 18:10:40.778605
3327 18:10:40.778707 Set Vref, RX VrefLevel [Byte0]: 48
3328 18:10:40.782254 [Byte1]: 48
3329 18:10:40.786566
3330 18:10:40.786674 Set Vref, RX VrefLevel [Byte0]: 49
3331 18:10:40.789557 [Byte1]: 49
3332 18:10:40.794608
3333 18:10:40.794705 Set Vref, RX VrefLevel [Byte0]: 50
3334 18:10:40.797669 [Byte1]: 50
3335 18:10:40.802594
3336 18:10:40.802667 Set Vref, RX VrefLevel [Byte0]: 51
3337 18:10:40.805626 [Byte1]: 51
3338 18:10:40.810358
3339 18:10:40.810457 Set Vref, RX VrefLevel [Byte0]: 52
3340 18:10:40.816206 [Byte1]: 52
3341 18:10:40.816306
3342 18:10:40.820114 Set Vref, RX VrefLevel [Byte0]: 53
3343 18:10:40.823563 [Byte1]: 53
3344 18:10:40.823660
3345 18:10:40.826815 Set Vref, RX VrefLevel [Byte0]: 54
3346 18:10:40.829877 [Byte1]: 54
3347 18:10:40.833550
3348 18:10:40.833649 Set Vref, RX VrefLevel [Byte0]: 55
3349 18:10:40.836983 [Byte1]: 55
3350 18:10:40.841393
3351 18:10:40.841494 Set Vref, RX VrefLevel [Byte0]: 56
3352 18:10:40.844510 [Byte1]: 56
3353 18:10:40.849166
3354 18:10:40.849269 Set Vref, RX VrefLevel [Byte0]: 57
3355 18:10:40.852598 [Byte1]: 57
3356 18:10:40.857255
3357 18:10:40.857330 Set Vref, RX VrefLevel [Byte0]: 58
3358 18:10:40.861030 [Byte1]: 58
3359 18:10:40.865358
3360 18:10:40.865460 Set Vref, RX VrefLevel [Byte0]: 59
3361 18:10:40.868179 [Byte1]: 59
3362 18:10:40.873410
3363 18:10:40.873513 Set Vref, RX VrefLevel [Byte0]: 60
3364 18:10:40.876202 [Byte1]: 60
3365 18:10:40.880523
3366 18:10:40.880624 Set Vref, RX VrefLevel [Byte0]: 61
3367 18:10:40.884276 [Byte1]: 61
3368 18:10:40.888526
3369 18:10:40.888631 Set Vref, RX VrefLevel [Byte0]: 62
3370 18:10:40.892163 [Byte1]: 62
3371 18:10:40.896618
3372 18:10:40.896720 Set Vref, RX VrefLevel [Byte0]: 63
3373 18:10:40.899455 [Byte1]: 63
3374 18:10:40.904531
3375 18:10:40.904632 Set Vref, RX VrefLevel [Byte0]: 64
3376 18:10:40.907387 [Byte1]: 64
3377 18:10:40.912323
3378 18:10:40.915357 Set Vref, RX VrefLevel [Byte0]: 65
3379 18:10:40.918281 [Byte1]: 65
3380 18:10:40.918383
3381 18:10:40.921784 Set Vref, RX VrefLevel [Byte0]: 66
3382 18:10:40.925185 [Byte1]: 66
3383 18:10:40.925286
3384 18:10:40.928976 Set Vref, RX VrefLevel [Byte0]: 67
3385 18:10:40.931655 [Byte1]: 67
3386 18:10:40.936030
3387 18:10:40.936134 Set Vref, RX VrefLevel [Byte0]: 68
3388 18:10:40.939333 [Byte1]: 68
3389 18:10:40.943593
3390 18:10:40.943696 Final RX Vref Byte 0 = 55 to rank0
3391 18:10:40.946830 Final RX Vref Byte 1 = 52 to rank0
3392 18:10:40.950340 Final RX Vref Byte 0 = 55 to rank1
3393 18:10:40.953691 Final RX Vref Byte 1 = 52 to rank1==
3394 18:10:40.957243 Dram Type= 6, Freq= 0, CH_1, rank 0
3395 18:10:40.960196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3396 18:10:40.963984 ==
3397 18:10:40.964093 DQS Delay:
3398 18:10:40.964203 DQS0 = 0, DQS1 = 0
3399 18:10:40.967323 DQM Delay:
3400 18:10:40.967423 DQM0 = 120, DQM1 = 117
3401 18:10:40.970701 DQ Delay:
3402 18:10:40.973923 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3403 18:10:40.977109 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3404 18:10:40.980254 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3405 18:10:40.983973 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3406 18:10:40.984079
3407 18:10:40.984183
3408 18:10:40.990224 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3409 18:10:40.993826 CH1 RK0: MR19=304, MR18=FF12
3410 18:10:41.000432 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3411 18:10:41.000542
3412 18:10:41.004135 ----->DramcWriteLeveling(PI) begin...
3413 18:10:41.004248 ==
3414 18:10:41.007015 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 18:10:41.010621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 18:10:41.010726 ==
3417 18:10:41.014369 Write leveling (Byte 0): 26 => 26
3418 18:10:41.017713 Write leveling (Byte 1): 28 => 28
3419 18:10:41.020746 DramcWriteLeveling(PI) end<-----
3420 18:10:41.020834
3421 18:10:41.020899 ==
3422 18:10:41.024266 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 18:10:41.027084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 18:10:41.030484 ==
3425 18:10:41.030584 [Gating] SW mode calibration
3426 18:10:41.040492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3427 18:10:41.044059 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3428 18:10:41.047355 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 18:10:41.053783 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 18:10:41.057243 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 18:10:41.060828 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 18:10:41.067366 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 18:10:41.071067 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3434 18:10:41.074248 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (1 0) (0 0)
3435 18:10:41.080790 0 15 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 0)
3436 18:10:41.083959 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 18:10:41.087426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 18:10:41.090762 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 18:10:41.097384 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 18:10:41.100963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 18:10:41.104588 1 0 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3442 18:10:41.111139 1 0 24 | B1->B0 | 4444 2e2e | 0 0 | (0 0) (0 0)
3443 18:10:41.114106 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 18:10:41.117705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 18:10:41.123919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 18:10:41.127562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 18:10:41.131158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 18:10:41.137299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 18:10:41.140906 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3450 18:10:41.144441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3451 18:10:41.150944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3452 18:10:41.154458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 18:10:41.157314 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 18:10:41.164242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 18:10:41.167167 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 18:10:41.170749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 18:10:41.177160 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 18:10:41.180674 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 18:10:41.183562 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 18:10:41.190245 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 18:10:41.193595 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 18:10:41.197068 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 18:10:41.204022 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 18:10:41.207428 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 18:10:41.210740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3466 18:10:41.216882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3467 18:10:41.220462 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3468 18:10:41.224221 Total UI for P1: 0, mck2ui 16
3469 18:10:41.226937 best dqsien dly found for B1: ( 1, 3, 22)
3470 18:10:41.230539 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 18:10:41.233472 Total UI for P1: 0, mck2ui 16
3472 18:10:41.237146 best dqsien dly found for B0: ( 1, 3, 26)
3473 18:10:41.239978 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3474 18:10:41.243570 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3475 18:10:41.243667
3476 18:10:41.246984 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3477 18:10:41.253379 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3478 18:10:41.253458 [Gating] SW calibration Done
3479 18:10:41.253524 ==
3480 18:10:41.256960 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 18:10:41.263285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 18:10:41.263389 ==
3483 18:10:41.263481 RX Vref Scan: 0
3484 18:10:41.263569
3485 18:10:41.267019 RX Vref 0 -> 0, step: 1
3486 18:10:41.267146
3487 18:10:41.270273 RX Delay -40 -> 252, step: 8
3488 18:10:41.273893 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3489 18:10:41.276682 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3490 18:10:41.280450 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3491 18:10:41.286721 iDelay=208, Bit 3, Center 119 (56 ~ 183) 128
3492 18:10:41.290461 iDelay=208, Bit 4, Center 119 (56 ~ 183) 128
3493 18:10:41.293230 iDelay=208, Bit 5, Center 135 (64 ~ 207) 144
3494 18:10:41.296798 iDelay=208, Bit 6, Center 131 (64 ~ 199) 136
3495 18:10:41.300218 iDelay=208, Bit 7, Center 123 (56 ~ 191) 136
3496 18:10:41.306815 iDelay=208, Bit 8, Center 107 (40 ~ 175) 136
3497 18:10:41.310172 iDelay=208, Bit 9, Center 107 (40 ~ 175) 136
3498 18:10:41.313119 iDelay=208, Bit 10, Center 119 (48 ~ 191) 144
3499 18:10:41.316295 iDelay=208, Bit 11, Center 115 (48 ~ 183) 136
3500 18:10:41.319594 iDelay=208, Bit 12, Center 127 (56 ~ 199) 144
3501 18:10:41.326712 iDelay=208, Bit 13, Center 127 (64 ~ 191) 128
3502 18:10:41.329632 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
3503 18:10:41.333238 iDelay=208, Bit 15, Center 123 (56 ~ 191) 136
3504 18:10:41.333336 ==
3505 18:10:41.336827 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 18:10:41.339870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 18:10:41.339971 ==
3508 18:10:41.343485 DQS Delay:
3509 18:10:41.343579 DQS0 = 0, DQS1 = 0
3510 18:10:41.346314 DQM Delay:
3511 18:10:41.346410 DQM0 = 121, DQM1 = 118
3512 18:10:41.349943 DQ Delay:
3513 18:10:41.353168 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3514 18:10:41.356807 DQ4 =119, DQ5 =135, DQ6 =131, DQ7 =123
3515 18:10:41.359569 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3516 18:10:41.363309 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3517 18:10:41.363404
3518 18:10:41.363494
3519 18:10:41.363580 ==
3520 18:10:41.366693 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 18:10:41.369422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 18:10:41.369499 ==
3523 18:10:41.369561
3524 18:10:41.369619
3525 18:10:41.373035 TX Vref Scan disable
3526 18:10:41.376486 == TX Byte 0 ==
3527 18:10:41.380090 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3528 18:10:41.383039 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3529 18:10:41.386580 == TX Byte 1 ==
3530 18:10:41.390182 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3531 18:10:41.393094 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3532 18:10:41.393193 ==
3533 18:10:41.396190 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 18:10:41.399631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 18:10:41.403215 ==
3536 18:10:41.413066 TX Vref=22, minBit 9, minWin=25, winSum=420
3537 18:10:41.416436 TX Vref=24, minBit 9, minWin=25, winSum=426
3538 18:10:41.419695 TX Vref=26, minBit 10, minWin=25, winSum=429
3539 18:10:41.423060 TX Vref=28, minBit 2, minWin=26, winSum=430
3540 18:10:41.426524 TX Vref=30, minBit 10, minWin=26, winSum=438
3541 18:10:41.433228 TX Vref=32, minBit 9, minWin=26, winSum=432
3542 18:10:41.436034 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
3543 18:10:41.436142
3544 18:10:41.439647 Final TX Range 1 Vref 30
3545 18:10:41.439745
3546 18:10:41.439845 ==
3547 18:10:41.443272 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 18:10:41.446203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 18:10:41.449861 ==
3550 18:10:41.449958
3551 18:10:41.450057
3552 18:10:41.450147 TX Vref Scan disable
3553 18:10:41.452842 == TX Byte 0 ==
3554 18:10:41.456180 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 18:10:41.462909 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 18:10:41.462988 == TX Byte 1 ==
3557 18:10:41.465864 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3558 18:10:41.472998 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3559 18:10:41.473076
3560 18:10:41.473140 [DATLAT]
3561 18:10:41.473200 Freq=1200, CH1 RK1
3562 18:10:41.473258
3563 18:10:41.476450 DATLAT Default: 0xd
3564 18:10:41.479259 0, 0xFFFF, sum = 0
3565 18:10:41.479361 1, 0xFFFF, sum = 0
3566 18:10:41.483083 2, 0xFFFF, sum = 0
3567 18:10:41.483184 3, 0xFFFF, sum = 0
3568 18:10:41.485812 4, 0xFFFF, sum = 0
3569 18:10:41.485923 5, 0xFFFF, sum = 0
3570 18:10:41.489434 6, 0xFFFF, sum = 0
3571 18:10:41.489537 7, 0xFFFF, sum = 0
3572 18:10:41.492343 8, 0xFFFF, sum = 0
3573 18:10:41.492430 9, 0xFFFF, sum = 0
3574 18:10:41.495891 10, 0xFFFF, sum = 0
3575 18:10:41.495965 11, 0xFFFF, sum = 0
3576 18:10:41.499400 12, 0x0, sum = 1
3577 18:10:41.499470 13, 0x0, sum = 2
3578 18:10:41.502406 14, 0x0, sum = 3
3579 18:10:41.502475 15, 0x0, sum = 4
3580 18:10:41.506066 best_step = 13
3581 18:10:41.506134
3582 18:10:41.506197 ==
3583 18:10:41.509698 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 18:10:41.512626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 18:10:41.512726 ==
3586 18:10:41.512816 RX Vref Scan: 0
3587 18:10:41.515485
3588 18:10:41.515579 RX Vref 0 -> 0, step: 1
3589 18:10:41.515671
3590 18:10:41.519186 RX Delay -5 -> 252, step: 4
3591 18:10:41.522180 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3592 18:10:41.529016 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3593 18:10:41.532239 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3594 18:10:41.535361 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3595 18:10:41.538639 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3596 18:10:41.541994 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3597 18:10:41.548582 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3598 18:10:41.552108 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3599 18:10:41.555895 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3600 18:10:41.558691 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3601 18:10:41.562416 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3602 18:10:41.568639 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3603 18:10:41.571952 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3604 18:10:41.575579 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3605 18:10:41.578325 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3606 18:10:41.585306 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3607 18:10:41.585407 ==
3608 18:10:41.588220 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 18:10:41.591633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 18:10:41.591710 ==
3611 18:10:41.591774 DQS Delay:
3612 18:10:41.595232 DQS0 = 0, DQS1 = 0
3613 18:10:41.595327 DQM Delay:
3614 18:10:41.598620 DQM0 = 120, DQM1 = 118
3615 18:10:41.598720 DQ Delay:
3616 18:10:41.601475 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3617 18:10:41.605144 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3618 18:10:41.608008 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3619 18:10:41.611610 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3620 18:10:41.611704
3621 18:10:41.615111
3622 18:10:41.621692 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3623 18:10:41.625227 CH1 RK1: MR19=403, MR18=11EE
3624 18:10:41.631771 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3625 18:10:41.635396 [RxdqsGatingPostProcess] freq 1200
3626 18:10:41.638133 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3627 18:10:41.641673 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 18:10:41.644816 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 18:10:41.648254 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 18:10:41.651691 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 18:10:41.654844 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 18:10:41.658095 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 18:10:41.661377 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 18:10:41.665238 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 18:10:41.668025 Pre-setting of DQS Precalculation
3636 18:10:41.671327 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3637 18:10:41.677914 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3638 18:10:41.688270 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3639 18:10:41.688382
3640 18:10:41.688451
3641 18:10:41.688514 [Calibration Summary] 2400 Mbps
3642 18:10:41.691946 CH 0, Rank 0
3643 18:10:41.694723 SW Impedance : PASS
3644 18:10:41.694830 DUTY Scan : NO K
3645 18:10:41.698240 ZQ Calibration : PASS
3646 18:10:41.698351 Jitter Meter : NO K
3647 18:10:41.701659 CBT Training : PASS
3648 18:10:41.704467 Write leveling : PASS
3649 18:10:41.704555 RX DQS gating : PASS
3650 18:10:41.708103 RX DQ/DQS(RDDQC) : PASS
3651 18:10:41.711778 TX DQ/DQS : PASS
3652 18:10:41.711896 RX DATLAT : PASS
3653 18:10:41.714446 RX DQ/DQS(Engine): PASS
3654 18:10:41.718133 TX OE : NO K
3655 18:10:41.718233 All Pass.
3656 18:10:41.718333
3657 18:10:41.718423 CH 0, Rank 1
3658 18:10:41.721768 SW Impedance : PASS
3659 18:10:41.724731 DUTY Scan : NO K
3660 18:10:41.724837 ZQ Calibration : PASS
3661 18:10:41.727626 Jitter Meter : NO K
3662 18:10:41.731310 CBT Training : PASS
3663 18:10:41.731421 Write leveling : PASS
3664 18:10:41.734186 RX DQS gating : PASS
3665 18:10:41.737896 RX DQ/DQS(RDDQC) : PASS
3666 18:10:41.738001 TX DQ/DQS : PASS
3667 18:10:41.740785 RX DATLAT : PASS
3668 18:10:41.744406 RX DQ/DQS(Engine): PASS
3669 18:10:41.744507 TX OE : NO K
3670 18:10:41.744607 All Pass.
3671 18:10:41.748014
3672 18:10:41.748117 CH 1, Rank 0
3673 18:10:41.750857 SW Impedance : PASS
3674 18:10:41.750951 DUTY Scan : NO K
3675 18:10:41.754233 ZQ Calibration : PASS
3676 18:10:41.754332 Jitter Meter : NO K
3677 18:10:41.757661 CBT Training : PASS
3678 18:10:41.761285 Write leveling : PASS
3679 18:10:41.761357 RX DQS gating : PASS
3680 18:10:41.764016 RX DQ/DQS(RDDQC) : PASS
3681 18:10:41.767490 TX DQ/DQS : PASS
3682 18:10:41.767587 RX DATLAT : PASS
3683 18:10:41.770917 RX DQ/DQS(Engine): PASS
3684 18:10:41.774401 TX OE : NO K
3685 18:10:41.774507 All Pass.
3686 18:10:41.774598
3687 18:10:41.774684 CH 1, Rank 1
3688 18:10:41.777789 SW Impedance : PASS
3689 18:10:41.781206 DUTY Scan : NO K
3690 18:10:41.781309 ZQ Calibration : PASS
3691 18:10:41.784292 Jitter Meter : NO K
3692 18:10:41.787442 CBT Training : PASS
3693 18:10:41.787542 Write leveling : PASS
3694 18:10:41.790518 RX DQS gating : PASS
3695 18:10:41.794322 RX DQ/DQS(RDDQC) : PASS
3696 18:10:41.794428 TX DQ/DQS : PASS
3697 18:10:41.797635 RX DATLAT : PASS
3698 18:10:41.800911 RX DQ/DQS(Engine): PASS
3699 18:10:41.801011 TX OE : NO K
3700 18:10:41.801113 All Pass.
3701 18:10:41.804356
3702 18:10:41.804443 DramC Write-DBI off
3703 18:10:41.807102 PER_BANK_REFRESH: Hybrid Mode
3704 18:10:41.807199 TX_TRACKING: ON
3705 18:10:41.817708 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3706 18:10:41.821006 [FAST_K] Save calibration result to emmc
3707 18:10:41.823840 dramc_set_vcore_voltage set vcore to 650000
3708 18:10:41.827398 Read voltage for 600, 5
3709 18:10:41.827501 Vio18 = 0
3710 18:10:41.830555 Vcore = 650000
3711 18:10:41.830651 Vdram = 0
3712 18:10:41.830740 Vddq = 0
3713 18:10:41.830826 Vmddr = 0
3714 18:10:41.837632 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3715 18:10:41.844019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3716 18:10:41.844133 MEM_TYPE=3, freq_sel=19
3717 18:10:41.847705 sv_algorithm_assistance_LP4_1600
3718 18:10:41.850550 ============ PULL DRAM RESETB DOWN ============
3719 18:10:41.857750 ========== PULL DRAM RESETB DOWN end =========
3720 18:10:41.860579 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3721 18:10:41.864124 ===================================
3722 18:10:41.867630 LPDDR4 DRAM CONFIGURATION
3723 18:10:41.870609 ===================================
3724 18:10:41.870706 EX_ROW_EN[0] = 0x0
3725 18:10:41.873997 EX_ROW_EN[1] = 0x0
3726 18:10:41.874102 LP4Y_EN = 0x0
3727 18:10:41.877582 WORK_FSP = 0x0
3728 18:10:41.877680 WL = 0x2
3729 18:10:41.880568 RL = 0x2
3730 18:10:41.880666 BL = 0x2
3731 18:10:41.884077 RPST = 0x0
3732 18:10:41.884178 RD_PRE = 0x0
3733 18:10:41.887097 WR_PRE = 0x1
3734 18:10:41.890225 WR_PST = 0x0
3735 18:10:41.890323 DBI_WR = 0x0
3736 18:10:41.894002 DBI_RD = 0x0
3737 18:10:41.894073 OTF = 0x1
3738 18:10:41.897156 ===================================
3739 18:10:41.900516 ===================================
3740 18:10:41.900594 ANA top config
3741 18:10:41.903855 ===================================
3742 18:10:41.907141 DLL_ASYNC_EN = 0
3743 18:10:41.910298 ALL_SLAVE_EN = 1
3744 18:10:41.914257 NEW_RANK_MODE = 1
3745 18:10:41.917301 DLL_IDLE_MODE = 1
3746 18:10:41.917399 LP45_APHY_COMB_EN = 1
3747 18:10:41.920536 TX_ODT_DIS = 1
3748 18:10:41.923566 NEW_8X_MODE = 1
3749 18:10:41.927336 ===================================
3750 18:10:41.930571 ===================================
3751 18:10:41.933480 data_rate = 1200
3752 18:10:41.937064 CKR = 1
3753 18:10:41.937166 DQ_P2S_RATIO = 8
3754 18:10:41.940672 ===================================
3755 18:10:41.943523 CA_P2S_RATIO = 8
3756 18:10:41.947317 DQ_CA_OPEN = 0
3757 18:10:41.950193 DQ_SEMI_OPEN = 0
3758 18:10:41.953773 CA_SEMI_OPEN = 0
3759 18:10:41.957365 CA_FULL_RATE = 0
3760 18:10:41.957467 DQ_CKDIV4_EN = 1
3761 18:10:41.960218 CA_CKDIV4_EN = 1
3762 18:10:41.963679 CA_PREDIV_EN = 0
3763 18:10:41.967255 PH8_DLY = 0
3764 18:10:41.970125 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3765 18:10:41.973812 DQ_AAMCK_DIV = 4
3766 18:10:41.973911 CA_AAMCK_DIV = 4
3767 18:10:41.977063 CA_ADMCK_DIV = 4
3768 18:10:41.980494 DQ_TRACK_CA_EN = 0
3769 18:10:41.983376 CA_PICK = 600
3770 18:10:41.986935 CA_MCKIO = 600
3771 18:10:41.990489 MCKIO_SEMI = 0
3772 18:10:41.993604 PLL_FREQ = 2288
3773 18:10:41.993702 DQ_UI_PI_RATIO = 32
3774 18:10:41.997169 CA_UI_PI_RATIO = 0
3775 18:10:42.000166 ===================================
3776 18:10:42.003615 ===================================
3777 18:10:42.006519 memory_type:LPDDR4
3778 18:10:42.010215 GP_NUM : 10
3779 18:10:42.010322 SRAM_EN : 1
3780 18:10:42.013714 MD32_EN : 0
3781 18:10:42.016457 ===================================
3782 18:10:42.016530 [ANA_INIT] >>>>>>>>>>>>>>
3783 18:10:42.020000 <<<<<< [CONFIGURE PHASE]: ANA_TX
3784 18:10:42.023482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3785 18:10:42.026924 ===================================
3786 18:10:42.029865 data_rate = 1200,PCW = 0X5800
3787 18:10:42.033276 ===================================
3788 18:10:42.036656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3789 18:10:42.043205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 18:10:42.050253 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 18:10:42.053047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3792 18:10:42.056703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3793 18:10:42.060141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3794 18:10:42.063133 [ANA_INIT] flow start
3795 18:10:42.063237 [ANA_INIT] PLL >>>>>>>>
3796 18:10:42.066692 [ANA_INIT] PLL <<<<<<<<
3797 18:10:42.069964 [ANA_INIT] MIDPI >>>>>>>>
3798 18:10:42.070061 [ANA_INIT] MIDPI <<<<<<<<
3799 18:10:42.073445 [ANA_INIT] DLL >>>>>>>>
3800 18:10:42.076406 [ANA_INIT] flow end
3801 18:10:42.079961 ============ LP4 DIFF to SE enter ============
3802 18:10:42.083683 ============ LP4 DIFF to SE exit ============
3803 18:10:42.086309 [ANA_INIT] <<<<<<<<<<<<<
3804 18:10:42.090045 [Flow] Enable top DCM control >>>>>
3805 18:10:42.092933 [Flow] Enable top DCM control <<<<<
3806 18:10:42.096575 Enable DLL master slave shuffle
3807 18:10:42.100193 ==============================================================
3808 18:10:42.103042 Gating Mode config
3809 18:10:42.110351 ==============================================================
3810 18:10:42.110456 Config description:
3811 18:10:42.120236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3812 18:10:42.126728 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3813 18:10:42.129618 SELPH_MODE 0: By rank 1: By Phase
3814 18:10:42.136405 ==============================================================
3815 18:10:42.139929 GAT_TRACK_EN = 1
3816 18:10:42.143398 RX_GATING_MODE = 2
3817 18:10:42.146306 RX_GATING_TRACK_MODE = 2
3818 18:10:42.149935 SELPH_MODE = 1
3819 18:10:42.152674 PICG_EARLY_EN = 1
3820 18:10:42.156136 VALID_LAT_VALUE = 1
3821 18:10:42.160061 ==============================================================
3822 18:10:42.163046 Enter into Gating configuration >>>>
3823 18:10:42.166266 Exit from Gating configuration <<<<
3824 18:10:42.169986 Enter into DVFS_PRE_config >>>>>
3825 18:10:42.182635 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3826 18:10:42.182752 Exit from DVFS_PRE_config <<<<<
3827 18:10:42.185945 Enter into PICG configuration >>>>
3828 18:10:42.189305 Exit from PICG configuration <<<<
3829 18:10:42.192817 [RX_INPUT] configuration >>>>>
3830 18:10:42.196412 [RX_INPUT] configuration <<<<<
3831 18:10:42.202966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3832 18:10:42.205701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3833 18:10:42.212329 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 18:10:42.219114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 18:10:42.225833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 18:10:42.232747 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 18:10:42.235455 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3838 18:10:42.239084 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3839 18:10:42.242437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3840 18:10:42.248797 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3841 18:10:42.252353 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3842 18:10:42.256180 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3843 18:10:42.258953 ===================================
3844 18:10:42.262596 LPDDR4 DRAM CONFIGURATION
3845 18:10:42.265670 ===================================
3846 18:10:42.269289 EX_ROW_EN[0] = 0x0
3847 18:10:42.269392 EX_ROW_EN[1] = 0x0
3848 18:10:42.272210 LP4Y_EN = 0x0
3849 18:10:42.272294 WORK_FSP = 0x0
3850 18:10:42.275635 WL = 0x2
3851 18:10:42.275731 RL = 0x2
3852 18:10:42.278972 BL = 0x2
3853 18:10:42.279155 RPST = 0x0
3854 18:10:42.282586 RD_PRE = 0x0
3855 18:10:42.282667 WR_PRE = 0x1
3856 18:10:42.285331 WR_PST = 0x0
3857 18:10:42.285413 DBI_WR = 0x0
3858 18:10:42.288650 DBI_RD = 0x0
3859 18:10:42.288778 OTF = 0x1
3860 18:10:42.292336 ===================================
3861 18:10:42.298853 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3862 18:10:42.301960 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3863 18:10:42.305072 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 18:10:42.308794 ===================================
3865 18:10:42.311786 LPDDR4 DRAM CONFIGURATION
3866 18:10:42.315444 ===================================
3867 18:10:42.315528 EX_ROW_EN[0] = 0x10
3868 18:10:42.319251 EX_ROW_EN[1] = 0x0
3869 18:10:42.322051 LP4Y_EN = 0x0
3870 18:10:42.322163 WORK_FSP = 0x0
3871 18:10:42.325555 WL = 0x2
3872 18:10:42.325669 RL = 0x2
3873 18:10:42.328483 BL = 0x2
3874 18:10:42.328566 RPST = 0x0
3875 18:10:42.332101 RD_PRE = 0x0
3876 18:10:42.332184 WR_PRE = 0x1
3877 18:10:42.335516 WR_PST = 0x0
3878 18:10:42.335599 DBI_WR = 0x0
3879 18:10:42.339135 DBI_RD = 0x0
3880 18:10:42.339218 OTF = 0x1
3881 18:10:42.341903 ===================================
3882 18:10:42.348372 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3883 18:10:42.352723 nWR fixed to 30
3884 18:10:42.356280 [ModeRegInit_LP4] CH0 RK0
3885 18:10:42.356396 [ModeRegInit_LP4] CH0 RK1
3886 18:10:42.359158 [ModeRegInit_LP4] CH1 RK0
3887 18:10:42.362887 [ModeRegInit_LP4] CH1 RK1
3888 18:10:42.362987 match AC timing 17
3889 18:10:42.369650 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3890 18:10:42.372353 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3891 18:10:42.376175 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3892 18:10:42.382338 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3893 18:10:42.385851 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3894 18:10:42.385935 ==
3895 18:10:42.389454 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 18:10:42.392336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3897 18:10:42.392427 ==
3898 18:10:42.399411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3899 18:10:42.405728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3900 18:10:42.409311 [CA 0] Center 36 (5~67) winsize 63
3901 18:10:42.412191 [CA 1] Center 36 (5~67) winsize 63
3902 18:10:42.415601 [CA 2] Center 34 (3~65) winsize 63
3903 18:10:42.418980 [CA 3] Center 33 (3~64) winsize 62
3904 18:10:42.422158 [CA 4] Center 33 (2~64) winsize 63
3905 18:10:42.425419 [CA 5] Center 32 (2~63) winsize 62
3906 18:10:42.425504
3907 18:10:42.428916 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3908 18:10:42.428997
3909 18:10:42.431891 [CATrainingPosCal] consider 1 rank data
3910 18:10:42.435688 u2DelayCellTimex100 = 270/100 ps
3911 18:10:42.439215 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3912 18:10:42.442090 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3913 18:10:42.445564 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3914 18:10:42.449096 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3915 18:10:42.455408 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3916 18:10:42.459054 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3917 18:10:42.459156
3918 18:10:42.462467 CA PerBit enable=1, Macro0, CA PI delay=32
3919 18:10:42.462564
3920 18:10:42.465362 [CBTSetCACLKResult] CA Dly = 32
3921 18:10:42.465432 CS Dly: 4 (0~35)
3922 18:10:42.465494 ==
3923 18:10:42.468993 Dram Type= 6, Freq= 0, CH_0, rank 1
3924 18:10:42.475430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 18:10:42.475535 ==
3926 18:10:42.478308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 18:10:42.484861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3928 18:10:42.488291 [CA 0] Center 35 (5~66) winsize 62
3929 18:10:42.491906 [CA 1] Center 35 (5~66) winsize 62
3930 18:10:42.494783 [CA 2] Center 34 (3~65) winsize 63
3931 18:10:42.498238 [CA 3] Center 34 (3~65) winsize 63
3932 18:10:42.501726 [CA 4] Center 33 (2~64) winsize 63
3933 18:10:42.505089 [CA 5] Center 32 (2~63) winsize 62
3934 18:10:42.505187
3935 18:10:42.508547 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3936 18:10:42.508623
3937 18:10:42.512095 [CATrainingPosCal] consider 2 rank data
3938 18:10:42.515084 u2DelayCellTimex100 = 270/100 ps
3939 18:10:42.518554 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3940 18:10:42.521456 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3941 18:10:42.528139 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3942 18:10:42.531734 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3943 18:10:42.535129 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3944 18:10:42.538482 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3945 18:10:42.538581
3946 18:10:42.541957 CA PerBit enable=1, Macro0, CA PI delay=32
3947 18:10:42.542054
3948 18:10:42.544878 [CBTSetCACLKResult] CA Dly = 32
3949 18:10:42.544980 CS Dly: 4 (0~35)
3950 18:10:42.545073
3951 18:10:42.548020 ----->DramcWriteLeveling(PI) begin...
3952 18:10:42.551652 ==
3953 18:10:42.554721 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 18:10:42.558245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 18:10:42.558344 ==
3956 18:10:42.561146 Write leveling (Byte 0): 33 => 33
3957 18:10:42.564643 Write leveling (Byte 1): 31 => 31
3958 18:10:42.568483 DramcWriteLeveling(PI) end<-----
3959 18:10:42.568584
3960 18:10:42.568677 ==
3961 18:10:42.571383 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 18:10:42.574710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 18:10:42.574813 ==
3964 18:10:42.578043 [Gating] SW mode calibration
3965 18:10:42.584518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3966 18:10:42.588204 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3967 18:10:42.594622 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 18:10:42.598186 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 18:10:42.601772 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 18:10:42.608207 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3971 18:10:42.611743 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
3972 18:10:42.614530 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 18:10:42.621757 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 18:10:42.624583 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 18:10:42.628247 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 18:10:42.634993 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 18:10:42.637998 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 18:10:42.641408 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
3979 18:10:42.647667 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3980 18:10:42.651318 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 18:10:42.654211 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 18:10:42.660795 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 18:10:42.664254 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 18:10:42.667590 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 18:10:42.674244 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 18:10:42.677548 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3987 18:10:42.681111 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3988 18:10:42.687656 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 18:10:42.690962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 18:10:42.694296 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 18:10:42.701312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 18:10:42.704706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 18:10:42.707538 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 18:10:42.714704 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 18:10:42.717616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 18:10:42.721131 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 18:10:42.724591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 18:10:42.731304 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 18:10:42.734473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 18:10:42.738052 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 18:10:42.744541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 18:10:42.747431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4003 18:10:42.751039 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4004 18:10:42.754508 Total UI for P1: 0, mck2ui 16
4005 18:10:42.757521 best dqsien dly found for B0: ( 0, 13, 12)
4006 18:10:42.764670 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 18:10:42.764756 Total UI for P1: 0, mck2ui 16
4008 18:10:42.770900 best dqsien dly found for B1: ( 0, 13, 16)
4009 18:10:42.774371 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4010 18:10:42.778194 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4011 18:10:42.778282
4012 18:10:42.781444 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4013 18:10:42.784153 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4014 18:10:42.787732 [Gating] SW calibration Done
4015 18:10:42.787815 ==
4016 18:10:42.791195 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 18:10:42.794737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 18:10:42.794822 ==
4019 18:10:42.797616 RX Vref Scan: 0
4020 18:10:42.797698
4021 18:10:42.797763 RX Vref 0 -> 0, step: 1
4022 18:10:42.797850
4023 18:10:42.801201 RX Delay -230 -> 252, step: 16
4024 18:10:42.808202 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4025 18:10:42.811291 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4026 18:10:42.814538 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4027 18:10:42.817558 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4028 18:10:42.820701 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4029 18:10:42.828027 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4030 18:10:42.831393 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4031 18:10:42.834269 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4032 18:10:42.837992 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4033 18:10:42.841006 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4034 18:10:42.847361 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4035 18:10:42.851114 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4036 18:10:42.854564 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4037 18:10:42.857264 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4038 18:10:42.864377 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4039 18:10:42.867357 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4040 18:10:42.867441 ==
4041 18:10:42.870929 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 18:10:42.873813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 18:10:42.873895 ==
4044 18:10:42.877315 DQS Delay:
4045 18:10:42.877397 DQS0 = 0, DQS1 = 0
4046 18:10:42.880894 DQM Delay:
4047 18:10:42.880977 DQM0 = 51, DQM1 = 45
4048 18:10:42.881042 DQ Delay:
4049 18:10:42.883672 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4050 18:10:42.887370 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =65
4051 18:10:42.890839 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4052 18:10:42.894202 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4053 18:10:42.894313
4054 18:10:42.894406
4055 18:10:42.894491 ==
4056 18:10:42.897838 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 18:10:42.904248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 18:10:42.904385 ==
4059 18:10:42.904482
4060 18:10:42.904550
4061 18:10:42.904611 TX Vref Scan disable
4062 18:10:42.907859 == TX Byte 0 ==
4063 18:10:42.911559 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4064 18:10:42.918295 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4065 18:10:42.918438 == TX Byte 1 ==
4066 18:10:42.921539 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4067 18:10:42.928207 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4068 18:10:42.928336 ==
4069 18:10:42.931482 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 18:10:42.934142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 18:10:42.934296 ==
4072 18:10:42.934399
4073 18:10:42.934495
4074 18:10:42.937964 TX Vref Scan disable
4075 18:10:42.941159 == TX Byte 0 ==
4076 18:10:42.944272 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 18:10:42.947810 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 18:10:42.947922 == TX Byte 1 ==
4079 18:10:42.954215 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4080 18:10:42.957934 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4081 18:10:42.958070
4082 18:10:42.958179 [DATLAT]
4083 18:10:42.961380 Freq=600, CH0 RK0
4084 18:10:42.961481
4085 18:10:42.961587 DATLAT Default: 0x9
4086 18:10:42.964064 0, 0xFFFF, sum = 0
4087 18:10:42.964178 1, 0xFFFF, sum = 0
4088 18:10:42.967588 2, 0xFFFF, sum = 0
4089 18:10:42.971247 3, 0xFFFF, sum = 0
4090 18:10:42.971358 4, 0xFFFF, sum = 0
4091 18:10:42.974039 5, 0xFFFF, sum = 0
4092 18:10:42.974140 6, 0xFFFF, sum = 0
4093 18:10:42.977470 7, 0xFFFF, sum = 0
4094 18:10:42.977553 8, 0x0, sum = 1
4095 18:10:42.980926 9, 0x0, sum = 2
4096 18:10:42.981008 10, 0x0, sum = 3
4097 18:10:42.981140 11, 0x0, sum = 4
4098 18:10:42.983927 best_step = 9
4099 18:10:42.984047
4100 18:10:42.984166 ==
4101 18:10:42.987479 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 18:10:42.991144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 18:10:42.991246 ==
4104 18:10:42.994005 RX Vref Scan: 1
4105 18:10:42.994121
4106 18:10:42.994217 RX Vref 0 -> 0, step: 1
4107 18:10:42.997290
4108 18:10:42.997398 RX Delay -163 -> 252, step: 8
4109 18:10:42.997492
4110 18:10:43.000620 Set Vref, RX VrefLevel [Byte0]: 53
4111 18:10:43.004232 [Byte1]: 48
4112 18:10:43.008490
4113 18:10:43.008577 Final RX Vref Byte 0 = 53 to rank0
4114 18:10:43.011380 Final RX Vref Byte 1 = 48 to rank0
4115 18:10:43.015129 Final RX Vref Byte 0 = 53 to rank1
4116 18:10:43.017925 Final RX Vref Byte 1 = 48 to rank1==
4117 18:10:43.021473 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 18:10:43.028556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 18:10:43.028647 ==
4120 18:10:43.028715 DQS Delay:
4121 18:10:43.028778 DQS0 = 0, DQS1 = 0
4122 18:10:43.031420 DQM Delay:
4123 18:10:43.031531 DQM0 = 53, DQM1 = 48
4124 18:10:43.034970 DQ Delay:
4125 18:10:43.037832 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4126 18:10:43.041486 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4127 18:10:43.044917 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4128 18:10:43.048423 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =56
4129 18:10:43.048505
4130 18:10:43.048571
4131 18:10:43.054533 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4132 18:10:43.058022 CH0 RK0: MR19=808, MR18=7164
4133 18:10:43.064637 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4134 18:10:43.064756
4135 18:10:43.067652 ----->DramcWriteLeveling(PI) begin...
4136 18:10:43.067734 ==
4137 18:10:43.071153 Dram Type= 6, Freq= 0, CH_0, rank 1
4138 18:10:43.074661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 18:10:43.074745 ==
4140 18:10:43.078318 Write leveling (Byte 0): 33 => 33
4141 18:10:43.081089 Write leveling (Byte 1): 31 => 31
4142 18:10:43.084539 DramcWriteLeveling(PI) end<-----
4143 18:10:43.084629
4144 18:10:43.084697 ==
4145 18:10:43.088149 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 18:10:43.091188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 18:10:43.091268 ==
4148 18:10:43.094724 [Gating] SW mode calibration
4149 18:10:43.101399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4150 18:10:43.108133 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4151 18:10:43.111639 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 18:10:43.114518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 18:10:43.121106 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 18:10:43.124710 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4155 18:10:43.128380 0 9 16 | B1->B0 | 2b2b 2626 | 0 0 | (1 1) (0 0)
4156 18:10:43.134800 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 18:10:43.138480 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 18:10:43.141242 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 18:10:43.148258 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 18:10:43.151193 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 18:10:43.154975 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 18:10:43.161282 0 10 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
4163 18:10:43.164699 0 10 16 | B1->B0 | 3e3e 3b3b | 0 0 | (0 0) (0 0)
4164 18:10:43.168259 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 18:10:43.174287 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 18:10:43.178013 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 18:10:43.180789 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 18:10:43.187516 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 18:10:43.191054 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 18:10:43.194746 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4171 18:10:43.201210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 18:10:43.204251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 18:10:43.207841 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 18:10:43.214095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 18:10:43.217680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 18:10:43.221273 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 18:10:43.227872 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 18:10:43.231421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 18:10:43.234131 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 18:10:43.240575 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 18:10:43.244202 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 18:10:43.247783 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 18:10:43.250802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 18:10:43.257763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 18:10:43.260727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4186 18:10:43.264543 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4187 18:10:43.270825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 18:10:43.274421 Total UI for P1: 0, mck2ui 16
4189 18:10:43.277359 best dqsien dly found for B0: ( 0, 13, 12)
4190 18:10:43.277433 Total UI for P1: 0, mck2ui 16
4191 18:10:43.284077 best dqsien dly found for B1: ( 0, 13, 14)
4192 18:10:43.287474 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4193 18:10:43.290999 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4194 18:10:43.291074
4195 18:10:43.294287 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4196 18:10:43.297445 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4197 18:10:43.300747 [Gating] SW calibration Done
4198 18:10:43.300825 ==
4199 18:10:43.304265 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 18:10:43.307214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 18:10:43.307303 ==
4202 18:10:43.310610 RX Vref Scan: 0
4203 18:10:43.310687
4204 18:10:43.310748 RX Vref 0 -> 0, step: 1
4205 18:10:43.314094
4206 18:10:43.314168 RX Delay -230 -> 252, step: 16
4207 18:10:43.321064 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4208 18:10:43.324098 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4209 18:10:43.327464 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4210 18:10:43.330570 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4211 18:10:43.337222 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4212 18:10:43.340766 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4213 18:10:43.344306 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4214 18:10:43.347142 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4215 18:10:43.350685 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4216 18:10:43.357412 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4217 18:10:43.360069 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4218 18:10:43.363721 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4219 18:10:43.367324 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4220 18:10:43.373812 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4221 18:10:43.377352 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4222 18:10:43.380283 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4223 18:10:43.380400 ==
4224 18:10:43.383976 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 18:10:43.386861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 18:10:43.386933 ==
4227 18:10:43.390419 DQS Delay:
4228 18:10:43.390507 DQS0 = 0, DQS1 = 0
4229 18:10:43.393990 DQM Delay:
4230 18:10:43.394059 DQM0 = 52, DQM1 = 43
4231 18:10:43.394119 DQ Delay:
4232 18:10:43.397003 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4233 18:10:43.400752 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4234 18:10:43.403643 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4235 18:10:43.407166 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4236 18:10:43.407240
4237 18:10:43.407304
4238 18:10:43.409991 ==
4239 18:10:43.413472 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 18:10:43.417022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 18:10:43.417094 ==
4242 18:10:43.417160
4243 18:10:43.417222
4244 18:10:43.420203 TX Vref Scan disable
4245 18:10:43.420272 == TX Byte 0 ==
4246 18:10:43.426725 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4247 18:10:43.430188 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4248 18:10:43.430266 == TX Byte 1 ==
4249 18:10:43.436464 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4250 18:10:43.439953 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4251 18:10:43.440032 ==
4252 18:10:43.443722 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 18:10:43.446802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 18:10:43.446875 ==
4255 18:10:43.446937
4256 18:10:43.446998
4257 18:10:43.449980 TX Vref Scan disable
4258 18:10:43.453083 == TX Byte 0 ==
4259 18:10:43.456466 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4260 18:10:43.460165 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4261 18:10:43.463493 == TX Byte 1 ==
4262 18:10:43.466553 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4263 18:10:43.470071 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4264 18:10:43.470152
4265 18:10:43.473614 [DATLAT]
4266 18:10:43.473685 Freq=600, CH0 RK1
4267 18:10:43.473749
4268 18:10:43.476483 DATLAT Default: 0x9
4269 18:10:43.476560 0, 0xFFFF, sum = 0
4270 18:10:43.480119 1, 0xFFFF, sum = 0
4271 18:10:43.480188 2, 0xFFFF, sum = 0
4272 18:10:43.483277 3, 0xFFFF, sum = 0
4273 18:10:43.483360 4, 0xFFFF, sum = 0
4274 18:10:43.486167 5, 0xFFFF, sum = 0
4275 18:10:43.486260 6, 0xFFFF, sum = 0
4276 18:10:43.489737 7, 0xFFFF, sum = 0
4277 18:10:43.489805 8, 0x0, sum = 1
4278 18:10:43.493375 9, 0x0, sum = 2
4279 18:10:43.493443 10, 0x0, sum = 3
4280 18:10:43.496312 11, 0x0, sum = 4
4281 18:10:43.496420 best_step = 9
4282 18:10:43.496480
4283 18:10:43.496541 ==
4284 18:10:43.499958 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 18:10:43.506551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 18:10:43.506622 ==
4287 18:10:43.506686 RX Vref Scan: 0
4288 18:10:43.506744
4289 18:10:43.510127 RX Vref 0 -> 0, step: 1
4290 18:10:43.510193
4291 18:10:43.513111 RX Delay -163 -> 252, step: 8
4292 18:10:43.516755 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4293 18:10:43.519874 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4294 18:10:43.526562 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4295 18:10:43.530049 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4296 18:10:43.532927 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4297 18:10:43.536645 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4298 18:10:43.540026 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4299 18:10:43.546149 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4300 18:10:43.549375 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4301 18:10:43.552871 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4302 18:10:43.556218 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4303 18:10:43.559548 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4304 18:10:43.565956 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4305 18:10:43.569320 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4306 18:10:43.572728 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4307 18:10:43.576154 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4308 18:10:43.576257 ==
4309 18:10:43.578954 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 18:10:43.585925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 18:10:43.586032 ==
4312 18:10:43.586127 DQS Delay:
4313 18:10:43.588933 DQS0 = 0, DQS1 = 0
4314 18:10:43.589013 DQM Delay:
4315 18:10:43.589079 DQM0 = 53, DQM1 = 47
4316 18:10:43.592226 DQ Delay:
4317 18:10:43.596118 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4318 18:10:43.599372 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4319 18:10:43.602196 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4320 18:10:43.605757 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4321 18:10:43.605826
4322 18:10:43.605886
4323 18:10:43.612250 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4324 18:10:43.615856 CH0 RK1: MR19=808, MR18=5E1F
4325 18:10:43.622256 CH0_RK1: MR19=0x808, MR18=0x5E1F, DQSOSC=392, MR23=63, INC=170, DEC=113
4326 18:10:43.626041 [RxdqsGatingPostProcess] freq 600
4327 18:10:43.632452 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4328 18:10:43.632526 Pre-setting of DQS Precalculation
4329 18:10:43.639002 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4330 18:10:43.639082 ==
4331 18:10:43.641816 Dram Type= 6, Freq= 0, CH_1, rank 0
4332 18:10:43.645376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 18:10:43.645482 ==
4334 18:10:43.651916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4335 18:10:43.658581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4336 18:10:43.661963 [CA 0] Center 36 (5~67) winsize 63
4337 18:10:43.665581 [CA 1] Center 36 (6~67) winsize 62
4338 18:10:43.669020 [CA 2] Center 35 (4~66) winsize 63
4339 18:10:43.671768 [CA 3] Center 34 (4~65) winsize 62
4340 18:10:43.675167 [CA 4] Center 34 (4~65) winsize 62
4341 18:10:43.678863 [CA 5] Center 34 (4~65) winsize 62
4342 18:10:43.678960
4343 18:10:43.682659 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4344 18:10:43.682754
4345 18:10:43.685482 [CATrainingPosCal] consider 1 rank data
4346 18:10:43.688436 u2DelayCellTimex100 = 270/100 ps
4347 18:10:43.691953 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4348 18:10:43.695432 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4349 18:10:43.698651 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4350 18:10:43.702352 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4351 18:10:43.705314 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4352 18:10:43.708733 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 18:10:43.708809
4354 18:10:43.715246 CA PerBit enable=1, Macro0, CA PI delay=34
4355 18:10:43.715320
4356 18:10:43.718612 [CBTSetCACLKResult] CA Dly = 34
4357 18:10:43.718696 CS Dly: 6 (0~37)
4358 18:10:43.718787 ==
4359 18:10:43.721392 Dram Type= 6, Freq= 0, CH_1, rank 1
4360 18:10:43.724931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 18:10:43.725017 ==
4362 18:10:43.731453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 18:10:43.737915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4364 18:10:43.741432 [CA 0] Center 36 (6~67) winsize 62
4365 18:10:43.744988 [CA 1] Center 36 (6~67) winsize 62
4366 18:10:43.747927 [CA 2] Center 35 (4~66) winsize 63
4367 18:10:43.751347 [CA 3] Center 35 (4~66) winsize 63
4368 18:10:43.754949 [CA 4] Center 35 (4~66) winsize 63
4369 18:10:43.757923 [CA 5] Center 34 (4~65) winsize 62
4370 18:10:43.757998
4371 18:10:43.761372 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4372 18:10:43.761452
4373 18:10:43.764657 [CATrainingPosCal] consider 2 rank data
4374 18:10:43.768219 u2DelayCellTimex100 = 270/100 ps
4375 18:10:43.771455 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4376 18:10:43.774625 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4377 18:10:43.778157 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4378 18:10:43.781494 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 18:10:43.784407 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 18:10:43.791566 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 18:10:43.791643
4382 18:10:43.794559 CA PerBit enable=1, Macro0, CA PI delay=34
4383 18:10:43.794635
4384 18:10:43.798261 [CBTSetCACLKResult] CA Dly = 34
4385 18:10:43.798336 CS Dly: 6 (0~38)
4386 18:10:43.798399
4387 18:10:43.801119 ----->DramcWriteLeveling(PI) begin...
4388 18:10:43.801194 ==
4389 18:10:43.804518 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 18:10:43.811004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 18:10:43.811079 ==
4392 18:10:43.814514 Write leveling (Byte 0): 28 => 28
4393 18:10:43.814585 Write leveling (Byte 1): 29 => 29
4394 18:10:43.818140 DramcWriteLeveling(PI) end<-----
4395 18:10:43.818211
4396 18:10:43.820803 ==
4397 18:10:43.820874 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 18:10:43.827468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 18:10:43.827567 ==
4400 18:10:43.831149 [Gating] SW mode calibration
4401 18:10:43.837396 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4402 18:10:43.841046 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4403 18:10:43.847451 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 18:10:43.850781 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4405 18:10:43.854673 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 18:10:43.861031 0 9 12 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
4407 18:10:43.863947 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 18:10:43.867393 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 18:10:43.874442 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 18:10:43.877394 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 18:10:43.880679 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 18:10:43.887521 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 18:10:43.890852 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4414 18:10:43.894388 0 10 12 | B1->B0 | 3434 3b3b | 0 0 | (1 1) (0 0)
4415 18:10:43.900729 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 18:10:43.903617 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 18:10:43.907190 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 18:10:43.913746 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 18:10:43.917125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 18:10:43.920799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 18:10:43.927259 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4422 18:10:43.930286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4423 18:10:43.933754 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 18:10:43.937299 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 18:10:43.943783 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 18:10:43.946858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 18:10:43.950644 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 18:10:43.956643 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 18:10:43.960430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 18:10:43.963399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 18:10:43.969973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 18:10:43.973481 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 18:10:43.977027 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 18:10:43.983443 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 18:10:43.987085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 18:10:43.989989 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 18:10:43.996521 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 18:10:43.999713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4439 18:10:44.003153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 18:10:44.007013 Total UI for P1: 0, mck2ui 16
4441 18:10:44.009764 best dqsien dly found for B0: ( 0, 13, 12)
4442 18:10:44.013264 Total UI for P1: 0, mck2ui 16
4443 18:10:44.016765 best dqsien dly found for B1: ( 0, 13, 14)
4444 18:10:44.019906 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4445 18:10:44.023360 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4446 18:10:44.023440
4447 18:10:44.029800 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4448 18:10:44.033237 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4449 18:10:44.036958 [Gating] SW calibration Done
4450 18:10:44.037063 ==
4451 18:10:44.039744 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 18:10:44.043338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 18:10:44.043412 ==
4454 18:10:44.043474 RX Vref Scan: 0
4455 18:10:44.043531
4456 18:10:44.046285 RX Vref 0 -> 0, step: 1
4457 18:10:44.046353
4458 18:10:44.050045 RX Delay -230 -> 252, step: 16
4459 18:10:44.053417 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4460 18:10:44.056278 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4461 18:10:44.062893 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4462 18:10:44.066628 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4463 18:10:44.069692 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4464 18:10:44.072874 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4465 18:10:44.079865 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4466 18:10:44.083362 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4467 18:10:44.086319 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4468 18:10:44.089672 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4469 18:10:44.096224 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4470 18:10:44.099990 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4471 18:10:44.102838 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4472 18:10:44.106551 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4473 18:10:44.112731 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4474 18:10:44.116174 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4475 18:10:44.116254 ==
4476 18:10:44.119418 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 18:10:44.122570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 18:10:44.122651 ==
4479 18:10:44.125699 DQS Delay:
4480 18:10:44.125778 DQS0 = 0, DQS1 = 0
4481 18:10:44.125842 DQM Delay:
4482 18:10:44.129032 DQM0 = 50, DQM1 = 45
4483 18:10:44.129112 DQ Delay:
4484 18:10:44.132411 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4485 18:10:44.136025 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4486 18:10:44.138780 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4487 18:10:44.142381 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4488 18:10:44.142461
4489 18:10:44.142525
4490 18:10:44.142584 ==
4491 18:10:44.146138 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 18:10:44.152655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 18:10:44.152769 ==
4494 18:10:44.152835
4495 18:10:44.152895
4496 18:10:44.152952 TX Vref Scan disable
4497 18:10:44.155528 == TX Byte 0 ==
4498 18:10:44.159150 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4499 18:10:44.162835 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4500 18:10:44.165650 == TX Byte 1 ==
4501 18:10:44.169554 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4502 18:10:44.175609 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4503 18:10:44.175689 ==
4504 18:10:44.178959 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 18:10:44.182225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 18:10:44.182305 ==
4507 18:10:44.182369
4508 18:10:44.182428
4509 18:10:44.185435 TX Vref Scan disable
4510 18:10:44.185515 == TX Byte 0 ==
4511 18:10:44.192296 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4512 18:10:44.196079 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4513 18:10:44.196159 == TX Byte 1 ==
4514 18:10:44.202074 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4515 18:10:44.205732 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4516 18:10:44.205813
4517 18:10:44.205877 [DATLAT]
4518 18:10:44.209356 Freq=600, CH1 RK0
4519 18:10:44.209436
4520 18:10:44.209499 DATLAT Default: 0x9
4521 18:10:44.212260 0, 0xFFFF, sum = 0
4522 18:10:44.212401 1, 0xFFFF, sum = 0
4523 18:10:44.215962 2, 0xFFFF, sum = 0
4524 18:10:44.216043 3, 0xFFFF, sum = 0
4525 18:10:44.219028 4, 0xFFFF, sum = 0
4526 18:10:44.222601 5, 0xFFFF, sum = 0
4527 18:10:44.222682 6, 0xFFFF, sum = 0
4528 18:10:44.225438 7, 0xFFFF, sum = 0
4529 18:10:44.225520 8, 0x0, sum = 1
4530 18:10:44.225587 9, 0x0, sum = 2
4531 18:10:44.228931 10, 0x0, sum = 3
4532 18:10:44.229011 11, 0x0, sum = 4
4533 18:10:44.232262 best_step = 9
4534 18:10:44.232400
4535 18:10:44.232517 ==
4536 18:10:44.235710 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 18:10:44.238851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 18:10:44.238932 ==
4539 18:10:44.242081 RX Vref Scan: 1
4540 18:10:44.242161
4541 18:10:44.242224 RX Vref 0 -> 0, step: 1
4542 18:10:44.242284
4543 18:10:44.245129 RX Delay -163 -> 252, step: 8
4544 18:10:44.245209
4545 18:10:44.248859 Set Vref, RX VrefLevel [Byte0]: 55
4546 18:10:44.251983 [Byte1]: 52
4547 18:10:44.256336
4548 18:10:44.256483 Final RX Vref Byte 0 = 55 to rank0
4549 18:10:44.259287 Final RX Vref Byte 1 = 52 to rank0
4550 18:10:44.262912 Final RX Vref Byte 0 = 55 to rank1
4551 18:10:44.265819 Final RX Vref Byte 1 = 52 to rank1==
4552 18:10:44.269393 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 18:10:44.276097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 18:10:44.276243 ==
4555 18:10:44.276457 DQS Delay:
4556 18:10:44.276569 DQS0 = 0, DQS1 = 0
4557 18:10:44.279662 DQM Delay:
4558 18:10:44.279741 DQM0 = 49, DQM1 = 46
4559 18:10:44.282591 DQ Delay:
4560 18:10:44.286224 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4561 18:10:44.289014 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4562 18:10:44.292533 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4563 18:10:44.296019 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4564 18:10:44.296183
4565 18:10:44.296291
4566 18:10:44.302513 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4567 18:10:44.305752 CH1 RK0: MR19=808, MR18=476C
4568 18:10:44.312943 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4569 18:10:44.313053
4570 18:10:44.316174 ----->DramcWriteLeveling(PI) begin...
4571 18:10:44.316318 ==
4572 18:10:44.319272 Dram Type= 6, Freq= 0, CH_1, rank 1
4573 18:10:44.322531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 18:10:44.322623 ==
4575 18:10:44.326123 Write leveling (Byte 0): 29 => 29
4576 18:10:44.329083 Write leveling (Byte 1): 29 => 29
4577 18:10:44.332710 DramcWriteLeveling(PI) end<-----
4578 18:10:44.332791
4579 18:10:44.332857 ==
4580 18:10:44.336262 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 18:10:44.339333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 18:10:44.339416 ==
4583 18:10:44.342140 [Gating] SW mode calibration
4584 18:10:44.349264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4585 18:10:44.355605 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4586 18:10:44.359163 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4587 18:10:44.366185 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 18:10:44.368889 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 18:10:44.372491 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 0)
4590 18:10:44.375934 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 18:10:44.382519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 18:10:44.385351 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 18:10:44.388997 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 18:10:44.395359 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 18:10:44.399185 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 18:10:44.402440 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4597 18:10:44.409082 0 10 12 | B1->B0 | 3636 3333 | 0 0 | (0 0) (0 0)
4598 18:10:44.412607 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4599 18:10:44.415574 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 18:10:44.421897 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 18:10:44.425437 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 18:10:44.429274 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 18:10:44.435276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 18:10:44.438716 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 18:10:44.442374 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4606 18:10:44.448792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 18:10:44.452269 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 18:10:44.455181 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 18:10:44.462219 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 18:10:44.465220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 18:10:44.469021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 18:10:44.475425 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 18:10:44.478339 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 18:10:44.481469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 18:10:44.488820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 18:10:44.491530 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 18:10:44.495585 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 18:10:44.501441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 18:10:44.504842 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 18:10:44.508298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 18:10:44.514795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 18:10:44.514872 Total UI for P1: 0, mck2ui 16
4623 18:10:44.521264 best dqsien dly found for B0: ( 0, 13, 10)
4624 18:10:44.521338 Total UI for P1: 0, mck2ui 16
4625 18:10:44.528102 best dqsien dly found for B1: ( 0, 13, 10)
4626 18:10:44.530969 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4627 18:10:44.534533 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4628 18:10:44.534611
4629 18:10:44.538297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4630 18:10:44.541072 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4631 18:10:44.544739 [Gating] SW calibration Done
4632 18:10:44.544810 ==
4633 18:10:44.548133 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 18:10:44.551485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 18:10:44.551560 ==
4636 18:10:44.554313 RX Vref Scan: 0
4637 18:10:44.554389
4638 18:10:44.554459 RX Vref 0 -> 0, step: 1
4639 18:10:44.554520
4640 18:10:44.557746 RX Delay -230 -> 252, step: 16
4641 18:10:44.560981 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4642 18:10:44.567835 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4643 18:10:44.571081 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4644 18:10:44.574573 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4645 18:10:44.577426 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4646 18:10:44.584874 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4647 18:10:44.587591 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4648 18:10:44.591017 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4649 18:10:44.594752 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4650 18:10:44.597452 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4651 18:10:44.604716 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4652 18:10:44.607558 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4653 18:10:44.611140 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4654 18:10:44.614693 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4655 18:10:44.621219 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4656 18:10:44.624098 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4657 18:10:44.624174 ==
4658 18:10:44.627635 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 18:10:44.631214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 18:10:44.631287 ==
4661 18:10:44.633982 DQS Delay:
4662 18:10:44.634057 DQS0 = 0, DQS1 = 0
4663 18:10:44.634120 DQM Delay:
4664 18:10:44.637483 DQM0 = 50, DQM1 = 47
4665 18:10:44.637561 DQ Delay:
4666 18:10:44.641095 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4667 18:10:44.644007 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4668 18:10:44.647627 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4669 18:10:44.650759 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4670 18:10:44.650830
4671 18:10:44.650892
4672 18:10:44.650957 ==
4673 18:10:44.654286 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 18:10:44.660707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 18:10:44.660785 ==
4676 18:10:44.660849
4677 18:10:44.660909
4678 18:10:44.660973 TX Vref Scan disable
4679 18:10:44.664368 == TX Byte 0 ==
4680 18:10:44.668276 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4681 18:10:44.674567 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4682 18:10:44.674643 == TX Byte 1 ==
4683 18:10:44.677807 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4684 18:10:44.684333 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4685 18:10:44.684439 ==
4686 18:10:44.687442 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 18:10:44.691139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 18:10:44.691219 ==
4689 18:10:44.691281
4690 18:10:44.691341
4691 18:10:44.694240 TX Vref Scan disable
4692 18:10:44.697391 == TX Byte 0 ==
4693 18:10:44.700865 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 18:10:44.704284 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 18:10:44.707819 == TX Byte 1 ==
4696 18:10:44.710766 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4697 18:10:44.714513 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4698 18:10:44.714595
4699 18:10:44.714660 [DATLAT]
4700 18:10:44.717996 Freq=600, CH1 RK1
4701 18:10:44.718078
4702 18:10:44.718143 DATLAT Default: 0x9
4703 18:10:44.720711 0, 0xFFFF, sum = 0
4704 18:10:44.724523 1, 0xFFFF, sum = 0
4705 18:10:44.724607 2, 0xFFFF, sum = 0
4706 18:10:44.727224 3, 0xFFFF, sum = 0
4707 18:10:44.727330 4, 0xFFFF, sum = 0
4708 18:10:44.731031 5, 0xFFFF, sum = 0
4709 18:10:44.731140 6, 0xFFFF, sum = 0
4710 18:10:44.733978 7, 0xFFFF, sum = 0
4711 18:10:44.734076 8, 0x0, sum = 1
4712 18:10:44.737483 9, 0x0, sum = 2
4713 18:10:44.737566 10, 0x0, sum = 3
4714 18:10:44.737632 11, 0x0, sum = 4
4715 18:10:44.740852 best_step = 9
4716 18:10:44.740932
4717 18:10:44.740997 ==
4718 18:10:44.744380 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 18:10:44.747477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 18:10:44.747562 ==
4721 18:10:44.751115 RX Vref Scan: 0
4722 18:10:44.751196
4723 18:10:44.751262 RX Vref 0 -> 0, step: 1
4724 18:10:44.753906
4725 18:10:44.753987 RX Delay -163 -> 252, step: 8
4726 18:10:44.761703 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4727 18:10:44.764544 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4728 18:10:44.768142 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4729 18:10:44.771684 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4730 18:10:44.777616 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4731 18:10:44.781432 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4732 18:10:44.784465 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4733 18:10:44.788071 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4734 18:10:44.791582 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4735 18:10:44.798020 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4736 18:10:44.801459 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4737 18:10:44.804723 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4738 18:10:44.807969 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4739 18:10:44.814482 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4740 18:10:44.817569 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4741 18:10:44.821192 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4742 18:10:44.821272 ==
4743 18:10:44.824082 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 18:10:44.827570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 18:10:44.827647 ==
4746 18:10:44.830658 DQS Delay:
4747 18:10:44.830730 DQS0 = 0, DQS1 = 0
4748 18:10:44.833969 DQM Delay:
4749 18:10:44.834040 DQM0 = 49, DQM1 = 46
4750 18:10:44.834106 DQ Delay:
4751 18:10:44.837295 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4752 18:10:44.840676 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4753 18:10:44.844092 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4754 18:10:44.847577 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4755 18:10:44.847650
4756 18:10:44.847713
4757 18:10:44.857596 [DQSOSCAuto] RK1, (LSB)MR18= 0x671d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4758 18:10:44.860645 CH1 RK1: MR19=808, MR18=671D
4759 18:10:44.864018 CH1_RK1: MR19=0x808, MR18=0x671D, DQSOSC=390, MR23=63, INC=172, DEC=114
4760 18:10:44.867383 [RxdqsGatingPostProcess] freq 600
4761 18:10:44.874048 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4762 18:10:44.877579 Pre-setting of DQS Precalculation
4763 18:10:44.880573 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4764 18:10:44.890819 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4765 18:10:44.897116 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4766 18:10:44.897196
4767 18:10:44.897275
4768 18:10:44.900723 [Calibration Summary] 1200 Mbps
4769 18:10:44.900801 CH 0, Rank 0
4770 18:10:44.903561 SW Impedance : PASS
4771 18:10:44.903631 DUTY Scan : NO K
4772 18:10:44.907327 ZQ Calibration : PASS
4773 18:10:44.910209 Jitter Meter : NO K
4774 18:10:44.910281 CBT Training : PASS
4775 18:10:44.913823 Write leveling : PASS
4776 18:10:44.916973 RX DQS gating : PASS
4777 18:10:44.917070 RX DQ/DQS(RDDQC) : PASS
4778 18:10:44.920529 TX DQ/DQS : PASS
4779 18:10:44.924046 RX DATLAT : PASS
4780 18:10:44.924121 RX DQ/DQS(Engine): PASS
4781 18:10:44.926960 TX OE : NO K
4782 18:10:44.927030 All Pass.
4783 18:10:44.927090
4784 18:10:44.930423 CH 0, Rank 1
4785 18:10:44.930492 SW Impedance : PASS
4786 18:10:44.933685 DUTY Scan : NO K
4787 18:10:44.937264 ZQ Calibration : PASS
4788 18:10:44.937381 Jitter Meter : NO K
4789 18:10:44.940671 CBT Training : PASS
4790 18:10:44.940754 Write leveling : PASS
4791 18:10:44.943959 RX DQS gating : PASS
4792 18:10:44.946924 RX DQ/DQS(RDDQC) : PASS
4793 18:10:44.947030 TX DQ/DQS : PASS
4794 18:10:44.950335 RX DATLAT : PASS
4795 18:10:44.953863 RX DQ/DQS(Engine): PASS
4796 18:10:44.953941 TX OE : NO K
4797 18:10:44.957272 All Pass.
4798 18:10:44.957349
4799 18:10:44.957412 CH 1, Rank 0
4800 18:10:44.960350 SW Impedance : PASS
4801 18:10:44.960439 DUTY Scan : NO K
4802 18:10:44.963451 ZQ Calibration : PASS
4803 18:10:44.967051 Jitter Meter : NO K
4804 18:10:44.967127 CBT Training : PASS
4805 18:10:44.970207 Write leveling : PASS
4806 18:10:44.973838 RX DQS gating : PASS
4807 18:10:44.973912 RX DQ/DQS(RDDQC) : PASS
4808 18:10:44.976907 TX DQ/DQS : PASS
4809 18:10:44.976991 RX DATLAT : PASS
4810 18:10:44.980584 RX DQ/DQS(Engine): PASS
4811 18:10:44.983528 TX OE : NO K
4812 18:10:44.983601 All Pass.
4813 18:10:44.983669
4814 18:10:44.983728 CH 1, Rank 1
4815 18:10:44.987202 SW Impedance : PASS
4816 18:10:44.990002 DUTY Scan : NO K
4817 18:10:44.990074 ZQ Calibration : PASS
4818 18:10:44.993776 Jitter Meter : NO K
4819 18:10:44.997332 CBT Training : PASS
4820 18:10:44.997406 Write leveling : PASS
4821 18:10:45.000093 RX DQS gating : PASS
4822 18:10:45.003863 RX DQ/DQS(RDDQC) : PASS
4823 18:10:45.003935 TX DQ/DQS : PASS
4824 18:10:45.007369 RX DATLAT : PASS
4825 18:10:45.010329 RX DQ/DQS(Engine): PASS
4826 18:10:45.010406 TX OE : NO K
4827 18:10:45.013786 All Pass.
4828 18:10:45.013856
4829 18:10:45.013916 DramC Write-DBI off
4830 18:10:45.016716 PER_BANK_REFRESH: Hybrid Mode
4831 18:10:45.016786 TX_TRACKING: ON
4832 18:10:45.027100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4833 18:10:45.029979 [FAST_K] Save calibration result to emmc
4834 18:10:45.033539 dramc_set_vcore_voltage set vcore to 662500
4835 18:10:45.037119 Read voltage for 933, 3
4836 18:10:45.037197 Vio18 = 0
4837 18:10:45.040006 Vcore = 662500
4838 18:10:45.040082 Vdram = 0
4839 18:10:45.040143 Vddq = 0
4840 18:10:45.040203 Vmddr = 0
4841 18:10:45.046643 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4842 18:10:45.053259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4843 18:10:45.053337 MEM_TYPE=3, freq_sel=17
4844 18:10:45.056754 sv_algorithm_assistance_LP4_1600
4845 18:10:45.060271 ============ PULL DRAM RESETB DOWN ============
4846 18:10:45.067065 ========== PULL DRAM RESETB DOWN end =========
4847 18:10:45.070099 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4848 18:10:45.073343 ===================================
4849 18:10:45.076506 LPDDR4 DRAM CONFIGURATION
4850 18:10:45.080460 ===================================
4851 18:10:45.080542 EX_ROW_EN[0] = 0x0
4852 18:10:45.083761 EX_ROW_EN[1] = 0x0
4853 18:10:45.083831 LP4Y_EN = 0x0
4854 18:10:45.086486 WORK_FSP = 0x0
4855 18:10:45.086562 WL = 0x3
4856 18:10:45.090086 RL = 0x3
4857 18:10:45.093389 BL = 0x2
4858 18:10:45.093460 RPST = 0x0
4859 18:10:45.096608 RD_PRE = 0x0
4860 18:10:45.096678 WR_PRE = 0x1
4861 18:10:45.099985 WR_PST = 0x0
4862 18:10:45.100064 DBI_WR = 0x0
4863 18:10:45.103600 DBI_RD = 0x0
4864 18:10:45.103673 OTF = 0x1
4865 18:10:45.106500 ===================================
4866 18:10:45.109960 ===================================
4867 18:10:45.112860 ANA top config
4868 18:10:45.116421 ===================================
4869 18:10:45.116504 DLL_ASYNC_EN = 0
4870 18:10:45.120196 ALL_SLAVE_EN = 1
4871 18:10:45.123050 NEW_RANK_MODE = 1
4872 18:10:45.126662 DLL_IDLE_MODE = 1
4873 18:10:45.126734 LP45_APHY_COMB_EN = 1
4874 18:10:45.129647 TX_ODT_DIS = 1
4875 18:10:45.133184 NEW_8X_MODE = 1
4876 18:10:45.136688 ===================================
4877 18:10:45.140247 ===================================
4878 18:10:45.143036 data_rate = 1866
4879 18:10:45.146657 CKR = 1
4880 18:10:45.149572 DQ_P2S_RATIO = 8
4881 18:10:45.153255 ===================================
4882 18:10:45.153364 CA_P2S_RATIO = 8
4883 18:10:45.156093 DQ_CA_OPEN = 0
4884 18:10:45.159816 DQ_SEMI_OPEN = 0
4885 18:10:45.163385 CA_SEMI_OPEN = 0
4886 18:10:45.166301 CA_FULL_RATE = 0
4887 18:10:45.166373 DQ_CKDIV4_EN = 1
4888 18:10:45.169883 CA_CKDIV4_EN = 1
4889 18:10:45.173407 CA_PREDIV_EN = 0
4890 18:10:45.176098 PH8_DLY = 0
4891 18:10:45.179499 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4892 18:10:45.182640 DQ_AAMCK_DIV = 4
4893 18:10:45.186425 CA_AAMCK_DIV = 4
4894 18:10:45.186499 CA_ADMCK_DIV = 4
4895 18:10:45.189724 DQ_TRACK_CA_EN = 0
4896 18:10:45.192965 CA_PICK = 933
4897 18:10:45.196031 CA_MCKIO = 933
4898 18:10:45.199432 MCKIO_SEMI = 0
4899 18:10:45.202754 PLL_FREQ = 3732
4900 18:10:45.202827 DQ_UI_PI_RATIO = 32
4901 18:10:45.206278 CA_UI_PI_RATIO = 0
4902 18:10:45.209606 ===================================
4903 18:10:45.213583 ===================================
4904 18:10:45.216616 memory_type:LPDDR4
4905 18:10:45.219733 GP_NUM : 10
4906 18:10:45.219810 SRAM_EN : 1
4907 18:10:45.223051 MD32_EN : 0
4908 18:10:45.226764 ===================================
4909 18:10:45.229633 [ANA_INIT] >>>>>>>>>>>>>>
4910 18:10:45.229707 <<<<<< [CONFIGURE PHASE]: ANA_TX
4911 18:10:45.232600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4912 18:10:45.236235 ===================================
4913 18:10:45.239631 data_rate = 1866,PCW = 0X8f00
4914 18:10:45.242585 ===================================
4915 18:10:45.246376 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4916 18:10:45.252792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 18:10:45.259264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4918 18:10:45.262969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4919 18:10:45.265993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4920 18:10:45.269621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4921 18:10:45.272541 [ANA_INIT] flow start
4922 18:10:45.272619 [ANA_INIT] PLL >>>>>>>>
4923 18:10:45.276224 [ANA_INIT] PLL <<<<<<<<
4924 18:10:45.278951 [ANA_INIT] MIDPI >>>>>>>>
4925 18:10:45.282589 [ANA_INIT] MIDPI <<<<<<<<
4926 18:10:45.282667 [ANA_INIT] DLL >>>>>>>>
4927 18:10:45.286260 [ANA_INIT] flow end
4928 18:10:45.289042 ============ LP4 DIFF to SE enter ============
4929 18:10:45.292597 ============ LP4 DIFF to SE exit ============
4930 18:10:45.295885 [ANA_INIT] <<<<<<<<<<<<<
4931 18:10:45.299165 [Flow] Enable top DCM control >>>>>
4932 18:10:45.302398 [Flow] Enable top DCM control <<<<<
4933 18:10:45.305829 Enable DLL master slave shuffle
4934 18:10:45.312336 ==============================================================
4935 18:10:45.312455 Gating Mode config
4936 18:10:45.319281 ==============================================================
4937 18:10:45.319360 Config description:
4938 18:10:45.328891 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4939 18:10:45.335503 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4940 18:10:45.342266 SELPH_MODE 0: By rank 1: By Phase
4941 18:10:45.345877 ==============================================================
4942 18:10:45.348758 GAT_TRACK_EN = 1
4943 18:10:45.352585 RX_GATING_MODE = 2
4944 18:10:45.355209 RX_GATING_TRACK_MODE = 2
4945 18:10:45.358868 SELPH_MODE = 1
4946 18:10:45.362459 PICG_EARLY_EN = 1
4947 18:10:45.365255 VALID_LAT_VALUE = 1
4948 18:10:45.368962 ==============================================================
4949 18:10:45.372056 Enter into Gating configuration >>>>
4950 18:10:45.375468 Exit from Gating configuration <<<<
4951 18:10:45.378340 Enter into DVFS_PRE_config >>>>>
4952 18:10:45.392299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4953 18:10:45.395239 Exit from DVFS_PRE_config <<<<<
4954 18:10:45.398859 Enter into PICG configuration >>>>
4955 18:10:45.401718 Exit from PICG configuration <<<<
4956 18:10:45.401801 [RX_INPUT] configuration >>>>>
4957 18:10:45.405242 [RX_INPUT] configuration <<<<<
4958 18:10:45.412070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4959 18:10:45.414884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4960 18:10:45.421670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4961 18:10:45.428651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4962 18:10:45.435101 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 18:10:45.441772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 18:10:45.444899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4965 18:10:45.448111 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4966 18:10:45.455030 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4967 18:10:45.458386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4968 18:10:45.461874 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4969 18:10:45.464784 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4970 18:10:45.468300 ===================================
4971 18:10:45.471251 LPDDR4 DRAM CONFIGURATION
4972 18:10:45.475036 ===================================
4973 18:10:45.478606 EX_ROW_EN[0] = 0x0
4974 18:10:45.478688 EX_ROW_EN[1] = 0x0
4975 18:10:45.481464 LP4Y_EN = 0x0
4976 18:10:45.481546 WORK_FSP = 0x0
4977 18:10:45.485286 WL = 0x3
4978 18:10:45.485368 RL = 0x3
4979 18:10:45.488151 BL = 0x2
4980 18:10:45.488232 RPST = 0x0
4981 18:10:45.491699 RD_PRE = 0x0
4982 18:10:45.491781 WR_PRE = 0x1
4983 18:10:45.494663 WR_PST = 0x0
4984 18:10:45.494742 DBI_WR = 0x0
4985 18:10:45.498414 DBI_RD = 0x0
4986 18:10:45.498494 OTF = 0x1
4987 18:10:45.501311 ===================================
4988 18:10:45.507893 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4989 18:10:45.511421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4990 18:10:45.514723 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 18:10:45.518379 ===================================
4992 18:10:45.521350 LPDDR4 DRAM CONFIGURATION
4993 18:10:45.524888 ===================================
4994 18:10:45.527893 EX_ROW_EN[0] = 0x10
4995 18:10:45.527972 EX_ROW_EN[1] = 0x0
4996 18:10:45.531450 LP4Y_EN = 0x0
4997 18:10:45.531530 WORK_FSP = 0x0
4998 18:10:45.534920 WL = 0x3
4999 18:10:45.535001 RL = 0x3
5000 18:10:45.538091 BL = 0x2
5001 18:10:45.538171 RPST = 0x0
5002 18:10:45.541257 RD_PRE = 0x0
5003 18:10:45.541337 WR_PRE = 0x1
5004 18:10:45.544617 WR_PST = 0x0
5005 18:10:45.544697 DBI_WR = 0x0
5006 18:10:45.548041 DBI_RD = 0x0
5007 18:10:45.548121 OTF = 0x1
5008 18:10:45.551344 ===================================
5009 18:10:45.557671 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5010 18:10:45.562784 nWR fixed to 30
5011 18:10:45.566000 [ModeRegInit_LP4] CH0 RK0
5012 18:10:45.566084 [ModeRegInit_LP4] CH0 RK1
5013 18:10:45.569087 [ModeRegInit_LP4] CH1 RK0
5014 18:10:45.572306 [ModeRegInit_LP4] CH1 RK1
5015 18:10:45.572439 match AC timing 9
5016 18:10:45.579620 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5017 18:10:45.582793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5018 18:10:45.586349 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5019 18:10:45.592764 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5020 18:10:45.595673 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5021 18:10:45.595757 ==
5022 18:10:45.599242 Dram Type= 6, Freq= 0, CH_0, rank 0
5023 18:10:45.602904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5024 18:10:45.602989 ==
5025 18:10:45.609437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5026 18:10:45.615874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5027 18:10:45.619329 [CA 0] Center 37 (6~68) winsize 63
5028 18:10:45.622733 [CA 1] Center 37 (6~68) winsize 63
5029 18:10:45.625546 [CA 2] Center 34 (4~65) winsize 62
5030 18:10:45.628877 [CA 3] Center 34 (3~65) winsize 63
5031 18:10:45.632595 [CA 4] Center 33 (3~64) winsize 62
5032 18:10:45.635566 [CA 5] Center 32 (2~62) winsize 61
5033 18:10:45.635652
5034 18:10:45.638556 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5035 18:10:45.638640
5036 18:10:45.642136 [CATrainingPosCal] consider 1 rank data
5037 18:10:45.645653 u2DelayCellTimex100 = 270/100 ps
5038 18:10:45.649015 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5039 18:10:45.651839 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5040 18:10:45.655478 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5041 18:10:45.658956 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5042 18:10:45.662522 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5043 18:10:45.668707 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5044 18:10:45.668791
5045 18:10:45.672283 CA PerBit enable=1, Macro0, CA PI delay=32
5046 18:10:45.672423
5047 18:10:45.675235 [CBTSetCACLKResult] CA Dly = 32
5048 18:10:45.675319 CS Dly: 5 (0~36)
5049 18:10:45.675406 ==
5050 18:10:45.678781 Dram Type= 6, Freq= 0, CH_0, rank 1
5051 18:10:45.681681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5052 18:10:45.685634 ==
5053 18:10:45.688308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5054 18:10:45.695377 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5055 18:10:45.698283 [CA 0] Center 37 (7~68) winsize 62
5056 18:10:45.701659 [CA 1] Center 37 (7~68) winsize 62
5057 18:10:45.705008 [CA 2] Center 34 (4~65) winsize 62
5058 18:10:45.708815 [CA 3] Center 34 (3~65) winsize 63
5059 18:10:45.711743 [CA 4] Center 32 (2~63) winsize 62
5060 18:10:45.715418 [CA 5] Center 32 (2~63) winsize 62
5061 18:10:45.715504
5062 18:10:45.718306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5063 18:10:45.718391
5064 18:10:45.721804 [CATrainingPosCal] consider 2 rank data
5065 18:10:45.725393 u2DelayCellTimex100 = 270/100 ps
5066 18:10:45.729025 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 18:10:45.731746 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5068 18:10:45.735276 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5069 18:10:45.738796 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5070 18:10:45.742380 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5071 18:10:45.748979 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5072 18:10:45.749065
5073 18:10:45.751809 CA PerBit enable=1, Macro0, CA PI delay=32
5074 18:10:45.751894
5075 18:10:45.755328 [CBTSetCACLKResult] CA Dly = 32
5076 18:10:45.755412 CS Dly: 5 (0~37)
5077 18:10:45.755498
5078 18:10:45.758561 ----->DramcWriteLeveling(PI) begin...
5079 18:10:45.758647 ==
5080 18:10:45.762219 Dram Type= 6, Freq= 0, CH_0, rank 0
5081 18:10:45.768534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5082 18:10:45.768620 ==
5083 18:10:45.771928 Write leveling (Byte 0): 32 => 32
5084 18:10:45.772013 Write leveling (Byte 1): 29 => 29
5085 18:10:45.775510 DramcWriteLeveling(PI) end<-----
5086 18:10:45.775593
5087 18:10:45.778328 ==
5088 18:10:45.778413 Dram Type= 6, Freq= 0, CH_0, rank 0
5089 18:10:45.785444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5090 18:10:45.785530 ==
5091 18:10:45.788289 [Gating] SW mode calibration
5092 18:10:45.795325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5093 18:10:45.798387 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5094 18:10:45.805289 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
5095 18:10:45.808716 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 18:10:45.811618 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 18:10:45.818153 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 18:10:45.821928 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 18:10:45.824745 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 18:10:45.831376 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5101 18:10:45.835054 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
5102 18:10:45.838428 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5103 18:10:45.844729 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 18:10:45.848369 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 18:10:45.851332 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 18:10:45.855046 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 18:10:45.861402 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 18:10:45.864650 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 18:10:45.868103 0 15 28 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5110 18:10:45.874512 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5111 18:10:45.877937 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 18:10:45.881442 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 18:10:45.887609 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 18:10:45.890976 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 18:10:45.894451 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 18:10:45.901389 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 18:10:45.904676 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 18:10:45.907612 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5119 18:10:45.914963 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 18:10:45.917684 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 18:10:45.921228 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 18:10:45.927788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 18:10:45.930938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 18:10:45.934412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 18:10:45.940866 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 18:10:45.944217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 18:10:45.947649 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 18:10:45.954218 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 18:10:45.957129 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 18:10:45.960620 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 18:10:45.967230 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 18:10:45.970602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 18:10:45.973916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5134 18:10:45.980872 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5135 18:10:45.983552 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 18:10:45.986984 Total UI for P1: 0, mck2ui 16
5137 18:10:45.990591 best dqsien dly found for B0: ( 1, 2, 28)
5138 18:10:45.993974 Total UI for P1: 0, mck2ui 16
5139 18:10:45.996859 best dqsien dly found for B1: ( 1, 2, 30)
5140 18:10:46.000542 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5141 18:10:46.003437 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5142 18:10:46.003517
5143 18:10:46.006820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5144 18:10:46.010261 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5145 18:10:46.013500 [Gating] SW calibration Done
5146 18:10:46.013581 ==
5147 18:10:46.017388 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 18:10:46.020105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 18:10:46.023703 ==
5150 18:10:46.023784 RX Vref Scan: 0
5151 18:10:46.023848
5152 18:10:46.026648 RX Vref 0 -> 0, step: 1
5153 18:10:46.026729
5154 18:10:46.030360 RX Delay -80 -> 252, step: 8
5155 18:10:46.033224 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5156 18:10:46.036997 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5157 18:10:46.039901 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5158 18:10:46.043701 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5159 18:10:46.050327 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5160 18:10:46.053015 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5161 18:10:46.056501 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5162 18:10:46.060216 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5163 18:10:46.063220 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5164 18:10:46.066783 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5165 18:10:46.073336 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5166 18:10:46.076736 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5167 18:10:46.079545 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5168 18:10:46.082921 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5169 18:10:46.086385 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5170 18:10:46.090031 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5171 18:10:46.092874 ==
5172 18:10:46.092955 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 18:10:46.099965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 18:10:46.100046 ==
5175 18:10:46.100111 DQS Delay:
5176 18:10:46.103374 DQS0 = 0, DQS1 = 0
5177 18:10:46.103454 DQM Delay:
5178 18:10:46.106580 DQM0 = 105, DQM1 = 94
5179 18:10:46.106662 DQ Delay:
5180 18:10:46.110149 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5181 18:10:46.113180 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5182 18:10:46.116791 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5183 18:10:46.119621 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5184 18:10:46.119701
5185 18:10:46.119765
5186 18:10:46.119824 ==
5187 18:10:46.123028 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 18:10:46.126296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 18:10:46.126377 ==
5190 18:10:46.126442
5191 18:10:46.129570
5192 18:10:46.129650 TX Vref Scan disable
5193 18:10:46.133142 == TX Byte 0 ==
5194 18:10:46.136137 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5195 18:10:46.139641 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5196 18:10:46.142724 == TX Byte 1 ==
5197 18:10:46.146367 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5198 18:10:46.149247 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5199 18:10:46.149328 ==
5200 18:10:46.152770 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 18:10:46.159524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 18:10:46.159607 ==
5203 18:10:46.159672
5204 18:10:46.159731
5205 18:10:46.159789 TX Vref Scan disable
5206 18:10:46.163433 == TX Byte 0 ==
5207 18:10:46.166965 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5208 18:10:46.173576 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5209 18:10:46.173657 == TX Byte 1 ==
5210 18:10:46.177215 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 18:10:46.183724 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 18:10:46.183805
5213 18:10:46.183869 [DATLAT]
5214 18:10:46.183929 Freq=933, CH0 RK0
5215 18:10:46.183988
5216 18:10:46.186628 DATLAT Default: 0xd
5217 18:10:46.186709 0, 0xFFFF, sum = 0
5218 18:10:46.189957 1, 0xFFFF, sum = 0
5219 18:10:46.193224 2, 0xFFFF, sum = 0
5220 18:10:46.193335 3, 0xFFFF, sum = 0
5221 18:10:46.196687 4, 0xFFFF, sum = 0
5222 18:10:46.196769 5, 0xFFFF, sum = 0
5223 18:10:46.200255 6, 0xFFFF, sum = 0
5224 18:10:46.200405 7, 0xFFFF, sum = 0
5225 18:10:46.203073 8, 0xFFFF, sum = 0
5226 18:10:46.203155 9, 0xFFFF, sum = 0
5227 18:10:46.206674 10, 0x0, sum = 1
5228 18:10:46.206756 11, 0x0, sum = 2
5229 18:10:46.210213 12, 0x0, sum = 3
5230 18:10:46.210295 13, 0x0, sum = 4
5231 18:10:46.210360 best_step = 11
5232 18:10:46.210420
5233 18:10:46.213451 ==
5234 18:10:46.216755 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 18:10:46.219629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 18:10:46.219713 ==
5237 18:10:46.219778 RX Vref Scan: 1
5238 18:10:46.219838
5239 18:10:46.223251 RX Vref 0 -> 0, step: 1
5240 18:10:46.223331
5241 18:10:46.226823 RX Delay -45 -> 252, step: 4
5242 18:10:46.226903
5243 18:10:46.229628 Set Vref, RX VrefLevel [Byte0]: 53
5244 18:10:46.232934 [Byte1]: 48
5245 18:10:46.233015
5246 18:10:46.236732 Final RX Vref Byte 0 = 53 to rank0
5247 18:10:46.239947 Final RX Vref Byte 1 = 48 to rank0
5248 18:10:46.243581 Final RX Vref Byte 0 = 53 to rank1
5249 18:10:46.246429 Final RX Vref Byte 1 = 48 to rank1==
5250 18:10:46.250053 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 18:10:46.253456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 18:10:46.253538 ==
5253 18:10:46.256473 DQS Delay:
5254 18:10:46.256554 DQS0 = 0, DQS1 = 0
5255 18:10:46.259838 DQM Delay:
5256 18:10:46.259919 DQM0 = 104, DQM1 = 94
5257 18:10:46.262875 DQ Delay:
5258 18:10:46.266493 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5259 18:10:46.269894 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5260 18:10:46.273275 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =88
5261 18:10:46.276244 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5262 18:10:46.276373
5263 18:10:46.276455
5264 18:10:46.282779 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5265 18:10:46.286528 CH0 RK0: MR19=505, MR18=332B
5266 18:10:46.292933 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5267 18:10:46.293015
5268 18:10:46.296463 ----->DramcWriteLeveling(PI) begin...
5269 18:10:46.296546 ==
5270 18:10:46.299436 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 18:10:46.302865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 18:10:46.302947 ==
5273 18:10:46.306203 Write leveling (Byte 0): 31 => 31
5274 18:10:46.309566 Write leveling (Byte 1): 28 => 28
5275 18:10:46.313103 DramcWriteLeveling(PI) end<-----
5276 18:10:46.313183
5277 18:10:46.313247 ==
5278 18:10:46.316011 Dram Type= 6, Freq= 0, CH_0, rank 1
5279 18:10:46.319480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 18:10:46.322954 ==
5281 18:10:46.323062 [Gating] SW mode calibration
5282 18:10:46.329440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5283 18:10:46.336298 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5284 18:10:46.339036 0 14 0 | B1->B0 | 3333 3333 | 0 1 | (0 0) (1 1)
5285 18:10:46.345944 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 18:10:46.349269 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 18:10:46.352671 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 18:10:46.359367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 18:10:46.362840 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 18:10:46.366234 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5291 18:10:46.373026 0 14 28 | B1->B0 | 2a2a 2e2e | 0 1 | (0 0) (1 0)
5292 18:10:46.375880 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 18:10:46.379544 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 18:10:46.386160 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 18:10:46.389633 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 18:10:46.392568 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 18:10:46.398991 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 18:10:46.402635 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5299 18:10:46.406202 0 15 28 | B1->B0 | 3535 3231 | 0 1 | (0 0) (0 0)
5300 18:10:46.409121 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 18:10:46.415545 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 18:10:46.419238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 18:10:46.422740 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 18:10:46.429109 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 18:10:46.432527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 18:10:46.435556 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 18:10:46.442167 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5308 18:10:46.445750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 18:10:46.448663 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 18:10:46.455848 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 18:10:46.458727 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 18:10:46.462512 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 18:10:46.469011 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 18:10:46.472191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 18:10:46.475688 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 18:10:46.481795 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 18:10:46.485390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 18:10:46.488918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 18:10:46.495343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 18:10:46.498756 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 18:10:46.502017 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 18:10:46.508887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 18:10:46.512284 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5324 18:10:46.515568 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 18:10:46.518543 Total UI for P1: 0, mck2ui 16
5326 18:10:46.522062 best dqsien dly found for B0: ( 1, 2, 28)
5327 18:10:46.525632 Total UI for P1: 0, mck2ui 16
5328 18:10:46.529064 best dqsien dly found for B1: ( 1, 2, 28)
5329 18:10:46.531966 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5330 18:10:46.535621 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5331 18:10:46.535701
5332 18:10:46.539067 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5333 18:10:46.545508 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5334 18:10:46.545589 [Gating] SW calibration Done
5335 18:10:46.545654 ==
5336 18:10:46.548606 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 18:10:46.555058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 18:10:46.555139 ==
5339 18:10:46.555203 RX Vref Scan: 0
5340 18:10:46.555264
5341 18:10:46.558717 RX Vref 0 -> 0, step: 1
5342 18:10:46.558812
5343 18:10:46.561665 RX Delay -80 -> 252, step: 8
5344 18:10:46.565371 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5345 18:10:46.568267 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5346 18:10:46.571896 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5347 18:10:46.578211 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5348 18:10:46.581592 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5349 18:10:46.584976 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5350 18:10:46.588190 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5351 18:10:46.591696 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5352 18:10:46.594994 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5353 18:10:46.601501 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5354 18:10:46.605059 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5355 18:10:46.607946 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5356 18:10:46.611421 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5357 18:10:46.614770 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5358 18:10:46.621140 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5359 18:10:46.624724 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5360 18:10:46.624804 ==
5361 18:10:46.628181 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 18:10:46.631113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 18:10:46.631195 ==
5364 18:10:46.631259 DQS Delay:
5365 18:10:46.634988 DQS0 = 0, DQS1 = 0
5366 18:10:46.635074 DQM Delay:
5367 18:10:46.638306 DQM0 = 105, DQM1 = 93
5368 18:10:46.638386 DQ Delay:
5369 18:10:46.641601 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5370 18:10:46.645015 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =111
5371 18:10:46.647951 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5372 18:10:46.651554 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5373 18:10:46.651634
5374 18:10:46.651697
5375 18:10:46.651756 ==
5376 18:10:46.655017 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 18:10:46.661606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 18:10:46.661689 ==
5379 18:10:46.661754
5380 18:10:46.661814
5381 18:10:46.661872 TX Vref Scan disable
5382 18:10:46.665309 == TX Byte 0 ==
5383 18:10:46.668260 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5384 18:10:46.671980 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5385 18:10:46.675400 == TX Byte 1 ==
5386 18:10:46.678262 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5387 18:10:46.685404 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5388 18:10:46.685484 ==
5389 18:10:46.688290 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 18:10:46.691881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 18:10:46.691977 ==
5392 18:10:46.692070
5393 18:10:46.692161
5394 18:10:46.694843 TX Vref Scan disable
5395 18:10:46.694923 == TX Byte 0 ==
5396 18:10:46.701965 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5397 18:10:46.705201 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5398 18:10:46.705277 == TX Byte 1 ==
5399 18:10:46.711562 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5400 18:10:46.715432 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5401 18:10:46.715513
5402 18:10:46.715577 [DATLAT]
5403 18:10:46.718231 Freq=933, CH0 RK1
5404 18:10:46.718312
5405 18:10:46.718375 DATLAT Default: 0xb
5406 18:10:46.721699 0, 0xFFFF, sum = 0
5407 18:10:46.721780 1, 0xFFFF, sum = 0
5408 18:10:46.724587 2, 0xFFFF, sum = 0
5409 18:10:46.728253 3, 0xFFFF, sum = 0
5410 18:10:46.728334 4, 0xFFFF, sum = 0
5411 18:10:46.731351 5, 0xFFFF, sum = 0
5412 18:10:46.731432 6, 0xFFFF, sum = 0
5413 18:10:46.734577 7, 0xFFFF, sum = 0
5414 18:10:46.734658 8, 0xFFFF, sum = 0
5415 18:10:46.737819 9, 0xFFFF, sum = 0
5416 18:10:46.737899 10, 0x0, sum = 1
5417 18:10:46.741584 11, 0x0, sum = 2
5418 18:10:46.741666 12, 0x0, sum = 3
5419 18:10:46.744786 13, 0x0, sum = 4
5420 18:10:46.744867 best_step = 11
5421 18:10:46.744932
5422 18:10:46.744992 ==
5423 18:10:46.747880 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 18:10:46.751357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 18:10:46.751438 ==
5426 18:10:46.754730 RX Vref Scan: 0
5427 18:10:46.754810
5428 18:10:46.757976 RX Vref 0 -> 0, step: 1
5429 18:10:46.758057
5430 18:10:46.758121 RX Delay -53 -> 252, step: 4
5431 18:10:46.765708 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5432 18:10:46.768927 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5433 18:10:46.772508 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5434 18:10:46.775324 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5435 18:10:46.778950 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5436 18:10:46.785406 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5437 18:10:46.788892 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5438 18:10:46.792488 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5439 18:10:46.795499 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5440 18:10:46.799238 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5441 18:10:46.802220 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5442 18:10:46.809068 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5443 18:10:46.811950 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5444 18:10:46.815355 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5445 18:10:46.818643 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5446 18:10:46.825883 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5447 18:10:46.825968 ==
5448 18:10:46.828708 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 18:10:46.832397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 18:10:46.832482 ==
5451 18:10:46.832568 DQS Delay:
5452 18:10:46.835409 DQS0 = 0, DQS1 = 0
5453 18:10:46.835493 DQM Delay:
5454 18:10:46.839075 DQM0 = 104, DQM1 = 94
5455 18:10:46.839159 DQ Delay:
5456 18:10:46.841920 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5457 18:10:46.845392 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5458 18:10:46.848908 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5459 18:10:46.851877 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5460 18:10:46.851961
5461 18:10:46.852046
5462 18:10:46.862109 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5463 18:10:46.862196 CH0 RK1: MR19=505, MR18=2A03
5464 18:10:46.868533 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5465 18:10:46.871752 [RxdqsGatingPostProcess] freq 933
5466 18:10:46.878749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5467 18:10:46.881672 best DQS0 dly(2T, 0.5T) = (0, 10)
5468 18:10:46.885152 best DQS1 dly(2T, 0.5T) = (0, 10)
5469 18:10:46.888574 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5470 18:10:46.891491 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5471 18:10:46.895348 best DQS0 dly(2T, 0.5T) = (0, 10)
5472 18:10:46.895429 best DQS1 dly(2T, 0.5T) = (0, 10)
5473 18:10:46.898319 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5474 18:10:46.902051 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5475 18:10:46.904984 Pre-setting of DQS Precalculation
5476 18:10:46.912293 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5477 18:10:46.912429 ==
5478 18:10:46.915298 Dram Type= 6, Freq= 0, CH_1, rank 0
5479 18:10:46.918262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 18:10:46.918347 ==
5481 18:10:46.925369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5482 18:10:46.931456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5483 18:10:46.935104 [CA 0] Center 36 (6~67) winsize 62
5484 18:10:46.937969 [CA 1] Center 36 (6~67) winsize 62
5485 18:10:46.941653 [CA 2] Center 35 (5~65) winsize 61
5486 18:10:46.944669 [CA 3] Center 34 (4~65) winsize 62
5487 18:10:46.948295 [CA 4] Center 34 (4~64) winsize 61
5488 18:10:46.951244 [CA 5] Center 33 (3~64) winsize 62
5489 18:10:46.951329
5490 18:10:46.954931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5491 18:10:46.955016
5492 18:10:46.958610 [CATrainingPosCal] consider 1 rank data
5493 18:10:46.961500 u2DelayCellTimex100 = 270/100 ps
5494 18:10:46.964642 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5495 18:10:46.968232 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5496 18:10:46.971820 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5497 18:10:46.974724 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 18:10:46.977759 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5499 18:10:46.981464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5500 18:10:46.981549
5501 18:10:46.987887 CA PerBit enable=1, Macro0, CA PI delay=33
5502 18:10:46.987972
5503 18:10:46.988074 [CBTSetCACLKResult] CA Dly = 33
5504 18:10:46.991360 CS Dly: 6 (0~37)
5505 18:10:46.991444 ==
5506 18:10:46.994828 Dram Type= 6, Freq= 0, CH_1, rank 1
5507 18:10:46.997999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 18:10:46.998084 ==
5509 18:10:47.004300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5510 18:10:47.011409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5511 18:10:47.014769 [CA 0] Center 36 (6~67) winsize 62
5512 18:10:47.018124 [CA 1] Center 37 (6~68) winsize 63
5513 18:10:47.021357 [CA 2] Center 35 (5~65) winsize 61
5514 18:10:47.024565 [CA 3] Center 34 (4~65) winsize 62
5515 18:10:47.028041 [CA 4] Center 34 (4~65) winsize 62
5516 18:10:47.031318 [CA 5] Center 33 (3~64) winsize 62
5517 18:10:47.031404
5518 18:10:47.034280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5519 18:10:47.034365
5520 18:10:47.037884 [CATrainingPosCal] consider 2 rank data
5521 18:10:47.041394 u2DelayCellTimex100 = 270/100 ps
5522 18:10:47.044207 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 18:10:47.047580 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5524 18:10:47.051106 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5525 18:10:47.054029 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5526 18:10:47.057663 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5527 18:10:47.064204 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5528 18:10:47.064289
5529 18:10:47.068077 CA PerBit enable=1, Macro0, CA PI delay=33
5530 18:10:47.068161
5531 18:10:47.070706 [CBTSetCACLKResult] CA Dly = 33
5532 18:10:47.070793 CS Dly: 7 (0~40)
5533 18:10:47.070878
5534 18:10:47.074233 ----->DramcWriteLeveling(PI) begin...
5535 18:10:47.074318 ==
5536 18:10:47.077904 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 18:10:47.080899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 18:10:47.084484 ==
5539 18:10:47.084568 Write leveling (Byte 0): 29 => 29
5540 18:10:47.087347 Write leveling (Byte 1): 30 => 30
5541 18:10:47.091070 DramcWriteLeveling(PI) end<-----
5542 18:10:47.091154
5543 18:10:47.091240 ==
5544 18:10:47.093977 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 18:10:47.101211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 18:10:47.101296 ==
5547 18:10:47.101382 [Gating] SW mode calibration
5548 18:10:47.110700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5549 18:10:47.114329 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5550 18:10:47.120471 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 18:10:47.123861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 18:10:47.127286 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 18:10:47.133758 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 18:10:47.137340 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 18:10:47.140959 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 18:10:47.144314 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
5557 18:10:47.150664 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5558 18:10:47.154097 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 18:10:47.157188 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 18:10:47.164002 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 18:10:47.167529 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 18:10:47.170507 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 18:10:47.176979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 18:10:47.180574 0 15 24 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5565 18:10:47.184220 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5566 18:10:47.190635 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 18:10:47.193589 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 18:10:47.197281 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 18:10:47.203764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 18:10:47.206737 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 18:10:47.210321 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 18:10:47.217180 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5573 18:10:47.220707 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5574 18:10:47.223592 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 18:10:47.230723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 18:10:47.233466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 18:10:47.236713 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 18:10:47.243283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 18:10:47.246601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 18:10:47.250300 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 18:10:47.256712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 18:10:47.260325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 18:10:47.263603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 18:10:47.269620 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 18:10:47.273354 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 18:10:47.276535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 18:10:47.282973 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5588 18:10:47.286887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5589 18:10:47.289929 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 18:10:47.293397 Total UI for P1: 0, mck2ui 16
5591 18:10:47.296286 best dqsien dly found for B0: ( 1, 2, 24)
5592 18:10:47.299886 Total UI for P1: 0, mck2ui 16
5593 18:10:47.303454 best dqsien dly found for B1: ( 1, 2, 22)
5594 18:10:47.306380 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5595 18:10:47.310019 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5596 18:10:47.310100
5597 18:10:47.312838 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5598 18:10:47.319633 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5599 18:10:47.319748 [Gating] SW calibration Done
5600 18:10:47.319817 ==
5601 18:10:47.323036 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 18:10:47.329541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 18:10:47.329623 ==
5604 18:10:47.329689 RX Vref Scan: 0
5605 18:10:47.329751
5606 18:10:47.333246 RX Vref 0 -> 0, step: 1
5607 18:10:47.333328
5608 18:10:47.336147 RX Delay -80 -> 252, step: 8
5609 18:10:47.339714 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5610 18:10:47.343202 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5611 18:10:47.346010 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5612 18:10:47.349697 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5613 18:10:47.356253 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5614 18:10:47.359333 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5615 18:10:47.362921 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5616 18:10:47.365867 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5617 18:10:47.369615 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5618 18:10:47.373254 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5619 18:10:47.379596 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5620 18:10:47.382943 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5621 18:10:47.385622 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5622 18:10:47.388972 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5623 18:10:47.392331 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5624 18:10:47.399173 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5625 18:10:47.399257 ==
5626 18:10:47.402594 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 18:10:47.406067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 18:10:47.406171 ==
5629 18:10:47.406238 DQS Delay:
5630 18:10:47.409568 DQS0 = 0, DQS1 = 0
5631 18:10:47.409678 DQM Delay:
5632 18:10:47.412347 DQM0 = 102, DQM1 = 98
5633 18:10:47.412444 DQ Delay:
5634 18:10:47.415959 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5635 18:10:47.418993 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5636 18:10:47.422490 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5637 18:10:47.426167 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5638 18:10:47.426313
5639 18:10:47.426440
5640 18:10:47.426528 ==
5641 18:10:47.428935 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 18:10:47.435945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 18:10:47.436030 ==
5644 18:10:47.436096
5645 18:10:47.436156
5646 18:10:47.436214 TX Vref Scan disable
5647 18:10:47.439398 == TX Byte 0 ==
5648 18:10:47.443043 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5649 18:10:47.445837 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5650 18:10:47.449108 == TX Byte 1 ==
5651 18:10:47.452379 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5652 18:10:47.459665 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5653 18:10:47.459749 ==
5654 18:10:47.462669 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 18:10:47.465487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 18:10:47.465568 ==
5657 18:10:47.465633
5658 18:10:47.465694
5659 18:10:47.469149 TX Vref Scan disable
5660 18:10:47.469229 == TX Byte 0 ==
5661 18:10:47.475815 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5662 18:10:47.479424 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5663 18:10:47.479535 == TX Byte 1 ==
5664 18:10:47.485887 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5665 18:10:47.488785 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5666 18:10:47.488861
5667 18:10:47.488932 [DATLAT]
5668 18:10:47.492262 Freq=933, CH1 RK0
5669 18:10:47.492404
5670 18:10:47.492469 DATLAT Default: 0xd
5671 18:10:47.495588 0, 0xFFFF, sum = 0
5672 18:10:47.495664 1, 0xFFFF, sum = 0
5673 18:10:47.498902 2, 0xFFFF, sum = 0
5674 18:10:47.498975 3, 0xFFFF, sum = 0
5675 18:10:47.502171 4, 0xFFFF, sum = 0
5676 18:10:47.505756 5, 0xFFFF, sum = 0
5677 18:10:47.505843 6, 0xFFFF, sum = 0
5678 18:10:47.508631 7, 0xFFFF, sum = 0
5679 18:10:47.508707 8, 0xFFFF, sum = 0
5680 18:10:47.512238 9, 0xFFFF, sum = 0
5681 18:10:47.512321 10, 0x0, sum = 1
5682 18:10:47.516202 11, 0x0, sum = 2
5683 18:10:47.516283 12, 0x0, sum = 3
5684 18:10:47.516377 13, 0x0, sum = 4
5685 18:10:47.518807 best_step = 11
5686 18:10:47.518912
5687 18:10:47.518987 ==
5688 18:10:47.522260 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 18:10:47.525409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 18:10:47.525491 ==
5691 18:10:47.528965 RX Vref Scan: 1
5692 18:10:47.529072
5693 18:10:47.529165 RX Vref 0 -> 0, step: 1
5694 18:10:47.531965
5695 18:10:47.532045 RX Delay -45 -> 252, step: 4
5696 18:10:47.532109
5697 18:10:47.535463 Set Vref, RX VrefLevel [Byte0]: 55
5698 18:10:47.538933 [Byte1]: 52
5699 18:10:47.542916
5700 18:10:47.542997 Final RX Vref Byte 0 = 55 to rank0
5701 18:10:47.546594 Final RX Vref Byte 1 = 52 to rank0
5702 18:10:47.549527 Final RX Vref Byte 0 = 55 to rank1
5703 18:10:47.553190 Final RX Vref Byte 1 = 52 to rank1==
5704 18:10:47.556591 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 18:10:47.563263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 18:10:47.563346 ==
5707 18:10:47.563412 DQS Delay:
5708 18:10:47.563512 DQS0 = 0, DQS1 = 0
5709 18:10:47.566684 DQM Delay:
5710 18:10:47.566765 DQM0 = 103, DQM1 = 99
5711 18:10:47.569590 DQ Delay:
5712 18:10:47.573128 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5713 18:10:47.576790 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5714 18:10:47.579678 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5715 18:10:47.583295 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5716 18:10:47.583376
5717 18:10:47.583441
5718 18:10:47.589796 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5719 18:10:47.592699 CH1 RK0: MR19=505, MR18=162D
5720 18:10:47.599998 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5721 18:10:47.600080
5722 18:10:47.602739 ----->DramcWriteLeveling(PI) begin...
5723 18:10:47.602822 ==
5724 18:10:47.606024 Dram Type= 6, Freq= 0, CH_1, rank 1
5725 18:10:47.609229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 18:10:47.609336 ==
5727 18:10:47.612842 Write leveling (Byte 0): 29 => 29
5728 18:10:47.616073 Write leveling (Byte 1): 29 => 29
5729 18:10:47.619518 DramcWriteLeveling(PI) end<-----
5730 18:10:47.619598
5731 18:10:47.619662 ==
5732 18:10:47.623085 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 18:10:47.629237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 18:10:47.629342 ==
5735 18:10:47.629469 [Gating] SW mode calibration
5736 18:10:47.639367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5737 18:10:47.643037 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5738 18:10:47.645808 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 18:10:47.652684 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 18:10:47.656225 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 18:10:47.659124 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 18:10:47.666404 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 18:10:47.669824 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5744 18:10:47.672459 0 14 24 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 1)
5745 18:10:47.679256 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5746 18:10:47.682618 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 18:10:47.686289 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 18:10:47.692735 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 18:10:47.695588 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 18:10:47.699376 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 18:10:47.705360 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 18:10:47.708853 0 15 24 | B1->B0 | 3434 2929 | 0 1 | (0 0) (0 0)
5753 18:10:47.712600 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 18:10:47.718856 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 18:10:47.722269 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 18:10:47.725526 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 18:10:47.731984 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 18:10:47.735475 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 18:10:47.738388 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 18:10:47.745455 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 18:10:47.748212 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5762 18:10:47.751674 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 18:10:47.758559 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 18:10:47.761424 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 18:10:47.764890 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 18:10:47.771327 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 18:10:47.775163 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 18:10:47.777955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 18:10:47.784705 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 18:10:47.788109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 18:10:47.791504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 18:10:47.798366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 18:10:47.801288 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 18:10:47.804898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 18:10:47.811456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 18:10:47.815083 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5777 18:10:47.818156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 18:10:47.821577 Total UI for P1: 0, mck2ui 16
5779 18:10:47.824385 best dqsien dly found for B0: ( 1, 2, 26)
5780 18:10:47.828138 Total UI for P1: 0, mck2ui 16
5781 18:10:47.830961 best dqsien dly found for B1: ( 1, 2, 24)
5782 18:10:47.834413 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5783 18:10:47.838013 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5784 18:10:47.838093
5785 18:10:47.844633 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5786 18:10:47.847862 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5787 18:10:47.847976 [Gating] SW calibration Done
5788 18:10:47.851228 ==
5789 18:10:47.851310 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 18:10:47.857617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 18:10:47.857699 ==
5792 18:10:47.857764 RX Vref Scan: 0
5793 18:10:47.857825
5794 18:10:47.860991 RX Vref 0 -> 0, step: 1
5795 18:10:47.861073
5796 18:10:47.864523 RX Delay -80 -> 252, step: 8
5797 18:10:47.867999 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5798 18:10:47.871281 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5799 18:10:47.874019 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5800 18:10:47.881364 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5801 18:10:47.884193 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5802 18:10:47.887812 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5803 18:10:47.890613 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5804 18:10:47.894303 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5805 18:10:47.900483 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5806 18:10:47.903708 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5807 18:10:47.907316 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5808 18:10:47.910921 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5809 18:10:47.913745 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5810 18:10:47.920278 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5811 18:10:47.924146 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5812 18:10:47.926977 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5813 18:10:47.927058 ==
5814 18:10:47.930540 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 18:10:47.934068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 18:10:47.934224 ==
5817 18:10:47.936946 DQS Delay:
5818 18:10:47.937052 DQS0 = 0, DQS1 = 0
5819 18:10:47.940609 DQM Delay:
5820 18:10:47.940691 DQM0 = 104, DQM1 = 98
5821 18:10:47.940755 DQ Delay:
5822 18:10:47.943574 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5823 18:10:47.947071 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5824 18:10:47.950785 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5825 18:10:47.956900 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5826 18:10:47.956982
5827 18:10:47.957047
5828 18:10:47.957107 ==
5829 18:10:47.960226 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 18:10:47.963530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 18:10:47.963637 ==
5832 18:10:47.963731
5833 18:10:47.963795
5834 18:10:47.966765 TX Vref Scan disable
5835 18:10:47.966846 == TX Byte 0 ==
5836 18:10:47.973576 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5837 18:10:47.976958 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5838 18:10:47.977039 == TX Byte 1 ==
5839 18:10:47.983328 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5840 18:10:47.986545 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5841 18:10:47.986627 ==
5842 18:10:47.989901 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 18:10:47.993651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 18:10:47.993732 ==
5845 18:10:47.993797
5846 18:10:47.996926
5847 18:10:47.997007 TX Vref Scan disable
5848 18:10:48.000174 == TX Byte 0 ==
5849 18:10:48.003245 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5850 18:10:48.006578 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5851 18:10:48.010200 == TX Byte 1 ==
5852 18:10:48.013452 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5853 18:10:48.016310 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5854 18:10:48.016405
5855 18:10:48.020039 [DATLAT]
5856 18:10:48.020119 Freq=933, CH1 RK1
5857 18:10:48.020184
5858 18:10:48.023728 DATLAT Default: 0xb
5859 18:10:48.023808 0, 0xFFFF, sum = 0
5860 18:10:48.026519 1, 0xFFFF, sum = 0
5861 18:10:48.026601 2, 0xFFFF, sum = 0
5862 18:10:48.030104 3, 0xFFFF, sum = 0
5863 18:10:48.030213 4, 0xFFFF, sum = 0
5864 18:10:48.033730 5, 0xFFFF, sum = 0
5865 18:10:48.033812 6, 0xFFFF, sum = 0
5866 18:10:48.036613 7, 0xFFFF, sum = 0
5867 18:10:48.040093 8, 0xFFFF, sum = 0
5868 18:10:48.040175 9, 0xFFFF, sum = 0
5869 18:10:48.042924 10, 0x0, sum = 1
5870 18:10:48.043006 11, 0x0, sum = 2
5871 18:10:48.043073 12, 0x0, sum = 3
5872 18:10:48.046642 13, 0x0, sum = 4
5873 18:10:48.046723 best_step = 11
5874 18:10:48.046788
5875 18:10:48.046848 ==
5876 18:10:48.050098 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 18:10:48.056621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 18:10:48.056703 ==
5879 18:10:48.056768 RX Vref Scan: 0
5880 18:10:48.056828
5881 18:10:48.059478 RX Vref 0 -> 0, step: 1
5882 18:10:48.059558
5883 18:10:48.063312 RX Delay -45 -> 252, step: 4
5884 18:10:48.066316 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5885 18:10:48.073422 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5886 18:10:48.076127 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5887 18:10:48.079365 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5888 18:10:48.082712 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5889 18:10:48.086549 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5890 18:10:48.092891 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5891 18:10:48.096217 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5892 18:10:48.099671 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5893 18:10:48.103225 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5894 18:10:48.105965 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5895 18:10:48.113164 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5896 18:10:48.116225 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5897 18:10:48.119316 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5898 18:10:48.122703 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5899 18:10:48.125827 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5900 18:10:48.125907 ==
5901 18:10:48.129329 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 18:10:48.135824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 18:10:48.135907 ==
5904 18:10:48.135972 DQS Delay:
5905 18:10:48.139494 DQS0 = 0, DQS1 = 0
5906 18:10:48.139575 DQM Delay:
5907 18:10:48.142429 DQM0 = 104, DQM1 = 99
5908 18:10:48.142509 DQ Delay:
5909 18:10:48.145880 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5910 18:10:48.149443 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5911 18:10:48.153080 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5912 18:10:48.156008 DQ12 =108, DQ13 =108, DQ14 =102, DQ15 =106
5913 18:10:48.156114
5914 18:10:48.156214
5915 18:10:48.166103 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5916 18:10:48.166187 CH1 RK1: MR19=504, MR18=2CFF
5917 18:10:48.172477 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5918 18:10:48.176158 [RxdqsGatingPostProcess] freq 933
5919 18:10:48.182729 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5920 18:10:48.185670 best DQS0 dly(2T, 0.5T) = (0, 10)
5921 18:10:48.189014 best DQS1 dly(2T, 0.5T) = (0, 10)
5922 18:10:48.193028 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5923 18:10:48.195651 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5924 18:10:48.195728 best DQS0 dly(2T, 0.5T) = (0, 10)
5925 18:10:48.199110 best DQS1 dly(2T, 0.5T) = (0, 10)
5926 18:10:48.202404 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5927 18:10:48.206268 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5928 18:10:48.208888 Pre-setting of DQS Precalculation
5929 18:10:48.215573 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5930 18:10:48.222692 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5931 18:10:48.229062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5932 18:10:48.229144
5933 18:10:48.229209
5934 18:10:48.232546 [Calibration Summary] 1866 Mbps
5935 18:10:48.232627 CH 0, Rank 0
5936 18:10:48.235805 SW Impedance : PASS
5937 18:10:48.238931 DUTY Scan : NO K
5938 18:10:48.239012 ZQ Calibration : PASS
5939 18:10:48.242014 Jitter Meter : NO K
5940 18:10:48.245975 CBT Training : PASS
5941 18:10:48.246059 Write leveling : PASS
5942 18:10:48.249147 RX DQS gating : PASS
5943 18:10:48.252059 RX DQ/DQS(RDDQC) : PASS
5944 18:10:48.252136 TX DQ/DQS : PASS
5945 18:10:48.255627 RX DATLAT : PASS
5946 18:10:48.258590 RX DQ/DQS(Engine): PASS
5947 18:10:48.258665 TX OE : NO K
5948 18:10:48.258729 All Pass.
5949 18:10:48.262239
5950 18:10:48.262314 CH 0, Rank 1
5951 18:10:48.265785 SW Impedance : PASS
5952 18:10:48.265862 DUTY Scan : NO K
5953 18:10:48.268744 ZQ Calibration : PASS
5954 18:10:48.268817 Jitter Meter : NO K
5955 18:10:48.272321 CBT Training : PASS
5956 18:10:48.275261 Write leveling : PASS
5957 18:10:48.275334 RX DQS gating : PASS
5958 18:10:48.278824 RX DQ/DQS(RDDQC) : PASS
5959 18:10:48.282457 TX DQ/DQS : PASS
5960 18:10:48.282531 RX DATLAT : PASS
5961 18:10:48.285339 RX DQ/DQS(Engine): PASS
5962 18:10:48.288950 TX OE : NO K
5963 18:10:48.289030 All Pass.
5964 18:10:48.289093
5965 18:10:48.289152 CH 1, Rank 0
5966 18:10:48.291894 SW Impedance : PASS
5967 18:10:48.295652 DUTY Scan : NO K
5968 18:10:48.295727 ZQ Calibration : PASS
5969 18:10:48.298379 Jitter Meter : NO K
5970 18:10:48.301819 CBT Training : PASS
5971 18:10:48.301893 Write leveling : PASS
5972 18:10:48.305247 RX DQS gating : PASS
5973 18:10:48.308670 RX DQ/DQS(RDDQC) : PASS
5974 18:10:48.308747 TX DQ/DQS : PASS
5975 18:10:48.312099 RX DATLAT : PASS
5976 18:10:48.315355 RX DQ/DQS(Engine): PASS
5977 18:10:48.315428 TX OE : NO K
5978 18:10:48.315492 All Pass.
5979 18:10:48.318401
5980 18:10:48.318549 CH 1, Rank 1
5981 18:10:48.322021 SW Impedance : PASS
5982 18:10:48.322098 DUTY Scan : NO K
5983 18:10:48.324850 ZQ Calibration : PASS
5984 18:10:48.328425 Jitter Meter : NO K
5985 18:10:48.328503 CBT Training : PASS
5986 18:10:48.331886 Write leveling : PASS
5987 18:10:48.331958 RX DQS gating : PASS
5988 18:10:48.334762 RX DQ/DQS(RDDQC) : PASS
5989 18:10:48.338496 TX DQ/DQS : PASS
5990 18:10:48.338577 RX DATLAT : PASS
5991 18:10:48.341913 RX DQ/DQS(Engine): PASS
5992 18:10:48.344907 TX OE : NO K
5993 18:10:48.344988 All Pass.
5994 18:10:48.345053
5995 18:10:48.348281 DramC Write-DBI off
5996 18:10:48.348401 PER_BANK_REFRESH: Hybrid Mode
5997 18:10:48.351507 TX_TRACKING: ON
5998 18:10:48.361460 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5999 18:10:48.364505 [FAST_K] Save calibration result to emmc
6000 18:10:48.368050 dramc_set_vcore_voltage set vcore to 650000
6001 18:10:48.370918 Read voltage for 400, 6
6002 18:10:48.371003 Vio18 = 0
6003 18:10:48.371073 Vcore = 650000
6004 18:10:48.374414 Vdram = 0
6005 18:10:48.374488 Vddq = 0
6006 18:10:48.374550 Vmddr = 0
6007 18:10:48.380949 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6008 18:10:48.384509 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6009 18:10:48.387501 MEM_TYPE=3, freq_sel=20
6010 18:10:48.390997 sv_algorithm_assistance_LP4_800
6011 18:10:48.394018 ============ PULL DRAM RESETB DOWN ============
6012 18:10:48.397917 ========== PULL DRAM RESETB DOWN end =========
6013 18:10:48.404503 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 18:10:48.407858 ===================================
6015 18:10:48.407932 LPDDR4 DRAM CONFIGURATION
6016 18:10:48.411415 ===================================
6017 18:10:48.414294 EX_ROW_EN[0] = 0x0
6018 18:10:48.417980 EX_ROW_EN[1] = 0x0
6019 18:10:48.418056 LP4Y_EN = 0x0
6020 18:10:48.420803 WORK_FSP = 0x0
6021 18:10:48.420873 WL = 0x2
6022 18:10:48.424222 RL = 0x2
6023 18:10:48.424292 BL = 0x2
6024 18:10:48.427759 RPST = 0x0
6025 18:10:48.427834 RD_PRE = 0x0
6026 18:10:48.431018 WR_PRE = 0x1
6027 18:10:48.431091 WR_PST = 0x0
6028 18:10:48.434193 DBI_WR = 0x0
6029 18:10:48.434262 DBI_RD = 0x0
6030 18:10:48.437344 OTF = 0x1
6031 18:10:48.441079 ===================================
6032 18:10:48.444625 ===================================
6033 18:10:48.444736 ANA top config
6034 18:10:48.447314 ===================================
6035 18:10:48.450974 DLL_ASYNC_EN = 0
6036 18:10:48.454060 ALL_SLAVE_EN = 1
6037 18:10:48.457563 NEW_RANK_MODE = 1
6038 18:10:48.457647 DLL_IDLE_MODE = 1
6039 18:10:48.460296 LP45_APHY_COMB_EN = 1
6040 18:10:48.463699 TX_ODT_DIS = 1
6041 18:10:48.467319 NEW_8X_MODE = 1
6042 18:10:48.470265 ===================================
6043 18:10:48.473913 ===================================
6044 18:10:48.477250 data_rate = 800
6045 18:10:48.477333 CKR = 1
6046 18:10:48.480478 DQ_P2S_RATIO = 4
6047 18:10:48.484118 ===================================
6048 18:10:48.487269 CA_P2S_RATIO = 4
6049 18:10:48.490612 DQ_CA_OPEN = 0
6050 18:10:48.494242 DQ_SEMI_OPEN = 1
6051 18:10:48.494324 CA_SEMI_OPEN = 1
6052 18:10:48.497082 CA_FULL_RATE = 0
6053 18:10:48.500750 DQ_CKDIV4_EN = 0
6054 18:10:48.503852 CA_CKDIV4_EN = 1
6055 18:10:48.506701 CA_PREDIV_EN = 0
6056 18:10:48.510221 PH8_DLY = 0
6057 18:10:48.510303 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6058 18:10:48.513866 DQ_AAMCK_DIV = 0
6059 18:10:48.516711 CA_AAMCK_DIV = 0
6060 18:10:48.520281 CA_ADMCK_DIV = 4
6061 18:10:48.523650 DQ_TRACK_CA_EN = 0
6062 18:10:48.526680 CA_PICK = 800
6063 18:10:48.530329 CA_MCKIO = 400
6064 18:10:48.530411 MCKIO_SEMI = 400
6065 18:10:48.533258 PLL_FREQ = 3016
6066 18:10:48.536899 DQ_UI_PI_RATIO = 32
6067 18:10:48.539821 CA_UI_PI_RATIO = 32
6068 18:10:48.543282 ===================================
6069 18:10:48.546616 ===================================
6070 18:10:48.549880 memory_type:LPDDR4
6071 18:10:48.549961 GP_NUM : 10
6072 18:10:48.553201 SRAM_EN : 1
6073 18:10:48.556534 MD32_EN : 0
6074 18:10:48.560320 ===================================
6075 18:10:48.560428 [ANA_INIT] >>>>>>>>>>>>>>
6076 18:10:48.563469 <<<<<< [CONFIGURE PHASE]: ANA_TX
6077 18:10:48.566834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6078 18:10:48.570387 ===================================
6079 18:10:48.573283 data_rate = 800,PCW = 0X7400
6080 18:10:48.576832 ===================================
6081 18:10:48.579739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6082 18:10:48.586259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 18:10:48.596619 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6084 18:10:48.602897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6085 18:10:48.606364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6086 18:10:48.609844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6087 18:10:48.609926 [ANA_INIT] flow start
6088 18:10:48.612994 [ANA_INIT] PLL >>>>>>>>
6089 18:10:48.616631 [ANA_INIT] PLL <<<<<<<<
6090 18:10:48.616712 [ANA_INIT] MIDPI >>>>>>>>
6091 18:10:48.619495 [ANA_INIT] MIDPI <<<<<<<<
6092 18:10:48.623209 [ANA_INIT] DLL >>>>>>>>
6093 18:10:48.623291 [ANA_INIT] flow end
6094 18:10:48.629466 ============ LP4 DIFF to SE enter ============
6095 18:10:48.632924 ============ LP4 DIFF to SE exit ============
6096 18:10:48.636517 [ANA_INIT] <<<<<<<<<<<<<
6097 18:10:48.640084 [Flow] Enable top DCM control >>>>>
6098 18:10:48.640168 [Flow] Enable top DCM control <<<<<
6099 18:10:48.643138 Enable DLL master slave shuffle
6100 18:10:48.649565 ==============================================================
6101 18:10:48.653171 Gating Mode config
6102 18:10:48.655953 ==============================================================
6103 18:10:48.659418 Config description:
6104 18:10:48.669639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6105 18:10:48.676614 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6106 18:10:48.679495 SELPH_MODE 0: By rank 1: By Phase
6107 18:10:48.685927 ==============================================================
6108 18:10:48.689132 GAT_TRACK_EN = 0
6109 18:10:48.692744 RX_GATING_MODE = 2
6110 18:10:48.696246 RX_GATING_TRACK_MODE = 2
6111 18:10:48.699170 SELPH_MODE = 1
6112 18:10:48.699251 PICG_EARLY_EN = 1
6113 18:10:48.702653 VALID_LAT_VALUE = 1
6114 18:10:48.709493 ==============================================================
6115 18:10:48.712267 Enter into Gating configuration >>>>
6116 18:10:48.717248 Exit from Gating configuration <<<<
6117 18:10:48.719248 Enter into DVFS_PRE_config >>>>>
6118 18:10:48.728612 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6119 18:10:48.732356 Exit from DVFS_PRE_config <<<<<
6120 18:10:48.735952 Enter into PICG configuration >>>>
6121 18:10:48.738712 Exit from PICG configuration <<<<
6122 18:10:48.742272 [RX_INPUT] configuration >>>>>
6123 18:10:48.745908 [RX_INPUT] configuration <<<<<
6124 18:10:48.748719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6125 18:10:48.755888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6126 18:10:48.762323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6127 18:10:48.768768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6128 18:10:48.775095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 18:10:48.782294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 18:10:48.785195 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6131 18:10:48.788789 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6132 18:10:48.792200 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6133 18:10:48.794946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6134 18:10:48.801923 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6135 18:10:48.805150 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6136 18:10:48.808295 ===================================
6137 18:10:48.811609 LPDDR4 DRAM CONFIGURATION
6138 18:10:48.815189 ===================================
6139 18:10:48.815293 EX_ROW_EN[0] = 0x0
6140 18:10:48.818690 EX_ROW_EN[1] = 0x0
6141 18:10:48.818789 LP4Y_EN = 0x0
6142 18:10:48.821426 WORK_FSP = 0x0
6143 18:10:48.821535 WL = 0x2
6144 18:10:48.825192 RL = 0x2
6145 18:10:48.828542 BL = 0x2
6146 18:10:48.828642 RPST = 0x0
6147 18:10:48.831916 RD_PRE = 0x0
6148 18:10:48.832019 WR_PRE = 0x1
6149 18:10:48.835075 WR_PST = 0x0
6150 18:10:48.835177 DBI_WR = 0x0
6151 18:10:48.838611 DBI_RD = 0x0
6152 18:10:48.838689 OTF = 0x1
6153 18:10:48.841376 ===================================
6154 18:10:48.844995 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6155 18:10:48.851441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6156 18:10:48.854932 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 18:10:48.857889 ===================================
6158 18:10:48.861561 LPDDR4 DRAM CONFIGURATION
6159 18:10:48.864552 ===================================
6160 18:10:48.864652 EX_ROW_EN[0] = 0x10
6161 18:10:48.868022 EX_ROW_EN[1] = 0x0
6162 18:10:48.868124 LP4Y_EN = 0x0
6163 18:10:48.871631 WORK_FSP = 0x0
6164 18:10:48.871734 WL = 0x2
6165 18:10:48.874390 RL = 0x2
6166 18:10:48.877987 BL = 0x2
6167 18:10:48.878090 RPST = 0x0
6168 18:10:48.880913 RD_PRE = 0x0
6169 18:10:48.881013 WR_PRE = 0x1
6170 18:10:48.884497 WR_PST = 0x0
6171 18:10:48.884594 DBI_WR = 0x0
6172 18:10:48.888220 DBI_RD = 0x0
6173 18:10:48.888315 OTF = 0x1
6174 18:10:48.890941 ===================================
6175 18:10:48.897568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6176 18:10:48.901988 nWR fixed to 30
6177 18:10:48.904836 [ModeRegInit_LP4] CH0 RK0
6178 18:10:48.904924 [ModeRegInit_LP4] CH0 RK1
6179 18:10:48.908352 [ModeRegInit_LP4] CH1 RK0
6180 18:10:48.911899 [ModeRegInit_LP4] CH1 RK1
6181 18:10:48.912009 match AC timing 19
6182 18:10:48.918608 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6183 18:10:48.921620 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6184 18:10:48.924762 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6185 18:10:48.931424 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6186 18:10:48.934659 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6187 18:10:48.934756 ==
6188 18:10:48.938097 Dram Type= 6, Freq= 0, CH_0, rank 0
6189 18:10:48.941002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6190 18:10:48.941084 ==
6191 18:10:48.947611 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6192 18:10:48.954759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6193 18:10:48.957808 [CA 0] Center 36 (8~64) winsize 57
6194 18:10:48.961227 [CA 1] Center 36 (8~64) winsize 57
6195 18:10:48.964250 [CA 2] Center 36 (8~64) winsize 57
6196 18:10:48.967705 [CA 3] Center 36 (8~64) winsize 57
6197 18:10:48.971485 [CA 4] Center 36 (8~64) winsize 57
6198 18:10:48.971568 [CA 5] Center 36 (8~64) winsize 57
6199 18:10:48.974190
6200 18:10:48.977744 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6201 18:10:48.977826
6202 18:10:48.981270 [CATrainingPosCal] consider 1 rank data
6203 18:10:48.984243 u2DelayCellTimex100 = 270/100 ps
6204 18:10:48.987765 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 18:10:48.991394 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 18:10:48.994317 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 18:10:48.997925 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 18:10:49.000867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 18:10:49.004501 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 18:10:49.004583
6211 18:10:49.008055 CA PerBit enable=1, Macro0, CA PI delay=36
6212 18:10:49.008136
6213 18:10:49.010897 [CBTSetCACLKResult] CA Dly = 36
6214 18:10:49.014613 CS Dly: 1 (0~32)
6215 18:10:49.014694 ==
6216 18:10:49.017458 Dram Type= 6, Freq= 0, CH_0, rank 1
6217 18:10:49.021133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 18:10:49.021215 ==
6219 18:10:49.027547 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 18:10:49.034270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6221 18:10:49.034353 [CA 0] Center 36 (8~64) winsize 57
6222 18:10:49.037635 [CA 1] Center 36 (8~64) winsize 57
6223 18:10:49.041206 [CA 2] Center 36 (8~64) winsize 57
6224 18:10:49.044502 [CA 3] Center 36 (8~64) winsize 57
6225 18:10:49.047546 [CA 4] Center 36 (8~64) winsize 57
6226 18:10:49.051023 [CA 5] Center 36 (8~64) winsize 57
6227 18:10:49.051104
6228 18:10:49.054408 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6229 18:10:49.054490
6230 18:10:49.057346 [CATrainingPosCal] consider 2 rank data
6231 18:10:49.060761 u2DelayCellTimex100 = 270/100 ps
6232 18:10:49.064215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 18:10:49.067530 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 18:10:49.074159 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 18:10:49.077275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 18:10:49.080910 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 18:10:49.084138 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 18:10:49.084219
6239 18:10:49.087130 CA PerBit enable=1, Macro0, CA PI delay=36
6240 18:10:49.087212
6241 18:10:49.090842 [CBTSetCACLKResult] CA Dly = 36
6242 18:10:49.090923 CS Dly: 1 (0~32)
6243 18:10:49.090989
6244 18:10:49.094224 ----->DramcWriteLeveling(PI) begin...
6245 18:10:49.097173 ==
6246 18:10:49.100721 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 18:10:49.103746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 18:10:49.103829 ==
6249 18:10:49.107505 Write leveling (Byte 0): 40 => 8
6250 18:10:49.110318 Write leveling (Byte 1): 40 => 8
6251 18:10:49.113797 DramcWriteLeveling(PI) end<-----
6252 18:10:49.113879
6253 18:10:49.113944 ==
6254 18:10:49.117625 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 18:10:49.120397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 18:10:49.120479 ==
6257 18:10:49.124193 [Gating] SW mode calibration
6258 18:10:49.130932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6259 18:10:49.133923 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6260 18:10:49.140851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 18:10:49.143817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6262 18:10:49.147364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 18:10:49.153883 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6264 18:10:49.157241 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 18:10:49.160690 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 18:10:49.167061 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 18:10:49.170556 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 18:10:49.174293 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 18:10:49.177184 Total UI for P1: 0, mck2ui 16
6270 18:10:49.180925 best dqsien dly found for B0: ( 0, 14, 24)
6271 18:10:49.183712 Total UI for P1: 0, mck2ui 16
6272 18:10:49.187014 best dqsien dly found for B1: ( 0, 14, 24)
6273 18:10:49.190650 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6274 18:10:49.194175 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6275 18:10:49.194256
6276 18:10:49.200306 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 18:10:49.203638 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6278 18:10:49.207321 [Gating] SW calibration Done
6279 18:10:49.207402 ==
6280 18:10:49.210395 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 18:10:49.214121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 18:10:49.214202 ==
6283 18:10:49.214267 RX Vref Scan: 0
6284 18:10:49.214328
6285 18:10:49.216961 RX Vref 0 -> 0, step: 1
6286 18:10:49.217041
6287 18:10:49.220465 RX Delay -410 -> 252, step: 16
6288 18:10:49.223507 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6289 18:10:49.230049 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6290 18:10:49.233647 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6291 18:10:49.237388 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6292 18:10:49.240089 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6293 18:10:49.246925 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6294 18:10:49.250471 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6295 18:10:49.253276 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6296 18:10:49.256777 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6297 18:10:49.263127 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6298 18:10:49.266684 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6299 18:10:49.270250 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6300 18:10:49.273216 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6301 18:10:49.279930 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6302 18:10:49.282915 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6303 18:10:49.286404 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6304 18:10:49.286484 ==
6305 18:10:49.289938 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 18:10:49.296285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 18:10:49.296409 ==
6308 18:10:49.296507 DQS Delay:
6309 18:10:49.299987 DQS0 = 27, DQS1 = 35
6310 18:10:49.300070 DQM Delay:
6311 18:10:49.300135 DQM0 = 9, DQM1 = 11
6312 18:10:49.302845 DQ Delay:
6313 18:10:49.306433 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6314 18:10:49.306513 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6315 18:10:49.309390 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6316 18:10:49.313043 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6317 18:10:49.313124
6318 18:10:49.313187
6319 18:10:49.316397 ==
6320 18:10:49.319838 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 18:10:49.323087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 18:10:49.323169 ==
6323 18:10:49.323234
6324 18:10:49.323294
6325 18:10:49.326085 TX Vref Scan disable
6326 18:10:49.326165 == TX Byte 0 ==
6327 18:10:49.329987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 18:10:49.336270 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 18:10:49.336377 == TX Byte 1 ==
6330 18:10:49.339178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 18:10:49.346234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 18:10:49.346315 ==
6333 18:10:49.348982 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 18:10:49.352377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 18:10:49.352471 ==
6336 18:10:49.352534
6337 18:10:49.352593
6338 18:10:49.355693 TX Vref Scan disable
6339 18:10:49.355773 == TX Byte 0 ==
6340 18:10:49.359508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 18:10:49.365798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 18:10:49.365880 == TX Byte 1 ==
6343 18:10:49.369231 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 18:10:49.375669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 18:10:49.375751
6346 18:10:49.375814 [DATLAT]
6347 18:10:49.375873 Freq=400, CH0 RK0
6348 18:10:49.379145
6349 18:10:49.379224 DATLAT Default: 0xf
6350 18:10:49.382541 0, 0xFFFF, sum = 0
6351 18:10:49.382623 1, 0xFFFF, sum = 0
6352 18:10:49.385873 2, 0xFFFF, sum = 0
6353 18:10:49.385954 3, 0xFFFF, sum = 0
6354 18:10:49.388628 4, 0xFFFF, sum = 0
6355 18:10:49.388709 5, 0xFFFF, sum = 0
6356 18:10:49.392323 6, 0xFFFF, sum = 0
6357 18:10:49.392444 7, 0xFFFF, sum = 0
6358 18:10:49.395877 8, 0xFFFF, sum = 0
6359 18:10:49.395958 9, 0xFFFF, sum = 0
6360 18:10:49.398756 10, 0xFFFF, sum = 0
6361 18:10:49.398837 11, 0xFFFF, sum = 0
6362 18:10:49.402246 12, 0xFFFF, sum = 0
6363 18:10:49.402327 13, 0x0, sum = 1
6364 18:10:49.405873 14, 0x0, sum = 2
6365 18:10:49.405954 15, 0x0, sum = 3
6366 18:10:49.408772 16, 0x0, sum = 4
6367 18:10:49.408853 best_step = 14
6368 18:10:49.408917
6369 18:10:49.408976 ==
6370 18:10:49.412275 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 18:10:49.418906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 18:10:49.418987 ==
6373 18:10:49.419051 RX Vref Scan: 1
6374 18:10:49.419110
6375 18:10:49.421838 RX Vref 0 -> 0, step: 1
6376 18:10:49.421917
6377 18:10:49.425357 RX Delay -311 -> 252, step: 8
6378 18:10:49.425438
6379 18:10:49.429021 Set Vref, RX VrefLevel [Byte0]: 53
6380 18:10:49.431684 [Byte1]: 48
6381 18:10:49.431764
6382 18:10:49.435186 Final RX Vref Byte 0 = 53 to rank0
6383 18:10:49.438505 Final RX Vref Byte 1 = 48 to rank0
6384 18:10:49.442210 Final RX Vref Byte 0 = 53 to rank1
6385 18:10:49.445093 Final RX Vref Byte 1 = 48 to rank1==
6386 18:10:49.448267 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 18:10:49.451753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 18:10:49.455198 ==
6389 18:10:49.455278 DQS Delay:
6390 18:10:49.455341 DQS0 = 24, DQS1 = 36
6391 18:10:49.458285 DQM Delay:
6392 18:10:49.458365 DQM0 = 7, DQM1 = 13
6393 18:10:49.461488 DQ Delay:
6394 18:10:49.461568 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6395 18:10:49.464918 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6396 18:10:49.468312 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6397 18:10:49.472036 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6398 18:10:49.472116
6399 18:10:49.472179
6400 18:10:49.481850 [DQSOSCAuto] RK0, (LSB)MR18= 0xc4b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6401 18:10:49.484805 CH0 RK0: MR19=C0C, MR18=C4B1
6402 18:10:49.488225 CH0_RK0: MR19=0xC0C, MR18=0xC4B1, DQSOSC=385, MR23=63, INC=398, DEC=265
6403 18:10:49.491762 ==
6404 18:10:49.494471 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 18:10:49.498203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 18:10:49.498285 ==
6407 18:10:49.501176 [Gating] SW mode calibration
6408 18:10:49.508149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6409 18:10:49.511624 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6410 18:10:49.518257 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 18:10:49.521055 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6412 18:10:49.524674 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 18:10:49.531205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6414 18:10:49.534882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 18:10:49.537882 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 18:10:49.544462 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 18:10:49.548117 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 18:10:49.551851 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 18:10:49.554511 Total UI for P1: 0, mck2ui 16
6420 18:10:49.557779 best dqsien dly found for B0: ( 0, 14, 24)
6421 18:10:49.561043 Total UI for P1: 0, mck2ui 16
6422 18:10:49.564561 best dqsien dly found for B1: ( 0, 14, 24)
6423 18:10:49.568111 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6424 18:10:49.571530 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6425 18:10:49.571615
6426 18:10:49.577652 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 18:10:49.581600 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6428 18:10:49.581685 [Gating] SW calibration Done
6429 18:10:49.584475 ==
6430 18:10:49.587647 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 18:10:49.591299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 18:10:49.591381 ==
6433 18:10:49.591447 RX Vref Scan: 0
6434 18:10:49.591507
6435 18:10:49.594722 RX Vref 0 -> 0, step: 1
6436 18:10:49.594843
6437 18:10:49.598060 RX Delay -410 -> 252, step: 16
6438 18:10:49.600887 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6439 18:10:49.604764 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6440 18:10:49.611028 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6441 18:10:49.614585 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6442 18:10:49.618056 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6443 18:10:49.621032 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6444 18:10:49.627615 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6445 18:10:49.631255 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6446 18:10:49.634230 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6447 18:10:49.637705 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6448 18:10:49.644491 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6449 18:10:49.648134 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6450 18:10:49.651554 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6451 18:10:49.654391 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6452 18:10:49.661559 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6453 18:10:49.664356 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6454 18:10:49.664452 ==
6455 18:10:49.668039 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 18:10:49.670916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 18:10:49.671002 ==
6458 18:10:49.674187 DQS Delay:
6459 18:10:49.674269 DQS0 = 27, DQS1 = 35
6460 18:10:49.677625 DQM Delay:
6461 18:10:49.677706 DQM0 = 13, DQM1 = 11
6462 18:10:49.677771 DQ Delay:
6463 18:10:49.681068 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6464 18:10:49.684517 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6465 18:10:49.687372 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6466 18:10:49.691043 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6467 18:10:49.691151
6468 18:10:49.691248
6469 18:10:49.691342 ==
6470 18:10:49.694550 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 18:10:49.700817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 18:10:49.700900 ==
6473 18:10:49.700983
6474 18:10:49.701044
6475 18:10:49.701103 TX Vref Scan disable
6476 18:10:49.704236 == TX Byte 0 ==
6477 18:10:49.707580 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6478 18:10:49.710910 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6479 18:10:49.714104 == TX Byte 1 ==
6480 18:10:49.717631 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6481 18:10:49.720592 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6482 18:10:49.720674 ==
6483 18:10:49.724100 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 18:10:49.730826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 18:10:49.730910 ==
6486 18:10:49.730975
6487 18:10:49.731035
6488 18:10:49.731093 TX Vref Scan disable
6489 18:10:49.734057 == TX Byte 0 ==
6490 18:10:49.737129 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6491 18:10:49.740862 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6492 18:10:49.743750 == TX Byte 1 ==
6493 18:10:49.747361 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6494 18:10:49.751052 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6495 18:10:49.751133
6496 18:10:49.753900 [DATLAT]
6497 18:10:49.753981 Freq=400, CH0 RK1
6498 18:10:49.754046
6499 18:10:49.757567 DATLAT Default: 0xe
6500 18:10:49.757648 0, 0xFFFF, sum = 0
6501 18:10:49.760482 1, 0xFFFF, sum = 0
6502 18:10:49.760565 2, 0xFFFF, sum = 0
6503 18:10:49.764140 3, 0xFFFF, sum = 0
6504 18:10:49.764248 4, 0xFFFF, sum = 0
6505 18:10:49.767761 5, 0xFFFF, sum = 0
6506 18:10:49.767843 6, 0xFFFF, sum = 0
6507 18:10:49.770674 7, 0xFFFF, sum = 0
6508 18:10:49.770756 8, 0xFFFF, sum = 0
6509 18:10:49.774247 9, 0xFFFF, sum = 0
6510 18:10:49.774328 10, 0xFFFF, sum = 0
6511 18:10:49.777396 11, 0xFFFF, sum = 0
6512 18:10:49.780648 12, 0xFFFF, sum = 0
6513 18:10:49.780730 13, 0x0, sum = 1
6514 18:10:49.780796 14, 0x0, sum = 2
6515 18:10:49.784086 15, 0x0, sum = 3
6516 18:10:49.784168 16, 0x0, sum = 4
6517 18:10:49.787365 best_step = 14
6518 18:10:49.787446
6519 18:10:49.787511 ==
6520 18:10:49.790235 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 18:10:49.793700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 18:10:49.793781 ==
6523 18:10:49.797260 RX Vref Scan: 0
6524 18:10:49.797342
6525 18:10:49.797406 RX Vref 0 -> 0, step: 1
6526 18:10:49.800137
6527 18:10:49.800218 RX Delay -311 -> 252, step: 8
6528 18:10:49.808701 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6529 18:10:49.812365 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6530 18:10:49.815252 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6531 18:10:49.818847 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6532 18:10:49.825250 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6533 18:10:49.828612 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6534 18:10:49.832188 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6535 18:10:49.834917 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6536 18:10:49.841748 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6537 18:10:49.844718 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6538 18:10:49.848425 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6539 18:10:49.854906 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6540 18:10:49.858275 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6541 18:10:49.861859 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6542 18:10:49.864824 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6543 18:10:49.871228 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6544 18:10:49.871309 ==
6545 18:10:49.874772 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 18:10:49.878423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 18:10:49.878505 ==
6548 18:10:49.878570 DQS Delay:
6549 18:10:49.881222 DQS0 = 24, DQS1 = 32
6550 18:10:49.881303 DQM Delay:
6551 18:10:49.884832 DQM0 = 9, DQM1 = 10
6552 18:10:49.884912 DQ Delay:
6553 18:10:49.887792 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6554 18:10:49.891289 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =20
6555 18:10:49.894632 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6556 18:10:49.898067 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6557 18:10:49.898149
6558 18:10:49.898214
6559 18:10:49.904559 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6560 18:10:49.908141 CH0 RK1: MR19=C0C, MR18=BA5A
6561 18:10:49.914466 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6562 18:10:49.918181 [RxdqsGatingPostProcess] freq 400
6563 18:10:49.924664 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6564 18:10:49.924745 best DQS0 dly(2T, 0.5T) = (0, 10)
6565 18:10:49.927707 best DQS1 dly(2T, 0.5T) = (0, 10)
6566 18:10:49.931493 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6567 18:10:49.934727 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6568 18:10:49.937524 best DQS0 dly(2T, 0.5T) = (0, 10)
6569 18:10:49.940983 best DQS1 dly(2T, 0.5T) = (0, 10)
6570 18:10:49.944657 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6571 18:10:49.947574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6572 18:10:49.951056 Pre-setting of DQS Precalculation
6573 18:10:49.957723 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6574 18:10:49.957825 ==
6575 18:10:49.960907 Dram Type= 6, Freq= 0, CH_1, rank 0
6576 18:10:49.964569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 18:10:49.964719 ==
6578 18:10:49.971099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6579 18:10:49.974228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6580 18:10:49.977927 [CA 0] Center 36 (8~64) winsize 57
6581 18:10:49.980841 [CA 1] Center 36 (8~64) winsize 57
6582 18:10:49.984599 [CA 2] Center 36 (8~64) winsize 57
6583 18:10:49.987957 [CA 3] Center 36 (8~64) winsize 57
6584 18:10:49.991037 [CA 4] Center 36 (8~64) winsize 57
6585 18:10:49.994675 [CA 5] Center 36 (8~64) winsize 57
6586 18:10:49.994756
6587 18:10:49.997521 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6588 18:10:49.997603
6589 18:10:50.001025 [CATrainingPosCal] consider 1 rank data
6590 18:10:50.003880 u2DelayCellTimex100 = 270/100 ps
6591 18:10:50.007218 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 18:10:50.010642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 18:10:50.014014 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 18:10:50.020978 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 18:10:50.024431 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 18:10:50.027304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 18:10:50.027385
6598 18:10:50.030864 CA PerBit enable=1, Macro0, CA PI delay=36
6599 18:10:50.030945
6600 18:10:50.033718 [CBTSetCACLKResult] CA Dly = 36
6601 18:10:50.033798 CS Dly: 1 (0~32)
6602 18:10:50.033863 ==
6603 18:10:50.037431 Dram Type= 6, Freq= 0, CH_1, rank 1
6604 18:10:50.043591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 18:10:50.043673 ==
6606 18:10:50.047252 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 18:10:50.053840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6608 18:10:50.057243 [CA 0] Center 36 (8~64) winsize 57
6609 18:10:50.060173 [CA 1] Center 36 (8~64) winsize 57
6610 18:10:50.063593 [CA 2] Center 36 (8~64) winsize 57
6611 18:10:50.067080 [CA 3] Center 36 (8~64) winsize 57
6612 18:10:50.069916 [CA 4] Center 36 (8~64) winsize 57
6613 18:10:50.073387 [CA 5] Center 36 (8~64) winsize 57
6614 18:10:50.073467
6615 18:10:50.077020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6616 18:10:50.077100
6617 18:10:50.080544 [CATrainingPosCal] consider 2 rank data
6618 18:10:50.083905 u2DelayCellTimex100 = 270/100 ps
6619 18:10:50.086615 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 18:10:50.089956 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 18:10:50.093808 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 18:10:50.096665 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 18:10:50.100375 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 18:10:50.106988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 18:10:50.107068
6626 18:10:50.110049 CA PerBit enable=1, Macro0, CA PI delay=36
6627 18:10:50.110129
6628 18:10:50.113511 [CBTSetCACLKResult] CA Dly = 36
6629 18:10:50.113651 CS Dly: 1 (0~32)
6630 18:10:50.113744
6631 18:10:50.116917 ----->DramcWriteLeveling(PI) begin...
6632 18:10:50.117026 ==
6633 18:10:50.119753 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 18:10:50.123358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 18:10:50.126733 ==
6636 18:10:50.126813 Write leveling (Byte 0): 40 => 8
6637 18:10:50.130066 Write leveling (Byte 1): 40 => 8
6638 18:10:50.133200 DramcWriteLeveling(PI) end<-----
6639 18:10:50.133288
6640 18:10:50.133352 ==
6641 18:10:50.136430 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 18:10:50.143344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 18:10:50.143425 ==
6644 18:10:50.146171 [Gating] SW mode calibration
6645 18:10:50.153098 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 18:10:50.156000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6647 18:10:50.163047 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 18:10:50.166028 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 18:10:50.169464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 18:10:50.176256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6651 18:10:50.179646 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 18:10:50.182770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 18:10:50.189164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 18:10:50.192694 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 18:10:50.196335 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 18:10:50.199314 Total UI for P1: 0, mck2ui 16
6657 18:10:50.202631 best dqsien dly found for B0: ( 0, 14, 24)
6658 18:10:50.205925 Total UI for P1: 0, mck2ui 16
6659 18:10:50.209724 best dqsien dly found for B1: ( 0, 14, 24)
6660 18:10:50.212475 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6661 18:10:50.216476 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6662 18:10:50.216557
6663 18:10:50.219186 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 18:10:50.225689 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6665 18:10:50.225770 [Gating] SW calibration Done
6666 18:10:50.225835 ==
6667 18:10:50.229289 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 18:10:50.235883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 18:10:50.235964 ==
6670 18:10:50.236029 RX Vref Scan: 0
6671 18:10:50.236091
6672 18:10:50.239363 RX Vref 0 -> 0, step: 1
6673 18:10:50.239444
6674 18:10:50.242789 RX Delay -410 -> 252, step: 16
6675 18:10:50.245986 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6676 18:10:50.249185 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6677 18:10:50.255686 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6678 18:10:50.259040 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6679 18:10:50.262460 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6680 18:10:50.265788 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6681 18:10:50.272280 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6682 18:10:50.276022 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6683 18:10:50.279215 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6684 18:10:50.282642 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6685 18:10:50.289111 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6686 18:10:50.292055 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6687 18:10:50.295605 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6688 18:10:50.299242 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6689 18:10:50.305652 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6690 18:10:50.308629 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6691 18:10:50.308710 ==
6692 18:10:50.312093 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 18:10:50.315586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 18:10:50.315671 ==
6695 18:10:50.318866 DQS Delay:
6696 18:10:50.318946 DQS0 = 27, DQS1 = 35
6697 18:10:50.322234 DQM Delay:
6698 18:10:50.322314 DQM0 = 9, DQM1 = 13
6699 18:10:50.322378 DQ Delay:
6700 18:10:50.325500 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6701 18:10:50.328547 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6702 18:10:50.332072 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 18:10:50.335058 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6704 18:10:50.335159
6705 18:10:50.335255
6706 18:10:50.335344 ==
6707 18:10:50.338601 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 18:10:50.345166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 18:10:50.345269 ==
6710 18:10:50.345364
6711 18:10:50.345454
6712 18:10:50.345540 TX Vref Scan disable
6713 18:10:50.348722 == TX Byte 0 ==
6714 18:10:50.352128 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 18:10:50.354853 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 18:10:50.358377 == TX Byte 1 ==
6717 18:10:50.361879 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 18:10:50.365288 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 18:10:50.365369 ==
6720 18:10:50.368702 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 18:10:50.375252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 18:10:50.375339 ==
6723 18:10:50.375404
6724 18:10:50.375464
6725 18:10:50.375523 TX Vref Scan disable
6726 18:10:50.378396 == TX Byte 0 ==
6727 18:10:50.381776 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 18:10:50.384988 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 18:10:50.388791 == TX Byte 1 ==
6730 18:10:50.391903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 18:10:50.395346 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 18:10:50.395427
6733 18:10:50.398734 [DATLAT]
6734 18:10:50.398814 Freq=400, CH1 RK0
6735 18:10:50.398879
6736 18:10:50.401408 DATLAT Default: 0xf
6737 18:10:50.401488 0, 0xFFFF, sum = 0
6738 18:10:50.405048 1, 0xFFFF, sum = 0
6739 18:10:50.405130 2, 0xFFFF, sum = 0
6740 18:10:50.408056 3, 0xFFFF, sum = 0
6741 18:10:50.408137 4, 0xFFFF, sum = 0
6742 18:10:50.411645 5, 0xFFFF, sum = 0
6743 18:10:50.411754 6, 0xFFFF, sum = 0
6744 18:10:50.415247 7, 0xFFFF, sum = 0
6745 18:10:50.415330 8, 0xFFFF, sum = 0
6746 18:10:50.418320 9, 0xFFFF, sum = 0
6747 18:10:50.418402 10, 0xFFFF, sum = 0
6748 18:10:50.422048 11, 0xFFFF, sum = 0
6749 18:10:50.425085 12, 0xFFFF, sum = 0
6750 18:10:50.425167 13, 0x0, sum = 1
6751 18:10:50.425233 14, 0x0, sum = 2
6752 18:10:50.428139 15, 0x0, sum = 3
6753 18:10:50.428221 16, 0x0, sum = 4
6754 18:10:50.431385 best_step = 14
6755 18:10:50.431466
6756 18:10:50.431530 ==
6757 18:10:50.434785 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 18:10:50.438174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 18:10:50.438256 ==
6760 18:10:50.441902 RX Vref Scan: 1
6761 18:10:50.441983
6762 18:10:50.442047 RX Vref 0 -> 0, step: 1
6763 18:10:50.442108
6764 18:10:50.445068 RX Delay -311 -> 252, step: 8
6765 18:10:50.445150
6766 18:10:50.448201 Set Vref, RX VrefLevel [Byte0]: 55
6767 18:10:50.451177 [Byte1]: 52
6768 18:10:50.456401
6769 18:10:50.456490 Final RX Vref Byte 0 = 55 to rank0
6770 18:10:50.459784 Final RX Vref Byte 1 = 52 to rank0
6771 18:10:50.463054 Final RX Vref Byte 0 = 55 to rank1
6772 18:10:50.466000 Final RX Vref Byte 1 = 52 to rank1==
6773 18:10:50.469630 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 18:10:50.476080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 18:10:50.476162 ==
6776 18:10:50.476227 DQS Delay:
6777 18:10:50.479497 DQS0 = 28, DQS1 = 32
6778 18:10:50.479592 DQM Delay:
6779 18:10:50.479658 DQM0 = 9, DQM1 = 10
6780 18:10:50.483046 DQ Delay:
6781 18:10:50.485969 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6782 18:10:50.486050 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6783 18:10:50.489438 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6784 18:10:50.492796 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6785 18:10:50.492876
6786 18:10:50.492940
6787 18:10:50.502745 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6788 18:10:50.506227 CH1 RK0: MR19=C0C, MR18=8FC8
6789 18:10:50.513094 CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265
6790 18:10:50.513177 ==
6791 18:10:50.515828 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 18:10:50.519494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 18:10:50.519576 ==
6794 18:10:50.523125 [Gating] SW mode calibration
6795 18:10:50.529723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6796 18:10:50.532682 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6797 18:10:50.539189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 18:10:50.543058 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6799 18:10:50.545894 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 18:10:50.552752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6801 18:10:50.556143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 18:10:50.559364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 18:10:50.566311 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 18:10:50.569538 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 18:10:50.572428 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 18:10:50.575686 Total UI for P1: 0, mck2ui 16
6807 18:10:50.579366 best dqsien dly found for B0: ( 0, 14, 24)
6808 18:10:50.583002 Total UI for P1: 0, mck2ui 16
6809 18:10:50.585864 best dqsien dly found for B1: ( 0, 14, 24)
6810 18:10:50.589495 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6811 18:10:50.592394 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6812 18:10:50.592474
6813 18:10:50.598992 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 18:10:50.602603 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6815 18:10:50.602701 [Gating] SW calibration Done
6816 18:10:50.605717 ==
6817 18:10:50.608899 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 18:10:50.612513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 18:10:50.612613 ==
6820 18:10:50.612709 RX Vref Scan: 0
6821 18:10:50.612799
6822 18:10:50.615981 RX Vref 0 -> 0, step: 1
6823 18:10:50.616083
6824 18:10:50.619304 RX Delay -410 -> 252, step: 16
6825 18:10:50.622616 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6826 18:10:50.628708 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6827 18:10:50.632431 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6828 18:10:50.635363 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6829 18:10:50.639057 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6830 18:10:50.645703 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6831 18:10:50.648647 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6832 18:10:50.652274 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6833 18:10:50.655380 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6834 18:10:50.658993 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6835 18:10:50.665331 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6836 18:10:50.668784 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6837 18:10:50.672188 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6838 18:10:50.678970 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6839 18:10:50.682149 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6840 18:10:50.685710 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6841 18:10:50.685791 ==
6842 18:10:50.688883 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 18:10:50.692211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 18:10:50.692293 ==
6845 18:10:50.695769 DQS Delay:
6846 18:10:50.695850 DQS0 = 35, DQS1 = 35
6847 18:10:50.698747 DQM Delay:
6848 18:10:50.698829 DQM0 = 18, DQM1 = 14
6849 18:10:50.702367 DQ Delay:
6850 18:10:50.702448 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6851 18:10:50.705330 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6852 18:10:50.708797 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6853 18:10:50.712279 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6854 18:10:50.712384
6855 18:10:50.712451
6856 18:10:50.715083 ==
6857 18:10:50.715164 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 18:10:50.722033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 18:10:50.722116 ==
6860 18:10:50.722182
6861 18:10:50.722242
6862 18:10:50.725348 TX Vref Scan disable
6863 18:10:50.725430 == TX Byte 0 ==
6864 18:10:50.728658 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6865 18:10:50.735028 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6866 18:10:50.735111 == TX Byte 1 ==
6867 18:10:50.738535 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6868 18:10:50.745250 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6869 18:10:50.745334 ==
6870 18:10:50.748781 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 18:10:50.751652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 18:10:50.751733 ==
6873 18:10:50.751799
6874 18:10:50.751859
6875 18:10:50.755235 TX Vref Scan disable
6876 18:10:50.755316 == TX Byte 0 ==
6877 18:10:50.758261 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6878 18:10:50.764674 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6879 18:10:50.764757 == TX Byte 1 ==
6880 18:10:50.768226 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6881 18:10:50.774620 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6882 18:10:50.774702
6883 18:10:50.774767 [DATLAT]
6884 18:10:50.774828 Freq=400, CH1 RK1
6885 18:10:50.774887
6886 18:10:50.778286 DATLAT Default: 0xe
6887 18:10:50.781734 0, 0xFFFF, sum = 0
6888 18:10:50.781818 1, 0xFFFF, sum = 0
6889 18:10:50.784459 2, 0xFFFF, sum = 0
6890 18:10:50.784541 3, 0xFFFF, sum = 0
6891 18:10:50.788040 4, 0xFFFF, sum = 0
6892 18:10:50.788122 5, 0xFFFF, sum = 0
6893 18:10:50.791409 6, 0xFFFF, sum = 0
6894 18:10:50.791492 7, 0xFFFF, sum = 0
6895 18:10:50.794641 8, 0xFFFF, sum = 0
6896 18:10:50.794724 9, 0xFFFF, sum = 0
6897 18:10:50.797828 10, 0xFFFF, sum = 0
6898 18:10:50.797911 11, 0xFFFF, sum = 0
6899 18:10:50.801647 12, 0xFFFF, sum = 0
6900 18:10:50.801730 13, 0x0, sum = 1
6901 18:10:50.804482 14, 0x0, sum = 2
6902 18:10:50.804564 15, 0x0, sum = 3
6903 18:10:50.807905 16, 0x0, sum = 4
6904 18:10:50.807987 best_step = 14
6905 18:10:50.808053
6906 18:10:50.808114 ==
6907 18:10:50.811451 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 18:10:50.814358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 18:10:50.818039 ==
6910 18:10:50.818121 RX Vref Scan: 0
6911 18:10:50.818186
6912 18:10:50.821290 RX Vref 0 -> 0, step: 1
6913 18:10:50.821371
6914 18:10:50.824793 RX Delay -311 -> 252, step: 8
6915 18:10:50.827829 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6916 18:10:50.834802 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6917 18:10:50.837528 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6918 18:10:50.840837 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6919 18:10:50.844464 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6920 18:10:50.851451 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6921 18:10:50.854274 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6922 18:10:50.857687 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6923 18:10:50.861029 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6924 18:10:50.867525 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6925 18:10:50.871268 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6926 18:10:50.874053 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6927 18:10:50.877677 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6928 18:10:50.884294 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6929 18:10:50.887741 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6930 18:10:50.891295 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6931 18:10:50.891377 ==
6932 18:10:50.894192 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 18:10:50.901378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 18:10:50.901461 ==
6935 18:10:50.901528 DQS Delay:
6936 18:10:50.904187 DQS0 = 28, DQS1 = 32
6937 18:10:50.904287 DQM Delay:
6938 18:10:50.904385 DQM0 = 11, DQM1 = 11
6939 18:10:50.907386 DQ Delay:
6940 18:10:50.910929 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6941 18:10:50.911034 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
6942 18:10:50.914269 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6943 18:10:50.917423 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6944 18:10:50.917526
6945 18:10:50.920904
6946 18:10:50.927245 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb4c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 386 ps
6947 18:10:50.930630 CH1 RK1: MR19=C0C, MR18=BB4C
6948 18:10:50.937124 CH1_RK1: MR19=0xC0C, MR18=0xBB4C, DQSOSC=386, MR23=63, INC=396, DEC=264
6949 18:10:50.940860 [RxdqsGatingPostProcess] freq 400
6950 18:10:50.944347 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6951 18:10:50.947026 best DQS0 dly(2T, 0.5T) = (0, 10)
6952 18:10:50.950449 best DQS1 dly(2T, 0.5T) = (0, 10)
6953 18:10:50.953830 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6954 18:10:50.957502 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6955 18:10:50.960375 best DQS0 dly(2T, 0.5T) = (0, 10)
6956 18:10:50.963892 best DQS1 dly(2T, 0.5T) = (0, 10)
6957 18:10:50.967300 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6958 18:10:50.970646 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6959 18:10:50.973878 Pre-setting of DQS Precalculation
6960 18:10:50.977275 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6961 18:10:50.983848 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6962 18:10:50.994051 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6963 18:10:50.994133
6964 18:10:50.994198
6965 18:10:50.997299 [Calibration Summary] 800 Mbps
6966 18:10:50.997381 CH 0, Rank 0
6967 18:10:51.000254 SW Impedance : PASS
6968 18:10:51.000336 DUTY Scan : NO K
6969 18:10:51.003850 ZQ Calibration : PASS
6970 18:10:51.006895 Jitter Meter : NO K
6971 18:10:51.006977 CBT Training : PASS
6972 18:10:51.010474 Write leveling : PASS
6973 18:10:51.010555 RX DQS gating : PASS
6974 18:10:51.013938 RX DQ/DQS(RDDQC) : PASS
6975 18:10:51.017401 TX DQ/DQS : PASS
6976 18:10:51.017482 RX DATLAT : PASS
6977 18:10:51.020274 RX DQ/DQS(Engine): PASS
6978 18:10:51.023728 TX OE : NO K
6979 18:10:51.023810 All Pass.
6980 18:10:51.023875
6981 18:10:51.023935 CH 0, Rank 1
6982 18:10:51.027168 SW Impedance : PASS
6983 18:10:51.029977 DUTY Scan : NO K
6984 18:10:51.030058 ZQ Calibration : PASS
6985 18:10:51.033343 Jitter Meter : NO K
6986 18:10:51.036659 CBT Training : PASS
6987 18:10:51.036739 Write leveling : NO K
6988 18:10:51.040216 RX DQS gating : PASS
6989 18:10:51.043170 RX DQ/DQS(RDDQC) : PASS
6990 18:10:51.043251 TX DQ/DQS : PASS
6991 18:10:51.046942 RX DATLAT : PASS
6992 18:10:51.049930 RX DQ/DQS(Engine): PASS
6993 18:10:51.050012 TX OE : NO K
6994 18:10:51.053405 All Pass.
6995 18:10:51.053486
6996 18:10:51.053550 CH 1, Rank 0
6997 18:10:51.056771 SW Impedance : PASS
6998 18:10:51.056852 DUTY Scan : NO K
6999 18:10:51.060261 ZQ Calibration : PASS
7000 18:10:51.063214 Jitter Meter : NO K
7001 18:10:51.063296 CBT Training : PASS
7002 18:10:51.066748 Write leveling : PASS
7003 18:10:51.066830 RX DQS gating : PASS
7004 18:10:51.069924 RX DQ/DQS(RDDQC) : PASS
7005 18:10:51.073326 TX DQ/DQS : PASS
7006 18:10:51.073408 RX DATLAT : PASS
7007 18:10:51.076949 RX DQ/DQS(Engine): PASS
7008 18:10:51.079747 TX OE : NO K
7009 18:10:51.079828 All Pass.
7010 18:10:51.079894
7011 18:10:51.079955 CH 1, Rank 1
7012 18:10:51.083308 SW Impedance : PASS
7013 18:10:51.086619 DUTY Scan : NO K
7014 18:10:51.086699 ZQ Calibration : PASS
7015 18:10:51.089825 Jitter Meter : NO K
7016 18:10:51.093322 CBT Training : PASS
7017 18:10:51.093403 Write leveling : NO K
7018 18:10:51.096468 RX DQS gating : PASS
7019 18:10:51.099738 RX DQ/DQS(RDDQC) : PASS
7020 18:10:51.099819 TX DQ/DQS : PASS
7021 18:10:51.103146 RX DATLAT : PASS
7022 18:10:51.106541 RX DQ/DQS(Engine): PASS
7023 18:10:51.106622 TX OE : NO K
7024 18:10:51.110122 All Pass.
7025 18:10:51.110203
7026 18:10:51.110267 DramC Write-DBI off
7027 18:10:51.113243 PER_BANK_REFRESH: Hybrid Mode
7028 18:10:51.113324 TX_TRACKING: ON
7029 18:10:51.123025 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7030 18:10:51.126404 [FAST_K] Save calibration result to emmc
7031 18:10:51.129259 dramc_set_vcore_voltage set vcore to 725000
7032 18:10:51.132682 Read voltage for 1600, 0
7033 18:10:51.132763 Vio18 = 0
7034 18:10:51.136078 Vcore = 725000
7035 18:10:51.136159 Vdram = 0
7036 18:10:51.136244 Vddq = 0
7037 18:10:51.139602 Vmddr = 0
7038 18:10:51.142954 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7039 18:10:51.149503 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7040 18:10:51.149585 MEM_TYPE=3, freq_sel=13
7041 18:10:51.152524 sv_algorithm_assistance_LP4_3733
7042 18:10:51.159617 ============ PULL DRAM RESETB DOWN ============
7043 18:10:51.163110 ========== PULL DRAM RESETB DOWN end =========
7044 18:10:51.165853 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7045 18:10:51.169228 ===================================
7046 18:10:51.172740 LPDDR4 DRAM CONFIGURATION
7047 18:10:51.175607 ===================================
7048 18:10:51.175688 EX_ROW_EN[0] = 0x0
7049 18:10:51.179268 EX_ROW_EN[1] = 0x0
7050 18:10:51.182885 LP4Y_EN = 0x0
7051 18:10:51.182966 WORK_FSP = 0x1
7052 18:10:51.185747 WL = 0x5
7053 18:10:51.185828 RL = 0x5
7054 18:10:51.189408 BL = 0x2
7055 18:10:51.189489 RPST = 0x0
7056 18:10:51.192224 RD_PRE = 0x0
7057 18:10:51.192323 WR_PRE = 0x1
7058 18:10:51.195704 WR_PST = 0x1
7059 18:10:51.195785 DBI_WR = 0x0
7060 18:10:51.199042 DBI_RD = 0x0
7061 18:10:51.199123 OTF = 0x1
7062 18:10:51.202523 ===================================
7063 18:10:51.205726 ===================================
7064 18:10:51.208923 ANA top config
7065 18:10:51.212324 ===================================
7066 18:10:51.212427 DLL_ASYNC_EN = 0
7067 18:10:51.215664 ALL_SLAVE_EN = 0
7068 18:10:51.219239 NEW_RANK_MODE = 1
7069 18:10:51.222766 DLL_IDLE_MODE = 1
7070 18:10:51.226172 LP45_APHY_COMB_EN = 1
7071 18:10:51.226253 TX_ODT_DIS = 0
7072 18:10:51.229020 NEW_8X_MODE = 1
7073 18:10:51.232527 ===================================
7074 18:10:51.235997 ===================================
7075 18:10:51.238882 data_rate = 3200
7076 18:10:51.242442 CKR = 1
7077 18:10:51.245362 DQ_P2S_RATIO = 8
7078 18:10:51.248850 ===================================
7079 18:10:51.248932 CA_P2S_RATIO = 8
7080 18:10:51.252314 DQ_CA_OPEN = 0
7081 18:10:51.255481 DQ_SEMI_OPEN = 0
7082 18:10:51.258812 CA_SEMI_OPEN = 0
7083 18:10:51.262230 CA_FULL_RATE = 0
7084 18:10:51.265801 DQ_CKDIV4_EN = 0
7085 18:10:51.265883 CA_CKDIV4_EN = 0
7086 18:10:51.268775 CA_PREDIV_EN = 0
7087 18:10:51.272327 PH8_DLY = 12
7088 18:10:51.275263 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7089 18:10:51.278842 DQ_AAMCK_DIV = 4
7090 18:10:51.281724 CA_AAMCK_DIV = 4
7091 18:10:51.281806 CA_ADMCK_DIV = 4
7092 18:10:51.285370 DQ_TRACK_CA_EN = 0
7093 18:10:51.288940 CA_PICK = 1600
7094 18:10:51.291881 CA_MCKIO = 1600
7095 18:10:51.295480 MCKIO_SEMI = 0
7096 18:10:51.299110 PLL_FREQ = 3068
7097 18:10:51.301970 DQ_UI_PI_RATIO = 32
7098 18:10:51.305515 CA_UI_PI_RATIO = 0
7099 18:10:51.309160 ===================================
7100 18:10:51.311883 ===================================
7101 18:10:51.311964 memory_type:LPDDR4
7102 18:10:51.315432 GP_NUM : 10
7103 18:10:51.315514 SRAM_EN : 1
7104 18:10:51.318647 MD32_EN : 0
7105 18:10:51.321721 ===================================
7106 18:10:51.325026 [ANA_INIT] >>>>>>>>>>>>>>
7107 18:10:51.328478 <<<<<< [CONFIGURE PHASE]: ANA_TX
7108 18:10:51.331682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7109 18:10:51.334882 ===================================
7110 18:10:51.338279 data_rate = 3200,PCW = 0X7600
7111 18:10:51.341687 ===================================
7112 18:10:51.345336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7113 18:10:51.348175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 18:10:51.355313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7115 18:10:51.358199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7116 18:10:51.361851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7117 18:10:51.365413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7118 18:10:51.368703 [ANA_INIT] flow start
7119 18:10:51.371805 [ANA_INIT] PLL >>>>>>>>
7120 18:10:51.371886 [ANA_INIT] PLL <<<<<<<<
7121 18:10:51.374922 [ANA_INIT] MIDPI >>>>>>>>
7122 18:10:51.378310 [ANA_INIT] MIDPI <<<<<<<<
7123 18:10:51.378392 [ANA_INIT] DLL >>>>>>>>
7124 18:10:51.381859 [ANA_INIT] DLL <<<<<<<<
7125 18:10:51.385413 [ANA_INIT] flow end
7126 18:10:51.388577 ============ LP4 DIFF to SE enter ============
7127 18:10:51.392295 ============ LP4 DIFF to SE exit ============
7128 18:10:51.395110 [ANA_INIT] <<<<<<<<<<<<<
7129 18:10:51.398786 [Flow] Enable top DCM control >>>>>
7130 18:10:51.401669 [Flow] Enable top DCM control <<<<<
7131 18:10:51.405416 Enable DLL master slave shuffle
7132 18:10:51.408238 ==============================================================
7133 18:10:51.411631 Gating Mode config
7134 18:10:51.418001 ==============================================================
7135 18:10:51.418083 Config description:
7136 18:10:51.427796 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7137 18:10:51.434809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7138 18:10:51.438149 SELPH_MODE 0: By rank 1: By Phase
7139 18:10:51.444683 ==============================================================
7140 18:10:51.447708 GAT_TRACK_EN = 1
7141 18:10:51.451498 RX_GATING_MODE = 2
7142 18:10:51.454397 RX_GATING_TRACK_MODE = 2
7143 18:10:51.458092 SELPH_MODE = 1
7144 18:10:51.461635 PICG_EARLY_EN = 1
7145 18:10:51.464632 VALID_LAT_VALUE = 1
7146 18:10:51.468235 ==============================================================
7147 18:10:51.471163 Enter into Gating configuration >>>>
7148 18:10:51.474543 Exit from Gating configuration <<<<
7149 18:10:51.477887 Enter into DVFS_PRE_config >>>>>
7150 18:10:51.491206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7151 18:10:51.491318 Exit from DVFS_PRE_config <<<<<
7152 18:10:51.494751 Enter into PICG configuration >>>>
7153 18:10:51.497765 Exit from PICG configuration <<<<
7154 18:10:51.501312 [RX_INPUT] configuration >>>>>
7155 18:10:51.504238 [RX_INPUT] configuration <<<<<
7156 18:10:51.510842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7157 18:10:51.514434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7158 18:10:51.520838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7159 18:10:51.527931 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7160 18:10:51.534066 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 18:10:51.540642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 18:10:51.544214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7163 18:10:51.547877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7164 18:10:51.550760 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7165 18:10:51.557612 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7166 18:10:51.560848 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7167 18:10:51.564036 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 18:10:51.567470 ===================================
7169 18:10:51.570586 LPDDR4 DRAM CONFIGURATION
7170 18:10:51.574040 ===================================
7171 18:10:51.577530 EX_ROW_EN[0] = 0x0
7172 18:10:51.577677 EX_ROW_EN[1] = 0x0
7173 18:10:51.580903 LP4Y_EN = 0x0
7174 18:10:51.581086 WORK_FSP = 0x1
7175 18:10:51.583849 WL = 0x5
7176 18:10:51.583954 RL = 0x5
7177 18:10:51.587309 BL = 0x2
7178 18:10:51.587410 RPST = 0x0
7179 18:10:51.590960 RD_PRE = 0x0
7180 18:10:51.591067 WR_PRE = 0x1
7181 18:10:51.594431 WR_PST = 0x1
7182 18:10:51.594532 DBI_WR = 0x0
7183 18:10:51.597163 DBI_RD = 0x0
7184 18:10:51.597294 OTF = 0x1
7185 18:10:51.600943 ===================================
7186 18:10:51.603987 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7187 18:10:51.611340 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7188 18:10:51.614081 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 18:10:51.617725 ===================================
7190 18:10:51.620672 LPDDR4 DRAM CONFIGURATION
7191 18:10:51.623650 ===================================
7192 18:10:51.623750 EX_ROW_EN[0] = 0x10
7193 18:10:51.626876 EX_ROW_EN[1] = 0x0
7194 18:10:51.630746 LP4Y_EN = 0x0
7195 18:10:51.630845 WORK_FSP = 0x1
7196 18:10:51.633546 WL = 0x5
7197 18:10:51.633643 RL = 0x5
7198 18:10:51.637116 BL = 0x2
7199 18:10:51.637213 RPST = 0x0
7200 18:10:51.639948 RD_PRE = 0x0
7201 18:10:51.640037 WR_PRE = 0x1
7202 18:10:51.643492 WR_PST = 0x1
7203 18:10:51.643606 DBI_WR = 0x0
7204 18:10:51.647192 DBI_RD = 0x0
7205 18:10:51.647291 OTF = 0x1
7206 18:10:51.650089 ===================================
7207 18:10:51.656623 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7208 18:10:51.656704 ==
7209 18:10:51.660337 Dram Type= 6, Freq= 0, CH_0, rank 0
7210 18:10:51.663277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7211 18:10:51.666868 ==
7212 18:10:51.666975 [Duty_Offset_Calibration]
7213 18:10:51.670163 B0:2 B1:1 CA:1
7214 18:10:51.670262
7215 18:10:51.673679 [DutyScan_Calibration_Flow] k_type=0
7216 18:10:51.682732
7217 18:10:51.682807 ==CLK 0==
7218 18:10:51.686014 Final CLK duty delay cell = 0
7219 18:10:51.689161 [0] MAX Duty = 5156%(X100), DQS PI = 22
7220 18:10:51.692191 [0] MIN Duty = 4907%(X100), DQS PI = 0
7221 18:10:51.692292 [0] AVG Duty = 5031%(X100)
7222 18:10:51.695525
7223 18:10:51.698680 CH0 CLK Duty spec in!! Max-Min= 249%
7224 18:10:51.702372 [DutyScan_Calibration_Flow] ====Done====
7225 18:10:51.702468
7226 18:10:51.705577 [DutyScan_Calibration_Flow] k_type=1
7227 18:10:51.721887
7228 18:10:51.721977 ==DQS 0 ==
7229 18:10:51.724686 Final DQS duty delay cell = -4
7230 18:10:51.728255 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7231 18:10:51.731787 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7232 18:10:51.734627 [-4] AVG Duty = 4891%(X100)
7233 18:10:51.734723
7234 18:10:51.734820 ==DQS 1 ==
7235 18:10:51.738276 Final DQS duty delay cell = 0
7236 18:10:51.741307 [0] MAX Duty = 5187%(X100), DQS PI = 20
7237 18:10:51.744763 [0] MIN Duty = 5031%(X100), DQS PI = 52
7238 18:10:51.748087 [0] AVG Duty = 5109%(X100)
7239 18:10:51.748162
7240 18:10:51.751725 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7241 18:10:51.751806
7242 18:10:51.754650 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7243 18:10:51.758337 [DutyScan_Calibration_Flow] ====Done====
7244 18:10:51.758419
7245 18:10:51.761201 [DutyScan_Calibration_Flow] k_type=3
7246 18:10:51.779315
7247 18:10:51.779398 ==DQM 0 ==
7248 18:10:51.782055 Final DQM duty delay cell = 0
7249 18:10:51.785699 [0] MAX Duty = 5187%(X100), DQS PI = 32
7250 18:10:51.789080 [0] MIN Duty = 4907%(X100), DQS PI = 0
7251 18:10:51.792512 [0] AVG Duty = 5047%(X100)
7252 18:10:51.792594
7253 18:10:51.792658 ==DQM 1 ==
7254 18:10:51.795278 Final DQM duty delay cell = 0
7255 18:10:51.798803 [0] MAX Duty = 5187%(X100), DQS PI = 60
7256 18:10:51.802296 [0] MIN Duty = 5031%(X100), DQS PI = 48
7257 18:10:51.805608 [0] AVG Duty = 5109%(X100)
7258 18:10:51.805708
7259 18:10:51.809316 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7260 18:10:51.809411
7261 18:10:51.811706 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7262 18:10:51.815406 [DutyScan_Calibration_Flow] ====Done====
7263 18:10:51.815506
7264 18:10:51.818372 [DutyScan_Calibration_Flow] k_type=2
7265 18:10:51.836134
7266 18:10:51.836237 ==DQ 0 ==
7267 18:10:51.839371 Final DQ duty delay cell = 0
7268 18:10:51.842550 [0] MAX Duty = 5062%(X100), DQS PI = 24
7269 18:10:51.846223 [0] MIN Duty = 4907%(X100), DQS PI = 0
7270 18:10:51.846300 [0] AVG Duty = 4984%(X100)
7271 18:10:51.846364
7272 18:10:51.849084 ==DQ 1 ==
7273 18:10:51.852583 Final DQ duty delay cell = 0
7274 18:10:51.856089 [0] MAX Duty = 5094%(X100), DQS PI = 4
7275 18:10:51.859587 [0] MIN Duty = 4907%(X100), DQS PI = 34
7276 18:10:51.859697 [0] AVG Duty = 5000%(X100)
7277 18:10:51.859789
7278 18:10:51.862352 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7279 18:10:51.865990
7280 18:10:51.868993 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7281 18:10:51.872786 [DutyScan_Calibration_Flow] ====Done====
7282 18:10:51.872887 ==
7283 18:10:51.876244 Dram Type= 6, Freq= 0, CH_1, rank 0
7284 18:10:51.879131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7285 18:10:51.879229 ==
7286 18:10:51.882735 [Duty_Offset_Calibration]
7287 18:10:51.882839 B0:1 B1:0 CA:0
7288 18:10:51.882933
7289 18:10:51.885571 [DutyScan_Calibration_Flow] k_type=0
7290 18:10:51.895045
7291 18:10:51.895145 ==CLK 0==
7292 18:10:51.898346 Final CLK duty delay cell = -4
7293 18:10:51.901869 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7294 18:10:51.905526 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7295 18:10:51.908588 [-4] AVG Duty = 4922%(X100)
7296 18:10:51.908691
7297 18:10:51.912085 CH1 CLK Duty spec in!! Max-Min= 156%
7298 18:10:51.914904 [DutyScan_Calibration_Flow] ====Done====
7299 18:10:51.915003
7300 18:10:51.918456 [DutyScan_Calibration_Flow] k_type=1
7301 18:10:51.935706
7302 18:10:51.935790 ==DQS 0 ==
7303 18:10:51.938794 Final DQS duty delay cell = 0
7304 18:10:51.942166 [0] MAX Duty = 5094%(X100), DQS PI = 34
7305 18:10:51.945290 [0] MIN Duty = 4844%(X100), DQS PI = 0
7306 18:10:51.948434 [0] AVG Duty = 4969%(X100)
7307 18:10:51.948524
7308 18:10:51.948587 ==DQS 1 ==
7309 18:10:51.952336 Final DQS duty delay cell = 0
7310 18:10:51.955643 [0] MAX Duty = 5249%(X100), DQS PI = 16
7311 18:10:51.958838 [0] MIN Duty = 4938%(X100), DQS PI = 8
7312 18:10:51.958938 [0] AVG Duty = 5093%(X100)
7313 18:10:51.961922
7314 18:10:51.965130 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7315 18:10:51.965209
7316 18:10:51.968622 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7317 18:10:51.971954 [DutyScan_Calibration_Flow] ====Done====
7318 18:10:51.972056
7319 18:10:51.975480 [DutyScan_Calibration_Flow] k_type=3
7320 18:10:51.992555
7321 18:10:51.992630 ==DQM 0 ==
7322 18:10:51.995505 Final DQM duty delay cell = 0
7323 18:10:51.999171 [0] MAX Duty = 5218%(X100), DQS PI = 20
7324 18:10:52.002002 [0] MIN Duty = 4969%(X100), DQS PI = 48
7325 18:10:52.005157 [0] AVG Duty = 5093%(X100)
7326 18:10:52.005228
7327 18:10:52.005289 ==DQM 1 ==
7328 18:10:52.008843 Final DQM duty delay cell = 0
7329 18:10:52.011597 [0] MAX Duty = 5093%(X100), DQS PI = 16
7330 18:10:52.015205 [0] MIN Duty = 4876%(X100), DQS PI = 52
7331 18:10:52.018860 [0] AVG Duty = 4984%(X100)
7332 18:10:52.018958
7333 18:10:52.021682 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7334 18:10:52.021780
7335 18:10:52.025190 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7336 18:10:52.028814 [DutyScan_Calibration_Flow] ====Done====
7337 18:10:52.028903
7338 18:10:52.031754 [DutyScan_Calibration_Flow] k_type=2
7339 18:10:52.047953
7340 18:10:52.048045 ==DQ 0 ==
7341 18:10:52.051453 Final DQ duty delay cell = -4
7342 18:10:52.054925 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7343 18:10:52.058375 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7344 18:10:52.061308 [-4] AVG Duty = 4937%(X100)
7345 18:10:52.061390
7346 18:10:52.061486 ==DQ 1 ==
7347 18:10:52.064944 Final DQ duty delay cell = 0
7348 18:10:52.068284 [0] MAX Duty = 5124%(X100), DQS PI = 18
7349 18:10:52.071618 [0] MIN Duty = 4938%(X100), DQS PI = 10
7350 18:10:52.075166 [0] AVG Duty = 5031%(X100)
7351 18:10:52.075323
7352 18:10:52.078219 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7353 18:10:52.078343
7354 18:10:52.081383 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7355 18:10:52.085201 [DutyScan_Calibration_Flow] ====Done====
7356 18:10:52.088287 nWR fixed to 30
7357 18:10:52.088480 [ModeRegInit_LP4] CH0 RK0
7358 18:10:52.091536 [ModeRegInit_LP4] CH0 RK1
7359 18:10:52.095245 [ModeRegInit_LP4] CH1 RK0
7360 18:10:52.098309 [ModeRegInit_LP4] CH1 RK1
7361 18:10:52.098413 match AC timing 5
7362 18:10:52.104675 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7363 18:10:52.108336 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7364 18:10:52.111055 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7365 18:10:52.117870 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7366 18:10:52.121554 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7367 18:10:52.121633 [MiockJmeterHQA]
7368 18:10:52.121697
7369 18:10:52.124612 [DramcMiockJmeter] u1RxGatingPI = 0
7370 18:10:52.128118 0 : 4363, 4137
7371 18:10:52.128218 4 : 4252, 4027
7372 18:10:52.130948 8 : 4366, 4139
7373 18:10:52.131050 12 : 4253, 4027
7374 18:10:52.134397 16 : 4365, 4140
7375 18:10:52.134496 20 : 4252, 4027
7376 18:10:52.134595 24 : 4360, 4137
7377 18:10:52.138296 28 : 4252, 4027
7378 18:10:52.138405 32 : 4363, 4138
7379 18:10:52.141191 36 : 4252, 4027
7380 18:10:52.141261 40 : 4253, 4027
7381 18:10:52.144191 44 : 4255, 4029
7382 18:10:52.144291 48 : 4250, 4026
7383 18:10:52.147842 52 : 4253, 4026
7384 18:10:52.147945 56 : 4250, 4027
7385 18:10:52.148024 60 : 4252, 4029
7386 18:10:52.151050 64 : 4255, 4029
7387 18:10:52.151147 68 : 4363, 4140
7388 18:10:52.154432 72 : 4250, 4027
7389 18:10:52.154505 76 : 4252, 4029
7390 18:10:52.157721 80 : 4252, 4026
7391 18:10:52.157822 84 : 4363, 4138
7392 18:10:52.157913 88 : 4250, 177
7393 18:10:52.161093 92 : 4250, 0
7394 18:10:52.161175 96 : 4252, 0
7395 18:10:52.164419 100 : 4361, 0
7396 18:10:52.164527 104 : 4250, 0
7397 18:10:52.164631 108 : 4250, 0
7398 18:10:52.167253 112 : 4250, 0
7399 18:10:52.167334 116 : 4250, 0
7400 18:10:52.170890 120 : 4252, 0
7401 18:10:52.170993 124 : 4252, 0
7402 18:10:52.171085 128 : 4250, 0
7403 18:10:52.174298 132 : 4253, 0
7404 18:10:52.174391 136 : 4250, 0
7405 18:10:52.174460 140 : 4250, 0
7406 18:10:52.177958 144 : 4252, 0
7407 18:10:52.178040 148 : 4360, 0
7408 18:10:52.180895 152 : 4250, 0
7409 18:10:52.181004 156 : 4250, 0
7410 18:10:52.181099 160 : 4250, 0
7411 18:10:52.184357 164 : 4250, 0
7412 18:10:52.184444 168 : 4250, 0
7413 18:10:52.187173 172 : 4250, 0
7414 18:10:52.187245 176 : 4250, 0
7415 18:10:52.187306 180 : 4250, 0
7416 18:10:52.190630 184 : 4250, 0
7417 18:10:52.190727 188 : 4250, 0
7418 18:10:52.193912 192 : 4361, 0
7419 18:10:52.194016 196 : 4360, 0
7420 18:10:52.194107 200 : 4250, 0
7421 18:10:52.197721 204 : 4361, 1270
7422 18:10:52.197821 208 : 4361, 4112
7423 18:10:52.200680 212 : 4247, 4024
7424 18:10:52.200756 216 : 4363, 4140
7425 18:10:52.204076 220 : 4252, 4029
7426 18:10:52.204173 224 : 4250, 4027
7427 18:10:52.207235 228 : 4363, 4138
7428 18:10:52.207307 232 : 4250, 4027
7429 18:10:52.210599 236 : 4363, 4137
7430 18:10:52.210674 240 : 4253, 4029
7431 18:10:52.214228 244 : 4250, 4027
7432 18:10:52.214333 248 : 4250, 4027
7433 18:10:52.214425 252 : 4252, 4030
7434 18:10:52.217071 256 : 4250, 4026
7435 18:10:52.217143 260 : 4363, 4138
7436 18:10:52.220690 264 : 4250, 4027
7437 18:10:52.220766 268 : 4250, 4027
7438 18:10:52.223417 272 : 4250, 4026
7439 18:10:52.223516 276 : 4250, 4027
7440 18:10:52.227150 280 : 4360, 4138
7441 18:10:52.227221 284 : 4250, 4027
7442 18:10:52.230164 288 : 4360, 4137
7443 18:10:52.230246 292 : 4250, 4026
7444 18:10:52.233661 296 : 4250, 4027
7445 18:10:52.233765 300 : 4249, 4027
7446 18:10:52.237372 304 : 4250, 4027
7447 18:10:52.237454 308 : 4255, 3993
7448 18:10:52.237519 312 : 4361, 2276
7449 18:10:52.240111 316 : 4250, 12
7450 18:10:52.240193
7451 18:10:52.243916 MIOCK jitter meter ch=0
7452 18:10:52.243997
7453 18:10:52.246636 1T = (316-88) = 228 dly cells
7454 18:10:52.250282 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7455 18:10:52.250392 ==
7456 18:10:52.253983 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 18:10:52.256793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7458 18:10:52.260267 ==
7459 18:10:52.263582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7460 18:10:52.266941 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7461 18:10:52.273726 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7462 18:10:52.280008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7463 18:10:52.287413 [CA 0] Center 43 (12~74) winsize 63
7464 18:10:52.290994 [CA 1] Center 43 (13~74) winsize 62
7465 18:10:52.293994 [CA 2] Center 38 (9~68) winsize 60
7466 18:10:52.297655 [CA 3] Center 38 (8~68) winsize 61
7467 18:10:52.300541 [CA 4] Center 37 (7~67) winsize 61
7468 18:10:52.304224 [CA 5] Center 36 (7~65) winsize 59
7469 18:10:52.304346
7470 18:10:52.307787 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7471 18:10:52.307909
7472 18:10:52.311166 [CATrainingPosCal] consider 1 rank data
7473 18:10:52.314706 u2DelayCellTimex100 = 285/100 ps
7474 18:10:52.317880 CA0 delay=43 (12~74),Diff = 7 PI (23 cell)
7475 18:10:52.324261 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7476 18:10:52.327653 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7477 18:10:52.330959 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7478 18:10:52.334008 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7479 18:10:52.337342 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7480 18:10:52.337766
7481 18:10:52.340932 CA PerBit enable=1, Macro0, CA PI delay=36
7482 18:10:52.341455
7483 18:10:52.343866 [CBTSetCACLKResult] CA Dly = 36
7484 18:10:52.347575 CS Dly: 9 (0~40)
7485 18:10:52.350496 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7486 18:10:52.354226 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7487 18:10:52.354646 ==
7488 18:10:52.357767 Dram Type= 6, Freq= 0, CH_0, rank 1
7489 18:10:52.360595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7490 18:10:52.364271 ==
7491 18:10:52.367834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7492 18:10:52.370640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7493 18:10:52.377830 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7494 18:10:52.380463 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7495 18:10:52.391683 [CA 0] Center 42 (12~73) winsize 62
7496 18:10:52.394504 [CA 1] Center 42 (12~73) winsize 62
7497 18:10:52.398138 [CA 2] Center 38 (8~68) winsize 61
7498 18:10:52.400899 [CA 3] Center 38 (8~68) winsize 61
7499 18:10:52.404502 [CA 4] Center 35 (6~65) winsize 60
7500 18:10:52.408257 [CA 5] Center 35 (5~65) winsize 61
7501 18:10:52.408763
7502 18:10:52.411150 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7503 18:10:52.411717
7504 18:10:52.414515 [CATrainingPosCal] consider 2 rank data
7505 18:10:52.417922 u2DelayCellTimex100 = 285/100 ps
7506 18:10:52.421217 CA0 delay=42 (12~73),Diff = 6 PI (20 cell)
7507 18:10:52.427986 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7508 18:10:52.430780 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7509 18:10:52.434440 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7510 18:10:52.437945 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7511 18:10:52.441463 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7512 18:10:52.441880
7513 18:10:52.443968 CA PerBit enable=1, Macro0, CA PI delay=36
7514 18:10:52.444429
7515 18:10:52.447891 [CBTSetCACLKResult] CA Dly = 36
7516 18:10:52.451083 CS Dly: 10 (0~42)
7517 18:10:52.454174 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7518 18:10:52.457271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7519 18:10:52.457576
7520 18:10:52.460778 ----->DramcWriteLeveling(PI) begin...
7521 18:10:52.461010 ==
7522 18:10:52.463767 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 18:10:52.467712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 18:10:52.470554 ==
7525 18:10:52.470785 Write leveling (Byte 0): 35 => 35
7526 18:10:52.474212 Write leveling (Byte 1): 28 => 28
7527 18:10:52.477077 DramcWriteLeveling(PI) end<-----
7528 18:10:52.477206
7529 18:10:52.477309 ==
7530 18:10:52.480740 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 18:10:52.487544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 18:10:52.487771 ==
7533 18:10:52.487893 [Gating] SW mode calibration
7534 18:10:52.497284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7535 18:10:52.500640 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7536 18:10:52.507403 1 4 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7537 18:10:52.510435 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 18:10:52.514341 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7539 18:10:52.516821 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7540 18:10:52.523490 1 4 16 | B1->B0 | 2424 3737 | 0 0 | (0 0) (1 1)
7541 18:10:52.527014 1 4 20 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
7542 18:10:52.530626 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7543 18:10:52.538082 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7544 18:10:52.540974 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7545 18:10:52.544541 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7546 18:10:52.551430 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7547 18:10:52.553893 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7548 18:10:52.557390 1 5 16 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
7549 18:10:52.564526 1 5 20 | B1->B0 | 2929 2525 | 0 0 | (0 1) (0 0)
7550 18:10:52.567616 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7551 18:10:52.571192 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7552 18:10:52.577755 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7553 18:10:52.580821 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 18:10:52.584008 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7555 18:10:52.591122 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (1 1)
7556 18:10:52.594156 1 6 16 | B1->B0 | 2c2c 3636 | 1 1 | (0 0) (0 0)
7557 18:10:52.597457 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7558 18:10:52.603907 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 18:10:52.606771 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 18:10:52.610272 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 18:10:52.616903 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 18:10:52.620306 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7563 18:10:52.623554 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 18:10:52.630098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7565 18:10:52.633834 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7566 18:10:52.637170 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 18:10:52.643714 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 18:10:52.646578 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 18:10:52.650273 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 18:10:52.656906 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 18:10:52.660540 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 18:10:52.663572 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 18:10:52.666853 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 18:10:52.673729 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 18:10:52.676505 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 18:10:52.679911 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 18:10:52.686722 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 18:10:52.690245 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7579 18:10:52.693806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 18:10:52.700424 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7581 18:10:52.703870 Total UI for P1: 0, mck2ui 16
7582 18:10:52.706357 best dqsien dly found for B0: ( 1, 9, 10)
7583 18:10:52.710126 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7584 18:10:52.713481 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 18:10:52.716728 Total UI for P1: 0, mck2ui 16
7586 18:10:52.720095 best dqsien dly found for B1: ( 1, 9, 20)
7587 18:10:52.723215 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7588 18:10:52.726911 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7589 18:10:52.727325
7590 18:10:52.733863 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7591 18:10:52.737108 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7592 18:10:52.740720 [Gating] SW calibration Done
7593 18:10:52.741360 ==
7594 18:10:52.743526 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 18:10:52.746991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 18:10:52.747556 ==
7597 18:10:52.747926 RX Vref Scan: 0
7598 18:10:52.748313
7599 18:10:52.749932 RX Vref 0 -> 0, step: 1
7600 18:10:52.750390
7601 18:10:52.753514 RX Delay 0 -> 252, step: 8
7602 18:10:52.757083 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7603 18:10:52.760333 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7604 18:10:52.766885 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7605 18:10:52.770113 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7606 18:10:52.773570 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7607 18:10:52.776422 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7608 18:10:52.779693 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7609 18:10:52.783224 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7610 18:10:52.789735 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7611 18:10:52.793323 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7612 18:10:52.796603 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7613 18:10:52.800282 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7614 18:10:52.802891 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7615 18:10:52.810169 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7616 18:10:52.813537 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7617 18:10:52.816333 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7618 18:10:52.816827 ==
7619 18:10:52.820146 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 18:10:52.823229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 18:10:52.826467 ==
7622 18:10:52.826929 DQS Delay:
7623 18:10:52.827296 DQS0 = 0, DQS1 = 0
7624 18:10:52.829566 DQM Delay:
7625 18:10:52.830026 DQM0 = 137, DQM1 = 130
7626 18:10:52.833012 DQ Delay:
7627 18:10:52.836729 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7628 18:10:52.839456 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7629 18:10:52.842923 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7630 18:10:52.846869 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7631 18:10:52.847425
7632 18:10:52.847793
7633 18:10:52.848137 ==
7634 18:10:52.849742 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 18:10:52.853271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 18:10:52.853829 ==
7637 18:10:52.854198
7638 18:10:52.854540
7639 18:10:52.856499 TX Vref Scan disable
7640 18:10:52.859853 == TX Byte 0 ==
7641 18:10:52.862958 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7642 18:10:52.866369 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7643 18:10:52.869553 == TX Byte 1 ==
7644 18:10:52.872811 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7645 18:10:52.876139 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7646 18:10:52.876588 ==
7647 18:10:52.879681 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 18:10:52.885735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 18:10:52.886240 ==
7650 18:10:52.897986
7651 18:10:52.901579 TX Vref early break, caculate TX vref
7652 18:10:52.905229 TX Vref=16, minBit 0, minWin=23, winSum=378
7653 18:10:52.907947 TX Vref=18, minBit 0, minWin=24, winSum=395
7654 18:10:52.911476 TX Vref=20, minBit 7, minWin=23, winSum=398
7655 18:10:52.914811 TX Vref=22, minBit 0, minWin=25, winSum=410
7656 18:10:52.918228 TX Vref=24, minBit 7, minWin=24, winSum=414
7657 18:10:52.924449 TX Vref=26, minBit 0, minWin=25, winSum=425
7658 18:10:52.928180 TX Vref=28, minBit 2, minWin=24, winSum=424
7659 18:10:52.931555 TX Vref=30, minBit 6, minWin=24, winSum=412
7660 18:10:52.934741 TX Vref=32, minBit 6, minWin=23, winSum=405
7661 18:10:52.938101 TX Vref=34, minBit 6, minWin=23, winSum=391
7662 18:10:52.944541 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
7663 18:10:52.944957
7664 18:10:52.948227 Final TX Range 0 Vref 26
7665 18:10:52.948695
7666 18:10:52.949027 ==
7667 18:10:52.951367 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 18:10:52.955179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 18:10:52.955695 ==
7670 18:10:52.956030
7671 18:10:52.956377
7672 18:10:52.957798 TX Vref Scan disable
7673 18:10:52.964489 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7674 18:10:52.965002 == TX Byte 0 ==
7675 18:10:52.968109 u2DelayCellOfst[0]=10 cells (3 PI)
7676 18:10:52.971593 u2DelayCellOfst[1]=13 cells (4 PI)
7677 18:10:52.974727 u2DelayCellOfst[2]=10 cells (3 PI)
7678 18:10:52.978052 u2DelayCellOfst[3]=6 cells (2 PI)
7679 18:10:52.981098 u2DelayCellOfst[4]=6 cells (2 PI)
7680 18:10:52.984439 u2DelayCellOfst[5]=0 cells (0 PI)
7681 18:10:52.987756 u2DelayCellOfst[6]=17 cells (5 PI)
7682 18:10:52.990794 u2DelayCellOfst[7]=17 cells (5 PI)
7683 18:10:52.994451 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7684 18:10:52.997623 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7685 18:10:53.001198 == TX Byte 1 ==
7686 18:10:53.001678 u2DelayCellOfst[8]=0 cells (0 PI)
7687 18:10:53.003967 u2DelayCellOfst[9]=0 cells (0 PI)
7688 18:10:53.007485 u2DelayCellOfst[10]=10 cells (3 PI)
7689 18:10:53.010638 u2DelayCellOfst[11]=6 cells (2 PI)
7690 18:10:53.014079 u2DelayCellOfst[12]=10 cells (3 PI)
7691 18:10:53.017696 u2DelayCellOfst[13]=13 cells (4 PI)
7692 18:10:53.020714 u2DelayCellOfst[14]=13 cells (4 PI)
7693 18:10:53.024742 u2DelayCellOfst[15]=10 cells (3 PI)
7694 18:10:53.027607 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7695 18:10:53.034468 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7696 18:10:53.034986 DramC Write-DBI on
7697 18:10:53.035322 ==
7698 18:10:53.037324 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 18:10:53.041225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 18:10:53.044441 ==
7701 18:10:53.044859
7702 18:10:53.045192
7703 18:10:53.045502 TX Vref Scan disable
7704 18:10:53.048085 == TX Byte 0 ==
7705 18:10:53.050897 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7706 18:10:53.054706 == TX Byte 1 ==
7707 18:10:53.057509 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7708 18:10:53.057928 DramC Write-DBI off
7709 18:10:53.061280
7710 18:10:53.061789 [DATLAT]
7711 18:10:53.062126 Freq=1600, CH0 RK0
7712 18:10:53.062437
7713 18:10:53.064315 DATLAT Default: 0xf
7714 18:10:53.064871 0, 0xFFFF, sum = 0
7715 18:10:53.067912 1, 0xFFFF, sum = 0
7716 18:10:53.068499 2, 0xFFFF, sum = 0
7717 18:10:53.071485 3, 0xFFFF, sum = 0
7718 18:10:53.074157 4, 0xFFFF, sum = 0
7719 18:10:53.074586 5, 0xFFFF, sum = 0
7720 18:10:53.077784 6, 0xFFFF, sum = 0
7721 18:10:53.078263 7, 0xFFFF, sum = 0
7722 18:10:53.080660 8, 0xFFFF, sum = 0
7723 18:10:53.081081 9, 0xFFFF, sum = 0
7724 18:10:53.084442 10, 0xFFFF, sum = 0
7725 18:10:53.084962 11, 0xFFFF, sum = 0
7726 18:10:53.087804 12, 0xFFFF, sum = 0
7727 18:10:53.088325 13, 0xFFFF, sum = 0
7728 18:10:53.090578 14, 0x0, sum = 1
7729 18:10:53.090998 15, 0x0, sum = 2
7730 18:10:53.094110 16, 0x0, sum = 3
7731 18:10:53.094579 17, 0x0, sum = 4
7732 18:10:53.097556 best_step = 15
7733 18:10:53.097981
7734 18:10:53.098428 ==
7735 18:10:53.100406 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 18:10:53.104010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 18:10:53.104475 ==
7738 18:10:53.107564 RX Vref Scan: 1
7739 18:10:53.107988
7740 18:10:53.108541 Set Vref Range= 24 -> 127
7741 18:10:53.108975
7742 18:10:53.110896 RX Vref 24 -> 127, step: 1
7743 18:10:53.111323
7744 18:10:53.114316 RX Delay 27 -> 252, step: 4
7745 18:10:53.114762
7746 18:10:53.117414 Set Vref, RX VrefLevel [Byte0]: 24
7747 18:10:53.120448 [Byte1]: 24
7748 18:10:53.120889
7749 18:10:53.123683 Set Vref, RX VrefLevel [Byte0]: 25
7750 18:10:53.127440 [Byte1]: 25
7751 18:10:53.127970
7752 18:10:53.131091 Set Vref, RX VrefLevel [Byte0]: 26
7753 18:10:53.133764 [Byte1]: 26
7754 18:10:53.137705
7755 18:10:53.138133 Set Vref, RX VrefLevel [Byte0]: 27
7756 18:10:53.141239 [Byte1]: 27
7757 18:10:53.145327
7758 18:10:53.145734 Set Vref, RX VrefLevel [Byte0]: 28
7759 18:10:53.148971 [Byte1]: 28
7760 18:10:53.152956
7761 18:10:53.153367 Set Vref, RX VrefLevel [Byte0]: 29
7762 18:10:53.156010 [Byte1]: 29
7763 18:10:53.160445
7764 18:10:53.160949 Set Vref, RX VrefLevel [Byte0]: 30
7765 18:10:53.164324 [Byte1]: 30
7766 18:10:53.168092
7767 18:10:53.168775 Set Vref, RX VrefLevel [Byte0]: 31
7768 18:10:53.171458 [Byte1]: 31
7769 18:10:53.175835
7770 18:10:53.176245 Set Vref, RX VrefLevel [Byte0]: 32
7771 18:10:53.179022 [Byte1]: 32
7772 18:10:53.183466
7773 18:10:53.183977 Set Vref, RX VrefLevel [Byte0]: 33
7774 18:10:53.186145 [Byte1]: 33
7775 18:10:53.190687
7776 18:10:53.191204 Set Vref, RX VrefLevel [Byte0]: 34
7777 18:10:53.193925 [Byte1]: 34
7778 18:10:53.198343
7779 18:10:53.198788 Set Vref, RX VrefLevel [Byte0]: 35
7780 18:10:53.201122 [Byte1]: 35
7781 18:10:53.205858
7782 18:10:53.206373 Set Vref, RX VrefLevel [Byte0]: 36
7783 18:10:53.209162 [Byte1]: 36
7784 18:10:53.213520
7785 18:10:53.213930 Set Vref, RX VrefLevel [Byte0]: 37
7786 18:10:53.216614 [Byte1]: 37
7787 18:10:53.220741
7788 18:10:53.221152 Set Vref, RX VrefLevel [Byte0]: 38
7789 18:10:53.223940 [Byte1]: 38
7790 18:10:53.228017
7791 18:10:53.231665 Set Vref, RX VrefLevel [Byte0]: 39
7792 18:10:53.232088 [Byte1]: 39
7793 18:10:53.236148
7794 18:10:53.236727 Set Vref, RX VrefLevel [Byte0]: 40
7795 18:10:53.238723 [Byte1]: 40
7796 18:10:53.242944
7797 18:10:53.243390 Set Vref, RX VrefLevel [Byte0]: 41
7798 18:10:53.246477 [Byte1]: 41
7799 18:10:53.251008
7800 18:10:53.251493 Set Vref, RX VrefLevel [Byte0]: 42
7801 18:10:53.253596 [Byte1]: 42
7802 18:10:53.258202
7803 18:10:53.258611 Set Vref, RX VrefLevel [Byte0]: 43
7804 18:10:53.261699 [Byte1]: 43
7805 18:10:53.265755
7806 18:10:53.266166 Set Vref, RX VrefLevel [Byte0]: 44
7807 18:10:53.269171 [Byte1]: 44
7808 18:10:53.273170
7809 18:10:53.273636 Set Vref, RX VrefLevel [Byte0]: 45
7810 18:10:53.276879 [Byte1]: 45
7811 18:10:53.280979
7812 18:10:53.281485 Set Vref, RX VrefLevel [Byte0]: 46
7813 18:10:53.284096 [Byte1]: 46
7814 18:10:53.288176
7815 18:10:53.288632 Set Vref, RX VrefLevel [Byte0]: 47
7816 18:10:53.291873 [Byte1]: 47
7817 18:10:53.296384
7818 18:10:53.296906 Set Vref, RX VrefLevel [Byte0]: 48
7819 18:10:53.299375 [Byte1]: 48
7820 18:10:53.303726
7821 18:10:53.304249 Set Vref, RX VrefLevel [Byte0]: 49
7822 18:10:53.307152 [Byte1]: 49
7823 18:10:53.311755
7824 18:10:53.312305 Set Vref, RX VrefLevel [Byte0]: 50
7825 18:10:53.314448 [Byte1]: 50
7826 18:10:53.318807
7827 18:10:53.319229 Set Vref, RX VrefLevel [Byte0]: 51
7828 18:10:53.321636 [Byte1]: 51
7829 18:10:53.326295
7830 18:10:53.326808 Set Vref, RX VrefLevel [Byte0]: 52
7831 18:10:53.329569 [Byte1]: 52
7832 18:10:53.333960
7833 18:10:53.334370 Set Vref, RX VrefLevel [Byte0]: 53
7834 18:10:53.336918 [Byte1]: 53
7835 18:10:53.341178
7836 18:10:53.341590 Set Vref, RX VrefLevel [Byte0]: 54
7837 18:10:53.344713 [Byte1]: 54
7838 18:10:53.349172
7839 18:10:53.349583 Set Vref, RX VrefLevel [Byte0]: 55
7840 18:10:53.351844 [Byte1]: 55
7841 18:10:53.356388
7842 18:10:53.356920 Set Vref, RX VrefLevel [Byte0]: 56
7843 18:10:53.360024 [Byte1]: 56
7844 18:10:53.363797
7845 18:10:53.364303 Set Vref, RX VrefLevel [Byte0]: 57
7846 18:10:53.367446 [Byte1]: 57
7847 18:10:53.371298
7848 18:10:53.371746 Set Vref, RX VrefLevel [Byte0]: 58
7849 18:10:53.374707 [Byte1]: 58
7850 18:10:53.379013
7851 18:10:53.379521 Set Vref, RX VrefLevel [Byte0]: 59
7852 18:10:53.382306 [Byte1]: 59
7853 18:10:53.386703
7854 18:10:53.387223 Set Vref, RX VrefLevel [Byte0]: 60
7855 18:10:53.389469 [Byte1]: 60
7856 18:10:53.394023
7857 18:10:53.394603 Set Vref, RX VrefLevel [Byte0]: 61
7858 18:10:53.397159 [Byte1]: 61
7859 18:10:53.401283
7860 18:10:53.401708 Set Vref, RX VrefLevel [Byte0]: 62
7861 18:10:53.404768 [Byte1]: 62
7862 18:10:53.409116
7863 18:10:53.409559 Set Vref, RX VrefLevel [Byte0]: 63
7864 18:10:53.412106 [Byte1]: 63
7865 18:10:53.416607
7866 18:10:53.417088 Set Vref, RX VrefLevel [Byte0]: 64
7867 18:10:53.419791 [Byte1]: 64
7868 18:10:53.423999
7869 18:10:53.424464 Set Vref, RX VrefLevel [Byte0]: 65
7870 18:10:53.427452 [Byte1]: 65
7871 18:10:53.431169
7872 18:10:53.431584 Set Vref, RX VrefLevel [Byte0]: 66
7873 18:10:53.434698 [Byte1]: 66
7874 18:10:53.439206
7875 18:10:53.439632 Set Vref, RX VrefLevel [Byte0]: 67
7876 18:10:53.442189 [Byte1]: 67
7877 18:10:53.446825
7878 18:10:53.447416 Set Vref, RX VrefLevel [Byte0]: 68
7879 18:10:53.449676 [Byte1]: 68
7880 18:10:53.454100
7881 18:10:53.454551 Set Vref, RX VrefLevel [Byte0]: 69
7882 18:10:53.457781 [Byte1]: 69
7883 18:10:53.461434
7884 18:10:53.461853 Set Vref, RX VrefLevel [Byte0]: 70
7885 18:10:53.465047 [Byte1]: 70
7886 18:10:53.469278
7887 18:10:53.469577 Set Vref, RX VrefLevel [Byte0]: 71
7888 18:10:53.472107 [Byte1]: 71
7889 18:10:53.476449
7890 18:10:53.476772 Set Vref, RX VrefLevel [Byte0]: 72
7891 18:10:53.480120 [Byte1]: 72
7892 18:10:53.483744
7893 18:10:53.484044 Set Vref, RX VrefLevel [Byte0]: 73
7894 18:10:53.487769 [Byte1]: 73
7895 18:10:53.491781
7896 18:10:53.495163 Set Vref, RX VrefLevel [Byte0]: 74
7897 18:10:53.495464 [Byte1]: 74
7898 18:10:53.499297
7899 18:10:53.499681 Set Vref, RX VrefLevel [Byte0]: 75
7900 18:10:53.502933 [Byte1]: 75
7901 18:10:53.506576
7902 18:10:53.506961 Set Vref, RX VrefLevel [Byte0]: 76
7903 18:10:53.509878 [Byte1]: 76
7904 18:10:53.514435
7905 18:10:53.515018 Final RX Vref Byte 0 = 58 to rank0
7906 18:10:53.517845 Final RX Vref Byte 1 = 62 to rank0
7907 18:10:53.521015 Final RX Vref Byte 0 = 58 to rank1
7908 18:10:53.524551 Final RX Vref Byte 1 = 62 to rank1==
7909 18:10:53.527325 Dram Type= 6, Freq= 0, CH_0, rank 0
7910 18:10:53.534027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7911 18:10:53.534545 ==
7912 18:10:53.534989 DQS Delay:
7913 18:10:53.535414 DQS0 = 0, DQS1 = 0
7914 18:10:53.537857 DQM Delay:
7915 18:10:53.538244 DQM0 = 134, DQM1 = 128
7916 18:10:53.540589 DQ Delay:
7917 18:10:53.543989 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7918 18:10:53.547771 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =140
7919 18:10:53.551082 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =120
7920 18:10:53.554233 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7921 18:10:53.554743
7922 18:10:53.555155
7923 18:10:53.555534
7924 18:10:53.557840 [DramC_TX_OE_Calibration] TA2
7925 18:10:53.560453 Original DQ_B0 (3 6) =30, OEN = 27
7926 18:10:53.563926 Original DQ_B1 (3 6) =30, OEN = 27
7927 18:10:53.566829 24, 0x0, End_B0=24 End_B1=24
7928 18:10:53.567222 25, 0x0, End_B0=25 End_B1=25
7929 18:10:53.570564 26, 0x0, End_B0=26 End_B1=26
7930 18:10:53.574079 27, 0x0, End_B0=27 End_B1=27
7931 18:10:53.577106 28, 0x0, End_B0=28 End_B1=28
7932 18:10:53.580852 29, 0x0, End_B0=29 End_B1=29
7933 18:10:53.581249 30, 0x0, End_B0=30 End_B1=30
7934 18:10:53.583675 31, 0x4141, End_B0=30 End_B1=30
7935 18:10:53.587282 Byte0 end_step=30 best_step=27
7936 18:10:53.590206 Byte1 end_step=30 best_step=27
7937 18:10:53.593893 Byte0 TX OE(2T, 0.5T) = (3, 3)
7938 18:10:53.596834 Byte1 TX OE(2T, 0.5T) = (3, 3)
7939 18:10:53.597224
7940 18:10:53.597672
7941 18:10:53.603168 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 392 ps
7942 18:10:53.606517 CH0 RK0: MR19=303, MR18=221D
7943 18:10:53.612959 CH0_RK0: MR19=0x303, MR18=0x221D, DQSOSC=392, MR23=63, INC=24, DEC=16
7944 18:10:53.613148
7945 18:10:53.616308 ----->DramcWriteLeveling(PI) begin...
7946 18:10:53.616534 ==
7947 18:10:53.619689 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 18:10:53.623092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 18:10:53.623290 ==
7950 18:10:53.626699 Write leveling (Byte 0): 34 => 34
7951 18:10:53.629436 Write leveling (Byte 1): 26 => 26
7952 18:10:53.633079 DramcWriteLeveling(PI) end<-----
7953 18:10:53.633208
7954 18:10:53.633279 ==
7955 18:10:53.636227 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 18:10:53.639795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 18:10:53.639957 ==
7958 18:10:53.643247 [Gating] SW mode calibration
7959 18:10:53.649433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7960 18:10:53.655952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7961 18:10:53.659614 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 18:10:53.666224 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 18:10:53.669333 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7964 18:10:53.672739 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7965 18:10:53.679666 1 4 16 | B1->B0 | 2b2b 3939 | 1 1 | (0 0) (1 1)
7966 18:10:53.682539 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7967 18:10:53.686281 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7968 18:10:53.692909 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7969 18:10:53.695825 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7970 18:10:53.699348 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7971 18:10:53.705831 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7972 18:10:53.709738 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 0) (1 0)
7973 18:10:53.712466 1 5 16 | B1->B0 | 2c2c 2a2a | 0 0 | (1 0) (1 0)
7974 18:10:53.719463 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7975 18:10:53.722983 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
7976 18:10:53.725876 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 18:10:53.729474 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 18:10:53.736006 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7979 18:10:53.739650 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7980 18:10:53.742422 1 6 12 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
7981 18:10:53.749040 1 6 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (1 1)
7982 18:10:53.752550 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 18:10:53.755882 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (1 1)
7984 18:10:53.762832 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 18:10:53.765724 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 18:10:53.769314 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 18:10:53.776124 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 18:10:53.779517 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 18:10:53.782828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 18:10:53.789009 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 18:10:53.792530 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 18:10:53.796012 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 18:10:53.802933 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 18:10:53.805795 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 18:10:53.809438 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 18:10:53.815973 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 18:10:53.818823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 18:10:53.822501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 18:10:53.826128 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 18:10:53.832600 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 18:10:53.836089 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 18:10:53.839372 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 18:10:53.845512 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 18:10:53.848858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8005 18:10:53.852408 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8006 18:10:53.859083 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 18:10:53.862867 Total UI for P1: 0, mck2ui 16
8008 18:10:53.865823 best dqsien dly found for B0: ( 1, 9, 14)
8009 18:10:53.865905 Total UI for P1: 0, mck2ui 16
8010 18:10:53.872498 best dqsien dly found for B1: ( 1, 9, 16)
8011 18:10:53.875949 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8012 18:10:53.879203 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8013 18:10:53.879377
8014 18:10:53.882810 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8015 18:10:53.886496 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8016 18:10:53.889667 [Gating] SW calibration Done
8017 18:10:53.889849 ==
8018 18:10:53.892291 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 18:10:53.895874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 18:10:53.896090 ==
8021 18:10:53.899529 RX Vref Scan: 0
8022 18:10:53.899708
8023 18:10:53.899856 RX Vref 0 -> 0, step: 1
8024 18:10:53.900006
8025 18:10:53.902422 RX Delay 0 -> 252, step: 8
8026 18:10:53.906265 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8027 18:10:53.912319 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8028 18:10:53.915491 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8029 18:10:53.919190 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8030 18:10:53.922522 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8031 18:10:53.925555 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8032 18:10:53.932265 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8033 18:10:53.935671 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8034 18:10:53.939404 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8035 18:10:53.942421 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8036 18:10:53.946085 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8037 18:10:53.952465 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8038 18:10:53.955665 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8039 18:10:53.958823 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8040 18:10:53.962751 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8041 18:10:53.965762 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8042 18:10:53.969016 ==
8043 18:10:53.972006 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 18:10:53.975604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 18:10:53.975789 ==
8046 18:10:53.975935 DQS Delay:
8047 18:10:53.979166 DQS0 = 0, DQS1 = 0
8048 18:10:53.979348 DQM Delay:
8049 18:10:53.981848 DQM0 = 137, DQM1 = 129
8050 18:10:53.982003 DQ Delay:
8051 18:10:53.985603 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8052 18:10:53.988377 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8053 18:10:53.991953 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8054 18:10:53.995604 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8055 18:10:53.995742
8056 18:10:53.995861
8057 18:10:53.995998 ==
8058 18:10:53.998512 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 18:10:54.005990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 18:10:54.006205 ==
8061 18:10:54.006361
8062 18:10:54.006494
8063 18:10:54.006613 TX Vref Scan disable
8064 18:10:54.009255 == TX Byte 0 ==
8065 18:10:54.012936 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8066 18:10:54.015830 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8067 18:10:54.019308 == TX Byte 1 ==
8068 18:10:54.022837 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8069 18:10:54.029784 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8070 18:10:54.030005 ==
8071 18:10:54.032657 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 18:10:54.035706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 18:10:54.035918 ==
8074 18:10:54.049268
8075 18:10:54.053014 TX Vref early break, caculate TX vref
8076 18:10:54.056053 TX Vref=16, minBit 1, minWin=23, winSum=389
8077 18:10:54.059985 TX Vref=18, minBit 1, minWin=24, winSum=399
8078 18:10:54.062968 TX Vref=20, minBit 1, minWin=23, winSum=402
8079 18:10:54.066064 TX Vref=22, minBit 0, minWin=25, winSum=412
8080 18:10:54.069280 TX Vref=24, minBit 0, minWin=25, winSum=422
8081 18:10:54.075982 TX Vref=26, minBit 7, minWin=25, winSum=429
8082 18:10:54.079493 TX Vref=28, minBit 1, minWin=25, winSum=425
8083 18:10:54.082359 TX Vref=30, minBit 4, minWin=25, winSum=418
8084 18:10:54.086136 TX Vref=32, minBit 0, minWin=24, winSum=409
8085 18:10:54.089472 TX Vref=34, minBit 0, minWin=24, winSum=402
8086 18:10:54.096127 [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 26
8087 18:10:54.096583
8088 18:10:54.099229 Final TX Range 0 Vref 26
8089 18:10:54.099649
8090 18:10:54.099981 ==
8091 18:10:54.102745 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 18:10:54.105644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 18:10:54.106067 ==
8094 18:10:54.106402
8095 18:10:54.106718
8096 18:10:54.109180 TX Vref Scan disable
8097 18:10:54.116248 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8098 18:10:54.116833 == TX Byte 0 ==
8099 18:10:54.119637 u2DelayCellOfst[0]=13 cells (4 PI)
8100 18:10:54.122461 u2DelayCellOfst[1]=17 cells (5 PI)
8101 18:10:54.126498 u2DelayCellOfst[2]=10 cells (3 PI)
8102 18:10:54.129054 u2DelayCellOfst[3]=10 cells (3 PI)
8103 18:10:54.132597 u2DelayCellOfst[4]=6 cells (2 PI)
8104 18:10:54.136176 u2DelayCellOfst[5]=0 cells (0 PI)
8105 18:10:54.139334 u2DelayCellOfst[6]=17 cells (5 PI)
8106 18:10:54.139847 u2DelayCellOfst[7]=13 cells (4 PI)
8107 18:10:54.146175 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8108 18:10:54.149336 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8109 18:10:54.149856 == TX Byte 1 ==
8110 18:10:54.152753 u2DelayCellOfst[8]=3 cells (1 PI)
8111 18:10:54.156256 u2DelayCellOfst[9]=0 cells (0 PI)
8112 18:10:54.159621 u2DelayCellOfst[10]=6 cells (2 PI)
8113 18:10:54.162796 u2DelayCellOfst[11]=3 cells (1 PI)
8114 18:10:54.165772 u2DelayCellOfst[12]=10 cells (3 PI)
8115 18:10:54.168717 u2DelayCellOfst[13]=10 cells (3 PI)
8116 18:10:54.172377 u2DelayCellOfst[14]=17 cells (5 PI)
8117 18:10:54.175828 u2DelayCellOfst[15]=10 cells (3 PI)
8118 18:10:54.178664 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8119 18:10:54.185736 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8120 18:10:54.186189 DramC Write-DBI on
8121 18:10:54.186540 ==
8122 18:10:54.188659 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 18:10:54.192476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 18:10:54.192902 ==
8125 18:10:54.195311
8126 18:10:54.195727
8127 18:10:54.196061 TX Vref Scan disable
8128 18:10:54.198753 == TX Byte 0 ==
8129 18:10:54.202200 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8130 18:10:54.205912 == TX Byte 1 ==
8131 18:10:54.208902 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8132 18:10:54.209339 DramC Write-DBI off
8133 18:10:54.211946
8134 18:10:54.212405 [DATLAT]
8135 18:10:54.212754 Freq=1600, CH0 RK1
8136 18:10:54.213072
8137 18:10:54.215829 DATLAT Default: 0xf
8138 18:10:54.216248 0, 0xFFFF, sum = 0
8139 18:10:54.219235 1, 0xFFFF, sum = 0
8140 18:10:54.219821 2, 0xFFFF, sum = 0
8141 18:10:54.222515 3, 0xFFFF, sum = 0
8142 18:10:54.225675 4, 0xFFFF, sum = 0
8143 18:10:54.226214 5, 0xFFFF, sum = 0
8144 18:10:54.229044 6, 0xFFFF, sum = 0
8145 18:10:54.229473 7, 0xFFFF, sum = 0
8146 18:10:54.232597 8, 0xFFFF, sum = 0
8147 18:10:54.233053 9, 0xFFFF, sum = 0
8148 18:10:54.235414 10, 0xFFFF, sum = 0
8149 18:10:54.235841 11, 0xFFFF, sum = 0
8150 18:10:54.238804 12, 0xFFFF, sum = 0
8151 18:10:54.239232 13, 0xFFFF, sum = 0
8152 18:10:54.242451 14, 0x0, sum = 1
8153 18:10:54.242880 15, 0x0, sum = 2
8154 18:10:54.245394 16, 0x0, sum = 3
8155 18:10:54.245820 17, 0x0, sum = 4
8156 18:10:54.249112 best_step = 15
8157 18:10:54.249531
8158 18:10:54.249865 ==
8159 18:10:54.251847 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 18:10:54.255576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 18:10:54.256016 ==
8162 18:10:54.256382 RX Vref Scan: 0
8163 18:10:54.258528
8164 18:10:54.258943 RX Vref 0 -> 0, step: 1
8165 18:10:54.259279
8166 18:10:54.262037 RX Delay 19 -> 252, step: 4
8167 18:10:54.265740 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8168 18:10:54.272295 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8169 18:10:54.275593 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8170 18:10:54.278781 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8171 18:10:54.281929 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8172 18:10:54.284831 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8173 18:10:54.291419 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8174 18:10:54.294854 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8175 18:10:54.298246 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8176 18:10:54.301452 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8177 18:10:54.305077 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8178 18:10:54.311917 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8179 18:10:54.315397 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8180 18:10:54.318310 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8181 18:10:54.321707 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8182 18:10:54.325497 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8183 18:10:54.328642 ==
8184 18:10:54.331994 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 18:10:54.335006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 18:10:54.335442 ==
8187 18:10:54.335781 DQS Delay:
8188 18:10:54.338502 DQS0 = 0, DQS1 = 0
8189 18:10:54.338924 DQM Delay:
8190 18:10:54.341986 DQM0 = 134, DQM1 = 127
8191 18:10:54.342422 DQ Delay:
8192 18:10:54.345325 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8193 18:10:54.348276 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8194 18:10:54.351967 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8195 18:10:54.355098 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8196 18:10:54.355628
8197 18:10:54.355971
8198 18:10:54.356283
8199 18:10:54.358724 [DramC_TX_OE_Calibration] TA2
8200 18:10:54.361485 Original DQ_B0 (3 6) =30, OEN = 27
8201 18:10:54.365117 Original DQ_B1 (3 6) =30, OEN = 27
8202 18:10:54.368208 24, 0x0, End_B0=24 End_B1=24
8203 18:10:54.372163 25, 0x0, End_B0=25 End_B1=25
8204 18:10:54.372743 26, 0x0, End_B0=26 End_B1=26
8205 18:10:54.374774 27, 0x0, End_B0=27 End_B1=27
8206 18:10:54.378370 28, 0x0, End_B0=28 End_B1=28
8207 18:10:54.381261 29, 0x0, End_B0=29 End_B1=29
8208 18:10:54.384919 30, 0x0, End_B0=30 End_B1=30
8209 18:10:54.385350 31, 0x4141, End_B0=30 End_B1=30
8210 18:10:54.388483 Byte0 end_step=30 best_step=27
8211 18:10:54.391510 Byte1 end_step=30 best_step=27
8212 18:10:54.395180 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 18:10:54.398101 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 18:10:54.398586
8215 18:10:54.398940
8216 18:10:54.404511 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8217 18:10:54.407698 CH0 RK1: MR19=303, MR18=210A
8218 18:10:54.415062 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8219 18:10:54.417761 [RxdqsGatingPostProcess] freq 1600
8220 18:10:54.424398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 18:10:54.424867 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 18:10:54.427933 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 18:10:54.431153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 18:10:54.434786 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 18:10:54.437503 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 18:10:54.440885 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 18:10:54.444259 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 18:10:54.447566 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 18:10:54.450868 Pre-setting of DQS Precalculation
8230 18:10:54.454495 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 18:10:54.454905 ==
8232 18:10:54.457789 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 18:10:54.464586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 18:10:54.465012 ==
8235 18:10:54.467582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 18:10:54.474396 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 18:10:54.477362 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 18:10:54.483695 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 18:10:54.491946 [CA 0] Center 42 (12~72) winsize 61
8240 18:10:54.495599 [CA 1] Center 42 (13~72) winsize 60
8241 18:10:54.498565 [CA 2] Center 39 (10~68) winsize 59
8242 18:10:54.502494 [CA 3] Center 39 (10~68) winsize 59
8243 18:10:54.505077 [CA 4] Center 38 (9~68) winsize 60
8244 18:10:54.508815 [CA 5] Center 37 (8~67) winsize 60
8245 18:10:54.509244
8246 18:10:54.512420 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8247 18:10:54.512847
8248 18:10:54.515724 [CATrainingPosCal] consider 1 rank data
8249 18:10:54.519001 u2DelayCellTimex100 = 285/100 ps
8250 18:10:54.521814 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8251 18:10:54.528657 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8252 18:10:54.532038 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8253 18:10:54.535480 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8254 18:10:54.538630 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8255 18:10:54.541731 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8256 18:10:54.542144
8257 18:10:54.545521 CA PerBit enable=1, Macro0, CA PI delay=37
8258 18:10:54.545938
8259 18:10:54.549071 [CBTSetCACLKResult] CA Dly = 37
8260 18:10:54.551717 CS Dly: 10 (0~41)
8261 18:10:54.555589 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 18:10:54.558263 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 18:10:54.558781 ==
8264 18:10:54.561748 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 18:10:54.565345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 18:10:54.568437 ==
8267 18:10:54.571822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 18:10:54.575080 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 18:10:54.582000 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 18:10:54.588109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 18:10:54.595948 [CA 0] Center 42 (12~72) winsize 61
8272 18:10:54.598787 [CA 1] Center 42 (13~72) winsize 60
8273 18:10:54.602599 [CA 2] Center 38 (9~68) winsize 60
8274 18:10:54.605401 [CA 3] Center 38 (9~67) winsize 59
8275 18:10:54.609094 [CA 4] Center 38 (8~68) winsize 61
8276 18:10:54.611990 [CA 5] Center 37 (8~67) winsize 60
8277 18:10:54.612609
8278 18:10:54.615821 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 18:10:54.616501
8280 18:10:54.618770 [CATrainingPosCal] consider 2 rank data
8281 18:10:54.622252 u2DelayCellTimex100 = 285/100 ps
8282 18:10:54.625163 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8283 18:10:54.631727 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8284 18:10:54.635329 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8285 18:10:54.638854 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8286 18:10:54.641778 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8287 18:10:54.645306 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 18:10:54.645718
8289 18:10:54.648764 CA PerBit enable=1, Macro0, CA PI delay=37
8290 18:10:54.649275
8291 18:10:54.651965 [CBTSetCACLKResult] CA Dly = 37
8292 18:10:54.655322 CS Dly: 11 (0~44)
8293 18:10:54.658679 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 18:10:54.661510 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 18:10:54.661936
8296 18:10:54.664990 ----->DramcWriteLeveling(PI) begin...
8297 18:10:54.665480 ==
8298 18:10:54.668462 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 18:10:54.674553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 18:10:54.674922 ==
8301 18:10:54.677917 Write leveling (Byte 0): 26 => 26
8302 18:10:54.681245 Write leveling (Byte 1): 29 => 29
8303 18:10:54.681554 DramcWriteLeveling(PI) end<-----
8304 18:10:54.681790
8305 18:10:54.684998 ==
8306 18:10:54.688098 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 18:10:54.691296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 18:10:54.691712 ==
8309 18:10:54.694759 [Gating] SW mode calibration
8310 18:10:54.701163 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 18:10:54.704800 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 18:10:54.711531 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 18:10:54.714174 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 18:10:54.718068 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8315 18:10:54.724879 1 4 12 | B1->B0 | 302f 3434 | 1 1 | (0 0) (1 1)
8316 18:10:54.727761 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 18:10:54.731201 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 18:10:54.737622 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 18:10:54.741060 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 18:10:54.744134 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 18:10:54.751377 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 18:10:54.754382 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8323 18:10:54.757978 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8324 18:10:54.764453 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8325 18:10:54.767824 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 18:10:54.771387 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 18:10:54.774018 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 18:10:54.781347 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 18:10:54.784226 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 18:10:54.788087 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8331 18:10:54.795023 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 18:10:54.797795 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 18:10:54.801292 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 18:10:54.807980 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 18:10:54.811277 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 18:10:54.814607 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 18:10:54.821186 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 18:10:54.824450 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 18:10:54.827858 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 18:10:54.834283 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 18:10:54.837492 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 18:10:54.840919 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 18:10:54.847152 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 18:10:54.850807 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 18:10:54.854006 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 18:10:54.860542 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 18:10:54.864086 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 18:10:54.867721 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 18:10:54.874557 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 18:10:54.877530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 18:10:54.880704 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 18:10:54.887594 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 18:10:54.890540 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8354 18:10:54.894284 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 18:10:54.900681 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 18:10:54.903749 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 18:10:54.907304 Total UI for P1: 0, mck2ui 16
8358 18:10:54.910477 best dqsien dly found for B0: ( 1, 9, 10)
8359 18:10:54.913736 Total UI for P1: 0, mck2ui 16
8360 18:10:54.916974 best dqsien dly found for B1: ( 1, 9, 8)
8361 18:10:54.920685 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8362 18:10:54.923547 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8363 18:10:54.923988
8364 18:10:54.927071 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8365 18:10:54.930406 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8366 18:10:54.933615 [Gating] SW calibration Done
8367 18:10:54.934198 ==
8368 18:10:54.937232 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 18:10:54.940112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 18:10:54.943283 ==
8371 18:10:54.943732 RX Vref Scan: 0
8372 18:10:54.944165
8373 18:10:54.947134 RX Vref 0 -> 0, step: 1
8374 18:10:54.947571
8375 18:10:54.948003 RX Delay 0 -> 252, step: 8
8376 18:10:54.953907 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8377 18:10:54.956779 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 18:10:54.960185 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 18:10:54.963668 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 18:10:54.967065 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 18:10:54.974239 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8382 18:10:54.976850 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8383 18:10:54.980401 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 18:10:54.983837 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 18:10:54.986536 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 18:10:54.993304 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 18:10:54.996701 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 18:10:55.000142 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 18:10:55.003686 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8390 18:10:55.007301 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 18:10:55.013626 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8392 18:10:55.014132 ==
8393 18:10:55.016467 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 18:10:55.020010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 18:10:55.020483 ==
8396 18:10:55.020921 DQS Delay:
8397 18:10:55.023476 DQS0 = 0, DQS1 = 0
8398 18:10:55.023929 DQM Delay:
8399 18:10:55.026855 DQM0 = 137, DQM1 = 133
8400 18:10:55.027291 DQ Delay:
8401 18:10:55.030170 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8402 18:10:55.032984 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8403 18:10:55.036584 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 18:10:55.040198 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8405 18:10:55.043342
8406 18:10:55.043749
8407 18:10:55.044077 ==
8408 18:10:55.046842 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 18:10:55.049634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 18:10:55.050074 ==
8411 18:10:55.050409
8412 18:10:55.050720
8413 18:10:55.053457 TX Vref Scan disable
8414 18:10:55.053986 == TX Byte 0 ==
8415 18:10:55.060257 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8416 18:10:55.063310 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8417 18:10:55.063739 == TX Byte 1 ==
8418 18:10:55.070300 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8419 18:10:55.072948 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8420 18:10:55.073373 ==
8421 18:10:55.076609 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 18:10:55.079604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 18:10:55.080061 ==
8424 18:10:55.093273
8425 18:10:55.096733 TX Vref early break, caculate TX vref
8426 18:10:55.099406 TX Vref=16, minBit 0, minWin=23, winSum=376
8427 18:10:55.103246 TX Vref=18, minBit 0, minWin=23, winSum=383
8428 18:10:55.106544 TX Vref=20, minBit 6, minWin=23, winSum=395
8429 18:10:55.110000 TX Vref=22, minBit 0, minWin=25, winSum=406
8430 18:10:55.112878 TX Vref=24, minBit 0, minWin=25, winSum=415
8431 18:10:55.119561 TX Vref=26, minBit 1, minWin=25, winSum=426
8432 18:10:55.123157 TX Vref=28, minBit 0, minWin=25, winSum=424
8433 18:10:55.126122 TX Vref=30, minBit 0, minWin=25, winSum=418
8434 18:10:55.130031 TX Vref=32, minBit 0, minWin=24, winSum=412
8435 18:10:55.132618 TX Vref=34, minBit 0, minWin=23, winSum=398
8436 18:10:55.139288 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8437 18:10:55.139711
8438 18:10:55.142902 Final TX Range 0 Vref 26
8439 18:10:55.143319
8440 18:10:55.143645 ==
8441 18:10:55.146653 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 18:10:55.149347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 18:10:55.149773 ==
8444 18:10:55.150109
8445 18:10:55.150421
8446 18:10:55.152767 TX Vref Scan disable
8447 18:10:55.159501 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8448 18:10:55.159919 == TX Byte 0 ==
8449 18:10:55.162487 u2DelayCellOfst[0]=17 cells (5 PI)
8450 18:10:55.166227 u2DelayCellOfst[1]=10 cells (3 PI)
8451 18:10:55.169611 u2DelayCellOfst[2]=0 cells (0 PI)
8452 18:10:55.172377 u2DelayCellOfst[3]=6 cells (2 PI)
8453 18:10:55.176319 u2DelayCellOfst[4]=6 cells (2 PI)
8454 18:10:55.179648 u2DelayCellOfst[5]=17 cells (5 PI)
8455 18:10:55.182171 u2DelayCellOfst[6]=17 cells (5 PI)
8456 18:10:55.182600 u2DelayCellOfst[7]=6 cells (2 PI)
8457 18:10:55.189068 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8458 18:10:55.192044 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8459 18:10:55.192276 == TX Byte 1 ==
8460 18:10:55.195578 u2DelayCellOfst[8]=0 cells (0 PI)
8461 18:10:55.199510 u2DelayCellOfst[9]=3 cells (1 PI)
8462 18:10:55.202299 u2DelayCellOfst[10]=13 cells (4 PI)
8463 18:10:55.205686 u2DelayCellOfst[11]=6 cells (2 PI)
8464 18:10:55.209174 u2DelayCellOfst[12]=17 cells (5 PI)
8465 18:10:55.212116 u2DelayCellOfst[13]=17 cells (5 PI)
8466 18:10:55.215702 u2DelayCellOfst[14]=17 cells (5 PI)
8467 18:10:55.218569 u2DelayCellOfst[15]=17 cells (5 PI)
8468 18:10:55.222134 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8469 18:10:55.228998 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8470 18:10:55.229370 DramC Write-DBI on
8471 18:10:55.229595 ==
8472 18:10:55.232306 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 18:10:55.235206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 18:10:55.238842 ==
8475 18:10:55.239196
8476 18:10:55.239479
8477 18:10:55.239794 TX Vref Scan disable
8478 18:10:55.242621 == TX Byte 0 ==
8479 18:10:55.245426 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8480 18:10:55.248726 == TX Byte 1 ==
8481 18:10:55.251936 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8482 18:10:55.252326 DramC Write-DBI off
8483 18:10:55.255457
8484 18:10:55.255859 [DATLAT]
8485 18:10:55.256195 Freq=1600, CH1 RK0
8486 18:10:55.256572
8487 18:10:55.258979 DATLAT Default: 0xf
8488 18:10:55.259398 0, 0xFFFF, sum = 0
8489 18:10:55.262650 1, 0xFFFF, sum = 0
8490 18:10:55.263090 2, 0xFFFF, sum = 0
8491 18:10:55.265661 3, 0xFFFF, sum = 0
8492 18:10:55.266088 4, 0xFFFF, sum = 0
8493 18:10:55.269297 5, 0xFFFF, sum = 0
8494 18:10:55.272492 6, 0xFFFF, sum = 0
8495 18:10:55.273041 7, 0xFFFF, sum = 0
8496 18:10:55.276004 8, 0xFFFF, sum = 0
8497 18:10:55.276470 9, 0xFFFF, sum = 0
8498 18:10:55.278839 10, 0xFFFF, sum = 0
8499 18:10:55.279265 11, 0xFFFF, sum = 0
8500 18:10:55.282382 12, 0xFFFF, sum = 0
8501 18:10:55.282816 13, 0xFFFF, sum = 0
8502 18:10:55.285566 14, 0x0, sum = 1
8503 18:10:55.285989 15, 0x0, sum = 2
8504 18:10:55.288871 16, 0x0, sum = 3
8505 18:10:55.289300 17, 0x0, sum = 4
8506 18:10:55.292265 best_step = 15
8507 18:10:55.292716
8508 18:10:55.293066 ==
8509 18:10:55.295607 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 18:10:55.298455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 18:10:55.298873 ==
8512 18:10:55.302187 RX Vref Scan: 1
8513 18:10:55.302608
8514 18:10:55.302961 Set Vref Range= 24 -> 127
8515 18:10:55.303278
8516 18:10:55.305130 RX Vref 24 -> 127, step: 1
8517 18:10:55.305550
8518 18:10:55.308776 RX Delay 27 -> 252, step: 4
8519 18:10:55.309198
8520 18:10:55.312412 Set Vref, RX VrefLevel [Byte0]: 24
8521 18:10:55.315160 [Byte1]: 24
8522 18:10:55.315592
8523 18:10:55.319037 Set Vref, RX VrefLevel [Byte0]: 25
8524 18:10:55.321675 [Byte1]: 25
8525 18:10:55.322103
8526 18:10:55.325563 Set Vref, RX VrefLevel [Byte0]: 26
8527 18:10:55.328337 [Byte1]: 26
8528 18:10:55.332705
8529 18:10:55.333125 Set Vref, RX VrefLevel [Byte0]: 27
8530 18:10:55.335348 [Byte1]: 27
8531 18:10:55.340085
8532 18:10:55.340547 Set Vref, RX VrefLevel [Byte0]: 28
8533 18:10:55.343344 [Byte1]: 28
8534 18:10:55.347362
8535 18:10:55.347801 Set Vref, RX VrefLevel [Byte0]: 29
8536 18:10:55.350924 [Byte1]: 29
8537 18:10:55.355291
8538 18:10:55.355723 Set Vref, RX VrefLevel [Byte0]: 30
8539 18:10:55.358564 [Byte1]: 30
8540 18:10:55.362521
8541 18:10:55.362989 Set Vref, RX VrefLevel [Byte0]: 31
8542 18:10:55.365799 [Byte1]: 31
8543 18:10:55.369973
8544 18:10:55.370405 Set Vref, RX VrefLevel [Byte0]: 32
8545 18:10:55.373585 [Byte1]: 32
8546 18:10:55.378165
8547 18:10:55.378594 Set Vref, RX VrefLevel [Byte0]: 33
8548 18:10:55.380876 [Byte1]: 33
8549 18:10:55.385298
8550 18:10:55.385806 Set Vref, RX VrefLevel [Byte0]: 34
8551 18:10:55.388637 [Byte1]: 34
8552 18:10:55.392625
8553 18:10:55.393050 Set Vref, RX VrefLevel [Byte0]: 35
8554 18:10:55.396251 [Byte1]: 35
8555 18:10:55.400605
8556 18:10:55.401022 Set Vref, RX VrefLevel [Byte0]: 36
8557 18:10:55.403396 [Byte1]: 36
8558 18:10:55.408035
8559 18:10:55.408505 Set Vref, RX VrefLevel [Byte0]: 37
8560 18:10:55.410717 [Byte1]: 37
8561 18:10:55.415048
8562 18:10:55.415578 Set Vref, RX VrefLevel [Byte0]: 38
8563 18:10:55.418608 [Byte1]: 38
8564 18:10:55.422791
8565 18:10:55.423241 Set Vref, RX VrefLevel [Byte0]: 39
8566 18:10:55.426477 [Byte1]: 39
8567 18:10:55.431170
8568 18:10:55.431682 Set Vref, RX VrefLevel [Byte0]: 40
8569 18:10:55.433695 [Byte1]: 40
8570 18:10:55.437902
8571 18:10:55.438331 Set Vref, RX VrefLevel [Byte0]: 41
8572 18:10:55.440755 [Byte1]: 41
8573 18:10:55.445104
8574 18:10:55.445521 Set Vref, RX VrefLevel [Byte0]: 42
8575 18:10:55.448683 [Byte1]: 42
8576 18:10:55.452798
8577 18:10:55.453216 Set Vref, RX VrefLevel [Byte0]: 43
8578 18:10:55.456201 [Byte1]: 43
8579 18:10:55.460335
8580 18:10:55.460791 Set Vref, RX VrefLevel [Byte0]: 44
8581 18:10:55.463663 [Byte1]: 44
8582 18:10:55.467766
8583 18:10:55.471587 Set Vref, RX VrefLevel [Byte0]: 45
8584 18:10:55.474837 [Byte1]: 45
8585 18:10:55.475256
8586 18:10:55.477459 Set Vref, RX VrefLevel [Byte0]: 46
8587 18:10:55.481112 [Byte1]: 46
8588 18:10:55.481534
8589 18:10:55.484602 Set Vref, RX VrefLevel [Byte0]: 47
8590 18:10:55.487395 [Byte1]: 47
8591 18:10:55.488001
8592 18:10:55.491185 Set Vref, RX VrefLevel [Byte0]: 48
8593 18:10:55.494047 [Byte1]: 48
8594 18:10:55.498126
8595 18:10:55.498543 Set Vref, RX VrefLevel [Byte0]: 49
8596 18:10:55.501493 [Byte1]: 49
8597 18:10:55.505659
8598 18:10:55.506076 Set Vref, RX VrefLevel [Byte0]: 50
8599 18:10:55.508658 [Byte1]: 50
8600 18:10:55.513665
8601 18:10:55.514140 Set Vref, RX VrefLevel [Byte0]: 51
8602 18:10:55.516487 [Byte1]: 51
8603 18:10:55.520655
8604 18:10:55.521070 Set Vref, RX VrefLevel [Byte0]: 52
8605 18:10:55.523966 [Byte1]: 52
8606 18:10:55.528552
8607 18:10:55.529103 Set Vref, RX VrefLevel [Byte0]: 53
8608 18:10:55.532063 [Byte1]: 53
8609 18:10:55.535597
8610 18:10:55.536103 Set Vref, RX VrefLevel [Byte0]: 54
8611 18:10:55.539311 [Byte1]: 54
8612 18:10:55.543432
8613 18:10:55.543849 Set Vref, RX VrefLevel [Byte0]: 55
8614 18:10:55.546814 [Byte1]: 55
8615 18:10:55.551491
8616 18:10:55.552000 Set Vref, RX VrefLevel [Byte0]: 56
8617 18:10:55.554154 [Byte1]: 56
8618 18:10:55.558619
8619 18:10:55.559151 Set Vref, RX VrefLevel [Byte0]: 57
8620 18:10:55.561529 [Byte1]: 57
8621 18:10:55.565920
8622 18:10:55.566480 Set Vref, RX VrefLevel [Byte0]: 58
8623 18:10:55.569089 [Byte1]: 58
8624 18:10:55.573361
8625 18:10:55.573778 Set Vref, RX VrefLevel [Byte0]: 59
8626 18:10:55.576701 [Byte1]: 59
8627 18:10:55.581280
8628 18:10:55.581695 Set Vref, RX VrefLevel [Byte0]: 60
8629 18:10:55.584542 [Byte1]: 60
8630 18:10:55.588490
8631 18:10:55.589051 Set Vref, RX VrefLevel [Byte0]: 61
8632 18:10:55.591713 [Byte1]: 61
8633 18:10:55.595947
8634 18:10:55.596489 Set Vref, RX VrefLevel [Byte0]: 62
8635 18:10:55.599569 [Byte1]: 62
8636 18:10:55.603440
8637 18:10:55.603922 Set Vref, RX VrefLevel [Byte0]: 63
8638 18:10:55.607261 [Byte1]: 63
8639 18:10:55.611702
8640 18:10:55.612366 Set Vref, RX VrefLevel [Byte0]: 64
8641 18:10:55.614307 [Byte1]: 64
8642 18:10:55.619000
8643 18:10:55.619577 Set Vref, RX VrefLevel [Byte0]: 65
8644 18:10:55.621734 [Byte1]: 65
8645 18:10:55.625973
8646 18:10:55.626552 Set Vref, RX VrefLevel [Byte0]: 66
8647 18:10:55.629654 [Byte1]: 66
8648 18:10:55.633583
8649 18:10:55.634121 Set Vref, RX VrefLevel [Byte0]: 67
8650 18:10:55.636894 [Byte1]: 67
8651 18:10:55.641121
8652 18:10:55.641624 Set Vref, RX VrefLevel [Byte0]: 68
8653 18:10:55.644391 [Byte1]: 68
8654 18:10:55.648632
8655 18:10:55.649163 Set Vref, RX VrefLevel [Byte0]: 69
8656 18:10:55.651736 [Byte1]: 69
8657 18:10:55.656053
8658 18:10:55.656622 Set Vref, RX VrefLevel [Byte0]: 70
8659 18:10:55.659672 [Byte1]: 70
8660 18:10:55.663800
8661 18:10:55.664213 Set Vref, RX VrefLevel [Byte0]: 71
8662 18:10:55.667489 [Byte1]: 71
8663 18:10:55.671815
8664 18:10:55.672392 Set Vref, RX VrefLevel [Byte0]: 72
8665 18:10:55.675191 [Byte1]: 72
8666 18:10:55.679051
8667 18:10:55.679488 Set Vref, RX VrefLevel [Byte0]: 73
8668 18:10:55.681954 [Byte1]: 73
8669 18:10:55.686337
8670 18:10:55.686753 Set Vref, RX VrefLevel [Byte0]: 74
8671 18:10:55.689814 [Byte1]: 74
8672 18:10:55.694332
8673 18:10:55.694743 Set Vref, RX VrefLevel [Byte0]: 75
8674 18:10:55.697127 [Byte1]: 75
8675 18:10:55.701205
8676 18:10:55.701613 Set Vref, RX VrefLevel [Byte0]: 76
8677 18:10:55.704970 [Byte1]: 76
8678 18:10:55.708851
8679 18:10:55.709280 Set Vref, RX VrefLevel [Byte0]: 77
8680 18:10:55.712472 [Byte1]: 77
8681 18:10:55.716574
8682 18:10:55.717170 Final RX Vref Byte 0 = 58 to rank0
8683 18:10:55.719637 Final RX Vref Byte 1 = 58 to rank0
8684 18:10:55.723153 Final RX Vref Byte 0 = 58 to rank1
8685 18:10:55.726109 Final RX Vref Byte 1 = 58 to rank1==
8686 18:10:55.730020 Dram Type= 6, Freq= 0, CH_1, rank 0
8687 18:10:55.736674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8688 18:10:55.737181 ==
8689 18:10:55.737545 DQS Delay:
8690 18:10:55.739507 DQS0 = 0, DQS1 = 0
8691 18:10:55.739920 DQM Delay:
8692 18:10:55.740250 DQM0 = 134, DQM1 = 131
8693 18:10:55.743149 DQ Delay:
8694 18:10:55.746109 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8695 18:10:55.749711 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8696 18:10:55.753325 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8697 18:10:55.756029 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8698 18:10:55.756580
8699 18:10:55.756999
8700 18:10:55.757423
8701 18:10:55.759716 [DramC_TX_OE_Calibration] TA2
8702 18:10:55.763015 Original DQ_B0 (3 6) =30, OEN = 27
8703 18:10:55.765992 Original DQ_B1 (3 6) =30, OEN = 27
8704 18:10:55.769300 24, 0x0, End_B0=24 End_B1=24
8705 18:10:55.769745 25, 0x0, End_B0=25 End_B1=25
8706 18:10:55.773092 26, 0x0, End_B0=26 End_B1=26
8707 18:10:55.776005 27, 0x0, End_B0=27 End_B1=27
8708 18:10:55.779497 28, 0x0, End_B0=28 End_B1=28
8709 18:10:55.782518 29, 0x0, End_B0=29 End_B1=29
8710 18:10:55.782983 30, 0x0, End_B0=30 End_B1=30
8711 18:10:55.786093 31, 0x4141, End_B0=30 End_B1=30
8712 18:10:55.789608 Byte0 end_step=30 best_step=27
8713 18:10:55.792487 Byte1 end_step=30 best_step=27
8714 18:10:55.796029 Byte0 TX OE(2T, 0.5T) = (3, 3)
8715 18:10:55.799499 Byte1 TX OE(2T, 0.5T) = (3, 3)
8716 18:10:55.800022
8717 18:10:55.800549
8718 18:10:55.806019 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8719 18:10:55.809816 CH1 RK0: MR19=303, MR18=1523
8720 18:10:55.815986 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8721 18:10:55.816448
8722 18:10:55.819406 ----->DramcWriteLeveling(PI) begin...
8723 18:10:55.819827 ==
8724 18:10:55.822665 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 18:10:55.826234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 18:10:55.826646 ==
8727 18:10:55.829003 Write leveling (Byte 0): 25 => 25
8728 18:10:55.832831 Write leveling (Byte 1): 28 => 28
8729 18:10:55.835703 DramcWriteLeveling(PI) end<-----
8730 18:10:55.836135
8731 18:10:55.836627 ==
8732 18:10:55.839174 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 18:10:55.842452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 18:10:55.842969 ==
8735 18:10:55.845893 [Gating] SW mode calibration
8736 18:10:55.852872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8737 18:10:55.859023 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8738 18:10:55.862732 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 18:10:55.869444 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 18:10:55.872726 1 4 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
8741 18:10:55.875728 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8742 18:10:55.882653 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 18:10:55.885981 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 18:10:55.889219 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 18:10:55.891958 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 18:10:55.899105 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 18:10:55.901741 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 18:10:55.908981 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8749 18:10:55.911948 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 1)
8750 18:10:55.916056 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 18:10:55.918311 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 18:10:55.925318 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 18:10:55.928190 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 18:10:55.932125 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 18:10:55.938173 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 18:10:55.941763 1 6 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
8757 18:10:55.945275 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8758 18:10:55.951851 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 18:10:55.955319 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 18:10:55.958435 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 18:10:55.964902 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 18:10:55.968446 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 18:10:55.971226 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 18:10:55.978114 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 18:10:55.981678 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 18:10:55.985250 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 18:10:55.991460 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 18:10:55.994880 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 18:10:55.998712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 18:10:56.005024 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 18:10:56.007935 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 18:10:56.011816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 18:10:56.018298 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 18:10:56.021757 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 18:10:56.024385 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 18:10:56.031844 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 18:10:56.034435 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 18:10:56.037783 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 18:10:56.044886 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8780 18:10:56.048139 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 18:10:56.051391 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8782 18:10:56.054403 Total UI for P1: 0, mck2ui 16
8783 18:10:56.057885 best dqsien dly found for B1: ( 1, 9, 6)
8784 18:10:56.064449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 18:10:56.064885 Total UI for P1: 0, mck2ui 16
8786 18:10:56.067880 best dqsien dly found for B0: ( 1, 9, 12)
8787 18:10:56.074740 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8788 18:10:56.077422 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8789 18:10:56.077849
8790 18:10:56.081143 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8791 18:10:56.084170 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8792 18:10:56.087425 [Gating] SW calibration Done
8793 18:10:56.087846 ==
8794 18:10:56.091096 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 18:10:56.093973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 18:10:56.094396 ==
8797 18:10:56.097657 RX Vref Scan: 0
8798 18:10:56.098076
8799 18:10:56.098415 RX Vref 0 -> 0, step: 1
8800 18:10:56.098732
8801 18:10:56.100934 RX Delay 0 -> 252, step: 8
8802 18:10:56.104127 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8803 18:10:56.110714 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8804 18:10:56.114281 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8805 18:10:56.117299 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8806 18:10:56.121087 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8807 18:10:56.123965 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8808 18:10:56.131309 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8809 18:10:56.134008 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8810 18:10:56.137617 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8811 18:10:56.140524 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8812 18:10:56.144198 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8813 18:10:56.150852 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8814 18:10:56.153745 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8815 18:10:56.157561 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8816 18:10:56.160419 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8817 18:10:56.164161 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8818 18:10:56.166752 ==
8819 18:10:56.167276 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 18:10:56.173885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 18:10:56.174544 ==
8822 18:10:56.174891 DQS Delay:
8823 18:10:56.176882 DQS0 = 0, DQS1 = 0
8824 18:10:56.177377 DQM Delay:
8825 18:10:56.180128 DQM0 = 136, DQM1 = 133
8826 18:10:56.180577 DQ Delay:
8827 18:10:56.184094 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8828 18:10:56.187242 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8829 18:10:56.190412 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8830 18:10:56.193776 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8831 18:10:56.194194
8832 18:10:56.194524
8833 18:10:56.194897 ==
8834 18:10:56.196788 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 18:10:56.203472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 18:10:56.204003 ==
8837 18:10:56.204398
8838 18:10:56.204731
8839 18:10:56.205036 TX Vref Scan disable
8840 18:10:56.207069 == TX Byte 0 ==
8841 18:10:56.210692 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8842 18:10:56.216951 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8843 18:10:56.217453 == TX Byte 1 ==
8844 18:10:56.220533 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8845 18:10:56.226869 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8846 18:10:56.227444 ==
8847 18:10:56.230786 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 18:10:56.233610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 18:10:56.234217 ==
8850 18:10:56.247129
8851 18:10:56.249925 TX Vref early break, caculate TX vref
8852 18:10:56.253577 TX Vref=16, minBit 0, minWin=23, winSum=381
8853 18:10:56.257022 TX Vref=18, minBit 0, minWin=23, winSum=392
8854 18:10:56.260957 TX Vref=20, minBit 2, minWin=23, winSum=403
8855 18:10:56.263478 TX Vref=22, minBit 0, minWin=23, winSum=409
8856 18:10:56.267496 TX Vref=24, minBit 0, minWin=25, winSum=420
8857 18:10:56.273990 TX Vref=26, minBit 0, minWin=26, winSum=426
8858 18:10:56.277273 TX Vref=28, minBit 0, minWin=26, winSum=425
8859 18:10:56.280089 TX Vref=30, minBit 0, minWin=25, winSum=420
8860 18:10:56.283732 TX Vref=32, minBit 0, minWin=24, winSum=413
8861 18:10:56.286748 TX Vref=34, minBit 0, minWin=24, winSum=406
8862 18:10:56.290197 TX Vref=36, minBit 0, minWin=24, winSum=399
8863 18:10:56.297496 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8864 18:10:56.297915
8865 18:10:56.300782 Final TX Range 0 Vref 26
8866 18:10:56.301197
8867 18:10:56.301529 ==
8868 18:10:56.304319 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 18:10:56.306910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 18:10:56.307343 ==
8871 18:10:56.307710
8872 18:10:56.308210
8873 18:10:56.310851 TX Vref Scan disable
8874 18:10:56.317060 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8875 18:10:56.317501 == TX Byte 0 ==
8876 18:10:56.320789 u2DelayCellOfst[0]=20 cells (6 PI)
8877 18:10:56.324056 u2DelayCellOfst[1]=10 cells (3 PI)
8878 18:10:56.327465 u2DelayCellOfst[2]=0 cells (0 PI)
8879 18:10:56.330479 u2DelayCellOfst[3]=6 cells (2 PI)
8880 18:10:56.333806 u2DelayCellOfst[4]=10 cells (3 PI)
8881 18:10:56.336987 u2DelayCellOfst[5]=17 cells (5 PI)
8882 18:10:56.340444 u2DelayCellOfst[6]=17 cells (5 PI)
8883 18:10:56.343836 u2DelayCellOfst[7]=6 cells (2 PI)
8884 18:10:56.346868 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8885 18:10:56.350214 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 18:10:56.350727 == TX Byte 1 ==
8887 18:10:56.353965 u2DelayCellOfst[8]=0 cells (0 PI)
8888 18:10:56.356920 u2DelayCellOfst[9]=3 cells (1 PI)
8889 18:10:56.360739 u2DelayCellOfst[10]=10 cells (3 PI)
8890 18:10:56.364280 u2DelayCellOfst[11]=6 cells (2 PI)
8891 18:10:56.367499 u2DelayCellOfst[12]=13 cells (4 PI)
8892 18:10:56.370798 u2DelayCellOfst[13]=13 cells (4 PI)
8893 18:10:56.374112 u2DelayCellOfst[14]=17 cells (5 PI)
8894 18:10:56.377403 u2DelayCellOfst[15]=17 cells (5 PI)
8895 18:10:56.380436 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8896 18:10:56.387587 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 18:10:56.388026 DramC Write-DBI on
8898 18:10:56.388403 ==
8899 18:10:56.390411 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 18:10:56.394345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 18:10:56.397047 ==
8902 18:10:56.397469
8903 18:10:56.397803
8904 18:10:56.398111 TX Vref Scan disable
8905 18:10:56.400784 == TX Byte 0 ==
8906 18:10:56.403834 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8907 18:10:56.407098 == TX Byte 1 ==
8908 18:10:56.411019 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 18:10:56.411543 DramC Write-DBI off
8910 18:10:56.413488
8911 18:10:56.413974 [DATLAT]
8912 18:10:56.414348 Freq=1600, CH1 RK1
8913 18:10:56.414667
8914 18:10:56.417113 DATLAT Default: 0xf
8915 18:10:56.417605 0, 0xFFFF, sum = 0
8916 18:10:56.420167 1, 0xFFFF, sum = 0
8917 18:10:56.420809 2, 0xFFFF, sum = 0
8918 18:10:56.423571 3, 0xFFFF, sum = 0
8919 18:10:56.423996 4, 0xFFFF, sum = 0
8920 18:10:56.426982 5, 0xFFFF, sum = 0
8921 18:10:56.430623 6, 0xFFFF, sum = 0
8922 18:10:56.431045 7, 0xFFFF, sum = 0
8923 18:10:56.433439 8, 0xFFFF, sum = 0
8924 18:10:56.433863 9, 0xFFFF, sum = 0
8925 18:10:56.436909 10, 0xFFFF, sum = 0
8926 18:10:56.437333 11, 0xFFFF, sum = 0
8927 18:10:56.440613 12, 0xFFFF, sum = 0
8928 18:10:56.441036 13, 0xFFFF, sum = 0
8929 18:10:56.443362 14, 0x0, sum = 1
8930 18:10:56.443786 15, 0x0, sum = 2
8931 18:10:56.446864 16, 0x0, sum = 3
8932 18:10:56.447286 17, 0x0, sum = 4
8933 18:10:56.449993 best_step = 15
8934 18:10:56.450442
8935 18:10:56.450900 ==
8936 18:10:56.453189 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 18:10:56.456522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 18:10:56.457028 ==
8939 18:10:56.457384 RX Vref Scan: 0
8940 18:10:56.459970
8941 18:10:56.460474 RX Vref 0 -> 0, step: 1
8942 18:10:56.460891
8943 18:10:56.463264 RX Delay 19 -> 252, step: 4
8944 18:10:56.466829 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8945 18:10:56.473050 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8946 18:10:56.476670 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8947 18:10:56.480235 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8948 18:10:56.483355 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8949 18:10:56.486869 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8950 18:10:56.489729 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8951 18:10:56.496446 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8952 18:10:56.500130 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8953 18:10:56.503316 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8954 18:10:56.506937 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8955 18:10:56.513334 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8956 18:10:56.516292 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8957 18:10:56.519443 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8958 18:10:56.523179 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8959 18:10:56.526163 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8960 18:10:56.529682 ==
8961 18:10:56.530183 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 18:10:56.536868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 18:10:56.537406 ==
8964 18:10:56.537752 DQS Delay:
8965 18:10:56.539395 DQS0 = 0, DQS1 = 0
8966 18:10:56.539808 DQM Delay:
8967 18:10:56.542828 DQM0 = 134, DQM1 = 130
8968 18:10:56.543352 DQ Delay:
8969 18:10:56.546478 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8970 18:10:56.549479 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8971 18:10:56.553136 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8972 18:10:56.556014 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8973 18:10:56.556484
8974 18:10:56.556879
8975 18:10:56.557193
8976 18:10:56.559554 [DramC_TX_OE_Calibration] TA2
8977 18:10:56.562974 Original DQ_B0 (3 6) =30, OEN = 27
8978 18:10:56.566033 Original DQ_B1 (3 6) =30, OEN = 27
8979 18:10:56.569557 24, 0x0, End_B0=24 End_B1=24
8980 18:10:56.573061 25, 0x0, End_B0=25 End_B1=25
8981 18:10:56.573483 26, 0x0, End_B0=26 End_B1=26
8982 18:10:56.575956 27, 0x0, End_B0=27 End_B1=27
8983 18:10:56.579439 28, 0x0, End_B0=28 End_B1=28
8984 18:10:56.583056 29, 0x0, End_B0=29 End_B1=29
8985 18:10:56.583480 30, 0x0, End_B0=30 End_B1=30
8986 18:10:56.585772 31, 0x4141, End_B0=30 End_B1=30
8987 18:10:56.589147 Byte0 end_step=30 best_step=27
8988 18:10:56.592534 Byte1 end_step=30 best_step=27
8989 18:10:56.595865 Byte0 TX OE(2T, 0.5T) = (3, 3)
8990 18:10:56.599332 Byte1 TX OE(2T, 0.5T) = (3, 3)
8991 18:10:56.599874
8992 18:10:56.600280
8993 18:10:56.605751 [DQSOSCAuto] RK1, (LSB)MR18= 0x2408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8994 18:10:56.609312 CH1 RK1: MR19=303, MR18=2408
8995 18:10:56.615544 CH1_RK1: MR19=0x303, MR18=0x2408, DQSOSC=391, MR23=63, INC=24, DEC=16
8996 18:10:56.619145 [RxdqsGatingPostProcess] freq 1600
8997 18:10:56.625473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8998 18:10:56.625856 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 18:10:56.628977 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 18:10:56.632250 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 18:10:56.635946 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 18:10:56.639139 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 18:10:56.642146 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 18:10:56.646063 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 18:10:56.648558 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 18:10:56.652720 Pre-setting of DQS Precalculation
9007 18:10:56.655799 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9008 18:10:56.662515 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9009 18:10:56.672382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9010 18:10:56.672721
9011 18:10:56.672929
9012 18:10:56.675520 [Calibration Summary] 3200 Mbps
9013 18:10:56.675964 CH 0, Rank 0
9014 18:10:56.678911 SW Impedance : PASS
9015 18:10:56.679337 DUTY Scan : NO K
9016 18:10:56.682365 ZQ Calibration : PASS
9017 18:10:56.685941 Jitter Meter : NO K
9018 18:10:56.686364 CBT Training : PASS
9019 18:10:56.688691 Write leveling : PASS
9020 18:10:56.692372 RX DQS gating : PASS
9021 18:10:56.692935 RX DQ/DQS(RDDQC) : PASS
9022 18:10:56.695304 TX DQ/DQS : PASS
9023 18:10:56.695753 RX DATLAT : PASS
9024 18:10:56.699117 RX DQ/DQS(Engine): PASS
9025 18:10:56.701882 TX OE : PASS
9026 18:10:56.702515 All Pass.
9027 18:10:56.703076
9028 18:10:56.703599 CH 0, Rank 1
9029 18:10:56.705634 SW Impedance : PASS
9030 18:10:56.708417 DUTY Scan : NO K
9031 18:10:56.708941 ZQ Calibration : PASS
9032 18:10:56.711797 Jitter Meter : NO K
9033 18:10:56.714819 CBT Training : PASS
9034 18:10:56.715197 Write leveling : PASS
9035 18:10:56.718583 RX DQS gating : PASS
9036 18:10:56.721429 RX DQ/DQS(RDDQC) : PASS
9037 18:10:56.721704 TX DQ/DQS : PASS
9038 18:10:56.724826 RX DATLAT : PASS
9039 18:10:56.728084 RX DQ/DQS(Engine): PASS
9040 18:10:56.728319 TX OE : PASS
9041 18:10:56.731483 All Pass.
9042 18:10:56.731680
9043 18:10:56.731848 CH 1, Rank 0
9044 18:10:56.735005 SW Impedance : PASS
9045 18:10:56.735107 DUTY Scan : NO K
9046 18:10:56.737959 ZQ Calibration : PASS
9047 18:10:56.742184 Jitter Meter : NO K
9048 18:10:56.742613 CBT Training : PASS
9049 18:10:56.745385 Write leveling : PASS
9050 18:10:56.745626 RX DQS gating : PASS
9051 18:10:56.748242 RX DQ/DQS(RDDQC) : PASS
9052 18:10:56.751937 TX DQ/DQS : PASS
9053 18:10:56.752177 RX DATLAT : PASS
9054 18:10:56.755720 RX DQ/DQS(Engine): PASS
9055 18:10:56.758501 TX OE : PASS
9056 18:10:56.758838 All Pass.
9057 18:10:56.759047
9058 18:10:56.759236 CH 1, Rank 1
9059 18:10:56.761792 SW Impedance : PASS
9060 18:10:56.765415 DUTY Scan : NO K
9061 18:10:56.765666 ZQ Calibration : PASS
9062 18:10:56.768430 Jitter Meter : NO K
9063 18:10:56.771408 CBT Training : PASS
9064 18:10:56.771647 Write leveling : PASS
9065 18:10:56.775018 RX DQS gating : PASS
9066 18:10:56.778405 RX DQ/DQS(RDDQC) : PASS
9067 18:10:56.778643 TX DQ/DQS : PASS
9068 18:10:56.781744 RX DATLAT : PASS
9069 18:10:56.785266 RX DQ/DQS(Engine): PASS
9070 18:10:56.785502 TX OE : PASS
9071 18:10:56.785695 All Pass.
9072 18:10:56.788238
9073 18:10:56.788494 DramC Write-DBI on
9074 18:10:56.791906 PER_BANK_REFRESH: Hybrid Mode
9075 18:10:56.792143 TX_TRACKING: ON
9076 18:10:56.801800 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9077 18:10:56.808185 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9078 18:10:56.818562 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 18:10:56.821966 [FAST_K] Save calibration result to emmc
9080 18:10:56.822473 sync common calibartion params.
9081 18:10:56.824906 sync cbt_mode0:1, 1:1
9082 18:10:56.828283 dram_init: ddr_geometry: 2
9083 18:10:56.831736 dram_init: ddr_geometry: 2
9084 18:10:56.832132 dram_init: ddr_geometry: 2
9085 18:10:56.835018 0:dram_rank_size:100000000
9086 18:10:56.838155 1:dram_rank_size:100000000
9087 18:10:56.841899 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9088 18:10:56.844969 DFS_SHUFFLE_HW_MODE: ON
9089 18:10:56.848146 dramc_set_vcore_voltage set vcore to 725000
9090 18:10:56.851574 Read voltage for 1600, 0
9091 18:10:56.851782 Vio18 = 0
9092 18:10:56.854995 Vcore = 725000
9093 18:10:56.855287 Vdram = 0
9094 18:10:56.855481 Vddq = 0
9095 18:10:56.855610 Vmddr = 0
9096 18:10:56.858205 switch to 3200 Mbps bootup
9097 18:10:56.861917 [DramcRunTimeConfig]
9098 18:10:56.862078 PHYPLL
9099 18:10:56.864605 DPM_CONTROL_AFTERK: ON
9100 18:10:56.864756 PER_BANK_REFRESH: ON
9101 18:10:56.868211 REFRESH_OVERHEAD_REDUCTION: ON
9102 18:10:56.871973 CMD_PICG_NEW_MODE: OFF
9103 18:10:56.872125 XRTWTW_NEW_MODE: ON
9104 18:10:56.874952 XRTRTR_NEW_MODE: ON
9105 18:10:56.875103 TX_TRACKING: ON
9106 18:10:56.878508 RDSEL_TRACKING: OFF
9107 18:10:56.878660 DQS Precalculation for DVFS: ON
9108 18:10:56.881479 RX_TRACKING: OFF
9109 18:10:56.881630 HW_GATING DBG: ON
9110 18:10:56.885346 ZQCS_ENABLE_LP4: ON
9111 18:10:56.888167 RX_PICG_NEW_MODE: ON
9112 18:10:56.888319 TX_PICG_NEW_MODE: ON
9113 18:10:56.891441 ENABLE_RX_DCM_DPHY: ON
9114 18:10:56.894970 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9115 18:10:56.895123 DUMMY_READ_FOR_TRACKING: OFF
9116 18:10:56.898093 !!! SPM_CONTROL_AFTERK: OFF
9117 18:10:56.901498 !!! SPM could not control APHY
9118 18:10:56.905007 IMPEDANCE_TRACKING: ON
9119 18:10:56.905247 TEMP_SENSOR: ON
9120 18:10:56.908079 HW_SAVE_FOR_SR: OFF
9121 18:10:56.911753 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9122 18:10:56.914737 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9123 18:10:56.915037 Read ODT Tracking: ON
9124 18:10:56.918427 Refresh Rate DeBounce: ON
9125 18:10:56.921438 DFS_NO_QUEUE_FLUSH: ON
9126 18:10:56.924706 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9127 18:10:56.925127 ENABLE_DFS_RUNTIME_MRW: OFF
9128 18:10:56.928328 DDR_RESERVE_NEW_MODE: ON
9129 18:10:56.931956 MR_CBT_SWITCH_FREQ: ON
9130 18:10:56.932484 =========================
9131 18:10:56.952012 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9132 18:10:56.954430 dram_init: ddr_geometry: 2
9133 18:10:56.972604 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9134 18:10:56.976135 dram_init: dram init end (result: 0)
9135 18:10:56.982868 DRAM-K: Full calibration passed in 24449 msecs
9136 18:10:56.985891 MRC: failed to locate region type 0.
9137 18:10:56.986108 DRAM rank0 size:0x100000000,
9138 18:10:56.989066 DRAM rank1 size=0x100000000
9139 18:10:56.999151 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9140 18:10:57.006150 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9141 18:10:57.012529 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9142 18:10:57.019031 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9143 18:10:57.022605 DRAM rank0 size:0x100000000,
9144 18:10:57.025803 DRAM rank1 size=0x100000000
9145 18:10:57.026220 CBMEM:
9146 18:10:57.029617 IMD: root @ 0xfffff000 254 entries.
9147 18:10:57.032426 IMD: root @ 0xffffec00 62 entries.
9148 18:10:57.036090 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9149 18:10:57.042838 WARNING: RO_VPD is uninitialized or empty.
9150 18:10:57.045790 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9151 18:10:57.052921 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9152 18:10:57.066016 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9153 18:10:57.077314 BS: romstage times (exec / console): total (unknown) / 23981 ms
9154 18:10:57.077841
9155 18:10:57.078178
9156 18:10:57.086995 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9157 18:10:57.090540 ARM64: Exception handlers installed.
9158 18:10:57.094021 ARM64: Testing exception
9159 18:10:57.097270 ARM64: Done test exception
9160 18:10:57.097681 Enumerating buses...
9161 18:10:57.100180 Show all devs... Before device enumeration.
9162 18:10:57.103762 Root Device: enabled 1
9163 18:10:57.107272 CPU_CLUSTER: 0: enabled 1
9164 18:10:57.107745 CPU: 00: enabled 1
9165 18:10:57.109904 Compare with tree...
9166 18:10:57.110507 Root Device: enabled 1
9167 18:10:57.113570 CPU_CLUSTER: 0: enabled 1
9168 18:10:57.117209 CPU: 00: enabled 1
9169 18:10:57.117504 Root Device scanning...
9170 18:10:57.120211 scan_static_bus for Root Device
9171 18:10:57.123843 CPU_CLUSTER: 0 enabled
9172 18:10:57.126795 scan_static_bus for Root Device done
9173 18:10:57.130221 scan_bus: bus Root Device finished in 8 msecs
9174 18:10:57.130598 done
9175 18:10:57.137177 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9176 18:10:57.140328 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9177 18:10:57.147018 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9178 18:10:57.149982 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9179 18:10:57.153604 Allocating resources...
9180 18:10:57.156787 Reading resources...
9181 18:10:57.160196 Root Device read_resources bus 0 link: 0
9182 18:10:57.160603 DRAM rank0 size:0x100000000,
9183 18:10:57.163932 DRAM rank1 size=0x100000000
9184 18:10:57.166792 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9185 18:10:57.170760 CPU: 00 missing read_resources
9186 18:10:57.173393 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9187 18:10:57.180854 Root Device read_resources bus 0 link: 0 done
9188 18:10:57.181371 Done reading resources.
9189 18:10:57.187111 Show resources in subtree (Root Device)...After reading.
9190 18:10:57.190248 Root Device child on link 0 CPU_CLUSTER: 0
9191 18:10:57.193550 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 18:10:57.203689 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 18:10:57.204223 CPU: 00
9194 18:10:57.207263 Root Device assign_resources, bus 0 link: 0
9195 18:10:57.210075 CPU_CLUSTER: 0 missing set_resources
9196 18:10:57.213605 Root Device assign_resources, bus 0 link: 0 done
9197 18:10:57.216245 Done setting resources.
9198 18:10:57.223561 Show resources in subtree (Root Device)...After assigning values.
9199 18:10:57.226303 Root Device child on link 0 CPU_CLUSTER: 0
9200 18:10:57.229599 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 18:10:57.239764 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 18:10:57.240264 CPU: 00
9203 18:10:57.243413 Done allocating resources.
9204 18:10:57.246169 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9205 18:10:57.249628 Enabling resources...
9206 18:10:57.249849 done.
9207 18:10:57.256075 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9208 18:10:57.256402 Initializing devices...
9209 18:10:57.259587 Root Device init
9210 18:10:57.259809 init hardware done!
9211 18:10:57.262630 0x00000018: ctrlr->caps
9212 18:10:57.266293 52.000 MHz: ctrlr->f_max
9213 18:10:57.266521 0.400 MHz: ctrlr->f_min
9214 18:10:57.269988 0x40ff8080: ctrlr->voltages
9215 18:10:57.270307 sclk: 390625
9216 18:10:57.273123 Bus Width = 1
9217 18:10:57.273468 sclk: 390625
9218 18:10:57.276287 Bus Width = 1
9219 18:10:57.276534 Early init status = 3
9220 18:10:57.282440 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9221 18:10:57.285779 in-header: 03 fc 00 00 01 00 00 00
9222 18:10:57.286042 in-data: 00
9223 18:10:57.292232 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9224 18:10:57.297456 in-header: 03 fd 00 00 00 00 00 00
9225 18:10:57.299587 in-data:
9226 18:10:57.303149 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9227 18:10:57.307212 in-header: 03 fc 00 00 01 00 00 00
9228 18:10:57.310355 in-data: 00
9229 18:10:57.314619 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9230 18:10:57.319354 in-header: 03 fd 00 00 00 00 00 00
9231 18:10:57.323275 in-data:
9232 18:10:57.326026 [SSUSB] Setting up USB HOST controller...
9233 18:10:57.329716 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9234 18:10:57.332923 [SSUSB] phy power-on done.
9235 18:10:57.336386 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9236 18:10:57.342460 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9237 18:10:57.345877 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9238 18:10:57.352895 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9239 18:10:57.359044 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9240 18:10:57.365880 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9241 18:10:57.372544 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9242 18:10:57.378790 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9243 18:10:57.382645 SPM: binary array size = 0x9dc
9244 18:10:57.385585 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9245 18:10:57.392255 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9246 18:10:57.399062 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9247 18:10:57.402306 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9248 18:10:57.408767 configure_display: Starting display init
9249 18:10:57.442608 anx7625_power_on_init: Init interface.
9250 18:10:57.446319 anx7625_disable_pd_protocol: Disabled PD feature.
9251 18:10:57.449861 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9252 18:10:57.476879 anx7625_start_dp_work: Secure OCM version=00
9253 18:10:57.480386 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9254 18:10:57.495360 sp_tx_get_edid_block: EDID Block = 1
9255 18:10:57.597865 Extracted contents:
9256 18:10:57.601230 header: 00 ff ff ff ff ff ff 00
9257 18:10:57.604562 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9258 18:10:57.608170 version: 01 04
9259 18:10:57.610812 basic params: 95 1f 11 78 0a
9260 18:10:57.614249 chroma info: 76 90 94 55 54 90 27 21 50 54
9261 18:10:57.617736 established: 00 00 00
9262 18:10:57.624331 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9263 18:10:57.627285 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9264 18:10:57.634128 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9265 18:10:57.640737 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9266 18:10:57.647077 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9267 18:10:57.650642 extensions: 00
9268 18:10:57.651052 checksum: fb
9269 18:10:57.651385
9270 18:10:57.654156 Manufacturer: IVO Model 57d Serial Number 0
9271 18:10:57.657110 Made week 0 of 2020
9272 18:10:57.657687 EDID version: 1.4
9273 18:10:57.660260 Digital display
9274 18:10:57.663647 6 bits per primary color channel
9275 18:10:57.664068 DisplayPort interface
9276 18:10:57.667585 Maximum image size: 31 cm x 17 cm
9277 18:10:57.670928 Gamma: 220%
9278 18:10:57.671480 Check DPMS levels
9279 18:10:57.673564 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9280 18:10:57.680233 First detailed timing is preferred timing
9281 18:10:57.680770 Established timings supported:
9282 18:10:57.683522 Standard timings supported:
9283 18:10:57.686899 Detailed timings
9284 18:10:57.690051 Hex of detail: 383680a07038204018303c0035ae10000019
9285 18:10:57.697070 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9286 18:10:57.700074 0780 0798 07c8 0820 hborder 0
9287 18:10:57.703964 0438 043b 0447 0458 vborder 0
9288 18:10:57.706946 -hsync -vsync
9289 18:10:57.707356 Did detailed timing
9290 18:10:57.713946 Hex of detail: 000000000000000000000000000000000000
9291 18:10:57.716685 Manufacturer-specified data, tag 0
9292 18:10:57.720293 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9293 18:10:57.723261 ASCII string: InfoVision
9294 18:10:57.726886 Hex of detail: 000000fe00523134304e574635205248200a
9295 18:10:57.729666 ASCII string: R140NWF5 RH
9296 18:10:57.730125 Checksum
9297 18:10:57.733269 Checksum: 0xfb (valid)
9298 18:10:57.736634 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9299 18:10:57.739671 DSI data_rate: 832800000 bps
9300 18:10:57.746523 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9301 18:10:57.750051 anx7625_parse_edid: pixelclock(138800).
9302 18:10:57.752890 hactive(1920), hsync(48), hfp(24), hbp(88)
9303 18:10:57.756295 vactive(1080), vsync(12), vfp(3), vbp(17)
9304 18:10:57.759927 anx7625_dsi_config: config dsi.
9305 18:10:57.766062 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9306 18:10:57.779988 anx7625_dsi_config: success to config DSI
9307 18:10:57.783282 anx7625_dp_start: MIPI phy setup OK.
9308 18:10:57.786853 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9309 18:10:57.789958 mtk_ddp_mode_set invalid vrefresh 60
9310 18:10:57.793319 main_disp_path_setup
9311 18:10:57.793913 ovl_layer_smi_id_en
9312 18:10:57.795917 ovl_layer_smi_id_en
9313 18:10:57.796329 ccorr_config
9314 18:10:57.796687 aal_config
9315 18:10:57.799485 gamma_config
9316 18:10:57.799903 postmask_config
9317 18:10:57.802684 dither_config
9318 18:10:57.806910 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9319 18:10:57.812777 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9320 18:10:57.816335 Root Device init finished in 553 msecs
9321 18:10:57.819547 CPU_CLUSTER: 0 init
9322 18:10:57.826428 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9323 18:10:57.829278 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9324 18:10:57.832975 APU_MBOX 0x190000b0 = 0x10001
9325 18:10:57.835857 APU_MBOX 0x190001b0 = 0x10001
9326 18:10:57.839514 APU_MBOX 0x190005b0 = 0x10001
9327 18:10:57.843021 APU_MBOX 0x190006b0 = 0x10001
9328 18:10:57.845873 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9329 18:10:57.858760 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9330 18:10:57.871512 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9331 18:10:57.877524 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9332 18:10:57.889525 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9333 18:10:57.898369 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9334 18:10:57.901945 CPU_CLUSTER: 0 init finished in 81 msecs
9335 18:10:57.904922 Devices initialized
9336 18:10:57.908529 Show all devs... After init.
9337 18:10:57.908942 Root Device: enabled 1
9338 18:10:57.912102 CPU_CLUSTER: 0: enabled 1
9339 18:10:57.914862 CPU: 00: enabled 1
9340 18:10:57.918457 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9341 18:10:57.921933 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9342 18:10:57.924596 ELOG: NV offset 0x57f000 size 0x1000
9343 18:10:57.931529 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9344 18:10:57.937765 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9345 18:10:57.941182 ELOG: Event(17) added with size 13 at 2024-06-11 18:06:14 UTC
9346 18:10:57.948210 out: cmd=0x121: 03 db 21 01 00 00 00 00
9347 18:10:57.951149 in-header: 03 e5 00 00 2c 00 00 00
9348 18:10:57.960929 in-data: 7a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 18:10:57.968054 ELOG: Event(A1) added with size 10 at 2024-06-11 18:06:14 UTC
9350 18:10:57.974479 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9351 18:10:57.981074 ELOG: Event(A0) added with size 9 at 2024-06-11 18:06:15 UTC
9352 18:10:57.984483 elog_add_boot_reason: Logged dev mode boot
9353 18:10:57.991163 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9354 18:10:57.991334 Finalize devices...
9355 18:10:57.994003 Devices finalized
9356 18:10:57.997453 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9357 18:10:58.000654 Writing coreboot table at 0xffe64000
9358 18:10:58.003954 0. 000000000010a000-0000000000113fff: RAMSTAGE
9359 18:10:58.007323 1. 0000000040000000-00000000400fffff: RAM
9360 18:10:58.014508 2. 0000000040100000-000000004032afff: RAMSTAGE
9361 18:10:58.017321 3. 000000004032b000-00000000545fffff: RAM
9362 18:10:58.021024 4. 0000000054600000-000000005465ffff: BL31
9363 18:10:58.023852 5. 0000000054660000-00000000ffe63fff: RAM
9364 18:10:58.031146 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9365 18:10:58.034865 7. 0000000100000000-000000023fffffff: RAM
9366 18:10:58.038193 Passing 5 GPIOs to payload:
9367 18:10:58.040871 NAME | PORT | POLARITY | VALUE
9368 18:10:58.044316 EC in RW | 0x000000aa | low | undefined
9369 18:10:58.051012 EC interrupt | 0x00000005 | low | undefined
9370 18:10:58.054633 TPM interrupt | 0x000000ab | high | undefined
9371 18:10:58.061329 SD card detect | 0x00000011 | high | undefined
9372 18:10:58.064431 speaker enable | 0x00000093 | high | undefined
9373 18:10:58.068164 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9374 18:10:58.071006 in-header: 03 f9 00 00 02 00 00 00
9375 18:10:58.074456 in-data: 02 00
9376 18:10:58.074872 ADC[4]: Raw value=904357 ID=7
9377 18:10:58.078233 ADC[3]: Raw value=213441 ID=1
9378 18:10:58.080892 RAM Code: 0x71
9379 18:10:58.081310 ADC[6]: Raw value=75701 ID=0
9380 18:10:58.084619 ADC[5]: Raw value=212703 ID=1
9381 18:10:58.087765 SKU Code: 0x1
9382 18:10:58.090871 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f641
9383 18:10:58.094228 coreboot table: 964 bytes.
9384 18:10:58.098076 IMD ROOT 0. 0xfffff000 0x00001000
9385 18:10:58.100845 IMD SMALL 1. 0xffffe000 0x00001000
9386 18:10:58.104638 RO MCACHE 2. 0xffffc000 0x00001104
9387 18:10:58.107522 CONSOLE 3. 0xfff7c000 0x00080000
9388 18:10:58.110873 FMAP 4. 0xfff7b000 0x00000452
9389 18:10:58.114535 TIME STAMP 5. 0xfff7a000 0x00000910
9390 18:10:58.117623 VBOOT WORK 6. 0xfff66000 0x00014000
9391 18:10:58.121281 RAMOOPS 7. 0xffe66000 0x00100000
9392 18:10:58.124357 COREBOOT 8. 0xffe64000 0x00002000
9393 18:10:58.124884 IMD small region:
9394 18:10:58.127869 IMD ROOT 0. 0xffffec00 0x00000400
9395 18:10:58.131113 VPD 1. 0xffffeb80 0x0000006c
9396 18:10:58.137728 MMC STATUS 2. 0xffffeb60 0x00000004
9397 18:10:58.141152 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9398 18:10:58.143987 Probing TPM: done!
9399 18:10:58.147381 Connected to device vid:did:rid of 1ae0:0028:00
9400 18:10:58.157382 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9401 18:10:58.160866 Initialized TPM device CR50 revision 0
9402 18:10:58.164268 Checking cr50 for pending updates
9403 18:10:58.167852 Reading cr50 TPM mode
9404 18:10:58.176485 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9405 18:10:58.183920 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9406 18:10:58.224032 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9407 18:10:58.226764 Checking segment from ROM address 0x40100000
9408 18:10:58.230364 Checking segment from ROM address 0x4010001c
9409 18:10:58.237029 Loading segment from ROM address 0x40100000
9410 18:10:58.237442 code (compression=0)
9411 18:10:58.246710 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9412 18:10:58.253888 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9413 18:10:58.254336 it's not compressed!
9414 18:10:58.260119 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9415 18:10:58.263464 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9416 18:10:58.284042 Loading segment from ROM address 0x4010001c
9417 18:10:58.284709 Entry Point 0x80000000
9418 18:10:58.287472 Loaded segments
9419 18:10:58.290788 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9420 18:10:58.297316 Jumping to boot code at 0x80000000(0xffe64000)
9421 18:10:58.304435 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9422 18:10:58.310549 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9423 18:10:58.318269 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9424 18:10:58.321683 Checking segment from ROM address 0x40100000
9425 18:10:58.324368 Checking segment from ROM address 0x4010001c
9426 18:10:58.331529 Loading segment from ROM address 0x40100000
9427 18:10:58.331611 code (compression=1)
9428 18:10:58.338489 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9429 18:10:58.347906 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9430 18:10:58.347995 using LZMA
9431 18:10:58.356678 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9432 18:10:58.363411 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9433 18:10:58.366999 Loading segment from ROM address 0x4010001c
9434 18:10:58.367197 Entry Point 0x54601000
9435 18:10:58.370279 Loaded segments
9436 18:10:58.373014 NOTICE: MT8192 bl31_setup
9437 18:10:58.380141 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9438 18:10:58.383697 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9439 18:10:58.387502 WARNING: region 0:
9440 18:10:58.390843 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 18:10:58.391104 WARNING: region 1:
9442 18:10:58.397598 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9443 18:10:58.400384 WARNING: region 2:
9444 18:10:58.404181 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9445 18:10:58.407526 WARNING: region 3:
9446 18:10:58.410604 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 18:10:58.413685 WARNING: region 4:
9448 18:10:58.417216 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 18:10:58.420383 WARNING: region 5:
9450 18:10:58.423669 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 18:10:58.426999 WARNING: region 6:
9452 18:10:58.430534 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 18:10:58.431051 WARNING: region 7:
9454 18:10:58.436921 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 18:10:58.444185 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9456 18:10:58.447690 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9457 18:10:58.450515 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9458 18:10:58.457016 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9459 18:10:58.460874 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9460 18:10:58.463663 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9461 18:10:58.471040 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9462 18:10:58.473876 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9463 18:10:58.477450 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9464 18:10:58.483754 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9465 18:10:58.487160 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9466 18:10:58.493945 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9467 18:10:58.497400 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9468 18:10:58.500731 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9469 18:10:58.507410 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9470 18:10:58.510739 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9471 18:10:58.514419 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9472 18:10:58.520815 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9473 18:10:58.524271 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9474 18:10:58.527575 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9475 18:10:58.534226 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9476 18:10:58.537714 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9477 18:10:58.544244 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9478 18:10:58.547537 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9479 18:10:58.550658 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9480 18:10:58.557386 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9481 18:10:58.560789 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9482 18:10:58.567401 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9483 18:10:58.570956 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9484 18:10:58.574633 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9485 18:10:58.581249 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9486 18:10:58.584151 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9487 18:10:58.587136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9488 18:10:58.594260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9489 18:10:58.597554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9490 18:10:58.601094 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9491 18:10:58.604287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9492 18:10:58.610652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9493 18:10:58.614155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9494 18:10:58.617676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9495 18:10:58.620613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9496 18:10:58.627529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9497 18:10:58.631483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9498 18:10:58.633943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9499 18:10:58.637379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9500 18:10:58.644078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9501 18:10:58.647249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9502 18:10:58.650891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9503 18:10:58.657668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9504 18:10:58.660986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9505 18:10:58.664902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9506 18:10:58.671211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9507 18:10:58.674710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9508 18:10:58.681066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9509 18:10:58.684059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9510 18:10:58.691235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9511 18:10:58.694017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9512 18:10:58.697713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9513 18:10:58.704211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9514 18:10:58.707969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9515 18:10:58.714533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9516 18:10:58.717580 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9517 18:10:58.724144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9518 18:10:58.727789 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9519 18:10:58.731606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9520 18:10:58.738182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9521 18:10:58.740669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9522 18:10:58.747813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9523 18:10:58.750998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9524 18:10:58.758167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9525 18:10:58.761234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9526 18:10:58.764838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9527 18:10:58.770858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9528 18:10:58.774399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9529 18:10:58.781223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9530 18:10:58.784447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9531 18:10:58.791360 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9532 18:10:58.794008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9533 18:10:58.797717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9534 18:10:58.804159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9535 18:10:58.807874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9536 18:10:58.814367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9537 18:10:58.817976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9538 18:10:58.824205 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9539 18:10:58.827710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9540 18:10:58.830883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9541 18:10:58.837674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9542 18:10:58.840819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9543 18:10:58.847352 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9544 18:10:58.850829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9545 18:10:58.857638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9546 18:10:58.861318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9547 18:10:58.864854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9548 18:10:58.871470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9549 18:10:58.874682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9550 18:10:58.881382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9551 18:10:58.884912 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9552 18:10:58.888117 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9553 18:10:58.891276 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9554 18:10:58.897795 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9555 18:10:58.901135 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9556 18:10:58.904373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9557 18:10:58.911468 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9558 18:10:58.914388 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9559 18:10:58.921575 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9560 18:10:58.924648 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9561 18:10:58.927553 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9562 18:10:58.934694 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9563 18:10:58.937407 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9564 18:10:58.944331 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9565 18:10:58.947829 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9566 18:10:58.950994 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9567 18:10:58.958077 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9568 18:10:58.961750 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9569 18:10:58.968024 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9570 18:10:58.971506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9571 18:10:58.974612 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9572 18:10:58.977864 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9573 18:10:58.984885 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9574 18:10:58.987833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9575 18:10:58.990894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9576 18:10:58.994637 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9577 18:10:59.000993 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9578 18:10:59.004567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9579 18:10:59.008142 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9580 18:10:59.014877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9581 18:10:59.018358 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9582 18:10:59.025247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9583 18:10:59.028561 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9584 18:10:59.031317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9585 18:10:59.038037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9586 18:10:59.041625 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9587 18:10:59.045215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9588 18:10:59.051391 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9589 18:10:59.054811 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9590 18:10:59.061150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9591 18:10:59.064302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9592 18:10:59.067471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9593 18:10:59.074337 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9594 18:10:59.077825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9595 18:10:59.084881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9596 18:10:59.087904 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9597 18:10:59.091293 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9598 18:10:59.097620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9599 18:10:59.101385 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9600 18:10:59.104585 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9601 18:10:59.111489 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9602 18:10:59.114359 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9603 18:10:59.120709 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9604 18:10:59.124669 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9605 18:10:59.127915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9606 18:10:59.134808 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9607 18:10:59.138548 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9608 18:10:59.144531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9609 18:10:59.148297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9610 18:10:59.151800 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9611 18:10:59.158860 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9612 18:10:59.161287 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9613 18:10:59.165126 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9614 18:10:59.171192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9615 18:10:59.174751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9616 18:10:59.181854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9617 18:10:59.184453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9618 18:10:59.188421 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9619 18:10:59.194557 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9620 18:10:59.198014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9621 18:10:59.204428 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9622 18:10:59.207956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9623 18:10:59.211274 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9624 18:10:59.217670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9625 18:10:59.221560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9626 18:10:59.227406 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9627 18:10:59.231039 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9628 18:10:59.234532 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9629 18:10:59.241188 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9630 18:10:59.244405 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9631 18:10:59.250790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9632 18:10:59.254324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9633 18:10:59.257344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9634 18:10:59.264220 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9635 18:10:59.267361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9636 18:10:59.270549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9637 18:10:59.277289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9638 18:10:59.281164 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9639 18:10:59.287297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9640 18:10:59.290613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9641 18:10:59.294108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9642 18:10:59.300493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9643 18:10:59.304265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9644 18:10:59.310942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9645 18:10:59.314670 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9646 18:10:59.321034 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9647 18:10:59.323786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9648 18:10:59.327867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9649 18:10:59.334150 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9650 18:10:59.337357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9651 18:10:59.343490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9652 18:10:59.347149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9653 18:10:59.350619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9654 18:10:59.357387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9655 18:10:59.360133 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9656 18:10:59.366739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9657 18:10:59.370239 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9658 18:10:59.377368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9659 18:10:59.380129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9660 18:10:59.383846 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9661 18:10:59.390299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9662 18:10:59.393733 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9663 18:10:59.400328 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9664 18:10:59.403699 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9665 18:10:59.406518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9666 18:10:59.413190 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9667 18:10:59.416879 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9668 18:10:59.423817 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9669 18:10:59.427475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9670 18:10:59.433647 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9671 18:10:59.436443 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9672 18:10:59.440330 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9673 18:10:59.446978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9674 18:10:59.450267 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9675 18:10:59.456567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9676 18:10:59.460530 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9677 18:10:59.463464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9678 18:10:59.470020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9679 18:10:59.473424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9680 18:10:59.479756 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9681 18:10:59.483082 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9682 18:10:59.490128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9683 18:10:59.492951 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9684 18:10:59.496492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9685 18:10:59.499336 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9686 18:10:59.506340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9687 18:10:59.509490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9688 18:10:59.512927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9689 18:10:59.515729 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9690 18:10:59.523154 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9691 18:10:59.526641 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9692 18:10:59.532877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9693 18:10:59.536365 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9694 18:10:59.539687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9695 18:10:59.546187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9696 18:10:59.549796 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9697 18:10:59.553165 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9698 18:10:59.559695 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9699 18:10:59.563381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9700 18:10:59.566401 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9701 18:10:59.572713 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9702 18:10:59.576272 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9703 18:10:59.579494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9704 18:10:59.586829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9705 18:10:59.589339 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9706 18:10:59.596150 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9707 18:10:59.599470 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9708 18:10:59.603081 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9709 18:10:59.609282 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9710 18:10:59.612835 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9711 18:10:59.619033 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9712 18:10:59.622398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9713 18:10:59.625756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9714 18:10:59.632078 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9715 18:10:59.635704 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9716 18:10:59.639617 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9717 18:10:59.645624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9718 18:10:59.648581 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9719 18:10:59.652040 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9720 18:10:59.658808 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9721 18:10:59.661879 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9722 18:10:59.668671 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9723 18:10:59.672105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9724 18:10:59.675778 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9725 18:10:59.678649 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9726 18:10:59.685560 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9727 18:10:59.689062 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9728 18:10:59.691762 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9729 18:10:59.695216 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9730 18:10:59.698971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9731 18:10:59.705626 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9732 18:10:59.709105 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9733 18:10:59.712521 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9734 18:10:59.715293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9735 18:10:59.721704 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9736 18:10:59.725312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9737 18:10:59.731875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9738 18:10:59.735338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9739 18:10:59.738864 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9740 18:10:59.745227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9741 18:10:59.748714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9742 18:10:59.755271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9743 18:10:59.758076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9744 18:10:59.761721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9745 18:10:59.768267 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9746 18:10:59.771793 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9747 18:10:59.778543 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9748 18:10:59.781562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9749 18:10:59.788668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9750 18:10:59.791758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9751 18:10:59.795091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9752 18:10:59.801414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9753 18:10:59.804917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9754 18:10:59.811399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9755 18:10:59.814933 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9756 18:10:59.818025 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9757 18:10:59.824605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9758 18:10:59.828099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9759 18:10:59.834760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9760 18:10:59.838060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9761 18:10:59.841716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9762 18:10:59.847986 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9763 18:10:59.851401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9764 18:10:59.857596 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9765 18:10:59.861302 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9766 18:10:59.867746 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9767 18:10:59.870655 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9768 18:10:59.874330 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9769 18:10:59.880689 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9770 18:10:59.884159 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9771 18:10:59.890714 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9772 18:10:59.894025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9773 18:10:59.897460 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9774 18:10:59.903694 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9775 18:10:59.907316 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9776 18:10:59.913758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9777 18:10:59.917539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9778 18:10:59.920213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9779 18:10:59.927467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9780 18:10:59.930875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9781 18:10:59.936864 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9782 18:10:59.940298 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9783 18:10:59.947042 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9784 18:10:59.949891 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9785 18:10:59.953239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9786 18:10:59.960360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9787 18:10:59.963479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9788 18:10:59.970256 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9789 18:10:59.973264 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9790 18:10:59.976895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9791 18:10:59.983303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9792 18:10:59.986919 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9793 18:10:59.993404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9794 18:10:59.997137 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9795 18:11:00.000087 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9796 18:11:00.006951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9797 18:11:00.010142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9798 18:11:00.016586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9799 18:11:00.020298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9800 18:11:00.023117 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9801 18:11:00.030264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9802 18:11:00.033301 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9803 18:11:00.039647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9804 18:11:00.043182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9805 18:11:00.050143 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9806 18:11:00.052986 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9807 18:11:00.056309 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9808 18:11:00.063373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9809 18:11:00.066271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9810 18:11:00.072908 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9811 18:11:00.076639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9812 18:11:00.079705 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9813 18:11:00.086659 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9814 18:11:00.090055 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9815 18:11:00.096469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9816 18:11:00.099991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9817 18:11:00.106464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9818 18:11:00.109998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9819 18:11:00.113190 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9820 18:11:00.120231 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9821 18:11:00.122880 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9822 18:11:00.129947 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9823 18:11:00.132932 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9824 18:11:00.139465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9825 18:11:00.143014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9826 18:11:00.146063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9827 18:11:00.153024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9828 18:11:00.155756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9829 18:11:00.163087 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9830 18:11:00.165960 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9831 18:11:00.172489 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9832 18:11:00.176018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9833 18:11:00.182566 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9834 18:11:00.185940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9835 18:11:00.192321 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9836 18:11:00.195565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9837 18:11:00.198719 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9838 18:11:00.205713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9839 18:11:00.209373 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9840 18:11:00.215810 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9841 18:11:00.219379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9842 18:11:00.225833 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9843 18:11:00.229008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9844 18:11:00.232241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9845 18:11:00.238787 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9846 18:11:00.242590 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9847 18:11:00.248985 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9848 18:11:00.251857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9849 18:11:00.259023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9850 18:11:00.262287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9851 18:11:00.265387 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9852 18:11:00.271769 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9853 18:11:00.275427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9854 18:11:00.282319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9855 18:11:00.285736 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9856 18:11:00.291994 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9857 18:11:00.295545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9858 18:11:00.298506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9859 18:11:00.305627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9860 18:11:00.308945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9861 18:11:00.315071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9862 18:11:00.318327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9863 18:11:00.325396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9864 18:11:00.328998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9865 18:11:00.335415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9866 18:11:00.338857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9867 18:11:00.345509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9868 18:11:00.348771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9869 18:11:00.355347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9870 18:11:00.358742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9871 18:11:00.364924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9872 18:11:00.368599 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9873 18:11:00.374844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9874 18:11:00.378617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9875 18:11:00.384933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9876 18:11:00.388456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9877 18:11:00.392000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9878 18:11:00.398146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9879 18:11:00.404723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9880 18:11:00.408316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9881 18:11:00.414787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9882 18:11:00.418352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9883 18:11:00.424941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9884 18:11:00.428298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9885 18:11:00.435055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9886 18:11:00.437786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9887 18:11:00.444843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9888 18:11:00.448309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9889 18:11:00.451068 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9890 18:11:00.454637 INFO: [APUAPC] vio 0
9891 18:11:00.457994 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9892 18:11:00.465098 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9893 18:11:00.468380 INFO: [APUAPC] D0_APC_0: 0x400510
9894 18:11:00.471647 INFO: [APUAPC] D0_APC_1: 0x0
9895 18:11:00.475037 INFO: [APUAPC] D0_APC_2: 0x1540
9896 18:11:00.475564 INFO: [APUAPC] D0_APC_3: 0x0
9897 18:11:00.477732 INFO: [APUAPC] D1_APC_0: 0xffffffff
9898 18:11:00.484905 INFO: [APUAPC] D1_APC_1: 0xffffffff
9899 18:11:00.485321 INFO: [APUAPC] D1_APC_2: 0x3fffff
9900 18:11:00.487759 INFO: [APUAPC] D1_APC_3: 0x0
9901 18:11:00.491413 INFO: [APUAPC] D2_APC_0: 0xffffffff
9902 18:11:00.494498 INFO: [APUAPC] D2_APC_1: 0xffffffff
9903 18:11:00.498101 INFO: [APUAPC] D2_APC_2: 0x3fffff
9904 18:11:00.501045 INFO: [APUAPC] D2_APC_3: 0x0
9905 18:11:00.504609 INFO: [APUAPC] D3_APC_0: 0xffffffff
9906 18:11:00.507890 INFO: [APUAPC] D3_APC_1: 0xffffffff
9907 18:11:00.511299 INFO: [APUAPC] D3_APC_2: 0x3fffff
9908 18:11:00.514463 INFO: [APUAPC] D3_APC_3: 0x0
9909 18:11:00.517679 INFO: [APUAPC] D4_APC_0: 0xffffffff
9910 18:11:00.520902 INFO: [APUAPC] D4_APC_1: 0xffffffff
9911 18:11:00.524445 INFO: [APUAPC] D4_APC_2: 0x3fffff
9912 18:11:00.527416 INFO: [APUAPC] D4_APC_3: 0x0
9913 18:11:00.531232 INFO: [APUAPC] D5_APC_0: 0xffffffff
9914 18:11:00.534022 INFO: [APUAPC] D5_APC_1: 0xffffffff
9915 18:11:00.537546 INFO: [APUAPC] D5_APC_2: 0x3fffff
9916 18:11:00.540856 INFO: [APUAPC] D5_APC_3: 0x0
9917 18:11:00.543972 INFO: [APUAPC] D6_APC_0: 0xffffffff
9918 18:11:00.547355 INFO: [APUAPC] D6_APC_1: 0xffffffff
9919 18:11:00.550648 INFO: [APUAPC] D6_APC_2: 0x3fffff
9920 18:11:00.554519 INFO: [APUAPC] D6_APC_3: 0x0
9921 18:11:00.557314 INFO: [APUAPC] D7_APC_0: 0xffffffff
9922 18:11:00.560699 INFO: [APUAPC] D7_APC_1: 0xffffffff
9923 18:11:00.564332 INFO: [APUAPC] D7_APC_2: 0x3fffff
9924 18:11:00.567907 INFO: [APUAPC] D7_APC_3: 0x0
9925 18:11:00.570842 INFO: [APUAPC] D8_APC_0: 0xffffffff
9926 18:11:00.574500 INFO: [APUAPC] D8_APC_1: 0xffffffff
9927 18:11:00.577883 INFO: [APUAPC] D8_APC_2: 0x3fffff
9928 18:11:00.581326 INFO: [APUAPC] D8_APC_3: 0x0
9929 18:11:00.584021 INFO: [APUAPC] D9_APC_0: 0xffffffff
9930 18:11:00.587326 INFO: [APUAPC] D9_APC_1: 0xffffffff
9931 18:11:00.591044 INFO: [APUAPC] D9_APC_2: 0x3fffff
9932 18:11:00.593924 INFO: [APUAPC] D9_APC_3: 0x0
9933 18:11:00.597611 INFO: [APUAPC] D10_APC_0: 0xffffffff
9934 18:11:00.600508 INFO: [APUAPC] D10_APC_1: 0xffffffff
9935 18:11:00.604097 INFO: [APUAPC] D10_APC_2: 0x3fffff
9936 18:11:00.607732 INFO: [APUAPC] D10_APC_3: 0x0
9937 18:11:00.610723 INFO: [APUAPC] D11_APC_0: 0xffffffff
9938 18:11:00.614507 INFO: [APUAPC] D11_APC_1: 0xffffffff
9939 18:11:00.617195 INFO: [APUAPC] D11_APC_2: 0x3fffff
9940 18:11:00.620639 INFO: [APUAPC] D11_APC_3: 0x0
9941 18:11:00.624036 INFO: [APUAPC] D12_APC_0: 0xffffffff
9942 18:11:00.627366 INFO: [APUAPC] D12_APC_1: 0xffffffff
9943 18:11:00.630654 INFO: [APUAPC] D12_APC_2: 0x3fffff
9944 18:11:00.633794 INFO: [APUAPC] D12_APC_3: 0x0
9945 18:11:00.637366 INFO: [APUAPC] D13_APC_0: 0xffffffff
9946 18:11:00.640266 INFO: [APUAPC] D13_APC_1: 0xffffffff
9947 18:11:00.644052 INFO: [APUAPC] D13_APC_2: 0x3fffff
9948 18:11:00.646846 INFO: [APUAPC] D13_APC_3: 0x0
9949 18:11:00.650334 INFO: [APUAPC] D14_APC_0: 0xffffffff
9950 18:11:00.653374 INFO: [APUAPC] D14_APC_1: 0xffffffff
9951 18:11:00.656853 INFO: [APUAPC] D14_APC_2: 0x3fffff
9952 18:11:00.659998 INFO: [APUAPC] D14_APC_3: 0x0
9953 18:11:00.663170 INFO: [APUAPC] D15_APC_0: 0xffffffff
9954 18:11:00.666515 INFO: [APUAPC] D15_APC_1: 0xffffffff
9955 18:11:00.669807 INFO: [APUAPC] D15_APC_2: 0x3fffff
9956 18:11:00.673136 INFO: [APUAPC] D15_APC_3: 0x0
9957 18:11:00.676634 INFO: [APUAPC] APC_CON: 0x4
9958 18:11:00.679992 INFO: [NOCDAPC] D0_APC_0: 0x0
9959 18:11:00.680096 INFO: [NOCDAPC] D0_APC_1: 0x0
9960 18:11:00.683404 INFO: [NOCDAPC] D1_APC_0: 0x0
9961 18:11:00.687002 INFO: [NOCDAPC] D1_APC_1: 0xfff
9962 18:11:00.689845 INFO: [NOCDAPC] D2_APC_0: 0x0
9963 18:11:00.693319 INFO: [NOCDAPC] D2_APC_1: 0xfff
9964 18:11:00.696725 INFO: [NOCDAPC] D3_APC_0: 0x0
9965 18:11:00.699634 INFO: [NOCDAPC] D3_APC_1: 0xfff
9966 18:11:00.703312 INFO: [NOCDAPC] D4_APC_0: 0x0
9967 18:11:00.706995 INFO: [NOCDAPC] D4_APC_1: 0xfff
9968 18:11:00.709864 INFO: [NOCDAPC] D5_APC_0: 0x0
9969 18:11:00.713372 INFO: [NOCDAPC] D5_APC_1: 0xfff
9970 18:11:00.713454 INFO: [NOCDAPC] D6_APC_0: 0x0
9971 18:11:00.716380 INFO: [NOCDAPC] D6_APC_1: 0xfff
9972 18:11:00.720103 INFO: [NOCDAPC] D7_APC_0: 0x0
9973 18:11:00.723001 INFO: [NOCDAPC] D7_APC_1: 0xfff
9974 18:11:00.726613 INFO: [NOCDAPC] D8_APC_0: 0x0
9975 18:11:00.730043 INFO: [NOCDAPC] D8_APC_1: 0xfff
9976 18:11:00.732887 INFO: [NOCDAPC] D9_APC_0: 0x0
9977 18:11:00.736988 INFO: [NOCDAPC] D9_APC_1: 0xfff
9978 18:11:00.740051 INFO: [NOCDAPC] D10_APC_0: 0x0
9979 18:11:00.743309 INFO: [NOCDAPC] D10_APC_1: 0xfff
9980 18:11:00.746676 INFO: [NOCDAPC] D11_APC_0: 0x0
9981 18:11:00.749990 INFO: [NOCDAPC] D11_APC_1: 0xfff
9982 18:11:00.750071 INFO: [NOCDAPC] D12_APC_0: 0x0
9983 18:11:00.752829 INFO: [NOCDAPC] D12_APC_1: 0xfff
9984 18:11:00.756503 INFO: [NOCDAPC] D13_APC_0: 0x0
9985 18:11:00.760009 INFO: [NOCDAPC] D13_APC_1: 0xfff
9986 18:11:00.762720 INFO: [NOCDAPC] D14_APC_0: 0x0
9987 18:11:00.766013 INFO: [NOCDAPC] D14_APC_1: 0xfff
9988 18:11:00.769755 INFO: [NOCDAPC] D15_APC_0: 0x0
9989 18:11:00.772996 INFO: [NOCDAPC] D15_APC_1: 0xfff
9990 18:11:00.776221 INFO: [NOCDAPC] APC_CON: 0x4
9991 18:11:00.779561 INFO: [APUAPC] set_apusys_apc done
9992 18:11:00.782623 INFO: [DEVAPC] devapc_init done
9993 18:11:00.786131 INFO: GICv3 without legacy support detected.
9994 18:11:00.789721 INFO: ARM GICv3 driver initialized in EL3
9995 18:11:00.792614 INFO: Maximum SPI INTID supported: 639
9996 18:11:00.799434 INFO: BL31: Initializing runtime services
9997 18:11:00.802710 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9998 18:11:00.806255 INFO: SPM: enable CPC mode
9999 18:11:00.812695 INFO: mcdi ready for mcusys-off-idle and system suspend
10000 18:11:00.816375 INFO: BL31: Preparing for EL3 exit to normal world
10001 18:11:00.819332 INFO: Entry point address = 0x80000000
10002 18:11:00.822939 INFO: SPSR = 0x8
10003 18:11:00.828146
10004 18:11:00.828318
10005 18:11:00.828430
10006 18:11:00.831687 Starting depthcharge on Spherion...
10007 18:11:00.831806
10008 18:11:00.831900 Wipe memory regions:
10009 18:11:00.831977
10010 18:11:00.832713 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10011 18:11:00.832837 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 18:11:00.832959 Setting prompt string to ['asurada:']
10013 18:11:00.833056 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 18:11:00.834985 [0x00000040000000, 0x00000054600000)
10015 18:11:00.956769
10016 18:11:00.956895 [0x00000054660000, 0x00000080000000)
10017 18:11:01.217521
10018 18:11:01.217675 [0x000000821a7280, 0x000000ffe64000)
10019 18:11:01.962334
10020 18:11:01.962832 [0x00000100000000, 0x00000240000000)
10021 18:11:03.851680
10022 18:11:03.855167 Initializing XHCI USB controller at 0x11200000.
10023 18:11:04.892538
10024 18:11:04.895807 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10025 18:11:04.895900
10026 18:11:04.895968
10027 18:11:04.896292 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 18:11:04.996667 asurada: tftpboot 192.168.201.1 14291441/tftp-deploy-_9_2ntuc/kernel/image.itb 14291441/tftp-deploy-_9_2ntuc/kernel/cmdline
10030 18:11:04.996853 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 18:11:04.996964 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10032 18:11:05.000857 tftpboot 192.168.201.1 14291441/tftp-deploy-_9_2ntuc/kernel/image.itp-deploy-_9_2ntuc/kernel/cmdline
10033 18:11:05.000944
10034 18:11:05.001009 Waiting for link
10035 18:11:05.161583
10036 18:11:05.161731 R8152: Initializing
10037 18:11:05.161800
10038 18:11:05.165053 Version 9 (ocp_data = 6010)
10039 18:11:05.165135
10040 18:11:05.167740 R8152: Done initializing
10041 18:11:05.167835
10042 18:11:05.167901 Adding net device
10043 18:11:07.114868
10044 18:11:07.115017 done.
10045 18:11:07.115083
10046 18:11:07.115143 MAC: 00:e0:4c:78:7a:aa
10047 18:11:07.115202
10048 18:11:07.118178 Sending DHCP discover... done.
10049 18:11:07.118281
10050 18:11:07.121043 Waiting for reply... done.
10051 18:11:07.121125
10052 18:11:07.124714 Sending DHCP request... done.
10053 18:11:07.124796
10054 18:11:07.124861 Waiting for reply... done.
10055 18:11:07.124923
10056 18:11:07.128089 My ip is 192.168.201.12
10057 18:11:07.128169
10058 18:11:07.131322 The DHCP server ip is 192.168.201.1
10059 18:11:07.131403
10060 18:11:07.134439 TFTP server IP predefined by user: 192.168.201.1
10061 18:11:07.134565
10062 18:11:07.141480 Bootfile predefined by user: 14291441/tftp-deploy-_9_2ntuc/kernel/image.itb
10063 18:11:07.141571
10064 18:11:07.144187 Sending tftp read request... done.
10065 18:11:07.144271
10066 18:11:07.147786 Waiting for the transfer...
10067 18:11:07.147869
10068 18:11:07.404962 00000000 ################################################################
10069 18:11:07.405138
10070 18:11:07.656010 00080000 ################################################################
10071 18:11:07.656179
10072 18:11:07.909347 00100000 ################################################################
10073 18:11:07.909508
10074 18:11:08.169524 00180000 ################################################################
10075 18:11:08.169660
10076 18:11:08.422950 00200000 ################################################################
10077 18:11:08.423175
10078 18:11:08.676200 00280000 ################################################################
10079 18:11:08.676386
10080 18:11:08.909943 00300000 ################################################################
10081 18:11:08.910082
10082 18:11:09.164858 00380000 ################################################################
10083 18:11:09.165030
10084 18:11:09.435864 00400000 ################################################################
10085 18:11:09.436083
10086 18:11:09.700678 00480000 ################################################################
10087 18:11:09.700866
10088 18:11:09.963278 00500000 ################################################################
10089 18:11:09.963429
10090 18:11:10.232434 00580000 ################################################################
10091 18:11:10.232582
10092 18:11:10.488291 00600000 ################################################################
10093 18:11:10.488463
10094 18:11:10.747639 00680000 ################################################################
10095 18:11:10.747791
10096 18:11:11.014697 00700000 ################################################################
10097 18:11:11.014862
10098 18:11:11.304283 00780000 ################################################################
10099 18:11:11.304477
10100 18:11:11.574750 00800000 ################################################################
10101 18:11:11.574948
10102 18:11:11.874632 00880000 ################################################################
10103 18:11:11.874774
10104 18:11:12.176277 00900000 ################################################################
10105 18:11:12.176456
10106 18:11:12.443648 00980000 ################################################################
10107 18:11:12.443797
10108 18:11:12.724782 00a00000 ################################################################
10109 18:11:12.724933
10110 18:11:13.018872 00a80000 ################################################################
10111 18:11:13.019015
10112 18:11:13.344525 00b00000 ################################################################
10113 18:11:13.344720
10114 18:11:13.617837 00b80000 ################################################################
10115 18:11:13.617996
10116 18:11:13.872218 00c00000 ################################################################
10117 18:11:13.872401
10118 18:11:14.132169 00c80000 ################################################################
10119 18:11:14.132397
10120 18:11:14.414660 00d00000 ################################################################
10121 18:11:14.414856
10122 18:11:14.700807 00d80000 ################################################################
10123 18:11:14.700952
10124 18:11:14.975505 00e00000 ################################################################
10125 18:11:14.975651
10126 18:11:15.244122 00e80000 ################################################################
10127 18:11:15.244288
10128 18:11:15.512141 00f00000 ################################################################
10129 18:11:15.512271
10130 18:11:15.777583 00f80000 ################################################################
10131 18:11:15.777743
10132 18:11:16.028532 01000000 ################################################################
10133 18:11:16.028679
10134 18:11:16.300493 01080000 ################################################################
10135 18:11:16.300632
10136 18:11:16.595181 01100000 ################################################################
10137 18:11:16.595319
10138 18:11:16.855129 01180000 ################################################################
10139 18:11:16.855281
10140 18:11:17.108276 01200000 ################################################################
10141 18:11:17.108467
10142 18:11:17.378679 01280000 ################################################################
10143 18:11:17.378844
10144 18:11:17.673926 01300000 ################################################################
10145 18:11:17.674075
10146 18:11:17.967266 01380000 ################################################################
10147 18:11:17.967416
10148 18:11:18.258514 01400000 ################################################################
10149 18:11:18.258660
10150 18:11:18.540575 01480000 ################################################################
10151 18:11:18.540712
10152 18:11:18.824515 01500000 ################################################################
10153 18:11:18.824666
10154 18:11:19.109848 01580000 ################################################################
10155 18:11:19.109997
10156 18:11:19.369773 01600000 ################################################################
10157 18:11:19.369958
10158 18:11:19.621638 01680000 ################################################################
10159 18:11:19.621794
10160 18:11:19.962182 01700000 ################################################################
10161 18:11:19.962665
10162 18:11:20.298413 01780000 ################################################################
10163 18:11:20.298563
10164 18:11:20.600399 01800000 ################################################################
10165 18:11:20.600547
10166 18:11:20.892871 01880000 ################################################################
10167 18:11:20.893019
10168 18:11:21.176999 01900000 ################################################################
10169 18:11:21.177143
10170 18:11:21.505274 01980000 ################################################################
10171 18:11:21.505789
10172 18:11:21.908665 01a00000 ################################################################
10173 18:11:21.909169
10174 18:11:22.225210 01a80000 ################################################################
10175 18:11:22.225340
10176 18:11:22.555691 01b00000 ################################################################
10177 18:11:22.555825
10178 18:11:22.839403 01b80000 ################################################################
10179 18:11:22.839566
10180 18:11:23.091309 01c00000 ################################################################
10181 18:11:23.091449
10182 18:11:23.358226 01c80000 ################################################################
10183 18:11:23.358366
10184 18:11:23.637542 01d00000 ################################################################
10185 18:11:23.637687
10186 18:11:23.897909 01d80000 ################################################################
10187 18:11:23.898048
10188 18:11:24.146043 01e00000 ################################################################
10189 18:11:24.146178
10190 18:11:24.410636 01e80000 ################################################################
10191 18:11:24.410779
10192 18:11:24.698754 01f00000 ################################################################
10193 18:11:24.698899
10194 18:11:24.982962 01f80000 ################################################################
10195 18:11:24.983097
10196 18:11:25.265426 02000000 ################################################################
10197 18:11:25.265577
10198 18:11:25.544676 02080000 ################################################################
10199 18:11:25.544820
10200 18:11:25.821796 02100000 ################################################################
10201 18:11:25.821949
10202 18:11:26.110780 02180000 ################################################################
10203 18:11:26.110935
10204 18:11:26.373633 02200000 ################################################################
10205 18:11:26.373809
10206 18:11:26.628661 02280000 ################################################################
10207 18:11:26.628796
10208 18:11:26.881051 02300000 ################################################################
10209 18:11:26.881203
10210 18:11:27.145146 02380000 ################################################################
10211 18:11:27.145287
10212 18:11:27.396805 02400000 ################################################################
10213 18:11:27.396967
10214 18:11:27.651991 02480000 ################################################################
10215 18:11:27.652162
10216 18:11:27.908404 02500000 ################################################################
10217 18:11:27.908564
10218 18:11:28.177960 02580000 ################################################################
10219 18:11:28.178105
10220 18:11:28.430190 02600000 ################################################################
10221 18:11:28.430325
10222 18:11:28.685646 02680000 ################################################################
10223 18:11:28.685782
10224 18:11:28.942260 02700000 ################################################################
10225 18:11:28.942396
10226 18:11:29.219314 02780000 ################################################################
10227 18:11:29.219481
10228 18:11:29.482469 02800000 ################################################################
10229 18:11:29.482638
10230 18:11:29.744905 02880000 ################################################################
10231 18:11:29.745048
10232 18:11:29.996970 02900000 ################################################################
10233 18:11:29.997106
10234 18:11:30.257888 02980000 ################################################################
10235 18:11:30.258057
10236 18:11:30.515799 02a00000 ################################################################
10237 18:11:30.515945
10238 18:11:30.800048 02a80000 ################################################################
10239 18:11:30.800178
10240 18:11:31.075524 02b00000 ################################################################
10241 18:11:31.075659
10242 18:11:31.326111 02b80000 ################################################################
10243 18:11:31.326269
10244 18:11:31.593605 02c00000 ################################################################
10245 18:11:31.593741
10246 18:11:31.844900 02c80000 ################################################################
10247 18:11:31.845034
10248 18:11:32.094263 02d00000 ################################################################
10249 18:11:32.094432
10250 18:11:32.350291 02d80000 ################################################################
10251 18:11:32.350437
10252 18:11:32.624003 02e00000 ################################################################
10253 18:11:32.624137
10254 18:11:32.889379 02e80000 ################################################################
10255 18:11:32.889523
10256 18:11:33.152964 02f00000 ################################################################
10257 18:11:33.153115
10258 18:11:33.420191 02f80000 ################################################################
10259 18:11:33.420327
10260 18:11:33.678028 03000000 ################################################################
10261 18:11:33.678164
10262 18:11:33.933516 03080000 ################################################################
10263 18:11:33.933674
10264 18:11:34.190254 03100000 ################################################################
10265 18:11:34.190388
10266 18:11:34.455388 03180000 ################################################################
10267 18:11:34.455521
10268 18:11:34.716157 03200000 ################################################################
10269 18:11:34.716322
10270 18:11:34.990697 03280000 ################################################################
10271 18:11:34.990828
10272 18:11:35.262512 03300000 ################################################################
10273 18:11:35.262676
10274 18:11:35.532889 03380000 ################################################################
10275 18:11:35.533023
10276 18:11:35.783506 03400000 ################################################################
10277 18:11:35.783644
10278 18:11:36.033840 03480000 ################################################################
10279 18:11:36.033974
10280 18:11:36.310414 03500000 ################################################################
10281 18:11:36.310567
10282 18:11:36.572836 03580000 ################################################################
10283 18:11:36.572989
10284 18:11:36.847214 03600000 ################################################################
10285 18:11:36.847364
10286 18:11:37.104754 03680000 ################################################################
10287 18:11:37.104889
10288 18:11:37.350525 03700000 ################################################################
10289 18:11:37.350664
10290 18:11:37.596210 03780000 ################################################################
10291 18:11:37.596385
10292 18:11:37.852212 03800000 ################################################################
10293 18:11:37.852378
10294 18:11:38.110759 03880000 ################################################################
10295 18:11:38.110903
10296 18:11:38.370423 03900000 ################################################################
10297 18:11:38.370589
10298 18:11:38.618065 03980000 ################################################################
10299 18:11:38.618197
10300 18:11:38.862891 03a00000 ################################################################
10301 18:11:38.863067
10302 18:11:39.105033 03a80000 ################################################################
10303 18:11:39.105183
10304 18:11:39.350891 03b00000 ################################################################
10305 18:11:39.351047
10306 18:11:39.598734 03b80000 ################################################################
10307 18:11:39.598882
10308 18:11:39.852099 03c00000 ################################################################
10309 18:11:39.852245
10310 18:11:40.100196 03c80000 ################################################################
10311 18:11:40.100414
10312 18:11:40.344580 03d00000 ################################################################
10313 18:11:40.344727
10314 18:11:40.590429 03d80000 ################################################################
10315 18:11:40.590609
10316 18:11:40.728968 03e00000 ##################################### done.
10317 18:11:40.729102
10318 18:11:40.732786 The bootfile was 65312118 bytes long.
10319 18:11:40.732861
10320 18:11:40.735787 Sending tftp read request... done.
10321 18:11:40.735875
10322 18:11:40.739564 Waiting for the transfer...
10323 18:11:40.739645
10324 18:11:40.742680 00000000 # done.
10325 18:11:40.742785
10326 18:11:40.749059 Command line loaded dynamically from TFTP file: 14291441/tftp-deploy-_9_2ntuc/kernel/cmdline
10327 18:11:40.749142
10328 18:11:40.762266 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10329 18:11:40.762380
10330 18:11:40.762474 Loading FIT.
10331 18:11:40.765806
10332 18:11:40.765909 Image ramdisk-1 has 52137722 bytes.
10333 18:11:40.766001
10334 18:11:40.769273 Image fdt-1 has 47258 bytes.
10335 18:11:40.769373
10336 18:11:40.772126 Image kernel-1 has 13125101 bytes.
10337 18:11:40.772225
10338 18:11:40.782530 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10339 18:11:40.782634
10340 18:11:40.798878 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10341 18:11:40.798995
10342 18:11:40.805687 Choosing best match conf-1 for compat google,spherion-rev2.
10343 18:11:40.808774
10344 18:11:40.813604 Connected to device vid:did:rid of 1ae0:0028:00
10345 18:11:40.821338
10346 18:11:40.825152 tpm_get_response: command 0x17b, return code 0x0
10347 18:11:40.825235
10348 18:11:40.828023 ec_init: CrosEC protocol v3 supported (256, 248)
10349 18:11:40.833370
10350 18:11:40.836308 tpm_cleanup: add release locality here.
10351 18:11:40.836424
10352 18:11:40.836519 Shutting down all USB controllers.
10353 18:11:40.840220
10354 18:11:40.840324 Removing current net device
10355 18:11:40.840428
10356 18:11:40.846273 Exiting depthcharge with code 4 at timestamp: 69286153
10357 18:11:40.846377
10358 18:11:40.850069 LZMA decompressing kernel-1 to 0x821a6718
10359 18:11:40.850150
10360 18:11:40.852916 LZMA decompressing kernel-1 to 0x40000000
10361 18:11:42.470848
10362 18:11:42.471011 jumping to kernel
10363 18:11:42.471542 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10364 18:11:42.471649 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10365 18:11:42.471728 Setting prompt string to ['Linux version [0-9]']
10366 18:11:42.471798 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10367 18:11:42.471873 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10368 18:11:42.552983
10369 18:11:42.555999 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10370 18:11:42.559958 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10371 18:11:42.560083 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10372 18:11:42.560184 Setting prompt string to []
10373 18:11:42.560308 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10374 18:11:42.560435 Using line separator: #'\n'#
10375 18:11:42.560524 No login prompt set.
10376 18:11:42.560623 Parsing kernel messages
10377 18:11:42.560708 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10378 18:11:42.560870 [login-action] Waiting for messages, (timeout 00:03:44)
10379 18:11:42.560939 Waiting using forced prompt support (timeout 00:01:52)
10380 18:11:42.579606 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10381 18:11:42.583090 [ 0.000000] random: crng init done
10382 18:11:42.589146 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10383 18:11:42.592894 [ 0.000000] efi: UEFI not found.
10384 18:11:42.599174 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10385 18:11:42.605913 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10386 18:11:42.615666 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10387 18:11:42.625935 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10388 18:11:42.632226 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10389 18:11:42.635817 [ 0.000000] printk: bootconsole [mtk8250] enabled
10390 18:11:42.645193 [ 0.000000] NUMA: No NUMA configuration found
10391 18:11:42.651584 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10392 18:11:42.658343 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10393 18:11:42.658426 [ 0.000000] Zone ranges:
10394 18:11:42.664818 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10395 18:11:42.667949 [ 0.000000] DMA32 empty
10396 18:11:42.674839 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10397 18:11:42.677752 [ 0.000000] Movable zone start for each node
10398 18:11:42.681363 [ 0.000000] Early memory node ranges
10399 18:11:42.687832 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10400 18:11:42.694380 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10401 18:11:42.700936 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10402 18:11:42.707354 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10403 18:11:42.714149 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10404 18:11:42.720669 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10405 18:11:42.777575 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10406 18:11:42.784184 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10407 18:11:42.790544 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10408 18:11:42.793817 [ 0.000000] psci: probing for conduit method from DT.
10409 18:11:42.800459 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10410 18:11:42.803786 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10411 18:11:42.810632 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10412 18:11:42.813863 [ 0.000000] psci: SMC Calling Convention v1.2
10413 18:11:42.820455 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10414 18:11:42.823530 [ 0.000000] Detected VIPT I-cache on CPU0
10415 18:11:42.830354 [ 0.000000] CPU features: detected: GIC system register CPU interface
10416 18:11:42.837284 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10417 18:11:42.843978 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10418 18:11:42.850371 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10419 18:11:42.857226 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10420 18:11:42.867070 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10421 18:11:42.870035 [ 0.000000] alternatives: applying boot alternatives
10422 18:11:42.876799 [ 0.000000] Fallback order for Node 0: 0
10423 18:11:42.883252 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10424 18:11:42.887111 [ 0.000000] Policy zone: Normal
10425 18:11:42.899756 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10426 18:11:42.909657 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10427 18:11:42.921568 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10428 18:11:42.931458 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10429 18:11:42.938488 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10430 18:11:42.941474 <6>[ 0.000000] software IO TLB: area num 8.
10431 18:11:42.998290 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10432 18:11:43.147476 <6>[ 0.000000] Memory: 7913144K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 439624K reserved, 32768K cma-reserved)
10433 18:11:43.154436 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10434 18:11:43.161279 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10435 18:11:43.164336 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10436 18:11:43.171027 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10437 18:11:43.177856 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10438 18:11:43.180997 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10439 18:11:43.190947 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10440 18:11:43.197349 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10441 18:11:43.204320 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10442 18:11:43.210772 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10443 18:11:43.214358 <6>[ 0.000000] GICv3: 608 SPIs implemented
10444 18:11:43.217284 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10445 18:11:43.224161 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10446 18:11:43.227683 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10447 18:11:43.233970 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10448 18:11:43.247408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10449 18:11:43.257101 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10450 18:11:43.267328 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10451 18:11:43.274832 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10452 18:11:43.287847 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10453 18:11:43.294681 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10454 18:11:43.300772 <6>[ 0.009183] Console: colour dummy device 80x25
10455 18:11:43.311025 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10456 18:11:43.317813 <6>[ 0.024382] pid_max: default: 32768 minimum: 301
10457 18:11:43.320853 <6>[ 0.029254] LSM: Security Framework initializing
10458 18:11:43.327285 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 18:11:43.337359 <6>[ 0.042035] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 18:11:43.343899 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10461 18:11:43.350942 <6>[ 0.058906] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 18:11:43.360706 <6>[ 0.065245] cblist_init_generic: Setting adjustable number of callback queues.
10463 18:11:43.367006 <6>[ 0.072717] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 18:11:43.370882 <6>[ 0.079118] rcu: Hierarchical SRCU implementation.
10465 18:11:43.377270 <6>[ 0.084163] rcu: Max phase no-delay instances is 1000.
10466 18:11:43.383956 <6>[ 0.091217] EFI services will not be available.
10467 18:11:43.387038 <6>[ 0.096176] smp: Bringing up secondary CPUs ...
10468 18:11:43.395185 <6>[ 0.101228] Detected VIPT I-cache on CPU1
10469 18:11:43.402190 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 18:11:43.408352 <6>[ 0.101333] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 18:11:43.412125 <6>[ 0.101673] Detected VIPT I-cache on CPU2
10472 18:11:43.421894 <6>[ 0.101728] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 18:11:43.428082 <6>[ 0.101748] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 18:11:43.432024 <6>[ 0.102008] Detected VIPT I-cache on CPU3
10475 18:11:43.438101 <6>[ 0.102054] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 18:11:43.444884 <6>[ 0.102068] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 18:11:43.451765 <6>[ 0.102374] CPU features: detected: Spectre-v4
10478 18:11:43.454857 <6>[ 0.102380] CPU features: detected: Spectre-BHB
10479 18:11:43.457865 <6>[ 0.102385] Detected PIPT I-cache on CPU4
10480 18:11:43.464608 <6>[ 0.102443] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 18:11:43.471337 <6>[ 0.102460] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 18:11:43.477959 <6>[ 0.102752] Detected PIPT I-cache on CPU5
10483 18:11:43.485140 <6>[ 0.102815] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 18:11:43.491330 <6>[ 0.102830] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 18:11:43.494751 <6>[ 0.103112] Detected PIPT I-cache on CPU6
10486 18:11:43.501723 <6>[ 0.103178] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 18:11:43.508090 <6>[ 0.103194] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 18:11:43.514807 <6>[ 0.103489] Detected PIPT I-cache on CPU7
10489 18:11:43.521850 <6>[ 0.103555] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 18:11:43.528262 <6>[ 0.103571] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 18:11:43.531299 <6>[ 0.103618] smp: Brought up 1 node, 8 CPUs
10492 18:11:43.538365 <6>[ 0.244969] SMP: Total of 8 processors activated.
10493 18:11:43.541100 <6>[ 0.249890] CPU features: detected: 32-bit EL0 Support
10494 18:11:43.551619 <6>[ 0.255254] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 18:11:43.557744 <6>[ 0.264054] CPU features: detected: Common not Private translations
10496 18:11:43.560904 <6>[ 0.270570] CPU features: detected: CRC32 instructions
10497 18:11:43.567764 <6>[ 0.275954] CPU features: detected: RCpc load-acquire (LDAPR)
10498 18:11:43.574874 <6>[ 0.281915] CPU features: detected: LSE atomic instructions
10499 18:11:43.580845 <6>[ 0.287696] CPU features: detected: Privileged Access Never
10500 18:11:43.584649 <6>[ 0.293511] CPU features: detected: RAS Extension Support
10501 18:11:43.594393 <6>[ 0.299120] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 18:11:43.597395 <6>[ 0.306385] CPU: All CPU(s) started at EL2
10503 18:11:43.604404 <6>[ 0.310701] alternatives: applying system-wide alternatives
10504 18:11:43.613396 <6>[ 0.321540] devtmpfs: initialized
10505 18:11:43.628540 <6>[ 0.330499] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10506 18:11:43.635444 <6>[ 0.340457] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10507 18:11:43.642329 <6>[ 0.348480] pinctrl core: initialized pinctrl subsystem
10508 18:11:43.645408 <6>[ 0.355171] DMI not present or invalid.
10509 18:11:43.652769 <6>[ 0.359589] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10510 18:11:43.662099 <6>[ 0.366461] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10511 18:11:43.669005 <6>[ 0.374053] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10512 18:11:43.678912 <6>[ 0.382273] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10513 18:11:43.681853 <6>[ 0.390516] audit: initializing netlink subsys (disabled)
10514 18:11:43.691559 <5>[ 0.396209] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10515 18:11:43.698332 <6>[ 0.396932] thermal_sys: Registered thermal governor 'step_wise'
10516 18:11:43.705154 <6>[ 0.404178] thermal_sys: Registered thermal governor 'power_allocator'
10517 18:11:43.708133 <6>[ 0.410432] cpuidle: using governor menu
10518 18:11:43.714776 <6>[ 0.421393] NET: Registered PF_QIPCRTR protocol family
10519 18:11:43.721476 <6>[ 0.426876] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10520 18:11:43.725228 <6>[ 0.433973] ASID allocator initialised with 32768 entries
10521 18:11:43.732188 <6>[ 0.440565] Serial: AMBA PL011 UART driver
10522 18:11:43.741274 <4>[ 0.449419] Trying to register duplicate clock ID: 134
10523 18:11:43.800870 <6>[ 0.512508] KASLR enabled
10524 18:11:43.815754 <6>[ 0.520260] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10525 18:11:43.821991 <6>[ 0.527273] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10526 18:11:43.828662 <6>[ 0.533762] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10527 18:11:43.835466 <6>[ 0.540769] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10528 18:11:43.841480 <6>[ 0.547257] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10529 18:11:43.848299 <6>[ 0.554262] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10530 18:11:43.855239 <6>[ 0.560749] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10531 18:11:43.861539 <6>[ 0.567753] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10532 18:11:43.864642 <6>[ 0.575221] ACPI: Interpreter disabled.
10533 18:11:43.873767 <6>[ 0.581660] iommu: Default domain type: Translated
10534 18:11:43.879979 <6>[ 0.586810] iommu: DMA domain TLB invalidation policy: strict mode
10535 18:11:43.883741 <5>[ 0.593471] SCSI subsystem initialized
10536 18:11:43.890406 <6>[ 0.597725] usbcore: registered new interface driver usbfs
10537 18:11:43.897261 <6>[ 0.603457] usbcore: registered new interface driver hub
10538 18:11:43.900299 <6>[ 0.609007] usbcore: registered new device driver usb
10539 18:11:43.907132 <6>[ 0.615126] pps_core: LinuxPPS API ver. 1 registered
10540 18:11:43.916948 <6>[ 0.620320] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10541 18:11:43.919988 <6>[ 0.629663] PTP clock support registered
10542 18:11:43.923284 <6>[ 0.633906] EDAC MC: Ver: 3.0.0
10543 18:11:43.930803 <6>[ 0.639096] FPGA manager framework
10544 18:11:43.937398 <6>[ 0.642772] Advanced Linux Sound Architecture Driver Initialized.
10545 18:11:43.940758 <6>[ 0.649554] vgaarb: loaded
10546 18:11:43.946995 <6>[ 0.652702] clocksource: Switched to clocksource arch_sys_counter
10547 18:11:43.950452 <5>[ 0.659144] VFS: Disk quotas dquot_6.6.0
10548 18:11:43.957469 <6>[ 0.663332] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10549 18:11:43.960638 <6>[ 0.670520] pnp: PnP ACPI: disabled
10550 18:11:43.969458 <6>[ 0.677268] NET: Registered PF_INET protocol family
10551 18:11:43.978770 <6>[ 0.682861] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10552 18:11:43.990241 <6>[ 0.695198] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10553 18:11:44.000770 <6>[ 0.704008] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10554 18:11:44.007042 <6>[ 0.711979] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10555 18:11:44.013359 <6>[ 0.720678] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10556 18:11:44.025600 <6>[ 0.730432] TCP: Hash tables configured (established 65536 bind 65536)
10557 18:11:44.032308 <6>[ 0.737300] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10558 18:11:44.038475 <6>[ 0.744500] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 18:11:44.045132 <6>[ 0.752208] NET: Registered PF_UNIX/PF_LOCAL protocol family
10560 18:11:44.052151 <6>[ 0.758352] RPC: Registered named UNIX socket transport module.
10561 18:11:44.055661 <6>[ 0.764505] RPC: Registered udp transport module.
10562 18:11:44.061792 <6>[ 0.769436] RPC: Registered tcp transport module.
10563 18:11:44.068204 <6>[ 0.774367] RPC: Registered tcp NFSv4.1 backchannel transport module.
10564 18:11:44.071749 <6>[ 0.781032] PCI: CLS 0 bytes, default 64
10565 18:11:44.075405 <6>[ 0.785402] Unpacking initramfs...
10566 18:11:44.085413 <6>[ 0.789123] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10567 18:11:44.091631 <6>[ 0.797748] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10568 18:11:44.098382 <6>[ 0.806546] kvm [1]: IPA Size Limit: 40 bits
10569 18:11:44.101665 <6>[ 0.811071] kvm [1]: GICv3: no GICV resource entry
10570 18:11:44.108428 <6>[ 0.816091] kvm [1]: disabling GICv2 emulation
10571 18:11:44.115306 <6>[ 0.820775] kvm [1]: GIC system register CPU interface enabled
10572 18:11:44.118374 <6>[ 0.826944] kvm [1]: vgic interrupt IRQ18
10573 18:11:44.125292 <6>[ 0.832768] kvm [1]: VHE mode initialized successfully
10574 18:11:44.131544 <5>[ 0.839179] Initialise system trusted keyrings
10575 18:11:44.138286 <6>[ 0.843978] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10576 18:11:44.145609 <6>[ 0.853939] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10577 18:11:44.152515 <5>[ 0.860317] NFS: Registering the id_resolver key type
10578 18:11:44.155597 <5>[ 0.865618] Key type id_resolver registered
10579 18:11:44.162466 <5>[ 0.870031] Key type id_legacy registered
10580 18:11:44.169044 <6>[ 0.874312] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10581 18:11:44.176018 <6>[ 0.881236] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10582 18:11:44.181993 <6>[ 0.888957] 9p: Installing v9fs 9p2000 file system support
10583 18:11:44.219288 <5>[ 0.926952] Key type asymmetric registered
10584 18:11:44.222442 <5>[ 0.931282] Asymmetric key parser 'x509' registered
10585 18:11:44.231843 <6>[ 0.936417] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10586 18:11:44.235354 <6>[ 0.944033] io scheduler mq-deadline registered
10587 18:11:44.238182 <6>[ 0.948796] io scheduler kyber registered
10588 18:11:44.257120 <6>[ 0.965623] EINJ: ACPI disabled.
10589 18:11:44.290398 <4>[ 0.992183] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10590 18:11:44.300652 <4>[ 1.002814] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 18:11:44.315131 <6>[ 1.023677] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10592 18:11:44.323463 <6>[ 1.031588] printk: console [ttyS0] disabled
10593 18:11:44.351286 <6>[ 1.056220] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10594 18:11:44.357635 <6>[ 1.065694] printk: console [ttyS0] enabled
10595 18:11:44.361125 <6>[ 1.065694] printk: console [ttyS0] enabled
10596 18:11:44.368144 <6>[ 1.074589] printk: bootconsole [mtk8250] disabled
10597 18:11:44.371048 <6>[ 1.074589] printk: bootconsole [mtk8250] disabled
10598 18:11:44.378179 <6>[ 1.085599] SuperH (H)SCI(F) driver initialized
10599 18:11:44.381053 <6>[ 1.090857] msm_serial: driver initialized
10600 18:11:44.395130 <6>[ 1.099737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10601 18:11:44.404638 <6>[ 1.108280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10602 18:11:44.411163 <6>[ 1.116821] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10603 18:11:44.420927 <6>[ 1.125450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10604 18:11:44.430905 <6>[ 1.134156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10605 18:11:44.437624 <6>[ 1.142876] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10606 18:11:44.448007 <6>[ 1.151416] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10607 18:11:44.454533 <6>[ 1.160211] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10608 18:11:44.464003 <6>[ 1.168754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10609 18:11:44.476031 <6>[ 1.184198] loop: module loaded
10610 18:11:44.482816 <6>[ 1.190002] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10611 18:11:44.505387 <4>[ 1.213289] mtk-pmic-keys: Failed to locate of_node [id: -1]
10612 18:11:44.511656 <6>[ 1.220130] megasas: 07.719.03.00-rc1
10613 18:11:44.521536 <6>[ 1.229838] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10614 18:11:44.532066 <6>[ 1.240082] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10615 18:11:44.548471 <6>[ 1.255992] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10616 18:11:44.604048 <6>[ 1.305171] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10617 18:11:46.281117 <6>[ 2.989544] Freeing initrd memory: 50912K
10618 18:11:46.293376 <6>[ 3.001439] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10619 18:11:46.304323 <6>[ 3.012526] tun: Universal TUN/TAP device driver, 1.6
10620 18:11:46.307398 <6>[ 3.018590] thunder_xcv, ver 1.0
10621 18:11:46.311194 <6>[ 3.022094] thunder_bgx, ver 1.0
10622 18:11:46.314043 <6>[ 3.025591] nicpf, ver 1.0
10623 18:11:46.324578 <6>[ 3.029619] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10624 18:11:46.327582 <6>[ 3.037094] hns3: Copyright (c) 2017 Huawei Corporation.
10625 18:11:46.334314 <6>[ 3.042682] hclge is initializing
10626 18:11:46.338030 <6>[ 3.046258] e1000: Intel(R) PRO/1000 Network Driver
10627 18:11:46.344267 <6>[ 3.051387] e1000: Copyright (c) 1999-2006 Intel Corporation.
10628 18:11:46.347867 <6>[ 3.057403] e1000e: Intel(R) PRO/1000 Network Driver
10629 18:11:46.354447 <6>[ 3.062619] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10630 18:11:46.361057 <6>[ 3.068804] igb: Intel(R) Gigabit Ethernet Network Driver
10631 18:11:46.367662 <6>[ 3.074454] igb: Copyright (c) 2007-2014 Intel Corporation.
10632 18:11:46.374318 <6>[ 3.080291] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10633 18:11:46.380829 <6>[ 3.086809] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10634 18:11:46.384171 <6>[ 3.093271] sky2: driver version 1.30
10635 18:11:46.391159 <6>[ 3.098198] usbcore: registered new device driver r8152-cfgselector
10636 18:11:46.397126 <6>[ 3.104741] usbcore: registered new interface driver r8152
10637 18:11:46.404088 <6>[ 3.110569] VFIO - User Level meta-driver version: 0.3
10638 18:11:46.410736 <6>[ 3.118809] usbcore: registered new interface driver usb-storage
10639 18:11:46.417367 <6>[ 3.125254] usbcore: registered new device driver onboard-usb-hub
10640 18:11:46.426126 <6>[ 3.134433] mt6397-rtc mt6359-rtc: registered as rtc0
10641 18:11:46.435975 <6>[ 3.139916] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:07:03 UTC (1718129223)
10642 18:11:46.439590 <6>[ 3.149510] i2c_dev: i2c /dev entries driver
10643 18:11:46.453320 <4>[ 3.161509] cpu cpu0: supply cpu not found, using dummy regulator
10644 18:11:46.459936 <4>[ 3.167955] cpu cpu1: supply cpu not found, using dummy regulator
10645 18:11:46.466971 <4>[ 3.174364] cpu cpu2: supply cpu not found, using dummy regulator
10646 18:11:46.472967 <4>[ 3.180769] cpu cpu3: supply cpu not found, using dummy regulator
10647 18:11:46.479849 <4>[ 3.187171] cpu cpu4: supply cpu not found, using dummy regulator
10648 18:11:46.486373 <4>[ 3.193567] cpu cpu5: supply cpu not found, using dummy regulator
10649 18:11:46.492941 <4>[ 3.199981] cpu cpu6: supply cpu not found, using dummy regulator
10650 18:11:46.499497 <4>[ 3.206378] cpu cpu7: supply cpu not found, using dummy regulator
10651 18:11:46.518968 <6>[ 3.227013] cpu cpu0: EM: created perf domain
10652 18:11:46.521813 <6>[ 3.231938] cpu cpu4: EM: created perf domain
10653 18:11:46.529403 <6>[ 3.237513] sdhci: Secure Digital Host Controller Interface driver
10654 18:11:46.535896 <6>[ 3.243945] sdhci: Copyright(c) Pierre Ossman
10655 18:11:46.542133 <6>[ 3.248902] Synopsys Designware Multimedia Card Interface Driver
10656 18:11:46.548950 <6>[ 3.255533] sdhci-pltfm: SDHCI platform and OF driver helper
10657 18:11:46.552072 <6>[ 3.255584] mmc0: CQHCI version 5.10
10658 18:11:46.558781 <6>[ 3.265446] ledtrig-cpu: registered to indicate activity on CPUs
10659 18:11:46.565554 <6>[ 3.272355] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10660 18:11:46.572434 <6>[ 3.279410] usbcore: registered new interface driver usbhid
10661 18:11:46.575453 <6>[ 3.285233] usbhid: USB HID core driver
10662 18:11:46.582363 <6>[ 3.289433] spi_master spi0: will run message pump with realtime priority
10663 18:11:46.625540 <6>[ 3.327034] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10664 18:11:46.644638 <6>[ 3.343059] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10665 18:11:46.648059 <6>[ 3.354293] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10666 18:11:46.656958 <6>[ 3.364881] cros-ec-spi spi0.0: Chrome EC device registered
10667 18:11:46.663649 <6>[ 3.370866] mmc0: Command Queue Engine enabled
10668 18:11:46.669630 <6>[ 3.375593] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10669 18:11:46.672985 <6>[ 3.383240] mmcblk0: mmc0:0001 DA4128 116 GiB
10670 18:11:46.682866 <6>[ 3.391373] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10671 18:11:46.690169 <6>[ 3.398601] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10672 18:11:46.696740 <6>[ 3.404490] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10673 18:11:46.706827 <6>[ 3.410548] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10674 18:11:46.713331 <6>[ 3.410556] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10675 18:11:46.716858 <6>[ 3.421216] NET: Registered PF_PACKET protocol family
10676 18:11:46.723374 <6>[ 3.431781] 9pnet: Installing 9P2000 support
10677 18:11:46.726838 <5>[ 3.436343] Key type dns_resolver registered
10678 18:11:46.733473 <6>[ 3.441324] registered taskstats version 1
10679 18:11:46.736424 <5>[ 3.445708] Loading compiled-in X.509 certificates
10680 18:11:46.766096 <4>[ 3.467691] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10681 18:11:46.775501 <4>[ 3.478408] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10682 18:11:46.790231 <6>[ 3.499097] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10683 18:11:46.797628 <6>[ 3.505906] xhci-mtk 11200000.usb: xHCI Host Controller
10684 18:11:46.804028 <6>[ 3.511410] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10685 18:11:46.814136 <6>[ 3.519265] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10686 18:11:46.820656 <6>[ 3.528806] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10687 18:11:46.827352 <6>[ 3.534911] xhci-mtk 11200000.usb: xHCI Host Controller
10688 18:11:46.833730 <6>[ 3.540401] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10689 18:11:46.840377 <6>[ 3.548055] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10690 18:11:46.847514 <6>[ 3.555874] hub 1-0:1.0: USB hub found
10691 18:11:46.850431 <6>[ 3.559901] hub 1-0:1.0: 1 port detected
10692 18:11:46.860940 <6>[ 3.564222] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10693 18:11:46.863881 <6>[ 3.572975] hub 2-0:1.0: USB hub found
10694 18:11:46.867594 <6>[ 3.576998] hub 2-0:1.0: 1 port detected
10695 18:11:46.875391 <6>[ 3.584220] mtk-msdc 11f70000.mmc: Got CD GPIO
10696 18:11:46.894177 <6>[ 3.598863] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10697 18:11:46.900275 <6>[ 3.607269] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10698 18:11:46.910695 <6>[ 3.615612] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10699 18:11:46.920706 <6>[ 3.623952] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10700 18:11:46.926652 <6>[ 3.632292] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10701 18:11:46.936936 <6>[ 3.640630] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10702 18:11:46.943359 <6>[ 3.648970] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10703 18:11:46.953749 <6>[ 3.657309] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10704 18:11:46.960056 <6>[ 3.665647] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10705 18:11:46.969847 <6>[ 3.673986] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10706 18:11:46.976508 <6>[ 3.682324] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10707 18:11:46.986453 <6>[ 3.690669] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10708 18:11:46.993365 <6>[ 3.699008] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10709 18:11:47.003527 <6>[ 3.707346] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10710 18:11:47.009587 <6>[ 3.715684] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10711 18:11:47.016267 <6>[ 3.724406] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10712 18:11:47.023501 <6>[ 3.731557] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10713 18:11:47.029810 <6>[ 3.738363] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10714 18:11:47.036426 <6>[ 3.745131] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10715 18:11:47.047084 <6>[ 3.752106] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10716 18:11:47.053571 <6>[ 3.758959] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10717 18:11:47.063071 <6>[ 3.768094] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10718 18:11:47.073350 <6>[ 3.777215] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10719 18:11:47.083200 <6>[ 3.786508] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10720 18:11:47.092972 <6>[ 3.795976] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10721 18:11:47.100313 <6>[ 3.805443] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10722 18:11:47.109769 <6>[ 3.814562] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10723 18:11:47.119538 <6>[ 3.824031] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10724 18:11:47.129539 <6>[ 3.833154] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10725 18:11:47.139596 <6>[ 3.842449] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10726 18:11:47.149874 <6>[ 3.852609] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10727 18:11:47.159870 <6>[ 3.864161] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10728 18:11:47.279573 <6>[ 3.985042] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10729 18:11:47.434686 <6>[ 4.143075] hub 1-1:1.0: USB hub found
10730 18:11:47.437596 <6>[ 4.147639] hub 1-1:1.0: 4 ports detected
10731 18:11:47.449092 <6>[ 4.157564] hub 1-1:1.0: USB hub found
10732 18:11:47.452335 <6>[ 4.161968] hub 1-1:1.0: 4 ports detected
10733 18:11:47.559952 <6>[ 4.265324] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10734 18:11:47.585563 <6>[ 4.294379] hub 2-1:1.0: USB hub found
10735 18:11:47.589313 <6>[ 4.298907] hub 2-1:1.0: 3 ports detected
10736 18:11:47.600941 <6>[ 4.309684] hub 2-1:1.0: USB hub found
10737 18:11:47.604561 <6>[ 4.314125] hub 2-1:1.0: 3 ports detected
10738 18:11:47.771680 <6>[ 4.477018] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10739 18:11:47.904038 <6>[ 4.612366] hub 1-1.4:1.0: USB hub found
10740 18:11:47.906870 <6>[ 4.616968] hub 1-1.4:1.0: 2 ports detected
10741 18:11:47.921628 <6>[ 4.630127] hub 1-1.4:1.0: USB hub found
10742 18:11:47.924484 <6>[ 4.634734] hub 1-1.4:1.0: 2 ports detected
10743 18:11:47.988218 <6>[ 4.693232] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10744 18:11:48.096307 <6>[ 4.801658] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10745 18:11:48.153155 <6>[ 4.858848] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10746 18:11:48.194107 <6>[ 4.902604] r8152 2-1.3:1.0 eth0: v1.12.13
10747 18:11:48.223216 <6>[ 4.928758] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10748 18:11:48.415582 <6>[ 5.121036] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10749 18:11:49.811504 <6>[ 6.520280] r8152 2-1.3:1.0 eth0: carrier on
10750 18:11:56.043773 <5>[ 6.544815] Sending DHCP requests .., OK
10751 18:11:56.050294 <6>[ 12.757305] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10752 18:11:56.053644 <6>[ 12.765617] IP-Config: Complete:
10753 18:11:56.066625 <6>[ 12.769108] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10754 18:11:56.073142 <6>[ 12.779814] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10755 18:11:56.079704 <6>[ 12.788429] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10756 18:11:56.086303 <6>[ 12.788439] nameserver0=192.168.201.1
10757 18:11:56.166132 <6>[ 12.800612] clk: Disabling unused clocks
10758 18:11:56.166700 <6>[ 12.806096] ALSA device list:
10759 18:11:56.166861 <6>[ 12.809394] No soundcards found.
10760 18:11:56.167012 <6>[ 12.817096] Freeing unused kernel memory: 8512K
10761 18:11:56.167141 <6>[ 12.822026] Run /init as init process
10762 18:11:56.167280 <6>[ 12.854357] NET: Registered PF_INET6 protocol family
10763 18:11:56.167402 <6>[ 12.860490] Segment Routing with IPv6
10764 18:11:56.167536 <6>[ 12.864459] In-situ OAM (IOAM) with IPv6
10765 18:11:56.196009 <30>[ 12.879258] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10766 18:11:56.202920 <30>[ 12.912305] systemd[1]: Detected architecture arm64.
10767 18:11:56.203018
10768 18:11:56.209410 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10769 18:11:56.209539
10770 18:11:56.227858 <30>[ 12.937104] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10771 18:11:56.368131 <30>[ 13.074331] systemd[1]: Queued start job for default target graphical.target.
10772 18:11:56.412491 <30>[ 13.118941] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10773 18:11:56.419391 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10774 18:11:56.439718 <30>[ 13.145837] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10775 18:11:56.449460 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10776 18:11:56.471589 <30>[ 13.177596] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10777 18:11:56.481397 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10778 18:11:56.499881 <30>[ 13.206200] systemd[1]: Created slice user.slice - User and Session Slice.
10779 18:11:56.506442 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10780 18:11:56.526007 <30>[ 13.229051] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10781 18:11:56.532455 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10782 18:11:56.554357 <30>[ 13.257156] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10783 18:11:56.560457 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10784 18:11:56.589379 <30>[ 13.285563] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10785 18:11:56.598764 <30>[ 13.305460] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10786 18:11:56.606002 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10787 18:11:56.623036 <30>[ 13.329039] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10788 18:11:56.629499 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10789 18:11:56.646629 <30>[ 13.353042] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10790 18:11:56.656719 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10791 18:11:56.671094 <30>[ 13.381077] systemd[1]: Reached target paths.target - Path Units.
10792 18:11:56.680908 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10793 18:11:56.699193 <30>[ 13.405449] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10794 18:11:56.705945 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10795 18:11:56.719273 <30>[ 13.428990] systemd[1]: Reached target slices.target - Slice Units.
10796 18:11:56.729453 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10797 18:11:56.744344 <30>[ 13.453518] systemd[1]: Reached target swap.target - Swaps.
10798 18:11:56.750366 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10799 18:11:56.771712 <30>[ 13.477537] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10800 18:11:56.781185 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10801 18:11:56.799695 <30>[ 13.505971] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10802 18:11:56.809353 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10803 18:11:56.828782 <30>[ 13.535273] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10804 18:11:56.838627 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10805 18:11:56.855476 <30>[ 13.561738] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10806 18:11:56.865279 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10807 18:11:56.883623 <30>[ 13.589621] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10808 18:11:56.889552 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10809 18:11:56.907048 <30>[ 13.613681] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10810 18:11:56.917544 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10811 18:11:56.936475 <30>[ 13.642412] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10812 18:11:56.946125 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10813 18:11:56.963666 <30>[ 13.670117] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10814 18:11:56.973558 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10815 18:11:57.014762 <30>[ 13.720973] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10816 18:11:57.021131 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10817 18:11:57.040509 <30>[ 13.746978] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10818 18:11:57.047451 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10819 18:11:57.069201 <30>[ 13.775641] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10820 18:11:57.076245 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10821 18:11:57.101526 <30>[ 13.801376] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10822 18:11:57.115027 <30>[ 13.821461] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10823 18:11:57.124710 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10824 18:11:57.148432 <30>[ 13.854604] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10825 18:11:57.154766 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10826 18:11:57.180065 <30>[ 13.886302] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10827 18:11:57.190159 Startin<6>[ 13.895655] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10828 18:11:57.196527 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10829 18:11:57.219801 <30>[ 13.926087] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10830 18:11:57.226562 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10831 18:11:57.252521 <30>[ 13.958306] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10832 18:11:57.258379 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10833 18:11:57.283810 <30>[ 13.990314] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10834 18:11:57.290260 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10835 18:11:57.319653 <30>[ 14.025734] systemd[1]: Starting systemd-journald.service - Journal Service...
10836 18:11:57.326391 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10837 18:11:57.345131 <30>[ 14.051649] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10838 18:11:57.351775 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10839 18:11:57.376885 <30>[ 14.080097] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10840 18:11:57.383442 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10841 18:11:57.406786 <30>[ 14.113069] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10842 18:11:57.416763 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10843 18:11:57.437524 <30>[ 14.143991] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10844 18:11:57.447375 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10845 18:11:57.467782 <30>[ 14.174189] systemd[1]: Started systemd-journald.service - Journal Service.
10846 18:11:57.474566 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10847 18:11:57.493516 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10848 18:11:57.511459 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10849 18:11:57.535809 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10850 18:11:57.560459 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10851 18:11:57.582686 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10852 18:11:57.601453 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10853 18:11:57.621336 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10854 18:11:57.641870 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10855 18:11:57.663847 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10856 18:11:57.684795 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10857 18:11:57.707798 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10858 18:11:57.729162 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10859 18:11:57.736063 See 'systemctl status systemd-remount-fs.service' for details.
10860 18:11:57.745649 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10861 18:11:57.765351 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10862 18:11:57.819582 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10863 18:11:57.841166 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10864 18:11:57.855546 <46>[ 14.562078] systemd-journald[194]: Received client request to flush runtime journal.
10865 18:11:57.868067 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10866 18:11:57.891386 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10867 18:11:57.914836 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10868 18:11:57.941471 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10869 18:11:57.964580 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10870 18:11:57.988129 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10871 18:11:58.012436 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10872 18:11:58.032309 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10873 18:11:58.083484 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10874 18:11:58.117345 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10875 18:11:58.139363 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10876 18:11:58.158894 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10877 18:11:58.214811 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10878 18:11:58.235260 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10879 18:11:58.262211 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10880 18:11:58.327500 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10881 18:11:58.350972 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10882 18:11:58.368412 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10883 18:11:58.400240 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10884 18:11:58.431913 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10885 18:11:58.469535 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10886 18:11:58.564599 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10887 18:11:58.583838 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10888 18:11:58.602922 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10889 18:11:58.620214 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10890 18:11:58.638972 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10891 18:11:58.651133 <3>[ 15.357410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 18:11:58.657749 <3>[ 15.365828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 18:11:58.667597 <3>[ 15.374118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 18:11:58.680660 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<6>[ 15.386417] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10895 18:11:58.687453 ocket[…- D-Bu<6>[ 15.389803] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10896 18:11:58.697645 <3>[ 15.390407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10897 18:11:58.707438 s System Message<3>[ 15.390419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 18:11:58.714083 <3>[ 15.390422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 18:11:58.723810 <3>[ 15.390429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 18:11:58.723949 Bus Socket.
10901 18:11:58.730665 <3>[ 15.390433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 18:11:58.740988 <6>[ 15.394160] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10903 18:11:58.746919 <3>[ 15.406246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 18:11:58.756892 <6>[ 15.408506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10905 18:11:58.763443 <6>[ 15.408513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10906 18:11:58.773710 <4>[ 15.408665] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10907 18:11:58.780281 <6>[ 15.409314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10908 18:11:58.790212 <6>[ 15.409318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10909 18:11:58.796960 <6>[ 15.411597] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10910 18:11:58.819604 <3>[ 15.421143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 18:11:58.819764 <6>[ 15.431043] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10912 18:11:58.823541 <3>[ 15.437321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 18:11:58.830310 <3>[ 15.437332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 18:11:58.836700 <6>[ 15.478961] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10915 18:11:58.846749 <6>[ 15.479410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10916 18:11:58.853500 <3>[ 15.480594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 18:11:58.863399 <3>[ 15.480612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10918 18:11:58.870150 <3>[ 15.480617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 18:11:58.877168 <3>[ 15.480623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 18:11:58.887362 <3>[ 15.480629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 18:11:58.894121 <3>[ 15.491698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 18:11:58.900686 <6>[ 15.496368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10923 18:11:58.910252 <6>[ 15.533903] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10924 18:11:58.917426 <6>[ 15.537030] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10925 18:11:58.924101 <6>[ 15.540139] remoteproc remoteproc0: scp is available
10926 18:11:58.933967 <4>[ 15.566346] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10927 18:11:58.936929 <4>[ 15.566346] Fallback method does not support PEC.
10928 18:11:58.943998 <6>[ 15.568513] remoteproc remoteproc0: powering up scp
10929 18:11:58.950275 <6>[ 15.592139] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10930 18:11:58.956514 <6>[ 15.593026] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10931 18:11:58.963945 <4>[ 15.593379] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10932 18:11:58.974430 <4>[ 15.593502] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10933 18:11:58.977465 <6>[ 15.600840] pci_bus 0000:00: root bus resource [bus 00-ff]
10934 18:11:58.984248 <6>[ 15.609023] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10935 18:11:58.994268 <3>[ 15.617067] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 18:11:59.001305 <6>[ 15.617088] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10937 18:11:59.010621 <6>[ 15.617099] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10938 18:11:59.017128 <6>[ 15.617221] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10939 18:11:59.023952 <6>[ 15.617260] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10940 18:11:59.027554 <6>[ 15.617441] pci 0000:00:00.0: supports D1 D2
10941 18:11:59.034184 <6>[ 15.617451] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10942 18:11:59.041533 <6>[ 15.657204] mc: Linux media interface: v0.10
10943 18:11:59.048133 <3>[ 15.683582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 18:11:59.058200 <6>[ 15.699607] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10945 18:11:59.064985 <6>[ 15.749952] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10946 18:11:59.071287 <6>[ 15.749958] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10947 18:11:59.080847 <6>[ 15.750147] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10948 18:11:59.090907 <6>[ 15.753600] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10949 18:11:59.097818 <6>[ 15.754552] remoteproc remoteproc0: remote processor scp is now up
10950 18:11:59.107549 <3>[ 15.757354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 18:11:59.114340 <6>[ 15.790773] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10952 18:11:59.120860 [[0;32m OK [<6>[ 15.828504] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10953 18:11:59.130892 0m] Reached targ<6>[ 15.837390] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10954 18:11:59.140776 et [0;1;39msock<6>[ 15.846521] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10955 18:11:59.147366 ets.target[0m -<6>[ 15.855258] pci 0000:01:00.0: supports D1 D2
10956 18:11:59.147504 Socket Units.
10957 18:11:59.153981 <6>[ 15.861014] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10958 18:11:59.154072
10959 18:11:59.164065 <6>[ 15.861584] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10960 18:11:59.192582 <3>[ 15.899312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 18:11:59.229000 <6>[ 15.938772] videodev: Linux video capture interface: v2.00
10962 18:11:59.241949 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10963 18:11:59.267763 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10964 18:11:59.274905 <6>[ 15.984666] Bluetooth: Core ver 2.22
10965 18:11:59.281338 <3>[ 15.986184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 18:11:59.293211 <6>[ 16.003197] NET: Registered PF_BLUETOOTH protocol family
10967 18:11:59.299885 <6>[ 16.008796] Bluetooth: HCI device and connection manager initialized
10968 18:11:59.306642 <6>[ 16.015453] Bluetooth: HCI socket layer initialized
10969 18:11:59.310319 <6>[ 16.020593] Bluetooth: L2CAP socket layer initialized
10970 18:11:59.316913 <6>[ 16.025920] Bluetooth: SCO socket layer initialized
10971 18:11:59.322917 <6>[ 16.025954] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10972 18:11:59.337935 <6>[ 16.043957] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10973 18:11:59.344276 <6>[ 16.044553] usbcore: registered new interface driver btusb
10974 18:11:59.350965 <6>[ 16.052312] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10975 18:11:59.360889 <6>[ 16.052318] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10976 18:11:59.367468 <6>[ 16.064734] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10977 18:11:59.377230 <4>[ 16.066576] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10978 18:11:59.383734 <6>[ 16.068006] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10979 18:11:59.393938 <6>[ 16.068034] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10980 18:11:59.401137 <6>[ 16.068051] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10981 18:11:59.404583 <6>[ 16.068069] pci 0000:00:00.0: PCI bridge to [bus 01]
10982 18:11:59.414767 <6>[ 16.068078] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10983 18:11:59.421492 <6>[ 16.070136] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10984 18:11:59.434534 <6>[ 16.072949] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10985 18:11:59.441488 <6>[ 16.073333] usbcore: registered new interface driver uvcvideo
10986 18:11:59.444814 <6>[ 16.074879] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10987 18:11:59.451239 <3>[ 16.081044] Bluetooth: hci0: Failed to load firmware file (-2)
10988 18:11:59.462141 <6>[ 16.095395] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10989 18:11:59.464902 <6>[ 16.096183] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10990 18:11:59.471943 <6>[ 16.096666] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10991 18:11:59.478621 <3>[ 16.099599] Bluetooth: hci0: Failed to set up firmware (-2)
10992 18:11:59.488874 <4>[ 16.099605] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10993 18:11:59.495388 <5>[ 16.102032] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10994 18:11:59.505523 <3>[ 16.120198] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 18:11:59.515709 <3>[ 16.122688] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10996 18:11:59.522076 <5>[ 16.140088] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10997 18:11:59.529397 <3>[ 16.171641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 18:11:59.539051 <5>[ 16.175660] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10999 18:11:59.546042 <3>[ 16.201512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 18:11:59.555732 <4>[ 16.203656] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11001 18:11:59.565809 <3>[ 16.245258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11002 18:11:59.568782 <6>[ 16.253047] cfg80211: failed to load regulatory.db
11003 18:11:59.575750 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11004 18:11:59.600765 <6>[ 16.307269] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11005 18:11:59.607295 <6>[ 16.314770] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11006 18:11:59.632804 <6>[ 16.341564] mt7921e 0000:01:00.0: ASIC revision: 79610010
11007 18:11:59.644594 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11008 18:11:59.664751 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11009 18:11:59.687167 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11010 18:11:59.737156 <6>[ 16.443433] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11011 18:11:59.740015 <6>[ 16.443433]
11012 18:11:59.746597 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11013 18:11:59.767881 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11014 18:11:59.789167 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11015 18:11:59.805977 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11016 18:11:59.825558 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11017 18:11:59.870708 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11018 18:11:59.895908 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11019 18:11:59.918558 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11020 18:11:59.940275 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11021 18:12:00.000165 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11022 18:12:00.006278 <6>[ 16.713384] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11023 18:12:00.023750 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11024 18:12:00.043792 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11025 18:12:00.058812 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11026 18:12:00.075249 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11027 18:12:00.127857 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11028 18:12:00.152801 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11029 18:12:00.173366 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11030 18:12:00.208502 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11031 18:12:00.245254
11032 18:12:00.248305 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11033 18:12:00.248446
11034 18:12:00.252054 debian-bookworm-arm64 login: root (automatic login)
11035 18:12:00.252160
11036 18:12:00.266583 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11037 18:12:00.266688
11038 18:12:00.273131 The programs included with the Debian GNU/Linux system are free software;
11039 18:12:00.279645 the exact distribution terms for each program are described in the
11040 18:12:00.283279 individual files in /usr/share/doc/*/copyright.
11041 18:12:00.283359
11042 18:12:00.289772 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11043 18:12:00.293217 permitted by applicable law.
11044 18:12:00.293616 Matched prompt #10: / #
11046 18:12:00.293934 Setting prompt string to ['/ #']
11047 18:12:00.294068 end: 2.2.5.1 login-action (duration 00:00:18) [common]
11049 18:12:00.294380 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
11050 18:12:00.294506 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11051 18:12:00.294623 Setting prompt string to ['/ #']
11052 18:12:00.294714 Forcing a shell prompt, looking for ['/ #']
11054 18:12:00.345035 / #
11055 18:12:00.345185 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11056 18:12:00.345266 Waiting using forced prompt support (timeout 00:02:30)
11057 18:12:00.350274
11058 18:12:00.350553 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11059 18:12:00.350648 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11060 18:12:00.350738 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11061 18:12:00.350831 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11062 18:12:00.350915 end: 2 depthcharge-action (duration 00:01:34) [common]
11063 18:12:00.351001 start: 3 lava-test-retry (timeout 00:05:00) [common]
11064 18:12:00.351087 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11065 18:12:00.351162 Using namespace: common
11067 18:12:00.451458 / # #
11068 18:12:00.451662 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11069 18:12:00.458925 #
11070 18:12:00.459204 Using /lava-14291441
11072 18:12:00.559539 / # export SHELL=/bin/sh
11073 18:12:00.564811 export SHELL=/bin/sh
11075 18:12:00.665276 / # . /lava-14291441/environment
11076 18:12:00.670504 . /lava-14291441/environment
11078 18:12:00.771043 / # /lava-14291441/bin/lava-test-runner /lava-14291441/0
11079 18:12:00.771233 Test shell timeout: 10s (minimum of the action and connection timeout)
11080 18:12:00.776030 /lava-14291441/bin/lava-test-runner /lava-14291441/0
11081 18:12:00.795743 + export TESTRUN_ID=0_cros-ec
11082 18:12:00.802307 +<8>[ 17.510290] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14291441_1.5.2.3.1>
11083 18:12:00.802600 Received signal: <STARTRUN> 0_cros-ec 14291441_1.5.2.3.1
11084 18:12:00.802705 Starting test lava.0_cros-ec (14291441_1.5.2.3.1)
11085 18:12:00.802820 Skipping test definition patterns.
11086 18:12:00.805236 cd /lava-14291441/0/tests/0_cros-ec
11087 18:12:00.808721 + cat uuid
11088 18:12:00.808797 + UUID=14291441_1.5.2.3.1
11089 18:12:00.808866 + set +x
11090 18:12:00.815447 + python3 -m cros.runners.lava_runner -v
11091 18:12:00.872258 <6>[ 17.582577] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11092 18:12:01.319448 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11093 18:12:01.326787 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11094 18:12:01.326901
11095 18:12:01.332881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11096 18:12:01.333157 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11098 18:12:01.342730 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11099 18:12:01.352755 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11100 18:12:01.352844
11101 18:12:01.359579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11102 18:12:01.359827 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11104 18:12:01.368970 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11105 18:12:01.376152 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11106 18:12:01.376252
11107 18:12:01.382604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11108 18:12:01.382853 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11110 18:12:01.389326 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11111 18:12:01.392855 Checks the standard ABI for the main Embedded Controller. ... ok
11112 18:12:01.392930
11113 18:12:01.398850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11114 18:12:01.399116 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11116 18:12:01.405971 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11117 18:12:01.412606 Checks the main Embedded controller character device. ... ok
11118 18:12:01.412693
11119 18:12:01.419109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11120 18:12:01.419359 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11122 18:12:01.425449 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11123 18:12:01.432028 Checks basic comunication with the main Embedded controller. ... ok
11124 18:12:01.432130
11125 18:12:01.435999 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11127 18:12:01.438781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11128 18:12:01.442172 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11129 18:12:01.451756 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11130 18:12:01.451856
11131 18:12:01.458356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11132 18:12:01.458624 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11134 18:12:01.465042 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11135 18:12:01.472049 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11136 18:12:01.472151
11137 18:12:01.478924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11138 18:12:01.479196 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11140 18:12:01.485187 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11141 18:12:01.491554 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11142 18:12:01.491659
11143 18:12:01.498573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11144 18:12:01.498852 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11146 18:12:01.505065 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11147 18:12:01.511354 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11148 18:12:01.511461
11149 18:12:01.518239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11150 18:12:01.518501 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11152 18:12:01.524705 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11153 18:12:01.534338 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11154 18:12:01.534433
11155 18:12:01.541009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11156 18:12:01.541267 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11158 18:12:01.547864 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11159 18:12:01.554450 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11160 18:12:01.554542
11161 18:12:01.561037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11162 18:12:01.561298 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11164 18:12:01.567726 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11165 18:12:01.574225 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11166 18:12:01.574329
11167 18:12:01.581025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11168 18:12:01.581270 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11170 18:12:01.587676 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11171 18:12:01.597993 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11172 18:12:01.598086
11173 18:12:01.604391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11174 18:12:01.604671 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11176 18:12:01.614039 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11177 18:12:01.617330 Check the cros battery ABI. ... skipped 'No BAT found'
11178 18:12:01.617429
11179 18:12:01.623896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11180 18:12:01.624153 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11182 18:12:01.634006 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11183 18:12:01.640544 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11184 18:12:01.640626
11185 18:12:01.647046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11186 18:12:01.647299 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11188 18:12:01.653926 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11189 18:12:01.660079 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11190 18:12:01.660177
11191 18:12:01.667110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11192 18:12:01.667377 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11194 18:12:01.676672 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11195 18:12:01.683950 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11196 18:12:01.684031
11197 18:12:01.689862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11198 18:12:01.689945
11199 18:12:01.690180 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11201 18:12:01.697300 ----------<8>[ 18.405154] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14291441_1.5.2.3.1>
11202 18:12:01.697554 Received signal: <ENDRUN> 0_cros-ec 14291441_1.5.2.3.1
11203 18:12:01.697641 Ending use of test pattern.
11204 18:12:01.697710 Ending test lava.0_cros-ec (14291441_1.5.2.3.1), duration 0.90
11206 18:12:01.703693 ------------------------------------------------------------
11207 18:12:01.703776 Ran 18 tests in 0.337s
11208 18:12:01.703842
11209 18:12:01.706510 OK (skipped=15)
11210 18:12:01.706609 + set +x
11211 18:12:01.710114 <LAVA_TEST_RUNNER EXIT>
11212 18:12:01.710365 ok: lava_test_shell seems to have completed
11213 18:12:01.710557 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11214 18:12:01.710656 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11215 18:12:01.710740 end: 3 lava-test-retry (duration 00:00:01) [common]
11216 18:12:01.710825 start: 4 finalize (timeout 00:08:02) [common]
11217 18:12:01.710920 start: 4.1 power-off (timeout 00:00:30) [common]
11218 18:12:01.711112 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11219 18:12:01.781131 >> Command sent successfully.
11220 18:12:01.783743 Returned 0 in 0 seconds
11221 18:12:01.884142 end: 4.1 power-off (duration 00:00:00) [common]
11223 18:12:01.884497 start: 4.2 read-feedback (timeout 00:08:01) [common]
11224 18:12:01.884761 Listened to connection for namespace 'common' for up to 1s
11225 18:12:02.885687 Finalising connection for namespace 'common'
11226 18:12:02.885862 Disconnecting from shell: Finalise
11227 18:12:02.885943 / #
11228 18:12:02.986270 end: 4.2 read-feedback (duration 00:00:01) [common]
11229 18:12:02.986451 end: 4 finalize (duration 00:00:01) [common]
11230 18:12:02.986568 Cleaning after the job
11231 18:12:02.986668 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/ramdisk
11232 18:12:02.992211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/kernel
11233 18:12:02.999912 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/dtb
11234 18:12:03.000122 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291441/tftp-deploy-_9_2ntuc/modules
11235 18:12:03.006262 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291441
11236 18:12:03.096084 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291441
11237 18:12:03.096263 Job finished correctly