Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 18:07:02.047930 lava-dispatcher, installed at version: 2024.03
2 18:07:02.048185 start: 0 validate
3 18:07:02.048362 Start time: 2024-06-11 18:07:02.048354+00:00 (UTC)
4 18:07:02.048508 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:07:02.048635 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 18:07:02.321281 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:07:02.321451 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:07:02.587091 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:07:02.587384 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:07:02.854047 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:07:02.854232 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:07:03.121276 validate duration: 1.07
14 18:07:03.121578 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:07:03.121695 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:07:03.121815 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:07:03.121945 Not decompressing ramdisk as can be used compressed.
18 18:07:03.122042 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 18:07:03.122110 saving as /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/ramdisk/rootfs.cpio.gz
20 18:07:03.122174 total size: 47897469 (45 MB)
21 18:07:03.123737 progress 0 % (0 MB)
22 18:07:03.137113 progress 5 % (2 MB)
23 18:07:03.149441 progress 10 % (4 MB)
24 18:07:03.162603 progress 15 % (6 MB)
25 18:07:03.175776 progress 20 % (9 MB)
26 18:07:03.188895 progress 25 % (11 MB)
27 18:07:03.202237 progress 30 % (13 MB)
28 18:07:03.215701 progress 35 % (16 MB)
29 18:07:03.229000 progress 40 % (18 MB)
30 18:07:03.242107 progress 45 % (20 MB)
31 18:07:03.255426 progress 50 % (22 MB)
32 18:07:03.268651 progress 55 % (25 MB)
33 18:07:03.281921 progress 60 % (27 MB)
34 18:07:03.295178 progress 65 % (29 MB)
35 18:07:03.307810 progress 70 % (32 MB)
36 18:07:03.320792 progress 75 % (34 MB)
37 18:07:03.333824 progress 80 % (36 MB)
38 18:07:03.346886 progress 85 % (38 MB)
39 18:07:03.359481 progress 90 % (41 MB)
40 18:07:03.371601 progress 95 % (43 MB)
41 18:07:03.383576 progress 100 % (45 MB)
42 18:07:03.383810 45 MB downloaded in 0.26 s (174.59 MB/s)
43 18:07:03.383970 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:07:03.384207 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:07:03.384294 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:07:03.384425 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:07:03.384565 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:07:03.384638 saving as /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/kernel/Image
50 18:07:03.384700 total size: 54813184 (52 MB)
51 18:07:03.384761 No compression specified
52 18:07:03.385858 progress 0 % (0 MB)
53 18:07:03.399849 progress 5 % (2 MB)
54 18:07:03.413990 progress 10 % (5 MB)
55 18:07:03.427823 progress 15 % (7 MB)
56 18:07:03.441693 progress 20 % (10 MB)
57 18:07:03.455558 progress 25 % (13 MB)
58 18:07:03.469471 progress 30 % (15 MB)
59 18:07:03.483746 progress 35 % (18 MB)
60 18:07:03.497787 progress 40 % (20 MB)
61 18:07:03.511671 progress 45 % (23 MB)
62 18:07:03.525699 progress 50 % (26 MB)
63 18:07:03.539592 progress 55 % (28 MB)
64 18:07:03.553352 progress 60 % (31 MB)
65 18:07:03.567276 progress 65 % (34 MB)
66 18:07:03.580973 progress 70 % (36 MB)
67 18:07:03.594966 progress 75 % (39 MB)
68 18:07:03.609152 progress 80 % (41 MB)
69 18:07:03.622993 progress 85 % (44 MB)
70 18:07:03.636829 progress 90 % (47 MB)
71 18:07:03.650559 progress 95 % (49 MB)
72 18:07:03.664093 progress 100 % (52 MB)
73 18:07:03.664329 52 MB downloaded in 0.28 s (186.94 MB/s)
74 18:07:03.664515 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:07:03.664751 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:07:03.664838 start: 1.3 download-retry (timeout 00:09:59) [common]
78 18:07:03.664984 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 18:07:03.665190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:07:03.665266 saving as /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/dtb/mt8192-asurada-spherion-r0.dtb
81 18:07:03.665328 total size: 47258 (0 MB)
82 18:07:03.665390 No compression specified
83 18:07:03.666512 progress 69 % (0 MB)
84 18:07:03.666781 progress 100 % (0 MB)
85 18:07:03.666936 0 MB downloaded in 0.00 s (28.06 MB/s)
86 18:07:03.667060 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:07:03.667281 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:07:03.667365 start: 1.4 download-retry (timeout 00:09:59) [common]
90 18:07:03.667448 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 18:07:03.667557 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:07:03.667625 saving as /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/modules/modules.tar
93 18:07:03.667685 total size: 8618176 (8 MB)
94 18:07:03.667746 Using unxz to decompress xz
95 18:07:03.671803 progress 0 % (0 MB)
96 18:07:03.690589 progress 5 % (0 MB)
97 18:07:03.717775 progress 10 % (0 MB)
98 18:07:03.747358 progress 15 % (1 MB)
99 18:07:03.772002 progress 20 % (1 MB)
100 18:07:03.795625 progress 25 % (2 MB)
101 18:07:03.819296 progress 30 % (2 MB)
102 18:07:03.845456 progress 35 % (2 MB)
103 18:07:03.870244 progress 40 % (3 MB)
104 18:07:03.895776 progress 45 % (3 MB)
105 18:07:03.921538 progress 50 % (4 MB)
106 18:07:03.951369 progress 55 % (4 MB)
107 18:07:03.977299 progress 60 % (4 MB)
108 18:07:04.001726 progress 65 % (5 MB)
109 18:07:04.029439 progress 70 % (5 MB)
110 18:07:04.053824 progress 75 % (6 MB)
111 18:07:04.080789 progress 80 % (6 MB)
112 18:07:04.106753 progress 85 % (7 MB)
113 18:07:04.134501 progress 90 % (7 MB)
114 18:07:04.160795 progress 95 % (7 MB)
115 18:07:04.188261 progress 100 % (8 MB)
116 18:07:04.192686 8 MB downloaded in 0.52 s (15.66 MB/s)
117 18:07:04.192926 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:07:04.193191 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:07:04.193286 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:07:04.193379 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:07:04.193462 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:07:04.193612 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:07:04.193860 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93
125 18:07:04.193993 makedir: /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin
126 18:07:04.194099 makedir: /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/tests
127 18:07:04.194199 makedir: /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/results
128 18:07:04.194316 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-add-keys
129 18:07:04.194462 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-add-sources
130 18:07:04.194593 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-background-process-start
131 18:07:04.194727 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-background-process-stop
132 18:07:04.194852 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-common-functions
133 18:07:04.194978 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-echo-ipv4
134 18:07:04.195102 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-install-packages
135 18:07:04.195228 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-installed-packages
136 18:07:04.195350 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-os-build
137 18:07:04.195474 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-probe-channel
138 18:07:04.195600 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-probe-ip
139 18:07:04.195724 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-target-ip
140 18:07:04.195846 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-target-mac
141 18:07:04.195968 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-target-storage
142 18:07:04.196098 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-case
143 18:07:04.196220 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-event
144 18:07:04.196364 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-feedback
145 18:07:04.196503 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-raise
146 18:07:04.196627 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-reference
147 18:07:04.196749 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-runner
148 18:07:04.196871 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-set
149 18:07:04.196997 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-test-shell
150 18:07:04.197123 Updating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-install-packages (oe)
151 18:07:04.197273 Updating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/bin/lava-installed-packages (oe)
152 18:07:04.197398 Creating /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/environment
153 18:07:04.197497 LAVA metadata
154 18:07:04.197569 - LAVA_JOB_ID=14291388
155 18:07:04.197633 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:07:04.197802 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:07:04.197876 skipped lava-vland-overlay
158 18:07:04.197950 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:07:04.198031 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:07:04.198105 skipped lava-multinode-overlay
161 18:07:04.198178 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:07:04.198263 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:07:04.198337 Loading test definitions
164 18:07:04.198426 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:07:04.198497 Using /lava-14291388 at stage 0
166 18:07:04.198810 uuid=14291388_1.5.2.3.1 testdef=None
167 18:07:04.198904 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:07:04.198989 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:07:04.199506 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:07:04.199817 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:07:04.200537 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:07:04.200768 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:07:04.201375 runner path: /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/0/tests/0_igt-kms-mediatek test_uuid 14291388_1.5.2.3.1
176 18:07:04.201533 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:07:04.201739 Creating lava-test-runner.conf files
179 18:07:04.201803 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291388/lava-overlay-2dqeab93/lava-14291388/0 for stage 0
180 18:07:04.201893 - 0_igt-kms-mediatek
181 18:07:04.201989 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:07:04.202073 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:07:04.209268 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:07:04.209376 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:07:04.209462 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:07:04.209547 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:07:04.209634 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:07:05.953870 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 18:07:05.954249 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 18:07:05.954366 extracting modules file /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291388/extract-overlay-ramdisk-v9l6tcuw/ramdisk
191 18:07:06.188876 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:07:06.189036 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 18:07:06.189130 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291388/compress-overlay-32pta3g7/overlay-1.5.2.4.tar.gz to ramdisk
194 18:07:06.189201 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291388/compress-overlay-32pta3g7/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291388/extract-overlay-ramdisk-v9l6tcuw/ramdisk
195 18:07:06.195930 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:07:06.196057 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 18:07:06.196148 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:07:06.196240 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 18:07:06.196325 Building ramdisk /var/lib/lava/dispatcher/tmp/14291388/extract-overlay-ramdisk-v9l6tcuw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291388/extract-overlay-ramdisk-v9l6tcuw/ramdisk
200 18:07:07.588721 >> 465983 blocks
201 18:07:14.055790 rename /var/lib/lava/dispatcher/tmp/14291388/extract-overlay-ramdisk-v9l6tcuw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/ramdisk/ramdisk.cpio.gz
202 18:07:14.056317 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 18:07:14.056512 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 18:07:14.056675 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 18:07:14.056838 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/kernel/Image']
206 18:07:28.203208 Returned 0 in 14 seconds
207 18:07:28.303809 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/kernel/image.itb
208 18:07:29.137343 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:07:29.137740 output: Created: Tue Jun 11 19:07:28 2024
210 18:07:29.137845 output: Image 0 (kernel-1)
211 18:07:29.137946 output: Description:
212 18:07:29.138037 output: Created: Tue Jun 11 19:07:28 2024
213 18:07:29.138141 output: Type: Kernel Image
214 18:07:29.138211 output: Compression: lzma compressed
215 18:07:29.138283 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:07:29.138347 output: Architecture: AArch64
217 18:07:29.138408 output: OS: Linux
218 18:07:29.138469 output: Load Address: 0x00000000
219 18:07:29.138530 output: Entry Point: 0x00000000
220 18:07:29.138597 output: Hash algo: crc32
221 18:07:29.138658 output: Hash value: 7a9e9d3e
222 18:07:29.138715 output: Image 1 (fdt-1)
223 18:07:29.138771 output: Description: mt8192-asurada-spherion-r0
224 18:07:29.138828 output: Created: Tue Jun 11 19:07:28 2024
225 18:07:29.138888 output: Type: Flat Device Tree
226 18:07:29.138944 output: Compression: uncompressed
227 18:07:29.138998 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:07:29.139052 output: Architecture: AArch64
229 18:07:29.139105 output: Hash algo: crc32
230 18:07:29.139163 output: Hash value: 0f8e4d2e
231 18:07:29.139217 output: Image 2 (ramdisk-1)
232 18:07:29.139270 output: Description: unavailable
233 18:07:29.139323 output: Created: Tue Jun 11 19:07:28 2024
234 18:07:29.139376 output: Type: RAMDisk Image
235 18:07:29.139433 output: Compression: Unknown Compression
236 18:07:29.139491 output: Data Size: 61002343 Bytes = 59572.60 KiB = 58.18 MiB
237 18:07:29.139545 output: Architecture: AArch64
238 18:07:29.139598 output: OS: Linux
239 18:07:29.139652 output: Load Address: unavailable
240 18:07:29.139705 output: Entry Point: unavailable
241 18:07:29.139764 output: Hash algo: crc32
242 18:07:29.139817 output: Hash value: ce811fb0
243 18:07:29.139871 output: Default Configuration: 'conf-1'
244 18:07:29.139923 output: Configuration 0 (conf-1)
245 18:07:29.139979 output: Description: mt8192-asurada-spherion-r0
246 18:07:29.140108 output: Kernel: kernel-1
247 18:07:29.140202 output: Init Ramdisk: ramdisk-1
248 18:07:29.140307 output: FDT: fdt-1
249 18:07:29.140433 output: Loadables: kernel-1
250 18:07:29.140516 output:
251 18:07:29.140763 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 18:07:29.140898 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 18:07:29.141040 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 18:07:29.141142 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 18:07:29.141228 No LXC device requested
256 18:07:29.141309 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:07:29.141396 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 18:07:29.141480 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:07:29.141555 Checking files for TFTP limit of 4294967296 bytes.
260 18:07:29.142060 end: 1 tftp-deploy (duration 00:00:26) [common]
261 18:07:29.142167 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:07:29.142260 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:07:29.142403 substitutions:
264 18:07:29.142471 - {DTB}: 14291388/tftp-deploy-_npp91nq/dtb/mt8192-asurada-spherion-r0.dtb
265 18:07:29.142538 - {INITRD}: 14291388/tftp-deploy-_npp91nq/ramdisk/ramdisk.cpio.gz
266 18:07:29.142604 - {KERNEL}: 14291388/tftp-deploy-_npp91nq/kernel/Image
267 18:07:29.142665 - {LAVA_MAC}: None
268 18:07:29.142723 - {PRESEED_CONFIG}: None
269 18:07:29.142780 - {PRESEED_LOCAL}: None
270 18:07:29.142835 - {RAMDISK}: 14291388/tftp-deploy-_npp91nq/ramdisk/ramdisk.cpio.gz
271 18:07:29.142897 - {ROOT_PART}: None
272 18:07:29.142954 - {ROOT}: None
273 18:07:29.143009 - {SERVER_IP}: 192.168.201.1
274 18:07:29.143064 - {TEE}: None
275 18:07:29.143121 Parsed boot commands:
276 18:07:29.143184 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:07:29.143355 Parsed boot commands: tftpboot 192.168.201.1 14291388/tftp-deploy-_npp91nq/kernel/image.itb 14291388/tftp-deploy-_npp91nq/kernel/cmdline
278 18:07:29.143450 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:07:29.143534 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:07:29.143630 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:07:29.143740 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:07:29.143822 Not connected, no need to disconnect.
283 18:07:29.143901 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:07:29.143993 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:07:29.144065 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 18:07:29.147927 Setting prompt string to ['lava-test: # ']
287 18:07:29.148373 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:07:29.148541 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:07:29.148645 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:07:29.148771 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:07:29.149086 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 18:07:34.283857 >> Command sent successfully.
293 18:07:34.286257 Returned 0 in 5 seconds
294 18:07:34.386662 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 18:07:34.387127 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 18:07:34.387244 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 18:07:34.387369 Setting prompt string to 'Starting depthcharge on Spherion...'
299 18:07:34.387474 Changing prompt to 'Starting depthcharge on Spherion...'
300 18:07:34.387587 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 18:07:34.388184 [Enter `^Ec?' for help]
302 18:07:34.559226
303 18:07:34.559410
304 18:07:34.559494 F0: 102B 0000
305 18:07:34.559571
306 18:07:34.559662 F3: 1001 0000 [0200]
307 18:07:34.559723
308 18:07:34.563163 F3: 1001 0000
309 18:07:34.563271
310 18:07:34.563338 F7: 102D 0000
311 18:07:34.563416
312 18:07:34.563488 F1: 0000 0000
313 18:07:34.563546
314 18:07:34.566952 V0: 0000 0000 [0001]
315 18:07:34.567038
316 18:07:34.567121 00: 0007 8000
317 18:07:34.567203
318 18:07:34.571193 01: 0000 0000
319 18:07:34.571287
320 18:07:34.571353 BP: 0C00 0209 [0000]
321 18:07:34.571414
322 18:07:34.571472 G0: 1182 0000
323 18:07:34.571530
324 18:07:34.574767 EC: 0000 0021 [4000]
325 18:07:34.574854
326 18:07:34.574919 S7: 0000 0000 [0000]
327 18:07:34.578170
328 18:07:34.578261 CC: 0000 0000 [0001]
329 18:07:34.578341
330 18:07:34.581578 T0: 0000 0040 [010F]
331 18:07:34.581665
332 18:07:34.581731 Jump to BL
333 18:07:34.581791
334 18:07:34.606023
335 18:07:34.606183
336 18:07:34.612764 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 18:07:34.616751 ARM64: Exception handlers installed.
338 18:07:34.620562 ARM64: Testing exception
339 18:07:34.623922 ARM64: Done test exception
340 18:07:34.631686 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 18:07:34.641551 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 18:07:34.648523 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 18:07:34.658938 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 18:07:34.665200 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 18:07:34.672299 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 18:07:34.682433 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 18:07:34.689356 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 18:07:34.709293 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 18:07:34.711964 WDT: Last reset was cold boot
350 18:07:34.715399 SPI1(PAD0) initialized at 2873684 Hz
351 18:07:34.718745 SPI5(PAD0) initialized at 992727 Hz
352 18:07:34.722512 VBOOT: Loading verstage.
353 18:07:34.728778 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 18:07:34.733610 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 18:07:34.736668 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 18:07:34.740314 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 18:07:34.746820 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 18:07:34.753632 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 18:07:34.764130 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 18:07:34.764290
361 18:07:34.764432
362 18:07:34.774494 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 18:07:34.777680 ARM64: Exception handlers installed.
364 18:07:34.781001 ARM64: Testing exception
365 18:07:34.781103 ARM64: Done test exception
366 18:07:34.788046 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 18:07:34.790825 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 18:07:34.804914 Probing TPM: . done!
369 18:07:34.805056 TPM ready after 0 ms
370 18:07:34.812141 Connected to device vid:did:rid of 1ae0:0028:00
371 18:07:34.818845 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 18:07:34.879514 Initialized TPM device CR50 revision 0
373 18:07:34.888649 tlcl_send_startup: Startup return code is 0
374 18:07:34.888823 TPM: setup succeeded
375 18:07:34.899823 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 18:07:34.908850 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 18:07:34.922499 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 18:07:34.931537 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 18:07:34.935165 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 18:07:34.939237 in-header: 03 07 00 00 08 00 00 00
381 18:07:34.943470 in-data: aa e4 47 04 13 02 00 00
382 18:07:34.946920 Chrome EC: UHEPI supported
383 18:07:34.954541 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 18:07:34.958208 in-header: 03 95 00 00 08 00 00 00
385 18:07:34.958314 in-data: 18 20 20 08 00 00 00 00
386 18:07:34.961612 Phase 1
387 18:07:34.965232 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 18:07:34.968843 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 18:07:34.976542 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 18:07:34.980263 Recovery requested (1009000e)
391 18:07:34.989482 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:07:34.993781 tlcl_extend: response is 0
393 18:07:35.003201 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:07:35.008702 tlcl_extend: response is 0
395 18:07:35.015047 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:07:35.035200 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
397 18:07:35.042202 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:07:35.042330
399 18:07:35.042400
400 18:07:35.051768 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:07:35.055125 ARM64: Exception handlers installed.
402 18:07:35.058435 ARM64: Testing exception
403 18:07:35.058569 ARM64: Done test exception
404 18:07:35.081052 pmic_efuse_setting: Set efuses in 11 msecs
405 18:07:35.084381 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:07:35.090827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:07:35.094356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:07:35.101904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:07:35.105242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:07:35.109643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:07:35.113323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:07:35.120821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:07:35.124213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:07:35.128032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:07:35.132154 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:07:35.139528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:07:35.143152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:07:35.146735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:07:35.154331 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:07:35.158016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:07:35.165244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:07:35.169097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:07:35.176882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:07:35.180209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:07:35.188056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:07:35.191595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:07:35.198479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:07:35.202231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:07:35.209954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:07:35.214192 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:07:35.221141 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:07:35.225331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:07:35.228954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:07:35.236047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:07:35.239562 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:07:35.243198 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:07:35.251091 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:07:35.254716 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:07:35.258784 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:07:35.265337 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:07:35.269438 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:07:35.276771 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:07:35.280922 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:07:35.285079 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:07:35.288623 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:07:35.291477 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:07:35.299467 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:07:35.303372 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:07:35.306961 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:07:35.310853 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:07:35.314861 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:07:35.318232 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:07:35.321777 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:07:35.329507 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:07:35.333089 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:07:35.336638 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:07:35.343963 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 18:07:35.351446 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:07:35.355643 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:07:35.366425 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:07:35.373684 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:07:35.377251 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:07:35.381272 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:07:35.388459 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:07:35.392624 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0xd
466 18:07:35.399635 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 18:07:35.404049 [RTC]rtc_osc_init,62: osc32con val = 0xde71
468 18:07:35.407383 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:07:35.418282 [RTC]rtc_get_frequency_meter,154: input=15, output=759
470 18:07:35.428110 [RTC]rtc_get_frequency_meter,154: input=23, output=941
471 18:07:35.437201 [RTC]rtc_get_frequency_meter,154: input=19, output=851
472 18:07:35.447304 [RTC]rtc_get_frequency_meter,154: input=17, output=803
473 18:07:35.456349 [RTC]rtc_get_frequency_meter,154: input=16, output=782
474 18:07:35.466858 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 18:07:35.476495 [RTC]rtc_get_frequency_meter,154: input=17, output=804
476 18:07:35.479875 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 18:07:35.483434 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 18:07:35.487634 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 18:07:35.494833 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 18:07:35.498652 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 18:07:35.502780 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 18:07:35.505445 ADC[4]: Raw value=906573 ID=7
483 18:07:35.505537 ADC[3]: Raw value=213441 ID=1
484 18:07:35.509854 RAM Code: 0x71
485 18:07:35.513292 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 18:07:35.517189 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 18:07:35.524597 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 18:07:35.532450 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 18:07:35.535914 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 18:07:35.540126 in-header: 03 07 00 00 08 00 00 00
491 18:07:35.543734 in-data: aa e4 47 04 13 02 00 00
492 18:07:35.547365 Chrome EC: UHEPI supported
493 18:07:35.554709 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 18:07:35.559074 in-header: 03 95 00 00 08 00 00 00
495 18:07:35.559200 in-data: 18 20 20 08 00 00 00 00
496 18:07:35.562665 MRC: failed to locate region type 0.
497 18:07:35.569736 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 18:07:35.573991 DRAM-K: Running full calibration
499 18:07:35.580701 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 18:07:35.580834 header.status = 0x0
501 18:07:35.584244 header.version = 0x6 (expected: 0x6)
502 18:07:35.588548 header.size = 0xd00 (expected: 0xd00)
503 18:07:35.588652 header.flags = 0x0
504 18:07:35.595537 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 18:07:35.613813 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 18:07:35.621651 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 18:07:35.625184 dram_init: ddr_geometry: 2
508 18:07:35.625294 [EMI] MDL number = 2
509 18:07:35.628648 [EMI] Get MDL freq = 0
510 18:07:35.628742 dram_init: ddr_type: 0
511 18:07:35.632243 is_discrete_lpddr4: 1
512 18:07:35.636346 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 18:07:35.636503
514 18:07:35.636605
515 18:07:35.636699 [Bian_co] ETT version 0.0.0.1
516 18:07:35.643137 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 18:07:35.643272
518 18:07:35.646630 dramc_set_vcore_voltage set vcore to 650000
519 18:07:35.650153 Read voltage for 800, 4
520 18:07:35.650251 Vio18 = 0
521 18:07:35.650318 Vcore = 650000
522 18:07:35.650380 Vdram = 0
523 18:07:35.654043 Vddq = 0
524 18:07:35.654134 Vmddr = 0
525 18:07:35.654201 dram_init: config_dvfs: 1
526 18:07:35.661198 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 18:07:35.665206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 18:07:35.668197 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 18:07:35.675684 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 18:07:35.678970 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 18:07:35.682029 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 18:07:35.682133 MEM_TYPE=3, freq_sel=18
533 18:07:35.685373 sv_algorithm_assistance_LP4_1600
534 18:07:35.692218 ============ PULL DRAM RESETB DOWN ============
535 18:07:35.696024 ========== PULL DRAM RESETB DOWN end =========
536 18:07:35.699817 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 18:07:35.703311 ===================================
538 18:07:35.707544 LPDDR4 DRAM CONFIGURATION
539 18:07:35.707663 ===================================
540 18:07:35.710751 EX_ROW_EN[0] = 0x0
541 18:07:35.710844 EX_ROW_EN[1] = 0x0
542 18:07:35.714696 LP4Y_EN = 0x0
543 18:07:35.714791 WORK_FSP = 0x0
544 18:07:35.718107 WL = 0x2
545 18:07:35.718270 RL = 0x2
546 18:07:35.721715 BL = 0x2
547 18:07:35.721805 RPST = 0x0
548 18:07:35.725069 RD_PRE = 0x0
549 18:07:35.725156 WR_PRE = 0x1
550 18:07:35.727982 WR_PST = 0x0
551 18:07:35.728099 DBI_WR = 0x0
552 18:07:35.731489 DBI_RD = 0x0
553 18:07:35.731626 OTF = 0x1
554 18:07:35.734976 ===================================
555 18:07:35.738399 ===================================
556 18:07:35.741992 ANA top config
557 18:07:35.745366 ===================================
558 18:07:35.745463 DLL_ASYNC_EN = 0
559 18:07:35.749170 ALL_SLAVE_EN = 1
560 18:07:35.752612 NEW_RANK_MODE = 1
561 18:07:35.755398 DLL_IDLE_MODE = 1
562 18:07:35.755490 LP45_APHY_COMB_EN = 1
563 18:07:35.758797 TX_ODT_DIS = 1
564 18:07:35.762321 NEW_8X_MODE = 1
565 18:07:35.765907 ===================================
566 18:07:35.769524 ===================================
567 18:07:35.772901 data_rate = 1600
568 18:07:35.776384 CKR = 1
569 18:07:35.776479 DQ_P2S_RATIO = 8
570 18:07:35.779784 ===================================
571 18:07:35.782931 CA_P2S_RATIO = 8
572 18:07:35.786128 DQ_CA_OPEN = 0
573 18:07:35.789474 DQ_SEMI_OPEN = 0
574 18:07:35.792887 CA_SEMI_OPEN = 0
575 18:07:35.793003 CA_FULL_RATE = 0
576 18:07:35.796426 DQ_CKDIV4_EN = 1
577 18:07:35.799611 CA_CKDIV4_EN = 1
578 18:07:35.803288 CA_PREDIV_EN = 0
579 18:07:35.806558 PH8_DLY = 0
580 18:07:35.809659 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 18:07:35.809747 DQ_AAMCK_DIV = 4
582 18:07:35.812741 CA_AAMCK_DIV = 4
583 18:07:35.816509 CA_ADMCK_DIV = 4
584 18:07:35.819664 DQ_TRACK_CA_EN = 0
585 18:07:35.823122 CA_PICK = 800
586 18:07:35.826858 CA_MCKIO = 800
587 18:07:35.826943 MCKIO_SEMI = 0
588 18:07:35.830390 PLL_FREQ = 3068
589 18:07:35.833883 DQ_UI_PI_RATIO = 32
590 18:07:35.837398 CA_UI_PI_RATIO = 0
591 18:07:35.840868 ===================================
592 18:07:35.844527 ===================================
593 18:07:35.844626 memory_type:LPDDR4
594 18:07:35.848278 GP_NUM : 10
595 18:07:35.848444 SRAM_EN : 1
596 18:07:35.852319 MD32_EN : 0
597 18:07:35.855765 ===================================
598 18:07:35.855884 [ANA_INIT] >>>>>>>>>>>>>>
599 18:07:35.859631 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 18:07:35.863660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 18:07:35.866479 ===================================
602 18:07:35.870244 data_rate = 1600,PCW = 0X7600
603 18:07:35.873660 ===================================
604 18:07:35.876552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 18:07:35.883016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 18:07:35.886508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 18:07:35.893105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 18:07:35.896482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 18:07:35.900029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 18:07:35.900124 [ANA_INIT] flow start
611 18:07:35.903606 [ANA_INIT] PLL >>>>>>>>
612 18:07:35.907203 [ANA_INIT] PLL <<<<<<<<
613 18:07:35.907286 [ANA_INIT] MIDPI >>>>>>>>
614 18:07:35.910043 [ANA_INIT] MIDPI <<<<<<<<
615 18:07:35.913342 [ANA_INIT] DLL >>>>>>>>
616 18:07:35.913419 [ANA_INIT] flow end
617 18:07:35.916678 ============ LP4 DIFF to SE enter ============
618 18:07:35.923389 ============ LP4 DIFF to SE exit ============
619 18:07:35.923488 [ANA_INIT] <<<<<<<<<<<<<
620 18:07:35.926851 [Flow] Enable top DCM control >>>>>
621 18:07:35.929928 [Flow] Enable top DCM control <<<<<
622 18:07:35.933659 Enable DLL master slave shuffle
623 18:07:35.940311 ==============================================================
624 18:07:35.940443 Gating Mode config
625 18:07:35.946526 ==============================================================
626 18:07:35.949926 Config description:
627 18:07:35.960106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 18:07:35.966834 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 18:07:35.970267 SELPH_MODE 0: By rank 1: By Phase
630 18:07:35.977121 ==============================================================
631 18:07:35.980364 GAT_TRACK_EN = 1
632 18:07:35.980478 RX_GATING_MODE = 2
633 18:07:35.983189 RX_GATING_TRACK_MODE = 2
634 18:07:35.986768 SELPH_MODE = 1
635 18:07:35.990228 PICG_EARLY_EN = 1
636 18:07:35.993041 VALID_LAT_VALUE = 1
637 18:07:36.000139 ==============================================================
638 18:07:36.003791 Enter into Gating configuration >>>>
639 18:07:36.007311 Exit from Gating configuration <<<<
640 18:07:36.009969 Enter into DVFS_PRE_config >>>>>
641 18:07:36.020290 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 18:07:36.023675 Exit from DVFS_PRE_config <<<<<
643 18:07:36.026588 Enter into PICG configuration >>>>
644 18:07:36.030285 Exit from PICG configuration <<<<
645 18:07:36.033769 [RX_INPUT] configuration >>>>>
646 18:07:36.037267 [RX_INPUT] configuration <<<<<
647 18:07:36.040156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 18:07:36.047050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 18:07:36.050139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 18:07:36.057150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 18:07:36.063495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 18:07:36.070340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 18:07:36.073568 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 18:07:36.076835 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 18:07:36.083545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 18:07:36.086846 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 18:07:36.090654 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 18:07:36.097237 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 18:07:36.100649 ===================================
660 18:07:36.100744 LPDDR4 DRAM CONFIGURATION
661 18:07:36.103575 ===================================
662 18:07:36.106964 EX_ROW_EN[0] = 0x0
663 18:07:36.107045 EX_ROW_EN[1] = 0x0
664 18:07:36.110354 LP4Y_EN = 0x0
665 18:07:36.110429 WORK_FSP = 0x0
666 18:07:36.113697 WL = 0x2
667 18:07:36.113781 RL = 0x2
668 18:07:36.117162 BL = 0x2
669 18:07:36.117263 RPST = 0x0
670 18:07:36.120669 RD_PRE = 0x0
671 18:07:36.120749 WR_PRE = 0x1
672 18:07:36.123532 WR_PST = 0x0
673 18:07:36.127291 DBI_WR = 0x0
674 18:07:36.127379 DBI_RD = 0x0
675 18:07:36.130745 OTF = 0x1
676 18:07:36.134188 ===================================
677 18:07:36.136933 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 18:07:36.140602 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 18:07:36.144046 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 18:07:36.146967 ===================================
681 18:07:36.150226 LPDDR4 DRAM CONFIGURATION
682 18:07:36.153660 ===================================
683 18:07:36.157046 EX_ROW_EN[0] = 0x10
684 18:07:36.157131 EX_ROW_EN[1] = 0x0
685 18:07:36.160492 LP4Y_EN = 0x0
686 18:07:36.160589 WORK_FSP = 0x0
687 18:07:36.163737 WL = 0x2
688 18:07:36.163824 RL = 0x2
689 18:07:36.167173 BL = 0x2
690 18:07:36.167248 RPST = 0x0
691 18:07:36.169922 RD_PRE = 0x0
692 18:07:36.170011 WR_PRE = 0x1
693 18:07:36.173410 WR_PST = 0x0
694 18:07:36.173506 DBI_WR = 0x0
695 18:07:36.176721 DBI_RD = 0x0
696 18:07:36.176800 OTF = 0x1
697 18:07:36.180580 ===================================
698 18:07:36.186562 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 18:07:36.191746 nWR fixed to 40
700 18:07:36.194871 [ModeRegInit_LP4] CH0 RK0
701 18:07:36.194952 [ModeRegInit_LP4] CH0 RK1
702 18:07:36.198499 [ModeRegInit_LP4] CH1 RK0
703 18:07:36.201708 [ModeRegInit_LP4] CH1 RK1
704 18:07:36.201796 match AC timing 13
705 18:07:36.208614 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 18:07:36.212021 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 18:07:36.214965 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 18:07:36.222288 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 18:07:36.225407 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 18:07:36.225505 [EMI DOE] emi_dcm 0
711 18:07:36.232538 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 18:07:36.232657 ==
713 18:07:36.235659 Dram Type= 6, Freq= 0, CH_0, rank 0
714 18:07:36.238442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 18:07:36.238534 ==
716 18:07:36.245431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 18:07:36.248510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 18:07:36.258885 [CA 0] Center 36 (6~67) winsize 62
719 18:07:36.262369 [CA 1] Center 36 (6~67) winsize 62
720 18:07:36.265750 [CA 2] Center 34 (4~65) winsize 62
721 18:07:36.269116 [CA 3] Center 33 (3~64) winsize 62
722 18:07:36.272524 [CA 4] Center 33 (2~64) winsize 63
723 18:07:36.276026 [CA 5] Center 32 (2~62) winsize 61
724 18:07:36.276127
725 18:07:36.279495 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 18:07:36.279579
727 18:07:36.282947 [CATrainingPosCal] consider 1 rank data
728 18:07:36.285873 u2DelayCellTimex100 = 270/100 ps
729 18:07:36.289336 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 18:07:36.292803 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 18:07:36.299843 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 18:07:36.302348 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 18:07:36.305887 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
734 18:07:36.309378 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
735 18:07:36.309470
736 18:07:36.312678 CA PerBit enable=1, Macro0, CA PI delay=32
737 18:07:36.312772
738 18:07:36.315977 [CBTSetCACLKResult] CA Dly = 32
739 18:07:36.316066 CS Dly: 5 (0~36)
740 18:07:36.316155 ==
741 18:07:36.319328 Dram Type= 6, Freq= 0, CH_0, rank 1
742 18:07:36.325958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 18:07:36.326085 ==
744 18:07:36.329540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 18:07:36.335759 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 18:07:36.345501 [CA 0] Center 36 (6~67) winsize 62
747 18:07:36.348586 [CA 1] Center 36 (6~67) winsize 62
748 18:07:36.352281 [CA 2] Center 34 (4~65) winsize 62
749 18:07:36.355507 [CA 3] Center 34 (4~65) winsize 62
750 18:07:36.359036 [CA 4] Center 33 (2~64) winsize 63
751 18:07:36.361805 [CA 5] Center 32 (2~63) winsize 62
752 18:07:36.361902
753 18:07:36.365522 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 18:07:36.365611
755 18:07:36.369142 [CATrainingPosCal] consider 2 rank data
756 18:07:36.372197 u2DelayCellTimex100 = 270/100 ps
757 18:07:36.375552 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 18:07:36.378883 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 18:07:36.385592 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
760 18:07:36.389224 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
761 18:07:36.391930 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
762 18:07:36.395565 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
763 18:07:36.395659
764 18:07:36.398753 CA PerBit enable=1, Macro0, CA PI delay=32
765 18:07:36.398841
766 18:07:36.401857 [CBTSetCACLKResult] CA Dly = 32
767 18:07:36.401944 CS Dly: 5 (0~37)
768 18:07:36.402012
769 18:07:36.405633 ----->DramcWriteLeveling(PI) begin...
770 18:07:36.408935 ==
771 18:07:36.409074 Dram Type= 6, Freq= 0, CH_0, rank 0
772 18:07:36.413321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 18:07:36.416705 ==
774 18:07:36.416802 Write leveling (Byte 0): 33 => 33
775 18:07:36.420262 Write leveling (Byte 1): 32 => 32
776 18:07:36.424284 DramcWriteLeveling(PI) end<-----
777 18:07:36.424419
778 18:07:36.424488 ==
779 18:07:36.427857 Dram Type= 6, Freq= 0, CH_0, rank 0
780 18:07:36.430555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 18:07:36.430638 ==
782 18:07:36.434026 [Gating] SW mode calibration
783 18:07:36.441403 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 18:07:36.447896 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 18:07:36.451578 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 18:07:36.454930 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 18:07:36.461488 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
788 18:07:36.465107 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 18:07:36.468183 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:07:36.474567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:07:36.477997 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:07:36.481434 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:07:36.484625 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:07:36.491159 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:07:36.495113 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:07:36.497984 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:07:36.504784 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:07:36.508292 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 18:07:36.511706 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 18:07:36.518610 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:07:36.521487 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:07:36.524975 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 18:07:36.531344 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
804 18:07:36.535264 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 18:07:36.537961 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:07:36.545138 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:07:36.548289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:07:36.551632 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 18:07:36.557987 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 18:07:36.561334 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 18:07:36.565157 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
812 18:07:36.571848 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
813 18:07:36.574738 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:07:36.578110 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:07:36.581535 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 18:07:36.588683 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 18:07:36.591583 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 18:07:36.594796 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
819 18:07:36.601687 0 10 8 | B1->B0 | 3131 2727 | 0 0 | (0 1) (0 0)
820 18:07:36.604571 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 18:07:36.608268 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:07:36.615118 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:07:36.618352 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 18:07:36.621784 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 18:07:36.628286 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 18:07:36.631733 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:07:36.635263 0 11 8 | B1->B0 | 2c2c 4343 | 0 0 | (1 1) (0 0)
828 18:07:36.641679 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
829 18:07:36.645195 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:07:36.648715 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:07:36.651512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 18:07:36.658353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 18:07:36.661675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 18:07:36.664849 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 18:07:36.671362 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 18:07:36.674832 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 18:07:36.678347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:07:36.684715 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:07:36.688228 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:07:36.691662 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:07:36.698404 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:07:36.701397 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:07:36.704927 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:07:36.711965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:07:36.715329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:07:36.718418 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:07:36.724874 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 18:07:36.728532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 18:07:36.731786 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 18:07:36.735509 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 18:07:36.742041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 18:07:36.745282 Total UI for P1: 0, mck2ui 16
853 18:07:36.748639 best dqsien dly found for B0: ( 0, 14, 6)
854 18:07:36.752107 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 18:07:36.755471 Total UI for P1: 0, mck2ui 16
856 18:07:36.759116 best dqsien dly found for B1: ( 0, 14, 8)
857 18:07:36.763236 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 18:07:36.766892 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 18:07:36.766997
860 18:07:36.769957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 18:07:36.773300 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 18:07:36.776597 [Gating] SW calibration Done
863 18:07:36.776735 ==
864 18:07:36.779839 Dram Type= 6, Freq= 0, CH_0, rank 0
865 18:07:36.782924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 18:07:36.783017 ==
867 18:07:36.786685 RX Vref Scan: 0
868 18:07:36.786774
869 18:07:36.786840 RX Vref 0 -> 0, step: 1
870 18:07:36.786901
871 18:07:36.789556 RX Delay -130 -> 252, step: 16
872 18:07:36.793275 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 18:07:36.799951 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
874 18:07:36.803071 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 18:07:36.806511 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
876 18:07:36.809965 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
877 18:07:36.813586 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
878 18:07:36.819848 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
879 18:07:36.823369 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
880 18:07:36.826555 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
881 18:07:36.829897 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
882 18:07:36.833342 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 18:07:36.839577 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
884 18:07:36.843035 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 18:07:36.846663 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
886 18:07:36.849834 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
887 18:07:36.853253 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 18:07:36.856615 ==
889 18:07:36.856709 Dram Type= 6, Freq= 0, CH_0, rank 0
890 18:07:36.863591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 18:07:36.863710 ==
892 18:07:36.863781 DQS Delay:
893 18:07:36.866500 DQS0 = 0, DQS1 = 0
894 18:07:36.866588 DQM Delay:
895 18:07:36.869622 DQM0 = 89, DQM1 = 82
896 18:07:36.869723 DQ Delay:
897 18:07:36.873640 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 18:07:36.876767 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 18:07:36.880028 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
900 18:07:36.883413 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
901 18:07:36.883509
902 18:07:36.883576
903 18:07:36.883636 ==
904 18:07:36.886937 Dram Type= 6, Freq= 0, CH_0, rank 0
905 18:07:36.890421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 18:07:36.890516 ==
907 18:07:36.890584
908 18:07:36.890645
909 18:07:36.893889 TX Vref Scan disable
910 18:07:36.893992 == TX Byte 0 ==
911 18:07:36.899957 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
912 18:07:36.903519 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
913 18:07:36.903614 == TX Byte 1 ==
914 18:07:36.910399 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
915 18:07:36.913542 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
916 18:07:36.913644 ==
917 18:07:36.917018 Dram Type= 6, Freq= 0, CH_0, rank 0
918 18:07:36.920452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 18:07:36.920547 ==
920 18:07:36.934160 TX Vref=22, minBit 8, minWin=26, winSum=447
921 18:07:36.937513 TX Vref=24, minBit 9, minWin=27, winSum=450
922 18:07:36.940929 TX Vref=26, minBit 10, minWin=27, winSum=454
923 18:07:36.944571 TX Vref=28, minBit 0, minWin=28, winSum=455
924 18:07:36.947238 TX Vref=30, minBit 5, minWin=28, winSum=458
925 18:07:36.953931 TX Vref=32, minBit 11, minWin=27, winSum=453
926 18:07:36.957485 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
927 18:07:36.957582
928 18:07:36.960969 Final TX Range 1 Vref 30
929 18:07:36.961061
930 18:07:36.961127 ==
931 18:07:36.963984 Dram Type= 6, Freq= 0, CH_0, rank 0
932 18:07:36.967392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 18:07:36.967481 ==
934 18:07:36.967555
935 18:07:36.970942
936 18:07:36.971029 TX Vref Scan disable
937 18:07:36.974399 == TX Byte 0 ==
938 18:07:36.977822 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
939 18:07:36.981199 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
940 18:07:36.984373 == TX Byte 1 ==
941 18:07:36.987650 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 18:07:36.990821 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 18:07:36.994635
944 18:07:36.994738 [DATLAT]
945 18:07:36.994829 Freq=800, CH0 RK0
946 18:07:36.994911
947 18:07:36.997499 DATLAT Default: 0xa
948 18:07:36.997593 0, 0xFFFF, sum = 0
949 18:07:37.000861 1, 0xFFFF, sum = 0
950 18:07:37.000954 2, 0xFFFF, sum = 0
951 18:07:37.004442 3, 0xFFFF, sum = 0
952 18:07:37.004587 4, 0xFFFF, sum = 0
953 18:07:37.007864 5, 0xFFFF, sum = 0
954 18:07:37.007960 6, 0xFFFF, sum = 0
955 18:07:37.011168 7, 0xFFFF, sum = 0
956 18:07:37.014763 8, 0xFFFF, sum = 0
957 18:07:37.014890 9, 0x0, sum = 1
958 18:07:37.014958 10, 0x0, sum = 2
959 18:07:37.017352 11, 0x0, sum = 3
960 18:07:37.017432 12, 0x0, sum = 4
961 18:07:37.021179 best_step = 10
962 18:07:37.021261
963 18:07:37.021329 ==
964 18:07:37.024486 Dram Type= 6, Freq= 0, CH_0, rank 0
965 18:07:37.027304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 18:07:37.027416 ==
967 18:07:37.031021 RX Vref Scan: 1
968 18:07:37.031099
969 18:07:37.031160 Set Vref Range= 32 -> 127
970 18:07:37.031224
971 18:07:37.034259 RX Vref 32 -> 127, step: 1
972 18:07:37.034341
973 18:07:37.037531 RX Delay -79 -> 252, step: 8
974 18:07:37.037619
975 18:07:37.041149 Set Vref, RX VrefLevel [Byte0]: 32
976 18:07:37.044498 [Byte1]: 32
977 18:07:37.044620
978 18:07:37.047813 Set Vref, RX VrefLevel [Byte0]: 33
979 18:07:37.050660 [Byte1]: 33
980 18:07:37.054660
981 18:07:37.054760 Set Vref, RX VrefLevel [Byte0]: 34
982 18:07:37.057481 [Byte1]: 34
983 18:07:37.062348
984 18:07:37.062493 Set Vref, RX VrefLevel [Byte0]: 35
985 18:07:37.065105 [Byte1]: 35
986 18:07:37.069903
987 18:07:37.070007 Set Vref, RX VrefLevel [Byte0]: 36
988 18:07:37.073240 [Byte1]: 36
989 18:07:37.077518
990 18:07:37.077612 Set Vref, RX VrefLevel [Byte0]: 37
991 18:07:37.081025 [Byte1]: 37
992 18:07:37.084553
993 18:07:37.084646 Set Vref, RX VrefLevel [Byte0]: 38
994 18:07:37.088195 [Byte1]: 38
995 18:07:37.092714
996 18:07:37.092858 Set Vref, RX VrefLevel [Byte0]: 39
997 18:07:37.095222 [Byte1]: 39
998 18:07:37.099918
999 18:07:37.100038 Set Vref, RX VrefLevel [Byte0]: 40
1000 18:07:37.103340 [Byte1]: 40
1001 18:07:37.107402
1002 18:07:37.110142 Set Vref, RX VrefLevel [Byte0]: 41
1003 18:07:37.110229 [Byte1]: 41
1004 18:07:37.114951
1005 18:07:37.115037 Set Vref, RX VrefLevel [Byte0]: 42
1006 18:07:37.118562 [Byte1]: 42
1007 18:07:37.122558
1008 18:07:37.122718 Set Vref, RX VrefLevel [Byte0]: 43
1009 18:07:37.125392 [Byte1]: 43
1010 18:07:37.129980
1011 18:07:37.130072 Set Vref, RX VrefLevel [Byte0]: 44
1012 18:07:37.133058 [Byte1]: 44
1013 18:07:37.137361
1014 18:07:37.137486 Set Vref, RX VrefLevel [Byte0]: 45
1015 18:07:37.140804 [Byte1]: 45
1016 18:07:37.145185
1017 18:07:37.145309 Set Vref, RX VrefLevel [Byte0]: 46
1018 18:07:37.148588 [Byte1]: 46
1019 18:07:37.152696
1020 18:07:37.152786 Set Vref, RX VrefLevel [Byte0]: 47
1021 18:07:37.156136 [Byte1]: 47
1022 18:07:37.160218
1023 18:07:37.160307 Set Vref, RX VrefLevel [Byte0]: 48
1024 18:07:37.163266 [Byte1]: 48
1025 18:07:37.168046
1026 18:07:37.168133 Set Vref, RX VrefLevel [Byte0]: 49
1027 18:07:37.170803 [Byte1]: 49
1028 18:07:37.175087
1029 18:07:37.175176 Set Vref, RX VrefLevel [Byte0]: 50
1030 18:07:37.178670 [Byte1]: 50
1031 18:07:37.182829
1032 18:07:37.182931 Set Vref, RX VrefLevel [Byte0]: 51
1033 18:07:37.186435 [Byte1]: 51
1034 18:07:37.190104
1035 18:07:37.190184 Set Vref, RX VrefLevel [Byte0]: 52
1036 18:07:37.193625 [Byte1]: 52
1037 18:07:37.197785
1038 18:07:37.197871 Set Vref, RX VrefLevel [Byte0]: 53
1039 18:07:37.201315 [Byte1]: 53
1040 18:07:37.205414
1041 18:07:37.205496 Set Vref, RX VrefLevel [Byte0]: 54
1042 18:07:37.208811 [Byte1]: 54
1043 18:07:37.213040
1044 18:07:37.213126 Set Vref, RX VrefLevel [Byte0]: 55
1045 18:07:37.216437 [Byte1]: 55
1046 18:07:37.220692
1047 18:07:37.220775 Set Vref, RX VrefLevel [Byte0]: 56
1048 18:07:37.223489 [Byte1]: 56
1049 18:07:37.228580
1050 18:07:37.228668 Set Vref, RX VrefLevel [Byte0]: 57
1051 18:07:37.231741 [Byte1]: 57
1052 18:07:37.235344
1053 18:07:37.235431 Set Vref, RX VrefLevel [Byte0]: 58
1054 18:07:37.238815 [Byte1]: 58
1055 18:07:37.243098
1056 18:07:37.243180 Set Vref, RX VrefLevel [Byte0]: 59
1057 18:07:37.246606 [Byte1]: 59
1058 18:07:37.250709
1059 18:07:37.250798 Set Vref, RX VrefLevel [Byte0]: 60
1060 18:07:37.254549 [Byte1]: 60
1061 18:07:37.258442
1062 18:07:37.258524 Set Vref, RX VrefLevel [Byte0]: 61
1063 18:07:37.261687 [Byte1]: 61
1064 18:07:37.265829
1065 18:07:37.265927 Set Vref, RX VrefLevel [Byte0]: 62
1066 18:07:37.268825 [Byte1]: 62
1067 18:07:37.273039
1068 18:07:37.273131 Set Vref, RX VrefLevel [Byte0]: 63
1069 18:07:37.276685 [Byte1]: 63
1070 18:07:37.280928
1071 18:07:37.281052 Set Vref, RX VrefLevel [Byte0]: 64
1072 18:07:37.284350 [Byte1]: 64
1073 18:07:37.288612
1074 18:07:37.288700 Set Vref, RX VrefLevel [Byte0]: 65
1075 18:07:37.291510 [Byte1]: 65
1076 18:07:37.295744
1077 18:07:37.295822 Set Vref, RX VrefLevel [Byte0]: 66
1078 18:07:37.299344 [Byte1]: 66
1079 18:07:37.303726
1080 18:07:37.303808 Set Vref, RX VrefLevel [Byte0]: 67
1081 18:07:37.307121 [Byte1]: 67
1082 18:07:37.311387
1083 18:07:37.311479 Set Vref, RX VrefLevel [Byte0]: 68
1084 18:07:37.314115 [Byte1]: 68
1085 18:07:37.318687
1086 18:07:37.318779 Set Vref, RX VrefLevel [Byte0]: 69
1087 18:07:37.322355 [Byte1]: 69
1088 18:07:37.326342
1089 18:07:37.326433 Set Vref, RX VrefLevel [Byte0]: 70
1090 18:07:37.329110 [Byte1]: 70
1091 18:07:37.333590
1092 18:07:37.333681 Set Vref, RX VrefLevel [Byte0]: 71
1093 18:07:37.336882 [Byte1]: 71
1094 18:07:37.341287
1095 18:07:37.341379 Set Vref, RX VrefLevel [Byte0]: 72
1096 18:07:37.344664 [Byte1]: 72
1097 18:07:37.348814
1098 18:07:37.348900 Set Vref, RX VrefLevel [Byte0]: 73
1099 18:07:37.352414 [Byte1]: 73
1100 18:07:37.356600
1101 18:07:37.356686 Set Vref, RX VrefLevel [Byte0]: 74
1102 18:07:37.359453 [Byte1]: 74
1103 18:07:37.363742
1104 18:07:37.363841 Set Vref, RX VrefLevel [Byte0]: 75
1105 18:07:37.367366 [Byte1]: 75
1106 18:07:37.371513
1107 18:07:37.371599 Set Vref, RX VrefLevel [Byte0]: 76
1108 18:07:37.374765 [Byte1]: 76
1109 18:07:37.379365
1110 18:07:37.379451 Set Vref, RX VrefLevel [Byte0]: 77
1111 18:07:37.382721 [Byte1]: 77
1112 18:07:37.386686
1113 18:07:37.386780 Set Vref, RX VrefLevel [Byte0]: 78
1114 18:07:37.390150 [Byte1]: 78
1115 18:07:37.394392
1116 18:07:37.394481 Final RX Vref Byte 0 = 50 to rank0
1117 18:07:37.397377 Final RX Vref Byte 1 = 56 to rank0
1118 18:07:37.400940 Final RX Vref Byte 0 = 50 to rank1
1119 18:07:37.403919 Final RX Vref Byte 1 = 56 to rank1==
1120 18:07:37.407156 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 18:07:37.410823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 18:07:37.414425 ==
1123 18:07:37.414514 DQS Delay:
1124 18:07:37.414580 DQS0 = 0, DQS1 = 0
1125 18:07:37.417888 DQM Delay:
1126 18:07:37.417973 DQM0 = 91, DQM1 = 84
1127 18:07:37.420725 DQ Delay:
1128 18:07:37.420908 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1129 18:07:37.427683 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1130 18:07:37.430585 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1131 18:07:37.433993 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1132 18:07:37.434079
1133 18:07:37.434142
1134 18:07:37.440822 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1135 18:07:37.444541 CH0 RK0: MR19=606, MR18=4A41
1136 18:07:37.450956 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1137 18:07:37.451083
1138 18:07:37.454507 ----->DramcWriteLeveling(PI) begin...
1139 18:07:37.454594 ==
1140 18:07:37.457330 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 18:07:37.460861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 18:07:37.460998 ==
1143 18:07:37.463735 Write leveling (Byte 0): 33 => 33
1144 18:07:37.467295 Write leveling (Byte 1): 29 => 29
1145 18:07:37.470787 DramcWriteLeveling(PI) end<-----
1146 18:07:37.470898
1147 18:07:37.470990 ==
1148 18:07:37.474327 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 18:07:37.477574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 18:07:37.477680 ==
1151 18:07:37.521436 [Gating] SW mode calibration
1152 18:07:37.521885 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 18:07:37.522025 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 18:07:37.522133 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 18:07:37.522220 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 18:07:37.522313 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 18:07:37.522409 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:07:37.522516 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:07:37.522606 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:07:37.540080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:07:37.540256 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:07:37.540580 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:07:37.540651 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:07:37.543430 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:07:37.547105 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:07:37.550120 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 18:07:37.553786 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 18:07:37.560236 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 18:07:37.563788 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 18:07:37.567355 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:07:37.573653 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:07:37.577099 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 18:07:37.580567 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:07:37.587003 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:07:37.590324 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 18:07:37.594247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 18:07:37.600365 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 18:07:37.603941 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 18:07:37.607309 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 18:07:37.610881 0 9 8 | B1->B0 | 2f2f 2c2c | 0 1 | (0 0) (0 0)
1181 18:07:37.617175 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:07:37.620590 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 18:07:37.623987 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 18:07:37.630304 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 18:07:37.633859 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 18:07:37.637410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 18:07:37.643861 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1188 18:07:37.647206 0 10 8 | B1->B0 | 2a2a 2929 | 1 0 | (1 0) (0 1)
1189 18:07:37.650886 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:07:37.654894 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 18:07:37.661936 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 18:07:37.665326 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 18:07:37.668816 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 18:07:37.672125 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 18:07:37.679194 0 11 4 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (0 0)
1196 18:07:37.683282 0 11 8 | B1->B0 | 3d3d 3b3b | 0 0 | (0 0) (0 0)
1197 18:07:37.686630 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:07:37.689789 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 18:07:37.696517 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 18:07:37.699640 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 18:07:37.703138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 18:07:37.710078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 18:07:37.713548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 18:07:37.716315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1205 18:07:37.723514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:07:37.726867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:07:37.730391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:07:37.733209 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:07:37.740247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:07:37.743826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:07:37.746768 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:07:37.753208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:07:37.756556 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:07:37.760652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 18:07:37.766801 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 18:07:37.770205 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 18:07:37.773704 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 18:07:37.780114 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 18:07:37.783737 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 18:07:37.787195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 18:07:37.790461 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 18:07:37.793860 Total UI for P1: 0, mck2ui 16
1223 18:07:37.797196 best dqsien dly found for B0: ( 0, 14, 8)
1224 18:07:37.800685 Total UI for P1: 0, mck2ui 16
1225 18:07:37.803788 best dqsien dly found for B1: ( 0, 14, 8)
1226 18:07:37.807220 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1227 18:07:37.810001 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 18:07:37.813779
1229 18:07:37.817093 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 18:07:37.820238 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 18:07:37.823396 [Gating] SW calibration Done
1232 18:07:37.823523 ==
1233 18:07:37.827436 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 18:07:37.830201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 18:07:37.830293 ==
1236 18:07:37.830383 RX Vref Scan: 0
1237 18:07:37.830464
1238 18:07:37.833722 RX Vref 0 -> 0, step: 1
1239 18:07:37.833807
1240 18:07:37.837273 RX Delay -130 -> 252, step: 16
1241 18:07:37.840730 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1242 18:07:37.843545 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1243 18:07:37.850568 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1244 18:07:37.854068 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1245 18:07:37.856841 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1246 18:07:37.860386 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1247 18:07:37.863747 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1248 18:07:37.870384 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1249 18:07:37.873806 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1250 18:07:37.876973 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1251 18:07:37.880308 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1252 18:07:37.883790 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1253 18:07:37.890305 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1254 18:07:37.893965 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1255 18:07:37.896812 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1256 18:07:37.900444 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1257 18:07:37.900537 ==
1258 18:07:37.903971 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 18:07:37.907428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 18:07:37.910267 ==
1261 18:07:37.910387 DQS Delay:
1262 18:07:37.910489 DQS0 = 0, DQS1 = 0
1263 18:07:37.913672 DQM Delay:
1264 18:07:37.913755 DQM0 = 90, DQM1 = 83
1265 18:07:37.917061 DQ Delay:
1266 18:07:37.917171 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1267 18:07:37.920717 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1268 18:07:37.924140 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1269 18:07:37.926799 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1270 18:07:37.930714
1271 18:07:37.930827
1272 18:07:37.930931 ==
1273 18:07:37.933834 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 18:07:37.937061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 18:07:37.937146 ==
1276 18:07:37.937237
1277 18:07:37.937325
1278 18:07:37.940367 TX Vref Scan disable
1279 18:07:37.940454 == TX Byte 0 ==
1280 18:07:37.947051 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1281 18:07:37.950346 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1282 18:07:37.950440 == TX Byte 1 ==
1283 18:07:37.957260 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1284 18:07:37.960737 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1285 18:07:37.960859 ==
1286 18:07:37.963518 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 18:07:37.967254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 18:07:37.967374 ==
1289 18:07:37.981037 TX Vref=22, minBit 8, minWin=27, winSum=450
1290 18:07:37.984544 TX Vref=24, minBit 4, minWin=28, winSum=456
1291 18:07:37.987986 TX Vref=26, minBit 4, minWin=28, winSum=456
1292 18:07:37.991588 TX Vref=28, minBit 4, minWin=28, winSum=459
1293 18:07:37.995152 TX Vref=30, minBit 4, minWin=28, winSum=456
1294 18:07:37.997655 TX Vref=32, minBit 8, minWin=27, winSum=452
1295 18:07:38.004607 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
1296 18:07:38.004721
1297 18:07:38.007432 Final TX Range 1 Vref 28
1298 18:07:38.007517
1299 18:07:38.007609 ==
1300 18:07:38.010995 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 18:07:38.014708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 18:07:38.014796 ==
1303 18:07:38.017462
1304 18:07:38.017544
1305 18:07:38.017608 TX Vref Scan disable
1306 18:07:38.021491 == TX Byte 0 ==
1307 18:07:38.024183 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1308 18:07:38.027581 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1309 18:07:38.031126 == TX Byte 1 ==
1310 18:07:38.034601 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1311 18:07:38.038117 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1312 18:07:38.040918
1313 18:07:38.041007 [DATLAT]
1314 18:07:38.041070 Freq=800, CH0 RK1
1315 18:07:38.041130
1316 18:07:38.044428 DATLAT Default: 0xa
1317 18:07:38.044513 0, 0xFFFF, sum = 0
1318 18:07:38.047866 1, 0xFFFF, sum = 0
1319 18:07:38.047972 2, 0xFFFF, sum = 0
1320 18:07:38.051365 3, 0xFFFF, sum = 0
1321 18:07:38.051480 4, 0xFFFF, sum = 0
1322 18:07:38.054729 5, 0xFFFF, sum = 0
1323 18:07:38.054802 6, 0xFFFF, sum = 0
1324 18:07:38.058078 7, 0xFFFF, sum = 0
1325 18:07:38.058163 8, 0xFFFF, sum = 0
1326 18:07:38.061334 9, 0x0, sum = 1
1327 18:07:38.061420 10, 0x0, sum = 2
1328 18:07:38.064327 11, 0x0, sum = 3
1329 18:07:38.064458 12, 0x0, sum = 4
1330 18:07:38.068009 best_step = 10
1331 18:07:38.068095
1332 18:07:38.068159 ==
1333 18:07:38.071089 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 18:07:38.074697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 18:07:38.074822 ==
1336 18:07:38.077855 RX Vref Scan: 0
1337 18:07:38.077941
1338 18:07:38.078005 RX Vref 0 -> 0, step: 1
1339 18:07:38.078065
1340 18:07:38.080942 RX Delay -79 -> 252, step: 8
1341 18:07:38.087800 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1342 18:07:38.091142 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1343 18:07:38.094361 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 18:07:38.098344 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1345 18:07:38.101225 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1346 18:07:38.107898 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1347 18:07:38.111478 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1348 18:07:38.114239 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 18:07:38.117737 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1350 18:07:38.121191 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1351 18:07:38.127577 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1352 18:07:38.131186 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1353 18:07:38.134576 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 18:07:38.137864 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1355 18:07:38.140748 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 18:07:38.147583 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 18:07:38.147691 ==
1358 18:07:38.151098 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 18:07:38.154416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 18:07:38.154544 ==
1361 18:07:38.154638 DQS Delay:
1362 18:07:38.157513 DQS0 = 0, DQS1 = 0
1363 18:07:38.157596 DQM Delay:
1364 18:07:38.161204 DQM0 = 92, DQM1 = 82
1365 18:07:38.161316 DQ Delay:
1366 18:07:38.164453 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1367 18:07:38.167950 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1368 18:07:38.170570 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1369 18:07:38.174075 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1370 18:07:38.174163
1371 18:07:38.174227
1372 18:07:38.180928 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1373 18:07:38.184560 CH0 RK1: MR19=606, MR18=4111
1374 18:07:38.191629 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 18:07:38.194324 [RxdqsGatingPostProcess] freq 800
1376 18:07:38.200834 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 18:07:38.204805 Pre-setting of DQS Precalculation
1378 18:07:38.207799 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 18:07:38.207902 ==
1380 18:07:38.211258 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 18:07:38.214447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 18:07:38.214529 ==
1383 18:07:38.221300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 18:07:38.227752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 18:07:38.236200 [CA 0] Center 36 (6~67) winsize 62
1386 18:07:38.239571 [CA 1] Center 36 (6~67) winsize 62
1387 18:07:38.242411 [CA 2] Center 35 (5~65) winsize 61
1388 18:07:38.245878 [CA 3] Center 34 (4~65) winsize 62
1389 18:07:38.249381 [CA 4] Center 34 (4~65) winsize 62
1390 18:07:38.252900 [CA 5] Center 34 (4~65) winsize 62
1391 18:07:38.252991
1392 18:07:38.256467 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1393 18:07:38.256546
1394 18:07:38.259265 [CATrainingPosCal] consider 1 rank data
1395 18:07:38.262765 u2DelayCellTimex100 = 270/100 ps
1396 18:07:38.266273 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 18:07:38.269820 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 18:07:38.275728 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 18:07:38.279250 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 18:07:38.282817 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 18:07:38.286197 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 18:07:38.286292
1403 18:07:38.289047 CA PerBit enable=1, Macro0, CA PI delay=34
1404 18:07:38.289164
1405 18:07:38.292954 [CBTSetCACLKResult] CA Dly = 34
1406 18:07:38.293050 CS Dly: 6 (0~37)
1407 18:07:38.293150 ==
1408 18:07:38.295980 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 18:07:38.302374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 18:07:38.302483 ==
1411 18:07:38.305751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 18:07:38.312878 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 18:07:38.322574 [CA 0] Center 36 (6~67) winsize 62
1414 18:07:38.325947 [CA 1] Center 37 (7~68) winsize 62
1415 18:07:38.329651 [CA 2] Center 35 (5~66) winsize 62
1416 18:07:38.333279 [CA 3] Center 34 (4~65) winsize 62
1417 18:07:38.337276 [CA 4] Center 35 (4~66) winsize 63
1418 18:07:38.341210 [CA 5] Center 34 (4~65) winsize 62
1419 18:07:38.341316
1420 18:07:38.344947 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 18:07:38.345061
1422 18:07:38.345142 [CATrainingPosCal] consider 2 rank data
1423 18:07:38.348955 u2DelayCellTimex100 = 270/100 ps
1424 18:07:38.352479 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 18:07:38.355810 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1426 18:07:38.362456 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 18:07:38.365323 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 18:07:38.368971 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 18:07:38.372307 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 18:07:38.372468
1431 18:07:38.375991 CA PerBit enable=1, Macro0, CA PI delay=34
1432 18:07:38.376119
1433 18:07:38.379375 [CBTSetCACLKResult] CA Dly = 34
1434 18:07:38.379461 CS Dly: 6 (0~38)
1435 18:07:38.379526
1436 18:07:38.382193 ----->DramcWriteLeveling(PI) begin...
1437 18:07:38.382304 ==
1438 18:07:38.385757 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 18:07:38.392608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 18:07:38.392730 ==
1441 18:07:38.396111 Write leveling (Byte 0): 26 => 26
1442 18:07:38.399493 Write leveling (Byte 1): 26 => 26
1443 18:07:38.399587 DramcWriteLeveling(PI) end<-----
1444 18:07:38.399654
1445 18:07:38.402433 ==
1446 18:07:38.405999 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 18:07:38.408933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 18:07:38.409029 ==
1449 18:07:38.412406 [Gating] SW mode calibration
1450 18:07:38.419480 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 18:07:38.422367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 18:07:38.429317 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 18:07:38.432322 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 18:07:38.435963 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:07:38.442375 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:07:38.445687 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:07:38.449150 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:07:38.456255 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:07:38.459374 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:07:38.462250 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 18:07:38.466298 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 18:07:38.472356 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:07:38.476125 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:07:38.479098 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 18:07:38.485717 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 18:07:38.489342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 18:07:38.492809 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 18:07:38.499573 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 18:07:38.502923 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 18:07:38.506281 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 18:07:38.512391 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:07:38.515947 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 18:07:38.519527 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 18:07:38.525741 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 18:07:38.529246 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 18:07:38.532831 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 18:07:38.539146 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1478 18:07:38.542816 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1479 18:07:38.546242 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 18:07:38.552764 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 18:07:38.555944 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 18:07:38.559261 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 18:07:38.562775 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 18:07:38.569047 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 18:07:38.572469 0 10 4 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (1 0)
1486 18:07:38.575517 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1487 18:07:38.582533 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 18:07:38.586028 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 18:07:38.589351 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 18:07:38.595584 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 18:07:38.599309 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 18:07:38.602611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 18:07:38.609161 0 11 4 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
1494 18:07:38.612528 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1495 18:07:38.615846 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:07:38.622327 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 18:07:38.625654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 18:07:38.629069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 18:07:38.635718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 18:07:38.639184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 18:07:38.642660 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 18:07:38.648949 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:07:38.652383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:07:38.655972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:07:38.662398 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:07:38.665711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:07:38.669048 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:07:38.672359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:07:38.679178 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:07:38.682560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:07:38.686222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 18:07:38.692334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 18:07:38.695900 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 18:07:38.699557 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 18:07:38.706443 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 18:07:38.709242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 18:07:38.712667 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 18:07:38.719398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 18:07:38.719509 Total UI for P1: 0, mck2ui 16
1520 18:07:38.722754 best dqsien dly found for B0: ( 0, 14, 4)
1521 18:07:38.725958 Total UI for P1: 0, mck2ui 16
1522 18:07:38.729614 best dqsien dly found for B1: ( 0, 14, 4)
1523 18:07:38.733072 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1524 18:07:38.739151 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 18:07:38.739260
1526 18:07:38.742488 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 18:07:38.746195 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 18:07:38.749224 [Gating] SW calibration Done
1529 18:07:38.749340 ==
1530 18:07:38.753111 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 18:07:38.755826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 18:07:38.755941 ==
1533 18:07:38.756042 RX Vref Scan: 0
1534 18:07:38.756142
1535 18:07:38.759332 RX Vref 0 -> 0, step: 1
1536 18:07:38.759438
1537 18:07:38.762799 RX Delay -130 -> 252, step: 16
1538 18:07:38.766321 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 18:07:38.769819 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 18:07:38.776031 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 18:07:38.779757 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 18:07:38.782959 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 18:07:38.786565 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 18:07:38.789221 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1545 18:07:38.796370 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 18:07:38.799813 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 18:07:38.802599 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 18:07:38.806137 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 18:07:38.809578 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 18:07:38.816659 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 18:07:38.819830 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1552 18:07:38.822863 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 18:07:38.826426 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1554 18:07:38.826524 ==
1555 18:07:38.830066 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 18:07:38.832853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 18:07:38.836245 ==
1558 18:07:38.836335 DQS Delay:
1559 18:07:38.836426 DQS0 = 0, DQS1 = 0
1560 18:07:38.839771 DQM Delay:
1561 18:07:38.839856 DQM0 = 93, DQM1 = 89
1562 18:07:38.843264 DQ Delay:
1563 18:07:38.846588 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 18:07:38.846679 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1565 18:07:38.849663 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 18:07:38.856148 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1567 18:07:38.856296
1568 18:07:38.856422
1569 18:07:38.856524 ==
1570 18:07:38.859669 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 18:07:38.863130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 18:07:38.863222 ==
1573 18:07:38.863323
1574 18:07:38.863422
1575 18:07:38.866257 TX Vref Scan disable
1576 18:07:38.866378 == TX Byte 0 ==
1577 18:07:38.873166 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 18:07:38.876332 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 18:07:38.876485 == TX Byte 1 ==
1580 18:07:38.882974 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1581 18:07:38.886341 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1582 18:07:38.886464 ==
1583 18:07:38.889465 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 18:07:38.892866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 18:07:38.892959 ==
1586 18:07:38.906675 TX Vref=22, minBit 0, minWin=26, winSum=429
1587 18:07:38.910345 TX Vref=24, minBit 0, minWin=26, winSum=440
1588 18:07:38.913615 TX Vref=26, minBit 1, minWin=27, winSum=441
1589 18:07:38.916437 TX Vref=28, minBit 3, minWin=26, winSum=447
1590 18:07:38.920035 TX Vref=30, minBit 1, minWin=27, winSum=447
1591 18:07:38.923323 TX Vref=32, minBit 0, minWin=27, winSum=443
1592 18:07:38.930113 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30
1593 18:07:38.930230
1594 18:07:38.933574 Final TX Range 1 Vref 30
1595 18:07:38.933698
1596 18:07:38.933793 ==
1597 18:07:38.937142 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 18:07:38.940839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 18:07:38.940926 ==
1600 18:07:38.940991
1601 18:07:38.941051
1602 18:07:38.943604 TX Vref Scan disable
1603 18:07:38.947040 == TX Byte 0 ==
1604 18:07:38.950675 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 18:07:38.954245 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 18:07:38.956936 == TX Byte 1 ==
1607 18:07:38.960537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1608 18:07:38.963868 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1609 18:07:38.963982
1610 18:07:38.967407 [DATLAT]
1611 18:07:38.967516 Freq=800, CH1 RK0
1612 18:07:38.967602
1613 18:07:38.970745 DATLAT Default: 0xa
1614 18:07:38.970866 0, 0xFFFF, sum = 0
1615 18:07:38.974181 1, 0xFFFF, sum = 0
1616 18:07:38.974306 2, 0xFFFF, sum = 0
1617 18:07:38.977341 3, 0xFFFF, sum = 0
1618 18:07:38.977422 4, 0xFFFF, sum = 0
1619 18:07:38.980224 5, 0xFFFF, sum = 0
1620 18:07:38.980348 6, 0xFFFF, sum = 0
1621 18:07:38.983992 7, 0xFFFF, sum = 0
1622 18:07:38.984115 8, 0xFFFF, sum = 0
1623 18:07:38.987483 9, 0x0, sum = 1
1624 18:07:38.987596 10, 0x0, sum = 2
1625 18:07:38.990509 11, 0x0, sum = 3
1626 18:07:38.990669 12, 0x0, sum = 4
1627 18:07:38.993980 best_step = 10
1628 18:07:38.994065
1629 18:07:38.994129 ==
1630 18:07:38.997151 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 18:07:39.000913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 18:07:39.001029 ==
1633 18:07:39.001122 RX Vref Scan: 1
1634 18:07:39.004239
1635 18:07:39.004352 Set Vref Range= 32 -> 127
1636 18:07:39.004460
1637 18:07:39.007033 RX Vref 32 -> 127, step: 1
1638 18:07:39.007107
1639 18:07:39.010695 RX Delay -79 -> 252, step: 8
1640 18:07:39.010798
1641 18:07:39.014323 Set Vref, RX VrefLevel [Byte0]: 32
1642 18:07:39.017094 [Byte1]: 32
1643 18:07:39.017195
1644 18:07:39.020625 Set Vref, RX VrefLevel [Byte0]: 33
1645 18:07:39.024261 [Byte1]: 33
1646 18:07:39.024397
1647 18:07:39.027063 Set Vref, RX VrefLevel [Byte0]: 34
1648 18:07:39.030386 [Byte1]: 34
1649 18:07:39.034801
1650 18:07:39.034933 Set Vref, RX VrefLevel [Byte0]: 35
1651 18:07:39.038006 [Byte1]: 35
1652 18:07:39.042146
1653 18:07:39.042285 Set Vref, RX VrefLevel [Byte0]: 36
1654 18:07:39.044971 [Byte1]: 36
1655 18:07:39.049293
1656 18:07:39.049402 Set Vref, RX VrefLevel [Byte0]: 37
1657 18:07:39.052724 [Byte1]: 37
1658 18:07:39.057053
1659 18:07:39.057167 Set Vref, RX VrefLevel [Byte0]: 38
1660 18:07:39.060577 [Byte1]: 38
1661 18:07:39.064862
1662 18:07:39.065011 Set Vref, RX VrefLevel [Byte0]: 39
1663 18:07:39.067567 [Byte1]: 39
1664 18:07:39.071947
1665 18:07:39.072067 Set Vref, RX VrefLevel [Byte0]: 40
1666 18:07:39.075562 [Byte1]: 40
1667 18:07:39.079769
1668 18:07:39.079881 Set Vref, RX VrefLevel [Byte0]: 41
1669 18:07:39.083156 [Byte1]: 41
1670 18:07:39.087300
1671 18:07:39.087450 Set Vref, RX VrefLevel [Byte0]: 42
1672 18:07:39.090048 [Byte1]: 42
1673 18:07:39.094803
1674 18:07:39.094918 Set Vref, RX VrefLevel [Byte0]: 43
1675 18:07:39.097916 [Byte1]: 43
1676 18:07:39.102384
1677 18:07:39.102478 Set Vref, RX VrefLevel [Byte0]: 44
1678 18:07:39.105196 [Byte1]: 44
1679 18:07:39.109749
1680 18:07:39.109845 Set Vref, RX VrefLevel [Byte0]: 45
1681 18:07:39.113508 [Byte1]: 45
1682 18:07:39.117629
1683 18:07:39.117722 Set Vref, RX VrefLevel [Byte0]: 46
1684 18:07:39.120875 [Byte1]: 46
1685 18:07:39.125197
1686 18:07:39.125289 Set Vref, RX VrefLevel [Byte0]: 47
1687 18:07:39.128183 [Byte1]: 47
1688 18:07:39.132612
1689 18:07:39.132742 Set Vref, RX VrefLevel [Byte0]: 48
1690 18:07:39.135834 [Byte1]: 48
1691 18:07:39.139877
1692 18:07:39.139990 Set Vref, RX VrefLevel [Byte0]: 49
1693 18:07:39.143329 [Byte1]: 49
1694 18:07:39.147605
1695 18:07:39.147730 Set Vref, RX VrefLevel [Byte0]: 50
1696 18:07:39.150616 [Byte1]: 50
1697 18:07:39.154826
1698 18:07:39.154914 Set Vref, RX VrefLevel [Byte0]: 51
1699 18:07:39.158421 [Byte1]: 51
1700 18:07:39.162796
1701 18:07:39.162919 Set Vref, RX VrefLevel [Byte0]: 52
1702 18:07:39.165579 [Byte1]: 52
1703 18:07:39.170419
1704 18:07:39.170550 Set Vref, RX VrefLevel [Byte0]: 53
1705 18:07:39.173799 [Byte1]: 53
1706 18:07:39.177526
1707 18:07:39.177650 Set Vref, RX VrefLevel [Byte0]: 54
1708 18:07:39.181282 [Byte1]: 54
1709 18:07:39.185518
1710 18:07:39.185621 Set Vref, RX VrefLevel [Byte0]: 55
1711 18:07:39.188351 [Byte1]: 55
1712 18:07:39.192499
1713 18:07:39.192598 Set Vref, RX VrefLevel [Byte0]: 56
1714 18:07:39.196097 [Byte1]: 56
1715 18:07:39.200277
1716 18:07:39.200411 Set Vref, RX VrefLevel [Byte0]: 57
1717 18:07:39.203673 [Byte1]: 57
1718 18:07:39.207763
1719 18:07:39.207883 Set Vref, RX VrefLevel [Byte0]: 58
1720 18:07:39.211128 [Byte1]: 58
1721 18:07:39.215014
1722 18:07:39.215135 Set Vref, RX VrefLevel [Byte0]: 59
1723 18:07:39.218377 [Byte1]: 59
1724 18:07:39.223291
1725 18:07:39.223428 Set Vref, RX VrefLevel [Byte0]: 60
1726 18:07:39.226489 [Byte1]: 60
1727 18:07:39.230719
1728 18:07:39.230815 Set Vref, RX VrefLevel [Byte0]: 61
1729 18:07:39.233619 [Byte1]: 61
1730 18:07:39.237966
1731 18:07:39.238062 Set Vref, RX VrefLevel [Byte0]: 62
1732 18:07:39.241011 [Byte1]: 62
1733 18:07:39.245970
1734 18:07:39.246075 Set Vref, RX VrefLevel [Byte0]: 63
1735 18:07:39.249219 [Byte1]: 63
1736 18:07:39.252818
1737 18:07:39.252927 Set Vref, RX VrefLevel [Byte0]: 64
1738 18:07:39.256686 [Byte1]: 64
1739 18:07:39.260759
1740 18:07:39.260879 Set Vref, RX VrefLevel [Byte0]: 65
1741 18:07:39.263730 [Byte1]: 65
1742 18:07:39.267922
1743 18:07:39.268016 Set Vref, RX VrefLevel [Byte0]: 66
1744 18:07:39.271390 [Byte1]: 66
1745 18:07:39.275676
1746 18:07:39.275776 Set Vref, RX VrefLevel [Byte0]: 67
1747 18:07:39.279448 [Byte1]: 67
1748 18:07:39.283656
1749 18:07:39.283744 Set Vref, RX VrefLevel [Byte0]: 68
1750 18:07:39.286620 [Byte1]: 68
1751 18:07:39.291176
1752 18:07:39.291286 Set Vref, RX VrefLevel [Byte0]: 69
1753 18:07:39.294402 [Byte1]: 69
1754 18:07:39.298778
1755 18:07:39.298904 Set Vref, RX VrefLevel [Byte0]: 70
1756 18:07:39.301766 [Byte1]: 70
1757 18:07:39.305684
1758 18:07:39.305798 Final RX Vref Byte 0 = 59 to rank0
1759 18:07:39.309373 Final RX Vref Byte 1 = 57 to rank0
1760 18:07:39.312852 Final RX Vref Byte 0 = 59 to rank1
1761 18:07:39.315762 Final RX Vref Byte 1 = 57 to rank1==
1762 18:07:39.319259 Dram Type= 6, Freq= 0, CH_1, rank 0
1763 18:07:39.325917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1764 18:07:39.326048 ==
1765 18:07:39.326121 DQS Delay:
1766 18:07:39.326185 DQS0 = 0, DQS1 = 0
1767 18:07:39.329252 DQM Delay:
1768 18:07:39.329334 DQM0 = 95, DQM1 = 89
1769 18:07:39.332660 DQ Delay:
1770 18:07:39.336054 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1771 18:07:39.336143 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1772 18:07:39.339656 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1773 18:07:39.346047 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1774 18:07:39.346153
1775 18:07:39.346222
1776 18:07:39.353097 [DQSOSCAuto] RK0, (LSB)MR18= 0x2845, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1777 18:07:39.356636 CH1 RK0: MR19=606, MR18=2845
1778 18:07:39.362770 CH1_RK0: MR19=0x606, MR18=0x2845, DQSOSC=392, MR23=63, INC=96, DEC=64
1779 18:07:39.362880
1780 18:07:39.366079 ----->DramcWriteLeveling(PI) begin...
1781 18:07:39.366171 ==
1782 18:07:39.369511 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 18:07:39.373066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 18:07:39.373173 ==
1785 18:07:39.376116 Write leveling (Byte 0): 27 => 27
1786 18:07:39.379697 Write leveling (Byte 1): 29 => 29
1787 18:07:39.383201 DramcWriteLeveling(PI) end<-----
1788 18:07:39.383296
1789 18:07:39.383363 ==
1790 18:07:39.386138 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 18:07:39.389687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 18:07:39.389809 ==
1793 18:07:39.392536 [Gating] SW mode calibration
1794 18:07:39.399540 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1795 18:07:39.405836 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1796 18:07:39.409495 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1797 18:07:39.413225 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1798 18:07:39.419173 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 18:07:39.422602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 18:07:39.426159 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 18:07:39.432882 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 18:07:39.435748 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 18:07:39.439444 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 18:07:39.446382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 18:07:39.449184 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 18:07:39.452650 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 18:07:39.459601 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 18:07:39.462723 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 18:07:39.466202 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 18:07:39.472509 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 18:07:39.475847 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 18:07:39.479525 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1813 18:07:39.483030 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1814 18:07:39.489273 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 18:07:39.493015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 18:07:39.495754 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 18:07:39.502761 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 18:07:39.506207 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 18:07:39.510153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 18:07:39.516298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 18:07:39.519805 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
1822 18:07:39.522517 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1823 18:07:39.529152 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 18:07:39.532512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 18:07:39.536033 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 18:07:39.542903 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 18:07:39.546166 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1828 18:07:39.549820 0 10 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1829 18:07:39.555746 0 10 4 | B1->B0 | 2c2c 2f2f | 0 0 | (1 0) (0 0)
1830 18:07:39.559260 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:07:39.562678 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 18:07:39.569415 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 18:07:39.572854 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 18:07:39.576436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 18:07:39.579124 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 18:07:39.586563 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1837 18:07:39.589391 0 11 4 | B1->B0 | 3b3b 2d2d | 1 0 | (0 0) (0 0)
1838 18:07:39.592818 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1839 18:07:39.599648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 18:07:39.603322 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 18:07:39.606475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 18:07:39.612672 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 18:07:39.616648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 18:07:39.619354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 18:07:39.626488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1846 18:07:39.629367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 18:07:39.632904 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 18:07:39.639379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 18:07:39.642696 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 18:07:39.645839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 18:07:39.653173 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 18:07:39.656481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 18:07:39.659212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 18:07:39.662722 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 18:07:39.669489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 18:07:39.672780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 18:07:39.676312 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 18:07:39.683151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 18:07:39.685907 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 18:07:39.689373 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1861 18:07:39.696394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1862 18:07:39.696511 Total UI for P1: 0, mck2ui 16
1863 18:07:39.702868 best dqsien dly found for B0: ( 0, 14, 0)
1864 18:07:39.706365 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 18:07:39.709971 Total UI for P1: 0, mck2ui 16
1866 18:07:39.713253 best dqsien dly found for B1: ( 0, 14, 4)
1867 18:07:39.715965 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1868 18:07:39.719319 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1869 18:07:39.719407
1870 18:07:39.722543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1871 18:07:39.726379 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 18:07:39.729609 [Gating] SW calibration Done
1873 18:07:39.729733 ==
1874 18:07:39.732650 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 18:07:39.736111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 18:07:39.736198 ==
1877 18:07:39.739761 RX Vref Scan: 0
1878 18:07:39.739847
1879 18:07:39.743174 RX Vref 0 -> 0, step: 1
1880 18:07:39.743248
1881 18:07:39.743312 RX Delay -130 -> 252, step: 16
1882 18:07:39.749583 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1883 18:07:39.752872 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1884 18:07:39.756404 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1885 18:07:39.759473 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1886 18:07:39.762807 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1887 18:07:39.770104 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1888 18:07:39.772869 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1889 18:07:39.776121 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1890 18:07:39.779710 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1891 18:07:39.783025 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1892 18:07:39.789854 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1893 18:07:39.792611 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1894 18:07:39.796121 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1895 18:07:39.799514 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1896 18:07:39.803047 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1897 18:07:39.809442 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1898 18:07:39.809564 ==
1899 18:07:39.812993 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 18:07:39.816471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 18:07:39.816579 ==
1902 18:07:39.816676 DQS Delay:
1903 18:07:39.819942 DQS0 = 0, DQS1 = 0
1904 18:07:39.820027 DQM Delay:
1905 18:07:39.822762 DQM0 = 92, DQM1 = 88
1906 18:07:39.822845 DQ Delay:
1907 18:07:39.826396 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1908 18:07:39.829887 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1909 18:07:39.833301 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1910 18:07:39.836076 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1911 18:07:39.836216
1912 18:07:39.836318
1913 18:07:39.836453 ==
1914 18:07:39.839799 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 18:07:39.843141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 18:07:39.846107 ==
1917 18:07:39.846267
1918 18:07:39.846371
1919 18:07:39.846492 TX Vref Scan disable
1920 18:07:39.849560 == TX Byte 0 ==
1921 18:07:39.853486 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1922 18:07:39.856072 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1923 18:07:39.859625 == TX Byte 1 ==
1924 18:07:39.863089 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1925 18:07:39.866562 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1926 18:07:39.866674 ==
1927 18:07:39.869804 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 18:07:39.876244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 18:07:39.876412 ==
1930 18:07:39.888214 TX Vref=22, minBit 3, minWin=26, winSum=442
1931 18:07:39.891742 TX Vref=24, minBit 0, minWin=27, winSum=448
1932 18:07:39.895097 TX Vref=26, minBit 0, minWin=27, winSum=448
1933 18:07:39.898492 TX Vref=28, minBit 2, minWin=27, winSum=450
1934 18:07:39.901896 TX Vref=30, minBit 2, minWin=27, winSum=451
1935 18:07:39.904952 TX Vref=32, minBit 2, minWin=27, winSum=448
1936 18:07:39.911200 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1937 18:07:39.911315
1938 18:07:39.914888 Final TX Range 1 Vref 30
1939 18:07:39.914977
1940 18:07:39.915042 ==
1941 18:07:39.918334 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 18:07:39.921703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 18:07:39.921796 ==
1944 18:07:39.924565
1945 18:07:39.924649
1946 18:07:39.924714 TX Vref Scan disable
1947 18:07:39.928258 == TX Byte 0 ==
1948 18:07:39.931663 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 18:07:39.935196 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 18:07:39.938771 == TX Byte 1 ==
1951 18:07:39.941764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1952 18:07:39.948617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1953 18:07:39.948722
1954 18:07:39.948788 [DATLAT]
1955 18:07:39.948849 Freq=800, CH1 RK1
1956 18:07:39.948907
1957 18:07:39.951771 DATLAT Default: 0xa
1958 18:07:39.951854 0, 0xFFFF, sum = 0
1959 18:07:39.955428 1, 0xFFFF, sum = 0
1960 18:07:39.955544 2, 0xFFFF, sum = 0
1961 18:07:39.958247 3, 0xFFFF, sum = 0
1962 18:07:39.958332 4, 0xFFFF, sum = 0
1963 18:07:39.961644 5, 0xFFFF, sum = 0
1964 18:07:39.961732 6, 0xFFFF, sum = 0
1965 18:07:39.965099 7, 0xFFFF, sum = 0
1966 18:07:39.968333 8, 0xFFFF, sum = 0
1967 18:07:39.968433 9, 0x0, sum = 1
1968 18:07:39.968501 10, 0x0, sum = 2
1969 18:07:39.971851 11, 0x0, sum = 3
1970 18:07:39.971938 12, 0x0, sum = 4
1971 18:07:39.974776 best_step = 10
1972 18:07:39.974860
1973 18:07:39.974925 ==
1974 18:07:39.978007 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 18:07:39.981808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 18:07:39.981898 ==
1977 18:07:39.984918 RX Vref Scan: 0
1978 18:07:39.985004
1979 18:07:39.985070 RX Vref 0 -> 0, step: 1
1980 18:07:39.985129
1981 18:07:39.988158 RX Delay -79 -> 252, step: 8
1982 18:07:39.994610 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1983 18:07:39.998481 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1984 18:07:40.001626 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1985 18:07:40.004800 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1986 18:07:40.008116 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1987 18:07:40.014905 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1988 18:07:40.018494 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1989 18:07:40.021345 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1990 18:07:40.024630 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1991 18:07:40.028121 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1992 18:07:40.031774 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1993 18:07:40.038132 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1994 18:07:40.041611 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1995 18:07:40.045142 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1996 18:07:40.047872 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1997 18:07:40.051320 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
1998 18:07:40.054884 ==
1999 18:07:40.054991 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 18:07:40.061511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 18:07:40.061646 ==
2002 18:07:40.061728 DQS Delay:
2003 18:07:40.065019 DQS0 = 0, DQS1 = 0
2004 18:07:40.065100 DQM Delay:
2005 18:07:40.068622 DQM0 = 97, DQM1 = 91
2006 18:07:40.068704 DQ Delay:
2007 18:07:40.071264 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2008 18:07:40.075389 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2009 18:07:40.078179 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2010 18:07:40.081799 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2011 18:07:40.081898
2012 18:07:40.081977
2013 18:07:40.088764 [DQSOSCAuto] RK1, (LSB)MR18= 0x430b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
2014 18:07:40.091418 CH1 RK1: MR19=606, MR18=430B
2015 18:07:40.098678 CH1_RK1: MR19=0x606, MR18=0x430B, DQSOSC=393, MR23=63, INC=95, DEC=63
2016 18:07:40.101975 [RxdqsGatingPostProcess] freq 800
2017 18:07:40.108059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 18:07:40.108175 Pre-setting of DQS Precalculation
2019 18:07:40.114699 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 18:07:40.121833 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 18:07:40.128296 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 18:07:40.128433
2023 18:07:40.128512
2024 18:07:40.131717 [Calibration Summary] 1600 Mbps
2025 18:07:40.135046 CH 0, Rank 0
2026 18:07:40.135139 SW Impedance : PASS
2027 18:07:40.138731 DUTY Scan : NO K
2028 18:07:40.138846 ZQ Calibration : PASS
2029 18:07:40.141356 Jitter Meter : NO K
2030 18:07:40.145163 CBT Training : PASS
2031 18:07:40.145235 Write leveling : PASS
2032 18:07:40.148595 RX DQS gating : PASS
2033 18:07:40.152171 RX DQ/DQS(RDDQC) : PASS
2034 18:07:40.152242 TX DQ/DQS : PASS
2035 18:07:40.155643 RX DATLAT : PASS
2036 18:07:40.158533 RX DQ/DQS(Engine): PASS
2037 18:07:40.158651 TX OE : NO K
2038 18:07:40.161906 All Pass.
2039 18:07:40.161978
2040 18:07:40.162038 CH 0, Rank 1
2041 18:07:40.165563 SW Impedance : PASS
2042 18:07:40.165637 DUTY Scan : NO K
2043 18:07:40.168862 ZQ Calibration : PASS
2044 18:07:40.168937 Jitter Meter : NO K
2045 18:07:40.171743 CBT Training : PASS
2046 18:07:40.175190 Write leveling : PASS
2047 18:07:40.175262 RX DQS gating : PASS
2048 18:07:40.178419 RX DQ/DQS(RDDQC) : PASS
2049 18:07:40.181644 TX DQ/DQS : PASS
2050 18:07:40.181735 RX DATLAT : PASS
2051 18:07:40.185243 RX DQ/DQS(Engine): PASS
2052 18:07:40.188371 TX OE : NO K
2053 18:07:40.188477 All Pass.
2054 18:07:40.188569
2055 18:07:40.188657 CH 1, Rank 0
2056 18:07:40.191567 SW Impedance : PASS
2057 18:07:40.195230 DUTY Scan : NO K
2058 18:07:40.195312 ZQ Calibration : PASS
2059 18:07:40.198651 Jitter Meter : NO K
2060 18:07:40.201824 CBT Training : PASS
2061 18:07:40.201909 Write leveling : PASS
2062 18:07:40.205097 RX DQS gating : PASS
2063 18:07:40.208254 RX DQ/DQS(RDDQC) : PASS
2064 18:07:40.208366 TX DQ/DQS : PASS
2065 18:07:40.212012 RX DATLAT : PASS
2066 18:07:40.212094 RX DQ/DQS(Engine): PASS
2067 18:07:40.215223 TX OE : NO K
2068 18:07:40.215306 All Pass.
2069 18:07:40.215370
2070 18:07:40.218443 CH 1, Rank 1
2071 18:07:40.218524 SW Impedance : PASS
2072 18:07:40.221932 DUTY Scan : NO K
2073 18:07:40.225291 ZQ Calibration : PASS
2074 18:07:40.225374 Jitter Meter : NO K
2075 18:07:40.228600 CBT Training : PASS
2076 18:07:40.232094 Write leveling : PASS
2077 18:07:40.232205 RX DQS gating : PASS
2078 18:07:40.235364 RX DQ/DQS(RDDQC) : PASS
2079 18:07:40.238474 TX DQ/DQS : PASS
2080 18:07:40.238614 RX DATLAT : PASS
2081 18:07:40.242230 RX DQ/DQS(Engine): PASS
2082 18:07:40.245591 TX OE : NO K
2083 18:07:40.245731 All Pass.
2084 18:07:40.245847
2085 18:07:40.245963 DramC Write-DBI off
2086 18:07:40.248488 PER_BANK_REFRESH: Hybrid Mode
2087 18:07:40.252039 TX_TRACKING: ON
2088 18:07:40.254874 [GetDramInforAfterCalByMRR] Vendor 6.
2089 18:07:40.258176 [GetDramInforAfterCalByMRR] Revision 606.
2090 18:07:40.261861 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 18:07:40.261972 MR0 0x3b3b
2092 18:07:40.265073 MR8 0x5151
2093 18:07:40.268650 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 18:07:40.268769
2095 18:07:40.268872 MR0 0x3b3b
2096 18:07:40.268964 MR8 0x5151
2097 18:07:40.272097 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 18:07:40.275426
2099 18:07:40.281543 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 18:07:40.284814 [FAST_K] Save calibration result to emmc
2101 18:07:40.288810 [FAST_K] Save calibration result to emmc
2102 18:07:40.291484 dram_init: config_dvfs: 1
2103 18:07:40.295088 dramc_set_vcore_voltage set vcore to 662500
2104 18:07:40.298696 Read voltage for 1200, 2
2105 18:07:40.298800 Vio18 = 0
2106 18:07:40.302098 Vcore = 662500
2107 18:07:40.302223 Vdram = 0
2108 18:07:40.302337 Vddq = 0
2109 18:07:40.302434 Vmddr = 0
2110 18:07:40.308543 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 18:07:40.314985 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 18:07:40.315100 MEM_TYPE=3, freq_sel=15
2113 18:07:40.318437 sv_algorithm_assistance_LP4_1600
2114 18:07:40.321594 ============ PULL DRAM RESETB DOWN ============
2115 18:07:40.328395 ========== PULL DRAM RESETB DOWN end =========
2116 18:07:40.331843 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 18:07:40.335393 ===================================
2118 18:07:40.338735 LPDDR4 DRAM CONFIGURATION
2119 18:07:40.341912 ===================================
2120 18:07:40.342024 EX_ROW_EN[0] = 0x0
2121 18:07:40.345276 EX_ROW_EN[1] = 0x0
2122 18:07:40.345384 LP4Y_EN = 0x0
2123 18:07:40.348730 WORK_FSP = 0x0
2124 18:07:40.348860 WL = 0x4
2125 18:07:40.352027 RL = 0x4
2126 18:07:40.352134 BL = 0x2
2127 18:07:40.354781 RPST = 0x0
2128 18:07:40.354886 RD_PRE = 0x0
2129 18:07:40.358475 WR_PRE = 0x1
2130 18:07:40.358561 WR_PST = 0x0
2131 18:07:40.361795 DBI_WR = 0x0
2132 18:07:40.365547 DBI_RD = 0x0
2133 18:07:40.365656 OTF = 0x1
2134 18:07:40.368201 ===================================
2135 18:07:40.371775 ===================================
2136 18:07:40.371853 ANA top config
2137 18:07:40.375147 ===================================
2138 18:07:40.378599 DLL_ASYNC_EN = 0
2139 18:07:40.382128 ALL_SLAVE_EN = 0
2140 18:07:40.384909 NEW_RANK_MODE = 1
2141 18:07:40.385020 DLL_IDLE_MODE = 1
2142 18:07:40.388416 LP45_APHY_COMB_EN = 1
2143 18:07:40.391701 TX_ODT_DIS = 1
2144 18:07:40.395224 NEW_8X_MODE = 1
2145 18:07:40.398067 ===================================
2146 18:07:40.401602 ===================================
2147 18:07:40.405223 data_rate = 2400
2148 18:07:40.408700 CKR = 1
2149 18:07:40.408787 DQ_P2S_RATIO = 8
2150 18:07:40.411689 ===================================
2151 18:07:40.415295 CA_P2S_RATIO = 8
2152 18:07:40.418465 DQ_CA_OPEN = 0
2153 18:07:40.421954 DQ_SEMI_OPEN = 0
2154 18:07:40.425353 CA_SEMI_OPEN = 0
2155 18:07:40.425438 CA_FULL_RATE = 0
2156 18:07:40.428150 DQ_CKDIV4_EN = 0
2157 18:07:40.431666 CA_CKDIV4_EN = 0
2158 18:07:40.435188 CA_PREDIV_EN = 0
2159 18:07:40.438447 PH8_DLY = 17
2160 18:07:40.442226 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 18:07:40.442307 DQ_AAMCK_DIV = 4
2162 18:07:40.445490 CA_AAMCK_DIV = 4
2163 18:07:40.448423 CA_ADMCK_DIV = 4
2164 18:07:40.452012 DQ_TRACK_CA_EN = 0
2165 18:07:40.455065 CA_PICK = 1200
2166 18:07:40.458777 CA_MCKIO = 1200
2167 18:07:40.461828 MCKIO_SEMI = 0
2168 18:07:40.461904 PLL_FREQ = 2366
2169 18:07:40.465476 DQ_UI_PI_RATIO = 32
2170 18:07:40.468551 CA_UI_PI_RATIO = 0
2171 18:07:40.471943 ===================================
2172 18:07:40.475423 ===================================
2173 18:07:40.478879 memory_type:LPDDR4
2174 18:07:40.478961 GP_NUM : 10
2175 18:07:40.481851 SRAM_EN : 1
2176 18:07:40.485209 MD32_EN : 0
2177 18:07:40.488580 ===================================
2178 18:07:40.488658 [ANA_INIT] >>>>>>>>>>>>>>
2179 18:07:40.492058 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 18:07:40.495434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 18:07:40.498805 ===================================
2182 18:07:40.502302 data_rate = 2400,PCW = 0X5b00
2183 18:07:40.505669 ===================================
2184 18:07:40.509312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 18:07:40.515528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 18:07:40.519008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 18:07:40.525214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 18:07:40.528718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 18:07:40.532168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 18:07:40.532249 [ANA_INIT] flow start
2191 18:07:40.535650 [ANA_INIT] PLL >>>>>>>>
2192 18:07:40.538746 [ANA_INIT] PLL <<<<<<<<
2193 18:07:40.538825 [ANA_INIT] MIDPI >>>>>>>>
2194 18:07:40.542185 [ANA_INIT] MIDPI <<<<<<<<
2195 18:07:40.545189 [ANA_INIT] DLL >>>>>>>>
2196 18:07:40.545267 [ANA_INIT] DLL <<<<<<<<
2197 18:07:40.548800 [ANA_INIT] flow end
2198 18:07:40.552277 ============ LP4 DIFF to SE enter ============
2199 18:07:40.559017 ============ LP4 DIFF to SE exit ============
2200 18:07:40.559099 [ANA_INIT] <<<<<<<<<<<<<
2201 18:07:40.562361 [Flow] Enable top DCM control >>>>>
2202 18:07:40.565721 [Flow] Enable top DCM control <<<<<
2203 18:07:40.568547 Enable DLL master slave shuffle
2204 18:07:40.575214 ==============================================================
2205 18:07:40.575301 Gating Mode config
2206 18:07:40.582034 ==============================================================
2207 18:07:40.585314 Config description:
2208 18:07:40.592043 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 18:07:40.598716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 18:07:40.605644 SELPH_MODE 0: By rank 1: By Phase
2211 18:07:40.612318 ==============================================================
2212 18:07:40.612486 GAT_TRACK_EN = 1
2213 18:07:40.615493 RX_GATING_MODE = 2
2214 18:07:40.619137 RX_GATING_TRACK_MODE = 2
2215 18:07:40.621787 SELPH_MODE = 1
2216 18:07:40.625276 PICG_EARLY_EN = 1
2217 18:07:40.628766 VALID_LAT_VALUE = 1
2218 18:07:40.635538 ==============================================================
2219 18:07:40.639002 Enter into Gating configuration >>>>
2220 18:07:40.641805 Exit from Gating configuration <<<<
2221 18:07:40.645551 Enter into DVFS_PRE_config >>>>>
2222 18:07:40.655110 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 18:07:40.658741 Exit from DVFS_PRE_config <<<<<
2224 18:07:40.662143 Enter into PICG configuration >>>>
2225 18:07:40.665574 Exit from PICG configuration <<<<
2226 18:07:40.665668 [RX_INPUT] configuration >>>>>
2227 18:07:40.668866 [RX_INPUT] configuration <<<<<
2228 18:07:40.675498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 18:07:40.682200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 18:07:40.684995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 18:07:40.692162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 18:07:40.698407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 18:07:40.705634 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 18:07:40.708389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 18:07:40.712411 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 18:07:40.718347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 18:07:40.722268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 18:07:40.725603 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 18:07:40.728516 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 18:07:40.731827 ===================================
2241 18:07:40.735014 LPDDR4 DRAM CONFIGURATION
2242 18:07:40.738280 ===================================
2243 18:07:40.741785 EX_ROW_EN[0] = 0x0
2244 18:07:40.741886 EX_ROW_EN[1] = 0x0
2245 18:07:40.745347 LP4Y_EN = 0x0
2246 18:07:40.745419 WORK_FSP = 0x0
2247 18:07:40.748809 WL = 0x4
2248 18:07:40.748877 RL = 0x4
2249 18:07:40.751625 BL = 0x2
2250 18:07:40.751693 RPST = 0x0
2251 18:07:40.755314 RD_PRE = 0x0
2252 18:07:40.755410 WR_PRE = 0x1
2253 18:07:40.758775 WR_PST = 0x0
2254 18:07:40.758875 DBI_WR = 0x0
2255 18:07:40.761677 DBI_RD = 0x0
2256 18:07:40.765132 OTF = 0x1
2257 18:07:40.765235 ===================================
2258 18:07:40.771438 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 18:07:40.774863 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 18:07:40.778363 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 18:07:40.781975 ===================================
2262 18:07:40.785210 LPDDR4 DRAM CONFIGURATION
2263 18:07:40.788535 ===================================
2264 18:07:40.791911 EX_ROW_EN[0] = 0x10
2265 18:07:40.791993 EX_ROW_EN[1] = 0x0
2266 18:07:40.794932 LP4Y_EN = 0x0
2267 18:07:40.795008 WORK_FSP = 0x0
2268 18:07:40.798421 WL = 0x4
2269 18:07:40.798531 RL = 0x4
2270 18:07:40.801632 BL = 0x2
2271 18:07:40.801734 RPST = 0x0
2272 18:07:40.805049 RD_PRE = 0x0
2273 18:07:40.805123 WR_PRE = 0x1
2274 18:07:40.808294 WR_PST = 0x0
2275 18:07:40.808378 DBI_WR = 0x0
2276 18:07:40.811531 DBI_RD = 0x0
2277 18:07:40.811609 OTF = 0x1
2278 18:07:40.814777 ===================================
2279 18:07:40.821664 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 18:07:40.821787 ==
2281 18:07:40.825350 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 18:07:40.831898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 18:07:40.831989 ==
2284 18:07:40.832054 [Duty_Offset_Calibration]
2285 18:07:40.835514 B0:2 B1:1 CA:1
2286 18:07:40.835623
2287 18:07:40.838067 [DutyScan_Calibration_Flow] k_type=0
2288 18:07:40.847060
2289 18:07:40.847154 ==CLK 0==
2290 18:07:40.850857 Final CLK duty delay cell = 0
2291 18:07:40.853595 [0] MAX Duty = 5187%(X100), DQS PI = 24
2292 18:07:40.856944 [0] MIN Duty = 4875%(X100), DQS PI = 0
2293 18:07:40.857038 [0] AVG Duty = 5031%(X100)
2294 18:07:40.857104
2295 18:07:40.860607 CH0 CLK Duty spec in!! Max-Min= 312%
2296 18:07:40.867001 [DutyScan_Calibration_Flow] ====Done====
2297 18:07:40.867109
2298 18:07:40.870352 [DutyScan_Calibration_Flow] k_type=1
2299 18:07:40.885859
2300 18:07:40.885982 ==DQS 0 ==
2301 18:07:40.889441 Final DQS duty delay cell = -4
2302 18:07:40.892573 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2303 18:07:40.895700 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2304 18:07:40.899172 [-4] AVG Duty = 4937%(X100)
2305 18:07:40.899293
2306 18:07:40.899383 ==DQS 1 ==
2307 18:07:40.902505 Final DQS duty delay cell = 0
2308 18:07:40.905809 [0] MAX Duty = 5156%(X100), DQS PI = 62
2309 18:07:40.909560 [0] MIN Duty = 5000%(X100), DQS PI = 32
2310 18:07:40.912231 [0] AVG Duty = 5078%(X100)
2311 18:07:40.912326
2312 18:07:40.915770 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2313 18:07:40.915857
2314 18:07:40.919120 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 18:07:40.922868 [DutyScan_Calibration_Flow] ====Done====
2316 18:07:40.922984
2317 18:07:40.926054 [DutyScan_Calibration_Flow] k_type=3
2318 18:07:40.942982
2319 18:07:40.943127 ==DQM 0 ==
2320 18:07:40.945807 Final DQM duty delay cell = 0
2321 18:07:40.949247 [0] MAX Duty = 5156%(X100), DQS PI = 30
2322 18:07:40.952786 [0] MIN Duty = 4907%(X100), DQS PI = 58
2323 18:07:40.955546 [0] AVG Duty = 5031%(X100)
2324 18:07:40.955634
2325 18:07:40.955697 ==DQM 1 ==
2326 18:07:40.958941 Final DQM duty delay cell = 0
2327 18:07:40.962351 [0] MAX Duty = 5093%(X100), DQS PI = 0
2328 18:07:40.965838 [0] MIN Duty = 5031%(X100), DQS PI = 14
2329 18:07:40.965941 [0] AVG Duty = 5062%(X100)
2330 18:07:40.969389
2331 18:07:40.972759 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2332 18:07:40.972875
2333 18:07:40.976362 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2334 18:07:40.979655 [DutyScan_Calibration_Flow] ====Done====
2335 18:07:40.979755
2336 18:07:40.982374 [DutyScan_Calibration_Flow] k_type=2
2337 18:07:40.999406
2338 18:07:40.999542 ==DQ 0 ==
2339 18:07:41.002657 Final DQ duty delay cell = 0
2340 18:07:41.005389 [0] MAX Duty = 5062%(X100), DQS PI = 34
2341 18:07:41.009205 [0] MIN Duty = 4844%(X100), DQS PI = 62
2342 18:07:41.009317 [0] AVG Duty = 4953%(X100)
2343 18:07:41.012292
2344 18:07:41.012402 ==DQ 1 ==
2345 18:07:41.015774 Final DQ duty delay cell = 0
2346 18:07:41.019363 [0] MAX Duty = 5093%(X100), DQS PI = 24
2347 18:07:41.022035 [0] MIN Duty = 4938%(X100), DQS PI = 34
2348 18:07:41.022116 [0] AVG Duty = 5015%(X100)
2349 18:07:41.022177
2350 18:07:41.025619 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2351 18:07:41.029347
2352 18:07:41.032754 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2353 18:07:41.035390 [DutyScan_Calibration_Flow] ====Done====
2354 18:07:41.035460 ==
2355 18:07:41.038877 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 18:07:41.042110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 18:07:41.042187 ==
2358 18:07:41.046113 [Duty_Offset_Calibration]
2359 18:07:41.046190 B0:1 B1:0 CA:0
2360 18:07:41.046250
2361 18:07:41.049376 [DutyScan_Calibration_Flow] k_type=0
2362 18:07:41.058496
2363 18:07:41.058577 ==CLK 0==
2364 18:07:41.062006 Final CLK duty delay cell = -4
2365 18:07:41.064831 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2366 18:07:41.068446 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2367 18:07:41.071920 [-4] AVG Duty = 4953%(X100)
2368 18:07:41.072015
2369 18:07:41.075226 CH1 CLK Duty spec in!! Max-Min= 93%
2370 18:07:41.078474 [DutyScan_Calibration_Flow] ====Done====
2371 18:07:41.078559
2372 18:07:41.081442 [DutyScan_Calibration_Flow] k_type=1
2373 18:07:41.098173
2374 18:07:41.098295 ==DQS 0 ==
2375 18:07:41.101669 Final DQS duty delay cell = 0
2376 18:07:41.104509 [0] MAX Duty = 5062%(X100), DQS PI = 22
2377 18:07:41.107957 [0] MIN Duty = 4844%(X100), DQS PI = 0
2378 18:07:41.108044 [0] AVG Duty = 4953%(X100)
2379 18:07:41.108110
2380 18:07:41.111415 ==DQS 1 ==
2381 18:07:41.114683 Final DQS duty delay cell = 0
2382 18:07:41.118091 [0] MAX Duty = 5187%(X100), DQS PI = 18
2383 18:07:41.121392 [0] MIN Duty = 4969%(X100), DQS PI = 10
2384 18:07:41.121480 [0] AVG Duty = 5078%(X100)
2385 18:07:41.121546
2386 18:07:41.128449 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2387 18:07:41.128547
2388 18:07:41.131512 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2389 18:07:41.134677 [DutyScan_Calibration_Flow] ====Done====
2390 18:07:41.134765
2391 18:07:41.138002 [DutyScan_Calibration_Flow] k_type=3
2392 18:07:41.154532
2393 18:07:41.154658 ==DQM 0 ==
2394 18:07:41.157985 Final DQM duty delay cell = 0
2395 18:07:41.161277 [0] MAX Duty = 5156%(X100), DQS PI = 8
2396 18:07:41.164870 [0] MIN Duty = 5000%(X100), DQS PI = 62
2397 18:07:41.164956 [0] AVG Duty = 5078%(X100)
2398 18:07:41.167713
2399 18:07:41.167796 ==DQM 1 ==
2400 18:07:41.171355 Final DQM duty delay cell = 0
2401 18:07:41.174900 [0] MAX Duty = 5031%(X100), DQS PI = 26
2402 18:07:41.177627 [0] MIN Duty = 4875%(X100), DQS PI = 36
2403 18:07:41.177711 [0] AVG Duty = 4953%(X100)
2404 18:07:41.181287
2405 18:07:41.184890 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2406 18:07:41.184974
2407 18:07:41.188263 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 18:07:41.191553 [DutyScan_Calibration_Flow] ====Done====
2409 18:07:41.191638
2410 18:07:41.194660 [DutyScan_Calibration_Flow] k_type=2
2411 18:07:41.210599
2412 18:07:41.210734 ==DQ 0 ==
2413 18:07:41.213413 Final DQ duty delay cell = -4
2414 18:07:41.216888 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2415 18:07:41.220145 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2416 18:07:41.223522 [-4] AVG Duty = 4984%(X100)
2417 18:07:41.223611
2418 18:07:41.223678 ==DQ 1 ==
2419 18:07:41.226745 Final DQ duty delay cell = 0
2420 18:07:41.230053 [0] MAX Duty = 5125%(X100), DQS PI = 20
2421 18:07:41.233636 [0] MIN Duty = 4969%(X100), DQS PI = 12
2422 18:07:41.237202 [0] AVG Duty = 5047%(X100)
2423 18:07:41.237287
2424 18:07:41.240528 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 18:07:41.240611
2426 18:07:41.243898 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2427 18:07:41.247116 [DutyScan_Calibration_Flow] ====Done====
2428 18:07:41.250344 nWR fixed to 30
2429 18:07:41.250429 [ModeRegInit_LP4] CH0 RK0
2430 18:07:41.254021 [ModeRegInit_LP4] CH0 RK1
2431 18:07:41.256780 [ModeRegInit_LP4] CH1 RK0
2432 18:07:41.260801 [ModeRegInit_LP4] CH1 RK1
2433 18:07:41.260890 match AC timing 7
2434 18:07:41.263475 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 18:07:41.270361 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 18:07:41.274065 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 18:07:41.277534 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 18:07:41.283799 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 18:07:41.283893 ==
2440 18:07:41.287301 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 18:07:41.290860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 18:07:41.290969 ==
2443 18:07:41.297460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 18:07:41.300755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2445 18:07:41.310861 [CA 0] Center 39 (8~70) winsize 63
2446 18:07:41.313684 [CA 1] Center 39 (8~70) winsize 63
2447 18:07:41.317560 [CA 2] Center 35 (5~66) winsize 62
2448 18:07:41.320763 [CA 3] Center 34 (4~65) winsize 62
2449 18:07:41.324263 [CA 4] Center 33 (3~64) winsize 62
2450 18:07:41.326938 [CA 5] Center 32 (3~62) winsize 60
2451 18:07:41.327053
2452 18:07:41.330359 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2453 18:07:41.330435
2454 18:07:41.333773 [CATrainingPosCal] consider 1 rank data
2455 18:07:41.337033 u2DelayCellTimex100 = 270/100 ps
2456 18:07:41.340320 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 18:07:41.343767 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 18:07:41.350809 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2459 18:07:41.354154 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2460 18:07:41.357484 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2461 18:07:41.360880 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2462 18:07:41.360996
2463 18:07:41.364268 CA PerBit enable=1, Macro0, CA PI delay=32
2464 18:07:41.364385
2465 18:07:41.367217 [CBTSetCACLKResult] CA Dly = 32
2466 18:07:41.367340 CS Dly: 6 (0~37)
2467 18:07:41.367439 ==
2468 18:07:41.370470 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 18:07:41.377500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 18:07:41.377603 ==
2471 18:07:41.380866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 18:07:41.387264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 18:07:41.396292 [CA 0] Center 38 (8~69) winsize 62
2474 18:07:41.399818 [CA 1] Center 38 (8~69) winsize 62
2475 18:07:41.403392 [CA 2] Center 35 (4~66) winsize 63
2476 18:07:41.406319 [CA 3] Center 34 (4~65) winsize 62
2477 18:07:41.409552 [CA 4] Center 33 (3~63) winsize 61
2478 18:07:41.412773 [CA 5] Center 32 (3~62) winsize 60
2479 18:07:41.412861
2480 18:07:41.416347 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2481 18:07:41.416428
2482 18:07:41.419961 [CATrainingPosCal] consider 2 rank data
2483 18:07:41.423431 u2DelayCellTimex100 = 270/100 ps
2484 18:07:41.426792 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 18:07:41.430019 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 18:07:41.433274 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 18:07:41.440349 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 18:07:41.443557 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2489 18:07:41.446888 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 18:07:41.446970
2491 18:07:41.450147 CA PerBit enable=1, Macro0, CA PI delay=32
2492 18:07:41.450228
2493 18:07:41.453616 [CBTSetCACLKResult] CA Dly = 32
2494 18:07:41.453693 CS Dly: 6 (0~38)
2495 18:07:41.453757
2496 18:07:41.456521 ----->DramcWriteLeveling(PI) begin...
2497 18:07:41.456612 ==
2498 18:07:41.460027 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 18:07:41.466872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 18:07:41.466965 ==
2501 18:07:41.470259 Write leveling (Byte 0): 36 => 36
2502 18:07:41.473428 Write leveling (Byte 1): 29 => 29
2503 18:07:41.473515 DramcWriteLeveling(PI) end<-----
2504 18:07:41.473589
2505 18:07:41.476489 ==
2506 18:07:41.479831 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 18:07:41.483370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 18:07:41.483476 ==
2509 18:07:41.486935 [Gating] SW mode calibration
2510 18:07:41.493190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 18:07:41.496607 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 18:07:41.503098 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2513 18:07:41.506764 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2514 18:07:41.510223 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 18:07:41.516530 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 18:07:41.519769 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 18:07:41.523680 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 18:07:41.530087 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2519 18:07:41.533600 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2520 18:07:41.536358 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2521 18:07:41.543452 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 18:07:41.546878 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 18:07:41.549914 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 18:07:41.556408 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 18:07:41.559824 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 18:07:41.563299 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2527 18:07:41.566832 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2528 18:07:41.573751 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2529 18:07:41.577003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 18:07:41.580274 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 18:07:41.586881 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 18:07:41.590102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 18:07:41.593391 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 18:07:41.599992 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 18:07:41.603528 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 18:07:41.606501 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 18:07:41.613345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 18:07:41.616732 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 18:07:41.620350 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 18:07:41.626355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 18:07:41.629717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 18:07:41.633568 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 18:07:41.640310 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 18:07:41.643317 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 18:07:41.646665 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 18:07:41.650103 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 18:07:41.656795 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 18:07:41.660059 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 18:07:41.663385 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 18:07:41.670381 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 18:07:41.673739 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 18:07:41.677400 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 18:07:41.679945 Total UI for P1: 0, mck2ui 16
2554 18:07:41.683720 best dqsien dly found for B0: ( 1, 3, 28)
2555 18:07:41.690621 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 18:07:41.690721 Total UI for P1: 0, mck2ui 16
2557 18:07:41.696919 best dqsien dly found for B1: ( 1, 4, 0)
2558 18:07:41.700406 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2559 18:07:41.703739 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 18:07:41.703858
2561 18:07:41.707215 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2562 18:07:41.710344 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 18:07:41.713603 [Gating] SW calibration Done
2564 18:07:41.713726 ==
2565 18:07:41.717064 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 18:07:41.720149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 18:07:41.720242 ==
2568 18:07:41.724055 RX Vref Scan: 0
2569 18:07:41.724145
2570 18:07:41.724213 RX Vref 0 -> 0, step: 1
2571 18:07:41.724275
2572 18:07:41.726775 RX Delay -40 -> 252, step: 8
2573 18:07:41.730391 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 18:07:41.733775 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2575 18:07:41.740471 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 18:07:41.743836 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2577 18:07:41.747050 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 18:07:41.750389 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2579 18:07:41.753915 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 18:07:41.760014 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 18:07:41.763452 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128
2582 18:07:41.766906 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2583 18:07:41.770187 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2584 18:07:41.773590 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2585 18:07:41.780467 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2586 18:07:41.783353 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2587 18:07:41.786876 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2588 18:07:41.790120 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2589 18:07:41.790202 ==
2590 18:07:41.793318 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 18:07:41.800385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 18:07:41.800484 ==
2593 18:07:41.800553 DQS Delay:
2594 18:07:41.803404 DQS0 = 0, DQS1 = 0
2595 18:07:41.803479 DQM Delay:
2596 18:07:41.803541 DQM0 = 121, DQM1 = 112
2597 18:07:41.806749 DQ Delay:
2598 18:07:41.810296 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2599 18:07:41.813660 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2600 18:07:41.817138 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =107
2601 18:07:41.820683 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2602 18:07:41.820761
2603 18:07:41.820823
2604 18:07:41.820881 ==
2605 18:07:41.823825 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 18:07:41.826617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 18:07:41.829987 ==
2608 18:07:41.830062
2609 18:07:41.830123
2610 18:07:41.830182 TX Vref Scan disable
2611 18:07:41.833616 == TX Byte 0 ==
2612 18:07:41.837217 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2613 18:07:41.840031 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2614 18:07:41.843693 == TX Byte 1 ==
2615 18:07:41.846734 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2616 18:07:41.850130 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2617 18:07:41.850205 ==
2618 18:07:41.853625 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 18:07:41.860400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 18:07:41.860516 ==
2621 18:07:41.871305 TX Vref=22, minBit 0, minWin=24, winSum=399
2622 18:07:41.874659 TX Vref=24, minBit 0, minWin=25, winSum=410
2623 18:07:41.878533 TX Vref=26, minBit 7, minWin=25, winSum=415
2624 18:07:41.881821 TX Vref=28, minBit 4, minWin=25, winSum=416
2625 18:07:41.884792 TX Vref=30, minBit 0, minWin=26, winSum=423
2626 18:07:41.888187 TX Vref=32, minBit 10, minWin=25, winSum=419
2627 18:07:41.894602 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
2628 18:07:41.894691
2629 18:07:41.898073 Final TX Range 1 Vref 30
2630 18:07:41.898158
2631 18:07:41.898225 ==
2632 18:07:41.901405 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 18:07:41.905132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 18:07:41.905217 ==
2635 18:07:41.905283
2636 18:07:41.907985
2637 18:07:41.908071 TX Vref Scan disable
2638 18:07:41.911504 == TX Byte 0 ==
2639 18:07:41.915069 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2640 18:07:41.918706 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2641 18:07:41.921487 == TX Byte 1 ==
2642 18:07:41.925233 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 18:07:41.928602 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 18:07:41.928686
2645 18:07:41.931359 [DATLAT]
2646 18:07:41.931442 Freq=1200, CH0 RK0
2647 18:07:41.931508
2648 18:07:41.934619 DATLAT Default: 0xd
2649 18:07:41.934701 0, 0xFFFF, sum = 0
2650 18:07:41.937927 1, 0xFFFF, sum = 0
2651 18:07:41.938013 2, 0xFFFF, sum = 0
2652 18:07:41.941521 3, 0xFFFF, sum = 0
2653 18:07:41.941606 4, 0xFFFF, sum = 0
2654 18:07:41.945095 5, 0xFFFF, sum = 0
2655 18:07:41.945179 6, 0xFFFF, sum = 0
2656 18:07:41.947911 7, 0xFFFF, sum = 0
2657 18:07:41.951539 8, 0xFFFF, sum = 0
2658 18:07:41.951623 9, 0xFFFF, sum = 0
2659 18:07:41.954804 10, 0xFFFF, sum = 0
2660 18:07:41.954888 11, 0xFFFF, sum = 0
2661 18:07:41.958494 12, 0x0, sum = 1
2662 18:07:41.958577 13, 0x0, sum = 2
2663 18:07:41.961815 14, 0x0, sum = 3
2664 18:07:41.961899 15, 0x0, sum = 4
2665 18:07:41.961984 best_step = 13
2666 18:07:41.962048
2667 18:07:41.965268 ==
2668 18:07:41.965350 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 18:07:41.971549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 18:07:41.971634 ==
2671 18:07:41.971699 RX Vref Scan: 1
2672 18:07:41.971760
2673 18:07:41.974741 Set Vref Range= 32 -> 127
2674 18:07:41.974824
2675 18:07:41.978149 RX Vref 32 -> 127, step: 1
2676 18:07:41.978232
2677 18:07:41.981692 RX Delay -13 -> 252, step: 4
2678 18:07:41.981775
2679 18:07:41.985015 Set Vref, RX VrefLevel [Byte0]: 32
2680 18:07:41.988322 [Byte1]: 32
2681 18:07:41.988414
2682 18:07:41.991547 Set Vref, RX VrefLevel [Byte0]: 33
2683 18:07:41.994706 [Byte1]: 33
2684 18:07:41.994789
2685 18:07:41.998645 Set Vref, RX VrefLevel [Byte0]: 34
2686 18:07:42.001462 [Byte1]: 34
2687 18:07:42.005706
2688 18:07:42.005787 Set Vref, RX VrefLevel [Byte0]: 35
2689 18:07:42.009087 [Byte1]: 35
2690 18:07:42.013481
2691 18:07:42.013563 Set Vref, RX VrefLevel [Byte0]: 36
2692 18:07:42.016555 [Byte1]: 36
2693 18:07:42.021337
2694 18:07:42.021420 Set Vref, RX VrefLevel [Byte0]: 37
2695 18:07:42.024754 [Byte1]: 37
2696 18:07:42.029586
2697 18:07:42.029669 Set Vref, RX VrefLevel [Byte0]: 38
2698 18:07:42.032352 [Byte1]: 38
2699 18:07:42.037526
2700 18:07:42.037613 Set Vref, RX VrefLevel [Byte0]: 39
2701 18:07:42.040298 [Byte1]: 39
2702 18:07:42.044892
2703 18:07:42.044975 Set Vref, RX VrefLevel [Byte0]: 40
2704 18:07:42.048565 [Byte1]: 40
2705 18:07:42.052868
2706 18:07:42.052978 Set Vref, RX VrefLevel [Byte0]: 41
2707 18:07:42.056307 [Byte1]: 41
2708 18:07:42.061208
2709 18:07:42.061293 Set Vref, RX VrefLevel [Byte0]: 42
2710 18:07:42.064041 [Byte1]: 42
2711 18:07:42.069075
2712 18:07:42.069161 Set Vref, RX VrefLevel [Byte0]: 43
2713 18:07:42.072051 [Byte1]: 43
2714 18:07:42.076705
2715 18:07:42.076787 Set Vref, RX VrefLevel [Byte0]: 44
2716 18:07:42.079945 [Byte1]: 44
2717 18:07:42.084406
2718 18:07:42.084488 Set Vref, RX VrefLevel [Byte0]: 45
2719 18:07:42.087698 [Byte1]: 45
2720 18:07:42.092321
2721 18:07:42.092413 Set Vref, RX VrefLevel [Byte0]: 46
2722 18:07:42.095754 [Byte1]: 46
2723 18:07:42.100603
2724 18:07:42.100687 Set Vref, RX VrefLevel [Byte0]: 47
2725 18:07:42.103808 [Byte1]: 47
2726 18:07:42.108018
2727 18:07:42.108100 Set Vref, RX VrefLevel [Byte0]: 48
2728 18:07:42.111981 [Byte1]: 48
2729 18:07:42.115947
2730 18:07:42.116030 Set Vref, RX VrefLevel [Byte0]: 49
2731 18:07:42.119403 [Byte1]: 49
2732 18:07:42.124077
2733 18:07:42.124159 Set Vref, RX VrefLevel [Byte0]: 50
2734 18:07:42.127464 [Byte1]: 50
2735 18:07:42.132121
2736 18:07:42.132204 Set Vref, RX VrefLevel [Byte0]: 51
2737 18:07:42.134901 [Byte1]: 51
2738 18:07:42.139798
2739 18:07:42.139880 Set Vref, RX VrefLevel [Byte0]: 52
2740 18:07:42.143212 [Byte1]: 52
2741 18:07:42.147374
2742 18:07:42.147456 Set Vref, RX VrefLevel [Byte0]: 53
2743 18:07:42.150848 [Byte1]: 53
2744 18:07:42.155331
2745 18:07:42.155413 Set Vref, RX VrefLevel [Byte0]: 54
2746 18:07:42.158582 [Byte1]: 54
2747 18:07:42.163462
2748 18:07:42.163544 Set Vref, RX VrefLevel [Byte0]: 55
2749 18:07:42.166914 [Byte1]: 55
2750 18:07:42.171284
2751 18:07:42.171367 Set Vref, RX VrefLevel [Byte0]: 56
2752 18:07:42.174656 [Byte1]: 56
2753 18:07:42.179580
2754 18:07:42.179661 Set Vref, RX VrefLevel [Byte0]: 57
2755 18:07:42.182578 [Byte1]: 57
2756 18:07:42.187134
2757 18:07:42.187217 Set Vref, RX VrefLevel [Byte0]: 58
2758 18:07:42.190529 [Byte1]: 58
2759 18:07:42.195015
2760 18:07:42.195097 Set Vref, RX VrefLevel [Byte0]: 59
2761 18:07:42.198562 [Byte1]: 59
2762 18:07:42.203211
2763 18:07:42.203299 Set Vref, RX VrefLevel [Byte0]: 60
2764 18:07:42.205956 [Byte1]: 60
2765 18:07:42.210826
2766 18:07:42.210910 Set Vref, RX VrefLevel [Byte0]: 61
2767 18:07:42.214326 [Byte1]: 61
2768 18:07:42.218853
2769 18:07:42.218938 Set Vref, RX VrefLevel [Byte0]: 62
2770 18:07:42.221998 [Byte1]: 62
2771 18:07:42.226588
2772 18:07:42.226672 Set Vref, RX VrefLevel [Byte0]: 63
2773 18:07:42.230303 [Byte1]: 63
2774 18:07:42.234332
2775 18:07:42.234420 Set Vref, RX VrefLevel [Byte0]: 64
2776 18:07:42.237408 [Byte1]: 64
2777 18:07:42.242598
2778 18:07:42.242685 Set Vref, RX VrefLevel [Byte0]: 65
2779 18:07:42.245323 [Byte1]: 65
2780 18:07:42.250348
2781 18:07:42.250435 Set Vref, RX VrefLevel [Byte0]: 66
2782 18:07:42.253634 [Byte1]: 66
2783 18:07:42.258289
2784 18:07:42.258375 Set Vref, RX VrefLevel [Byte0]: 67
2785 18:07:42.261687 [Byte1]: 67
2786 18:07:42.265900
2787 18:07:42.265989 Set Vref, RX VrefLevel [Byte0]: 68
2788 18:07:42.269473 [Byte1]: 68
2789 18:07:42.273743
2790 18:07:42.273829 Set Vref, RX VrefLevel [Byte0]: 69
2791 18:07:42.277217 [Byte1]: 69
2792 18:07:42.281501
2793 18:07:42.281585 Set Vref, RX VrefLevel [Byte0]: 70
2794 18:07:42.285105 [Byte1]: 70
2795 18:07:42.289921
2796 18:07:42.290008 Set Vref, RX VrefLevel [Byte0]: 71
2797 18:07:42.293198 [Byte1]: 71
2798 18:07:42.297779
2799 18:07:42.297869 Set Vref, RX VrefLevel [Byte0]: 72
2800 18:07:42.301000 [Byte1]: 72
2801 18:07:42.305146
2802 18:07:42.305231 Final RX Vref Byte 0 = 55 to rank0
2803 18:07:42.308576 Final RX Vref Byte 1 = 43 to rank0
2804 18:07:42.312009 Final RX Vref Byte 0 = 55 to rank1
2805 18:07:42.315458 Final RX Vref Byte 1 = 43 to rank1==
2806 18:07:42.318988 Dram Type= 6, Freq= 0, CH_0, rank 0
2807 18:07:42.325370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2808 18:07:42.325461 ==
2809 18:07:42.325528 DQS Delay:
2810 18:07:42.325589 DQS0 = 0, DQS1 = 0
2811 18:07:42.328761 DQM Delay:
2812 18:07:42.328845 DQM0 = 120, DQM1 = 109
2813 18:07:42.332219 DQ Delay:
2814 18:07:42.335476 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2815 18:07:42.338575 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2816 18:07:42.342542 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
2817 18:07:42.345452 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
2818 18:07:42.345537
2819 18:07:42.345602
2820 18:07:42.352117 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2821 18:07:42.355247 CH0 RK0: MR19=404, MR18=150F
2822 18:07:42.362054 CH0_RK0: MR19=0x404, MR18=0x150F, DQSOSC=401, MR23=63, INC=40, DEC=27
2823 18:07:42.362147
2824 18:07:42.365224 ----->DramcWriteLeveling(PI) begin...
2825 18:07:42.365310 ==
2826 18:07:42.368905 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 18:07:42.372214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 18:07:42.375747 ==
2829 18:07:42.375833 Write leveling (Byte 0): 34 => 34
2830 18:07:42.378586 Write leveling (Byte 1): 29 => 29
2831 18:07:42.382074 DramcWriteLeveling(PI) end<-----
2832 18:07:42.382157
2833 18:07:42.382229 ==
2834 18:07:42.385608 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 18:07:42.391876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 18:07:42.391963 ==
2837 18:07:42.392030 [Gating] SW mode calibration
2838 18:07:42.402325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2839 18:07:42.405488 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2840 18:07:42.408747 0 15 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
2841 18:07:42.415685 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 18:07:42.418449 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 18:07:42.421712 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 18:07:42.428799 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 18:07:42.432147 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 18:07:42.434966 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 18:07:42.441901 0 15 28 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
2848 18:07:42.445443 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2849 18:07:42.448967 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 18:07:42.455342 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 18:07:42.458644 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 18:07:42.461995 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 18:07:42.468735 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 18:07:42.471684 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2855 18:07:42.475265 1 0 28 | B1->B0 | 3434 3736 | 0 1 | (0 0) (0 0)
2856 18:07:42.482306 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 18:07:42.485574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 18:07:42.488579 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 18:07:42.492004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 18:07:42.498946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 18:07:42.502244 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 18:07:42.505672 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 18:07:42.511948 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2864 18:07:42.515760 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 18:07:42.519135 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 18:07:42.525496 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 18:07:42.528788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 18:07:42.532521 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 18:07:42.538659 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 18:07:42.542309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 18:07:42.545537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 18:07:42.552068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 18:07:42.555417 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 18:07:42.558765 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 18:07:42.565146 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 18:07:42.568666 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 18:07:42.572189 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 18:07:42.578454 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 18:07:42.581864 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2880 18:07:42.585123 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2881 18:07:42.588484 Total UI for P1: 0, mck2ui 16
2882 18:07:42.591894 best dqsien dly found for B1: ( 1, 3, 28)
2883 18:07:42.595336 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 18:07:42.598824 Total UI for P1: 0, mck2ui 16
2885 18:07:42.602016 best dqsien dly found for B0: ( 1, 3, 30)
2886 18:07:42.605695 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2887 18:07:42.608627 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2888 18:07:42.612275
2889 18:07:42.615227 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2890 18:07:42.619007 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2891 18:07:42.622231 [Gating] SW calibration Done
2892 18:07:42.622317 ==
2893 18:07:42.625314 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 18:07:42.628884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 18:07:42.628970 ==
2896 18:07:42.629036 RX Vref Scan: 0
2897 18:07:42.629112
2898 18:07:42.632537 RX Vref 0 -> 0, step: 1
2899 18:07:42.632619
2900 18:07:42.636163 RX Delay -40 -> 252, step: 8
2901 18:07:42.638941 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 18:07:42.642511 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2903 18:07:42.649116 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 18:07:42.652643 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2905 18:07:42.655530 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2906 18:07:42.659073 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2907 18:07:42.662220 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 18:07:42.665357 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 18:07:42.672460 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 18:07:42.675324 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2911 18:07:42.678836 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2912 18:07:42.682467 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 18:07:42.685875 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2914 18:07:42.692055 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2915 18:07:42.695504 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2916 18:07:42.699228 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2917 18:07:42.699314 ==
2918 18:07:42.702340 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 18:07:42.705880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 18:07:42.708768 ==
2921 18:07:42.708850 DQS Delay:
2922 18:07:42.708914 DQS0 = 0, DQS1 = 0
2923 18:07:42.712162 DQM Delay:
2924 18:07:42.712243 DQM0 = 122, DQM1 = 112
2925 18:07:42.715595 DQ Delay:
2926 18:07:42.719136 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2927 18:07:42.722530 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2928 18:07:42.725346 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2929 18:07:42.729113 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2930 18:07:42.729199
2931 18:07:42.729277
2932 18:07:42.729336 ==
2933 18:07:42.732473 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 18:07:42.735773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 18:07:42.735873 ==
2936 18:07:42.735957
2937 18:07:42.736017
2938 18:07:42.739308 TX Vref Scan disable
2939 18:07:42.742445 == TX Byte 0 ==
2940 18:07:42.746235 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2941 18:07:42.749118 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2942 18:07:42.752230 == TX Byte 1 ==
2943 18:07:42.755655 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2944 18:07:42.759162 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2945 18:07:42.759253 ==
2946 18:07:42.762256 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 18:07:42.765718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 18:07:42.768931 ==
2949 18:07:42.779850 TX Vref=22, minBit 1, minWin=25, winSum=413
2950 18:07:42.782671 TX Vref=24, minBit 1, minWin=24, winSum=416
2951 18:07:42.786289 TX Vref=26, minBit 1, minWin=25, winSum=419
2952 18:07:42.789821 TX Vref=28, minBit 0, minWin=26, winSum=422
2953 18:07:42.792735 TX Vref=30, minBit 1, minWin=26, winSum=425
2954 18:07:42.796033 TX Vref=32, minBit 5, minWin=25, winSum=424
2955 18:07:42.802708 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
2956 18:07:42.802831
2957 18:07:42.806211 Final TX Range 1 Vref 30
2958 18:07:42.806314
2959 18:07:42.806405 ==
2960 18:07:42.809749 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 18:07:42.813040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 18:07:42.813128 ==
2963 18:07:42.813230
2964 18:07:42.816462
2965 18:07:42.816547 TX Vref Scan disable
2966 18:07:42.819241 == TX Byte 0 ==
2967 18:07:42.822689 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2968 18:07:42.826269 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2969 18:07:42.829792 == TX Byte 1 ==
2970 18:07:42.832527 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2971 18:07:42.836249 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2972 18:07:42.836390
2973 18:07:42.839636 [DATLAT]
2974 18:07:42.839737 Freq=1200, CH0 RK1
2975 18:07:42.839833
2976 18:07:42.843185 DATLAT Default: 0xd
2977 18:07:42.843258 0, 0xFFFF, sum = 0
2978 18:07:42.846762 1, 0xFFFF, sum = 0
2979 18:07:42.846838 2, 0xFFFF, sum = 0
2980 18:07:42.849897 3, 0xFFFF, sum = 0
2981 18:07:42.849972 4, 0xFFFF, sum = 0
2982 18:07:42.852639 5, 0xFFFF, sum = 0
2983 18:07:42.852730 6, 0xFFFF, sum = 0
2984 18:07:42.856043 7, 0xFFFF, sum = 0
2985 18:07:42.856141 8, 0xFFFF, sum = 0
2986 18:07:42.859691 9, 0xFFFF, sum = 0
2987 18:07:42.863255 10, 0xFFFF, sum = 0
2988 18:07:42.863340 11, 0xFFFF, sum = 0
2989 18:07:42.866125 12, 0x0, sum = 1
2990 18:07:42.866225 13, 0x0, sum = 2
2991 18:07:42.866317 14, 0x0, sum = 3
2992 18:07:42.869740 15, 0x0, sum = 4
2993 18:07:42.869839 best_step = 13
2994 18:07:42.869934
2995 18:07:42.870023 ==
2996 18:07:42.873230 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 18:07:42.879674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 18:07:42.879785 ==
2999 18:07:42.879876 RX Vref Scan: 0
3000 18:07:42.879964
3001 18:07:42.882847 RX Vref 0 -> 0, step: 1
3002 18:07:42.882941
3003 18:07:42.886492 RX Delay -13 -> 252, step: 4
3004 18:07:42.889907 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3005 18:07:42.893444 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3006 18:07:42.899592 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 18:07:42.902976 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3008 18:07:42.906099 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3009 18:07:42.910119 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3010 18:07:42.912808 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3011 18:07:42.919856 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3012 18:07:42.922924 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3013 18:07:42.926343 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3014 18:07:42.929509 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3015 18:07:42.933083 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3016 18:07:42.939490 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 18:07:42.942953 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3018 18:07:42.946607 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3019 18:07:42.949383 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3020 18:07:42.949482 ==
3021 18:07:42.952816 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 18:07:42.959489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 18:07:42.959575 ==
3024 18:07:42.959641 DQS Delay:
3025 18:07:42.959702 DQS0 = 0, DQS1 = 0
3026 18:07:42.963542 DQM Delay:
3027 18:07:42.963627 DQM0 = 121, DQM1 = 109
3028 18:07:42.966351 DQ Delay:
3029 18:07:42.969770 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3030 18:07:42.973195 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3031 18:07:42.976679 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3032 18:07:42.980115 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3033 18:07:42.980230
3034 18:07:42.980322
3035 18:07:42.986560 [DQSOSCAuto] RK1, (LSB)MR18= 0xcec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3036 18:07:42.990032 CH0 RK1: MR19=403, MR18=CEC
3037 18:07:42.996311 CH0_RK1: MR19=0x403, MR18=0xCEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3038 18:07:42.999875 [RxdqsGatingPostProcess] freq 1200
3039 18:07:43.006895 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 18:07:43.006981 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 18:07:43.009542 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 18:07:43.012971 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 18:07:43.016713 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 18:07:43.019871 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 18:07:43.022879 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 18:07:43.026835 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 18:07:43.030098 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 18:07:43.032971 Pre-setting of DQS Precalculation
3049 18:07:43.036223 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 18:07:43.039875 ==
3051 18:07:43.043358 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 18:07:43.046396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 18:07:43.046481 ==
3054 18:07:43.049816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 18:07:43.056444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3056 18:07:43.065888 [CA 0] Center 37 (7~68) winsize 62
3057 18:07:43.069243 [CA 1] Center 37 (7~68) winsize 62
3058 18:07:43.071953 [CA 2] Center 35 (5~65) winsize 61
3059 18:07:43.075857 [CA 3] Center 34 (4~64) winsize 61
3060 18:07:43.078806 [CA 4] Center 34 (4~64) winsize 61
3061 18:07:43.082280 [CA 5] Center 33 (3~63) winsize 61
3062 18:07:43.082364
3063 18:07:43.085835 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3064 18:07:43.085942
3065 18:07:43.088763 [CATrainingPosCal] consider 1 rank data
3066 18:07:43.092290 u2DelayCellTimex100 = 270/100 ps
3067 18:07:43.095709 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3068 18:07:43.098590 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 18:07:43.105585 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 18:07:43.108552 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3071 18:07:43.112035 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3072 18:07:43.115685 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3073 18:07:43.115767
3074 18:07:43.119103 CA PerBit enable=1, Macro0, CA PI delay=33
3075 18:07:43.119245
3076 18:07:43.122206 [CBTSetCACLKResult] CA Dly = 33
3077 18:07:43.122278 CS Dly: 8 (0~39)
3078 18:07:43.125731 ==
3079 18:07:43.125840 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 18:07:43.132245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 18:07:43.132346 ==
3082 18:07:43.135078 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 18:07:43.141720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3084 18:07:43.151497 [CA 0] Center 38 (8~68) winsize 61
3085 18:07:43.154895 [CA 1] Center 37 (7~68) winsize 62
3086 18:07:43.157737 [CA 2] Center 35 (5~65) winsize 61
3087 18:07:43.161297 [CA 3] Center 35 (5~65) winsize 61
3088 18:07:43.164430 [CA 4] Center 34 (4~65) winsize 62
3089 18:07:43.167614 [CA 5] Center 34 (4~64) winsize 61
3090 18:07:43.167717
3091 18:07:43.170960 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3092 18:07:43.171071
3093 18:07:43.174427 [CATrainingPosCal] consider 2 rank data
3094 18:07:43.177704 u2DelayCellTimex100 = 270/100 ps
3095 18:07:43.181121 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3096 18:07:43.184310 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3097 18:07:43.191583 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3098 18:07:43.194499 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3099 18:07:43.198122 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 18:07:43.200993 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3101 18:07:43.201087
3102 18:07:43.204578 CA PerBit enable=1, Macro0, CA PI delay=33
3103 18:07:43.204669
3104 18:07:43.208129 [CBTSetCACLKResult] CA Dly = 33
3105 18:07:43.208218 CS Dly: 9 (0~41)
3106 18:07:43.208324
3107 18:07:43.211129 ----->DramcWriteLeveling(PI) begin...
3108 18:07:43.214840 ==
3109 18:07:43.214930 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 18:07:43.221231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 18:07:43.221332 ==
3112 18:07:43.224764 Write leveling (Byte 0): 26 => 26
3113 18:07:43.227587 Write leveling (Byte 1): 27 => 27
3114 18:07:43.231282 DramcWriteLeveling(PI) end<-----
3115 18:07:43.231379
3116 18:07:43.231469 ==
3117 18:07:43.234727 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 18:07:43.238283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 18:07:43.238374 ==
3120 18:07:43.241834 [Gating] SW mode calibration
3121 18:07:43.247897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 18:07:43.251295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 18:07:43.258056 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 18:07:43.261542 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 18:07:43.264937 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 18:07:43.271295 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 18:07:43.274849 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 18:07:43.278372 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 18:07:43.284881 0 15 24 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
3130 18:07:43.288528 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3131 18:07:43.291451 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 18:07:43.298242 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 18:07:43.301364 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 18:07:43.304638 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 18:07:43.308005 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 18:07:43.315124 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 18:07:43.318246 1 0 24 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
3138 18:07:43.321579 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 18:07:43.328301 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 18:07:43.331288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 18:07:43.334832 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 18:07:43.341389 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 18:07:43.345035 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 18:07:43.348575 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 18:07:43.354744 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 18:07:43.358399 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 18:07:43.361704 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 18:07:43.368283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 18:07:43.371695 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 18:07:43.375044 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 18:07:43.381657 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 18:07:43.385278 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 18:07:43.388621 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 18:07:43.391571 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 18:07:43.398169 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 18:07:43.401645 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 18:07:43.405186 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 18:07:43.411654 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 18:07:43.415175 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 18:07:43.418094 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 18:07:43.425404 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3162 18:07:43.428154 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 18:07:43.431770 Total UI for P1: 0, mck2ui 16
3164 18:07:43.435092 best dqsien dly found for B0: ( 1, 3, 24)
3165 18:07:43.438795 Total UI for P1: 0, mck2ui 16
3166 18:07:43.441745 best dqsien dly found for B1: ( 1, 3, 24)
3167 18:07:43.445003 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3168 18:07:43.448086 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3169 18:07:43.448192
3170 18:07:43.451946 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3171 18:07:43.454734 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3172 18:07:43.458865 [Gating] SW calibration Done
3173 18:07:43.458951 ==
3174 18:07:43.461928 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 18:07:43.465269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 18:07:43.468902 ==
3177 18:07:43.468981 RX Vref Scan: 0
3178 18:07:43.469045
3179 18:07:43.471876 RX Vref 0 -> 0, step: 1
3180 18:07:43.471970
3181 18:07:43.472033 RX Delay -40 -> 252, step: 8
3182 18:07:43.478808 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3183 18:07:43.482211 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3184 18:07:43.485112 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3185 18:07:43.488505 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3186 18:07:43.492215 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3187 18:07:43.498543 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3188 18:07:43.501497 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3189 18:07:43.505273 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3190 18:07:43.508771 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3191 18:07:43.512216 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3192 18:07:43.518287 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3193 18:07:43.521689 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3194 18:07:43.525410 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3195 18:07:43.528660 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3196 18:07:43.532225 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3197 18:07:43.538865 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3198 18:07:43.538950 ==
3199 18:07:43.541680 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 18:07:43.545228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 18:07:43.545304 ==
3202 18:07:43.545367 DQS Delay:
3203 18:07:43.548731 DQS0 = 0, DQS1 = 0
3204 18:07:43.548808 DQM Delay:
3205 18:07:43.552336 DQM0 = 120, DQM1 = 116
3206 18:07:43.552416 DQ Delay:
3207 18:07:43.555271 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3208 18:07:43.558909 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3209 18:07:43.562023 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3210 18:07:43.565194 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3211 18:07:43.565277
3212 18:07:43.565341
3213 18:07:43.568363 ==
3214 18:07:43.572011 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 18:07:43.575800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 18:07:43.575915 ==
3217 18:07:43.576012
3218 18:07:43.576102
3219 18:07:43.578536 TX Vref Scan disable
3220 18:07:43.578633 == TX Byte 0 ==
3221 18:07:43.581873 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3222 18:07:43.588756 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3223 18:07:43.588847 == TX Byte 1 ==
3224 18:07:43.592288 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 18:07:43.598561 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 18:07:43.598682 ==
3227 18:07:43.602236 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 18:07:43.604901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 18:07:43.605026 ==
3230 18:07:43.617366 TX Vref=22, minBit 9, minWin=25, winSum=416
3231 18:07:43.620084 TX Vref=24, minBit 9, minWin=24, winSum=417
3232 18:07:43.623750 TX Vref=26, minBit 9, minWin=25, winSum=421
3233 18:07:43.626849 TX Vref=28, minBit 10, minWin=25, winSum=425
3234 18:07:43.630110 TX Vref=30, minBit 2, minWin=26, winSum=428
3235 18:07:43.633614 TX Vref=32, minBit 9, minWin=26, winSum=429
3236 18:07:43.640466 [TxChooseVref] Worse bit 9, Min win 26, Win sum 429, Final Vref 32
3237 18:07:43.640560
3238 18:07:43.644008 Final TX Range 1 Vref 32
3239 18:07:43.644123
3240 18:07:43.644218 ==
3241 18:07:43.646791 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 18:07:43.650253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 18:07:43.650341 ==
3244 18:07:43.650407
3245 18:07:43.650468
3246 18:07:43.653730 TX Vref Scan disable
3247 18:07:43.657375 == TX Byte 0 ==
3248 18:07:43.660109 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3249 18:07:43.663729 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3250 18:07:43.667303 == TX Byte 1 ==
3251 18:07:43.670108 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 18:07:43.673799 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 18:07:43.673927
3254 18:07:43.677022 [DATLAT]
3255 18:07:43.677110 Freq=1200, CH1 RK0
3256 18:07:43.677177
3257 18:07:43.680174 DATLAT Default: 0xd
3258 18:07:43.680290 0, 0xFFFF, sum = 0
3259 18:07:43.683798 1, 0xFFFF, sum = 0
3260 18:07:43.683907 2, 0xFFFF, sum = 0
3261 18:07:43.687287 3, 0xFFFF, sum = 0
3262 18:07:43.687403 4, 0xFFFF, sum = 0
3263 18:07:43.690609 5, 0xFFFF, sum = 0
3264 18:07:43.690691 6, 0xFFFF, sum = 0
3265 18:07:43.693607 7, 0xFFFF, sum = 0
3266 18:07:43.693725 8, 0xFFFF, sum = 0
3267 18:07:43.697154 9, 0xFFFF, sum = 0
3268 18:07:43.700502 10, 0xFFFF, sum = 0
3269 18:07:43.700627 11, 0xFFFF, sum = 0
3270 18:07:43.703561 12, 0x0, sum = 1
3271 18:07:43.703670 13, 0x0, sum = 2
3272 18:07:43.703779 14, 0x0, sum = 3
3273 18:07:43.707528 15, 0x0, sum = 4
3274 18:07:43.707641 best_step = 13
3275 18:07:43.707733
3276 18:07:43.707799 ==
3277 18:07:43.710209 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 18:07:43.717622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 18:07:43.717745 ==
3280 18:07:43.717844 RX Vref Scan: 1
3281 18:07:43.717936
3282 18:07:43.720327 Set Vref Range= 32 -> 127
3283 18:07:43.720413
3284 18:07:43.723882 RX Vref 32 -> 127, step: 1
3285 18:07:43.723966
3286 18:07:43.727671 RX Delay -5 -> 252, step: 4
3287 18:07:43.727764
3288 18:07:43.730484 Set Vref, RX VrefLevel [Byte0]: 32
3289 18:07:43.733470 [Byte1]: 32
3290 18:07:43.733562
3291 18:07:43.737062 Set Vref, RX VrefLevel [Byte0]: 33
3292 18:07:43.740629 [Byte1]: 33
3293 18:07:43.740747
3294 18:07:43.744215 Set Vref, RX VrefLevel [Byte0]: 34
3295 18:07:43.746721 [Byte1]: 34
3296 18:07:43.750763
3297 18:07:43.750876 Set Vref, RX VrefLevel [Byte0]: 35
3298 18:07:43.754260 [Byte1]: 35
3299 18:07:43.758645
3300 18:07:43.758754 Set Vref, RX VrefLevel [Byte0]: 36
3301 18:07:43.762088 [Byte1]: 36
3302 18:07:43.766751
3303 18:07:43.766862 Set Vref, RX VrefLevel [Byte0]: 37
3304 18:07:43.769761 [Byte1]: 37
3305 18:07:43.774881
3306 18:07:43.774967 Set Vref, RX VrefLevel [Byte0]: 38
3307 18:07:43.777631 [Byte1]: 38
3308 18:07:43.781974
3309 18:07:43.782078 Set Vref, RX VrefLevel [Byte0]: 39
3310 18:07:43.785657 [Byte1]: 39
3311 18:07:43.790480
3312 18:07:43.790567 Set Vref, RX VrefLevel [Byte0]: 40
3313 18:07:43.793315 [Byte1]: 40
3314 18:07:43.798231
3315 18:07:43.798339 Set Vref, RX VrefLevel [Byte0]: 41
3316 18:07:43.801034 [Byte1]: 41
3317 18:07:43.806121
3318 18:07:43.806235 Set Vref, RX VrefLevel [Byte0]: 42
3319 18:07:43.808807 [Byte1]: 42
3320 18:07:43.813529
3321 18:07:43.813656 Set Vref, RX VrefLevel [Byte0]: 43
3322 18:07:43.817273 [Byte1]: 43
3323 18:07:43.821486
3324 18:07:43.821597 Set Vref, RX VrefLevel [Byte0]: 44
3325 18:07:43.825104 [Byte1]: 44
3326 18:07:43.829299
3327 18:07:43.829405 Set Vref, RX VrefLevel [Byte0]: 45
3328 18:07:43.832530 [Byte1]: 45
3329 18:07:43.836746
3330 18:07:43.836824 Set Vref, RX VrefLevel [Byte0]: 46
3331 18:07:43.840251 [Byte1]: 46
3332 18:07:43.844651
3333 18:07:43.844723 Set Vref, RX VrefLevel [Byte0]: 47
3334 18:07:43.848200 [Byte1]: 47
3335 18:07:43.852517
3336 18:07:43.852614 Set Vref, RX VrefLevel [Byte0]: 48
3337 18:07:43.855931 [Byte1]: 48
3338 18:07:43.860932
3339 18:07:43.861002 Set Vref, RX VrefLevel [Byte0]: 49
3340 18:07:43.864113 [Byte1]: 49
3341 18:07:43.868610
3342 18:07:43.868688 Set Vref, RX VrefLevel [Byte0]: 50
3343 18:07:43.871876 [Byte1]: 50
3344 18:07:43.876284
3345 18:07:43.876389 Set Vref, RX VrefLevel [Byte0]: 51
3346 18:07:43.879443 [Byte1]: 51
3347 18:07:43.884182
3348 18:07:43.884284 Set Vref, RX VrefLevel [Byte0]: 52
3349 18:07:43.888002 [Byte1]: 52
3350 18:07:43.891875
3351 18:07:43.891975 Set Vref, RX VrefLevel [Byte0]: 53
3352 18:07:43.895463 [Byte1]: 53
3353 18:07:43.899664
3354 18:07:43.899767 Set Vref, RX VrefLevel [Byte0]: 54
3355 18:07:43.903279 [Byte1]: 54
3356 18:07:43.907770
3357 18:07:43.907874 Set Vref, RX VrefLevel [Byte0]: 55
3358 18:07:43.911008 [Byte1]: 55
3359 18:07:43.915877
3360 18:07:43.915962 Set Vref, RX VrefLevel [Byte0]: 56
3361 18:07:43.919020 [Byte1]: 56
3362 18:07:43.923156
3363 18:07:43.923259 Set Vref, RX VrefLevel [Byte0]: 57
3364 18:07:43.926843 [Byte1]: 57
3365 18:07:43.931104
3366 18:07:43.931217 Set Vref, RX VrefLevel [Byte0]: 58
3367 18:07:43.934655 [Byte1]: 58
3368 18:07:43.939421
3369 18:07:43.939517 Set Vref, RX VrefLevel [Byte0]: 59
3370 18:07:43.942312 [Byte1]: 59
3371 18:07:43.946854
3372 18:07:43.946958 Set Vref, RX VrefLevel [Byte0]: 60
3373 18:07:43.950435 [Byte1]: 60
3374 18:07:43.955199
3375 18:07:43.955301 Set Vref, RX VrefLevel [Byte0]: 61
3376 18:07:43.958576 [Byte1]: 61
3377 18:07:43.962684
3378 18:07:43.962796 Set Vref, RX VrefLevel [Byte0]: 62
3379 18:07:43.966352 [Byte1]: 62
3380 18:07:43.970520
3381 18:07:43.970621 Set Vref, RX VrefLevel [Byte0]: 63
3382 18:07:43.974001 [Byte1]: 63
3383 18:07:43.978487
3384 18:07:43.978591 Set Vref, RX VrefLevel [Byte0]: 64
3385 18:07:43.982175 [Byte1]: 64
3386 18:07:43.986183
3387 18:07:43.986287 Set Vref, RX VrefLevel [Byte0]: 65
3388 18:07:43.989464 [Byte1]: 65
3389 18:07:43.994256
3390 18:07:43.994360 Set Vref, RX VrefLevel [Byte0]: 66
3391 18:07:43.997695 [Byte1]: 66
3392 18:07:44.001908
3393 18:07:44.002016 Set Vref, RX VrefLevel [Byte0]: 67
3394 18:07:44.005401 [Byte1]: 67
3395 18:07:44.009741
3396 18:07:44.009851 Final RX Vref Byte 0 = 53 to rank0
3397 18:07:44.013441 Final RX Vref Byte 1 = 47 to rank0
3398 18:07:44.016851 Final RX Vref Byte 0 = 53 to rank1
3399 18:07:44.020180 Final RX Vref Byte 1 = 47 to rank1==
3400 18:07:44.023575 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 18:07:44.030150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 18:07:44.030238 ==
3403 18:07:44.030341 DQS Delay:
3404 18:07:44.030442 DQS0 = 0, DQS1 = 0
3405 18:07:44.033561 DQM Delay:
3406 18:07:44.033649 DQM0 = 119, DQM1 = 116
3407 18:07:44.036513 DQ Delay:
3408 18:07:44.039811 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3409 18:07:44.043326 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3410 18:07:44.046410 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3411 18:07:44.049815 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3412 18:07:44.049893
3413 18:07:44.049961
3414 18:07:44.056673 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3415 18:07:44.060064 CH1 RK0: MR19=404, MR18=215
3416 18:07:44.066464 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3417 18:07:44.066588
3418 18:07:44.069667 ----->DramcWriteLeveling(PI) begin...
3419 18:07:44.069783 ==
3420 18:07:44.073126 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 18:07:44.076769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 18:07:44.076879 ==
3423 18:07:44.079722 Write leveling (Byte 0): 27 => 27
3424 18:07:44.083730 Write leveling (Byte 1): 28 => 28
3425 18:07:44.086829 DramcWriteLeveling(PI) end<-----
3426 18:07:44.086934
3427 18:07:44.087030 ==
3428 18:07:44.089665 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 18:07:44.093236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 18:07:44.096435 ==
3431 18:07:44.096559 [Gating] SW mode calibration
3432 18:07:44.106495 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 18:07:44.109874 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 18:07:44.113368 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 18:07:44.120102 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 18:07:44.123348 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 18:07:44.126696 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 18:07:44.133272 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 18:07:44.136731 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3440 18:07:44.140223 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (0 1) (1 0)
3441 18:07:44.146663 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3442 18:07:44.150340 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 18:07:44.153117 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 18:07:44.160248 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 18:07:44.163736 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 18:07:44.167168 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 18:07:44.169946 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3448 18:07:44.176682 1 0 24 | B1->B0 | 4242 3232 | 0 0 | (1 1) (0 0)
3449 18:07:44.180306 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 18:07:44.183593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 18:07:44.190518 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 18:07:44.193258 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 18:07:44.196510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 18:07:44.203691 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 18:07:44.206839 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3456 18:07:44.210406 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3457 18:07:44.216697 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3458 18:07:44.220109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 18:07:44.223077 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 18:07:44.229940 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 18:07:44.233305 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 18:07:44.236328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 18:07:44.243364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 18:07:44.246803 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 18:07:44.250204 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 18:07:44.256784 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 18:07:44.259674 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 18:07:44.263213 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 18:07:44.269824 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 18:07:44.273474 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 18:07:44.276214 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 18:07:44.282781 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3473 18:07:44.286198 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3474 18:07:44.289525 Total UI for P1: 0, mck2ui 16
3475 18:07:44.293014 best dqsien dly found for B1: ( 1, 3, 24)
3476 18:07:44.296367 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 18:07:44.300110 Total UI for P1: 0, mck2ui 16
3478 18:07:44.302796 best dqsien dly found for B0: ( 1, 3, 28)
3479 18:07:44.306204 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3480 18:07:44.309684 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3481 18:07:44.309766
3482 18:07:44.312849 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3483 18:07:44.319886 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3484 18:07:44.319971 [Gating] SW calibration Done
3485 18:07:44.320045 ==
3486 18:07:44.323223 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 18:07:44.329793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 18:07:44.329890 ==
3489 18:07:44.329959 RX Vref Scan: 0
3490 18:07:44.330022
3491 18:07:44.332639 RX Vref 0 -> 0, step: 1
3492 18:07:44.332721
3493 18:07:44.336067 RX Delay -40 -> 252, step: 8
3494 18:07:44.340121 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3495 18:07:44.343052 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3496 18:07:44.346427 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3497 18:07:44.352644 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3498 18:07:44.356046 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3499 18:07:44.359410 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3500 18:07:44.363211 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3501 18:07:44.366127 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3502 18:07:44.372461 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3503 18:07:44.376005 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3504 18:07:44.379692 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3505 18:07:44.383157 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3506 18:07:44.386042 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3507 18:07:44.392617 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3508 18:07:44.396155 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3509 18:07:44.398967 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3510 18:07:44.399052 ==
3511 18:07:44.402361 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 18:07:44.405886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 18:07:44.405971 ==
3514 18:07:44.409195 DQS Delay:
3515 18:07:44.409279 DQS0 = 0, DQS1 = 0
3516 18:07:44.412523 DQM Delay:
3517 18:07:44.412607 DQM0 = 121, DQM1 = 118
3518 18:07:44.415912 DQ Delay:
3519 18:07:44.419213 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3520 18:07:44.422553 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3521 18:07:44.425815 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3522 18:07:44.429333 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3523 18:07:44.429419
3524 18:07:44.429486
3525 18:07:44.429546 ==
3526 18:07:44.432644 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 18:07:44.435806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 18:07:44.435891 ==
3529 18:07:44.435958
3530 18:07:44.436019
3531 18:07:44.439126 TX Vref Scan disable
3532 18:07:44.442549 == TX Byte 0 ==
3533 18:07:44.445854 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3534 18:07:44.449085 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3535 18:07:44.452799 == TX Byte 1 ==
3536 18:07:44.455535 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 18:07:44.459143 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 18:07:44.459248 ==
3539 18:07:44.463289 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 18:07:44.466109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 18:07:44.469068 ==
3542 18:07:44.479209 TX Vref=22, minBit 0, minWin=26, winSum=421
3543 18:07:44.482183 TX Vref=24, minBit 1, minWin=26, winSum=426
3544 18:07:44.485698 TX Vref=26, minBit 2, minWin=26, winSum=428
3545 18:07:44.488896 TX Vref=28, minBit 6, minWin=26, winSum=430
3546 18:07:44.492507 TX Vref=30, minBit 9, minWin=26, winSum=434
3547 18:07:44.498895 TX Vref=32, minBit 1, minWin=26, winSum=432
3548 18:07:44.502412 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3549 18:07:44.502560
3550 18:07:44.505242 Final TX Range 1 Vref 30
3551 18:07:44.505354
3552 18:07:44.505447 ==
3553 18:07:44.508828 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 18:07:44.512072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 18:07:44.515035 ==
3556 18:07:44.515144
3557 18:07:44.515238
3558 18:07:44.515325 TX Vref Scan disable
3559 18:07:44.518451 == TX Byte 0 ==
3560 18:07:44.522096 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 18:07:44.525256 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 18:07:44.528515 == TX Byte 1 ==
3563 18:07:44.531945 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 18:07:44.538472 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 18:07:44.538571
3566 18:07:44.538639 [DATLAT]
3567 18:07:44.538700 Freq=1200, CH1 RK1
3568 18:07:44.538760
3569 18:07:44.541771 DATLAT Default: 0xd
3570 18:07:44.541855 0, 0xFFFF, sum = 0
3571 18:07:44.545070 1, 0xFFFF, sum = 0
3572 18:07:44.548369 2, 0xFFFF, sum = 0
3573 18:07:44.548455 3, 0xFFFF, sum = 0
3574 18:07:44.551731 4, 0xFFFF, sum = 0
3575 18:07:44.551815 5, 0xFFFF, sum = 0
3576 18:07:44.555194 6, 0xFFFF, sum = 0
3577 18:07:44.555280 7, 0xFFFF, sum = 0
3578 18:07:44.558624 8, 0xFFFF, sum = 0
3579 18:07:44.558708 9, 0xFFFF, sum = 0
3580 18:07:44.562123 10, 0xFFFF, sum = 0
3581 18:07:44.562209 11, 0xFFFF, sum = 0
3582 18:07:44.565072 12, 0x0, sum = 1
3583 18:07:44.565157 13, 0x0, sum = 2
3584 18:07:44.568674 14, 0x0, sum = 3
3585 18:07:44.568760 15, 0x0, sum = 4
3586 18:07:44.571916 best_step = 13
3587 18:07:44.572000
3588 18:07:44.572066 ==
3589 18:07:44.575398 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 18:07:44.578304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 18:07:44.578390 ==
3592 18:07:44.578457 RX Vref Scan: 0
3593 18:07:44.578518
3594 18:07:44.581894 RX Vref 0 -> 0, step: 1
3595 18:07:44.581987
3596 18:07:44.585479 RX Delay -5 -> 252, step: 4
3597 18:07:44.588248 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3598 18:07:44.595414 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3599 18:07:44.598129 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3600 18:07:44.601603 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3601 18:07:44.605299 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3602 18:07:44.608438 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3603 18:07:44.614712 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3604 18:07:44.618155 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3605 18:07:44.621813 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3606 18:07:44.624493 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3607 18:07:44.628145 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3608 18:07:44.634544 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3609 18:07:44.637869 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3610 18:07:44.641816 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3611 18:07:44.644795 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3612 18:07:44.648027 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3613 18:07:44.651375 ==
3614 18:07:44.654473 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 18:07:44.657958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 18:07:44.658077 ==
3617 18:07:44.658146 DQS Delay:
3618 18:07:44.661612 DQS0 = 0, DQS1 = 0
3619 18:07:44.661704 DQM Delay:
3620 18:07:44.664291 DQM0 = 120, DQM1 = 116
3621 18:07:44.664428 DQ Delay:
3622 18:07:44.667834 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3623 18:07:44.671075 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3624 18:07:44.674492 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3625 18:07:44.677660 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3626 18:07:44.677764
3627 18:07:44.677833
3628 18:07:44.687955 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3629 18:07:44.691018 CH1 RK1: MR19=403, MR18=12EE
3630 18:07:44.694602 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3631 18:07:44.697988 [RxdqsGatingPostProcess] freq 1200
3632 18:07:44.704234 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 18:07:44.707895 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 18:07:44.711046 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 18:07:44.714313 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 18:07:44.718036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 18:07:44.721052 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 18:07:44.724567 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 18:07:44.727323 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 18:07:44.730998 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 18:07:44.734167 Pre-setting of DQS Precalculation
3642 18:07:44.737814 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 18:07:44.744161 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 18:07:44.751117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 18:07:44.753859
3646 18:07:44.754019
3647 18:07:44.754121 [Calibration Summary] 2400 Mbps
3648 18:07:44.757358 CH 0, Rank 0
3649 18:07:44.757533 SW Impedance : PASS
3650 18:07:44.760423 DUTY Scan : NO K
3651 18:07:44.763594 ZQ Calibration : PASS
3652 18:07:44.763734 Jitter Meter : NO K
3653 18:07:44.767367 CBT Training : PASS
3654 18:07:44.770476 Write leveling : PASS
3655 18:07:44.770644 RX DQS gating : PASS
3656 18:07:44.773789 RX DQ/DQS(RDDQC) : PASS
3657 18:07:44.777043 TX DQ/DQS : PASS
3658 18:07:44.777198 RX DATLAT : PASS
3659 18:07:44.780553 RX DQ/DQS(Engine): PASS
3660 18:07:44.783545 TX OE : NO K
3661 18:07:44.783698 All Pass.
3662 18:07:44.783806
3663 18:07:44.783900 CH 0, Rank 1
3664 18:07:44.787517 SW Impedance : PASS
3665 18:07:44.790723 DUTY Scan : NO K
3666 18:07:44.790857 ZQ Calibration : PASS
3667 18:07:44.793556 Jitter Meter : NO K
3668 18:07:44.796886 CBT Training : PASS
3669 18:07:44.796987 Write leveling : PASS
3670 18:07:44.800125 RX DQS gating : PASS
3671 18:07:44.803517 RX DQ/DQS(RDDQC) : PASS
3672 18:07:44.803617 TX DQ/DQS : PASS
3673 18:07:44.807386 RX DATLAT : PASS
3674 18:07:44.807496 RX DQ/DQS(Engine): PASS
3675 18:07:44.810308 TX OE : NO K
3676 18:07:44.810390 All Pass.
3677 18:07:44.810456
3678 18:07:44.813749 CH 1, Rank 0
3679 18:07:44.813837 SW Impedance : PASS
3680 18:07:44.816854 DUTY Scan : NO K
3681 18:07:44.820304 ZQ Calibration : PASS
3682 18:07:44.820408 Jitter Meter : NO K
3683 18:07:44.823309 CBT Training : PASS
3684 18:07:44.826861 Write leveling : PASS
3685 18:07:44.826978 RX DQS gating : PASS
3686 18:07:44.830503 RX DQ/DQS(RDDQC) : PASS
3687 18:07:44.833518 TX DQ/DQS : PASS
3688 18:07:44.833603 RX DATLAT : PASS
3689 18:07:44.836808 RX DQ/DQS(Engine): PASS
3690 18:07:44.840667 TX OE : NO K
3691 18:07:44.840825 All Pass.
3692 18:07:44.840933
3693 18:07:44.841028 CH 1, Rank 1
3694 18:07:44.843925 SW Impedance : PASS
3695 18:07:44.846727 DUTY Scan : NO K
3696 18:07:44.846886 ZQ Calibration : PASS
3697 18:07:44.850244 Jitter Meter : NO K
3698 18:07:44.853784 CBT Training : PASS
3699 18:07:44.853874 Write leveling : PASS
3700 18:07:44.857060 RX DQS gating : PASS
3701 18:07:44.857150 RX DQ/DQS(RDDQC) : PASS
3702 18:07:44.860385 TX DQ/DQS : PASS
3703 18:07:44.863925 RX DATLAT : PASS
3704 18:07:44.864037 RX DQ/DQS(Engine): PASS
3705 18:07:44.867077 TX OE : NO K
3706 18:07:44.867229 All Pass.
3707 18:07:44.867349
3708 18:07:44.869900 DramC Write-DBI off
3709 18:07:44.873457 PER_BANK_REFRESH: Hybrid Mode
3710 18:07:44.873613 TX_TRACKING: ON
3711 18:07:44.883779 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 18:07:44.886640 [FAST_K] Save calibration result to emmc
3713 18:07:44.890288 dramc_set_vcore_voltage set vcore to 650000
3714 18:07:44.893125 Read voltage for 600, 5
3715 18:07:44.893268 Vio18 = 0
3716 18:07:44.893367 Vcore = 650000
3717 18:07:44.897132 Vdram = 0
3718 18:07:44.897265 Vddq = 0
3719 18:07:44.897338 Vmddr = 0
3720 18:07:44.903488 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 18:07:44.906736 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 18:07:44.910062 MEM_TYPE=3, freq_sel=19
3723 18:07:44.913874 sv_algorithm_assistance_LP4_1600
3724 18:07:44.916935 ============ PULL DRAM RESETB DOWN ============
3725 18:07:44.923616 ========== PULL DRAM RESETB DOWN end =========
3726 18:07:44.926821 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 18:07:44.930158 ===================================
3728 18:07:44.933056 LPDDR4 DRAM CONFIGURATION
3729 18:07:44.936615 ===================================
3730 18:07:44.936701 EX_ROW_EN[0] = 0x0
3731 18:07:44.939704 EX_ROW_EN[1] = 0x0
3732 18:07:44.939788 LP4Y_EN = 0x0
3733 18:07:44.943074 WORK_FSP = 0x0
3734 18:07:44.943151 WL = 0x2
3735 18:07:44.946662 RL = 0x2
3736 18:07:44.946739 BL = 0x2
3737 18:07:44.949580 RPST = 0x0
3738 18:07:44.949652 RD_PRE = 0x0
3739 18:07:44.953257 WR_PRE = 0x1
3740 18:07:44.953327 WR_PST = 0x0
3741 18:07:44.956809 DBI_WR = 0x0
3742 18:07:44.959508 DBI_RD = 0x0
3743 18:07:44.959579 OTF = 0x1
3744 18:07:44.963072 ===================================
3745 18:07:44.966291 ===================================
3746 18:07:44.966374 ANA top config
3747 18:07:44.969967 ===================================
3748 18:07:44.973228 DLL_ASYNC_EN = 0
3749 18:07:44.976448 ALL_SLAVE_EN = 1
3750 18:07:44.980049 NEW_RANK_MODE = 1
3751 18:07:44.982947 DLL_IDLE_MODE = 1
3752 18:07:44.983036 LP45_APHY_COMB_EN = 1
3753 18:07:44.986253 TX_ODT_DIS = 1
3754 18:07:44.989724 NEW_8X_MODE = 1
3755 18:07:45.011913 ===================================
3756 18:07:45.012081 ===================================
3757 18:07:45.012188 data_rate = 1200
3758 18:07:45.012290 CKR = 1
3759 18:07:45.012392 DQ_P2S_RATIO = 8
3760 18:07:45.012494 ===================================
3761 18:07:45.012592 CA_P2S_RATIO = 8
3762 18:07:45.012888 DQ_CA_OPEN = 0
3763 18:07:45.016515 DQ_SEMI_OPEN = 0
3764 18:07:45.019791 CA_SEMI_OPEN = 0
3765 18:07:45.022457 CA_FULL_RATE = 0
3766 18:07:45.022538 DQ_CKDIV4_EN = 1
3767 18:07:45.026110 CA_CKDIV4_EN = 1
3768 18:07:45.029405 CA_PREDIV_EN = 0
3769 18:07:45.032790 PH8_DLY = 0
3770 18:07:45.035898 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 18:07:45.035979 DQ_AAMCK_DIV = 4
3772 18:07:45.039153 CA_AAMCK_DIV = 4
3773 18:07:45.042483 CA_ADMCK_DIV = 4
3774 18:07:45.046015 DQ_TRACK_CA_EN = 0
3775 18:07:45.049737 CA_PICK = 600
3776 18:07:45.053262 CA_MCKIO = 600
3777 18:07:45.056049 MCKIO_SEMI = 0
3778 18:07:45.056123 PLL_FREQ = 2288
3779 18:07:45.059577 DQ_UI_PI_RATIO = 32
3780 18:07:45.062663 CA_UI_PI_RATIO = 0
3781 18:07:45.065937 ===================================
3782 18:07:45.069430 ===================================
3783 18:07:45.072876 memory_type:LPDDR4
3784 18:07:45.072988 GP_NUM : 10
3785 18:07:45.076187 SRAM_EN : 1
3786 18:07:45.079611 MD32_EN : 0
3787 18:07:45.082374 ===================================
3788 18:07:45.082459 [ANA_INIT] >>>>>>>>>>>>>>
3789 18:07:45.085989 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 18:07:45.089452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 18:07:45.092307 ===================================
3792 18:07:45.095855 data_rate = 1200,PCW = 0X5800
3793 18:07:45.099214 ===================================
3794 18:07:45.102741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 18:07:45.109346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 18:07:45.112279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 18:07:45.119210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 18:07:45.122211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 18:07:45.125902 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 18:07:45.129461 [ANA_INIT] flow start
3801 18:07:45.129543 [ANA_INIT] PLL >>>>>>>>
3802 18:07:45.132454 [ANA_INIT] PLL <<<<<<<<
3803 18:07:45.135757 [ANA_INIT] MIDPI >>>>>>>>
3804 18:07:45.135847 [ANA_INIT] MIDPI <<<<<<<<
3805 18:07:45.139330 [ANA_INIT] DLL >>>>>>>>
3806 18:07:45.142441 [ANA_INIT] flow end
3807 18:07:45.145651 ============ LP4 DIFF to SE enter ============
3808 18:07:45.148894 ============ LP4 DIFF to SE exit ============
3809 18:07:45.151994 [ANA_INIT] <<<<<<<<<<<<<
3810 18:07:45.155529 [Flow] Enable top DCM control >>>>>
3811 18:07:45.159322 [Flow] Enable top DCM control <<<<<
3812 18:07:45.162661 Enable DLL master slave shuffle
3813 18:07:45.165656 ==============================================================
3814 18:07:45.168903 Gating Mode config
3815 18:07:45.175570 ==============================================================
3816 18:07:45.175713 Config description:
3817 18:07:45.185593 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 18:07:45.192799 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 18:07:45.195716 SELPH_MODE 0: By rank 1: By Phase
3820 18:07:45.201911 ==============================================================
3821 18:07:45.205553 GAT_TRACK_EN = 1
3822 18:07:45.209178 RX_GATING_MODE = 2
3823 18:07:45.212507 RX_GATING_TRACK_MODE = 2
3824 18:07:45.215642 SELPH_MODE = 1
3825 18:07:45.219131 PICG_EARLY_EN = 1
3826 18:07:45.222378 VALID_LAT_VALUE = 1
3827 18:07:45.225090 ==============================================================
3828 18:07:45.228686 Enter into Gating configuration >>>>
3829 18:07:45.232142 Exit from Gating configuration <<<<
3830 18:07:45.235166 Enter into DVFS_PRE_config >>>>>
3831 18:07:45.248743 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 18:07:45.248897 Exit from DVFS_PRE_config <<<<<
3833 18:07:45.251885 Enter into PICG configuration >>>>
3834 18:07:45.255398 Exit from PICG configuration <<<<
3835 18:07:45.258657 [RX_INPUT] configuration >>>>>
3836 18:07:45.261803 [RX_INPUT] configuration <<<<<
3837 18:07:45.268162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 18:07:45.271738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 18:07:45.278561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 18:07:45.285479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 18:07:45.291643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 18:07:45.298691 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 18:07:45.301522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 18:07:45.305105 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 18:07:45.308563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 18:07:45.314926 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 18:07:45.318509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 18:07:45.321234 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 18:07:45.324641 ===================================
3850 18:07:45.327833 LPDDR4 DRAM CONFIGURATION
3851 18:07:45.331680 ===================================
3852 18:07:45.331787 EX_ROW_EN[0] = 0x0
3853 18:07:45.334782 EX_ROW_EN[1] = 0x0
3854 18:07:45.338021 LP4Y_EN = 0x0
3855 18:07:45.338112 WORK_FSP = 0x0
3856 18:07:45.341633 WL = 0x2
3857 18:07:45.341719 RL = 0x2
3858 18:07:45.344747 BL = 0x2
3859 18:07:45.344831 RPST = 0x0
3860 18:07:45.348353 RD_PRE = 0x0
3861 18:07:45.348440 WR_PRE = 0x1
3862 18:07:45.351130 WR_PST = 0x0
3863 18:07:45.351213 DBI_WR = 0x0
3864 18:07:45.355047 DBI_RD = 0x0
3865 18:07:45.355132 OTF = 0x1
3866 18:07:45.357915 ===================================
3867 18:07:45.361138 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 18:07:45.368033 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 18:07:45.371390 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 18:07:45.374333 ===================================
3871 18:07:45.378410 LPDDR4 DRAM CONFIGURATION
3872 18:07:45.381147 ===================================
3873 18:07:45.381236 EX_ROW_EN[0] = 0x10
3874 18:07:45.384653 EX_ROW_EN[1] = 0x0
3875 18:07:45.388085 LP4Y_EN = 0x0
3876 18:07:45.388175 WORK_FSP = 0x0
3877 18:07:45.391059 WL = 0x2
3878 18:07:45.391147 RL = 0x2
3879 18:07:45.394506 BL = 0x2
3880 18:07:45.394593 RPST = 0x0
3881 18:07:45.397647 RD_PRE = 0x0
3882 18:07:45.397790 WR_PRE = 0x1
3883 18:07:45.401380 WR_PST = 0x0
3884 18:07:45.401473 DBI_WR = 0x0
3885 18:07:45.404700 DBI_RD = 0x0
3886 18:07:45.404793 OTF = 0x1
3887 18:07:45.407646 ===================================
3888 18:07:45.414765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 18:07:45.418313 nWR fixed to 30
3890 18:07:45.421841 [ModeRegInit_LP4] CH0 RK0
3891 18:07:45.421936 [ModeRegInit_LP4] CH0 RK1
3892 18:07:45.425377 [ModeRegInit_LP4] CH1 RK0
3893 18:07:45.428210 [ModeRegInit_LP4] CH1 RK1
3894 18:07:45.428334 match AC timing 17
3895 18:07:45.435223 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 18:07:45.438533 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 18:07:45.441817 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 18:07:45.448209 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 18:07:45.451700 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 18:07:45.451809 ==
3901 18:07:45.454764 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 18:07:45.458218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 18:07:45.458361 ==
3904 18:07:45.464803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 18:07:45.471761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3906 18:07:45.475030 [CA 0] Center 35 (5~66) winsize 62
3907 18:07:45.478625 [CA 1] Center 35 (5~66) winsize 62
3908 18:07:45.481304 [CA 2] Center 33 (3~64) winsize 62
3909 18:07:45.484505 [CA 3] Center 33 (2~64) winsize 63
3910 18:07:45.487888 [CA 4] Center 33 (2~64) winsize 63
3911 18:07:45.491948 [CA 5] Center 32 (2~63) winsize 62
3912 18:07:45.492059
3913 18:07:45.494987 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3914 18:07:45.495071
3915 18:07:45.498404 [CATrainingPosCal] consider 1 rank data
3916 18:07:45.501283 u2DelayCellTimex100 = 270/100 ps
3917 18:07:45.505139 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3918 18:07:45.508635 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3919 18:07:45.511982 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3920 18:07:45.514719 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 18:07:45.518358 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3922 18:07:45.524746 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3923 18:07:45.524863
3924 18:07:45.528292 CA PerBit enable=1, Macro0, CA PI delay=32
3925 18:07:45.528407
3926 18:07:45.531149 [CBTSetCACLKResult] CA Dly = 32
3927 18:07:45.531250 CS Dly: 4 (0~35)
3928 18:07:45.531340 ==
3929 18:07:45.534955 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 18:07:45.537604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 18:07:45.541235 ==
3932 18:07:45.544628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 18:07:45.551156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3934 18:07:45.554786 [CA 0] Center 35 (5~66) winsize 62
3935 18:07:45.558074 [CA 1] Center 35 (5~66) winsize 62
3936 18:07:45.560827 [CA 2] Center 34 (3~65) winsize 63
3937 18:07:45.564691 [CA 3] Center 34 (3~65) winsize 63
3938 18:07:45.568071 [CA 4] Center 33 (2~64) winsize 63
3939 18:07:45.571331 [CA 5] Center 32 (2~63) winsize 62
3940 18:07:45.571442
3941 18:07:45.574510 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3942 18:07:45.574617
3943 18:07:45.577919 [CATrainingPosCal] consider 2 rank data
3944 18:07:45.580845 u2DelayCellTimex100 = 270/100 ps
3945 18:07:45.584035 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 18:07:45.587716 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3947 18:07:45.590857 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 18:07:45.597739 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3949 18:07:45.600355 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3950 18:07:45.604249 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3951 18:07:45.604397
3952 18:07:45.606994 CA PerBit enable=1, Macro0, CA PI delay=32
3953 18:07:45.607107
3954 18:07:45.610765 [CBTSetCACLKResult] CA Dly = 32
3955 18:07:45.610896 CS Dly: 4 (0~36)
3956 18:07:45.611015
3957 18:07:45.614014 ----->DramcWriteLeveling(PI) begin...
3958 18:07:45.617230 ==
3959 18:07:45.617351 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 18:07:45.624165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 18:07:45.624323 ==
3962 18:07:45.627007 Write leveling (Byte 0): 33 => 33
3963 18:07:45.630637 Write leveling (Byte 1): 32 => 32
3964 18:07:45.634202 DramcWriteLeveling(PI) end<-----
3965 18:07:45.634340
3966 18:07:45.634413 ==
3967 18:07:45.637059 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 18:07:45.640565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 18:07:45.640708 ==
3970 18:07:45.644165 [Gating] SW mode calibration
3971 18:07:45.650568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 18:07:45.653830 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 18:07:45.660439 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 18:07:45.663889 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 18:07:45.666741 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 18:07:45.673771 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
3977 18:07:45.677186 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3978 18:07:45.680382 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 18:07:45.687063 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 18:07:45.690735 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 18:07:45.693208 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 18:07:45.700498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 18:07:45.703673 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 18:07:45.706803 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3985 18:07:45.713267 0 10 16 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3986 18:07:45.716451 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 18:07:45.719860 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 18:07:45.726668 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 18:07:45.730258 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 18:07:45.733285 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 18:07:45.739690 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 18:07:45.743221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3993 18:07:45.746641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3994 18:07:45.753095 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 18:07:45.756715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 18:07:45.760022 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 18:07:45.765982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 18:07:45.769399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 18:07:45.773046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 18:07:45.779207 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 18:07:45.782599 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 18:07:45.786526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 18:07:45.793107 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 18:07:45.796058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 18:07:45.799476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 18:07:45.805856 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 18:07:45.809347 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 18:07:45.812331 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 18:07:45.819137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4010 18:07:45.819241 Total UI for P1: 0, mck2ui 16
4011 18:07:45.825837 best dqsien dly found for B0: ( 0, 13, 12)
4012 18:07:45.829505 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 18:07:45.832281 Total UI for P1: 0, mck2ui 16
4014 18:07:45.835925 best dqsien dly found for B1: ( 0, 13, 16)
4015 18:07:45.839244 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 18:07:45.842981 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 18:07:45.843072
4018 18:07:45.845887 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 18:07:45.849798 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 18:07:45.852659 [Gating] SW calibration Done
4021 18:07:45.852741 ==
4022 18:07:45.856032 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 18:07:45.859130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 18:07:45.859241 ==
4025 18:07:45.862437 RX Vref Scan: 0
4026 18:07:45.862556
4027 18:07:45.866008 RX Vref 0 -> 0, step: 1
4028 18:07:45.866117
4029 18:07:45.866219 RX Delay -230 -> 252, step: 16
4030 18:07:45.872930 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4031 18:07:45.876363 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4032 18:07:45.879128 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4033 18:07:45.882676 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4034 18:07:45.889454 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 18:07:45.892787 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4036 18:07:45.895705 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 18:07:45.899401 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 18:07:45.902859 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4039 18:07:45.909183 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4040 18:07:45.912490 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4041 18:07:45.916191 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4042 18:07:45.919784 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4043 18:07:45.926244 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4044 18:07:45.929623 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4045 18:07:45.932331 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4046 18:07:45.932456 ==
4047 18:07:45.935727 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 18:07:45.939144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 18:07:45.942755 ==
4050 18:07:45.942866 DQS Delay:
4051 18:07:45.942960 DQS0 = 0, DQS1 = 0
4052 18:07:45.946199 DQM Delay:
4053 18:07:45.946329 DQM0 = 49, DQM1 = 45
4054 18:07:45.949494 DQ Delay:
4055 18:07:45.949587 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4056 18:07:45.952678 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4057 18:07:45.955764 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4058 18:07:45.958851 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4059 18:07:45.958990
4060 18:07:45.962121
4061 18:07:45.962250 ==
4062 18:07:45.966213 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 18:07:45.969211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 18:07:45.969338 ==
4065 18:07:45.969438
4066 18:07:45.969530
4067 18:07:45.972185 TX Vref Scan disable
4068 18:07:45.972300 == TX Byte 0 ==
4069 18:07:45.978722 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 18:07:45.982139 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 18:07:45.982269 == TX Byte 1 ==
4072 18:07:45.989544 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4073 18:07:45.992035 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4074 18:07:45.992155 ==
4075 18:07:45.995583 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 18:07:45.998989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 18:07:45.999107 ==
4078 18:07:45.999206
4079 18:07:45.999299
4080 18:07:46.002507 TX Vref Scan disable
4081 18:07:46.006168 == TX Byte 0 ==
4082 18:07:46.008927 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 18:07:46.012561 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 18:07:46.015765 == TX Byte 1 ==
4085 18:07:46.019249 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4086 18:07:46.022256 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4087 18:07:46.022370
4088 18:07:46.025891 [DATLAT]
4089 18:07:46.026004 Freq=600, CH0 RK0
4090 18:07:46.026100
4091 18:07:46.028754 DATLAT Default: 0x9
4092 18:07:46.028867 0, 0xFFFF, sum = 0
4093 18:07:46.032326 1, 0xFFFF, sum = 0
4094 18:07:46.032454 2, 0xFFFF, sum = 0
4095 18:07:46.036036 3, 0xFFFF, sum = 0
4096 18:07:46.036201 4, 0xFFFF, sum = 0
4097 18:07:46.039019 5, 0xFFFF, sum = 0
4098 18:07:46.039154 6, 0xFFFF, sum = 0
4099 18:07:46.042563 7, 0xFFFF, sum = 0
4100 18:07:46.042703 8, 0x0, sum = 1
4101 18:07:46.045887 9, 0x0, sum = 2
4102 18:07:46.046029 10, 0x0, sum = 3
4103 18:07:46.048882 11, 0x0, sum = 4
4104 18:07:46.049008 best_step = 9
4105 18:07:46.049112
4106 18:07:46.049209 ==
4107 18:07:46.052253 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 18:07:46.055800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 18:07:46.059135 ==
4110 18:07:46.059262 RX Vref Scan: 1
4111 18:07:46.059357
4112 18:07:46.062191 RX Vref 0 -> 0, step: 1
4113 18:07:46.062305
4114 18:07:46.065815 RX Delay -163 -> 252, step: 8
4115 18:07:46.065926
4116 18:07:46.068619 Set Vref, RX VrefLevel [Byte0]: 55
4117 18:07:46.072175 [Byte1]: 43
4118 18:07:46.072293
4119 18:07:46.075738 Final RX Vref Byte 0 = 55 to rank0
4120 18:07:46.078590 Final RX Vref Byte 1 = 43 to rank0
4121 18:07:46.081930 Final RX Vref Byte 0 = 55 to rank1
4122 18:07:46.085360 Final RX Vref Byte 1 = 43 to rank1==
4123 18:07:46.088875 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 18:07:46.092142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 18:07:46.092261 ==
4126 18:07:46.092367 DQS Delay:
4127 18:07:46.095195 DQS0 = 0, DQS1 = 0
4128 18:07:46.095293 DQM Delay:
4129 18:07:46.098339 DQM0 = 53, DQM1 = 48
4130 18:07:46.098455 DQ Delay:
4131 18:07:46.102306 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4132 18:07:46.105576 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4133 18:07:46.108613 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4134 18:07:46.111832 DQ12 =52, DQ13 =56, DQ14 =60, DQ15 =56
4135 18:07:46.111976
4136 18:07:46.112075
4137 18:07:46.121814 [DQSOSCAuto] RK0, (LSB)MR18= 0x695c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
4138 18:07:46.121945 CH0 RK0: MR19=808, MR18=695C
4139 18:07:46.128325 CH0_RK0: MR19=0x808, MR18=0x695C, DQSOSC=390, MR23=63, INC=172, DEC=114
4140 18:07:46.128431
4141 18:07:46.132096 ----->DramcWriteLeveling(PI) begin...
4142 18:07:46.132214 ==
4143 18:07:46.135065 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 18:07:46.141597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 18:07:46.141690 ==
4146 18:07:46.145084 Write leveling (Byte 0): 36 => 36
4147 18:07:46.148911 Write leveling (Byte 1): 31 => 31
4148 18:07:46.149006 DramcWriteLeveling(PI) end<-----
4149 18:07:46.151612
4150 18:07:46.151685 ==
4151 18:07:46.155173 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 18:07:46.158838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 18:07:46.158915 ==
4154 18:07:46.161483 [Gating] SW mode calibration
4155 18:07:46.168181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 18:07:46.171640 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 18:07:46.178228 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 18:07:46.181734 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 18:07:46.184729 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 18:07:46.191534 0 9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 0)
4161 18:07:46.194986 0 9 16 | B1->B0 | 2e2e 2d2d | 1 1 | (1 1) (1 1)
4162 18:07:46.197718 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 18:07:46.204593 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 18:07:46.208265 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 18:07:46.211013 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 18:07:46.218081 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 18:07:46.221031 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 18:07:46.224977 0 10 12 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (1 1)
4169 18:07:46.231314 0 10 16 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (0 0)
4170 18:07:46.234937 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 18:07:46.238586 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 18:07:46.244902 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 18:07:46.247846 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 18:07:46.251446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 18:07:46.258129 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 18:07:46.261864 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4177 18:07:46.265494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 18:07:46.271465 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 18:07:46.274822 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 18:07:46.277876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 18:07:46.281318 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 18:07:46.287859 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 18:07:46.291621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 18:07:46.294717 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 18:07:46.300670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 18:07:46.304483 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 18:07:46.307929 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 18:07:46.314489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 18:07:46.317982 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 18:07:46.320764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 18:07:46.327921 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4192 18:07:46.331064 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4193 18:07:46.334341 Total UI for P1: 0, mck2ui 16
4194 18:07:46.337861 best dqsien dly found for B0: ( 0, 13, 10)
4195 18:07:46.341264 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 18:07:46.344818 Total UI for P1: 0, mck2ui 16
4197 18:07:46.348045 best dqsien dly found for B1: ( 0, 13, 10)
4198 18:07:46.351197 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4199 18:07:46.354160 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4200 18:07:46.354278
4201 18:07:46.360882 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4202 18:07:46.364176 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4203 18:07:46.367541 [Gating] SW calibration Done
4204 18:07:46.367652 ==
4205 18:07:46.371133 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 18:07:46.374032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 18:07:46.374129 ==
4208 18:07:46.374224 RX Vref Scan: 0
4209 18:07:46.374315
4210 18:07:46.377065 RX Vref 0 -> 0, step: 1
4211 18:07:46.377167
4212 18:07:46.380680 RX Delay -230 -> 252, step: 16
4213 18:07:46.384404 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4214 18:07:46.390675 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4215 18:07:46.394357 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4216 18:07:46.397393 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4217 18:07:46.400567 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4218 18:07:46.404032 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4219 18:07:46.410700 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4220 18:07:46.414213 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4221 18:07:46.417664 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4222 18:07:46.420711 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4223 18:07:46.424357 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4224 18:07:46.430988 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4225 18:07:46.433836 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4226 18:07:46.437308 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4227 18:07:46.440678 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4228 18:07:46.447190 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4229 18:07:46.447301 ==
4230 18:07:46.450197 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 18:07:46.453817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 18:07:46.453898 ==
4233 18:07:46.453964 DQS Delay:
4234 18:07:46.457186 DQS0 = 0, DQS1 = 0
4235 18:07:46.457291 DQM Delay:
4236 18:07:46.460220 DQM0 = 54, DQM1 = 44
4237 18:07:46.460326 DQ Delay:
4238 18:07:46.463675 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4239 18:07:46.467252 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4240 18:07:46.470350 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4241 18:07:46.473397 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4242 18:07:46.473510
4243 18:07:46.473605
4244 18:07:46.473708 ==
4245 18:07:46.477289 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 18:07:46.480531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 18:07:46.483319 ==
4248 18:07:46.483425
4249 18:07:46.483518
4250 18:07:46.483607 TX Vref Scan disable
4251 18:07:46.487317 == TX Byte 0 ==
4252 18:07:46.490477 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4253 18:07:46.493663 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4254 18:07:46.496997 == TX Byte 1 ==
4255 18:07:46.500158 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4256 18:07:46.503822 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4257 18:07:46.506700 ==
4258 18:07:46.506810 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 18:07:46.513181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 18:07:46.513299 ==
4261 18:07:46.513370
4262 18:07:46.513433
4263 18:07:46.517010 TX Vref Scan disable
4264 18:07:46.517114 == TX Byte 0 ==
4265 18:07:46.523161 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4266 18:07:46.526486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4267 18:07:46.526595 == TX Byte 1 ==
4268 18:07:46.533805 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 18:07:46.536665 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 18:07:46.536770
4271 18:07:46.536867 [DATLAT]
4272 18:07:46.540373 Freq=600, CH0 RK1
4273 18:07:46.540485
4274 18:07:46.540583 DATLAT Default: 0x9
4275 18:07:46.543282 0, 0xFFFF, sum = 0
4276 18:07:46.543368 1, 0xFFFF, sum = 0
4277 18:07:46.546771 2, 0xFFFF, sum = 0
4278 18:07:46.546869 3, 0xFFFF, sum = 0
4279 18:07:46.550348 4, 0xFFFF, sum = 0
4280 18:07:46.553735 5, 0xFFFF, sum = 0
4281 18:07:46.553824 6, 0xFFFF, sum = 0
4282 18:07:46.556353 7, 0xFFFF, sum = 0
4283 18:07:46.556439 8, 0x0, sum = 1
4284 18:07:46.556507 9, 0x0, sum = 2
4285 18:07:46.559835 10, 0x0, sum = 3
4286 18:07:46.559950 11, 0x0, sum = 4
4287 18:07:46.563424 best_step = 9
4288 18:07:46.563534
4289 18:07:46.563632 ==
4290 18:07:46.566495 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 18:07:46.570033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 18:07:46.570141 ==
4293 18:07:46.572890 RX Vref Scan: 0
4294 18:07:46.572997
4295 18:07:46.573088 RX Vref 0 -> 0, step: 1
4296 18:07:46.573176
4297 18:07:46.576508 RX Delay -163 -> 252, step: 8
4298 18:07:46.583443 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4299 18:07:46.587080 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4300 18:07:46.590533 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4301 18:07:46.593909 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4302 18:07:46.597220 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4303 18:07:46.603421 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4304 18:07:46.607075 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4305 18:07:46.610069 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4306 18:07:46.613267 iDelay=197, Bit 8, Center 36 (-99 ~ 172) 272
4307 18:07:46.617249 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4308 18:07:46.623680 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4309 18:07:46.626470 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4310 18:07:46.629837 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4311 18:07:46.633655 iDelay=197, Bit 13, Center 52 (-83 ~ 188) 272
4312 18:07:46.640058 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4313 18:07:46.643699 iDelay=197, Bit 15, Center 56 (-83 ~ 196) 280
4314 18:07:46.643811 ==
4315 18:07:46.646838 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 18:07:46.650400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 18:07:46.650509 ==
4318 18:07:46.650609 DQS Delay:
4319 18:07:46.653113 DQS0 = 0, DQS1 = 0
4320 18:07:46.653220 DQM Delay:
4321 18:07:46.656638 DQM0 = 53, DQM1 = 46
4322 18:07:46.656742 DQ Delay:
4323 18:07:46.659712 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4324 18:07:46.663050 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4325 18:07:46.666731 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4326 18:07:46.670046 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4327 18:07:46.670151
4328 18:07:46.670239
4329 18:07:46.679822 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4330 18:07:46.679938 CH0 RK1: MR19=808, MR18=5D1E
4331 18:07:46.687004 CH0_RK1: MR19=0x808, MR18=0x5D1E, DQSOSC=392, MR23=63, INC=170, DEC=113
4332 18:07:46.689948 [RxdqsGatingPostProcess] freq 600
4333 18:07:46.696649 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 18:07:46.700141 Pre-setting of DQS Precalculation
4335 18:07:46.703949 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 18:07:46.704060 ==
4337 18:07:46.706635 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 18:07:46.710467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 18:07:46.713229 ==
4340 18:07:46.717105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 18:07:46.723359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4342 18:07:46.727043 [CA 0] Center 35 (5~66) winsize 62
4343 18:07:46.730204 [CA 1] Center 36 (6~66) winsize 61
4344 18:07:46.733622 [CA 2] Center 34 (4~65) winsize 62
4345 18:07:46.736765 [CA 3] Center 34 (4~65) winsize 62
4346 18:07:46.740119 [CA 4] Center 34 (4~65) winsize 62
4347 18:07:46.743221 [CA 5] Center 34 (4~64) winsize 61
4348 18:07:46.743332
4349 18:07:46.746575 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4350 18:07:46.746668
4351 18:07:46.749641 [CATrainingPosCal] consider 1 rank data
4352 18:07:46.753029 u2DelayCellTimex100 = 270/100 ps
4353 18:07:46.756627 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4354 18:07:46.759466 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4355 18:07:46.763154 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 18:07:46.769210 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 18:07:46.772941 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 18:07:46.776273 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4359 18:07:46.776357
4360 18:07:46.779486 CA PerBit enable=1, Macro0, CA PI delay=34
4361 18:07:46.779569
4362 18:07:46.782855 [CBTSetCACLKResult] CA Dly = 34
4363 18:07:46.782963 CS Dly: 6 (0~37)
4364 18:07:46.783058 ==
4365 18:07:46.786323 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 18:07:46.792403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 18:07:46.792488 ==
4368 18:07:46.796081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 18:07:46.802497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4370 18:07:46.805933 [CA 0] Center 36 (5~67) winsize 63
4371 18:07:46.809233 [CA 1] Center 36 (5~67) winsize 63
4372 18:07:46.812694 [CA 2] Center 34 (4~65) winsize 62
4373 18:07:46.815770 [CA 3] Center 34 (4~65) winsize 62
4374 18:07:46.819477 [CA 4] Center 34 (4~65) winsize 62
4375 18:07:46.822598 [CA 5] Center 34 (4~65) winsize 62
4376 18:07:46.822706
4377 18:07:46.825962 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4378 18:07:46.826042
4379 18:07:46.829019 [CATrainingPosCal] consider 2 rank data
4380 18:07:46.832555 u2DelayCellTimex100 = 270/100 ps
4381 18:07:46.835856 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4382 18:07:46.839253 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4383 18:07:46.845972 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 18:07:46.849606 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4385 18:07:46.852329 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 18:07:46.856187 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4387 18:07:46.856361
4388 18:07:46.859463 CA PerBit enable=1, Macro0, CA PI delay=34
4389 18:07:46.859559
4390 18:07:46.862220 [CBTSetCACLKResult] CA Dly = 34
4391 18:07:46.862306 CS Dly: 6 (0~38)
4392 18:07:46.862370
4393 18:07:46.865781 ----->DramcWriteLeveling(PI) begin...
4394 18:07:46.869441 ==
4395 18:07:46.872266 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 18:07:46.875870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 18:07:46.875956 ==
4398 18:07:46.879352 Write leveling (Byte 0): 30 => 30
4399 18:07:46.882550 Write leveling (Byte 1): 30 => 30
4400 18:07:46.885731 DramcWriteLeveling(PI) end<-----
4401 18:07:46.885823
4402 18:07:46.885891 ==
4403 18:07:46.889072 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 18:07:46.892358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 18:07:46.892468 ==
4406 18:07:46.896173 [Gating] SW mode calibration
4407 18:07:46.902507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 18:07:46.905378 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 18:07:46.912238 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 18:07:46.915933 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 18:07:46.918860 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 18:07:46.925788 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 0)
4413 18:07:46.928571 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 18:07:46.932185 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 18:07:46.938832 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 18:07:46.942241 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 18:07:46.945345 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 18:07:46.952026 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 18:07:46.955469 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 18:07:46.959021 0 10 12 | B1->B0 | 3838 3938 | 0 1 | (0 0) (0 0)
4421 18:07:46.965626 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 18:07:46.968701 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 18:07:46.971919 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 18:07:46.978996 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 18:07:46.982085 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 18:07:46.985555 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 18:07:46.992258 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 18:07:46.995444 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4429 18:07:46.998625 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 18:07:47.005423 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 18:07:47.008287 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 18:07:47.011678 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 18:07:47.018600 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 18:07:47.021904 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 18:07:47.025501 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 18:07:47.031796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 18:07:47.035224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 18:07:47.038793 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 18:07:47.045345 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 18:07:47.048308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 18:07:47.051834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 18:07:47.058358 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 18:07:47.061398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 18:07:47.064798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4445 18:07:47.067943 Total UI for P1: 0, mck2ui 16
4446 18:07:47.071730 best dqsien dly found for B0: ( 0, 13, 8)
4447 18:07:47.074960 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 18:07:47.078199 Total UI for P1: 0, mck2ui 16
4449 18:07:47.081416 best dqsien dly found for B1: ( 0, 13, 12)
4450 18:07:47.085333 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4451 18:07:47.091449 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4452 18:07:47.091531
4453 18:07:47.094841 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4454 18:07:47.098039 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4455 18:07:47.101457 [Gating] SW calibration Done
4456 18:07:47.101531 ==
4457 18:07:47.105152 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 18:07:47.108305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 18:07:47.108438 ==
4460 18:07:47.111585 RX Vref Scan: 0
4461 18:07:47.111659
4462 18:07:47.111722 RX Vref 0 -> 0, step: 1
4463 18:07:47.111781
4464 18:07:47.114551 RX Delay -230 -> 252, step: 16
4465 18:07:47.117874 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4466 18:07:47.125163 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4467 18:07:47.128059 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4468 18:07:47.131197 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 18:07:47.134838 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 18:07:47.137865 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4471 18:07:47.144834 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4472 18:07:47.147759 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 18:07:47.151445 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4474 18:07:47.154875 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4475 18:07:47.161210 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4476 18:07:47.164232 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4477 18:07:47.167826 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4478 18:07:47.171180 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4479 18:07:47.174250 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4480 18:07:47.180970 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4481 18:07:47.181053 ==
4482 18:07:47.184194 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 18:07:47.188252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 18:07:47.188396 ==
4485 18:07:47.188463 DQS Delay:
4486 18:07:47.191598 DQS0 = 0, DQS1 = 0
4487 18:07:47.191679 DQM Delay:
4488 18:07:47.194637 DQM0 = 49, DQM1 = 49
4489 18:07:47.194717 DQ Delay:
4490 18:07:47.197527 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4491 18:07:47.201381 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4492 18:07:47.203880 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4493 18:07:47.207292 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4494 18:07:47.207373
4495 18:07:47.207437
4496 18:07:47.207496 ==
4497 18:07:47.210635 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 18:07:47.214257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 18:07:47.217749 ==
4500 18:07:47.217830
4501 18:07:47.217933
4502 18:07:47.218024 TX Vref Scan disable
4503 18:07:47.220928 == TX Byte 0 ==
4504 18:07:47.224013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4505 18:07:47.227383 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4506 18:07:47.230736 == TX Byte 1 ==
4507 18:07:47.234111 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 18:07:47.237510 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 18:07:47.240977 ==
4510 18:07:47.243962 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 18:07:47.247544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 18:07:47.247631 ==
4513 18:07:47.247696
4514 18:07:47.247756
4515 18:07:47.250992 TX Vref Scan disable
4516 18:07:47.251081 == TX Byte 0 ==
4517 18:07:47.257597 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 18:07:47.260369 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 18:07:47.260518 == TX Byte 1 ==
4520 18:07:47.267169 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 18:07:47.270242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 18:07:47.270325
4523 18:07:47.270389 [DATLAT]
4524 18:07:47.273857 Freq=600, CH1 RK0
4525 18:07:47.273938
4526 18:07:47.274001 DATLAT Default: 0x9
4527 18:07:47.277541 0, 0xFFFF, sum = 0
4528 18:07:47.277623 1, 0xFFFF, sum = 0
4529 18:07:47.281006 2, 0xFFFF, sum = 0
4530 18:07:47.281089 3, 0xFFFF, sum = 0
4531 18:07:47.283640 4, 0xFFFF, sum = 0
4532 18:07:47.287208 5, 0xFFFF, sum = 0
4533 18:07:47.287317 6, 0xFFFF, sum = 0
4534 18:07:47.290588 7, 0xFFFF, sum = 0
4535 18:07:47.290698 8, 0x0, sum = 1
4536 18:07:47.290800 9, 0x0, sum = 2
4537 18:07:47.293533 10, 0x0, sum = 3
4538 18:07:47.293633 11, 0x0, sum = 4
4539 18:07:47.297181 best_step = 9
4540 18:07:47.297251
4541 18:07:47.297326 ==
4542 18:07:47.300681 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 18:07:47.303771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 18:07:47.303868 ==
4545 18:07:47.307176 RX Vref Scan: 1
4546 18:07:47.307244
4547 18:07:47.307302 RX Vref 0 -> 0, step: 1
4548 18:07:47.307358
4549 18:07:47.310407 RX Delay -163 -> 252, step: 8
4550 18:07:47.310487
4551 18:07:47.313944 Set Vref, RX VrefLevel [Byte0]: 53
4552 18:07:47.316963 [Byte1]: 47
4553 18:07:47.320839
4554 18:07:47.320957 Final RX Vref Byte 0 = 53 to rank0
4555 18:07:47.323996 Final RX Vref Byte 1 = 47 to rank0
4556 18:07:47.327392 Final RX Vref Byte 0 = 53 to rank1
4557 18:07:47.330921 Final RX Vref Byte 1 = 47 to rank1==
4558 18:07:47.334273 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 18:07:47.337878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 18:07:47.341317 ==
4561 18:07:47.341400 DQS Delay:
4562 18:07:47.341465 DQS0 = 0, DQS1 = 0
4563 18:07:47.344618 DQM Delay:
4564 18:07:47.344699 DQM0 = 47, DQM1 = 45
4565 18:07:47.347801 DQ Delay:
4566 18:07:47.351313 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =44
4567 18:07:47.351394 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4568 18:07:47.354216 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4569 18:07:47.357795 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4570 18:07:47.360765
4571 18:07:47.360845
4572 18:07:47.367253 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4573 18:07:47.370759 CH1 RK0: MR19=808, MR18=446A
4574 18:07:47.377363 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4575 18:07:47.377462
4576 18:07:47.380560 ----->DramcWriteLeveling(PI) begin...
4577 18:07:47.380661 ==
4578 18:07:47.384093 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 18:07:47.387328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 18:07:47.387426 ==
4581 18:07:47.390939 Write leveling (Byte 0): 29 => 29
4582 18:07:47.393713 Write leveling (Byte 1): 30 => 30
4583 18:07:47.397468 DramcWriteLeveling(PI) end<-----
4584 18:07:47.397551
4585 18:07:47.397616 ==
4586 18:07:47.400897 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 18:07:47.403601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 18:07:47.403684 ==
4589 18:07:47.407195 [Gating] SW mode calibration
4590 18:07:47.413480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 18:07:47.420433 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 18:07:47.424132 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 18:07:47.430052 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 18:07:47.433406 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 18:07:47.437163 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4596 18:07:47.440079 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 18:07:47.447061 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 18:07:47.450453 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 18:07:47.453365 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 18:07:47.460483 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 18:07:47.463601 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 18:07:47.467107 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 18:07:47.473504 0 10 12 | B1->B0 | 3e3e 3232 | 0 0 | (0 0) (0 0)
4604 18:07:47.476903 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 18:07:47.480549 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 18:07:47.486890 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 18:07:47.490381 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 18:07:47.493871 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 18:07:47.499910 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 18:07:47.503225 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 18:07:47.506794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4612 18:07:47.513262 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 18:07:47.516534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 18:07:47.520504 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 18:07:47.526866 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 18:07:47.530360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 18:07:47.533846 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 18:07:47.540320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 18:07:47.543929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 18:07:47.546649 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 18:07:47.549988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 18:07:47.556679 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 18:07:47.560076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 18:07:47.563888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 18:07:47.570158 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 18:07:47.573739 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4627 18:07:47.576902 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4628 18:07:47.580649 Total UI for P1: 0, mck2ui 16
4629 18:07:47.583652 best dqsien dly found for B1: ( 0, 13, 8)
4630 18:07:47.590004 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 18:07:47.590085 Total UI for P1: 0, mck2ui 16
4632 18:07:47.597104 best dqsien dly found for B0: ( 0, 13, 12)
4633 18:07:47.600262 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4634 18:07:47.603767 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4635 18:07:47.603849
4636 18:07:47.606632 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 18:07:47.610126 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4638 18:07:47.613561 [Gating] SW calibration Done
4639 18:07:47.613642 ==
4640 18:07:47.617244 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 18:07:47.619931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 18:07:47.620013 ==
4643 18:07:47.623403 RX Vref Scan: 0
4644 18:07:47.623484
4645 18:07:47.623568 RX Vref 0 -> 0, step: 1
4646 18:07:47.623631
4647 18:07:47.626728 RX Delay -230 -> 252, step: 16
4648 18:07:47.633949 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4649 18:07:47.636792 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 18:07:47.640035 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4651 18:07:47.643559 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 18:07:47.646499 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 18:07:47.653523 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4654 18:07:47.656959 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4655 18:07:47.660095 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 18:07:47.663565 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 18:07:47.667028 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4658 18:07:47.673256 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 18:07:47.676677 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 18:07:47.680099 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 18:07:47.683573 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4662 18:07:47.689964 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 18:07:47.693242 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 18:07:47.693324 ==
4665 18:07:47.696645 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 18:07:47.699850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 18:07:47.699958 ==
4668 18:07:47.703385 DQS Delay:
4669 18:07:47.703466 DQS0 = 0, DQS1 = 0
4670 18:07:47.703529 DQM Delay:
4671 18:07:47.706997 DQM0 = 50, DQM1 = 48
4672 18:07:47.707078 DQ Delay:
4673 18:07:47.710081 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4674 18:07:47.713616 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4675 18:07:47.716976 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4676 18:07:47.720301 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4677 18:07:47.720434
4678 18:07:47.720499
4679 18:07:47.720558 ==
4680 18:07:47.723029 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 18:07:47.730210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 18:07:47.730293 ==
4683 18:07:47.730359
4684 18:07:47.730423
4685 18:07:47.730479 TX Vref Scan disable
4686 18:07:47.733481 == TX Byte 0 ==
4687 18:07:47.737042 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4688 18:07:47.740496 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4689 18:07:47.743961 == TX Byte 1 ==
4690 18:07:47.747366 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 18:07:47.753735 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 18:07:47.753815 ==
4693 18:07:47.757262 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 18:07:47.760005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 18:07:47.760086 ==
4696 18:07:47.760150
4697 18:07:47.760209
4698 18:07:47.763439 TX Vref Scan disable
4699 18:07:47.763519 == TX Byte 0 ==
4700 18:07:47.770330 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 18:07:47.773546 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 18:07:47.776903 == TX Byte 1 ==
4703 18:07:47.780454 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 18:07:47.783824 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 18:07:47.783906
4706 18:07:47.783970 [DATLAT]
4707 18:07:47.786629 Freq=600, CH1 RK1
4708 18:07:47.786711
4709 18:07:47.786774 DATLAT Default: 0x9
4710 18:07:47.790177 0, 0xFFFF, sum = 0
4711 18:07:47.790259 1, 0xFFFF, sum = 0
4712 18:07:47.793663 2, 0xFFFF, sum = 0
4713 18:07:47.793744 3, 0xFFFF, sum = 0
4714 18:07:47.796960 4, 0xFFFF, sum = 0
4715 18:07:47.800141 5, 0xFFFF, sum = 0
4716 18:07:47.800224 6, 0xFFFF, sum = 0
4717 18:07:47.803327 7, 0xFFFF, sum = 0
4718 18:07:47.803409 8, 0x0, sum = 1
4719 18:07:47.803474 9, 0x0, sum = 2
4720 18:07:47.806917 10, 0x0, sum = 3
4721 18:07:47.806999 11, 0x0, sum = 4
4722 18:07:47.810204 best_step = 9
4723 18:07:47.810285
4724 18:07:47.810348 ==
4725 18:07:47.813303 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 18:07:47.816486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 18:07:47.816568 ==
4728 18:07:47.819691 RX Vref Scan: 0
4729 18:07:47.819771
4730 18:07:47.819834 RX Vref 0 -> 0, step: 1
4731 18:07:47.823030
4732 18:07:47.823110 RX Delay -163 -> 252, step: 8
4733 18:07:47.830664 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4734 18:07:47.834084 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4735 18:07:47.837470 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 18:07:47.840837 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4737 18:07:47.843619 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 18:07:47.850781 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 18:07:47.854230 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4740 18:07:47.857022 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4741 18:07:47.860547 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4742 18:07:47.864110 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4743 18:07:47.870312 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4744 18:07:47.873818 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4745 18:07:47.877131 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4746 18:07:47.880580 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4747 18:07:47.887206 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4748 18:07:47.890668 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4749 18:07:47.890749 ==
4750 18:07:47.893389 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 18:07:47.896892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 18:07:47.896973 ==
4753 18:07:47.900386 DQS Delay:
4754 18:07:47.900467 DQS0 = 0, DQS1 = 0
4755 18:07:47.900531 DQM Delay:
4756 18:07:47.904011 DQM0 = 49, DQM1 = 45
4757 18:07:47.904091 DQ Delay:
4758 18:07:47.906910 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4759 18:07:47.910156 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4760 18:07:47.913431 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4761 18:07:47.916986 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4762 18:07:47.917067
4763 18:07:47.917130
4764 18:07:47.926576 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4765 18:07:47.930730 CH1 RK1: MR19=808, MR18=6B21
4766 18:07:47.933333 CH1_RK1: MR19=0x808, MR18=0x6B21, DQSOSC=389, MR23=63, INC=173, DEC=115
4767 18:07:47.936902 [RxdqsGatingPostProcess] freq 600
4768 18:07:47.943718 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 18:07:47.946926 Pre-setting of DQS Precalculation
4770 18:07:47.950428 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 18:07:47.957226 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 18:07:47.967020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 18:07:47.967125
4774 18:07:47.967217
4775 18:07:47.969891 [Calibration Summary] 1200 Mbps
4776 18:07:47.969964 CH 0, Rank 0
4777 18:07:47.973567 SW Impedance : PASS
4778 18:07:47.973652 DUTY Scan : NO K
4779 18:07:47.977075 ZQ Calibration : PASS
4780 18:07:47.977155 Jitter Meter : NO K
4781 18:07:47.980528 CBT Training : PASS
4782 18:07:47.983251 Write leveling : PASS
4783 18:07:47.983330 RX DQS gating : PASS
4784 18:07:47.986602 RX DQ/DQS(RDDQC) : PASS
4785 18:07:47.989870 TX DQ/DQS : PASS
4786 18:07:47.989952 RX DATLAT : PASS
4787 18:07:47.993319 RX DQ/DQS(Engine): PASS
4788 18:07:47.996658 TX OE : NO K
4789 18:07:47.996741 All Pass.
4790 18:07:47.996810
4791 18:07:47.996875 CH 0, Rank 1
4792 18:07:48.000022 SW Impedance : PASS
4793 18:07:48.003427 DUTY Scan : NO K
4794 18:07:48.003501 ZQ Calibration : PASS
4795 18:07:48.007296 Jitter Meter : NO K
4796 18:07:48.009898 CBT Training : PASS
4797 18:07:48.009978 Write leveling : PASS
4798 18:07:48.013472 RX DQS gating : PASS
4799 18:07:48.016960 RX DQ/DQS(RDDQC) : PASS
4800 18:07:48.017039 TX DQ/DQS : PASS
4801 18:07:48.020193 RX DATLAT : PASS
4802 18:07:48.020273 RX DQ/DQS(Engine): PASS
4803 18:07:48.023518 TX OE : NO K
4804 18:07:48.023611 All Pass.
4805 18:07:48.023676
4806 18:07:48.026819 CH 1, Rank 0
4807 18:07:48.026936 SW Impedance : PASS
4808 18:07:48.030067 DUTY Scan : NO K
4809 18:07:48.033457 ZQ Calibration : PASS
4810 18:07:48.033537 Jitter Meter : NO K
4811 18:07:48.036966 CBT Training : PASS
4812 18:07:48.039855 Write leveling : PASS
4813 18:07:48.039935 RX DQS gating : PASS
4814 18:07:48.043157 RX DQ/DQS(RDDQC) : PASS
4815 18:07:48.046505 TX DQ/DQS : PASS
4816 18:07:48.046626 RX DATLAT : PASS
4817 18:07:48.049907 RX DQ/DQS(Engine): PASS
4818 18:07:48.053075 TX OE : NO K
4819 18:07:48.053187 All Pass.
4820 18:07:48.053282
4821 18:07:48.053384 CH 1, Rank 1
4822 18:07:48.056309 SW Impedance : PASS
4823 18:07:48.059552 DUTY Scan : NO K
4824 18:07:48.059678 ZQ Calibration : PASS
4825 18:07:48.063842 Jitter Meter : NO K
4826 18:07:48.067073 CBT Training : PASS
4827 18:07:48.067213 Write leveling : PASS
4828 18:07:48.070232 RX DQS gating : PASS
4829 18:07:48.073671 RX DQ/DQS(RDDQC) : PASS
4830 18:07:48.074218 TX DQ/DQS : PASS
4831 18:07:48.076886 RX DATLAT : PASS
4832 18:07:48.080622 RX DQ/DQS(Engine): PASS
4833 18:07:48.080976 TX OE : NO K
4834 18:07:48.081443 All Pass.
4835 18:07:48.081761
4836 18:07:48.083263 DramC Write-DBI off
4837 18:07:48.086887 PER_BANK_REFRESH: Hybrid Mode
4838 18:07:48.087392 TX_TRACKING: ON
4839 18:07:48.096973 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 18:07:48.100421 [FAST_K] Save calibration result to emmc
4841 18:07:48.103603 dramc_set_vcore_voltage set vcore to 662500
4842 18:07:48.106922 Read voltage for 933, 3
4843 18:07:48.107301 Vio18 = 0
4844 18:07:48.110459 Vcore = 662500
4845 18:07:48.110835 Vdram = 0
4846 18:07:48.111136 Vddq = 0
4847 18:07:48.111415 Vmddr = 0
4848 18:07:48.116828 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 18:07:48.120326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 18:07:48.123160 MEM_TYPE=3, freq_sel=17
4851 18:07:48.126684 sv_algorithm_assistance_LP4_1600
4852 18:07:48.129946 ============ PULL DRAM RESETB DOWN ============
4853 18:07:48.136712 ========== PULL DRAM RESETB DOWN end =========
4854 18:07:48.140135 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 18:07:48.143722 ===================================
4856 18:07:48.146762 LPDDR4 DRAM CONFIGURATION
4857 18:07:48.150115 ===================================
4858 18:07:48.150494 EX_ROW_EN[0] = 0x0
4859 18:07:48.153584 EX_ROW_EN[1] = 0x0
4860 18:07:48.153961 LP4Y_EN = 0x0
4861 18:07:48.156395 WORK_FSP = 0x0
4862 18:07:48.156775 WL = 0x3
4863 18:07:48.159757 RL = 0x3
4864 18:07:48.160135 BL = 0x2
4865 18:07:48.162952 RPST = 0x0
4866 18:07:48.163329 RD_PRE = 0x0
4867 18:07:48.166150 WR_PRE = 0x1
4868 18:07:48.166527 WR_PST = 0x0
4869 18:07:48.169450 DBI_WR = 0x0
4870 18:07:48.172877 DBI_RD = 0x0
4871 18:07:48.173290 OTF = 0x1
4872 18:07:48.176225 ===================================
4873 18:07:48.180049 ===================================
4874 18:07:48.180460 ANA top config
4875 18:07:48.182930 ===================================
4876 18:07:48.186379 DLL_ASYNC_EN = 0
4877 18:07:48.190186 ALL_SLAVE_EN = 1
4878 18:07:48.192764 NEW_RANK_MODE = 1
4879 18:07:48.196468 DLL_IDLE_MODE = 1
4880 18:07:48.196952 LP45_APHY_COMB_EN = 1
4881 18:07:48.199500 TX_ODT_DIS = 1
4882 18:07:48.202982 NEW_8X_MODE = 1
4883 18:07:48.206559 ===================================
4884 18:07:48.210035 ===================================
4885 18:07:48.213154 data_rate = 1866
4886 18:07:48.216811 CKR = 1
4887 18:07:48.217302 DQ_P2S_RATIO = 8
4888 18:07:48.220425 ===================================
4889 18:07:48.222905 CA_P2S_RATIO = 8
4890 18:07:48.226497 DQ_CA_OPEN = 0
4891 18:07:48.229964 DQ_SEMI_OPEN = 0
4892 18:07:48.233340 CA_SEMI_OPEN = 0
4893 18:07:48.236775 CA_FULL_RATE = 0
4894 18:07:48.237191 DQ_CKDIV4_EN = 1
4895 18:07:48.239657 CA_CKDIV4_EN = 1
4896 18:07:48.243036 CA_PREDIV_EN = 0
4897 18:07:48.246373 PH8_DLY = 0
4898 18:07:48.249634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 18:07:48.250252 DQ_AAMCK_DIV = 4
4900 18:07:48.253066 CA_AAMCK_DIV = 4
4901 18:07:48.256328 CA_ADMCK_DIV = 4
4902 18:07:48.259844 DQ_TRACK_CA_EN = 0
4903 18:07:48.263384 CA_PICK = 933
4904 18:07:48.266226 CA_MCKIO = 933
4905 18:07:48.269556 MCKIO_SEMI = 0
4906 18:07:48.269996 PLL_FREQ = 3732
4907 18:07:48.272908 DQ_UI_PI_RATIO = 32
4908 18:07:48.276838 CA_UI_PI_RATIO = 0
4909 18:07:48.279835 ===================================
4910 18:07:48.282889 ===================================
4911 18:07:48.286516 memory_type:LPDDR4
4912 18:07:48.289508 GP_NUM : 10
4913 18:07:48.289926 SRAM_EN : 1
4914 18:07:48.292940 MD32_EN : 0
4915 18:07:48.296291 ===================================
4916 18:07:48.296772 [ANA_INIT] >>>>>>>>>>>>>>
4917 18:07:48.299194 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 18:07:48.302609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 18:07:48.305896 ===================================
4920 18:07:48.309173 data_rate = 1866,PCW = 0X8f00
4921 18:07:48.312550 ===================================
4922 18:07:48.315981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 18:07:48.322551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 18:07:48.325862 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 18:07:48.332640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 18:07:48.335993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 18:07:48.339329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 18:07:48.342414 [ANA_INIT] flow start
4929 18:07:48.342842 [ANA_INIT] PLL >>>>>>>>
4930 18:07:48.345886 [ANA_INIT] PLL <<<<<<<<
4931 18:07:48.349534 [ANA_INIT] MIDPI >>>>>>>>
4932 18:07:48.349954 [ANA_INIT] MIDPI <<<<<<<<
4933 18:07:48.352383 [ANA_INIT] DLL >>>>>>>>
4934 18:07:48.355931 [ANA_INIT] flow end
4935 18:07:48.359453 ============ LP4 DIFF to SE enter ============
4936 18:07:48.362591 ============ LP4 DIFF to SE exit ============
4937 18:07:48.365866 [ANA_INIT] <<<<<<<<<<<<<
4938 18:07:48.369689 [Flow] Enable top DCM control >>>>>
4939 18:07:48.372883 [Flow] Enable top DCM control <<<<<
4940 18:07:48.375966 Enable DLL master slave shuffle
4941 18:07:48.379584 ==============================================================
4942 18:07:48.382620 Gating Mode config
4943 18:07:48.389381 ==============================================================
4944 18:07:48.389805 Config description:
4945 18:07:48.399203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 18:07:48.405760 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 18:07:48.409135 SELPH_MODE 0: By rank 1: By Phase
4948 18:07:48.415621 ==============================================================
4949 18:07:48.418759 GAT_TRACK_EN = 1
4950 18:07:48.422527 RX_GATING_MODE = 2
4951 18:07:48.425853 RX_GATING_TRACK_MODE = 2
4952 18:07:48.429309 SELPH_MODE = 1
4953 18:07:48.432685 PICG_EARLY_EN = 1
4954 18:07:48.435826 VALID_LAT_VALUE = 1
4955 18:07:48.438948 ==============================================================
4956 18:07:48.442462 Enter into Gating configuration >>>>
4957 18:07:48.445670 Exit from Gating configuration <<<<
4958 18:07:48.449050 Enter into DVFS_PRE_config >>>>>
4959 18:07:48.458659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 18:07:48.461977 Exit from DVFS_PRE_config <<<<<
4961 18:07:48.465510 Enter into PICG configuration >>>>
4962 18:07:48.468954 Exit from PICG configuration <<<<
4963 18:07:48.471806 [RX_INPUT] configuration >>>>>
4964 18:07:48.475071 [RX_INPUT] configuration <<<<<
4965 18:07:48.482077 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 18:07:48.485176 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 18:07:48.491929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 18:07:48.498015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 18:07:48.504894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 18:07:48.511291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 18:07:48.514742 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 18:07:48.518165 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 18:07:48.521429 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 18:07:48.527829 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 18:07:48.531462 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 18:07:48.535103 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 18:07:48.538266 ===================================
4978 18:07:48.541366 LPDDR4 DRAM CONFIGURATION
4979 18:07:48.544310 ===================================
4980 18:07:48.544446 EX_ROW_EN[0] = 0x0
4981 18:07:48.548245 EX_ROW_EN[1] = 0x0
4982 18:07:48.551484 LP4Y_EN = 0x0
4983 18:07:48.551565 WORK_FSP = 0x0
4984 18:07:48.554942 WL = 0x3
4985 18:07:48.555024 RL = 0x3
4986 18:07:48.557670 BL = 0x2
4987 18:07:48.557753 RPST = 0x0
4988 18:07:48.561414 RD_PRE = 0x0
4989 18:07:48.561496 WR_PRE = 0x1
4990 18:07:48.564748 WR_PST = 0x0
4991 18:07:48.564829 DBI_WR = 0x0
4992 18:07:48.567574 DBI_RD = 0x0
4993 18:07:48.567656 OTF = 0x1
4994 18:07:48.570957 ===================================
4995 18:07:48.574439 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 18:07:48.580916 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 18:07:48.584171 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 18:07:48.587635 ===================================
4999 18:07:48.590908 LPDDR4 DRAM CONFIGURATION
5000 18:07:48.594058 ===================================
5001 18:07:48.594141 EX_ROW_EN[0] = 0x10
5002 18:07:48.597836 EX_ROW_EN[1] = 0x0
5003 18:07:48.600889 LP4Y_EN = 0x0
5004 18:07:48.600971 WORK_FSP = 0x0
5005 18:07:48.604633 WL = 0x3
5006 18:07:48.604717 RL = 0x3
5007 18:07:48.607241 BL = 0x2
5008 18:07:48.607323 RPST = 0x0
5009 18:07:48.610645 RD_PRE = 0x0
5010 18:07:48.610728 WR_PRE = 0x1
5011 18:07:48.614241 WR_PST = 0x0
5012 18:07:48.614324 DBI_WR = 0x0
5013 18:07:48.616962 DBI_RD = 0x0
5014 18:07:48.617043 OTF = 0x1
5015 18:07:48.620768 ===================================
5016 18:07:48.627269 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 18:07:48.631757 nWR fixed to 30
5018 18:07:48.634919 [ModeRegInit_LP4] CH0 RK0
5019 18:07:48.635002 [ModeRegInit_LP4] CH0 RK1
5020 18:07:48.638193 [ModeRegInit_LP4] CH1 RK0
5021 18:07:48.641683 [ModeRegInit_LP4] CH1 RK1
5022 18:07:48.641766 match AC timing 9
5023 18:07:48.648487 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 18:07:48.651673 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 18:07:48.654997 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 18:07:48.661591 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 18:07:48.665365 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 18:07:48.665474 ==
5029 18:07:48.667957 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 18:07:48.671490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 18:07:48.671576 ==
5032 18:07:48.678371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 18:07:48.684702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5034 18:07:48.688167 [CA 0] Center 37 (7~68) winsize 62
5035 18:07:48.691118 [CA 1] Center 37 (7~68) winsize 62
5036 18:07:48.695164 [CA 2] Center 34 (4~65) winsize 62
5037 18:07:48.697821 [CA 3] Center 34 (3~65) winsize 63
5038 18:07:48.701253 [CA 4] Center 33 (3~64) winsize 62
5039 18:07:48.704640 [CA 5] Center 32 (2~62) winsize 61
5040 18:07:48.704722
5041 18:07:48.708014 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5042 18:07:48.708095
5043 18:07:48.711123 [CATrainingPosCal] consider 1 rank data
5044 18:07:48.714487 u2DelayCellTimex100 = 270/100 ps
5045 18:07:48.717663 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 18:07:48.721263 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 18:07:48.724454 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5048 18:07:48.727927 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5049 18:07:48.731225 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5050 18:07:48.737448 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5051 18:07:48.737552
5052 18:07:48.741399 CA PerBit enable=1, Macro0, CA PI delay=32
5053 18:07:48.741486
5054 18:07:48.744496 [CBTSetCACLKResult] CA Dly = 32
5055 18:07:48.744582 CS Dly: 5 (0~36)
5056 18:07:48.744668 ==
5057 18:07:48.747788 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 18:07:48.751347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 18:07:48.754134 ==
5060 18:07:48.757611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 18:07:48.763941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5062 18:07:48.767308 [CA 0] Center 37 (7~68) winsize 62
5063 18:07:48.770699 [CA 1] Center 37 (7~68) winsize 62
5064 18:07:48.774321 [CA 2] Center 34 (4~65) winsize 62
5065 18:07:48.777241 [CA 3] Center 34 (3~65) winsize 63
5066 18:07:48.780856 [CA 4] Center 32 (2~63) winsize 62
5067 18:07:48.784627 [CA 5] Center 32 (2~62) winsize 61
5068 18:07:48.784713
5069 18:07:48.787384 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5070 18:07:48.787469
5071 18:07:48.790694 [CATrainingPosCal] consider 2 rank data
5072 18:07:48.794290 u2DelayCellTimex100 = 270/100 ps
5073 18:07:48.798067 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 18:07:48.801669 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 18:07:48.804302 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 18:07:48.808230 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5077 18:07:48.815096 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 18:07:48.818272 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5079 18:07:48.818839
5080 18:07:48.820950 CA PerBit enable=1, Macro0, CA PI delay=32
5081 18:07:48.821387
5082 18:07:48.824283 [CBTSetCACLKResult] CA Dly = 32
5083 18:07:48.824772 CS Dly: 6 (0~38)
5084 18:07:48.825209
5085 18:07:48.827574 ----->DramcWriteLeveling(PI) begin...
5086 18:07:48.828091 ==
5087 18:07:48.831019 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 18:07:48.837692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 18:07:48.838216 ==
5090 18:07:48.840942 Write leveling (Byte 0): 30 => 30
5091 18:07:48.845024 Write leveling (Byte 1): 30 => 30
5092 18:07:48.845581 DramcWriteLeveling(PI) end<-----
5093 18:07:48.846047
5094 18:07:48.847641 ==
5095 18:07:48.851729 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 18:07:48.854323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 18:07:48.854750 ==
5098 18:07:48.858221 [Gating] SW mode calibration
5099 18:07:48.864294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 18:07:48.867735 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 18:07:48.874538 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5102 18:07:48.878265 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 18:07:48.881172 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 18:07:48.887485 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 18:07:48.890973 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 18:07:48.894361 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 18:07:48.900609 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
5108 18:07:48.903433 0 14 28 | B1->B0 | 3333 2929 | 1 0 | (1 0) (1 1)
5109 18:07:48.906977 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5110 18:07:48.913304 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 18:07:48.916829 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 18:07:48.920224 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 18:07:48.926657 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 18:07:48.930006 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 18:07:48.933369 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5116 18:07:48.940216 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
5117 18:07:48.943649 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5118 18:07:48.946815 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 18:07:48.953825 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 18:07:48.957138 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 18:07:48.959841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 18:07:48.966598 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 18:07:48.970482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 18:07:48.973646 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 18:07:48.980451 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5126 18:07:48.983645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 18:07:48.986808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 18:07:48.993783 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 18:07:48.996581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 18:07:49.000210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 18:07:49.003590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 18:07:49.010338 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 18:07:49.013729 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 18:07:49.016858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 18:07:49.023088 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 18:07:49.026635 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 18:07:49.030394 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 18:07:49.036760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 18:07:49.040078 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 18:07:49.043461 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5141 18:07:49.049639 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 18:07:49.052878 Total UI for P1: 0, mck2ui 16
5143 18:07:49.056810 best dqsien dly found for B0: ( 1, 2, 26)
5144 18:07:49.059904 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 18:07:49.063315 Total UI for P1: 0, mck2ui 16
5146 18:07:49.066443 best dqsien dly found for B1: ( 1, 2, 30)
5147 18:07:49.069699 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 18:07:49.072860 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 18:07:49.073275
5150 18:07:49.076413 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 18:07:49.079564 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 18:07:49.082855 [Gating] SW calibration Done
5153 18:07:49.083273 ==
5154 18:07:49.086218 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 18:07:49.093073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 18:07:49.093494 ==
5157 18:07:49.093828 RX Vref Scan: 0
5158 18:07:49.094138
5159 18:07:49.096329 RX Vref 0 -> 0, step: 1
5160 18:07:49.096786
5161 18:07:49.099494 RX Delay -80 -> 252, step: 8
5162 18:07:49.102616 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 18:07:49.105943 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 18:07:49.109470 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 18:07:49.112904 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 18:07:49.119258 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 18:07:49.122728 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5168 18:07:49.125586 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5169 18:07:49.129030 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5170 18:07:49.132409 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5171 18:07:49.139026 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5172 18:07:49.142753 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5173 18:07:49.145972 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5174 18:07:49.149473 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5175 18:07:49.152618 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5176 18:07:49.156148 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5177 18:07:49.162733 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5178 18:07:49.163232 ==
5179 18:07:49.166142 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 18:07:49.169406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 18:07:49.169828 ==
5182 18:07:49.170163 DQS Delay:
5183 18:07:49.172443 DQS0 = 0, DQS1 = 0
5184 18:07:49.172862 DQM Delay:
5185 18:07:49.175790 DQM0 = 104, DQM1 = 95
5186 18:07:49.176308 DQ Delay:
5187 18:07:49.178955 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 18:07:49.182651 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5189 18:07:49.185724 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5190 18:07:49.188870 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5191 18:07:49.189285
5192 18:07:49.189613
5193 18:07:49.189918 ==
5194 18:07:49.192924 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 18:07:49.199387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 18:07:49.199864 ==
5197 18:07:49.200201
5198 18:07:49.200561
5199 18:07:49.200863 TX Vref Scan disable
5200 18:07:49.202802 == TX Byte 0 ==
5201 18:07:49.206579 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5202 18:07:49.212663 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5203 18:07:49.213085 == TX Byte 1 ==
5204 18:07:49.215676 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 18:07:49.222529 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 18:07:49.222951 ==
5207 18:07:49.226349 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 18:07:49.228885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 18:07:49.229304 ==
5210 18:07:49.229638
5211 18:07:49.229941
5212 18:07:49.232427 TX Vref Scan disable
5213 18:07:49.232846 == TX Byte 0 ==
5214 18:07:49.252806 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5215 18:07:49.253262 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5216 18:07:49.253755 == TX Byte 1 ==
5217 18:07:49.254082 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 18:07:49.254389 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 18:07:49.254688
5220 18:07:49.254972 [DATLAT]
5221 18:07:49.255588 Freq=933, CH0 RK0
5222 18:07:49.255902
5223 18:07:49.256193 DATLAT Default: 0xd
5224 18:07:49.259024 0, 0xFFFF, sum = 0
5225 18:07:49.259452 1, 0xFFFF, sum = 0
5226 18:07:49.262721 2, 0xFFFF, sum = 0
5227 18:07:49.265988 3, 0xFFFF, sum = 0
5228 18:07:49.266410 4, 0xFFFF, sum = 0
5229 18:07:49.269040 5, 0xFFFF, sum = 0
5230 18:07:49.269464 6, 0xFFFF, sum = 0
5231 18:07:49.272516 7, 0xFFFF, sum = 0
5232 18:07:49.272938 8, 0xFFFF, sum = 0
5233 18:07:49.275978 9, 0xFFFF, sum = 0
5234 18:07:49.276538 10, 0x0, sum = 1
5235 18:07:49.278615 11, 0x0, sum = 2
5236 18:07:49.279039 12, 0x0, sum = 3
5237 18:07:49.279376 13, 0x0, sum = 4
5238 18:07:49.282429 best_step = 11
5239 18:07:49.282884
5240 18:07:49.283217 ==
5241 18:07:49.285606 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 18:07:49.288642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 18:07:49.289063 ==
5244 18:07:49.292472 RX Vref Scan: 1
5245 18:07:49.292888
5246 18:07:49.293219 RX Vref 0 -> 0, step: 1
5247 18:07:49.295557
5248 18:07:49.295986 RX Delay -53 -> 252, step: 4
5249 18:07:49.296317
5250 18:07:49.299205 Set Vref, RX VrefLevel [Byte0]: 55
5251 18:07:49.302242 [Byte1]: 43
5252 18:07:49.306890
5253 18:07:49.307362 Final RX Vref Byte 0 = 55 to rank0
5254 18:07:49.309808 Final RX Vref Byte 1 = 43 to rank0
5255 18:07:49.313172 Final RX Vref Byte 0 = 55 to rank1
5256 18:07:49.316558 Final RX Vref Byte 1 = 43 to rank1==
5257 18:07:49.319798 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 18:07:49.326378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 18:07:49.326793 ==
5260 18:07:49.327120 DQS Delay:
5261 18:07:49.327653 DQS0 = 0, DQS1 = 0
5262 18:07:49.330116 DQM Delay:
5263 18:07:49.330655 DQM0 = 104, DQM1 = 95
5264 18:07:49.333321 DQ Delay:
5265 18:07:49.336399 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5266 18:07:49.339746 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5267 18:07:49.343215 DQ8 =86, DQ9 =86, DQ10 =98, DQ11 =90
5268 18:07:49.345960 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =100
5269 18:07:49.346376
5270 18:07:49.346703
5271 18:07:49.353306 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5272 18:07:49.356168 CH0 RK0: MR19=505, MR18=2F27
5273 18:07:49.363710 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5274 18:07:49.364229
5275 18:07:49.366291 ----->DramcWriteLeveling(PI) begin...
5276 18:07:49.366827 ==
5277 18:07:49.369672 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 18:07:49.373203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 18:07:49.375914 ==
5280 18:07:49.376326 Write leveling (Byte 0): 34 => 34
5281 18:07:49.379868 Write leveling (Byte 1): 30 => 30
5282 18:07:49.383402 DramcWriteLeveling(PI) end<-----
5283 18:07:49.383932
5284 18:07:49.384473 ==
5285 18:07:49.386421 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 18:07:49.392839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 18:07:49.393255 ==
5288 18:07:49.393580 [Gating] SW mode calibration
5289 18:07:49.402995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 18:07:49.406341 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 18:07:49.409817 0 14 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
5292 18:07:49.416287 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 18:07:49.419471 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 18:07:49.422955 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 18:07:49.429841 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 18:07:49.432503 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 18:07:49.435829 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 18:07:49.443224 0 14 28 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
5299 18:07:49.445757 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5300 18:07:49.449041 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 18:07:49.456082 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 18:07:49.459536 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 18:07:49.462814 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 18:07:49.469329 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 18:07:49.472716 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 18:07:49.475889 0 15 28 | B1->B0 | 3434 3535 | 0 0 | (0 0) (1 1)
5307 18:07:49.482721 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5308 18:07:49.486042 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 18:07:49.488705 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 18:07:49.495785 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 18:07:49.498841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 18:07:49.502250 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 18:07:49.509142 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 18:07:49.512643 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5315 18:07:49.515932 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 18:07:49.521992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 18:07:49.525638 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 18:07:49.529028 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 18:07:49.532470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 18:07:49.538808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 18:07:49.542169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 18:07:49.545488 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 18:07:49.552053 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 18:07:49.555431 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 18:07:49.558672 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 18:07:49.565793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 18:07:49.568807 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 18:07:49.572008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 18:07:49.578541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 18:07:49.582103 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 18:07:49.585379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 18:07:49.588890 Total UI for P1: 0, mck2ui 16
5333 18:07:49.591830 best dqsien dly found for B0: ( 1, 2, 28)
5334 18:07:49.595342 Total UI for P1: 0, mck2ui 16
5335 18:07:49.598917 best dqsien dly found for B1: ( 1, 2, 28)
5336 18:07:49.601752 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 18:07:49.605070 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 18:07:49.605324
5339 18:07:49.611656 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 18:07:49.615258 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 18:07:49.618712 [Gating] SW calibration Done
5342 18:07:49.618839 ==
5343 18:07:49.621537 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 18:07:49.624995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 18:07:49.625107 ==
5346 18:07:49.625196 RX Vref Scan: 0
5347 18:07:49.625279
5348 18:07:49.628105 RX Vref 0 -> 0, step: 1
5349 18:07:49.628203
5350 18:07:49.631281 RX Delay -80 -> 252, step: 8
5351 18:07:49.634737 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 18:07:49.637870 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5353 18:07:49.644607 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5354 18:07:49.648136 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 18:07:49.651379 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 18:07:49.654606 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5357 18:07:49.658176 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5358 18:07:49.661224 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 18:07:49.668069 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 18:07:49.671187 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5361 18:07:49.674499 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5362 18:07:49.677579 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5363 18:07:49.681040 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5364 18:07:49.684596 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5365 18:07:49.691078 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5366 18:07:49.694328 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 18:07:49.694408 ==
5368 18:07:49.697609 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 18:07:49.700857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 18:07:49.700939 ==
5371 18:07:49.704884 DQS Delay:
5372 18:07:49.704964 DQS0 = 0, DQS1 = 0
5373 18:07:49.705028 DQM Delay:
5374 18:07:49.707549 DQM0 = 105, DQM1 = 93
5375 18:07:49.707629 DQ Delay:
5376 18:07:49.710930 DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =99
5377 18:07:49.714233 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5378 18:07:49.717583 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5379 18:07:49.720980 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5380 18:07:49.721061
5381 18:07:49.721124
5382 18:07:49.721182 ==
5383 18:07:49.724504 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 18:07:49.731278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 18:07:49.731359 ==
5386 18:07:49.731424
5387 18:07:49.731483
5388 18:07:49.731539 TX Vref Scan disable
5389 18:07:49.734825 == TX Byte 0 ==
5390 18:07:49.738290 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5391 18:07:49.744587 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5392 18:07:49.744667 == TX Byte 1 ==
5393 18:07:49.748242 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5394 18:07:49.754615 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5395 18:07:49.754696 ==
5396 18:07:49.757893 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 18:07:49.761137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 18:07:49.761218 ==
5399 18:07:49.761282
5400 18:07:49.761340
5401 18:07:49.764782 TX Vref Scan disable
5402 18:07:49.764863 == TX Byte 0 ==
5403 18:07:49.771452 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5404 18:07:49.774631 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5405 18:07:49.774712 == TX Byte 1 ==
5406 18:07:49.781164 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5407 18:07:49.784715 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5408 18:07:49.784826
5409 18:07:49.784919 [DATLAT]
5410 18:07:49.787797 Freq=933, CH0 RK1
5411 18:07:49.787877
5412 18:07:49.787940 DATLAT Default: 0xb
5413 18:07:49.790961 0, 0xFFFF, sum = 0
5414 18:07:49.791043 1, 0xFFFF, sum = 0
5415 18:07:49.794373 2, 0xFFFF, sum = 0
5416 18:07:49.797988 3, 0xFFFF, sum = 0
5417 18:07:49.798070 4, 0xFFFF, sum = 0
5418 18:07:49.801830 5, 0xFFFF, sum = 0
5419 18:07:49.801992 6, 0xFFFF, sum = 0
5420 18:07:49.804636 7, 0xFFFF, sum = 0
5421 18:07:49.804748 8, 0xFFFF, sum = 0
5422 18:07:49.807720 9, 0xFFFF, sum = 0
5423 18:07:49.807802 10, 0x0, sum = 1
5424 18:07:49.810976 11, 0x0, sum = 2
5425 18:07:49.811058 12, 0x0, sum = 3
5426 18:07:49.811123 13, 0x0, sum = 4
5427 18:07:49.814286 best_step = 11
5428 18:07:49.814373
5429 18:07:49.814455 ==
5430 18:07:49.817718 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 18:07:49.821039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 18:07:49.821150 ==
5433 18:07:49.824188 RX Vref Scan: 0
5434 18:07:49.824320
5435 18:07:49.827591 RX Vref 0 -> 0, step: 1
5436 18:07:49.827690
5437 18:07:49.827769 RX Delay -53 -> 252, step: 4
5438 18:07:49.835149 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5439 18:07:49.838767 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5440 18:07:49.841587 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5441 18:07:49.845119 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5442 18:07:49.848570 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5443 18:07:49.855008 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5444 18:07:49.858509 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5445 18:07:49.862076 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5446 18:07:49.865433 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164
5447 18:07:49.869156 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5448 18:07:49.871797 iDelay=199, Bit 10, Center 92 (11 ~ 174) 164
5449 18:07:49.878811 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5450 18:07:49.882331 iDelay=199, Bit 12, Center 98 (19 ~ 178) 160
5451 18:07:49.885688 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5452 18:07:49.888520 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5453 18:07:49.891972 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5454 18:07:49.895414 ==
5455 18:07:49.899084 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 18:07:49.902077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 18:07:49.902519 ==
5458 18:07:49.902961 DQS Delay:
5459 18:07:49.905079 DQS0 = 0, DQS1 = 0
5460 18:07:49.905513 DQM Delay:
5461 18:07:49.908849 DQM0 = 105, DQM1 = 93
5462 18:07:49.909285 DQ Delay:
5463 18:07:49.911816 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5464 18:07:49.915084 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5465 18:07:49.918224 DQ8 =84, DQ9 =82, DQ10 =92, DQ11 =86
5466 18:07:49.921857 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =100
5467 18:07:49.922290
5468 18:07:49.922726
5469 18:07:49.932006 [DQSOSCAuto] RK1, (LSB)MR18= 0x26fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5470 18:07:49.932484 CH0 RK1: MR19=504, MR18=26FE
5471 18:07:49.938171 CH0_RK1: MR19=0x504, MR18=0x26FE, DQSOSC=409, MR23=63, INC=64, DEC=43
5472 18:07:49.941999 [RxdqsGatingPostProcess] freq 933
5473 18:07:49.948337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 18:07:49.951727 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 18:07:49.955230 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 18:07:49.957999 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 18:07:49.961586 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 18:07:49.965053 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 18:07:49.968030 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 18:07:49.968664 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 18:07:49.971412 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 18:07:49.974953 Pre-setting of DQS Precalculation
5483 18:07:49.981623 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 18:07:49.982042 ==
5485 18:07:49.984963 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 18:07:49.987904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 18:07:49.988419 ==
5488 18:07:49.994886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 18:07:50.001297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5490 18:07:50.004635 [CA 0] Center 36 (6~67) winsize 62
5491 18:07:50.008168 [CA 1] Center 37 (6~68) winsize 63
5492 18:07:50.011190 [CA 2] Center 34 (4~65) winsize 62
5493 18:07:50.014508 [CA 3] Center 34 (4~64) winsize 61
5494 18:07:50.017981 [CA 4] Center 34 (4~65) winsize 62
5495 18:07:50.020832 [CA 5] Center 33 (3~64) winsize 62
5496 18:07:50.021279
5497 18:07:50.024227 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5498 18:07:50.024697
5499 18:07:50.027290 [CATrainingPosCal] consider 1 rank data
5500 18:07:50.030782 u2DelayCellTimex100 = 270/100 ps
5501 18:07:50.034052 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 18:07:50.037648 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5503 18:07:50.040707 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 18:07:50.044375 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5505 18:07:50.047419 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5506 18:07:50.050660 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 18:07:50.051075
5508 18:07:50.057477 CA PerBit enable=1, Macro0, CA PI delay=33
5509 18:07:50.057915
5510 18:07:50.058432 [CBTSetCACLKResult] CA Dly = 33
5511 18:07:50.061443 CS Dly: 7 (0~38)
5512 18:07:50.061991 ==
5513 18:07:50.064121 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 18:07:50.067630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 18:07:50.068188 ==
5516 18:07:50.074076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 18:07:50.080724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5518 18:07:50.084103 [CA 0] Center 36 (6~67) winsize 62
5519 18:07:50.087499 [CA 1] Center 37 (7~68) winsize 62
5520 18:07:50.090677 [CA 2] Center 35 (5~65) winsize 61
5521 18:07:50.093773 [CA 3] Center 34 (4~65) winsize 62
5522 18:07:50.097605 [CA 4] Center 34 (4~65) winsize 62
5523 18:07:50.100312 [CA 5] Center 33 (3~64) winsize 62
5524 18:07:50.100587
5525 18:07:50.103976 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5526 18:07:50.104203
5527 18:07:50.107584 [CATrainingPosCal] consider 2 rank data
5528 18:07:50.110934 u2DelayCellTimex100 = 270/100 ps
5529 18:07:50.113737 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 18:07:50.117152 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5531 18:07:50.120683 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5532 18:07:50.124078 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 18:07:50.126975 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 18:07:50.133992 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 18:07:50.134353
5536 18:07:50.137173 CA PerBit enable=1, Macro0, CA PI delay=33
5537 18:07:50.137535
5538 18:07:50.140880 [CBTSetCACLKResult] CA Dly = 33
5539 18:07:50.141334 CS Dly: 7 (0~39)
5540 18:07:50.141679
5541 18:07:50.143578 ----->DramcWriteLeveling(PI) begin...
5542 18:07:50.144004 ==
5543 18:07:50.147260 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 18:07:50.150506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 18:07:50.153870 ==
5546 18:07:50.157343 Write leveling (Byte 0): 29 => 29
5547 18:07:50.157765 Write leveling (Byte 1): 29 => 29
5548 18:07:50.160541 DramcWriteLeveling(PI) end<-----
5549 18:07:50.160963
5550 18:07:50.161292 ==
5551 18:07:50.163895 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 18:07:50.170061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 18:07:50.170484 ==
5554 18:07:50.173709 [Gating] SW mode calibration
5555 18:07:50.180182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 18:07:50.183489 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 18:07:50.189844 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 18:07:50.193339 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 18:07:50.196706 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 18:07:50.203287 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 18:07:50.207115 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 18:07:50.210253 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5563 18:07:50.216562 0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5564 18:07:50.220233 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5565 18:07:50.223642 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 18:07:50.230020 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 18:07:50.233522 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 18:07:50.236714 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 18:07:50.240327 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 18:07:50.246669 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 18:07:50.250116 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5572 18:07:50.253283 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5573 18:07:50.259938 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 18:07:50.263208 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 18:07:50.266610 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 18:07:50.273315 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 18:07:50.276738 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 18:07:50.280208 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 18:07:50.286165 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 18:07:50.289790 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5581 18:07:50.292997 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 18:07:50.299446 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 18:07:50.302828 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 18:07:50.305914 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 18:07:50.312653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 18:07:50.316146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 18:07:50.319539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 18:07:50.325996 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 18:07:50.329491 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 18:07:50.332873 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 18:07:50.339714 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 18:07:50.343095 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 18:07:50.345822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 18:07:50.352876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 18:07:50.356517 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 18:07:50.359358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 18:07:50.366288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 18:07:50.366710 Total UI for P1: 0, mck2ui 16
5599 18:07:50.369554 best dqsien dly found for B0: ( 1, 2, 26)
5600 18:07:50.372918 Total UI for P1: 0, mck2ui 16
5601 18:07:50.376142 best dqsien dly found for B1: ( 1, 2, 26)
5602 18:07:50.382816 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5603 18:07:50.385556 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5604 18:07:50.385975
5605 18:07:50.388814 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5606 18:07:50.392231 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 18:07:50.395737 [Gating] SW calibration Done
5608 18:07:50.396154 ==
5609 18:07:50.399250 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 18:07:50.402096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 18:07:50.402517 ==
5612 18:07:50.405633 RX Vref Scan: 0
5613 18:07:50.406051
5614 18:07:50.406381 RX Vref 0 -> 0, step: 1
5615 18:07:50.406691
5616 18:07:50.409267 RX Delay -80 -> 252, step: 8
5617 18:07:50.412012 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5618 18:07:50.418957 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 18:07:50.422234 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 18:07:50.425626 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 18:07:50.428825 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 18:07:50.432478 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5623 18:07:50.435336 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 18:07:50.441995 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5625 18:07:50.445603 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5626 18:07:50.448773 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5627 18:07:50.451569 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 18:07:50.455277 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 18:07:50.458664 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5630 18:07:50.465013 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5631 18:07:50.468458 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5632 18:07:50.471995 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5633 18:07:50.472459 ==
5634 18:07:50.474991 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 18:07:50.478332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 18:07:50.481587 ==
5637 18:07:50.482006 DQS Delay:
5638 18:07:50.482341 DQS0 = 0, DQS1 = 0
5639 18:07:50.485089 DQM Delay:
5640 18:07:50.485660 DQM0 = 102, DQM1 = 98
5641 18:07:50.488159 DQ Delay:
5642 18:07:50.491597 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5643 18:07:50.494869 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5644 18:07:50.498332 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5645 18:07:50.501565 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =103
5646 18:07:50.501987
5647 18:07:50.502321
5648 18:07:50.502628 ==
5649 18:07:50.504701 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 18:07:50.507990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 18:07:50.508501 ==
5652 18:07:50.508854
5653 18:07:50.509165
5654 18:07:50.511472 TX Vref Scan disable
5655 18:07:50.515036 == TX Byte 0 ==
5656 18:07:50.517836 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5657 18:07:50.521369 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5658 18:07:50.524792 == TX Byte 1 ==
5659 18:07:50.528231 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 18:07:50.531771 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 18:07:50.532193 ==
5662 18:07:50.534789 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 18:07:50.537882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 18:07:50.538304 ==
5665 18:07:50.541287
5666 18:07:50.541723
5667 18:07:50.542060 TX Vref Scan disable
5668 18:07:50.544807 == TX Byte 0 ==
5669 18:07:50.548293 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5670 18:07:50.551385 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5671 18:07:50.554585 == TX Byte 1 ==
5672 18:07:50.557933 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 18:07:50.564691 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 18:07:50.565151
5675 18:07:50.565487 [DATLAT]
5676 18:07:50.565802 Freq=933, CH1 RK0
5677 18:07:50.566104
5678 18:07:50.568009 DATLAT Default: 0xd
5679 18:07:50.568477 0, 0xFFFF, sum = 0
5680 18:07:50.571283 1, 0xFFFF, sum = 0
5681 18:07:50.571712 2, 0xFFFF, sum = 0
5682 18:07:50.574615 3, 0xFFFF, sum = 0
5683 18:07:50.578086 4, 0xFFFF, sum = 0
5684 18:07:50.578513 5, 0xFFFF, sum = 0
5685 18:07:50.581350 6, 0xFFFF, sum = 0
5686 18:07:50.581777 7, 0xFFFF, sum = 0
5687 18:07:50.584774 8, 0xFFFF, sum = 0
5688 18:07:50.585197 9, 0xFFFF, sum = 0
5689 18:07:50.588105 10, 0x0, sum = 1
5690 18:07:50.588580 11, 0x0, sum = 2
5691 18:07:50.591409 12, 0x0, sum = 3
5692 18:07:50.591850 13, 0x0, sum = 4
5693 18:07:50.592192 best_step = 11
5694 18:07:50.592661
5695 18:07:50.594679 ==
5696 18:07:50.597763 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 18:07:50.600792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 18:07:50.601213 ==
5699 18:07:50.601560 RX Vref Scan: 1
5700 18:07:50.601873
5701 18:07:50.604540 RX Vref 0 -> 0, step: 1
5702 18:07:50.604958
5703 18:07:50.607464 RX Delay -45 -> 252, step: 4
5704 18:07:50.607882
5705 18:07:50.611122 Set Vref, RX VrefLevel [Byte0]: 53
5706 18:07:50.614595 [Byte1]: 47
5707 18:07:50.615017
5708 18:07:50.617970 Final RX Vref Byte 0 = 53 to rank0
5709 18:07:50.620771 Final RX Vref Byte 1 = 47 to rank0
5710 18:07:50.624452 Final RX Vref Byte 0 = 53 to rank1
5711 18:07:50.627240 Final RX Vref Byte 1 = 47 to rank1==
5712 18:07:50.630743 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 18:07:50.634281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 18:07:50.634901 ==
5715 18:07:50.637126 DQS Delay:
5716 18:07:50.637676 DQS0 = 0, DQS1 = 0
5717 18:07:50.641283 DQM Delay:
5718 18:07:50.641819 DQM0 = 102, DQM1 = 97
5719 18:07:50.643974 DQ Delay:
5720 18:07:50.644586 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5721 18:07:50.650984 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5722 18:07:50.654694 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =90
5723 18:07:50.657352 DQ12 =102, DQ13 =104, DQ14 =102, DQ15 =106
5724 18:07:50.657788
5725 18:07:50.658171
5726 18:07:50.664405 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5727 18:07:50.667817 CH1 RK0: MR19=505, MR18=182F
5728 18:07:50.674337 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5729 18:07:50.674803
5730 18:07:50.677156 ----->DramcWriteLeveling(PI) begin...
5731 18:07:50.677617 ==
5732 18:07:50.680851 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 18:07:50.684529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 18:07:50.684987 ==
5735 18:07:50.687390 Write leveling (Byte 0): 29 => 29
5736 18:07:50.690967 Write leveling (Byte 1): 27 => 27
5737 18:07:50.694337 DramcWriteLeveling(PI) end<-----
5738 18:07:50.694756
5739 18:07:50.695086 ==
5740 18:07:50.697319 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 18:07:50.700991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 18:07:50.701413 ==
5743 18:07:50.704394 [Gating] SW mode calibration
5744 18:07:50.710629 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 18:07:50.717128 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 18:07:50.720840 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5747 18:07:50.727008 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 18:07:50.730516 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 18:07:50.734139 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 18:07:50.740315 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 18:07:50.743782 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 18:07:50.747290 0 14 24 | B1->B0 | 2b2b 3333 | 1 1 | (1 1) (1 1)
5753 18:07:50.753742 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5754 18:07:50.756971 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 18:07:50.760480 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 18:07:50.766778 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 18:07:50.770222 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 18:07:50.773803 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 18:07:50.780100 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 18:07:50.783359 0 15 24 | B1->B0 | 3333 2525 | 0 0 | (0 0) (0 0)
5761 18:07:50.786890 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5762 18:07:50.793640 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 18:07:50.797209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 18:07:50.799919 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 18:07:50.803404 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 18:07:50.810255 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 18:07:50.813237 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 18:07:50.816620 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5769 18:07:50.823304 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 18:07:50.826788 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 18:07:50.829668 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 18:07:50.836565 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 18:07:50.839920 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 18:07:50.843402 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 18:07:50.849993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 18:07:50.852960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 18:07:50.856154 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 18:07:50.862668 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 18:07:50.866084 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 18:07:50.869605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 18:07:50.876682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 18:07:50.880088 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 18:07:50.882870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 18:07:50.889843 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 18:07:50.892673 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 18:07:50.896704 Total UI for P1: 0, mck2ui 16
5787 18:07:50.899792 best dqsien dly found for B0: ( 1, 2, 26)
5788 18:07:50.903259 Total UI for P1: 0, mck2ui 16
5789 18:07:50.906681 best dqsien dly found for B1: ( 1, 2, 26)
5790 18:07:50.909530 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5791 18:07:50.913052 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5792 18:07:50.913505
5793 18:07:50.916701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5794 18:07:50.919897 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 18:07:50.922758 [Gating] SW calibration Done
5796 18:07:50.923213 ==
5797 18:07:50.926215 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 18:07:50.929574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 18:07:50.932745 ==
5800 18:07:50.933568 RX Vref Scan: 0
5801 18:07:50.933993
5802 18:07:50.936297 RX Vref 0 -> 0, step: 1
5803 18:07:50.936769
5804 18:07:50.937202 RX Delay -80 -> 252, step: 8
5805 18:07:50.943480 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5806 18:07:50.946591 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5807 18:07:50.949756 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5808 18:07:50.952943 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5809 18:07:50.956237 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5810 18:07:50.959557 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5811 18:07:50.966062 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5812 18:07:50.969461 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5813 18:07:50.973139 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5814 18:07:50.976156 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5815 18:07:50.979624 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5816 18:07:50.983382 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5817 18:07:50.989644 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5818 18:07:50.993092 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5819 18:07:50.996786 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5820 18:07:50.999692 iDelay=208, Bit 15, Center 107 (24 ~ 191) 168
5821 18:07:51.000128 ==
5822 18:07:51.002989 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 18:07:51.009702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 18:07:51.010149 ==
5825 18:07:51.010484 DQS Delay:
5826 18:07:51.013146 DQS0 = 0, DQS1 = 0
5827 18:07:51.013590 DQM Delay:
5828 18:07:51.013972 DQM0 = 102, DQM1 = 98
5829 18:07:51.016697 DQ Delay:
5830 18:07:51.019467 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5831 18:07:51.022686 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5832 18:07:51.026129 DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =91
5833 18:07:51.029826 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5834 18:07:51.030305
5835 18:07:51.030675
5836 18:07:51.031057 ==
5837 18:07:51.032583 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 18:07:51.036034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 18:07:51.036572 ==
5840 18:07:51.036978
5841 18:07:51.037351
5842 18:07:51.039405 TX Vref Scan disable
5843 18:07:51.042776 == TX Byte 0 ==
5844 18:07:51.045872 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5845 18:07:51.049590 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5846 18:07:51.052777 == TX Byte 1 ==
5847 18:07:51.055927 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 18:07:51.059203 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 18:07:51.059619 ==
5850 18:07:51.063174 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 18:07:51.069383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 18:07:51.069831 ==
5853 18:07:51.070225
5854 18:07:51.070556
5855 18:07:51.070886 TX Vref Scan disable
5856 18:07:51.073452 == TX Byte 0 ==
5857 18:07:51.076467 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5858 18:07:51.083320 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5859 18:07:51.083871 == TX Byte 1 ==
5860 18:07:51.086769 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5861 18:07:51.093052 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5862 18:07:51.093476
5863 18:07:51.093917 [DATLAT]
5864 18:07:51.094239 Freq=933, CH1 RK1
5865 18:07:51.094557
5866 18:07:51.096856 DATLAT Default: 0xb
5867 18:07:51.097279 0, 0xFFFF, sum = 0
5868 18:07:51.099748 1, 0xFFFF, sum = 0
5869 18:07:51.100202 2, 0xFFFF, sum = 0
5870 18:07:51.103091 3, 0xFFFF, sum = 0
5871 18:07:51.106342 4, 0xFFFF, sum = 0
5872 18:07:51.106973 5, 0xFFFF, sum = 0
5873 18:07:51.109715 6, 0xFFFF, sum = 0
5874 18:07:51.110164 7, 0xFFFF, sum = 0
5875 18:07:51.113132 8, 0xFFFF, sum = 0
5876 18:07:51.113662 9, 0xFFFF, sum = 0
5877 18:07:51.116585 10, 0x0, sum = 1
5878 18:07:51.117142 11, 0x0, sum = 2
5879 18:07:51.120444 12, 0x0, sum = 3
5880 18:07:51.120884 13, 0x0, sum = 4
5881 18:07:51.121339 best_step = 11
5882 18:07:51.121749
5883 18:07:51.122869 ==
5884 18:07:51.126583 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 18:07:51.129693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 18:07:51.130193 ==
5887 18:07:51.130798 RX Vref Scan: 0
5888 18:07:51.131224
5889 18:07:51.132483 RX Vref 0 -> 0, step: 1
5890 18:07:51.132997
5891 18:07:51.136005 RX Delay -45 -> 252, step: 4
5892 18:07:51.139585 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5893 18:07:51.146053 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5894 18:07:51.149414 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5895 18:07:51.152748 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5896 18:07:51.156045 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5897 18:07:51.159634 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5898 18:07:51.166506 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5899 18:07:51.169873 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5900 18:07:51.172885 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5901 18:07:51.176536 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5902 18:07:51.179554 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5903 18:07:51.182951 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5904 18:07:51.189824 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5905 18:07:51.192821 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5906 18:07:51.196226 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5907 18:07:51.199684 iDelay=203, Bit 15, Center 106 (23 ~ 190) 168
5908 18:07:51.200100 ==
5909 18:07:51.202483 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 18:07:51.209276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 18:07:51.209697 ==
5912 18:07:51.210029 DQS Delay:
5913 18:07:51.212460 DQS0 = 0, DQS1 = 0
5914 18:07:51.212878 DQM Delay:
5915 18:07:51.215489 DQM0 = 104, DQM1 = 98
5916 18:07:51.215907 DQ Delay:
5917 18:07:51.219305 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5918 18:07:51.222907 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5919 18:07:51.226429 DQ8 =90, DQ9 =86, DQ10 =98, DQ11 =92
5920 18:07:51.229236 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5921 18:07:51.229653
5922 18:07:51.229982
5923 18:07:51.239235 [DQSOSCAuto] RK1, (LSB)MR18= 0x2cff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5924 18:07:51.239659 CH1 RK1: MR19=504, MR18=2CFF
5925 18:07:51.245504 CH1_RK1: MR19=0x504, MR18=0x2CFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5926 18:07:51.249219 [RxdqsGatingPostProcess] freq 933
5927 18:07:51.255712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 18:07:51.259080 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 18:07:51.262379 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 18:07:51.265813 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 18:07:51.269207 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 18:07:51.269630 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 18:07:51.272260 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 18:07:51.275418 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 18:07:51.278988 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 18:07:51.282214 Pre-setting of DQS Precalculation
5937 18:07:51.288548 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 18:07:51.295374 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 18:07:51.301892 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 18:07:51.302455
5941 18:07:51.302932
5942 18:07:51.305414 [Calibration Summary] 1866 Mbps
5943 18:07:51.305834 CH 0, Rank 0
5944 18:07:51.308935 SW Impedance : PASS
5945 18:07:51.312310 DUTY Scan : NO K
5946 18:07:51.312868 ZQ Calibration : PASS
5947 18:07:51.315205 Jitter Meter : NO K
5948 18:07:51.318599 CBT Training : PASS
5949 18:07:51.319066 Write leveling : PASS
5950 18:07:51.322120 RX DQS gating : PASS
5951 18:07:51.325707 RX DQ/DQS(RDDQC) : PASS
5952 18:07:51.326130 TX DQ/DQS : PASS
5953 18:07:51.328321 RX DATLAT : PASS
5954 18:07:51.332238 RX DQ/DQS(Engine): PASS
5955 18:07:51.332716 TX OE : NO K
5956 18:07:51.333116 All Pass.
5957 18:07:51.335435
5958 18:07:51.335852 CH 0, Rank 1
5959 18:07:51.338355 SW Impedance : PASS
5960 18:07:51.338931 DUTY Scan : NO K
5961 18:07:51.341667 ZQ Calibration : PASS
5962 18:07:51.344813 Jitter Meter : NO K
5963 18:07:51.345376 CBT Training : PASS
5964 18:07:51.348417 Write leveling : PASS
5965 18:07:51.348848 RX DQS gating : PASS
5966 18:07:51.351921 RX DQ/DQS(RDDQC) : PASS
5967 18:07:51.355399 TX DQ/DQS : PASS
5968 18:07:51.356025 RX DATLAT : PASS
5969 18:07:51.358807 RX DQ/DQS(Engine): PASS
5970 18:07:51.361621 TX OE : NO K
5971 18:07:51.362220 All Pass.
5972 18:07:51.362774
5973 18:07:51.363302 CH 1, Rank 0
5974 18:07:51.365283 SW Impedance : PASS
5975 18:07:51.368646 DUTY Scan : NO K
5976 18:07:51.369252 ZQ Calibration : PASS
5977 18:07:51.371490 Jitter Meter : NO K
5978 18:07:51.374817 CBT Training : PASS
5979 18:07:51.375421 Write leveling : PASS
5980 18:07:51.378708 RX DQS gating : PASS
5981 18:07:51.381821 RX DQ/DQS(RDDQC) : PASS
5982 18:07:51.382438 TX DQ/DQS : PASS
5983 18:07:51.384946 RX DATLAT : PASS
5984 18:07:51.388329 RX DQ/DQS(Engine): PASS
5985 18:07:51.388874 TX OE : NO K
5986 18:07:51.389244 All Pass.
5987 18:07:51.391796
5988 18:07:51.392215 CH 1, Rank 1
5989 18:07:51.395164 SW Impedance : PASS
5990 18:07:51.395718 DUTY Scan : NO K
5991 18:07:51.398345 ZQ Calibration : PASS
5992 18:07:51.398947 Jitter Meter : NO K
5993 18:07:51.401639 CBT Training : PASS
5994 18:07:51.405256 Write leveling : PASS
5995 18:07:51.405801 RX DQS gating : PASS
5996 18:07:51.408525 RX DQ/DQS(RDDQC) : PASS
5997 18:07:51.411625 TX DQ/DQS : PASS
5998 18:07:51.412279 RX DATLAT : PASS
5999 18:07:51.414868 RX DQ/DQS(Engine): PASS
6000 18:07:51.418432 TX OE : NO K
6001 18:07:51.418995 All Pass.
6002 18:07:51.419368
6003 18:07:51.421273 DramC Write-DBI off
6004 18:07:51.421694 PER_BANK_REFRESH: Hybrid Mode
6005 18:07:51.424842 TX_TRACKING: ON
6006 18:07:51.431152 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 18:07:51.438154 [FAST_K] Save calibration result to emmc
6008 18:07:51.441780 dramc_set_vcore_voltage set vcore to 650000
6009 18:07:51.442335 Read voltage for 400, 6
6010 18:07:51.444612 Vio18 = 0
6011 18:07:51.445032 Vcore = 650000
6012 18:07:51.445397 Vdram = 0
6013 18:07:51.448129 Vddq = 0
6014 18:07:51.448677 Vmddr = 0
6015 18:07:51.451431 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 18:07:51.458526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 18:07:51.461646 MEM_TYPE=3, freq_sel=20
6018 18:07:51.464680 sv_algorithm_assistance_LP4_800
6019 18:07:51.468217 ============ PULL DRAM RESETB DOWN ============
6020 18:07:51.471310 ========== PULL DRAM RESETB DOWN end =========
6021 18:07:51.474840 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 18:07:51.478295 ===================================
6023 18:07:51.481249 LPDDR4 DRAM CONFIGURATION
6024 18:07:51.484615 ===================================
6025 18:07:51.487679 EX_ROW_EN[0] = 0x0
6026 18:07:51.488258 EX_ROW_EN[1] = 0x0
6027 18:07:51.491505 LP4Y_EN = 0x0
6028 18:07:51.491994 WORK_FSP = 0x0
6029 18:07:51.494704 WL = 0x2
6030 18:07:51.495146 RL = 0x2
6031 18:07:51.497990 BL = 0x2
6032 18:07:51.498464 RPST = 0x0
6033 18:07:51.501355 RD_PRE = 0x0
6034 18:07:51.504784 WR_PRE = 0x1
6035 18:07:51.505255 WR_PST = 0x0
6036 18:07:51.508075 DBI_WR = 0x0
6037 18:07:51.508629 DBI_RD = 0x0
6038 18:07:51.511305 OTF = 0x1
6039 18:07:51.514187 ===================================
6040 18:07:51.517777 ===================================
6041 18:07:51.518209 ANA top config
6042 18:07:51.520924 ===================================
6043 18:07:51.524263 DLL_ASYNC_EN = 0
6044 18:07:51.527551 ALL_SLAVE_EN = 1
6045 18:07:51.528047 NEW_RANK_MODE = 1
6046 18:07:51.531169 DLL_IDLE_MODE = 1
6047 18:07:51.534763 LP45_APHY_COMB_EN = 1
6048 18:07:51.537569 TX_ODT_DIS = 1
6049 18:07:51.537988 NEW_8X_MODE = 1
6050 18:07:51.541071 ===================================
6051 18:07:51.543967 ===================================
6052 18:07:51.547473 data_rate = 800
6053 18:07:51.551003 CKR = 1
6054 18:07:51.553799 DQ_P2S_RATIO = 4
6055 18:07:51.557173 ===================================
6056 18:07:51.560699 CA_P2S_RATIO = 4
6057 18:07:51.564187 DQ_CA_OPEN = 0
6058 18:07:51.567732 DQ_SEMI_OPEN = 1
6059 18:07:51.568189 CA_SEMI_OPEN = 1
6060 18:07:51.570327 CA_FULL_RATE = 0
6061 18:07:51.574394 DQ_CKDIV4_EN = 0
6062 18:07:51.577146 CA_CKDIV4_EN = 1
6063 18:07:51.580760 CA_PREDIV_EN = 0
6064 18:07:51.581217 PH8_DLY = 0
6065 18:07:51.584130 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 18:07:51.588061 DQ_AAMCK_DIV = 0
6067 18:07:51.590710 CA_AAMCK_DIV = 0
6068 18:07:51.594057 CA_ADMCK_DIV = 4
6069 18:07:51.597045 DQ_TRACK_CA_EN = 0
6070 18:07:51.600572 CA_PICK = 800
6071 18:07:51.601000 CA_MCKIO = 400
6072 18:07:51.603620 MCKIO_SEMI = 400
6073 18:07:51.607279 PLL_FREQ = 3016
6074 18:07:51.610358 DQ_UI_PI_RATIO = 32
6075 18:07:51.614110 CA_UI_PI_RATIO = 32
6076 18:07:51.617293 ===================================
6077 18:07:51.620554 ===================================
6078 18:07:51.623648 memory_type:LPDDR4
6079 18:07:51.624149 GP_NUM : 10
6080 18:07:51.626881 SRAM_EN : 1
6081 18:07:51.627388 MD32_EN : 0
6082 18:07:51.631009 ===================================
6083 18:07:51.633625 [ANA_INIT] >>>>>>>>>>>>>>
6084 18:07:51.637459 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 18:07:51.640572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 18:07:51.643925 ===================================
6087 18:07:51.647462 data_rate = 800,PCW = 0X7400
6088 18:07:51.650898 ===================================
6089 18:07:51.653615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 18:07:51.657293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 18:07:51.670205 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 18:07:51.673882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 18:07:51.677320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 18:07:51.681031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 18:07:51.684172 [ANA_INIT] flow start
6096 18:07:51.686975 [ANA_INIT] PLL >>>>>>>>
6097 18:07:51.687392 [ANA_INIT] PLL <<<<<<<<
6098 18:07:51.690511 [ANA_INIT] MIDPI >>>>>>>>
6099 18:07:51.693871 [ANA_INIT] MIDPI <<<<<<<<
6100 18:07:51.694287 [ANA_INIT] DLL >>>>>>>>
6101 18:07:51.697422 [ANA_INIT] flow end
6102 18:07:51.700314 ============ LP4 DIFF to SE enter ============
6103 18:07:51.707391 ============ LP4 DIFF to SE exit ============
6104 18:07:51.707818 [ANA_INIT] <<<<<<<<<<<<<
6105 18:07:51.710854 [Flow] Enable top DCM control >>>>>
6106 18:07:51.714327 [Flow] Enable top DCM control <<<<<
6107 18:07:51.717404 Enable DLL master slave shuffle
6108 18:07:51.723823 ==============================================================
6109 18:07:51.724243 Gating Mode config
6110 18:07:51.730238 ==============================================================
6111 18:07:51.733561 Config description:
6112 18:07:51.740376 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 18:07:51.746943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 18:07:51.753724 SELPH_MODE 0: By rank 1: By Phase
6115 18:07:51.759882 ==============================================================
6116 18:07:51.760506 GAT_TRACK_EN = 0
6117 18:07:51.763393 RX_GATING_MODE = 2
6118 18:07:51.767070 RX_GATING_TRACK_MODE = 2
6119 18:07:51.770164 SELPH_MODE = 1
6120 18:07:51.773767 PICG_EARLY_EN = 1
6121 18:07:51.776477 VALID_LAT_VALUE = 1
6122 18:07:51.783454 ==============================================================
6123 18:07:51.787456 Enter into Gating configuration >>>>
6124 18:07:51.790430 Exit from Gating configuration <<<<
6125 18:07:51.793721 Enter into DVFS_PRE_config >>>>>
6126 18:07:51.803084 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 18:07:51.806512 Exit from DVFS_PRE_config <<<<<
6128 18:07:51.810112 Enter into PICG configuration >>>>
6129 18:07:51.813064 Exit from PICG configuration <<<<
6130 18:07:51.816611 [RX_INPUT] configuration >>>>>
6131 18:07:51.817083 [RX_INPUT] configuration <<<<<
6132 18:07:51.823300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 18:07:51.829630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 18:07:51.836195 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 18:07:51.839582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 18:07:51.846492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 18:07:51.852815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 18:07:51.856446 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 18:07:51.859621 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 18:07:51.866114 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 18:07:51.869282 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 18:07:51.872715 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 18:07:51.879561 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 18:07:51.882422 ===================================
6145 18:07:51.882607 LPDDR4 DRAM CONFIGURATION
6146 18:07:51.886190 ===================================
6147 18:07:51.889586 EX_ROW_EN[0] = 0x0
6148 18:07:51.889769 EX_ROW_EN[1] = 0x0
6149 18:07:51.892459 LP4Y_EN = 0x0
6150 18:07:51.896128 WORK_FSP = 0x0
6151 18:07:51.896396 WL = 0x2
6152 18:07:51.899491 RL = 0x2
6153 18:07:51.899679 BL = 0x2
6154 18:07:51.902172 RPST = 0x0
6155 18:07:51.902411 RD_PRE = 0x0
6156 18:07:51.905951 WR_PRE = 0x1
6157 18:07:51.906133 WR_PST = 0x0
6158 18:07:51.909615 DBI_WR = 0x0
6159 18:07:51.909797 DBI_RD = 0x0
6160 18:07:51.912449 OTF = 0x1
6161 18:07:51.915850 ===================================
6162 18:07:51.919580 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 18:07:51.922325 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 18:07:51.928954 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 18:07:51.929138 ===================================
6166 18:07:51.932141 LPDDR4 DRAM CONFIGURATION
6167 18:07:51.935763 ===================================
6168 18:07:51.938856 EX_ROW_EN[0] = 0x10
6169 18:07:51.939039 EX_ROW_EN[1] = 0x0
6170 18:07:51.942296 LP4Y_EN = 0x0
6171 18:07:51.942486 WORK_FSP = 0x0
6172 18:07:51.945982 WL = 0x2
6173 18:07:51.946165 RL = 0x2
6174 18:07:51.948753 BL = 0x2
6175 18:07:51.952287 RPST = 0x0
6176 18:07:51.952496 RD_PRE = 0x0
6177 18:07:51.955589 WR_PRE = 0x1
6178 18:07:51.955770 WR_PST = 0x0
6179 18:07:51.958748 DBI_WR = 0x0
6180 18:07:51.958830 DBI_RD = 0x0
6181 18:07:51.961877 OTF = 0x1
6182 18:07:51.965569 ===================================
6183 18:07:51.968833 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 18:07:51.974142 nWR fixed to 30
6185 18:07:51.977735 [ModeRegInit_LP4] CH0 RK0
6186 18:07:51.977818 [ModeRegInit_LP4] CH0 RK1
6187 18:07:51.980964 [ModeRegInit_LP4] CH1 RK0
6188 18:07:51.984191 [ModeRegInit_LP4] CH1 RK1
6189 18:07:51.984301 match AC timing 19
6190 18:07:51.991023 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 18:07:51.994408 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 18:07:51.997516 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 18:07:52.004157 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 18:07:52.007275 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 18:07:52.007358 ==
6196 18:07:52.010810 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 18:07:52.014140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 18:07:52.014222 ==
6199 18:07:52.020761 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 18:07:52.027677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6201 18:07:52.030615 [CA 0] Center 36 (8~64) winsize 57
6202 18:07:52.034106 [CA 1] Center 36 (8~64) winsize 57
6203 18:07:52.037642 [CA 2] Center 36 (8~64) winsize 57
6204 18:07:52.037736 [CA 3] Center 36 (8~64) winsize 57
6205 18:07:52.040604 [CA 4] Center 36 (8~64) winsize 57
6206 18:07:52.044727 [CA 5] Center 36 (8~64) winsize 57
6207 18:07:52.045215
6208 18:07:52.050991 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6209 18:07:52.051444
6210 18:07:52.054570 [CATrainingPosCal] consider 1 rank data
6211 18:07:52.057828 u2DelayCellTimex100 = 270/100 ps
6212 18:07:52.061031 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 18:07:52.064640 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 18:07:52.067330 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 18:07:52.070762 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 18:07:52.074229 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 18:07:52.077759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 18:07:52.078125
6219 18:07:52.080619 CA PerBit enable=1, Macro0, CA PI delay=36
6220 18:07:52.080920
6221 18:07:52.084358 [CBTSetCACLKResult] CA Dly = 36
6222 18:07:52.087431 CS Dly: 1 (0~32)
6223 18:07:52.087738 ==
6224 18:07:52.090997 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 18:07:52.094016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 18:07:52.094334 ==
6227 18:07:52.100748 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 18:07:52.103936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6229 18:07:52.107390 [CA 0] Center 36 (8~64) winsize 57
6230 18:07:52.110594 [CA 1] Center 36 (8~64) winsize 57
6231 18:07:52.114296 [CA 2] Center 36 (8~64) winsize 57
6232 18:07:52.117436 [CA 3] Center 36 (8~64) winsize 57
6233 18:07:52.120611 [CA 4] Center 36 (8~64) winsize 57
6234 18:07:52.124484 [CA 5] Center 36 (8~64) winsize 57
6235 18:07:52.124886
6236 18:07:52.127551 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6237 18:07:52.127878
6238 18:07:52.131013 [CATrainingPosCal] consider 2 rank data
6239 18:07:52.134066 u2DelayCellTimex100 = 270/100 ps
6240 18:07:52.137413 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 18:07:52.140712 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 18:07:52.144186 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 18:07:52.147782 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 18:07:52.154220 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 18:07:52.157022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 18:07:52.157203
6247 18:07:52.160691 CA PerBit enable=1, Macro0, CA PI delay=36
6248 18:07:52.160898
6249 18:07:52.164287 [CBTSetCACLKResult] CA Dly = 36
6250 18:07:52.164511 CS Dly: 1 (0~32)
6251 18:07:52.164677
6252 18:07:52.167576 ----->DramcWriteLeveling(PI) begin...
6253 18:07:52.167771 ==
6254 18:07:52.170585 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 18:07:52.177207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 18:07:52.177359 ==
6257 18:07:52.180723 Write leveling (Byte 0): 40 => 8
6258 18:07:52.180872 Write leveling (Byte 1): 40 => 8
6259 18:07:52.183912 DramcWriteLeveling(PI) end<-----
6260 18:07:52.184060
6261 18:07:52.184178 ==
6262 18:07:52.187336 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 18:07:52.194092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 18:07:52.194245 ==
6265 18:07:52.197187 [Gating] SW mode calibration
6266 18:07:52.204319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 18:07:52.207251 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 18:07:52.214109 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 18:07:52.217669 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 18:07:52.221173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 18:07:52.227314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 18:07:52.230596 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 18:07:52.233641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 18:07:52.240362 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 18:07:52.244608 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 18:07:52.247378 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 18:07:52.250718 Total UI for P1: 0, mck2ui 16
6278 18:07:52.253916 best dqsien dly found for B0: ( 0, 14, 24)
6279 18:07:52.257228 Total UI for P1: 0, mck2ui 16
6280 18:07:52.260616 best dqsien dly found for B1: ( 0, 14, 24)
6281 18:07:52.264246 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 18:07:52.266933 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 18:07:52.267083
6284 18:07:52.270394 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 18:07:52.276995 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 18:07:52.277246 [Gating] SW calibration Done
6287 18:07:52.277452 ==
6288 18:07:52.280623 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 18:07:52.287128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 18:07:52.287214 ==
6291 18:07:52.287279 RX Vref Scan: 0
6292 18:07:52.287341
6293 18:07:52.290159 RX Vref 0 -> 0, step: 1
6294 18:07:52.290241
6295 18:07:52.293597 RX Delay -410 -> 252, step: 16
6296 18:07:52.297143 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6297 18:07:52.300232 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6298 18:07:52.306985 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6299 18:07:52.309743 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6300 18:07:52.313275 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6301 18:07:52.316630 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6302 18:07:52.323118 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6303 18:07:52.326601 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6304 18:07:52.329991 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6305 18:07:52.332975 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6306 18:07:52.339872 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6307 18:07:52.343231 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6308 18:07:52.346458 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6309 18:07:52.349533 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6310 18:07:52.356542 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6311 18:07:52.360108 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6312 18:07:52.360195 ==
6313 18:07:52.363416 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 18:07:52.366284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 18:07:52.366366 ==
6316 18:07:52.369735 DQS Delay:
6317 18:07:52.369817 DQS0 = 27, DQS1 = 35
6318 18:07:52.373590 DQM Delay:
6319 18:07:52.373738 DQM0 = 12, DQM1 = 11
6320 18:07:52.373834 DQ Delay:
6321 18:07:52.375993 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6322 18:07:52.379765 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6323 18:07:52.382631 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6324 18:07:52.386338 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6325 18:07:52.386435
6326 18:07:52.386502
6327 18:07:52.386562 ==
6328 18:07:52.389223 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 18:07:52.395886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 18:07:52.395963 ==
6331 18:07:52.396026
6332 18:07:52.396085
6333 18:07:52.396144 TX Vref Scan disable
6334 18:07:52.399747 == TX Byte 0 ==
6335 18:07:52.402596 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 18:07:52.405930 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 18:07:52.409322 == TX Byte 1 ==
6338 18:07:52.412673 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 18:07:52.416110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 18:07:52.416224 ==
6341 18:07:52.419510 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 18:07:52.425970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 18:07:52.426052 ==
6344 18:07:52.426117
6345 18:07:52.426178
6346 18:07:52.426236 TX Vref Scan disable
6347 18:07:52.429488 == TX Byte 0 ==
6348 18:07:52.432279 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 18:07:52.436042 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 18:07:52.439056 == TX Byte 1 ==
6351 18:07:52.442536 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 18:07:52.445621 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 18:07:52.445728
6354 18:07:52.449226 [DATLAT]
6355 18:07:52.449330 Freq=400, CH0 RK0
6356 18:07:52.449417
6357 18:07:52.452551 DATLAT Default: 0xf
6358 18:07:52.452647 0, 0xFFFF, sum = 0
6359 18:07:52.455618 1, 0xFFFF, sum = 0
6360 18:07:52.455726 2, 0xFFFF, sum = 0
6361 18:07:52.459248 3, 0xFFFF, sum = 0
6362 18:07:52.459361 4, 0xFFFF, sum = 0
6363 18:07:52.462673 5, 0xFFFF, sum = 0
6364 18:07:52.462781 6, 0xFFFF, sum = 0
6365 18:07:52.465857 7, 0xFFFF, sum = 0
6366 18:07:52.465941 8, 0xFFFF, sum = 0
6367 18:07:52.469577 9, 0xFFFF, sum = 0
6368 18:07:52.472955 10, 0xFFFF, sum = 0
6369 18:07:52.473045 11, 0xFFFF, sum = 0
6370 18:07:52.476208 12, 0xFFFF, sum = 0
6371 18:07:52.476335 13, 0x0, sum = 1
6372 18:07:52.478971 14, 0x0, sum = 2
6373 18:07:52.479117 15, 0x0, sum = 3
6374 18:07:52.479208 16, 0x0, sum = 4
6375 18:07:52.482182 best_step = 14
6376 18:07:52.482315
6377 18:07:52.482434 ==
6378 18:07:52.485559 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 18:07:52.489194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 18:07:52.489326 ==
6381 18:07:52.492552 RX Vref Scan: 1
6382 18:07:52.492719
6383 18:07:52.495443 RX Vref 0 -> 0, step: 1
6384 18:07:52.495582
6385 18:07:52.495693 RX Delay -311 -> 252, step: 8
6386 18:07:52.495797
6387 18:07:52.498931 Set Vref, RX VrefLevel [Byte0]: 55
6388 18:07:52.502656 [Byte1]: 43
6389 18:07:52.507642
6390 18:07:52.507799 Final RX Vref Byte 0 = 55 to rank0
6391 18:07:52.511070 Final RX Vref Byte 1 = 43 to rank0
6392 18:07:52.514512 Final RX Vref Byte 0 = 55 to rank1
6393 18:07:52.517906 Final RX Vref Byte 1 = 43 to rank1==
6394 18:07:52.520837 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 18:07:52.527395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 18:07:52.527733 ==
6397 18:07:52.528035 DQS Delay:
6398 18:07:52.530988 DQS0 = 24, DQS1 = 36
6399 18:07:52.531282 DQM Delay:
6400 18:07:52.531489 DQM0 = 7, DQM1 = 14
6401 18:07:52.534303 DQ Delay:
6402 18:07:52.537577 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6403 18:07:52.537834 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6404 18:07:52.540998 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6405 18:07:52.544531 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6406 18:07:52.544799
6407 18:07:52.545005
6408 18:07:52.554295 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6409 18:07:52.557086 CH0 RK0: MR19=C0C, MR18=C9B7
6410 18:07:52.563976 CH0_RK0: MR19=0xC0C, MR18=0xC9B7, DQSOSC=384, MR23=63, INC=400, DEC=267
6411 18:07:52.564377 ==
6412 18:07:52.567149 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 18:07:52.571002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 18:07:52.571259 ==
6415 18:07:52.574276 [Gating] SW mode calibration
6416 18:07:52.580812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 18:07:52.584281 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 18:07:52.590284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 18:07:52.594278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 18:07:52.597432 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 18:07:52.603808 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 18:07:52.607137 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 18:07:52.610573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 18:07:52.617046 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 18:07:52.620476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 18:07:52.623363 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 18:07:52.626990 Total UI for P1: 0, mck2ui 16
6428 18:07:52.630186 best dqsien dly found for B0: ( 0, 14, 24)
6429 18:07:52.633520 Total UI for P1: 0, mck2ui 16
6430 18:07:52.637248 best dqsien dly found for B1: ( 0, 14, 24)
6431 18:07:52.639989 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 18:07:52.643515 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 18:07:52.646925
6434 18:07:52.650260 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 18:07:52.653359 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 18:07:52.656704 [Gating] SW calibration Done
6437 18:07:52.656844 ==
6438 18:07:52.660119 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 18:07:52.663563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 18:07:52.663709 ==
6441 18:07:52.663833 RX Vref Scan: 0
6442 18:07:52.666470
6443 18:07:52.666592 RX Vref 0 -> 0, step: 1
6444 18:07:52.666688
6445 18:07:52.669876 RX Delay -410 -> 252, step: 16
6446 18:07:52.673258 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6447 18:07:52.680263 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6448 18:07:52.683724 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6449 18:07:52.687204 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6450 18:07:52.689843 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6451 18:07:52.696867 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6452 18:07:52.699855 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6453 18:07:52.703386 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6454 18:07:52.706575 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6455 18:07:52.713642 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6456 18:07:52.716543 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6457 18:07:52.720039 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6458 18:07:52.723597 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6459 18:07:52.730188 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6460 18:07:52.733489 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6461 18:07:52.736539 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6462 18:07:52.736689 ==
6463 18:07:52.739676 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 18:07:52.743261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 18:07:52.746031 ==
6466 18:07:52.746160 DQS Delay:
6467 18:07:52.746262 DQS0 = 27, DQS1 = 35
6468 18:07:52.749557 DQM Delay:
6469 18:07:52.749685 DQM0 = 12, DQM1 = 14
6470 18:07:52.753303 DQ Delay:
6471 18:07:52.753434 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6472 18:07:52.756471 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6473 18:07:52.759828 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6474 18:07:52.762997 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6475 18:07:52.763141
6476 18:07:52.763270
6477 18:07:52.763391 ==
6478 18:07:52.766217 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 18:07:52.773369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 18:07:52.773522 ==
6481 18:07:52.773658
6482 18:07:52.773786
6483 18:07:52.776258 TX Vref Scan disable
6484 18:07:52.776408 == TX Byte 0 ==
6485 18:07:52.779532 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6486 18:07:52.782992 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6487 18:07:52.786334 == TX Byte 1 ==
6488 18:07:52.789969 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6489 18:07:52.792714 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6490 18:07:52.796215 ==
6491 18:07:52.799184 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 18:07:52.802661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 18:07:52.802803 ==
6494 18:07:52.802894
6495 18:07:52.802977
6496 18:07:52.806266 TX Vref Scan disable
6497 18:07:52.806380 == TX Byte 0 ==
6498 18:07:52.809224 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6499 18:07:52.815947 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6500 18:07:52.816062 == TX Byte 1 ==
6501 18:07:52.819631 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 18:07:52.823207 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 18:07:52.826417
6504 18:07:52.826531 [DATLAT]
6505 18:07:52.826620 Freq=400, CH0 RK1
6506 18:07:52.826705
6507 18:07:52.829187 DATLAT Default: 0xe
6508 18:07:52.829335 0, 0xFFFF, sum = 0
6509 18:07:52.832629 1, 0xFFFF, sum = 0
6510 18:07:52.832744 2, 0xFFFF, sum = 0
6511 18:07:52.836280 3, 0xFFFF, sum = 0
6512 18:07:52.836409 4, 0xFFFF, sum = 0
6513 18:07:52.839614 5, 0xFFFF, sum = 0
6514 18:07:52.839733 6, 0xFFFF, sum = 0
6515 18:07:52.842656 7, 0xFFFF, sum = 0
6516 18:07:52.846606 8, 0xFFFF, sum = 0
6517 18:07:52.846764 9, 0xFFFF, sum = 0
6518 18:07:52.849286 10, 0xFFFF, sum = 0
6519 18:07:52.849401 11, 0xFFFF, sum = 0
6520 18:07:52.852936 12, 0xFFFF, sum = 0
6521 18:07:52.853050 13, 0x0, sum = 1
6522 18:07:52.856055 14, 0x0, sum = 2
6523 18:07:52.856169 15, 0x0, sum = 3
6524 18:07:52.859440 16, 0x0, sum = 4
6525 18:07:52.859597 best_step = 14
6526 18:07:52.859733
6527 18:07:52.859860 ==
6528 18:07:52.862665 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 18:07:52.866312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 18:07:52.866441 ==
6531 18:07:52.869060 RX Vref Scan: 0
6532 18:07:52.869201
6533 18:07:52.872267 RX Vref 0 -> 0, step: 1
6534 18:07:52.872446
6535 18:07:52.872585 RX Delay -311 -> 252, step: 8
6536 18:07:52.881197 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6537 18:07:52.884668 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6538 18:07:52.888145 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6539 18:07:52.894101 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6540 18:07:52.897607 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6541 18:07:52.901161 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6542 18:07:52.904029 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6543 18:07:52.907609 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6544 18:07:52.914305 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6545 18:07:52.917377 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6546 18:07:52.920870 iDelay=217, Bit 10, Center -20 (-231 ~ 192) 424
6547 18:07:52.924574 iDelay=217, Bit 11, Center -32 (-247 ~ 184) 432
6548 18:07:52.931640 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6549 18:07:52.934074 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6550 18:07:52.937419 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6551 18:07:52.944383 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6552 18:07:52.944493 ==
6553 18:07:52.947953 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 18:07:52.950555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 18:07:52.950671 ==
6556 18:07:52.950772 DQS Delay:
6557 18:07:52.954205 DQS0 = 24, DQS1 = 36
6558 18:07:52.954295 DQM Delay:
6559 18:07:52.957774 DQM0 = 9, DQM1 = 13
6560 18:07:52.957863 DQ Delay:
6561 18:07:52.960891 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6562 18:07:52.964154 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6563 18:07:52.967636 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6564 18:07:52.971089 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6565 18:07:52.971191
6566 18:07:52.971283
6567 18:07:52.977466 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6568 18:07:52.980825 CH0 RK1: MR19=C0C, MR18=BC5C
6569 18:07:52.987048 CH0_RK1: MR19=0xC0C, MR18=0xBC5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6570 18:07:52.990339 [RxdqsGatingPostProcess] freq 400
6571 18:07:52.997128 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 18:07:52.997211 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 18:07:53.000911 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 18:07:53.004226 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 18:07:53.007234 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 18:07:53.011017 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 18:07:53.013772 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 18:07:53.017377 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 18:07:53.020235 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 18:07:53.023914 Pre-setting of DQS Precalculation
6581 18:07:53.027298 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 18:07:53.030813 ==
6583 18:07:53.033590 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 18:07:53.036971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 18:07:53.037054 ==
6586 18:07:53.040451 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 18:07:53.047056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6588 18:07:53.050861 [CA 0] Center 36 (8~64) winsize 57
6589 18:07:53.054126 [CA 1] Center 36 (8~64) winsize 57
6590 18:07:53.057422 [CA 2] Center 36 (8~64) winsize 57
6591 18:07:53.060498 [CA 3] Center 36 (8~64) winsize 57
6592 18:07:53.064002 [CA 4] Center 36 (8~64) winsize 57
6593 18:07:53.067519 [CA 5] Center 36 (8~64) winsize 57
6594 18:07:53.067602
6595 18:07:53.070322 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6596 18:07:53.070405
6597 18:07:53.073826 [CATrainingPosCal] consider 1 rank data
6598 18:07:53.077381 u2DelayCellTimex100 = 270/100 ps
6599 18:07:53.080204 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 18:07:53.083942 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 18:07:53.087458 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 18:07:53.090265 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 18:07:53.093899 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 18:07:53.100541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 18:07:53.100623
6606 18:07:53.103747 CA PerBit enable=1, Macro0, CA PI delay=36
6607 18:07:53.103829
6608 18:07:53.106799 [CBTSetCACLKResult] CA Dly = 36
6609 18:07:53.106881 CS Dly: 1 (0~32)
6610 18:07:53.106946 ==
6611 18:07:53.110450 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 18:07:53.113584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 18:07:53.117323 ==
6614 18:07:53.120282 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 18:07:53.127027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6616 18:07:53.130387 [CA 0] Center 36 (8~64) winsize 57
6617 18:07:53.133771 [CA 1] Center 36 (8~64) winsize 57
6618 18:07:53.136891 [CA 2] Center 36 (8~64) winsize 57
6619 18:07:53.140181 [CA 3] Center 36 (8~64) winsize 57
6620 18:07:53.143910 [CA 4] Center 36 (8~64) winsize 57
6621 18:07:53.146602 [CA 5] Center 36 (8~64) winsize 57
6622 18:07:53.146694
6623 18:07:53.150135 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6624 18:07:53.150246
6625 18:07:53.153629 [CATrainingPosCal] consider 2 rank data
6626 18:07:53.156888 u2DelayCellTimex100 = 270/100 ps
6627 18:07:53.160106 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 18:07:53.163429 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 18:07:53.166626 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 18:07:53.170121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 18:07:53.173949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 18:07:53.177264 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 18:07:53.177352
6634 18:07:53.180104 CA PerBit enable=1, Macro0, CA PI delay=36
6635 18:07:53.183729
6636 18:07:53.183810 [CBTSetCACLKResult] CA Dly = 36
6637 18:07:53.186556 CS Dly: 1 (0~32)
6638 18:07:53.186650
6639 18:07:53.190245 ----->DramcWriteLeveling(PI) begin...
6640 18:07:53.190326 ==
6641 18:07:53.193128 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 18:07:53.196754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 18:07:53.196836 ==
6644 18:07:53.200276 Write leveling (Byte 0): 40 => 8
6645 18:07:53.203245 Write leveling (Byte 1): 40 => 8
6646 18:07:53.206816 DramcWriteLeveling(PI) end<-----
6647 18:07:53.206937
6648 18:07:53.207028 ==
6649 18:07:53.210402 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 18:07:53.213637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 18:07:53.213778 ==
6652 18:07:53.216615 [Gating] SW mode calibration
6653 18:07:53.223127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 18:07:53.229964 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 18:07:53.233215 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 18:07:53.239703 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 18:07:53.242950 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 18:07:53.247211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 18:07:53.253130 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 18:07:53.256669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 18:07:53.259832 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 18:07:53.263604 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 18:07:53.269732 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 18:07:53.272831 Total UI for P1: 0, mck2ui 16
6665 18:07:53.276290 best dqsien dly found for B0: ( 0, 14, 24)
6666 18:07:53.279513 Total UI for P1: 0, mck2ui 16
6667 18:07:53.282986 best dqsien dly found for B1: ( 0, 14, 24)
6668 18:07:53.286048 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 18:07:53.290047 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 18:07:53.290147
6671 18:07:53.293066 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 18:07:53.296043 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 18:07:53.299577 [Gating] SW calibration Done
6674 18:07:53.299655 ==
6675 18:07:53.303185 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 18:07:53.306047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 18:07:53.306156 ==
6678 18:07:53.309641 RX Vref Scan: 0
6679 18:07:53.309740
6680 18:07:53.313104 RX Vref 0 -> 0, step: 1
6681 18:07:53.313179
6682 18:07:53.313243 RX Delay -410 -> 252, step: 16
6683 18:07:53.319762 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6684 18:07:53.323120 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6685 18:07:53.326228 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6686 18:07:53.332758 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6687 18:07:53.336115 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6688 18:07:53.339541 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6689 18:07:53.342941 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6690 18:07:53.346118 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6691 18:07:53.353060 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6692 18:07:53.356387 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6693 18:07:53.359243 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6694 18:07:53.366075 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6695 18:07:53.369413 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6696 18:07:53.372973 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6697 18:07:53.376474 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6698 18:07:53.382647 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6699 18:07:53.382730 ==
6700 18:07:53.386124 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 18:07:53.389654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 18:07:53.389738 ==
6703 18:07:53.389804 DQS Delay:
6704 18:07:53.392649 DQS0 = 35, DQS1 = 35
6705 18:07:53.392732 DQM Delay:
6706 18:07:53.395752 DQM0 = 17, DQM1 = 13
6707 18:07:53.395832 DQ Delay:
6708 18:07:53.399677 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6709 18:07:53.402404 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6710 18:07:53.405700 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 18:07:53.409226 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6712 18:07:53.409308
6713 18:07:53.409373
6714 18:07:53.409431 ==
6715 18:07:53.412768 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 18:07:53.415829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 18:07:53.415911 ==
6718 18:07:53.416000
6719 18:07:53.416073
6720 18:07:53.418771 TX Vref Scan disable
6721 18:07:53.422331 == TX Byte 0 ==
6722 18:07:53.425940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 18:07:53.429141 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 18:07:53.432571 == TX Byte 1 ==
6725 18:07:53.435615 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 18:07:53.439234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 18:07:53.439330 ==
6728 18:07:53.442322 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 18:07:53.445805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 18:07:53.445887 ==
6731 18:07:53.445951
6732 18:07:53.449272
6733 18:07:53.449357 TX Vref Scan disable
6734 18:07:53.452655 == TX Byte 0 ==
6735 18:07:53.455434 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 18:07:53.458862 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 18:07:53.462397 == TX Byte 1 ==
6738 18:07:53.466047 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 18:07:53.468989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 18:07:53.469097
6741 18:07:53.469190 [DATLAT]
6742 18:07:53.472244 Freq=400, CH1 RK0
6743 18:07:53.472328
6744 18:07:53.472421 DATLAT Default: 0xf
6745 18:07:53.475900 0, 0xFFFF, sum = 0
6746 18:07:53.475983 1, 0xFFFF, sum = 0
6747 18:07:53.478959 2, 0xFFFF, sum = 0
6748 18:07:53.482115 3, 0xFFFF, sum = 0
6749 18:07:53.482203 4, 0xFFFF, sum = 0
6750 18:07:53.485697 5, 0xFFFF, sum = 0
6751 18:07:53.485780 6, 0xFFFF, sum = 0
6752 18:07:53.489104 7, 0xFFFF, sum = 0
6753 18:07:53.489183 8, 0xFFFF, sum = 0
6754 18:07:53.492024 9, 0xFFFF, sum = 0
6755 18:07:53.492135 10, 0xFFFF, sum = 0
6756 18:07:53.495735 11, 0xFFFF, sum = 0
6757 18:07:53.495847 12, 0xFFFF, sum = 0
6758 18:07:53.498695 13, 0x0, sum = 1
6759 18:07:53.498807 14, 0x0, sum = 2
6760 18:07:53.502283 15, 0x0, sum = 3
6761 18:07:53.502368 16, 0x0, sum = 4
6762 18:07:53.505517 best_step = 14
6763 18:07:53.505605
6764 18:07:53.505693 ==
6765 18:07:53.509045 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 18:07:53.512384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 18:07:53.512474 ==
6768 18:07:53.512555 RX Vref Scan: 1
6769 18:07:53.515522
6770 18:07:53.515632 RX Vref 0 -> 0, step: 1
6771 18:07:53.515727
6772 18:07:53.518804 RX Delay -311 -> 252, step: 8
6773 18:07:53.518893
6774 18:07:53.521757 Set Vref, RX VrefLevel [Byte0]: 53
6775 18:07:53.525330 [Byte1]: 47
6776 18:07:53.529129
6777 18:07:53.529205 Final RX Vref Byte 0 = 53 to rank0
6778 18:07:53.532515 Final RX Vref Byte 1 = 47 to rank0
6779 18:07:53.535758 Final RX Vref Byte 0 = 53 to rank1
6780 18:07:53.539315 Final RX Vref Byte 1 = 47 to rank1==
6781 18:07:53.542827 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 18:07:53.549531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 18:07:53.549655 ==
6784 18:07:53.549757 DQS Delay:
6785 18:07:53.552234 DQS0 = 32, DQS1 = 32
6786 18:07:53.552350 DQM Delay:
6787 18:07:53.552433 DQM0 = 13, DQM1 = 11
6788 18:07:53.555825 DQ Delay:
6789 18:07:53.559286 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6790 18:07:53.562176 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6791 18:07:53.562290 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6792 18:07:53.569224 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6793 18:07:53.569345
6794 18:07:53.569462
6795 18:07:53.575469 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ac3, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6796 18:07:53.579066 CH1 RK0: MR19=C0C, MR18=8AC3
6797 18:07:53.585163 CH1_RK0: MR19=0xC0C, MR18=0x8AC3, DQSOSC=385, MR23=63, INC=398, DEC=265
6798 18:07:53.585276 ==
6799 18:07:53.589004 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 18:07:53.592076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 18:07:53.592160 ==
6802 18:07:53.595353 [Gating] SW mode calibration
6803 18:07:53.602374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 18:07:53.609184 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 18:07:53.612106 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 18:07:53.615586 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 18:07:53.622165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 18:07:53.625792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 18:07:53.629124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 18:07:53.635615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 18:07:53.639004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 18:07:53.642322 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 18:07:53.648625 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 18:07:53.648711 Total UI for P1: 0, mck2ui 16
6815 18:07:53.652483 best dqsien dly found for B0: ( 0, 14, 24)
6816 18:07:53.655145 Total UI for P1: 0, mck2ui 16
6817 18:07:53.658650 best dqsien dly found for B1: ( 0, 14, 24)
6818 18:07:53.662284 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 18:07:53.668429 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 18:07:53.668515
6821 18:07:53.671894 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 18:07:53.675364 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 18:07:53.679352 [Gating] SW calibration Done
6824 18:07:53.679461 ==
6825 18:07:53.682067 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 18:07:53.685052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 18:07:53.685136 ==
6828 18:07:53.688508 RX Vref Scan: 0
6829 18:07:53.688590
6830 18:07:53.688655 RX Vref 0 -> 0, step: 1
6831 18:07:53.688717
6832 18:07:53.691907 RX Delay -410 -> 252, step: 16
6833 18:07:53.695588 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6834 18:07:53.702067 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6835 18:07:53.705555 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6836 18:07:53.709031 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6837 18:07:53.712248 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6838 18:07:53.718746 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6839 18:07:53.722004 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6840 18:07:53.725114 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6841 18:07:53.728311 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6842 18:07:53.735363 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6843 18:07:53.738623 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6844 18:07:53.742006 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6845 18:07:53.745536 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6846 18:07:53.751486 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6847 18:07:53.754972 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6848 18:07:53.758385 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6849 18:07:53.758468 ==
6850 18:07:53.762039 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 18:07:53.768541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 18:07:53.768626 ==
6853 18:07:53.768691 DQS Delay:
6854 18:07:53.771373 DQS0 = 35, DQS1 = 35
6855 18:07:53.771454 DQM Delay:
6856 18:07:53.771547 DQM0 = 17, DQM1 = 13
6857 18:07:53.774949 DQ Delay:
6858 18:07:53.778598 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6859 18:07:53.781530 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6860 18:07:53.781610 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6861 18:07:53.788397 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6862 18:07:53.788503
6863 18:07:53.788597
6864 18:07:53.788684 ==
6865 18:07:53.791558 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 18:07:53.795077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 18:07:53.795205 ==
6868 18:07:53.795357
6869 18:07:53.795492
6870 18:07:53.798451 TX Vref Scan disable
6871 18:07:53.798573 == TX Byte 0 ==
6872 18:07:53.801635 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6873 18:07:53.808325 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6874 18:07:53.808436 == TX Byte 1 ==
6875 18:07:53.811279 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6876 18:07:53.817914 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6877 18:07:53.818002 ==
6878 18:07:53.820902 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 18:07:53.824452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 18:07:53.824558 ==
6881 18:07:53.824651
6882 18:07:53.824741
6883 18:07:53.827805 TX Vref Scan disable
6884 18:07:53.827875 == TX Byte 0 ==
6885 18:07:53.834534 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6886 18:07:53.837534 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6887 18:07:53.837635 == TX Byte 1 ==
6888 18:07:53.844822 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 18:07:53.847783 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 18:07:53.847867
6891 18:07:53.847931 [DATLAT]
6892 18:07:53.851602 Freq=400, CH1 RK1
6893 18:07:53.851684
6894 18:07:53.851747 DATLAT Default: 0xe
6895 18:07:53.854588 0, 0xFFFF, sum = 0
6896 18:07:53.854697 1, 0xFFFF, sum = 0
6897 18:07:53.857804 2, 0xFFFF, sum = 0
6898 18:07:53.857886 3, 0xFFFF, sum = 0
6899 18:07:53.861118 4, 0xFFFF, sum = 0
6900 18:07:53.861214 5, 0xFFFF, sum = 0
6901 18:07:53.864528 6, 0xFFFF, sum = 0
6902 18:07:53.864610 7, 0xFFFF, sum = 0
6903 18:07:53.867835 8, 0xFFFF, sum = 0
6904 18:07:53.867957 9, 0xFFFF, sum = 0
6905 18:07:53.870763 10, 0xFFFF, sum = 0
6906 18:07:53.870862 11, 0xFFFF, sum = 0
6907 18:07:53.874239 12, 0xFFFF, sum = 0
6908 18:07:53.874350 13, 0x0, sum = 1
6909 18:07:53.878015 14, 0x0, sum = 2
6910 18:07:53.878119 15, 0x0, sum = 3
6911 18:07:53.880750 16, 0x0, sum = 4
6912 18:07:53.880823 best_step = 14
6913 18:07:53.880887
6914 18:07:53.880946 ==
6915 18:07:53.884097 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 18:07:53.890689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 18:07:53.890787 ==
6918 18:07:53.890876 RX Vref Scan: 0
6919 18:07:53.890963
6920 18:07:53.894286 RX Vref 0 -> 0, step: 1
6921 18:07:53.894386
6922 18:07:53.897632 RX Delay -311 -> 252, step: 8
6923 18:07:53.903837 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6924 18:07:53.907301 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6925 18:07:53.910792 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6926 18:07:53.914401 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6927 18:07:53.921039 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6928 18:07:53.924300 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6929 18:07:53.927606 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6930 18:07:53.930686 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6931 18:07:53.937452 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6932 18:07:53.941064 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6933 18:07:53.943660 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6934 18:07:53.947121 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6935 18:07:53.954057 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6936 18:07:53.957281 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6937 18:07:53.960895 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6938 18:07:53.964090 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6939 18:07:53.967726 ==
6940 18:07:53.967809 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 18:07:53.973809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 18:07:53.973921 ==
6943 18:07:53.974026 DQS Delay:
6944 18:07:53.976886 DQS0 = 28, DQS1 = 36
6945 18:07:53.976961 DQM Delay:
6946 18:07:53.980230 DQM0 = 10, DQM1 = 14
6947 18:07:53.980348 DQ Delay:
6948 18:07:53.984123 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6949 18:07:53.987288 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6950 18:07:53.990457 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6951 18:07:53.993782 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6952 18:07:53.993879
6953 18:07:53.993971
6954 18:07:54.000622 [DQSOSCAuto] RK1, (LSB)MR18= 0xc250, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6955 18:07:54.004080 CH1 RK1: MR19=C0C, MR18=C250
6956 18:07:54.010375 CH1_RK1: MR19=0xC0C, MR18=0xC250, DQSOSC=385, MR23=63, INC=398, DEC=265
6957 18:07:54.013868 [RxdqsGatingPostProcess] freq 400
6958 18:07:54.017520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 18:07:54.021045 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 18:07:54.023708 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 18:07:54.027357 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 18:07:54.030525 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 18:07:54.033460 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 18:07:54.036959 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 18:07:54.040243 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 18:07:54.043898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 18:07:54.047385 Pre-setting of DQS Precalculation
6968 18:07:54.050189 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 18:07:54.060325 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 18:07:54.066793 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 18:07:54.067215
6972 18:07:54.067583
6973 18:07:54.070300 [Calibration Summary] 800 Mbps
6974 18:07:54.070854 CH 0, Rank 0
6975 18:07:54.073636 SW Impedance : PASS
6976 18:07:54.074226 DUTY Scan : NO K
6977 18:07:54.077117 ZQ Calibration : PASS
6978 18:07:54.080546 Jitter Meter : NO K
6979 18:07:54.080974 CBT Training : PASS
6980 18:07:54.083403 Write leveling : PASS
6981 18:07:54.086982 RX DQS gating : PASS
6982 18:07:54.087525 RX DQ/DQS(RDDQC) : PASS
6983 18:07:54.090441 TX DQ/DQS : PASS
6984 18:07:54.093926 RX DATLAT : PASS
6985 18:07:54.094486 RX DQ/DQS(Engine): PASS
6986 18:07:54.096982 TX OE : NO K
6987 18:07:54.097617 All Pass.
6988 18:07:54.098130
6989 18:07:54.100637 CH 0, Rank 1
6990 18:07:54.101086 SW Impedance : PASS
6991 18:07:54.103439 DUTY Scan : NO K
6992 18:07:54.107210 ZQ Calibration : PASS
6993 18:07:54.107715 Jitter Meter : NO K
6994 18:07:54.109975 CBT Training : PASS
6995 18:07:54.110567 Write leveling : NO K
6996 18:07:54.113512 RX DQS gating : PASS
6997 18:07:54.117033 RX DQ/DQS(RDDQC) : PASS
6998 18:07:54.117583 TX DQ/DQS : PASS
6999 18:07:54.120294 RX DATLAT : PASS
7000 18:07:54.123455 RX DQ/DQS(Engine): PASS
7001 18:07:54.123881 TX OE : NO K
7002 18:07:54.127108 All Pass.
7003 18:07:54.127639
7004 18:07:54.128122 CH 1, Rank 0
7005 18:07:54.130424 SW Impedance : PASS
7006 18:07:54.130941 DUTY Scan : NO K
7007 18:07:54.133159 ZQ Calibration : PASS
7008 18:07:54.136624 Jitter Meter : NO K
7009 18:07:54.137205 CBT Training : PASS
7010 18:07:54.140040 Write leveling : PASS
7011 18:07:54.143317 RX DQS gating : PASS
7012 18:07:54.143762 RX DQ/DQS(RDDQC) : PASS
7013 18:07:54.146751 TX DQ/DQS : PASS
7014 18:07:54.150168 RX DATLAT : PASS
7015 18:07:54.150742 RX DQ/DQS(Engine): PASS
7016 18:07:54.153031 TX OE : NO K
7017 18:07:54.153564 All Pass.
7018 18:07:54.153913
7019 18:07:54.156582 CH 1, Rank 1
7020 18:07:54.157060 SW Impedance : PASS
7021 18:07:54.159998 DUTY Scan : NO K
7022 18:07:54.163435 ZQ Calibration : PASS
7023 18:07:54.163850 Jitter Meter : NO K
7024 18:07:54.166976 CBT Training : PASS
7025 18:07:54.167391 Write leveling : NO K
7026 18:07:54.169697 RX DQS gating : PASS
7027 18:07:54.173585 RX DQ/DQS(RDDQC) : PASS
7028 18:07:54.173997 TX DQ/DQS : PASS
7029 18:07:54.177008 RX DATLAT : PASS
7030 18:07:54.179776 RX DQ/DQS(Engine): PASS
7031 18:07:54.180261 TX OE : NO K
7032 18:07:54.183031 All Pass.
7033 18:07:54.183112
7034 18:07:54.183212 DramC Write-DBI off
7035 18:07:54.186323 PER_BANK_REFRESH: Hybrid Mode
7036 18:07:54.186412 TX_TRACKING: ON
7037 18:07:54.196479 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 18:07:54.200010 [FAST_K] Save calibration result to emmc
7039 18:07:54.203196 dramc_set_vcore_voltage set vcore to 725000
7040 18:07:54.206145 Read voltage for 1600, 0
7041 18:07:54.206218 Vio18 = 0
7042 18:07:54.209616 Vcore = 725000
7043 18:07:54.209687 Vdram = 0
7044 18:07:54.209748 Vddq = 0
7045 18:07:54.212553 Vmddr = 0
7046 18:07:54.216009 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 18:07:54.223009 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 18:07:54.223113 MEM_TYPE=3, freq_sel=13
7049 18:07:54.226072 sv_algorithm_assistance_LP4_3733
7050 18:07:54.233067 ============ PULL DRAM RESETB DOWN ============
7051 18:07:54.236484 ========== PULL DRAM RESETB DOWN end =========
7052 18:07:54.239595 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 18:07:54.242910 ===================================
7054 18:07:54.246432 LPDDR4 DRAM CONFIGURATION
7055 18:07:54.249628 ===================================
7056 18:07:54.249732 EX_ROW_EN[0] = 0x0
7057 18:07:54.252550 EX_ROW_EN[1] = 0x0
7058 18:07:54.256600 LP4Y_EN = 0x0
7059 18:07:54.256691 WORK_FSP = 0x1
7060 18:07:54.259400 WL = 0x5
7061 18:07:54.259502 RL = 0x5
7062 18:07:54.263126 BL = 0x2
7063 18:07:54.263228 RPST = 0x0
7064 18:07:54.265919 RD_PRE = 0x0
7065 18:07:54.266051 WR_PRE = 0x1
7066 18:07:54.269463 WR_PST = 0x1
7067 18:07:54.269551 DBI_WR = 0x0
7068 18:07:54.272951 DBI_RD = 0x0
7069 18:07:54.273040 OTF = 0x1
7070 18:07:54.275953 ===================================
7071 18:07:54.279593 ===================================
7072 18:07:54.283093 ANA top config
7073 18:07:54.285945 ===================================
7074 18:07:54.286041 DLL_ASYNC_EN = 0
7075 18:07:54.289404 ALL_SLAVE_EN = 0
7076 18:07:54.293207 NEW_RANK_MODE = 1
7077 18:07:54.295977 DLL_IDLE_MODE = 1
7078 18:07:54.296093 LP45_APHY_COMB_EN = 1
7079 18:07:54.299616 TX_ODT_DIS = 0
7080 18:07:54.302659 NEW_8X_MODE = 1
7081 18:07:54.306110 ===================================
7082 18:07:54.309280 ===================================
7083 18:07:54.312786 data_rate = 3200
7084 18:07:54.316352 CKR = 1
7085 18:07:54.319205 DQ_P2S_RATIO = 8
7086 18:07:54.322743 ===================================
7087 18:07:54.322855 CA_P2S_RATIO = 8
7088 18:07:54.326538 DQ_CA_OPEN = 0
7089 18:07:54.329202 DQ_SEMI_OPEN = 0
7090 18:07:54.332758 CA_SEMI_OPEN = 0
7091 18:07:54.335577 CA_FULL_RATE = 0
7092 18:07:54.339636 DQ_CKDIV4_EN = 0
7093 18:07:54.339719 CA_CKDIV4_EN = 0
7094 18:07:54.342466 CA_PREDIV_EN = 0
7095 18:07:54.345933 PH8_DLY = 12
7096 18:07:54.349188 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 18:07:54.352688 DQ_AAMCK_DIV = 4
7098 18:07:54.355849 CA_AAMCK_DIV = 4
7099 18:07:54.355931 CA_ADMCK_DIV = 4
7100 18:07:54.359247 DQ_TRACK_CA_EN = 0
7101 18:07:54.362373 CA_PICK = 1600
7102 18:07:54.366059 CA_MCKIO = 1600
7103 18:07:54.369323 MCKIO_SEMI = 0
7104 18:07:54.372184 PLL_FREQ = 3068
7105 18:07:54.375773 DQ_UI_PI_RATIO = 32
7106 18:07:54.375887 CA_UI_PI_RATIO = 0
7107 18:07:54.379144 ===================================
7108 18:07:54.382452 ===================================
7109 18:07:54.385730 memory_type:LPDDR4
7110 18:07:54.389065 GP_NUM : 10
7111 18:07:54.389146 SRAM_EN : 1
7112 18:07:54.392692 MD32_EN : 0
7113 18:07:54.395883 ===================================
7114 18:07:54.398746 [ANA_INIT] >>>>>>>>>>>>>>
7115 18:07:54.402478 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 18:07:54.405350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 18:07:54.409171 ===================================
7118 18:07:54.409267 data_rate = 3200,PCW = 0X7600
7119 18:07:54.412710 ===================================
7120 18:07:54.415865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 18:07:54.422249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 18:07:54.428838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 18:07:54.432676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 18:07:54.435369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 18:07:54.439018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 18:07:54.442256 [ANA_INIT] flow start
7127 18:07:54.445768 [ANA_INIT] PLL >>>>>>>>
7128 18:07:54.445946 [ANA_INIT] PLL <<<<<<<<
7129 18:07:54.448894 [ANA_INIT] MIDPI >>>>>>>>
7130 18:07:54.452260 [ANA_INIT] MIDPI <<<<<<<<
7131 18:07:54.452491 [ANA_INIT] DLL >>>>>>>>
7132 18:07:54.455177 [ANA_INIT] DLL <<<<<<<<
7133 18:07:54.458536 [ANA_INIT] flow end
7134 18:07:54.461793 ============ LP4 DIFF to SE enter ============
7135 18:07:54.465332 ============ LP4 DIFF to SE exit ============
7136 18:07:54.468816 [ANA_INIT] <<<<<<<<<<<<<
7137 18:07:54.471894 [Flow] Enable top DCM control >>>>>
7138 18:07:54.475367 [Flow] Enable top DCM control <<<<<
7139 18:07:54.478904 Enable DLL master slave shuffle
7140 18:07:54.482275 ==============================================================
7141 18:07:54.485847 Gating Mode config
7142 18:07:54.491933 ==============================================================
7143 18:07:54.492014 Config description:
7144 18:07:54.501678 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 18:07:54.508493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 18:07:54.512004 SELPH_MODE 0: By rank 1: By Phase
7147 18:07:54.518347 ==============================================================
7148 18:07:54.521696 GAT_TRACK_EN = 1
7149 18:07:54.524999 RX_GATING_MODE = 2
7150 18:07:54.528249 RX_GATING_TRACK_MODE = 2
7151 18:07:54.531859 SELPH_MODE = 1
7152 18:07:54.535236 PICG_EARLY_EN = 1
7153 18:07:54.535334 VALID_LAT_VALUE = 1
7154 18:07:54.542156 ==============================================================
7155 18:07:54.544925 Enter into Gating configuration >>>>
7156 18:07:54.548419 Exit from Gating configuration <<<<
7157 18:07:54.551855 Enter into DVFS_PRE_config >>>>>
7158 18:07:54.561984 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 18:07:54.565066 Exit from DVFS_PRE_config <<<<<
7160 18:07:54.568202 Enter into PICG configuration >>>>
7161 18:07:54.571544 Exit from PICG configuration <<<<
7162 18:07:54.574998 [RX_INPUT] configuration >>>>>
7163 18:07:54.578446 [RX_INPUT] configuration <<<<<
7164 18:07:54.582052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 18:07:54.588517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 18:07:54.594838 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 18:07:54.601224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 18:07:54.608257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 18:07:54.614795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 18:07:54.618039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 18:07:54.621000 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 18:07:54.624813 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 18:07:54.630994 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 18:07:54.634623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 18:07:54.637722 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 18:07:54.641175 ===================================
7177 18:07:54.644833 LPDDR4 DRAM CONFIGURATION
7178 18:07:54.647605 ===================================
7179 18:07:54.647686 EX_ROW_EN[0] = 0x0
7180 18:07:54.651067 EX_ROW_EN[1] = 0x0
7181 18:07:54.654730 LP4Y_EN = 0x0
7182 18:07:54.654810 WORK_FSP = 0x1
7183 18:07:54.657849 WL = 0x5
7184 18:07:54.657929 RL = 0x5
7185 18:07:54.660967 BL = 0x2
7186 18:07:54.661048 RPST = 0x0
7187 18:07:54.664482 RD_PRE = 0x0
7188 18:07:54.664563 WR_PRE = 0x1
7189 18:07:54.668005 WR_PST = 0x1
7190 18:07:54.668095 DBI_WR = 0x0
7191 18:07:54.670858 DBI_RD = 0x0
7192 18:07:54.670939 OTF = 0x1
7193 18:07:54.674320 ===================================
7194 18:07:54.677879 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 18:07:54.684601 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 18:07:54.687781 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 18:07:54.690691 ===================================
7198 18:07:54.694205 LPDDR4 DRAM CONFIGURATION
7199 18:07:54.697649 ===================================
7200 18:07:54.697731 EX_ROW_EN[0] = 0x10
7201 18:07:54.701013 EX_ROW_EN[1] = 0x0
7202 18:07:54.701122 LP4Y_EN = 0x0
7203 18:07:54.704679 WORK_FSP = 0x1
7204 18:07:54.707578 WL = 0x5
7205 18:07:54.707660 RL = 0x5
7206 18:07:54.711014 BL = 0x2
7207 18:07:54.711096 RPST = 0x0
7208 18:07:54.714572 RD_PRE = 0x0
7209 18:07:54.714653 WR_PRE = 0x1
7210 18:07:54.718035 WR_PST = 0x1
7211 18:07:54.718116 DBI_WR = 0x0
7212 18:07:54.720810 DBI_RD = 0x0
7213 18:07:54.720893 OTF = 0x1
7214 18:07:54.724198 ===================================
7215 18:07:54.730971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 18:07:54.731054 ==
7217 18:07:54.734430 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 18:07:54.737882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 18:07:54.737965 ==
7220 18:07:54.741241 [Duty_Offset_Calibration]
7221 18:07:54.744136 B0:2 B1:1 CA:1
7222 18:07:54.744244
7223 18:07:54.747590 [DutyScan_Calibration_Flow] k_type=0
7224 18:07:54.756275
7225 18:07:54.756384 ==CLK 0==
7226 18:07:54.759534 Final CLK duty delay cell = 0
7227 18:07:54.762695 [0] MAX Duty = 5187%(X100), DQS PI = 24
7228 18:07:54.765823 [0] MIN Duty = 4876%(X100), DQS PI = 48
7229 18:07:54.765905 [0] AVG Duty = 5031%(X100)
7230 18:07:54.769277
7231 18:07:54.772589 CH0 CLK Duty spec in!! Max-Min= 311%
7232 18:07:54.775655 [DutyScan_Calibration_Flow] ====Done====
7233 18:07:54.775737
7234 18:07:54.778856 [DutyScan_Calibration_Flow] k_type=1
7235 18:07:54.795235
7236 18:07:54.795345 ==DQS 0 ==
7237 18:07:54.798560 Final DQS duty delay cell = -4
7238 18:07:54.802000 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7239 18:07:54.804772 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7240 18:07:54.808293 [-4] AVG Duty = 4891%(X100)
7241 18:07:54.808431
7242 18:07:54.808496 ==DQS 1 ==
7243 18:07:54.811879 Final DQS duty delay cell = 0
7244 18:07:54.815342 [0] MAX Duty = 5187%(X100), DQS PI = 2
7245 18:07:54.818181 [0] MIN Duty = 5031%(X100), DQS PI = 52
7246 18:07:54.821778 [0] AVG Duty = 5109%(X100)
7247 18:07:54.821858
7248 18:07:54.825129 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7249 18:07:54.825210
7250 18:07:54.828553 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7251 18:07:54.831975 [DutyScan_Calibration_Flow] ====Done====
7252 18:07:54.832055
7253 18:07:54.835578 [DutyScan_Calibration_Flow] k_type=3
7254 18:07:54.852741
7255 18:07:54.852821 ==DQM 0 ==
7256 18:07:54.856138 Final DQM duty delay cell = 0
7257 18:07:54.859503 [0] MAX Duty = 5187%(X100), DQS PI = 32
7258 18:07:54.862472 [0] MIN Duty = 4907%(X100), DQS PI = 54
7259 18:07:54.862553 [0] AVG Duty = 5047%(X100)
7260 18:07:54.865765
7261 18:07:54.865845 ==DQM 1 ==
7262 18:07:54.869181 Final DQM duty delay cell = 0
7263 18:07:54.872749 [0] MAX Duty = 5187%(X100), DQS PI = 20
7264 18:07:54.876220 [0] MIN Duty = 5031%(X100), DQS PI = 50
7265 18:07:54.879019 [0] AVG Duty = 5109%(X100)
7266 18:07:54.879100
7267 18:07:54.882215 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7268 18:07:54.882296
7269 18:07:54.885788 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7270 18:07:54.889021 [DutyScan_Calibration_Flow] ====Done====
7271 18:07:54.889101
7272 18:07:54.892082 [DutyScan_Calibration_Flow] k_type=2
7273 18:07:54.909668
7274 18:07:54.909749 ==DQ 0 ==
7275 18:07:54.913287 Final DQ duty delay cell = 0
7276 18:07:54.916298 [0] MAX Duty = 5062%(X100), DQS PI = 26
7277 18:07:54.919513 [0] MIN Duty = 4907%(X100), DQS PI = 0
7278 18:07:54.919599 [0] AVG Duty = 4984%(X100)
7279 18:07:54.922855
7280 18:07:54.922940 ==DQ 1 ==
7281 18:07:54.926353 Final DQ duty delay cell = 0
7282 18:07:54.929809 [0] MAX Duty = 5125%(X100), DQS PI = 22
7283 18:07:54.933386 [0] MIN Duty = 4907%(X100), DQS PI = 34
7284 18:07:54.933486 [0] AVG Duty = 5016%(X100)
7285 18:07:54.933565
7286 18:07:54.936481 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7287 18:07:54.939763
7288 18:07:54.943125 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7289 18:07:54.946436 [DutyScan_Calibration_Flow] ====Done====
7290 18:07:54.946568 ==
7291 18:07:54.949594 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 18:07:54.953030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 18:07:54.953181 ==
7294 18:07:54.956495 [Duty_Offset_Calibration]
7295 18:07:54.956575 B0:1 B1:0 CA:0
7296 18:07:54.956638
7297 18:07:54.959504 [DutyScan_Calibration_Flow] k_type=0
7298 18:07:54.968995
7299 18:07:54.969094 ==CLK 0==
7300 18:07:54.972382 Final CLK duty delay cell = -4
7301 18:07:54.976061 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7302 18:07:54.979629 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7303 18:07:54.982175 [-4] AVG Duty = 4906%(X100)
7304 18:07:54.982293
7305 18:07:54.985633 CH1 CLK Duty spec in!! Max-Min= 125%
7306 18:07:54.988918 [DutyScan_Calibration_Flow] ====Done====
7307 18:07:54.989078
7308 18:07:54.992335 [DutyScan_Calibration_Flow] k_type=1
7309 18:07:55.009015
7310 18:07:55.009405 ==DQS 0 ==
7311 18:07:55.012264 Final DQS duty delay cell = 0
7312 18:07:55.015966 [0] MAX Duty = 5094%(X100), DQS PI = 32
7313 18:07:55.019316 [0] MIN Duty = 4844%(X100), DQS PI = 2
7314 18:07:55.019800 [0] AVG Duty = 4969%(X100)
7315 18:07:55.022750
7316 18:07:55.023199 ==DQS 1 ==
7317 18:07:55.026013 Final DQS duty delay cell = 0
7318 18:07:55.029699 [0] MAX Duty = 5249%(X100), DQS PI = 16
7319 18:07:55.032966 [0] MIN Duty = 4938%(X100), DQS PI = 8
7320 18:07:55.033406 [0] AVG Duty = 5093%(X100)
7321 18:07:55.035840
7322 18:07:55.039003 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7323 18:07:55.039420
7324 18:07:55.042288 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7325 18:07:55.046236 [DutyScan_Calibration_Flow] ====Done====
7326 18:07:55.046644
7327 18:07:55.049315 [DutyScan_Calibration_Flow] k_type=3
7328 18:07:55.066189
7329 18:07:55.066601 ==DQM 0 ==
7330 18:07:55.069569 Final DQM duty delay cell = 0
7331 18:07:55.072942 [0] MAX Duty = 5187%(X100), DQS PI = 10
7332 18:07:55.076405 [0] MIN Duty = 4969%(X100), DQS PI = 48
7333 18:07:55.080045 [0] AVG Duty = 5078%(X100)
7334 18:07:55.080502
7335 18:07:55.080835 ==DQM 1 ==
7336 18:07:55.082614 Final DQM duty delay cell = 0
7337 18:07:55.086033 [0] MAX Duty = 5093%(X100), DQS PI = 16
7338 18:07:55.089509 [0] MIN Duty = 4907%(X100), DQS PI = 32
7339 18:07:55.092811 [0] AVG Duty = 5000%(X100)
7340 18:07:55.093220
7341 18:07:55.096421 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7342 18:07:55.096837
7343 18:07:55.099219 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7344 18:07:55.102713 [DutyScan_Calibration_Flow] ====Done====
7345 18:07:55.103124
7346 18:07:55.106170 [DutyScan_Calibration_Flow] k_type=2
7347 18:07:55.122533
7348 18:07:55.122938 ==DQ 0 ==
7349 18:07:55.125862 Final DQ duty delay cell = -4
7350 18:07:55.128670 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7351 18:07:55.132164 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7352 18:07:55.135386 [-4] AVG Duty = 4968%(X100)
7353 18:07:55.135835
7354 18:07:55.136468 ==DQ 1 ==
7355 18:07:55.138741 Final DQ duty delay cell = 0
7356 18:07:55.142257 [0] MAX Duty = 5124%(X100), DQS PI = 18
7357 18:07:55.145630 [0] MIN Duty = 4938%(X100), DQS PI = 8
7358 18:07:55.148686 [0] AVG Duty = 5031%(X100)
7359 18:07:55.149096
7360 18:07:55.152438 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7361 18:07:55.152850
7362 18:07:55.155520 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7363 18:07:55.158789 [DutyScan_Calibration_Flow] ====Done====
7364 18:07:55.161963 nWR fixed to 30
7365 18:07:55.165202 [ModeRegInit_LP4] CH0 RK0
7366 18:07:55.165620 [ModeRegInit_LP4] CH0 RK1
7367 18:07:55.168551 [ModeRegInit_LP4] CH1 RK0
7368 18:07:55.171851 [ModeRegInit_LP4] CH1 RK1
7369 18:07:55.172285 match AC timing 5
7370 18:07:55.178821 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 18:07:55.182074 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 18:07:55.185169 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 18:07:55.192143 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 18:07:55.195001 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 18:07:55.195594 [MiockJmeterHQA]
7376 18:07:55.196197
7377 18:07:55.198680 [DramcMiockJmeter] u1RxGatingPI = 0
7378 18:07:55.201681 0 : 4255, 4030
7379 18:07:55.202222 4 : 4258, 4029
7380 18:07:55.204886 8 : 4252, 4027
7381 18:07:55.205274 12 : 4254, 4029
7382 18:07:55.208447 16 : 4363, 4138
7383 18:07:55.208870 20 : 4252, 4027
7384 18:07:55.209236 24 : 4252, 4027
7385 18:07:55.212202 28 : 4252, 4027
7386 18:07:55.212773 32 : 4255, 4029
7387 18:07:55.215060 36 : 4252, 4027
7388 18:07:55.215485 40 : 4253, 4026
7389 18:07:55.218581 44 : 4366, 4140
7390 18:07:55.219237 48 : 4252, 4027
7391 18:07:55.219585 52 : 4255, 4029
7392 18:07:55.221790 56 : 4250, 4027
7393 18:07:55.222235 60 : 4360, 4137
7394 18:07:55.224885 64 : 4250, 4027
7395 18:07:55.225368 68 : 4361, 4137
7396 18:07:55.228303 72 : 4252, 4029
7397 18:07:55.229020 76 : 4250, 4027
7398 18:07:55.231441 80 : 4250, 4027
7399 18:07:55.231844 84 : 4253, 4029
7400 18:07:55.232186 88 : 4360, 220
7401 18:07:55.235049 92 : 4252, 0
7402 18:07:55.235371 96 : 4364, 0
7403 18:07:55.238547 100 : 4253, 0
7404 18:07:55.238776 104 : 4249, 0
7405 18:07:55.238960 108 : 4252, 0
7406 18:07:55.241249 112 : 4360, 0
7407 18:07:55.241478 116 : 4361, 0
7408 18:07:55.241658 120 : 4247, 0
7409 18:07:55.244558 124 : 4250, 0
7410 18:07:55.244837 128 : 4250, 0
7411 18:07:55.248103 132 : 4363, 0
7412 18:07:55.248337 136 : 4250, 0
7413 18:07:55.248704 140 : 4250, 0
7414 18:07:55.250931 144 : 4361, 0
7415 18:07:55.251261 148 : 4360, 0
7416 18:07:55.254699 152 : 4250, 0
7417 18:07:55.254928 156 : 4250, 0
7418 18:07:55.255110 160 : 4253, 0
7419 18:07:55.258041 164 : 4250, 0
7420 18:07:55.258376 168 : 4250, 0
7421 18:07:55.261600 172 : 4253, 0
7422 18:07:55.261836 176 : 4250, 0
7423 18:07:55.262087 180 : 4250, 0
7424 18:07:55.264192 184 : 4363, 0
7425 18:07:55.264491 188 : 4250, 0
7426 18:07:55.267829 192 : 4250, 0
7427 18:07:55.268056 196 : 4250, 0
7428 18:07:55.268320 200 : 4253, 0
7429 18:07:55.271307 204 : 4251, 1340
7430 18:07:55.271608 208 : 4250, 3976
7431 18:07:55.274854 212 : 4250, 4026
7432 18:07:55.275083 216 : 4250, 4027
7433 18:07:55.278464 220 : 4250, 4027
7434 18:07:55.278719 224 : 4250, 4026
7435 18:07:55.281155 228 : 4252, 4030
7436 18:07:55.281383 232 : 4250, 4027
7437 18:07:55.281565 236 : 4361, 4138
7438 18:07:55.284712 240 : 4360, 4137
7439 18:07:55.284944 244 : 4250, 4027
7440 18:07:55.288135 248 : 4363, 4140
7441 18:07:55.288444 252 : 4361, 4137
7442 18:07:55.290886 256 : 4250, 4027
7443 18:07:55.291192 260 : 4250, 4026
7444 18:07:55.294204 264 : 4252, 4030
7445 18:07:55.294431 268 : 4250, 4027
7446 18:07:55.298105 272 : 4250, 4027
7447 18:07:55.298348 276 : 4250, 4026
7448 18:07:55.301057 280 : 4252, 4029
7449 18:07:55.301283 284 : 4250, 4027
7450 18:07:55.304693 288 : 4360, 4137
7451 18:07:55.304919 292 : 4360, 4137
7452 18:07:55.305099 296 : 4247, 4025
7453 18:07:55.307894 300 : 4363, 4140
7454 18:07:55.308212 304 : 4360, 4137
7455 18:07:55.311252 308 : 4250, 3975
7456 18:07:55.311453 312 : 4250, 2102
7457 18:07:55.311703
7458 18:07:55.314624 MIOCK jitter meter ch=0
7459 18:07:55.315038
7460 18:07:55.317977 1T = (312-88) = 224 dly cells
7461 18:07:55.324979 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7462 18:07:55.325413 ==
7463 18:07:55.328139 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 18:07:55.331032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 18:07:55.331451 ==
7466 18:07:55.337559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 18:07:55.340779 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 18:07:55.344616 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 18:07:55.350757 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 18:07:55.359879 [CA 0] Center 42 (12~73) winsize 62
7471 18:07:55.363174 [CA 1] Center 42 (12~73) winsize 62
7472 18:07:55.366775 [CA 2] Center 37 (8~67) winsize 60
7473 18:07:55.369809 [CA 3] Center 37 (7~67) winsize 61
7474 18:07:55.373056 [CA 4] Center 36 (6~66) winsize 61
7475 18:07:55.376950 [CA 5] Center 35 (6~64) winsize 59
7476 18:07:55.377549
7477 18:07:55.379631 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 18:07:55.380146
7479 18:07:55.383056 [CATrainingPosCal] consider 1 rank data
7480 18:07:55.386652 u2DelayCellTimex100 = 290/100 ps
7481 18:07:55.390332 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 18:07:55.396696 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 18:07:55.400150 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7484 18:07:55.403122 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 18:07:55.406426 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 18:07:55.410048 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 18:07:55.410273
7488 18:07:55.413546 CA PerBit enable=1, Macro0, CA PI delay=35
7489 18:07:55.413836
7490 18:07:55.416796 [CBTSetCACLKResult] CA Dly = 35
7491 18:07:55.417079 CS Dly: 9 (0~40)
7492 18:07:55.423074 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 18:07:55.426385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 18:07:55.426677 ==
7495 18:07:55.429529 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 18:07:55.433132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 18:07:55.433446 ==
7498 18:07:55.439904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 18:07:55.442776 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 18:07:55.449920 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 18:07:55.452922 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 18:07:55.462519 [CA 0] Center 42 (12~73) winsize 62
7503 18:07:55.466326 [CA 1] Center 42 (12~73) winsize 62
7504 18:07:55.469591 [CA 2] Center 38 (8~68) winsize 61
7505 18:07:55.472846 [CA 3] Center 38 (8~68) winsize 61
7506 18:07:55.476551 [CA 4] Center 35 (6~65) winsize 60
7507 18:07:55.479558 [CA 5] Center 35 (5~65) winsize 61
7508 18:07:55.479664
7509 18:07:55.482659 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 18:07:55.482762
7511 18:07:55.486329 [CATrainingPosCal] consider 2 rank data
7512 18:07:55.489857 u2DelayCellTimex100 = 290/100 ps
7513 18:07:55.492711 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7514 18:07:55.500003 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 18:07:55.502743 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 18:07:55.506416 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 18:07:55.509957 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7518 18:07:55.512975 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 18:07:55.513494
7520 18:07:55.516510 CA PerBit enable=1, Macro0, CA PI delay=35
7521 18:07:55.516927
7522 18:07:55.519818 [CBTSetCACLKResult] CA Dly = 35
7523 18:07:55.523228 CS Dly: 10 (0~42)
7524 18:07:55.526477 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 18:07:55.529324 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 18:07:55.529874
7527 18:07:55.532801 ----->DramcWriteLeveling(PI) begin...
7528 18:07:55.533332 ==
7529 18:07:55.536310 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 18:07:55.543050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 18:07:55.543469 ==
7532 18:07:55.546492 Write leveling (Byte 0): 34 => 34
7533 18:07:55.546910 Write leveling (Byte 1): 29 => 29
7534 18:07:55.549855 DramcWriteLeveling(PI) end<-----
7535 18:07:55.550273
7536 18:07:55.550601 ==
7537 18:07:55.552669 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 18:07:55.559400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 18:07:55.559818 ==
7540 18:07:55.562741 [Gating] SW mode calibration
7541 18:07:55.569293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 18:07:55.572472 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 18:07:55.579222 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 18:07:55.582694 1 4 4 | B1->B0 | 2323 2221 | 0 1 | (0 0) (0 0)
7545 18:07:55.586080 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7546 18:07:55.592963 1 4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7547 18:07:55.596263 1 4 16 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7548 18:07:55.599295 1 4 20 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
7549 18:07:55.606020 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7550 18:07:55.609560 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7551 18:07:55.612448 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7552 18:07:55.615966 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7553 18:07:55.622944 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 18:07:55.626353 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7555 18:07:55.629112 1 5 16 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
7556 18:07:55.636103 1 5 20 | B1->B0 | 2424 2424 | 1 0 | (1 0) (0 0)
7557 18:07:55.638912 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7558 18:07:55.642286 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7559 18:07:55.649471 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7560 18:07:55.652709 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 18:07:55.655605 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7562 18:07:55.662643 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 18:07:55.665923 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7564 18:07:55.669669 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 18:07:55.675803 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 18:07:55.678792 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 18:07:55.682433 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 18:07:55.688742 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 18:07:55.692064 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 18:07:55.695519 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 18:07:55.701966 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7572 18:07:55.705361 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 18:07:55.708736 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 18:07:55.715625 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 18:07:55.719061 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 18:07:55.722197 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 18:07:55.728889 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 18:07:55.732183 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 18:07:55.735307 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 18:07:55.741977 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 18:07:55.745337 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 18:07:55.748808 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 18:07:55.754947 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 18:07:55.758714 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 18:07:55.761968 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 18:07:55.768310 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 18:07:55.771758 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7588 18:07:55.775173 Total UI for P1: 0, mck2ui 16
7589 18:07:55.778668 best dqsien dly found for B0: ( 1, 9, 10)
7590 18:07:55.782068 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 18:07:55.784874 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 18:07:55.788645 Total UI for P1: 0, mck2ui 16
7593 18:07:55.792306 best dqsien dly found for B1: ( 1, 9, 20)
7594 18:07:55.794922 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 18:07:55.801784 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7596 18:07:55.802370
7597 18:07:55.804676 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 18:07:55.808030 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7599 18:07:55.811773 [Gating] SW calibration Done
7600 18:07:55.812380 ==
7601 18:07:55.815045 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 18:07:55.818138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 18:07:55.818696 ==
7604 18:07:55.821845 RX Vref Scan: 0
7605 18:07:55.822417
7606 18:07:55.822947 RX Vref 0 -> 0, step: 1
7607 18:07:55.823438
7608 18:07:55.824737 RX Delay 0 -> 252, step: 8
7609 18:07:55.828015 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 18:07:55.831404 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 18:07:55.838170 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7612 18:07:55.841521 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 18:07:55.845018 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 18:07:55.847907 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 18:07:55.851421 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 18:07:55.858028 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 18:07:55.861615 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 18:07:55.864587 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7619 18:07:55.867902 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 18:07:55.871571 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 18:07:55.877927 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7622 18:07:55.881325 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7623 18:07:55.884760 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7624 18:07:55.887686 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 18:07:55.888299 ==
7626 18:07:55.891095 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 18:07:55.897144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 18:07:55.897253 ==
7629 18:07:55.897377 DQS Delay:
7630 18:07:55.900728 DQS0 = 0, DQS1 = 0
7631 18:07:55.900811 DQM Delay:
7632 18:07:55.900876 DQM0 = 137, DQM1 = 131
7633 18:07:55.904166 DQ Delay:
7634 18:07:55.907120 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7635 18:07:55.910595 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7636 18:07:55.914128 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7637 18:07:55.917077 DQ12 =135, DQ13 =139, DQ14 =143, DQ15 =135
7638 18:07:55.917157
7639 18:07:55.917228
7640 18:07:55.917293 ==
7641 18:07:55.920573 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 18:07:55.927493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 18:07:55.927595 ==
7644 18:07:55.927676
7645 18:07:55.927751
7646 18:07:55.927831 TX Vref Scan disable
7647 18:07:55.930472 == TX Byte 0 ==
7648 18:07:55.933803 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7649 18:07:55.937112 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7650 18:07:55.940113 == TX Byte 1 ==
7651 18:07:55.943519 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7652 18:07:55.947119 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7653 18:07:55.950494 ==
7654 18:07:55.953741 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 18:07:55.957197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 18:07:55.957280 ==
7657 18:07:55.969560
7658 18:07:55.973180 TX Vref early break, caculate TX vref
7659 18:07:55.976128 TX Vref=16, minBit 4, minWin=23, winSum=378
7660 18:07:55.979713 TX Vref=18, minBit 7, minWin=23, winSum=387
7661 18:07:55.982637 TX Vref=20, minBit 0, minWin=24, winSum=398
7662 18:07:55.986671 TX Vref=22, minBit 0, minWin=24, winSum=407
7663 18:07:55.989285 TX Vref=24, minBit 3, minWin=25, winSum=421
7664 18:07:55.996236 TX Vref=26, minBit 1, minWin=26, winSum=429
7665 18:07:55.999357 TX Vref=28, minBit 1, minWin=25, winSum=424
7666 18:07:56.003025 TX Vref=30, minBit 6, minWin=24, winSum=414
7667 18:07:56.006255 TX Vref=32, minBit 6, minWin=24, winSum=408
7668 18:07:56.009662 TX Vref=34, minBit 6, minWin=22, winSum=393
7669 18:07:56.016024 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
7670 18:07:56.016132
7671 18:07:56.019571 Final TX Range 0 Vref 26
7672 18:07:56.019674
7673 18:07:56.019754 ==
7674 18:07:56.022774 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 18:07:56.026123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 18:07:56.026235 ==
7677 18:07:56.026322
7678 18:07:56.026414
7679 18:07:56.028981 TX Vref Scan disable
7680 18:07:56.035831 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7681 18:07:56.035912 == TX Byte 0 ==
7682 18:07:56.039201 u2DelayCellOfst[0]=10 cells (3 PI)
7683 18:07:56.043095 u2DelayCellOfst[1]=13 cells (4 PI)
7684 18:07:56.046223 u2DelayCellOfst[2]=10 cells (3 PI)
7685 18:07:56.049084 u2DelayCellOfst[3]=10 cells (3 PI)
7686 18:07:56.052540 u2DelayCellOfst[4]=10 cells (3 PI)
7687 18:07:56.056064 u2DelayCellOfst[5]=0 cells (0 PI)
7688 18:07:56.059424 u2DelayCellOfst[6]=16 cells (5 PI)
7689 18:07:56.062797 u2DelayCellOfst[7]=13 cells (4 PI)
7690 18:07:56.066039 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7691 18:07:56.069441 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7692 18:07:56.072263 == TX Byte 1 ==
7693 18:07:56.072412 u2DelayCellOfst[8]=0 cells (0 PI)
7694 18:07:56.075769 u2DelayCellOfst[9]=0 cells (0 PI)
7695 18:07:56.079195 u2DelayCellOfst[10]=6 cells (2 PI)
7696 18:07:56.082846 u2DelayCellOfst[11]=6 cells (2 PI)
7697 18:07:56.086380 u2DelayCellOfst[12]=10 cells (3 PI)
7698 18:07:56.089111 u2DelayCellOfst[13]=10 cells (3 PI)
7699 18:07:56.092427 u2DelayCellOfst[14]=13 cells (4 PI)
7700 18:07:56.095481 u2DelayCellOfst[15]=10 cells (3 PI)
7701 18:07:56.099320 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7702 18:07:56.105669 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7703 18:07:56.105773 DramC Write-DBI on
7704 18:07:56.105871 ==
7705 18:07:56.108767 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 18:07:56.112439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 18:07:56.115579 ==
7708 18:07:56.115659
7709 18:07:56.115721
7710 18:07:56.115781 TX Vref Scan disable
7711 18:07:56.119265 == TX Byte 0 ==
7712 18:07:56.122216 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7713 18:07:56.125557 == TX Byte 1 ==
7714 18:07:56.129356 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7715 18:07:56.132768 DramC Write-DBI off
7716 18:07:56.132848
7717 18:07:56.132911 [DATLAT]
7718 18:07:56.132969 Freq=1600, CH0 RK0
7719 18:07:56.133025
7720 18:07:56.135594 DATLAT Default: 0xf
7721 18:07:56.135674 0, 0xFFFF, sum = 0
7722 18:07:56.139160 1, 0xFFFF, sum = 0
7723 18:07:56.139241 2, 0xFFFF, sum = 0
7724 18:07:56.142547 3, 0xFFFF, sum = 0
7725 18:07:56.145690 4, 0xFFFF, sum = 0
7726 18:07:56.145771 5, 0xFFFF, sum = 0
7727 18:07:56.148798 6, 0xFFFF, sum = 0
7728 18:07:56.148879 7, 0xFFFF, sum = 0
7729 18:07:56.152558 8, 0xFFFF, sum = 0
7730 18:07:56.152653 9, 0xFFFF, sum = 0
7731 18:07:56.155310 10, 0xFFFF, sum = 0
7732 18:07:56.155391 11, 0xFFFF, sum = 0
7733 18:07:56.158789 12, 0xFFFF, sum = 0
7734 18:07:56.158871 13, 0xFFFF, sum = 0
7735 18:07:56.162281 14, 0x0, sum = 1
7736 18:07:56.162363 15, 0x0, sum = 2
7737 18:07:56.165729 16, 0x0, sum = 3
7738 18:07:56.165810 17, 0x0, sum = 4
7739 18:07:56.168939 best_step = 15
7740 18:07:56.169018
7741 18:07:56.169081 ==
7742 18:07:56.172009 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 18:07:56.175492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 18:07:56.175575 ==
7745 18:07:56.179025 RX Vref Scan: 1
7746 18:07:56.179104
7747 18:07:56.179167 Set Vref Range= 24 -> 127
7748 18:07:56.179226
7749 18:07:56.181873 RX Vref 24 -> 127, step: 1
7750 18:07:56.181963
7751 18:07:56.185403 RX Delay 27 -> 252, step: 4
7752 18:07:56.185484
7753 18:07:56.188676 Set Vref, RX VrefLevel [Byte0]: 24
7754 18:07:56.192135 [Byte1]: 24
7755 18:07:56.192207
7756 18:07:56.195506 Set Vref, RX VrefLevel [Byte0]: 25
7757 18:07:56.198346 [Byte1]: 25
7758 18:07:56.201678
7759 18:07:56.201755 Set Vref, RX VrefLevel [Byte0]: 26
7760 18:07:56.205037 [Byte1]: 26
7761 18:07:56.209122
7762 18:07:56.209222 Set Vref, RX VrefLevel [Byte0]: 27
7763 18:07:56.212671 [Byte1]: 27
7764 18:07:56.216574
7765 18:07:56.216652 Set Vref, RX VrefLevel [Byte0]: 28
7766 18:07:56.220116 [Byte1]: 28
7767 18:07:56.224229
7768 18:07:56.224326 Set Vref, RX VrefLevel [Byte0]: 29
7769 18:07:56.227569 [Byte1]: 29
7770 18:07:56.232138
7771 18:07:56.232241 Set Vref, RX VrefLevel [Byte0]: 30
7772 18:07:56.234980 [Byte1]: 30
7773 18:07:56.239534
7774 18:07:56.239604 Set Vref, RX VrefLevel [Byte0]: 31
7775 18:07:56.242425 [Byte1]: 31
7776 18:07:56.247012
7777 18:07:56.247125 Set Vref, RX VrefLevel [Byte0]: 32
7778 18:07:56.250433 [Byte1]: 32
7779 18:07:56.254536
7780 18:07:56.254636 Set Vref, RX VrefLevel [Byte0]: 33
7781 18:07:56.257886 [Byte1]: 33
7782 18:07:56.261998
7783 18:07:56.262089 Set Vref, RX VrefLevel [Byte0]: 34
7784 18:07:56.265322 [Byte1]: 34
7785 18:07:56.269619
7786 18:07:56.269722 Set Vref, RX VrefLevel [Byte0]: 35
7787 18:07:56.272990 [Byte1]: 35
7788 18:07:56.276819
7789 18:07:56.276929 Set Vref, RX VrefLevel [Byte0]: 36
7790 18:07:56.280060 [Byte1]: 36
7791 18:07:56.284908
7792 18:07:56.284987 Set Vref, RX VrefLevel [Byte0]: 37
7793 18:07:56.287689 [Byte1]: 37
7794 18:07:56.291881
7795 18:07:56.291987 Set Vref, RX VrefLevel [Byte0]: 38
7796 18:07:56.295200 [Byte1]: 38
7797 18:07:56.299423
7798 18:07:56.299526 Set Vref, RX VrefLevel [Byte0]: 39
7799 18:07:56.302930 [Byte1]: 39
7800 18:07:56.307092
7801 18:07:56.307208 Set Vref, RX VrefLevel [Byte0]: 40
7802 18:07:56.310699 [Byte1]: 40
7803 18:07:56.314621
7804 18:07:56.314707 Set Vref, RX VrefLevel [Byte0]: 41
7805 18:07:56.318312 [Byte1]: 41
7806 18:07:56.322287
7807 18:07:56.322367 Set Vref, RX VrefLevel [Byte0]: 42
7808 18:07:56.325850 [Byte1]: 42
7809 18:07:56.329988
7810 18:07:56.330067 Set Vref, RX VrefLevel [Byte0]: 43
7811 18:07:56.333441 [Byte1]: 43
7812 18:07:56.337543
7813 18:07:56.337624 Set Vref, RX VrefLevel [Byte0]: 44
7814 18:07:56.340824 [Byte1]: 44
7815 18:07:56.345159
7816 18:07:56.345262 Set Vref, RX VrefLevel [Byte0]: 45
7817 18:07:56.347924 [Byte1]: 45
7818 18:07:56.352652
7819 18:07:56.352732 Set Vref, RX VrefLevel [Byte0]: 46
7820 18:07:56.355991 [Byte1]: 46
7821 18:07:56.359833
7822 18:07:56.359913 Set Vref, RX VrefLevel [Byte0]: 47
7823 18:07:56.363539 [Byte1]: 47
7824 18:07:56.368022
7825 18:07:56.368101 Set Vref, RX VrefLevel [Byte0]: 48
7826 18:07:56.370920 [Byte1]: 48
7827 18:07:56.374948
7828 18:07:56.375027 Set Vref, RX VrefLevel [Byte0]: 49
7829 18:07:56.378274 [Byte1]: 49
7830 18:07:56.382559
7831 18:07:56.382645 Set Vref, RX VrefLevel [Byte0]: 50
7832 18:07:56.386096 [Byte1]: 50
7833 18:07:56.390456
7834 18:07:56.390555 Set Vref, RX VrefLevel [Byte0]: 51
7835 18:07:56.393602 [Byte1]: 51
7836 18:07:56.397755
7837 18:07:56.397863 Set Vref, RX VrefLevel [Byte0]: 52
7838 18:07:56.401766 [Byte1]: 52
7839 18:07:56.405671
7840 18:07:56.406081 Set Vref, RX VrefLevel [Byte0]: 53
7841 18:07:56.409019 [Byte1]: 53
7842 18:07:56.413131
7843 18:07:56.416628 Set Vref, RX VrefLevel [Byte0]: 54
7844 18:07:56.417042 [Byte1]: 54
7845 18:07:56.420628
7846 18:07:56.421039 Set Vref, RX VrefLevel [Byte0]: 55
7847 18:07:56.424033 [Byte1]: 55
7848 18:07:56.428040
7849 18:07:56.428524 Set Vref, RX VrefLevel [Byte0]: 56
7850 18:07:56.431693 [Byte1]: 56
7851 18:07:56.435737
7852 18:07:56.436146 Set Vref, RX VrefLevel [Byte0]: 57
7853 18:07:56.438569 [Byte1]: 57
7854 18:07:56.443480
7855 18:07:56.443917 Set Vref, RX VrefLevel [Byte0]: 58
7856 18:07:56.446230 [Byte1]: 58
7857 18:07:56.450446
7858 18:07:56.450872 Set Vref, RX VrefLevel [Byte0]: 59
7859 18:07:56.454058 [Byte1]: 59
7860 18:07:56.458316
7861 18:07:56.458749 Set Vref, RX VrefLevel [Byte0]: 60
7862 18:07:56.461836 [Byte1]: 60
7863 18:07:56.466010
7864 18:07:56.466451 Set Vref, RX VrefLevel [Byte0]: 61
7865 18:07:56.469343 [Byte1]: 61
7866 18:07:56.473283
7867 18:07:56.473735 Set Vref, RX VrefLevel [Byte0]: 62
7868 18:07:56.476706 [Byte1]: 62
7869 18:07:56.480830
7870 18:07:56.481248 Set Vref, RX VrefLevel [Byte0]: 63
7871 18:07:56.484401 [Byte1]: 63
7872 18:07:56.488492
7873 18:07:56.488911 Set Vref, RX VrefLevel [Byte0]: 64
7874 18:07:56.491464 [Byte1]: 64
7875 18:07:56.495697
7876 18:07:56.496117 Set Vref, RX VrefLevel [Byte0]: 65
7877 18:07:56.499091 [Byte1]: 65
7878 18:07:56.503411
7879 18:07:56.503925 Set Vref, RX VrefLevel [Byte0]: 66
7880 18:07:56.506771 [Byte1]: 66
7881 18:07:56.510699
7882 18:07:56.511123 Set Vref, RX VrefLevel [Byte0]: 67
7883 18:07:56.514313 [Byte1]: 67
7884 18:07:56.518228
7885 18:07:56.518648 Set Vref, RX VrefLevel [Byte0]: 68
7886 18:07:56.522044 [Byte1]: 68
7887 18:07:56.526225
7888 18:07:56.526847 Set Vref, RX VrefLevel [Byte0]: 69
7889 18:07:56.529701 [Byte1]: 69
7890 18:07:56.533334
7891 18:07:56.533837 Set Vref, RX VrefLevel [Byte0]: 70
7892 18:07:56.537117 [Byte1]: 70
7893 18:07:56.540992
7894 18:07:56.541414 Set Vref, RX VrefLevel [Byte0]: 71
7895 18:07:56.547301 [Byte1]: 71
7896 18:07:56.547785
7897 18:07:56.550952 Set Vref, RX VrefLevel [Byte0]: 72
7898 18:07:56.554350 [Byte1]: 72
7899 18:07:56.554985
7900 18:07:56.557308 Set Vref, RX VrefLevel [Byte0]: 73
7901 18:07:56.560780 [Byte1]: 73
7902 18:07:56.561203
7903 18:07:56.564329 Final RX Vref Byte 0 = 56 to rank0
7904 18:07:56.568004 Final RX Vref Byte 1 = 61 to rank0
7905 18:07:56.570711 Final RX Vref Byte 0 = 56 to rank1
7906 18:07:56.574090 Final RX Vref Byte 1 = 61 to rank1==
7907 18:07:56.577557 Dram Type= 6, Freq= 0, CH_0, rank 0
7908 18:07:56.580906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7909 18:07:56.584140 ==
7910 18:07:56.584608 DQS Delay:
7911 18:07:56.584944 DQS0 = 0, DQS1 = 0
7912 18:07:56.587859 DQM Delay:
7913 18:07:56.588307 DQM0 = 133, DQM1 = 127
7914 18:07:56.590480 DQ Delay:
7915 18:07:56.593909 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7916 18:07:56.597472 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7917 18:07:56.601045 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7918 18:07:56.603904 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7919 18:07:56.604324
7920 18:07:56.604706
7921 18:07:56.605013
7922 18:07:56.607347 [DramC_TX_OE_Calibration] TA2
7923 18:07:56.610664 Original DQ_B0 (3 6) =30, OEN = 27
7924 18:07:56.614051 Original DQ_B1 (3 6) =30, OEN = 27
7925 18:07:56.614524 24, 0x0, End_B0=24 End_B1=24
7926 18:07:56.617315 25, 0x0, End_B0=25 End_B1=25
7927 18:07:56.620805 26, 0x0, End_B0=26 End_B1=26
7928 18:07:56.623932 27, 0x0, End_B0=27 End_B1=27
7929 18:07:56.627245 28, 0x0, End_B0=28 End_B1=28
7930 18:07:56.627862 29, 0x0, End_B0=29 End_B1=29
7931 18:07:56.630840 30, 0x0, End_B0=30 End_B1=30
7932 18:07:56.633908 31, 0x4141, End_B0=30 End_B1=30
7933 18:07:56.636976 Byte0 end_step=30 best_step=27
7934 18:07:56.640401 Byte1 end_step=30 best_step=27
7935 18:07:56.643604 Byte0 TX OE(2T, 0.5T) = (3, 3)
7936 18:07:56.644220 Byte1 TX OE(2T, 0.5T) = (3, 3)
7937 18:07:56.644782
7938 18:07:56.646999
7939 18:07:56.653743 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7940 18:07:56.656957 CH0 RK0: MR19=303, MR18=2622
7941 18:07:56.663617 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7942 18:07:56.664200
7943 18:07:56.666959 ----->DramcWriteLeveling(PI) begin...
7944 18:07:56.667536 ==
7945 18:07:56.670223 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 18:07:56.673645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 18:07:56.674099 ==
7948 18:07:56.677092 Write leveling (Byte 0): 34 => 34
7949 18:07:56.680181 Write leveling (Byte 1): 25 => 25
7950 18:07:56.683664 DramcWriteLeveling(PI) end<-----
7951 18:07:56.684099
7952 18:07:56.684573 ==
7953 18:07:56.686991 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 18:07:56.690162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 18:07:56.690733 ==
7956 18:07:56.693534 [Gating] SW mode calibration
7957 18:07:56.700477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7958 18:07:56.706759 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7959 18:07:56.710315 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7960 18:07:56.713849 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7961 18:07:56.720633 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7962 18:07:56.723705 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7963 18:07:56.726570 1 4 16 | B1->B0 | 2f2f 3636 | 0 1 | (0 0) (1 1)
7964 18:07:56.733701 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7965 18:07:56.737169 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7966 18:07:56.740771 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7967 18:07:56.747287 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7968 18:07:56.750135 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7969 18:07:56.753672 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7970 18:07:56.756939 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
7971 18:07:56.763526 1 5 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)
7972 18:07:56.767482 1 5 20 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7973 18:07:56.770105 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7974 18:07:56.777022 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7975 18:07:56.780049 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7976 18:07:56.783231 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7977 18:07:56.790225 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7978 18:07:56.793511 1 6 12 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
7979 18:07:56.796840 1 6 16 | B1->B0 | 3f3f 4645 | 0 1 | (0 0) (0 0)
7980 18:07:56.803438 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7981 18:07:56.806422 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 18:07:56.810292 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 18:07:56.816984 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 18:07:56.819873 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 18:07:56.823394 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 18:07:56.829668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
7987 18:07:56.833512 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7988 18:07:56.836259 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 18:07:56.843160 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 18:07:56.846675 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 18:07:56.849490 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 18:07:56.856395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 18:07:56.859697 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 18:07:56.863124 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 18:07:56.869279 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 18:07:56.872616 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 18:07:56.876284 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 18:07:56.882987 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 18:07:56.886658 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 18:07:56.889469 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 18:07:56.896059 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8002 18:07:56.899193 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8003 18:07:56.902922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8004 18:07:56.905884 Total UI for P1: 0, mck2ui 16
8005 18:07:56.909319 best dqsien dly found for B0: ( 1, 9, 10)
8006 18:07:56.912617 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 18:07:56.915950 Total UI for P1: 0, mck2ui 16
8008 18:07:56.919158 best dqsien dly found for B1: ( 1, 9, 16)
8009 18:07:56.922862 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8010 18:07:56.929653 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8011 18:07:56.930058
8012 18:07:56.932824 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8013 18:07:56.935903 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8014 18:07:56.939803 [Gating] SW calibration Done
8015 18:07:56.940217 ==
8016 18:07:56.942943 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 18:07:56.946027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 18:07:56.946449 ==
8019 18:07:56.949617 RX Vref Scan: 0
8020 18:07:56.950132
8021 18:07:56.950469 RX Vref 0 -> 0, step: 1
8022 18:07:56.950781
8023 18:07:56.953314 RX Delay 0 -> 252, step: 8
8024 18:07:56.956419 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8025 18:07:56.960006 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8026 18:07:56.966212 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8027 18:07:56.969698 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8028 18:07:56.973355 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8029 18:07:56.976274 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8030 18:07:56.979247 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8031 18:07:56.985675 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8032 18:07:56.989178 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8033 18:07:56.992740 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8034 18:07:56.996525 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8035 18:07:56.999014 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8036 18:07:57.006231 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8037 18:07:57.009662 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8038 18:07:57.012329 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8039 18:07:57.015694 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8040 18:07:57.016158 ==
8041 18:07:57.019333 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 18:07:57.025755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 18:07:57.026226 ==
8044 18:07:57.026599 DQS Delay:
8045 18:07:57.028990 DQS0 = 0, DQS1 = 0
8046 18:07:57.029447 DQM Delay:
8047 18:07:57.032480 DQM0 = 137, DQM1 = 130
8048 18:07:57.032994 DQ Delay:
8049 18:07:57.035426 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8050 18:07:57.039283 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8051 18:07:57.042759 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8052 18:07:57.045886 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8053 18:07:57.046313
8054 18:07:57.046640
8055 18:07:57.046946 ==
8056 18:07:57.048583 Dram Type= 6, Freq= 0, CH_0, rank 1
8057 18:07:57.055600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8058 18:07:57.056117 ==
8059 18:07:57.056497
8060 18:07:57.056809
8061 18:07:57.057106 TX Vref Scan disable
8062 18:07:57.058842 == TX Byte 0 ==
8063 18:07:57.062359 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8064 18:07:57.069025 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8065 18:07:57.069535 == TX Byte 1 ==
8066 18:07:57.072138 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8067 18:07:57.079201 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8068 18:07:57.079745 ==
8069 18:07:57.082061 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 18:07:57.085401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 18:07:57.085877 ==
8072 18:07:57.098485
8073 18:07:57.101901 TX Vref early break, caculate TX vref
8074 18:07:57.105416 TX Vref=16, minBit 7, minWin=22, winSum=384
8075 18:07:57.109037 TX Vref=18, minBit 0, minWin=23, winSum=393
8076 18:07:57.111637 TX Vref=20, minBit 1, minWin=24, winSum=408
8077 18:07:57.115325 TX Vref=22, minBit 1, minWin=25, winSum=415
8078 18:07:57.118705 TX Vref=24, minBit 1, minWin=25, winSum=419
8079 18:07:57.125480 TX Vref=26, minBit 1, minWin=25, winSum=430
8080 18:07:57.128435 TX Vref=28, minBit 1, minWin=25, winSum=426
8081 18:07:57.132158 TX Vref=30, minBit 1, minWin=25, winSum=418
8082 18:07:57.135307 TX Vref=32, minBit 0, minWin=24, winSum=410
8083 18:07:57.138578 TX Vref=34, minBit 1, minWin=24, winSum=404
8084 18:07:57.144987 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8085 18:07:57.145326
8086 18:07:57.148722 Final TX Range 0 Vref 26
8087 18:07:57.149022
8088 18:07:57.149257 ==
8089 18:07:57.151532 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 18:07:57.155453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 18:07:57.155753 ==
8092 18:07:57.155990
8093 18:07:57.156211
8094 18:07:57.158938 TX Vref Scan disable
8095 18:07:57.165742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8096 18:07:57.166262 == TX Byte 0 ==
8097 18:07:57.169027 u2DelayCellOfst[0]=13 cells (4 PI)
8098 18:07:57.172537 u2DelayCellOfst[1]=16 cells (5 PI)
8099 18:07:57.175368 u2DelayCellOfst[2]=10 cells (3 PI)
8100 18:07:57.178506 u2DelayCellOfst[3]=10 cells (3 PI)
8101 18:07:57.182472 u2DelayCellOfst[4]=6 cells (2 PI)
8102 18:07:57.185040 u2DelayCellOfst[5]=0 cells (0 PI)
8103 18:07:57.188626 u2DelayCellOfst[6]=16 cells (5 PI)
8104 18:07:57.189237 u2DelayCellOfst[7]=13 cells (4 PI)
8105 18:07:57.195147 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8106 18:07:57.198676 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8107 18:07:57.199210 == TX Byte 1 ==
8108 18:07:57.201888 u2DelayCellOfst[8]=3 cells (1 PI)
8109 18:07:57.205353 u2DelayCellOfst[9]=0 cells (0 PI)
8110 18:07:57.208804 u2DelayCellOfst[10]=6 cells (2 PI)
8111 18:07:57.211902 u2DelayCellOfst[11]=6 cells (2 PI)
8112 18:07:57.215344 u2DelayCellOfst[12]=10 cells (3 PI)
8113 18:07:57.219273 u2DelayCellOfst[13]=13 cells (4 PI)
8114 18:07:57.221651 u2DelayCellOfst[14]=16 cells (5 PI)
8115 18:07:57.224903 u2DelayCellOfst[15]=10 cells (3 PI)
8116 18:07:57.228539 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8117 18:07:57.235367 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8118 18:07:57.235914 DramC Write-DBI on
8119 18:07:57.236276 ==
8120 18:07:57.238742 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 18:07:57.241998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 18:07:57.242566 ==
8123 18:07:57.245138
8124 18:07:57.245615
8125 18:07:57.245980 TX Vref Scan disable
8126 18:07:57.248335 == TX Byte 0 ==
8127 18:07:57.251533 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8128 18:07:57.254944 == TX Byte 1 ==
8129 18:07:57.258690 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8130 18:07:57.261823 DramC Write-DBI off
8131 18:07:57.262242
8132 18:07:57.262580 [DATLAT]
8133 18:07:57.263086 Freq=1600, CH0 RK1
8134 18:07:57.263420
8135 18:07:57.265532 DATLAT Default: 0xf
8136 18:07:57.266047 0, 0xFFFF, sum = 0
8137 18:07:57.269047 1, 0xFFFF, sum = 0
8138 18:07:57.269573 2, 0xFFFF, sum = 0
8139 18:07:57.271893 3, 0xFFFF, sum = 0
8140 18:07:57.275347 4, 0xFFFF, sum = 0
8141 18:07:57.275868 5, 0xFFFF, sum = 0
8142 18:07:57.278728 6, 0xFFFF, sum = 0
8143 18:07:57.279243 7, 0xFFFF, sum = 0
8144 18:07:57.281660 8, 0xFFFF, sum = 0
8145 18:07:57.282183 9, 0xFFFF, sum = 0
8146 18:07:57.285454 10, 0xFFFF, sum = 0
8147 18:07:57.285906 11, 0xFFFF, sum = 0
8148 18:07:57.288231 12, 0xFFFF, sum = 0
8149 18:07:57.288683 13, 0xFFFF, sum = 0
8150 18:07:57.291760 14, 0x0, sum = 1
8151 18:07:57.292187 15, 0x0, sum = 2
8152 18:07:57.294864 16, 0x0, sum = 3
8153 18:07:57.295289 17, 0x0, sum = 4
8154 18:07:57.298883 best_step = 15
8155 18:07:57.299399
8156 18:07:57.299732 ==
8157 18:07:57.301702 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 18:07:57.305208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 18:07:57.305631 ==
8160 18:07:57.305966 RX Vref Scan: 0
8161 18:07:57.308451
8162 18:07:57.308867 RX Vref 0 -> 0, step: 1
8163 18:07:57.309205
8164 18:07:57.311269 RX Delay 19 -> 252, step: 4
8165 18:07:57.315114 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8166 18:07:57.321930 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8167 18:07:57.324480 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8168 18:07:57.328081 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8169 18:07:57.331462 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8170 18:07:57.334549 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8171 18:07:57.341779 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8172 18:07:57.344414 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8173 18:07:57.347716 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8174 18:07:57.351262 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8175 18:07:57.354378 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8176 18:07:57.361560 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8177 18:07:57.364742 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8178 18:07:57.367494 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8179 18:07:57.370996 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8180 18:07:57.374513 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8181 18:07:57.377863 ==
8182 18:07:57.381211 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 18:07:57.384112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 18:07:57.384658 ==
8185 18:07:57.385010 DQS Delay:
8186 18:07:57.387454 DQS0 = 0, DQS1 = 0
8187 18:07:57.388147 DQM Delay:
8188 18:07:57.390913 DQM0 = 134, DQM1 = 127
8189 18:07:57.391610 DQ Delay:
8190 18:07:57.394501 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8191 18:07:57.397955 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8192 18:07:57.400935 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8193 18:07:57.404314 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8194 18:07:57.404779
8195 18:07:57.405110
8196 18:07:57.405446
8197 18:07:57.407579 [DramC_TX_OE_Calibration] TA2
8198 18:07:57.410793 Original DQ_B0 (3 6) =30, OEN = 27
8199 18:07:57.414337 Original DQ_B1 (3 6) =30, OEN = 27
8200 18:07:57.417735 24, 0x0, End_B0=24 End_B1=24
8201 18:07:57.420929 25, 0x0, End_B0=25 End_B1=25
8202 18:07:57.421429 26, 0x0, End_B0=26 End_B1=26
8203 18:07:57.424547 27, 0x0, End_B0=27 End_B1=27
8204 18:07:57.427297 28, 0x0, End_B0=28 End_B1=28
8205 18:07:57.431040 29, 0x0, End_B0=29 End_B1=29
8206 18:07:57.434393 30, 0x0, End_B0=30 End_B1=30
8207 18:07:57.434913 31, 0x4141, End_B0=30 End_B1=30
8208 18:07:57.437792 Byte0 end_step=30 best_step=27
8209 18:07:57.441025 Byte1 end_step=30 best_step=27
8210 18:07:57.444200 Byte0 TX OE(2T, 0.5T) = (3, 3)
8211 18:07:57.447371 Byte1 TX OE(2T, 0.5T) = (3, 3)
8212 18:07:57.447826
8213 18:07:57.448160
8214 18:07:57.454348 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8215 18:07:57.457363 CH0 RK1: MR19=303, MR18=2109
8216 18:07:57.463840 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8217 18:07:57.467319 [RxdqsGatingPostProcess] freq 1600
8218 18:07:57.474183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8219 18:07:57.474613 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 18:07:57.477482 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 18:07:57.480535 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 18:07:57.483716 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 18:07:57.487388 best DQS0 dly(2T, 0.5T) = (1, 1)
8224 18:07:57.490853 best DQS1 dly(2T, 0.5T) = (1, 1)
8225 18:07:57.493565 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8226 18:07:57.497800 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8227 18:07:57.500654 Pre-setting of DQS Precalculation
8228 18:07:57.504109 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8229 18:07:57.504735 ==
8230 18:07:57.507888 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 18:07:57.513851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 18:07:57.514401 ==
8233 18:07:57.517054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8234 18:07:57.523568 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8235 18:07:57.527345 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8236 18:07:57.533816 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8237 18:07:57.541555 [CA 0] Center 42 (13~72) winsize 60
8238 18:07:57.544914 [CA 1] Center 42 (12~72) winsize 61
8239 18:07:57.548235 [CA 2] Center 38 (9~68) winsize 60
8240 18:07:57.551309 [CA 3] Center 38 (9~67) winsize 59
8241 18:07:57.554738 [CA 4] Center 38 (9~68) winsize 60
8242 18:07:57.558146 [CA 5] Center 37 (8~67) winsize 60
8243 18:07:57.558710
8244 18:07:57.561303 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8245 18:07:57.561767
8246 18:07:57.564875 [CATrainingPosCal] consider 1 rank data
8247 18:07:57.568059 u2DelayCellTimex100 = 290/100 ps
8248 18:07:57.571050 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8249 18:07:57.577859 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8250 18:07:57.581017 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8251 18:07:57.584199 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8252 18:07:57.587892 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 18:07:57.591353 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8254 18:07:57.591880
8255 18:07:57.594777 CA PerBit enable=1, Macro0, CA PI delay=37
8256 18:07:57.595211
8257 18:07:57.597915 [CBTSetCACLKResult] CA Dly = 37
8258 18:07:57.601074 CS Dly: 11 (0~42)
8259 18:07:57.604756 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8260 18:07:57.608027 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8261 18:07:57.608699 ==
8262 18:07:57.611358 Dram Type= 6, Freq= 0, CH_1, rank 1
8263 18:07:57.614276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 18:07:57.614754 ==
8265 18:07:57.621015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 18:07:57.624554 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 18:07:57.631018 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 18:07:57.634179 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 18:07:57.644520 [CA 0] Center 42 (12~72) winsize 61
8270 18:07:57.647974 [CA 1] Center 42 (12~72) winsize 61
8271 18:07:57.650852 [CA 2] Center 38 (9~68) winsize 60
8272 18:07:57.654337 [CA 3] Center 38 (8~68) winsize 61
8273 18:07:57.657853 [CA 4] Center 38 (8~69) winsize 62
8274 18:07:57.661282 [CA 5] Center 37 (8~67) winsize 60
8275 18:07:57.661798
8276 18:07:57.664872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 18:07:57.665384
8278 18:07:57.667622 [CATrainingPosCal] consider 2 rank data
8279 18:07:57.670934 u2DelayCellTimex100 = 290/100 ps
8280 18:07:57.674521 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8281 18:07:57.681170 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8282 18:07:57.684445 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8283 18:07:57.687852 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8284 18:07:57.690625 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 18:07:57.694035 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 18:07:57.694497
8287 18:07:57.697286 CA PerBit enable=1, Macro0, CA PI delay=37
8288 18:07:57.697747
8289 18:07:57.700440 [CBTSetCACLKResult] CA Dly = 37
8290 18:07:57.704221 CS Dly: 12 (0~44)
8291 18:07:57.707556 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 18:07:57.710642 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 18:07:57.711183
8294 18:07:57.714279 ----->DramcWriteLeveling(PI) begin...
8295 18:07:57.714889 ==
8296 18:07:57.717150 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 18:07:57.724052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 18:07:57.724535 ==
8299 18:07:57.727603 Write leveling (Byte 0): 26 => 26
8300 18:07:57.728013 Write leveling (Byte 1): 29 => 29
8301 18:07:57.730385 DramcWriteLeveling(PI) end<-----
8302 18:07:57.730715
8303 18:07:57.730970 ==
8304 18:07:57.733614 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 18:07:57.740602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 18:07:57.740838 ==
8307 18:07:57.743542 [Gating] SW mode calibration
8308 18:07:57.750711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8309 18:07:57.753933 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8310 18:07:57.760136 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 18:07:57.763660 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8312 18:07:57.767255 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8313 18:07:57.773564 1 4 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8314 18:07:57.777542 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 18:07:57.780388 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 18:07:57.787227 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 18:07:57.790660 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 18:07:57.793935 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 18:07:57.797500 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 18:07:57.803674 1 5 8 | B1->B0 | 3434 2f2f | 0 1 | (0 1) (1 0)
8321 18:07:57.807180 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
8322 18:07:57.810445 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 18:07:57.817298 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 18:07:57.820252 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 18:07:57.823634 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 18:07:57.830512 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 18:07:57.833605 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 18:07:57.837444 1 6 8 | B1->B0 | 2424 3e3e | 0 0 | (0 0) (0 0)
8329 18:07:57.843902 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8330 18:07:57.846893 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 18:07:57.850516 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 18:07:57.856796 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 18:07:57.860366 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 18:07:57.863686 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 18:07:57.870355 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 18:07:57.874040 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8337 18:07:57.877020 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 18:07:57.883336 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 18:07:57.886972 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 18:07:57.890248 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 18:07:57.897013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 18:07:57.900391 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 18:07:57.903282 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 18:07:57.910314 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 18:07:57.913185 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 18:07:57.916729 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 18:07:57.923647 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 18:07:57.926517 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 18:07:57.930221 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 18:07:57.936758 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 18:07:57.940224 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 18:07:57.943004 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 18:07:57.946735 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8354 18:07:57.953240 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 18:07:57.956815 Total UI for P1: 0, mck2ui 16
8356 18:07:57.959695 best dqsien dly found for B0: ( 1, 9, 12)
8357 18:07:57.963326 Total UI for P1: 0, mck2ui 16
8358 18:07:57.966509 best dqsien dly found for B1: ( 1, 9, 12)
8359 18:07:57.969861 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8360 18:07:57.973476 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8361 18:07:57.973977
8362 18:07:57.976568 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8363 18:07:57.979477 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8364 18:07:57.982837 [Gating] SW calibration Done
8365 18:07:57.983297 ==
8366 18:07:57.986402 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 18:07:57.989541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 18:07:57.990076 ==
8369 18:07:57.992724 RX Vref Scan: 0
8370 18:07:57.993251
8371 18:07:57.996520 RX Vref 0 -> 0, step: 1
8372 18:07:57.997073
8373 18:07:57.997551 RX Delay 0 -> 252, step: 8
8374 18:07:58.003041 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8375 18:07:58.006397 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8376 18:07:58.009232 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8377 18:07:58.012999 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8378 18:07:58.015841 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8379 18:07:58.023013 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8380 18:07:58.026337 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8381 18:07:58.029088 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8382 18:07:58.032582 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8383 18:07:58.036215 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8384 18:07:58.039074 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8385 18:07:58.046348 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8386 18:07:58.049285 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8387 18:07:58.052684 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8388 18:07:58.056107 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8389 18:07:58.059380 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8390 18:07:58.062915 ==
8391 18:07:58.065716 Dram Type= 6, Freq= 0, CH_1, rank 0
8392 18:07:58.069320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8393 18:07:58.069433 ==
8394 18:07:58.069570 DQS Delay:
8395 18:07:58.072288 DQS0 = 0, DQS1 = 0
8396 18:07:58.072406 DQM Delay:
8397 18:07:58.075622 DQM0 = 136, DQM1 = 133
8398 18:07:58.075701 DQ Delay:
8399 18:07:58.079136 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8400 18:07:58.082759 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8401 18:07:58.085534 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8402 18:07:58.089012 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8403 18:07:58.089117
8404 18:07:58.089210
8405 18:07:58.089296 ==
8406 18:07:58.092374 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 18:07:58.099058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8408 18:07:58.099151 ==
8409 18:07:58.099224
8410 18:07:58.099292
8411 18:07:58.099357 TX Vref Scan disable
8412 18:07:58.102906 == TX Byte 0 ==
8413 18:07:58.106548 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8414 18:07:58.109949 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8415 18:07:58.112708 == TX Byte 1 ==
8416 18:07:58.116386 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8417 18:07:58.122432 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8418 18:07:58.122633 ==
8419 18:07:58.125879 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 18:07:58.129515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 18:07:58.129772 ==
8422 18:07:58.141794
8423 18:07:58.145170 TX Vref early break, caculate TX vref
8424 18:07:58.148728 TX Vref=16, minBit 0, minWin=23, winSum=376
8425 18:07:58.151799 TX Vref=18, minBit 1, minWin=23, winSum=388
8426 18:07:58.155261 TX Vref=20, minBit 0, minWin=24, winSum=397
8427 18:07:58.158835 TX Vref=22, minBit 0, minWin=24, winSum=404
8428 18:07:58.162077 TX Vref=24, minBit 0, minWin=25, winSum=418
8429 18:07:58.168734 TX Vref=26, minBit 0, minWin=25, winSum=421
8430 18:07:58.172319 TX Vref=28, minBit 0, minWin=25, winSum=426
8431 18:07:58.175614 TX Vref=30, minBit 0, minWin=24, winSum=416
8432 18:07:58.178153 TX Vref=32, minBit 6, minWin=24, winSum=410
8433 18:07:58.181694 TX Vref=34, minBit 0, minWin=24, winSum=400
8434 18:07:58.188723 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8435 18:07:58.189270
8436 18:07:58.191549 Final TX Range 0 Vref 28
8437 18:07:58.192124
8438 18:07:58.192653 ==
8439 18:07:58.195438 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 18:07:58.197804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 18:07:58.198263 ==
8442 18:07:58.198620
8443 18:07:58.198951
8444 18:07:58.201250 TX Vref Scan disable
8445 18:07:58.208197 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8446 18:07:58.208659 == TX Byte 0 ==
8447 18:07:58.211121 u2DelayCellOfst[0]=16 cells (5 PI)
8448 18:07:58.214602 u2DelayCellOfst[1]=10 cells (3 PI)
8449 18:07:58.217848 u2DelayCellOfst[2]=0 cells (0 PI)
8450 18:07:58.221093 u2DelayCellOfst[3]=6 cells (2 PI)
8451 18:07:58.224877 u2DelayCellOfst[4]=10 cells (3 PI)
8452 18:07:58.227853 u2DelayCellOfst[5]=16 cells (5 PI)
8453 18:07:58.231818 u2DelayCellOfst[6]=16 cells (5 PI)
8454 18:07:58.234254 u2DelayCellOfst[7]=3 cells (1 PI)
8455 18:07:58.238484 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8456 18:07:58.241220 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8457 18:07:58.244831 == TX Byte 1 ==
8458 18:07:58.245346 u2DelayCellOfst[8]=0 cells (0 PI)
8459 18:07:58.247990 u2DelayCellOfst[9]=3 cells (1 PI)
8460 18:07:58.251095 u2DelayCellOfst[10]=13 cells (4 PI)
8461 18:07:58.254495 u2DelayCellOfst[11]=6 cells (2 PI)
8462 18:07:58.258028 u2DelayCellOfst[12]=16 cells (5 PI)
8463 18:07:58.260910 u2DelayCellOfst[13]=16 cells (5 PI)
8464 18:07:58.264666 u2DelayCellOfst[14]=16 cells (5 PI)
8465 18:07:58.268508 u2DelayCellOfst[15]=16 cells (5 PI)
8466 18:07:58.271284 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8467 18:07:58.277997 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8468 18:07:58.278567 DramC Write-DBI on
8469 18:07:58.278936 ==
8470 18:07:58.281030 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 18:07:58.287701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 18:07:58.288163 ==
8473 18:07:58.288568
8474 18:07:58.288910
8475 18:07:58.289234 TX Vref Scan disable
8476 18:07:58.291582 == TX Byte 0 ==
8477 18:07:58.295152 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8478 18:07:58.297696 == TX Byte 1 ==
8479 18:07:58.301762 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8480 18:07:58.304848 DramC Write-DBI off
8481 18:07:58.305309
8482 18:07:58.305670 [DATLAT]
8483 18:07:58.306007 Freq=1600, CH1 RK0
8484 18:07:58.306334
8485 18:07:58.308318 DATLAT Default: 0xf
8486 18:07:58.308832 0, 0xFFFF, sum = 0
8487 18:07:58.311589 1, 0xFFFF, sum = 0
8488 18:07:58.315076 2, 0xFFFF, sum = 0
8489 18:07:58.315643 3, 0xFFFF, sum = 0
8490 18:07:58.318165 4, 0xFFFF, sum = 0
8491 18:07:58.318633 5, 0xFFFF, sum = 0
8492 18:07:58.321059 6, 0xFFFF, sum = 0
8493 18:07:58.321525 7, 0xFFFF, sum = 0
8494 18:07:58.324437 8, 0xFFFF, sum = 0
8495 18:07:58.324903 9, 0xFFFF, sum = 0
8496 18:07:58.327866 10, 0xFFFF, sum = 0
8497 18:07:58.328334 11, 0xFFFF, sum = 0
8498 18:07:58.331356 12, 0xFFFF, sum = 0
8499 18:07:58.331820 13, 0xFFFF, sum = 0
8500 18:07:58.334681 14, 0x0, sum = 1
8501 18:07:58.335185 15, 0x0, sum = 2
8502 18:07:58.337806 16, 0x0, sum = 3
8503 18:07:58.338536 17, 0x0, sum = 4
8504 18:07:58.341020 best_step = 15
8505 18:07:58.341659
8506 18:07:58.342117 ==
8507 18:07:58.344537 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 18:07:58.347258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 18:07:58.347750 ==
8510 18:07:58.348330 RX Vref Scan: 1
8511 18:07:58.350664
8512 18:07:58.351241 Set Vref Range= 24 -> 127
8513 18:07:58.351702
8514 18:07:58.354072 RX Vref 24 -> 127, step: 1
8515 18:07:58.354490
8516 18:07:58.357467 RX Delay 27 -> 252, step: 4
8517 18:07:58.357943
8518 18:07:58.361041 Set Vref, RX VrefLevel [Byte0]: 24
8519 18:07:58.363999 [Byte1]: 24
8520 18:07:58.364586
8521 18:07:58.367794 Set Vref, RX VrefLevel [Byte0]: 25
8522 18:07:58.371366 [Byte1]: 25
8523 18:07:58.371862
8524 18:07:58.374082 Set Vref, RX VrefLevel [Byte0]: 26
8525 18:07:58.377364 [Byte1]: 26
8526 18:07:58.381578
8527 18:07:58.381997 Set Vref, RX VrefLevel [Byte0]: 27
8528 18:07:58.385017 [Byte1]: 27
8529 18:07:58.388814
8530 18:07:58.392197 Set Vref, RX VrefLevel [Byte0]: 28
8531 18:07:58.395415 [Byte1]: 28
8532 18:07:58.396052
8533 18:07:58.398817 Set Vref, RX VrefLevel [Byte0]: 29
8534 18:07:58.401872 [Byte1]: 29
8535 18:07:58.402496
8536 18:07:58.405465 Set Vref, RX VrefLevel [Byte0]: 30
8537 18:07:58.408831 [Byte1]: 30
8538 18:07:58.409441
8539 18:07:58.412466 Set Vref, RX VrefLevel [Byte0]: 31
8540 18:07:58.414838 [Byte1]: 31
8541 18:07:58.419110
8542 18:07:58.419571 Set Vref, RX VrefLevel [Byte0]: 32
8543 18:07:58.421897 [Byte1]: 32
8544 18:07:58.426069
8545 18:07:58.426400 Set Vref, RX VrefLevel [Byte0]: 33
8546 18:07:58.429624 [Byte1]: 33
8547 18:07:58.434162
8548 18:07:58.434448 Set Vref, RX VrefLevel [Byte0]: 34
8549 18:07:58.437150 [Byte1]: 34
8550 18:07:58.441159
8551 18:07:58.441277 Set Vref, RX VrefLevel [Byte0]: 35
8552 18:07:58.444568 [Byte1]: 35
8553 18:07:58.448796
8554 18:07:58.449009 Set Vref, RX VrefLevel [Byte0]: 36
8555 18:07:58.452169 [Byte1]: 36
8556 18:07:58.456304
8557 18:07:58.456472 Set Vref, RX VrefLevel [Byte0]: 37
8558 18:07:58.459929 [Byte1]: 37
8559 18:07:58.464183
8560 18:07:58.464351 Set Vref, RX VrefLevel [Byte0]: 38
8561 18:07:58.466909 [Byte1]: 38
8562 18:07:58.471152
8563 18:07:58.471308 Set Vref, RX VrefLevel [Byte0]: 39
8564 18:07:58.474516 [Byte1]: 39
8565 18:07:58.478985
8566 18:07:58.479144 Set Vref, RX VrefLevel [Byte0]: 40
8567 18:07:58.482042 [Byte1]: 40
8568 18:07:58.486715
8569 18:07:58.486874 Set Vref, RX VrefLevel [Byte0]: 41
8570 18:07:58.489911 [Byte1]: 41
8571 18:07:58.494246
8572 18:07:58.494410 Set Vref, RX VrefLevel [Byte0]: 42
8573 18:07:58.497453 [Byte1]: 42
8574 18:07:58.501496
8575 18:07:58.501584 Set Vref, RX VrefLevel [Byte0]: 43
8576 18:07:58.504855 [Byte1]: 43
8577 18:07:58.508798
8578 18:07:58.508883 Set Vref, RX VrefLevel [Byte0]: 44
8579 18:07:58.512464 [Byte1]: 44
8580 18:07:58.516334
8581 18:07:58.516428 Set Vref, RX VrefLevel [Byte0]: 45
8582 18:07:58.520196 [Byte1]: 45
8583 18:07:58.524155
8584 18:07:58.524242 Set Vref, RX VrefLevel [Byte0]: 46
8585 18:07:58.527741 [Byte1]: 46
8586 18:07:58.532249
8587 18:07:58.532332 Set Vref, RX VrefLevel [Byte0]: 47
8588 18:07:58.534994 [Byte1]: 47
8589 18:07:58.539110
8590 18:07:58.539192 Set Vref, RX VrefLevel [Byte0]: 48
8591 18:07:58.543003 [Byte1]: 48
8592 18:07:58.546948
8593 18:07:58.547059 Set Vref, RX VrefLevel [Byte0]: 49
8594 18:07:58.549756 [Byte1]: 49
8595 18:07:58.554425
8596 18:07:58.554508 Set Vref, RX VrefLevel [Byte0]: 50
8597 18:07:58.557783 [Byte1]: 50
8598 18:07:58.561997
8599 18:07:58.562079 Set Vref, RX VrefLevel [Byte0]: 51
8600 18:07:58.565467 [Byte1]: 51
8601 18:07:58.568979
8602 18:07:58.569152 Set Vref, RX VrefLevel [Byte0]: 52
8603 18:07:58.572495 [Byte1]: 52
8604 18:07:58.576643
8605 18:07:58.576802 Set Vref, RX VrefLevel [Byte0]: 53
8606 18:07:58.580145 [Byte1]: 53
8607 18:07:58.584243
8608 18:07:58.584408 Set Vref, RX VrefLevel [Byte0]: 54
8609 18:07:58.587747 [Byte1]: 54
8610 18:07:58.591838
8611 18:07:58.591992 Set Vref, RX VrefLevel [Byte0]: 55
8612 18:07:58.595132 [Byte1]: 55
8613 18:07:58.599981
8614 18:07:58.600063 Set Vref, RX VrefLevel [Byte0]: 56
8615 18:07:58.602670 [Byte1]: 56
8616 18:07:58.607314
8617 18:07:58.607394 Set Vref, RX VrefLevel [Byte0]: 57
8618 18:07:58.610158 [Byte1]: 57
8619 18:07:58.614753
8620 18:07:58.614832 Set Vref, RX VrefLevel [Byte0]: 58
8621 18:07:58.618123 [Byte1]: 58
8622 18:07:58.622035
8623 18:07:58.622145 Set Vref, RX VrefLevel [Byte0]: 59
8624 18:07:58.625476 [Byte1]: 59
8625 18:07:58.629641
8626 18:07:58.629721 Set Vref, RX VrefLevel [Byte0]: 60
8627 18:07:58.632511 [Byte1]: 60
8628 18:07:58.636991
8629 18:07:58.637075 Set Vref, RX VrefLevel [Byte0]: 61
8630 18:07:58.640210 [Byte1]: 61
8631 18:07:58.644562
8632 18:07:58.644640 Set Vref, RX VrefLevel [Byte0]: 62
8633 18:07:58.647805 [Byte1]: 62
8634 18:07:58.652285
8635 18:07:58.652389 Set Vref, RX VrefLevel [Byte0]: 63
8636 18:07:58.655470 [Byte1]: 63
8637 18:07:58.659914
8638 18:07:58.659986 Set Vref, RX VrefLevel [Byte0]: 64
8639 18:07:58.663293 [Byte1]: 64
8640 18:07:58.667387
8641 18:07:58.667460 Set Vref, RX VrefLevel [Byte0]: 65
8642 18:07:58.670209 [Byte1]: 65
8643 18:07:58.674404
8644 18:07:58.674482 Set Vref, RX VrefLevel [Byte0]: 66
8645 18:07:58.677997 [Byte1]: 66
8646 18:07:58.682237
8647 18:07:58.682321 Set Vref, RX VrefLevel [Byte0]: 67
8648 18:07:58.685700 [Byte1]: 67
8649 18:07:58.689945
8650 18:07:58.690052 Set Vref, RX VrefLevel [Byte0]: 68
8651 18:07:58.692713 [Byte1]: 68
8652 18:07:58.697557
8653 18:07:58.697648 Set Vref, RX VrefLevel [Byte0]: 69
8654 18:07:58.701111 [Byte1]: 69
8655 18:07:58.704830
8656 18:07:58.704913 Set Vref, RX VrefLevel [Byte0]: 70
8657 18:07:58.708061 [Byte1]: 70
8658 18:07:58.712975
8659 18:07:58.713056 Set Vref, RX VrefLevel [Byte0]: 71
8660 18:07:58.715603 [Byte1]: 71
8661 18:07:58.719846
8662 18:07:58.719950 Set Vref, RX VrefLevel [Byte0]: 72
8663 18:07:58.723060 [Byte1]: 72
8664 18:07:58.727752
8665 18:07:58.727832 Set Vref, RX VrefLevel [Byte0]: 73
8666 18:07:58.730587 [Byte1]: 73
8667 18:07:58.734914
8668 18:07:58.734994 Set Vref, RX VrefLevel [Byte0]: 74
8669 18:07:58.738740 [Byte1]: 74
8670 18:07:58.742417
8671 18:07:58.742497 Set Vref, RX VrefLevel [Byte0]: 75
8672 18:07:58.745938 [Byte1]: 75
8673 18:07:58.750067
8674 18:07:58.750154 Set Vref, RX VrefLevel [Byte0]: 76
8675 18:07:58.753667 [Byte1]: 76
8676 18:07:58.757715
8677 18:07:58.757796 Final RX Vref Byte 0 = 59 to rank0
8678 18:07:58.760933 Final RX Vref Byte 1 = 57 to rank0
8679 18:07:58.763962 Final RX Vref Byte 0 = 59 to rank1
8680 18:07:58.767523 Final RX Vref Byte 1 = 57 to rank1==
8681 18:07:58.770799 Dram Type= 6, Freq= 0, CH_1, rank 0
8682 18:07:58.777306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8683 18:07:58.777386 ==
8684 18:07:58.777460 DQS Delay:
8685 18:07:58.777521 DQS0 = 0, DQS1 = 0
8686 18:07:58.781062 DQM Delay:
8687 18:07:58.781142 DQM0 = 133, DQM1 = 131
8688 18:07:58.784552 DQ Delay:
8689 18:07:58.787563 DQ0 =140, DQ1 =128, DQ2 =120, DQ3 =130
8690 18:07:58.791137 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8691 18:07:58.794115 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8692 18:07:58.797648 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8693 18:07:58.797722
8694 18:07:58.797783
8695 18:07:58.797840
8696 18:07:58.801224 [DramC_TX_OE_Calibration] TA2
8697 18:07:58.804616 Original DQ_B0 (3 6) =30, OEN = 27
8698 18:07:58.808060 Original DQ_B1 (3 6) =30, OEN = 27
8699 18:07:58.810793 24, 0x0, End_B0=24 End_B1=24
8700 18:07:58.810887 25, 0x0, End_B0=25 End_B1=25
8701 18:07:58.814148 26, 0x0, End_B0=26 End_B1=26
8702 18:07:58.817404 27, 0x0, End_B0=27 End_B1=27
8703 18:07:58.820822 28, 0x0, End_B0=28 End_B1=28
8704 18:07:58.820900 29, 0x0, End_B0=29 End_B1=29
8705 18:07:58.824256 30, 0x0, End_B0=30 End_B1=30
8706 18:07:58.827877 31, 0x4141, End_B0=30 End_B1=30
8707 18:07:58.831211 Byte0 end_step=30 best_step=27
8708 18:07:58.834066 Byte1 end_step=30 best_step=27
8709 18:07:58.837595 Byte0 TX OE(2T, 0.5T) = (3, 3)
8710 18:07:58.837672 Byte1 TX OE(2T, 0.5T) = (3, 3)
8711 18:07:58.837734
8712 18:07:58.840666
8713 18:07:58.847430 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8714 18:07:58.851076 CH1 RK0: MR19=303, MR18=1624
8715 18:07:58.857504 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8716 18:07:58.857583
8717 18:07:58.861127 ----->DramcWriteLeveling(PI) begin...
8718 18:07:58.861220 ==
8719 18:07:58.864118 Dram Type= 6, Freq= 0, CH_1, rank 1
8720 18:07:58.867202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8721 18:07:58.867283 ==
8722 18:07:58.870621 Write leveling (Byte 0): 26 => 26
8723 18:07:58.874308 Write leveling (Byte 1): 28 => 28
8724 18:07:58.877507 DramcWriteLeveling(PI) end<-----
8725 18:07:58.877587
8726 18:07:58.877650 ==
8727 18:07:58.880718 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 18:07:58.884029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 18:07:58.884130 ==
8730 18:07:58.887140 [Gating] SW mode calibration
8731 18:07:58.893821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8732 18:07:58.900782 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8733 18:07:58.904038 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 18:07:58.907441 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8735 18:07:58.914155 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8736 18:07:58.917151 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8737 18:07:58.920601 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 18:07:58.927281 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 18:07:58.930415 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 18:07:58.933858 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 18:07:58.940626 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 18:07:58.943658 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8743 18:07:58.947205 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8744 18:07:58.953519 1 5 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 0)
8745 18:07:58.957103 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 18:07:58.960590 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 18:07:58.967033 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 18:07:58.970211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 18:07:58.973418 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 18:07:58.980227 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 18:07:58.983725 1 6 8 | B1->B0 | 3d3d 2323 | 0 0 | (1 1) (0 0)
8752 18:07:58.986969 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
8753 18:07:58.993622 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 18:07:58.997179 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 18:07:58.999862 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 18:07:59.006779 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 18:07:59.009913 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 18:07:59.013219 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8759 18:07:59.019778 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8760 18:07:59.023422 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8761 18:07:59.026469 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8762 18:07:59.030080 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 18:07:59.036355 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 18:07:59.039686 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 18:07:59.043433 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 18:07:59.049786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 18:07:59.053175 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 18:07:59.056786 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 18:07:59.063106 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 18:07:59.066513 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 18:07:59.069974 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 18:07:59.076239 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 18:07:59.079662 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 18:07:59.083388 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8775 18:07:59.090036 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8776 18:07:59.093222 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8777 18:07:59.096746 Total UI for P1: 0, mck2ui 16
8778 18:07:59.099878 best dqsien dly found for B1: ( 1, 9, 6)
8779 18:07:59.103565 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8780 18:07:59.109746 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 18:07:59.109834 Total UI for P1: 0, mck2ui 16
8782 18:07:59.113287 best dqsien dly found for B0: ( 1, 9, 14)
8783 18:07:59.120127 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8784 18:07:59.122904 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8785 18:07:59.122982
8786 18:07:59.126451 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8787 18:07:59.129822 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8788 18:07:59.133209 [Gating] SW calibration Done
8789 18:07:59.133317 ==
8790 18:07:59.136575 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 18:07:59.139990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 18:07:59.140090 ==
8793 18:07:59.143223 RX Vref Scan: 0
8794 18:07:59.143333
8795 18:07:59.143421 RX Vref 0 -> 0, step: 1
8796 18:07:59.143484
8797 18:07:59.146528 RX Delay 0 -> 252, step: 8
8798 18:07:59.149657 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8799 18:07:59.155810 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8800 18:07:59.159799 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8801 18:07:59.162566 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8802 18:07:59.166178 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8803 18:07:59.169653 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8804 18:07:59.173078 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8805 18:07:59.179520 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8806 18:07:59.182984 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8807 18:07:59.185832 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8808 18:07:59.189232 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8809 18:07:59.196329 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8810 18:07:59.199523 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8811 18:07:59.202807 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8812 18:07:59.205594 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8813 18:07:59.209156 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8814 18:07:59.212893 ==
8815 18:07:59.212965 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 18:07:59.219307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 18:07:59.219386 ==
8818 18:07:59.219450 DQS Delay:
8819 18:07:59.222608 DQS0 = 0, DQS1 = 0
8820 18:07:59.222692 DQM Delay:
8821 18:07:59.226177 DQM0 = 136, DQM1 = 134
8822 18:07:59.226258 DQ Delay:
8823 18:07:59.228966 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8824 18:07:59.232543 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8825 18:07:59.235630 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =131
8826 18:07:59.238998 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8827 18:07:59.239074
8828 18:07:59.239143
8829 18:07:59.239202 ==
8830 18:07:59.242444 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 18:07:59.249087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 18:07:59.249184 ==
8833 18:07:59.249252
8834 18:07:59.249312
8835 18:07:59.249369 TX Vref Scan disable
8836 18:07:59.252347 == TX Byte 0 ==
8837 18:07:59.255822 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8838 18:07:59.262247 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8839 18:07:59.262330 == TX Byte 1 ==
8840 18:07:59.265933 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8841 18:07:59.269095 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8842 18:07:59.272304 ==
8843 18:07:59.275771 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 18:07:59.279402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 18:07:59.279477 ==
8846 18:07:59.292069
8847 18:07:59.295753 TX Vref early break, caculate TX vref
8848 18:07:59.299131 TX Vref=16, minBit 0, minWin=23, winSum=380
8849 18:07:59.302573 TX Vref=18, minBit 0, minWin=23, winSum=391
8850 18:07:59.306092 TX Vref=20, minBit 0, minWin=23, winSum=399
8851 18:07:59.308678 TX Vref=22, minBit 0, minWin=24, winSum=408
8852 18:07:59.312139 TX Vref=24, minBit 0, minWin=24, winSum=413
8853 18:07:59.319041 TX Vref=26, minBit 0, minWin=26, winSum=426
8854 18:07:59.322450 TX Vref=28, minBit 0, minWin=26, winSum=425
8855 18:07:59.325606 TX Vref=30, minBit 0, minWin=25, winSum=419
8856 18:07:59.328855 TX Vref=32, minBit 6, minWin=24, winSum=412
8857 18:07:59.332056 TX Vref=34, minBit 0, minWin=24, winSum=406
8858 18:07:59.335148 TX Vref=36, minBit 1, minWin=23, winSum=396
8859 18:07:59.342248 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8860 18:07:59.342326
8861 18:07:59.345796 Final TX Range 0 Vref 26
8862 18:07:59.345872
8863 18:07:59.345933 ==
8864 18:07:59.348451 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 18:07:59.351895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 18:07:59.351970 ==
8867 18:07:59.352031
8868 18:07:59.355409
8869 18:07:59.355484 TX Vref Scan disable
8870 18:07:59.361665 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8871 18:07:59.361768 == TX Byte 0 ==
8872 18:07:59.365287 u2DelayCellOfst[0]=16 cells (5 PI)
8873 18:07:59.368591 u2DelayCellOfst[1]=10 cells (3 PI)
8874 18:07:59.371981 u2DelayCellOfst[2]=0 cells (0 PI)
8875 18:07:59.375293 u2DelayCellOfst[3]=6 cells (2 PI)
8876 18:07:59.378584 u2DelayCellOfst[4]=6 cells (2 PI)
8877 18:07:59.381844 u2DelayCellOfst[5]=16 cells (5 PI)
8878 18:07:59.385031 u2DelayCellOfst[6]=16 cells (5 PI)
8879 18:07:59.388501 u2DelayCellOfst[7]=6 cells (2 PI)
8880 18:07:59.391972 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8881 18:07:59.394858 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8882 18:07:59.398567 == TX Byte 1 ==
8883 18:07:59.401359 u2DelayCellOfst[8]=0 cells (0 PI)
8884 18:07:59.404946 u2DelayCellOfst[9]=3 cells (1 PI)
8885 18:07:59.405027 u2DelayCellOfst[10]=10 cells (3 PI)
8886 18:07:59.408313 u2DelayCellOfst[11]=3 cells (1 PI)
8887 18:07:59.411763 u2DelayCellOfst[12]=13 cells (4 PI)
8888 18:07:59.415043 u2DelayCellOfst[13]=13 cells (4 PI)
8889 18:07:59.418426 u2DelayCellOfst[14]=16 cells (5 PI)
8890 18:07:59.421919 u2DelayCellOfst[15]=16 cells (5 PI)
8891 18:07:59.424701 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8892 18:07:59.431786 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 18:07:59.431875 DramC Write-DBI on
8894 18:07:59.431941 ==
8895 18:07:59.435337 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 18:07:59.441190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 18:07:59.441265 ==
8898 18:07:59.441327
8899 18:07:59.441384
8900 18:07:59.441440 TX Vref Scan disable
8901 18:07:59.445464 == TX Byte 0 ==
8902 18:07:59.448614 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8903 18:07:59.452117 == TX Byte 1 ==
8904 18:07:59.455298 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8905 18:07:59.458708 DramC Write-DBI off
8906 18:07:59.458828
8907 18:07:59.458922 [DATLAT]
8908 18:07:59.459009 Freq=1600, CH1 RK1
8909 18:07:59.459096
8910 18:07:59.461996 DATLAT Default: 0xf
8911 18:07:59.465451 0, 0xFFFF, sum = 0
8912 18:07:59.465554 1, 0xFFFF, sum = 0
8913 18:07:59.468285 2, 0xFFFF, sum = 0
8914 18:07:59.468428 3, 0xFFFF, sum = 0
8915 18:07:59.471789 4, 0xFFFF, sum = 0
8916 18:07:59.471897 5, 0xFFFF, sum = 0
8917 18:07:59.475321 6, 0xFFFF, sum = 0
8918 18:07:59.475422 7, 0xFFFF, sum = 0
8919 18:07:59.478259 8, 0xFFFF, sum = 0
8920 18:07:59.478446 9, 0xFFFF, sum = 0
8921 18:07:59.481660 10, 0xFFFF, sum = 0
8922 18:07:59.481736 11, 0xFFFF, sum = 0
8923 18:07:59.485141 12, 0xFFFF, sum = 0
8924 18:07:59.485252 13, 0xFFFF, sum = 0
8925 18:07:59.488558 14, 0x0, sum = 1
8926 18:07:59.488665 15, 0x0, sum = 2
8927 18:07:59.491812 16, 0x0, sum = 3
8928 18:07:59.491941 17, 0x0, sum = 4
8929 18:07:59.494911 best_step = 15
8930 18:07:59.495069
8931 18:07:59.495192 ==
8932 18:07:59.498237 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 18:07:59.501417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 18:07:59.501518 ==
8935 18:07:59.505317 RX Vref Scan: 0
8936 18:07:59.505398
8937 18:07:59.505473 RX Vref 0 -> 0, step: 1
8938 18:07:59.505533
8939 18:07:59.508596 RX Delay 19 -> 252, step: 4
8940 18:07:59.512081 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8941 18:07:59.518871 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8942 18:07:59.521800 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8943 18:07:59.524825 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8944 18:07:59.528198 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8945 18:07:59.531600 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8946 18:07:59.535160 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8947 18:07:59.541779 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8948 18:07:59.545324 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8949 18:07:59.548124 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8950 18:07:59.551513 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8951 18:07:59.558069 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8952 18:07:59.561700 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8953 18:07:59.564735 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8954 18:07:59.568509 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8955 18:07:59.571834 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8956 18:07:59.571910 ==
8957 18:07:59.574630 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 18:07:59.581755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 18:07:59.581828 ==
8960 18:07:59.581889 DQS Delay:
8961 18:07:59.584668 DQS0 = 0, DQS1 = 0
8962 18:07:59.584735 DQM Delay:
8963 18:07:59.588166 DQM0 = 134, DQM1 = 130
8964 18:07:59.588232 DQ Delay:
8965 18:07:59.591618 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8966 18:07:59.595017 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8967 18:07:59.598508 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8968 18:07:59.602103 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8969 18:07:59.602183
8970 18:07:59.602246
8971 18:07:59.602304
8972 18:07:59.605433 [DramC_TX_OE_Calibration] TA2
8973 18:07:59.608213 Original DQ_B0 (3 6) =30, OEN = 27
8974 18:07:59.611564 Original DQ_B1 (3 6) =30, OEN = 27
8975 18:07:59.614672 24, 0x0, End_B0=24 End_B1=24
8976 18:07:59.614746 25, 0x0, End_B0=25 End_B1=25
8977 18:07:59.618189 26, 0x0, End_B0=26 End_B1=26
8978 18:07:59.621474 27, 0x0, End_B0=27 End_B1=27
8979 18:07:59.625056 28, 0x0, End_B0=28 End_B1=28
8980 18:07:59.628085 29, 0x0, End_B0=29 End_B1=29
8981 18:07:59.628166 30, 0x0, End_B0=30 End_B1=30
8982 18:07:59.631537 31, 0x4141, End_B0=30 End_B1=30
8983 18:07:59.634627 Byte0 end_step=30 best_step=27
8984 18:07:59.638130 Byte1 end_step=30 best_step=27
8985 18:07:59.641583 Byte0 TX OE(2T, 0.5T) = (3, 3)
8986 18:07:59.644937 Byte1 TX OE(2T, 0.5T) = (3, 3)
8987 18:07:59.645017
8988 18:07:59.645081
8989 18:07:59.651220 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8990 18:07:59.654622 CH1 RK1: MR19=303, MR18=2308
8991 18:07:59.661895 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
8992 18:07:59.664655 [RxdqsGatingPostProcess] freq 1600
8993 18:07:59.668073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8994 18:07:59.671553 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 18:07:59.674891 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 18:07:59.677981 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 18:07:59.681574 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 18:07:59.684437 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 18:07:59.687789 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 18:07:59.691692 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 18:07:59.694522 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 18:07:59.697878 Pre-setting of DQS Precalculation
9003 18:07:59.701502 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9004 18:07:59.707847 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9005 18:07:59.718132 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9006 18:07:59.718213
9007 18:07:59.718275
9008 18:07:59.718333 [Calibration Summary] 3200 Mbps
9009 18:07:59.721028 CH 0, Rank 0
9010 18:07:59.724687 SW Impedance : PASS
9011 18:07:59.724767 DUTY Scan : NO K
9012 18:07:59.727588 ZQ Calibration : PASS
9013 18:07:59.727668 Jitter Meter : NO K
9014 18:07:59.731477 CBT Training : PASS
9015 18:07:59.734462 Write leveling : PASS
9016 18:07:59.734542 RX DQS gating : PASS
9017 18:07:59.737888 RX DQ/DQS(RDDQC) : PASS
9018 18:07:59.741023 TX DQ/DQS : PASS
9019 18:07:59.741105 RX DATLAT : PASS
9020 18:07:59.744170 RX DQ/DQS(Engine): PASS
9021 18:07:59.747525 TX OE : PASS
9022 18:07:59.747605 All Pass.
9023 18:07:59.747668
9024 18:07:59.747725 CH 0, Rank 1
9025 18:07:59.751093 SW Impedance : PASS
9026 18:07:59.754596 DUTY Scan : NO K
9027 18:07:59.754676 ZQ Calibration : PASS
9028 18:07:59.757338 Jitter Meter : NO K
9029 18:07:59.760678 CBT Training : PASS
9030 18:07:59.760778 Write leveling : PASS
9031 18:07:59.764201 RX DQS gating : PASS
9032 18:07:59.767710 RX DQ/DQS(RDDQC) : PASS
9033 18:07:59.767790 TX DQ/DQS : PASS
9034 18:07:59.771264 RX DATLAT : PASS
9035 18:07:59.771344 RX DQ/DQS(Engine): PASS
9036 18:07:59.774060 TX OE : PASS
9037 18:07:59.774140 All Pass.
9038 18:07:59.774203
9039 18:07:59.777515 CH 1, Rank 0
9040 18:07:59.777595 SW Impedance : PASS
9041 18:07:59.781268 DUTY Scan : NO K
9042 18:07:59.783933 ZQ Calibration : PASS
9043 18:07:59.784013 Jitter Meter : NO K
9044 18:07:59.787525 CBT Training : PASS
9045 18:07:59.790664 Write leveling : PASS
9046 18:07:59.790744 RX DQS gating : PASS
9047 18:07:59.794012 RX DQ/DQS(RDDQC) : PASS
9048 18:07:59.797658 TX DQ/DQS : PASS
9049 18:07:59.797739 RX DATLAT : PASS
9050 18:07:59.801129 RX DQ/DQS(Engine): PASS
9051 18:07:59.804049 TX OE : PASS
9052 18:07:59.804129 All Pass.
9053 18:07:59.804192
9054 18:07:59.804268 CH 1, Rank 1
9055 18:07:59.807659 SW Impedance : PASS
9056 18:07:59.811191 DUTY Scan : NO K
9057 18:07:59.811271 ZQ Calibration : PASS
9058 18:07:59.814392 Jitter Meter : NO K
9059 18:07:59.817468 CBT Training : PASS
9060 18:07:59.817548 Write leveling : PASS
9061 18:07:59.820981 RX DQS gating : PASS
9062 18:07:59.821099 RX DQ/DQS(RDDQC) : PASS
9063 18:07:59.824418 TX DQ/DQS : PASS
9064 18:07:59.827235 RX DATLAT : PASS
9065 18:07:59.827315 RX DQ/DQS(Engine): PASS
9066 18:07:59.830681 TX OE : PASS
9067 18:07:59.830762 All Pass.
9068 18:07:59.830824
9069 18:07:59.834036 DramC Write-DBI on
9070 18:07:59.837441 PER_BANK_REFRESH: Hybrid Mode
9071 18:07:59.837521 TX_TRACKING: ON
9072 18:07:59.847553 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9073 18:07:59.854163 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9074 18:07:59.864132 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 18:07:59.867563 [FAST_K] Save calibration result to emmc
9076 18:07:59.867639 sync common calibartion params.
9077 18:07:59.870936 sync cbt_mode0:1, 1:1
9078 18:07:59.873652 dram_init: ddr_geometry: 2
9079 18:07:59.873732 dram_init: ddr_geometry: 2
9080 18:07:59.877279 dram_init: ddr_geometry: 2
9081 18:07:59.880894 0:dram_rank_size:100000000
9082 18:07:59.883618 1:dram_rank_size:100000000
9083 18:07:59.887222 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9084 18:07:59.890715 DFS_SHUFFLE_HW_MODE: ON
9085 18:07:59.894098 dramc_set_vcore_voltage set vcore to 725000
9086 18:07:59.896874 Read voltage for 1600, 0
9087 18:07:59.896954 Vio18 = 0
9088 18:07:59.900303 Vcore = 725000
9089 18:07:59.900434 Vdram = 0
9090 18:07:59.900498 Vddq = 0
9091 18:07:59.900557 Vmddr = 0
9092 18:07:59.903944 switch to 3200 Mbps bootup
9093 18:07:59.907320 [DramcRunTimeConfig]
9094 18:07:59.907399 PHYPLL
9095 18:07:59.910526 DPM_CONTROL_AFTERK: ON
9096 18:07:59.910605 PER_BANK_REFRESH: ON
9097 18:07:59.913881 REFRESH_OVERHEAD_REDUCTION: ON
9098 18:07:59.916626 CMD_PICG_NEW_MODE: OFF
9099 18:07:59.916706 XRTWTW_NEW_MODE: ON
9100 18:07:59.920541 XRTRTR_NEW_MODE: ON
9101 18:07:59.920624 TX_TRACKING: ON
9102 18:07:59.923839 RDSEL_TRACKING: OFF
9103 18:07:59.926937 DQS Precalculation for DVFS: ON
9104 18:07:59.927018 RX_TRACKING: OFF
9105 18:07:59.927082 HW_GATING DBG: ON
9106 18:07:59.929993 ZQCS_ENABLE_LP4: ON
9107 18:07:59.933680 RX_PICG_NEW_MODE: ON
9108 18:07:59.933774 TX_PICG_NEW_MODE: ON
9109 18:07:59.936371 ENABLE_RX_DCM_DPHY: ON
9110 18:07:59.939786 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9111 18:07:59.943126 DUMMY_READ_FOR_TRACKING: OFF
9112 18:07:59.943207 !!! SPM_CONTROL_AFTERK: OFF
9113 18:07:59.946396 !!! SPM could not control APHY
9114 18:07:59.949720 IMPEDANCE_TRACKING: ON
9115 18:07:59.949801 TEMP_SENSOR: ON
9116 18:07:59.953263 HW_SAVE_FOR_SR: OFF
9117 18:07:59.956581 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9118 18:07:59.960073 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9119 18:07:59.960153 Read ODT Tracking: ON
9120 18:07:59.963198 Refresh Rate DeBounce: ON
9121 18:07:59.966461 DFS_NO_QUEUE_FLUSH: ON
9122 18:07:59.970065 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9123 18:07:59.970145 ENABLE_DFS_RUNTIME_MRW: OFF
9124 18:07:59.973412 DDR_RESERVE_NEW_MODE: ON
9125 18:07:59.976615 MR_CBT_SWITCH_FREQ: ON
9126 18:07:59.976695 =========================
9127 18:07:59.996961 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9128 18:07:59.999777 dram_init: ddr_geometry: 2
9129 18:08:00.018253 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9130 18:08:00.021272 dram_init: dram init end (result: 0)
9131 18:08:00.027835 DRAM-K: Full calibration passed in 24443 msecs
9132 18:08:00.031345 MRC: failed to locate region type 0.
9133 18:08:00.031427 DRAM rank0 size:0x100000000,
9134 18:08:00.034726 DRAM rank1 size=0x100000000
9135 18:08:00.044438 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9136 18:08:00.051400 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9137 18:08:00.057948 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9138 18:08:00.067235 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9139 18:08:00.067349 DRAM rank0 size:0x100000000,
9140 18:08:00.070743 DRAM rank1 size=0x100000000
9141 18:08:00.070851 CBMEM:
9142 18:08:00.074498 IMD: root @ 0xfffff000 254 entries.
9143 18:08:00.077912 IMD: root @ 0xffffec00 62 entries.
9144 18:08:00.080538 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9145 18:08:00.087327 WARNING: RO_VPD is uninitialized or empty.
9146 18:08:00.090547 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9147 18:08:00.098022 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9148 18:08:00.110874 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9149 18:08:00.122168 BS: romstage times (exec / console): total (unknown) / 23977 ms
9150 18:08:00.122297
9151 18:08:00.122375
9152 18:08:00.132351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9153 18:08:00.135805 ARM64: Exception handlers installed.
9154 18:08:00.139533 ARM64: Testing exception
9155 18:08:00.142239 ARM64: Done test exception
9156 18:08:00.142320 Enumerating buses...
9157 18:08:00.146001 Show all devs... Before device enumeration.
9158 18:08:00.148779 Root Device: enabled 1
9159 18:08:00.152131 CPU_CLUSTER: 0: enabled 1
9160 18:08:00.152240 CPU: 00: enabled 1
9161 18:08:00.155401 Compare with tree...
9162 18:08:00.155481 Root Device: enabled 1
9163 18:08:00.159000 CPU_CLUSTER: 0: enabled 1
9164 18:08:00.162406 CPU: 00: enabled 1
9165 18:08:00.162507 Root Device scanning...
9166 18:08:00.165773 scan_static_bus for Root Device
9167 18:08:00.169056 CPU_CLUSTER: 0 enabled
9168 18:08:00.172518 scan_static_bus for Root Device done
9169 18:08:00.175327 scan_bus: bus Root Device finished in 8 msecs
9170 18:08:00.175428 done
9171 18:08:00.182430 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9172 18:08:00.185405 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9173 18:08:00.192230 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9174 18:08:00.195724 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9175 18:08:00.198658 Allocating resources...
9176 18:08:00.198735 Reading resources...
9177 18:08:00.205076 Root Device read_resources bus 0 link: 0
9178 18:08:00.205164 DRAM rank0 size:0x100000000,
9179 18:08:00.208486 DRAM rank1 size=0x100000000
9180 18:08:00.212029 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9181 18:08:00.215757 CPU: 00 missing read_resources
9182 18:08:00.218509 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9183 18:08:00.225469 Root Device read_resources bus 0 link: 0 done
9184 18:08:00.225552 Done reading resources.
9185 18:08:00.231934 Show resources in subtree (Root Device)...After reading.
9186 18:08:00.235623 Root Device child on link 0 CPU_CLUSTER: 0
9187 18:08:00.238303 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 18:08:00.248581 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 18:08:00.248666 CPU: 00
9190 18:08:00.252468 Root Device assign_resources, bus 0 link: 0
9191 18:08:00.255130 CPU_CLUSTER: 0 missing set_resources
9192 18:08:00.258549 Root Device assign_resources, bus 0 link: 0 done
9193 18:08:00.262131 Done setting resources.
9194 18:08:00.268470 Show resources in subtree (Root Device)...After assigning values.
9195 18:08:00.272011 Root Device child on link 0 CPU_CLUSTER: 0
9196 18:08:00.275282 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 18:08:00.285204 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 18:08:00.285300 CPU: 00
9199 18:08:00.288497 Done allocating resources.
9200 18:08:00.292204 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9201 18:08:00.295195 Enabling resources...
9202 18:08:00.295278 done.
9203 18:08:00.301898 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9204 18:08:00.302002 Initializing devices...
9205 18:08:00.305138 Root Device init
9206 18:08:00.305251 init hardware done!
9207 18:08:00.308059 0x00000018: ctrlr->caps
9208 18:08:00.311433 52.000 MHz: ctrlr->f_max
9209 18:08:00.311509 0.400 MHz: ctrlr->f_min
9210 18:08:00.314904 0x40ff8080: ctrlr->voltages
9211 18:08:00.315012 sclk: 390625
9212 18:08:00.318696 Bus Width = 1
9213 18:08:00.318793 sclk: 390625
9214 18:08:00.321880 Bus Width = 1
9215 18:08:00.321983 Early init status = 3
9216 18:08:00.328260 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9217 18:08:00.331784 in-header: 03 fc 00 00 01 00 00 00
9218 18:08:00.331889 in-data: 00
9219 18:08:00.338220 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9220 18:08:00.341766 in-header: 03 fd 00 00 00 00 00 00
9221 18:08:00.345174 in-data:
9222 18:08:00.348449 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9223 18:08:00.352587 in-header: 03 fc 00 00 01 00 00 00
9224 18:08:00.356061 in-data: 00
9225 18:08:00.359183 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9226 18:08:00.367893 in-header: 03 fd 00 00 00 00 00 00
9227 18:08:00.367998 in-data:
9228 18:08:00.371656 [SSUSB] Setting up USB HOST controller...
9229 18:08:00.374942 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9230 18:08:00.378112 [SSUSB] phy power-on done.
9231 18:08:00.381361 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9232 18:08:00.388233 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9233 18:08:00.390987 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9234 18:08:00.397609 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9235 18:08:00.404259 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9236 18:08:00.411254 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9237 18:08:00.417534 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9238 18:08:00.424046 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9239 18:08:00.427737 SPM: binary array size = 0x9dc
9240 18:08:00.430904 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9241 18:08:00.437650 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9242 18:08:00.443974 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9243 18:08:00.450498 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9244 18:08:00.453784 configure_display: Starting display init
9245 18:08:00.488196 anx7625_power_on_init: Init interface.
9246 18:08:00.491420 anx7625_disable_pd_protocol: Disabled PD feature.
9247 18:08:00.494890 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9248 18:08:00.522700 anx7625_start_dp_work: Secure OCM version=00
9249 18:08:00.526215 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9250 18:08:00.540479 sp_tx_get_edid_block: EDID Block = 1
9251 18:08:00.643655 Extracted contents:
9252 18:08:00.646381 header: 00 ff ff ff ff ff ff 00
9253 18:08:00.649799 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9254 18:08:00.653227 version: 01 04
9255 18:08:00.656560 basic params: 95 1f 11 78 0a
9256 18:08:00.660120 chroma info: 76 90 94 55 54 90 27 21 50 54
9257 18:08:00.663082 established: 00 00 00
9258 18:08:00.666652 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9259 18:08:00.673419 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9260 18:08:00.679711 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9261 18:08:00.686373 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9262 18:08:00.693619 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9263 18:08:00.696521 extensions: 00
9264 18:08:00.696613 checksum: fb
9265 18:08:00.696676
9266 18:08:00.699657 Manufacturer: IVO Model 57d Serial Number 0
9267 18:08:00.703093 Made week 0 of 2020
9268 18:08:00.703196 EDID version: 1.4
9269 18:08:00.706428 Digital display
9270 18:08:00.709751 6 bits per primary color channel
9271 18:08:00.709829 DisplayPort interface
9272 18:08:00.712948 Maximum image size: 31 cm x 17 cm
9273 18:08:00.716406 Gamma: 220%
9274 18:08:00.716498 Check DPMS levels
9275 18:08:00.719941 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9276 18:08:00.722882 First detailed timing is preferred timing
9277 18:08:00.726399 Established timings supported:
9278 18:08:00.729963 Standard timings supported:
9279 18:08:00.730045 Detailed timings
9280 18:08:00.736672 Hex of detail: 383680a07038204018303c0035ae10000019
9281 18:08:00.739841 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9282 18:08:00.746185 0780 0798 07c8 0820 hborder 0
9283 18:08:00.749703 0438 043b 0447 0458 vborder 0
9284 18:08:00.749782 -hsync -vsync
9285 18:08:00.753388 Did detailed timing
9286 18:08:00.756042 Hex of detail: 000000000000000000000000000000000000
9287 18:08:00.759477 Manufacturer-specified data, tag 0
9288 18:08:00.766544 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9289 18:08:00.766626 ASCII string: InfoVision
9290 18:08:00.772844 Hex of detail: 000000fe00523134304e574635205248200a
9291 18:08:00.776234 ASCII string: R140NWF5 RH
9292 18:08:00.776360 Checksum
9293 18:08:00.776438 Checksum: 0xfb (valid)
9294 18:08:00.783154 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9295 18:08:00.785836 DSI data_rate: 832800000 bps
9296 18:08:00.789791 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9297 18:08:00.796497 anx7625_parse_edid: pixelclock(138800).
9298 18:08:00.799368 hactive(1920), hsync(48), hfp(24), hbp(88)
9299 18:08:00.802752 vactive(1080), vsync(12), vfp(3), vbp(17)
9300 18:08:00.805971 anx7625_dsi_config: config dsi.
9301 18:08:00.812875 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9302 18:08:00.825426 anx7625_dsi_config: success to config DSI
9303 18:08:00.828105 anx7625_dp_start: MIPI phy setup OK.
9304 18:08:00.831741 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9305 18:08:00.835074 mtk_ddp_mode_set invalid vrefresh 60
9306 18:08:00.838494 main_disp_path_setup
9307 18:08:00.838596 ovl_layer_smi_id_en
9308 18:08:00.841541 ovl_layer_smi_id_en
9309 18:08:00.841638 ccorr_config
9310 18:08:00.841729 aal_config
9311 18:08:00.845408 gamma_config
9312 18:08:00.845510 postmask_config
9313 18:08:00.848659 dither_config
9314 18:08:00.852048 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9315 18:08:00.858423 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9316 18:08:00.861402 Root Device init finished in 554 msecs
9317 18:08:00.864759 CPU_CLUSTER: 0 init
9318 18:08:00.871807 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9319 18:08:00.877921 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9320 18:08:00.878004 APU_MBOX 0x190000b0 = 0x10001
9321 18:08:00.881455 APU_MBOX 0x190001b0 = 0x10001
9322 18:08:00.884959 APU_MBOX 0x190005b0 = 0x10001
9323 18:08:00.887713 APU_MBOX 0x190006b0 = 0x10001
9324 18:08:00.894666 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9325 18:08:00.904162 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9326 18:08:00.916476 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9327 18:08:00.923082 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9328 18:08:00.934867 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9329 18:08:00.943927 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9330 18:08:00.947529 CPU_CLUSTER: 0 init finished in 81 msecs
9331 18:08:00.950530 Devices initialized
9332 18:08:00.954084 Show all devs... After init.
9333 18:08:00.954161 Root Device: enabled 1
9334 18:08:00.957427 CPU_CLUSTER: 0: enabled 1
9335 18:08:00.960859 CPU: 00: enabled 1
9336 18:08:00.963909 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9337 18:08:00.967285 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9338 18:08:00.970359 ELOG: NV offset 0x57f000 size 0x1000
9339 18:08:00.976821 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9340 18:08:00.983345 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9341 18:08:00.986869 ELOG: Event(17) added with size 13 at 2024-06-11 18:03:17 UTC
9342 18:08:00.993929 out: cmd=0x121: 03 db 21 01 00 00 00 00
9343 18:08:00.996678 in-header: 03 e9 00 00 2c 00 00 00
9344 18:08:01.007222 in-data: 76 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 18:08:01.013621 ELOG: Event(A1) added with size 10 at 2024-06-11 18:03:17 UTC
9346 18:08:01.020064 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9347 18:08:01.026853 ELOG: Event(A0) added with size 9 at 2024-06-11 18:03:17 UTC
9348 18:08:01.030301 elog_add_boot_reason: Logged dev mode boot
9349 18:08:01.036492 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9350 18:08:01.036571 Finalize devices...
9351 18:08:01.039808 Devices finalized
9352 18:08:01.043289 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9353 18:08:01.046571 Writing coreboot table at 0xffe64000
9354 18:08:01.050074 0. 000000000010a000-0000000000113fff: RAMSTAGE
9355 18:08:01.053540 1. 0000000040000000-00000000400fffff: RAM
9356 18:08:01.059744 2. 0000000040100000-000000004032afff: RAMSTAGE
9357 18:08:01.063098 3. 000000004032b000-00000000545fffff: RAM
9358 18:08:01.066758 4. 0000000054600000-000000005465ffff: BL31
9359 18:08:01.070205 5. 0000000054660000-00000000ffe63fff: RAM
9360 18:08:01.076701 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9361 18:08:01.079975 7. 0000000100000000-000000023fffffff: RAM
9362 18:08:01.083334 Passing 5 GPIOs to payload:
9363 18:08:01.086519 NAME | PORT | POLARITY | VALUE
9364 18:08:01.089541 EC in RW | 0x000000aa | low | undefined
9365 18:08:01.096268 EC interrupt | 0x00000005 | low | undefined
9366 18:08:01.099491 TPM interrupt | 0x000000ab | high | undefined
9367 18:08:01.106435 SD card detect | 0x00000011 | high | undefined
9368 18:08:01.109924 speaker enable | 0x00000093 | high | undefined
9369 18:08:01.112777 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9370 18:08:01.116435 in-header: 03 f9 00 00 02 00 00 00
9371 18:08:01.119710 in-data: 02 00
9372 18:08:01.123335 ADC[4]: Raw value=904357 ID=7
9373 18:08:01.123418 ADC[3]: Raw value=213810 ID=1
9374 18:08:01.126000 RAM Code: 0x71
9375 18:08:01.129492 ADC[6]: Raw value=75332 ID=0
9376 18:08:01.129573 ADC[5]: Raw value=213072 ID=1
9377 18:08:01.132703 SKU Code: 0x1
9378 18:08:01.136113 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f641
9379 18:08:01.139508 coreboot table: 964 bytes.
9380 18:08:01.142780 IMD ROOT 0. 0xfffff000 0x00001000
9381 18:08:01.146178 IMD SMALL 1. 0xffffe000 0x00001000
9382 18:08:01.149655 RO MCACHE 2. 0xffffc000 0x00001104
9383 18:08:01.153035 CONSOLE 3. 0xfff7c000 0x00080000
9384 18:08:01.156061 FMAP 4. 0xfff7b000 0x00000452
9385 18:08:01.159627 TIME STAMP 5. 0xfff7a000 0x00000910
9386 18:08:01.163342 VBOOT WORK 6. 0xfff66000 0x00014000
9387 18:08:01.165933 RAMOOPS 7. 0xffe66000 0x00100000
9388 18:08:01.169495 COREBOOT 8. 0xffe64000 0x00002000
9389 18:08:01.173008 IMD small region:
9390 18:08:01.176287 IMD ROOT 0. 0xffffec00 0x00000400
9391 18:08:01.179844 VPD 1. 0xffffeb80 0x0000006c
9392 18:08:01.182844 MMC STATUS 2. 0xffffeb60 0x00000004
9393 18:08:01.186119 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9394 18:08:01.189549 Probing TPM: done!
9395 18:08:01.192915 Connected to device vid:did:rid of 1ae0:0028:00
9396 18:08:01.203453 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9397 18:08:01.206675 Initialized TPM device CR50 revision 0
9398 18:08:01.210640 Checking cr50 for pending updates
9399 18:08:01.214570 Reading cr50 TPM mode
9400 18:08:01.222727 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9401 18:08:01.229097 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9402 18:08:01.269384 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9403 18:08:01.272851 Checking segment from ROM address 0x40100000
9404 18:08:01.276475 Checking segment from ROM address 0x4010001c
9405 18:08:01.282816 Loading segment from ROM address 0x40100000
9406 18:08:01.282907 code (compression=0)
9407 18:08:01.289632 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9408 18:08:01.299356 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9409 18:08:01.299439 it's not compressed!
9410 18:08:01.305884 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9411 18:08:01.309270 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9412 18:08:01.329932 Loading segment from ROM address 0x4010001c
9413 18:08:01.330016 Entry Point 0x80000000
9414 18:08:01.333052 Loaded segments
9415 18:08:01.336972 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9416 18:08:01.343807 Jumping to boot code at 0x80000000(0xffe64000)
9417 18:08:01.349751 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9418 18:08:01.357047 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9419 18:08:01.364197 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9420 18:08:01.367562 Checking segment from ROM address 0x40100000
9421 18:08:01.371113 Checking segment from ROM address 0x4010001c
9422 18:08:01.377855 Loading segment from ROM address 0x40100000
9423 18:08:01.377937 code (compression=1)
9424 18:08:01.384811 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9425 18:08:01.394744 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9426 18:08:01.394826 using LZMA
9427 18:08:01.402954 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9428 18:08:01.409517 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9429 18:08:01.412777 Loading segment from ROM address 0x4010001c
9430 18:08:01.412851 Entry Point 0x54601000
9431 18:08:01.415887 Loaded segments
9432 18:08:01.419068 NOTICE: MT8192 bl31_setup
9433 18:08:01.426348 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9434 18:08:01.429546 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9435 18:08:01.433096 WARNING: region 0:
9436 18:08:01.436383 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 18:08:01.436478 WARNING: region 1:
9438 18:08:01.442748 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9439 18:08:01.446383 WARNING: region 2:
9440 18:08:01.449678 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9441 18:08:01.453465 WARNING: region 3:
9442 18:08:01.456498 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 18:08:01.459720 WARNING: region 4:
9444 18:08:01.463291 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 18:08:01.466667 WARNING: region 5:
9446 18:08:01.470057 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 18:08:01.472982 WARNING: region 6:
9448 18:08:01.476325 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 18:08:01.476451 WARNING: region 7:
9450 18:08:01.483214 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 18:08:01.489942 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9452 18:08:01.493199 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9453 18:08:01.496948 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9454 18:08:01.503022 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9455 18:08:01.506518 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9456 18:08:01.509784 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9457 18:08:01.516278 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9458 18:08:01.519803 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9459 18:08:01.523046 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9460 18:08:01.529424 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9461 18:08:01.532853 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9462 18:08:01.539754 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9463 18:08:01.543419 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9464 18:08:01.546160 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9465 18:08:01.552766 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9466 18:08:01.556248 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9467 18:08:01.563067 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9468 18:08:01.565902 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9469 18:08:01.569214 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9470 18:08:01.576167 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9471 18:08:01.579801 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9472 18:08:01.582774 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9473 18:08:01.589278 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9474 18:08:01.592739 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9475 18:08:01.599384 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9476 18:08:01.602868 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9477 18:08:01.606463 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9478 18:08:01.612738 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9479 18:08:01.616085 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9480 18:08:01.623127 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9481 18:08:01.626648 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9482 18:08:01.629493 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9483 18:08:01.636428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9484 18:08:01.639724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9485 18:08:01.643289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9486 18:08:01.646135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9487 18:08:01.649645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9488 18:08:01.656373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9489 18:08:01.659818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9490 18:08:01.663033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9491 18:08:01.666449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9492 18:08:01.673151 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9493 18:08:01.676568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9494 18:08:01.679935 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9495 18:08:01.683368 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9496 18:08:01.689673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9497 18:08:01.692958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9498 18:08:01.696929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9499 18:08:01.703111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9500 18:08:01.706730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9501 18:08:01.710179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9502 18:08:01.716464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9503 18:08:01.719997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9504 18:08:01.726815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9505 18:08:01.729662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9506 18:08:01.736826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9507 18:08:01.739678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9508 18:08:01.743021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9509 18:08:01.749929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9510 18:08:01.753385 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9511 18:08:01.759688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9512 18:08:01.763260 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9513 18:08:01.769751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9514 18:08:01.773209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9515 18:08:01.779982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9516 18:08:01.783514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9517 18:08:01.786834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9518 18:08:01.793132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9519 18:08:01.796656 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9520 18:08:01.803510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9521 18:08:01.806834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9522 18:08:01.810322 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9523 18:08:01.816495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9524 18:08:01.820232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9525 18:08:01.827099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9526 18:08:01.830333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9527 18:08:01.836698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9528 18:08:01.840190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9529 18:08:01.847309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9530 18:08:01.849994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9531 18:08:01.853324 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9532 18:08:01.860226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9533 18:08:01.863164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9534 18:08:01.869856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9535 18:08:01.873748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9536 18:08:01.876597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9537 18:08:01.883630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9538 18:08:01.887163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9539 18:08:01.893728 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9540 18:08:01.897101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9541 18:08:01.903316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9542 18:08:01.906820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9543 18:08:01.913548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9544 18:08:01.916953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9545 18:08:01.920403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9546 18:08:01.926680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9547 18:08:01.930074 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9548 18:08:01.933483 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9549 18:08:01.940272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9550 18:08:01.943324 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9551 18:08:01.946932 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9552 18:08:01.950238 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9553 18:08:01.956975 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9554 18:08:01.960002 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9555 18:08:01.966814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9556 18:08:01.970158 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9557 18:08:01.973808 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9558 18:08:01.980454 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9559 18:08:01.983461 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9560 18:08:01.990293 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9561 18:08:01.993723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9562 18:08:01.997173 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9563 18:08:02.003710 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9564 18:08:02.007291 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9565 18:08:02.013493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9566 18:08:02.016818 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9567 18:08:02.020098 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9568 18:08:02.026834 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9569 18:08:02.030608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9570 18:08:02.033938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9571 18:08:02.037279 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9572 18:08:02.043612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9573 18:08:02.046608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9574 18:08:02.050430 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9575 18:08:02.056759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9576 18:08:02.059847 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9577 18:08:02.063327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9578 18:08:02.070165 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9579 18:08:02.073393 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9580 18:08:02.080017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9581 18:08:02.083164 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9582 18:08:02.086417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9583 18:08:02.093413 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9584 18:08:02.096724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9585 18:08:02.100304 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9586 18:08:02.106599 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9587 18:08:02.109909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9588 18:08:02.113722 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9589 18:08:02.120443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9590 18:08:02.123603 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9591 18:08:02.130645 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9592 18:08:02.133327 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9593 18:08:02.136973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9594 18:08:02.143255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9595 18:08:02.147008 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9596 18:08:02.153209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9597 18:08:02.156602 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9598 18:08:02.160017 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9599 18:08:02.166553 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9600 18:08:02.170016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9601 18:08:02.176909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9602 18:08:02.180160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9603 18:08:02.183396 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9604 18:08:02.190130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9605 18:08:02.193903 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9606 18:08:02.196500 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9607 18:08:02.203334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9608 18:08:02.206771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9609 18:08:02.213754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9610 18:08:02.217116 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9611 18:08:02.220556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9612 18:08:02.226829 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9613 18:08:02.230097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9614 18:08:02.237062 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9615 18:08:02.240319 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9616 18:08:02.243262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9617 18:08:02.250141 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9618 18:08:02.253532 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9619 18:08:02.259871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9620 18:08:02.263230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9621 18:08:02.266520 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9622 18:08:02.272924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9623 18:08:02.276506 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9624 18:08:02.279829 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9625 18:08:02.286138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9626 18:08:02.289463 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9627 18:08:02.296302 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9628 18:08:02.299599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9629 18:08:02.302794 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9630 18:08:02.309719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9631 18:08:02.312789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9632 18:08:02.319706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9633 18:08:02.323056 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9634 18:08:02.326435 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9635 18:08:02.332663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9636 18:08:02.336144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9637 18:08:02.342442 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9638 18:08:02.345827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9639 18:08:02.349155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9640 18:08:02.355472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9641 18:08:02.358834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9642 18:08:02.365889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9643 18:08:02.368801 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9644 18:08:02.375905 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9645 18:08:02.379192 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9646 18:08:02.382423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9647 18:08:02.389301 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9648 18:08:02.392156 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9649 18:08:02.398939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9650 18:08:02.402534 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9651 18:08:02.405496 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9652 18:08:02.412110 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9653 18:08:02.415356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9654 18:08:02.422086 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9655 18:08:02.424984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9656 18:08:02.431839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9657 18:08:02.435229 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9658 18:08:02.438630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9659 18:08:02.445431 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9660 18:08:02.448181 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9661 18:08:02.454957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9662 18:08:02.458316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9663 18:08:02.465401 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9664 18:08:02.468111 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9665 18:08:02.471719 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9666 18:08:02.478210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9667 18:08:02.481499 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9668 18:08:02.488676 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9669 18:08:02.492037 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9670 18:08:02.498139 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9671 18:08:02.501547 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9672 18:08:02.504876 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9673 18:08:02.511266 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9674 18:08:02.514429 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9675 18:08:02.521274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9676 18:08:02.524772 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9677 18:08:02.528141 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9678 18:08:02.534406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9679 18:08:02.538090 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9680 18:08:02.541471 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9681 18:08:02.547744 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9682 18:08:02.551289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9683 18:08:02.554683 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9684 18:08:02.557812 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9685 18:08:02.564520 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9686 18:08:02.567831 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9687 18:08:02.574269 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9688 18:08:02.577750 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9689 18:08:02.581077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9690 18:08:02.587332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9691 18:08:02.590751 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9692 18:08:02.594153 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9693 18:08:02.601210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9694 18:08:02.604139 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9695 18:08:02.607399 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9696 18:08:02.614263 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9697 18:08:02.617822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9698 18:08:02.623942 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9699 18:08:02.627301 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9700 18:08:02.630698 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9701 18:08:02.637506 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9702 18:08:02.640765 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9703 18:08:02.644156 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9704 18:08:02.650817 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9705 18:08:02.654214 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9706 18:08:02.657528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9707 18:08:02.664300 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9708 18:08:02.667152 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9709 18:08:02.673927 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9710 18:08:02.677433 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9711 18:08:02.680289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9712 18:08:02.687444 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9713 18:08:02.690239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9714 18:08:02.693776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9715 18:08:02.700518 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9716 18:08:02.703808 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9717 18:08:02.710252 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9718 18:08:02.713622 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9719 18:08:02.717021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9720 18:08:02.720487 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9721 18:08:02.726727 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9722 18:08:02.730175 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9723 18:08:02.733978 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9724 18:08:02.737422 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9725 18:08:02.740779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9726 18:08:02.747053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9727 18:08:02.750537 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9728 18:08:02.753456 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9729 18:08:02.756799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9730 18:08:02.763927 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9731 18:08:02.767319 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9732 18:08:02.770164 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9733 18:08:02.776733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9734 18:08:02.780170 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9735 18:08:02.787366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9736 18:08:02.790316 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9737 18:08:02.793806 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9738 18:08:02.800513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9739 18:08:02.803477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9740 18:08:02.810578 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9741 18:08:02.813980 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9742 18:08:02.817026 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9743 18:08:02.823534 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9744 18:08:02.826811 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9745 18:08:02.833470 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9746 18:08:02.836798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9747 18:08:02.843583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9748 18:08:02.846549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9749 18:08:02.849908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9750 18:08:02.856806 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9751 18:08:02.860535 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9752 18:08:02.866743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9753 18:08:02.870324 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9754 18:08:02.873303 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9755 18:08:02.880013 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9756 18:08:02.883368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9757 18:08:02.889391 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9758 18:08:02.892933 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9759 18:08:02.896513 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9760 18:08:02.902681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9761 18:08:02.906063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9762 18:08:02.913091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9763 18:08:02.915882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9764 18:08:02.919334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9765 18:08:02.926046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9766 18:08:02.929555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9767 18:08:02.936179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9768 18:08:02.939428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9769 18:08:02.945891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9770 18:08:02.949523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9771 18:08:02.952800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9772 18:08:02.959319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9773 18:08:02.962500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9774 18:08:02.969435 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9775 18:08:02.972997 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9776 18:08:02.975698 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9777 18:08:02.982391 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9778 18:08:02.986215 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9779 18:08:02.992398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9780 18:08:02.995696 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9781 18:08:02.999301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9782 18:08:03.005407 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9783 18:08:03.008866 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9784 18:08:03.015780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9785 18:08:03.019382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9786 18:08:03.025642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9787 18:08:03.029094 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9788 18:08:03.032379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9789 18:08:03.039106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9790 18:08:03.042618 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9791 18:08:03.048604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9792 18:08:03.052293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9793 18:08:03.055365 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9794 18:08:03.062592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9795 18:08:03.065318 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9796 18:08:03.072247 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9797 18:08:03.075350 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9798 18:08:03.078757 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9799 18:08:03.085276 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9800 18:08:03.088883 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9801 18:08:03.095446 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9802 18:08:03.098613 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9803 18:08:03.105675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9804 18:08:03.108407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9805 18:08:03.111685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9806 18:08:03.118517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9807 18:08:03.122148 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9808 18:08:03.128432 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9809 18:08:03.131950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9810 18:08:03.138328 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9811 18:08:03.141506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9812 18:08:03.144753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9813 18:08:03.151612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9814 18:08:03.154892 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9815 18:08:03.161433 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9816 18:08:03.164902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9817 18:08:03.171944 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9818 18:08:03.175163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9819 18:08:03.178702 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9820 18:08:03.184700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9821 18:08:03.188482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9822 18:08:03.194704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9823 18:08:03.198279 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9824 18:08:03.205028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9825 18:08:03.208123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9826 18:08:03.214845 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9827 18:08:03.218064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9828 18:08:03.221201 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9829 18:08:03.227714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9830 18:08:03.231192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9831 18:08:03.238181 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9832 18:08:03.240936 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9833 18:08:03.247807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9834 18:08:03.251035 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9835 18:08:03.254329 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9836 18:08:03.261331 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9837 18:08:03.264883 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9838 18:08:03.271338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9839 18:08:03.274395 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9840 18:08:03.281125 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9841 18:08:03.284709 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9842 18:08:03.291193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9843 18:08:03.294276 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9844 18:08:03.297357 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9845 18:08:03.304154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9846 18:08:03.307642 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9847 18:08:03.314260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9848 18:08:03.317235 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9849 18:08:03.324156 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9850 18:08:03.327383 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9851 18:08:03.330679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9852 18:08:03.336962 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9853 18:08:03.340478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9854 18:08:03.347477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9855 18:08:03.350506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9856 18:08:03.353793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9857 18:08:03.360576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9858 18:08:03.363944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9859 18:08:03.370255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9860 18:08:03.373869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9861 18:08:03.380782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9862 18:08:03.383938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9863 18:08:03.390309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9864 18:08:03.393687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9865 18:08:03.400277 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9866 18:08:03.403663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9867 18:08:03.410192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9868 18:08:03.413669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9869 18:08:03.420624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9870 18:08:03.423765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9871 18:08:03.430188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9872 18:08:03.433771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9873 18:08:03.439939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9874 18:08:03.443725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9875 18:08:03.450498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9876 18:08:03.453904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9877 18:08:03.460131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9878 18:08:03.463481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9879 18:08:03.470442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9880 18:08:03.473164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9881 18:08:03.480073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9882 18:08:03.483549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9883 18:08:03.489927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9884 18:08:03.493524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9885 18:08:03.496992 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9886 18:08:03.500447 INFO: [APUAPC] vio 0
9887 18:08:03.506821 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9888 18:08:03.509872 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9889 18:08:03.513235 INFO: [APUAPC] D0_APC_0: 0x400510
9890 18:08:03.516607 INFO: [APUAPC] D0_APC_1: 0x0
9891 18:08:03.519741 INFO: [APUAPC] D0_APC_2: 0x1540
9892 18:08:03.522966 INFO: [APUAPC] D0_APC_3: 0x0
9893 18:08:03.526625 INFO: [APUAPC] D1_APC_0: 0xffffffff
9894 18:08:03.530017 INFO: [APUAPC] D1_APC_1: 0xffffffff
9895 18:08:03.533297 INFO: [APUAPC] D1_APC_2: 0x3fffff
9896 18:08:03.536427 INFO: [APUAPC] D1_APC_3: 0x0
9897 18:08:03.539949 INFO: [APUAPC] D2_APC_0: 0xffffffff
9898 18:08:03.542794 INFO: [APUAPC] D2_APC_1: 0xffffffff
9899 18:08:03.546249 INFO: [APUAPC] D2_APC_2: 0x3fffff
9900 18:08:03.546330 INFO: [APUAPC] D2_APC_3: 0x0
9901 18:08:03.552994 INFO: [APUAPC] D3_APC_0: 0xffffffff
9902 18:08:03.556190 INFO: [APUAPC] D3_APC_1: 0xffffffff
9903 18:08:03.559538 INFO: [APUAPC] D3_APC_2: 0x3fffff
9904 18:08:03.559619 INFO: [APUAPC] D3_APC_3: 0x0
9905 18:08:03.562944 INFO: [APUAPC] D4_APC_0: 0xffffffff
9906 18:08:03.569210 INFO: [APUAPC] D4_APC_1: 0xffffffff
9907 18:08:03.569293 INFO: [APUAPC] D4_APC_2: 0x3fffff
9908 18:08:03.573056 INFO: [APUAPC] D4_APC_3: 0x0
9909 18:08:03.576482 INFO: [APUAPC] D5_APC_0: 0xffffffff
9910 18:08:03.579254 INFO: [APUAPC] D5_APC_1: 0xffffffff
9911 18:08:03.582783 INFO: [APUAPC] D5_APC_2: 0x3fffff
9912 18:08:03.586247 INFO: [APUAPC] D5_APC_3: 0x0
9913 18:08:03.589694 INFO: [APUAPC] D6_APC_0: 0xffffffff
9914 18:08:03.593460 INFO: [APUAPC] D6_APC_1: 0xffffffff
9915 18:08:03.596122 INFO: [APUAPC] D6_APC_2: 0x3fffff
9916 18:08:03.599718 INFO: [APUAPC] D6_APC_3: 0x0
9917 18:08:03.603215 INFO: [APUAPC] D7_APC_0: 0xffffffff
9918 18:08:03.606080 INFO: [APUAPC] D7_APC_1: 0xffffffff
9919 18:08:03.609740 INFO: [APUAPC] D7_APC_2: 0x3fffff
9920 18:08:03.612991 INFO: [APUAPC] D7_APC_3: 0x0
9921 18:08:03.616161 INFO: [APUAPC] D8_APC_0: 0xffffffff
9922 18:08:03.619589 INFO: [APUAPC] D8_APC_1: 0xffffffff
9923 18:08:03.622803 INFO: [APUAPC] D8_APC_2: 0x3fffff
9924 18:08:03.626220 INFO: [APUAPC] D8_APC_3: 0x0
9925 18:08:03.629785 INFO: [APUAPC] D9_APC_0: 0xffffffff
9926 18:08:03.632931 INFO: [APUAPC] D9_APC_1: 0xffffffff
9927 18:08:03.636485 INFO: [APUAPC] D9_APC_2: 0x3fffff
9928 18:08:03.639704 INFO: [APUAPC] D9_APC_3: 0x0
9929 18:08:03.643042 INFO: [APUAPC] D10_APC_0: 0xffffffff
9930 18:08:03.646114 INFO: [APUAPC] D10_APC_1: 0xffffffff
9931 18:08:03.649653 INFO: [APUAPC] D10_APC_2: 0x3fffff
9932 18:08:03.652879 INFO: [APUAPC] D10_APC_3: 0x0
9933 18:08:03.656351 INFO: [APUAPC] D11_APC_0: 0xffffffff
9934 18:08:03.659230 INFO: [APUAPC] D11_APC_1: 0xffffffff
9935 18:08:03.662591 INFO: [APUAPC] D11_APC_2: 0x3fffff
9936 18:08:03.666190 INFO: [APUAPC] D11_APC_3: 0x0
9937 18:08:03.669470 INFO: [APUAPC] D12_APC_0: 0xffffffff
9938 18:08:03.672803 INFO: [APUAPC] D12_APC_1: 0xffffffff
9939 18:08:03.676247 INFO: [APUAPC] D12_APC_2: 0x3fffff
9940 18:08:03.679698 INFO: [APUAPC] D12_APC_3: 0x0
9941 18:08:03.682741 INFO: [APUAPC] D13_APC_0: 0xffffffff
9942 18:08:03.686120 INFO: [APUAPC] D13_APC_1: 0xffffffff
9943 18:08:03.689623 INFO: [APUAPC] D13_APC_2: 0x3fffff
9944 18:08:03.693245 INFO: [APUAPC] D13_APC_3: 0x0
9945 18:08:03.695913 INFO: [APUAPC] D14_APC_0: 0xffffffff
9946 18:08:03.699310 INFO: [APUAPC] D14_APC_1: 0xffffffff
9947 18:08:03.702918 INFO: [APUAPC] D14_APC_2: 0x3fffff
9948 18:08:03.706225 INFO: [APUAPC] D14_APC_3: 0x0
9949 18:08:03.709680 INFO: [APUAPC] D15_APC_0: 0xffffffff
9950 18:08:03.712558 INFO: [APUAPC] D15_APC_1: 0xffffffff
9951 18:08:03.716054 INFO: [APUAPC] D15_APC_2: 0x3fffff
9952 18:08:03.719581 INFO: [APUAPC] D15_APC_3: 0x0
9953 18:08:03.722461 INFO: [APUAPC] APC_CON: 0x4
9954 18:08:03.725848 INFO: [NOCDAPC] D0_APC_0: 0x0
9955 18:08:03.729440 INFO: [NOCDAPC] D0_APC_1: 0x0
9956 18:08:03.729524 INFO: [NOCDAPC] D1_APC_0: 0x0
9957 18:08:03.732250 INFO: [NOCDAPC] D1_APC_1: 0xfff
9958 18:08:03.736169 INFO: [NOCDAPC] D2_APC_0: 0x0
9959 18:08:03.739644 INFO: [NOCDAPC] D2_APC_1: 0xfff
9960 18:08:03.742965 INFO: [NOCDAPC] D3_APC_0: 0x0
9961 18:08:03.746070 INFO: [NOCDAPC] D3_APC_1: 0xfff
9962 18:08:03.749029 INFO: [NOCDAPC] D4_APC_0: 0x0
9963 18:08:03.752218 INFO: [NOCDAPC] D4_APC_1: 0xfff
9964 18:08:03.755417 INFO: [NOCDAPC] D5_APC_0: 0x0
9965 18:08:03.759351 INFO: [NOCDAPC] D5_APC_1: 0xfff
9966 18:08:03.762549 INFO: [NOCDAPC] D6_APC_0: 0x0
9967 18:08:03.762633 INFO: [NOCDAPC] D6_APC_1: 0xfff
9968 18:08:03.765947 INFO: [NOCDAPC] D7_APC_0: 0x0
9969 18:08:03.768632 INFO: [NOCDAPC] D7_APC_1: 0xfff
9970 18:08:03.772264 INFO: [NOCDAPC] D8_APC_0: 0x0
9971 18:08:03.775666 INFO: [NOCDAPC] D8_APC_1: 0xfff
9972 18:08:03.779294 INFO: [NOCDAPC] D9_APC_0: 0x0
9973 18:08:03.781950 INFO: [NOCDAPC] D9_APC_1: 0xfff
9974 18:08:03.785557 INFO: [NOCDAPC] D10_APC_0: 0x0
9975 18:08:03.788772 INFO: [NOCDAPC] D10_APC_1: 0xfff
9976 18:08:03.792172 INFO: [NOCDAPC] D11_APC_0: 0x0
9977 18:08:03.795586 INFO: [NOCDAPC] D11_APC_1: 0xfff
9978 18:08:03.799097 INFO: [NOCDAPC] D12_APC_0: 0x0
9979 18:08:03.802608 INFO: [NOCDAPC] D12_APC_1: 0xfff
9980 18:08:03.802690 INFO: [NOCDAPC] D13_APC_0: 0x0
9981 18:08:03.805339 INFO: [NOCDAPC] D13_APC_1: 0xfff
9982 18:08:03.808890 INFO: [NOCDAPC] D14_APC_0: 0x0
9983 18:08:03.812560 INFO: [NOCDAPC] D14_APC_1: 0xfff
9984 18:08:03.815842 INFO: [NOCDAPC] D15_APC_0: 0x0
9985 18:08:03.819256 INFO: [NOCDAPC] D15_APC_1: 0xfff
9986 18:08:03.822109 INFO: [NOCDAPC] APC_CON: 0x4
9987 18:08:03.825784 INFO: [APUAPC] set_apusys_apc done
9988 18:08:03.829398 INFO: [DEVAPC] devapc_init done
9989 18:08:03.832205 INFO: GICv3 without legacy support detected.
9990 18:08:03.835607 INFO: ARM GICv3 driver initialized in EL3
9991 18:08:03.838594 INFO: Maximum SPI INTID supported: 639
9992 18:08:03.845165 INFO: BL31: Initializing runtime services
9993 18:08:03.848882 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9994 18:08:03.852058 INFO: SPM: enable CPC mode
9995 18:08:03.858908 INFO: mcdi ready for mcusys-off-idle and system suspend
9996 18:08:03.862394 INFO: BL31: Preparing for EL3 exit to normal world
9997 18:08:03.865718 INFO: Entry point address = 0x80000000
9998 18:08:03.868679 INFO: SPSR = 0x8
9999 18:08:03.874250
10000 18:08:03.874332
10001 18:08:03.874397
10002 18:08:03.875076 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10003 18:08:03.875181 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 18:08:03.875266 Setting prompt string to ['asurada:']
10005 18:08:03.875343 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 18:08:03.877730 Starting depthcharge on Spherion...
10007 18:08:03.877814
10008 18:08:03.877879 Wipe memory regions:
10009 18:08:03.877940
10010 18:08:03.880908 [0x00000040000000, 0x00000054600000)
10011 18:08:04.003400
10012 18:08:04.003538 [0x00000054660000, 0x00000080000000)
10013 18:08:04.263415
10014 18:08:04.263568 [0x000000821a7280, 0x000000ffe64000)
10015 18:08:05.007506
10016 18:08:05.007659 [0x00000100000000, 0x00000240000000)
10017 18:08:06.896373
10018 18:08:06.899802 Initializing XHCI USB controller at 0x11200000.
10019 18:08:07.938253
10020 18:08:07.941305 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10021 18:08:07.941429
10022 18:08:07.941526
10023 18:08:07.941861 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 18:08:08.042281 asurada: tftpboot 192.168.201.1 14291388/tftp-deploy-_npp91nq/kernel/image.itb 14291388/tftp-deploy-_npp91nq/kernel/cmdline
10026 18:08:08.042499 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10027 18:08:08.042623 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10028 18:08:08.047155 tftpboot 192.168.201.1 14291388/tftp-deploy-_npp91nq/kernel/image.ittp-deploy-_npp91nq/kernel/cmdline
10029 18:08:08.047283
10030 18:08:08.047385 Waiting for link
10031 18:08:08.207133
10032 18:08:08.207322 R8152: Initializing
10033 18:08:08.207425
10034 18:08:08.210542 Version 9 (ocp_data = 6010)
10035 18:08:08.210660
10036 18:08:08.214278 R8152: Done initializing
10037 18:08:08.214392
10038 18:08:08.214490 Adding net device
10039 18:08:10.085956
10040 18:08:10.086151 done.
10041 18:08:10.086255
10042 18:08:10.086352 MAC: 00:e0:4c:78:7a:aa
10043 18:08:10.086450
10044 18:08:10.089343 Sending DHCP discover... done.
10045 18:08:10.089454
10046 18:08:13.143301 Waiting for reply... done.
10047 18:08:13.143494
10048 18:08:13.143604 Sending DHCP request... done.
10049 18:08:13.146451
10050 18:08:13.151074 Waiting for reply... done.
10051 18:08:13.151200
10052 18:08:13.151301 My ip is 192.168.201.12
10053 18:08:13.151398
10054 18:08:13.154451 The DHCP server ip is 192.168.201.1
10055 18:08:13.154565
10056 18:08:13.161681 TFTP server IP predefined by user: 192.168.201.1
10057 18:08:13.161799
10058 18:08:13.167571 Bootfile predefined by user: 14291388/tftp-deploy-_npp91nq/kernel/image.itb
10059 18:08:13.167691
10060 18:08:13.167793 Sending tftp read request... done.
10061 18:08:13.171265
10062 18:08:13.174615 Waiting for the transfer...
10063 18:08:13.174734
10064 18:08:13.439259 00000000 ################################################################
10065 18:08:13.439404
10066 18:08:13.781754 00080000 ################################################################
10067 18:08:13.781934
10068 18:08:14.070441 00100000 ################################################################
10069 18:08:14.070586
10070 18:08:14.327466 00180000 ################################################################
10071 18:08:14.327602
10072 18:08:14.591808 00200000 ################################################################
10073 18:08:14.591963
10074 18:08:14.858131 00280000 ################################################################
10075 18:08:14.858312
10076 18:08:15.123616 00300000 ################################################################
10077 18:08:15.123810
10078 18:08:15.382162 00380000 ################################################################
10079 18:08:15.382319
10080 18:08:15.640007 00400000 ################################################################
10081 18:08:15.640192
10082 18:08:15.910628 00480000 ################################################################
10083 18:08:15.910797
10084 18:08:16.199680 00500000 ################################################################
10085 18:08:16.199850
10086 18:08:16.472973 00580000 ################################################################
10087 18:08:16.473126
10088 18:08:16.757294 00600000 ################################################################
10089 18:08:16.757491
10090 18:08:17.052868 00680000 ################################################################
10091 18:08:17.053059
10092 18:08:17.327344 00700000 ################################################################
10093 18:08:17.327493
10094 18:08:17.588803 00780000 ################################################################
10095 18:08:17.588987
10096 18:08:17.851020 00800000 ################################################################
10097 18:08:17.851201
10098 18:08:18.118848 00880000 ################################################################
10099 18:08:18.118990
10100 18:08:18.370999 00900000 ################################################################
10101 18:08:18.371177
10102 18:08:18.640562 00980000 ################################################################
10103 18:08:18.640704
10104 18:08:18.901146 00a00000 ################################################################
10105 18:08:18.901300
10106 18:08:19.172315 00a80000 ################################################################
10107 18:08:19.172491
10108 18:08:19.435810 00b00000 ################################################################
10109 18:08:19.435988
10110 18:08:19.723883 00b80000 ################################################################
10111 18:08:19.724061
10112 18:08:20.001748 00c00000 ################################################################
10113 18:08:20.001908
10114 18:08:20.264202 00c80000 ################################################################
10115 18:08:20.264387
10116 18:08:20.529831 00d00000 ################################################################
10117 18:08:20.529983
10118 18:08:20.794938 00d80000 ################################################################
10119 18:08:20.795109
10120 18:08:21.053647 00e00000 ################################################################
10121 18:08:21.053818
10122 18:08:21.329989 00e80000 ################################################################
10123 18:08:21.330141
10124 18:08:21.621693 00f00000 ################################################################
10125 18:08:21.621858
10126 18:08:21.904652 00f80000 ################################################################
10127 18:08:21.904803
10128 18:08:22.194053 01000000 ################################################################
10129 18:08:22.194203
10130 18:08:22.489257 01080000 ################################################################
10131 18:08:22.489517
10132 18:08:22.783097 01100000 ################################################################
10133 18:08:22.783248
10134 18:08:23.079494 01180000 ################################################################
10135 18:08:23.079673
10136 18:08:23.344698 01200000 ################################################################
10137 18:08:23.344894
10138 18:08:23.608569 01280000 ################################################################
10139 18:08:23.608752
10140 18:08:23.881231 01300000 ################################################################
10141 18:08:23.881391
10142 18:08:24.150543 01380000 ################################################################
10143 18:08:24.150690
10144 18:08:24.431714 01400000 ################################################################
10145 18:08:24.431861
10146 18:08:24.719529 01480000 ################################################################
10147 18:08:24.719680
10148 18:08:25.021417 01500000 ################################################################
10149 18:08:25.021565
10150 18:08:25.320318 01580000 ################################################################
10151 18:08:25.320512
10152 18:08:25.615830 01600000 ################################################################
10153 18:08:25.615969
10154 18:08:25.892178 01680000 ################################################################
10155 18:08:25.892315
10156 18:08:26.148820 01700000 ################################################################
10157 18:08:26.148959
10158 18:08:26.412379 01780000 ################################################################
10159 18:08:26.412511
10160 18:08:26.674756 01800000 ################################################################
10161 18:08:26.674888
10162 18:08:26.934448 01880000 ################################################################
10163 18:08:26.934580
10164 18:08:27.185597 01900000 ################################################################
10165 18:08:27.185744
10166 18:08:27.451770 01980000 ################################################################
10167 18:08:27.451927
10168 18:08:27.711493 01a00000 ################################################################
10169 18:08:27.711631
10170 18:08:27.965877 01a80000 ################################################################
10171 18:08:27.966043
10172 18:08:28.219560 01b00000 ################################################################
10173 18:08:28.219727
10174 18:08:28.482873 01b80000 ################################################################
10175 18:08:28.483008
10176 18:08:28.743111 01c00000 ################################################################
10177 18:08:28.743247
10178 18:08:28.996171 01c80000 ################################################################
10179 18:08:28.996330
10180 18:08:29.252451 01d00000 ################################################################
10181 18:08:29.252618
10182 18:08:29.507762 01d80000 ################################################################
10183 18:08:29.507926
10184 18:08:29.767278 01e00000 ################################################################
10185 18:08:29.767441
10186 18:08:30.025228 01e80000 ################################################################
10187 18:08:30.025388
10188 18:08:30.292305 01f00000 ################################################################
10189 18:08:30.292467
10190 18:08:30.549917 01f80000 ################################################################
10191 18:08:30.550056
10192 18:08:30.810362 02000000 ################################################################
10193 18:08:30.810528
10194 18:08:31.071876 02080000 ################################################################
10195 18:08:31.072055
10196 18:08:31.329366 02100000 ################################################################
10197 18:08:31.329504
10198 18:08:31.593047 02180000 ################################################################
10199 18:08:31.593184
10200 18:08:31.851017 02200000 ################################################################
10201 18:08:31.851157
10202 18:08:32.105719 02280000 ################################################################
10203 18:08:32.105880
10204 18:08:32.366338 02300000 ################################################################
10205 18:08:32.366482
10206 18:08:32.630698 02380000 ################################################################
10207 18:08:32.630861
10208 18:08:32.889870 02400000 ################################################################
10209 18:08:32.890009
10210 18:08:33.151553 02480000 ################################################################
10211 18:08:33.151692
10212 18:08:33.439064 02500000 ################################################################
10213 18:08:33.439203
10214 18:08:33.757696 02580000 ################################################################
10215 18:08:33.757845
10216 18:08:34.087014 02600000 ################################################################
10217 18:08:34.087162
10218 18:08:34.412273 02680000 ################################################################
10219 18:08:34.412420
10220 18:08:34.730136 02700000 ################################################################
10221 18:08:34.730314
10222 18:08:34.985855 02780000 ################################################################
10223 18:08:34.986019
10224 18:08:35.237524 02800000 ################################################################
10225 18:08:35.237688
10226 18:08:35.491977 02880000 ################################################################
10227 18:08:35.492144
10228 18:08:35.733607 02900000 ################################################################
10229 18:08:35.733788
10230 18:08:35.973633 02980000 ################################################################
10231 18:08:35.973811
10232 18:08:36.214143 02a00000 ################################################################
10233 18:08:36.214301
10234 18:08:36.461093 02a80000 ################################################################
10235 18:08:36.461266
10236 18:08:36.702685 02b00000 ################################################################
10237 18:08:36.702856
10238 18:08:36.940016 02b80000 ################################################################
10239 18:08:36.940191
10240 18:08:37.177113 02c00000 ################################################################
10241 18:08:37.177262
10242 18:08:37.415282 02c80000 ################################################################
10243 18:08:37.415455
10244 18:08:37.650491 02d00000 ################################################################
10245 18:08:37.650667
10246 18:08:37.879384 02d80000 ################################################################
10247 18:08:37.879529
10248 18:08:38.110773 02e00000 ################################################################
10249 18:08:38.110942
10250 18:08:38.343646 02e80000 ################################################################
10251 18:08:38.343826
10252 18:08:38.578280 02f00000 ################################################################
10253 18:08:38.578457
10254 18:08:38.807763 02f80000 ################################################################
10255 18:08:38.807947
10256 18:08:39.037558 03000000 ################################################################
10257 18:08:39.037722
10258 18:08:39.269615 03080000 ################################################################
10259 18:08:39.269784
10260 18:08:39.504238 03100000 ################################################################
10261 18:08:39.504419
10262 18:08:39.737961 03180000 ################################################################
10263 18:08:39.738125
10264 18:08:39.972700 03200000 ################################################################
10265 18:08:39.972866
10266 18:08:40.206356 03280000 ################################################################
10267 18:08:40.206519
10268 18:08:40.440879 03300000 ################################################################
10269 18:08:40.441083
10270 18:08:40.675089 03380000 ################################################################
10271 18:08:40.675256
10272 18:08:40.907154 03400000 ################################################################
10273 18:08:40.907321
10274 18:08:41.140378 03480000 ################################################################
10275 18:08:41.140550
10276 18:08:41.375594 03500000 ################################################################
10277 18:08:41.375771
10278 18:08:41.612650 03580000 ################################################################
10279 18:08:41.612788
10280 18:08:41.863274 03600000 ################################################################
10281 18:08:41.863450
10282 18:08:42.107669 03680000 ################################################################
10283 18:08:42.107802
10284 18:08:42.355533 03700000 ################################################################
10285 18:08:42.355672
10286 18:08:42.599759 03780000 ################################################################
10287 18:08:42.599922
10288 18:08:42.847038 03800000 ################################################################
10289 18:08:42.847199
10290 18:08:43.093330 03880000 ################################################################
10291 18:08:43.093469
10292 18:08:43.342148 03900000 ################################################################
10293 18:08:43.342298
10294 18:08:43.588278 03980000 ################################################################
10295 18:08:43.588433
10296 18:08:43.833081 03a00000 ################################################################
10297 18:08:43.833219
10298 18:08:44.093978 03a80000 ################################################################
10299 18:08:44.094116
10300 18:08:44.345825 03b00000 ################################################################
10301 18:08:44.345959
10302 18:08:44.593236 03b80000 ################################################################
10303 18:08:44.593408
10304 18:08:44.841132 03c00000 ################################################################
10305 18:08:44.841298
10306 18:08:45.089261 03c80000 ################################################################
10307 18:08:45.089436
10308 18:08:45.339094 03d00000 ################################################################
10309 18:08:45.339270
10310 18:08:45.585785 03d80000 ################################################################
10311 18:08:45.585959
10312 18:08:45.833234 03e00000 ################################################################
10313 18:08:45.833404
10314 18:08:46.083910 03e80000 ################################################################
10315 18:08:46.084065
10316 18:08:46.336584 03f00000 ################################################################
10317 18:08:46.336735
10318 18:08:46.582252 03f80000 ################################################################
10319 18:08:46.582386
10320 18:08:46.828842 04000000 ################################################################
10321 18:08:46.829025
10322 18:08:47.070544 04080000 ################################################################
10323 18:08:47.070734
10324 18:08:47.314283 04100000 ################################################################
10325 18:08:47.314455
10326 18:08:47.566300 04180000 ################################################################
10327 18:08:47.566434
10328 18:08:47.811898 04200000 ################################################################
10329 18:08:47.812039
10330 18:08:48.055386 04280000 ################################################################
10331 18:08:48.055557
10332 18:08:48.299119 04300000 ################################################################
10333 18:08:48.299295
10334 18:08:48.540466 04380000 ################################################################
10335 18:08:48.540640
10336 18:08:48.786653 04400000 ################################################################
10337 18:08:48.786832
10338 18:08:49.031789 04480000 ################################################################
10339 18:08:49.031924
10340 18:08:49.279044 04500000 ################################################################
10341 18:08:49.279196
10342 18:08:49.520877 04580000 ################################################################
10343 18:08:49.521058
10344 18:08:49.770577 04600000 ################################################################
10345 18:08:49.770744
10346 18:08:49.889718 04680000 ############################### done.
10347 18:08:49.889886
10348 18:08:49.892867 The bootfile was 74176738 bytes long.
10349 18:08:49.892984
10350 18:08:49.893085 Sending tftp read request... done.
10351 18:08:49.896115
10352 18:08:49.896250 Waiting for the transfer...
10353 18:08:49.896378
10354 18:08:49.899648 00000000 # done.
10355 18:08:49.899769
10356 18:08:49.906546 Command line loaded dynamically from TFTP file: 14291388/tftp-deploy-_npp91nq/kernel/cmdline
10357 18:08:49.906680
10358 18:08:49.919638 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10359 18:08:49.919766
10360 18:08:49.922627 Loading FIT.
10361 18:08:49.922743
10362 18:08:49.926391 Image ramdisk-1 has 61002343 bytes.
10363 18:08:49.926511
10364 18:08:49.926607 Image fdt-1 has 47258 bytes.
10365 18:08:49.926700
10366 18:08:49.929354 Image kernel-1 has 13125101 bytes.
10367 18:08:49.929433
10368 18:08:49.939105 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10369 18:08:49.939227
10370 18:08:49.956234 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10371 18:08:49.956381
10372 18:08:49.962628 Choosing best match conf-1 for compat google,spherion-rev2.
10373 18:08:49.966486
10374 18:08:49.971106 Connected to device vid:did:rid of 1ae0:0028:00
10375 18:08:49.979565
10376 18:08:49.982371 tpm_get_response: command 0x17b, return code 0x0
10377 18:08:49.982458
10378 18:08:49.985530 ec_init: CrosEC protocol v3 supported (256, 248)
10379 18:08:49.989369
10380 18:08:49.993175 tpm_cleanup: add release locality here.
10381 18:08:49.993271
10382 18:08:49.993338 Shutting down all USB controllers.
10383 18:08:49.996189
10384 18:08:49.996264 Removing current net device
10385 18:08:49.996327
10386 18:08:50.003216 Exiting depthcharge with code 4 at timestamp: 75393031
10387 18:08:50.003310
10388 18:08:50.006662 LZMA decompressing kernel-1 to 0x821a6718
10389 18:08:50.006750
10390 18:08:50.009703 LZMA decompressing kernel-1 to 0x40000000
10391 18:08:51.626990
10392 18:08:51.627123 jumping to kernel
10393 18:08:51.627648 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10394 18:08:51.627751 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10395 18:08:51.627830 Setting prompt string to ['Linux version [0-9]']
10396 18:08:51.627899 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10397 18:08:51.627968 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10398 18:08:51.710074
10399 18:08:51.713434 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10400 18:08:51.716985 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10401 18:08:51.717087 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10402 18:08:51.717161 Setting prompt string to []
10403 18:08:51.717290 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10404 18:08:51.717431 Using line separator: #'\n'#
10405 18:08:51.717495 No login prompt set.
10406 18:08:51.717560 Parsing kernel messages
10407 18:08:51.717616 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10408 18:08:51.717724 [login-action] Waiting for messages, (timeout 00:03:37)
10409 18:08:51.717792 Waiting using forced prompt support (timeout 00:01:49)
10410 18:08:51.736840 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10411 18:08:51.739780 [ 0.000000] random: crng init done
10412 18:08:51.746425 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10413 18:08:51.749505 [ 0.000000] efi: UEFI not found.
10414 18:08:51.756484 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10415 18:08:51.766011 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10416 18:08:51.772923 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10417 18:08:51.783217 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10418 18:08:51.789725 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10419 18:08:51.796310 [ 0.000000] printk: bootconsole [mtk8250] enabled
10420 18:08:51.803010 [ 0.000000] NUMA: No NUMA configuration found
10421 18:08:51.809428 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10422 18:08:51.812396 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10423 18:08:51.816252 [ 0.000000] Zone ranges:
10424 18:08:51.822659 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10425 18:08:51.826310 [ 0.000000] DMA32 empty
10426 18:08:51.832837 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10427 18:08:51.836305 [ 0.000000] Movable zone start for each node
10428 18:08:51.839137 [ 0.000000] Early memory node ranges
10429 18:08:51.846052 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10430 18:08:51.852616 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10431 18:08:51.859277 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10432 18:08:51.865811 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10433 18:08:51.872585 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10434 18:08:51.879139 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10435 18:08:51.934591 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10436 18:08:51.941221 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10437 18:08:51.948314 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10438 18:08:51.951041 [ 0.000000] psci: probing for conduit method from DT.
10439 18:08:51.957476 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10440 18:08:51.961057 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10441 18:08:51.968101 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10442 18:08:51.970863 [ 0.000000] psci: SMC Calling Convention v1.2
10443 18:08:51.977742 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10444 18:08:51.981503 [ 0.000000] Detected VIPT I-cache on CPU0
10445 18:08:51.988069 [ 0.000000] CPU features: detected: GIC system register CPU interface
10446 18:08:51.994161 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10447 18:08:52.000851 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10448 18:08:52.008033 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10449 18:08:52.014161 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10450 18:08:52.024457 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10451 18:08:52.027410 [ 0.000000] alternatives: applying boot alternatives
10452 18:08:52.034176 [ 0.000000] Fallback order for Node 0: 0
10453 18:08:52.040954 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10454 18:08:52.043879 [ 0.000000] Policy zone: Normal
10455 18:08:52.057243 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10456 18:08:52.066911 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10457 18:08:52.078758 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10458 18:08:52.088799 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10459 18:08:52.096043 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10460 18:08:52.098711 <6>[ 0.000000] software IO TLB: area num 8.
10461 18:08:52.155753 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10462 18:08:52.305324 <6>[ 0.000000] Memory: 7904488K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 448280K reserved, 32768K cma-reserved)
10463 18:08:52.311455 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10464 18:08:52.318077 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10465 18:08:52.321860 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10466 18:08:52.327982 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10467 18:08:52.334484 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10468 18:08:52.337753 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10469 18:08:52.347702 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10470 18:08:52.354560 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10471 18:08:52.361053 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10472 18:08:52.367750 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10473 18:08:52.370965 <6>[ 0.000000] GICv3: 608 SPIs implemented
10474 18:08:52.374684 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10475 18:08:52.380674 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10476 18:08:52.384246 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10477 18:08:52.390728 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10478 18:08:52.404079 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10479 18:08:52.417210 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10480 18:08:52.424038 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10481 18:08:52.431327 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10482 18:08:52.445279 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10483 18:08:52.451389 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10484 18:08:52.457968 <6>[ 0.009178] Console: colour dummy device 80x25
10485 18:08:52.468210 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10486 18:08:52.474530 <6>[ 0.024375] pid_max: default: 32768 minimum: 301
10487 18:08:52.477780 <6>[ 0.029246] LSM: Security Framework initializing
10488 18:08:52.484212 <6>[ 0.034184] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10489 18:08:52.494673 <6>[ 0.041997] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10490 18:08:52.504055 <6>[ 0.051412] cblist_init_generic: Setting adjustable number of callback queues.
10491 18:08:52.507463 <6>[ 0.058899] cblist_init_generic: Setting shift to 3 and lim to 1.
10492 18:08:52.517456 <6>[ 0.065238] cblist_init_generic: Setting adjustable number of callback queues.
10493 18:08:52.524393 <6>[ 0.072664] cblist_init_generic: Setting shift to 3 and lim to 1.
10494 18:08:52.527518 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10495 18:08:52.534058 <6>[ 0.084119] rcu: Max phase no-delay instances is 1000.
10496 18:08:52.540841 <6>[ 0.091177] EFI services will not be available.
10497 18:08:52.543691 <6>[ 0.096164] smp: Bringing up secondary CPUs ...
10498 18:08:52.552134 <6>[ 0.101214] Detected VIPT I-cache on CPU1
10499 18:08:52.559312 <6>[ 0.101286] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10500 18:08:52.565620 <6>[ 0.101318] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10501 18:08:52.569179 <6>[ 0.101654] Detected VIPT I-cache on CPU2
10502 18:08:52.579005 <6>[ 0.101706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10503 18:08:52.585677 <6>[ 0.101722] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10504 18:08:52.588377 <6>[ 0.101981] Detected VIPT I-cache on CPU3
10505 18:08:52.595481 <6>[ 0.102028] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10506 18:08:52.601529 <6>[ 0.102041] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10507 18:08:52.605292 <6>[ 0.102345] CPU features: detected: Spectre-v4
10508 18:08:52.612004 <6>[ 0.102351] CPU features: detected: Spectre-BHB
10509 18:08:52.614837 <6>[ 0.102356] Detected PIPT I-cache on CPU4
10510 18:08:52.621961 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10511 18:08:52.628097 <6>[ 0.102431] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10512 18:08:52.634558 <6>[ 0.102723] Detected PIPT I-cache on CPU5
10513 18:08:52.641558 <6>[ 0.102786] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10514 18:08:52.647952 <6>[ 0.102802] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10515 18:08:52.650981 <6>[ 0.103086] Detected PIPT I-cache on CPU6
10516 18:08:52.657843 <6>[ 0.103152] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10517 18:08:52.668117 <6>[ 0.103168] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10518 18:08:52.671092 <6>[ 0.103465] Detected PIPT I-cache on CPU7
10519 18:08:52.677899 <6>[ 0.103533] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10520 18:08:52.684629 <6>[ 0.103549] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10521 18:08:52.687782 <6>[ 0.103596] smp: Brought up 1 node, 8 CPUs
10522 18:08:52.694409 <6>[ 0.245094] SMP: Total of 8 processors activated.
10523 18:08:52.698192 <6>[ 0.250015] CPU features: detected: 32-bit EL0 Support
10524 18:08:52.708079 <6>[ 0.255411] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10525 18:08:52.714668 <6>[ 0.264212] CPU features: detected: Common not Private translations
10526 18:08:52.721230 <6>[ 0.270688] CPU features: detected: CRC32 instructions
10527 18:08:52.724675 <6>[ 0.276039] CPU features: detected: RCpc load-acquire (LDAPR)
10528 18:08:52.730864 <6>[ 0.282036] CPU features: detected: LSE atomic instructions
10529 18:08:52.737850 <6>[ 0.287818] CPU features: detected: Privileged Access Never
10530 18:08:52.744312 <6>[ 0.293633] CPU features: detected: RAS Extension Support
10531 18:08:52.750645 <6>[ 0.299242] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10532 18:08:52.754320 <6>[ 0.306461] CPU: All CPU(s) started at EL2
10533 18:08:52.761164 <6>[ 0.310777] alternatives: applying system-wide alternatives
10534 18:08:52.770098 <6>[ 0.321612] devtmpfs: initialized
10535 18:08:52.782322 <6>[ 0.330423] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10536 18:08:52.792159 <6>[ 0.340380] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10537 18:08:52.798958 <6>[ 0.348393] pinctrl core: initialized pinctrl subsystem
10538 18:08:52.802465 <6>[ 0.355074] DMI not present or invalid.
10539 18:08:52.809446 <6>[ 0.359481] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10540 18:08:52.819172 <6>[ 0.366330] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10541 18:08:52.825606 <6>[ 0.373917] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10542 18:08:52.835950 <6>[ 0.382136] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10543 18:08:52.838925 <6>[ 0.390376] audit: initializing netlink subsys (disabled)
10544 18:08:52.848484 <5>[ 0.396073] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10545 18:08:52.855426 <6>[ 0.396784] thermal_sys: Registered thermal governor 'step_wise'
10546 18:08:52.861973 <6>[ 0.404039] thermal_sys: Registered thermal governor 'power_allocator'
10547 18:08:52.865569 <6>[ 0.410295] cpuidle: using governor menu
10548 18:08:52.872337 <6>[ 0.421255] NET: Registered PF_QIPCRTR protocol family
10549 18:08:52.878331 <6>[ 0.426738] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10550 18:08:52.881921 <6>[ 0.433842] ASID allocator initialised with 32768 entries
10551 18:08:52.889121 <6>[ 0.440413] Serial: AMBA PL011 UART driver
10552 18:08:52.897956 <4>[ 0.449298] Trying to register duplicate clock ID: 134
10553 18:08:52.956167 <6>[ 0.510839] KASLR enabled
10554 18:08:52.970447 <6>[ 0.518545] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10555 18:08:52.977261 <6>[ 0.525559] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10556 18:08:52.984243 <6>[ 0.532047] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10557 18:08:52.990180 <6>[ 0.539051] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10558 18:08:52.996862 <6>[ 0.545536] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10559 18:08:53.003970 <6>[ 0.552541] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10560 18:08:53.010314 <6>[ 0.559028] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10561 18:08:53.016825 <6>[ 0.566032] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10562 18:08:53.020067 <6>[ 0.573511] ACPI: Interpreter disabled.
10563 18:08:53.028488 <6>[ 0.579944] iommu: Default domain type: Translated
10564 18:08:53.034895 <6>[ 0.585057] iommu: DMA domain TLB invalidation policy: strict mode
10565 18:08:53.038589 <5>[ 0.591718] SCSI subsystem initialized
10566 18:08:53.045167 <6>[ 0.595886] usbcore: registered new interface driver usbfs
10567 18:08:53.051548 <6>[ 0.601619] usbcore: registered new interface driver hub
10568 18:08:53.055069 <6>[ 0.607170] usbcore: registered new device driver usb
10569 18:08:53.062269 <6>[ 0.613272] pps_core: LinuxPPS API ver. 1 registered
10570 18:08:53.072178 <6>[ 0.618465] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10571 18:08:53.075061 <6>[ 0.627812] PTP clock support registered
10572 18:08:53.078786 <6>[ 0.632055] EDAC MC: Ver: 3.0.0
10573 18:08:53.085765 <6>[ 0.637217] FPGA manager framework
10574 18:08:53.092562 <6>[ 0.640902] Advanced Linux Sound Architecture Driver Initialized.
10575 18:08:53.096295 <6>[ 0.647674] vgaarb: loaded
10576 18:08:53.102185 <6>[ 0.650819] clocksource: Switched to clocksource arch_sys_counter
10577 18:08:53.106095 <5>[ 0.657236] VFS: Disk quotas dquot_6.6.0
10578 18:08:53.112195 <6>[ 0.661423] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10579 18:08:53.115897 <6>[ 0.668613] pnp: PnP ACPI: disabled
10580 18:08:53.123911 <6>[ 0.675315] NET: Registered PF_INET protocol family
10581 18:08:53.133944 <6>[ 0.680907] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10582 18:08:53.145338 <6>[ 0.693248] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10583 18:08:53.155237 <6>[ 0.702061] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10584 18:08:53.162099 <6>[ 0.710035] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10585 18:08:53.168785 <6>[ 0.718734] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10586 18:08:53.180373 <6>[ 0.728493] TCP: Hash tables configured (established 65536 bind 65536)
10587 18:08:53.187321 <6>[ 0.735355] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10588 18:08:53.194055 <6>[ 0.742553] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10589 18:08:53.200227 <6>[ 0.750254] NET: Registered PF_UNIX/PF_LOCAL protocol family
10590 18:08:53.206688 <6>[ 0.756414] RPC: Registered named UNIX socket transport module.
10591 18:08:53.210636 <6>[ 0.762567] RPC: Registered udp transport module.
10592 18:08:53.216729 <6>[ 0.767500] RPC: Registered tcp transport module.
10593 18:08:53.223743 <6>[ 0.772432] RPC: Registered tcp NFSv4.1 backchannel transport module.
10594 18:08:53.226651 <6>[ 0.779100] PCI: CLS 0 bytes, default 64
10595 18:08:53.229737 <6>[ 0.783434] Unpacking initramfs...
10596 18:08:53.254745 <6>[ 0.802936] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10597 18:08:53.264627 <6>[ 0.811586] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10598 18:08:53.268230 <6>[ 0.820427] kvm [1]: IPA Size Limit: 40 bits
10599 18:08:53.274712 <6>[ 0.824945] kvm [1]: GICv3: no GICV resource entry
10600 18:08:53.277776 <6>[ 0.829966] kvm [1]: disabling GICv2 emulation
10601 18:08:53.284773 <6>[ 0.834668] kvm [1]: GIC system register CPU interface enabled
10602 18:08:53.288052 <6>[ 0.840847] kvm [1]: vgic interrupt IRQ18
10603 18:08:53.294381 <6>[ 0.845199] kvm [1]: VHE mode initialized successfully
10604 18:08:53.301127 <5>[ 0.851667] Initialise system trusted keyrings
10605 18:08:53.307986 <6>[ 0.856456] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10606 18:08:53.315501 <6>[ 0.866441] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10607 18:08:53.322194 <5>[ 0.872866] NFS: Registering the id_resolver key type
10608 18:08:53.325233 <5>[ 0.878160] Key type id_resolver registered
10609 18:08:53.331395 <5>[ 0.882575] Key type id_legacy registered
10610 18:08:53.338253 <6>[ 0.886869] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10611 18:08:53.345349 <6>[ 0.893792] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10612 18:08:53.351288 <6>[ 0.901525] 9p: Installing v9fs 9p2000 file system support
10613 18:08:53.387957 <5>[ 0.938866] Key type asymmetric registered
10614 18:08:53.390849 <5>[ 0.943197] Asymmetric key parser 'x509' registered
10615 18:08:53.400510 <6>[ 0.948351] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10616 18:08:53.404033 <6>[ 0.955971] io scheduler mq-deadline registered
10617 18:08:53.407410 <6>[ 0.960746] io scheduler kyber registered
10618 18:08:53.426520 <6>[ 0.977663] EINJ: ACPI disabled.
10619 18:08:53.459430 <4>[ 1.003755] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 18:08:53.469191 <4>[ 1.014388] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 18:08:53.484061 <6>[ 1.035439] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10622 18:08:53.492135 <6>[ 1.043454] printk: console [ttyS0] disabled
10623 18:08:53.519940 <6>[ 1.068085] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10624 18:08:53.526642 <6>[ 1.077584] printk: console [ttyS0] enabled
10625 18:08:53.530550 <6>[ 1.077584] printk: console [ttyS0] enabled
10626 18:08:53.536989 <6>[ 1.086478] printk: bootconsole [mtk8250] disabled
10627 18:08:53.540222 <6>[ 1.086478] printk: bootconsole [mtk8250] disabled
10628 18:08:53.546805 <6>[ 1.097688] SuperH (H)SCI(F) driver initialized
10629 18:08:53.550173 <6>[ 1.102985] msm_serial: driver initialized
10630 18:08:53.564033 <6>[ 1.111983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10631 18:08:53.574038 <6>[ 1.120529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10632 18:08:53.580662 <6>[ 1.129071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10633 18:08:53.591240 <6>[ 1.137700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10634 18:08:53.597394 <6>[ 1.146407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10635 18:08:53.607253 <6>[ 1.155121] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10636 18:08:53.617647 <6>[ 1.163664] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10637 18:08:53.624381 <6>[ 1.172469] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10638 18:08:53.634454 <6>[ 1.181013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10639 18:08:53.645479 <6>[ 1.196730] loop: module loaded
10640 18:08:53.652218 <6>[ 1.202705] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10641 18:08:53.674540 <4>[ 1.226092] mtk-pmic-keys: Failed to locate of_node [id: -1]
10642 18:08:53.681999 <6>[ 1.232969] megasas: 07.719.03.00-rc1
10643 18:08:53.690903 <6>[ 1.242552] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10644 18:08:53.699311 <6>[ 1.250207] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10645 18:08:53.715568 <6>[ 1.266993] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10646 18:08:53.772232 <6>[ 1.317147] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10647 18:08:55.925713 <6>[ 3.477389] Freeing initrd memory: 59568K
10648 18:08:55.937816 <6>[ 3.489098] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10649 18:08:55.948433 <6>[ 3.499962] tun: Universal TUN/TAP device driver, 1.6
10650 18:08:55.951394 <6>[ 3.506025] thunder_xcv, ver 1.0
10651 18:08:55.955337 <6>[ 3.509532] thunder_bgx, ver 1.0
10652 18:08:55.958035 <6>[ 3.513029] nicpf, ver 1.0
10653 18:08:55.968880 <6>[ 3.517034] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10654 18:08:55.972321 <6>[ 3.524509] hns3: Copyright (c) 2017 Huawei Corporation.
10655 18:08:55.979210 <6>[ 3.530095] hclge is initializing
10656 18:08:55.981954 <6>[ 3.533673] e1000: Intel(R) PRO/1000 Network Driver
10657 18:08:55.988762 <6>[ 3.538803] e1000: Copyright (c) 1999-2006 Intel Corporation.
10658 18:08:55.991876 <6>[ 3.544816] e1000e: Intel(R) PRO/1000 Network Driver
10659 18:08:55.998620 <6>[ 3.550031] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10660 18:08:56.005106 <6>[ 3.556216] igb: Intel(R) Gigabit Ethernet Network Driver
10661 18:08:56.011642 <6>[ 3.561865] igb: Copyright (c) 2007-2014 Intel Corporation.
10662 18:08:56.018298 <6>[ 3.567703] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10663 18:08:56.024894 <6>[ 3.574221] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10664 18:08:56.028538 <6>[ 3.580677] sky2: driver version 1.30
10665 18:08:56.035018 <6>[ 3.585596] usbcore: registered new device driver r8152-cfgselector
10666 18:08:56.041336 <6>[ 3.592132] usbcore: registered new interface driver r8152
10667 18:08:56.048065 <6>[ 3.597946] VFIO - User Level meta-driver version: 0.3
10668 18:08:56.054898 <6>[ 3.606182] usbcore: registered new interface driver usb-storage
10669 18:08:56.061669 <6>[ 3.612627] usbcore: registered new device driver onboard-usb-hub
10670 18:08:56.070065 <6>[ 3.621751] mt6397-rtc mt6359-rtc: registered as rtc0
10671 18:08:56.080201 <6>[ 3.627218] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:04:12 UTC (1718129052)
10672 18:08:56.083230 <6>[ 3.636777] i2c_dev: i2c /dev entries driver
10673 18:08:56.096914 <4>[ 3.648691] cpu cpu0: supply cpu not found, using dummy regulator
10674 18:08:56.103849 <4>[ 3.655130] cpu cpu1: supply cpu not found, using dummy regulator
10675 18:08:56.110773 <4>[ 3.661536] cpu cpu2: supply cpu not found, using dummy regulator
10676 18:08:56.117219 <4>[ 3.667949] cpu cpu3: supply cpu not found, using dummy regulator
10677 18:08:56.123590 <4>[ 3.674347] cpu cpu4: supply cpu not found, using dummy regulator
10678 18:08:56.130400 <4>[ 3.680742] cpu cpu5: supply cpu not found, using dummy regulator
10679 18:08:56.137106 <4>[ 3.687161] cpu cpu6: supply cpu not found, using dummy regulator
10680 18:08:56.143224 <4>[ 3.693558] cpu cpu7: supply cpu not found, using dummy regulator
10681 18:08:56.162434 <6>[ 3.714196] cpu cpu0: EM: created perf domain
10682 18:08:56.166031 <6>[ 3.719122] cpu cpu4: EM: created perf domain
10683 18:08:56.172707 <6>[ 3.724393] sdhci: Secure Digital Host Controller Interface driver
10684 18:08:56.179488 <6>[ 3.730826] sdhci: Copyright(c) Pierre Ossman
10685 18:08:56.186575 <6>[ 3.735780] Synopsys Designware Multimedia Card Interface Driver
10686 18:08:56.192658 <6>[ 3.742409] sdhci-pltfm: SDHCI platform and OF driver helper
10687 18:08:56.196383 <6>[ 3.742453] mmc0: CQHCI version 5.10
10688 18:08:56.202954 <6>[ 3.752785] ledtrig-cpu: registered to indicate activity on CPUs
10689 18:08:56.209621 <6>[ 3.759863] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10690 18:08:56.216096 <6>[ 3.766955] usbcore: registered new interface driver usbhid
10691 18:08:56.219196 <6>[ 3.772776] usbhid: USB HID core driver
10692 18:08:56.225837 <6>[ 3.776968] spi_master spi0: will run message pump with realtime priority
10693 18:08:56.273821 <6>[ 3.819062] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10694 18:08:56.292768 <6>[ 3.834715] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10695 18:08:56.296283 <6>[ 3.846803] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10696 18:08:56.303738 <6>[ 3.855496] cros-ec-spi spi0.0: Chrome EC device registered
10697 18:08:56.310272 <6>[ 3.861549] mmc0: Command Queue Engine enabled
10698 18:08:56.316927 <6>[ 3.866276] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10699 18:08:56.323570 <6>[ 3.874053] mmcblk0: mmc0:0001 DA4128 116 GiB
10700 18:08:56.330082 <6>[ 3.874728] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10701 18:08:56.336870 <6>[ 3.882306] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10702 18:08:56.343557 <6>[ 3.889250] NET: Registered PF_PACKET protocol family
10703 18:08:56.347405 <6>[ 3.894981] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10704 18:08:56.353389 <6>[ 3.899395] 9pnet: Installing 9P2000 support
10705 18:08:56.357186 <6>[ 3.905132] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10706 18:08:56.364050 <5>[ 3.909092] Key type dns_resolver registered
10707 18:08:56.370082 <6>[ 3.914973] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10708 18:08:56.373663 <6>[ 3.919326] registered taskstats version 1
10709 18:08:56.376787 <5>[ 3.929682] Loading compiled-in X.509 certificates
10710 18:08:56.411873 <4>[ 3.956871] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10711 18:08:56.421388 <4>[ 3.967546] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10712 18:08:56.435604 <6>[ 3.987315] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10713 18:08:56.442257 <6>[ 3.994075] xhci-mtk 11200000.usb: xHCI Host Controller
10714 18:08:56.449185 <6>[ 3.999582] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10715 18:08:56.459485 <6>[ 4.007444] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10716 18:08:56.465653 <6>[ 4.016882] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10717 18:08:56.472308 <6>[ 4.023109] xhci-mtk 11200000.usb: xHCI Host Controller
10718 18:08:56.479450 <6>[ 4.028605] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10719 18:08:56.485959 <6>[ 4.036269] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10720 18:08:56.492688 <6>[ 4.044108] hub 1-0:1.0: USB hub found
10721 18:08:56.496273 <6>[ 4.048141] hub 1-0:1.0: 1 port detected
10722 18:08:56.502888 <6>[ 4.052447] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10723 18:08:56.509205 <6>[ 4.061238] hub 2-0:1.0: USB hub found
10724 18:08:56.512707 <6>[ 4.065280] hub 2-0:1.0: 1 port detected
10725 18:08:56.521623 <6>[ 4.073270] mtk-msdc 11f70000.mmc: Got CD GPIO
10726 18:08:56.536149 <6>[ 4.084607] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10727 18:08:56.546473 <6>[ 4.092998] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10728 18:08:56.553005 <6>[ 4.101340] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10729 18:08:56.562641 <6>[ 4.109681] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10730 18:08:56.569619 <6>[ 4.118019] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10731 18:08:56.579454 <6>[ 4.126357] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10732 18:08:56.586343 <6>[ 4.134696] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10733 18:08:56.595950 <6>[ 4.143033] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10734 18:08:56.602471 <6>[ 4.151375] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10735 18:08:56.612328 <6>[ 4.159714] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10736 18:08:56.619284 <6>[ 4.168052] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10737 18:08:56.629256 <6>[ 4.176395] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10738 18:08:56.635856 <6>[ 4.184734] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10739 18:08:56.645844 <6>[ 4.193073] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10740 18:08:56.652618 <6>[ 4.201411] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10741 18:08:56.658633 <6>[ 4.210015] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10742 18:08:56.665546 <6>[ 4.217165] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10743 18:08:56.672642 <6>[ 4.223977] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10744 18:08:56.682433 <6>[ 4.230741] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10745 18:08:56.689341 <6>[ 4.237682] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10746 18:08:56.695489 <6>[ 4.244564] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10747 18:08:56.705159 <6>[ 4.253698] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10748 18:08:56.715575 <6>[ 4.262821] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10749 18:08:56.725280 <6>[ 4.272115] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10750 18:08:56.735212 <6>[ 4.281582] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10751 18:08:56.741875 <6>[ 4.291048] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10752 18:08:56.751874 <6>[ 4.300169] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10753 18:08:56.761953 <6>[ 4.309634] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10754 18:08:56.772076 <6>[ 4.318753] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10755 18:08:56.781842 <6>[ 4.328048] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10756 18:08:56.791221 <6>[ 4.338208] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10757 18:08:56.801538 <6>[ 4.349995] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10758 18:08:56.926295 <6>[ 4.475105] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10759 18:08:57.081193 <6>[ 4.632952] hub 1-1:1.0: USB hub found
10760 18:08:57.084926 <6>[ 4.637459] hub 1-1:1.0: 4 ports detected
10761 18:08:57.094799 <6>[ 4.646699] hub 1-1:1.0: USB hub found
10762 18:08:57.098369 <6>[ 4.651120] hub 1-1:1.0: 4 ports detected
10763 18:08:57.206909 <6>[ 4.755426] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10764 18:08:57.233177 <6>[ 4.785045] hub 2-1:1.0: USB hub found
10765 18:08:57.236317 <6>[ 4.789571] hub 2-1:1.0: 3 ports detected
10766 18:08:57.248207 <6>[ 4.799777] hub 2-1:1.0: USB hub found
10767 18:08:57.251060 <6>[ 4.804204] hub 2-1:1.0: 3 ports detected
10768 18:08:57.418559 <6>[ 4.967079] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10769 18:08:57.551099 <6>[ 5.103014] hub 1-1.4:1.0: USB hub found
10770 18:08:57.554343 <6>[ 5.107686] hub 1-1.4:1.0: 2 ports detected
10771 18:08:57.567324 <6>[ 5.118727] hub 1-1.4:1.0: USB hub found
10772 18:08:57.570290 <6>[ 5.123418] hub 1-1.4:1.0: 2 ports detected
10773 18:08:57.638663 <6>[ 5.187084] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10774 18:08:57.747449 <6>[ 5.295780] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10775 18:08:57.782793 <4>[ 5.331078] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10776 18:08:57.792700 <4>[ 5.340206] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10777 18:08:57.832196 <6>[ 5.383950] r8152 2-1.3:1.0 eth0: v1.12.13
10778 18:08:57.870145 <6>[ 5.419000] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10779 18:08:58.062359 <6>[ 5.610946] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10780 18:08:59.503491 <6>[ 7.055701] r8152 2-1.3:1.0 eth0: carrier on
10781 18:09:00.181659 <5>[ 7.086878] Sending DHCP requests .
10782 18:09:00.188215 <3>[ 7.733049] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[7c7e2508]
10783 18:09:00.194816 <3>[ 7.743687] DHCP/BOOTP: Reply not for us on eth0, op[2] xid[7c7e2508]
10784 18:09:02.539651 <4>[ 10.079130] ., OK
10785 18:09:02.549387 <6>[ 10.097159] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10786 18:09:02.552683 <6>[ 10.105466] IP-Config: Complete:
10787 18:09:02.563284 <6>[ 10.108962] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10788 18:09:02.572549 <6>[ 10.119681] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10789 18:09:02.579240 <6>[ 10.128304] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10790 18:09:02.582535 <6>[ 10.128313] nameserver0=192.168.201.1
10791 18:09:02.589107 <6>[ 10.140507] clk: Disabling unused clocks
10792 18:09:02.592932 <6>[ 10.146016] ALSA device list:
10793 18:09:02.595968 <6>[ 10.149300] No soundcards found.
10794 18:09:02.605087 <6>[ 10.156910] Freeing unused kernel memory: 8512K
10795 18:09:02.608783 <6>[ 10.161820] Run /init as init process
10796 18:09:02.638257 <6>[ 10.190296] NET: Registered PF_INET6 protocol family
10797 18:09:02.645457 <6>[ 10.197137] Segment Routing with IPv6
10798 18:09:02.648437 <6>[ 10.201080] In-situ OAM (IOAM) with IPv6
10799 18:09:02.691593 <30>[ 10.217132] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10800 18:09:02.698439 <30>[ 10.250192] systemd[1]: Detected architecture arm64.
10801 18:09:02.698777
10802 18:09:02.704699 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10803 18:09:02.704999
10804 18:09:02.723461 <30>[ 10.275176] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10805 18:09:02.834791 <30>[ 10.383422] systemd[1]: Queued start job for default target graphical.target.
10806 18:09:02.883628 <30>[ 10.432717] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10807 18:09:02.890363 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10808 18:09:02.911531 <30>[ 10.459822] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10809 18:09:02.920983 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10810 18:09:02.938835 <30>[ 10.487937] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10811 18:09:02.948560 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10812 18:09:02.966410 <30>[ 10.515649] systemd[1]: Created slice user.slice - User and Session Slice.
10813 18:09:02.973363 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10814 18:09:02.993266 <30>[ 10.539211] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10815 18:09:02.999827 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10816 18:09:03.022541 <30>[ 10.567737] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10817 18:09:03.028890 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10818 18:09:03.056324 <30>[ 10.595578] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10819 18:09:03.066695 <30>[ 10.615452] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10820 18:09:03.073255 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10821 18:09:03.090148 <30>[ 10.639348] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10822 18:09:03.097258 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10823 18:09:03.114113 <30>[ 10.663139] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10824 18:09:03.124057 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10825 18:09:03.138839 <30>[ 10.691137] systemd[1]: Reached target paths.target - Path Units.
10826 18:09:03.145085 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10827 18:09:03.166742 <30>[ 10.715503] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10828 18:09:03.172678 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10829 18:09:03.186608 <30>[ 10.739047] systemd[1]: Reached target slices.target - Slice Units.
10830 18:09:03.196856 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10831 18:09:03.210418 <30>[ 10.763101] systemd[1]: Reached target swap.target - Swaps.
10832 18:09:03.217356 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10833 18:09:03.233893 <30>[ 10.783092] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10834 18:09:03.243827 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10835 18:09:03.263097 <30>[ 10.811974] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10836 18:09:03.272559 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10837 18:09:03.292314 <30>[ 10.841135] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10838 18:09:03.301872 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10839 18:09:03.318886 <30>[ 10.867815] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10840 18:09:03.328644 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10841 18:09:03.346675 <30>[ 10.895764] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10842 18:09:03.353543 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10843 18:09:03.370692 <30>[ 10.919753] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10844 18:09:03.380147 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10845 18:09:03.398548 <30>[ 10.947604] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10846 18:09:03.408649 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10847 18:09:03.458027 <30>[ 11.007256] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10848 18:09:03.464781 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10849 18:09:03.483637 <30>[ 11.032901] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10850 18:09:03.490106 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10851 18:09:03.512208 <30>[ 11.061358] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10852 18:09:03.518833 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10853 18:09:03.544998 <30>[ 11.087694] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10854 18:09:03.558384 <30>[ 11.107484] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10855 18:09:03.568106 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10856 18:09:03.618227 <30>[ 11.167494] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10857 18:09:03.624879 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10858 18:09:03.650970 <30>[ 11.200346] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10859 18:09:03.664447 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 11.213825] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10860 18:09:03.668161 Module dm_mod...
10861 18:09:03.691776 <30>[ 11.240457] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10862 18:09:03.697771 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10863 18:09:03.762436 <30>[ 11.311731] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10864 18:09:03.772519 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10865 18:09:03.795435 <30>[ 11.344466] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10866 18:09:03.801503 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10867 18:09:03.830771 <30>[ 11.380067] systemd[1]: Starting systemd-journald.service - Journal Service...
10868 18:09:03.837587 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10869 18:09:03.857428 <30>[ 11.406349] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10870 18:09:03.863807 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10871 18:09:03.888320 <30>[ 11.434178] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10872 18:09:03.894802 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10873 18:09:03.918133 <30>[ 11.467649] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10874 18:09:03.928794 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10875 18:09:03.949033 <30>[ 11.498353] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10876 18:09:03.955929 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10877 18:09:03.978923 <30>[ 11.528080] systemd[1]: Started systemd-journald.service - Journal Service.
10878 18:09:03.985465 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10879 18:09:04.004763 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10880 18:09:04.022992 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10881 18:09:04.043053 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10882 18:09:04.062731 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10883 18:09:04.088506 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10884 18:09:04.111764 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10885 18:09:04.136454 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10886 18:09:04.157044 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10887 18:09:04.177290 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10888 18:09:04.200838 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10889 18:09:04.219730 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10890 18:09:04.240436 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10891 18:09:04.247567 See 'systemctl status systemd-remount-fs.service' for details.
10892 18:09:04.256944 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10893 18:09:04.276990 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10894 18:09:04.350193 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10895 18:09:04.374934 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10896 18:09:04.393708 <46>[ 11.942876] systemd-journald[183]: Received client request to flush runtime journal.
10897 18:09:04.406585 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10898 18:09:04.427408 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10899 18:09:04.450203 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10900 18:09:04.475565 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10901 18:09:04.495518 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10902 18:09:04.515346 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10903 18:09:04.535479 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10904 18:09:04.555196 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10905 18:09:04.627103 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10906 18:09:04.653004 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10907 18:09:04.670507 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10908 18:09:04.689988 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10909 18:09:04.751110 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10910 18:09:04.775561 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10911 18:09:04.798235 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10912 18:09:04.853127 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10913 18:09:04.880281 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10914 18:09:04.901358 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10915 18:09:04.964306 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10916 18:09:04.989026 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10917 18:09:05.023344 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10918 18:09:05.111473 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10919 18:09:05.131249 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10920 18:09:05.150810 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10921 18:09:05.157724 <6>[ 12.707866] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10922 18:09:05.177710 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard <6>[ 12.724389] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10923 18:09:05.184003 unused blocks on<6>[ 12.733823] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10924 18:09:05.187417 ce a week.
10925 18:09:05.194378 <4>[ 12.743265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10926 18:09:05.204456 <6>[ 12.753903] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10927 18:09:05.211134 <6>[ 12.758009] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10928 18:09:05.221061 <6>[ 12.762082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10929 18:09:05.227827 <6>[ 12.769621] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10930 18:09:05.237652 <3>[ 12.778301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10931 18:09:05.244521 <6>[ 12.784840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10932 18:09:05.251029 <6>[ 12.784860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10933 18:09:05.261104 <6>[ 12.784865] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10934 18:09:05.270709 <6>[ 12.784871] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10935 18:09:05.277544 <6>[ 12.786222] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10936 18:09:05.284145 <6>[ 12.818531] mc: Linux media interface: v0.10
10937 18:09:05.290519 <4>[ 12.818529] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10938 18:09:05.297552 <6>[ 12.818583] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10939 18:09:05.304402 <4>[ 12.818653] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10940 18:09:05.313817 <3>[ 12.827162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10941 18:09:05.320564 <6>[ 12.831846] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10942 18:09:05.327411 <6>[ 12.837854] remoteproc remoteproc0: scp is available
10943 18:09:05.334065 <3>[ 12.840406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10944 18:09:05.340289 <6>[ 12.847993] remoteproc remoteproc0: powering up scp
10945 18:09:05.346971 <3>[ 12.855375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10946 18:09:05.356768 <6>[ 12.863600] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10947 18:09:05.360415 <6>[ 12.864424] videodev: Linux video capture interface: v2.00
10948 18:09:05.370715 <3>[ 12.871414] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10949 18:09:05.374417 <6>[ 12.878280] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10950 18:09:05.385161 <4>[ 12.879619] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10951 18:09:05.388141 <4>[ 12.879619] Fallback method does not support PEC.
10952 18:09:05.397594 <3>[ 12.883416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10953 18:09:05.404469 <6>[ 12.904713] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10954 18:09:05.411195 <3>[ 12.913241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10955 18:09:05.417508 <6>[ 12.918959] pci_bus 0000:00: root bus resource [bus 00-ff]
10956 18:09:05.424434 <3>[ 12.927081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 18:09:05.434458 <6>[ 12.927503] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10958 18:09:05.444917 <6>[ 12.931555] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10959 18:09:05.454651 <6>[ 12.931957] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10960 18:09:05.461335 <6>[ 12.932636] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10961 18:09:05.470829 <6>[ 12.932641] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10962 18:09:05.477515 <6>[ 12.932714] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10963 18:09:05.487158 <3>[ 12.936650] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 18:09:05.493782 <3>[ 12.946427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 18:09:05.500708 <6>[ 12.954389] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10966 18:09:05.507598 <6>[ 12.954456] pci 0000:00:00.0: supports D1 D2
10967 18:09:05.514489 <3>[ 12.961398] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 18:09:05.521188 <6>[ 12.969335] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10969 18:09:05.528227 <6>[ 12.970691] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10970 18:09:05.539025 <3>[ 12.975165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 18:09:05.545812 <6>[ 12.983414] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10972 18:09:05.552615 <3>[ 12.992572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 18:09:05.555498 <6>[ 12.993385] Bluetooth: Core ver 2.22
10974 18:09:05.562447 <6>[ 12.993490] NET: Registered PF_BLUETOOTH protocol family
10975 18:09:05.568675 <6>[ 12.993494] Bluetooth: HCI device and connection manager initialized
10976 18:09:05.572182 <6>[ 12.993513] Bluetooth: HCI socket layer initialized
10977 18:09:05.579070 <6>[ 12.993522] Bluetooth: L2CAP socket layer initialized
10978 18:09:05.585527 <6>[ 12.993536] Bluetooth: SCO socket layer initialized
10979 18:09:05.592233 <6>[ 13.002645] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10980 18:09:05.599118 <6>[ 13.004624] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10981 18:09:05.612863 <6>[ 13.005833] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10982 18:09:05.615732 <6>[ 13.005926] usbcore: registered new interface driver uvcvideo
10983 18:09:05.625803 <3>[ 13.011990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 18:09:05.632406 <6>[ 13.017148] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10985 18:09:05.639434 <6>[ 13.018791] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10986 18:09:05.646410 <6>[ 13.018794] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10987 18:09:05.652833 <6>[ 13.018800] remoteproc remoteproc0: remote processor scp is now up
10988 18:09:05.663045 <3>[ 13.028746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 18:09:05.669440 <6>[ 13.029371] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10990 18:09:05.676544 <6>[ 13.030460] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10991 18:09:05.686250 <6>[ 13.033113] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10992 18:09:05.693402 <6>[ 13.034974] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10993 18:09:05.700182 <3>[ 13.043852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10994 18:09:05.706955 <6>[ 13.051951] pci 0000:01:00.0: supports D1 D2
10995 18:09:05.710889 <6>[ 13.052473] usbcore: registered new interface driver btusb
10996 18:09:05.720476 <4>[ 13.053421] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10997 18:09:05.727356 <3>[ 13.053434] Bluetooth: hci0: Failed to load firmware file (-2)
10998 18:09:05.734099 <3>[ 13.053437] Bluetooth: hci0: Failed to set up firmware (-2)
10999 18:09:05.743475 <4>[ 13.053442] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11000 18:09:05.753554 <3>[ 13.059333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11001 18:09:05.760111 <6>[ 13.063843] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11002 18:09:05.766773 <3>[ 13.071920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11003 18:09:05.774853 <3>[ 13.090431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 18:09:05.784409 <6>[ 13.095002] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11005 18:09:05.791498 <6>[ 13.095030] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11006 18:09:05.798042 <6>[ 13.095033] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11007 18:09:05.808361 <6>[ 13.095041] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11008 18:09:05.815016 <6>[ 13.095054] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11009 18:09:05.825187 <6>[ 13.095066] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11010 18:09:05.828977 <6>[ 13.095079] pci 0000:00:00.0: PCI bridge to [bus 01]
11011 18:09:05.835797 <6>[ 13.095084] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11012 18:09:05.845498 <3>[ 13.095151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 18:09:05.849257 <6>[ 13.095232] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11014 18:09:05.856240 <6>[ 13.095710] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11015 18:09:05.862378 <6>[ 13.096161] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11016 18:09:05.873164 <3>[ 13.101761] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11017 18:09:05.879821 <3>[ 13.113878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 18:09:05.889495 <5>[ 13.115145] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11019 18:09:05.896140 <3>[ 13.117997] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11020 18:09:05.903252 <5>[ 13.131979] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11021 18:09:05.912739 <3>[ 13.152249] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 18:09:05.919540 <5>[ 13.156034] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11023 18:09:05.929704 <3>[ 13.198511] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 18:09:05.939516 <4>[ 13.205373] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11025 18:09:05.945613 <3>[ 13.233536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 18:09:05.952110 <6>[ 13.234690] cfg80211: failed to load regulatory.db
11027 18:09:05.959084 <3>[ 13.264022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 18:09:05.969014 <6>[ 13.306949] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11029 18:09:05.975888 <3>[ 13.331145] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 18:09:05.982612 <6>[ 13.333812] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11031 18:09:05.989035 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11032 18:09:06.007136 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<6>[ 13.558993] mt7921e 0000:01:00.0: ASIC revision: 79610010
11033 18:09:06.013559 ocket[…- D-Bus System Message Bus Socket.
11034 18:09:06.030198 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11035 18:09:06.050166 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11036 18:09:06.103501 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11037 18:09:06.113498 <6>[ 13.661472] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11038 18:09:06.113631 <6>[ 13.661472]
11039 18:09:06.139930 <46>[ 13.675773] systemd-journald[183]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11040 18:09:06.152688 <46>[ 13.697066] systemd-journald[183]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11041 18:09:06.166165 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11042 18:09:06.184621 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11043 18:09:06.203307 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11044 18:09:06.244978 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11045 18:09:06.300859 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11046 18:09:06.322942 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11047 18:09:06.338635 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11048 18:09:06.359444 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11049 18:09:06.383083 <6>[ 13.931613] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11050 18:09:06.420382 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11051 18:09:06.446075 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11052 18:09:06.463163 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11053 18:09:06.478884 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11054 18:09:06.498928 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11055 18:09:06.563890 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11056 18:09:06.589180 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11057 18:09:06.614116 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11058 18:09:06.684264 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11059 18:09:06.703340 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11060 18:09:06.727792 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11061 18:09:06.769053
11062 18:09:06.772611 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11063 18:09:06.772750
11064 18:09:06.775437 debian-bookworm-arm64 login: root (automatic login)
11065 18:09:06.775539
11066 18:09:06.792125 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11067 18:09:06.792261
11068 18:09:06.798529 The programs included with the Debian GNU/Linux system are free software;
11069 18:09:06.805540 the exact distribution terms for each program are described in the
11070 18:09:06.808606 individual files in /usr/share/doc/*/copyright.
11071 18:09:06.808766
11072 18:09:06.815235 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11073 18:09:06.818278 permitted by applicable law.
11074 18:09:06.818728 Matched prompt #10: / #
11076 18:09:06.818929 Setting prompt string to ['/ #']
11077 18:09:06.819024 end: 2.2.5.1 login-action (duration 00:00:15) [common]
11079 18:09:06.819218 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11080 18:09:06.819305 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11081 18:09:06.819375 Setting prompt string to ['/ #']
11082 18:09:06.819436 Forcing a shell prompt, looking for ['/ #']
11084 18:09:06.869646 / #
11085 18:09:06.869848 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11086 18:09:06.869962 Waiting using forced prompt support (timeout 00:02:30)
11087 18:09:06.874413
11088 18:09:06.874693 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11089 18:09:06.874787 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
11090 18:09:06.874882 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11091 18:09:06.874972 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
11092 18:09:06.875084 end: 2 depthcharge-action (duration 00:01:38) [common]
11093 18:09:06.875190 start: 3 lava-test-retry (timeout 00:07:56) [common]
11094 18:09:06.875278 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11095 18:09:06.875370 Using namespace: common
11097 18:09:06.975710 / # #
11098 18:09:06.975872 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11099 18:09:06.980841 #
11100 18:09:06.981111 Using /lava-14291388
11102 18:09:07.081430 / # export SHELL=/bin/sh
11103 18:09:07.086301 export SHELL=/bin/sh
11105 18:09:07.186825 / # . /lava-14291388/environment
11106 18:09:07.191983 . /lava-14291388/environment
11108 18:09:07.292509 / # /lava-14291388/bin/lava-test-runner /lava-14291388/0
11109 18:09:07.292662 Test shell timeout: 10s (minimum of the action and connection timeout)
11110 18:09:07.293010 /lava-14291388/bin/lava-test-runner /lava-14291388/0<6>[ 14.819257] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11111 18:09:07.297645
11112 18:09:07.344472 + export TESTRUN_ID=0_igt-kms-me<8>[ 14.877679] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14291388_1.5.2.3.1>
11113 18:09:07.344601 diatek
11114 18:09:07.344672 + cd /lava-14291388/0/tests/0_igt-kms-mediatek
11115 18:09:07.344735 + cat uuid
11116 18:09:07.344795 + UUID=14291388_1.5.2.3.1
11117 18:09:07.344854 + set +x
11118 18:09:07.345094 Received signal: <STARTRUN> 0_igt-kms-mediatek 14291388_1.5.2.3.1
11119 18:09:07.345160 Starting test lava.0_igt-kms-mediatek (14291388_1.5.2.3.1)
11120 18:09:07.345238 Skipping test definition patterns.
11121 18:09:07.349337 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getsta<8>[ 14.901357] <LAVA_SIGNAL_TESTSET START core_auth>
11122 18:09:07.349587 Received signal: <TESTSET> START core_auth
11123 18:09:07.349658 Starting test_set core_auth
11124 18:09:07.362899 ts core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11125 18:09:07.368957 <14>[ 14.921716] [IGT] core_auth: executing
11126 18:09:07.375985 IGT-Version: 1.2<14>[ 14.926098] [IGT] core_auth: starting subtest getclient-simple
11127 18:09:07.385867 8-ga44ebfe (aarc<14>[ 14.933823] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11128 18:09:07.388653 h64) (Linux: 6.1<14>[ 14.942057] [IGT] core_auth: exiting, ret=0
11129 18:09:07.392315 .92-cip22 aarch64)
11130 18:09:07.395269 Using IGT_SRANDOM=1718129064 for randomisation
11131 18:09:07.405333 Starting sub<8>[ 14.953535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11132 18:09:07.405424 test: getclient-simple
11133 18:09:07.405707 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11135 18:09:07.408493 Opened device: /dev/dri/card0
11136 18:09:07.412299 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11137 18:09:07.423000 <14>[ 14.975673] [IGT] core_auth: executing
11138 18:09:07.429090 IGT-Version: 1.2<14>[ 14.980031] [IGT] core_auth: starting subtest getclient-master-drop
11139 18:09:07.439698 8-ga44ebfe (aarc<14>[ 14.988099] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11140 18:09:07.446362 h64) (Linux: 6.1<14>[ 14.996793] [IGT] core_auth: exiting, ret=0
11141 18:09:07.446455 .92-cip22 aarch64)
11142 18:09:07.455753 Using IGT_SRANDOM=1718129064<8>[ 15.006776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11143 18:09:07.456015 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11145 18:09:07.459210 for randomisation
11146 18:09:07.462764 Starting subtest: getclient-master-drop
11147 18:09:07.465532 Opened device: /dev/dri/card0
11148 18:09:07.468893 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11149 18:09:07.475684 <14>[ 15.028170] [IGT] core_auth: executing
11150 18:09:07.482460 IGT-Version: 1.2<14>[ 15.032567] [IGT] core_auth: starting subtest basic-auth
11151 18:09:07.489185 8-ga44ebfe (aarc<14>[ 15.039581] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11152 18:09:07.495487 <14>[ 15.047336] [IGT] core_auth: exiting, ret=0
11153 18:09:07.495572 h64) (Linux: 6.1.92-cip22 aarch64)
11154 18:09:07.509277 Using IGT_SRANDOM=1718129064 for randomisati<8>[ 15.057485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11155 18:09:07.509372 on
11156 18:09:07.509613 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11158 18:09:07.512315 Opened device: /dev/dri/card0
11159 18:09:07.512427 Starting subtest: basic-auth
11160 18:09:07.518387 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11161 18:09:07.527498 <14>[ 15.080663] [IGT] core_auth: executing
11162 18:09:07.534399 IGT-Version: 1.2<14>[ 15.085093] [IGT] core_auth: starting subtest many-magics
11163 18:09:07.538115 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11164 18:09:07.547821 Using IGT_SRANDOM=1718129064<14>[ 15.098286] [IGT] core_auth: finished subtest many-magics, SUCCESS
11165 18:09:07.554721 for randomisati<14>[ 15.105579] [IGT] core_auth: exiting, ret=0
11166 18:09:07.554816 on
11167 18:09:07.557679 Opened device: /dev/dri/card0
11168 18:09:07.560976 Starting subtest: many-magics
11169 18:09:07.567700 Reopening devi<8>[ 15.117099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11170 18:09:07.567990 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11172 18:09:07.570773 ce failed after 1020 opens
11173 18:09:07.574506 [1m<8>[ 15.127689] <LAVA_SIGNAL_TESTSET STOP>
11174 18:09:07.574761 Received signal: <TESTSET> STOP
11175 18:09:07.574837 Closing test_set core_auth
11176 18:09:07.577357 Subtest many-magics: SUCCESS (0.006s)[0m
11177 18:09:07.607330 <14>[ 15.160188] [IGT] core_getclient: executing
11178 18:09:07.614007 IGT-Version: 1.2<14>[ 15.165197] [IGT] core_getclient: exiting, ret=0
11179 18:09:07.617037 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11180 18:09:07.627591 Using IGT_SR<8>[ 15.175884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11181 18:09:07.627850 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11183 18:09:07.630535 ANDOM=1718129064 for randomisation
11184 18:09:07.630610 Opened device: /dev/dri/card0
11185 18:09:07.633567 SUCCESS (0.006s)
11186 18:09:07.669569 <14>[ 15.222685] [IGT] core_getstats: executing
11187 18:09:07.676469 IGT-Version: 1.2<14>[ 15.227701] [IGT] core_getstats: exiting, ret=0
11188 18:09:07.679616 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11189 18:09:07.689636 Using IGT_SRANDOM=1718129064<8>[ 15.239310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11190 18:09:07.689921 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11192 18:09:07.693452 for randomisation
11193 18:09:07.693530 Opened device: /dev/dri/card0
11194 18:09:07.696524 SUCCESS (0.006s)
11195 18:09:07.734059 <14>[ 15.287132] [IGT] core_getversion: executing
11196 18:09:07.741297 IGT-Version: 1.2<14>[ 15.292411] [IGT] core_getversion: exiting, ret=0
11197 18:09:07.744325 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11198 18:09:07.757302 Using IGT_SRANDOM=1718129064 for randomisati<8>[ 15.305896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11199 18:09:07.757410 on
11200 18:09:07.757677 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11202 18:09:07.760584 Opened device: /dev/dri/card0
11203 18:09:07.760668 SUCCESS (0.006s)
11204 18:09:07.802075 <14>[ 15.354745] [IGT] core_setmaster_vs_auth: executing
11205 18:09:07.808442 IGT-Version: 1.2<14>[ 15.360404] [IGT] core_setmaster_vs_auth: exiting, ret=0
11206 18:09:07.814899 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11207 18:09:07.825049 Using IGT_SRANDOM=1718129064<8>[ 15.372738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11208 18:09:07.825151 for randomisation
11209 18:09:07.825418 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11211 18:09:07.828639 Opened device: /dev/dri/card0
11212 18:09:07.831475 SUCCESS (0.007s)
11213 18:09:07.847673 <8>[ 15.400255] <LAVA_SIGNAL_TESTSET START drm_read>
11214 18:09:07.847959 Received signal: <TESTSET> START drm_read
11215 18:09:07.848032 Starting test_set drm_read
11216 18:09:07.866230 <14>[ 15.418856] [IGT] drm_read: executing
11217 18:09:07.869206 IGT-Version: 1.2<14>[ 15.423450] [IGT] drm_read: exiting, ret=77
11218 18:09:07.876088 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11219 18:09:07.885991 Using IGT_SRANDOM=1718129064<8>[ 15.435023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11220 18:09:07.886082 for randomisation
11221 18:09:07.886342 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11223 18:09:07.889106 Opened device: /dev/dri/card0
11224 18:09:07.892997 No KMS driver or no outputs, pipes: 16, outputs: 0
11225 18:09:07.899122 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11226 18:09:07.902506 <14>[ 15.456860] [IGT] drm_read: executing
11227 18:09:07.909325 IGT-Version: 1.2<14>[ 15.461463] [IGT] drm_read: exiting, ret=77
11228 18:09:07.912196 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11229 18:09:07.922347 Using IGT_SRANDOM=1718129064<8>[ 15.473906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11230 18:09:07.922644 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11232 18:09:07.926023 for randomisation
11233 18:09:07.928853 Opened device: /dev/dri/card0
11234 18:09:07.932577 No KMS driver or no outputs, pipes: 16, outputs: 0
11235 18:09:07.935388 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11236 18:09:07.943003 <14>[ 15.495562] [IGT] drm_read: executing
11237 18:09:07.949517 IGT-Version: 1.2<14>[ 15.500040] [IGT] drm_read: exiting, ret=77
11238 18:09:07.952502 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11239 18:09:07.959122 Using IGT_SR<8>[ 15.510735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11240 18:09:07.959385 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11242 18:09:07.962660 ANDOM=1718129064 for randomisation
11243 18:09:07.966229 Opened device: /dev/dri/card0
11244 18:09:07.969419 No KMS driver or no outputs, pipes: 16, outputs: 0
11245 18:09:07.976106 [1mSubtest empty-block: SKIP (0.000s)[0m
11246 18:09:07.979161 <14>[ 15.532235] [IGT] drm_read: executing
11247 18:09:07.985858 IGT-Version: 1.2<14>[ 15.536818] [IGT] drm_read: exiting, ret=77
11248 18:09:07.988966 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11249 18:09:07.995758 Using IGT_SR<8>[ 15.547786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11250 18:09:07.996049 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11252 18:09:07.999529 ANDOM=1718129064 for randomisation
11253 18:09:08.002604 Opened device: /dev/dri/card0
11254 18:09:08.008839 No KMS driver or no outputs, pipes: 16, outputs: 0
11255 18:09:08.012492 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11256 18:09:08.019182 <14>[ 15.571727] [IGT] drm_read: executing
11257 18:09:08.022117 IGT-Version: 1.2<14>[ 15.576179] [IGT] drm_read: exiting, ret=77
11258 18:09:08.029264 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11259 18:09:08.035715 Using IGT_SR<8>[ 15.586945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11260 18:09:08.036292 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11262 18:09:08.039517 ANDOM=1718129065 for randomisation
11263 18:09:08.042407 Opened device: /dev/dri/card0
11264 18:09:08.049592 No KMS driver or no outputs, pipes: 16, outputs: 0
11265 18:09:08.056026 [1mSubtest short-buffer-block: SKIP (0.0<14>[ 15.608256] [IGT] drm_read: executing
11266 18:09:08.056750 00s)[0m
11267 18:09:08.058767 <14>[ 15.613226] [IGT] drm_read: exiting, ret=77
11268 18:09:08.065798 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11269 18:09:08.076602 Using IGT_SR<8>[ 15.623887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11270 18:09:08.077132 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11272 18:09:08.079429 ANDOM=1718129065 for randomisation
11273 18:09:08.081862 Opened device: /dev/dri/card0
11274 18:09:08.085574 No KMS driver or no outputs, pipes: 16, outputs: 0
11275 18:09:08.092269 [1mSubtest short-buffer-nonblock: SKIP (<14>[ 15.646637] [IGT] drm_read: executing
11276 18:09:08.095373 0.000s)[0m
11277 18:09:08.098398 <14>[ 15.651600] [IGT] drm_read: exiting, ret=77
11278 18:09:08.111496 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 15.662053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11279 18:09:08.111679 4)
11280 18:09:08.112016 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11282 18:09:08.118269 Using IGT_SRANDOM=1718129065<8>[ 15.671448] <LAVA_SIGNAL_TESTSET STOP>
11283 18:09:08.118699 Received signal: <TESTSET> STOP
11284 18:09:08.118917 Closing test_set drm_read
11285 18:09:08.121921 for randomisation
11286 18:09:08.122151 Opened device: /dev/dri/card0
11287 18:09:08.128722 No KMS driver or no outputs, pipes: 16, outputs: 0
11288 18:09:08.131650 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11289 18:09:08.150831 <8>[ 15.703400] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11290 18:09:08.151483 Received signal: <TESTSET> START kms_addfb_basic
11291 18:09:08.151879 Starting test_set kms_addfb_basic
11292 18:09:08.186214 <14>[ 15.738652] [IGT] kms_addfb_basic: executing
11293 18:09:08.199647 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 15.748326] [IGT] kms_addfb_basic: starting subtest unused-handle
11294 18:09:08.200160 4)
11295 18:09:08.206279 Using IGT_SR<14>[ 15.755784] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11296 18:09:08.208990 ANDOM=1718129065 for randomisation
11297 18:09:08.212805 Opened device: /dev/dri/card0
11298 18:09:08.215778 Starting subtest: unused-handle
11299 18:09:08.222705 [1mSubtest <14>[ 15.773285] [IGT] kms_addfb_basic: exiting, ret=0
11300 18:09:08.225779 unused-handle: SUCCESS (0.000s)[0m
11301 18:09:08.232542 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11303 18:09:08.235904 Test requirement not met in<8>[ 15.784235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11304 18:09:08.238478 function igt_require_intel, file ../lib/drmtest.c:880:
11305 18:09:08.241638 Test requirement: is_intel_device(fd)
11306 18:09:08.251599 Test requirement not met in function igt_require_intel, file ../<14>[ 15.805472] [IGT] kms_addfb_basic: executing
11307 18:09:08.255478 lib/drmtest.c:880:
11308 18:09:08.258456 Test requirement: is_intel_device(fd)
11309 18:09:08.265286 No KM<14>[ 15.815067] [IGT] kms_addfb_basic: starting subtest unused-pitches
11310 18:09:08.274997 S driver or no o<14>[ 15.822627] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11311 18:09:08.275111 utputs, pipes: 16, outputs: 0
11312 18:09:08.288199 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<14>[ 15.839325] [IGT] kms_addfb_basic: exiting, ret=0
11313 18:09:08.288315 )
11314 18:09:08.291228 Using IGT_SRANDOM=1718129065 for randomisation
11315 18:09:08.301306 Opened device: /dev/dri/card0<8>[ 15.850651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11316 18:09:08.301425
11317 18:09:08.301713 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11319 18:09:08.304304 Starting subtest: unused-pitches
11320 18:09:08.308136 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11321 18:09:08.314771 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11322 18:09:08.321368 Test r<14>[ 15.873550] [IGT] kms_addfb_basic: executing
11323 18:09:08.324326 equirement: is_intel_device(fd)
11324 18:09:08.334473 Test requirement not met in fun<14>[ 15.883355] [IGT] kms_addfb_basic: starting subtest unused-offsets
11325 18:09:08.341331 ction igt_requir<14>[ 15.891180] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11326 18:09:08.344791 e_intel, file ../lib/drmtest.c:880:
11327 18:09:08.347631 Test requirement: is_intel_device(fd)
11328 18:09:08.354249 No KMS driver or no <14>[ 15.907888] [IGT] kms_addfb_basic: exiting, ret=0
11329 18:09:08.357703 outputs, pipes: 16, outputs: 0
11330 18:09:08.367973 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 15.919384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11331 18:09:08.368270 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11333 18:09:08.370859 .92-cip22 aarch64)
11334 18:09:08.374572 Using IGT_SRANDOM=1718129065 for randomisation
11335 18:09:08.377720 Opened device: /dev/dri/card0
11336 18:09:08.380799 Starting subtest: unused-offsets
11337 18:09:08.387853 [1mSubtest unused-offsets: SUCCESS (0.000s<14>[ 15.942301] [IGT] kms_addfb_basic: executing
11338 18:09:08.390624 )[0m
11339 18:09:08.401062 Test requirement not met in function igt_require_intel, f<14>[ 15.951649] [IGT] kms_addfb_basic: starting subtest unused-modifier
11340 18:09:08.410430 ile ../lib/drmte<14>[ 15.959593] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11341 18:09:08.410546 st.c:880:
11342 18:09:08.414266 Test requirement: is_intel_device(fd)
11343 18:09:08.423688 Test requirement not met in function igt_requi<14>[ 15.976345] [IGT] kms_addfb_basic: exiting, ret=0
11344 18:09:08.427386 re_intel, file ../lib/drmtest.c:880:
11345 18:09:08.430797 Test requirement: is_intel_device(fd)
11346 18:09:08.437096 No <8>[ 15.987598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11347 18:09:08.437396 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11349 18:09:08.441054 KMS driver or no outputs, pipes: 16, outputs: 0
11350 18:09:08.447150 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11351 18:09:08.453888 Using IGT_SRANDOM=1718129065 for randomisation
11352 18:09:08.457430 Opened devi<14>[ 16.010322] [IGT] kms_addfb_basic: executing
11353 18:09:08.460199 ce: /dev/dri/card0
11354 18:09:08.463831 Starting subtest: unused-modifier
11355 18:09:08.470481 [1mSubte<14>[ 16.020355] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11356 18:09:08.480909 st unused-modifi<14>[ 16.028638] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11357 18:09:08.481003 er: SUCCESS (0.000s)[0m
11358 18:09:08.494079 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 16.045217] [IGT] kms_addfb_basic: exiting, ret=77
11359 18:09:08.494198 mtest.c:880:
11360 18:09:08.496975 Test requirement: is_intel_device(fd)
11361 18:09:08.507252 Test requirement not met in<8>[ 16.056823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11362 18:09:08.507518 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11364 18:09:08.514080 function igt_require_intel, file ../lib/drmtest.c:880:
11365 18:09:08.517005 Test requirement: is_intel_device(fd)
11366 18:09:08.520198 No KMS driver or no outputs, pipes: 16, outputs: 0
11367 18:09:08.526974 IGT-Version: 1.28-ga44ebfe (<14>[ 16.080495] [IGT] kms_addfb_basic: executing
11368 18:09:08.529979 aarch64) (Linux: 6.1.92-cip22 aarch64)
11369 18:09:08.540166 Using IGT_SRANDOM=171812<14>[ 16.089776] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11370 18:09:08.550057 9065 for randomi<14>[ 16.098783] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11371 18:09:08.550172 sation
11372 18:09:08.553652 Opened device: /dev/dri/card0
11373 18:09:08.556526 Starting subtest: clobberred-modifier
11374 18:09:08.563451 Test requirement n<14>[ 16.116252] [IGT] kms_addfb_basic: exiting, ret=77
11375 18:09:08.569968 ot met in function igt_require_i915, file ../lib/drmtest.c:885:
11376 18:09:08.580349 Test requiremen<8>[ 16.127750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11377 18:09:08.580474 t: is_i915_device(fd)
11378 18:09:08.580722 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11380 18:09:08.587128 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11381 18:09:08.593044 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11382 18:09:08.599796 Test requirement:<14>[ 16.151368] [IGT] kms_addfb_basic: executing
11383 18:09:08.599884 is_intel_device(fd)
11384 18:09:08.610224 Test requirement not met in function igt_r<14>[ 16.161491] [IGT] kms_addfb_basic: starting subtest legacy-format
11385 18:09:08.613352 equire_intel, file ../lib/drmtest.c:880:
11386 18:09:08.619924 Test requirement: is_intel_device(fd)
11387 18:09:08.626107 <14>[ 16.175077] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11388 18:09:08.626220
11389 18:09:08.629905 No KMS driver or no outputs, pipes: 16, outputs: 0
11390 18:09:08.639773 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 16.191197] [IGT] kms_addfb_basic: exiting, ret=0
11391 18:09:08.639869 : 6.1.92-cip22 aarch64)
11392 18:09:08.646457 Using IGT_SRANDOM=1718129065 for randomisation
11393 18:09:08.653256 Opened <8>[ 16.202595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11394 18:09:08.653516 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11396 18:09:08.656277 device: /dev/dri/card0
11397 18:09:08.659929 Starting subtest: invalid-smem-bo-on-discrete
11398 18:09:08.665987 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11399 18:09:08.672641 Test requirement: is_<14>[ 16.225704] [IGT] kms_addfb_basic: executing
11400 18:09:08.672722 intel_device(fd)
11401 18:09:08.679444 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11402 18:09:08.686227 Te<14>[ 16.237242] [IGT] kms_addfb_basic: starting subtest no-handle
11403 18:09:08.692773 st requirement n<14>[ 16.243887] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11404 18:09:08.699177 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11405 18:09:08.706276 Test requireme<14>[ 16.257951] [IGT] kms_addfb_basic: exiting, ret=0
11406 18:09:08.709238 nt: is_intel_device(fd)
11407 18:09:08.719257 Test requirement not met in function igt_require_intel,<8>[ 16.270460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11408 18:09:08.719531 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11410 18:09:08.722999 file ../lib/drmtest.c:880:
11411 18:09:08.726009 Test requirement: is_intel_device(fd)
11412 18:09:08.729008 No KMS driver or no outputs, pipes: 16, outputs: 0
11413 18:09:08.739725 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 16.292431] [IGT] kms_addfb_basic: executing
11414 18:09:08.739817 2 aarch64)
11415 18:09:08.745629 Using IGT_SRANDOM=1718129065 for randomisation
11416 18:09:08.752813 Opened device: /dev/<14>[ 16.304404] [IGT] kms_addfb_basic: starting subtest basic
11417 18:09:08.752949 dri/card0
11418 18:09:08.758897 Start<14>[ 16.310601] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11419 18:09:08.762669 ing subtest: legacy-format
11420 18:09:08.765619 Successfully fuzzed 10000 {bpp, depth} variations
11421 18:09:08.772522 <14>[ 16.324609] [IGT] kms_addfb_basic: exiting, ret=0
11422 18:09:08.775739 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11423 18:09:08.785609 Test requirement not met in func<8>[ 16.336483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11424 18:09:08.785872 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11426 18:09:08.789365 tion igt_require_intel, file ../lib/drmtest.c:880:
11427 18:09:08.792315 Test requirement: is_intel_device(fd)
11428 18:09:08.802334 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11429 18:09:08.805777 T<14>[ 16.357800] [IGT] kms_addfb_basic: executing
11430 18:09:08.808908 est requirement: is_intel_device(fd)
11431 18:09:08.818570 No KMS driver or no outputs, pipes: 16, ou<14>[ 16.370345] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11432 18:09:08.818659 tputs: 0
11433 18:09:08.829021 IGT-Ve<14>[ 16.377142] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11434 18:09:08.831861 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11435 18:09:08.838381 Using IGT_SRANDOM=<14>[ 16.391543] [IGT] kms_addfb_basic: exiting, ret=0
11436 18:09:08.842093 1718129065 for randomisation
11437 18:09:08.845037 Opened device: /dev/dri/card0
11438 18:09:08.851908 Starting subtest: n<8>[ 16.403654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11439 18:09:08.852197 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11441 18:09:08.854944 o-handle
11442 18:09:08.858681 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11443 18:09:08.865605 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11444 18:09:08.871705 Test requirement: is_intel_device(fd)<14>[ 16.426371] [IGT] kms_addfb_basic: executing
11445 18:09:08.874713
11446 18:09:08.888543 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<14>[ 16.437940] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11447 18:09:08.888639 880:
11448 18:09:08.894865 Test requi<14>[ 16.444895] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11449 18:09:08.897960 rement: is_intel_device(fd)
11450 18:09:08.901763 No KMS driver or no outputs, pipes: 16, outputs: 0
11451 18:09:08.907872 <14>[ 16.459346] [IGT] kms_addfb_basic: exiting, ret=0
11452 18:09:08.907951
11453 18:09:08.914735 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11454 18:09:08.921773 Using IGT_SRANDOM=171812906<8>[ 16.473295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11455 18:09:08.922029 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11457 18:09:08.924874 5 for randomisation
11458 18:09:08.928299 Opened device: /dev/dri/card0
11459 18:09:08.928425 Starting subtest: basic
11460 18:09:08.931090 [1mSubtest basic: SUCCESS (0.000s)[0m
11461 18:09:08.941244 Test requirement not met in function igt_require_intel, fi<14>[ 16.494767] [IGT] kms_addfb_basic: executing
11462 18:09:08.944710 le ../lib/drmtest.c:880:
11463 18:09:08.948233 Test requirement: is_intel_device(fd)
11464 18:09:08.954249 Test requiremen<14>[ 16.507239] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11465 18:09:08.964124 t not met in fun<14>[ 16.514027] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11466 18:09:08.967986 ction igt_require_intel, file ../lib/drmtest.c:880:
11467 18:09:08.978012 Test requirement: is_intel_<14>[ 16.528476] [IGT] kms_addfb_basic: exiting, ret=0
11468 18:09:08.978108 device(fd)
11469 18:09:08.981084 No KMS driver or no outputs, pipes: 16, outputs: 0
11470 18:09:08.990663 IGT-Version: 1.2<8>[ 16.540317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11471 18:09:08.990955 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11473 18:09:08.994351 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11474 18:09:08.997909 Using IGT_SRANDOM=1718129065 for randomisation
11475 18:09:09.000818 Opened device: /dev/dri/card0
11476 18:09:09.007644 Starting subtest: bad-pitch-0<14>[ 16.562410] [IGT] kms_addfb_basic: executing
11477 18:09:09.010842
11478 18:09:09.013934 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11479 18:09:09.020925 Test requirement not met in fun<14>[ 16.573631] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11480 18:09:09.030533 ction igt_requir<14>[ 16.580633] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11481 18:09:09.034179 e_intel, file ../lib/drmtest.c:880:
11482 18:09:09.037841 Test requirement: is_intel_device(fd)
11483 18:09:09.043771 Test<14>[ 16.595248] [IGT] kms_addfb_basic: exiting, ret=0
11484 18:09:09.050615 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11485 18:09:09.056973 <8>[ 16.607086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11486 18:09:09.057261 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11488 18:09:09.061020 Test requirement: is_intel_device(fd)
11489 18:09:09.063839 No KMS driver or no outputs, pipes: 16, outputs: 0
11490 18:09:09.070782 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11491 18:09:09.077140 Using IGT_SRANDOM<14>[ 16.629317] [IGT] kms_addfb_basic: executing
11492 18:09:09.080616 =1718129065 for randomisation
11493 18:09:09.083653 Opened device: /dev/dri/card0
11494 18:09:09.090888 Starting subtest: <14>[ 16.641863] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11495 18:09:09.091003 bad-pitch-32
11496 18:09:09.100489 [<14>[ 16.648872] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11497 18:09:09.103557 1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11498 18:09:09.110839 Test requirement not met in functi<14>[ 16.663504] [IGT] kms_addfb_basic: exiting, ret=0
11499 18:09:09.117110 on igt_require_intel, file ../lib/drmtest.c:880:
11500 18:09:09.126758 Test requirement: is_intel_dev<8>[ 16.675303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11501 18:09:09.126871 ice(fd)
11502 18:09:09.127140 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11504 18:09:09.133537 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11505 18:09:09.136702 Test requirement: is_intel_device(fd)
11506 18:09:09.147046 No KMS driver or no outputs, pipes: 16, outp<14>[ 16.697763] [IGT] kms_addfb_basic: executing
11507 18:09:09.147157 uts: 0
11508 18:09:09.153694 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11509 18:09:09.160475 Usin<14>[ 16.710203] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11510 18:09:09.167212 g IGT_SRANDOM=17<14>[ 16.717204] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11511 18:09:09.170168 18129065 for randomisation
11512 18:09:09.173707 Opened device: /dev/dri/card0
11513 18:09:09.180352 Starting subtest: bad<14>[ 16.731870] [IGT] kms_addfb_basic: exiting, ret=0
11514 18:09:09.180430 -pitch-63
11515 18:09:09.183299 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11516 18:09:09.193013 Test requirement not <8>[ 16.743583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11517 18:09:09.193296 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11519 18:09:09.199757 met in function igt_require_intel, file ../lib/drmtest.c:880:
11520 18:09:09.203503 Test requirement: is_intel_device(fd)
11521 18:09:09.213354 Test requirement not met in function igt_require_intel, file ../lib/drmtes<14>[ 16.766098] [IGT] kms_addfb_basic: executing
11522 18:09:09.216228 t.c:880:
11523 18:09:09.219932 Test requirement: is_intel_device(fd)
11524 18:09:09.226525 No KMS driver or no outputs, pi<14>[ 16.778604] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11525 18:09:09.236149 pes: 16, outputs<14>[ 16.785841] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11526 18:09:09.236266 : 0
11527 18:09:09.243270 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11528 18:09:09.249312 Using I<14>[ 16.800116] [IGT] kms_addfb_basic: exiting, ret=0
11529 18:09:09.253169 GT_SRANDOM=1718129066 for randomisation
11530 18:09:09.253256 Opened device: /dev/dri/card0
11531 18:09:09.262633 Starting<8>[ 16.812181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11532 18:09:09.262921 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11534 18:09:09.265693 subtest: bad-pitch-128
11535 18:09:09.269445 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11536 18:09:09.276526 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11537 18:09:09.279542 Te<14>[ 16.834185] [IGT] kms_addfb_basic: executing
11538 18:09:09.283194 st requirement: is_intel_device(fd)
11539 18:09:09.295842 Test requirement not met in function igt_re<14>[ 16.845609] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11540 18:09:09.302808 quire_intel, fil<14>[ 16.852668] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11541 18:09:09.305963 e ../lib/drmtest.c:880:
11542 18:09:09.308805 Test requirement: is_intel_device(fd)
11543 18:09:09.315421 No KMS driver or<14>[ 16.867399] [IGT] kms_addfb_basic: exiting, ret=0
11544 18:09:09.319325 no outputs, pipes: 16, outputs: 0
11545 18:09:09.328699 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 16.879310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11546 18:09:09.328989 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11548 18:09:09.332218 6.1.92-cip22 aarch64)
11549 18:09:09.335837 Using IGT_SRANDOM=1718129066 for randomisation
11550 18:09:09.338698 Opened device: /dev/dri/card0
11551 18:09:09.342654 Starting subtest: bad-pitch-256
11552 18:09:09.348659 [1mSubtest bad-pitch-256: SUCCESS (0.00<14>[ 16.901720] [IGT] kms_addfb_basic: executing
11553 18:09:09.348776 0s)[0m
11554 18:09:09.358452 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11555 18:09:09.365763 Test requirement: i<14>[ 16.916188] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11556 18:09:09.375172 s_intel_device(f<14>[ 16.924615] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11557 18:09:09.375295 d)
11558 18:09:09.385145 Test requirement not met in function igt_req<14>[ 16.937810] [IGT] kms_addfb_basic: exiting, ret=0
11559 18:09:09.388198 uire_intel, file ../lib/drmtest.c:880:
11560 18:09:09.391995 Test requirement: is_intel_device(fd)
11561 18:09:09.398593 N<8>[ 16.948714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11562 18:09:09.398879 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11564 18:09:09.405336 o KMS driver or no outputs, pipes: 16, outputs: 0
11565 18:09:09.411677 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11566 18:09:09.415551 Using IGT_SRANDOM=1718129066 for randomisation
11567 18:09:09.418454 Opened de<14>[ 16.971704] [IGT] kms_addfb_basic: executing
11568 18:09:09.421626 vice: /dev/dri/card0
11569 18:09:09.425453 Starting subtest: bad-pitch-1024
11570 18:09:09.428464 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11571 18:09:09.435357 Test r<14>[ 16.986249] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11572 18:09:09.444645 equirement not m<14>[ 16.994510] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11573 18:09:09.454678 et in function igt_require_intel, file ../lib/dr<14>[ 17.007294] [IGT] kms_addfb_basic: exiting, ret=0
11574 18:09:09.454770 mtest.c:880:
11575 18:09:09.458424 Test requirement: is_intel_device(fd)
11576 18:09:09.468289 Test requirement not met in<8>[ 17.018106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11577 18:09:09.468620 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11579 18:09:09.474884 function igt_require_intel, file ../lib/drmtest.c:880:
11580 18:09:09.477698 Test requirement: is_intel_device(fd)
11581 18:09:09.481392 No KMS driver or no outputs, pipes: 16, outputs: 0
11582 18:09:09.488116 IGT-Version:<14>[ 17.040385] [IGT] kms_addfb_basic: executing
11583 18:09:09.491079 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11584 18:09:09.498081 Using IGT_SRANDOM=1718129066 for randomisation
11585 18:09:09.504557 Opened d<14>[ 17.053840] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11586 18:09:09.514700 evice: /dev/dri/<14>[ 17.062346] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11587 18:09:09.514828 card0
11588 18:09:09.517583 Starting subtest: bad-pitch-999
11589 18:09:09.521345 [1mSubt<14>[ 17.075617] [IGT] kms_addfb_basic: exiting, ret=0
11590 18:09:09.527654 est bad-pitch-999: SUCCESS (0.000s)[0m
11591 18:09:09.534529 Test requirement not me<8>[ 17.086270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11592 18:09:09.534793 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11594 18:09:09.541432 t in function igt_require_intel, file ../lib/drmtest.c:880:
11595 18:09:09.544504 Test requirement: is_intel_device(fd)
11596 18:09:09.550668 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11597 18:09:09.554338 Test requirement: is_intel_device(fd)
11598 18:09:09.560804 No KMS driver or no outputs, pipes: 16, outputs: 0
11599 18:09:09.567732 IGT-Version: 1.28-ga44ebfe (a<14>[ 17.119126] [IGT] kms_addfb_basic: executing
11600 18:09:09.570752 arch64) (Linux: 6.1.92-cip22 aarch64)
11601 18:09:09.573756 Using IGT_SRANDOM=1718129066 for randomisation
11602 18:09:09.577602 Opened device: /dev/dri/card0
11603 18:09:09.583815 Starting s<14>[ 17.134781] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11604 18:09:09.594172 ubtest: bad-pitc<14>[ 17.143013] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11605 18:09:09.594258 h-65536
11606 18:09:09.600838 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11607 18:09:09.603879 Test<14>[ 17.156279] [IGT] kms_addfb_basic: exiting, ret=0
11608 18:09:09.617004 requirement not met in function igt_require_intel, file ../lib/<8>[ 17.167536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11609 18:09:09.617289 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11611 18:09:09.619975 drmtest.c:880:
11612 18:09:09.623504 Test requirement: is_intel_device(fd)
11613 18:09:09.630490 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11614 18:09:09.637029 Test requirement: is_<14>[ 17.189137] [IGT] kms_addfb_basic: executing
11615 18:09:09.637140 intel_device(fd)
11616 18:09:09.643296 No KMS driver or no outputs, pipes: 16, outputs: 0
11617 18:09:09.653495 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <14>[ 17.204390] [IGT] kms_addfb_basic: starting subtest master-rmfb
11618 18:09:09.653590 aarch64)
11619 18:09:09.663400 Using <14>[ 17.211679] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11620 18:09:09.669846 IGT_SRANDOM=1718129066 for rando<14>[ 17.222023] [IGT] kms_addfb_basic: exiting, ret=0
11621 18:09:09.669953 misation
11622 18:09:09.673185 Opened device: /dev/dri/card0
11623 18:09:09.682956 Starting subtest: inval<8>[ 17.232144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11624 18:09:09.683063 id-get-prop-any
11625 18:09:09.683328 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11627 18:09:09.689127 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11628 18:09:09.695885 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11629 18:09:09.699057 Tes<14>[ 17.253855] [IGT] kms_addfb_basic: executing
11630 18:09:09.702739 t requirement: is_intel_device(fd)
11631 18:09:09.712370 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11632 18:09:09.718845 Test requirement: is_int<14>[ 17.271184] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11633 18:09:09.722879 el_device(fd)
11634 18:09:09.728825 N<14>[ 17.279187] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11635 18:09:09.735431 o KMS driver or <14>[ 17.288749] [IGT] kms_addfb_basic: exiting, ret=0
11636 18:09:09.738945 no outputs, pipes: 16, outputs: 0
11637 18:09:09.749116 IGT-Version: 1.28-ga44ebfe (a<8>[ 17.300504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11638 18:09:09.749390 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11640 18:09:09.752041 arch64) (Linux: 6.1.92-cip22 aarch64)
11641 18:09:09.758810 Using IGT_SRANDOM=1718129066 for randomisation
11642 18:09:09.761971 Opened device: /dev/dri/card0
11643 18:09:09.765877 Starting subtest: invalid-get-prop
11644 18:09:09.769104 [1mSubtest invalid-ge<14>[ 17.322663] [IGT] kms_addfb_basic: executing
11645 18:09:09.772523 t-prop: SUCCESS (0.000s)[0m
11646 18:09:09.779031 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11647 18:09:09.788697 Test requirement: is_intel_dev<14>[ 17.340880] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11648 18:09:09.792336 ice(fd)
11649 18:09:09.798539 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11650 18:09:09.802406 Test requirement: is_intel_device(fd)
11651 18:09:09.805427 No KMS driver or no outputs, pipes: 16, outputs: 0
11652 18:09:09.812602 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11653 18:09:09.815381 Using IGT_SRANDOM=1718129066 for randomisation
11654 18:09:09.818377 Opened device: /dev/dri/card0
11655 18:09:09.821839 Starting subtest: invalid-set-prop-any
11656 18:09:09.828827 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11657 18:09:09.835197 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11658 18:09:09.838272 Test requirement: is_intel_device(fd)
11659 18:09:09.844985 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11660 18:09:09.848510 Test requirement: is_intel_device(fd)
11661 18:09:09.851472 No KMS driver or no outputs, pipes: 16, outputs: 0
11662 18:09:09.858517 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11663 18:09:09.861571 Using IGT_SRANDOM=1718129066 for randomisation
11664 18:09:09.864858 Opened device: /dev/dri/card0
11665 18:09:09.868568 Starting subtest: invalid-set-prop
11666 18:09:09.874494 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11667 18:09:09.881579 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11668 18:09:09.884415 Test requirement: is_intel_device(fd)
11669 18:09:09.891311 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11670 18:09:09.894819 Test requirement: is_intel_device(fd)
11671 18:09:09.898077 No KMS driver or no outputs, pipes: 16, outputs: 0
11672 18:09:09.904514 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11673 18:09:09.908371 Using IGT_SRANDOM=1718129066 for randomisation
11674 18:09:09.911473 Opened device: /dev/dri/card0
11675 18:09:09.914714 Starting subtest: master-rmfb
11676 18:09:09.917713 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11677 18:09:09.924652 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11678 18:09:09.928278 Test requirement: is_intel_device(fd)
11679 18:09:09.937888 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11680 18:09:09.941479 Test requirement: is_intel_device(fd)
11681 18:09:09.944289 No KMS driver or no outputs, pipes: 16, outputs: 0
11682 18:09:09.950797 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11683 18:09:09.954515 Using IGT_SRANDOM=1718129066 for randomisation
11684 18:09:09.957426 Opened device: /dev/dri/card0
11685 18:09:09.961395 Starting subtest: addfb25-modifier-no-flag
11686 18:09:09.967658 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11687 18:09:09.974369 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11688 18:09:09.977254 Test requirement: is_intel_device(fd)
11689 18:09:09.984274 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11690 18:09:09.987491 Test requirement: is_intel_device(fd)
11691 18:09:09.994386 No KMS driver or no outputs, pipes: 16, outputs: 0
11692 18:09:09.997489 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11693 18:09:10.004078 Using IGT_SRANDOM=1718129066 for randomisation
11694 18:09:10.004181 Opened device: /dev/dri/card0
11695 18:09:10.007611 Starting subtest: addfb25-bad-modifier
11696 18:09:10.017069 (kms_addfb_basic:434) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11697 18:09:10.037054 (kms_addfb_basic:434) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11698 18:09:10.040760 (kms_addfb_basic:434) CRITICAL: error: 0 != -1
11699 18:09:10.040929 Stack trace:
11700 18:09:10.046676 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11701 18:09:10.050503 #1 [<unknown>+0xafad4358]
11702 18:09:10.050615 #2 [<unknown>+0xafad5fbc]
11703 18:09:10.053511 #3 [<unknown>+0xafad156c]
11704 18:09:10.057235 #4 [__libc_init_first+0x80]
11705 18:09:10.060841 #5 [__libc_start_main+0x98]
11706 18:09:10.060937 #6 [<unknown>+0xafad15b0]
11707 18:09:10.063665 Subtest addfb25-bad-modifier failed.
11708 18:09:10.066813 **** DEBUG ****
11709 18:09:10.073546 (kms_addfb_basic:434) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11710 18:09:10.083596 (kms_addfb_basic:434) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11711 18:09:10.103200 (kms_addfb_basic:434) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11712 18:09:10.106988 (kms_addfb_basic:434) CRITICAL: error: 0 != -1
11713 18:09:10.110134 (kms_addfb_basic:434) igt_core-INFO: Stack trace:
11714 18:09:10.120494 (kms_addfb_basic:434) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11715 18:09:10.123455 (kms_addfb_basic:434) igt_core-INFO: #1 [<unknown>+0xafad4358]
11716 18:09:10.130181 (kms_addfb_basic:434) igt_core-INFO: #2 [<unknown>+0xafad5fbc]
11717 18:09:10.136302 (<14>[ 17.687465] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11718 18:09:10.143164 kms_addfb_basic:<14>[ 17.696487] [IGT] kms_addfb_basic: exiting, ret=98
11719 18:09:10.150264 434) igt_core-INFO: #3 [<unknown>+0xafad156c]
11720 18:09:10.160134 (kms_addfb_basic:434) igt_core-<8>[ 17.708448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11721 18:09:10.160471 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11723 18:09:10.163232 INFO: #4 [__libc_init_first+0x80]
11724 18:09:10.169632 (kms_addfb_basic:434) igt_core-INFO: #5 [__libc_start_main+0x98]
11725 18:09:10.173062 (kms_addfb_basic:434) igt_core-INFO: #6 [<unknown>+0xafad15b0]
11726 18:09:10.179588 **** <14>[ 17.731404] [IGT] kms_addfb_basic: executing
11727 18:09:10.179694 END ****
11728 18:09:10.186530 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11729 18:09:10.193236 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11730 18:09:10.199857 Test requir<14>[ 17.750101] [IGT] kms_addfb_basic: exiting, ret=77
11731 18:09:10.199973 ement: is_intel_device(fd)
11732 18:09:10.213022 Test requirement not met in function<8>[ 17.761138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11733 18:09:10.213282 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11735 18:09:10.216659 igt_require_intel, file ../lib/drmtest.c:880:
11736 18:09:10.219737 Test requirement: is_intel_device(fd)
11737 18:09:10.226425 No KMS driver or no outputs, pipes: 16, outputs: 0
11738 18:09:10.229396 IGT-Version: 1.28-ga4<14>[ 17.783443] [IGT] kms_addfb_basic: executing
11739 18:09:10.236257 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11740 18:09:10.239483 Using IGT_SRANDOM=1718129067 for randomisation
11741 18:09:10.242435 Opened device: /dev/dri/card0
11742 18:09:10.249476 Test requirement not met in functi<14>[ 17.801916] [IGT] kms_addfb_basic: exiting, ret=77
11743 18:09:10.256251 on igt_require_intel, file ../lib/drmtest.c:880:
11744 18:09:10.262500 Test requireme<8>[ 17.812822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11745 18:09:10.262759 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11747 18:09:10.266198 nt: is_intel_device(fd)
11748 18:09:10.272544 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11749 18:09:10.282136 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 17.835367] [IGT] kms_addfb_basic: executing
11750 18:09:10.282222 test.c:880:
11751 18:09:10.285815 Test requirement: is_intel_device(fd)
11752 18:09:10.292177 No KMS driver or no outputs, pipes: 16, outputs: 0
11753 18:09:10.302121 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 17.853039] [IGT] kms_addfb_basic: exiting, ret=77
11754 18:09:10.302238 2 aarch64)
11755 18:09:10.305138 Using IGT_SRANDOM=1718129067 for randomisation
11756 18:09:10.315306 Open<8>[ 17.863739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11757 18:09:10.315594 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11759 18:09:10.319018 ed device: /dev/dri/card0
11760 18:09:10.325472 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11761 18:09:10.328274 Test requirement: is_intel_device(fd)
11762 18:09:10.335099 [1mSubtes<14>[ 17.886684] [IGT] kms_addfb_basic: executing
11763 18:09:10.338508 t addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11764 18:09:10.345296 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11765 18:09:10.351731 Test requirement: is_intel_devi<14>[ 17.905114] [IGT] kms_addfb_basic: exiting, ret=77
11766 18:09:10.354761 ce(fd)
11767 18:09:10.358673 No KMS driver or no outputs, pipes: 16, outputs: 0
11768 18:09:10.364765 IGT-<8>[ 17.915925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11769 18:09:10.365058 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11771 18:09:10.371636 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11772 18:09:10.374680 Using IGT_SRANDOM=1718129067 for randomisation
11773 18:09:10.378002 Opened device: /dev/dri/card0
11774 18:09:10.384691 Test requirement <14>[ 17.938606] [IGT] kms_addfb_basic: executing
11775 18:09:10.391808 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11776 18:09:10.394837 Test requirement: is_intel_device(fd)
11777 18:09:10.404551 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0<14>[ 17.956104] [IGT] kms_addfb_basic: exiting, ret=77
11778 18:09:10.404640 .000s)[0m
11779 18:09:10.418165 Test requirement not met in function igt_require_int<8>[ 17.967042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11780 18:09:10.418462 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11782 18:09:10.421277 el, file ../lib/drmtest.c:880:
11783 18:09:10.424888 Test requirement: is_intel_device(fd)
11784 18:09:10.427820 No KMS driver or no outputs, pipes: 16, outputs: 0
11785 18:09:10.437971 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 17.989720] [IGT] kms_addfb_basic: executing
11786 18:09:10.438095 (Linux: 6.1.92-cip22 aarch64)
11787 18:09:10.444689 Using IGT_SRANDOM=1718129067 for randomisation
11788 18:09:10.447518 Opened device: /dev/dri/card0
11789 18:09:10.454141 Test requirement not met in function igt_require_i<14>[ 18.007797] [IGT] kms_addfb_basic: exiting, ret=77
11790 18:09:10.457627 ntel, file ../lib/drmtest.c:880:
11791 18:09:10.467549 Test requirement: is_intel_dev<8>[ 18.018269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11792 18:09:10.467853 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11794 18:09:10.470884 ice(fd)
11795 18:09:10.477348 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11796 18:09:10.481062 Test requirement: is_intel_device(fd)
11797 18:09:10.487370 [1mSubtest basic-x-tiled-le<14>[ 18.040911] [IGT] kms_addfb_basic: executing
11798 18:09:10.490420 gacy: SKIP (0.000s)[0m
11799 18:09:10.494379 No KMS driver or no outputs, pipes: 16, outputs: 0
11800 18:09:10.500412 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11801 18:09:10.507290 Using IGT_SRAND<14>[ 18.058361] [IGT] kms_addfb_basic: exiting, ret=77
11802 18:09:10.510354 OM=1718129067 for randomisation
11803 18:09:10.513988 Opened device: /dev/dri/card0
11804 18:09:10.520434 <8>[ 18.069485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11805 18:09:10.520713 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11807 18:09:10.527215 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11808 18:09:10.530187 Test requirement: is_intel_device(fd)
11809 18:09:10.540461 Test requirement not met in function igt_require_inte<14>[ 18.092154] [IGT] kms_addfb_basic: executing
11810 18:09:10.544188 l, file ../lib/drmtest.c:880:
11811 18:09:10.547267 Test requirement: is_intel_device(fd)
11812 18:09:10.550374 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11813 18:09:10.560247 No KMS driver or no outputs, pip<14>[ 18.111124] [IGT] kms_addfb_basic: exiting, ret=77
11814 18:09:10.560333 es: 16, outputs: 0
11815 18:09:10.570811 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 18.121552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11816 18:09:10.571078 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11818 18:09:10.573616 6.1.92-cip22 aarch64)
11819 18:09:10.577328 Using IGT_SRANDOM=1718129067 for randomisation
11820 18:09:10.580258 Opened device: /dev/dri/card0
11821 18:09:10.590254 Test requirement not met in function igt_require_intel, f<14>[ 18.143328] [IGT] kms_addfb_basic: executing
11822 18:09:10.593717 ile ../lib/drmtest.c:880:
11823 18:09:10.597274 Test requirement: is_intel_device(fd)
11824 18:09:10.603498 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11825 18:09:10.610389 Test requi<14>[ 18.160955] [IGT] kms_addfb_basic: exiting, ret=77
11826 18:09:10.610469 rement: is_intel_device(fd)
11827 18:09:10.620277 [1mSubtest tile-pitch-mismatch: SK<8>[ 18.171842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11828 18:09:10.620585 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11830 18:09:10.623475 IP (0.000s)[0m
11831 18:09:10.626849 No KMS driver or no outputs, pipes: 16, outputs: 0
11832 18:09:10.633377 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11833 18:09:10.639716 Using IGT_SRANDOM=17181<14>[ 18.192745] [IGT] kms_addfb_basic: executing
11834 18:09:10.643213 29067 for randomisation
11835 18:09:10.643299 Opened device: /dev/dri/card0
11836 18:09:10.653456 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11837 18:09:10.659982 Test requirement: is<14>[ 18.210901] [IGT] kms_addfb_basic: exiting, ret=77
11838 18:09:10.660074 _intel_device(fd)
11839 18:09:10.669871 Test requirement not met in function igt_requ<8>[ 18.221464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11840 18:09:10.670165 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11842 18:09:10.673418 ire_intel, file ../lib/drmtest.c:880:
11843 18:09:10.676791 Test requirement: is_intel_device(fd)
11844 18:09:10.683190 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11845 18:09:10.689999 No KMS driver or no outputs, pipes: 16, outpu<14>[ 18.243494] [IGT] kms_addfb_basic: executing
11846 18:09:10.692809 ts: 0
11847 18:09:10.695992 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11848 18:09:10.702696 Using IGT_SRANDOM=1718129067 for randomisation
11849 18:09:10.706071 Opened device: /dev/dri/card0
11850 18:09:10.709396 Test r<14>[ 18.262214] [IGT] kms_addfb_basic: exiting, ret=77
11851 18:09:10.722689 equirement not met in function igt_require_intel, file ../lib/dr<8>[ 18.272974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11852 18:09:10.722779 mtest.c:880:
11853 18:09:10.723019 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11855 18:09:10.725604 Test requirement: is_intel_device(fd)
11856 18:09:10.735534 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11857 18:09:10.742354 Test requirement: is_in<14>[ 18.294480] [IGT] kms_addfb_basic: executing
11858 18:09:10.742445 tel_device(fd)
11859 18:09:10.749215 No KMS driver or no outputs, pipes: 16, outputs: 0
11860 18:09:10.752454 [1mSubtest size-max: SKIP (0.000s)[0m
11861 18:09:10.758664 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92<14>[ 18.312433] [IGT] kms_addfb_basic: exiting, ret=77
11862 18:09:10.761940 -cip22 aarch64)
11863 18:09:10.765403 Using IGT_SRANDOM=1718129067 for randomisation
11864 18:09:10.771923 <8>[ 18.323167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11865 18:09:10.772022
11866 18:09:10.772264 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11868 18:09:10.775712 Opened device: /dev/dri/card0
11869 18:09:10.781662 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11870 18:09:10.785401 Test requirement: is_intel_device(fd)
11871 18:09:10.791744 Test <14>[ 18.344818] [IGT] kms_addfb_basic: executing
11872 18:09:10.798502 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11873 18:09:10.802248 Test requirement: is_intel_device(fd)
11874 18:09:10.811916 No KMS driver or no outputs, pipes: 16, ou<14>[ 18.362368] [IGT] kms_addfb_basic: exiting, ret=77
11875 18:09:10.812019 tputs: 0
11876 18:09:10.815191 [1mSubtest too-wide: SKIP (0.000s)[0m
11877 18:09:10.824916 IGT-Version: <8>[ 18.373256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11878 18:09:10.825301 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11880 18:09:10.828520 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11881 18:09:10.834637 Using IGT_SRANDOM=1718129067 for randomisation
11882 18:09:10.834760 Opened device: /dev/dri/card0
11883 18:09:10.841469 Test requirement not met i<14>[ 18.395821] [IGT] kms_addfb_basic: executing
11884 18:09:10.848096 n function igt_require_intel, file ../lib/drmtest.c:880:
11885 18:09:10.851905 Test requirement: is_intel_device(fd)
11886 18:09:10.861722 Test requirement not met in function igt_require_intel, file ..<14>[ 18.413771] [IGT] kms_addfb_basic: exiting, ret=77
11887 18:09:10.864860 /lib/drmtest.c:880:
11888 18:09:10.868439 Test requirement: is_intel_device(fd)
11889 18:09:10.874571 No K<8>[ 18.424960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11890 18:09:10.874858 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11892 18:09:10.878084 MS driver or no outputs, pipes: 16, outputs: 0
11893 18:09:10.884642 [1mSubtest too-high: SKIP (0.000s)[0m
11894 18:09:10.888167 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11895 18:09:10.894786 Using IGT_SRANDOM=1<14>[ 18.447746] [IGT] kms_addfb_basic: executing
11896 18:09:10.897742 718129067 for randomisation
11897 18:09:10.901579 Opened device: /dev/dri/card0
11898 18:09:10.907951 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11899 18:09:10.914227 Test requirement<14>[ 18.466250] [IGT] kms_addfb_basic: exiting, ret=77
11900 18:09:10.917950 : is_intel_device(fd)
11901 18:09:10.927835 Test requirement not met in function igt_<8>[ 18.477434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11902 18:09:10.928127 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11904 18:09:10.931100 require_intel, file ../lib/drmtest.c:880:
11905 18:09:10.934601 Test requirement: is_intel_device(fd)
11906 18:09:10.941248 No KMS driver or no outputs, pipes: 16, outputs: 0
11907 18:09:10.947387 [1mSubtest bo-too-small: <14>[ 18.499901] [IGT] kms_addfb_basic: executing
11908 18:09:10.947494 SKIP (0.000s)[0m
11909 18:09:10.954173 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11910 18:09:10.957787 Using IGT_SRANDOM=1718129067 for randomisation
11911 18:09:10.964514 Opened device: /dev/dri/c<14>[ 18.517558] [IGT] kms_addfb_basic: exiting, ret=77
11912 18:09:10.967373 ard0
11913 18:09:10.980839 Test requirement not met in function igt_require_intel, fi<8>[ 18.528758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11914 18:09:10.980983 le ../lib/drmtest.c:880:
11915 18:09:10.981247 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11917 18:09:10.984107 Test requirement: is_intel_device(fd)
11918 18:09:10.994045 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11919 18:09:10.997529 Test requir<14>[ 18.551464] [IGT] kms_addfb_basic: executing
11920 18:09:11.000809 ement: is_intel_device(fd)
11921 18:09:11.003749 No KMS driver or no outputs, pipes: 16, outputs: 0
11922 18:09:11.007626 [1mSubtest small-bo: SKIP (0.000s)[0m
11923 18:09:11.017363 IGT-Version: 1.28-ga44ebfe (aarch64) (L<14>[ 18.569215] [IGT] kms_addfb_basic: exiting, ret=77
11924 18:09:11.020327 inux: 6.1.92-cip22 aarch64)
11925 18:09:11.030372 Using IGT_SRANDOM=1718129067 for ra<8>[ 18.579876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11926 18:09:11.030473 ndomisation
11927 18:09:11.030723 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11929 18:09:11.036759 Ope<8>[ 18.589740] <LAVA_SIGNAL_TESTSET STOP>
11930 18:09:11.036848 ned device: /dev/dri/card0
11931 18:09:11.037088 Received signal: <TESTSET> STOP
11932 18:09:11.037157 Closing test_set kms_addfb_basic
11933 18:09:11.046503 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11934 18:09:11.049730 Test requirement: is_intel_device(fd)
11935 18:09:11.057084 Test requirement not met in function igt_<8>[ 18.609643] <LAVA_SIGNAL_TESTSET START kms_atomic>
11936 18:09:11.057360 Received signal: <TESTSET> START kms_atomic
11937 18:09:11.057468 Starting test_set kms_atomic
11938 18:09:11.060273 require_intel, file ../lib/drmtest.c:880:
11939 18:09:11.063661 Test requirement: is_intel_device(fd)
11940 18:09:11.070426 No KMS driver or no outputs, pipes: 16, outputs: 0
11941 18:09:11.076306 [1mSubtest bo-too-small-d<14>[ 18.628717] [IGT] kms_atomic: executing
11942 18:09:11.079899 ue-to-tiling: SK<14>[ 18.634404] [IGT] kms_atomic: exiting, ret=77
11943 18:09:11.083553 IP (0.000s)[0m
11944 18:09:11.093018 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.<8>[ 18.644584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11945 18:09:11.093299 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11947 18:09:11.097052 1.92-cip22 aarch64)
11948 18:09:11.099691 Using IGT_SRANDOM=1718129067 for randomisation
11949 18:09:11.103141 Opened device: /dev/dri/card0
11950 18:09:11.113078 Test requirement not met in function igt_require_intel, file<14>[ 18.666779] [IGT] kms_atomic: executing
11951 18:09:11.120142 ../lib/drmtest.<14>[ 18.671788] [IGT] kms_atomic: exiting, ret=77
11952 18:09:11.120272 c:880:
11953 18:09:11.123113 Test requirement: is_intel_device(fd)
11954 18:09:11.133015 Test requirement <8>[ 18.681963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11955 18:09:11.133347 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11957 18:09:11.139840 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11958 18:09:11.143013 Test requirement: is_intel_device(fd)
11959 18:09:11.146534 No KMS driver or no outputs, pipes: 16, outputs: 0
11960 18:09:11.149573 [<14>[ 18.704492] [IGT] kms_atomic: executing
11961 18:09:11.156178 1mSubtest addfb2<14>[ 18.709392] [IGT] kms_atomic: exiting, ret=77
11962 18:09:11.159666 5-y-tiled-legacy: SKIP (0.000s)[0m
11963 18:09:11.169846 IGT-Version: 1.28-ga44ebfe <8>[ 18.719496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11964 18:09:11.170116 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11966 18:09:11.176555 (aarch64) (Linux: 6.1.92-cip22 aarch64)
11967 18:09:11.179650 Using IGT_SRANDOM=1718129067 for randomisation
11968 18:09:11.183292 Opened device: /dev/dri/card0
11969 18:09:11.189973 Test requirement not met in function igt<14>[ 18.743424] [IGT] kms_atomic: executing
11970 18:09:11.195991 _require_intel, <14>[ 18.748157] [IGT] kms_atomic: exiting, ret=77
11971 18:09:11.199264 file ../lib/drmtest.c:880:
11972 18:09:11.209687 Test requirement: is_intel_device(fd<8>[ 18.758232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11973 18:09:11.209838 )
11974 18:09:11.210097 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11976 18:09:11.216061 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11977 18:09:11.219802 Test requirement: is_intel_device(fd)
11978 18:09:11.225445 No KMS driver or no outputs, pipes<14>[ 18.780657] [IGT] kms_atomic: executing
11979 18:09:11.232242 : 16, outputs: 0<14>[ 18.785838] [IGT] kms_atomic: exiting, ret=77
11980 18:09:11.232412
11981 18:09:11.238921 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11982 18:09:11.245820 IGT-Ve<8>[ 18.795776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11983 18:09:11.246096 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11985 18:09:11.252512 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11986 18:09:11.255493 Using IGT_SRANDOM=1718129067 for randomisation
11987 18:09:11.259852 Opened device: /dev/dri/card0
11988 18:09:11.262261 Test requirement no<14>[ 18.817467] [IGT] kms_atomic: executing
11989 18:09:11.269115 t met in functio<14>[ 18.822332] [IGT] kms_atomic: exiting, ret=77
11990 18:09:11.275111 n igt_require_intel, file ../lib/drmtest.c:880:
11991 18:09:11.281487 Test requiremen<8>[ 18.832479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11992 18:09:11.281752 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11994 18:09:11.284897 t: is_intel_device(fd)
11995 18:09:11.291495 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11996 18:09:11.295086 Test requirement: is_intel_device(fd)
11997 18:09:11.301786 No KMS driver<14>[ 18.854696] [IGT] kms_atomic: executing
11998 18:09:11.308552 or no outputs, <14>[ 18.859802] [IGT] kms_atomic: exiting, ret=77
11999 18:09:11.308630 pipes: 16, outputs: 0
12000 18:09:11.321621 [1mSubtest addfb25-y-tiled-small-legacy:<8>[ 18.869996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12001 18:09:11.321713 SKIP (0.000s)[0m
12002 18:09:11.321965 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12004 18:09:11.327984 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12005 18:09:11.331488 Using IGT_SRANDOM=1718129068 for randomisation
12006 18:09:11.337828 Opened device: /dev/dri/<14>[ 18.892624] [IGT] kms_atomic: executing
12007 18:09:11.337910 card0
12008 18:09:11.345017 Test requ<14>[ 18.897464] [IGT] kms_atomic: exiting, ret=77
12009 18:09:11.357856 irement not met in function igt_require_intel, file ../lib/drmte<8>[ 18.907472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12010 18:09:11.358144 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12012 18:09:11.360916 st.c:880:
12013 18:09:11.364593 Test requirement: is_intel_device(fd)
12014 18:09:11.371584 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12015 18:09:11.374602 Test requirement: is_intel_device(fd)
12016 18:09:11.381429 No KMS driver or no outputs, pipes:<14>[ 18.934548] [IGT] kms_atomic: executing
12017 18:09:11.381516 16, outputs: 0
12018 18:09:11.387605 <14>[ 18.939702] [IGT] kms_atomic: exiting, ret=77
12019 18:09:11.387689
12020 18:09:11.391218 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12021 18:09:11.401329 IGT-Version: 1.<8>[ 18.949849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12022 18:09:11.401594 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12024 18:09:11.403822 28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12025 18:09:11.410840 Using IGT_SRANDOM=1718129068 for randomisation
12026 18:09:11.410956 Opened device: /dev/dri/card0
12027 18:09:11.417355 No KMS driver or no outputs,<14>[ 18.971813] [IGT] kms_atomic: executing
12028 18:09:11.423636 pipes: 16, outp<14>[ 18.977077] [IGT] kms_atomic: exiting, ret=77
12029 18:09:11.423749 uts: 0
12030 18:09:11.430518 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12031 18:09:11.437222 IGT<8>[ 18.987627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12032 18:09:11.437481 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12034 18:09:11.443850 -Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12035 18:09:11.447412 Using IGT_SRANDOM=1718129068 for randomisation
12036 18:09:11.450343 Opened device: /dev/dri/card0
12037 18:09:11.456803 No KMS driver or<14>[ 19.009734] [IGT] kms_atomic: executing
12038 18:09:11.463875 no outputs, pip<14>[ 19.015207] [IGT] kms_atomic: exiting, ret=77
12039 18:09:11.463981 es: 16, outputs: 0
12040 18:09:11.476977 [1mSubtest plane-primary-legacy: SKIP (0.00<8>[ 19.025339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12041 18:09:11.477066 0s)[0m
12042 18:09:11.477331 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12044 18:09:11.483573 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12045 18:09:11.486747 Using IGT_SRANDOM=1718129068 for randomisation
12046 18:09:11.489844 Opened device: /dev/dri/card0
12047 18:09:11.496431 No KMS driver or no <14>[ 19.048161] [IGT] kms_atomic: executing
12048 18:09:11.499498 outputs, pipes: <14>[ 19.054106] [IGT] kms_atomic: exiting, ret=77
12049 18:09:11.503288 16, outputs: 0
12050 18:09:11.512781 [1mSubtest plane-primary-overlay-mutable-zpos: <8>[ 19.064401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12051 18:09:11.513039 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12053 18:09:11.519569 SKIP (0.000s)[0<8>[ 19.074317] <LAVA_SIGNAL_TESTSET STOP>
12054 18:09:11.519654 m
12055 18:09:11.519886 Received signal: <TESTSET> STOP
12056 18:09:11.519951 Closing test_set kms_atomic
12057 18:09:11.526478 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12058 18:09:11.529752 Using IGT_SRANDOM=1718129068 for randomisation
12059 18:09:11.533296 Opened device: /dev/dri/card0
12060 18:09:11.536530 No KMS driver or no outputs, pipes: 16, outputs: 0
12061 18:09:11.542978 [1mSu<8>[ 19.095326] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12062 18:09:11.543241 Received signal: <TESTSET> START kms_flip_event_leak
12063 18:09:11.543422 Starting test_set kms_flip_event_leak
12064 18:09:11.549890 btest plane-immutable-zpos: SKIP (0.000s)[0m
12065 18:09:11.552742 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12066 18:09:11.560072 Using IGT_SRANDOM=1718129068 for randomisation
12067 18:09:11.560153 Opened device: /dev/dri/card0
12068 18:09:11.566446 No KMS driver <14>[ 19.119645] [IGT] kms_flip_event_leak: executing
12069 18:09:11.572990 or no outputs, p<14>[ 19.126103] [IGT] kms_flip_event_leak: exiting, ret=77
12070 18:09:11.575801 ipes: 16, outputs: 0
12071 18:09:11.579168 [1mSubtest test-only: SKIP (0.000s)[0m
12072 18:09:11.585763 <8>[ 19.137292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12073 18:09:11.586021 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12075 18:09:11.592550 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 19.146043] <LAVA_SIGNAL_TESTSET STOP>
12076 18:09:11.592805 Received signal: <TESTSET> STOP
12077 18:09:11.592876 Closing test_set kms_flip_event_leak
12078 18:09:11.595662 h64) (Linux: 6.1.92-cip22 aarch64)
12079 18:09:11.599801 Using IGT_SRANDOM=1718129068 for randomisation
12080 18:09:11.602716 Opened device: /dev/dri/card0
12081 18:09:11.608962 No KMS driver or no outputs, pipes: 16, outputs: 0
12082 18:09:11.615421 [1mSubtest plane-cursor-<8>[ 19.168109] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12083 18:09:11.615684 Received signal: <TESTSET> START kms_prop_blob
12084 18:09:11.615757 Starting test_set kms_prop_blob
12085 18:09:11.618798 legacy: SKIP (0.000s)[0m
12086 18:09:11.622733 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12087 18:09:11.628949 Using IGT_SRANDOM=1718129068 for randomisation
12088 18:09:11.629033 Opened device: /dev/dri/card0
12089 18:09:11.639161 No KMS driver or no outputs, pipes<14>[ 19.190671] [IGT] kms_prop_blob: executing
12090 18:09:11.645569 : 16, outputs: 0<14>[ 19.196414] [IGT] kms_prop_blob: starting subtest basic
12091 18:09:11.645661
12092 18:09:11.652018 [1mSubtest pl<14>[ 19.203168] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12093 18:09:11.659220 <14>[ 19.211002] [IGT] kms_prop_blob: exiting, ret=0
12094 18:09:11.662220 ane-invalid-params: SKIP (0.000s)[0m
12095 18:09:11.669017 IGT-Versi<8>[ 19.220041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12096 18:09:11.669275 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12098 18:09:11.672074 on: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12099 18:09:11.678784 Using IGT_SRANDOM=1718129068 for randomisation
12100 18:09:11.678866 Opened device: /dev/dri/card0
12101 18:09:11.685404 No KMS driver or no ou<14>[ 19.239862] [IGT] kms_prop_blob: executing
12102 18:09:11.695166 tputs, pipes: 16<14>[ 19.245162] [IGT] kms_prop_blob: starting subtest blob-prop-core
12103 18:09:11.695252 , outputs: 0
12104 18:09:11.702048 [<14>[ 19.252710] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12105 18:09:11.708313 1mSubtest plane-<14>[ 19.261287] [IGT] kms_prop_blob: exiting, ret=0
12106 18:09:11.711496 invalid-params-fence: SKIP (0.000s)[0m
12107 18:09:11.722008 IGT-Version: 1.28-ga44e<8>[ 19.271809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12108 18:09:11.722265 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12110 18:09:11.725348 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12111 18:09:11.731943 Using IGT_SRANDOM=1718129068 for randomisation
12112 18:09:11.732023 Opened device: /dev/dri/card0
12113 18:09:11.741461 No KMS driver or no outputs, pipes: <14>[ 19.293578] [IGT] kms_prop_blob: executing
12114 18:09:11.741558 16, outputs: 0
12115 18:09:11.748494 <14>[ 19.299014] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12116 18:09:11.757835 [1mSubtest crtc<14>[ 19.306989] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12117 18:09:11.764714 -invalid-params:<14>[ 19.315817] [IGT] kms_prop_blob: exiting, ret=0
12118 18:09:11.764802 SKIP (0.000s)[0m
12119 18:09:11.777880 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<8>[ 19.326241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12120 18:09:11.777969 6.1.92-cip22 aarch64)
12121 18:09:11.778216 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12123 18:09:11.784628 Using IGT_SRANDOM=1718129068 for randomisation
12124 18:09:11.784740 Opened device: /dev/dri/card0
12125 18:09:11.791518 No KMS driver or no outputs, pipes: 16, outputs: 0
12126 18:09:11.794205 [1mS<14>[ 19.348692] [IGT] kms_prop_blob: executing
12127 18:09:11.804302 ubtest crtc-inva<14>[ 19.353828] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12128 18:09:11.811411 lid-params-fence<14>[ 19.361759] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12129 18:09:11.817518 : SKIP (0.000s)<14>[ 19.370604] [IGT] kms_prop_blob: exiting, ret=0
12130 18:09:11.817601 [0m
12131 18:09:11.831241 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 19.381113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12132 18:09:11.831335 arch64)
12133 18:09:11.831583 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12135 18:09:11.837755 Using IGT_SRANDOM=1718129068 for randomisation
12136 18:09:11.837838 Opened device: /dev/dri/card0
12137 18:09:11.844646 No KMS driver or no outputs, pipes: 16, outputs: 0
12138 18:09:11.850691 [1mSubtest atomic-i<14>[ 19.403463] [IGT] kms_prop_blob: executing
12139 18:09:11.857661 nvalid-params: S<14>[ 19.408637] [IGT] kms_prop_blob: starting subtest blob-multiple
12140 18:09:11.867239 KIP (0.000s)[0m<14>[ 19.416225] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12141 18:09:11.867364
12142 18:09:11.873782 IGT-Version: 1<14>[ 19.424547] [IGT] kms_prop_blob: exiting, ret=0
12143 18:09:11.877361 .28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12144 18:09:11.884068 Using IGT_<8>[ 19.435241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12145 18:09:11.884347 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12147 18:09:11.887238 SRANDOM=1718129068 for randomisation
12148 18:09:11.890668 Opened device: /dev/dri/card0
12149 18:09:11.897123 No KMS driver or no outputs, pipes: 16, outputs: 0
12150 18:09:11.900654 [1mSubtest atomic-plane-damage: SKIP (0.000s)[0m
12151 18:09:11.904212 IGT<14>[ 19.457402] [IGT] kms_prop_blob: executing
12152 18:09:11.913961 -Version: 1.28-g<14>[ 19.463630] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12153 18:09:11.923885 a44ebfe (aarch64<14>[ 19.471638] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12154 18:09:11.930405 ) (Linux: 6.1.92<14>[ 19.480739] [IGT] kms_prop_blob: exiting, ret=0
12155 18:09:11.930490 -cip22 aarch64)
12156 18:09:11.940191 Using IGT_SRANDOM=1718129068 fo<8>[ 19.491003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12157 18:09:11.940481 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12159 18:09:11.943080 r randomisation
12160 18:09:11.943158 Opened device: /dev/dri/card0
12161 18:09:11.949694 No KMS driver or no outputs, pipes: 16, outputs: 0
12162 18:09:11.953407 [1mSubtest basic: SKIP (0.000s)[0m
12163 18:09:11.959516 IGT-Version: 1.28-ga44<14>[ 19.512015] [IGT] kms_prop_blob: executing
12164 18:09:11.966452 ebfe (aarch64) (<14>[ 19.517635] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12165 18:09:11.976195 Linux: 6.1.92-ci<14>[ 19.525259] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12166 18:09:11.976317 p22 aarch64)
12167 18:09:11.982886 Us<14>[ 19.534163] [IGT] kms_prop_blob: exiting, ret=0
12168 18:09:11.985958 ing IGT_SRANDOM=1718129068 for randomisation
12169 18:09:11.996233 Opened device: /de<8>[ 19.544535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12170 18:09:11.996370 v/dri/card0
12171 18:09:11.996617 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12173 18:09:11.999651 Starting subtest: basic
12174 18:09:12.002493 [1mSubtest basic: SUCCESS (0.000s)[0m
12175 18:09:12.006018 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12176 18:09:12.013143 Using IGT_SRA<14>[ 19.566844] [IGT] kms_prop_blob: executing
12177 18:09:12.022794 NDOM=1718129068 <14>[ 19.571902] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12178 18:09:12.029498 for randomisatio<14>[ 19.580065] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12179 18:09:12.029623 n
12180 18:09:12.036095 Opened device<14>[ 19.589179] [IGT] kms_prop_blob: exiting, ret=0
12181 18:09:12.039060 : /dev/dri/card0
12182 18:09:12.042862 Starting subtest: blob-prop-core
12183 18:09:12.049545 [1mSubtest <8>[ 19.599491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12184 18:09:12.049845 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12186 18:09:12.052513 blob-prop-core: SUCCESS (0.000s)[0m
12187 18:09:12.058974 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12188 18:09:12.062647 Using IGT_SRANDOM=1718129068 for randomisation
12189 18:09:12.069115 Opened<14>[ 19.621824] [IGT] kms_prop_blob: executing
12190 18:09:12.075727 device: /dev/dr<14>[ 19.627339] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12191 18:09:12.079393 i/card0
12192 18:09:12.085598 Startin<14>[ 19.635224] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12193 18:09:12.092201 g subtest: blob-<14>[ 19.643807] [IGT] kms_prop_blob: exiting, ret=0
12194 18:09:12.092292 prop-validate
12195 18:09:12.105323 [1mSubtest blob-prop-validate: SUCCESS (0.000s)<8>[ 19.654419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12196 18:09:12.105421 [0m
12197 18:09:12.105663 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12199 18:09:12.108973 IGT-Version<8>[ 19.664211] <LAVA_SIGNAL_TESTSET STOP>
12200 18:09:12.109230 Received signal: <TESTSET> STOP
12201 18:09:12.109311 Closing test_set kms_prop_blob
12202 18:09:12.115659 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12203 18:09:12.118759 Using IGT_SRANDOM=1718129068 for randomisation
12204 18:09:12.122637 Opened device: /dev/dri/card0
12205 18:09:12.125328 Starting subtest: blob-prop-lifetime
12206 18:09:12.132375 [1mSubtest blob-prop-lifetime: SU<8>[ 19.685451] <LAVA_SIGNAL_TESTSET START kms_setmode>
12207 18:09:12.132634 Received signal: <TESTSET> START kms_setmode
12208 18:09:12.132707 Starting test_set kms_setmode
12209 18:09:12.135126 CCESS (0.000s)[0m
12210 18:09:12.142129 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12211 18:09:12.145573 Using IGT_SRANDOM=1718129068 for randomisation
12212 18:09:12.148293 Opened device: /dev/dri/card0
12213 18:09:12.152120 Starting <14>[ 19.706147] [IGT] kms_setmode: executing
12214 18:09:12.158988 subtest: blob-mu<14>[ 19.711747] [IGT] kms_setmode: starting subtest basic
12215 18:09:12.162067 ltiple
12216 18:09:12.168868 [1mSubt<14>[ 19.718271] [IGT] kms_setmode: finished subtest basic, SKIP
12217 18:09:12.171750 est blob-multipl<14>[ 19.725645] [IGT] kms_setmode: exiting, ret=77
12218 18:09:12.174921 e: SUCCESS (0.000s)[0m
12219 18:09:12.185435 IGT-Version: 1.28-ga44e<8>[ 19.735841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12220 18:09:12.185701 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12222 18:09:12.188645 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12223 18:09:12.191458 Using IGT_SRANDOM=1718129068 for randomisation
12224 18:09:12.195326 Opened device: /dev/dri/card0
12225 18:09:12.201356 Starting subtest: invalid-get-prop-a<14>[ 19.756136] [IGT] kms_setmode: executing
12226 18:09:12.201443 ny
12227 18:09:12.211483 [1mSubtest <14>[ 19.761057] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12228 18:09:12.218435 invalid-get-prop<14>[ 19.769129] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12229 18:09:12.225043 -any: SUCCESS (0<14>[ 19.778044] [IGT] kms_setmode: exiting, ret=77
12230 18:09:12.227938 .000s)[0m
12231 18:09:12.238334 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-<8>[ 19.789050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12232 18:09:12.238637 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12234 18:09:12.241504 cip22 aarch64)
12235 18:09:12.244373 Using IGT_SRANDOM=1718129068 for randomisation
12236 18:09:12.247920 Opened device: /dev/dri/card0
12237 18:09:12.251336 Starting subtest: invalid-get-prop
12238 18:09:12.254724 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12239 18:09:12.261394 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12240 18:09:12.264705 Using<14>[ 19.819414] [IGT] kms_setmode: executing
12241 18:09:12.274405 IGT_SRANDOM=171<14>[ 19.824755] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12242 18:09:12.284220 8129069 for rand<14>[ 19.832925] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12243 18:09:12.284365 omisation
12244 18:09:12.290875 Opene<14>[ 19.842157] [IGT] kms_setmode: exiting, ret=77
12245 18:09:12.290998 d device: /dev/dri/card0
12246 18:09:12.304516 Starting subtest: invalid-set-prop-any<8>[ 19.852792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12247 18:09:12.304602
12248 18:09:12.304844 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12250 18:09:12.307697 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12251 18:09:12.314320 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12252 18:09:12.317376 Using IGT_SRANDOM=1718129069 for randomisation
12253 18:09:12.320952 Opened device: /dev/dri/card0
12254 18:09:12.324450 Starting subtest: invalid-set-prop
12255 18:09:12.334019 [1mSubtest invalid-set-prop: SUCCESS (0.000s)<14>[ 19.886648] [IGT] kms_setmode: executing
12256 18:09:12.334107 [0m
12257 18:09:12.340752 IGT-Version<14>[ 19.891797] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12258 18:09:12.350598 : 1.28-ga44ebfe <14>[ 19.900087] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12259 18:09:12.357443 (aarch64) (Linux<14>[ 19.909425] [IGT] kms_setmode: exiting, ret=77
12260 18:09:12.360485 : 6.1.92-cip22 aarch64)
12261 18:09:12.370469 Using IGT_SRANDOM=1718129069 for random<8>[ 19.921084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12262 18:09:12.370561 isation
12263 18:09:12.370806 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12265 18:09:12.373762 Opened device: /dev/dri/card0
12266 18:09:12.377359 Starting subtest: basic
12267 18:09:12.380920 No dynamic tests executed.
12268 18:09:12.383684 [1mSubtest basic: SKIP (0.000s)[0m
12269 18:09:12.390525 IGT-Version: 1.28-ga44ebfe (a<14>[ 19.943383] [IGT] kms_setmode: executing
12270 18:09:12.397423 arch64) (Linux: <14>[ 19.948195] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12271 18:09:12.407055 6.1.92-cip22 aar<14>[ 19.955961] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12272 18:09:12.407171 ch64)
12273 18:09:12.413934 Using IGT<14>[ 19.964730] [IGT] kms_setmode: exiting, ret=77
12274 18:09:12.417021 _SRANDOM=1718129069 for randomisation
12275 18:09:12.423952 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12277 18:09:12.427430 Opened device: /dev/dri/c<8>[ 19.975255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12278 18:09:12.427534 ard0
12279 18:09:12.430488 Starting subtest: basic-clone-single-crtc
12280 18:09:12.433520 No dynamic tests executed.
12281 18:09:12.436996 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12282 18:09:12.443765 IGT-Version: 1.28-ga44ebfe <14>[ 19.997274] [IGT] kms_setmode: executing
12283 18:09:12.453737 (aarch64) (Linux<14>[ 20.002601] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12284 18:09:12.463942 : 6.1.92-cip22 a<14>[ 20.011621] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12285 18:09:12.464036 arch64)
12286 18:09:12.470494 Using I<14>[ 20.021502] [IGT] kms_setmode: exiting, ret=77
12287 18:09:12.473534 GT_SRANDOM=1718129069 for randomisation
12288 18:09:12.483728 Opened device: /dev/dri<8>[ 20.031861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12289 18:09:12.483813 /card0
12290 18:09:12.484054 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12292 18:09:12.490460 Starting<8>[ 20.043353] <LAVA_SIGNAL_TESTSET STOP>
12293 18:09:12.490716 Received signal: <TESTSET> STOP
12294 18:09:12.490787 Closing test_set kms_setmode
12295 18:09:12.493426 subtest: invalid-clone-single-crtc
12296 18:09:12.493507 No dynamic tests executed.
12297 18:09:12.499931 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12298 18:09:12.506666 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12299 18:09:12.509591 U<8>[ 20.063648] <LAVA_SIGNAL_TESTSET START kms_vblank>
12300 18:09:12.509876 Received signal: <TESTSET> START kms_vblank
12301 18:09:12.509975 Starting test_set kms_vblank
12302 18:09:12.516310 sing IGT_SRANDOM=1718129069 for randomisation
12303 18:09:12.516405 Opened device: /dev/dri/card0
12304 18:09:12.522871 Starting subtest: invalid-clone-exclusive-crtc
12305 18:09:12.522955 No dynamic tests executed.
12306 18:09:12.529535 [1mSu<14>[ 20.083199] [IGT] kms_vblank: executing
12307 18:09:12.536376 btest invalid-cl<14>[ 20.087877] [IGT] kms_vblank: exiting, ret=77
12308 18:09:12.539375 one-exclusive-crtc: SKIP (0.000s)[0m
12309 18:09:12.549535 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 20.100394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12310 18:09:12.549666 ux: 6.1.92-cip22 aarch64)
12311 18:09:12.549946 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12313 18:09:12.555965 Using IGT_SRANDOM=1718129069 for randomisation
12314 18:09:12.556084 Opened device: /dev/dri/card0
12315 18:09:12.562583 Starting subtest: clone-exclusive-crtc
12316 18:09:12.562697 No dynamic tests executed.
12317 18:09:12.570027 [1mSubtest clone-<14>[ 20.123606] [IGT] kms_vblank: executing
12318 18:09:12.575934 exclusive-crtc: <14>[ 20.128476] [IGT] kms_vblank: exiting, ret=77
12319 18:09:12.576048 SKIP (0.000s)[0m
12320 18:09:12.589800 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<8>[ 20.141018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12321 18:09:12.589914 ch64)
12322 18:09:12.590200 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12324 18:09:12.593133 Using IGT_SRANDOM=1718129069 for randomisation
12325 18:09:12.595998 Opened device: /dev/dri/card0
12326 18:09:12.602958 Starting subtest: invalid-clone-single-crtc-stealing
12327 18:09:12.606131 No dynamic tests exe<14>[ 20.161328] [IGT] kms_vblank: executing
12328 18:09:12.609084 cuted.
12329 18:09:12.612613 [1mSubt<14>[ 20.166190] [IGT] kms_vblank: exiting, ret=77
12330 18:09:12.619179 est invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12331 18:09:12.625691 IGT-V<8>[ 20.176435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12332 18:09:12.625964 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12334 18:09:12.632309 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12335 18:09:12.635449 Using IGT_SRANDOM=1718129069 for randomisation
12336 18:09:12.639322 Opened device: /dev/dri/card0
12337 18:09:12.646135 No KMS driver or n<14>[ 20.197816] [IGT] kms_vblank: executing
12338 18:09:12.648926 o outputs, pipes<14>[ 20.203278] [IGT] kms_vblank: exiting, ret=77
12339 18:09:12.652456 : 16, outputs: 0
12340 18:09:12.656045 [1mSubtest invalid: SKIP (0.000s)[0m
12341 18:09:12.662371 IGT-Ve<8>[ 20.213382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12342 18:09:12.662673 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12344 18:09:12.669540 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12345 18:09:12.672277 Using IGT_SRANDOM=1718129069 for randomisation
12346 18:09:12.675857 Opened device: /dev/dri/card0
12347 18:09:12.682234 No KMS driver or no outputs, pipes:<14>[ 20.235701] [IGT] kms_vblank: executing
12348 18:09:12.682323 16, outputs: 0
12349 18:09:12.689122 <14>[ 20.241223] [IGT] kms_vblank: exiting, ret=77
12350 18:09:12.689209
12351 18:09:12.692955 [1mSubtest crtc-id: SKIP (0.000s)[0m
12352 18:09:12.702978 IGT-Version: 1.28-ga44e<8>[ 20.251715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12353 18:09:12.703264 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12355 18:09:12.705554 bfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12356 18:09:12.709283 Using IGT_SRANDOM=1718129069 for randomisation
12357 18:09:12.712290 Opened device: /dev/dri/card0
12358 18:09:12.716193 No KMS driver or no outputs, pipes: 16, outputs: 0
12359 18:09:12.722625 <14>[ 20.273971] [IGT] kms_vblank: executing
12360 18:09:12.725879 [1mSubtest accu<14>[ 20.279871] [IGT] kms_vblank: exiting, ret=77
12361 18:09:12.728871 racy-idle: SKIP (0.000s)[0m
12362 18:09:12.738863 IGT-Version: 1.28-ga44ebfe (aarch6<8>[ 20.290058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12363 18:09:12.739149 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12365 18:09:12.742321 4) (Linux: 6.1.92-cip22 aarch64)
12366 18:09:12.745725 Using IGT_SRANDOM=1718129069 for randomisation
12367 18:09:12.749350 Opened device: /dev/dri/card0
12368 18:09:12.759021 No KMS driver or no outputs, pipes: 16, outputs<14>[ 20.310928] [IGT] kms_vblank: executing
12369 18:09:12.759111 : 0
12370 18:09:12.765488 [1mSubtest<14>[ 20.316705] [IGT] kms_vblank: exiting, ret=77
12371 18:09:12.765565 query-idle: SKIP (0.000s)[0m
12372 18:09:12.775911 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 20.326867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12373 18:09:12.776169 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12375 18:09:12.778767 h64) (Linux: 6.1.92-cip22 aarch64)
12376 18:09:12.785916 Using IGT_SRANDOM=1718129069 for randomisation
12377 18:09:12.785998 Opened device: /dev/dri/card0
12378 18:09:12.795776 No KMS driver or no outputs, pipes: 16, outpu<14>[ 20.348486] [IGT] kms_vblank: executing
12379 18:09:12.795861 ts: 0
12380 18:09:12.801749 [1mSubte<14>[ 20.354134] [IGT] kms_vblank: exiting, ret=77
12381 18:09:12.805509 st query-idle-hang: SKIP (0.000s)[0m
12382 18:09:12.811860 IGT-Version: 1.28-ga44ebf<8>[ 20.364139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12383 18:09:12.812144 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12385 18:09:12.818615 e (aarch64) (Linux: 6.1.92-cip22 aarch64)
12386 18:09:12.822218 Using IGT_SRANDOM=1718129069 for randomisation
12387 18:09:12.825342 Opened device: /dev/dri/card0
12388 18:09:12.832020 No KMS driver or no outputs, pipes: 16<14>[ 20.385877] [IGT] kms_vblank: executing
12389 18:09:12.832101 , outputs: 0
12390 18:09:12.838615 [<14>[ 20.390927] [IGT] kms_vblank: exiting, ret=77
12391 18:09:12.842100 1mSubtest query-forked: SKIP (0.000s)[0m
12392 18:09:12.852369 IGT-Version: 1.28-ga4<8>[ 20.401259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12393 18:09:12.852649 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12395 18:09:12.855570 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12396 18:09:12.859150 Using IGT_SRANDOM=1718129069 for randomisation
12397 18:09:12.862023 Opened device: /dev/dri/card0
12398 18:09:12.872151 No KMS driver or no outputs, pipes: 16, outputs: 0<14>[ 20.423309] [IGT] kms_vblank: executing
12399 18:09:12.872263
12400 18:09:12.875001 [1mSubtest qu<14>[ 20.429401] [IGT] kms_vblank: exiting, ret=77
12401 18:09:12.878498 ery-forked-hang: SKIP (0.000s)[0m
12402 18:09:12.888681 IGT-Version: 1.28-ga44ebfe (<8>[ 20.439524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12403 18:09:12.888942 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12405 18:09:12.892367 aarch64) (Linux: 6.1.92-cip22 aarch64)
12406 18:09:12.898357 Using IGT_SRANDOM=1718129069 for randomisation
12407 18:09:12.898439 Opened device: /dev/dri/card0
12408 18:09:12.908164 No KMS driver or no outputs, pipes: 16, o<14>[ 20.461142] [IGT] kms_vblank: executing
12409 18:09:12.908248 utputs: 0
12410 18:09:12.914729 [1mS<14>[ 20.466638] [IGT] kms_vblank: exiting, ret=77
12411 18:09:12.918283 ubtest query-busy: SKIP (0.000s)[0m
12412 18:09:12.928392 IGT-Version: 1.28-ga44ebfe<8>[ 20.476987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12413 18:09:12.928655 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12415 18:09:12.931404 (aarch64) (Linux: 6.1.92-cip22 aarch64)
12416 18:09:12.935231 Using IGT_SRANDOM=1718129069 for randomisation
12417 18:09:12.937959 Opened device: /dev/dri/card0
12418 18:09:12.945029 No KMS driver or no outputs, pipes: 16,<14>[ 20.499282] [IGT] kms_vblank: executing
12419 18:09:12.948458 outputs: 0
12420 18:09:12.951362 [1<14>[ 20.504344] [IGT] kms_vblank: exiting, ret=77
12421 18:09:12.954475 mSubtest query-busy-hang: SKIP (0.000s)[0m
12422 18:09:12.964534 IGT-Version: 1.28-g<8>[ 20.514586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12423 18:09:12.964793 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12425 18:09:12.967456 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12426 18:09:12.971069 Using IGT_SRANDOM=1718129069 for randomisation
12427 18:09:12.974921 Opened device: /dev/dri/card0
12428 18:09:12.980909 No KMS driver or no outputs, pip<14>[ 20.535750] [IGT] kms_vblank: executing
12429 18:09:12.987731 es: 16, outputs:<14>[ 20.541098] [IGT] kms_vblank: exiting, ret=77
12430 18:09:12.987822 0
12431 18:09:12.994257 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12432 18:09:13.000812 IGT-Versio<8>[ 20.551594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12433 18:09:13.001092 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12435 18:09:13.007367 n: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12436 18:09:13.011129 Using IGT_SRANDOM=1718129069 for randomisation
12437 18:09:13.014121 Opened device: /dev/dri/card0
12438 18:09:13.020775 No KMS driver or no out<14>[ 20.572542] [IGT] kms_vblank: executing
12439 18:09:13.024456 puts, pipes: 16,<14>[ 20.578132] [IGT] kms_vblank: exiting, ret=77
12440 18:09:13.027401 outputs: 0
12441 18:09:13.037482 [1mSubtest query-forked-busy-hang: SKIP (0.000s)[<8>[ 20.588522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12442 18:09:13.037568 0m
12443 18:09:13.037808 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12445 18:09:13.044295 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12446 18:09:13.047158 Using IGT_SRANDOM=1718129069 for randomisation
12447 18:09:13.050719 Opened device: /dev/dri/card0
12448 18:09:13.057837 No KMS dr<14>[ 20.609750] [IGT] kms_vblank: executing
12449 18:09:13.060971 iver or no outpu<14>[ 20.615227] [IGT] kms_vblank: exiting, ret=77
12450 18:09:13.063845 ts, pipes: 16, outputs: 0
12451 18:09:13.073827 [1mSubtest wait-idle: SKIP (0.000s)<8>[ 20.625136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12452 18:09:13.073915 [0m
12453 18:09:13.074154 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12455 18:09:13.081144 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12456 18:09:13.087154 Using IGT_SRANDOM=1718129070 for randomisation
12457 18:09:13.087234 Opened device: /dev/dri/card0
12458 18:09:13.094213 No KMS driver or no outp<14>[ 20.647976] [IGT] kms_vblank: executing
12459 18:09:13.100579 uts, pipes: 16, <14>[ 20.653602] [IGT] kms_vblank: exiting, ret=77
12460 18:09:13.100659 outputs: 0
12461 18:09:13.106915 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12462 18:09:13.113838 IGT-V<8>[ 20.663695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12463 18:09:13.114116 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12465 18:09:13.117049 ersion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12466 18:09:13.123582 Using IGT_SRANDOM=1718129070 for randomisation
12467 18:09:13.123662 Opened device: /dev/dri/card0
12468 18:09:13.130460 No KMS driver or n<14>[ 20.684630] [IGT] kms_vblank: executing
12469 18:09:13.137109 o outputs, pipes<14>[ 20.690235] [IGT] kms_vblank: exiting, ret=77
12470 18:09:13.140557 : 16, outputs: 0
12471 18:09:13.144296 [1mSubtest wait-forked: SKIP (0.000s)[0m
12472 18:09:13.150711 IG<8>[ 20.700430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12473 18:09:13.150973 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12475 18:09:13.157103 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12476 18:09:13.160557 Using IGT_SRANDOM=1718129070 for randomisation
12477 18:09:13.163585 Opened device: /dev/dri/card0
12478 18:09:13.167433 No KMS driver o<14>[ 20.721676] [IGT] kms_vblank: executing
12479 18:09:13.173676 r no outputs, pi<14>[ 20.727438] [IGT] kms_vblank: exiting, ret=77
12480 18:09:13.177154 pes: 16, outputs: 0
12481 18:09:13.187253 [1mSubtest wait-forked-hang: SKIP (0.000s)<8>[ 20.737398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12482 18:09:13.187355 [0m
12483 18:09:13.187593 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12485 18:09:13.194063 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12486 18:09:13.197107 Using IGT_SRANDOM=1718129070 for randomisation
12487 18:09:13.200609 Opened device: /dev/dri/card0
12488 18:09:13.207021 No KMS <14>[ 20.759691] [IGT] kms_vblank: executing
12489 18:09:13.210003 driver or no out<14>[ 20.764383] [IGT] kms_vblank: exiting, ret=77
12490 18:09:13.213676 puts, pipes: 16, outputs: 0
12491 18:09:13.223944 [1mSubtest wait-busy: SKIP (0.000s<8>[ 20.774626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12492 18:09:13.224220 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12494 18:09:13.227116 )[0m
12495 18:09:13.229914 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12496 18:09:13.236790 Using IGT_SRANDOM=1718129070 for randomisation
12497 18:09:13.240032 Opened device: /dev/d<14>[ 20.795781] [IGT] kms_vblank: executing
12498 18:09:13.243846 ri/card0
12499 18:09:13.246619 No KMS<14>[ 20.800730] [IGT] kms_vblank: exiting, ret=77
12500 18:09:13.253566 driver or no outputs, pipes: 16, outputs: 0
12501 18:09:13.260192 [1mSubtest wait-b<8>[ 20.811320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12502 18:09:13.260453 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12504 18:09:13.262984 usy-hang: SKIP (0.000s)[0m
12505 18:09:13.270045 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12506 18:09:13.273131 Using IGT_SRANDOM=1718129070 for randomisation
12507 18:09:13.279747 Opened device: <14>[ 20.833308] [IGT] kms_vblank: executing
12508 18:09:13.279833 /dev/dri/card0
12509 18:09:13.286201 <14>[ 20.838236] [IGT] kms_vblank: exiting, ret=77
12510 18:09:13.289844 No KMS driver or no outputs, pipes: 16, outputs: 0
12511 18:09:13.300248 [1mSubtest <8>[ 20.848551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12512 18:09:13.300505 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12514 18:09:13.303390 wait-forked-busy: SKIP (0.000s)[0m
12515 18:09:13.310095 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12516 18:09:13.313154 Using IGT_SRANDOM=1718129070 for randomisation
12517 18:09:13.320130 Opened device: /dev/dri<14>[ 20.871994] [IGT] kms_vblank: executing
12518 18:09:13.320214 /card0
12519 18:09:13.326093 No KMS d<14>[ 20.877603] [IGT] kms_vblank: exiting, ret=77
12520 18:09:13.329763 river or no outputs, pipes: 16, outputs: 0
12521 18:09:13.339244 [1mSubtest wait-for<8>[ 20.888021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12522 18:09:13.339522 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12524 18:09:13.342678 ked-busy-hang: SKIP (0.000s)[0m
12525 18:09:13.346185 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12526 18:09:13.353116 Using IGT_SRANDOM=1718129070 for randomisation
12527 18:09:13.355907 Opened dev<14>[ 20.909983] [IGT] kms_vblank: executing
12528 18:09:13.362338 ice: /dev/dri/ca<14>[ 20.915509] [IGT] kms_vblank: exiting, ret=77
12529 18:09:13.362429 rd0
12530 18:09:13.369520 No KMS driver or no outputs, pipes: 16, outputs: 0
12531 18:09:13.375587 [1mSub<8>[ 20.925711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12532 18:09:13.375856 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12534 18:09:13.378796 test ts-continuation-idle: SKIP (0.000s)[0m
12535 18:09:13.385725 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12536 18:09:13.392222 Using IGT_SRANDOM=1718129070 for randomisation
12537 18:09:13.392335 Opened device: /dev/dri/card0
12538 18:09:13.399069 No KMS driver o<14>[ 20.952162] [IGT] kms_vblank: executing
12539 18:09:13.405726 r no outputs, pi<14>[ 20.957980] [IGT] kms_vblank: exiting, ret=77
12540 18:09:13.405809 pes: 16, outputs: 0
12541 18:09:13.419276 [1mSubtest ts-continuation-idle-hang: SKIP<8>[ 20.968075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12542 18:09:13.419364 (0.000s)[0m
12543 18:09:13.419604 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12545 18:09:13.425875 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12546 18:09:13.428776 Using IGT_SRANDOM=1718129070 for randomisation
12547 18:09:13.432562 Opened device: /dev/dri/card0
12548 18:09:13.438735 No KMS driver <14>[ 20.991838] [IGT] kms_vblank: executing
12549 18:09:13.445317 or no outputs, p<14>[ 20.997171] [IGT] kms_vblank: exiting, ret=77
12550 18:09:13.445400 ipes: 16, outputs: 0
12551 18:09:13.458362 [1mSubtest ts-continuation-dpms-rpm: SKIP<8>[ 21.007470] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12552 18:09:13.458454 (0.000s)[0m
12553 18:09:13.458694 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12555 18:09:13.465220 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12556 18:09:13.468918 Using IGT_SRANDOM=1718129070 for randomisation
12557 18:09:13.475190 Opened device: /dev/dri/card0<14>[ 21.029894] [IGT] kms_vblank: executing
12558 18:09:13.475280
12559 18:09:13.481910 No KMS driver <14>[ 21.035318] [IGT] kms_vblank: exiting, ret=77
12560 18:09:13.485393 or no outputs, pipes: 16, outputs: 0
12561 18:09:13.495418 [1mSubtest ts-continuatio<8>[ 21.045358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12562 18:09:13.495681 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12564 18:09:13.498357 n-dpms-suspend: SKIP (0.000s)[0m
12565 18:09:13.505197 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12566 18:09:13.508199 Using IGT_SRANDOM=1718129070 for randomisation
12567 18:09:13.514668 Opened de<14>[ 21.068183] [IGT] kms_vblank: executing
12568 18:09:13.521677 vice: /dev/dri/c<14>[ 21.073282] [IGT] kms_vblank: exiting, ret=77
12569 18:09:13.521788 ard0
12570 18:09:13.524644 No KMS driver or no outputs, pipes: 16, outputs: 0
12571 18:09:13.534740 [1mSu<8>[ 21.083568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12572 18:09:13.535000 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12574 18:09:13.541961 btest ts-continuation-suspend: S<8>[ 21.094348] <LAVA_SIGNAL_TESTSET STOP>
12575 18:09:13.542219 Received signal: <TESTSET> STOP
12576 18:09:13.542295 Closing test_set kms_vblank
12577 18:09:13.548485 KIP (0.000s)[0m<8>[ 21.100744] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14291388_1.5.2.3.1>
12578 18:09:13.548574
12579 18:09:13.548833 Received signal: <ENDRUN> 0_igt-kms-mediatek 14291388_1.5.2.3.1
12580 18:09:13.548919 Ending use of test pattern.
12581 18:09:13.548993 Ending test lava.0_igt-kms-mediatek (14291388_1.5.2.3.1), duration 6.20
12583 18:09:13.555282 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12584 18:09:13.557997 Using IGT_SRANDOM=1718129070 for randomisation
12585 18:09:13.561506 Opened device: /dev/dri/card0
12586 18:09:13.568285 No KMS driver or no outputs, pipes: 16, outputs: 0
12587 18:09:13.571161 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12588 18:09:13.577870 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12589 18:09:13.581395 Using IGT_SRANDOM=1718129070 for randomisation
12590 18:09:13.585110 Opened device: /dev/dri/card0
12591 18:09:13.588089 No KMS driver or no outputs, pipes: 16, outputs: 0
12592 18:09:13.594894 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12593 18:09:13.601461 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12594 18:09:13.604295 Using IGT_SRANDOM=1718129070 for randomisation
12595 18:09:13.608272 Opened device: /dev/dri/card0
12596 18:09:13.611139 No KMS driver or no outputs, pipes: 16, outputs: 0
12597 18:09:13.618416 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12598 18:09:13.618499 + set +x
12599 18:09:13.618741 ok: lava_test_shell seems to have completed
12600 18:09:13.620331 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12601 18:09:13.620491 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12602 18:09:13.620583 end: 3 lava-test-retry (duration 00:00:07) [common]
12603 18:09:13.620671 start: 4 finalize (timeout 00:07:50) [common]
12604 18:09:13.620759 start: 4.1 power-off (timeout 00:00:30) [common]
12605 18:09:13.620914 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
12606 18:09:13.698483 >> Command sent successfully.
12607 18:09:13.700891 Returned 0 in 0 seconds
12608 18:09:13.801305 end: 4.1 power-off (duration 00:00:00) [common]
12610 18:09:13.801631 start: 4.2 read-feedback (timeout 00:07:49) [common]
12612 18:09:13.802183 Listened to connection for namespace 'common' for up to 1s
12613 18:09:14.802816 Finalising connection for namespace 'common'
12614 18:09:14.802991 Disconnecting from shell: Finalise
12615 18:09:14.803066 / #
12616 18:09:14.903359 end: 4.2 read-feedback (duration 00:00:01) [common]
12617 18:09:14.903520 end: 4 finalize (duration 00:00:01) [common]
12618 18:09:14.903638 Cleaning after the job
12619 18:09:14.903742 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/ramdisk
12620 18:09:14.910489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/kernel
12621 18:09:14.925818 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/dtb
12622 18:09:14.926036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291388/tftp-deploy-_npp91nq/modules
12623 18:09:14.931819 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291388
12624 18:09:15.043988 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291388
12625 18:09:15.044167 Job finished correctly