Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 49
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 18:35:10.763620 lava-dispatcher, installed at version: 2024.03
2 18:35:10.763850 start: 0 validate
3 18:35:10.763988 Start time: 2024-06-11 18:35:10.763980+00:00 (UTC)
4 18:35:10.764118 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:35:10.764259 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:35:11.044770 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:35:11.045467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:35:11.356508 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:35:11.357166 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 18:35:11.635480 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:35:11.635663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:35:12.178726 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:35:12.179546 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:35:12.496443 validate duration: 1.73
16 18:35:12.496750 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:35:12.496858 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:35:12.496954 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:35:12.497095 Not decompressing ramdisk as can be used compressed.
20 18:35:12.497189 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:35:12.497263 saving as /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/ramdisk/initrd.cpio.gz
22 18:35:12.497335 total size: 5628169 (5 MB)
23 18:35:12.498520 progress 0 % (0 MB)
24 18:35:12.500467 progress 5 % (0 MB)
25 18:35:12.502360 progress 10 % (0 MB)
26 18:35:12.504058 progress 15 % (0 MB)
27 18:35:12.505937 progress 20 % (1 MB)
28 18:35:12.507646 progress 25 % (1 MB)
29 18:35:12.509524 progress 30 % (1 MB)
30 18:35:12.511373 progress 35 % (1 MB)
31 18:35:12.513027 progress 40 % (2 MB)
32 18:35:12.514899 progress 45 % (2 MB)
33 18:35:12.516572 progress 50 % (2 MB)
34 18:35:12.518413 progress 55 % (2 MB)
35 18:35:12.520257 progress 60 % (3 MB)
36 18:35:12.521901 progress 65 % (3 MB)
37 18:35:12.523768 progress 70 % (3 MB)
38 18:35:12.525359 progress 75 % (4 MB)
39 18:35:12.527056 progress 80 % (4 MB)
40 18:35:12.528626 progress 85 % (4 MB)
41 18:35:12.530348 progress 90 % (4 MB)
42 18:35:12.532050 progress 95 % (5 MB)
43 18:35:12.533587 progress 100 % (5 MB)
44 18:35:12.533947 5 MB downloaded in 0.04 s (146.60 MB/s)
45 18:35:12.534104 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:35:12.534369 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:35:12.534462 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:35:12.534553 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:35:12.534694 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:35:12.534773 saving as /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/kernel/Image
52 18:35:12.534841 total size: 54813184 (52 MB)
53 18:35:12.534908 No compression specified
54 18:35:12.536230 progress 0 % (0 MB)
55 18:35:12.551902 progress 5 % (2 MB)
56 18:35:12.567527 progress 10 % (5 MB)
57 18:35:12.583070 progress 15 % (7 MB)
58 18:35:12.598499 progress 20 % (10 MB)
59 18:35:12.613561 progress 25 % (13 MB)
60 18:35:12.628721 progress 30 % (15 MB)
61 18:35:12.644255 progress 35 % (18 MB)
62 18:35:12.659795 progress 40 % (20 MB)
63 18:35:12.675207 progress 45 % (23 MB)
64 18:35:12.690811 progress 50 % (26 MB)
65 18:35:12.706265 progress 55 % (28 MB)
66 18:35:12.721473 progress 60 % (31 MB)
67 18:35:12.736757 progress 65 % (34 MB)
68 18:35:12.751998 progress 70 % (36 MB)
69 18:35:12.767296 progress 75 % (39 MB)
70 18:35:12.782921 progress 80 % (41 MB)
71 18:35:12.798424 progress 85 % (44 MB)
72 18:35:12.814352 progress 90 % (47 MB)
73 18:35:12.829551 progress 95 % (49 MB)
74 18:35:12.844593 progress 100 % (52 MB)
75 18:35:12.844855 52 MB downloaded in 0.31 s (168.62 MB/s)
76 18:35:12.845023 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:35:12.845279 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:35:12.845376 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:35:12.845469 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:35:12.845619 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 18:35:12.845696 saving as /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 18:35:12.845765 total size: 57695 (0 MB)
84 18:35:12.845834 No compression specified
85 18:35:12.847082 progress 56 % (0 MB)
86 18:35:12.847387 progress 100 % (0 MB)
87 18:35:12.847626 0 MB downloaded in 0.00 s (29.62 MB/s)
88 18:35:12.847762 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:35:12.848016 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:35:12.848112 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:35:12.848203 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:35:12.848329 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:35:12.848405 saving as /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/nfsrootfs/full.rootfs.tar
95 18:35:12.848472 total size: 120894716 (115 MB)
96 18:35:12.848540 Using unxz to decompress xz
97 18:35:12.852911 progress 0 % (0 MB)
98 18:35:13.230506 progress 5 % (5 MB)
99 18:35:13.624581 progress 10 % (11 MB)
100 18:35:14.008346 progress 15 % (17 MB)
101 18:35:14.366125 progress 20 % (23 MB)
102 18:35:14.693734 progress 25 % (28 MB)
103 18:35:15.084056 progress 30 % (34 MB)
104 18:35:15.453093 progress 35 % (40 MB)
105 18:35:15.636495 progress 40 % (46 MB)
106 18:35:15.831599 progress 45 % (51 MB)
107 18:35:16.169703 progress 50 % (57 MB)
108 18:35:16.579459 progress 55 % (63 MB)
109 18:35:16.961315 progress 60 % (69 MB)
110 18:35:17.336003 progress 65 % (74 MB)
111 18:35:17.722054 progress 70 % (80 MB)
112 18:35:18.114240 progress 75 % (86 MB)
113 18:35:18.490089 progress 80 % (92 MB)
114 18:35:18.878921 progress 85 % (98 MB)
115 18:35:19.269888 progress 90 % (103 MB)
116 18:35:19.630583 progress 95 % (109 MB)
117 18:35:20.027915 progress 100 % (115 MB)
118 18:35:20.033804 115 MB downloaded in 7.19 s (16.05 MB/s)
119 18:35:20.034087 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:35:20.034385 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:35:20.034490 start: 1.5 download-retry (timeout 00:09:52) [common]
123 18:35:20.034588 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 18:35:20.034757 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:35:20.034837 saving as /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/modules/modules.tar
126 18:35:20.034904 total size: 8618176 (8 MB)
127 18:35:20.034975 Using unxz to decompress xz
128 18:35:20.039391 progress 0 % (0 MB)
129 18:35:20.060391 progress 5 % (0 MB)
130 18:35:20.091075 progress 10 % (0 MB)
131 18:35:20.123686 progress 15 % (1 MB)
132 18:35:20.150155 progress 20 % (1 MB)
133 18:35:20.176304 progress 25 % (2 MB)
134 18:35:20.202378 progress 30 % (2 MB)
135 18:35:20.231293 progress 35 % (2 MB)
136 18:35:20.258411 progress 40 % (3 MB)
137 18:35:20.283495 progress 45 % (3 MB)
138 18:35:20.310038 progress 50 % (4 MB)
139 18:35:20.337534 progress 55 % (4 MB)
140 18:35:20.364147 progress 60 % (4 MB)
141 18:35:20.390300 progress 65 % (5 MB)
142 18:35:20.420104 progress 70 % (5 MB)
143 18:35:20.446506 progress 75 % (6 MB)
144 18:35:20.475144 progress 80 % (6 MB)
145 18:35:20.501836 progress 85 % (7 MB)
146 18:35:20.529825 progress 90 % (7 MB)
147 18:35:20.558139 progress 95 % (7 MB)
148 18:35:20.588011 progress 100 % (8 MB)
149 18:35:20.592711 8 MB downloaded in 0.56 s (14.73 MB/s)
150 18:35:20.592978 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:35:20.593263 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:35:20.593365 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:35:20.593466 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:35:24.427289 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc
156 18:35:24.427513 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:35:24.427622 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 18:35:24.427813 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n
159 18:35:24.427960 makedir: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin
160 18:35:24.428074 makedir: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/tests
161 18:35:24.428185 makedir: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/results
162 18:35:24.428295 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-add-keys
163 18:35:24.428451 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-add-sources
164 18:35:24.428591 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-background-process-start
165 18:35:24.428732 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-background-process-stop
166 18:35:24.428869 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-common-functions
167 18:35:24.429005 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-echo-ipv4
168 18:35:24.429143 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-install-packages
169 18:35:24.429280 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-installed-packages
170 18:35:24.429416 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-os-build
171 18:35:24.429554 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-probe-channel
172 18:35:24.429691 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-probe-ip
173 18:35:24.429832 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-target-ip
174 18:35:24.429968 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-target-mac
175 18:35:24.430105 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-target-storage
176 18:35:24.430243 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-case
177 18:35:24.430380 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-event
178 18:35:24.430515 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-feedback
179 18:35:24.430652 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-raise
180 18:35:24.430788 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-reference
181 18:35:24.430925 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-runner
182 18:35:24.431059 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-set
183 18:35:24.431205 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-test-shell
184 18:35:24.431347 Updating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-add-keys (debian)
185 18:35:24.431522 Updating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-add-sources (debian)
186 18:35:24.431677 Updating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-install-packages (debian)
187 18:35:24.431827 Updating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-installed-packages (debian)
188 18:35:24.431976 Updating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/bin/lava-os-build (debian)
189 18:35:24.432107 Creating /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/environment
190 18:35:24.432212 LAVA metadata
191 18:35:24.432285 - LAVA_JOB_ID=14291342
192 18:35:24.432353 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:35:24.432474 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 18:35:24.432548 skipped lava-vland-overlay
195 18:35:24.432630 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:35:24.432717 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 18:35:24.432782 skipped lava-multinode-overlay
198 18:35:24.432867 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:35:24.432953 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 18:35:24.433032 Loading test definitions
201 18:35:24.433127 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 18:35:24.433220 Using /lava-14291342 at stage 0
203 18:35:24.433538 uuid=14291342_1.6.2.3.1 testdef=None
204 18:35:24.433635 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:35:24.433727 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 18:35:24.434220 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:35:24.434466 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 18:35:24.435074 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:35:24.435328 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 18:35:24.435923 runner path: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/0/tests/0_timesync-off test_uuid 14291342_1.6.2.3.1
213 18:35:24.436095 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:35:24.436340 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 18:35:24.436420 Using /lava-14291342 at stage 0
217 18:35:24.436527 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:35:24.436624 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/0/tests/1_kselftest-alsa'
219 18:35:26.430261 Running '/usr/bin/git checkout kernelci.org
220 18:35:26.591955 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 18:35:26.592764 uuid=14291342_1.6.2.3.5 testdef=None
222 18:35:26.592958 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:35:26.593243 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 18:35:26.594146 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:35:26.594394 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 18:35:26.595473 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:35:26.595750 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 18:35:26.596810 runner path: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/0/tests/1_kselftest-alsa test_uuid 14291342_1.6.2.3.5
232 18:35:26.596909 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 18:35:26.596979 BRANCH='cip'
234 18:35:26.597044 SKIPFILE='/dev/null'
235 18:35:26.597109 SKIP_INSTALL='True'
236 18:35:26.597169 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:35:26.597232 TST_CASENAME=''
238 18:35:26.597295 TST_CMDFILES='alsa'
239 18:35:26.597449 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:35:26.597669 Creating lava-test-runner.conf files
242 18:35:26.597740 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291342/lava-overlay-829_ik0n/lava-14291342/0 for stage 0
243 18:35:26.597840 - 0_timesync-off
244 18:35:26.597953 - 1_kselftest-alsa
245 18:35:26.598059 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:35:26.598155 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 18:35:34.873801 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:35:34.873981 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 18:35:34.874099 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:35:34.874266 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:35:34.874381 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 18:35:35.055363 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:35:35.055808 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 18:35:35.055948 extracting modules file /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc
255 18:35:35.300019 extracting modules file /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291342/extract-overlay-ramdisk-vbg8wpiq/ramdisk
256 18:35:35.544363 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:35:35.544556 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 18:35:35.544679 [common] Applying overlay to NFS
259 18:35:35.544767 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291342/compress-overlay-_wolbnbl/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc
260 18:35:36.563938 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:35:36.564117 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 18:35:36.564218 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:35:36.564314 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 18:35:36.564408 Building ramdisk /var/lib/lava/dispatcher/tmp/14291342/extract-overlay-ramdisk-vbg8wpiq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291342/extract-overlay-ramdisk-vbg8wpiq/ramdisk
265 18:35:36.958426 >> 130400 blocks
266 18:35:39.198700 rename /var/lib/lava/dispatcher/tmp/14291342/extract-overlay-ramdisk-vbg8wpiq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/ramdisk/ramdisk.cpio.gz
267 18:35:39.199188 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 18:35:39.199327 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 18:35:39.199469 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 18:35:39.199603 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/kernel/Image']
271 18:35:53.144575 Returned 0 in 13 seconds
272 18:35:53.245651 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/kernel/image.itb
273 18:35:53.634606 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:35:53.635020 output: Created: Tue Jun 11 19:35:53 2024
275 18:35:53.635109 output: Image 0 (kernel-1)
276 18:35:53.635180 output: Description:
277 18:35:53.635248 output: Created: Tue Jun 11 19:35:53 2024
278 18:35:53.635317 output: Type: Kernel Image
279 18:35:53.635385 output: Compression: lzma compressed
280 18:35:53.635466 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:35:53.635533 output: Architecture: AArch64
282 18:35:53.635601 output: OS: Linux
283 18:35:53.635666 output: Load Address: 0x00000000
284 18:35:53.635733 output: Entry Point: 0x00000000
285 18:35:53.635799 output: Hash algo: crc32
286 18:35:53.635863 output: Hash value: 7a9e9d3e
287 18:35:53.635926 output: Image 1 (fdt-1)
288 18:35:53.635987 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 18:35:53.636049 output: Created: Tue Jun 11 19:35:53 2024
290 18:35:53.636114 output: Type: Flat Device Tree
291 18:35:53.636174 output: Compression: uncompressed
292 18:35:53.636237 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 18:35:53.636296 output: Architecture: AArch64
294 18:35:53.636355 output: Hash algo: crc32
295 18:35:53.636414 output: Hash value: a9713552
296 18:35:53.636473 output: Image 2 (ramdisk-1)
297 18:35:53.636532 output: Description: unavailable
298 18:35:53.636591 output: Created: Tue Jun 11 19:35:53 2024
299 18:35:53.636651 output: Type: RAMDisk Image
300 18:35:53.636711 output: Compression: Unknown Compression
301 18:35:53.636770 output: Data Size: 18734143 Bytes = 18295.06 KiB = 17.87 MiB
302 18:35:53.636830 output: Architecture: AArch64
303 18:35:53.636889 output: OS: Linux
304 18:35:53.636948 output: Load Address: unavailable
305 18:35:53.637012 output: Entry Point: unavailable
306 18:35:53.637078 output: Hash algo: crc32
307 18:35:53.637138 output: Hash value: ffcaedf0
308 18:35:53.637197 output: Default Configuration: 'conf-1'
309 18:35:53.637257 output: Configuration 0 (conf-1)
310 18:35:53.637316 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 18:35:53.637375 output: Kernel: kernel-1
312 18:35:53.637434 output: Init Ramdisk: ramdisk-1
313 18:35:53.637492 output: FDT: fdt-1
314 18:35:53.637551 output: Loadables: kernel-1
315 18:35:53.637610 output:
316 18:35:53.637835 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 18:35:53.637948 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 18:35:53.638070 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 18:35:53.638174 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 18:35:53.638262 No LXC device requested
321 18:35:53.638349 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:35:53.638450 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 18:35:53.638539 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:35:53.638613 Checking files for TFTP limit of 4294967296 bytes.
325 18:35:53.639266 end: 1 tftp-deploy (duration 00:00:41) [common]
326 18:35:53.639427 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:35:53.639567 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:35:53.639720 substitutions:
329 18:35:53.639797 - {DTB}: 14291342/tftp-deploy-s8lw49u8/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 18:35:53.639869 - {INITRD}: 14291342/tftp-deploy-s8lw49u8/ramdisk/ramdisk.cpio.gz
331 18:35:53.639935 - {KERNEL}: 14291342/tftp-deploy-s8lw49u8/kernel/Image
332 18:35:53.640002 - {LAVA_MAC}: None
333 18:35:53.640066 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc
334 18:35:53.640129 - {NFS_SERVER_IP}: 192.168.201.1
335 18:35:53.640191 - {PRESEED_CONFIG}: None
336 18:35:53.640252 - {PRESEED_LOCAL}: None
337 18:35:53.640313 - {RAMDISK}: 14291342/tftp-deploy-s8lw49u8/ramdisk/ramdisk.cpio.gz
338 18:35:53.640373 - {ROOT_PART}: None
339 18:35:53.640433 - {ROOT}: None
340 18:35:53.640493 - {SERVER_IP}: 192.168.201.1
341 18:35:53.640553 - {TEE}: None
342 18:35:53.640612 Parsed boot commands:
343 18:35:53.640670 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:35:53.640871 Parsed boot commands: tftpboot 192.168.201.1 14291342/tftp-deploy-s8lw49u8/kernel/image.itb 14291342/tftp-deploy-s8lw49u8/kernel/cmdline
345 18:35:53.640969 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:35:53.641067 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:35:53.641167 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:35:53.641263 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:35:53.641342 Not connected, no need to disconnect.
350 18:35:53.641424 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:35:53.641515 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:35:53.641590 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
353 18:35:53.645743 Setting prompt string to ['lava-test: # ']
354 18:35:53.646168 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:35:53.646294 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:35:53.646412 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:35:53.646520 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:35:53.646732 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
359 18:36:03.828061 Returned 0 in 10 seconds
360 18:36:03.928781 end: 2.2.2.1 pdu-reboot (duration 00:00:10) [common]
362 18:36:03.929140 end: 2.2.2 reset-device (duration 00:00:10) [common]
363 18:36:03.929248 start: 2.2.3 depthcharge-start (timeout 00:04:50) [common]
364 18:36:03.929353 Setting prompt string to 'Starting depthcharge on Juniper...'
365 18:36:03.929433 Changing prompt to 'Starting depthcharge on Juniper...'
366 18:36:03.929507 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 18:36:03.929969 [Enter `^Ec?' for help]
368 18:36:03.930062 [DL] 00000000 00000000 010701
369 18:36:03.930139
370 18:36:03.930212
371 18:36:03.930281 F0: 102B 0000
372 18:36:03.930352
373 18:36:03.930421 F3: 1006 0033 [0200]
374 18:36:03.930490
375 18:36:03.930555 F3: 4001 00E0 [0200]
376 18:36:03.930619
377 18:36:03.930681 F3: 0000 0000
378 18:36:03.930743
379 18:36:03.930803 V0: 0000 0000 [0001]
380 18:36:03.930864
381 18:36:03.930923 00: 1027 0002
382 18:36:03.930988
383 18:36:03.931048 01: 0000 0000
384 18:36:03.931110
385 18:36:03.931170 BP: 0C00 0251 [0000]
386 18:36:03.931230
387 18:36:03.931289 G0: 1182 0000
388 18:36:03.931348
389 18:36:03.931414 EC: 0004 0000 [0001]
390 18:36:03.931476
391 18:36:03.931537 S7: 0000 0000 [0000]
392 18:36:03.931597
393 18:36:03.931657 CC: 0000 0000 [0001]
394 18:36:03.931717
395 18:36:03.931777 T0: 0000 00DB [000F]
396 18:36:03.931837
397 18:36:03.931897 Jump to BL
398 18:36:03.931958
399 18:36:03.932017
400 18:36:03.932077
401 18:36:03.932137 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 18:36:03.932203 ARM64: Exception handlers installed.
403 18:36:03.932265 ARM64: Testing exception
404 18:36:03.932325 ARM64: Done test exception
405 18:36:03.932385 WDT: Last reset was cold boot
406 18:36:03.932445 SPI0(PAD0) initialized at 992727 Hz
407 18:36:03.932530 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 18:36:03.932595 Manufacturer: ef
409 18:36:03.932658 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 18:36:03.932720 Probing TPM: . done!
411 18:36:03.932780 TPM ready after 0 ms
412 18:36:03.932841 Connected to device vid:did:rid of 1ae0:0028:00
413 18:36:03.932902 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 18:36:03.932964 Initialized TPM device CR50 revision 0
415 18:36:03.933025 tlcl_send_startup: Startup return code is 0
416 18:36:03.933086 TPM: setup succeeded
417 18:36:03.933148 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 18:36:03.933209 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 18:36:03.933270 in-header: 03 19 00 00 08 00 00 00
420 18:36:03.933330 in-data: a2 e0 47 00 13 00 00 00
421 18:36:03.933391 Chrome EC: UHEPI supported
422 18:36:03.933452 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 18:36:03.933513 in-header: 03 a1 00 00 08 00 00 00
424 18:36:03.933574 in-data: 84 60 60 10 00 00 00 00
425 18:36:03.933635 Phase 1
426 18:36:03.933695 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 18:36:03.933757 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 18:36:03.933818 VB2:vb2_check_recovery() Recovery was requested manually
429 18:36:03.933879 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 18:36:03.933941 Recovery requested (1009000e)
431 18:36:03.934002 tlcl_extend: response is 0
432 18:36:03.934063 tlcl_extend: response is 0
433 18:36:03.934123
434 18:36:03.934182
435 18:36:03.934242 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 18:36:03.934304 ARM64: Exception handlers installed.
437 18:36:03.934365 ARM64: Testing exception
438 18:36:03.934425 ARM64: Done test exception
439 18:36:03.934485 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x201c
440 18:36:03.934546 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 18:36:03.934607 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 18:36:03.934668 [RTC]rtc_get_frequency_meter,134: input=0xf, output=912
443 18:36:03.934729 [RTC]rtc_get_frequency_meter,134: input=0x7, output=778
444 18:36:03.934789 [RTC]rtc_get_frequency_meter,134: input=0xb, output=846
445 18:36:03.934850 [RTC]rtc_get_frequency_meter,134: input=0x9, output=812
446 18:36:03.934910 [RTC]rtc_get_frequency_meter,134: input=0x8, output=796
447 18:36:03.934970 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
448 18:36:03.935031 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 18:36:03.935092 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 18:36:03.935153 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 18:36:03.935214 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 18:36:03.935275 in-header: 03 19 00 00 08 00 00 00
453 18:36:03.935335 in-data: a2 e0 47 00 13 00 00 00
454 18:36:03.935396 Chrome EC: UHEPI supported
455 18:36:03.935462 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 18:36:03.935524 in-header: 03 a1 00 00 08 00 00 00
457 18:36:03.935584 in-data: 84 60 60 10 00 00 00 00
458 18:36:03.935645 Skip loading cached calibration data
459 18:36:03.935706 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 18:36:03.935767 in-header: 03 a1 00 00 08 00 00 00
461 18:36:03.935826 in-data: 84 60 60 10 00 00 00 00
462 18:36:03.935886 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 18:36:03.935947 in-header: 03 a1 00 00 08 00 00 00
464 18:36:03.936008 in-data: 84 60 60 10 00 00 00 00
465 18:36:03.936068 ADC[3]: Raw value=215860 ID=1
466 18:36:03.936129 Manufacturer: ef
467 18:36:03.936189 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 18:36:03.936251 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 18:36:03.936312 CBFS @ 21000 size 3d4000
470 18:36:03.936373 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 18:36:03.936434 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 18:36:03.936495 CBFS: Found @ offset 3c700 size 44
473 18:36:03.936555 DRAM-K: Full Calibration
474 18:36:03.936615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 18:36:03.936677 CBFS @ 21000 size 3d4000
476 18:36:03.936737 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 18:36:03.936798 CBFS: Locating 'fallback/dram'
478 18:36:03.936859 CBFS: Found @ offset 24b00 size 12268
479 18:36:03.936920 read SPI 0x45b44 0x1224c: 22775 us, 3263 KB/s, 26.104 Mbps
480 18:36:03.936980 ddr_geometry: 1, config: 0x0
481 18:36:03.937041 header.status = 0x0
482 18:36:03.937102 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 18:36:03.937163 header.version = 0x5 (expected: 0x5)
484 18:36:03.937224 header.size = 0x8f0 (expected: 0x8f0)
485 18:36:03.937284 header.config = 0x0
486 18:36:03.937344 header.flags = 0x0
487 18:36:03.937404 header.checksum = 0x0
488 18:36:03.937660 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 18:36:03.937732 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 18:36:03.937796 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 18:36:03.937857 ddr_geometry:1
492 18:36:03.937919 [EMI] new MDL number = 1
493 18:36:03.937980 dram_cbt_mode_extern: 0
494 18:36:03.938040 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 18:36:03.938101 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 18:36:03.938162
497 18:36:03.938222
498 18:36:03.938283 [Bianco] ETT version 0.0.0.1
499 18:36:03.938343 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 18:36:03.938403
501 18:36:03.938463 vSetVcoreByFreq with vcore:762500, freq=1600
502 18:36:03.938526
503 18:36:03.938587 [DramcInit]
504 18:36:03.938647 AutoRefreshCKEOff AutoREF OFF
505 18:36:03.938707 DDRPhyPLLSetting-CKEOFF
506 18:36:03.938768 DDRPhyPLLSetting-CKEON
507 18:36:03.938828
508 18:36:03.938888 Enable WDQS
509 18:36:03.938948 [ModeRegInit_LP4] CH0 RK0
510 18:36:03.939009 Write Rank0 MR13 =0x18
511 18:36:03.939068 Write Rank0 MR12 =0x5d
512 18:36:03.939129 Write Rank0 MR1 =0x56
513 18:36:03.939190 Write Rank0 MR2 =0x1a
514 18:36:03.939250 Write Rank0 MR11 =0x0
515 18:36:03.939310 Write Rank0 MR22 =0x38
516 18:36:03.939370 Write Rank0 MR14 =0x5d
517 18:36:03.939438 Write Rank0 MR3 =0x30
518 18:36:03.939499 Write Rank0 MR13 =0x58
519 18:36:03.939559 Write Rank0 MR12 =0x5d
520 18:36:03.939620 Write Rank0 MR1 =0x56
521 18:36:03.939680 Write Rank0 MR2 =0x2d
522 18:36:03.939740 Write Rank0 MR11 =0x23
523 18:36:03.939800 Write Rank0 MR22 =0x34
524 18:36:03.939860 Write Rank0 MR14 =0x10
525 18:36:03.939920 Write Rank0 MR3 =0x30
526 18:36:03.939980 Write Rank0 MR13 =0xd8
527 18:36:03.940039 [ModeRegInit_LP4] CH0 RK1
528 18:36:03.940099 Write Rank1 MR13 =0x18
529 18:36:03.940159 Write Rank1 MR12 =0x5d
530 18:36:03.940220 Write Rank1 MR1 =0x56
531 18:36:03.940279 Write Rank1 MR2 =0x1a
532 18:36:03.940339 Write Rank1 MR11 =0x0
533 18:36:03.940399 Write Rank1 MR22 =0x38
534 18:36:03.940459 Write Rank1 MR14 =0x5d
535 18:36:03.940518 Write Rank1 MR3 =0x30
536 18:36:03.940579 Write Rank1 MR13 =0x58
537 18:36:03.940639 Write Rank1 MR12 =0x5d
538 18:36:03.940698 Write Rank1 MR1 =0x56
539 18:36:03.940758 Write Rank1 MR2 =0x2d
540 18:36:03.940818 Write Rank1 MR11 =0x23
541 18:36:03.940877 Write Rank1 MR22 =0x34
542 18:36:03.940938 Write Rank1 MR14 =0x10
543 18:36:03.940998 Write Rank1 MR3 =0x30
544 18:36:03.941058 Write Rank1 MR13 =0xd8
545 18:36:03.941118 [ModeRegInit_LP4] CH1 RK0
546 18:36:03.941178 Write Rank0 MR13 =0x18
547 18:36:03.941237 Write Rank0 MR12 =0x5d
548 18:36:03.941297 Write Rank0 MR1 =0x56
549 18:36:03.941357 Write Rank0 MR2 =0x1a
550 18:36:03.941418 Write Rank0 MR11 =0x0
551 18:36:03.941478 Write Rank0 MR22 =0x38
552 18:36:03.941538 Write Rank0 MR14 =0x5d
553 18:36:03.941597 Write Rank0 MR3 =0x30
554 18:36:03.941657 Write Rank0 MR13 =0x58
555 18:36:03.941716 Write Rank0 MR12 =0x5d
556 18:36:03.941776 Write Rank0 MR1 =0x56
557 18:36:03.941836 Write Rank0 MR2 =0x2d
558 18:36:03.941896 Write Rank0 MR11 =0x23
559 18:36:03.941955 Write Rank0 MR22 =0x34
560 18:36:03.942015 Write Rank0 MR14 =0x10
561 18:36:03.942075 Write Rank0 MR3 =0x30
562 18:36:03.942134 Write Rank0 MR13 =0xd8
563 18:36:03.942194 [ModeRegInit_LP4] CH1 RK1
564 18:36:03.942254 Write Rank1 MR13 =0x18
565 18:36:03.942313 Write Rank1 MR12 =0x5d
566 18:36:03.942373 Write Rank1 MR1 =0x56
567 18:36:03.942432 Write Rank1 MR2 =0x1a
568 18:36:03.942493 Write Rank1 MR11 =0x0
569 18:36:03.942552 Write Rank1 MR22 =0x38
570 18:36:03.942612 Write Rank1 MR14 =0x5d
571 18:36:03.942675 Write Rank1 MR3 =0x30
572 18:36:03.942735 Write Rank1 MR13 =0x58
573 18:36:03.942796 Write Rank1 MR12 =0x5d
574 18:36:03.942855 Write Rank1 MR1 =0x56
575 18:36:03.942915 Write Rank1 MR2 =0x2d
576 18:36:03.942975 Write Rank1 MR11 =0x23
577 18:36:03.943035 Write Rank1 MR22 =0x34
578 18:36:03.943095 Write Rank1 MR14 =0x10
579 18:36:03.943155 Write Rank1 MR3 =0x30
580 18:36:03.943214 Write Rank1 MR13 =0xd8
581 18:36:03.943285 match AC timing 3
582 18:36:03.943349 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 18:36:03.943416 [MiockJmeterHQA]
584 18:36:03.943478 vSetVcoreByFreq with vcore:762500, freq=1600
585 18:36:03.943539
586 18:36:03.943600 MIOCK jitter meter ch=0
587 18:36:03.943661
588 18:36:03.943721 1T = (102-17) = 85 dly cells
589 18:36:03.943784 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
590 18:36:03.943845 vSetVcoreByFreq with vcore:725000, freq=1200
591 18:36:03.943906
592 18:36:03.943966 MIOCK jitter meter ch=0
593 18:36:03.944027
594 18:36:03.944086 1T = (97-17) = 80 dly cells
595 18:36:03.944148 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
596 18:36:03.944209 vSetVcoreByFreq with vcore:725000, freq=800
597 18:36:03.944269
598 18:36:03.944329 MIOCK jitter meter ch=0
599 18:36:03.944389
600 18:36:03.944448 1T = (97-17) = 80 dly cells
601 18:36:03.944509 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
602 18:36:03.944570 vSetVcoreByFreq with vcore:762500, freq=1600
603 18:36:03.944630 vSetVcoreByFreq with vcore:762500, freq=1600
604 18:36:03.944690
605 18:36:03.944751 K DRVP
606 18:36:03.944811 1. OCD DRVP=0 CALOUT=0
607 18:36:03.944872 1. OCD DRVP=1 CALOUT=0
608 18:36:03.944933 1. OCD DRVP=2 CALOUT=0
609 18:36:03.944996 1. OCD DRVP=3 CALOUT=0
610 18:36:03.945057 1. OCD DRVP=4 CALOUT=0
611 18:36:03.945119 1. OCD DRVP=5 CALOUT=0
612 18:36:03.945180 1. OCD DRVP=6 CALOUT=0
613 18:36:03.945242 1. OCD DRVP=7 CALOUT=0
614 18:36:03.945303 1. OCD DRVP=8 CALOUT=0
615 18:36:03.945364 1. OCD DRVP=9 CALOUT=1
616 18:36:03.945425
617 18:36:03.945486 1. OCD DRVP calibration OK! DRVP=9
618 18:36:03.945548
619 18:36:03.945608
620 18:36:03.945668
621 18:36:03.945728 K ODTN
622 18:36:03.945788 3. OCD ODTN=0 ,CALOUT=1
623 18:36:03.945852 3. OCD ODTN=1 ,CALOUT=1
624 18:36:03.945914 3. OCD ODTN=2 ,CALOUT=1
625 18:36:03.945975 3. OCD ODTN=3 ,CALOUT=1
626 18:36:03.946036 3. OCD ODTN=4 ,CALOUT=1
627 18:36:03.946098 3. OCD ODTN=5 ,CALOUT=1
628 18:36:03.946160 3. OCD ODTN=6 ,CALOUT=1
629 18:36:03.946221 3. OCD ODTN=7 ,CALOUT=0
630 18:36:03.946283
631 18:36:03.946342 3. OCD ODTN calibration OK! ODTN=7
632 18:36:03.946404
633 18:36:03.946464 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
634 18:36:03.946525 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
635 18:36:03.946586 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
636 18:36:03.946662
637 18:36:03.946723 K DRVP
638 18:36:03.946784 1. OCD DRVP=0 CALOUT=0
639 18:36:03.946846 1. OCD DRVP=1 CALOUT=0
640 18:36:03.946908 1. OCD DRVP=2 CALOUT=0
641 18:36:03.946970 1. OCD DRVP=3 CALOUT=0
642 18:36:03.947031 1. OCD DRVP=4 CALOUT=0
643 18:36:03.947093 1. OCD DRVP=5 CALOUT=0
644 18:36:03.947154 1. OCD DRVP=6 CALOUT=0
645 18:36:03.947216 1. OCD DRVP=7 CALOUT=0
646 18:36:03.947277 1. OCD DRVP=8 CALOUT=0
647 18:36:03.947338 1. OCD DRVP=9 CALOUT=0
648 18:36:03.947399 1. OCD DRVP=10 CALOUT=0
649 18:36:03.947469 1. OCD DRVP=11 CALOUT=1
650 18:36:03.947531
651 18:36:03.947591 1. OCD DRVP calibration OK! DRVP=11
652 18:36:03.947654
653 18:36:03.947714
654 18:36:03.947775
655 18:36:03.947835 K ODTN
656 18:36:03.947895 3. OCD ODTN=0 ,CALOUT=1
657 18:36:03.948149 3. OCD ODTN=1 ,CALOUT=1
658 18:36:03.948220 3. OCD ODTN=2 ,CALOUT=1
659 18:36:03.948283 3. OCD ODTN=3 ,CALOUT=1
660 18:36:03.948345 3. OCD ODTN=4 ,CALOUT=1
661 18:36:03.948407 3. OCD ODTN=5 ,CALOUT=1
662 18:36:03.948469 3. OCD ODTN=6 ,CALOUT=1
663 18:36:03.948531 3. OCD ODTN=7 ,CALOUT=1
664 18:36:03.948603 3. OCD ODTN=8 ,CALOUT=1
665 18:36:03.948677 3. OCD ODTN=9 ,CALOUT=1
666 18:36:03.948785 3. OCD ODTN=10 ,CALOUT=1
667 18:36:03.948853 3. OCD ODTN=11 ,CALOUT=1
668 18:36:03.948915 3. OCD ODTN=12 ,CALOUT=1
669 18:36:03.948978 3. OCD ODTN=13 ,CALOUT=1
670 18:36:03.949040 3. OCD ODTN=14 ,CALOUT=1
671 18:36:03.949102 3. OCD ODTN=15 ,CALOUT=0
672 18:36:03.949164
673 18:36:03.949225 3. OCD ODTN calibration OK! ODTN=15
674 18:36:03.949287
675 18:36:03.949347 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
676 18:36:03.949408 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
677 18:36:03.949469 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
678 18:36:03.949530
679 18:36:03.949591 [DramcInit]
680 18:36:03.949651 AutoRefreshCKEOff AutoREF OFF
681 18:36:03.949711 DDRPhyPLLSetting-CKEOFF
682 18:36:03.949771 DDRPhyPLLSetting-CKEON
683 18:36:03.949831
684 18:36:03.949891 Enable WDQS
685 18:36:03.949951 ==
686 18:36:03.950011 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 18:36:03.950072 fsp= 1, odt_onoff= 1, Byte mode= 0
688 18:36:03.950133 ==
689 18:36:03.950193 [Duty_Offset_Calibration]
690 18:36:03.950254
691 18:36:03.950314 ===========================
692 18:36:03.950374 B0:1 B1:1 CA:1
693 18:36:03.950434 ==
694 18:36:03.950494 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 18:36:03.950555 fsp= 1, odt_onoff= 1, Byte mode= 0
696 18:36:03.950616 ==
697 18:36:03.950675 [Duty_Offset_Calibration]
698 18:36:03.950736
699 18:36:03.950795 ===========================
700 18:36:03.950856 B0:1 B1:0 CA:2
701 18:36:03.950916 [ModeRegInit_LP4] CH0 RK0
702 18:36:03.950976 Write Rank0 MR13 =0x18
703 18:36:03.951036 Write Rank0 MR12 =0x5d
704 18:36:03.951096 Write Rank0 MR1 =0x56
705 18:36:03.951156 Write Rank0 MR2 =0x1a
706 18:36:03.951216 Write Rank0 MR11 =0x0
707 18:36:03.951276 Write Rank0 MR22 =0x38
708 18:36:03.951336 Write Rank0 MR14 =0x5d
709 18:36:03.951396 Write Rank0 MR3 =0x30
710 18:36:03.951464 Write Rank0 MR13 =0x58
711 18:36:03.951524 Write Rank0 MR12 =0x5d
712 18:36:03.951585 Write Rank0 MR1 =0x56
713 18:36:03.951644 Write Rank0 MR2 =0x2d
714 18:36:03.951704 Write Rank0 MR11 =0x23
715 18:36:03.951764 Write Rank0 MR22 =0x34
716 18:36:03.951824 Write Rank0 MR14 =0x10
717 18:36:03.951883 Write Rank0 MR3 =0x30
718 18:36:03.951943 Write Rank0 MR13 =0xd8
719 18:36:03.952003 [ModeRegInit_LP4] CH0 RK1
720 18:36:03.952063 Write Rank1 MR13 =0x18
721 18:36:03.952123 Write Rank1 MR12 =0x5d
722 18:36:03.952182 Write Rank1 MR1 =0x56
723 18:36:03.952242 Write Rank1 MR2 =0x1a
724 18:36:03.952301 Write Rank1 MR11 =0x0
725 18:36:03.952361 Write Rank1 MR22 =0x38
726 18:36:03.952421 Write Rank1 MR14 =0x5d
727 18:36:03.952481 Write Rank1 MR3 =0x30
728 18:36:03.952541 Write Rank1 MR13 =0x58
729 18:36:03.952601 Write Rank1 MR12 =0x5d
730 18:36:03.952661 Write Rank1 MR1 =0x56
731 18:36:03.952721 Write Rank1 MR2 =0x2d
732 18:36:03.952781 Write Rank1 MR11 =0x23
733 18:36:03.952841 Write Rank1 MR22 =0x34
734 18:36:03.952900 Write Rank1 MR14 =0x10
735 18:36:03.952960 Write Rank1 MR3 =0x30
736 18:36:03.953020 Write Rank1 MR13 =0xd8
737 18:36:03.953080 [ModeRegInit_LP4] CH1 RK0
738 18:36:03.953140 Write Rank0 MR13 =0x18
739 18:36:03.953199 Write Rank0 MR12 =0x5d
740 18:36:03.953259 Write Rank0 MR1 =0x56
741 18:36:03.953319 Write Rank0 MR2 =0x1a
742 18:36:03.953379 Write Rank0 MR11 =0x0
743 18:36:03.953439 Write Rank0 MR22 =0x38
744 18:36:03.953499 Write Rank0 MR14 =0x5d
745 18:36:03.953558 Write Rank0 MR3 =0x30
746 18:36:03.953618 Write Rank0 MR13 =0x58
747 18:36:03.953678 Write Rank0 MR12 =0x5d
748 18:36:03.953737 Write Rank0 MR1 =0x56
749 18:36:03.953797 Write Rank0 MR2 =0x2d
750 18:36:03.953857 Write Rank0 MR11 =0x23
751 18:36:03.953916 Write Rank0 MR22 =0x34
752 18:36:03.953976 Write Rank0 MR14 =0x10
753 18:36:03.954036 Write Rank0 MR3 =0x30
754 18:36:03.954096 Write Rank0 MR13 =0xd8
755 18:36:03.954156 [ModeRegInit_LP4] CH1 RK1
756 18:36:03.954215 Write Rank1 MR13 =0x18
757 18:36:03.954275 Write Rank1 MR12 =0x5d
758 18:36:03.954334 Write Rank1 MR1 =0x56
759 18:36:03.954394 Write Rank1 MR2 =0x1a
760 18:36:03.954453 Write Rank1 MR11 =0x0
761 18:36:03.954513 Write Rank1 MR22 =0x38
762 18:36:03.954575 Write Rank1 MR14 =0x5d
763 18:36:03.954635 Write Rank1 MR3 =0x30
764 18:36:03.954696 Write Rank1 MR13 =0x58
765 18:36:03.954756 Write Rank1 MR12 =0x5d
766 18:36:03.954815 Write Rank1 MR1 =0x56
767 18:36:03.954875 Write Rank1 MR2 =0x2d
768 18:36:03.954935 Write Rank1 MR11 =0x23
769 18:36:03.954995 Write Rank1 MR22 =0x34
770 18:36:03.955055 Write Rank1 MR14 =0x10
771 18:36:03.955114 Write Rank1 MR3 =0x30
772 18:36:03.955174 Write Rank1 MR13 =0xd8
773 18:36:03.955234 match AC timing 3
774 18:36:03.955294 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 18:36:03.955355 DramC Write-DBI off
776 18:36:03.955419 DramC Read-DBI off
777 18:36:03.955480 Write Rank0 MR13 =0x59
778 18:36:03.955540 ==
779 18:36:03.955600 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 18:36:03.955661 fsp= 1, odt_onoff= 1, Byte mode= 0
781 18:36:03.955722 ==
782 18:36:03.955782 === u2Vref_new: 0x56 --> 0x2d
783 18:36:03.955843 === u2Vref_new: 0x58 --> 0x38
784 18:36:03.955903 === u2Vref_new: 0x5a --> 0x39
785 18:36:03.955964 === u2Vref_new: 0x5c --> 0x3c
786 18:36:03.956024 === u2Vref_new: 0x5e --> 0x3d
787 18:36:03.956085 === u2Vref_new: 0x60 --> 0xa0
788 18:36:03.956145 [CA 0] Center 34 (6~63) winsize 58
789 18:36:03.956206 [CA 1] Center 36 (9~63) winsize 55
790 18:36:03.956266 [CA 2] Center 29 (0~58) winsize 59
791 18:36:03.956326 [CA 3] Center 24 (-3~52) winsize 56
792 18:36:03.956386 [CA 4] Center 25 (-3~54) winsize 58
793 18:36:03.956447 [CA 5] Center 29 (0~59) winsize 60
794 18:36:03.956507
795 18:36:03.956567 [CATrainingPosCal] consider 1 rank data
796 18:36:03.956627 u2DelayCellTimex100 = 735/100 ps
797 18:36:03.956687 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
798 18:36:03.956748 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
799 18:36:03.956808 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
800 18:36:03.956868 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
801 18:36:03.956929 CA4 delay=25 (-3~54),Diff = 1 PI (1 cell)
802 18:36:03.956989 CA5 delay=29 (0~59),Diff = 5 PI (6 cell)
803 18:36:03.957049
804 18:36:03.957109 CA PerBit enable=1, Macro0, CA PI delay=24
805 18:36:03.957169 === u2Vref_new: 0x5e --> 0x3d
806 18:36:03.957229
807 18:36:03.957289 Vref(ca) range 1: 30
808 18:36:03.957349
809 18:36:03.957409 CS Dly= 9 (40-0-32)
810 18:36:03.957469 Write Rank0 MR13 =0xd8
811 18:36:03.957529 Write Rank0 MR13 =0xd8
812 18:36:03.957589 Write Rank0 MR12 =0x5e
813 18:36:03.957648 Write Rank1 MR13 =0x59
814 18:36:03.957708 ==
815 18:36:03.957768 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 18:36:03.958045 fsp= 1, odt_onoff= 1, Byte mode= 0
817 18:36:03.958118 ==
818 18:36:03.958180 === u2Vref_new: 0x56 --> 0x2d
819 18:36:03.958242 === u2Vref_new: 0x58 --> 0x38
820 18:36:03.958303 === u2Vref_new: 0x5a --> 0x39
821 18:36:03.958363 === u2Vref_new: 0x5c --> 0x3c
822 18:36:03.958424 === u2Vref_new: 0x5e --> 0x3d
823 18:36:03.958485 === u2Vref_new: 0x60 --> 0xa0
824 18:36:03.958546 [CA 0] Center 36 (10~63) winsize 54
825 18:36:03.958606 [CA 1] Center 36 (9~63) winsize 55
826 18:36:03.958667 [CA 2] Center 31 (2~60) winsize 59
827 18:36:03.958728 [CA 3] Center 25 (-3~53) winsize 57
828 18:36:03.958789 [CA 4] Center 25 (-3~54) winsize 58
829 18:36:03.958848 [CA 5] Center 31 (2~61) winsize 60
830 18:36:03.958909
831 18:36:03.958969 [CATrainingPosCal] consider 2 rank data
832 18:36:03.959030 u2DelayCellTimex100 = 735/100 ps
833 18:36:03.959091 CA0 delay=36 (10~63),Diff = 12 PI (15 cell)
834 18:36:03.959152 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
835 18:36:03.959213 CA2 delay=30 (2~58),Diff = 6 PI (7 cell)
836 18:36:03.959273 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
837 18:36:03.959333 CA4 delay=25 (-3~54),Diff = 1 PI (1 cell)
838 18:36:03.959394 CA5 delay=30 (2~59),Diff = 6 PI (7 cell)
839 18:36:03.959462
840 18:36:03.959523 CA PerBit enable=1, Macro0, CA PI delay=24
841 18:36:03.959584 === u2Vref_new: 0x5a --> 0x39
842 18:36:03.959646
843 18:36:03.959706 Vref(ca) range 1: 26
844 18:36:03.959766
845 18:36:03.959826 CS Dly= 7 (38-0-32)
846 18:36:03.959886 Write Rank1 MR13 =0xd8
847 18:36:03.959947 Write Rank1 MR13 =0xd8
848 18:36:03.960007 Write Rank1 MR12 =0x5a
849 18:36:03.960067 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 18:36:03.960128 Write Rank0 MR2 =0xad
851 18:36:03.960188 [Write Leveling]
852 18:36:03.960248 delay byte0 byte1 byte2 byte3
853 18:36:03.960309
854 18:36:03.960369 10 0 0
855 18:36:03.960431 11 0 0
856 18:36:03.960493 12 0 0
857 18:36:03.960554 13 0 0
858 18:36:03.960615 14 0 0
859 18:36:03.960677 15 0 0
860 18:36:03.960739 16 0 0
861 18:36:03.960800 17 0 0
862 18:36:03.960861 18 0 0
863 18:36:03.960922 19 0 0
864 18:36:03.960983 20 0 0
865 18:36:03.961044 21 0 0
866 18:36:03.961105 22 0 0
867 18:36:03.961166 23 0 0
868 18:36:03.961227 24 0 ff
869 18:36:03.961288 25 0 ff
870 18:36:03.961349 26 0 ff
871 18:36:03.961410 27 0 ff
872 18:36:03.961472 28 0 ff
873 18:36:03.961533 29 0 ff
874 18:36:03.961593 30 0 ff
875 18:36:03.961655 31 0 ff
876 18:36:03.961715 32 0 ff
877 18:36:03.961776 33 ff ff
878 18:36:03.961838 34 ff ff
879 18:36:03.961899 35 ff ff
880 18:36:03.961960 36 ff ff
881 18:36:03.962022 37 ff ff
882 18:36:03.962082 38 ff ff
883 18:36:03.962144 39 ff ff
884 18:36:03.962206 pass bytecount = 0xff (0xff: all bytes pass)
885 18:36:03.962267
886 18:36:03.962328 DQS0 dly: 33
887 18:36:03.962388 DQS1 dly: 24
888 18:36:03.962449 Write Rank0 MR2 =0x2d
889 18:36:03.962509 [RankSwap] Rank num 2, (Multi 1), Rank 0
890 18:36:03.962570 Write Rank0 MR1 =0xd6
891 18:36:03.962631 [Gating]
892 18:36:03.962691 ==
893 18:36:03.962751 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
894 18:36:03.962813 fsp= 1, odt_onoff= 1, Byte mode= 0
895 18:36:03.962873 ==
896 18:36:03.962933 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
897 18:36:03.962995 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
898 18:36:03.963057 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
899 18:36:03.963118 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
900 18:36:03.963181 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
901 18:36:03.963242 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
902 18:36:03.963304 3 1 24 |909 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
903 18:36:03.963365 3 1 28 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
904 18:36:03.963434 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
905 18:36:03.963496 3 2 4 |3534 403 |(11 11)(11 11) |(0 0)(1 1)| 0
906 18:36:03.963558 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
907 18:36:03.963619 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
908 18:36:03.963680 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
909 18:36:03.963742 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
910 18:36:03.963804 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 18:36:03.963865 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 18:36:03.963931 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
913 18:36:03.963994 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
914 18:36:03.964055 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
915 18:36:03.964116 [Byte 1] Lead/lag falling Transition (3, 3, 8)
916 18:36:03.964177 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 18:36:03.964239 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
918 18:36:03.964300 3 3 20 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
919 18:36:03.964362 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
920 18:36:03.964423 3 3 28 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
921 18:36:03.964484 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
922 18:36:03.964545 3 4 4 |3d3d 707 |(11 11)(11 11) |(1 1)(1 1)| 0
923 18:36:03.964607 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 18:36:03.964668 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 18:36:03.964730 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 18:36:03.964791 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 18:36:03.964853 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 18:36:03.964914 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 18:36:03.964975 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 18:36:03.965036 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 18:36:03.965097 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 18:36:03.965159 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 18:36:03.965219 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
934 18:36:03.965280 [Byte 0] Lead/lag falling Transition (3, 5, 16)
935 18:36:03.965341 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
936 18:36:03.965402 [Byte 0] Lead/lag Transition tap number (2)
937 18:36:03.965463 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
938 18:36:03.965524 [Byte 1] Lead/lag falling Transition (3, 5, 24)
939 18:36:03.965585 3 5 28 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
940 18:36:03.965646 [Byte 0]First pass (3, 5, 28)
941 18:36:03.965903 [Byte 1] Lead/lag Transition tap number (2)
942 18:36:03.965972 3 6 0 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
943 18:36:03.966035 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
944 18:36:03.966098 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 18:36:03.966160 [Byte 1]First pass (3, 6, 8)
946 18:36:03.966220 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 18:36:03.966282 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 18:36:03.966343 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 18:36:03.966405 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 18:36:03.966466 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 18:36:03.966528 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 18:36:03.966589 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
953 18:36:03.966651 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
954 18:36:03.966712 All bytes gating window > 1UI, Early break!
955 18:36:03.966773
956 18:36:03.966833 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
957 18:36:03.966893
958 18:36:03.966953 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 28)
959 18:36:03.967013
960 18:36:03.967072
961 18:36:03.967131
962 18:36:03.967190 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
963 18:36:03.967250
964 18:36:03.967310 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
965 18:36:03.967370
966 18:36:03.967435
967 18:36:03.967495 Write Rank0 MR1 =0x56
968 18:36:03.967554
969 18:36:03.967614 best RODT dly(2T, 0.5T) = (2, 2)
970 18:36:03.967673
971 18:36:03.967732 best RODT dly(2T, 0.5T) = (2, 2)
972 18:36:03.967792 ==
973 18:36:03.967851 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
974 18:36:03.967912 fsp= 1, odt_onoff= 1, Byte mode= 0
975 18:36:03.967972 ==
976 18:36:03.968032 Start DQ dly to find pass range UseTestEngine =0
977 18:36:03.968093 x-axis: bit #, y-axis: DQ dly (-127~63)
978 18:36:03.968153 RX Vref Scan = 0
979 18:36:03.968213 -26, [0] xxxxxxxx xxxxxxxx [MSB]
980 18:36:03.968275 -25, [0] xxxxxxxx xxxxxxxx [MSB]
981 18:36:03.968337 -24, [0] xxxxxxxx xxxxxxxx [MSB]
982 18:36:03.968398 -23, [0] xxxxxxxx xxxxxxxx [MSB]
983 18:36:03.968459 -22, [0] xxxxxxxx xxxxxxxx [MSB]
984 18:36:03.968521 -21, [0] xxxxxxxx xxxxxxxx [MSB]
985 18:36:03.968582 -20, [0] xxxxxxxx xxxxxxxx [MSB]
986 18:36:03.968643 -19, [0] xxxxxxxx xxxxxxxx [MSB]
987 18:36:03.968704 -18, [0] xxxxxxxx xxxxxxxx [MSB]
988 18:36:03.968764 -17, [0] xxxxxxxx xxxxxxxx [MSB]
989 18:36:03.968825 -16, [0] xxxxxxxx xxxxxxxx [MSB]
990 18:36:03.968885 -15, [0] xxxxxxxx xxxxxxxx [MSB]
991 18:36:03.968946 -14, [0] xxxxxxxx xxxxxxxx [MSB]
992 18:36:03.969006 -13, [0] xxxxxxxx xxxxxxxx [MSB]
993 18:36:03.969068 -12, [0] xxxxxxxx xxxxxxxx [MSB]
994 18:36:03.969128 -11, [0] xxxxxxxx xxxxxxxx [MSB]
995 18:36:03.969189 -10, [0] xxxxxxxx xxxxxxxx [MSB]
996 18:36:03.969250 -9, [0] xxxxxxxx xxxxxxxx [MSB]
997 18:36:03.969311 -8, [0] xxxxxxxx xxxxxxxx [MSB]
998 18:36:03.969372 -7, [0] xxxxxxxx xxxxxxxx [MSB]
999 18:36:03.969432 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1000 18:36:03.969494 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1001 18:36:03.969555 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1002 18:36:03.969616 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1003 18:36:03.969676 -2, [0] xxxoxxxx oxxxxxxx [MSB]
1004 18:36:03.969737 -1, [0] xxxoxxxx ooxoxxxx [MSB]
1005 18:36:03.969798 0, [0] xxxoxoxx ooxoxxxx [MSB]
1006 18:36:03.969859 1, [0] xxxoxoox ooxoooxx [MSB]
1007 18:36:03.969920 2, [0] xxxoxoox ooxoooxx [MSB]
1008 18:36:03.969981 3, [0] xxxoxooo ooxoooox [MSB]
1009 18:36:03.970042 4, [0] xxxoxoox ooxoooox [MSB]
1010 18:36:03.970103 5, [0] xooooooo ooxooooo [MSB]
1011 18:36:03.970164 6, [0] oooooooo ooxooooo [MSB]
1012 18:36:03.970227 7, [0] oooooooo ooxooooo [MSB]
1013 18:36:03.970288 32, [0] oooxoooo oooooooo [MSB]
1014 18:36:03.970350 33, [0] oooxoooo xooooooo [MSB]
1015 18:36:03.970410 34, [0] oooxoooo xooooooo [MSB]
1016 18:36:03.970471 35, [0] oooxoooo xooooooo [MSB]
1017 18:36:03.970531 36, [0] oooxoxox xooxoooo [MSB]
1018 18:36:03.970592 37, [0] oooxoxxx xxoxxooo [MSB]
1019 18:36:03.970652 38, [0] oooxoxxx xxoxxoxo [MSB]
1020 18:36:03.970712 39, [0] oooxxxxx xxoxxxxo [MSB]
1021 18:36:03.970773 40, [0] xxoxxxxx xxoxxxxo [MSB]
1022 18:36:03.970834 41, [0] xxxxxxxx xxoxxxxo [MSB]
1023 18:36:03.970895 42, [0] xxxxxxxx xxoxxxxx [MSB]
1024 18:36:03.970955 43, [0] xxxxxxxx xxoxxxxx [MSB]
1025 18:36:03.971024 44, [0] xxxxxxxx xxxxxxxx [MSB]
1026 18:36:03.971088 iDelay=44, Bit 0, Center 22 (6 ~ 39) 34
1027 18:36:03.971148 iDelay=44, Bit 1, Center 22 (5 ~ 39) 35
1028 18:36:03.971208 iDelay=44, Bit 2, Center 22 (5 ~ 40) 36
1029 18:36:03.971268 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
1030 18:36:03.971327 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
1031 18:36:03.971386 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
1032 18:36:03.971449 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
1033 18:36:03.971507 iDelay=44, Bit 7, Center 20 (5 ~ 35) 31
1034 18:36:03.971567 iDelay=44, Bit 8, Center 14 (-3 ~ 32) 36
1035 18:36:03.971625 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
1036 18:36:03.971684 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
1037 18:36:03.971743 iDelay=44, Bit 11, Center 17 (-1 ~ 35) 37
1038 18:36:03.971802 iDelay=44, Bit 12, Center 18 (1 ~ 36) 36
1039 18:36:03.971861 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
1040 18:36:03.971920 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
1041 18:36:03.971979 iDelay=44, Bit 15, Center 23 (5 ~ 41) 37
1042 18:36:03.972038 ==
1043 18:36:03.972097 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1044 18:36:03.972157 fsp= 1, odt_onoff= 1, Byte mode= 0
1045 18:36:03.972216 ==
1046 18:36:03.972275 DQS Delay:
1047 18:36:03.972333 DQS0 = 0, DQS1 = 0
1048 18:36:03.972391 DQM Delay:
1049 18:36:03.972450 DQM0 = 19, DQM1 = 19
1050 18:36:03.972508 DQ Delay:
1051 18:36:03.972567 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1052 18:36:03.972625 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
1053 18:36:03.972686 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =17
1054 18:36:03.972745 DQ12 =18, DQ13 =19, DQ14 =20, DQ15 =23
1055 18:36:03.972803
1056 18:36:03.972861
1057 18:36:03.972919 DramC Write-DBI off
1058 18:36:03.972977 ==
1059 18:36:03.973036 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1060 18:36:03.973096 fsp= 1, odt_onoff= 1, Byte mode= 0
1061 18:36:03.973154 ==
1062 18:36:03.973213 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1063 18:36:03.973272
1064 18:36:03.973331 Begin, DQ Scan Range 920~1176
1065 18:36:03.973390
1066 18:36:03.973447
1067 18:36:03.973506 TX Vref Scan disable
1068 18:36:03.973564 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1069 18:36:03.973625 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1070 18:36:03.973684 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1071 18:36:03.973745 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1072 18:36:03.974006 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1073 18:36:03.974074 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1074 18:36:03.974136 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1075 18:36:03.974198 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1076 18:36:03.974258 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1077 18:36:03.974318 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1078 18:36:03.974378 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1079 18:36:03.974438 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1080 18:36:03.974498 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1081 18:36:03.974558 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1082 18:36:03.974618 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1083 18:36:03.974678 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1084 18:36:03.974738 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1085 18:36:03.974798 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1086 18:36:03.974858 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1087 18:36:03.974919 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1088 18:36:03.974979 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1089 18:36:03.975040 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1090 18:36:03.975099 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1091 18:36:03.975160 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1092 18:36:03.975220 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1093 18:36:03.975280 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1094 18:36:03.975340 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1095 18:36:03.975399 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1096 18:36:03.975466 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1097 18:36:03.975527 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1098 18:36:03.975587 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1099 18:36:03.975647 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1100 18:36:03.975707 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1101 18:36:03.975767 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1102 18:36:03.975826 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1103 18:36:03.975886 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1104 18:36:03.975946 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1105 18:36:03.976006 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1106 18:36:03.976066 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1107 18:36:03.976126 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1108 18:36:03.976186 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1109 18:36:03.976246 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1110 18:36:03.976306 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1111 18:36:03.976366 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1112 18:36:03.976427 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1113 18:36:03.976487 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1114 18:36:03.976547 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1115 18:36:03.976607 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1116 18:36:03.976668 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1117 18:36:03.976728 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1118 18:36:03.976788 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1119 18:36:03.976848 971 |3 6 11|[0] xxxxxxxx oooooooo [MSB]
1120 18:36:03.976909 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1121 18:36:03.976969 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1122 18:36:03.977028 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1123 18:36:03.977088 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1124 18:36:03.977148 976 |3 6 16|[0] xxxoxoox oooooooo [MSB]
1125 18:36:03.977208 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1126 18:36:03.977268 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1127 18:36:03.977328 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1128 18:36:03.977388 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1129 18:36:03.977448 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1130 18:36:03.977507 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1131 18:36:03.977567 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1132 18:36:03.977627 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1133 18:36:03.977687 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1134 18:36:03.977747 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1135 18:36:03.977808 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1136 18:36:03.977868 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1137 18:36:03.977929 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1138 18:36:03.977989 998 |3 6 38|[0] oooxxxxx xxxxxxxx [MSB]
1139 18:36:03.978049 999 |3 6 39|[0] xxoxxxxx xxxxxxxx [MSB]
1140 18:36:03.978108 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1141 18:36:03.978168 Byte0, DQ PI dly=986, DQM PI dly= 986
1142 18:36:03.978227 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1143 18:36:03.978287
1144 18:36:03.978345 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1145 18:36:03.978405
1146 18:36:03.978463 Byte1, DQ PI dly=977, DQM PI dly= 977
1147 18:36:03.978521 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1148 18:36:03.978585
1149 18:36:03.978644 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1150 18:36:03.978704
1151 18:36:03.978762 ==
1152 18:36:03.978821 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1153 18:36:03.978880 fsp= 1, odt_onoff= 1, Byte mode= 0
1154 18:36:03.978939 ==
1155 18:36:03.978998 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1156 18:36:03.979057
1157 18:36:03.979116 Begin, DQ Scan Range 953~1017
1158 18:36:03.979175 Write Rank0 MR14 =0x0
1159 18:36:03.979234
1160 18:36:03.979292 CH=0, VrefRange= 0, VrefLevel = 0
1161 18:36:03.979351 TX Bit0 (980~994) 15 987, Bit8 (968~978) 11 973,
1162 18:36:03.979418 TX Bit1 (978~993) 16 985, Bit9 (969~983) 15 976,
1163 18:36:03.979480 TX Bit2 (980~994) 15 987, Bit10 (975~987) 13 981,
1164 18:36:03.979539 TX Bit3 (976~987) 12 981, Bit11 (968~982) 15 975,
1165 18:36:03.979598 TX Bit4 (978~992) 15 985, Bit12 (970~983) 14 976,
1166 18:36:03.979657 TX Bit5 (977~991) 15 984, Bit13 (970~984) 15 977,
1167 18:36:03.979717 TX Bit6 (978~991) 14 984, Bit14 (969~984) 16 976,
1168 18:36:03.979776 TX Bit7 (979~992) 14 985, Bit15 (975~986) 12 980,
1169 18:36:03.979835
1170 18:36:03.979894 wait MRW command Rank0 MR14 =0x2 fired (1)
1171 18:36:03.979953 Write Rank0 MR14 =0x2
1172 18:36:03.980012
1173 18:36:03.980070 CH=0, VrefRange= 0, VrefLevel = 2
1174 18:36:03.980128 TX Bit0 (979~994) 16 986, Bit8 (967~979) 13 973,
1175 18:36:03.980188 TX Bit1 (978~994) 17 986, Bit9 (969~984) 16 976,
1176 18:36:03.980246 TX Bit2 (979~994) 16 986, Bit10 (975~988) 14 981,
1177 18:36:03.980305 TX Bit3 (975~988) 14 981, Bit11 (968~982) 15 975,
1178 18:36:03.980564 TX Bit4 (978~993) 16 985, Bit12 (970~984) 15 977,
1179 18:36:03.980635 TX Bit5 (977~992) 16 984, Bit13 (969~984) 16 976,
1180 18:36:03.980695 TX Bit6 (977~992) 16 984, Bit14 (969~985) 17 977,
1181 18:36:03.980756 TX Bit7 (978~993) 16 985, Bit15 (974~986) 13 980,
1182 18:36:03.980815
1183 18:36:03.980874 wait MRW command Rank0 MR14 =0x4 fired (1)
1184 18:36:03.980934 Write Rank0 MR14 =0x4
1185 18:36:03.980996
1186 18:36:03.981055 CH=0, VrefRange= 0, VrefLevel = 4
1187 18:36:03.981114 TX Bit0 (979~996) 18 987, Bit8 (967~981) 15 974,
1188 18:36:03.981174 TX Bit1 (978~994) 17 986, Bit9 (969~984) 16 976,
1189 18:36:03.981233 TX Bit2 (979~996) 18 987, Bit10 (974~989) 16 981,
1190 18:36:03.981293 TX Bit3 (975~989) 15 982, Bit11 (968~983) 16 975,
1191 18:36:03.981352 TX Bit4 (978~993) 16 985, Bit12 (970~984) 15 977,
1192 18:36:03.981411 TX Bit5 (976~992) 17 984, Bit13 (969~984) 16 976,
1193 18:36:03.981471 TX Bit6 (977~992) 16 984, Bit14 (969~985) 17 977,
1194 18:36:03.981530 TX Bit7 (978~993) 16 985, Bit15 (974~988) 15 981,
1195 18:36:03.981590
1196 18:36:03.981648 Write Rank0 MR14 =0x6
1197 18:36:03.981707
1198 18:36:03.981765 CH=0, VrefRange= 0, VrefLevel = 6
1199 18:36:03.981824 TX Bit0 (978~996) 19 987, Bit8 (967~982) 16 974,
1200 18:36:03.981884 TX Bit1 (978~995) 18 986, Bit9 (968~985) 18 976,
1201 18:36:03.981943 TX Bit2 (978~996) 19 987, Bit10 (974~990) 17 982,
1202 18:36:03.982003 TX Bit3 (975~990) 16 982, Bit11 (968~983) 16 975,
1203 18:36:03.982062 TX Bit4 (978~993) 16 985, Bit12 (969~985) 17 977,
1204 18:36:03.982121 TX Bit5 (976~993) 18 984, Bit13 (969~985) 17 977,
1205 18:36:03.982181 TX Bit6 (977~993) 17 985, Bit14 (969~986) 18 977,
1206 18:36:03.982239 TX Bit7 (978~994) 17 986, Bit15 (974~989) 16 981,
1207 18:36:03.982299
1208 18:36:03.982357 Write Rank0 MR14 =0x8
1209 18:36:03.982415
1210 18:36:03.982473 CH=0, VrefRange= 0, VrefLevel = 8
1211 18:36:03.982532 TX Bit0 (978~998) 21 988, Bit8 (967~982) 16 974,
1212 18:36:03.982591 TX Bit1 (977~995) 19 986, Bit9 (968~985) 18 976,
1213 18:36:03.982650 TX Bit2 (978~998) 21 988, Bit10 (974~990) 17 982,
1214 18:36:03.982709 TX Bit3 (975~991) 17 983, Bit11 (967~984) 18 975,
1215 18:36:03.982768 TX Bit4 (977~995) 19 986, Bit12 (969~985) 17 977,
1216 18:36:03.982835 TX Bit5 (976~993) 18 984, Bit13 (969~985) 17 977,
1217 18:36:03.982899 TX Bit6 (977~993) 17 985, Bit14 (969~987) 19 978,
1218 18:36:03.982958 TX Bit7 (977~994) 18 985, Bit15 (973~990) 18 981,
1219 18:36:03.983018
1220 18:36:03.983076 Write Rank0 MR14 =0xa
1221 18:36:03.983135
1222 18:36:03.983193 CH=0, VrefRange= 0, VrefLevel = 10
1223 18:36:03.983252 TX Bit0 (978~998) 21 988, Bit8 (966~983) 18 974,
1224 18:36:03.983312 TX Bit1 (978~996) 19 987, Bit9 (968~985) 18 976,
1225 18:36:03.983371 TX Bit2 (978~997) 20 987, Bit10 (974~990) 17 982,
1226 18:36:03.983444 TX Bit3 (974~991) 18 982, Bit11 (967~984) 18 975,
1227 18:36:03.983505 TX Bit4 (977~995) 19 986, Bit12 (969~985) 17 977,
1228 18:36:03.983564 TX Bit5 (975~994) 20 984, Bit13 (969~986) 18 977,
1229 18:36:03.983624 TX Bit6 (977~994) 18 985, Bit14 (968~987) 20 977,
1230 18:36:03.983684 TX Bit7 (978~995) 18 986, Bit15 (973~990) 18 981,
1231 18:36:03.983743
1232 18:36:03.983802 Write Rank0 MR14 =0xc
1233 18:36:03.983862
1234 18:36:03.983921 CH=0, VrefRange= 0, VrefLevel = 12
1235 18:36:03.983980 TX Bit0 (978~998) 21 988, Bit8 (966~983) 18 974,
1236 18:36:03.984040 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
1237 18:36:03.984100 TX Bit2 (978~998) 21 988, Bit10 (973~991) 19 982,
1238 18:36:03.984159 TX Bit3 (974~992) 19 983, Bit11 (967~985) 19 976,
1239 18:36:03.984218 TX Bit4 (977~996) 20 986, Bit12 (969~986) 18 977,
1240 18:36:03.984278 TX Bit5 (975~994) 20 984, Bit13 (969~987) 19 978,
1241 18:36:03.984337 TX Bit6 (976~994) 19 985, Bit14 (968~988) 21 978,
1242 18:36:03.984397 TX Bit7 (977~995) 19 986, Bit15 (973~990) 18 981,
1243 18:36:03.984455
1244 18:36:03.984514 Write Rank0 MR14 =0xe
1245 18:36:03.984572
1246 18:36:03.984630 CH=0, VrefRange= 0, VrefLevel = 14
1247 18:36:03.984689 TX Bit0 (977~999) 23 988, Bit8 (966~984) 19 975,
1248 18:36:03.984748 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
1249 18:36:03.984807 TX Bit2 (977~998) 22 987, Bit10 (972~991) 20 981,
1250 18:36:03.984866 TX Bit3 (973~992) 20 982, Bit11 (967~985) 19 976,
1251 18:36:03.984925 TX Bit4 (977~997) 21 987, Bit12 (969~987) 19 978,
1252 18:36:03.984984 TX Bit5 (975~994) 20 984, Bit13 (968~987) 20 977,
1253 18:36:03.985044 TX Bit6 (976~995) 20 985, Bit14 (968~989) 22 978,
1254 18:36:03.985103 TX Bit7 (977~996) 20 986, Bit15 (971~990) 20 980,
1255 18:36:03.985162
1256 18:36:03.985221 Write Rank0 MR14 =0x10
1257 18:36:03.985279
1258 18:36:03.985338 CH=0, VrefRange= 0, VrefLevel = 16
1259 18:36:03.985397 TX Bit0 (978~999) 22 988, Bit8 (966~984) 19 975,
1260 18:36:03.985456 TX Bit1 (977~999) 23 988, Bit9 (967~987) 21 977,
1261 18:36:03.985516 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
1262 18:36:03.985575 TX Bit3 (973~992) 20 982, Bit11 (967~986) 20 976,
1263 18:36:03.985635 TX Bit4 (977~998) 22 987, Bit12 (969~987) 19 978,
1264 18:36:03.985694 TX Bit5 (975~995) 21 985, Bit13 (968~988) 21 978,
1265 18:36:03.985753 TX Bit6 (976~995) 20 985, Bit14 (968~990) 23 979,
1266 18:36:03.985813 TX Bit7 (977~996) 20 986, Bit15 (971~991) 21 981,
1267 18:36:03.985873
1268 18:36:03.985931 Write Rank0 MR14 =0x12
1269 18:36:03.985990
1270 18:36:03.986049 CH=0, VrefRange= 0, VrefLevel = 18
1271 18:36:03.986107 TX Bit0 (977~999) 23 988, Bit8 (965~985) 21 975,
1272 18:36:03.986167 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
1273 18:36:03.986226 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
1274 18:36:03.986289 TX Bit3 (973~993) 21 983, Bit11 (966~987) 22 976,
1275 18:36:03.986359 TX Bit4 (976~998) 23 987, Bit12 (968~989) 22 978,
1276 18:36:03.986419 TX Bit5 (974~995) 22 984, Bit13 (968~989) 22 978,
1277 18:36:03.986479 TX Bit6 (976~996) 21 986, Bit14 (968~990) 23 979,
1278 18:36:03.986733 TX Bit7 (977~998) 22 987, Bit15 (970~991) 22 980,
1279 18:36:03.986801
1280 18:36:03.986861 Write Rank0 MR14 =0x14
1281 18:36:03.986921
1282 18:36:03.986980 CH=0, VrefRange= 0, VrefLevel = 20
1283 18:36:03.987040 TX Bit0 (977~1000) 24 988, Bit8 (965~985) 21 975,
1284 18:36:03.987101 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
1285 18:36:03.987160 TX Bit2 (977~1000) 24 988, Bit10 (971~992) 22 981,
1286 18:36:03.987220 TX Bit3 (972~993) 22 982, Bit11 (966~987) 22 976,
1287 18:36:03.987279 TX Bit4 (976~999) 24 987, Bit12 (968~989) 22 978,
1288 18:36:03.987339 TX Bit5 (974~996) 23 985, Bit13 (968~989) 22 978,
1289 18:36:03.987398 TX Bit6 (976~997) 22 986, Bit14 (967~990) 24 978,
1290 18:36:03.987465 TX Bit7 (977~999) 23 988, Bit15 (970~992) 23 981,
1291 18:36:03.987525
1292 18:36:03.987584 Write Rank0 MR14 =0x16
1293 18:36:03.987642
1294 18:36:03.987701 CH=0, VrefRange= 0, VrefLevel = 22
1295 18:36:03.987759 TX Bit0 (977~1000) 24 988, Bit8 (965~986) 22 975,
1296 18:36:03.987819 TX Bit1 (976~999) 24 987, Bit9 (967~990) 24 978,
1297 18:36:03.987879 TX Bit2 (977~999) 23 988, Bit10 (970~993) 24 981,
1298 18:36:03.987938 TX Bit3 (971~994) 24 982, Bit11 (966~988) 23 977,
1299 18:36:03.987998 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1300 18:36:03.988058 TX Bit5 (974~997) 24 985, Bit13 (967~990) 24 978,
1301 18:36:03.988117 TX Bit6 (975~998) 24 986, Bit14 (967~990) 24 978,
1302 18:36:03.988177 TX Bit7 (977~999) 23 988, Bit15 (970~992) 23 981,
1303 18:36:03.988236
1304 18:36:03.988294 Write Rank0 MR14 =0x18
1305 18:36:03.988353
1306 18:36:03.988411 CH=0, VrefRange= 0, VrefLevel = 24
1307 18:36:03.988471 TX Bit0 (977~1000) 24 988, Bit8 (964~986) 23 975,
1308 18:36:03.988531 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1309 18:36:03.988591 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
1310 18:36:03.988650 TX Bit3 (971~994) 24 982, Bit11 (966~989) 24 977,
1311 18:36:03.988710 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1312 18:36:03.988769 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1313 18:36:03.988828 TX Bit6 (975~998) 24 986, Bit14 (967~991) 25 979,
1314 18:36:03.988887 TX Bit7 (976~999) 24 987, Bit15 (969~992) 24 980,
1315 18:36:03.988946
1316 18:36:03.989005 Write Rank0 MR14 =0x1a
1317 18:36:03.989064
1318 18:36:03.989122 CH=0, VrefRange= 0, VrefLevel = 26
1319 18:36:03.989181 TX Bit0 (977~1001) 25 989, Bit8 (964~986) 23 975,
1320 18:36:03.989240 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1321 18:36:03.989299 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
1322 18:36:03.989358 TX Bit3 (971~994) 24 982, Bit11 (965~989) 25 977,
1323 18:36:03.989417 TX Bit4 (976~1000) 25 988, Bit12 (968~990) 23 979,
1324 18:36:03.989476 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1325 18:36:03.989536 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1326 18:36:03.989594 TX Bit7 (976~1000) 25 988, Bit15 (969~992) 24 980,
1327 18:36:03.989653
1328 18:36:03.989711 Write Rank0 MR14 =0x1c
1329 18:36:03.989769
1330 18:36:03.989827 CH=0, VrefRange= 0, VrefLevel = 28
1331 18:36:03.989886 TX Bit0 (976~1001) 26 988, Bit8 (963~987) 25 975,
1332 18:36:03.989946 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1333 18:36:03.990005 TX Bit2 (976~1001) 26 988, Bit10 (969~994) 26 981,
1334 18:36:03.990064 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1335 18:36:03.990123 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1336 18:36:03.990182 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1337 18:36:03.990242 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1338 18:36:03.990301 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1339 18:36:03.990360
1340 18:36:03.990419 Write Rank0 MR14 =0x1e
1341 18:36:03.990478
1342 18:36:03.990537 CH=0, VrefRange= 0, VrefLevel = 30
1343 18:36:03.990596 TX Bit0 (976~1001) 26 988, Bit8 (963~987) 25 975,
1344 18:36:03.990655 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1345 18:36:03.990714 TX Bit2 (976~1001) 26 988, Bit10 (969~994) 26 981,
1346 18:36:03.990773 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1347 18:36:03.990833 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1348 18:36:03.990892 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1349 18:36:03.990952 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1350 18:36:03.991011 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1351 18:36:03.991070
1352 18:36:03.991129 Write Rank0 MR14 =0x20
1353 18:36:03.991187
1354 18:36:03.991245 CH=0, VrefRange= 0, VrefLevel = 32
1355 18:36:03.991304 TX Bit0 (976~1001) 26 988, Bit8 (963~987) 25 975,
1356 18:36:03.991364 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1357 18:36:03.991428 TX Bit2 (976~1001) 26 988, Bit10 (969~994) 26 981,
1358 18:36:03.991488 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1359 18:36:03.991547 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1360 18:36:03.991607 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1361 18:36:03.991666 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1362 18:36:03.991724 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1363 18:36:03.991783
1364 18:36:03.991841 Write Rank0 MR14 =0x22
1365 18:36:03.991899
1366 18:36:03.991956 CH=0, VrefRange= 0, VrefLevel = 34
1367 18:36:03.992015 TX Bit0 (976~1001) 26 988, Bit8 (963~987) 25 975,
1368 18:36:03.992074 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1369 18:36:03.992133 TX Bit2 (976~1001) 26 988, Bit10 (969~994) 26 981,
1370 18:36:03.992191 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1371 18:36:03.992250 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1372 18:36:03.992309 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1373 18:36:03.992367 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1374 18:36:03.992426 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1375 18:36:03.992485
1376 18:36:03.992543 Write Rank0 MR14 =0x24
1377 18:36:03.992620
1378 18:36:03.992678 CH=0, VrefRange= 0, VrefLevel = 36
1379 18:36:03.992737 TX Bit0 (976~1001) 26 988, Bit8 (963~987) 25 975,
1380 18:36:03.992989 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1381 18:36:03.993056 TX Bit2 (976~1001) 26 988, Bit10 (969~994) 26 981,
1382 18:36:03.993116 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1383 18:36:03.993176 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1384 18:36:03.993235 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1385 18:36:03.993294 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1386 18:36:03.993353 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1387 18:36:03.993412
1388 18:36:03.993470
1389 18:36:03.993528 TX Vref found, early break! 376< 382
1390 18:36:03.993591 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1391 18:36:03.993651 u1DelayCellOfst[0]=7 cells (6 PI)
1392 18:36:03.993710 u1DelayCellOfst[1]=7 cells (6 PI)
1393 18:36:03.993769 u1DelayCellOfst[2]=7 cells (6 PI)
1394 18:36:03.993827 u1DelayCellOfst[3]=0 cells (0 PI)
1395 18:36:03.993885 u1DelayCellOfst[4]=7 cells (6 PI)
1396 18:36:03.993943 u1DelayCellOfst[5]=3 cells (3 PI)
1397 18:36:03.994002 u1DelayCellOfst[6]=6 cells (5 PI)
1398 18:36:03.994062 u1DelayCellOfst[7]=7 cells (6 PI)
1399 18:36:03.994121 Byte0, DQ PI dly=982, DQM PI dly= 985
1400 18:36:03.994180 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1401 18:36:03.994240
1402 18:36:03.994298 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1403 18:36:03.994357
1404 18:36:03.994415 u1DelayCellOfst[8]=0 cells (0 PI)
1405 18:36:03.994472 u1DelayCellOfst[9]=3 cells (3 PI)
1406 18:36:03.994530 u1DelayCellOfst[10]=7 cells (6 PI)
1407 18:36:03.994589 u1DelayCellOfst[11]=2 cells (2 PI)
1408 18:36:03.994646 u1DelayCellOfst[12]=5 cells (4 PI)
1409 18:36:03.994704 u1DelayCellOfst[13]=3 cells (3 PI)
1410 18:36:03.994762 u1DelayCellOfst[14]=5 cells (4 PI)
1411 18:36:03.994821 u1DelayCellOfst[15]=7 cells (6 PI)
1412 18:36:03.994879 Byte1, DQ PI dly=975, DQM PI dly= 978
1413 18:36:03.994937 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1414 18:36:03.994997
1415 18:36:03.995055 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1416 18:36:03.995114
1417 18:36:03.995171 Write Rank0 MR14 =0x1c
1418 18:36:03.995230
1419 18:36:03.995288 Final TX Range 0 Vref 28
1420 18:36:03.995347
1421 18:36:03.995413 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1422 18:36:03.995477
1423 18:36:03.995536 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1424 18:36:03.995596 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1425 18:36:03.995655 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1426 18:36:03.995714 Write Rank0 MR3 =0xb0
1427 18:36:03.995773 DramC Write-DBI on
1428 18:36:03.995830 ==
1429 18:36:03.995889 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1430 18:36:03.995947 fsp= 1, odt_onoff= 1, Byte mode= 0
1431 18:36:03.996006 ==
1432 18:36:03.996065 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1433 18:36:03.996124
1434 18:36:03.996182 Begin, DQ Scan Range 698~762
1435 18:36:03.996240
1436 18:36:03.996298
1437 18:36:03.996356 TX Vref Scan disable
1438 18:36:03.996415 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1439 18:36:03.996476 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1440 18:36:03.996536 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1441 18:36:03.996596 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1442 18:36:03.996656 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1443 18:36:03.996715 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1444 18:36:03.996775 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1445 18:36:03.996835 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1446 18:36:03.996894 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1447 18:36:03.996954 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1448 18:36:03.997014 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1449 18:36:03.997074 709 |2 6 5|[0] xxxxxxxx oooooooo [MSB]
1450 18:36:03.997133 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1451 18:36:03.997193 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1452 18:36:03.997252 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1453 18:36:03.997312 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1454 18:36:03.997371 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1455 18:36:03.997430 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1456 18:36:03.997489 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1457 18:36:03.997548 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1458 18:36:03.997607 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1459 18:36:03.997667 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1460 18:36:03.997726 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1461 18:36:03.997785 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1462 18:36:03.997844 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1463 18:36:03.997903 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1464 18:36:03.997962 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1465 18:36:03.998021 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1466 18:36:03.998081 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1467 18:36:03.998140 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1468 18:36:03.998200 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1469 18:36:03.998259 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1470 18:36:03.998318 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1471 18:36:03.998378 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1472 18:36:03.998437 Byte0, DQ PI dly=732, DQM PI dly= 732
1473 18:36:03.998496 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1474 18:36:03.998555
1475 18:36:03.998651 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1476 18:36:03.998741
1477 18:36:03.998802 Byte1, DQ PI dly=721, DQM PI dly= 721
1478 18:36:03.998862 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
1479 18:36:03.998922
1480 18:36:03.998980 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
1481 18:36:03.999039
1482 18:36:03.999097 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1483 18:36:03.999157 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1484 18:36:03.999216 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1485 18:36:03.999275 Write Rank0 MR3 =0x30
1486 18:36:03.999333 DramC Write-DBI off
1487 18:36:03.999391
1488 18:36:03.999455 [DATLAT]
1489 18:36:03.999514 Freq=1600, CH0 RK0, use_rxtx_scan=0
1490 18:36:03.999573
1491 18:36:03.999631 DATLAT Default: 0xf
1492 18:36:03.999690 7, 0xFFFF, sum=0
1493 18:36:03.999749 8, 0xFFFF, sum=0
1494 18:36:03.999809 9, 0xFFFF, sum=0
1495 18:36:03.999868 10, 0xFFFF, sum=0
1496 18:36:03.999927 11, 0xFFFF, sum=0
1497 18:36:03.999986 12, 0xFFFF, sum=0
1498 18:36:04.000045 13, 0xFFFF, sum=0
1499 18:36:04.000311 14, 0x0, sum=1
1500 18:36:04.000382 15, 0x0, sum=2
1501 18:36:04.000444 16, 0x0, sum=3
1502 18:36:04.000504 17, 0x0, sum=4
1503 18:36:04.000564 pattern=2 first_step=14 total pass=5 best_step=16
1504 18:36:04.000623 ==
1505 18:36:04.000682 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1506 18:36:04.000741 fsp= 1, odt_onoff= 1, Byte mode= 0
1507 18:36:04.000801 ==
1508 18:36:04.000859 Start DQ dly to find pass range UseTestEngine =1
1509 18:36:04.000918 x-axis: bit #, y-axis: DQ dly (-127~63)
1510 18:36:04.000977 RX Vref Scan = 1
1511 18:36:04.001036
1512 18:36:04.001093 RX Vref found, early break!
1513 18:36:04.001152
1514 18:36:04.001210 Final RX Vref 12, apply to both rank0 and 1
1515 18:36:04.001269 ==
1516 18:36:04.001328 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1517 18:36:04.001389 fsp= 1, odt_onoff= 1, Byte mode= 0
1518 18:36:04.001448 ==
1519 18:36:04.001506 DQS Delay:
1520 18:36:04.001564 DQS0 = 0, DQS1 = 0
1521 18:36:04.001622 DQM Delay:
1522 18:36:04.001680 DQM0 = 19, DQM1 = 18
1523 18:36:04.001738 DQ Delay:
1524 18:36:04.001796 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1525 18:36:04.001855 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
1526 18:36:04.001913 DQ8 =14, DQ9 =16, DQ10 =25, DQ11 =16
1527 18:36:04.001971 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1528 18:36:04.002030
1529 18:36:04.002088
1530 18:36:04.002146
1531 18:36:04.002204 [DramC_TX_OE_Calibration] TA2
1532 18:36:04.002262 Original DQ_B0 (3 6) =30, OEN = 27
1533 18:36:04.002321 Original DQ_B1 (3 6) =30, OEN = 27
1534 18:36:04.002380 23, 0x0, End_B0=23 End_B1=23
1535 18:36:04.002440 24, 0x0, End_B0=24 End_B1=24
1536 18:36:04.002499 25, 0x0, End_B0=25 End_B1=25
1537 18:36:04.002558 26, 0x0, End_B0=26 End_B1=26
1538 18:36:04.002616 27, 0x0, End_B0=27 End_B1=27
1539 18:36:04.002676 28, 0x0, End_B0=28 End_B1=28
1540 18:36:04.002735 29, 0x0, End_B0=29 End_B1=29
1541 18:36:04.002793 30, 0x0, End_B0=30 End_B1=30
1542 18:36:04.002852 31, 0xFFFF, End_B0=30 End_B1=30
1543 18:36:04.002912 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1544 18:36:04.002971 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1545 18:36:04.003029
1546 18:36:04.003086
1547 18:36:04.003145 Write Rank0 MR23 =0x3f
1548 18:36:04.003203 [DQSOSC]
1549 18:36:04.003262 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1550 18:36:04.003321 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=15, DEC=22
1551 18:36:04.003381 Write Rank0 MR23 =0x3f
1552 18:36:04.003446 [DQSOSC]
1553 18:36:04.003505 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
1554 18:36:04.003564 CH0 RK0: MR19=303, MR18=F0F
1555 18:36:04.003623 [RankSwap] Rank num 2, (Multi 1), Rank 1
1556 18:36:04.003681 Write Rank0 MR2 =0xad
1557 18:36:04.003741 [Write Leveling]
1558 18:36:04.003799 delay byte0 byte1 byte2 byte3
1559 18:36:04.003858
1560 18:36:04.003916 10 0 0
1561 18:36:04.003976 11 0 0
1562 18:36:04.004036 12 0 0
1563 18:36:04.004095 13 0 0
1564 18:36:04.004154 14 0 0
1565 18:36:04.004214 15 0 0
1566 18:36:04.004272 16 0 0
1567 18:36:04.004331 17 0 0
1568 18:36:04.004390 18 0 0
1569 18:36:04.004449 19 0 0
1570 18:36:04.004508 20 0 0
1571 18:36:04.004567 21 0 0
1572 18:36:04.004626 22 0 0
1573 18:36:04.004686 23 0 0
1574 18:36:04.004744 24 0 ff
1575 18:36:04.004804 25 0 ff
1576 18:36:04.004862 26 ff ff
1577 18:36:04.004922 27 ff ff
1578 18:36:04.004981 28 ff ff
1579 18:36:04.005040 29 ff ff
1580 18:36:04.005100 30 ff ff
1581 18:36:04.005159 31 ff ff
1582 18:36:04.005218 32 ff ff
1583 18:36:04.005277 pass bytecount = 0xff (0xff: all bytes pass)
1584 18:36:04.005336
1585 18:36:04.005394 DQS0 dly: 26
1586 18:36:04.005452 DQS1 dly: 24
1587 18:36:04.005510 Write Rank0 MR2 =0x2d
1588 18:36:04.005569 [RankSwap] Rank num 2, (Multi 1), Rank 0
1589 18:36:04.005627 Write Rank1 MR1 =0xd6
1590 18:36:04.005685 [Gating]
1591 18:36:04.005743 ==
1592 18:36:04.005801 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1593 18:36:04.005860 fsp= 1, odt_onoff= 1, Byte mode= 0
1594 18:36:04.005918 ==
1595 18:36:04.005976 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1596 18:36:04.006036 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1597 18:36:04.006096 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1598 18:36:04.006155 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1599 18:36:04.006215 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1600 18:36:04.006274 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1601 18:36:04.006335 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1602 18:36:04.006395 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1603 18:36:04.006455 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1604 18:36:04.006515 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1605 18:36:04.006574 3 2 8 |404 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1606 18:36:04.006634 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1607 18:36:04.006693 3 2 16 |3534 3d3c |(11 11)(11 11) |(0 0)(1 1)| 0
1608 18:36:04.006753 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1609 18:36:04.006812 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1610 18:36:04.006872 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1611 18:36:04.006931 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1612 18:36:04.006990 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1613 18:36:04.007049 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 18:36:04.007108 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 18:36:04.007168 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1616 18:36:04.007227 3 3 20 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
1617 18:36:04.007286 3 3 24 |3534 1a19 |(11 11)(11 11) |(0 0)(1 1)| 0
1618 18:36:04.007345 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1619 18:36:04.007408 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1620 18:36:04.007468 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1621 18:36:04.007528 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1622 18:36:04.007588 3 4 8 |808 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1623 18:36:04.007648 3 4 12 |2626 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1624 18:36:04.007707 3 4 16 |3d3d 908 |(11 11)(11 11) |(1 1)(1 1)| 0
1625 18:36:04.007767 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1626 18:36:04.007827 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1627 18:36:04.007887 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1628 18:36:04.007946 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1629 18:36:04.008201 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1630 18:36:04.008268 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 18:36:04.008330 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1632 18:36:04.008390 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1633 18:36:04.008450 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1634 18:36:04.008510 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 18:36:04.008571 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1636 18:36:04.008632 [Byte 0] Lead/lag falling Transition (3, 5, 28)
1637 18:36:04.008691 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1638 18:36:04.008751 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1639 18:36:04.008810 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1640 18:36:04.008870 [Byte 0] Lead/lag Transition tap number (4)
1641 18:36:04.008929 [Byte 1] Lead/lag Transition tap number (1)
1642 18:36:04.008988 3 6 12 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
1643 18:36:04.009048 [Byte 0]First pass (3, 6, 12)
1644 18:36:04.009107 3 6 16 |4646 808 |(0 0)(11 11) |(0 0)(0 0)| 0
1645 18:36:04.009167 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1646 18:36:04.009227 [Byte 1]First pass (3, 6, 20)
1647 18:36:04.009285 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1648 18:36:04.009345 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1649 18:36:04.009405 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1650 18:36:04.009465 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1651 18:36:04.009525 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1652 18:36:04.009585 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1653 18:36:04.009644 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1654 18:36:04.009703 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1655 18:36:04.009763 All bytes gating window > 1UI, Early break!
1656 18:36:04.009821
1657 18:36:04.009880 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1658 18:36:04.009938
1659 18:36:04.009996 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
1660 18:36:04.010054
1661 18:36:04.010113
1662 18:36:04.010170
1663 18:36:04.010229 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1664 18:36:04.010287
1665 18:36:04.010345 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
1666 18:36:04.010403
1667 18:36:04.010461
1668 18:36:04.010519 Write Rank1 MR1 =0x56
1669 18:36:04.010577
1670 18:36:04.010635 best RODT dly(2T, 0.5T) = (2, 3)
1671 18:36:04.010694
1672 18:36:04.010752 best RODT dly(2T, 0.5T) = (2, 3)
1673 18:36:04.010811 ==
1674 18:36:04.010870 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1675 18:36:04.010930 fsp= 1, odt_onoff= 1, Byte mode= 0
1676 18:36:04.010988 ==
1677 18:36:04.011046 Start DQ dly to find pass range UseTestEngine =0
1678 18:36:04.011105 x-axis: bit #, y-axis: DQ dly (-127~63)
1679 18:36:04.011163 RX Vref Scan = 0
1680 18:36:04.011221 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1681 18:36:04.011281 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1682 18:36:04.011340 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1683 18:36:04.011399 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1684 18:36:04.011466 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1685 18:36:04.011526 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1686 18:36:04.011584 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1687 18:36:04.011644 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1688 18:36:04.011703 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1689 18:36:04.011763 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1690 18:36:04.011822 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1691 18:36:04.011882 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1692 18:36:04.011942 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1693 18:36:04.012001 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1694 18:36:04.012059 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1695 18:36:04.012119 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1696 18:36:04.012178 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1697 18:36:04.012237 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1698 18:36:04.012297 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1699 18:36:04.012377 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1700 18:36:04.012437 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1701 18:36:04.012497 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1702 18:36:04.012556 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1703 18:36:04.012625 -3, [0] xxxxxxxx oxxoxxxx [MSB]
1704 18:36:04.012705 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1705 18:36:04.012806 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1706 18:36:04.012873 0, [0] xxxoxxxx oxxoxxxx [MSB]
1707 18:36:04.012935 1, [0] xxxoxoox ooxoooxx [MSB]
1708 18:36:04.012995 2, [0] xxxoxooo ooxoooxx [MSB]
1709 18:36:04.013055 3, [0] xxxooooo ooxoooox [MSB]
1710 18:36:04.013115 4, [0] oooooooo ooxoooox [MSB]
1711 18:36:04.013175 5, [0] oooooooo ooxooooo [MSB]
1712 18:36:04.013234 6, [0] oooooooo ooxooooo [MSB]
1713 18:36:04.013295 34, [0] oooxoooo xooooooo [MSB]
1714 18:36:04.013355 35, [0] oooxoooo xooooooo [MSB]
1715 18:36:04.013415 36, [0] oooxoooo xooxoooo [MSB]
1716 18:36:04.013474 37, [0] oooxoxoo xxoxoxxo [MSB]
1717 18:36:04.013534 38, [0] oooxoxoo xxoxxxxo [MSB]
1718 18:36:04.013593 39, [0] oooxoxxx xxoxxxxo [MSB]
1719 18:36:04.013652 40, [0] oooxoxxx xxoxxxxo [MSB]
1720 18:36:04.013712 41, [0] oxxxxxxx xxoxxxxx [MSB]
1721 18:36:04.013770 42, [0] oxxxxxxx xxoxxxxx [MSB]
1722 18:36:04.013829 43, [0] xxxxxxxx xxoxxxxx [MSB]
1723 18:36:04.013888 44, [0] xxxxxxxx xxoxxxxx [MSB]
1724 18:36:04.013948 45, [0] xxxxxxxx xxxxxxxx [MSB]
1725 18:36:04.014006 iDelay=45, Bit 0, Center 23 (4 ~ 42) 39
1726 18:36:04.014065 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1727 18:36:04.014123 iDelay=45, Bit 2, Center 22 (4 ~ 40) 37
1728 18:36:04.014181 iDelay=45, Bit 3, Center 15 (-2 ~ 33) 36
1729 18:36:04.014240 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1730 18:36:04.014298 iDelay=45, Bit 5, Center 18 (1 ~ 36) 36
1731 18:36:04.014356 iDelay=45, Bit 6, Center 19 (1 ~ 38) 38
1732 18:36:04.014414 iDelay=45, Bit 7, Center 20 (2 ~ 38) 37
1733 18:36:04.014472 iDelay=45, Bit 8, Center 15 (-3 ~ 33) 37
1734 18:36:04.014530 iDelay=45, Bit 9, Center 18 (1 ~ 36) 36
1735 18:36:04.014588 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1736 18:36:04.014646 iDelay=45, Bit 11, Center 16 (-3 ~ 35) 39
1737 18:36:04.014704 iDelay=45, Bit 12, Center 19 (1 ~ 37) 37
1738 18:36:04.014762 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1739 18:36:04.014820 iDelay=45, Bit 14, Center 19 (3 ~ 36) 34
1740 18:36:04.014878 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1741 18:36:04.014936 ==
1742 18:36:04.014995 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1743 18:36:04.015054 fsp= 1, odt_onoff= 1, Byte mode= 0
1744 18:36:04.015113 ==
1745 18:36:04.015171 DQS Delay:
1746 18:36:04.015229 DQS0 = 0, DQS1 = 0
1747 18:36:04.015287 DQM Delay:
1748 18:36:04.015346 DQM0 = 20, DQM1 = 19
1749 18:36:04.015608 DQ Delay:
1750 18:36:04.015674 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =15
1751 18:36:04.015734 DQ4 =21, DQ5 =18, DQ6 =19, DQ7 =20
1752 18:36:04.015794 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1753 18:36:04.015853 DQ12 =19, DQ13 =18, DQ14 =19, DQ15 =22
1754 18:36:04.015911
1755 18:36:04.015970
1756 18:36:04.016027 DramC Write-DBI off
1757 18:36:04.016086 ==
1758 18:36:04.016144 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1759 18:36:04.016203 fsp= 1, odt_onoff= 1, Byte mode= 0
1760 18:36:04.016262 ==
1761 18:36:04.016321 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1762 18:36:04.016380
1763 18:36:04.016437 Begin, DQ Scan Range 920~1176
1764 18:36:04.016496
1765 18:36:04.016554
1766 18:36:04.016638 TX Vref Scan disable
1767 18:36:04.016699 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1768 18:36:04.016760 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1769 18:36:04.016820 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1770 18:36:04.016880 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1771 18:36:04.016940 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1772 18:36:04.016999 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1773 18:36:04.017059 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1774 18:36:04.017118 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1775 18:36:04.017178 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1776 18:36:04.017237 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1777 18:36:04.017297 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1778 18:36:04.017357 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1779 18:36:04.017416 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1780 18:36:04.017476 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1781 18:36:04.017535 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1782 18:36:04.017595 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1783 18:36:04.017655 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1784 18:36:04.017714 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1785 18:36:04.017773 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1786 18:36:04.017833 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1787 18:36:04.017893 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1788 18:36:04.017952 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1789 18:36:04.018011 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1790 18:36:04.018070 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1791 18:36:04.018130 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1792 18:36:04.018190 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1793 18:36:04.018249 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1794 18:36:04.018308 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1795 18:36:04.018367 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1796 18:36:04.018427 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1797 18:36:04.018486 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1798 18:36:04.018546 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1799 18:36:04.018606 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1800 18:36:04.018665 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1801 18:36:04.018725 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1802 18:36:04.018784 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1803 18:36:04.018844 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1804 18:36:04.018903 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1805 18:36:04.018963 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1806 18:36:04.019022 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1807 18:36:04.019082 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1808 18:36:04.019141 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1809 18:36:04.019201 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1810 18:36:04.019260 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1811 18:36:04.019320 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1812 18:36:04.019380 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1813 18:36:04.019452 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1814 18:36:04.019513 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1815 18:36:04.019573 968 |3 6 8|[0] xxxxxxxx oxxoxxxx [MSB]
1816 18:36:04.019632 969 |3 6 9|[0] xxxxxxxx ooxoxxxx [MSB]
1817 18:36:04.019692 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1818 18:36:04.019752 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1819 18:36:04.019812 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1820 18:36:04.019871 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1821 18:36:04.019930 974 |3 6 14|[0] xoxooooo ooxooooo [MSB]
1822 18:36:04.019990 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1823 18:36:04.020050 987 |3 6 27|[0] oooooooo xooooooo [MSB]
1824 18:36:04.020110 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1825 18:36:04.020169 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1826 18:36:04.020229 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1827 18:36:04.020289 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1828 18:36:04.020349 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1829 18:36:04.020408 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1830 18:36:04.020468 Byte0, DQ PI dly=982, DQM PI dly= 982
1831 18:36:04.020526 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1832 18:36:04.020585
1833 18:36:04.020643 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1834 18:36:04.020702
1835 18:36:04.020760 Byte1, DQ PI dly=979, DQM PI dly= 979
1836 18:36:04.020818 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1837 18:36:04.020877
1838 18:36:04.020935 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1839 18:36:04.020993
1840 18:36:04.021051 ==
1841 18:36:04.021109 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1842 18:36:04.021168 fsp= 1, odt_onoff= 1, Byte mode= 0
1843 18:36:04.021226 ==
1844 18:36:04.021284 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1845 18:36:04.021343
1846 18:36:04.021401 Begin, DQ Scan Range 955~1019
1847 18:36:04.021460 Write Rank1 MR14 =0x0
1848 18:36:04.021517
1849 18:36:04.021576 CH=0, VrefRange= 0, VrefLevel = 0
1850 18:36:04.021634 TX Bit0 (977~991) 15 984, Bit8 (969~982) 14 975,
1851 18:36:04.021693 TX Bit1 (977~987) 11 982, Bit9 (971~985) 15 978,
1852 18:36:04.021751 TX Bit2 (977~989) 13 983, Bit10 (977~985) 9 981,
1853 18:36:04.021810 TX Bit3 (971~983) 13 977, Bit11 (971~983) 13 977,
1854 18:36:04.021869 TX Bit4 (976~989) 14 982, Bit12 (973~985) 13 979,
1855 18:36:04.021928 TX Bit5 (973~986) 14 979, Bit13 (975~983) 9 979,
1856 18:36:04.021986 TX Bit6 (975~987) 13 981, Bit14 (975~985) 11 980,
1857 18:36:04.022044 TX Bit7 (976~989) 14 982, Bit15 (976~985) 10 980,
1858 18:36:04.022103
1859 18:36:04.022160 Write Rank1 MR14 =0x2
1860 18:36:04.022218
1861 18:36:04.022275 CH=0, VrefRange= 0, VrefLevel = 2
1862 18:36:04.022333 TX Bit0 (977~991) 15 984, Bit8 (969~983) 15 976,
1863 18:36:04.022392 TX Bit1 (976~989) 14 982, Bit9 (970~985) 16 977,
1864 18:36:04.022682 TX Bit2 (977~990) 14 983, Bit10 (976~990) 15 983,
1865 18:36:04.022759 TX Bit3 (970~984) 15 977, Bit11 (970~983) 14 976,
1866 18:36:04.022822 TX Bit4 (976~990) 15 983, Bit12 (972~985) 14 978,
1867 18:36:04.022883 TX Bit5 (973~986) 14 979, Bit13 (975~983) 9 979,
1868 18:36:04.022942 TX Bit6 (975~989) 15 982, Bit14 (974~985) 12 979,
1869 18:36:04.023002 TX Bit7 (975~990) 16 982, Bit15 (975~990) 16 982,
1870 18:36:04.023060
1871 18:36:04.023119 Write Rank1 MR14 =0x4
1872 18:36:04.023177
1873 18:36:04.023235 CH=0, VrefRange= 0, VrefLevel = 4
1874 18:36:04.023295 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1875 18:36:04.023354 TX Bit1 (976~989) 14 982, Bit9 (970~985) 16 977,
1876 18:36:04.023423 TX Bit2 (977~991) 15 984, Bit10 (976~990) 15 983,
1877 18:36:04.023484 TX Bit3 (970~984) 15 977, Bit11 (970~984) 15 977,
1878 18:36:04.023543 TX Bit4 (975~990) 16 982, Bit12 (972~985) 14 978,
1879 18:36:04.023602 TX Bit5 (972~987) 16 979, Bit13 (974~984) 11 979,
1880 18:36:04.023661 TX Bit6 (974~990) 17 982, Bit14 (974~986) 13 980,
1881 18:36:04.023720 TX Bit7 (975~990) 16 982, Bit15 (976~990) 15 983,
1882 18:36:04.023778
1883 18:36:04.023835 Write Rank1 MR14 =0x6
1884 18:36:04.023894
1885 18:36:04.023952 CH=0, VrefRange= 0, VrefLevel = 6
1886 18:36:04.024011 TX Bit0 (977~992) 16 984, Bit8 (969~984) 16 976,
1887 18:36:04.024069 TX Bit1 (976~990) 15 983, Bit9 (970~986) 17 978,
1888 18:36:04.024127 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1889 18:36:04.024185 TX Bit3 (970~985) 16 977, Bit11 (969~984) 16 976,
1890 18:36:04.024244 TX Bit4 (975~991) 17 983, Bit12 (972~987) 16 979,
1891 18:36:04.024302 TX Bit5 (972~989) 18 980, Bit13 (973~984) 12 978,
1892 18:36:04.024361 TX Bit6 (974~990) 17 982, Bit14 (973~987) 15 980,
1893 18:36:04.024420 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1894 18:36:04.024478
1895 18:36:04.024536 Write Rank1 MR14 =0x8
1896 18:36:04.024604
1897 18:36:04.024664 CH=0, VrefRange= 0, VrefLevel = 8
1898 18:36:04.024723 TX Bit0 (976~993) 18 984, Bit8 (968~984) 17 976,
1899 18:36:04.024782 TX Bit1 (976~991) 16 983, Bit9 (970~987) 18 978,
1900 18:36:04.024841 TX Bit2 (977~991) 15 984, Bit10 (976~991) 16 983,
1901 18:36:04.024900 TX Bit3 (970~986) 17 978, Bit11 (969~984) 16 976,
1902 18:36:04.024960 TX Bit4 (975~991) 17 983, Bit12 (971~987) 17 979,
1903 18:36:04.025019 TX Bit5 (971~989) 19 980, Bit13 (972~985) 14 978,
1904 18:36:04.025078 TX Bit6 (974~990) 17 982, Bit14 (971~989) 19 980,
1905 18:36:04.025137 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1906 18:36:04.025196
1907 18:36:04.025253 Write Rank1 MR14 =0xa
1908 18:36:04.025311
1909 18:36:04.025370 CH=0, VrefRange= 0, VrefLevel = 10
1910 18:36:04.025428 TX Bit0 (976~993) 18 984, Bit8 (968~984) 17 976,
1911 18:36:04.025487 TX Bit1 (975~991) 17 983, Bit9 (969~988) 20 978,
1912 18:36:04.025546 TX Bit2 (976~992) 17 984, Bit10 (976~991) 16 983,
1913 18:36:04.025606 TX Bit3 (969~987) 19 978, Bit11 (969~985) 17 977,
1914 18:36:04.025664 TX Bit4 (975~992) 18 983, Bit12 (970~989) 20 979,
1915 18:36:04.025723 TX Bit5 (971~990) 20 980, Bit13 (972~986) 15 979,
1916 18:36:04.025782 TX Bit6 (973~991) 19 982, Bit14 (971~989) 19 980,
1917 18:36:04.025841 TX Bit7 (974~992) 19 983, Bit15 (975~992) 18 983,
1918 18:36:04.025899
1919 18:36:04.025958 wait MRW command Rank1 MR14 =0xc fired (1)
1920 18:36:04.026016 Write Rank1 MR14 =0xc
1921 18:36:04.026074
1922 18:36:04.026132 CH=0, VrefRange= 0, VrefLevel = 12
1923 18:36:04.026190 TX Bit0 (976~994) 19 985, Bit8 (968~985) 18 976,
1924 18:36:04.026249 TX Bit1 (975~991) 17 983, Bit9 (969~988) 20 978,
1925 18:36:04.026308 TX Bit2 (976~992) 17 984, Bit10 (975~992) 18 983,
1926 18:36:04.026367 TX Bit3 (969~988) 20 978, Bit11 (969~986) 18 977,
1927 18:36:04.026426 TX Bit4 (974~992) 19 983, Bit12 (970~988) 19 979,
1928 18:36:04.026485 TX Bit5 (971~990) 20 980, Bit13 (972~986) 15 979,
1929 18:36:04.026543 TX Bit6 (973~991) 19 982, Bit14 (971~989) 19 980,
1930 18:36:04.026602 TX Bit7 (973~992) 20 982, Bit15 (975~992) 18 983,
1931 18:36:04.026661
1932 18:36:04.026719 Write Rank1 MR14 =0xe
1933 18:36:04.026776
1934 18:36:04.026834 CH=0, VrefRange= 0, VrefLevel = 14
1935 18:36:04.026893 TX Bit0 (976~994) 19 985, Bit8 (968~986) 19 977,
1936 18:36:04.026952 TX Bit1 (975~992) 18 983, Bit9 (969~989) 21 979,
1937 18:36:04.027011 TX Bit2 (976~993) 18 984, Bit10 (975~992) 18 983,
1938 18:36:04.027070 TX Bit3 (969~988) 20 978, Bit11 (968~986) 19 977,
1939 18:36:04.027135 TX Bit4 (974~992) 19 983, Bit12 (970~990) 21 980,
1940 18:36:04.027194 TX Bit5 (970~990) 21 980, Bit13 (971~987) 17 979,
1941 18:36:04.027253 TX Bit6 (972~991) 20 981, Bit14 (971~990) 20 980,
1942 18:36:04.027311 TX Bit7 (973~992) 20 982, Bit15 (974~992) 19 983,
1943 18:36:04.027369
1944 18:36:04.027433 Write Rank1 MR14 =0x10
1945 18:36:04.027492
1946 18:36:04.027550 CH=0, VrefRange= 0, VrefLevel = 16
1947 18:36:04.027608 TX Bit0 (976~995) 20 985, Bit8 (968~987) 20 977,
1948 18:36:04.027668 TX Bit1 (975~992) 18 983, Bit9 (969~990) 22 979,
1949 18:36:04.027726 TX Bit2 (976~993) 18 984, Bit10 (975~993) 19 984,
1950 18:36:04.027785 TX Bit3 (969~989) 21 979, Bit11 (968~987) 20 977,
1951 18:36:04.027844 TX Bit4 (973~993) 21 983, Bit12 (970~990) 21 980,
1952 18:36:04.027902 TX Bit5 (970~991) 22 980, Bit13 (971~988) 18 979,
1953 18:36:04.027960 TX Bit6 (971~992) 22 981, Bit14 (970~990) 21 980,
1954 18:36:04.028018 TX Bit7 (973~993) 21 983, Bit15 (974~993) 20 983,
1955 18:36:04.028077
1956 18:36:04.028135 Write Rank1 MR14 =0x12
1957 18:36:04.028192
1958 18:36:04.028250 CH=0, VrefRange= 0, VrefLevel = 18
1959 18:36:04.028309 TX Bit0 (976~996) 21 986, Bit8 (967~987) 21 977,
1960 18:36:04.028367 TX Bit1 (974~993) 20 983, Bit9 (969~990) 22 979,
1961 18:36:04.028426 TX Bit2 (976~994) 19 985, Bit10 (975~993) 19 984,
1962 18:36:04.028484 TX Bit3 (968~990) 23 979, Bit11 (968~988) 21 978,
1963 18:36:04.028543 TX Bit4 (973~993) 21 983, Bit12 (969~990) 22 979,
1964 18:36:04.028824 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1965 18:36:04.028898 TX Bit6 (971~992) 22 981, Bit14 (970~991) 22 980,
1966 18:36:04.028960 TX Bit7 (972~993) 22 982, Bit15 (973~993) 21 983,
1967 18:36:04.029021
1968 18:36:04.029080 Write Rank1 MR14 =0x14
1969 18:36:04.029139
1970 18:36:04.029197 CH=0, VrefRange= 0, VrefLevel = 20
1971 18:36:04.029256 TX Bit0 (975~996) 22 985, Bit8 (967~988) 22 977,
1972 18:36:04.029316 TX Bit1 (974~994) 21 984, Bit9 (969~990) 22 979,
1973 18:36:04.029375 TX Bit2 (975~995) 21 985, Bit10 (973~995) 23 984,
1974 18:36:04.029434 TX Bit3 (968~990) 23 979, Bit11 (968~989) 22 978,
1975 18:36:04.302698 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1976 18:36:04.302851 TX Bit5 (970~991) 22 980, Bit13 (970~989) 20 979,
1977 18:36:04.302926 TX Bit6 (971~992) 22 981, Bit14 (969~991) 23 980,
1978 18:36:04.302994 TX Bit7 (972~994) 23 983, Bit15 (974~994) 21 984,
1979 18:36:04.303059
1980 18:36:04.303121 Write Rank1 MR14 =0x16
1981 18:36:04.303184
1982 18:36:04.303245 CH=0, VrefRange= 0, VrefLevel = 22
1983 18:36:04.303306 TX Bit0 (975~997) 23 986, Bit8 (967~989) 23 978,
1984 18:36:04.303368 TX Bit1 (973~994) 22 983, Bit9 (969~991) 23 980,
1985 18:36:04.303436 TX Bit2 (975~995) 21 985, Bit10 (974~995) 22 984,
1986 18:36:04.303498 TX Bit3 (968~990) 23 979, Bit11 (968~989) 22 978,
1987 18:36:04.303558 TX Bit4 (972~994) 23 983, Bit12 (969~991) 23 980,
1988 18:36:04.303617 TX Bit5 (970~992) 23 981, Bit13 (970~990) 21 980,
1989 18:36:04.303677 TX Bit6 (970~993) 24 981, Bit14 (969~991) 23 980,
1990 18:36:04.303736 TX Bit7 (972~994) 23 983, Bit15 (972~994) 23 983,
1991 18:36:04.303795
1992 18:36:04.303853 Write Rank1 MR14 =0x18
1993 18:36:04.303912
1994 18:36:04.303970 CH=0, VrefRange= 0, VrefLevel = 24
1995 18:36:04.304028 TX Bit0 (975~997) 23 986, Bit8 (967~990) 24 978,
1996 18:36:04.304087 TX Bit1 (973~994) 22 983, Bit9 (968~991) 24 979,
1997 18:36:04.304146 TX Bit2 (975~995) 21 985, Bit10 (973~995) 23 984,
1998 18:36:04.304204 TX Bit3 (968~991) 24 979, Bit11 (967~989) 23 978,
1999 18:36:04.304263 TX Bit4 (972~994) 23 983, Bit12 (968~991) 24 979,
2000 18:36:04.304321 TX Bit5 (969~992) 24 980, Bit13 (969~990) 22 979,
2001 18:36:04.304380 TX Bit6 (970~993) 24 981, Bit14 (969~992) 24 980,
2002 18:36:04.304439 TX Bit7 (971~994) 24 982, Bit15 (972~995) 24 983,
2003 18:36:04.304497
2004 18:36:04.304555 Write Rank1 MR14 =0x1a
2005 18:36:04.304614
2006 18:36:04.304671 CH=0, VrefRange= 0, VrefLevel = 26
2007 18:36:04.304731 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2008 18:36:04.304790 TX Bit1 (973~995) 23 984, Bit9 (968~991) 24 979,
2009 18:36:04.304849 TX Bit2 (975~996) 22 985, Bit10 (973~997) 25 985,
2010 18:36:04.304907 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2011 18:36:04.304966 TX Bit4 (971~996) 26 983, Bit12 (969~992) 24 980,
2012 18:36:04.305024 TX Bit5 (969~992) 24 980, Bit13 (969~991) 23 980,
2013 18:36:04.305083 TX Bit6 (970~994) 25 982, Bit14 (969~992) 24 980,
2014 18:36:04.305141 TX Bit7 (971~996) 26 983, Bit15 (973~995) 23 984,
2015 18:36:04.305200
2016 18:36:04.305257 Write Rank1 MR14 =0x1c
2017 18:36:04.305315
2018 18:36:04.305372 CH=0, VrefRange= 0, VrefLevel = 28
2019 18:36:04.305431 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2020 18:36:04.305489 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2021 18:36:04.305548 TX Bit2 (975~997) 23 986, Bit10 (972~997) 26 984,
2022 18:36:04.305606 TX Bit3 (967~991) 25 979, Bit11 (967~990) 24 978,
2023 18:36:04.305664 TX Bit4 (971~996) 26 983, Bit12 (968~992) 25 980,
2024 18:36:04.305723 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2025 18:36:04.305782 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
2026 18:36:04.305840 TX Bit7 (970~996) 27 983, Bit15 (971~996) 26 983,
2027 18:36:04.305899
2028 18:36:04.305957 Write Rank1 MR14 =0x1e
2029 18:36:04.306015
2030 18:36:04.306073 CH=0, VrefRange= 0, VrefLevel = 30
2031 18:36:04.306131 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2032 18:36:04.306189 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
2033 18:36:04.306248 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2034 18:36:04.306307 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
2035 18:36:04.306365 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2036 18:36:04.306423 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2037 18:36:04.306481 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2038 18:36:04.306540 TX Bit7 (971~997) 27 984, Bit15 (971~996) 26 983,
2039 18:36:04.306598
2040 18:36:04.306656 Write Rank1 MR14 =0x20
2041 18:36:04.306713
2042 18:36:04.306770 CH=0, VrefRange= 0, VrefLevel = 32
2043 18:36:04.306828 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2044 18:36:04.306886 TX Bit1 (972~996) 25 984, Bit9 (968~991) 24 979,
2045 18:36:04.306945 TX Bit2 (974~997) 24 985, Bit10 (972~997) 26 984,
2046 18:36:04.307003 TX Bit3 (967~991) 25 979, Bit11 (967~991) 25 979,
2047 18:36:04.307062 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2048 18:36:04.307121 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2049 18:36:04.307180 TX Bit6 (969~995) 27 982, Bit14 (968~992) 25 980,
2050 18:36:04.307238 TX Bit7 (971~997) 27 984, Bit15 (971~996) 26 983,
2051 18:36:04.307297
2052 18:36:04.307354 Write Rank1 MR14 =0x22
2053 18:36:04.307426
2054 18:36:04.307487 CH=0, VrefRange= 0, VrefLevel = 34
2055 18:36:04.307546 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2056 18:36:04.307605 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2057 18:36:04.307665 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2058 18:36:04.307724 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2059 18:36:04.307783 TX Bit4 (971~996) 26 983, Bit12 (968~991) 24 979,
2060 18:36:04.307842 TX Bit5 (969~993) 25 981, Bit13 (968~992) 25 980,
2061 18:36:04.307901 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
2062 18:36:04.307959 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2063 18:36:04.308017
2064 18:36:04.308075 Write Rank1 MR14 =0x24
2065 18:36:04.308134
2066 18:36:04.308407 CH=0, VrefRange= 0, VrefLevel = 36
2067 18:36:04.308476 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2068 18:36:04.308536 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2069 18:36:04.308595 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2070 18:36:04.308653 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2071 18:36:04.308712 TX Bit4 (971~996) 26 983, Bit12 (968~991) 24 979,
2072 18:36:04.308770 TX Bit5 (969~993) 25 981, Bit13 (968~992) 25 980,
2073 18:36:04.308829 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
2074 18:36:04.308887 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2075 18:36:04.308946
2076 18:36:04.309005 Write Rank1 MR14 =0x26
2077 18:36:04.309064
2078 18:36:04.309122 CH=0, VrefRange= 0, VrefLevel = 38
2079 18:36:04.309182 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2080 18:36:04.309241 TX Bit1 (973~996) 24 984, Bit9 (968~991) 24 979,
2081 18:36:04.309300 TX Bit2 (973~998) 26 985, Bit10 (972~997) 26 984,
2082 18:36:04.309358 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2083 18:36:04.309417 TX Bit4 (971~996) 26 983, Bit12 (968~991) 24 979,
2084 18:36:04.309476 TX Bit5 (969~993) 25 981, Bit13 (968~992) 25 980,
2085 18:36:04.309534 TX Bit6 (970~994) 25 982, Bit14 (968~992) 25 980,
2086 18:36:04.309592 TX Bit7 (971~996) 26 983, Bit15 (971~995) 25 983,
2087 18:36:04.309651
2088 18:36:04.309709
2089 18:36:04.309767 TX Vref found, early break! 374< 379
2090 18:36:04.309827 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2091 18:36:04.309887 u1DelayCellOfst[0]=9 cells (7 PI)
2092 18:36:04.309946 u1DelayCellOfst[1]=6 cells (5 PI)
2093 18:36:04.310004 u1DelayCellOfst[2]=7 cells (6 PI)
2094 18:36:04.310063 u1DelayCellOfst[3]=0 cells (0 PI)
2095 18:36:04.310121 u1DelayCellOfst[4]=5 cells (4 PI)
2096 18:36:04.310180 u1DelayCellOfst[5]=2 cells (2 PI)
2097 18:36:04.310238 u1DelayCellOfst[6]=3 cells (3 PI)
2098 18:36:04.310296 u1DelayCellOfst[7]=5 cells (4 PI)
2099 18:36:04.310354 Byte0, DQ PI dly=979, DQM PI dly= 982
2100 18:36:04.310413 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2101 18:36:04.310473
2102 18:36:04.310532 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2103 18:36:04.310592
2104 18:36:04.310650 u1DelayCellOfst[8]=0 cells (0 PI)
2105 18:36:04.310709 u1DelayCellOfst[9]=1 cells (1 PI)
2106 18:36:04.310768 u1DelayCellOfst[10]=7 cells (6 PI)
2107 18:36:04.310827 u1DelayCellOfst[11]=0 cells (0 PI)
2108 18:36:04.310885 u1DelayCellOfst[12]=1 cells (1 PI)
2109 18:36:04.310943 u1DelayCellOfst[13]=2 cells (2 PI)
2110 18:36:04.311001 u1DelayCellOfst[14]=2 cells (2 PI)
2111 18:36:04.311060 u1DelayCellOfst[15]=6 cells (5 PI)
2112 18:36:04.311118 Byte1, DQ PI dly=978, DQM PI dly= 981
2113 18:36:04.311177 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2114 18:36:04.311236
2115 18:36:04.311295 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2116 18:36:04.311354
2117 18:36:04.311420 Write Rank1 MR14 =0x22
2118 18:36:04.311481
2119 18:36:04.311539 Final TX Range 0 Vref 34
2120 18:36:04.311598
2121 18:36:04.311656 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2122 18:36:04.311716
2123 18:36:04.311774 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2124 18:36:04.311834 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2125 18:36:04.311893 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2126 18:36:04.311952 Write Rank1 MR3 =0xb0
2127 18:36:04.312010 DramC Write-DBI on
2128 18:36:04.312069 ==
2129 18:36:04.312128 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2130 18:36:04.312187 fsp= 1, odt_onoff= 1, Byte mode= 0
2131 18:36:04.312246 ==
2132 18:36:04.312305 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2133 18:36:04.312365
2134 18:36:04.312423 Begin, DQ Scan Range 701~765
2135 18:36:04.312482
2136 18:36:04.312540
2137 18:36:04.312597 TX Vref Scan disable
2138 18:36:04.312656 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2139 18:36:04.312716 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2140 18:36:04.312776 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2141 18:36:04.312836 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2142 18:36:04.312895 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2143 18:36:04.312955 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2144 18:36:04.313015 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2145 18:36:04.313076 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2146 18:36:04.313135 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2147 18:36:04.313195 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2148 18:36:04.313255 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2149 18:36:04.313314 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2150 18:36:04.313374 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2151 18:36:04.313434 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2152 18:36:04.313493 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2153 18:36:04.313552 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2154 18:36:04.313612 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2155 18:36:04.313672 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2156 18:36:04.313731 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2157 18:36:04.313791 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2158 18:36:04.313850 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2159 18:36:04.313910 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2160 18:36:04.313970 Byte0, DQ PI dly=728, DQM PI dly= 728
2161 18:36:04.314029 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2162 18:36:04.314089
2163 18:36:04.314148 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2164 18:36:04.314207
2165 18:36:04.314266 Byte1, DQ PI dly=723, DQM PI dly= 723
2166 18:36:04.314325 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2167 18:36:04.314384
2168 18:36:04.314443 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2169 18:36:04.314502
2170 18:36:04.314560 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2171 18:36:04.314619 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2172 18:36:04.314678 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2173 18:36:04.314738 Write Rank1 MR3 =0x30
2174 18:36:04.314796 DramC Write-DBI off
2175 18:36:04.314855
2176 18:36:04.314913 [DATLAT]
2177 18:36:04.314971 Freq=1600, CH0 RK1, use_rxtx_scan=0
2178 18:36:04.315030
2179 18:36:04.315088 DATLAT Default: 0x10
2180 18:36:04.315147 7, 0xFFFF, sum=0
2181 18:36:04.315206 8, 0xFFFF, sum=0
2182 18:36:04.315266 9, 0xFFFF, sum=0
2183 18:36:04.315531 10, 0xFFFF, sum=0
2184 18:36:04.315602 11, 0xFFFF, sum=0
2185 18:36:04.315664 12, 0xFFFF, sum=0
2186 18:36:04.315724 13, 0xFFFF, sum=0
2187 18:36:04.315784 14, 0x0, sum=1
2188 18:36:04.315844 15, 0x0, sum=2
2189 18:36:04.315904 16, 0x0, sum=3
2190 18:36:04.315964 17, 0x0, sum=4
2191 18:36:04.316023 pattern=2 first_step=14 total pass=5 best_step=16
2192 18:36:04.316082 ==
2193 18:36:04.316141 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2194 18:36:04.316200 fsp= 1, odt_onoff= 1, Byte mode= 0
2195 18:36:04.316259 ==
2196 18:36:04.316318 Start DQ dly to find pass range UseTestEngine =1
2197 18:36:04.316377 x-axis: bit #, y-axis: DQ dly (-127~63)
2198 18:36:04.316436 RX Vref Scan = 0
2199 18:36:04.316494 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2200 18:36:04.316555 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2201 18:36:04.316614 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2202 18:36:04.316674 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2203 18:36:04.316733 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2204 18:36:04.316793 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2205 18:36:04.316852 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2206 18:36:04.316912 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2207 18:36:04.316972 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2208 18:36:04.317031 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2209 18:36:04.317091 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2210 18:36:04.317151 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2211 18:36:04.317210 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2212 18:36:04.317270 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2213 18:36:04.317329 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2214 18:36:04.317389 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2215 18:36:04.317449 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2216 18:36:04.317509 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2217 18:36:04.317569 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2218 18:36:04.317629 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2219 18:36:04.317689 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2220 18:36:04.317763 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2221 18:36:04.317827 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2222 18:36:04.319915 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2223 18:36:04.323270 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2224 18:36:04.326805 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2225 18:36:04.330074 0, [0] xxxoxxxx oxxoxxxx [MSB]
2226 18:36:04.333422 1, [0] xxxoxoxx ooxoooxx [MSB]
2227 18:36:04.333531 2, [0] xxxoxoxx ooxoooxx [MSB]
2228 18:36:04.336912 3, [0] xxxoxooo ooxoooox [MSB]
2229 18:36:04.340157 4, [0] xxxoxooo ooxoooox [MSB]
2230 18:36:04.343436 5, [0] xoxooooo ooxoooox [MSB]
2231 18:36:04.346561 6, [0] oooooooo ooxooooo [MSB]
2232 18:36:04.350180 33, [0] oooooooo xooooooo [MSB]
2233 18:36:04.353679 34, [0] oooxoooo xooooooo [MSB]
2234 18:36:04.356617 35, [0] oooxoxoo xooxoooo [MSB]
2235 18:36:04.360065 36, [0] oooxoxoo xooxoxoo [MSB]
2236 18:36:04.363423 37, [0] oooxoxoo xxoxoxoo [MSB]
2237 18:36:04.366367 38, [0] oooxoxxx xxoxxxxo [MSB]
2238 18:36:04.366462 39, [0] oxxxoxxx xxoxxxxo [MSB]
2239 18:36:04.369693 40, [0] oxxxxxxx xxoxxxxo [MSB]
2240 18:36:04.372899 41, [0] xxxxxxxx xxoxxxxx [MSB]
2241 18:36:04.376571 42, [0] xxxxxxxx xxoxxxxx [MSB]
2242 18:36:04.379532 43, [0] xxxxxxxx xxoxxxxx [MSB]
2243 18:36:04.382988 44, [0] xxxxxxxx xxxxxxxx [MSB]
2244 18:36:04.386749 iDelay=44, Bit 0, Center 23 (6 ~ 40) 35
2245 18:36:04.389729 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2246 18:36:04.393328 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2247 18:36:04.396266 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2248 18:36:04.399861 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2249 18:36:04.403123 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2250 18:36:04.406733 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2251 18:36:04.410014 iDelay=44, Bit 7, Center 20 (3 ~ 37) 35
2252 18:36:04.413131 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2253 18:36:04.416592 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2254 18:36:04.419970 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2255 18:36:04.426270 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2256 18:36:04.429723 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2257 18:36:04.433160 iDelay=44, Bit 13, Center 18 (1 ~ 35) 35
2258 18:36:04.436606 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
2259 18:36:04.440107 iDelay=44, Bit 15, Center 23 (6 ~ 40) 35
2260 18:36:04.440213 ==
2261 18:36:04.443320 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2262 18:36:04.446972 fsp= 1, odt_onoff= 1, Byte mode= 0
2263 18:36:04.447066 ==
2264 18:36:04.449629 DQS Delay:
2265 18:36:04.449721 DQS0 = 0, DQS1 = 0
2266 18:36:04.453087 DQM Delay:
2267 18:36:04.453179 DQM0 = 20, DQM1 = 19
2268 18:36:04.453251 DQ Delay:
2269 18:36:04.456833 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =15
2270 18:36:04.459966 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2271 18:36:04.463296 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2272 18:36:04.466685 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =23
2273 18:36:04.466782
2274 18:36:04.466853
2275 18:36:04.466919
2276 18:36:04.470112 [DramC_TX_OE_Calibration] TA2
2277 18:36:04.473324 Original DQ_B0 (3 6) =30, OEN = 27
2278 18:36:04.476916 Original DQ_B1 (3 6) =30, OEN = 27
2279 18:36:04.479865 23, 0x0, End_B0=23 End_B1=23
2280 18:36:04.483142 24, 0x0, End_B0=24 End_B1=24
2281 18:36:04.483239 25, 0x0, End_B0=25 End_B1=25
2282 18:36:04.486724 26, 0x0, End_B0=26 End_B1=26
2283 18:36:04.490101 27, 0x0, End_B0=27 End_B1=27
2284 18:36:04.493405 28, 0x0, End_B0=28 End_B1=28
2285 18:36:04.496815 29, 0x0, End_B0=29 End_B1=29
2286 18:36:04.496915 30, 0x0, End_B0=30 End_B1=30
2287 18:36:04.499834 31, 0xFFFF, End_B0=30 End_B1=30
2288 18:36:04.506719 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2289 18:36:04.510079 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2290 18:36:04.513171
2291 18:36:04.513263
2292 18:36:04.513334 Write Rank1 MR23 =0x3f
2293 18:36:04.513401 [DQSOSC]
2294 18:36:04.523102 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2295 18:36:04.529905 CH0_RK1: MR19=0x202, MR18=0xD8D8, DQSOSC=432, MR23=63, INC=13, DEC=19
2296 18:36:04.529998 Write Rank1 MR23 =0x3f
2297 18:36:04.533164 [DQSOSC]
2298 18:36:04.539946 [DQSOSCAuto] RK1, (LSB)MR18= 0xd5d5, (MSB)MR19= 0x202, tDQSOscB0 = 434 ps tDQSOscB1 = 434 ps
2299 18:36:04.543329 CH0 RK1: MR19=202, MR18=D5D5
2300 18:36:04.546549 [RxdqsGatingPostProcess] freq 1600
2301 18:36:04.550038 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2302 18:36:04.553293 Rank: 0
2303 18:36:04.553384 best DQS0 dly(2T, 0.5T) = (2, 5)
2304 18:36:04.556721 best DQS1 dly(2T, 0.5T) = (2, 5)
2305 18:36:04.560385 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2306 18:36:04.563947 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2307 18:36:04.566879 Rank: 1
2308 18:36:04.566969 best DQS0 dly(2T, 0.5T) = (2, 6)
2309 18:36:04.570138 best DQS1 dly(2T, 0.5T) = (2, 6)
2310 18:36:04.573720 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2311 18:36:04.576787 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2312 18:36:04.583618 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2313 18:36:04.586483 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2314 18:36:04.590065 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2315 18:36:04.593830 Write Rank0 MR13 =0x59
2316 18:36:04.593932 ==
2317 18:36:04.597212 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2318 18:36:04.600118 fsp= 1, odt_onoff= 1, Byte mode= 0
2319 18:36:04.600214 ==
2320 18:36:04.603619 === u2Vref_new: 0x56 --> 0x3a
2321 18:36:04.606897 === u2Vref_new: 0x58 --> 0x58
2322 18:36:04.610459 === u2Vref_new: 0x5a --> 0x5a
2323 18:36:04.613605 === u2Vref_new: 0x5c --> 0x78
2324 18:36:04.617013 === u2Vref_new: 0x5e --> 0x7a
2325 18:36:04.620474 === u2Vref_new: 0x60 --> 0x90
2326 18:36:04.624160 [CA 0] Center 38 (13~63) winsize 51
2327 18:36:04.626797 [CA 1] Center 37 (12~63) winsize 52
2328 18:36:04.630211 [CA 2] Center 34 (6~63) winsize 58
2329 18:36:04.633707 [CA 3] Center 34 (6~63) winsize 58
2330 18:36:04.633811 [CA 4] Center 34 (6~63) winsize 58
2331 18:36:04.636759 [CA 5] Center 28 (-2~59) winsize 62
2332 18:36:04.636858
2333 18:36:04.643660 [CATrainingPosCal] consider 1 rank data
2334 18:36:04.643780 u2DelayCellTimex100 = 735/100 ps
2335 18:36:04.650348 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2336 18:36:04.653625 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2337 18:36:04.657058 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2338 18:36:04.660097 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2339 18:36:04.664031 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2340 18:36:04.667009 CA5 delay=28 (-2~59),Diff = 0 PI (0 cell)
2341 18:36:04.667101
2342 18:36:04.670460 CA PerBit enable=1, Macro0, CA PI delay=28
2343 18:36:04.673967 === u2Vref_new: 0x60 --> 0x90
2344 18:36:04.674059
2345 18:36:04.677176 Vref(ca) range 1: 32
2346 18:36:04.677268
2347 18:36:04.677339 CS Dly= 12 (43-0-32)
2348 18:36:04.680329 Write Rank0 MR13 =0xd8
2349 18:36:04.683946 Write Rank0 MR13 =0xd8
2350 18:36:04.684039 Write Rank0 MR12 =0x60
2351 18:36:04.687249 Write Rank1 MR13 =0x59
2352 18:36:04.687341 ==
2353 18:36:04.690914 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2354 18:36:04.693705 fsp= 1, odt_onoff= 1, Byte mode= 0
2355 18:36:04.693797 ==
2356 18:36:04.697436 === u2Vref_new: 0x56 --> 0x3a
2357 18:36:04.700766 === u2Vref_new: 0x58 --> 0x58
2358 18:36:04.704470 === u2Vref_new: 0x5a --> 0x5a
2359 18:36:04.707166 === u2Vref_new: 0x5c --> 0x78
2360 18:36:04.710776 === u2Vref_new: 0x5e --> 0x7a
2361 18:36:04.714094 === u2Vref_new: 0x60 --> 0x90
2362 18:36:04.717517 [CA 0] Center 38 (13~63) winsize 51
2363 18:36:04.720754 [CA 1] Center 38 (13~63) winsize 51
2364 18:36:04.724456 [CA 2] Center 35 (7~63) winsize 57
2365 18:36:04.727237 [CA 3] Center 34 (6~63) winsize 58
2366 18:36:04.730636 [CA 4] Center 35 (7~63) winsize 57
2367 18:36:04.734048 [CA 5] Center 27 (-2~57) winsize 60
2368 18:36:04.734191
2369 18:36:04.737674 [CATrainingPosCal] consider 2 rank data
2370 18:36:04.741021 u2DelayCellTimex100 = 735/100 ps
2371 18:36:04.744106 CA0 delay=38 (13~63),Diff = 11 PI (14 cell)
2372 18:36:04.747772 CA1 delay=38 (13~63),Diff = 11 PI (14 cell)
2373 18:36:04.750945 CA2 delay=35 (7~63),Diff = 8 PI (10 cell)
2374 18:36:04.754118 CA3 delay=34 (6~63),Diff = 7 PI (9 cell)
2375 18:36:04.757727 CA4 delay=35 (7~63),Diff = 8 PI (10 cell)
2376 18:36:04.760960 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2377 18:36:04.761060
2378 18:36:04.764092 CA PerBit enable=1, Macro0, CA PI delay=27
2379 18:36:04.767879 === u2Vref_new: 0x5e --> 0x7a
2380 18:36:04.767977
2381 18:36:04.770731 Vref(ca) range 1: 30
2382 18:36:04.770825
2383 18:36:04.774081 CS Dly= 12 (43-0-32)
2384 18:36:04.774175 Write Rank1 MR13 =0xd8
2385 18:36:04.777846 Write Rank1 MR13 =0xd8
2386 18:36:04.777937 Write Rank1 MR12 =0x5e
2387 18:36:04.780984 [RankSwap] Rank num 2, (Multi 1), Rank 0
2388 18:36:04.784296 Write Rank0 MR2 =0xad
2389 18:36:04.787379 [Write Leveling]
2390 18:36:04.787479 delay byte0 byte1 byte2 byte3
2391 18:36:04.787550
2392 18:36:04.791241 10 0 0
2393 18:36:04.791333 11 0 0
2394 18:36:04.793935 12 0 0
2395 18:36:04.794027 13 0 0
2396 18:36:04.797381 14 0 0
2397 18:36:04.797474 15 0 0
2398 18:36:04.797545 16 0 0
2399 18:36:04.800803 17 0 0
2400 18:36:04.800895 18 0 0
2401 18:36:04.804155 19 0 0
2402 18:36:04.804248 20 0 0
2403 18:36:04.804321 21 0 0
2404 18:36:04.807574 22 0 0
2405 18:36:04.807666 23 0 0
2406 18:36:04.810876 24 0 ff
2407 18:36:04.810967 25 0 ff
2408 18:36:04.814344 26 0 ff
2409 18:36:04.814436 27 0 ff
2410 18:36:04.814508 28 0 ff
2411 18:36:04.817789 29 0 ff
2412 18:36:04.817881 30 0 ff
2413 18:36:04.820542 31 0 ff
2414 18:36:04.820634 32 ff ff
2415 18:36:04.823876 33 ff ff
2416 18:36:04.823969 34 ff ff
2417 18:36:04.827370 35 ff ff
2418 18:36:04.827472 36 ff ff
2419 18:36:04.830995 37 ff ff
2420 18:36:04.831086 38 ff ff
2421 18:36:04.833984 pass bytecount = 0xff (0xff: all bytes pass)
2422 18:36:04.834079
2423 18:36:04.837534 DQS0 dly: 32
2424 18:36:04.837625 DQS1 dly: 24
2425 18:36:04.840858 Write Rank0 MR2 =0x2d
2426 18:36:04.844274 [RankSwap] Rank num 2, (Multi 1), Rank 0
2427 18:36:04.844369 Write Rank0 MR1 =0xd6
2428 18:36:04.847865 [Gating]
2429 18:36:04.847955 ==
2430 18:36:04.850939 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2431 18:36:04.853812 fsp= 1, odt_onoff= 1, Byte mode= 0
2432 18:36:04.853903 ==
2433 18:36:04.857272 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2434 18:36:04.864007 3 1 4 |3535 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2435 18:36:04.867400 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2436 18:36:04.870580 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2437 18:36:04.877345 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2438 18:36:04.880629 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2439 18:36:04.884114 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2440 18:36:04.890883 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2441 18:36:04.894001 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2442 18:36:04.897615 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2443 18:36:04.904185 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2444 18:36:04.907321 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2445 18:36:04.910793 3 2 16 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2446 18:36:04.914108 3 2 20 |403 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2447 18:36:04.920569 3 2 24 |3d3d d0c |(11 11)(11 1) |(1 1)(0 0)| 0
2448 18:36:04.924140 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2449 18:36:04.927172 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2450 18:36:04.934060 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2451 18:36:04.937851 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2452 18:36:04.940540 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2453 18:36:04.947330 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2454 18:36:04.950456 3 3 20 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2455 18:36:04.953954 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2456 18:36:04.957425 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2457 18:36:04.963542 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2458 18:36:04.967348 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2459 18:36:04.970502 [Byte 1] Lead/lag Transition tap number (1)
2460 18:36:04.977292 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2461 18:36:04.980475 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2462 18:36:04.983730 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2463 18:36:04.990659 3 4 16 |b0a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2464 18:36:04.993556 3 4 20 |e0e 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2465 18:36:04.996841 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2466 18:36:05.000198 3 4 28 |3d3d 1817 |(11 11)(11 11) |(1 1)(1 1)| 0
2467 18:36:05.006770 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2468 18:36:05.010096 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2469 18:36:05.013664 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2470 18:36:05.020648 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2471 18:36:05.023626 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2472 18:36:05.026897 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2473 18:36:05.033681 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2474 18:36:05.037101 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2475 18:36:05.039962 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2476 18:36:05.047232 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2477 18:36:05.050118 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2478 18:36:05.053380 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2479 18:36:05.056903 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2480 18:36:05.063262 [Byte 0] Lead/lag Transition tap number (2)
2481 18:36:05.066606 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2482 18:36:05.070364 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2483 18:36:05.073856 3 6 20 |404 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2484 18:36:05.080189 3 6 24 |4646 3e3d |(0 0)(11 11) |(0 0)(1 0)| 0
2485 18:36:05.083515 [Byte 0]First pass (3, 6, 24)
2486 18:36:05.086493 [Byte 1] Lead/lag Transition tap number (3)
2487 18:36:05.089976 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2488 18:36:05.093240 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2489 18:36:05.096643 [Byte 1]First pass (3, 7, 0)
2490 18:36:05.100364 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2491 18:36:05.103311 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2492 18:36:05.106537 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2493 18:36:05.113535 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2494 18:36:05.116942 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2495 18:36:05.119756 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2496 18:36:05.123389 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2497 18:36:05.130082 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2498 18:36:05.133131 All bytes gating window > 1UI, Early break!
2499 18:36:05.133223
2500 18:36:05.136438 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2501 18:36:05.136530
2502 18:36:05.139872 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 22)
2503 18:36:05.139964
2504 18:36:05.140035
2505 18:36:05.140100
2506 18:36:05.143080 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2507 18:36:05.143172
2508 18:36:05.149863 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 22)
2509 18:36:05.149972
2510 18:36:05.150045
2511 18:36:05.150111 Write Rank0 MR1 =0x56
2512 18:36:05.150175
2513 18:36:05.152923 best RODT dly(2T, 0.5T) = (2, 3)
2514 18:36:05.153015
2515 18:36:05.156392 best RODT dly(2T, 0.5T) = (2, 3)
2516 18:36:05.156483 ==
2517 18:36:05.163059 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2518 18:36:05.166652 fsp= 1, odt_onoff= 1, Byte mode= 0
2519 18:36:05.166744 ==
2520 18:36:05.170087 Start DQ dly to find pass range UseTestEngine =0
2521 18:36:05.173146 x-axis: bit #, y-axis: DQ dly (-127~63)
2522 18:36:05.176326 RX Vref Scan = 0
2523 18:36:05.176418 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2524 18:36:05.179741 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2525 18:36:05.183223 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2526 18:36:05.186316 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2527 18:36:05.190051 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2528 18:36:05.193223 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2529 18:36:05.196299 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2530 18:36:05.199626 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2531 18:36:05.202999 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2532 18:36:05.203132 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2533 18:36:05.206294 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2534 18:36:05.209583 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2535 18:36:05.212482 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2536 18:36:05.216076 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2537 18:36:05.219387 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2538 18:36:05.222949 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2539 18:36:05.225931 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2540 18:36:05.226030 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2541 18:36:05.229534 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2542 18:36:05.232941 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2543 18:36:05.236274 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2544 18:36:05.239037 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2545 18:36:05.242375 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2546 18:36:05.245771 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2547 18:36:05.245874 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2548 18:36:05.249300 -1, [0] xxxoxxxx ooxxxxxo [MSB]
2549 18:36:05.252675 0, [0] xxxoxxxx ooxxxxxo [MSB]
2550 18:36:05.255719 1, [0] xxxoxxxx ooxxxxxo [MSB]
2551 18:36:05.259185 2, [0] xxooxxxx oooxxxxo [MSB]
2552 18:36:05.262755 3, [0] oxooxxxo oooxxxxo [MSB]
2553 18:36:05.262849 4, [0] ooooxxxo oooxooxo [MSB]
2554 18:36:05.265911 5, [0] oooooxoo ooooooxo [MSB]
2555 18:36:05.269234 32, [0] oooooooo ooooooox [MSB]
2556 18:36:05.272677 33, [0] oooooooo ooooooox [MSB]
2557 18:36:05.275878 34, [0] oooooooo ooooooox [MSB]
2558 18:36:05.278932 35, [0] oooxoooo xxooooox [MSB]
2559 18:36:05.282138 36, [0] oooxoooo xxooooox [MSB]
2560 18:36:05.285898 37, [0] ooxxoooo xxooooox [MSB]
2561 18:36:05.285992 38, [0] ooxxoooo xxooooox [MSB]
2562 18:36:05.288796 39, [0] ooxxooox xxooooox [MSB]
2563 18:36:05.292094 40, [0] oxxxxoox xxxoooox [MSB]
2564 18:36:05.295726 41, [0] xxxxxoox xxxxxxxx [MSB]
2565 18:36:05.298897 42, [0] xxxxxxxx xxxxxxxx [MSB]
2566 18:36:05.302309 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
2567 18:36:05.305402 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
2568 18:36:05.308850 iDelay=42, Bit 2, Center 19 (2 ~ 36) 35
2569 18:36:05.312240 iDelay=42, Bit 3, Center 16 (-1 ~ 34) 36
2570 18:36:05.315594 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
2571 18:36:05.319037 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
2572 18:36:05.322095 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
2573 18:36:05.325381 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
2574 18:36:05.329056 iDelay=42, Bit 8, Center 16 (-1 ~ 34) 36
2575 18:36:05.335762 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
2576 18:36:05.339211 iDelay=42, Bit 10, Center 20 (2 ~ 39) 38
2577 18:36:05.342065 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
2578 18:36:05.345392 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
2579 18:36:05.348874 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
2580 18:36:05.352284 iDelay=42, Bit 14, Center 23 (6 ~ 40) 35
2581 18:36:05.355505 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
2582 18:36:05.355597 ==
2583 18:36:05.361934 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2584 18:36:05.365336 fsp= 1, odt_onoff= 1, Byte mode= 0
2585 18:36:05.365429 ==
2586 18:36:05.365500 DQS Delay:
2587 18:36:05.368718 DQS0 = 0, DQS1 = 0
2588 18:36:05.368810 DQM Delay:
2589 18:36:05.368882 DQM0 = 20, DQM1 = 19
2590 18:36:05.372017 DQ Delay:
2591 18:36:05.375116 DQ0 =21, DQ1 =21, DQ2 =19, DQ3 =16
2592 18:36:05.378531 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
2593 18:36:05.382240 DQ8 =16, DQ9 =16, DQ10 =20, DQ11 =22
2594 18:36:05.385098 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
2595 18:36:05.385190
2596 18:36:05.385261
2597 18:36:05.385328 DramC Write-DBI off
2598 18:36:05.385392 ==
2599 18:36:05.391770 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2600 18:36:05.395040 fsp= 1, odt_onoff= 1, Byte mode= 0
2601 18:36:05.395132 ==
2602 18:36:05.398452 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2603 18:36:05.398544
2604 18:36:05.401910 Begin, DQ Scan Range 920~1176
2605 18:36:05.402001
2606 18:36:05.402096
2607 18:36:05.405313 TX Vref Scan disable
2608 18:36:05.408369 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2609 18:36:05.411726 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2610 18:36:05.415145 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2611 18:36:05.418633 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2612 18:36:05.421598 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2613 18:36:05.424870 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2614 18:36:05.428402 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2615 18:36:05.431768 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2616 18:36:05.435147 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2617 18:36:05.438040 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2618 18:36:05.441452 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2619 18:36:05.448359 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2620 18:36:05.451722 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2621 18:36:05.455313 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2622 18:36:05.458026 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2623 18:36:05.461655 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2624 18:36:05.464896 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2625 18:36:05.468377 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2626 18:36:05.471222 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2627 18:36:05.474717 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2628 18:36:05.478033 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2629 18:36:05.481360 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2630 18:36:05.484799 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2631 18:36:05.487976 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2632 18:36:05.491622 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2633 18:36:05.494731 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2634 18:36:05.497904 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2635 18:36:05.504721 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2636 18:36:05.508263 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2637 18:36:05.511260 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2638 18:36:05.514348 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2639 18:36:05.517737 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2640 18:36:05.521030 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2641 18:36:05.524609 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2642 18:36:05.527912 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2643 18:36:05.531179 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2644 18:36:05.534496 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2645 18:36:05.537923 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2646 18:36:05.541213 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2647 18:36:05.544598 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2648 18:36:05.548094 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2649 18:36:05.551379 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2650 18:36:05.554644 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2651 18:36:05.557752 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2652 18:36:05.561138 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2653 18:36:05.567867 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2654 18:36:05.571375 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2655 18:36:05.574505 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2656 18:36:05.578009 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2657 18:36:05.581374 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2658 18:36:05.584769 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
2659 18:36:05.587660 971 |3 6 11|[0] xxxxxxxx oooxxxxo [MSB]
2660 18:36:05.591145 972 |3 6 12|[0] xxxxxxxx oooxoxoo [MSB]
2661 18:36:05.594462 973 |3 6 13|[0] xxxxxxxx oooooxoo [MSB]
2662 18:36:05.597683 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2663 18:36:05.601477 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2664 18:36:05.604283 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2665 18:36:05.607606 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2666 18:36:05.611335 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2667 18:36:05.614066 979 |3 6 19|[0] xooooxoo oooooooo [MSB]
2668 18:36:05.617670 980 |3 6 20|[0] oooooxoo oooooooo [MSB]
2669 18:36:05.624846 986 |3 6 26|[0] oooooooo ooooooox [MSB]
2670 18:36:05.628244 987 |3 6 27|[0] oooooooo oxooooox [MSB]
2671 18:36:05.631374 988 |3 6 28|[0] oooooooo oxooooox [MSB]
2672 18:36:05.634609 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
2673 18:36:05.638253 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2674 18:36:05.641446 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2675 18:36:05.644856 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2676 18:36:05.647804 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2677 18:36:05.651523 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2678 18:36:05.654458 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2679 18:36:05.657913 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2680 18:36:05.661046 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
2681 18:36:05.664750 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
2682 18:36:05.667540 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2683 18:36:05.674661 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2684 18:36:05.677595 Byte0, DQ PI dly=988, DQM PI dly= 988
2685 18:36:05.681138 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2686 18:36:05.681231
2687 18:36:05.684299 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2688 18:36:05.684392
2689 18:36:05.687910 Byte1, DQ PI dly=979, DQM PI dly= 979
2690 18:36:05.694071 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2691 18:36:05.694163
2692 18:36:05.697533 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2693 18:36:05.697625
2694 18:36:05.697696 ==
2695 18:36:05.704136 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2696 18:36:05.704227 fsp= 1, odt_onoff= 1, Byte mode= 0
2697 18:36:05.707271 ==
2698 18:36:05.710564 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2699 18:36:05.710656
2700 18:36:05.714049 Begin, DQ Scan Range 955~1019
2701 18:36:05.714141 Write Rank0 MR14 =0x0
2702 18:36:05.723852
2703 18:36:05.723942 CH=1, VrefRange= 0, VrefLevel = 0
2704 18:36:05.730048 TX Bit0 (983~998) 16 990, Bit8 (971~984) 14 977,
2705 18:36:05.733449 TX Bit1 (982~994) 13 988, Bit9 (974~983) 10 978,
2706 18:36:05.740178 TX Bit2 (980~994) 15 987, Bit10 (975~986) 12 980,
2707 18:36:05.743643 TX Bit3 (978~991) 14 984, Bit11 (976~986) 11 981,
2708 18:36:05.746599 TX Bit4 (982~996) 15 989, Bit12 (975~986) 12 980,
2709 18:36:05.753661 TX Bit5 (984~995) 12 989, Bit13 (977~987) 11 982,
2710 18:36:05.756433 TX Bit6 (982~995) 14 988, Bit14 (975~986) 12 980,
2711 18:36:05.763624 TX Bit7 (982~994) 13 988, Bit15 (969~980) 12 974,
2712 18:36:05.763713
2713 18:36:05.763783 Write Rank0 MR14 =0x2
2714 18:36:05.772724
2715 18:36:05.772812 CH=1, VrefRange= 0, VrefLevel = 2
2716 18:36:05.779293 TX Bit0 (983~999) 17 991, Bit8 (972~984) 13 978,
2717 18:36:05.782577 TX Bit1 (982~995) 14 988, Bit9 (973~983) 11 978,
2718 18:36:05.789371 TX Bit2 (980~994) 15 987, Bit10 (975~986) 12 980,
2719 18:36:05.792771 TX Bit3 (978~992) 15 985, Bit11 (976~987) 12 981,
2720 18:36:05.796221 TX Bit4 (981~996) 16 988, Bit12 (975~987) 13 981,
2721 18:36:05.802534 TX Bit5 (984~996) 13 990, Bit13 (976~988) 13 982,
2722 18:36:05.806021 TX Bit6 (982~995) 14 988, Bit14 (975~987) 13 981,
2723 18:36:05.809391 TX Bit7 (982~994) 13 988, Bit15 (969~980) 12 974,
2724 18:36:05.809483
2725 18:36:05.812478 Write Rank0 MR14 =0x4
2726 18:36:05.821356
2727 18:36:05.821446 CH=1, VrefRange= 0, VrefLevel = 4
2728 18:36:05.828129 TX Bit0 (982~999) 18 990, Bit8 (971~985) 15 978,
2729 18:36:05.831380 TX Bit1 (981~995) 15 988, Bit9 (971~984) 14 977,
2730 18:36:05.838591 TX Bit2 (978~994) 17 986, Bit10 (974~987) 14 980,
2731 18:36:05.841963 TX Bit3 (977~992) 16 984, Bit11 (976~988) 13 982,
2732 18:36:05.844971 TX Bit4 (981~998) 18 989, Bit12 (975~988) 14 981,
2733 18:36:05.851271 TX Bit5 (983~998) 16 990, Bit13 (976~988) 13 982,
2734 18:36:05.854757 TX Bit6 (982~996) 15 989, Bit14 (974~988) 15 981,
2735 18:36:05.858228 TX Bit7 (982~995) 14 988, Bit15 (969~982) 14 975,
2736 18:36:05.858321
2737 18:36:05.861641 Write Rank0 MR14 =0x6
2738 18:36:05.870576
2739 18:36:05.870667 CH=1, VrefRange= 0, VrefLevel = 6
2740 18:36:05.877217 TX Bit0 (982~999) 18 990, Bit8 (970~985) 16 977,
2741 18:36:05.880072 TX Bit1 (980~996) 17 988, Bit9 (971~984) 14 977,
2742 18:36:05.886739 TX Bit2 (978~995) 18 986, Bit10 (973~988) 16 980,
2743 18:36:05.890435 TX Bit3 (977~993) 17 985, Bit11 (975~989) 15 982,
2744 18:36:05.893818 TX Bit4 (980~998) 19 989, Bit12 (974~989) 16 981,
2745 18:36:05.900353 TX Bit5 (983~998) 16 990, Bit13 (976~989) 14 982,
2746 18:36:05.903271 TX Bit6 (981~998) 18 989, Bit14 (973~989) 17 981,
2747 18:36:05.906880 TX Bit7 (981~996) 16 988, Bit15 (969~983) 15 976,
2748 18:36:05.906972
2749 18:36:05.910249 Write Rank0 MR14 =0x8
2750 18:36:05.919741
2751 18:36:05.919832 CH=1, VrefRange= 0, VrefLevel = 8
2752 18:36:05.926131 TX Bit0 (982~1000) 19 991, Bit8 (970~985) 16 977,
2753 18:36:05.929548 TX Bit1 (980~997) 18 988, Bit9 (971~985) 15 978,
2754 18:36:05.936208 TX Bit2 (978~996) 19 987, Bit10 (973~989) 17 981,
2755 18:36:05.939157 TX Bit3 (977~994) 18 985, Bit11 (974~990) 17 982,
2756 18:36:05.942677 TX Bit4 (980~999) 20 989, Bit12 (974~990) 17 982,
2757 18:36:05.949054 TX Bit5 (983~999) 17 991, Bit13 (975~990) 16 982,
2758 18:36:05.952676 TX Bit6 (981~998) 18 989, Bit14 (973~990) 18 981,
2759 18:36:05.956079 TX Bit7 (981~997) 17 989, Bit15 (968~983) 16 975,
2760 18:36:05.959400
2761 18:36:05.959502 Write Rank0 MR14 =0xa
2762 18:36:05.968593
2763 18:36:05.972068 CH=1, VrefRange= 0, VrefLevel = 10
2764 18:36:05.975739 TX Bit0 (982~1000) 19 991, Bit8 (970~986) 17 978,
2765 18:36:05.978635 TX Bit1 (980~998) 19 989, Bit9 (971~985) 15 978,
2766 18:36:05.984973 TX Bit2 (978~997) 20 987, Bit10 (972~990) 19 981,
2767 18:36:05.988222 TX Bit3 (977~994) 18 985, Bit11 (974~991) 18 982,
2768 18:36:05.991640 TX Bit4 (979~999) 21 989, Bit12 (973~991) 19 982,
2769 18:36:05.998087 TX Bit5 (983~999) 17 991, Bit13 (975~991) 17 983,
2770 18:36:06.001679 TX Bit6 (980~999) 20 989, Bit14 (974~991) 18 982,
2771 18:36:06.008022 TX Bit7 (980~998) 19 989, Bit15 (968~984) 17 976,
2772 18:36:06.008113
2773 18:36:06.008184 Write Rank0 MR14 =0xc
2774 18:36:06.017776
2775 18:36:06.021405 CH=1, VrefRange= 0, VrefLevel = 12
2776 18:36:06.024603 TX Bit0 (981~1001) 21 991, Bit8 (970~987) 18 978,
2777 18:36:06.027930 TX Bit1 (979~999) 21 989, Bit9 (970~985) 16 977,
2778 18:36:06.034182 TX Bit2 (977~997) 21 987, Bit10 (973~991) 19 982,
2779 18:36:06.037856 TX Bit3 (977~994) 18 985, Bit11 (974~991) 18 982,
2780 18:36:06.040908 TX Bit4 (979~1000) 22 989, Bit12 (972~992) 21 982,
2781 18:36:06.047801 TX Bit5 (982~999) 18 990, Bit13 (975~991) 17 983,
2782 18:36:06.050690 TX Bit6 (980~999) 20 989, Bit14 (973~992) 20 982,
2783 18:36:06.057396 TX Bit7 (980~998) 19 989, Bit15 (968~984) 17 976,
2784 18:36:06.057486
2785 18:36:06.057556 Write Rank0 MR14 =0xe
2786 18:36:06.067293
2787 18:36:06.070854 CH=1, VrefRange= 0, VrefLevel = 14
2788 18:36:06.074399 TX Bit0 (981~1001) 21 991, Bit8 (970~987) 18 978,
2789 18:36:06.077687 TX Bit1 (978~999) 22 988, Bit9 (970~986) 17 978,
2790 18:36:06.084043 TX Bit2 (978~998) 21 988, Bit10 (972~991) 20 981,
2791 18:36:06.087625 TX Bit3 (976~995) 20 985, Bit11 (973~991) 19 982,
2792 18:36:06.090949 TX Bit4 (979~1000) 22 989, Bit12 (972~992) 21 982,
2793 18:36:06.097250 TX Bit5 (982~1000) 19 991, Bit13 (975~991) 17 983,
2794 18:36:06.100621 TX Bit6 (980~999) 20 989, Bit14 (972~992) 21 982,
2795 18:36:06.106966 TX Bit7 (979~999) 21 989, Bit15 (968~985) 18 976,
2796 18:36:06.107056
2797 18:36:06.107125 Write Rank0 MR14 =0x10
2798 18:36:06.117088
2799 18:36:06.120190 CH=1, VrefRange= 0, VrefLevel = 16
2800 18:36:06.123836 TX Bit0 (981~1001) 21 991, Bit8 (970~988) 19 979,
2801 18:36:06.126909 TX Bit1 (978~1000) 23 989, Bit9 (970~986) 17 978,
2802 18:36:06.134063 TX Bit2 (977~999) 23 988, Bit10 (971~991) 21 981,
2803 18:36:06.137337 TX Bit3 (976~996) 21 986, Bit11 (973~992) 20 982,
2804 18:36:06.140726 TX Bit4 (979~1000) 22 989, Bit12 (972~992) 21 982,
2805 18:36:06.147063 TX Bit5 (981~1000) 20 990, Bit13 (973~992) 20 982,
2806 18:36:06.150467 TX Bit6 (979~1000) 22 989, Bit14 (972~992) 21 982,
2807 18:36:06.157173 TX Bit7 (979~999) 21 989, Bit15 (967~985) 19 976,
2808 18:36:06.157263
2809 18:36:06.157332 Write Rank0 MR14 =0x12
2810 18:36:06.166842
2811 18:36:06.170333 CH=1, VrefRange= 0, VrefLevel = 18
2812 18:36:06.173458 TX Bit0 (980~1002) 23 991, Bit8 (969~989) 21 979,
2813 18:36:06.177060 TX Bit1 (978~1000) 23 989, Bit9 (970~987) 18 978,
2814 18:36:06.183738 TX Bit2 (977~999) 23 988, Bit10 (971~991) 21 981,
2815 18:36:06.187018 TX Bit3 (976~996) 21 986, Bit11 (972~992) 21 982,
2816 18:36:06.190443 TX Bit4 (978~1000) 23 989, Bit12 (971~993) 23 982,
2817 18:36:06.196670 TX Bit5 (981~1001) 21 991, Bit13 (974~992) 19 983,
2818 18:36:06.200132 TX Bit6 (979~1000) 22 989, Bit14 (971~992) 22 981,
2819 18:36:06.207111 TX Bit7 (979~1000) 22 989, Bit15 (967~986) 20 976,
2820 18:36:06.207202
2821 18:36:06.207273 Write Rank0 MR14 =0x14
2822 18:36:06.217275
2823 18:36:06.220036 CH=1, VrefRange= 0, VrefLevel = 20
2824 18:36:06.223634 TX Bit0 (980~1002) 23 991, Bit8 (969~990) 22 979,
2825 18:36:06.227163 TX Bit1 (978~1000) 23 989, Bit9 (970~987) 18 978,
2826 18:36:06.233183 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
2827 18:36:06.236567 TX Bit3 (976~997) 22 986, Bit11 (973~992) 20 982,
2828 18:36:06.240421 TX Bit4 (978~1001) 24 989, Bit12 (972~993) 22 982,
2829 18:36:06.246768 TX Bit5 (980~1001) 22 990, Bit13 (973~992) 20 982,
2830 18:36:06.250309 TX Bit6 (978~1000) 23 989, Bit14 (971~993) 23 982,
2831 18:36:06.256509 TX Bit7 (979~1000) 22 989, Bit15 (967~986) 20 976,
2832 18:36:06.256602
2833 18:36:06.256745 Write Rank0 MR14 =0x16
2834 18:36:06.266951
2835 18:36:06.270093 CH=1, VrefRange= 0, VrefLevel = 22
2836 18:36:06.273401 TX Bit0 (979~1002) 24 990, Bit8 (969~990) 22 979,
2837 18:36:06.276709 TX Bit1 (977~1001) 25 989, Bit9 (969~988) 20 978,
2838 18:36:06.283420 TX Bit2 (977~1000) 24 988, Bit10 (970~992) 23 981,
2839 18:36:06.287276 TX Bit3 (976~998) 23 987, Bit11 (971~992) 22 981,
2840 18:36:06.290260 TX Bit4 (978~1001) 24 989, Bit12 (972~993) 22 982,
2841 18:36:06.297026 TX Bit5 (980~1001) 22 990, Bit13 (972~993) 22 982,
2842 18:36:06.300341 TX Bit6 (978~1001) 24 989, Bit14 (971~993) 23 982,
2843 18:36:06.306531 TX Bit7 (978~1000) 23 989, Bit15 (966~987) 22 976,
2844 18:36:06.306622
2845 18:36:06.306692 Write Rank0 MR14 =0x18
2846 18:36:06.317149
2847 18:36:06.320619 CH=1, VrefRange= 0, VrefLevel = 24
2848 18:36:06.323851 TX Bit0 (980~1003) 24 991, Bit8 (969~990) 22 979,
2849 18:36:06.327139 TX Bit1 (978~1001) 24 989, Bit9 (969~989) 21 979,
2850 18:36:06.334090 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
2851 18:36:06.337247 TX Bit3 (976~998) 23 987, Bit11 (971~993) 23 982,
2852 18:36:06.340259 TX Bit4 (977~1001) 25 989, Bit12 (971~993) 23 982,
2853 18:36:06.346960 TX Bit5 (979~1002) 24 990, Bit13 (972~993) 22 982,
2854 18:36:06.350493 TX Bit6 (978~1001) 24 989, Bit14 (971~993) 23 982,
2855 18:36:06.357130 TX Bit7 (978~1000) 23 989, Bit15 (966~987) 22 976,
2856 18:36:06.357222
2857 18:36:06.357294 Write Rank0 MR14 =0x1a
2858 18:36:06.367864
2859 18:36:06.367954 CH=1, VrefRange= 0, VrefLevel = 26
2860 18:36:06.374658 TX Bit0 (978~1003) 26 990, Bit8 (969~991) 23 980,
2861 18:36:06.377859 TX Bit1 (978~1001) 24 989, Bit9 (970~990) 21 980,
2862 18:36:06.384086 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
2863 18:36:06.387695 TX Bit3 (975~999) 25 987, Bit11 (971~993) 23 982,
2864 18:36:06.391316 TX Bit4 (977~1002) 26 989, Bit12 (970~994) 25 982,
2865 18:36:06.397497 TX Bit5 (979~1002) 24 990, Bit13 (972~993) 22 982,
2866 18:36:06.400714 TX Bit6 (978~1001) 24 989, Bit14 (970~994) 25 982,
2867 18:36:06.407542 TX Bit7 (978~1001) 24 989, Bit15 (966~988) 23 977,
2868 18:36:06.407634
2869 18:36:06.407705 Write Rank0 MR14 =0x1c
2870 18:36:06.417759
2871 18:36:06.421516 CH=1, VrefRange= 0, VrefLevel = 28
2872 18:36:06.424577 TX Bit0 (978~1004) 27 991, Bit8 (968~991) 24 979,
2873 18:36:06.428174 TX Bit1 (978~1001) 24 989, Bit9 (968~990) 23 979,
2874 18:36:06.435096 TX Bit2 (976~1001) 26 988, Bit10 (970~993) 24 981,
2875 18:36:06.437951 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
2876 18:36:06.441633 TX Bit4 (978~1002) 25 990, Bit12 (970~994) 25 982,
2877 18:36:06.448029 TX Bit5 (979~1003) 25 991, Bit13 (971~993) 23 982,
2878 18:36:06.451549 TX Bit6 (978~1001) 24 989, Bit14 (970~994) 25 982,
2879 18:36:06.458240 TX Bit7 (978~1001) 24 989, Bit15 (966~988) 23 977,
2880 18:36:06.458332
2881 18:36:06.458403 Write Rank0 MR14 =0x1e
2882 18:36:06.468639
2883 18:36:06.472038 CH=1, VrefRange= 0, VrefLevel = 30
2884 18:36:06.475239 TX Bit0 (978~1004) 27 991, Bit8 (968~991) 24 979,
2885 18:36:06.478328 TX Bit1 (977~1001) 25 989, Bit9 (969~991) 23 980,
2886 18:36:06.484946 TX Bit2 (976~1000) 25 988, Bit10 (969~993) 25 981,
2887 18:36:06.488561 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
2888 18:36:06.491693 TX Bit4 (978~1002) 25 990, Bit12 (970~993) 24 981,
2889 18:36:06.498494 TX Bit5 (979~1003) 25 991, Bit13 (971~994) 24 982,
2890 18:36:06.501871 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
2891 18:36:06.508452 TX Bit7 (978~1001) 24 989, Bit15 (965~987) 23 976,
2892 18:36:06.508543
2893 18:36:06.508614 Write Rank0 MR14 =0x20
2894 18:36:06.518747
2895 18:36:06.522431 CH=1, VrefRange= 0, VrefLevel = 32
2896 18:36:06.525744 TX Bit0 (978~1004) 27 991, Bit8 (968~992) 25 980,
2897 18:36:06.528763 TX Bit1 (977~1002) 26 989, Bit9 (968~991) 24 979,
2898 18:36:06.535523 TX Bit2 (976~1000) 25 988, Bit10 (970~993) 24 981,
2899 18:36:06.538584 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
2900 18:36:06.542035 TX Bit4 (978~1002) 25 990, Bit12 (970~993) 24 981,
2901 18:36:06.549233 TX Bit5 (978~1003) 26 990, Bit13 (971~994) 24 982,
2902 18:36:06.551858 TX Bit6 (977~1002) 26 989, Bit14 (970~993) 24 981,
2903 18:36:06.558497 TX Bit7 (978~1002) 25 990, Bit15 (965~987) 23 976,
2904 18:36:06.558586
2905 18:36:06.558655 Write Rank0 MR14 =0x22
2906 18:36:06.569466
2907 18:36:06.572381 CH=1, VrefRange= 0, VrefLevel = 34
2908 18:36:06.575874 TX Bit0 (978~1004) 27 991, Bit8 (968~992) 25 980,
2909 18:36:06.579083 TX Bit1 (977~1002) 26 989, Bit9 (968~991) 24 979,
2910 18:36:06.585959 TX Bit2 (976~1000) 25 988, Bit10 (970~993) 24 981,
2911 18:36:06.589280 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
2912 18:36:06.592153 TX Bit4 (978~1002) 25 990, Bit12 (970~993) 24 981,
2913 18:36:06.599313 TX Bit5 (978~1003) 26 990, Bit13 (971~994) 24 982,
2914 18:36:06.602432 TX Bit6 (977~1002) 26 989, Bit14 (970~993) 24 981,
2915 18:36:06.609209 TX Bit7 (978~1002) 25 990, Bit15 (965~987) 23 976,
2916 18:36:06.609297
2917 18:36:06.612368 wait MRW command Rank0 MR14 =0x24 fired (1)
2918 18:36:06.615194 Write Rank0 MR14 =0x24
2919 18:36:06.623328
2920 18:36:06.626802 CH=1, VrefRange= 0, VrefLevel = 36
2921 18:36:06.630088 TX Bit0 (978~1004) 27 991, Bit8 (968~992) 25 980,
2922 18:36:06.633257 TX Bit1 (977~1002) 26 989, Bit9 (968~991) 24 979,
2923 18:36:06.640053 TX Bit2 (976~1000) 25 988, Bit10 (970~993) 24 981,
2924 18:36:06.643208 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
2925 18:36:06.646750 TX Bit4 (978~1002) 25 990, Bit12 (970~993) 24 981,
2926 18:36:06.653352 TX Bit5 (978~1003) 26 990, Bit13 (971~994) 24 982,
2927 18:36:06.656963 TX Bit6 (977~1002) 26 989, Bit14 (970~993) 24 981,
2928 18:36:06.662833 TX Bit7 (978~1002) 25 990, Bit15 (965~987) 23 976,
2929 18:36:06.662925
2930 18:36:06.662996 Write Rank0 MR14 =0x26
2931 18:36:06.673498
2932 18:36:06.677322 CH=1, VrefRange= 0, VrefLevel = 38
2933 18:36:06.680023 TX Bit0 (978~1004) 27 991, Bit8 (968~992) 25 980,
2934 18:36:06.683754 TX Bit1 (977~1002) 26 989, Bit9 (968~991) 24 979,
2935 18:36:06.690627 TX Bit2 (976~1000) 25 988, Bit10 (970~993) 24 981,
2936 18:36:06.693624 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
2937 18:36:06.697001 TX Bit4 (978~1002) 25 990, Bit12 (970~993) 24 981,
2938 18:36:06.703784 TX Bit5 (978~1003) 26 990, Bit13 (971~994) 24 982,
2939 18:36:06.706615 TX Bit6 (977~1002) 26 989, Bit14 (970~993) 24 981,
2940 18:36:06.713623 TX Bit7 (978~1002) 25 990, Bit15 (965~987) 23 976,
2941 18:36:06.713716
2942 18:36:06.713787
2943 18:36:06.717085 TX Vref found, early break! 371< 378
2944 18:36:06.720073 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2945 18:36:06.723904 u1DelayCellOfst[0]=5 cells (4 PI)
2946 18:36:06.727053 u1DelayCellOfst[1]=2 cells (2 PI)
2947 18:36:06.730002 u1DelayCellOfst[2]=1 cells (1 PI)
2948 18:36:06.733809 u1DelayCellOfst[3]=0 cells (0 PI)
2949 18:36:06.737101 u1DelayCellOfst[4]=3 cells (3 PI)
2950 18:36:06.740198 u1DelayCellOfst[5]=3 cells (3 PI)
2951 18:36:06.740291 u1DelayCellOfst[6]=2 cells (2 PI)
2952 18:36:06.743815 u1DelayCellOfst[7]=3 cells (3 PI)
2953 18:36:06.746873 Byte0, DQ PI dly=987, DQM PI dly= 989
2954 18:36:06.753398 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2955 18:36:06.753490
2956 18:36:06.756624 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2957 18:36:06.756716
2958 18:36:06.760151 u1DelayCellOfst[8]=5 cells (4 PI)
2959 18:36:06.763247 u1DelayCellOfst[9]=3 cells (3 PI)
2960 18:36:06.766585 u1DelayCellOfst[10]=6 cells (5 PI)
2961 18:36:06.770217 u1DelayCellOfst[11]=7 cells (6 PI)
2962 18:36:06.773316 u1DelayCellOfst[12]=6 cells (5 PI)
2963 18:36:06.776559 u1DelayCellOfst[13]=7 cells (6 PI)
2964 18:36:06.779784 u1DelayCellOfst[14]=6 cells (5 PI)
2965 18:36:06.783381 u1DelayCellOfst[15]=0 cells (0 PI)
2966 18:36:06.786445 Byte1, DQ PI dly=976, DQM PI dly= 979
2967 18:36:06.790267 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 16)
2968 18:36:06.790360
2969 18:36:06.793373 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 16)
2970 18:36:06.793465
2971 18:36:06.796393 Write Rank0 MR14 =0x20
2972 18:36:06.796484
2973 18:36:06.799609 Final TX Range 0 Vref 32
2974 18:36:06.799701
2975 18:36:06.806527 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2976 18:36:06.806619
2977 18:36:06.812883 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2978 18:36:06.819805 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2979 18:36:06.826634 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2980 18:36:06.826726 Write Rank0 MR3 =0xb0
2981 18:36:06.830076 DramC Write-DBI on
2982 18:36:06.830166 ==
2983 18:36:06.833519 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2984 18:36:06.836391 fsp= 1, odt_onoff= 1, Byte mode= 0
2985 18:36:06.840059 ==
2986 18:36:06.843419 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2987 18:36:06.843511
2988 18:36:06.846612 Begin, DQ Scan Range 699~763
2989 18:36:06.846707
2990 18:36:06.846778
2991 18:36:06.846843 TX Vref Scan disable
2992 18:36:06.850021 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2993 18:36:06.852927 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2994 18:36:06.859810 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2995 18:36:06.863054 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2996 18:36:06.866099 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2997 18:36:06.869949 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2998 18:36:06.873077 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2999 18:36:06.876042 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3000 18:36:06.879393 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3001 18:36:06.882887 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3002 18:36:06.886272 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3003 18:36:06.889260 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3004 18:36:06.893025 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3005 18:36:06.896307 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3006 18:36:06.899244 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3007 18:36:06.903069 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3008 18:36:06.905782 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3009 18:36:06.909260 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3010 18:36:06.912742 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3011 18:36:06.916232 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3012 18:36:06.919131 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3013 18:36:06.926082 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3014 18:36:06.929479 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3015 18:36:06.932499 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3016 18:36:06.936074 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3017 18:36:06.942887 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3018 18:36:06.946237 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3019 18:36:06.949159 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3020 18:36:06.952317 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3021 18:36:06.955697 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3022 18:36:06.959388 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3023 18:36:06.962496 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3024 18:36:06.965848 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3025 18:36:06.969543 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3026 18:36:06.972167 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3027 18:36:06.975605 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3028 18:36:06.978974 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3029 18:36:06.982469 Byte0, DQ PI dly=735, DQM PI dly= 735
3030 18:36:06.989076 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
3031 18:36:06.989167
3032 18:36:06.992521 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
3033 18:36:06.992613
3034 18:36:06.995892 Byte1, DQ PI dly=724, DQM PI dly= 724
3035 18:36:06.998766 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
3036 18:36:06.998857
3037 18:36:07.005427 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
3038 18:36:07.005519
3039 18:36:07.012057 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3040 18:36:07.018758 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3041 18:36:07.025167 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3042 18:36:07.025259 Write Rank0 MR3 =0x30
3043 18:36:07.028578 DramC Write-DBI off
3044 18:36:07.028669
3045 18:36:07.028740 [DATLAT]
3046 18:36:07.032038 Freq=1600, CH1 RK0, use_rxtx_scan=0
3047 18:36:07.032129
3048 18:36:07.035612 DATLAT Default: 0xf
3049 18:36:07.035703 7, 0xFFFF, sum=0
3050 18:36:07.038772 8, 0xFFFF, sum=0
3051 18:36:07.038865 9, 0xFFFF, sum=0
3052 18:36:07.042063 10, 0xFFFF, sum=0
3053 18:36:07.042155 11, 0xFFFF, sum=0
3054 18:36:07.045542 12, 0xFFFF, sum=0
3055 18:36:07.045632 13, 0xFFFF, sum=0
3056 18:36:07.048612 14, 0x0, sum=1
3057 18:36:07.048703 15, 0x0, sum=2
3058 18:36:07.048776 16, 0x0, sum=3
3059 18:36:07.051930 17, 0x0, sum=4
3060 18:36:07.055368 pattern=2 first_step=14 total pass=5 best_step=16
3061 18:36:07.055479 ==
3062 18:36:07.062193 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3063 18:36:07.065054 fsp= 1, odt_onoff= 1, Byte mode= 0
3064 18:36:07.065144 ==
3065 18:36:07.068249 Start DQ dly to find pass range UseTestEngine =1
3066 18:36:07.071757 x-axis: bit #, y-axis: DQ dly (-127~63)
3067 18:36:07.075094 RX Vref Scan = 1
3068 18:36:07.181360
3069 18:36:07.181528 RX Vref found, early break!
3070 18:36:07.181604
3071 18:36:07.188443 Final RX Vref 11, apply to both rank0 and 1
3072 18:36:07.188589 ==
3073 18:36:07.191262 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3074 18:36:07.194729 fsp= 1, odt_onoff= 1, Byte mode= 0
3075 18:36:07.194823 ==
3076 18:36:07.194894 DQS Delay:
3077 18:36:07.198230 DQS0 = 0, DQS1 = 0
3078 18:36:07.198322 DQM Delay:
3079 18:36:07.201991 DQM0 = 20, DQM1 = 19
3080 18:36:07.202158 DQ Delay:
3081 18:36:07.204945 DQ0 =22, DQ1 =21, DQ2 =19, DQ3 =17
3082 18:36:07.208299 DQ4 =21, DQ5 =22, DQ6 =24, DQ7 =20
3083 18:36:07.211749 DQ8 =16, DQ9 =15, DQ10 =20, DQ11 =22
3084 18:36:07.214930 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3085 18:36:07.215061
3086 18:36:07.215152
3087 18:36:07.215237
3088 18:36:07.218449 [DramC_TX_OE_Calibration] TA2
3089 18:36:07.221805 Original DQ_B0 (3 6) =30, OEN = 27
3090 18:36:07.225170 Original DQ_B1 (3 6) =30, OEN = 27
3091 18:36:07.228423 23, 0x0, End_B0=23 End_B1=23
3092 18:36:07.228584 24, 0x0, End_B0=24 End_B1=24
3093 18:36:07.231220 25, 0x0, End_B0=25 End_B1=25
3094 18:36:07.234538 26, 0x0, End_B0=26 End_B1=26
3095 18:36:07.238262 27, 0x0, End_B0=27 End_B1=27
3096 18:36:07.238496 28, 0x0, End_B0=28 End_B1=28
3097 18:36:07.241447 29, 0x0, End_B0=29 End_B1=29
3098 18:36:07.244894 30, 0x0, End_B0=30 End_B1=30
3099 18:36:07.248275 31, 0xFFFF, End_B0=30 End_B1=30
3100 18:36:07.254857 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3101 18:36:07.258027 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3102 18:36:07.258172
3103 18:36:07.258280
3104 18:36:07.261394 Write Rank0 MR23 =0x3f
3105 18:36:07.261521 [DQSOSC]
3106 18:36:07.271230 [DQSOSCAuto] RK0, (LSB)MR18= 0xbdbd, (MSB)MR19= 0x202, tDQSOscB0 = 449 ps tDQSOscB1 = 449 ps
3107 18:36:07.274934 CH1_RK0: MR19=0x202, MR18=0xBDBD, DQSOSC=449, MR23=63, INC=12, DEC=18
3108 18:36:07.278129 Write Rank0 MR23 =0x3f
3109 18:36:07.278223 [DQSOSC]
3110 18:36:07.288053 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3111 18:36:07.291296 CH1 RK0: MR19=202, MR18=BFBF
3112 18:36:07.294352 [RankSwap] Rank num 2, (Multi 1), Rank 1
3113 18:36:07.294450 Write Rank0 MR2 =0xad
3114 18:36:07.297974 [Write Leveling]
3115 18:36:07.300961 delay byte0 byte1 byte2 byte3
3116 18:36:07.301051
3117 18:36:07.301122 10 0 0
3118 18:36:07.304534 11 0 0
3119 18:36:07.304657 12 0 0
3120 18:36:07.304761 13 0 0
3121 18:36:07.307826 14 0 0
3122 18:36:07.307920 15 0 0
3123 18:36:07.310706 16 0 0
3124 18:36:07.310830 17 0 0
3125 18:36:07.310935 18 0 0
3126 18:36:07.314343 19 0 0
3127 18:36:07.314472 20 0 0
3128 18:36:07.317923 21 0 0
3129 18:36:07.318058 22 0 0
3130 18:36:07.321346 23 0 0
3131 18:36:07.321439 24 0 0
3132 18:36:07.321511 25 0 ff
3133 18:36:07.324212 26 0 ff
3134 18:36:07.324304 27 0 ff
3135 18:36:07.327708 28 0 ff
3136 18:36:07.327801 29 0 ff
3137 18:36:07.330934 30 0 ff
3138 18:36:07.331027 31 0 ff
3139 18:36:07.331099 32 0 ff
3140 18:36:07.334384 33 0 ff
3141 18:36:07.334505 34 ff ff
3142 18:36:07.337898 35 ff ff
3143 18:36:07.338005 36 ff ff
3144 18:36:07.341400 37 ff ff
3145 18:36:07.341493 38 ff ff
3146 18:36:07.344465 39 ff ff
3147 18:36:07.344593 40 ff ff
3148 18:36:07.347560 pass bytecount = 0xff (0xff: all bytes pass)
3149 18:36:07.347645
3150 18:36:07.350964 DQS0 dly: 34
3151 18:36:07.351056 DQS1 dly: 25
3152 18:36:07.354124 Write Rank0 MR2 =0x2d
3153 18:36:07.357410 [RankSwap] Rank num 2, (Multi 1), Rank 0
3154 18:36:07.357505 Write Rank1 MR1 =0xd6
3155 18:36:07.361088 [Gating]
3156 18:36:07.361182 ==
3157 18:36:07.364008 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3158 18:36:07.367614 fsp= 1, odt_onoff= 1, Byte mode= 0
3159 18:36:07.367709 ==
3160 18:36:07.374459 3 1 0 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
3161 18:36:07.377498 3 1 4 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3162 18:36:07.380640 3 1 8 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3163 18:36:07.387294 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3164 18:36:07.390852 3 1 16 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3165 18:36:07.394328 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3166 18:36:07.401405 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3167 18:36:07.404160 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3168 18:36:07.407524 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3169 18:36:07.410772 3 2 4 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3170 18:36:07.417567 3 2 8 |b0a 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3171 18:36:07.420411 3 2 12 |3d3d 2c2c |(11 11)(11 0) |(1 1)(0 0)| 0
3172 18:36:07.424208 3 2 16 |3d3d 201 |(11 11)(11 11) |(1 1)(0 0)| 0
3173 18:36:07.430910 3 2 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3174 18:36:07.434581 3 2 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3175 18:36:07.437783 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3176 18:36:07.443944 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3177 18:36:07.447183 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3178 18:36:07.450735 3 3 8 |909 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3179 18:36:07.457303 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3180 18:36:07.460448 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3181 18:36:07.463878 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3182 18:36:07.467601 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3183 18:36:07.473931 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3184 18:36:07.477368 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3185 18:36:07.481022 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3186 18:36:07.487553 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3187 18:36:07.490869 3 4 8 |2121 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3188 18:36:07.493838 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3189 18:36:07.500840 3 4 16 |3d3d 2625 |(11 11)(11 11) |(1 1)(1 1)| 0
3190 18:36:07.503997 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3191 18:36:07.507343 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 18:36:07.514085 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 18:36:07.516911 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3194 18:36:07.520445 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3195 18:36:07.527336 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3196 18:36:07.530172 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3197 18:36:07.534250 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3198 18:36:07.540096 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3199 18:36:07.543509 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3200 18:36:07.547299 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3201 18:36:07.550566 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3202 18:36:07.557171 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3203 18:36:07.560328 [Byte 0] Lead/lag Transition tap number (3)
3204 18:36:07.563503 [Byte 1] Lead/lag falling Transition (3, 6, 0)
3205 18:36:07.567093 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3206 18:36:07.574005 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3207 18:36:07.576810 [Byte 1] Lead/lag Transition tap number (3)
3208 18:36:07.580349 3 6 12 |4646 201f |(0 0)(11 11) |(0 0)(0 0)| 0
3209 18:36:07.583571 [Byte 0]First pass (3, 6, 12)
3210 18:36:07.586787 3 6 16 |4646 404 |(0 0)(11 11) |(0 0)(0 0)| 0
3211 18:36:07.590371 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3212 18:36:07.593871 [Byte 1]First pass (3, 6, 20)
3213 18:36:07.596884 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3214 18:36:07.603817 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3215 18:36:07.606732 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3216 18:36:07.610172 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3217 18:36:07.612806 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3218 18:36:07.619896 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3219 18:36:07.623392 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3220 18:36:07.626170 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3221 18:36:07.629782 All bytes gating window > 1UI, Early break!
3222 18:36:07.630162
3223 18:36:07.632551 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3224 18:36:07.632930
3225 18:36:07.635875 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 6)
3226 18:36:07.636227
3227 18:36:07.639379
3228 18:36:07.639778
3229 18:36:07.642795 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3230 18:36:07.643158
3231 18:36:07.646362 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3232 18:36:07.646831
3233 18:36:07.647109
3234 18:36:07.649697 Write Rank1 MR1 =0x56
3235 18:36:07.650161
3236 18:36:07.652927 best RODT dly(2T, 0.5T) = (2, 2)
3237 18:36:07.653281
3238 18:36:07.655955 best RODT dly(2T, 0.5T) = (2, 3)
3239 18:36:07.656305 ==
3240 18:36:07.659117 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3241 18:36:07.662880 fsp= 1, odt_onoff= 1, Byte mode= 0
3242 18:36:07.663432 ==
3243 18:36:07.666500 Start DQ dly to find pass range UseTestEngine =0
3244 18:36:07.673088 x-axis: bit #, y-axis: DQ dly (-127~63)
3245 18:36:07.673554 RX Vref Scan = 0
3246 18:36:07.675966 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3247 18:36:07.679691 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3248 18:36:07.683168 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3249 18:36:07.686761 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3250 18:36:07.687228 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3251 18:36:07.689923 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3252 18:36:07.692832 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3253 18:36:07.696199 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3254 18:36:07.699787 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3255 18:36:07.703093 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3256 18:36:07.706285 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3257 18:36:07.709755 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3258 18:36:07.710230 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3259 18:36:07.713010 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3260 18:36:07.716153 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3261 18:36:07.719718 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3262 18:36:07.722183 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3263 18:36:07.725759 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3264 18:36:07.729216 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3265 18:36:07.732970 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3266 18:36:07.733436 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3267 18:36:07.735821 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3268 18:36:07.738930 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3269 18:36:07.741979 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3270 18:36:07.745577 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3271 18:36:07.748606 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3272 18:36:07.752142 0, [0] xxxoxxxx xoxxxxxo [MSB]
3273 18:36:07.752503 1, [0] xxooxxxx ooxxxxxo [MSB]
3274 18:36:07.755235 2, [0] xxooxxxx ooxxxxxo [MSB]
3275 18:36:07.758939 3, [0] xxoooxxo oooxxxxo [MSB]
3276 18:36:07.762122 4, [0] oooooxoo oooxoxxo [MSB]
3277 18:36:07.765537 5, [0] oooooooo ooooooxo [MSB]
3278 18:36:07.769198 32, [0] oooooooo ooooooox [MSB]
3279 18:36:07.772115 33, [0] oooooooo ooooooox [MSB]
3280 18:36:07.772477 34, [0] oooooooo ooooooox [MSB]
3281 18:36:07.775505 35, [0] oooxoooo xxooooox [MSB]
3282 18:36:07.778730 36, [0] oooxoooo xxooooox [MSB]
3283 18:36:07.781811 37, [0] ooxxoooo xxooooox [MSB]
3284 18:36:07.785552 38, [0] ooxxoooo xxooooox [MSB]
3285 18:36:07.788801 39, [0] oxxxxoox xxooooox [MSB]
3286 18:36:07.791826 40, [0] oxxxxoox xxxoooox [MSB]
3287 18:36:07.792293 41, [0] oxxxxoox xxxxxoox [MSB]
3288 18:36:07.795494 42, [0] xxxxxxxx xxxxxxxx [MSB]
3289 18:36:07.798641 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3290 18:36:07.801833 iDelay=42, Bit 1, Center 21 (4 ~ 38) 35
3291 18:36:07.805105 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
3292 18:36:07.812012 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3293 18:36:07.815154 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36
3294 18:36:07.818281 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
3295 18:36:07.821534 iDelay=42, Bit 6, Center 22 (4 ~ 41) 38
3296 18:36:07.825545 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3297 18:36:07.828139 iDelay=42, Bit 8, Center 17 (1 ~ 34) 34
3298 18:36:07.831488 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3299 18:36:07.835339 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3300 18:36:07.838408 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3301 18:36:07.841517 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3302 18:36:07.845238 iDelay=42, Bit 13, Center 23 (5 ~ 41) 37
3303 18:36:07.848012 iDelay=42, Bit 14, Center 23 (6 ~ 41) 36
3304 18:36:07.854655 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3305 18:36:07.855143 ==
3306 18:36:07.857736 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3307 18:36:07.861290 fsp= 1, odt_onoff= 1, Byte mode= 0
3308 18:36:07.861670 ==
3309 18:36:07.864532 DQS Delay:
3310 18:36:07.864908 DQS0 = 0, DQS1 = 0
3311 18:36:07.865203 DQM Delay:
3312 18:36:07.867946 DQM0 = 20, DQM1 = 19
3313 18:36:07.868326 DQ Delay:
3314 18:36:07.870903 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3315 18:36:07.874245 DQ4 =20, DQ5 =23, DQ6 =22, DQ7 =20
3316 18:36:07.878031 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3317 18:36:07.881120 DQ12 =22, DQ13 =23, DQ14 =23, DQ15 =14
3318 18:36:07.881515
3319 18:36:07.881910
3320 18:36:07.884683 DramC Write-DBI off
3321 18:36:07.885178 ==
3322 18:36:07.887301 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3323 18:36:07.891246 fsp= 1, odt_onoff= 1, Byte mode= 0
3324 18:36:07.891833 ==
3325 18:36:07.897775 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3326 18:36:07.898279
3327 18:36:07.901280 Begin, DQ Scan Range 921~1177
3328 18:36:07.901779
3329 18:36:07.902184
3330 18:36:07.902560 TX Vref Scan disable
3331 18:36:07.904620 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3332 18:36:07.907714 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3333 18:36:07.910697 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3334 18:36:07.917325 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3335 18:36:07.920890 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3336 18:36:07.924135 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3337 18:36:07.927682 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3338 18:36:07.930390 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3339 18:36:07.934138 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3340 18:36:07.937276 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3341 18:36:07.940584 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3342 18:36:07.943857 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3343 18:36:07.947143 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3344 18:36:07.950646 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3345 18:36:07.953934 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3346 18:36:07.957589 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3347 18:36:07.960853 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3348 18:36:07.963752 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3349 18:36:07.970849 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3350 18:36:07.974194 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3351 18:36:07.977338 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3352 18:36:07.980832 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3353 18:36:07.983530 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3354 18:36:07.987465 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3355 18:36:07.990876 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3356 18:36:07.993879 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3357 18:36:07.996818 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3358 18:36:08.000552 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3359 18:36:08.003565 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3360 18:36:08.007002 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3361 18:36:08.010080 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3362 18:36:08.013470 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3363 18:36:08.016820 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3364 18:36:08.020328 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3365 18:36:08.027101 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3366 18:36:08.030671 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3367 18:36:08.033874 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3368 18:36:08.036684 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3369 18:36:08.040114 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3370 18:36:08.043261 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3371 18:36:08.047016 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3372 18:36:08.050366 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3373 18:36:08.053195 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3374 18:36:08.057076 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3375 18:36:08.060342 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3376 18:36:08.063337 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3377 18:36:08.066765 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3378 18:36:08.070169 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3379 18:36:08.073730 969 |3 6 9|[0] xxxxxxxx oxxxxxxo [MSB]
3380 18:36:08.076520 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
3381 18:36:08.080128 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
3382 18:36:08.083357 972 |3 6 12|[0] xxxxxxxx oooxxxoo [MSB]
3383 18:36:08.087203 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3384 18:36:08.093673 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3385 18:36:08.097219 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3386 18:36:08.100002 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3387 18:36:08.103229 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3388 18:36:08.106801 978 |3 6 18|[0] xxoooxxx oooooooo [MSB]
3389 18:36:08.110321 979 |3 6 19|[0] ooooooox oooooooo [MSB]
3390 18:36:08.113540 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3391 18:36:08.116351 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3392 18:36:08.119834 988 |3 6 28|[0] oooooooo ooooooox [MSB]
3393 18:36:08.123573 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3394 18:36:08.126350 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3395 18:36:08.133232 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3396 18:36:08.136698 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3397 18:36:08.139847 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3398 18:36:08.143112 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3399 18:36:08.146463 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3400 18:36:08.149845 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3401 18:36:08.153199 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3402 18:36:08.156912 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3403 18:36:08.160271 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3404 18:36:08.163187 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3405 18:36:08.166910 1001 |3 6 41|[0] oxxxxoxx xxxxxxxx [MSB]
3406 18:36:08.169942 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
3407 18:36:08.173060 Byte0, DQ PI dly=988, DQM PI dly= 988
3408 18:36:08.179775 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3409 18:36:08.180258
3410 18:36:08.182554 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3411 18:36:08.182933
3412 18:36:08.185814 Byte1, DQ PI dly=979, DQM PI dly= 979
3413 18:36:08.189354 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
3414 18:36:08.189837
3415 18:36:08.196559 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
3416 18:36:08.197060
3417 18:36:08.197460 ==
3418 18:36:08.199312 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3419 18:36:08.202990 fsp= 1, odt_onoff= 1, Byte mode= 0
3420 18:36:08.203530 ==
3421 18:36:08.209501 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3422 18:36:08.209998
3423 18:36:08.212910 Begin, DQ Scan Range 955~1019
3424 18:36:08.213303 Write Rank1 MR14 =0x0
3425 18:36:08.221802
3426 18:36:08.222270 CH=1, VrefRange= 0, VrefLevel = 0
3427 18:36:08.228443 TX Bit0 (982~998) 17 990, Bit8 (971~985) 15 978,
3428 18:36:08.231997 TX Bit1 (981~996) 16 988, Bit9 (972~984) 13 978,
3429 18:36:08.238424 TX Bit2 (979~994) 16 986, Bit10 (975~986) 12 980,
3430 18:36:08.241897 TX Bit3 (978~990) 13 984, Bit11 (976~987) 12 981,
3431 18:36:08.244965 TX Bit4 (981~996) 16 988, Bit12 (976~986) 11 981,
3432 18:36:08.251806 TX Bit5 (983~998) 16 990, Bit13 (976~988) 13 982,
3433 18:36:08.255400 TX Bit6 (982~997) 16 989, Bit14 (977~986) 10 981,
3434 18:36:08.259010 TX Bit7 (983~994) 12 988, Bit15 (970~979) 10 974,
3435 18:36:08.259513
3436 18:36:08.261885 Write Rank1 MR14 =0x2
3437 18:36:08.270934
3438 18:36:08.271461 CH=1, VrefRange= 0, VrefLevel = 2
3439 18:36:08.277407 TX Bit0 (983~998) 16 990, Bit8 (971~985) 15 978,
3440 18:36:08.280742 TX Bit1 (981~997) 17 989, Bit9 (972~985) 14 978,
3441 18:36:08.287047 TX Bit2 (979~995) 17 987, Bit10 (975~986) 12 980,
3442 18:36:08.290807 TX Bit3 (978~991) 14 984, Bit11 (975~988) 14 981,
3443 18:36:08.293704 TX Bit4 (980~997) 18 988, Bit12 (976~986) 11 981,
3444 18:36:08.300404 TX Bit5 (982~998) 17 990, Bit13 (976~989) 14 982,
3445 18:36:08.303758 TX Bit6 (981~998) 18 989, Bit14 (976~986) 11 981,
3446 18:36:08.307615 TX Bit7 (983~995) 13 989, Bit15 (969~980) 12 974,
3447 18:36:08.310480
3448 18:36:08.311014 Write Rank1 MR14 =0x4
3449 18:36:08.319807
3450 18:36:08.320339 CH=1, VrefRange= 0, VrefLevel = 4
3451 18:36:08.326290 TX Bit0 (983~999) 17 991, Bit8 (970~986) 17 978,
3452 18:36:08.330074 TX Bit1 (980~998) 19 989, Bit9 (971~985) 15 978,
3453 18:36:08.336354 TX Bit2 (978~995) 18 986, Bit10 (975~987) 13 981,
3454 18:36:08.339943 TX Bit3 (978~991) 14 984, Bit11 (975~989) 15 982,
3455 18:36:08.342957 TX Bit4 (980~997) 18 988, Bit12 (975~987) 13 981,
3456 18:36:08.349348 TX Bit5 (982~999) 18 990, Bit13 (975~990) 16 982,
3457 18:36:08.352670 TX Bit6 (981~998) 18 989, Bit14 (976~986) 11 981,
3458 18:36:08.355765 TX Bit7 (982~996) 15 989, Bit15 (969~982) 14 975,
3459 18:36:08.359318
3460 18:36:08.359889 Write Rank1 MR14 =0x6
3461 18:36:08.368004
3462 18:36:08.368436 CH=1, VrefRange= 0, VrefLevel = 6
3463 18:36:08.374861 TX Bit0 (981~999) 19 990, Bit8 (970~986) 17 978,
3464 18:36:08.378095 TX Bit1 (980~998) 19 989, Bit9 (971~986) 16 978,
3465 18:36:08.384427 TX Bit2 (978~996) 19 987, Bit10 (974~988) 15 981,
3466 18:36:08.387817 TX Bit3 (977~992) 16 984, Bit11 (975~989) 15 982,
3467 18:36:08.391518 TX Bit4 (980~998) 19 989, Bit12 (975~989) 15 982,
3468 18:36:08.398218 TX Bit5 (981~999) 19 990, Bit13 (975~991) 17 983,
3469 18:36:08.401447 TX Bit6 (980~999) 20 989, Bit14 (975~988) 14 981,
3470 18:36:08.404771 TX Bit7 (982~996) 15 989, Bit15 (969~983) 15 976,
3471 18:36:08.408041
3472 18:36:08.408515 Write Rank1 MR14 =0x8
3473 18:36:08.417551
3474 18:36:08.417902 CH=1, VrefRange= 0, VrefLevel = 8
3475 18:36:08.423937 TX Bit0 (980~1000) 21 990, Bit8 (970~986) 17 978,
3476 18:36:08.427420 TX Bit1 (979~998) 20 988, Bit9 (970~986) 17 978,
3477 18:36:08.434557 TX Bit2 (978~997) 20 987, Bit10 (973~988) 16 980,
3478 18:36:08.437212 TX Bit3 (977~993) 17 985, Bit11 (975~991) 17 983,
3479 18:36:08.441196 TX Bit4 (979~998) 20 988, Bit12 (975~990) 16 982,
3480 18:36:08.447182 TX Bit5 (981~1000) 20 990, Bit13 (974~991) 18 982,
3481 18:36:08.450705 TX Bit6 (980~999) 20 989, Bit14 (974~988) 15 981,
3482 18:36:08.454447 TX Bit7 (982~998) 17 990, Bit15 (969~984) 16 976,
3483 18:36:08.457426
3484 18:36:08.457801 Write Rank1 MR14 =0xa
3485 18:36:08.467011
3486 18:36:08.467564 CH=1, VrefRange= 0, VrefLevel = 10
3487 18:36:08.473896 TX Bit0 (981~1000) 20 990, Bit8 (970~987) 18 978,
3488 18:36:08.476891 TX Bit1 (979~999) 21 989, Bit9 (970~986) 17 978,
3489 18:36:08.483700 TX Bit2 (978~998) 21 988, Bit10 (973~989) 17 981,
3490 18:36:08.487055 TX Bit3 (977~994) 18 985, Bit11 (974~991) 18 982,
3491 18:36:08.490235 TX Bit4 (979~999) 21 989, Bit12 (973~990) 18 981,
3492 18:36:08.497018 TX Bit5 (980~1000) 21 990, Bit13 (974~992) 19 983,
3493 18:36:08.500000 TX Bit6 (979~999) 21 989, Bit14 (973~989) 17 981,
3494 18:36:08.507247 TX Bit7 (981~998) 18 989, Bit15 (969~984) 16 976,
3495 18:36:08.507821
3496 18:36:08.508267 Write Rank1 MR14 =0xc
3497 18:36:08.516948
3498 18:36:08.519843 CH=1, VrefRange= 0, VrefLevel = 12
3499 18:36:08.523103 TX Bit0 (980~1001) 22 990, Bit8 (970~988) 19 979,
3500 18:36:08.526586 TX Bit1 (979~999) 21 989, Bit9 (970~988) 19 979,
3501 18:36:08.533224 TX Bit2 (978~998) 21 988, Bit10 (972~991) 20 981,
3502 18:36:08.536841 TX Bit3 (977~995) 19 986, Bit11 (973~991) 19 982,
3503 18:36:08.539986 TX Bit4 (979~999) 21 989, Bit12 (973~991) 19 982,
3504 18:36:08.545835 TX Bit5 (980~1001) 22 990, Bit13 (973~992) 20 982,
3505 18:36:08.549368 TX Bit6 (979~1000) 22 989, Bit14 (974~989) 16 981,
3506 18:36:08.556242 TX Bit7 (980~998) 19 989, Bit15 (968~984) 17 976,
3507 18:36:08.556779
3508 18:36:08.557108 Write Rank1 MR14 =0xe
3509 18:36:08.566211
3510 18:36:08.570044 CH=1, VrefRange= 0, VrefLevel = 14
3511 18:36:08.573046 TX Bit0 (980~1001) 22 990, Bit8 (970~988) 19 979,
3512 18:36:08.575578 TX Bit1 (979~1000) 22 989, Bit9 (970~988) 19 979,
3513 18:36:08.582924 TX Bit2 (978~998) 21 988, Bit10 (972~991) 20 981,
3514 18:36:08.586507 TX Bit3 (977~996) 20 986, Bit11 (973~992) 20 982,
3515 18:36:08.589257 TX Bit4 (978~999) 22 988, Bit12 (973~991) 19 982,
3516 18:36:08.596023 TX Bit5 (980~1001) 22 990, Bit13 (973~992) 20 982,
3517 18:36:08.599486 TX Bit6 (978~1000) 23 989, Bit14 (972~991) 20 981,
3518 18:36:08.605968 TX Bit7 (980~999) 20 989, Bit15 (967~985) 19 976,
3519 18:36:08.606487
3520 18:36:08.606808 Write Rank1 MR14 =0x10
3521 18:36:08.616256
3522 18:36:08.619795 CH=1, VrefRange= 0, VrefLevel = 16
3523 18:36:08.622443 TX Bit0 (980~1002) 23 991, Bit8 (969~989) 21 979,
3524 18:36:08.626159 TX Bit1 (978~1000) 23 989, Bit9 (970~988) 19 979,
3525 18:36:08.632870 TX Bit2 (978~999) 22 988, Bit10 (971~991) 21 981,
3526 18:36:08.636001 TX Bit3 (976~997) 22 986, Bit11 (973~992) 20 982,
3527 18:36:08.639450 TX Bit4 (978~1000) 23 989, Bit12 (972~991) 20 981,
3528 18:36:08.646253 TX Bit5 (979~1001) 23 990, Bit13 (973~993) 21 983,
3529 18:36:08.648994 TX Bit6 (978~1000) 23 989, Bit14 (972~991) 20 981,
3530 18:36:08.655950 TX Bit7 (980~999) 20 989, Bit15 (967~985) 19 976,
3531 18:36:08.656434
3532 18:36:08.656754 Write Rank1 MR14 =0x12
3533 18:36:08.666362
3534 18:36:08.669306 CH=1, VrefRange= 0, VrefLevel = 18
3535 18:36:08.672453 TX Bit0 (979~1002) 24 990, Bit8 (969~990) 22 979,
3536 18:36:08.675937 TX Bit1 (978~1000) 23 989, Bit9 (970~990) 21 980,
3537 18:36:08.683220 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
3538 18:36:08.686136 TX Bit3 (976~997) 22 986, Bit11 (973~992) 20 982,
3539 18:36:08.689366 TX Bit4 (978~1000) 23 989, Bit12 (972~992) 21 982,
3540 18:36:08.695445 TX Bit5 (979~1002) 24 990, Bit13 (973~993) 21 983,
3541 18:36:08.699523 TX Bit6 (978~1000) 23 989, Bit14 (971~992) 22 981,
3542 18:36:08.706279 TX Bit7 (980~1000) 21 990, Bit15 (967~986) 20 976,
3543 18:36:08.706788
3544 18:36:08.707116 Write Rank1 MR14 =0x14
3545 18:36:08.716476
3546 18:36:08.719485 CH=1, VrefRange= 0, VrefLevel = 20
3547 18:36:08.723132 TX Bit0 (979~1003) 25 991, Bit8 (969~991) 23 980,
3548 18:36:08.726825 TX Bit1 (978~1001) 24 989, Bit9 (970~990) 21 980,
3549 18:36:08.732723 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
3550 18:36:08.736324 TX Bit3 (976~998) 23 987, Bit11 (971~993) 23 982,
3551 18:36:08.739454 TX Bit4 (978~1001) 24 989, Bit12 (971~992) 22 981,
3552 18:36:08.746064 TX Bit5 (979~1002) 24 990, Bit13 (972~993) 22 982,
3553 18:36:08.749432 TX Bit6 (978~1001) 24 989, Bit14 (971~992) 22 981,
3554 18:36:08.756117 TX Bit7 (979~1000) 22 989, Bit15 (967~986) 20 976,
3555 18:36:08.756497
3556 18:36:08.756792 Write Rank1 MR14 =0x16
3557 18:36:08.766638
3558 18:36:08.770312 CH=1, VrefRange= 0, VrefLevel = 22
3559 18:36:08.773615 TX Bit0 (979~1003) 25 991, Bit8 (969~991) 23 980,
3560 18:36:08.776877 TX Bit1 (978~1001) 24 989, Bit9 (969~991) 23 980,
3561 18:36:08.783232 TX Bit2 (977~999) 23 988, Bit10 (970~992) 23 981,
3562 18:36:08.786412 TX Bit3 (976~998) 23 987, Bit11 (971~993) 23 982,
3563 18:36:08.789671 TX Bit4 (978~1001) 24 989, Bit12 (971~992) 22 981,
3564 18:36:08.796123 TX Bit5 (978~1003) 26 990, Bit13 (972~994) 23 983,
3565 18:36:08.799585 TX Bit6 (978~1001) 24 989, Bit14 (971~992) 22 981,
3566 18:36:08.805872 TX Bit7 (979~1000) 22 989, Bit15 (966~987) 22 976,
3567 18:36:08.806371
3568 18:36:08.806778 Write Rank1 MR14 =0x18
3569 18:36:08.817329
3570 18:36:08.820644 CH=1, VrefRange= 0, VrefLevel = 24
3571 18:36:08.823585 TX Bit0 (978~1004) 27 991, Bit8 (968~991) 24 979,
3572 18:36:08.827081 TX Bit1 (978~1002) 25 990, Bit9 (969~991) 23 980,
3573 18:36:08.833445 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
3574 18:36:08.837228 TX Bit3 (975~998) 24 986, Bit11 (971~993) 23 982,
3575 18:36:08.839982 TX Bit4 (978~1002) 25 990, Bit12 (971~993) 23 982,
3576 18:36:08.846607 TX Bit5 (978~1003) 26 990, Bit13 (972~993) 22 982,
3577 18:36:08.850379 TX Bit6 (978~1002) 25 990, Bit14 (971~993) 23 982,
3578 18:36:08.856808 TX Bit7 (979~1001) 23 990, Bit15 (966~987) 22 976,
3579 18:36:08.857244
3580 18:36:08.857671 Write Rank1 MR14 =0x1a
3581 18:36:08.867797
3582 18:36:08.868323 CH=1, VrefRange= 0, VrefLevel = 26
3583 18:36:08.875056 TX Bit0 (979~1004) 26 991, Bit8 (968~992) 25 980,
3584 18:36:08.877775 TX Bit1 (978~1002) 25 990, Bit9 (969~991) 23 980,
3585 18:36:08.884355 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
3586 18:36:08.887269 TX Bit3 (975~999) 25 987, Bit11 (971~994) 24 982,
3587 18:36:08.890681 TX Bit4 (977~1002) 26 989, Bit12 (971~993) 23 982,
3588 18:36:08.897394 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3589 18:36:08.900949 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
3590 18:36:08.908068 TX Bit7 (978~1002) 25 990, Bit15 (966~988) 23 977,
3591 18:36:08.908608
3592 18:36:08.908942 Write Rank1 MR14 =0x1c
3593 18:36:08.918490
3594 18:36:08.921742 CH=1, VrefRange= 0, VrefLevel = 28
3595 18:36:08.925186 TX Bit0 (978~1005) 28 991, Bit8 (968~992) 25 980,
3596 18:36:08.928300 TX Bit1 (978~1003) 26 990, Bit9 (969~992) 24 980,
3597 18:36:08.934946 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
3598 18:36:08.938471 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3599 18:36:08.941624 TX Bit4 (978~1002) 25 990, Bit12 (971~993) 23 982,
3600 18:36:08.947868 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3601 18:36:08.951042 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
3602 18:36:08.957855 TX Bit7 (978~1002) 25 990, Bit15 (966~989) 24 977,
3603 18:36:08.958359
3604 18:36:08.958683 Write Rank1 MR14 =0x1e
3605 18:36:08.968761
3606 18:36:08.972394 CH=1, VrefRange= 0, VrefLevel = 30
3607 18:36:08.975574 TX Bit0 (978~1005) 28 991, Bit8 (968~991) 24 979,
3608 18:36:08.979140 TX Bit1 (977~1003) 27 990, Bit9 (969~991) 23 980,
3609 18:36:08.985631 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
3610 18:36:08.988914 TX Bit3 (974~999) 26 986, Bit11 (970~994) 25 982,
3611 18:36:08.992329 TX Bit4 (978~1002) 25 990, Bit12 (970~994) 25 982,
3612 18:36:08.999441 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3613 18:36:09.002516 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
3614 18:36:09.008743 TX Bit7 (978~1002) 25 990, Bit15 (964~989) 26 976,
3615 18:36:09.009261
3616 18:36:09.009583 Write Rank1 MR14 =0x20
3617 18:36:09.020029
3618 18:36:09.022855 CH=1, VrefRange= 0, VrefLevel = 32
3619 18:36:09.026458 TX Bit0 (979~1005) 27 992, Bit8 (968~991) 24 979,
3620 18:36:09.029760 TX Bit1 (978~1003) 26 990, Bit9 (968~991) 24 979,
3621 18:36:09.036371 TX Bit2 (976~1001) 26 988, Bit10 (970~993) 24 981,
3622 18:36:09.039901 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3623 18:36:09.042954 TX Bit4 (978~1003) 26 990, Bit12 (970~994) 25 982,
3624 18:36:09.049976 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3625 18:36:09.052935 TX Bit6 (977~1004) 28 990, Bit14 (970~994) 25 982,
3626 18:36:09.059301 TX Bit7 (978~1003) 26 990, Bit15 (965~989) 25 977,
3627 18:36:09.059839
3628 18:36:09.060182 Write Rank1 MR14 =0x22
3629 18:36:09.070556
3630 18:36:09.073301 CH=1, VrefRange= 0, VrefLevel = 34
3631 18:36:09.077028 TX Bit0 (979~1005) 27 992, Bit8 (968~991) 24 979,
3632 18:36:09.080426 TX Bit1 (978~1003) 26 990, Bit9 (968~991) 24 979,
3633 18:36:09.087019 TX Bit2 (976~1001) 26 988, Bit10 (970~993) 24 981,
3634 18:36:09.090218 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3635 18:36:09.093298 TX Bit4 (978~1003) 26 990, Bit12 (970~994) 25 982,
3636 18:36:09.100381 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3637 18:36:09.103269 TX Bit6 (977~1004) 28 990, Bit14 (970~994) 25 982,
3638 18:36:09.110044 TX Bit7 (978~1003) 26 990, Bit15 (965~989) 25 977,
3639 18:36:09.110550
3640 18:36:09.110875 Write Rank1 MR14 =0x24
3641 18:36:09.120644
3642 18:36:09.123965 CH=1, VrefRange= 0, VrefLevel = 36
3643 18:36:09.127189 TX Bit0 (979~1005) 27 992, Bit8 (968~991) 24 979,
3644 18:36:09.130839 TX Bit1 (978~1003) 26 990, Bit9 (968~991) 24 979,
3645 18:36:09.137401 TX Bit2 (976~1001) 26 988, Bit10 (970~993) 24 981,
3646 18:36:09.140803 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3647 18:36:09.143522 TX Bit4 (978~1003) 26 990, Bit12 (970~994) 25 982,
3648 18:36:09.150181 TX Bit5 (978~1004) 27 991, Bit13 (971~994) 24 982,
3649 18:36:09.153664 TX Bit6 (977~1004) 28 990, Bit14 (970~994) 25 982,
3650 18:36:09.160075 TX Bit7 (978~1003) 26 990, Bit15 (965~989) 25 977,
3651 18:36:09.160227
3652 18:36:09.160311
3653 18:36:09.163225 TX Vref found, early break! 385< 386
3654 18:36:09.166952 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3655 18:36:09.169975 u1DelayCellOfst[0]=6 cells (5 PI)
3656 18:36:09.173588 u1DelayCellOfst[1]=3 cells (3 PI)
3657 18:36:09.176800 u1DelayCellOfst[2]=1 cells (1 PI)
3658 18:36:09.179936 u1DelayCellOfst[3]=0 cells (0 PI)
3659 18:36:09.183270 u1DelayCellOfst[4]=3 cells (3 PI)
3660 18:36:09.187061 u1DelayCellOfst[5]=5 cells (4 PI)
3661 18:36:09.190061 u1DelayCellOfst[6]=3 cells (3 PI)
3662 18:36:09.190178 u1DelayCellOfst[7]=3 cells (3 PI)
3663 18:36:09.193436 Byte0, DQ PI dly=987, DQM PI dly= 989
3664 18:36:09.200166 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3665 18:36:09.200286
3666 18:36:09.203022 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3667 18:36:09.203140
3668 18:36:09.206393 u1DelayCellOfst[8]=2 cells (2 PI)
3669 18:36:09.209655 u1DelayCellOfst[9]=2 cells (2 PI)
3670 18:36:09.213325 u1DelayCellOfst[10]=5 cells (4 PI)
3671 18:36:09.216438 u1DelayCellOfst[11]=6 cells (5 PI)
3672 18:36:09.219822 u1DelayCellOfst[12]=6 cells (5 PI)
3673 18:36:09.223191 u1DelayCellOfst[13]=6 cells (5 PI)
3674 18:36:09.226673 u1DelayCellOfst[14]=6 cells (5 PI)
3675 18:36:09.230084 u1DelayCellOfst[15]=0 cells (0 PI)
3676 18:36:09.233444 Byte1, DQ PI dly=977, DQM PI dly= 979
3677 18:36:09.236828 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3678 18:36:09.237181
3679 18:36:09.240236 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3680 18:36:09.240606
3681 18:36:09.243448 Write Rank1 MR14 =0x20
3682 18:36:09.243800
3683 18:36:09.246574 Final TX Range 0 Vref 32
3684 18:36:09.246926
3685 18:36:09.253487 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3686 18:36:09.254032
3687 18:36:09.260286 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3688 18:36:09.266255 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3689 18:36:09.273046 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3690 18:36:09.273251 Write Rank1 MR3 =0xb0
3691 18:36:09.276561 DramC Write-DBI on
3692 18:36:09.276734 ==
3693 18:36:09.282610 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3694 18:36:09.286197 fsp= 1, odt_onoff= 1, Byte mode= 0
3695 18:36:09.286556 ==
3696 18:36:09.290025 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3697 18:36:09.290381
3698 18:36:09.292883 Begin, DQ Scan Range 699~763
3699 18:36:09.293486
3700 18:36:09.293900
3701 18:36:09.294181 TX Vref Scan disable
3702 18:36:09.299382 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3703 18:36:09.302773 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3704 18:36:09.306184 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3705 18:36:09.309005 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3706 18:36:09.312566 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3707 18:36:09.316102 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3708 18:36:09.319581 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3709 18:36:09.322675 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3710 18:36:09.325825 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3711 18:36:09.329321 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3712 18:36:09.332374 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3713 18:36:09.335770 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3714 18:36:09.339399 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3715 18:36:09.342998 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3716 18:36:09.345514 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3717 18:36:09.349368 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3718 18:36:09.352937 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3719 18:36:09.355674 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3720 18:36:09.359347 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3721 18:36:09.366474 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3722 18:36:09.369276 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3723 18:36:09.372346 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3724 18:36:09.376026 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3725 18:36:09.379598 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3726 18:36:09.385661 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3727 18:36:09.389391 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3728 18:36:09.392775 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3729 18:36:09.395491 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3730 18:36:09.399136 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3731 18:36:09.402734 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3732 18:36:09.405575 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3733 18:36:09.409085 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3734 18:36:09.412427 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3735 18:36:09.415795 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3736 18:36:09.418990 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3737 18:36:09.421848 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3738 18:36:09.425465 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
3739 18:36:09.429023 Byte0, DQ PI dly=735, DQM PI dly= 735
3740 18:36:09.435224 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
3741 18:36:09.435655
3742 18:36:09.438972 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
3743 18:36:09.439381
3744 18:36:09.442464 Byte1, DQ PI dly=724, DQM PI dly= 724
3745 18:36:09.445435 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
3746 18:36:09.445822
3747 18:36:09.451912 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
3748 18:36:09.452297
3749 18:36:09.458802 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3750 18:36:09.465345 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3751 18:36:09.472064 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3752 18:36:09.475346 Write Rank1 MR3 =0x30
3753 18:36:09.475754 DramC Write-DBI off
3754 18:36:09.476050
3755 18:36:09.476327 [DATLAT]
3756 18:36:09.478814 Freq=1600, CH1 RK1, use_rxtx_scan=0
3757 18:36:09.479196
3758 18:36:09.482297 DATLAT Default: 0x10
3759 18:36:09.482789 7, 0xFFFF, sum=0
3760 18:36:09.485437 8, 0xFFFF, sum=0
3761 18:36:09.485822 9, 0xFFFF, sum=0
3762 18:36:09.489218 10, 0xFFFF, sum=0
3763 18:36:09.489711 11, 0xFFFF, sum=0
3764 18:36:09.492113 12, 0xFFFF, sum=0
3765 18:36:09.492498 13, 0xFFFF, sum=0
3766 18:36:09.495827 14, 0x0, sum=1
3767 18:36:09.496318 15, 0x0, sum=2
3768 18:36:09.498737 16, 0x0, sum=3
3769 18:36:09.499230 17, 0x0, sum=4
3770 18:36:09.502373 pattern=2 first_step=14 total pass=5 best_step=16
3771 18:36:09.502855 ==
3772 18:36:09.509215 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3773 18:36:09.512009 fsp= 1, odt_onoff= 1, Byte mode= 0
3774 18:36:09.512524 ==
3775 18:36:09.515646 Start DQ dly to find pass range UseTestEngine =1
3776 18:36:09.519164 x-axis: bit #, y-axis: DQ dly (-127~63)
3777 18:36:09.522636 RX Vref Scan = 0
3778 18:36:09.525377 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3779 18:36:09.528952 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3780 18:36:09.529480 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3781 18:36:09.531910 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3782 18:36:09.535526 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3783 18:36:09.538522 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3784 18:36:09.542535 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3785 18:36:09.545283 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3786 18:36:09.548942 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3787 18:36:09.551654 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3788 18:36:09.552098 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3789 18:36:09.555245 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3790 18:36:09.558444 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3791 18:36:09.562546 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3792 18:36:09.565409 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3793 18:36:09.568246 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3794 18:36:09.571484 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3795 18:36:09.575076 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3796 18:36:09.575675 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3797 18:36:09.578618 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3798 18:36:09.581725 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3799 18:36:09.585238 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3800 18:36:09.588187 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3801 18:36:09.591893 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3802 18:36:09.595154 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3803 18:36:09.595836 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3804 18:36:09.598404 0, [0] xxooxxxx ooxxxxxo [MSB]
3805 18:36:09.602202 1, [0] xxooxxxx ooxxxxxo [MSB]
3806 18:36:09.605035 2, [0] xxooxxxx ooxxxxxo [MSB]
3807 18:36:09.608353 3, [0] oxooxxxo oooxxxxo [MSB]
3808 18:36:09.611533 4, [0] oooooxxo ooooooxo [MSB]
3809 18:36:09.615566 32, [0] oooooooo ooooooox [MSB]
3810 18:36:09.618308 33, [0] oooooooo ooooooox [MSB]
3811 18:36:09.621790 34, [0] oooooooo ooooooox [MSB]
3812 18:36:09.624771 35, [0] oooxoooo xxooooox [MSB]
3813 18:36:09.628929 36, [0] oooxoooo xxooooox [MSB]
3814 18:36:09.629461 37, [0] ooxxoooo xxooooox [MSB]
3815 18:36:09.631401 38, [0] ooxxoooo xxooooox [MSB]
3816 18:36:09.634893 39, [0] ooxxooox xxooooox [MSB]
3817 18:36:09.638726 40, [0] oxxxxoox xxxoooox [MSB]
3818 18:36:09.641533 41, [0] xxxxxxox xxxxxxxx [MSB]
3819 18:36:09.644794 42, [0] xxxxxxxx xxxxxxxx [MSB]
3820 18:36:09.648032 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
3821 18:36:09.651471 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3822 18:36:09.654874 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3823 18:36:09.658428 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3824 18:36:09.661705 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3825 18:36:09.665145 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3826 18:36:09.668316 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3827 18:36:09.671614 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3828 18:36:09.675345 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3829 18:36:09.678125 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3830 18:36:09.681583 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3831 18:36:09.688315 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3832 18:36:09.691528 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3833 18:36:09.695055 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3834 18:36:09.698554 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3835 18:36:09.701460 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3836 18:36:09.701988 ==
3837 18:36:09.707971 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3838 18:36:09.708485 fsp= 1, odt_onoff= 1, Byte mode= 0
3839 18:36:09.711786 ==
3840 18:36:09.712302 DQS Delay:
3841 18:36:09.712626 DQS0 = 0, DQS1 = 0
3842 18:36:09.715014 DQM Delay:
3843 18:36:09.715580 DQM0 = 20, DQM1 = 19
3844 18:36:09.718372 DQ Delay:
3845 18:36:09.720898 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =16
3846 18:36:09.721313 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3847 18:36:09.724686 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3848 18:36:09.728346 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
3849 18:36:09.731069
3850 18:36:09.731517
3851 18:36:09.731846
3852 18:36:09.732146 [DramC_TX_OE_Calibration] TA2
3853 18:36:09.734725 Original DQ_B0 (3 6) =30, OEN = 27
3854 18:36:09.738032 Original DQ_B1 (3 6) =30, OEN = 27
3855 18:36:09.741205 23, 0x0, End_B0=23 End_B1=23
3856 18:36:09.744707 24, 0x0, End_B0=24 End_B1=24
3857 18:36:09.747648 25, 0x0, End_B0=25 End_B1=25
3858 18:36:09.748074 26, 0x0, End_B0=26 End_B1=26
3859 18:36:09.751262 27, 0x0, End_B0=27 End_B1=27
3860 18:36:09.754503 28, 0x0, End_B0=28 End_B1=28
3861 18:36:09.758038 29, 0x0, End_B0=29 End_B1=29
3862 18:36:09.761178 30, 0x0, End_B0=30 End_B1=30
3863 18:36:09.761671 31, 0xFFFF, End_B0=30 End_B1=30
3864 18:36:09.767573 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3865 18:36:09.774617 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3866 18:36:09.775137
3867 18:36:09.775512
3868 18:36:09.775823 Write Rank1 MR23 =0x3f
3869 18:36:09.778359 [DQSOSC]
3870 18:36:09.784560 [DQSOSCAuto] RK1, (LSB)MR18= 0xcbcb, (MSB)MR19= 0x202, tDQSOscB0 = 440 ps tDQSOscB1 = 440 ps
3871 18:36:09.790938 CH1_RK1: MR19=0x202, MR18=0xCBCB, DQSOSC=440, MR23=63, INC=12, DEC=19
3872 18:36:09.794618 Write Rank1 MR23 =0x3f
3873 18:36:09.795176 [DQSOSC]
3874 18:36:09.800974 [DQSOSCAuto] RK1, (LSB)MR18= 0xcaca, (MSB)MR19= 0x202, tDQSOscB0 = 441 ps tDQSOscB1 = 441 ps
3875 18:36:09.804321 CH1 RK1: MR19=202, MR18=CACA
3876 18:36:09.807281 [RxdqsGatingPostProcess] freq 1600
3877 18:36:09.814249 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3878 18:36:09.814763 Rank: 0
3879 18:36:09.817333 best DQS0 dly(2T, 0.5T) = (2, 6)
3880 18:36:09.820975 best DQS1 dly(2T, 0.5T) = (2, 6)
3881 18:36:09.824141 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3882 18:36:09.827533 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3883 18:36:09.828058 Rank: 1
3884 18:36:09.830656 best DQS0 dly(2T, 0.5T) = (2, 5)
3885 18:36:09.833889 best DQS1 dly(2T, 0.5T) = (2, 6)
3886 18:36:09.837823 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3887 18:36:09.841030 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3888 18:36:09.843963 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3889 18:36:09.847927 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3890 18:36:09.850745 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3891 18:36:09.851134
3892 18:36:09.851461
3893 18:36:09.853892 [Calibration Summary] Freqency 1600
3894 18:36:09.857900 CH 0, Rank 0
3895 18:36:09.858284 All Pass.
3896 18:36:09.858594
3897 18:36:09.861226 CH 0, Rank 1
3898 18:36:09.861711 All Pass.
3899 18:36:09.862010
3900 18:36:09.862287 CH 1, Rank 0
3901 18:36:09.862555 All Pass.
3902 18:36:09.864102
3903 18:36:09.864482 CH 1, Rank 1
3904 18:36:09.864780 All Pass.
3905 18:36:09.865060
3906 18:36:09.870938 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3907 18:36:09.877598 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3908 18:36:09.884121 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3909 18:36:09.887626 Write Rank0 MR3 =0xb0
3910 18:36:09.894563 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3911 18:36:09.900956 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3912 18:36:09.907547 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3913 18:36:09.910999 Write Rank1 MR3 =0xb0
3914 18:36:09.918145 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3915 18:36:09.924227 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3916 18:36:09.930941 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3917 18:36:09.933855 Write Rank0 MR3 =0xb0
3918 18:36:09.937644 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3919 18:36:09.946916 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3920 18:36:09.954114 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3921 18:36:09.954551 Write Rank1 MR3 =0xb0
3922 18:36:09.957069 DramC Write-DBI on
3923 18:36:09.960429 [GetDramInforAfterCalByMRR] Vendor 6.
3924 18:36:09.963963 [GetDramInforAfterCalByMRR] Revision 505.
3925 18:36:09.964372 MR8 1111
3926 18:36:09.970806 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3927 18:36:09.971302 MR8 1111
3928 18:36:09.973719 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3929 18:36:09.977406 MR8 1111
3930 18:36:09.980303 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3931 18:36:09.980712 MR8 1111
3932 18:36:09.987171 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3933 18:36:09.997362 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3934 18:36:09.997855 Write Rank0 MR13 =0xd0
3935 18:36:10.000750 Write Rank1 MR13 =0xd0
3936 18:36:10.001233 Write Rank0 MR13 =0xd0
3937 18:36:10.003604 Write Rank1 MR13 =0xd0
3938 18:36:10.007449 Save calibration result to emmc
3939 18:36:10.007971
3940 18:36:10.008297
3941 18:36:10.010396 [DramcModeReg_Check] Freq_1600, FSP_1
3942 18:36:10.010880 FSP_1, CH_0, RK0
3943 18:36:10.013903 Write Rank0 MR13 =0xd8
3944 18:36:10.017064 MR12 = 0x5e (global = 0x5e) match
3945 18:36:10.020344 MR14 = 0x1c (global = 0x1c) match
3946 18:36:10.020854 FSP_1, CH_0, RK1
3947 18:36:10.024110 Write Rank1 MR13 =0xd8
3948 18:36:10.027238 MR12 = 0x5a (global = 0x5a) match
3949 18:36:10.030745 MR14 = 0x22 (global = 0x22) match
3950 18:36:10.031262 FSP_1, CH_1, RK0
3951 18:36:10.033936 Write Rank0 MR13 =0xd8
3952 18:36:10.037403 MR12 = 0x60 (global = 0x60) match
3953 18:36:10.040410 MR14 = 0x20 (global = 0x20) match
3954 18:36:10.040929 FSP_1, CH_1, RK1
3955 18:36:10.043573 Write Rank1 MR13 =0xd8
3956 18:36:10.046779 MR12 = 0x5e (global = 0x5e) match
3957 18:36:10.051089 MR14 = 0x20 (global = 0x20) match
3958 18:36:10.051920
3959 18:36:10.053282 [MEM_TEST] 02: After DFS, before run time config
3960 18:36:10.065879 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3961 18:36:10.066417
3962 18:36:10.066762 [TA2_TEST]
3963 18:36:10.067072 === TA2 HW
3964 18:36:10.069223 TA2 PAT: XTALK
3965 18:36:10.072527 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3966 18:36:10.079199 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3967 18:36:10.082567 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3968 18:36:10.088397 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3969 18:36:10.088946
3970 18:36:10.089328
3971 18:36:10.089638 Settings after calibration
3972 18:36:10.089934
3973 18:36:10.091515 [DramcRunTimeConfig]
3974 18:36:10.095832 TransferPLLToSPMControl - MODE SW PHYPLL
3975 18:36:10.098233 TX_TRACKING: ON
3976 18:36:10.098650 RX_TRACKING: ON
3977 18:36:10.099080 HW_GATING: ON
3978 18:36:10.101890 HW_GATING DBG: OFF
3979 18:36:10.102409 ddr_geometry:1
3980 18:36:10.104825 ddr_geometry:1
3981 18:36:10.105241 ddr_geometry:1
3982 18:36:10.108514 ddr_geometry:1
3983 18:36:10.108896 ddr_geometry:1
3984 18:36:10.109194 ddr_geometry:1
3985 18:36:10.111885 ddr_geometry:1
3986 18:36:10.112267 ddr_geometry:1
3987 18:36:10.115119 High Freq DUMMY_READ_FOR_TRACKING: ON
3988 18:36:10.118549 ZQCS_ENABLE_LP4: OFF
3989 18:36:10.121780 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3990 18:36:10.125099 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3991 18:36:10.125589 SPM_CONTROL_AFTERK: ON
3992 18:36:10.128147 IMPEDANCE_TRACKING: ON
3993 18:36:10.128530 TEMP_SENSOR: ON
3994 18:36:10.131542 PER_BANK_REFRESH: ON
3995 18:36:10.134910 HW_SAVE_FOR_SR: ON
3996 18:36:10.138414 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3997 18:36:10.138908 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3998 18:36:10.145126 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3999 18:36:10.145525 Read ODT Tracking: ON
4000 18:36:10.147951 =========================
4001 18:36:10.148336
4002 18:36:10.148632 [TA2_TEST]
4003 18:36:10.151507 === TA2 HW
4004 18:36:10.154952 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4005 18:36:10.158534 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4006 18:36:10.164727 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4007 18:36:10.168107 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4008 18:36:10.168493
4009 18:36:10.171516 [MEM_TEST] 03: After run time config
4010 18:36:10.183960 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4011 18:36:10.186857 [complex_mem_test] start addr:0x40024000, len:131072
4012 18:36:10.391183 1st complex R/W mem test pass
4013 18:36:10.398206 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4014 18:36:10.401342 sync preloader write leveling
4015 18:36:10.404569 sync preloader cbt_mr12
4016 18:36:10.405136 sync preloader cbt_clk_dly
4017 18:36:10.407819 sync preloader cbt_cmd_dly
4018 18:36:10.411258 sync preloader cbt_cs
4019 18:36:10.414615 sync preloader cbt_ca_perbit_delay
4020 18:36:10.415134 sync preloader clk_delay
4021 18:36:10.417538 sync preloader dqs_delay
4022 18:36:10.420801 sync preloader u1Gating2T_Save
4023 18:36:10.424013 sync preloader u1Gating05T_Save
4024 18:36:10.427559 sync preloader u1Gatingfine_tune_Save
4025 18:36:10.430481 sync preloader u1Gatingucpass_count_Save
4026 18:36:10.433629 sync preloader u1TxWindowPerbitVref_Save
4027 18:36:10.436783 sync preloader u1TxCenter_min_Save
4028 18:36:10.440756 sync preloader u1TxCenter_max_Save
4029 18:36:10.443391 sync preloader u1Txwin_center_Save
4030 18:36:10.446624 sync preloader u1Txfirst_pass_Save
4031 18:36:10.450402 sync preloader u1Txlast_pass_Save
4032 18:36:10.450495 sync preloader u1RxDatlat_Save
4033 18:36:10.456682 sync preloader u1RxWinPerbitVref_Save
4034 18:36:10.460217 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4035 18:36:10.463353 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4036 18:36:10.466737 sync preloader delay_cell_unit
4037 18:36:10.473560 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4038 18:36:10.476869 sync preloader write leveling
4039 18:36:10.476994 sync preloader cbt_mr12
4040 18:36:10.480448 sync preloader cbt_clk_dly
4041 18:36:10.483134 sync preloader cbt_cmd_dly
4042 18:36:10.483333 sync preloader cbt_cs
4043 18:36:10.486576 sync preloader cbt_ca_perbit_delay
4044 18:36:10.489967 sync preloader clk_delay
4045 18:36:10.493193 sync preloader dqs_delay
4046 18:36:10.493285 sync preloader u1Gating2T_Save
4047 18:36:10.496788 sync preloader u1Gating05T_Save
4048 18:36:10.499741 sync preloader u1Gatingfine_tune_Save
4049 18:36:10.503002 sync preloader u1Gatingucpass_count_Save
4050 18:36:10.510002 sync preloader u1TxWindowPerbitVref_Save
4051 18:36:10.510101 sync preloader u1TxCenter_min_Save
4052 18:36:10.513374 sync preloader u1TxCenter_max_Save
4053 18:36:10.516647 sync preloader u1Txwin_center_Save
4054 18:36:10.519671 sync preloader u1Txfirst_pass_Save
4055 18:36:10.522991 sync preloader u1Txlast_pass_Save
4056 18:36:10.526841 sync preloader u1RxDatlat_Save
4057 18:36:10.529653 sync preloader u1RxWinPerbitVref_Save
4058 18:36:10.533335 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4059 18:36:10.536722 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4060 18:36:10.539752 sync preloader delay_cell_unit
4061 18:36:10.546811 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4062 18:36:10.550155 sync preloader write leveling
4063 18:36:10.553421 sync preloader cbt_mr12
4064 18:36:10.556726 sync preloader cbt_clk_dly
4065 18:36:10.556896 sync preloader cbt_cmd_dly
4066 18:36:10.560034 sync preloader cbt_cs
4067 18:36:10.563146 sync preloader cbt_ca_perbit_delay
4068 18:36:10.563319 sync preloader clk_delay
4069 18:36:10.566475 sync preloader dqs_delay
4070 18:36:10.570132 sync preloader u1Gating2T_Save
4071 18:36:10.573146 sync preloader u1Gating05T_Save
4072 18:36:10.576245 sync preloader u1Gatingfine_tune_Save
4073 18:36:10.580255 sync preloader u1Gatingucpass_count_Save
4074 18:36:10.583230 sync preloader u1TxWindowPerbitVref_Save
4075 18:36:10.586425 sync preloader u1TxCenter_min_Save
4076 18:36:10.589954 sync preloader u1TxCenter_max_Save
4077 18:36:10.593313 sync preloader u1Txwin_center_Save
4078 18:36:10.596560 sync preloader u1Txfirst_pass_Save
4079 18:36:10.600205 sync preloader u1Txlast_pass_Save
4080 18:36:10.603922 sync preloader u1RxDatlat_Save
4081 18:36:10.606571 sync preloader u1RxWinPerbitVref_Save
4082 18:36:10.610363 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4083 18:36:10.613446 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4084 18:36:10.616646 sync preloader delay_cell_unit
4085 18:36:10.619930 just_for_test_dump_coreboot_params dump all params
4086 18:36:10.622913 dump source = 0x0
4087 18:36:10.623295 dump params frequency:1600
4088 18:36:10.626215 dump params rank number:2
4089 18:36:10.626689
4090 18:36:10.629422 dump params write leveling
4091 18:36:10.632962 write leveling[0][0][0] = 0x21
4092 18:36:10.636015 write leveling[0][0][1] = 0x18
4093 18:36:10.636400 write leveling[0][1][0] = 0x1a
4094 18:36:10.639396 write leveling[0][1][1] = 0x18
4095 18:36:10.642827 write leveling[1][0][0] = 0x20
4096 18:36:10.646133 write leveling[1][0][1] = 0x18
4097 18:36:10.649571 write leveling[1][1][0] = 0x22
4098 18:36:10.653480 write leveling[1][1][1] = 0x19
4099 18:36:10.653975 dump params cbt_cs
4100 18:36:10.656056 cbt_cs[0][0] = 0x8
4101 18:36:10.656441 cbt_cs[0][1] = 0x8
4102 18:36:10.659454 cbt_cs[1][0] = 0xc
4103 18:36:10.659832 cbt_cs[1][1] = 0xc
4104 18:36:10.662662 dump params cbt_mr12
4105 18:36:10.663019 cbt_mr12[0][0] = 0x1e
4106 18:36:10.666348 cbt_mr12[0][1] = 0x1a
4107 18:36:10.669947 cbt_mr12[1][0] = 0x20
4108 18:36:10.670302 cbt_mr12[1][1] = 0x1e
4109 18:36:10.672806 dump params tx window
4110 18:36:10.675925 tx_center_min[0][0][0] = 982
4111 18:36:10.676278 tx_center_max[0][0][0] = 988
4112 18:36:10.679214 tx_center_min[0][0][1] = 975
4113 18:36:10.683065 tx_center_max[0][0][1] = 981
4114 18:36:10.686314 tx_center_min[0][1][0] = 979
4115 18:36:10.686834 tx_center_max[0][1][0] = 986
4116 18:36:10.689443 tx_center_min[0][1][1] = 978
4117 18:36:10.692748 tx_center_max[0][1][1] = 984
4118 18:36:10.696263 tx_center_min[1][0][0] = 987
4119 18:36:10.699912 tx_center_max[1][0][0] = 991
4120 18:36:10.700400 tx_center_min[1][0][1] = 976
4121 18:36:10.703358 tx_center_max[1][0][1] = 982
4122 18:36:10.705823 tx_center_min[1][1][0] = 987
4123 18:36:10.709354 tx_center_max[1][1][0] = 992
4124 18:36:10.712967 tx_center_min[1][1][1] = 977
4125 18:36:10.713347 tx_center_max[1][1][1] = 982
4126 18:36:10.715991 dump params tx window
4127 18:36:10.719396 tx_win_center[0][0][0] = 988
4128 18:36:10.722903 tx_first_pass[0][0][0] = 976
4129 18:36:10.723286 tx_last_pass[0][0][0] = 1001
4130 18:36:10.726093 tx_win_center[0][0][1] = 988
4131 18:36:10.729408 tx_first_pass[0][0][1] = 976
4132 18:36:10.732596 tx_last_pass[0][0][1] = 1000
4133 18:36:10.735782 tx_win_center[0][0][2] = 988
4134 18:36:10.736163 tx_first_pass[0][0][2] = 976
4135 18:36:10.739274 tx_last_pass[0][0][2] = 1001
4136 18:36:10.742298 tx_win_center[0][0][3] = 982
4137 18:36:10.746000 tx_first_pass[0][0][3] = 970
4138 18:36:10.746380 tx_last_pass[0][0][3] = 995
4139 18:36:10.749225 tx_win_center[0][0][4] = 988
4140 18:36:10.752247 tx_first_pass[0][0][4] = 976
4141 18:36:10.755958 tx_last_pass[0][0][4] = 1000
4142 18:36:10.758965 tx_win_center[0][0][5] = 985
4143 18:36:10.759353 tx_first_pass[0][0][5] = 973
4144 18:36:10.762349 tx_last_pass[0][0][5] = 998
4145 18:36:10.765653 tx_win_center[0][0][6] = 987
4146 18:36:10.768941 tx_first_pass[0][0][6] = 975
4147 18:36:10.769334 tx_last_pass[0][0][6] = 999
4148 18:36:10.772214 tx_win_center[0][0][7] = 988
4149 18:36:10.776076 tx_first_pass[0][0][7] = 976
4150 18:36:10.779852 tx_last_pass[0][0][7] = 1000
4151 18:36:10.782572 tx_win_center[0][0][8] = 975
4152 18:36:10.783091 tx_first_pass[0][0][8] = 963
4153 18:36:10.785889 tx_last_pass[0][0][8] = 987
4154 18:36:10.788778 tx_win_center[0][0][9] = 978
4155 18:36:10.792322 tx_first_pass[0][0][9] = 967
4156 18:36:10.795482 tx_last_pass[0][0][9] = 990
4157 18:36:10.795868 tx_win_center[0][0][10] = 981
4158 18:36:10.799124 tx_first_pass[0][0][10] = 969
4159 18:36:10.802295 tx_last_pass[0][0][10] = 994
4160 18:36:10.805690 tx_win_center[0][0][11] = 977
4161 18:36:10.808674 tx_first_pass[0][0][11] = 965
4162 18:36:10.809053 tx_last_pass[0][0][11] = 989
4163 18:36:10.812122 tx_win_center[0][0][12] = 979
4164 18:36:10.815428 tx_first_pass[0][0][12] = 967
4165 18:36:10.819504 tx_last_pass[0][0][12] = 991
4166 18:36:10.822138 tx_win_center[0][0][13] = 978
4167 18:36:10.822521 tx_first_pass[0][0][13] = 967
4168 18:36:10.825946 tx_last_pass[0][0][13] = 990
4169 18:36:10.828751 tx_win_center[0][0][14] = 979
4170 18:36:10.832330 tx_first_pass[0][0][14] = 967
4171 18:36:10.835893 tx_last_pass[0][0][14] = 991
4172 18:36:10.836417 tx_win_center[0][0][15] = 981
4173 18:36:10.838965 tx_first_pass[0][0][15] = 969
4174 18:36:10.842411 tx_last_pass[0][0][15] = 993
4175 18:36:10.845314 tx_win_center[0][1][0] = 986
4176 18:36:10.848602 tx_first_pass[0][1][0] = 974
4177 18:36:10.849016 tx_last_pass[0][1][0] = 998
4178 18:36:10.851953 tx_win_center[0][1][1] = 984
4179 18:36:10.855134 tx_first_pass[0][1][1] = 973
4180 18:36:10.859078 tx_last_pass[0][1][1] = 996
4181 18:36:10.859646 tx_win_center[0][1][2] = 985
4182 18:36:10.862002 tx_first_pass[0][1][2] = 973
4183 18:36:10.865758 tx_last_pass[0][1][2] = 998
4184 18:36:10.868783 tx_win_center[0][1][3] = 979
4185 18:36:10.871871 tx_first_pass[0][1][3] = 968
4186 18:36:10.872256 tx_last_pass[0][1][3] = 991
4187 18:36:10.875482 tx_win_center[0][1][4] = 983
4188 18:36:10.878428 tx_first_pass[0][1][4] = 971
4189 18:36:10.881719 tx_last_pass[0][1][4] = 996
4190 18:36:10.882107 tx_win_center[0][1][5] = 981
4191 18:36:10.885435 tx_first_pass[0][1][5] = 969
4192 18:36:10.889048 tx_last_pass[0][1][5] = 993
4193 18:36:10.891855 tx_win_center[0][1][6] = 982
4194 18:36:10.895196 tx_first_pass[0][1][6] = 970
4195 18:36:10.895370 tx_last_pass[0][1][6] = 994
4196 18:36:10.898443 tx_win_center[0][1][7] = 983
4197 18:36:10.901357 tx_first_pass[0][1][7] = 971
4198 18:36:10.905031 tx_last_pass[0][1][7] = 996
4199 18:36:10.905157 tx_win_center[0][1][8] = 978
4200 18:36:10.908679 tx_first_pass[0][1][8] = 966
4201 18:36:10.911779 tx_last_pass[0][1][8] = 990
4202 18:36:10.914717 tx_win_center[0][1][9] = 979
4203 18:36:10.918398 tx_first_pass[0][1][9] = 968
4204 18:36:10.918496 tx_last_pass[0][1][9] = 991
4205 18:36:10.921500 tx_win_center[0][1][10] = 984
4206 18:36:10.924689 tx_first_pass[0][1][10] = 972
4207 18:36:10.928060 tx_last_pass[0][1][10] = 997
4208 18:36:10.931390 tx_win_center[0][1][11] = 978
4209 18:36:10.931492 tx_first_pass[0][1][11] = 967
4210 18:36:10.935073 tx_last_pass[0][1][11] = 990
4211 18:36:10.938030 tx_win_center[0][1][12] = 979
4212 18:36:10.941744 tx_first_pass[0][1][12] = 968
4213 18:36:10.944589 tx_last_pass[0][1][12] = 991
4214 18:36:10.944680 tx_win_center[0][1][13] = 980
4215 18:36:10.948460 tx_first_pass[0][1][13] = 968
4216 18:36:10.951282 tx_last_pass[0][1][13] = 992
4217 18:36:10.954518 tx_win_center[0][1][14] = 980
4218 18:36:10.958288 tx_first_pass[0][1][14] = 968
4219 18:36:10.958382 tx_last_pass[0][1][14] = 992
4220 18:36:10.961409 tx_win_center[0][1][15] = 983
4221 18:36:10.964957 tx_first_pass[0][1][15] = 971
4222 18:36:10.967984 tx_last_pass[0][1][15] = 995
4223 18:36:10.971026 tx_win_center[1][0][0] = 991
4224 18:36:10.971117 tx_first_pass[1][0][0] = 978
4225 18:36:10.974601 tx_last_pass[1][0][0] = 1004
4226 18:36:10.977978 tx_win_center[1][0][1] = 989
4227 18:36:10.981183 tx_first_pass[1][0][1] = 977
4228 18:36:10.984382 tx_last_pass[1][0][1] = 1002
4229 18:36:10.984563 tx_win_center[1][0][2] = 988
4230 18:36:10.988085 tx_first_pass[1][0][2] = 976
4231 18:36:10.991101 tx_last_pass[1][0][2] = 1000
4232 18:36:10.994556 tx_win_center[1][0][3] = 987
4233 18:36:10.994647 tx_first_pass[1][0][3] = 975
4234 18:36:10.998019 tx_last_pass[1][0][3] = 999
4235 18:36:11.001239 tx_win_center[1][0][4] = 990
4236 18:36:11.004444 tx_first_pass[1][0][4] = 978
4237 18:36:11.007804 tx_last_pass[1][0][4] = 1002
4238 18:36:11.007900 tx_win_center[1][0][5] = 990
4239 18:36:11.010789 tx_first_pass[1][0][5] = 978
4240 18:36:11.014476 tx_last_pass[1][0][5] = 1003
4241 18:36:11.017965 tx_win_center[1][0][6] = 989
4242 18:36:11.021104 tx_first_pass[1][0][6] = 977
4243 18:36:11.021197 tx_last_pass[1][0][6] = 1002
4244 18:36:11.024057 tx_win_center[1][0][7] = 990
4245 18:36:11.027552 tx_first_pass[1][0][7] = 978
4246 18:36:11.030648 tx_last_pass[1][0][7] = 1002
4247 18:36:11.034264 tx_win_center[1][0][8] = 980
4248 18:36:11.034356 tx_first_pass[1][0][8] = 968
4249 18:36:11.037241 tx_last_pass[1][0][8] = 992
4250 18:36:11.040763 tx_win_center[1][0][9] = 979
4251 18:36:11.044313 tx_first_pass[1][0][9] = 968
4252 18:36:11.044406 tx_last_pass[1][0][9] = 991
4253 18:36:11.047437 tx_win_center[1][0][10] = 981
4254 18:36:11.050719 tx_first_pass[1][0][10] = 970
4255 18:36:11.053878 tx_last_pass[1][0][10] = 993
4256 18:36:11.057212 tx_win_center[1][0][11] = 982
4257 18:36:11.060609 tx_first_pass[1][0][11] = 970
4258 18:36:11.060725 tx_last_pass[1][0][11] = 994
4259 18:36:11.064231 tx_win_center[1][0][12] = 981
4260 18:36:11.067311 tx_first_pass[1][0][12] = 970
4261 18:36:11.070791 tx_last_pass[1][0][12] = 993
4262 18:36:11.070959 tx_win_center[1][0][13] = 982
4263 18:36:11.074263 tx_first_pass[1][0][13] = 971
4264 18:36:11.077440 tx_last_pass[1][0][13] = 994
4265 18:36:11.080802 tx_win_center[1][0][14] = 981
4266 18:36:11.084553 tx_first_pass[1][0][14] = 970
4267 18:36:11.087390 tx_last_pass[1][0][14] = 993
4268 18:36:11.087591 tx_win_center[1][0][15] = 976
4269 18:36:11.090900 tx_first_pass[1][0][15] = 965
4270 18:36:11.093945 tx_last_pass[1][0][15] = 987
4271 18:36:11.097640 tx_win_center[1][1][0] = 992
4272 18:36:11.100545 tx_first_pass[1][1][0] = 979
4273 18:36:11.100714 tx_last_pass[1][1][0] = 1005
4274 18:36:11.103785 tx_win_center[1][1][1] = 990
4275 18:36:11.107464 tx_first_pass[1][1][1] = 978
4276 18:36:11.110850 tx_last_pass[1][1][1] = 1003
4277 18:36:11.111094 tx_win_center[1][1][2] = 988
4278 18:36:11.114254 tx_first_pass[1][1][2] = 976
4279 18:36:11.116909 tx_last_pass[1][1][2] = 1001
4280 18:36:11.120383 tx_win_center[1][1][3] = 987
4281 18:36:11.123858 tx_first_pass[1][1][3] = 975
4282 18:36:11.124166 tx_last_pass[1][1][3] = 999
4283 18:36:11.127330 tx_win_center[1][1][4] = 990
4284 18:36:11.130644 tx_first_pass[1][1][4] = 978
4285 18:36:11.134622 tx_last_pass[1][1][4] = 1003
4286 18:36:11.135142 tx_win_center[1][1][5] = 991
4287 18:36:11.137646 tx_first_pass[1][1][5] = 978
4288 18:36:11.140850 tx_last_pass[1][1][5] = 1004
4289 18:36:11.143714 tx_win_center[1][1][6] = 990
4290 18:36:11.147198 tx_first_pass[1][1][6] = 977
4291 18:36:11.147671 tx_last_pass[1][1][6] = 1004
4292 18:36:11.150613 tx_win_center[1][1][7] = 990
4293 18:36:11.154505 tx_first_pass[1][1][7] = 978
4294 18:36:11.157020 tx_last_pass[1][1][7] = 1003
4295 18:36:11.160372 tx_win_center[1][1][8] = 979
4296 18:36:11.160757 tx_first_pass[1][1][8] = 968
4297 18:36:11.164222 tx_last_pass[1][1][8] = 991
4298 18:36:11.167263 tx_win_center[1][1][9] = 979
4299 18:36:11.170905 tx_first_pass[1][1][9] = 968
4300 18:36:11.173733 tx_last_pass[1][1][9] = 991
4301 18:36:11.174247 tx_win_center[1][1][10] = 981
4302 18:36:11.177368 tx_first_pass[1][1][10] = 970
4303 18:36:11.180151 tx_last_pass[1][1][10] = 993
4304 18:36:11.184011 tx_win_center[1][1][11] = 982
4305 18:36:11.187281 tx_first_pass[1][1][11] = 970
4306 18:36:11.187929 tx_last_pass[1][1][11] = 994
4307 18:36:11.190547 tx_win_center[1][1][12] = 982
4308 18:36:11.193438 tx_first_pass[1][1][12] = 970
4309 18:36:11.196986 tx_last_pass[1][1][12] = 994
4310 18:36:11.200367 tx_win_center[1][1][13] = 982
4311 18:36:11.200788 tx_first_pass[1][1][13] = 971
4312 18:36:11.203441 tx_last_pass[1][1][13] = 994
4313 18:36:11.206962 tx_win_center[1][1][14] = 982
4314 18:36:11.210600 tx_first_pass[1][1][14] = 970
4315 18:36:11.213831 tx_last_pass[1][1][14] = 994
4316 18:36:11.214526 tx_win_center[1][1][15] = 977
4317 18:36:11.217260 tx_first_pass[1][1][15] = 965
4318 18:36:11.219952 tx_last_pass[1][1][15] = 989
4319 18:36:11.223325 dump params rx window
4320 18:36:11.223783 rx_firspass[0][0][0] = 5
4321 18:36:11.226931 rx_lastpass[0][0][0] = 38
4322 18:36:11.230869 rx_firspass[0][0][1] = 5
4323 18:36:11.231384 rx_lastpass[0][0][1] = 37
4324 18:36:11.233240 rx_firspass[0][0][2] = 6
4325 18:36:11.236907 rx_lastpass[0][0][2] = 36
4326 18:36:11.240728 rx_firspass[0][0][3] = -2
4327 18:36:11.241240 rx_lastpass[0][0][3] = 31
4328 18:36:11.243563 rx_firspass[0][0][4] = 4
4329 18:36:11.247212 rx_lastpass[0][0][4] = 37
4330 18:36:11.247770 rx_firspass[0][0][5] = 1
4331 18:36:11.249665 rx_lastpass[0][0][5] = 32
4332 18:36:11.253447 rx_firspass[0][0][6] = 3
4333 18:36:11.253958 rx_lastpass[0][0][6] = 34
4334 18:36:11.256563 rx_firspass[0][0][7] = 5
4335 18:36:11.259905 rx_lastpass[0][0][7] = 36
4336 18:36:11.263191 rx_firspass[0][0][8] = -4
4337 18:36:11.263751 rx_lastpass[0][0][8] = 33
4338 18:36:11.266713 rx_firspass[0][0][9] = 0
4339 18:36:11.269950 rx_lastpass[0][0][9] = 33
4340 18:36:11.270366 rx_firspass[0][0][10] = 7
4341 18:36:11.273167 rx_lastpass[0][0][10] = 41
4342 18:36:11.276014 rx_firspass[0][0][11] = 1
4343 18:36:11.279476 rx_lastpass[0][0][11] = 33
4344 18:36:11.279859 rx_firspass[0][0][12] = 1
4345 18:36:11.283270 rx_lastpass[0][0][12] = 37
4346 18:36:11.286078 rx_firspass[0][0][13] = 3
4347 18:36:11.289542 rx_lastpass[0][0][13] = 34
4348 18:36:11.289921 rx_firspass[0][0][14] = 1
4349 18:36:11.293179 rx_lastpass[0][0][14] = 37
4350 18:36:11.296569 rx_firspass[0][0][15] = 5
4351 18:36:11.296829 rx_lastpass[0][0][15] = 37
4352 18:36:11.299749 rx_firspass[0][1][0] = 6
4353 18:36:11.302648 rx_lastpass[0][1][0] = 40
4354 18:36:11.306025 rx_firspass[0][1][1] = 5
4355 18:36:11.306197 rx_lastpass[0][1][1] = 38
4356 18:36:11.309038 rx_firspass[0][1][2] = 6
4357 18:36:11.312365 rx_lastpass[0][1][2] = 38
4358 18:36:11.312492 rx_firspass[0][1][3] = -2
4359 18:36:11.315741 rx_lastpass[0][1][3] = 33
4360 18:36:11.319006 rx_firspass[0][1][4] = 5
4361 18:36:11.319153 rx_lastpass[0][1][4] = 39
4362 18:36:11.322457 rx_firspass[0][1][5] = 1
4363 18:36:11.325773 rx_lastpass[0][1][5] = 34
4364 18:36:11.329407 rx_firspass[0][1][6] = 3
4365 18:36:11.329515 rx_lastpass[0][1][6] = 37
4366 18:36:11.332738 rx_firspass[0][1][7] = 3
4367 18:36:11.335783 rx_lastpass[0][1][7] = 37
4368 18:36:11.335891 rx_firspass[0][1][8] = -2
4369 18:36:11.339100 rx_lastpass[0][1][8] = 32
4370 18:36:11.342233 rx_firspass[0][1][9] = 1
4371 18:36:11.342322 rx_lastpass[0][1][9] = 36
4372 18:36:11.345743 rx_firspass[0][1][10] = 7
4373 18:36:11.349527 rx_lastpass[0][1][10] = 43
4374 18:36:11.352764 rx_firspass[0][1][11] = -2
4375 18:36:11.352855 rx_lastpass[0][1][11] = 34
4376 18:36:11.355966 rx_firspass[0][1][12] = 1
4377 18:36:11.359173 rx_lastpass[0][1][12] = 37
4378 18:36:11.362110 rx_firspass[0][1][13] = 1
4379 18:36:11.362201 rx_lastpass[0][1][13] = 35
4380 18:36:11.365799 rx_firspass[0][1][14] = 3
4381 18:36:11.369167 rx_lastpass[0][1][14] = 37
4382 18:36:11.369258 rx_firspass[0][1][15] = 6
4383 18:36:11.372180 rx_lastpass[0][1][15] = 40
4384 18:36:11.375768 rx_firspass[1][0][0] = 4
4385 18:36:11.379099 rx_lastpass[1][0][0] = 39
4386 18:36:11.379189 rx_firspass[1][0][1] = 3
4387 18:36:11.382688 rx_lastpass[1][0][1] = 38
4388 18:36:11.386203 rx_firspass[1][0][2] = 3
4389 18:36:11.386440 rx_lastpass[1][0][2] = 36
4390 18:36:11.389484 rx_firspass[1][0][3] = 0
4391 18:36:11.393174 rx_lastpass[1][0][3] = 34
4392 18:36:11.393338 rx_firspass[1][0][4] = 4
4393 18:36:11.395696 rx_lastpass[1][0][4] = 38
4394 18:36:11.399294 rx_firspass[1][0][5] = 5
4395 18:36:11.402259 rx_lastpass[1][0][5] = 39
4396 18:36:11.402393 rx_firspass[1][0][6] = 7
4397 18:36:11.405717 rx_lastpass[1][0][6] = 40
4398 18:36:11.409236 rx_firspass[1][0][7] = 5
4399 18:36:11.409431 rx_lastpass[1][0][7] = 38
4400 18:36:11.412337 rx_firspass[1][0][8] = 0
4401 18:36:11.415576 rx_lastpass[1][0][8] = 33
4402 18:36:11.419148 rx_firspass[1][0][9] = -1
4403 18:36:11.419313 rx_lastpass[1][0][9] = 32
4404 18:36:11.422150 rx_firspass[1][0][10] = 4
4405 18:36:11.425727 rx_lastpass[1][0][10] = 35
4406 18:36:11.425972 rx_firspass[1][0][11] = 5
4407 18:36:11.429169 rx_lastpass[1][0][11] = 38
4408 18:36:11.432583 rx_firspass[1][0][12] = 5
4409 18:36:11.435484 rx_lastpass[1][0][12] = 38
4410 18:36:11.435757 rx_firspass[1][0][13] = 5
4411 18:36:11.439516 rx_lastpass[1][0][13] = 37
4412 18:36:11.442370 rx_firspass[1][0][14] = 7
4413 18:36:11.446057 rx_lastpass[1][0][14] = 38
4414 18:36:11.446515 rx_firspass[1][0][15] = -4
4415 18:36:11.449221 rx_lastpass[1][0][15] = 30
4416 18:36:11.452745 rx_firspass[1][1][0] = 3
4417 18:36:11.453223 rx_lastpass[1][1][0] = 40
4418 18:36:11.455795 rx_firspass[1][1][1] = 4
4419 18:36:11.459273 rx_lastpass[1][1][1] = 39
4420 18:36:11.462188 rx_firspass[1][1][2] = 0
4421 18:36:11.462568 rx_lastpass[1][1][2] = 36
4422 18:36:11.466191 rx_firspass[1][1][3] = -2
4423 18:36:11.469432 rx_lastpass[1][1][3] = 34
4424 18:36:11.469906 rx_firspass[1][1][4] = 4
4425 18:36:11.472290 rx_lastpass[1][1][4] = 39
4426 18:36:11.476043 rx_firspass[1][1][5] = 5
4427 18:36:11.476522 rx_lastpass[1][1][5] = 40
4428 18:36:11.479540 rx_firspass[1][1][6] = 5
4429 18:36:11.482461 rx_lastpass[1][1][6] = 41
4430 18:36:11.485618 rx_firspass[1][1][7] = 3
4431 18:36:11.486120 rx_lastpass[1][1][7] = 38
4432 18:36:11.489000 rx_firspass[1][1][8] = 0
4433 18:36:11.492255 rx_lastpass[1][1][8] = 34
4434 18:36:11.492769 rx_firspass[1][1][9] = -1
4435 18:36:11.495761 rx_lastpass[1][1][9] = 34
4436 18:36:11.498814 rx_firspass[1][1][10] = 3
4437 18:36:11.502309 rx_lastpass[1][1][10] = 39
4438 18:36:11.502786 rx_firspass[1][1][11] = 4
4439 18:36:11.505476 rx_lastpass[1][1][11] = 40
4440 18:36:11.509039 rx_firspass[1][1][12] = 4
4441 18:36:11.509523 rx_lastpass[1][1][12] = 40
4442 18:36:11.512119 rx_firspass[1][1][13] = 4
4443 18:36:11.515635 rx_lastpass[1][1][13] = 40
4444 18:36:11.518691 rx_firspass[1][1][14] = 5
4445 18:36:11.519078 rx_lastpass[1][1][14] = 40
4446 18:36:11.521742 rx_firspass[1][1][15] = -3
4447 18:36:11.525276 rx_lastpass[1][1][15] = 31
4448 18:36:11.525657 dump params clk_delay
4449 18:36:11.528714 clk_delay[0] = 1
4450 18:36:11.529288 clk_delay[1] = 0
4451 18:36:11.532303 dump params dqs_delay
4452 18:36:11.535586 dqs_delay[0][0] = -2
4453 18:36:11.536021 dqs_delay[0][1] = 0
4454 18:36:11.538452 dqs_delay[1][0] = 0
4455 18:36:11.538880 dqs_delay[1][1] = 0
4456 18:36:11.542077 dump params delay_cell_unit = 735
4457 18:36:11.544962 dump source = 0x0
4458 18:36:11.545393 dump params frequency:1200
4459 18:36:11.548272 dump params rank number:2
4460 18:36:11.548615
4461 18:36:11.551855 dump params write leveling
4462 18:36:11.555392 write leveling[0][0][0] = 0x0
4463 18:36:11.556043 write leveling[0][0][1] = 0x0
4464 18:36:11.558690 write leveling[0][1][0] = 0x0
4465 18:36:11.561970 write leveling[0][1][1] = 0x0
4466 18:36:11.564862 write leveling[1][0][0] = 0x0
4467 18:36:11.568727 write leveling[1][0][1] = 0x0
4468 18:36:11.569072 write leveling[1][1][0] = 0x0
4469 18:36:11.571490 write leveling[1][1][1] = 0x0
4470 18:36:11.575357 dump params cbt_cs
4471 18:36:11.575738 cbt_cs[0][0] = 0x0
4472 18:36:11.578250 cbt_cs[0][1] = 0x0
4473 18:36:11.578592 cbt_cs[1][0] = 0x0
4474 18:36:11.581814 cbt_cs[1][1] = 0x0
4475 18:36:11.582258 dump params cbt_mr12
4476 18:36:11.585127 cbt_mr12[0][0] = 0x0
4477 18:36:11.588856 cbt_mr12[0][1] = 0x0
4478 18:36:11.589302 cbt_mr12[1][0] = 0x0
4479 18:36:11.592014 cbt_mr12[1][1] = 0x0
4480 18:36:11.592358 dump params tx window
4481 18:36:11.595512 tx_center_min[0][0][0] = 0
4482 18:36:11.598888 tx_center_max[0][0][0] = 0
4483 18:36:11.602086 tx_center_min[0][0][1] = 0
4484 18:36:11.602530 tx_center_max[0][0][1] = 0
4485 18:36:11.605507 tx_center_min[0][1][0] = 0
4486 18:36:11.608215 tx_center_max[0][1][0] = 0
4487 18:36:11.608572 tx_center_min[0][1][1] = 0
4488 18:36:11.612046 tx_center_max[0][1][1] = 0
4489 18:36:11.615314 tx_center_min[1][0][0] = 0
4490 18:36:11.618659 tx_center_max[1][0][0] = 0
4491 18:36:11.619105 tx_center_min[1][0][1] = 0
4492 18:36:11.622059 tx_center_max[1][0][1] = 0
4493 18:36:11.624756 tx_center_min[1][1][0] = 0
4494 18:36:11.628730 tx_center_max[1][1][0] = 0
4495 18:36:11.629187 tx_center_min[1][1][1] = 0
4496 18:36:11.631924 tx_center_max[1][1][1] = 0
4497 18:36:11.635121 dump params tx window
4498 18:36:11.635622 tx_win_center[0][0][0] = 0
4499 18:36:11.638392 tx_first_pass[0][0][0] = 0
4500 18:36:11.642174 tx_last_pass[0][0][0] = 0
4501 18:36:11.644834 tx_win_center[0][0][1] = 0
4502 18:36:11.645181 tx_first_pass[0][0][1] = 0
4503 18:36:11.648314 tx_last_pass[0][0][1] = 0
4504 18:36:11.651448 tx_win_center[0][0][2] = 0
4505 18:36:11.655312 tx_first_pass[0][0][2] = 0
4506 18:36:11.655874 tx_last_pass[0][0][2] = 0
4507 18:36:11.658684 tx_win_center[0][0][3] = 0
4508 18:36:11.661535 tx_first_pass[0][0][3] = 0
4509 18:36:11.662052 tx_last_pass[0][0][3] = 0
4510 18:36:11.665045 tx_win_center[0][0][4] = 0
4511 18:36:11.668085 tx_first_pass[0][0][4] = 0
4512 18:36:11.671386 tx_last_pass[0][0][4] = 0
4513 18:36:11.671843 tx_win_center[0][0][5] = 0
4514 18:36:11.674682 tx_first_pass[0][0][5] = 0
4515 18:36:11.678201 tx_last_pass[0][0][5] = 0
4516 18:36:11.681324 tx_win_center[0][0][6] = 0
4517 18:36:11.681737 tx_first_pass[0][0][6] = 0
4518 18:36:11.684884 tx_last_pass[0][0][6] = 0
4519 18:36:11.688375 tx_win_center[0][0][7] = 0
4520 18:36:11.688757 tx_first_pass[0][0][7] = 0
4521 18:36:11.691379 tx_last_pass[0][0][7] = 0
4522 18:36:11.694623 tx_win_center[0][0][8] = 0
4523 18:36:11.697552 tx_first_pass[0][0][8] = 0
4524 18:36:11.697798 tx_last_pass[0][0][8] = 0
4525 18:36:11.700900 tx_win_center[0][0][9] = 0
4526 18:36:11.704348 tx_first_pass[0][0][9] = 0
4527 18:36:11.707906 tx_last_pass[0][0][9] = 0
4528 18:36:11.708050 tx_win_center[0][0][10] = 0
4529 18:36:11.711217 tx_first_pass[0][0][10] = 0
4530 18:36:11.714559 tx_last_pass[0][0][10] = 0
4531 18:36:11.717356 tx_win_center[0][0][11] = 0
4532 18:36:11.717465 tx_first_pass[0][0][11] = 0
4533 18:36:11.721342 tx_last_pass[0][0][11] = 0
4534 18:36:11.724486 tx_win_center[0][0][12] = 0
4535 18:36:11.727477 tx_first_pass[0][0][12] = 0
4536 18:36:11.727568 tx_last_pass[0][0][12] = 0
4537 18:36:11.730786 tx_win_center[0][0][13] = 0
4538 18:36:11.734051 tx_first_pass[0][0][13] = 0
4539 18:36:11.737497 tx_last_pass[0][0][13] = 0
4540 18:36:11.737588 tx_win_center[0][0][14] = 0
4541 18:36:11.740775 tx_first_pass[0][0][14] = 0
4542 18:36:11.744422 tx_last_pass[0][0][14] = 0
4543 18:36:11.747195 tx_win_center[0][0][15] = 0
4544 18:36:11.747286 tx_first_pass[0][0][15] = 0
4545 18:36:11.750857 tx_last_pass[0][0][15] = 0
4546 18:36:11.754309 tx_win_center[0][1][0] = 0
4547 18:36:11.757147 tx_first_pass[0][1][0] = 0
4548 18:36:11.757238 tx_last_pass[0][1][0] = 0
4549 18:36:11.760686 tx_win_center[0][1][1] = 0
4550 18:36:11.764094 tx_first_pass[0][1][1] = 0
4551 18:36:11.764232 tx_last_pass[0][1][1] = 0
4552 18:36:11.767618 tx_win_center[0][1][2] = 0
4553 18:36:11.770852 tx_first_pass[0][1][2] = 0
4554 18:36:11.773837 tx_last_pass[0][1][2] = 0
4555 18:36:11.773946 tx_win_center[0][1][3] = 0
4556 18:36:11.777579 tx_first_pass[0][1][3] = 0
4557 18:36:11.780850 tx_last_pass[0][1][3] = 0
4558 18:36:11.784129 tx_win_center[0][1][4] = 0
4559 18:36:11.784220 tx_first_pass[0][1][4] = 0
4560 18:36:11.787416 tx_last_pass[0][1][4] = 0
4561 18:36:11.791084 tx_win_center[0][1][5] = 0
4562 18:36:11.791173 tx_first_pass[0][1][5] = 0
4563 18:36:11.794834 tx_last_pass[0][1][5] = 0
4564 18:36:11.797582 tx_win_center[0][1][6] = 0
4565 18:36:11.800730 tx_first_pass[0][1][6] = 0
4566 18:36:11.800900 tx_last_pass[0][1][6] = 0
4567 18:36:11.803868 tx_win_center[0][1][7] = 0
4568 18:36:11.807096 tx_first_pass[0][1][7] = 0
4569 18:36:11.810448 tx_last_pass[0][1][7] = 0
4570 18:36:11.810567 tx_win_center[0][1][8] = 0
4571 18:36:11.814608 tx_first_pass[0][1][8] = 0
4572 18:36:11.816947 tx_last_pass[0][1][8] = 0
4573 18:36:11.817130 tx_win_center[0][1][9] = 0
4574 18:36:11.820681 tx_first_pass[0][1][9] = 0
4575 18:36:11.823966 tx_last_pass[0][1][9] = 0
4576 18:36:11.827735 tx_win_center[0][1][10] = 0
4577 18:36:11.827941 tx_first_pass[0][1][10] = 0
4578 18:36:11.830753 tx_last_pass[0][1][10] = 0
4579 18:36:11.834217 tx_win_center[0][1][11] = 0
4580 18:36:11.837254 tx_first_pass[0][1][11] = 0
4581 18:36:11.837463 tx_last_pass[0][1][11] = 0
4582 18:36:11.840864 tx_win_center[0][1][12] = 0
4583 18:36:11.843984 tx_first_pass[0][1][12] = 0
4584 18:36:11.847140 tx_last_pass[0][1][12] = 0
4585 18:36:11.847381 tx_win_center[0][1][13] = 0
4586 18:36:11.850734 tx_first_pass[0][1][13] = 0
4587 18:36:11.854280 tx_last_pass[0][1][13] = 0
4588 18:36:11.857509 tx_win_center[0][1][14] = 0
4589 18:36:11.857873 tx_first_pass[0][1][14] = 0
4590 18:36:11.860632 tx_last_pass[0][1][14] = 0
4591 18:36:11.864117 tx_win_center[0][1][15] = 0
4592 18:36:11.867530 tx_first_pass[0][1][15] = 0
4593 18:36:11.868060 tx_last_pass[0][1][15] = 0
4594 18:36:11.870692 tx_win_center[1][0][0] = 0
4595 18:36:11.873974 tx_first_pass[1][0][0] = 0
4596 18:36:11.877744 tx_last_pass[1][0][0] = 0
4597 18:36:11.878227 tx_win_center[1][0][1] = 0
4598 18:36:11.880632 tx_first_pass[1][0][1] = 0
4599 18:36:11.883863 tx_last_pass[1][0][1] = 0
4600 18:36:11.884375 tx_win_center[1][0][2] = 0
4601 18:36:11.887917 tx_first_pass[1][0][2] = 0
4602 18:36:11.891219 tx_last_pass[1][0][2] = 0
4603 18:36:11.894318 tx_win_center[1][0][3] = 0
4604 18:36:11.894830 tx_first_pass[1][0][3] = 0
4605 18:36:11.897468 tx_last_pass[1][0][3] = 0
4606 18:36:11.901116 tx_win_center[1][0][4] = 0
4607 18:36:11.904032 tx_first_pass[1][0][4] = 0
4608 18:36:11.904543 tx_last_pass[1][0][4] = 0
4609 18:36:11.907567 tx_win_center[1][0][5] = 0
4610 18:36:11.911387 tx_first_pass[1][0][5] = 0
4611 18:36:11.911939 tx_last_pass[1][0][5] = 0
4612 18:36:11.914267 tx_win_center[1][0][6] = 0
4613 18:36:11.917691 tx_first_pass[1][0][6] = 0
4614 18:36:11.920626 tx_last_pass[1][0][6] = 0
4615 18:36:11.921146 tx_win_center[1][0][7] = 0
4616 18:36:11.923829 tx_first_pass[1][0][7] = 0
4617 18:36:11.927563 tx_last_pass[1][0][7] = 0
4618 18:36:11.931281 tx_win_center[1][0][8] = 0
4619 18:36:11.931843 tx_first_pass[1][0][8] = 0
4620 18:36:11.933958 tx_last_pass[1][0][8] = 0
4621 18:36:11.937165 tx_win_center[1][0][9] = 0
4622 18:36:11.940162 tx_first_pass[1][0][9] = 0
4623 18:36:11.940575 tx_last_pass[1][0][9] = 0
4624 18:36:11.944113 tx_win_center[1][0][10] = 0
4625 18:36:11.947079 tx_first_pass[1][0][10] = 0
4626 18:36:11.950276 tx_last_pass[1][0][10] = 0
4627 18:36:11.950696 tx_win_center[1][0][11] = 0
4628 18:36:11.954147 tx_first_pass[1][0][11] = 0
4629 18:36:11.957240 tx_last_pass[1][0][11] = 0
4630 18:36:11.959949 tx_win_center[1][0][12] = 0
4631 18:36:11.960362 tx_first_pass[1][0][12] = 0
4632 18:36:11.964049 tx_last_pass[1][0][12] = 0
4633 18:36:11.967056 tx_win_center[1][0][13] = 0
4634 18:36:11.970421 tx_first_pass[1][0][13] = 0
4635 18:36:11.970965 tx_last_pass[1][0][13] = 0
4636 18:36:11.973313 tx_win_center[1][0][14] = 0
4637 18:36:11.976795 tx_first_pass[1][0][14] = 0
4638 18:36:11.979907 tx_last_pass[1][0][14] = 0
4639 18:36:11.980502 tx_win_center[1][0][15] = 0
4640 18:36:11.983065 tx_first_pass[1][0][15] = 0
4641 18:36:11.986875 tx_last_pass[1][0][15] = 0
4642 18:36:11.990063 tx_win_center[1][1][0] = 0
4643 18:36:11.990371 tx_first_pass[1][1][0] = 0
4644 18:36:11.993054 tx_last_pass[1][1][0] = 0
4645 18:36:11.996739 tx_win_center[1][1][1] = 0
4646 18:36:11.996975 tx_first_pass[1][1][1] = 0
4647 18:36:12.000275 tx_last_pass[1][1][1] = 0
4648 18:36:12.002818 tx_win_center[1][1][2] = 0
4649 18:36:12.006457 tx_first_pass[1][1][2] = 0
4650 18:36:12.006614 tx_last_pass[1][1][2] = 0
4651 18:36:12.009800 tx_win_center[1][1][3] = 0
4652 18:36:12.012725 tx_first_pass[1][1][3] = 0
4653 18:36:12.016214 tx_last_pass[1][1][3] = 0
4654 18:36:12.016333 tx_win_center[1][1][4] = 0
4655 18:36:12.019630 tx_first_pass[1][1][4] = 0
4656 18:36:12.023121 tx_last_pass[1][1][4] = 0
4657 18:36:12.023227 tx_win_center[1][1][5] = 0
4658 18:36:12.026722 tx_first_pass[1][1][5] = 0
4659 18:36:12.030334 tx_last_pass[1][1][5] = 0
4660 18:36:12.032831 tx_win_center[1][1][6] = 0
4661 18:36:12.032985 tx_first_pass[1][1][6] = 0
4662 18:36:12.036461 tx_last_pass[1][1][6] = 0
4663 18:36:12.039709 tx_win_center[1][1][7] = 0
4664 18:36:12.043010 tx_first_pass[1][1][7] = 0
4665 18:36:12.043192 tx_last_pass[1][1][7] = 0
4666 18:36:12.046663 tx_win_center[1][1][8] = 0
4667 18:36:12.049269 tx_first_pass[1][1][8] = 0
4668 18:36:12.049431 tx_last_pass[1][1][8] = 0
4669 18:36:12.053000 tx_win_center[1][1][9] = 0
4670 18:36:12.055897 tx_first_pass[1][1][9] = 0
4671 18:36:12.059771 tx_last_pass[1][1][9] = 0
4672 18:36:12.060121 tx_win_center[1][1][10] = 0
4673 18:36:12.063062 tx_first_pass[1][1][10] = 0
4674 18:36:12.066509 tx_last_pass[1][1][10] = 0
4675 18:36:12.069622 tx_win_center[1][1][11] = 0
4676 18:36:12.069880 tx_first_pass[1][1][11] = 0
4677 18:36:12.072868 tx_last_pass[1][1][11] = 0
4678 18:36:12.076629 tx_win_center[1][1][12] = 0
4679 18:36:12.079890 tx_first_pass[1][1][12] = 0
4680 18:36:12.080222 tx_last_pass[1][1][12] = 0
4681 18:36:12.083065 tx_win_center[1][1][13] = 0
4682 18:36:12.086809 tx_first_pass[1][1][13] = 0
4683 18:36:12.090133 tx_last_pass[1][1][13] = 0
4684 18:36:12.090622 tx_win_center[1][1][14] = 0
4685 18:36:12.093206 tx_first_pass[1][1][14] = 0
4686 18:36:12.096101 tx_last_pass[1][1][14] = 0
4687 18:36:12.099844 tx_win_center[1][1][15] = 0
4688 18:36:12.100358 tx_first_pass[1][1][15] = 0
4689 18:36:12.103231 tx_last_pass[1][1][15] = 0
4690 18:36:12.106534 dump params rx window
4691 18:36:12.106960 rx_firspass[0][0][0] = 0
4692 18:36:12.109513 rx_lastpass[0][0][0] = 0
4693 18:36:12.113208 rx_firspass[0][0][1] = 0
4694 18:36:12.116355 rx_lastpass[0][0][1] = 0
4695 18:36:12.116843 rx_firspass[0][0][2] = 0
4696 18:36:12.119686 rx_lastpass[0][0][2] = 0
4697 18:36:12.123237 rx_firspass[0][0][3] = 0
4698 18:36:12.123811 rx_lastpass[0][0][3] = 0
4699 18:36:12.126304 rx_firspass[0][0][4] = 0
4700 18:36:12.129973 rx_lastpass[0][0][4] = 0
4701 18:36:12.130497 rx_firspass[0][0][5] = 0
4702 18:36:12.132620 rx_lastpass[0][0][5] = 0
4703 18:36:12.136257 rx_firspass[0][0][6] = 0
4704 18:36:12.136783 rx_lastpass[0][0][6] = 0
4705 18:36:12.139511 rx_firspass[0][0][7] = 0
4706 18:36:12.143320 rx_lastpass[0][0][7] = 0
4707 18:36:12.143890 rx_firspass[0][0][8] = 0
4708 18:36:12.145986 rx_lastpass[0][0][8] = 0
4709 18:36:12.149694 rx_firspass[0][0][9] = 0
4710 18:36:12.150230 rx_lastpass[0][0][9] = 0
4711 18:36:12.153082 rx_firspass[0][0][10] = 0
4712 18:36:12.155964 rx_lastpass[0][0][10] = 0
4713 18:36:12.159264 rx_firspass[0][0][11] = 0
4714 18:36:12.159726 rx_lastpass[0][0][11] = 0
4715 18:36:12.162526 rx_firspass[0][0][12] = 0
4716 18:36:12.166249 rx_lastpass[0][0][12] = 0
4717 18:36:12.166834 rx_firspass[0][0][13] = 0
4718 18:36:12.169369 rx_lastpass[0][0][13] = 0
4719 18:36:12.172767 rx_firspass[0][0][14] = 0
4720 18:36:12.176022 rx_lastpass[0][0][14] = 0
4721 18:36:12.176454 rx_firspass[0][0][15] = 0
4722 18:36:12.179499 rx_lastpass[0][0][15] = 0
4723 18:36:12.182949 rx_firspass[0][1][0] = 0
4724 18:36:12.183539 rx_lastpass[0][1][0] = 0
4725 18:36:12.186196 rx_firspass[0][1][1] = 0
4726 18:36:12.189737 rx_lastpass[0][1][1] = 0
4727 18:36:12.190272 rx_firspass[0][1][2] = 0
4728 18:36:12.192648 rx_lastpass[0][1][2] = 0
4729 18:36:12.195683 rx_firspass[0][1][3] = 0
4730 18:36:12.199543 rx_lastpass[0][1][3] = 0
4731 18:36:12.200077 rx_firspass[0][1][4] = 0
4732 18:36:12.203134 rx_lastpass[0][1][4] = 0
4733 18:36:12.205770 rx_firspass[0][1][5] = 0
4734 18:36:12.206203 rx_lastpass[0][1][5] = 0
4735 18:36:12.209452 rx_firspass[0][1][6] = 0
4736 18:36:12.213104 rx_lastpass[0][1][6] = 0
4737 18:36:12.213646 rx_firspass[0][1][7] = 0
4738 18:36:12.216203 rx_lastpass[0][1][7] = 0
4739 18:36:12.219185 rx_firspass[0][1][8] = 0
4740 18:36:12.219653 rx_lastpass[0][1][8] = 0
4741 18:36:12.222214 rx_firspass[0][1][9] = 0
4742 18:36:12.225599 rx_lastpass[0][1][9] = 0
4743 18:36:12.229554 rx_firspass[0][1][10] = 0
4744 18:36:12.230118 rx_lastpass[0][1][10] = 0
4745 18:36:12.232424 rx_firspass[0][1][11] = 0
4746 18:36:12.235945 rx_lastpass[0][1][11] = 0
4747 18:36:12.236477 rx_firspass[0][1][12] = 0
4748 18:36:12.239202 rx_lastpass[0][1][12] = 0
4749 18:36:12.242656 rx_firspass[0][1][13] = 0
4750 18:36:12.245793 rx_lastpass[0][1][13] = 0
4751 18:36:12.246315 rx_firspass[0][1][14] = 0
4752 18:36:12.249012 rx_lastpass[0][1][14] = 0
4753 18:36:12.252344 rx_firspass[0][1][15] = 0
4754 18:36:12.252757 rx_lastpass[0][1][15] = 0
4755 18:36:12.255856 rx_firspass[1][0][0] = 0
4756 18:36:12.258618 rx_lastpass[1][0][0] = 0
4757 18:36:12.259032 rx_firspass[1][0][1] = 0
4758 18:36:12.262268 rx_lastpass[1][0][1] = 0
4759 18:36:12.265489 rx_firspass[1][0][2] = 0
4760 18:36:12.268788 rx_lastpass[1][0][2] = 0
4761 18:36:12.269296 rx_firspass[1][0][3] = 0
4762 18:36:12.272071 rx_lastpass[1][0][3] = 0
4763 18:36:12.275482 rx_firspass[1][0][4] = 0
4764 18:36:12.275864 rx_lastpass[1][0][4] = 0
4765 18:36:12.279556 rx_firspass[1][0][5] = 0
4766 18:36:12.282425 rx_lastpass[1][0][5] = 0
4767 18:36:12.282912 rx_firspass[1][0][6] = 0
4768 18:36:12.285976 rx_lastpass[1][0][6] = 0
4769 18:36:12.289615 rx_firspass[1][0][7] = 0
4770 18:36:12.290103 rx_lastpass[1][0][7] = 0
4771 18:36:12.292136 rx_firspass[1][0][8] = 0
4772 18:36:12.295198 rx_lastpass[1][0][8] = 0
4773 18:36:12.295599 rx_firspass[1][0][9] = 0
4774 18:36:12.298751 rx_lastpass[1][0][9] = 0
4775 18:36:12.302401 rx_firspass[1][0][10] = 0
4776 18:36:12.305906 rx_lastpass[1][0][10] = 0
4777 18:36:12.306394 rx_firspass[1][0][11] = 0
4778 18:36:12.308933 rx_lastpass[1][0][11] = 0
4779 18:36:12.312321 rx_firspass[1][0][12] = 0
4780 18:36:12.312807 rx_lastpass[1][0][12] = 0
4781 18:36:12.315448 rx_firspass[1][0][13] = 0
4782 18:36:12.318614 rx_lastpass[1][0][13] = 0
4783 18:36:12.321801 rx_firspass[1][0][14] = 0
4784 18:36:12.322203 rx_lastpass[1][0][14] = 0
4785 18:36:12.325375 rx_firspass[1][0][15] = 0
4786 18:36:12.328430 rx_lastpass[1][0][15] = 0
4787 18:36:12.328889 rx_firspass[1][1][0] = 0
4788 18:36:12.331782 rx_lastpass[1][1][0] = 0
4789 18:36:12.335600 rx_firspass[1][1][1] = 0
4790 18:36:12.335995 rx_lastpass[1][1][1] = 0
4791 18:36:12.338666 rx_firspass[1][1][2] = 0
4792 18:36:12.342244 rx_lastpass[1][1][2] = 0
4793 18:36:12.345017 rx_firspass[1][1][3] = 0
4794 18:36:12.345413 rx_lastpass[1][1][3] = 0
4795 18:36:12.348355 rx_firspass[1][1][4] = 0
4796 18:36:12.352099 rx_lastpass[1][1][4] = 0
4797 18:36:12.352491 rx_firspass[1][1][5] = 0
4798 18:36:12.355166 rx_lastpass[1][1][5] = 0
4799 18:36:12.358777 rx_firspass[1][1][6] = 0
4800 18:36:12.359165 rx_lastpass[1][1][6] = 0
4801 18:36:12.361640 rx_firspass[1][1][7] = 0
4802 18:36:12.365269 rx_lastpass[1][1][7] = 0
4803 18:36:12.365771 rx_firspass[1][1][8] = 0
4804 18:36:12.368885 rx_lastpass[1][1][8] = 0
4805 18:36:12.371906 rx_firspass[1][1][9] = 0
4806 18:36:12.372301 rx_lastpass[1][1][9] = 0
4807 18:36:12.374828 rx_firspass[1][1][10] = 0
4808 18:36:12.378743 rx_lastpass[1][1][10] = 0
4809 18:36:12.382099 rx_firspass[1][1][11] = 0
4810 18:36:12.382596 rx_lastpass[1][1][11] = 0
4811 18:36:12.385514 rx_firspass[1][1][12] = 0
4812 18:36:12.388235 rx_lastpass[1][1][12] = 0
4813 18:36:12.388634 rx_firspass[1][1][13] = 0
4814 18:36:12.391884 rx_lastpass[1][1][13] = 0
4815 18:36:12.395105 rx_firspass[1][1][14] = 0
4816 18:36:12.398542 rx_lastpass[1][1][14] = 0
4817 18:36:12.399047 rx_firspass[1][1][15] = 0
4818 18:36:12.401894 rx_lastpass[1][1][15] = 0
4819 18:36:12.404775 dump params clk_delay
4820 18:36:12.405278 clk_delay[0] = 0
4821 18:36:12.407941 clk_delay[1] = 0
4822 18:36:12.408332 dump params dqs_delay
4823 18:36:12.411916 dqs_delay[0][0] = 0
4824 18:36:12.412416 dqs_delay[0][1] = 0
4825 18:36:12.415105 dqs_delay[1][0] = 0
4826 18:36:12.415646 dqs_delay[1][1] = 0
4827 18:36:12.418272 dump params delay_cell_unit = 735
4828 18:36:12.421288 dump source = 0x0
4829 18:36:12.421679 dump params frequency:800
4830 18:36:12.424672 dump params rank number:2
4831 18:36:12.425066
4832 18:36:12.428046 dump params write leveling
4833 18:36:12.432081 write leveling[0][0][0] = 0x0
4834 18:36:12.434908 write leveling[0][0][1] = 0x0
4835 18:36:12.435429 write leveling[0][1][0] = 0x0
4836 18:36:12.438373 write leveling[0][1][1] = 0x0
4837 18:36:12.441355 write leveling[1][0][0] = 0x0
4838 18:36:12.444647 write leveling[1][0][1] = 0x0
4839 18:36:12.447700 write leveling[1][1][0] = 0x0
4840 18:36:12.448097 write leveling[1][1][1] = 0x0
4841 18:36:12.451280 dump params cbt_cs
4842 18:36:12.454621 cbt_cs[0][0] = 0x0
4843 18:36:12.455014 cbt_cs[0][1] = 0x0
4844 18:36:12.457986 cbt_cs[1][0] = 0x0
4845 18:36:12.458461 cbt_cs[1][1] = 0x0
4846 18:36:12.460840 dump params cbt_mr12
4847 18:36:12.461231 cbt_mr12[0][0] = 0x0
4848 18:36:12.464105 cbt_mr12[0][1] = 0x0
4849 18:36:12.464525 cbt_mr12[1][0] = 0x0
4850 18:36:12.467642 cbt_mr12[1][1] = 0x0
4851 18:36:12.471061 dump params tx window
4852 18:36:12.471474 tx_center_min[0][0][0] = 0
4853 18:36:12.474196 tx_center_max[0][0][0] = 0
4854 18:36:12.477570 tx_center_min[0][0][1] = 0
4855 18:36:12.477964 tx_center_max[0][0][1] = 0
4856 18:36:12.481150 tx_center_min[0][1][0] = 0
4857 18:36:12.484164 tx_center_max[0][1][0] = 0
4858 18:36:12.487465 tx_center_min[0][1][1] = 0
4859 18:36:12.487860 tx_center_max[0][1][1] = 0
4860 18:36:12.491318 tx_center_min[1][0][0] = 0
4861 18:36:12.494694 tx_center_max[1][0][0] = 0
4862 18:36:12.497856 tx_center_min[1][0][1] = 0
4863 18:36:12.498254 tx_center_max[1][0][1] = 0
4864 18:36:12.500889 tx_center_min[1][1][0] = 0
4865 18:36:12.504375 tx_center_max[1][1][0] = 0
4866 18:36:12.508086 tx_center_min[1][1][1] = 0
4867 18:36:12.508588 tx_center_max[1][1][1] = 0
4868 18:36:12.511566 dump params tx window
4869 18:36:12.514346 tx_win_center[0][0][0] = 0
4870 18:36:12.514839 tx_first_pass[0][0][0] = 0
4871 18:36:12.517705 tx_last_pass[0][0][0] = 0
4872 18:36:12.521249 tx_win_center[0][0][1] = 0
4873 18:36:12.524200 tx_first_pass[0][0][1] = 0
4874 18:36:12.524598 tx_last_pass[0][0][1] = 0
4875 18:36:12.527886 tx_win_center[0][0][2] = 0
4876 18:36:12.531115 tx_first_pass[0][0][2] = 0
4877 18:36:12.531554 tx_last_pass[0][0][2] = 0
4878 18:36:12.533895 tx_win_center[0][0][3] = 0
4879 18:36:12.537629 tx_first_pass[0][0][3] = 0
4880 18:36:12.540894 tx_last_pass[0][0][3] = 0
4881 18:36:12.541302 tx_win_center[0][0][4] = 0
4882 18:36:12.543718 tx_first_pass[0][0][4] = 0
4883 18:36:12.547218 tx_last_pass[0][0][4] = 0
4884 18:36:12.550958 tx_win_center[0][0][5] = 0
4885 18:36:12.551374 tx_first_pass[0][0][5] = 0
4886 18:36:12.553865 tx_last_pass[0][0][5] = 0
4887 18:36:12.557025 tx_win_center[0][0][6] = 0
4888 18:36:12.560504 tx_first_pass[0][0][6] = 0
4889 18:36:12.560798 tx_last_pass[0][0][6] = 0
4890 18:36:12.563618 tx_win_center[0][0][7] = 0
4891 18:36:12.567428 tx_first_pass[0][0][7] = 0
4892 18:36:12.567643 tx_last_pass[0][0][7] = 0
4893 18:36:12.570625 tx_win_center[0][0][8] = 0
4894 18:36:12.573561 tx_first_pass[0][0][8] = 0
4895 18:36:12.577063 tx_last_pass[0][0][8] = 0
4896 18:36:12.577228 tx_win_center[0][0][9] = 0
4897 18:36:12.580339 tx_first_pass[0][0][9] = 0
4898 18:36:12.583361 tx_last_pass[0][0][9] = 0
4899 18:36:12.586926 tx_win_center[0][0][10] = 0
4900 18:36:12.587129 tx_first_pass[0][0][10] = 0
4901 18:36:12.590129 tx_last_pass[0][0][10] = 0
4902 18:36:12.593339 tx_win_center[0][0][11] = 0
4903 18:36:12.596830 tx_first_pass[0][0][11] = 0
4904 18:36:12.596966 tx_last_pass[0][0][11] = 0
4905 18:36:12.599994 tx_win_center[0][0][12] = 0
4906 18:36:12.603438 tx_first_pass[0][0][12] = 0
4907 18:36:12.606681 tx_last_pass[0][0][12] = 0
4908 18:36:12.606832 tx_win_center[0][0][13] = 0
4909 18:36:12.610237 tx_first_pass[0][0][13] = 0
4910 18:36:12.613578 tx_last_pass[0][0][13] = 0
4911 18:36:12.616653 tx_win_center[0][0][14] = 0
4912 18:36:12.616798 tx_first_pass[0][0][14] = 0
4913 18:36:12.619887 tx_last_pass[0][0][14] = 0
4914 18:36:12.623122 tx_win_center[0][0][15] = 0
4915 18:36:12.626486 tx_first_pass[0][0][15] = 0
4916 18:36:12.626611 tx_last_pass[0][0][15] = 0
4917 18:36:12.629974 tx_win_center[0][1][0] = 0
4918 18:36:12.633571 tx_first_pass[0][1][0] = 0
4919 18:36:12.636778 tx_last_pass[0][1][0] = 0
4920 18:36:12.636899 tx_win_center[0][1][1] = 0
4921 18:36:12.639677 tx_first_pass[0][1][1] = 0
4922 18:36:12.643016 tx_last_pass[0][1][1] = 0
4923 18:36:12.643150 tx_win_center[0][1][2] = 0
4924 18:36:12.646694 tx_first_pass[0][1][2] = 0
4925 18:36:12.650300 tx_last_pass[0][1][2] = 0
4926 18:36:12.652990 tx_win_center[0][1][3] = 0
4927 18:36:12.653167 tx_first_pass[0][1][3] = 0
4928 18:36:12.656513 tx_last_pass[0][1][3] = 0
4929 18:36:12.659691 tx_win_center[0][1][4] = 0
4930 18:36:12.663073 tx_first_pass[0][1][4] = 0
4931 18:36:12.663251 tx_last_pass[0][1][4] = 0
4932 18:36:12.666594 tx_win_center[0][1][5] = 0
4933 18:36:12.669785 tx_first_pass[0][1][5] = 0
4934 18:36:12.669920 tx_last_pass[0][1][5] = 0
4935 18:36:12.673140 tx_win_center[0][1][6] = 0
4936 18:36:12.676474 tx_first_pass[0][1][6] = 0
4937 18:36:12.679617 tx_last_pass[0][1][6] = 0
4938 18:36:12.679730 tx_win_center[0][1][7] = 0
4939 18:36:12.682911 tx_first_pass[0][1][7] = 0
4940 18:36:12.686164 tx_last_pass[0][1][7] = 0
4941 18:36:12.689707 tx_win_center[0][1][8] = 0
4942 18:36:12.689816 tx_first_pass[0][1][8] = 0
4943 18:36:12.692765 tx_last_pass[0][1][8] = 0
4944 18:36:12.696264 tx_win_center[0][1][9] = 0
4945 18:36:12.696365 tx_first_pass[0][1][9] = 0
4946 18:36:12.699788 tx_last_pass[0][1][9] = 0
4947 18:36:12.703105 tx_win_center[0][1][10] = 0
4948 18:36:12.706350 tx_first_pass[0][1][10] = 0
4949 18:36:12.706448 tx_last_pass[0][1][10] = 0
4950 18:36:12.709497 tx_win_center[0][1][11] = 0
4951 18:36:12.712921 tx_first_pass[0][1][11] = 0
4952 18:36:12.716064 tx_last_pass[0][1][11] = 0
4953 18:36:12.716160 tx_win_center[0][1][12] = 0
4954 18:36:12.719307 tx_first_pass[0][1][12] = 0
4955 18:36:12.722524 tx_last_pass[0][1][12] = 0
4956 18:36:12.726007 tx_win_center[0][1][13] = 0
4957 18:36:12.726133 tx_first_pass[0][1][13] = 0
4958 18:36:12.729602 tx_last_pass[0][1][13] = 0
4959 18:36:12.732697 tx_win_center[0][1][14] = 0
4960 18:36:12.735956 tx_first_pass[0][1][14] = 0
4961 18:36:12.736052 tx_last_pass[0][1][14] = 0
4962 18:36:12.739268 tx_win_center[0][1][15] = 0
4963 18:36:12.742966 tx_first_pass[0][1][15] = 0
4964 18:36:12.746272 tx_last_pass[0][1][15] = 0
4965 18:36:12.746365 tx_win_center[1][0][0] = 0
4966 18:36:12.749210 tx_first_pass[1][0][0] = 0
4967 18:36:12.752796 tx_last_pass[1][0][0] = 0
4968 18:36:12.756179 tx_win_center[1][0][1] = 0
4969 18:36:12.756340 tx_first_pass[1][0][1] = 0
4970 18:36:12.759430 tx_last_pass[1][0][1] = 0
4971 18:36:12.762729 tx_win_center[1][0][2] = 0
4972 18:36:12.765776 tx_first_pass[1][0][2] = 0
4973 18:36:12.765976 tx_last_pass[1][0][2] = 0
4974 18:36:12.769282 tx_win_center[1][0][3] = 0
4975 18:36:12.772678 tx_first_pass[1][0][3] = 0
4976 18:36:12.772849 tx_last_pass[1][0][3] = 0
4977 18:36:12.775956 tx_win_center[1][0][4] = 0
4978 18:36:12.779248 tx_first_pass[1][0][4] = 0
4979 18:36:12.782631 tx_last_pass[1][0][4] = 0
4980 18:36:12.782786 tx_win_center[1][0][5] = 0
4981 18:36:12.785755 tx_first_pass[1][0][5] = 0
4982 18:36:12.789125 tx_last_pass[1][0][5] = 0
4983 18:36:12.792497 tx_win_center[1][0][6] = 0
4984 18:36:12.792602 tx_first_pass[1][0][6] = 0
4985 18:36:12.795883 tx_last_pass[1][0][6] = 0
4986 18:36:12.799206 tx_win_center[1][0][7] = 0
4987 18:36:12.799304 tx_first_pass[1][0][7] = 0
4988 18:36:12.802862 tx_last_pass[1][0][7] = 0
4989 18:36:12.805673 tx_win_center[1][0][8] = 0
4990 18:36:12.809004 tx_first_pass[1][0][8] = 0
4991 18:36:12.809131 tx_last_pass[1][0][8] = 0
4992 18:36:12.812300 tx_win_center[1][0][9] = 0
4993 18:36:12.815631 tx_first_pass[1][0][9] = 0
4994 18:36:12.819222 tx_last_pass[1][0][9] = 0
4995 18:36:12.819314 tx_win_center[1][0][10] = 0
4996 18:36:12.822626 tx_first_pass[1][0][10] = 0
4997 18:36:12.825670 tx_last_pass[1][0][10] = 0
4998 18:36:12.828921 tx_win_center[1][0][11] = 0
4999 18:36:12.829013 tx_first_pass[1][0][11] = 0
5000 18:36:12.832622 tx_last_pass[1][0][11] = 0
5001 18:36:12.836006 tx_win_center[1][0][12] = 0
5002 18:36:12.839184 tx_first_pass[1][0][12] = 0
5003 18:36:12.839276 tx_last_pass[1][0][12] = 0
5004 18:36:12.842223 tx_win_center[1][0][13] = 0
5005 18:36:12.845417 tx_first_pass[1][0][13] = 0
5006 18:36:12.848750 tx_last_pass[1][0][13] = 0
5007 18:36:12.848842 tx_win_center[1][0][14] = 0
5008 18:36:12.852279 tx_first_pass[1][0][14] = 0
5009 18:36:12.855458 tx_last_pass[1][0][14] = 0
5010 18:36:12.858900 tx_win_center[1][0][15] = 0
5011 18:36:12.859008 tx_first_pass[1][0][15] = 0
5012 18:36:12.862368 tx_last_pass[1][0][15] = 0
5013 18:36:12.865340 tx_win_center[1][1][0] = 0
5014 18:36:12.868853 tx_first_pass[1][1][0] = 0
5015 18:36:12.868981 tx_last_pass[1][1][0] = 0
5016 18:36:12.872351 tx_win_center[1][1][1] = 0
5017 18:36:12.875558 tx_first_pass[1][1][1] = 0
5018 18:36:12.875701 tx_last_pass[1][1][1] = 0
5019 18:36:12.878681 tx_win_center[1][1][2] = 0
5020 18:36:12.881869 tx_first_pass[1][1][2] = 0
5021 18:36:12.885351 tx_last_pass[1][1][2] = 0
5022 18:36:12.885539 tx_win_center[1][1][3] = 0
5023 18:36:12.888801 tx_first_pass[1][1][3] = 0
5024 18:36:12.892048 tx_last_pass[1][1][3] = 0
5025 18:36:12.895452 tx_win_center[1][1][4] = 0
5026 18:36:12.895721 tx_first_pass[1][1][4] = 0
5027 18:36:12.898963 tx_last_pass[1][1][4] = 0
5028 18:36:12.902312 tx_win_center[1][1][5] = 0
5029 18:36:12.902662 tx_first_pass[1][1][5] = 0
5030 18:36:12.906046 tx_last_pass[1][1][5] = 0
5031 18:36:12.908776 tx_win_center[1][1][6] = 0
5032 18:36:12.912201 tx_first_pass[1][1][6] = 0
5033 18:36:12.912551 tx_last_pass[1][1][6] = 0
5034 18:36:12.915873 tx_win_center[1][1][7] = 0
5035 18:36:12.918718 tx_first_pass[1][1][7] = 0
5036 18:36:12.922512 tx_last_pass[1][1][7] = 0
5037 18:36:12.922921 tx_win_center[1][1][8] = 0
5038 18:36:12.925749 tx_first_pass[1][1][8] = 0
5039 18:36:12.928854 tx_last_pass[1][1][8] = 0
5040 18:36:12.929200 tx_win_center[1][1][9] = 0
5041 18:36:12.932027 tx_first_pass[1][1][9] = 0
5042 18:36:12.935201 tx_last_pass[1][1][9] = 0
5043 18:36:12.938896 tx_win_center[1][1][10] = 0
5044 18:36:12.939244 tx_first_pass[1][1][10] = 0
5045 18:36:12.942316 tx_last_pass[1][1][10] = 0
5046 18:36:12.945844 tx_win_center[1][1][11] = 0
5047 18:36:12.949238 tx_first_pass[1][1][11] = 0
5048 18:36:12.949703 tx_last_pass[1][1][11] = 0
5049 18:36:12.952039 tx_win_center[1][1][12] = 0
5050 18:36:12.955908 tx_first_pass[1][1][12] = 0
5051 18:36:12.958957 tx_last_pass[1][1][12] = 0
5052 18:36:12.959321 tx_win_center[1][1][13] = 0
5053 18:36:12.961972 tx_first_pass[1][1][13] = 0
5054 18:36:12.965592 tx_last_pass[1][1][13] = 0
5055 18:36:12.968659 tx_win_center[1][1][14] = 0
5056 18:36:12.969017 tx_first_pass[1][1][14] = 0
5057 18:36:12.971808 tx_last_pass[1][1][14] = 0
5058 18:36:12.975371 tx_win_center[1][1][15] = 0
5059 18:36:12.978760 tx_first_pass[1][1][15] = 0
5060 18:36:12.979117 tx_last_pass[1][1][15] = 0
5061 18:36:12.982185 dump params rx window
5062 18:36:12.984859 rx_firspass[0][0][0] = 0
5063 18:36:12.985216 rx_lastpass[0][0][0] = 0
5064 18:36:12.988445 rx_firspass[0][0][1] = 0
5065 18:36:12.991908 rx_lastpass[0][0][1] = 0
5066 18:36:12.992270 rx_firspass[0][0][2] = 0
5067 18:36:12.995384 rx_lastpass[0][0][2] = 0
5068 18:36:12.998514 rx_firspass[0][0][3] = 0
5069 18:36:13.002224 rx_lastpass[0][0][3] = 0
5070 18:36:13.002677 rx_firspass[0][0][4] = 0
5071 18:36:13.005456 rx_lastpass[0][0][4] = 0
5072 18:36:13.008303 rx_firspass[0][0][5] = 0
5073 18:36:13.008747 rx_lastpass[0][0][5] = 0
5074 18:36:13.012030 rx_firspass[0][0][6] = 0
5075 18:36:13.015290 rx_lastpass[0][0][6] = 0
5076 18:36:13.015703 rx_firspass[0][0][7] = 0
5077 18:36:13.018745 rx_lastpass[0][0][7] = 0
5078 18:36:13.021884 rx_firspass[0][0][8] = 0
5079 18:36:13.022240 rx_lastpass[0][0][8] = 0
5080 18:36:13.025220 rx_firspass[0][0][9] = 0
5081 18:36:13.028362 rx_lastpass[0][0][9] = 0
5082 18:36:13.028715 rx_firspass[0][0][10] = 0
5083 18:36:13.031823 rx_lastpass[0][0][10] = 0
5084 18:36:13.035365 rx_firspass[0][0][11] = 0
5085 18:36:13.038505 rx_lastpass[0][0][11] = 0
5086 18:36:13.038862 rx_firspass[0][0][12] = 0
5087 18:36:13.041534 rx_lastpass[0][0][12] = 0
5088 18:36:13.045378 rx_firspass[0][0][13] = 0
5089 18:36:13.048307 rx_lastpass[0][0][13] = 0
5090 18:36:13.048691 rx_firspass[0][0][14] = 0
5091 18:36:13.051507 rx_lastpass[0][0][14] = 0
5092 18:36:13.054974 rx_firspass[0][0][15] = 0
5093 18:36:13.055320 rx_lastpass[0][0][15] = 0
5094 18:36:13.058706 rx_firspass[0][1][0] = 0
5095 18:36:13.061622 rx_lastpass[0][1][0] = 0
5096 18:36:13.061968 rx_firspass[0][1][1] = 0
5097 18:36:13.065096 rx_lastpass[0][1][1] = 0
5098 18:36:13.068467 rx_firspass[0][1][2] = 0
5099 18:36:13.068814 rx_lastpass[0][1][2] = 0
5100 18:36:13.071779 rx_firspass[0][1][3] = 0
5101 18:36:13.074814 rx_lastpass[0][1][3] = 0
5102 18:36:13.078403 rx_firspass[0][1][4] = 0
5103 18:36:13.078758 rx_lastpass[0][1][4] = 0
5104 18:36:13.081906 rx_firspass[0][1][5] = 0
5105 18:36:13.085467 rx_lastpass[0][1][5] = 0
5106 18:36:13.085823 rx_firspass[0][1][6] = 0
5107 18:36:13.088059 rx_lastpass[0][1][6] = 0
5108 18:36:13.091531 rx_firspass[0][1][7] = 0
5109 18:36:13.091878 rx_lastpass[0][1][7] = 0
5110 18:36:13.095001 rx_firspass[0][1][8] = 0
5111 18:36:13.098807 rx_lastpass[0][1][8] = 0
5112 18:36:13.099162 rx_firspass[0][1][9] = 0
5113 18:36:13.101402 rx_lastpass[0][1][9] = 0
5114 18:36:13.105295 rx_firspass[0][1][10] = 0
5115 18:36:13.108540 rx_lastpass[0][1][10] = 0
5116 18:36:13.108890 rx_firspass[0][1][11] = 0
5117 18:36:13.111665 rx_lastpass[0][1][11] = 0
5118 18:36:13.115154 rx_firspass[0][1][12] = 0
5119 18:36:13.115545 rx_lastpass[0][1][12] = 0
5120 18:36:13.117936 rx_firspass[0][1][13] = 0
5121 18:36:13.121691 rx_lastpass[0][1][13] = 0
5122 18:36:13.124912 rx_firspass[0][1][14] = 0
5123 18:36:13.125258 rx_lastpass[0][1][14] = 0
5124 18:36:13.127779 rx_firspass[0][1][15] = 0
5125 18:36:13.131455 rx_lastpass[0][1][15] = 0
5126 18:36:13.131813 rx_firspass[1][0][0] = 0
5127 18:36:13.134825 rx_lastpass[1][0][0] = 0
5128 18:36:13.138454 rx_firspass[1][0][1] = 0
5129 18:36:13.138809 rx_lastpass[1][0][1] = 0
5130 18:36:13.141475 rx_firspass[1][0][2] = 0
5131 18:36:13.144717 rx_lastpass[1][0][2] = 0
5132 18:36:13.145072 rx_firspass[1][0][3] = 0
5133 18:36:13.148148 rx_lastpass[1][0][3] = 0
5134 18:36:13.151660 rx_firspass[1][0][4] = 0
5135 18:36:13.154692 rx_lastpass[1][0][4] = 0
5136 18:36:13.155045 rx_firspass[1][0][5] = 0
5137 18:36:13.158318 rx_lastpass[1][0][5] = 0
5138 18:36:13.161838 rx_firspass[1][0][6] = 0
5139 18:36:13.162195 rx_lastpass[1][0][6] = 0
5140 18:36:13.165194 rx_firspass[1][0][7] = 0
5141 18:36:13.168135 rx_lastpass[1][0][7] = 0
5142 18:36:13.168621 rx_firspass[1][0][8] = 0
5143 18:36:13.171652 rx_lastpass[1][0][8] = 0
5144 18:36:13.174454 rx_firspass[1][0][9] = 0
5145 18:36:13.174915 rx_lastpass[1][0][9] = 0
5146 18:36:13.178183 rx_firspass[1][0][10] = 0
5147 18:36:13.181525 rx_lastpass[1][0][10] = 0
5148 18:36:13.181882 rx_firspass[1][0][11] = 0
5149 18:36:13.185247 rx_lastpass[1][0][11] = 0
5150 18:36:13.188158 rx_firspass[1][0][12] = 0
5151 18:36:13.191674 rx_lastpass[1][0][12] = 0
5152 18:36:13.192137 rx_firspass[1][0][13] = 0
5153 18:36:13.194692 rx_lastpass[1][0][13] = 0
5154 18:36:13.198634 rx_firspass[1][0][14] = 0
5155 18:36:13.199029 rx_lastpass[1][0][14] = 0
5156 18:36:13.202122 rx_firspass[1][0][15] = 0
5157 18:36:13.204921 rx_lastpass[1][0][15] = 0
5158 18:36:13.208227 rx_firspass[1][1][0] = 0
5159 18:36:13.208575 rx_lastpass[1][1][0] = 0
5160 18:36:13.211280 rx_firspass[1][1][1] = 0
5161 18:36:13.214892 rx_lastpass[1][1][1] = 0
5162 18:36:13.215242 rx_firspass[1][1][2] = 0
5163 18:36:13.218116 rx_lastpass[1][1][2] = 0
5164 18:36:13.221197 rx_firspass[1][1][3] = 0
5165 18:36:13.221557 rx_lastpass[1][1][3] = 0
5166 18:36:13.224323 rx_firspass[1][1][4] = 0
5167 18:36:13.227850 rx_lastpass[1][1][4] = 0
5168 18:36:13.228204 rx_firspass[1][1][5] = 0
5169 18:36:13.231041 rx_lastpass[1][1][5] = 0
5170 18:36:13.234369 rx_firspass[1][1][6] = 0
5171 18:36:13.237669 rx_lastpass[1][1][6] = 0
5172 18:36:13.238093 rx_firspass[1][1][7] = 0
5173 18:36:13.241114 rx_lastpass[1][1][7] = 0
5174 18:36:13.244526 rx_firspass[1][1][8] = 0
5175 18:36:13.244881 rx_lastpass[1][1][8] = 0
5176 18:36:13.247702 rx_firspass[1][1][9] = 0
5177 18:36:13.250848 rx_lastpass[1][1][9] = 0
5178 18:36:13.251104 rx_firspass[1][1][10] = 0
5179 18:36:13.254362 rx_lastpass[1][1][10] = 0
5180 18:36:13.257203 rx_firspass[1][1][11] = 0
5181 18:36:13.260551 rx_lastpass[1][1][11] = 0
5182 18:36:13.260718 rx_firspass[1][1][12] = 0
5183 18:36:13.264090 rx_lastpass[1][1][12] = 0
5184 18:36:13.267285 rx_firspass[1][1][13] = 0
5185 18:36:13.267442 rx_lastpass[1][1][13] = 0
5186 18:36:13.271066 rx_firspass[1][1][14] = 0
5187 18:36:13.274267 rx_lastpass[1][1][14] = 0
5188 18:36:13.277237 rx_firspass[1][1][15] = 0
5189 18:36:13.277344 rx_lastpass[1][1][15] = 0
5190 18:36:13.280935 dump params clk_delay
5191 18:36:13.281031 clk_delay[0] = 0
5192 18:36:13.284360 clk_delay[1] = 0
5193 18:36:13.284456 dump params dqs_delay
5194 18:36:13.287376 dqs_delay[0][0] = 0
5195 18:36:13.287476 dqs_delay[0][1] = 0
5196 18:36:13.290831 dqs_delay[1][0] = 0
5197 18:36:13.293790 dqs_delay[1][1] = 0
5198 18:36:13.293881 dump params delay_cell_unit = 735
5199 18:36:13.297245 mt_set_emi_preloader end
5200 18:36:13.303671 [mt_mem_init] dram size: 0x100000000, rank number: 2
5201 18:36:13.307167 [complex_mem_test] start addr:0x40000000, len:20480
5202 18:36:13.343726 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5203 18:36:13.350280 [complex_mem_test] start addr:0x80000000, len:20480
5204 18:36:13.385854 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5205 18:36:13.392160 [complex_mem_test] start addr:0xc0000000, len:20480
5206 18:36:13.428272 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5207 18:36:13.434773 [complex_mem_test] start addr:0x56000000, len:8192
5208 18:36:13.451702 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5209 18:36:13.451819 ddr_geometry:1
5210 18:36:13.458537 [complex_mem_test] start addr:0x80000000, len:8192
5211 18:36:13.475365 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5212 18:36:13.478550 dram_init: dram init end (result: 0)
5213 18:36:13.485202 Successfully loaded DRAM blobs and ran DRAM calibration
5214 18:36:13.495025 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5215 18:36:13.495131 CBMEM:
5216 18:36:13.498632 IMD: root @ 00000000fffff000 254 entries.
5217 18:36:13.502102 IMD: root @ 00000000ffffec00 62 entries.
5218 18:36:13.508501 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5219 18:36:13.515050 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5220 18:36:13.518658 in-header: 03 a1 00 00 08 00 00 00
5221 18:36:13.521601 in-data: 84 60 60 10 00 00 00 00
5222 18:36:13.524922 Chrome EC: clear events_b mask to 0x0000000020004000
5223 18:36:13.532440 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5224 18:36:13.536071 in-header: 03 fd 00 00 00 00 00 00
5225 18:36:13.536161 in-data:
5226 18:36:13.542274 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5227 18:36:13.542365 CBFS @ 21000 size 3d4000
5228 18:36:13.548799 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5229 18:36:13.552372 CBFS: Locating 'fallback/ramstage'
5230 18:36:13.555793 CBFS: Found @ offset 10d40 size d563
5231 18:36:13.577105 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5232 18:36:13.589412 Accumulated console time in romstage 13552 ms
5233 18:36:13.589557
5234 18:36:13.589630
5235 18:36:13.599266 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5236 18:36:13.602357 ARM64: Exception handlers installed.
5237 18:36:13.602449 ARM64: Testing exception
5238 18:36:13.606309 ARM64: Done test exception
5239 18:36:13.609600 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5240 18:36:13.612571 Manufacturer: ef
5241 18:36:13.615739 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5242 18:36:13.623042 WARNING: RO_VPD is uninitialized or empty.
5243 18:36:13.625776 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5244 18:36:13.628811 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5245 18:36:13.639416 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5246 18:36:13.642185 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5247 18:36:13.649367 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5248 18:36:13.649560 Enumerating buses...
5249 18:36:13.656128 Show all devs... Before device enumeration.
5250 18:36:13.656335 Root Device: enabled 1
5251 18:36:13.658819 CPU_CLUSTER: 0: enabled 1
5252 18:36:13.659016 CPU: 00: enabled 1
5253 18:36:13.662551 Compare with tree...
5254 18:36:13.665607 Root Device: enabled 1
5255 18:36:13.665883 CPU_CLUSTER: 0: enabled 1
5256 18:36:13.669147 CPU: 00: enabled 1
5257 18:36:13.672578 Root Device scanning...
5258 18:36:13.672881 root_dev_scan_bus for Root Device
5259 18:36:13.675517 CPU_CLUSTER: 0 enabled
5260 18:36:13.679028 root_dev_scan_bus for Root Device done
5261 18:36:13.685828 scan_bus: scanning of bus Root Device took 10689 usecs
5262 18:36:13.686279 done
5263 18:36:13.689158 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5264 18:36:13.692928 Allocating resources...
5265 18:36:13.693434 Reading resources...
5266 18:36:13.699508 Root Device read_resources bus 0 link: 0
5267 18:36:13.702435 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5268 18:36:13.706099 CPU: 00 missing read_resources
5269 18:36:13.709449 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5270 18:36:13.712296 Root Device read_resources bus 0 link: 0 done
5271 18:36:13.715341 Done reading resources.
5272 18:36:13.718879 Show resources in subtree (Root Device)...After reading.
5273 18:36:13.722149 Root Device child on link 0 CPU_CLUSTER: 0
5274 18:36:13.728733 CPU_CLUSTER: 0 child on link 0 CPU: 00
5275 18:36:13.734949 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5276 18:36:13.735375 CPU: 00
5277 18:36:13.738403 Setting resources...
5278 18:36:13.741865 Root Device assign_resources, bus 0 link: 0
5279 18:36:13.745246 CPU_CLUSTER: 0 missing set_resources
5280 18:36:13.748874 Root Device assign_resources, bus 0 link: 0
5281 18:36:13.752016 Done setting resources.
5282 18:36:13.758375 Show resources in subtree (Root Device)...After assigning values.
5283 18:36:13.761713 Root Device child on link 0 CPU_CLUSTER: 0
5284 18:36:13.765025 CPU_CLUSTER: 0 child on link 0 CPU: 00
5285 18:36:13.775113 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5286 18:36:13.775662 CPU: 00
5287 18:36:13.778096 Done allocating resources.
5288 18:36:13.782030 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5289 18:36:13.785022 Enabling resources...
5290 18:36:13.785441 done.
5291 18:36:13.788496 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5292 18:36:13.791555 Initializing devices...
5293 18:36:13.791951 Root Device init ...
5294 18:36:13.798423 mainboard_init: Starting display init.
5295 18:36:13.798819 ADC[4]: Raw value=75746 ID=0
5296 18:36:13.821612 anx7625_power_on_init: Init interface.
5297 18:36:13.825064 anx7625_disable_pd_protocol: Disabled PD feature.
5298 18:36:13.831963 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5299 18:36:13.878662 anx7625_start_dp_work: Secure OCM version=00
5300 18:36:13.882018 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5301 18:36:13.899013 sp_tx_get_edid_block: EDID Block = 1
5302 18:36:14.016852 Extracted contents:
5303 18:36:14.019513 header: 00 ff ff ff ff ff ff 00
5304 18:36:14.023339 serial number: 06 af 5c 14 00 00 00 00 00 1a
5305 18:36:14.026995 version: 01 04
5306 18:36:14.029812 basic params: 95 1a 0e 78 02
5307 18:36:14.033239 chroma info: 99 85 95 55 56 92 28 22 50 54
5308 18:36:14.036199 established: 00 00 00
5309 18:36:14.042716 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5310 18:36:14.046385 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5311 18:36:14.052863 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5312 18:36:14.059240 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5313 18:36:14.066173 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5314 18:36:14.069870 extensions: 00
5315 18:36:14.070396 checksum: ae
5316 18:36:14.070832
5317 18:36:14.073161 Manufacturer: AUO Model 145c Serial Number 0
5318 18:36:14.076139 Made week 0 of 2016
5319 18:36:14.076566 EDID version: 1.4
5320 18:36:14.079983 Digital display
5321 18:36:14.082870 6 bits per primary color channel
5322 18:36:14.083439 DisplayPort interface
5323 18:36:14.086400 Maximum image size: 26 cm x 14 cm
5324 18:36:14.089549 Gamma: 220%
5325 18:36:14.089973 Check DPMS levels
5326 18:36:14.092609 Supported color formats: RGB 4:4:4
5327 18:36:14.095836 First detailed timing is preferred timing
5328 18:36:14.099678 Established timings supported:
5329 18:36:14.102608 Standard timings supported:
5330 18:36:14.103133 Detailed timings
5331 18:36:14.109996 Hex of detail: ce1d56ea50001a3030204600009010000018
5332 18:36:14.113082 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5333 18:36:14.116066 0556 0586 05a6 0640 hborder 0
5334 18:36:14.119639 0300 0304 030a 031a vborder 0
5335 18:36:14.123111 -hsync -vsync
5336 18:36:14.125713 Did detailed timing
5337 18:36:14.129092 Hex of detail: 0000000f0000000000000000000000000020
5338 18:36:14.132725 Manufacturer-specified data, tag 15
5339 18:36:14.139522 Hex of detail: 000000fe0041554f0a202020202020202020
5340 18:36:14.140030 ASCII string: AUO
5341 18:36:14.142715 Hex of detail: 000000fe004231313658414230312e34200a
5342 18:36:14.145663 ASCII string: B116XAB01.4
5343 18:36:14.146071 Checksum
5344 18:36:14.149311 Checksum: 0xae (valid)
5345 18:36:14.156103 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5346 18:36:14.156664 DSI data_rate: 457800000 bps
5347 18:36:14.163629 anx7625_parse_edid: set default k value to 0x3d for panel
5348 18:36:14.166970 anx7625_parse_edid: pixelclock(76300).
5349 18:36:14.170334 hactive(1366), hsync(32), hfp(48), hbp(154)
5350 18:36:14.173510 vactive(768), vsync(6), vfp(4), vbp(16)
5351 18:36:14.176903 anx7625_dsi_config: config dsi.
5352 18:36:14.185509 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5353 18:36:14.205570 anx7625_dsi_config: success to config DSI
5354 18:36:14.209081 anx7625_dp_start: MIPI phy setup OK.
5355 18:36:14.212831 [SSUSB] Setting up USB HOST controller...
5356 18:36:14.215663 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5357 18:36:14.219570 [SSUSB] phy power-on done.
5358 18:36:14.222858 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5359 18:36:14.225941 in-header: 03 fc 01 00 00 00 00 00
5360 18:36:14.226352 in-data:
5361 18:36:14.232677 handle_proto3_response: EC response with error code: 1
5362 18:36:14.233089 SPM: pcm index = 1
5363 18:36:14.236056 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5364 18:36:14.239100 CBFS @ 21000 size 3d4000
5365 18:36:14.245905 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5366 18:36:14.249161 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5367 18:36:14.252947 CBFS: Found @ offset 1e7c0 size 1026
5368 18:36:14.259036 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5369 18:36:14.262880 SPM: binary array size = 2988
5370 18:36:14.266136 SPM: version = pcm_allinone_v1.17.2_20180829
5371 18:36:14.269304 SPM binary loaded in 32 msecs
5372 18:36:14.277155 spm_kick_im_to_fetch: ptr = 000000004021eec2
5373 18:36:14.280118 spm_kick_im_to_fetch: len = 2988
5374 18:36:14.280493 SPM: spm_kick_pcm_to_run
5375 18:36:14.283385 SPM: spm_kick_pcm_to_run done
5376 18:36:14.286913 SPM: spm_init done in 52 msecs
5377 18:36:14.290018 Root Device init finished in 494996 usecs
5378 18:36:14.293444 CPU_CLUSTER: 0 init ...
5379 18:36:14.303585 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5380 18:36:14.307077 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5381 18:36:14.310493 CBFS @ 21000 size 3d4000
5382 18:36:14.313689 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5383 18:36:14.316942 CBFS: Locating 'sspm.bin'
5384 18:36:14.320454 CBFS: Found @ offset 208c0 size 41cb
5385 18:36:14.330382 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5386 18:36:14.338031 CPU_CLUSTER: 0 init finished in 42804 usecs
5387 18:36:14.338540 Devices initialized
5388 18:36:14.341633 Show all devs... After init.
5389 18:36:14.344228 Root Device: enabled 1
5390 18:36:14.344638 CPU_CLUSTER: 0: enabled 1
5391 18:36:14.347676 CPU: 00: enabled 1
5392 18:36:14.350996 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5393 18:36:14.354505 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5394 18:36:14.358067 ELOG: NV offset 0x558000 size 0x1000
5395 18:36:14.365825 read SPI 0x558000 0x1000: 1265 us, 3237 KB/s, 25.896 Mbps
5396 18:36:14.372362 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5397 18:36:14.375948 ELOG: Event(17) added with size 13 at 2024-06-11 18:35:16 UTC
5398 18:36:14.378869 out: cmd=0x121: 03 db 21 01 00 00 00 00
5399 18:36:14.382200 in-header: 03 f6 00 00 2c 00 00 00
5400 18:36:14.396067 in-data: df 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 df b9 04 00 06 80 00 00 79 fa 00 00 06 80 00 00 97 bf 03 00 06 80 00 00 16 04 05 00
5401 18:36:14.399162 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5402 18:36:14.402904 in-header: 03 19 00 00 08 00 00 00
5403 18:36:14.405646 in-data: a2 e0 47 00 13 00 00 00
5404 18:36:14.409192 Chrome EC: UHEPI supported
5405 18:36:14.415583 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5406 18:36:14.419001 in-header: 03 e1 00 00 08 00 00 00
5407 18:36:14.421782 in-data: 84 20 60 10 00 00 00 00
5408 18:36:14.425682 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5409 18:36:14.431997 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5410 18:36:14.435841 in-header: 03 e1 00 00 08 00 00 00
5411 18:36:14.439203 in-data: 84 20 60 10 00 00 00 00
5412 18:36:14.445631 ELOG: Event(A1) added with size 10 at 2024-06-11 18:35:16 UTC
5413 18:36:14.452201 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5414 18:36:14.454778 ELOG: Event(A0) added with size 9 at 2024-06-11 18:35:16 UTC
5415 18:36:14.462411 elog_add_boot_reason: Logged dev mode boot
5416 18:36:14.462933 Finalize devices...
5417 18:36:14.465814 Devices finalized
5418 18:36:14.468852 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5419 18:36:14.471679 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5420 18:36:14.478714 ELOG: Event(91) added with size 10 at 2024-06-11 18:35:16 UTC
5421 18:36:14.481561 Writing coreboot table at 0xffeda000
5422 18:36:14.484934 0. 0000000000114000-000000000011efff: RAMSTAGE
5423 18:36:14.491695 1. 0000000040000000-000000004023cfff: RAMSTAGE
5424 18:36:14.494952 2. 000000004023d000-00000000545fffff: RAM
5425 18:36:14.498594 3. 0000000054600000-000000005465ffff: BL31
5426 18:36:14.501541 4. 0000000054660000-00000000ffed9fff: RAM
5427 18:36:14.509161 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5428 18:36:14.511801 6. 0000000100000000-000000013fffffff: RAM
5429 18:36:14.514906 Passing 5 GPIOs to payload:
5430 18:36:14.518511 NAME | PORT | POLARITY | VALUE
5431 18:36:14.521816 write protect | 0x00000096 | low | high
5432 18:36:14.528526 EC in RW | 0x000000b1 | high | undefined
5433 18:36:14.532118 EC interrupt | 0x00000097 | low | undefined
5434 18:36:14.538579 TPM interrupt | 0x00000099 | high | undefined
5435 18:36:14.541267 speaker enable | 0x000000af | high | undefined
5436 18:36:14.545240 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5437 18:36:14.548700 in-header: 03 f7 00 00 02 00 00 00
5438 18:36:14.549213 in-data: 04 00
5439 18:36:14.551536 Board ID: 4
5440 18:36:14.555283 ADC[3]: Raw value=215149 ID=1
5441 18:36:14.555830 RAM code: 1
5442 18:36:14.556160 SKU ID: 16
5443 18:36:14.561996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5444 18:36:14.562527 CBFS @ 21000 size 3d4000
5445 18:36:14.568386 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5446 18:36:14.574752 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum d144
5447 18:36:14.575168 coreboot table: 940 bytes.
5448 18:36:14.581264 IMD ROOT 0. 00000000fffff000 00001000
5449 18:36:14.585031 IMD SMALL 1. 00000000ffffe000 00001000
5450 18:36:14.588752 CONSOLE 2. 00000000fffde000 00020000
5451 18:36:14.591170 FMAP 3. 00000000fffdd000 0000047c
5452 18:36:14.594536 TIME STAMP 4. 00000000fffdc000 00000910
5453 18:36:14.597937 RAMOOPS 5. 00000000ffedc000 00100000
5454 18:36:14.601323 COREBOOT 6. 00000000ffeda000 00002000
5455 18:36:14.604762 IMD small region:
5456 18:36:14.607778 IMD ROOT 0. 00000000ffffec00 00000400
5457 18:36:14.611294 VBOOT WORK 1. 00000000ffffeb00 00000100
5458 18:36:14.615200 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5459 18:36:14.618002 VPD 3. 00000000ffffea60 0000006c
5460 18:36:14.624606 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5461 18:36:14.631117 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5462 18:36:14.634227 in-header: 03 e1 00 00 08 00 00 00
5463 18:36:14.637820 in-data: 84 20 60 10 00 00 00 00
5464 18:36:14.640697 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5465 18:36:14.644409 CBFS @ 21000 size 3d4000
5466 18:36:14.647955 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5467 18:36:14.651171 CBFS: Locating 'fallback/payload'
5468 18:36:14.659878 CBFS: Found @ offset dc040 size 439a0
5469 18:36:14.747322 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5470 18:36:14.750899 Checking segment from ROM address 0x0000000040003a00
5471 18:36:14.757325 Checking segment from ROM address 0x0000000040003a1c
5472 18:36:14.760689 Loading segment from ROM address 0x0000000040003a00
5473 18:36:14.764447 code (compression=0)
5474 18:36:14.773982 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5475 18:36:14.780439 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5476 18:36:14.783955 it's not compressed!
5477 18:36:14.786797 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5478 18:36:14.794153 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5479 18:36:14.801442 Loading segment from ROM address 0x0000000040003a1c
5480 18:36:14.804889 Entry Point 0x0000000080000000
5481 18:36:14.805339 Loaded segments
5482 18:36:14.811626 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5483 18:36:14.814632 Jumping to boot code at 0000000080000000(00000000ffeda000)
5484 18:36:14.825047 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5485 18:36:14.828001 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5486 18:36:14.831481 CBFS @ 21000 size 3d4000
5487 18:36:14.838062 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5488 18:36:14.841672 CBFS: Locating 'fallback/bl31'
5489 18:36:14.845142 CBFS: Found @ offset 36dc0 size 5820
5490 18:36:14.855787 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5491 18:36:14.859195 Checking segment from ROM address 0x0000000040003a00
5492 18:36:14.865750 Checking segment from ROM address 0x0000000040003a1c
5493 18:36:14.869186 Loading segment from ROM address 0x0000000040003a00
5494 18:36:14.872092 code (compression=1)
5495 18:36:14.878507 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5496 18:36:14.889205 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5497 18:36:14.889724 using LZMA
5498 18:36:14.897420 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5499 18:36:14.904260 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5500 18:36:14.907986 Loading segment from ROM address 0x0000000040003a1c
5501 18:36:14.910646 Entry Point 0x0000000054601000
5502 18:36:14.911165 Loaded segments
5503 18:36:14.914341 NOTICE: MT8183 bl31_setup
5504 18:36:14.921399 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5505 18:36:14.924505 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5506 18:36:14.927727 INFO: [DEVAPC] dump DEVAPC registers:
5507 18:36:14.937805 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5508 18:36:14.944520 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5509 18:36:14.954674 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5510 18:36:14.960853 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5511 18:36:14.970923 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5512 18:36:14.978060 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5513 18:36:14.987462 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5514 18:36:14.994080 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5515 18:36:15.003610 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5516 18:36:15.011200 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5517 18:36:15.020179 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5518 18:36:15.027347 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5519 18:36:15.033910 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5520 18:36:15.043643 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5521 18:36:15.050311 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5522 18:36:15.056887 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5523 18:36:15.063832 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5524 18:36:15.073822 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5525 18:36:15.080293 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5526 18:36:15.086706 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5527 18:36:15.093491 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5528 18:36:15.099742 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5529 18:36:15.103307 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5530 18:36:15.107507 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5531 18:36:15.110652 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5532 18:36:15.113389 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5533 18:36:15.116733 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5534 18:36:15.123389 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5535 18:36:15.129901 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5536 18:36:15.130410 WARNING: region 0:
5537 18:36:15.133303 WARNING: apc:0x168, sa:0x0, ea:0xfff
5538 18:36:15.136807 WARNING: region 1:
5539 18:36:15.139922 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5540 18:36:15.140340 WARNING: region 2:
5541 18:36:15.146195 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5542 18:36:15.146695 WARNING: region 3:
5543 18:36:15.150163 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5544 18:36:15.153003 WARNING: region 4:
5545 18:36:15.156796 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5546 18:36:15.157313 WARNING: region 5:
5547 18:36:15.159863 WARNING: apc:0x0, sa:0x0, ea:0x0
5548 18:36:15.163497 WARNING: region 6:
5549 18:36:15.166455 WARNING: apc:0x0, sa:0x0, ea:0x0
5550 18:36:15.166977 WARNING: region 7:
5551 18:36:15.170108 WARNING: apc:0x0, sa:0x0, ea:0x0
5552 18:36:15.176247 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5553 18:36:15.179381 INFO: SPM: enable SPMC mode
5554 18:36:15.182688 NOTICE: spm_boot_init() start
5555 18:36:15.186634 NOTICE: spm_boot_init() end
5556 18:36:15.189666 INFO: BL31: Initializing runtime services
5557 18:36:15.195849 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5558 18:36:15.199242 INFO: BL31: Preparing for EL3 exit to normal world
5559 18:36:15.203337 INFO: Entry point address = 0x80000000
5560 18:36:15.205800 INFO: SPSR = 0x8
5561 18:36:15.227526
5562 18:36:15.228048
5563 18:36:15.228381
5564 18:36:15.229890 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5565 18:36:15.230388 start: 2.2.4 bootloader-commands (timeout 00:04:38) [common]
5566 18:36:15.230946 Setting prompt string to ['jacuzzi:']
5567 18:36:15.231385 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:38)
5568 18:36:15.232083 Starting depthcharge on Juniper...
5569 18:36:15.232428
5570 18:36:15.234283 vboot_handoff: creating legacy vboot_handoff structure
5571 18:36:15.234696
5572 18:36:15.237875 ec_init(0): CrosEC protocol v3 supported (544, 544)
5573 18:36:15.240751
5574 18:36:15.241165 Wipe memory regions:
5575 18:36:15.241490
5576 18:36:15.243946 [0x00000040000000, 0x00000054600000)
5577 18:36:15.286937
5578 18:36:15.287506 [0x00000054660000, 0x00000080000000)
5579 18:36:15.378996
5580 18:36:15.379561 [0x000000811994a0, 0x000000ffeda000)
5581 18:36:15.639030
5582 18:36:15.639762 [0x00000100000000, 0x00000140000000)
5583 18:36:15.771884
5584 18:36:15.775570 Initializing XHCI USB controller at 0x11200000.
5585 18:36:15.798103
5586 18:36:15.801468 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5587 18:36:15.801979
5588 18:36:15.802307
5589 18:36:15.803078 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5591 18:36:15.904323 jacuzzi: tftpboot 192.168.201.1 14291342/tftp-deploy-s8lw49u8/kernel/image.itb 14291342/tftp-deploy-s8lw49u8/kernel/cmdline
5592 18:36:15.904882 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5593 18:36:15.905210 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
5594 18:36:15.909863 tftpboot 192.168.201.1 14291342/tftp-deploy-s8lw49u8/kernel/image.itp-deploy-s8lw49u8/kernel/cmdline
5595 18:36:15.910251
5596 18:36:15.910547 Waiting for link
5597 18:36:16.311937
5598 18:36:16.312477 R8152: Initializing
5599 18:36:16.312813
5600 18:36:16.315098 Version 9 (ocp_data = 6010)
5601 18:36:16.315659
5602 18:36:16.318639 R8152: Done initializing
5603 18:36:16.319146
5604 18:36:16.319531 Adding net device
5605 18:36:16.703863
5606 18:36:16.704373 done.
5607 18:36:16.704701
5608 18:36:16.705055 MAC: 00:e0:4c:68:0b:b9
5609 18:36:16.705383
5610 18:36:16.707385 Sending DHCP discover... done.
5611 18:36:16.707838
5612 18:36:16.710319 Waiting for reply... done.
5613 18:36:16.710732
5614 18:36:16.715177 Sending DHCP request... done.
5615 18:36:16.715634
5616 18:36:16.729595 Waiting for reply... done.
5617 18:36:16.730111
5618 18:36:16.730438 My ip is 192.168.201.13
5619 18:36:16.730741
5620 18:36:16.732830 The DHCP server ip is 192.168.201.1
5621 18:36:16.733249
5622 18:36:16.739786 TFTP server IP predefined by user: 192.168.201.1
5623 18:36:16.740301
5624 18:36:16.746281 Bootfile predefined by user: 14291342/tftp-deploy-s8lw49u8/kernel/image.itb
5625 18:36:16.746794
5626 18:36:16.747222 Sending tftp read request... done.
5627 18:36:16.749338
5628 18:36:16.754972 Waiting for the transfer...
5629 18:36:16.755441
5630 18:36:17.139864 00000000 ################################################################
5631 18:36:17.140311
5632 18:36:17.524485 00080000 ################################################################
5633 18:36:17.524956
5634 18:36:17.814550 00100000 ################################################################
5635 18:36:17.814709
5636 18:36:18.093442 00180000 ################################################################
5637 18:36:18.093627
5638 18:36:18.363818 00200000 ################################################################
5639 18:36:18.363968
5640 18:36:18.669840 00280000 ################################################################
5641 18:36:18.670308
5642 18:36:18.999825 00300000 ################################################################
5643 18:36:18.999986
5644 18:36:19.258646 00380000 ################################################################
5645 18:36:19.258807
5646 18:36:19.513059 00400000 ################################################################
5647 18:36:19.513235
5648 18:36:19.767700 00480000 ################################################################
5649 18:36:19.767889
5650 18:36:20.022320 00500000 ################################################################
5651 18:36:20.022468
5652 18:36:20.278502 00580000 ################################################################
5653 18:36:20.278656
5654 18:36:20.531796 00600000 ################################################################
5655 18:36:20.531949
5656 18:36:20.785515 00680000 ################################################################
5657 18:36:20.785697
5658 18:36:21.037632 00700000 ################################################################
5659 18:36:21.037779
5660 18:36:21.289097 00780000 ################################################################
5661 18:36:21.289256
5662 18:36:21.542381 00800000 ################################################################
5663 18:36:21.542544
5664 18:36:21.794173 00880000 ################################################################
5665 18:36:21.794353
5666 18:36:22.046470 00900000 ################################################################
5667 18:36:22.046625
5668 18:36:22.301169 00980000 ################################################################
5669 18:36:22.301322
5670 18:36:22.554922 00a00000 ################################################################
5671 18:36:22.555077
5672 18:36:22.809327 00a80000 ################################################################
5673 18:36:22.809479
5674 18:36:23.063814 00b00000 ################################################################
5675 18:36:23.063965
5676 18:36:23.320654 00b80000 ################################################################
5677 18:36:23.320808
5678 18:36:23.601548 00c00000 ################################################################
5679 18:36:23.601732
5680 18:36:23.869387 00c80000 ################################################################
5681 18:36:23.869545
5682 18:36:24.122965 00d00000 ################################################################
5683 18:36:24.123141
5684 18:36:24.375780 00d80000 ################################################################
5685 18:36:24.375927
5686 18:36:24.649381 00e00000 ################################################################
5687 18:36:24.649542
5688 18:36:24.894463 00e80000 ################################################################
5689 18:36:24.894626
5690 18:36:25.134528 00f00000 ################################################################
5691 18:36:25.134716
5692 18:36:25.385467 00f80000 ################################################################
5693 18:36:25.385647
5694 18:36:25.648843 01000000 ################################################################
5695 18:36:25.648994
5696 18:36:25.902333 01080000 ################################################################
5697 18:36:25.902512
5698 18:36:26.219987 01100000 ################################################################
5699 18:36:26.220492
5700 18:36:26.638135 01180000 ################################################################
5701 18:36:26.638644
5702 18:36:27.072580 01200000 ################################################################
5703 18:36:27.073149
5704 18:36:27.419380 01280000 ################################################################
5705 18:36:27.419552
5706 18:36:27.694896 01300000 ################################################################
5707 18:36:27.695084
5708 18:36:27.993789 01380000 ################################################################
5709 18:36:27.993938
5710 18:36:28.295684 01400000 ################################################################
5711 18:36:28.295835
5712 18:36:28.582536 01480000 ################################################################
5713 18:36:28.582718
5714 18:36:28.868150 01500000 ################################################################
5715 18:36:28.868304
5716 18:36:29.212588 01580000 ################################################################
5717 18:36:29.213108
5718 18:36:29.606028 01600000 ################################################################
5719 18:36:29.606172
5720 18:36:29.916852 01680000 ################################################################
5721 18:36:29.917034
5722 18:36:30.175911 01700000 ################################################################
5723 18:36:30.176097
5724 18:36:30.431411 01780000 ################################################################
5725 18:36:30.431567
5726 18:36:30.697785 01800000 ################################################################
5727 18:36:30.697927
5728 18:36:30.946836 01880000 ################################################################
5729 18:36:30.946992
5730 18:36:31.202341 01900000 ################################################################
5731 18:36:31.202479
5732 18:36:31.458632 01980000 ################################################################
5733 18:36:31.458794
5734 18:36:31.713329 01a00000 ################################################################
5735 18:36:31.713525
5736 18:36:31.987597 01a80000 ################################################################
5737 18:36:31.987762
5738 18:36:32.260051 01b00000 ################################################################
5739 18:36:32.260195
5740 18:36:32.547429 01b80000 ################################################################
5741 18:36:32.547579
5742 18:36:32.797837 01c00000 ################################################################
5743 18:36:32.797994
5744 18:36:33.070142 01c80000 ################################################################
5745 18:36:33.070289
5746 18:36:33.323265 01d00000 ################################################################
5747 18:36:33.323452
5748 18:36:33.577347 01d80000 ################################################################
5749 18:36:33.577498
5750 18:36:33.800278 01e00000 ######################################################### done.
5751 18:36:33.800432
5752 18:36:33.803617 The bootfile was 31918990 bytes long.
5753 18:36:33.803706
5754 18:36:33.807249 Sending tftp read request... done.
5755 18:36:33.807347
5756 18:36:33.810629 Waiting for the transfer...
5757 18:36:33.810724
5758 18:36:33.810821 00000000 # done.
5759 18:36:33.810891
5760 18:36:33.820152 Command line loaded dynamically from TFTP file: 14291342/tftp-deploy-s8lw49u8/kernel/cmdline
5761 18:36:33.820247
5762 18:36:33.846773 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5763 18:36:33.846909
5764 18:36:33.847018 Loading FIT.
5765 18:36:33.847120
5766 18:36:33.850330 Image ramdisk-1 has 18734143 bytes.
5767 18:36:33.850422
5768 18:36:33.852917 Image fdt-1 has 57695 bytes.
5769 18:36:33.853011
5770 18:36:33.856765 Image kernel-1 has 13125101 bytes.
5771 18:36:33.856855
5772 18:36:33.862794 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5773 18:36:33.862883
5774 18:36:33.876500 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5775 18:36:33.876605
5776 18:36:33.883422 Choosing best match conf-1 for compat google,juniper-sku16.
5777 18:36:33.883532
5778 18:36:33.886150 Connected to device vid:did:rid of 1ae0:0028:00
5779 18:36:33.940683
5780 18:36:33.944175 tpm_get_response: command 0x17b, return code 0x0
5781 18:36:33.944590
5782 18:36:33.947553 tpm_cleanup: add release locality here.
5783 18:36:33.948012
5784 18:36:33.950272 Shutting down all USB controllers.
5785 18:36:33.950727
5786 18:36:33.953816 Removing current net device
5787 18:36:33.954255
5788 18:36:33.957339 Exiting depthcharge with code 4 at timestamp: 35909582
5789 18:36:33.957824
5790 18:36:33.960696 LZMA decompressing kernel-1 to 0x80193568
5791 18:36:33.961110
5792 18:36:33.966929 LZMA decompressing kernel-1 to 0x40000000
5793 18:36:35.831151
5794 18:36:35.831313 jumping to kernel
5795 18:36:35.831801 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5796 18:36:35.831908 start: 2.2.5 auto-login-action (timeout 00:04:18) [common]
5797 18:36:35.831993 Setting prompt string to ['Linux version [0-9]']
5798 18:36:35.832068 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5799 18:36:35.832142 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5800 18:36:35.906741
5801 18:36:35.910027 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5802 18:36:35.913645 start: 2.2.5.1 login-action (timeout 00:04:18) [common]
5803 18:36:35.914156 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5804 18:36:35.914523 Setting prompt string to []
5805 18:36:35.914899 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5806 18:36:35.915245 Using line separator: #'\n'#
5807 18:36:35.915578 No login prompt set.
5808 18:36:35.915889 Parsing kernel messages
5809 18:36:35.916168 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5810 18:36:35.916682 [login-action] Waiting for messages, (timeout 00:04:18)
5811 18:36:35.917014 Waiting using forced prompt support (timeout 00:02:09)
5812 18:36:35.933359 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
5813 18:36:35.936633 [ 0.000000] random: crng init done
5814 18:36:35.943246 [ 0.000000] Machine model: Google juniper sku16 board
5815 18:36:35.943712 [ 0.000000] efi: UEFI not found.
5816 18:36:35.953495 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5817 18:36:35.959785 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5818 18:36:35.970251 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5819 18:36:35.973636 [ 0.000000] printk: bootconsole [mtk8250] enabled
5820 18:36:35.981254 [ 0.000000] NUMA: No NUMA configuration found
5821 18:36:35.987842 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5822 18:36:35.994416 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5823 18:36:35.994662 [ 0.000000] Zone ranges:
5824 18:36:36.000920 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5825 18:36:36.004375 [ 0.000000] DMA32 empty
5826 18:36:36.011044 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5827 18:36:36.014563 [ 0.000000] Movable zone start for each node
5828 18:36:36.017774 [ 0.000000] Early memory node ranges
5829 18:36:36.024449 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5830 18:36:36.030925 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5831 18:36:36.037868 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5832 18:36:36.044055 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5833 18:36:36.051075 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5834 18:36:36.057394 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5835 18:36:36.073617 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5836 18:36:36.080420 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5837 18:36:36.087268 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5838 18:36:36.090769 [ 0.000000] psci: probing for conduit method from DT.
5839 18:36:36.097310 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5840 18:36:36.100616 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5841 18:36:36.107341 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5842 18:36:36.110202 [ 0.000000] psci: SMC Calling Convention v1.1
5843 18:36:36.116867 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5844 18:36:36.120408 [ 0.000000] Detected VIPT I-cache on CPU0
5845 18:36:36.126928 [ 0.000000] CPU features: detected: GIC system register CPU interface
5846 18:36:36.133778 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5847 18:36:36.140447 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5848 18:36:36.147128 [ 0.000000] CPU features: detected: ARM erratum 845719
5849 18:36:36.150719 [ 0.000000] alternatives: applying boot alternatives
5850 18:36:36.153771 [ 0.000000] Fallback order for Node 0: 0
5851 18:36:36.160845 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5852 18:36:36.163511 [ 0.000000] Policy zone: Normal
5853 18:36:36.190262 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5854 18:36:36.203319 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5855 18:36:36.213245 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5856 18:36:36.220046 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5857 18:36:36.226393 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5858 18:36:36.229778 <6>[ 0.000000] software IO TLB: area num 8.
5859 18:36:36.257736 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5860 18:36:36.315660 <6>[ 0.000000] Memory: 3896776K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261688K reserved, 32768K cma-reserved)
5861 18:36:36.322060 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5862 18:36:36.328841 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5863 18:36:36.331940 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5864 18:36:36.338828 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5865 18:36:36.345387 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5866 18:36:36.348352 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5867 18:36:36.358466 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5868 18:36:36.365601 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5869 18:36:36.368559 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5870 18:36:36.380348 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5871 18:36:36.386931 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5872 18:36:36.390659 <6>[ 0.000000] GICv3: 640 SPIs implemented
5873 18:36:36.393998 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5874 18:36:36.400139 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5875 18:36:36.403525 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5876 18:36:36.410350 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5877 18:36:36.423343 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5878 18:36:36.433749 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5879 18:36:36.439952 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5880 18:36:36.452252 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5881 18:36:36.465474 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5882 18:36:36.471994 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5883 18:36:36.479146 <6>[ 0.009470] Console: colour dummy device 80x25
5884 18:36:36.481945 <6>[ 0.014515] printk: console [tty1] enabled
5885 18:36:36.492052 <6>[ 0.018900] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5886 18:36:36.498858 <6>[ 0.029364] pid_max: default: 32768 minimum: 301
5887 18:36:36.502467 <6>[ 0.034245] LSM: Security Framework initializing
5888 18:36:36.512345 <6>[ 0.039159] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5889 18:36:36.519145 <6>[ 0.046782] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5890 18:36:36.525512 <4>[ 0.055655] cacheinfo: Unable to detect cache hierarchy for CPU 0
5891 18:36:36.535572 <6>[ 0.062285] cblist_init_generic: Setting adjustable number of callback queues.
5892 18:36:36.541990 <6>[ 0.069730] cblist_init_generic: Setting shift to 3 and lim to 1.
5893 18:36:36.548795 <6>[ 0.076082] cblist_init_generic: Setting adjustable number of callback queues.
5894 18:36:36.555201 <6>[ 0.083527] cblist_init_generic: Setting shift to 3 and lim to 1.
5895 18:36:36.558533 <6>[ 0.089925] rcu: Hierarchical SRCU implementation.
5896 18:36:36.565396 <6>[ 0.094951] rcu: Max phase no-delay instances is 1000.
5897 18:36:36.572868 <6>[ 0.102869] EFI services will not be available.
5898 18:36:36.575759 <6>[ 0.107819] smp: Bringing up secondary CPUs ...
5899 18:36:36.586299 <6>[ 0.113110] Detected VIPT I-cache on CPU1
5900 18:36:36.593169 <4>[ 0.113158] cacheinfo: Unable to detect cache hierarchy for CPU 1
5901 18:36:36.599357 <6>[ 0.113167] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5902 18:36:36.605979 <6>[ 0.113199] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5903 18:36:36.609049 <6>[ 0.113679] Detected VIPT I-cache on CPU2
5904 18:36:36.615886 <4>[ 0.113710] cacheinfo: Unable to detect cache hierarchy for CPU 2
5905 18:36:36.622302 <6>[ 0.113715] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5906 18:36:36.629176 <6>[ 0.113727] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5907 18:36:36.635544 <6>[ 0.114175] Detected VIPT I-cache on CPU3
5908 18:36:36.639040 <4>[ 0.114205] cacheinfo: Unable to detect cache hierarchy for CPU 3
5909 18:36:36.648891 <6>[ 0.114210] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5910 18:36:36.655849 <6>[ 0.114221] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5911 18:36:36.659226 <6>[ 0.114796] CPU features: detected: Spectre-v2
5912 18:36:36.662645 <6>[ 0.114805] CPU features: detected: Spectre-BHB
5913 18:36:36.668901 <6>[ 0.114809] CPU features: detected: ARM erratum 858921
5914 18:36:36.672450 <6>[ 0.114815] Detected VIPT I-cache on CPU4
5915 18:36:36.678765 <4>[ 0.114863] cacheinfo: Unable to detect cache hierarchy for CPU 4
5916 18:36:36.685671 <6>[ 0.114870] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5917 18:36:36.692101 <6>[ 0.114878] arch_timer: Enabling local workaround for ARM erratum 858921
5918 18:36:36.698586 <6>[ 0.114889] arch_timer: CPU4: Trapping CNTVCT access
5919 18:36:36.705349 <6>[ 0.114897] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5920 18:36:36.708538 <6>[ 0.115382] Detected VIPT I-cache on CPU5
5921 18:36:36.715251 <4>[ 0.115423] cacheinfo: Unable to detect cache hierarchy for CPU 5
5922 18:36:36.722086 <6>[ 0.115428] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5923 18:36:36.732070 <6>[ 0.115435] arch_timer: Enabling local workaround for ARM erratum 858921
5924 18:36:36.735687 <6>[ 0.115441] arch_timer: CPU5: Trapping CNTVCT access
5925 18:36:36.741812 <6>[ 0.115446] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5926 18:36:36.745244 <6>[ 0.115882] Detected VIPT I-cache on CPU6
5927 18:36:36.751905 <4>[ 0.115927] cacheinfo: Unable to detect cache hierarchy for CPU 6
5928 18:36:36.758585 <6>[ 0.115934] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5929 18:36:36.768613 <6>[ 0.115941] arch_timer: Enabling local workaround for ARM erratum 858921
5930 18:36:36.772015 <6>[ 0.115947] arch_timer: CPU6: Trapping CNTVCT access
5931 18:36:36.778607 <6>[ 0.115952] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5932 18:36:36.781817 <6>[ 0.116482] Detected VIPT I-cache on CPU7
5933 18:36:36.788518 <4>[ 0.116526] cacheinfo: Unable to detect cache hierarchy for CPU 7
5934 18:36:36.798527 <6>[ 0.116532] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5935 18:36:36.805234 <6>[ 0.116539] arch_timer: Enabling local workaround for ARM erratum 858921
5936 18:36:36.808372 <6>[ 0.116546] arch_timer: CPU7: Trapping CNTVCT access
5937 18:36:36.814998 <6>[ 0.116551] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5938 18:36:36.818306 <6>[ 0.116604] smp: Brought up 1 node, 8 CPUs
5939 18:36:36.825220 <6>[ 0.355471] SMP: Total of 8 processors activated.
5940 18:36:36.831877 <6>[ 0.360407] CPU features: detected: 32-bit EL0 Support
5941 18:36:36.835069 <6>[ 0.365778] CPU features: detected: 32-bit EL1 Support
5942 18:36:36.841589 <6>[ 0.371144] CPU features: detected: CRC32 instructions
5943 18:36:36.844964 <6>[ 0.376572] CPU: All CPU(s) started at EL2
5944 18:36:36.851367 <6>[ 0.380910] alternatives: applying system-wide alternatives
5945 18:36:36.858072 <6>[ 0.388874] devtmpfs: initialized
5946 18:36:36.873766 <6>[ 0.397826] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5947 18:36:36.880514 <6>[ 0.407775] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5948 18:36:36.884354 <6>[ 0.415503] pinctrl core: initialized pinctrl subsystem
5949 18:36:36.892448 <6>[ 0.422613] DMI not present or invalid.
5950 18:36:36.898785 <6>[ 0.426984] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5951 18:36:36.905859 <6>[ 0.433893] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5952 18:36:36.915257 <6>[ 0.441420] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5953 18:36:36.921951 <6>[ 0.449671] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5954 18:36:36.928546 <6>[ 0.457848] audit: initializing netlink subsys (disabled)
5955 18:36:36.935378 <5>[ 0.463552] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5956 18:36:36.941872 <6>[ 0.464533] thermal_sys: Registered thermal governor 'step_wise'
5957 18:36:36.948345 <6>[ 0.471517] thermal_sys: Registered thermal governor 'power_allocator'
5958 18:36:36.951766 <6>[ 0.477815] cpuidle: using governor menu
5959 18:36:36.958309 <6>[ 0.488778] NET: Registered PF_QIPCRTR protocol family
5960 18:36:36.965300 <6>[ 0.494276] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5961 18:36:36.971519 <6>[ 0.501375] ASID allocator initialised with 32768 entries
5962 18:36:36.978669 <6>[ 0.508139] Serial: AMBA PL011 UART driver
5963 18:36:36.988006 <4>[ 0.518526] Trying to register duplicate clock ID: 113
5964 18:36:37.047605 <6>[ 0.574810] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5965 18:36:37.061928 <6>[ 0.589143] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5966 18:36:37.065156 <6>[ 0.598901] KASLR enabled
5967 18:36:37.080073 <6>[ 0.606902] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5968 18:36:37.086423 <6>[ 0.613904] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5969 18:36:37.093163 <6>[ 0.620380] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5970 18:36:37.099596 <6>[ 0.627371] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5971 18:36:37.106195 <6>[ 0.633845] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5972 18:36:37.113544 <6>[ 0.640835] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5973 18:36:37.119916 <6>[ 0.647309] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5974 18:36:37.126329 <6>[ 0.654299] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5975 18:36:37.129300 <6>[ 0.661863] ACPI: Interpreter disabled.
5976 18:36:37.139488 <6>[ 0.669851] iommu: Default domain type: Translated
5977 18:36:37.145696 <6>[ 0.674958] iommu: DMA domain TLB invalidation policy: strict mode
5978 18:36:37.149230 <5>[ 0.681588] SCSI subsystem initialized
5979 18:36:37.156057 <6>[ 0.686001] usbcore: registered new interface driver usbfs
5980 18:36:37.162285 <6>[ 0.691730] usbcore: registered new interface driver hub
5981 18:36:37.165817 <6>[ 0.697271] usbcore: registered new device driver usb
5982 18:36:37.173131 <6>[ 0.703580] pps_core: LinuxPPS API ver. 1 registered
5983 18:36:37.183243 <6>[ 0.708764] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5984 18:36:37.186253 <6>[ 0.718088] PTP clock support registered
5985 18:36:37.189335 <6>[ 0.722340] EDAC MC: Ver: 3.0.0
5986 18:36:37.197839 <6>[ 0.727977] FPGA manager framework
5987 18:36:37.204026 <6>[ 0.731659] Advanced Linux Sound Architecture Driver Initialized.
5988 18:36:37.207519 <6>[ 0.738410] vgaarb: loaded
5989 18:36:37.214426 <6>[ 0.741538] clocksource: Switched to clocksource arch_sys_counter
5990 18:36:37.217998 <5>[ 0.747968] VFS: Disk quotas dquot_6.6.0
5991 18:36:37.223699 <6>[ 0.752143] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5992 18:36:37.227062 <6>[ 0.759317] pnp: PnP ACPI: disabled
5993 18:36:37.236135 <6>[ 0.766230] NET: Registered PF_INET protocol family
5994 18:36:37.242686 <6>[ 0.771462] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5995 18:36:37.254128 <6>[ 0.781352] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5996 18:36:37.264189 <6>[ 0.790105] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5997 18:36:37.270664 <6>[ 0.798054] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5998 18:36:37.277415 <6>[ 0.806286] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5999 18:36:37.283794 <6>[ 0.814381] TCP: Hash tables configured (established 32768 bind 32768)
6000 18:36:37.294295 <6>[ 0.821211] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6001 18:36:37.300993 <6>[ 0.828185] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6002 18:36:37.307060 <6>[ 0.835663] NET: Registered PF_UNIX/PF_LOCAL protocol family
6003 18:36:37.313951 <6>[ 0.841750] RPC: Registered named UNIX socket transport module.
6004 18:36:37.317348 <6>[ 0.847895] RPC: Registered udp transport module.
6005 18:36:37.324103 <6>[ 0.852819] RPC: Registered tcp transport module.
6006 18:36:37.330432 <6>[ 0.857743] RPC: Registered tcp NFSv4.1 backchannel transport module.
6007 18:36:37.334072 <6>[ 0.864394] PCI: CLS 0 bytes, default 64
6008 18:36:37.336987 <6>[ 0.868680] Unpacking initramfs...
6009 18:36:37.358687 <6>[ 0.885669] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6010 18:36:37.368469 <6>[ 0.894289] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6011 18:36:37.371596 <6>[ 0.903134] kvm [1]: IPA Size Limit: 40 bits
6012 18:36:37.379063 <6>[ 0.909466] kvm [1]: vgic-v2@c420000
6013 18:36:37.381931 <6>[ 0.913281] kvm [1]: GIC system register CPU interface enabled
6014 18:36:37.388914 <6>[ 0.919447] kvm [1]: vgic interrupt IRQ18
6015 18:36:37.391806 <6>[ 0.923796] kvm [1]: Hyp mode initialized successfully
6016 18:36:37.399488 <5>[ 0.930073] Initialise system trusted keyrings
6017 18:36:37.406301 <6>[ 0.934925] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6018 18:36:37.414172 <6>[ 0.944905] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6019 18:36:37.420853 <5>[ 0.951338] NFS: Registering the id_resolver key type
6020 18:36:37.424413 <5>[ 0.956644] Key type id_resolver registered
6021 18:36:37.431037 <5>[ 0.961059] Key type id_legacy registered
6022 18:36:37.437773 <6>[ 0.965376] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6023 18:36:37.444427 <6>[ 0.972297] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6024 18:36:37.450834 <6>[ 0.980054] 9p: Installing v9fs 9p2000 file system support
6025 18:36:37.478806 <5>[ 1.008724] Key type asymmetric registered
6026 18:36:37.481543 <5>[ 1.013069] Asymmetric key parser 'x509' registered
6027 18:36:37.491315 <6>[ 1.018224] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6028 18:36:37.494835 <6>[ 1.025847] io scheduler mq-deadline registered
6029 18:36:37.498363 <6>[ 1.030604] io scheduler kyber registered
6030 18:36:37.520650 <6>[ 1.051479] EINJ: ACPI disabled.
6031 18:36:37.527329 <4>[ 1.055249] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6032 18:36:37.565490 <6>[ 1.096029] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6033 18:36:37.573745 <6>[ 1.104510] printk: console [ttyS0] disabled
6034 18:36:37.602629 <6>[ 1.129165] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6035 18:36:37.608340 <6>[ 1.138639] printk: console [ttyS0] enabled
6036 18:36:37.611890 <6>[ 1.138639] printk: console [ttyS0] enabled
6037 18:36:37.618978 <6>[ 1.147558] printk: bootconsole [mtk8250] disabled
6038 18:36:37.621722 <6>[ 1.147558] printk: bootconsole [mtk8250] disabled
6039 18:36:37.632178 <3>[ 1.158089] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6040 18:36:37.638346 <3>[ 1.166473] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6041 18:36:37.667751 <6>[ 1.194891] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6042 18:36:37.674354 <6>[ 1.204548] serial serial0: tty port ttyS1 registered
6043 18:36:37.681012 <6>[ 1.211102] SuperH (H)SCI(F) driver initialized
6044 18:36:37.684368 <6>[ 1.216617] msm_serial: driver initialized
6045 18:36:37.699789 <6>[ 1.226938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6046 18:36:37.709707 <6>[ 1.235533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6047 18:36:37.716637 <6>[ 1.244107] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6048 18:36:37.726600 <6>[ 1.252678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6049 18:36:37.732658 <6>[ 1.261335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6050 18:36:37.743088 <6>[ 1.269995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6051 18:36:37.752825 <6>[ 1.278731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6052 18:36:37.759474 <6>[ 1.287468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6053 18:36:37.769481 <6>[ 1.296032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6054 18:36:37.778967 <6>[ 1.304834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6055 18:36:37.787117 <4>[ 1.317199] cacheinfo: Unable to detect cache hierarchy for CPU 0
6056 18:36:37.795902 <6>[ 1.326579] loop: module loaded
6057 18:36:37.808122 <6>[ 1.338475] vsim1: Bringing 1800000uV into 2700000-2700000uV
6058 18:36:37.825947 <6>[ 1.356665] megasas: 07.719.03.00-rc1
6059 18:36:37.835381 <6>[ 1.365508] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6060 18:36:37.846755 <6>[ 1.376920] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6061 18:36:37.863114 <6>[ 1.393744] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6062 18:36:37.920510 <6>[ 1.444100] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6063 18:36:37.947219 <6>[ 1.477586] Freeing initrd memory: 18292K
6064 18:36:37.962425 <4>[ 1.489394] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6065 18:36:37.969430 <4>[ 1.498624] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6066 18:36:37.976002 <4>[ 1.505322] Hardware name: Google juniper sku16 board (DT)
6067 18:36:37.978705 <4>[ 1.511062] Call trace:
6068 18:36:37.982337 <4>[ 1.513762] dump_backtrace.part.0+0xe0/0xf0
6069 18:36:37.985910 <4>[ 1.518299] show_stack+0x18/0x30
6070 18:36:37.988792 <4>[ 1.521871] dump_stack_lvl+0x68/0x84
6071 18:36:37.992508 <4>[ 1.525792] dump_stack+0x18/0x34
6072 18:36:37.998881 <4>[ 1.529362] sysfs_warn_dup+0x64/0x80
6073 18:36:38.002318 <4>[ 1.533283] sysfs_do_create_link_sd+0xf0/0x100
6074 18:36:38.005361 <4>[ 1.538071] sysfs_create_link+0x20/0x40
6075 18:36:38.012469 <4>[ 1.542250] bus_add_device+0x68/0x10c
6076 18:36:38.015641 <4>[ 1.546256] device_add+0x340/0x7ac
6077 18:36:38.018779 <4>[ 1.549999] of_device_add+0x44/0x60
6078 18:36:38.022153 <4>[ 1.553833] of_platform_device_create_pdata+0x90/0x120
6079 18:36:38.029255 <4>[ 1.559314] of_platform_bus_create+0x170/0x370
6080 18:36:38.032734 <4>[ 1.564101] of_platform_populate+0x50/0xfc
6081 18:36:38.039061 <4>[ 1.568540] parse_mtd_partitions+0x1dc/0x510
6082 18:36:38.042151 <4>[ 1.573154] mtd_device_parse_register+0xf8/0x2e0
6083 18:36:38.045230 <4>[ 1.578112] spi_nor_probe+0x21c/0x2f0
6084 18:36:38.052183 <4>[ 1.582118] spi_mem_probe+0x6c/0xb0
6085 18:36:38.055205 <4>[ 1.585951] spi_probe+0x84/0xe4
6086 18:36:38.058558 <4>[ 1.589433] really_probe+0xbc/0x2e0
6087 18:36:38.062118 <4>[ 1.593263] __driver_probe_device+0x78/0x11c
6088 18:36:38.065506 <4>[ 1.597875] driver_probe_device+0xd8/0x160
6089 18:36:38.072473 <4>[ 1.602313] __device_attach_driver+0xb8/0x134
6090 18:36:38.075332 <4>[ 1.607012] bus_for_each_drv+0x78/0xd0
6091 18:36:38.078476 <4>[ 1.611103] __device_attach+0xa8/0x1c0
6092 18:36:38.085227 <4>[ 1.615193] device_initial_probe+0x14/0x20
6093 18:36:38.088628 <4>[ 1.619631] bus_probe_device+0x9c/0xa4
6094 18:36:38.092043 <4>[ 1.623721] device_add+0x3ac/0x7ac
6095 18:36:38.095185 <4>[ 1.627464] __spi_add_device+0x78/0x120
6096 18:36:38.098562 <4>[ 1.631642] spi_add_device+0x40/0x7c
6097 18:36:38.105178 <4>[ 1.635559] spi_register_controller+0x610/0xad0
6098 18:36:38.108554 <4>[ 1.640432] devm_spi_register_controller+0x4c/0xa4
6099 18:36:38.115332 <4>[ 1.645565] mtk_spi_probe+0x3f8/0x650
6100 18:36:38.118626 <4>[ 1.649569] platform_probe+0x68/0xe0
6101 18:36:38.121552 <4>[ 1.653487] really_probe+0xbc/0x2e0
6102 18:36:38.125045 <4>[ 1.657318] __driver_probe_device+0x78/0x11c
6103 18:36:38.132091 <4>[ 1.661929] driver_probe_device+0xd8/0x160
6104 18:36:38.135513 <4>[ 1.666367] __driver_attach+0x94/0x19c
6105 18:36:38.138946 <4>[ 1.670458] bus_for_each_dev+0x70/0xd0
6106 18:36:38.141901 <4>[ 1.674547] driver_attach+0x24/0x30
6107 18:36:38.148843 <4>[ 1.678377] bus_add_driver+0x154/0x20c
6108 18:36:38.152133 <4>[ 1.682467] driver_register+0x78/0x130
6109 18:36:38.155014 <4>[ 1.686559] __platform_driver_register+0x28/0x34
6110 18:36:38.162024 <4>[ 1.691518] mtk_spi_driver_init+0x1c/0x28
6111 18:36:38.164973 <4>[ 1.695872] do_one_initcall+0x50/0x1d0
6112 18:36:38.168340 <4>[ 1.699962] kernel_init_freeable+0x21c/0x288
6113 18:36:38.171569 <4>[ 1.704575] kernel_init+0x24/0x12c
6114 18:36:38.175589 <4>[ 1.708320] ret_from_fork+0x10/0x20
6115 18:36:38.187166 <6>[ 1.717209] tun: Universal TUN/TAP device driver, 1.6
6116 18:36:38.190372 <6>[ 1.723503] thunder_xcv, ver 1.0
6117 18:36:38.193274 <6>[ 1.727019] thunder_bgx, ver 1.0
6118 18:36:38.196661 <6>[ 1.730521] nicpf, ver 1.0
6119 18:36:38.207898 <6>[ 1.734886] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6120 18:36:38.211355 <6>[ 1.742371] hns3: Copyright (c) 2017 Huawei Corporation.
6121 18:36:38.217552 <6>[ 1.747966] hclge is initializing
6122 18:36:38.221478 <6>[ 1.751551] e1000: Intel(R) PRO/1000 Network Driver
6123 18:36:38.227746 <6>[ 1.756686] e1000: Copyright (c) 1999-2006 Intel Corporation.
6124 18:36:38.231210 <6>[ 1.762707] e1000e: Intel(R) PRO/1000 Network Driver
6125 18:36:38.237914 <6>[ 1.767927] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6126 18:36:38.244596 <6>[ 1.774122] igb: Intel(R) Gigabit Ethernet Network Driver
6127 18:36:38.251081 <6>[ 1.779777] igb: Copyright (c) 2007-2014 Intel Corporation.
6128 18:36:38.257900 <6>[ 1.785619] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6129 18:36:38.264039 <6>[ 1.792142] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6130 18:36:38.267718 <6>[ 1.798694] sky2: driver version 1.30
6131 18:36:38.274428 <6>[ 1.803940] usbcore: registered new device driver r8152-cfgselector
6132 18:36:38.281135 <6>[ 1.810481] usbcore: registered new interface driver r8152
6133 18:36:38.287542 <6>[ 1.816319] VFIO - User Level meta-driver version: 0.3
6134 18:36:38.294583 <6>[ 1.824140] mtu3 11201000.usb: uwk - reg:0x420, version:101
6135 18:36:38.300881 <4>[ 1.830016] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6136 18:36:38.307519 <6>[ 1.837299] mtu3 11201000.usb: dr_mode: 1, drd: auto
6137 18:36:38.314683 <6>[ 1.842525] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6138 18:36:38.317351 <6>[ 1.848713] mtu3 11201000.usb: usb3-drd: 0
6139 18:36:38.324052 <6>[ 1.854297] mtu3 11201000.usb: xHCI platform device register success...
6140 18:36:38.336147 <4>[ 1.862989] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6141 18:36:38.339322 <6>[ 1.870931] xhci-mtk 11200000.usb: xHCI Host Controller
6142 18:36:38.349798 <6>[ 1.876439] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6143 18:36:38.356028 <6>[ 1.884158] xhci-mtk 11200000.usb: USB3 root hub has no ports
6144 18:36:38.362987 <6>[ 1.890167] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6145 18:36:38.369561 <6>[ 1.899612] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6146 18:36:38.376029 <6>[ 1.905686] xhci-mtk 11200000.usb: xHCI Host Controller
6147 18:36:38.382799 <6>[ 1.911174] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6148 18:36:38.389018 <6>[ 1.918835] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6149 18:36:38.392622 <6>[ 1.925663] hub 1-0:1.0: USB hub found
6150 18:36:38.399291 <6>[ 1.929692] hub 1-0:1.0: 1 port detected
6151 18:36:38.409219 <6>[ 1.935057] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6152 18:36:38.412342 <6>[ 1.943689] hub 2-0:1.0: USB hub found
6153 18:36:38.419205 <3>[ 1.947737] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6154 18:36:38.425656 <6>[ 1.955631] usbcore: registered new interface driver usb-storage
6155 18:36:38.432215 <6>[ 1.962256] usbcore: registered new device driver onboard-usb-hub
6156 18:36:38.446657 <4>[ 1.973653] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6157 18:36:38.455709 <6>[ 1.985897] mt6397-rtc mt6358-rtc: registered as rtc0
6158 18:36:38.465680 <6>[ 1.991380] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-11T18:35:40 UTC (1718130940)
6159 18:36:38.468633 <6>[ 2.001266] i2c_dev: i2c /dev entries driver
6160 18:36:38.480400 <6>[ 2.007664] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6161 18:36:38.490740 <6>[ 2.015982] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6162 18:36:38.493829 <6>[ 2.024891] i2c 4-0058: Fixed dependency cycle(s) with /panel
6163 18:36:38.503897 <6>[ 2.030921] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6164 18:36:38.510547 <3>[ 2.038383] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6165 18:36:38.528191 <6>[ 2.058312] cpu cpu0: EM: created perf domain
6166 18:36:38.537938 <6>[ 2.063820] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6167 18:36:38.544814 <6>[ 2.075131] cpu cpu4: EM: created perf domain
6168 18:36:38.551301 <6>[ 2.081860] sdhci: Secure Digital Host Controller Interface driver
6169 18:36:38.558027 <6>[ 2.088312] sdhci: Copyright(c) Pierre Ossman
6170 18:36:38.564589 <6>[ 2.093720] Synopsys Designware Multimedia Card Interface Driver
6171 18:36:38.571635 <6>[ 2.094214] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6172 18:36:38.574635 <6>[ 2.100808] sdhci-pltfm: SDHCI platform and OF driver helper
6173 18:36:38.583090 <6>[ 2.113206] ledtrig-cpu: registered to indicate activity on CPUs
6174 18:36:38.590531 <6>[ 2.120924] usbcore: registered new interface driver usbhid
6175 18:36:38.593802 <6>[ 2.126766] usbhid: USB HID core driver
6176 18:36:38.604788 <6>[ 2.131084] spi_master spi2: will run message pump with realtime priority
6177 18:36:38.608506 <4>[ 2.131230] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6178 18:36:38.618611 <4>[ 2.145373] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6179 18:36:38.629140 <6>[ 2.149638] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6180 18:36:38.646875 <6>[ 2.167339] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6181 18:36:38.653524 <4>[ 2.175773] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6182 18:36:38.656662 <6>[ 2.188109] cros-ec-spi spi2.0: Chrome EC device registered
6183 18:36:38.668265 <4>[ 2.195377] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6184 18:36:38.679909 <4>[ 2.206933] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6185 18:36:38.686506 <4>[ 2.216049] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6186 18:36:38.699440 <6>[ 2.226051] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6187 18:36:38.743255 <6>[ 2.273571] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6188 18:36:38.750758 <6>[ 2.281042] mmc0: new HS400 MMC card at address 0001
6189 18:36:38.760896 <6>[ 2.283804] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6190 18:36:38.771036 <6>[ 2.293917] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6191 18:36:38.777341 <6>[ 2.296628] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6192 18:36:38.787027 <6>[ 2.300252] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6193 18:36:38.793781 <6>[ 2.302242] NET: Registered PF_PACKET protocol family
6194 18:36:38.797103 <6>[ 2.302392] 9pnet: Installing 9P2000 support
6195 18:36:38.800621 <5>[ 2.302452] Key type dns_resolver registered
6196 18:36:38.807165 <6>[ 2.303196] registered taskstats version 1
6197 18:36:38.810510 <5>[ 2.303222] Loading compiled-in X.509 certificates
6198 18:36:38.820651 <6>[ 2.307420] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6199 18:36:38.827475 <6>[ 2.327324] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6200 18:36:38.837268 <3>[ 2.340972] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6201 18:36:38.840644 <6>[ 2.344636] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6202 18:36:38.847127 <6>[ 2.349672] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6203 18:36:38.853864 <6>[ 2.358116] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6204 18:36:38.864042 <6>[ 2.364020] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6205 18:36:38.870933 <6>[ 2.372635] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6206 18:36:38.877132 <6>[ 2.379015] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6207 18:36:38.887480 <6>[ 2.414466] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6208 18:36:38.897441 <6>[ 2.422989] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6209 18:36:38.904021 <6>[ 2.431506] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6210 18:36:38.914071 <6>[ 2.440025] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6211 18:36:38.920674 <6>[ 2.448542] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6212 18:36:38.930492 <6>[ 2.457061] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6213 18:36:38.937202 <6>[ 2.466301] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6214 18:36:38.943690 <6>[ 2.473847] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6215 18:36:38.950444 <6>[ 2.481152] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6216 18:36:38.961397 <6>[ 2.488399] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6217 18:36:38.967715 <6>[ 2.495868] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6218 18:36:38.974382 <6>[ 2.504177] panfrost 13040000.gpu: clock rate = 511999970
6219 18:36:38.984367 <6>[ 2.509867] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6220 18:36:38.987856 <6>[ 2.512667] hub 1-1:1.0: USB hub found
6221 18:36:38.997428 <6>[ 2.520091] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6222 18:36:39.001055 <6>[ 2.523847] hub 1-1:1.0: 3 ports detected
6223 18:36:39.007461 <6>[ 2.531429] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6224 18:36:39.020930 <6>[ 2.544134] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6225 18:36:39.027588 <6>[ 2.556211] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6226 18:36:39.037736 <6>[ 2.565044] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6227 18:36:39.047900 <6>[ 2.573870] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6228 18:36:39.057447 <6>[ 2.583016] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6229 18:36:39.064370 <6>[ 2.592145] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6230 18:36:39.074353 <6>[ 2.601277] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6231 18:36:39.084298 <6>[ 2.610578] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6232 18:36:39.094650 <6>[ 2.619877] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6233 18:36:39.104456 <6>[ 2.629350] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6234 18:36:39.110681 <6>[ 2.638824] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6235 18:36:39.121226 <6>[ 2.647948] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6236 18:36:39.194321 <6>[ 2.721093] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6237 18:36:39.204057 <6>[ 2.729995] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6238 18:36:39.214820 <6>[ 2.741754] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6239 18:36:39.302221 <6>[ 2.829699] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6240 18:36:39.917526 <6>[ 3.025971] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6241 18:36:39.926916 <4>[ 3.142886] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6242 18:36:39.933828 <4>[ 3.142905] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6243 18:36:39.940304 <6>[ 3.183565] r8152 1-1.2:1.0 eth0: v1.12.13
6244 18:36:39.947201 <6>[ 3.261567] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6245 18:36:39.953701 <6>[ 3.427764] Console: switching to colour frame buffer device 170x48
6246 18:36:39.959919 <6>[ 3.488386] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6247 18:36:39.981639 <6>[ 3.505602] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6248 18:36:40.001718 <6>[ 3.525299] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6249 18:36:40.011685 <6>[ 3.538095] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6250 18:36:40.018141 <6>[ 3.546665] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6251 18:36:40.031898 <6>[ 3.555714] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6252 18:36:40.050965 <6>[ 3.574781] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6253 18:36:41.313269 <6>[ 4.843468] r8152 1-1.2:1.0 eth0: carrier on
6254 18:36:44.055200 <5>[ 4.865563] Sending DHCP requests .., OK
6255 18:36:44.062422 <6>[ 7.590043] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6256 18:36:44.065295 <6>[ 7.598475] IP-Config: Complete:
6257 18:36:44.078528 <6>[ 7.602044] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6258 18:36:44.088384 <6>[ 7.612947] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6259 18:36:44.100484 <6>[ 7.627220] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6260 18:36:44.108654 <6>[ 7.627231] nameserver0=192.168.201.1
6261 18:36:44.116529 <6>[ 7.647009] clk: Disabling unused clocks
6262 18:36:44.121141 <6>[ 7.654945] ALSA device list:
6263 18:36:44.130404 <6>[ 7.660985] No soundcards found.
6264 18:36:44.139732 <6>[ 7.670214] Freeing unused kernel memory: 8512K
6265 18:36:44.146974 <6>[ 7.677351] Run /init as init process
6266 18:36:44.158430 Loading, please wait...
6267 18:36:44.194288 Starting systemd-udevd version 252.22-1~deb12u1
6268 18:36:44.508995 <6>[ 8.035975] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6269 18:36:44.527113 <4>[ 8.053651] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6270 18:36:44.542605 <3>[ 8.064274] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6271 18:36:44.552134 <6>[ 8.070526] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6272 18:36:44.558394 <3>[ 8.075618] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6273 18:36:44.568607 <6>[ 8.093071] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6274 18:36:44.578264 <3>[ 8.093176] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6275 18:36:44.590919 <3>[ 8.117837] elan_i2c 2-0015: Error applying setting, reverse things back
6276 18:36:44.597666 <6>[ 8.126558] mc: Linux media interface: v0.10
6277 18:36:44.607149 <3>[ 8.127003] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6278 18:36:44.617569 <6>[ 8.146346] videodev: Linux video capture interface: v2.00
6279 18:36:44.629473 <4>[ 8.156391] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6280 18:36:44.636498 <5>[ 8.159286] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6281 18:36:44.655757 <3>[ 8.178989] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6282 18:36:44.661861 <4>[ 8.179418] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6283 18:36:44.668567 <3>[ 8.180115] mtk-scp 10500000.scp: invalid resource
6284 18:36:44.678993 <6>[ 8.180437] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6285 18:36:44.685519 <5>[ 8.190111] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6286 18:36:44.692204 <5>[ 8.190727] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6287 18:36:44.704667 <4>[ 8.191104] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6288 18:36:44.712408 <6>[ 8.204599] remoteproc remoteproc0: scp is available
6289 18:36:44.719981 <6>[ 8.205912] cfg80211: failed to load regulatory.db
6290 18:36:44.730419 <3>[ 8.206769] debugfs: File 'Playback' in directory 'dapm' already present!
6291 18:36:44.736869 <3>[ 8.206777] debugfs: File 'Capture' in directory 'dapm' already present!
6292 18:36:44.748404 <4>[ 8.213581] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6293 18:36:44.762572 <3>[ 8.288586] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6294 18:36:44.769390 <6>[ 8.289635] remoteproc remoteproc0: powering up scp
6295 18:36:44.776061 <3>[ 8.298323] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6296 18:36:44.786189 <4>[ 8.303422] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6297 18:36:44.792628 <3>[ 8.315545] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6298 18:36:44.799960 <3>[ 8.320270] remoteproc remoteproc0: request_firmware failed: -2
6299 18:36:44.820717 <3>[ 8.347812] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6300 18:36:44.830868 <6>[ 8.347936] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6301 18:36:44.837554 <3>[ 8.356371] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6302 18:36:44.848784 <3>[ 8.356382] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6303 18:36:44.858363 <3>[ 8.356392] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6304 18:36:44.870288 <3>[ 8.397288] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6305 18:36:44.880305 <3>[ 8.407046] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6306 18:36:44.935450 <6>[ 8.458880] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6307 18:36:44.970504 <6>[ 8.500689] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6308 18:36:44.985942 <6>[ 8.512583] cs_system_cfg: CoreSight Configuration manager initialised
6309 18:36:45.000202 <6>[ 8.526897] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6310 18:36:45.006746 <6>[ 8.527838] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6311 18:36:45.012868 <3>[ 8.529770] thermal_sys: Failed to find 'trips' node
6312 18:36:45.024862 <3>[ 8.529777] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6313 18:36:45.035351 <3>[ 8.529793] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6314 18:36:45.046939 <4>[ 8.529800] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6315 18:36:45.053689 <3>[ 8.533263] thermal_sys: Failed to find 'trips' node
6316 18:36:45.064701 <3>[ 8.533268] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6317 18:36:45.074962 <3>[ 8.533281] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6318 18:36:45.086289 <4>[ 8.533288] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6319 18:36:45.097376 <6>[ 8.533366] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6320 18:36:45.107749 <6>[ 8.535463] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6321 18:36:45.114249 <6>[ 8.634006] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6322 18:36:45.126166 <6>[ 8.652927] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6323 18:36:45.138681 <6>[ 8.653366] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6324 18:36:45.145869 <6>[ 8.665614] Bluetooth: Core ver 2.22
6325 18:36:45.157331 <6>[ 8.684186] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6326 18:36:45.163794 <6>[ 8.685832] NET: Registered PF_BLUETOOTH protocol family
6327 18:36:45.170449 <6>[ 8.692919] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6328 18:36:45.176975 <6>[ 8.697955] Bluetooth: HCI device and connection manager initialized
6329 18:36:45.189232 <6>[ 8.715548] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6330 18:36:45.192447 <6>[ 8.715857] Bluetooth: HCI socket layer initialized
6331 18:36:45.198761 <6>[ 8.717946] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6332 18:36:45.210685 <6>[ 8.724877] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6333 18:36:45.217247 <6>[ 8.728947] Bluetooth: L2CAP socket layer initialized
6334 18:36:45.223962 <6>[ 8.728972] Bluetooth: SCO socket layer initialized
6335 18:36:45.227768 <6>[ 8.752908] Bluetooth: HCI UART driver ver 2.3
6336 18:36:45.237254 <6>[ 8.754846] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6337 18:36:45.244019 <6>[ 8.759724] Bluetooth: HCI UART protocol H4 registered
6338 18:36:45.254030 <6>[ 8.765930] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6339 18:36:45.260367 <6>[ 8.772463] Bluetooth: HCI UART protocol LL registered
6340 18:36:45.266992 <6>[ 8.778408] usbcore: registered new interface driver uvcvideo
6341 18:36:45.277302 <6>[ 8.785889] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6342 18:36:45.287596 <6>[ 8.785897] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6343 18:36:45.297451 <6>[ 8.785999] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6344 18:36:45.304411 <6>[ 8.789598] Bluetooth: HCI UART protocol Three-wire (H5) registered
6345 18:36:45.317310 <6>[ 8.847246] Bluetooth: HCI UART protocol Broadcom registered
6346 18:36:45.323845 <6>[ 8.853915] Bluetooth: HCI UART protocol QCA registered
6347 18:36:45.329920 <6>[ 8.856128] Bluetooth: hci0: setting up ROME/QCA6390
6348 18:36:45.333533 <6>[ 8.859415] Bluetooth: HCI UART protocol Marvell registered
6349 18:36:45.346251 Begin: Loading essential drivers ... done.
6350 18:36:45.349709 Begin: Running /scripts/init-premount ... done.
6351 18:36:45.357003 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6352 18:36:45.366883 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6353 18:36:45.369787 Device /sys/class/net/eth0 found
6354 18:36:45.370214 done.
6355 18:36:45.376641 Begin: Waiting up to 180 secs for any network device to become available ... done.
6356 18:36:45.408756 <6>[ 8.935182] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6357 18:36:45.418644 <4>[ 8.944753] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6358 18:36:45.422168 <4>[ 8.944753] Fallback method does not support PEC.
6359 18:36:45.429727 IP-Config: eth0 hardware address 00:e0:4c:68:0b:b9 mtu 1500 DHCP
6360 18:36:45.439475 IP-Config: eth0 complete (dhcp f<3>[ 8.966803] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6361 18:36:45.443042 rom 192.168.201.1):
6362 18:36:45.450278 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6363 18:36:45.460212 gateway: 192.168.201.1 dns0 : 192<3>[ 8.987125] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6364 18:36:45.463591 .168.201.1 dns1 : 0.0.0.0
6365 18:36:45.470365 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-0
6366 18:36:45.476795 domain : lava-rack
6367 18:36:45.480435 rootserver: 192.168.201.1 rootpath:
6368 18:36:45.483363 filename :
6369 18:36:45.546342 <3>[ 9.076754] Bluetooth: hci0: Frame reassembly failed (-84)
6370 18:36:45.670115 done.
6371 18:36:45.676354 Begin: Running /scripts/nfs-bottom ... done.
6372 18:36:45.688859 Begin: Running /scripts/init-bottom ... done.
6373 18:36:45.783484 <6>[ 9.310137] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6374 18:36:45.820564 <6>[ 9.350707] Bluetooth: hci0: QCA Product ID :0x00000008
6375 18:36:45.828423 <6>[ 9.358654] Bluetooth: hci0: QCA SOC Version :0x00000044
6376 18:36:45.835859 <6>[ 9.366468] Bluetooth: hci0: QCA ROM Version :0x00000302
6377 18:36:45.845080 <6>[ 9.375144] Bluetooth: hci0: QCA Patch Version:0x00000111
6378 18:36:45.853073 <6>[ 9.383525] Bluetooth: hci0: QCA controller version 0x00440302
6379 18:36:45.864619 <6>[ 9.391988] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6380 18:36:45.874720 <4>[ 9.401876] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6381 18:36:45.886488 <3>[ 9.413182] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6382 18:36:45.893427 <3>[ 9.423359] Bluetooth: hci0: QCA Failed to download patch (-2)
6383 18:36:45.914318 <4>[ 9.441607] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6384 18:36:45.934195 <4>[ 9.461106] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6385 18:36:45.950152 <4>[ 9.476960] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6386 18:36:45.960701 <4>[ 9.490729] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6387 18:36:47.096957 <6>[ 10.627404] NET: Registered PF_INET6 protocol family
6388 18:36:47.108686 <6>[ 10.639084] Segment Routing with IPv6
6389 18:36:47.115011 <6>[ 10.645568] In-situ OAM (IOAM) with IPv6
6390 18:36:47.288034 <30>[ 10.792081] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6391 18:36:47.307627 <30>[ 10.838101] systemd[1]: Detected architecture arm64.
6392 18:36:47.318343
6393 18:36:47.321525 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6394 18:36:47.321617
6395 18:36:47.343618 <30>[ 10.874318] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6396 18:36:48.299700 <30>[ 11.826520] systemd[1]: Queued start job for default target graphical.target.
6397 18:36:48.340393 <30>[ 11.867192] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6398 18:36:48.352423 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6399 18:36:48.372706 <30>[ 11.899785] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6400 18:36:48.385347 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6401 18:36:48.404868 <30>[ 11.931962] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6402 18:36:48.418912 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6403 18:36:48.436299 <30>[ 11.963305] systemd[1]: Created slice user.slice - User and Session Slice.
6404 18:36:48.447705 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6405 18:36:48.469882 <30>[ 11.994131] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6406 18:36:48.482662 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6407 18:36:48.502131 <30>[ 12.025953] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6408 18:36:48.513578 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6409 18:36:48.540502 <30>[ 12.057883] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6410 18:36:48.559140 <30>[ 12.086456] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6411 18:36:48.566237 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6412 18:36:48.586691 <30>[ 12.113930] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6413 18:36:48.599073 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6414 18:36:48.618642 <30>[ 12.145778] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6415 18:36:48.632585 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6416 18:36:48.647045 <30>[ 12.177819] systemd[1]: Reached target paths.target - Path Units.
6417 18:36:48.661384 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6418 18:36:48.678347 <30>[ 12.205721] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6419 18:36:48.690875 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6420 18:36:48.703369 <30>[ 12.233704] systemd[1]: Reached target slices.target - Slice Units.
6421 18:36:48.717578 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6422 18:36:48.731011 <30>[ 12.261752] systemd[1]: Reached target swap.target - Swaps.
6423 18:36:48.741924 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6424 18:36:48.762921 <30>[ 12.289798] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6425 18:36:48.775919 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6426 18:36:48.794802 <30>[ 12.322175] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6427 18:36:48.808102 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6428 18:36:48.829317 <30>[ 12.356476] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6429 18:36:48.842955 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6430 18:36:48.860148 <30>[ 12.387525] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6431 18:36:48.871288 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6432 18:36:48.891696 <30>[ 12.419234] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6433 18:36:48.904201 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6434 18:36:48.924541 <30>[ 12.451784] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6435 18:36:48.937905 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6436 18:36:48.957404 <30>[ 12.484934] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6437 18:36:48.970602 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6438 18:36:48.987342 <30>[ 12.514325] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6439 18:36:48.999904 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6440 18:36:49.042405 <30>[ 12.569890] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6441 18:36:49.054603 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6442 18:36:49.068122 <30>[ 12.595212] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6443 18:36:49.081365 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6444 18:36:49.126970 <30>[ 12.654169] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6445 18:36:49.138403 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6446 18:36:49.161911 <30>[ 12.682641] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6447 18:36:49.186086 <30>[ 12.713651] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6448 18:36:49.198223 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6449 18:36:49.242641 <30>[ 12.770227] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6450 18:36:49.256347 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6451 18:36:49.281382 <30>[ 12.808256] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6452 18:36:49.292279 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6453 18:36:49.314862 <30>[ 12.842167] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6454 18:36:49.328534 Startin<6>[ 12.853766] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6455 18:36:49.331705 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6456 18:36:49.357205 <30>[ 12.884255] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6457 18:36:49.371632 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6458 18:36:49.411083 <30>[ 12.938560] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6459 18:36:49.422277 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6460 18:36:49.443699 <30>[ 12.970849] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6461 18:36:49.451922 Startin<6>[ 12.983494] fuse: init (API version 7.37)
6462 18:36:49.459200 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6463 18:36:49.514865 <30>[ 13.042411] systemd[1]: Starting systemd-journald.service - Journal Service...
6464 18:36:49.526627 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6465 18:36:49.550430 <30>[ 13.077701] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6466 18:36:49.561105 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6467 18:36:49.594176 <30>[ 13.118126] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6468 18:36:49.607288 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6469 18:36:49.651290 <30>[ 13.178626] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6470 18:36:49.664649 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6471 18:36:49.688490 <30>[ 13.215913] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6472 18:36:49.701556 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6473 18:36:49.725379 <30>[ 13.252822] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6474 18:36:49.736086 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6475 18:36:49.759146 <30>[ 13.286395] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6476 18:36:49.769601 <3>[ 13.295840] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6477 18:36:49.784161 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 13.311588] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6478 18:36:49.787519 X Message Queue File System.
6479 18:36:49.802976 <30>[ 13.330160] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6480 18:36:49.809894 <3>[ 13.330487] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6481 18:36:49.830874 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 13.357218] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6482 18:36:49.830973 File System.
6483 18:36:49.846961 <3>[ 13.373628] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6484 18:36:49.857387 <30>[ 13.383044] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6485 18:36:49.864042 <3>[ 13.391091] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6486 18:36:49.878422 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6487 18:36:49.885106 <3>[ 13.412747] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6488 18:36:49.897106 <30>[ 13.426906] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6489 18:36:49.907336 <3>[ 13.430041] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6490 18:36:49.914912 <30>[ 13.434791] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6491 18:36:49.930040 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6492 18:36:49.947005 <30>[ 13.474335] systemd[1]: Started systemd-journald.service - Journal Service.
6493 18:36:49.957035 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6494 18:36:49.979631 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6495 18:36:50.001567 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6496 18:36:50.021282 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6497 18:36:50.041459 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6498 18:36:50.060981 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6499 18:36:50.080479 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6500 18:36:50.100173 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6501 18:36:50.120186 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6502 18:36:50.149040 <4>[ 13.669260] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6503 18:36:50.160300 <3>[ 13.687485] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6504 18:36:50.173161 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6505 18:36:50.219883 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6506 18:36:50.246613 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6507 18:36:50.268523 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6508 18:36:50.292194 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6509 18:36:50.322217 Starting [0;1;39msyste<46>[ 13.848443] systemd-journald[320]: Received client request to flush runtime journal.
6510 18:36:50.325324 md-sysctl.se…ce[0m - Apply Kernel Variables...
6511 18:36:50.349334 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6512 18:36:50.375755 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6513 18:36:50.400020 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6514 18:36:50.421059 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6515 18:36:50.442102 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6516 18:36:51.460768 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6517 18:36:51.484724 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6518 18:36:51.528391 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6519 18:36:51.794869 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6520 18:36:51.892727 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6521 18:36:51.912247 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6522 18:36:51.931054 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6523 18:36:51.975681 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6524 18:36:52.001287 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6525 18:36:52.263122 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6526 18:36:52.327063 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6527 18:36:52.345786 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6528 18:36:52.406116 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6529 18:36:52.579392 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization..<4>[ 16.108456] power_supply_show_property: 4 callbacks suppressed
6530 18:36:52.579560 .
6531 18:36:52.590128 <3>[ 16.108472] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6532 18:36:52.600813 <3>[ 16.116082] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6533 18:36:52.615878 <3>[ 16.142821] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6534 18:36:52.632157 <3>[ 16.158969] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6535 18:36:52.647110 <3>[ 16.173732] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6536 18:36:52.661149 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP..<3>[ 16.188633] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6537 18:36:52.664510 .
6538 18:36:52.679206 <3>[ 16.206313] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6539 18:36:52.695349 <3>[ 16.222267] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6540 18:36:52.712647 <3>[ 16.239325] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6541 18:36:52.728142 <3>[ 16.255279] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6542 18:36:52.852046 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6543 18:36:52.874976 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6544 18:36:52.900052 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6545 18:36:52.948027 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6546 18:36:52.984728 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6547 18:36:53.046344 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6548 18:36:53.104595 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6549 18:36:53.129744 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6550 18:36:53.154950 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6551 18:36:53.217384 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6552 18:36:53.237628 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6553 18:36:53.256732 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6554 18:36:53.280205 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6555 18:36:53.300614 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6556 18:36:53.325950 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6557 18:36:53.345984 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6558 18:36:53.362364 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6559 18:36:53.383424 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6560 18:36:53.399832 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6561 18:36:53.425385 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6562 18:36:53.446146 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6563 18:36:53.463590 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6564 18:36:53.486298 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6565 18:36:53.507083 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6566 18:36:53.523968 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6567 18:36:53.542984 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6568 18:36:53.561235 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6569 18:36:53.578847 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6570 18:36:53.595653 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6571 18:36:53.644301 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6572 18:36:53.667618 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6573 18:36:53.698025 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6574 18:36:53.743123 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6575 18:36:53.767113 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6576 18:36:53.789642 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6577 18:36:53.813405 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6578 18:36:53.940159 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6579 18:36:53.989694 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6580 18:36:54.040684 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6581 18:36:54.069491 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6582 18:36:54.090615 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6583 18:36:54.109264 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6584 18:36:54.135537 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6585 18:36:54.156875 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6586 18:36:54.180192 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6587 18:36:54.224567 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6588 18:36:54.317928 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6589 18:36:54.395221
6590 18:36:54.398222 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6591 18:36:54.398321
6592 18:36:54.401608 debian-bookworm-arm64 login: root (automatic login)
6593 18:36:54.401699
6594 18:36:54.678072 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
6595 18:36:54.678211
6596 18:36:54.684229 The programs included with the Debian GNU/Linux system are free software;
6597 18:36:54.691564 the exact distribution terms for each program are described in the
6598 18:36:54.694385 individual files in /usr/share/doc/*/copyright.
6599 18:36:54.694476
6600 18:36:54.701092 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6601 18:36:54.704109 permitted by applicable law.
6602 18:36:55.833210 Matched prompt #10: / #
6604 18:36:55.833583 Setting prompt string to ['/ #']
6605 18:36:55.833688 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6607 18:36:55.833903 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6608 18:36:55.834000 start: 2.2.6 expect-shell-connection (timeout 00:03:58) [common]
6609 18:36:55.834078 Setting prompt string to ['/ #']
6610 18:36:55.834147 Forcing a shell prompt, looking for ['/ #']
6612 18:36:55.884350 / #
6613 18:36:55.884470 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6614 18:36:55.884556 Waiting using forced prompt support (timeout 00:02:30)
6615 18:36:55.889506
6616 18:36:55.889812 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6617 18:36:55.889943 start: 2.2.7 export-device-env (timeout 00:03:58) [common]
6619 18:36:55.990299 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc'
6620 18:36:55.995502 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291342/extract-nfsrootfs-qbjqbfnc'
6622 18:36:56.096007 / # export NFS_SERVER_IP='192.168.201.1'
6623 18:36:56.100798 export NFS_SERVER_IP='192.168.201.1'
6624 18:36:56.101218 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6625 18:36:56.101385 end: 2.2 depthcharge-retry (duration 00:01:02) [common]
6626 18:36:56.101596 end: 2 depthcharge-action (duration 00:01:02) [common]
6627 18:36:56.101771 start: 3 lava-test-retry (timeout 00:08:16) [common]
6628 18:36:56.101933 start: 3.1 lava-test-shell (timeout 00:08:16) [common]
6629 18:36:56.102104 Using namespace: common
6631 18:36:56.202570 / # #
6632 18:36:56.202728 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6633 18:36:56.207896 #
6634 18:36:56.208192 Using /lava-14291342
6636 18:36:56.308537 / # export SHELL=/bin/bash
6637 18:36:56.313065 export SHELL=/bin/bash
6639 18:36:56.413606 / # . /lava-14291342/environment
6640 18:36:56.418800 . /lava-14291342/environment
6642 18:36:56.523492 / # /lava-14291342/bin/lava-test-runner /lava-14291342/0
6643 18:36:56.523676 Test shell timeout: 10s (minimum of the action and connection timeout)
6644 18:36:56.528675 /lava-14291342/bin/lava-test-runner /lava-14291342/0
6645 18:36:56.747526 + export TESTRUN_ID=0_timesync-off
6646 18:36:56.750573 + TESTRUN_ID=0_timesync-off
6647 18:36:56.753931 + cd /lava-14291342/0/tests/0_timesync-off
6648 18:36:56.757572 ++ cat uuid
6649 18:36:56.760790 + UUID=14291342_1.6.2.3.1
6650 18:36:56.760901 + set +x
6651 18:36:56.764044 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291342_1.6.2.3.1>
6652 18:36:56.764345 Received signal: <STARTRUN> 0_timesync-off 14291342_1.6.2.3.1
6653 18:36:56.764456 Starting test lava.0_timesync-off (14291342_1.6.2.3.1)
6654 18:36:56.764597 Skipping test definition patterns.
6655 18:36:56.767143 + systemctl stop systemd-timesyncd
6656 18:36:56.831774 + set +x
6657 18:36:56.834596 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291342_1.6.2.3.1>
6658 18:36:56.834858 Received signal: <ENDRUN> 0_timesync-off 14291342_1.6.2.3.1
6659 18:36:56.834954 Ending use of test pattern.
6660 18:36:56.835045 Ending test lava.0_timesync-off (14291342_1.6.2.3.1), duration 0.07
6662 18:36:56.895512 + export TESTRUN_ID=1_kselftest-alsa
6663 18:36:56.898901 + TESTRUN_ID=1_kselftest-alsa
6664 18:36:56.905712 + cd /lava-14291342/0/tests/1_kselftest-alsa
6665 18:36:56.905830 ++ cat uuid
6666 18:36:56.908543 + UUID=14291342_1.6.2.3.5
6667 18:36:56.908653 + set +x
6668 18:36:56.912014 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14291342_1.6.2.3.5>
6669 18:36:56.912270 Received signal: <STARTRUN> 1_kselftest-alsa 14291342_1.6.2.3.5
6670 18:36:56.912352 Starting test lava.1_kselftest-alsa (14291342_1.6.2.3.5)
6671 18:36:56.912475 Skipping test definition patterns.
6672 18:36:56.915165 + cd ./automated/linux/kselftest/
6673 18:36:56.944857 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6674 18:36:56.977404 INFO: install_deps skipped
6675 18:36:57.469001 --2024-06-11 18:35:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6676 18:36:57.480142 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6677 18:36:57.634009 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6678 18:36:57.787543 HTTP request sent, awaiting response... 200 OK
6679 18:36:57.790903 Length: 1647744 (1.6M) [application/octet-stream]
6680 18:36:57.794190 Saving to: 'kselftest_armhf.tar.gz'
6681 18:36:57.794281
6682 18:36:57.794353
6683 18:36:58.096060 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6684 18:36:58.402673 kselftest_armhf.tar 2%[ ] 46.39K 151KB/s
6685 18:36:58.872497 kselftest_armhf.tar 13%[=> ] 214.67K 349KB/s
6686 18:36:58.970266 kselftest_armhf.tar 45%[========> ] 733.14K 676KB/s
6687 18:36:58.977293 kselftest_armhf.tar 100%[===================>] 1.57M 1.33MB/s in 1.2s
6688 18:36:58.977384
6689 18:36:59.121925 2024-06-11 18:36:01 (1.33 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
6690 18:36:59.122084
6691 18:37:03.217887 skiplist:
6692 18:37:03.221197 ========================================
6693 18:37:03.224524 ========================================
6694 18:37:03.264003 alsa:mixer-test
6695 18:37:03.283037 ============== Tests to run ===============
6696 18:37:03.286679 alsa:mixer-test
6697 18:37:03.289784 ===========End Tests to run ===============
6698 18:37:03.293508 shardfile-alsa pass
6699 18:37:03.403414 <12>[ 26.933437] kselftest: Running tests in alsa
6700 18:37:03.414020 TAP version 13
6701 18:37:03.427664 1..1
6702 18:37:03.442631 # selftests: alsa: mixer-test
6703 18:37:03.591105 <6>[ 27.114790] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6704 18:37:03.604491 <6>[ 27.127194] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6705 18:37:03.617846 <6>[ 27.139495] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6706 18:37:03.627416 <6>[ 27.151789] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6707 18:37:03.641007 <6>[ 27.164044] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6708 18:37:03.650657 <6>[ 27.176280] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6709 18:37:03.663843 <6>[ 27.187748] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6710 18:37:03.674454 <6>[ 27.199132] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6711 18:37:03.687411 <6>[ 27.210477] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6712 18:37:03.697549 <6>[ 27.221814] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6713 18:37:03.710702 <6>[ 27.233161] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6714 18:37:03.720564 <6>[ 27.244493] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6715 18:37:03.730228 <6>[ 27.255826] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6716 18:37:03.743418 <6>[ 27.267161] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6717 18:37:03.753648 <6>[ 27.278504] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6718 18:37:03.766825 <6>[ 27.289864] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6719 18:37:03.776416 <6>[ 27.301220] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6720 18:37:03.790128 <6>[ 27.312594] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6721 18:37:03.799418 <6>[ 27.323979] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6722 18:37:03.813176 <6>[ 27.335351] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6723 18:37:03.822779 <6>[ 27.346738] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6724 18:37:03.832579 <6>[ 27.358120] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6725 18:37:03.845637 <6>[ 27.369457] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6726 18:37:03.855970 <6>[ 27.380793] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6727 18:37:03.868986 <6>[ 27.392126] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6728 18:37:03.878974 <6>[ 27.403464] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6729 18:37:03.892401 <6>[ 27.414795] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6730 18:37:03.902478 <6>[ 27.426125] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6731 18:37:03.912235 <6>[ 27.437463] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6732 18:37:03.925483 # TAP version 13<6>[ 27.448803] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6733 18:37:03.925764
6734 18:37:03.928854 # 1..658
6735 18:37:03.929126 # ok 1 get_value.0.93
6736 18:37:03.931891 # ok 2 name.0.93
6737 18:37:03.932247 # ok 3 write_default.0.93
6738 18:37:03.935150 # ok 4 write_valid.0.93
6739 18:37:03.938522 # ok 5 write_invalid.0.93
6740 18:37:03.942394 # ok 6 event_missing.0.93
6741 18:37:03.942694 # ok 7 event_spurious.0.93
6742 18:37:03.945346 # ok 8 get_value.0.92
6743 18:37:03.945687 # ok 9 name.0.92
6744 18:37:03.948882 # ok 10 write_default.0.92
6745 18:37:03.951909 # ok 11 write_valid.0.92
6746 18:37:03.955223 # ok 12 write_invalid.0.92
6747 18:37:03.955489 # ok 13 event_missing.0.92
6748 18:37:03.958386 # ok 14 event_spurious.0.92
6749 18:37:03.961667 # ok 15 get_value.0.91
6750 18:37:03.961918 # ok 16 name.0.91
6751 18:37:03.965226 # ok 17 write_default.0.91
6752 18:37:03.968168 # ok 18 write_valid.0.91
6753 18:37:03.971810 # ok 19 write_invalid.0.91
6754 18:37:03.972079 # ok 20 event_missing.0.91
6755 18:37:03.975304 # ok 21 event_spurious.0.91
6756 18:37:03.978182 # ok 22 get_value.0.90
6757 18:37:03.978512 # ok 23 name.0.90
6758 18:37:03.981905 # ok 24 write_default.0.90
6759 18:37:03.985029 # ok 25 write_valid.0.90
6760 18:37:03.988281 # ok 26 write_invalid.0.90
6761 18:37:03.988539 # ok 27 event_missing.0.90
6762 18:37:03.991268 # ok 28 event_spurious.0.90
6763 18:37:03.994898 # ok 29 get_value.0.89
6764 18:37:03.995107 # ok 30 name.0.89
6765 18:37:03.998494 # ok 31 write_default.0.89
6766 18:37:04.001651 # ok 32 write_valid.0.89
6767 18:37:04.004692 # ok 33 write_invalid.0.89
6768 18:37:04.007687 # ok 34 event_missing.0.89
6769 18:37:04.007805 # ok 35 event_spurious.0.89
6770 18:37:04.011411 # ok 36 get_value.0.88
6771 18:37:04.014556 # ok 37 name.0.88
6772 18:37:04.014679 # ok 38 write_default.0.88
6773 18:37:04.021217 # # Spurious event generated for AIF Out Mux
6774 18:37:04.024476 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6775 18:37:04.030936 # # Spurious event generated for AIF Out Mux
6776 18:37:04.034327 # not ok 39 write_valid.0.88
6777 18:37:04.034416 # ok 40 write_invalid.0.88
6778 18:37:04.037428 # ok 41 event_missing.0.88
6779 18:37:04.041142 # not ok 42 event_spurious.0.88
6780 18:37:04.044303 # ok 43 get_value.0.87
6781 18:37:04.044384 # ok 44 name.0.87
6782 18:37:04.047944 # ok 45 write_default.0.87
6783 18:37:04.051045 # ok 46 write_valid.0.87
6784 18:37:04.053864 # ok 47 write_invalid.0.87
6785 18:37:04.057947 # ok 48 event_missing.0.87
6786 18:37:04.058030 # ok 49 event_spurious.0.87
6787 18:37:04.060568 # ok 50 get_value.0.86
6788 18:37:04.064126 # ok 51 name.0.86
6789 18:37:04.064207 # ok 52 write_default.0.86
6790 18:37:04.071212 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6791 18:37:04.074114 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6792 18:37:04.080729 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6793 18:37:04.084235 # not ok 53 write_valid.0.86
6794 18:37:04.087197 # ok 54 write_invalid.0.86
6795 18:37:04.087278 # ok 55 event_missing.0.86
6796 18:37:04.090637 # ok 56 event_spurious.0.86
6797 18:37:04.093782 # ok 57 get_value.0.85
6798 18:37:04.093868 # ok 58 name.0.85
6799 18:37:04.097022 # ok 59 write_default.0.85
6800 18:37:04.103944 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6801 18:37:04.107666 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6802 18:37:04.110681 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6803 18:37:04.114354 # not ok 60 write_valid.0.85
6804 18:37:04.117255 # ok 61 write_invalid.0.85
6805 18:37:04.120397 # ok 62 event_missing.0.85
6806 18:37:04.120478 # ok 63 event_spurious.0.85
6807 18:37:04.123584 # ok 64 get_value.0.84
6808 18:37:04.127201 # ok 65 name.0.84
6809 18:37:04.127281 # ok 66 write_default.0.84
6810 18:37:04.130181 # ok 67 write_valid.0.84
6811 18:37:04.133867 # ok 68 write_invalid.0.84
6812 18:37:04.137093 # ok 69 event_missing.0.84
6813 18:37:04.140644 # ok 70 event_spurious.0.84
6814 18:37:04.140735 # ok 71 get_value.0.83
6815 18:37:04.143686 # ok 72 name.0.83
6816 18:37:04.147259 # ok 73 write_default.0.83
6817 18:37:04.147349 # ok 74 write_valid.0.83
6818 18:37:04.150125 # ok 75 write_invalid.0.83
6819 18:37:04.153661 # ok 76 event_missing.0.83
6820 18:37:04.156745 # ok 77 event_spurious.0.83
6821 18:37:04.160125 # ok 78 get_value.0.82
6822 18:37:04.160215 # ok 79 name.0.82
6823 18:37:04.163572 # # Headset Jack is not writeable
6824 18:37:04.166706 # ok 80 # SKIP write_default.0.82
6825 18:37:04.170274 # # Headset Jack is not writeable
6826 18:37:04.173831 # ok 81 # SKIP write_valid.0.82
6827 18:37:04.176941 # # Headset Jack is not writeable
6828 18:37:04.180472 # ok 82 # SKIP write_invalid.0.82
6829 18:37:04.183963 # ok 83 event_missing.0.82
6830 18:37:04.187129 # ok 84 event_spurious.0.82
6831 18:37:04.187219 # ok 85 get_value.0.81
6832 18:37:04.190663 # ok 86 name.0.81
6833 18:37:04.190753 # ok 87 write_default.0.81
6834 18:37:04.196948 # # No event generated for Wake-on-Voice Phase2 Switch
6835 18:37:04.200357 # # No event generated for Wake-on-Voice Phase2 Switch
6836 18:37:04.203822 # ok 88 write_valid.0.81
6837 18:37:04.210154 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6838 18:37:04.213421 # # No event generated for Wake-on-Voice Phase2 Switch
6839 18:37:04.216850 # not ok 89 write_invalid.0.81
6840 18:37:04.219895 # not ok 90 event_missing.0.81
6841 18:37:04.223696 # ok 91 event_spurious.0.81
6842 18:37:04.223786 # ok 92 get_value.0.80
6843 18:37:04.226526 # ok 93 name.0.80
6844 18:37:04.230091 # ok 94 write_default.0.80
6845 18:37:04.230182 # ok 95 write_valid.0.80
6846 18:37:04.233584 # ok 96 write_invalid.0.80
6847 18:37:04.236963 # ok 97 event_missing.0.80
6848 18:37:04.240120 # ok 98 event_spurious.0.80
6849 18:37:04.243542 # # Handset Volume.0 value -13 less than minimum 0
6850 18:37:04.246870 # not ok 99 get_value.0.79
6851 18:37:04.246960 # ok 100 name.0.79
6852 18:37:04.253347 # # snd_ctl_elem_write() failed: Invalid argument
6853 18:37:04.256433 # not ok 101 write_default.0.79
6854 18:37:04.259959 # # snd_ctl_elem_write() failed: Invalid argument
6855 18:37:04.263122 # not ok 102 write_valid.0.79
6856 18:37:04.266534 # # snd_ctl_elem_write() failed: Invalid argument
6857 18:37:04.269759 # not ok 103 write_invalid.0.79
6858 18:37:04.273045 # ok 104 event_missing.0.79
6859 18:37:04.276746 # ok 105 event_spurious.0.79
6860 18:37:04.280098 # # Lineout Volume.0 value -13 less than minimum 0
6861 18:37:04.283244 # # Lineout Volume.1 value -13 less than minimum 0
6862 18:37:04.286696 # not ok 106 get_value.0.78
6863 18:37:04.289870 # ok 107 name.0.78
6864 18:37:04.293398 # # snd_ctl_elem_write() failed: Invalid argument
6865 18:37:04.296720 # not ok 108 write_default.0.78
6866 18:37:04.299884 # # snd_ctl_elem_write() failed: Invalid argument
6867 18:37:04.303396 # not ok 109 write_valid.0.78
6868 18:37:04.307075 # # snd_ctl_elem_write() failed: Invalid argument
6869 18:37:04.309940 # not ok 110 write_invalid.0.78
6870 18:37:04.312967 # ok 111 event_missing.0.78
6871 18:37:04.316359 # ok 112 event_spurious.0.78
6872 18:37:04.320096 # # Headphone Volume.0 value -13 less than minimum 0
6873 18:37:04.326693 # # Headphone Volume.1 value -13 less than minimum 0
6874 18:37:04.329755 # not ok 113 get_value.0.77
6875 18:37:04.329841 # ok 114 name.0.77
6876 18:37:04.336149 # # snd_ctl_elem_write() failed: Invalid argument
6877 18:37:04.336270 # not ok 115 write_default.0.77
6878 18:37:04.342838 # # snd_ctl_elem_write() failed: Invalid argument
6879 18:37:04.346545 # not ok 116 write_valid.0.77
6880 18:37:04.349640 # # snd_ctl_elem_write() failed: Invalid argument
6881 18:37:04.352751 # not ok 117 write_invalid.0.77
6882 18:37:04.355775 # ok 118 event_missing.0.77
6883 18:37:04.359656 # ok 119 event_spurious.0.77
6884 18:37:04.359737 # ok 120 get_value.0.76
6885 18:37:04.366131 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6886 18:37:04.369270 # not ok 121 name.0.76
6887 18:37:04.372966 # ok 122 write_default.0.76
6888 18:37:04.376370 # ok 123 write_valid.0.76
6889 18:37:04.376455 # ok 124 write_invalid.0.76
6890 18:37:04.379357 # ok 125 event_missing.0.76
6891 18:37:04.383084 # ok 126 event_spurious.0.76
6892 18:37:04.386079 # ok 127 get_value.0.75
6893 18:37:04.392471 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6894 18:37:04.392573 # not ok 128 name.0.75
6895 18:37:04.396023 # ok 129 write_default.0.75
6896 18:37:04.399493 # ok 130 write_valid.0.75
6897 18:37:04.402570 # ok 131 write_invalid.0.75
6898 18:37:04.402663 # ok 132 event_missing.0.75
6899 18:37:04.406309 # ok 133 event_spurious.0.75
6900 18:37:04.409887 # ok 134 get_value.0.74
6901 18:37:04.416105 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6902 18:37:04.419472 # not ok 135 name.0.74
6903 18:37:04.419566 # ok 136 write_default.0.74
6904 18:37:04.422291 # ok 137 write_valid.0.74
6905 18:37:04.425669 # ok 138 write_invalid.0.74
6906 18:37:04.429215 # ok 139 event_missing.0.74
6907 18:37:04.432496 # ok 140 event_spurious.0.74
6908 18:37:04.432590 # ok 141 get_value.0.73
6909 18:37:04.438924 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6910 18:37:04.442626 # not ok 142 name.0.73
6911 18:37:04.445618 # ok 143 write_default.0.73
6912 18:37:04.445711 # ok 144 write_valid.0.73
6913 18:37:04.449099 # ok 145 write_invalid.0.73
6914 18:37:04.452722 # ok 146 event_missing.0.73
6915 18:37:04.455694 # ok 147 event_spurious.0.73
6916 18:37:04.459017 # ok 148 get_value.0.72
6917 18:37:04.465477 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6918 18:37:04.465571 # not ok 149 name.0.72
6919 18:37:04.468954 # ok 150 write_default.0.72
6920 18:37:04.471871 # ok 151 write_valid.0.72
6921 18:37:04.471965 # ok 152 write_invalid.0.72
6922 18:37:04.475246 # ok 153 event_missing.0.72
6923 18:37:04.478547 # ok 154 event_spurious.0.72
6924 18:37:04.481841 # ok 155 get_value.0.71
6925 18:37:04.488556 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6926 18:37:04.488685 # not ok 156 name.0.71
6927 18:37:04.492304 # ok 157 write_default.0.71
6928 18:37:04.495426 # ok 158 write_valid.0.71
6929 18:37:04.498511 # ok 159 write_invalid.0.71
6930 18:37:04.498605 # ok 160 event_missing.0.71
6931 18:37:04.502084 # ok 161 event_spurious.0.71
6932 18:37:04.505476 # ok 162 get_value.0.70
6933 18:37:04.511782 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6934 18:37:04.511908 # not ok 163 name.0.70
6935 18:37:04.515130 # ok 164 write_default.0.70
6936 18:37:04.518897 # ok 165 write_valid.0.70
6937 18:37:04.521690 # ok 166 write_invalid.0.70
6938 18:37:04.525263 # ok 167 event_missing.0.70
6939 18:37:04.525343 # ok 168 event_spurious.0.70
6940 18:37:04.528605 # ok 169 get_value.0.69
6941 18:37:04.535245 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6942 18:37:04.538199 # not ok 170 name.0.69
6943 18:37:04.538292 # ok 171 write_default.0.69
6944 18:37:04.541706 # ok 172 write_valid.0.69
6945 18:37:04.545199 # ok 173 write_invalid.0.69
6946 18:37:04.548352 # ok 174 event_missing.0.69
6947 18:37:04.551847 # ok 175 event_spurious.0.69
6948 18:37:04.551935 # ok 176 get_value.0.68
6949 18:37:04.558436 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6950 18:37:04.561940 # not ok 177 name.0.68
6951 18:37:04.565158 # ok 178 write_default.0.68
6952 18:37:04.565261 # ok 179 write_valid.0.68
6953 18:37:04.568337 # ok 180 write_invalid.0.68
6954 18:37:04.571696 # ok 181 event_missing.0.68
6955 18:37:04.574669 # ok 182 event_spurious.0.68
6956 18:37:04.574751 # ok 183 get_value.0.67
6957 18:37:04.581353 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6958 18:37:04.585100 # not ok 184 name.0.67
6959 18:37:04.588015 # ok 185 write_default.0.67
6960 18:37:04.588135 # ok 186 write_valid.0.67
6961 18:37:04.591715 # ok 187 write_invalid.0.67
6962 18:37:04.594735 # ok 188 event_missing.0.67
6963 18:37:04.598230 # ok 189 event_spurious.0.67
6964 18:37:04.598311 # ok 190 get_value.0.66
6965 18:37:04.604921 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6966 18:37:04.608281 # not ok 191 name.0.66
6967 18:37:04.611568 # ok 192 write_default.0.66
6968 18:37:04.611658 # ok 193 write_valid.0.66
6969 18:37:04.614598 # ok 194 write_invalid.0.66
6970 18:37:04.617842 # ok 195 event_missing.0.66
6971 18:37:04.621438 # ok 196 event_spurious.0.66
6972 18:37:04.621526 # ok 197 get_value.0.65
6973 18:37:04.627877 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6974 18:37:04.631334 # not ok 198 name.0.65
6975 18:37:04.634739 # ok 199 write_default.0.65
6976 18:37:04.634830 # ok 200 write_valid.0.65
6977 18:37:04.638270 # ok 201 write_invalid.0.65
6978 18:37:04.641555 # ok 202 event_missing.0.65
6979 18:37:04.644577 # ok 203 event_spurious.0.65
6980 18:37:04.644667 # ok 204 get_value.0.64
6981 18:37:04.651718 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6982 18:37:04.654685 # not ok 205 name.0.64
6983 18:37:04.657670 # ok 206 write_default.0.64
6984 18:37:04.657761 # ok 207 write_valid.0.64
6985 18:37:04.661204 # ok 208 write_invalid.0.64
6986 18:37:04.664433 # ok 209 event_missing.0.64
6987 18:37:04.667871 # ok 210 event_spurious.0.64
6988 18:37:04.667962 # ok 211 get_value.0.63
6989 18:37:04.674840 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6990 18:37:04.677437 # not ok 212 name.0.63
6991 18:37:04.681161 # ok 213 write_default.0.63
6992 18:37:04.681252 # ok 214 write_valid.0.63
6993 18:37:04.684355 # ok 215 write_invalid.0.63
6994 18:37:04.687529 # ok 216 event_missing.0.63
6995 18:37:04.690802 # ok 217 event_spurious.0.63
6996 18:37:04.690897 # ok 218 get_value.0.62
6997 18:37:04.697634 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
6998 18:37:04.700904 # not ok 219 name.0.62
6999 18:37:04.704446 # ok 220 write_default.0.62
7000 18:37:04.704537 # ok 221 write_valid.0.62
7001 18:37:04.707634 # ok 222 write_invalid.0.62
7002 18:37:04.710610 # ok 223 event_missing.0.62
7003 18:37:04.714096 # ok 224 event_spurious.0.62
7004 18:37:04.714194 # ok 225 get_value.0.61
7005 18:37:04.720410 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7006 18:37:04.724020 # not ok 226 name.0.61
7007 18:37:04.727359 # ok 227 write_default.0.61
7008 18:37:04.727471 # ok 228 write_valid.0.61
7009 18:37:04.730470 # ok 229 write_invalid.0.61
7010 18:37:04.733816 # ok 230 event_missing.0.61
7011 18:37:04.737358 # ok 231 event_spurious.0.61
7012 18:37:04.737565 # ok 232 get_value.0.60
7013 18:37:04.743685 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
7014 18:37:04.747062 # not ok 233 name.0.60
7015 18:37:04.750244 # ok 234 write_default.0.60
7016 18:37:04.750335 # ok 235 write_valid.0.60
7017 18:37:04.753677 # ok 236 write_invalid.0.60
7018 18:37:04.756956 # ok 237 event_missing.0.60
7019 18:37:04.760304 # ok 238 event_spurious.0.60
7020 18:37:04.760394 # ok 239 get_value.0.59
7021 18:37:04.767090 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
7022 18:37:04.770425 # not ok 240 name.0.59
7023 18:37:04.770515 # ok 241 write_default.0.59
7024 18:37:04.773596 # ok 242 write_valid.0.59
7025 18:37:04.777056 # ok 243 write_invalid.0.59
7026 18:37:04.780332 # ok 244 event_missing.0.59
7027 18:37:04.780422 # ok 245 event_spurious.0.59
7028 18:37:04.783639 # ok 246 get_value.0.58
7029 18:37:04.790144 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7030 18:37:04.793541 # not ok 247 name.0.58
7031 18:37:04.793632 # ok 248 write_default.0.58
7032 18:37:04.796916 # ok 249 write_valid.0.58
7033 18:37:04.800356 # ok 250 write_invalid.0.58
7034 18:37:04.803844 # ok 251 event_missing.0.58
7035 18:37:04.803935 # ok 252 event_spurious.0.58
7036 18:37:04.807006 # ok 253 get_value.0.57
7037 18:37:04.813792 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7038 18:37:04.813900 # not ok 254 name.0.57
7039 18:37:04.816753 # ok 255 write_default.0.57
7040 18:37:04.820507 # ok 256 write_valid.0.57
7041 18:37:04.823804 # ok 257 write_invalid.0.57
7042 18:37:04.823895 # ok 258 event_missing.0.57
7043 18:37:04.826843 # ok 259 event_spurious.0.57
7044 18:37:04.830261 # ok 260 get_value.0.56
7045 18:37:04.833436 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7046 18:37:04.836887 # not ok 261 name.0.56
7047 18:37:04.840098 # ok 262 write_default.0.56
7048 18:37:04.843364 # ok 263 write_valid.0.56
7049 18:37:04.843493 # ok 264 write_invalid.0.56
7050 18:37:04.846769 # ok 265 event_missing.0.56
7051 18:37:04.850183 # ok 266 event_spurious.0.56
7052 18:37:04.853320 # ok 267 get_value.0.55
7053 18:37:04.856614 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7054 18:37:04.859983 # not ok 268 name.0.55
7055 18:37:04.863365 # ok 269 write_default.0.55
7056 18:37:04.863496 # ok 270 write_valid.0.55
7057 18:37:04.866717 # ok 271 write_invalid.0.55
7058 18:37:04.869947 # ok 272 event_missing.0.55
7059 18:37:04.873612 # ok 273 event_spurious.0.55
7060 18:37:04.873702 # ok 274 get_value.0.54
7061 18:37:04.880190 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7062 18:37:04.883037 # not ok 275 name.0.54
7063 18:37:04.883157 # ok 276 write_default.0.54
7064 18:37:04.886473 # ok 277 write_valid.0.54
7065 18:37:04.889552 # ok 278 write_invalid.0.54
7066 18:37:04.893212 # ok 279 event_missing.0.54
7067 18:37:04.896460 # ok 280 event_spurious.0.54
7068 18:37:04.896551 # ok 281 get_value.0.53
7069 18:37:04.903098 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7070 18:37:04.906611 # not ok 282 name.0.53
7071 18:37:04.906701 # ok 283 write_default.0.53
7072 18:37:04.909337 # ok 284 write_valid.0.53
7073 18:37:04.913040 # ok 285 write_invalid.0.53
7074 18:37:04.916231 # ok 286 event_missing.0.53
7075 18:37:04.916321 # ok 287 event_spurious.0.53
7076 18:37:04.919799 # ok 288 get_value.0.52
7077 18:37:04.926489 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7078 18:37:04.926580 # not ok 289 name.0.52
7079 18:37:04.929353 # ok 290 write_default.0.52
7080 18:37:04.933043 # ok 291 write_valid.0.52
7081 18:37:04.935824 # ok 292 write_invalid.0.52
7082 18:37:04.935914 # ok 293 event_missing.0.52
7083 18:37:04.939563 # ok 294 event_spurious.0.52
7084 18:37:04.942490 # ok 295 get_value.0.51
7085 18:37:04.949014 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7086 18:37:04.949106 # not ok 296 name.0.51
7087 18:37:04.952594 # ok 297 write_default.0.51
7088 18:37:04.955788 # ok 298 write_valid.0.51
7089 18:37:04.955878 # ok 299 write_invalid.0.51
7090 18:37:04.959258 # ok 300 event_missing.0.51
7091 18:37:04.962837 # ok 301 event_spurious.0.51
7092 18:37:04.966077 # ok 302 get_value.0.50
7093 18:37:04.969165 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7094 18:37:04.972695 # not ok 303 name.0.50
7095 18:37:04.975770 # ok 304 write_default.0.50
7096 18:37:04.975861 # ok 305 write_valid.0.50
7097 18:37:04.979333 # ok 306 write_invalid.0.50
7098 18:37:04.982698 # ok 307 event_missing.0.50
7099 18:37:04.985675 # ok 308 event_spurious.0.50
7100 18:37:04.985765 # ok 309 get_value.0.49
7101 18:37:04.992627 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7102 18:37:04.995553 # not ok 310 name.0.49
7103 18:37:04.999344 # ok 311 write_default.0.49
7104 18:37:04.999443 # ok 312 write_valid.0.49
7105 18:37:05.002117 # ok 313 write_invalid.0.49
7106 18:37:05.005832 # ok 314 event_missing.0.49
7107 18:37:05.009042 # ok 315 event_spurious.0.49
7108 18:37:05.009132 # ok 316 get_value.0.48
7109 18:37:05.015321 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7110 18:37:05.018996 # not ok 317 name.0.48
7111 18:37:05.019085 # ok 318 write_default.0.48
7112 18:37:05.022236 # ok 319 write_valid.0.48
7113 18:37:05.025363 # ok 320 write_invalid.0.48
7114 18:37:05.028897 # ok 321 event_missing.0.48
7115 18:37:05.028983 # ok 322 event_spurious.0.48
7116 18:37:05.032043 # ok 323 get_value.0.47
7117 18:37:05.038553 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7118 18:37:05.038643 # not ok 324 name.0.47
7119 18:37:05.042186 # ok 325 write_default.0.47
7120 18:37:05.045265 # ok 326 write_valid.0.47
7121 18:37:05.048564 # ok 327 write_invalid.0.47
7122 18:37:05.048684 # ok 328 event_missing.0.47
7123 18:37:05.052083 # ok 329 event_spurious.0.47
7124 18:37:05.055014 # ok 330 get_value.0.46
7125 18:37:05.061773 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7126 18:37:05.061863 # not ok 331 name.0.46
7127 18:37:05.065134 # ok 332 write_default.0.46
7128 18:37:05.068482 # ok 333 write_valid.0.46
7129 18:37:05.072150 # ok 334 write_invalid.0.46
7130 18:37:05.072240 # ok 335 event_missing.0.46
7131 18:37:05.075158 # ok 336 event_spurious.0.46
7132 18:37:05.078979 # ok 337 get_value.0.45
7133 18:37:05.081679 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7134 18:37:05.085066 # not ok 338 name.0.45
7135 18:37:05.088441 # ok 339 write_default.0.45
7136 18:37:05.091360 # ok 340 write_valid.0.45
7137 18:37:05.091459 # ok 341 write_invalid.0.45
7138 18:37:05.095470 # ok 342 event_missing.0.45
7139 18:37:05.098261 # ok 343 event_spurious.0.45
7140 18:37:05.102083 # ok 344 get_value.0.44
7141 18:37:05.105013 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7142 18:37:05.108661 # not ok 345 name.0.44
7143 18:37:05.111702 # ok 346 write_default.0.44
7144 18:37:05.111792 # ok 347 write_valid.0.44
7145 18:37:05.114712 # ok 348 write_invalid.0.44
7146 18:37:05.117955 # ok 349 event_missing.0.44
7147 18:37:05.121356 # ok 350 event_spurious.0.44
7148 18:37:05.121447 # ok 351 get_value.0.43
7149 18:37:05.128192 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7150 18:37:05.131253 # not ok 352 name.0.43
7151 18:37:05.131342 # ok 353 write_default.0.43
7152 18:37:05.134693 # ok 354 write_valid.0.43
7153 18:37:05.138266 # ok 355 write_invalid.0.43
7154 18:37:05.141170 # ok 356 event_missing.0.43
7155 18:37:05.141260 # ok 357 event_spurious.0.43
7156 18:37:05.145004 # ok 358 get_value.0.42
7157 18:37:05.151572 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7158 18:37:05.151663 # not ok 359 name.0.42
7159 18:37:05.154801 # ok 360 write_default.0.42
7160 18:37:05.158413 # ok 361 write_valid.0.42
7161 18:37:05.161422 # ok 362 write_invalid.0.42
7162 18:37:05.161513 # ok 363 event_missing.0.42
7163 18:37:05.164395 # ok 364 event_spurious.0.42
7164 18:37:05.167947 # ok 365 get_value.0.41
7165 18:37:05.174820 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7166 18:37:05.174911 # not ok 366 name.0.41
7167 18:37:05.177970 # ok 367 write_default.0.41
7168 18:37:05.181164 # ok 368 write_valid.0.41
7169 18:37:05.184335 # ok 369 write_invalid.0.41
7170 18:37:05.184426 # ok 370 event_missing.0.41
7171 18:37:05.188072 # ok 371 event_spurious.0.41
7172 18:37:05.191466 # ok 372 get_value.0.40
7173 18:37:05.194733 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7174 18:37:05.197898 # not ok 373 name.0.40
7175 18:37:05.201082 # ok 374 write_default.0.40
7176 18:37:05.204717 # ok 375 write_valid.0.40
7177 18:37:05.204807 # ok 376 write_invalid.0.40
7178 18:37:05.207664 # ok 377 event_missing.0.40
7179 18:37:05.211298 # ok 378 event_spurious.0.40
7180 18:37:05.214171 # ok 379 get_value.0.39
7181 18:37:05.218129 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7182 18:37:05.220842 # not ok 380 name.0.39
7183 18:37:05.224124 # ok 381 write_default.0.39
7184 18:37:05.224215 # ok 382 write_valid.0.39
7185 18:37:05.227432 # ok 383 write_invalid.0.39
7186 18:37:05.231046 # ok 384 event_missing.0.39
7187 18:37:05.234154 # ok 385 event_spurious.0.39
7188 18:37:05.234248 # ok 386 get_value.0.38
7189 18:37:05.240939 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7190 18:37:05.244088 # not ok 387 name.0.38
7191 18:37:05.247523 # ok 388 write_default.0.38
7192 18:37:05.247613 # ok 389 write_valid.0.38
7193 18:37:05.250916 # ok 390 write_invalid.0.38
7194 18:37:05.254191 # ok 391 event_missing.0.38
7195 18:37:05.257458 # ok 392 event_spurious.0.38
7196 18:37:05.257548 # ok 393 get_value.0.37
7197 18:37:05.264295 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7198 18:37:05.267705 # not ok 394 name.0.37
7199 18:37:05.270783 # ok 395 write_default.0.37
7200 18:37:05.270873 # ok 396 write_valid.0.37
7201 18:37:05.274461 # ok 397 write_invalid.0.37
7202 18:37:05.277261 # ok 398 event_missing.0.37
7203 18:37:05.280547 # ok 399 event_spurious.0.37
7204 18:37:05.280637 # ok 400 get_value.0.36
7205 18:37:05.287462 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7206 18:37:05.290903 # not ok 401 name.0.36
7207 18:37:05.293884 # ok 402 write_default.0.36
7208 18:37:05.294002 # ok 403 write_valid.0.36
7209 18:37:05.297411 # ok 404 write_invalid.0.36
7210 18:37:05.300977 # ok 405 event_missing.0.36
7211 18:37:05.303959 # ok 406 event_spurious.0.36
7212 18:37:05.304049 # ok 407 get_value.0.35
7213 18:37:05.310700 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7214 18:37:05.313996 # not ok 408 name.0.35
7215 18:37:05.317195 # ok 409 write_default.0.35
7216 18:37:05.317285 # ok 410 write_valid.0.35
7217 18:37:05.320284 # ok 411 write_invalid.0.35
7218 18:37:05.323925 # ok 412 event_missing.0.35
7219 18:37:05.327183 # ok 413 event_spurious.0.35
7220 18:37:05.327273 # ok 414 get_value.0.34
7221 18:37:05.333782 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7222 18:37:05.337114 # not ok 415 name.0.34
7223 18:37:05.340266 # ok 416 write_default.0.34
7224 18:37:05.340356 # ok 417 write_valid.0.34
7225 18:37:05.343672 # ok 418 write_invalid.0.34
7226 18:37:05.347078 # ok 419 event_missing.0.34
7227 18:37:05.350425 # ok 420 event_spurious.0.34
7228 18:37:05.350516 # ok 421 get_value.0.33
7229 18:37:05.356607 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7230 18:37:05.360454 # not ok 422 name.0.33
7231 18:37:05.360545 # ok 423 write_default.0.33
7232 18:37:05.363312 # ok 424 write_valid.0.33
7233 18:37:05.366793 # ok 425 write_invalid.0.33
7234 18:37:05.370275 # ok 426 event_missing.0.33
7235 18:37:05.370366 # ok 427 event_spurious.0.33
7236 18:37:05.373700 # ok 428 get_value.0.32
7237 18:37:05.380409 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7238 18:37:05.383397 # not ok 429 name.0.32
7239 18:37:05.383494 # ok 430 write_default.0.32
7240 18:37:05.386863 # ok 431 write_valid.0.32
7241 18:37:05.390185 # ok 432 write_invalid.0.32
7242 18:37:05.393160 # ok 433 event_missing.0.32
7243 18:37:05.393250 # ok 434 event_spurious.0.32
7244 18:37:05.396526 # ok 435 get_value.0.31
7245 18:37:05.403609 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7246 18:37:05.406379 # not ok 436 name.0.31
7247 18:37:05.406469 # ok 437 write_default.0.31
7248 18:37:05.409843 # ok 438 write_valid.0.31
7249 18:37:05.412890 # ok 439 write_invalid.0.31
7250 18:37:05.416711 # ok 440 event_missing.0.31
7251 18:37:05.416802 # ok 441 event_spurious.0.31
7252 18:37:05.419435 # ok 442 get_value.0.30
7253 18:37:05.426497 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7254 18:37:05.429879 # not ok 443 name.0.30
7255 18:37:05.429970 # ok 444 write_default.0.30
7256 18:37:05.432795 # ok 445 write_valid.0.30
7257 18:37:05.436338 # ok 446 write_invalid.0.30
7258 18:37:05.439763 # ok 447 event_missing.0.30
7259 18:37:05.439855 # ok 448 event_spurious.0.30
7260 18:37:05.442808 # ok 449 get_value.0.29
7261 18:37:05.446253 # ok 450 name.0.29
7262 18:37:05.446344 # ok 451 write_default.0.29
7263 18:37:05.449819 # ok 452 write_valid.0.29
7264 18:37:05.453075 # ok 453 write_invalid.0.29
7265 18:37:05.456062 # ok 454 event_missing.0.29
7266 18:37:05.456152 # ok 455 event_spurious.0.29
7267 18:37:05.459349 # ok 456 get_value.0.28
7268 18:37:05.463034 # ok 457 name.0.28
7269 18:37:05.463124 # ok 458 write_default.0.28
7270 18:37:05.466045 # ok 459 write_valid.0.28
7271 18:37:05.469549 # ok 460 write_invalid.0.28
7272 18:37:05.473208 # ok 461 event_missing.0.28
7273 18:37:05.473299 # ok 462 event_spurious.0.28
7274 18:37:05.476010 # ok 463 get_value.0.27
7275 18:37:05.479773 # ok 464 name.0.27
7276 18:37:05.479864 # ok 465 write_default.0.27
7277 18:37:05.482652 # ok 466 write_valid.0.27
7278 18:37:05.486003 # ok 467 write_invalid.0.27
7279 18:37:05.489771 # ok 468 event_missing.0.27
7280 18:37:05.489870 # ok 469 event_spurious.0.27
7281 18:37:05.492671 # ok 470 get_value.0.26
7282 18:37:05.492779 # ok 471 name.0.26
7283 18:37:05.496008 # ok 472 write_default.0.26
7284 18:37:05.499325 # ok 473 write_valid.0.26
7285 18:37:05.502670 # ok 474 write_invalid.0.26
7286 18:37:05.502799 # ok 475 event_missing.0.26
7287 18:37:05.505888 # ok 476 event_spurious.0.26
7288 18:37:05.509113 # ok 477 get_value.0.25
7289 18:37:05.509203 # ok 478 name.0.25
7290 18:37:05.512679 # ok 479 write_default.0.25
7291 18:37:05.515682 # ok 480 write_valid.0.25
7292 18:37:05.519081 # ok 481 write_invalid.0.25
7293 18:37:05.519172 # ok 482 event_missing.0.25
7294 18:37:05.522660 # ok 483 event_spurious.0.25
7295 18:37:05.525674 # ok 484 get_value.0.24
7296 18:37:05.525765 # ok 485 name.0.24
7297 18:37:05.529043 # ok 486 write_default.0.24
7298 18:37:05.532055 # ok 487 write_valid.0.24
7299 18:37:05.535473 # ok 488 write_invalid.0.24
7300 18:37:05.535565 # ok 489 event_missing.0.24
7301 18:37:05.539468 # ok 490 event_spurious.0.24
7302 18:37:05.542587 # ok 491 get_value.0.23
7303 18:37:05.542678 # ok 492 name.0.23
7304 18:37:05.545554 # ok 493 write_default.0.23
7305 18:37:05.548641 # ok 494 write_valid.0.23
7306 18:37:05.551974 # ok 495 write_invalid.0.23
7307 18:37:05.552065 # ok 496 event_missing.0.23
7308 18:37:05.555339 # ok 497 event_spurious.0.23
7309 18:37:05.558801 # ok 498 get_value.0.22
7310 18:37:05.558892 # ok 499 name.0.22
7311 18:37:05.562290 # ok 500 write_default.0.22
7312 18:37:05.565708 # ok 501 write_valid.0.22
7313 18:37:05.569048 # ok 502 write_invalid.0.22
7314 18:37:05.569140 # ok 503 event_missing.0.22
7315 18:37:05.572014 # ok 504 event_spurious.0.22
7316 18:37:05.575208 # ok 505 get_value.0.21
7317 18:37:05.581827 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7318 18:37:05.581919 # not ok 506 name.0.21
7319 18:37:05.585295 # ok 507 write_default.0.21
7320 18:37:05.588501 # ok 508 write_valid.0.21
7321 18:37:05.591765 # ok 509 write_invalid.0.21
7322 18:37:05.591856 # ok 510 event_missing.0.21
7323 18:37:05.595070 # ok 511 event_spurious.0.21
7324 18:37:05.598416 # ok 512 get_value.0.20
7325 18:37:05.605119 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7326 18:37:05.605212 # not ok 513 name.0.20
7327 18:37:05.608596 # ok 514 write_default.0.20
7328 18:37:05.611619 # ok 515 write_valid.0.20
7329 18:37:05.615116 # ok 516 write_invalid.0.20
7330 18:37:05.615207 # ok 517 event_missing.0.20
7331 18:37:05.618744 # ok 518 event_spurious.0.20
7332 18:37:05.621653 # ok 519 get_value.0.19
7333 18:37:05.628415 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7334 18:37:05.628507 # not ok 520 name.0.19
7335 18:37:05.631533 # ok 521 write_default.0.19
7336 18:37:05.635256 # ok 522 write_valid.0.19
7337 18:37:05.638246 # ok 523 write_invalid.0.19
7338 18:37:05.638337 # ok 524 event_missing.0.19
7339 18:37:05.641719 # ok 525 event_spurious.0.19
7340 18:37:05.644699 # ok 526 get_value.0.18
7341 18:37:05.651605 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7342 18:37:05.651698 # not ok 527 name.0.18
7343 18:37:05.654694 # ok 528 write_default.0.18
7344 18:37:05.657948 # ok 529 write_valid.0.18
7345 18:37:05.658039 # ok 530 write_invalid.0.18
7346 18:37:05.661797 # ok 531 event_missing.0.18
7347 18:37:05.664671 # ok 532 event_spurious.0.18
7348 18:37:05.668238 # ok 533 get_value.0.17
7349 18:37:05.671283 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7350 18:37:05.674516 # not ok 534 name.0.17
7351 18:37:05.677753 # ok 535 write_default.0.17
7352 18:37:05.677844 # ok 536 write_valid.0.17
7353 18:37:05.681698 # ok 537 write_invalid.0.17
7354 18:37:05.684427 # ok 538 event_missing.0.17
7355 18:37:05.688012 # ok 539 event_spurious.0.17
7356 18:37:05.688103 # ok 540 get_value.0.16
7357 18:37:05.694556 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7358 18:37:05.697800 # not ok 541 name.0.16
7359 18:37:05.700986 # ok 542 write_default.0.16
7360 18:37:05.704821 # ok 543 write_valid.0.16
7361 18:37:05.704912 # ok 544 write_invalid.0.16
7362 18:37:05.707811 # ok 545 event_missing.0.16
7363 18:37:05.711965 # ok 546 event_spurious.0.16
7364 18:37:05.714612 # ok 547 get_value.0.15
7365 18:37:05.717826 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7366 18:37:05.721022 # not ok 548 name.0.15
7367 18:37:05.724746 # ok 549 write_default.0.15
7368 18:37:05.727752 # ok 550 write_valid.0.15
7369 18:37:05.727843 # ok 551 write_invalid.0.15
7370 18:37:05.730985 # ok 552 event_missing.0.15
7371 18:37:05.734589 # ok 553 event_spurious.0.15
7372 18:37:05.737539 # ok 554 get_value.0.14
7373 18:37:05.744833 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7374 18:37:05.745258 # not ok 555 name.0.14
7375 18:37:05.747971 # ok 556 write_default.0.14
7376 18:37:05.751678 # ok 557 write_valid.0.14
7377 18:37:05.752097 # ok 558 write_invalid.0.14
7378 18:37:05.754741 # ok 559 event_missing.0.14
7379 18:37:05.757760 # ok 560 event_spurious.0.14
7380 18:37:05.761104 # ok 561 get_value.0.13
7381 18:37:05.767755 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7382 18:37:05.768217 # not ok 562 name.0.13
7383 18:37:05.771133 # ok 563 write_default.0.13
7384 18:37:05.774322 # ok 564 write_valid.0.13
7385 18:37:05.777632 # ok 565 write_invalid.0.13
7386 18:37:05.778174 # ok 566 event_missing.0.13
7387 18:37:05.780804 # ok 567 event_spurious.0.13
7388 18:37:05.783928 # ok 568 get_value.0.12
7389 18:37:05.791197 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7390 18:37:05.791773 # not ok 569 name.0.12
7391 18:37:05.794381 # ok 570 write_default.0.12
7392 18:37:05.797641 # ok 571 write_valid.0.12
7393 18:37:05.800703 # ok 572 write_invalid.0.12
7394 18:37:05.801006 # ok 573 event_missing.0.12
7395 18:37:05.804048 # ok 574 event_spurious.0.12
7396 18:37:05.807029 # ok 575 get_value.0.11
7397 18:37:05.813923 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7398 18:37:05.814079 # not ok 576 name.0.11
7399 18:37:05.816965 # ok 577 write_default.0.11
7400 18:37:05.820293 # ok 578 write_valid.0.11
7401 18:37:05.823435 # ok 579 write_invalid.0.11
7402 18:37:05.826706 # ok 580 event_missing.0.11
7403 18:37:05.826848 # ok 581 event_spurious.0.11
7404 18:37:05.830215 # ok 582 get_value.0.10
7405 18:37:05.837146 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7406 18:37:05.840137 # not ok 583 name.0.10
7407 18:37:05.840244 # ok 584 write_default.0.10
7408 18:37:05.843956 # ok 585 write_valid.0.10
7409 18:37:05.846856 # ok 586 write_invalid.0.10
7410 18:37:05.850494 # ok 587 event_missing.0.10
7411 18:37:05.850602 # ok 588 event_spurious.0.10
7412 18:37:05.853365 # ok 589 get_value.0.9
7413 18:37:05.860043 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7414 18:37:05.860192 # not ok 590 name.0.9
7415 18:37:05.863235 # ok 591 write_default.0.9
7416 18:37:05.866919 # ok 592 write_valid.0.9
7417 18:37:05.870115 # ok 593 write_invalid.0.9
7418 18:37:05.870213 # ok 594 event_missing.0.9
7419 18:37:05.873883 # ok 595 event_spurious.0.9
7420 18:37:05.876867 # ok 596 get_value.0.8
7421 18:37:05.882968 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7422 18:37:05.883107 # not ok 597 name.0.8
7423 18:37:05.886661 # ok 598 write_default.0.8
7424 18:37:05.890052 # ok 599 write_valid.0.8
7425 18:37:05.893416 # ok 600 write_invalid.0.8
7426 18:37:05.893572 # ok 601 event_missing.0.8
7427 18:37:05.896827 # ok 602 event_spurious.0.8
7428 18:37:05.899982 # ok 603 get_value.0.7
7429 18:37:05.906859 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7430 18:37:05.906972 # not ok 604 name.0.7
7431 18:37:05.910429 # ok 605 write_default.0.7
7432 18:37:05.913897 # ok 606 write_valid.0.7
7433 18:37:05.914008 # ok 607 write_invalid.0.7
7434 18:37:05.917307 # ok 608 event_missing.0.7
7435 18:37:05.920521 # ok 609 event_spurious.0.7
7436 18:37:05.923350 # ok 610 get_value.0.6
7437 18:37:05.926686 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7438 18:37:05.930241 # not ok 611 name.0.6
7439 18:37:05.933664 # ok 612 write_default.0.6
7440 18:37:05.933872 # ok 613 write_valid.0.6
7441 18:37:05.936899 # ok 614 write_invalid.0.6
7442 18:37:05.939928 # ok 615 event_missing.0.6
7443 18:37:05.943334 # ok 616 event_spurious.0.6
7444 18:37:05.943531 # ok 617 get_value.0.5
7445 18:37:05.946600 # ok 618 name.0.5
7446 18:37:05.949966 # ok 619 write_default.0.5
7447 18:37:05.953023 # # No event generated for MTKAIF_DMIC
7448 18:37:05.956519 # # No event generated for MTKAIF_DMIC
7449 18:37:05.960319 # ok 620 write_valid.0.5
7450 18:37:05.960631 # ok 621 write_invalid.0.5
7451 18:37:05.963776 # not ok 622 event_missing.0.5
7452 18:37:05.966666 # ok 623 event_spurious.0.5
7453 18:37:05.970172 # ok 624 get_value.0.4
7454 18:37:05.970522 # ok 625 name.0.4
7455 18:37:05.973368 # ok 626 write_default.0.4
7456 18:37:05.976950 # # No event generated for I2S5_HD_Mux
7457 18:37:05.979927 # # No event generated for I2S5_HD_Mux
7458 18:37:05.983073 # ok 627 write_valid.0.4
7459 18:37:05.986511 # ok 628 write_invalid.0.4
7460 18:37:05.986856 # not ok 629 event_missing.0.4
7461 18:37:05.990173 # ok 630 event_spurious.0.4
7462 18:37:05.993757 # ok 631 get_value.0.3
7463 18:37:05.994072 # ok 632 name.0.3
7464 18:37:05.996496 # ok 633 write_default.0.3
7465 18:37:06.000021 # # No event generated for I2S3_HD_Mux
7466 18:37:06.003304 # # No event generated for I2S3_HD_Mux
7467 18:37:06.006282 # ok 634 write_valid.0.3
7468 18:37:06.010060 # ok 635 write_invalid.0.3
7469 18:37:06.010509 # not ok 636 event_missing.0.3
7470 18:37:06.012790 # ok 637 event_spurious.0.3
7471 18:37:06.016480 # ok 638 get_value.0.2
7472 18:37:06.017002 # ok 639 name.0.2
7473 18:37:06.019985 # ok 640 write_default.0.2
7474 18:37:06.022914 # # No event generated for I2S2_HD_Mux
7475 18:37:06.026575 # # No event generated for I2S2_HD_Mux
7476 18:37:06.029489 # ok 641 write_valid.0.2
7477 18:37:06.032868 # ok 642 write_invalid.0.2
7478 18:37:06.033194 # not ok 643 event_missing.0.2
7479 18:37:06.036342 # ok 644 event_spurious.0.2
7480 18:37:06.039637 # ok 645 get_value.0.1
7481 18:37:06.039958 # ok 646 name.0.1
7482 18:37:06.043015 # ok 647 write_default.0.1
7483 18:37:06.046706 # # No event generated for I2S1_HD_Mux
7484 18:37:06.049678 # # No event generated for I2S1_HD_Mux
7485 18:37:06.053054 # ok 648 write_valid.0.1
7486 18:37:06.056480 # ok 649 write_invalid.0.1
7487 18:37:06.056805 # not ok 650 event_missing.0.1
7488 18:37:06.059319 # ok 651 event_spurious.0.1
7489 18:37:06.062730 # ok 652 get_value.0.0
7490 18:37:06.062822 # ok 653 name.0.0
7491 18:37:06.066065 # ok 654 write_default.0.0
7492 18:37:06.069425 # # No event generated for I2S0_HD_Mux
7493 18:37:06.072325 # # No event generated for I2S0_HD_Mux
7494 18:37:06.076121 # ok 655 write_valid.0.0
7495 18:37:06.079354 # ok 656 write_invalid.0.0
7496 18:37:06.082783 # not ok 657 event_missing.0.0
7497 18:37:06.082881 # ok 658 event_spurious.0.0
7498 18:37:06.089109 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7499 18:37:06.092573 ok 1 selftests: alsa: mixer-test
7500 18:37:07.746580 alsa_mixer-test_get_value_0_93 pass
7501 18:37:07.749567 alsa_mixer-test_name_0_93 pass
7502 18:37:07.752855 alsa_mixer-test_write_default_0_93 pass
7503 18:37:07.756298 alsa_mixer-test_write_valid_0_93 pass
7504 18:37:07.759853 alsa_mixer-test_write_invalid_0_93 pass
7505 18:37:07.766236 alsa_mixer-test_event_missing_0_93 pass
7506 18:37:07.769928 alsa_mixer-test_event_spurious_0_93 pass
7507 18:37:07.773031 alsa_mixer-test_get_value_0_92 pass
7508 18:37:07.776843 alsa_mixer-test_name_0_92 pass
7509 18:37:07.779803 alsa_mixer-test_write_default_0_92 pass
7510 18:37:07.783292 alsa_mixer-test_write_valid_0_92 pass
7511 18:37:07.786401 alsa_mixer-test_write_invalid_0_92 pass
7512 18:37:07.789336 alsa_mixer-test_event_missing_0_92 pass
7513 18:37:07.793106 alsa_mixer-test_event_spurious_0_92 pass
7514 18:37:07.795976 alsa_mixer-test_get_value_0_91 pass
7515 18:37:07.799489 alsa_mixer-test_name_0_91 pass
7516 18:37:07.803068 alsa_mixer-test_write_default_0_91 pass
7517 18:37:07.806409 alsa_mixer-test_write_valid_0_91 pass
7518 18:37:07.809786 alsa_mixer-test_write_invalid_0_91 pass
7519 18:37:07.812944 alsa_mixer-test_event_missing_0_91 pass
7520 18:37:07.816716 alsa_mixer-test_event_spurious_0_91 pass
7521 18:37:07.820009 alsa_mixer-test_get_value_0_90 pass
7522 18:37:07.823072 alsa_mixer-test_name_0_90 pass
7523 18:37:07.826505 alsa_mixer-test_write_default_0_90 pass
7524 18:37:07.830458 alsa_mixer-test_write_valid_0_90 pass
7525 18:37:07.833063 alsa_mixer-test_write_invalid_0_90 pass
7526 18:37:07.836781 alsa_mixer-test_event_missing_0_90 pass
7527 18:37:07.839436 alsa_mixer-test_event_spurious_0_90 pass
7528 18:37:07.843561 alsa_mixer-test_get_value_0_89 pass
7529 18:37:07.847105 alsa_mixer-test_name_0_89 pass
7530 18:37:07.849807 alsa_mixer-test_write_default_0_89 pass
7531 18:37:07.853681 alsa_mixer-test_write_valid_0_89 pass
7532 18:37:07.856121 alsa_mixer-test_write_invalid_0_89 pass
7533 18:37:07.859739 alsa_mixer-test_event_missing_0_89 pass
7534 18:37:07.862911 alsa_mixer-test_event_spurious_0_89 pass
7535 18:37:07.866311 alsa_mixer-test_get_value_0_88 pass
7536 18:37:07.869422 alsa_mixer-test_name_0_88 pass
7537 18:37:07.873212 alsa_mixer-test_write_default_0_88 pass
7538 18:37:07.879283 alsa_mixer-test_write_valid_0_88 fail
7539 18:37:07.882970 alsa_mixer-test_write_invalid_0_88 pass
7540 18:37:07.886074 alsa_mixer-test_event_missing_0_88 pass
7541 18:37:07.889309 alsa_mixer-test_event_spurious_0_88 fail
7542 18:37:07.892264 alsa_mixer-test_get_value_0_87 pass
7543 18:37:07.895978 alsa_mixer-test_name_0_87 pass
7544 18:37:07.899227 alsa_mixer-test_write_default_0_87 pass
7545 18:37:07.902444 alsa_mixer-test_write_valid_0_87 pass
7546 18:37:07.905993 alsa_mixer-test_write_invalid_0_87 pass
7547 18:37:07.909405 alsa_mixer-test_event_missing_0_87 pass
7548 18:37:07.912553 alsa_mixer-test_event_spurious_0_87 pass
7549 18:37:07.915796 alsa_mixer-test_get_value_0_86 pass
7550 18:37:07.919526 alsa_mixer-test_name_0_86 pass
7551 18:37:07.922397 alsa_mixer-test_write_default_0_86 pass
7552 18:37:07.925925 alsa_mixer-test_write_valid_0_86 fail
7553 18:37:07.929247 alsa_mixer-test_write_invalid_0_86 pass
7554 18:37:07.935895 alsa_mixer-test_event_missing_0_86 pass
7555 18:37:07.939261 alsa_mixer-test_event_spurious_0_86 pass
7556 18:37:07.943212 alsa_mixer-test_get_value_0_85 pass
7557 18:37:07.946291 alsa_mixer-test_name_0_85 pass
7558 18:37:07.949465 alsa_mixer-test_write_default_0_85 pass
7559 18:37:07.953137 alsa_mixer-test_write_valid_0_85 fail
7560 18:37:07.955981 alsa_mixer-test_write_invalid_0_85 pass
7561 18:37:07.959678 alsa_mixer-test_event_missing_0_85 pass
7562 18:37:07.962383 alsa_mixer-test_event_spurious_0_85 pass
7563 18:37:07.965711 alsa_mixer-test_get_value_0_84 pass
7564 18:37:07.969624 alsa_mixer-test_name_0_84 pass
7565 18:37:07.973176 alsa_mixer-test_write_default_0_84 pass
7566 18:37:07.976074 alsa_mixer-test_write_valid_0_84 pass
7567 18:37:07.979657 alsa_mixer-test_write_invalid_0_84 pass
7568 18:37:07.982630 alsa_mixer-test_event_missing_0_84 pass
7569 18:37:07.986034 alsa_mixer-test_event_spurious_0_84 pass
7570 18:37:07.989398 alsa_mixer-test_get_value_0_83 pass
7571 18:37:07.992416 alsa_mixer-test_name_0_83 pass
7572 18:37:07.996370 alsa_mixer-test_write_default_0_83 pass
7573 18:37:08.002545 alsa_mixer-test_write_valid_0_83 pass
7574 18:37:08.005442 alsa_mixer-test_write_invalid_0_83 pass
7575 18:37:08.009216 alsa_mixer-test_event_missing_0_83 pass
7576 18:37:08.012302 alsa_mixer-test_event_spurious_0_83 pass
7577 18:37:08.015460 alsa_mixer-test_get_value_0_82 pass
7578 18:37:08.018762 alsa_mixer-test_name_0_82 pass
7579 18:37:08.022008 alsa_mixer-test_write_default_0_82 skip
7580 18:37:08.025306 alsa_mixer-test_write_valid_0_82 skip
7581 18:37:08.028506 alsa_mixer-test_write_invalid_0_82 skip
7582 18:37:08.032312 alsa_mixer-test_event_missing_0_82 pass
7583 18:37:08.035324 alsa_mixer-test_event_spurious_0_82 pass
7584 18:37:08.038553 alsa_mixer-test_get_value_0_81 pass
7585 18:37:08.041744 alsa_mixer-test_name_0_81 pass
7586 18:37:08.045256 alsa_mixer-test_write_default_0_81 pass
7587 18:37:08.049074 alsa_mixer-test_write_valid_0_81 pass
7588 18:37:08.055230 alsa_mixer-test_write_invalid_0_81 fail
7589 18:37:08.059238 alsa_mixer-test_event_missing_0_81 fail
7590 18:37:08.061952 alsa_mixer-test_event_spurious_0_81 pass
7591 18:37:08.065323 alsa_mixer-test_get_value_0_80 pass
7592 18:37:08.069329 alsa_mixer-test_name_0_80 pass
7593 18:37:08.071733 alsa_mixer-test_write_default_0_80 pass
7594 18:37:08.075179 alsa_mixer-test_write_valid_0_80 pass
7595 18:37:08.078930 alsa_mixer-test_write_invalid_0_80 pass
7596 18:37:08.082176 alsa_mixer-test_event_missing_0_80 pass
7597 18:37:08.085322 alsa_mixer-test_event_spurious_0_80 pass
7598 18:37:08.088518 alsa_mixer-test_get_value_0_79 fail
7599 18:37:08.092119 alsa_mixer-test_name_0_79 pass
7600 18:37:08.095141 alsa_mixer-test_write_default_0_79 fail
7601 18:37:08.098123 alsa_mixer-test_write_valid_0_79 fail
7602 18:37:08.102395 alsa_mixer-test_write_invalid_0_79 fail
7603 18:37:08.104715 alsa_mixer-test_event_missing_0_79 pass
7604 18:37:08.111391 alsa_mixer-test_event_spurious_0_79 pass
7605 18:37:08.115277 alsa_mixer-test_get_value_0_78 fail
7606 18:37:08.115932 alsa_mixer-test_name_0_78 pass
7607 18:37:08.121992 alsa_mixer-test_write_default_0_78 fail
7608 18:37:08.125002 alsa_mixer-test_write_valid_0_78 fail
7609 18:37:08.128172 alsa_mixer-test_write_invalid_0_78 fail
7610 18:37:08.131601 alsa_mixer-test_event_missing_0_78 pass
7611 18:37:08.135064 alsa_mixer-test_event_spurious_0_78 pass
7612 18:37:08.138697 alsa_mixer-test_get_value_0_77 fail
7613 18:37:08.141381 alsa_mixer-test_name_0_77 pass
7614 18:37:08.144703 alsa_mixer-test_write_default_0_77 fail
7615 18:37:08.148126 alsa_mixer-test_write_valid_0_77 fail
7616 18:37:08.151605 alsa_mixer-test_write_invalid_0_77 fail
7617 18:37:08.154909 alsa_mixer-test_event_missing_0_77 pass
7618 18:37:08.158368 alsa_mixer-test_event_spurious_0_77 pass
7619 18:37:08.161643 alsa_mixer-test_get_value_0_76 pass
7620 18:37:08.164800 alsa_mixer-test_name_0_76 fail
7621 18:37:08.168191 alsa_mixer-test_write_default_0_76 pass
7622 18:37:08.171512 alsa_mixer-test_write_valid_0_76 pass
7623 18:37:08.178474 alsa_mixer-test_write_invalid_0_76 pass
7624 18:37:08.181513 alsa_mixer-test_event_missing_0_76 pass
7625 18:37:08.184146 alsa_mixer-test_event_spurious_0_76 pass
7626 18:37:08.188086 alsa_mixer-test_get_value_0_75 pass
7627 18:37:08.191771 alsa_mixer-test_name_0_75 fail
7628 18:37:08.194015 alsa_mixer-test_write_default_0_75 pass
7629 18:37:08.198012 alsa_mixer-test_write_valid_0_75 pass
7630 18:37:08.201076 alsa_mixer-test_write_invalid_0_75 pass
7631 18:37:08.204083 alsa_mixer-test_event_missing_0_75 pass
7632 18:37:08.207852 alsa_mixer-test_event_spurious_0_75 pass
7633 18:37:08.210591 alsa_mixer-test_get_value_0_74 pass
7634 18:37:08.214199 alsa_mixer-test_name_0_74 fail
7635 18:37:08.217711 alsa_mixer-test_write_default_0_74 pass
7636 18:37:08.220519 alsa_mixer-test_write_valid_0_74 pass
7637 18:37:08.223938 alsa_mixer-test_write_invalid_0_74 pass
7638 18:37:08.230637 alsa_mixer-test_event_missing_0_74 pass
7639 18:37:08.233653 alsa_mixer-test_event_spurious_0_74 pass
7640 18:37:08.237255 alsa_mixer-test_get_value_0_73 pass
7641 18:37:08.240991 alsa_mixer-test_name_0_73 fail
7642 18:37:08.243581 alsa_mixer-test_write_default_0_73 pass
7643 18:37:08.247269 alsa_mixer-test_write_valid_0_73 pass
7644 18:37:08.250476 alsa_mixer-test_write_invalid_0_73 pass
7645 18:37:08.253556 alsa_mixer-test_event_missing_0_73 pass
7646 18:37:08.257574 alsa_mixer-test_event_spurious_0_73 pass
7647 18:37:08.260765 alsa_mixer-test_get_value_0_72 pass
7648 18:37:08.263786 alsa_mixer-test_name_0_72 fail
7649 18:37:08.267085 alsa_mixer-test_write_default_0_72 pass
7650 18:37:08.270525 alsa_mixer-test_write_valid_0_72 pass
7651 18:37:08.274003 alsa_mixer-test_write_invalid_0_72 pass
7652 18:37:08.277113 alsa_mixer-test_event_missing_0_72 pass
7653 18:37:08.280534 alsa_mixer-test_event_spurious_0_72 pass
7654 18:37:08.283805 alsa_mixer-test_get_value_0_71 pass
7655 18:37:08.287128 alsa_mixer-test_name_0_71 fail
7656 18:37:08.290900 alsa_mixer-test_write_default_0_71 pass
7657 18:37:08.293735 alsa_mixer-test_write_valid_0_71 pass
7658 18:37:08.297079 alsa_mixer-test_write_invalid_0_71 pass
7659 18:37:08.303716 alsa_mixer-test_event_missing_0_71 pass
7660 18:37:08.307010 alsa_mixer-test_event_spurious_0_71 pass
7661 18:37:08.310048 alsa_mixer-test_get_value_0_70 pass
7662 18:37:08.310477 alsa_mixer-test_name_0_70 fail
7663 18:37:08.316731 alsa_mixer-test_write_default_0_70 pass
7664 18:37:08.319862 alsa_mixer-test_write_valid_0_70 pass
7665 18:37:08.323518 alsa_mixer-test_write_invalid_0_70 pass
7666 18:37:08.327027 alsa_mixer-test_event_missing_0_70 pass
7667 18:37:08.330618 alsa_mixer-test_event_spurious_0_70 pass
7668 18:37:08.333765 alsa_mixer-test_get_value_0_69 pass
7669 18:37:08.337089 alsa_mixer-test_name_0_69 fail
7670 18:37:08.340123 alsa_mixer-test_write_default_0_69 pass
7671 18:37:08.343953 alsa_mixer-test_write_valid_0_69 pass
7672 18:37:08.346696 alsa_mixer-test_write_invalid_0_69 pass
7673 18:37:08.350283 alsa_mixer-test_event_missing_0_69 pass
7674 18:37:08.356942 alsa_mixer-test_event_spurious_0_69 pass
7675 18:37:08.360384 alsa_mixer-test_get_value_0_68 pass
7676 18:37:08.363151 alsa_mixer-test_name_0_68 fail
7677 18:37:08.366642 alsa_mixer-test_write_default_0_68 pass
7678 18:37:08.370108 alsa_mixer-test_write_valid_0_68 pass
7679 18:37:08.373308 alsa_mixer-test_write_invalid_0_68 pass
7680 18:37:08.376670 alsa_mixer-test_event_missing_0_68 pass
7681 18:37:08.383327 alsa_mixer-test_event_spurious_0_68 pass
7682 18:37:08.386442 alsa_mixer-test_get_value_0_67 pass
7683 18:37:08.386965 alsa_mixer-test_name_0_67 fail
7684 18:37:08.393363 alsa_mixer-test_write_default_0_67 pass
7685 18:37:08.396461 alsa_mixer-test_write_valid_0_67 pass
7686 18:37:08.400118 alsa_mixer-test_write_invalid_0_67 pass
7687 18:37:08.402740 alsa_mixer-test_event_missing_0_67 pass
7688 18:37:08.406452 alsa_mixer-test_event_spurious_0_67 pass
7689 18:37:08.410053 alsa_mixer-test_get_value_0_66 pass
7690 18:37:08.413303 alsa_mixer-test_name_0_66 fail
7691 18:37:08.416384 alsa_mixer-test_write_default_0_66 pass
7692 18:37:08.422939 alsa_mixer-test_write_valid_0_66 pass
7693 18:37:08.425936 alsa_mixer-test_write_invalid_0_66 pass
7694 18:37:08.429169 alsa_mixer-test_event_missing_0_66 pass
7695 18:37:08.432949 alsa_mixer-test_event_spurious_0_66 pass
7696 18:37:08.436262 alsa_mixer-test_get_value_0_65 pass
7697 18:37:08.439145 alsa_mixer-test_name_0_65 fail
7698 18:37:08.442424 alsa_mixer-test_write_default_0_65 pass
7699 18:37:08.446430 alsa_mixer-test_write_valid_0_65 pass
7700 18:37:08.453066 alsa_mixer-test_write_invalid_0_65 pass
7701 18:37:08.455787 alsa_mixer-test_event_missing_0_65 pass
7702 18:37:08.459242 alsa_mixer-test_event_spurious_0_65 pass
7703 18:37:08.462728 alsa_mixer-test_get_value_0_64 pass
7704 18:37:08.466112 alsa_mixer-test_name_0_64 fail
7705 18:37:08.469237 alsa_mixer-test_write_default_0_64 pass
7706 18:37:08.472461 alsa_mixer-test_write_valid_0_64 pass
7707 18:37:08.475699 alsa_mixer-test_write_invalid_0_64 pass
7708 18:37:08.482503 alsa_mixer-test_event_missing_0_64 pass
7709 18:37:08.485634 alsa_mixer-test_event_spurious_0_64 pass
7710 18:37:08.488389 alsa_mixer-test_get_value_0_63 pass
7711 18:37:08.492298 alsa_mixer-test_name_0_63 fail
7712 18:37:08.495328 alsa_mixer-test_write_default_0_63 pass
7713 18:37:08.499239 alsa_mixer-test_write_valid_0_63 pass
7714 18:37:08.502057 alsa_mixer-test_write_invalid_0_63 pass
7715 18:37:08.508723 alsa_mixer-test_event_missing_0_63 pass
7716 18:37:08.511537 alsa_mixer-test_event_spurious_0_63 pass
7717 18:37:08.514918 alsa_mixer-test_get_value_0_62 pass
7718 18:37:08.518506 alsa_mixer-test_name_0_62 fail
7719 18:37:08.522076 alsa_mixer-test_write_default_0_62 pass
7720 18:37:08.525138 alsa_mixer-test_write_valid_0_62 pass
7721 18:37:08.528663 alsa_mixer-test_write_invalid_0_62 pass
7722 18:37:08.531578 alsa_mixer-test_event_missing_0_62 pass
7723 18:37:08.538552 alsa_mixer-test_event_spurious_0_62 pass
7724 18:37:08.541781 alsa_mixer-test_get_value_0_61 pass
7725 18:37:08.544518 alsa_mixer-test_name_0_61 fail
7726 18:37:08.548610 alsa_mixer-test_write_default_0_61 pass
7727 18:37:08.551551 alsa_mixer-test_write_valid_0_61 pass
7728 18:37:08.554847 alsa_mixer-test_write_invalid_0_61 pass
7729 18:37:08.557957 alsa_mixer-test_event_missing_0_61 pass
7730 18:37:08.561465 alsa_mixer-test_event_spurious_0_61 pass
7731 18:37:08.564551 alsa_mixer-test_get_value_0_60 pass
7732 18:37:08.567902 alsa_mixer-test_name_0_60 fail
7733 18:37:08.571111 alsa_mixer-test_write_default_0_60 pass
7734 18:37:08.575056 alsa_mixer-test_write_valid_0_60 pass
7735 18:37:08.578585 alsa_mixer-test_write_invalid_0_60 pass
7736 18:37:08.581774 alsa_mixer-test_event_missing_0_60 pass
7737 18:37:08.584955 alsa_mixer-test_event_spurious_0_60 pass
7738 18:37:08.588068 alsa_mixer-test_get_value_0_59 pass
7739 18:37:08.591400 alsa_mixer-test_name_0_59 fail
7740 18:37:08.595068 alsa_mixer-test_write_default_0_59 pass
7741 18:37:08.598691 alsa_mixer-test_write_valid_0_59 pass
7742 18:37:08.604958 alsa_mixer-test_write_invalid_0_59 pass
7743 18:37:08.608335 alsa_mixer-test_event_missing_0_59 pass
7744 18:37:08.611128 alsa_mixer-test_event_spurious_0_59 pass
7745 18:37:08.614755 alsa_mixer-test_get_value_0_58 pass
7746 18:37:08.617851 alsa_mixer-test_name_0_58 fail
7747 18:37:08.621807 alsa_mixer-test_write_default_0_58 pass
7748 18:37:08.624441 alsa_mixer-test_write_valid_0_58 pass
7749 18:37:08.627688 alsa_mixer-test_write_invalid_0_58 pass
7750 18:37:08.631774 alsa_mixer-test_event_missing_0_58 pass
7751 18:37:08.638227 alsa_mixer-test_event_spurious_0_58 pass
7752 18:37:08.641591 alsa_mixer-test_get_value_0_57 pass
7753 18:37:08.644747 alsa_mixer-test_name_0_57 fail
7754 18:37:08.648400 alsa_mixer-test_write_default_0_57 pass
7755 18:37:08.651442 alsa_mixer-test_write_valid_0_57 pass
7756 18:37:08.654811 alsa_mixer-test_write_invalid_0_57 pass
7757 18:37:08.657646 alsa_mixer-test_event_missing_0_57 pass
7758 18:37:08.664482 alsa_mixer-test_event_spurious_0_57 pass
7759 18:37:08.667376 alsa_mixer-test_get_value_0_56 pass
7760 18:37:08.671266 alsa_mixer-test_name_0_56 fail
7761 18:37:08.674496 alsa_mixer-test_write_default_0_56 pass
7762 18:37:08.677977 alsa_mixer-test_write_valid_0_56 pass
7763 18:37:08.681002 alsa_mixer-test_write_invalid_0_56 pass
7764 18:37:08.684369 alsa_mixer-test_event_missing_0_56 pass
7765 18:37:08.687326 alsa_mixer-test_event_spurious_0_56 pass
7766 18:37:08.691115 alsa_mixer-test_get_value_0_55 pass
7767 18:37:08.694235 alsa_mixer-test_name_0_55 fail
7768 18:37:08.700402 alsa_mixer-test_write_default_0_55 pass
7769 18:37:08.704320 alsa_mixer-test_write_valid_0_55 pass
7770 18:37:08.707612 alsa_mixer-test_write_invalid_0_55 pass
7771 18:37:08.710097 alsa_mixer-test_event_missing_0_55 pass
7772 18:37:08.713507 alsa_mixer-test_event_spurious_0_55 pass
7773 18:37:08.717456 alsa_mixer-test_get_value_0_54 pass
7774 18:37:08.720429 alsa_mixer-test_name_0_54 fail
7775 18:37:08.723526 alsa_mixer-test_write_default_0_54 pass
7776 18:37:08.730315 alsa_mixer-test_write_valid_0_54 pass
7777 18:37:08.733568 alsa_mixer-test_write_invalid_0_54 pass
7778 18:37:08.736837 alsa_mixer-test_event_missing_0_54 pass
7779 18:37:08.740076 alsa_mixer-test_event_spurious_0_54 pass
7780 18:37:08.743295 alsa_mixer-test_get_value_0_53 pass
7781 18:37:08.746462 alsa_mixer-test_name_0_53 fail
7782 18:37:08.749854 alsa_mixer-test_write_default_0_53 pass
7783 18:37:08.753048 alsa_mixer-test_write_valid_0_53 pass
7784 18:37:08.760030 alsa_mixer-test_write_invalid_0_53 pass
7785 18:37:08.763354 alsa_mixer-test_event_missing_0_53 pass
7786 18:37:08.766251 alsa_mixer-test_event_spurious_0_53 pass
7787 18:37:08.770212 alsa_mixer-test_get_value_0_52 pass
7788 18:37:08.773685 alsa_mixer-test_name_0_52 fail
7789 18:37:08.776164 alsa_mixer-test_write_default_0_52 pass
7790 18:37:08.780009 alsa_mixer-test_write_valid_0_52 pass
7791 18:37:08.783380 alsa_mixer-test_write_invalid_0_52 pass
7792 18:37:08.786546 alsa_mixer-test_event_missing_0_52 pass
7793 18:37:08.789983 alsa_mixer-test_event_spurious_0_52 pass
7794 18:37:08.793530 alsa_mixer-test_get_value_0_51 pass
7795 18:37:08.796155 alsa_mixer-test_name_0_51 fail
7796 18:37:08.799871 alsa_mixer-test_write_default_0_51 pass
7797 18:37:08.802908 alsa_mixer-test_write_valid_0_51 pass
7798 18:37:08.805946 alsa_mixer-test_write_invalid_0_51 pass
7799 18:37:08.809563 alsa_mixer-test_event_missing_0_51 pass
7800 18:37:08.816074 alsa_mixer-test_event_spurious_0_51 pass
7801 18:37:08.819278 alsa_mixer-test_get_value_0_50 pass
7802 18:37:08.819730 alsa_mixer-test_name_0_50 fail
7803 18:37:08.826287 alsa_mixer-test_write_default_0_50 pass
7804 18:37:08.829683 alsa_mixer-test_write_valid_0_50 pass
7805 18:37:08.832557 alsa_mixer-test_write_invalid_0_50 pass
7806 18:37:08.836061 alsa_mixer-test_event_missing_0_50 pass
7807 18:37:08.840195 alsa_mixer-test_event_spurious_0_50 pass
7808 18:37:08.842728 alsa_mixer-test_get_value_0_49 pass
7809 18:37:08.845953 alsa_mixer-test_name_0_49 fail
7810 18:37:08.849967 alsa_mixer-test_write_default_0_49 pass
7811 18:37:08.852826 alsa_mixer-test_write_valid_0_49 pass
7812 18:37:08.855781 alsa_mixer-test_write_invalid_0_49 pass
7813 18:37:08.859604 alsa_mixer-test_event_missing_0_49 pass
7814 18:37:08.863033 alsa_mixer-test_event_spurious_0_49 pass
7815 18:37:08.866067 alsa_mixer-test_get_value_0_48 pass
7816 18:37:08.869089 alsa_mixer-test_name_0_48 fail
7817 18:37:08.872623 alsa_mixer-test_write_default_0_48 pass
7818 18:37:08.876004 alsa_mixer-test_write_valid_0_48 pass
7819 18:37:08.882964 alsa_mixer-test_write_invalid_0_48 pass
7820 18:37:08.885757 alsa_mixer-test_event_missing_0_48 pass
7821 18:37:08.889239 alsa_mixer-test_event_spurious_0_48 pass
7822 18:37:08.891974 alsa_mixer-test_get_value_0_47 pass
7823 18:37:08.895363 alsa_mixer-test_name_0_47 fail
7824 18:37:08.899353 alsa_mixer-test_write_default_0_47 pass
7825 18:37:08.902811 alsa_mixer-test_write_valid_0_47 pass
7826 18:37:08.905985 alsa_mixer-test_write_invalid_0_47 pass
7827 18:37:08.909439 alsa_mixer-test_event_missing_0_47 pass
7828 18:37:08.912367 alsa_mixer-test_event_spurious_0_47 pass
7829 18:37:08.915998 alsa_mixer-test_get_value_0_46 pass
7830 18:37:08.918839 alsa_mixer-test_name_0_46 fail
7831 18:37:08.922248 alsa_mixer-test_write_default_0_46 pass
7832 18:37:08.925449 alsa_mixer-test_write_valid_0_46 pass
7833 18:37:08.928957 alsa_mixer-test_write_invalid_0_46 pass
7834 18:37:08.932287 alsa_mixer-test_event_missing_0_46 pass
7835 18:37:08.938952 alsa_mixer-test_event_spurious_0_46 pass
7836 18:37:08.941989 alsa_mixer-test_get_value_0_45 pass
7837 18:37:08.942431 alsa_mixer-test_name_0_45 fail
7838 18:37:08.948316 alsa_mixer-test_write_default_0_45 pass
7839 18:37:08.951784 alsa_mixer-test_write_valid_0_45 pass
7840 18:37:08.955334 alsa_mixer-test_write_invalid_0_45 pass
7841 18:37:08.958247 alsa_mixer-test_event_missing_0_45 pass
7842 18:37:08.961841 alsa_mixer-test_event_spurious_0_45 pass
7843 18:37:08.965287 alsa_mixer-test_get_value_0_44 pass
7844 18:37:08.968018 alsa_mixer-test_name_0_44 fail
7845 18:37:08.971677 alsa_mixer-test_write_default_0_44 pass
7846 18:37:08.975129 alsa_mixer-test_write_valid_0_44 pass
7847 18:37:08.978172 alsa_mixer-test_write_invalid_0_44 pass
7848 18:37:08.981609 alsa_mixer-test_event_missing_0_44 pass
7849 18:37:08.984604 alsa_mixer-test_event_spurious_0_44 pass
7850 18:37:08.988262 alsa_mixer-test_get_value_0_43 pass
7851 18:37:08.992123 alsa_mixer-test_name_0_43 fail
7852 18:37:08.994510 alsa_mixer-test_write_default_0_43 pass
7853 18:37:08.998032 alsa_mixer-test_write_valid_0_43 pass
7854 18:37:09.004591 alsa_mixer-test_write_invalid_0_43 pass
7855 18:37:09.008165 alsa_mixer-test_event_missing_0_43 pass
7856 18:37:09.011695 alsa_mixer-test_event_spurious_0_43 pass
7857 18:37:09.014643 alsa_mixer-test_get_value_0_42 pass
7858 18:37:09.018134 alsa_mixer-test_name_0_42 fail
7859 18:37:09.021203 alsa_mixer-test_write_default_0_42 pass
7860 18:37:09.024956 alsa_mixer-test_write_valid_0_42 pass
7861 18:37:09.027877 alsa_mixer-test_write_invalid_0_42 pass
7862 18:37:09.031166 alsa_mixer-test_event_missing_0_42 pass
7863 18:37:09.034749 alsa_mixer-test_event_spurious_0_42 pass
7864 18:37:09.038180 alsa_mixer-test_get_value_0_41 pass
7865 18:37:09.041461 alsa_mixer-test_name_0_41 fail
7866 18:37:09.048315 alsa_mixer-test_write_default_0_41 pass
7867 18:37:09.051857 alsa_mixer-test_write_valid_0_41 pass
7868 18:37:09.054344 alsa_mixer-test_write_invalid_0_41 pass
7869 18:37:09.058098 alsa_mixer-test_event_missing_0_41 pass
7870 18:37:09.061461 alsa_mixer-test_event_spurious_0_41 pass
7871 18:37:09.064964 alsa_mixer-test_get_value_0_40 pass
7872 18:37:09.067922 alsa_mixer-test_name_0_40 fail
7873 18:37:09.071121 alsa_mixer-test_write_default_0_40 pass
7874 18:37:09.074716 alsa_mixer-test_write_valid_0_40 pass
7875 18:37:09.081172 alsa_mixer-test_write_invalid_0_40 pass
7876 18:37:09.084421 alsa_mixer-test_event_missing_0_40 pass
7877 18:37:09.087780 alsa_mixer-test_event_spurious_0_40 pass
7878 18:37:09.091306 alsa_mixer-test_get_value_0_39 pass
7879 18:37:09.094692 alsa_mixer-test_name_0_39 fail
7880 18:37:09.098076 alsa_mixer-test_write_default_0_39 pass
7881 18:37:09.100961 alsa_mixer-test_write_valid_0_39 pass
7882 18:37:09.107524 alsa_mixer-test_write_invalid_0_39 pass
7883 18:37:09.110634 alsa_mixer-test_event_missing_0_39 pass
7884 18:37:09.113879 alsa_mixer-test_event_spurious_0_39 pass
7885 18:37:09.117174 alsa_mixer-test_get_value_0_38 pass
7886 18:37:09.120394 alsa_mixer-test_name_0_38 fail
7887 18:37:09.124053 alsa_mixer-test_write_default_0_38 pass
7888 18:37:09.127358 alsa_mixer-test_write_valid_0_38 pass
7889 18:37:09.130654 alsa_mixer-test_write_invalid_0_38 pass
7890 18:37:09.134514 alsa_mixer-test_event_missing_0_38 pass
7891 18:37:09.137442 alsa_mixer-test_event_spurious_0_38 pass
7892 18:37:09.140935 alsa_mixer-test_get_value_0_37 pass
7893 18:37:09.143945 alsa_mixer-test_name_0_37 fail
7894 18:37:09.147273 alsa_mixer-test_write_default_0_37 pass
7895 18:37:09.150950 alsa_mixer-test_write_valid_0_37 pass
7896 18:37:09.154184 alsa_mixer-test_write_invalid_0_37 pass
7897 18:37:09.157291 alsa_mixer-test_event_missing_0_37 pass
7898 18:37:09.161166 alsa_mixer-test_event_spurious_0_37 pass
7899 18:37:09.164007 alsa_mixer-test_get_value_0_36 pass
7900 18:37:09.167460 alsa_mixer-test_name_0_36 fail
7901 18:37:09.170804 alsa_mixer-test_write_default_0_36 pass
7902 18:37:09.174314 alsa_mixer-test_write_valid_0_36 pass
7903 18:37:09.177896 alsa_mixer-test_write_invalid_0_36 pass
7904 18:37:09.180825 alsa_mixer-test_event_missing_0_36 pass
7905 18:37:09.184174 alsa_mixer-test_event_spurious_0_36 pass
7906 18:37:09.187236 alsa_mixer-test_get_value_0_35 pass
7907 18:37:09.190430 alsa_mixer-test_name_0_35 fail
7908 18:37:09.193887 alsa_mixer-test_write_default_0_35 pass
7909 18:37:09.200817 alsa_mixer-test_write_valid_0_35 pass
7910 18:37:09.204063 alsa_mixer-test_write_invalid_0_35 pass
7911 18:37:09.207323 alsa_mixer-test_event_missing_0_35 pass
7912 18:37:09.210555 alsa_mixer-test_event_spurious_0_35 pass
7913 18:37:09.214030 alsa_mixer-test_get_value_0_34 pass
7914 18:37:09.217028 alsa_mixer-test_name_0_34 fail
7915 18:37:09.220270 alsa_mixer-test_write_default_0_34 pass
7916 18:37:09.223923 alsa_mixer-test_write_valid_0_34 pass
7917 18:37:09.226775 alsa_mixer-test_write_invalid_0_34 pass
7918 18:37:09.230339 alsa_mixer-test_event_missing_0_34 pass
7919 18:37:09.234035 alsa_mixer-test_event_spurious_0_34 pass
7920 18:37:09.237132 alsa_mixer-test_get_value_0_33 pass
7921 18:37:09.240161 alsa_mixer-test_name_0_33 fail
7922 18:37:09.243766 alsa_mixer-test_write_default_0_33 pass
7923 18:37:09.246690 alsa_mixer-test_write_valid_0_33 pass
7924 18:37:09.250431 alsa_mixer-test_write_invalid_0_33 pass
7925 18:37:09.253738 alsa_mixer-test_event_missing_0_33 pass
7926 18:37:09.260335 alsa_mixer-test_event_spurious_0_33 pass
7927 18:37:09.263771 alsa_mixer-test_get_value_0_32 pass
7928 18:37:09.264283 alsa_mixer-test_name_0_32 fail
7929 18:37:09.270178 alsa_mixer-test_write_default_0_32 pass
7930 18:37:09.273540 alsa_mixer-test_write_valid_0_32 pass
7931 18:37:09.276795 alsa_mixer-test_write_invalid_0_32 pass
7932 18:37:09.279786 alsa_mixer-test_event_missing_0_32 pass
7933 18:37:09.283205 alsa_mixer-test_event_spurious_0_32 pass
7934 18:37:09.286639 alsa_mixer-test_get_value_0_31 pass
7935 18:37:09.290351 alsa_mixer-test_name_0_31 fail
7936 18:37:09.293623 alsa_mixer-test_write_default_0_31 pass
7937 18:37:09.296719 alsa_mixer-test_write_valid_0_31 pass
7938 18:37:09.300092 alsa_mixer-test_write_invalid_0_31 pass
7939 18:37:09.303625 alsa_mixer-test_event_missing_0_31 pass
7940 18:37:09.306947 alsa_mixer-test_event_spurious_0_31 pass
7941 18:37:09.310327 alsa_mixer-test_get_value_0_30 pass
7942 18:37:09.313144 alsa_mixer-test_name_0_30 fail
7943 18:37:09.316538 alsa_mixer-test_write_default_0_30 pass
7944 18:37:09.320206 alsa_mixer-test_write_valid_0_30 pass
7945 18:37:09.322893 alsa_mixer-test_write_invalid_0_30 pass
7946 18:37:09.326554 alsa_mixer-test_event_missing_0_30 pass
7947 18:37:09.330263 alsa_mixer-test_event_spurious_0_30 pass
7948 18:37:09.333127 alsa_mixer-test_get_value_0_29 pass
7949 18:37:09.336461 alsa_mixer-test_name_0_29 pass
7950 18:37:09.339981 alsa_mixer-test_write_default_0_29 pass
7951 18:37:09.343039 alsa_mixer-test_write_valid_0_29 pass
7952 18:37:09.349508 alsa_mixer-test_write_invalid_0_29 pass
7953 18:37:09.353198 alsa_mixer-test_event_missing_0_29 pass
7954 18:37:09.356201 alsa_mixer-test_event_spurious_0_29 pass
7955 18:37:09.359495 alsa_mixer-test_get_value_0_28 pass
7956 18:37:09.363214 alsa_mixer-test_name_0_28 pass
7957 18:37:09.366353 alsa_mixer-test_write_default_0_28 pass
7958 18:37:09.369838 alsa_mixer-test_write_valid_0_28 pass
7959 18:37:09.373162 alsa_mixer-test_write_invalid_0_28 pass
7960 18:37:09.376408 alsa_mixer-test_event_missing_0_28 pass
7961 18:37:09.379349 alsa_mixer-test_event_spurious_0_28 pass
7962 18:37:09.382881 alsa_mixer-test_get_value_0_27 pass
7963 18:37:09.386265 alsa_mixer-test_name_0_27 pass
7964 18:37:09.389631 alsa_mixer-test_write_default_0_27 pass
7965 18:37:09.393079 alsa_mixer-test_write_valid_0_27 pass
7966 18:37:09.396310 alsa_mixer-test_write_invalid_0_27 pass
7967 18:37:09.400122 alsa_mixer-test_event_missing_0_27 pass
7968 18:37:09.406320 alsa_mixer-test_event_spurious_0_27 pass
7969 18:37:09.409798 alsa_mixer-test_get_value_0_26 pass
7970 18:37:09.410311 alsa_mixer-test_name_0_26 pass
7971 18:37:09.416233 alsa_mixer-test_write_default_0_26 pass
7972 18:37:09.418909 alsa_mixer-test_write_valid_0_26 pass
7973 18:37:09.422108 alsa_mixer-test_write_invalid_0_26 pass
7974 18:37:09.426049 alsa_mixer-test_event_missing_0_26 pass
7975 18:37:09.429498 alsa_mixer-test_event_spurious_0_26 pass
7976 18:37:09.432292 alsa_mixer-test_get_value_0_25 pass
7977 18:37:09.435830 alsa_mixer-test_name_0_25 pass
7978 18:37:09.439482 alsa_mixer-test_write_default_0_25 pass
7979 18:37:09.442099 alsa_mixer-test_write_valid_0_25 pass
7980 18:37:09.445560 alsa_mixer-test_write_invalid_0_25 pass
7981 18:37:09.448738 alsa_mixer-test_event_missing_0_25 pass
7982 18:37:09.452177 alsa_mixer-test_event_spurious_0_25 pass
7983 18:37:09.455592 alsa_mixer-test_get_value_0_24 pass
7984 18:37:09.458753 alsa_mixer-test_name_0_24 pass
7985 18:37:09.462357 alsa_mixer-test_write_default_0_24 pass
7986 18:37:09.465811 alsa_mixer-test_write_valid_0_24 pass
7987 18:37:09.472423 alsa_mixer-test_write_invalid_0_24 pass
7988 18:37:09.475676 alsa_mixer-test_event_missing_0_24 pass
7989 18:37:09.479334 alsa_mixer-test_event_spurious_0_24 pass
7990 18:37:09.482052 alsa_mixer-test_get_value_0_23 pass
7991 18:37:09.485507 alsa_mixer-test_name_0_23 pass
7992 18:37:09.488617 alsa_mixer-test_write_default_0_23 pass
7993 18:37:09.491922 alsa_mixer-test_write_valid_0_23 pass
7994 18:37:09.495639 alsa_mixer-test_write_invalid_0_23 pass
7995 18:37:09.499081 alsa_mixer-test_event_missing_0_23 pass
7996 18:37:09.502200 alsa_mixer-test_event_spurious_0_23 pass
7997 18:37:09.505720 alsa_mixer-test_get_value_0_22 pass
7998 18:37:09.508348 alsa_mixer-test_name_0_22 pass
7999 18:37:09.511894 alsa_mixer-test_write_default_0_22 pass
8000 18:37:09.515450 alsa_mixer-test_write_valid_0_22 pass
8001 18:37:09.518493 alsa_mixer-test_write_invalid_0_22 pass
8002 18:37:09.521940 alsa_mixer-test_event_missing_0_22 pass
8003 18:37:09.528295 alsa_mixer-test_event_spurious_0_22 pass
8004 18:37:09.531822 alsa_mixer-test_get_value_0_21 pass
8005 18:37:09.532235 alsa_mixer-test_name_0_21 fail
8006 18:37:09.539067 alsa_mixer-test_write_default_0_21 pass
8007 18:37:09.542183 alsa_mixer-test_write_valid_0_21 pass
8008 18:37:09.545378 alsa_mixer-test_write_invalid_0_21 pass
8009 18:37:09.548436 alsa_mixer-test_event_missing_0_21 pass
8010 18:37:09.552234 alsa_mixer-test_event_spurious_0_21 pass
8011 18:37:09.555126 alsa_mixer-test_get_value_0_20 pass
8012 18:37:09.559082 alsa_mixer-test_name_0_20 fail
8013 18:37:09.562532 alsa_mixer-test_write_default_0_20 pass
8014 18:37:09.565500 alsa_mixer-test_write_valid_0_20 pass
8015 18:37:09.568447 alsa_mixer-test_write_invalid_0_20 pass
8016 18:37:09.571731 alsa_mixer-test_event_missing_0_20 pass
8017 18:37:09.575964 alsa_mixer-test_event_spurious_0_20 pass
8018 18:37:09.578432 alsa_mixer-test_get_value_0_19 pass
8019 18:37:09.582020 alsa_mixer-test_name_0_19 fail
8020 18:37:09.585144 alsa_mixer-test_write_default_0_19 pass
8021 18:37:09.588149 alsa_mixer-test_write_valid_0_19 pass
8022 18:37:09.591987 alsa_mixer-test_write_invalid_0_19 pass
8023 18:37:09.595569 alsa_mixer-test_event_missing_0_19 pass
8024 18:37:09.598449 alsa_mixer-test_event_spurious_0_19 pass
8025 18:37:09.601921 alsa_mixer-test_get_value_0_18 pass
8026 18:37:09.605187 alsa_mixer-test_name_0_18 fail
8027 18:37:09.608308 alsa_mixer-test_write_default_0_18 pass
8028 18:37:09.610993 alsa_mixer-test_write_valid_0_18 pass
8029 18:37:09.614985 alsa_mixer-test_write_invalid_0_18 pass
8030 18:37:09.617867 alsa_mixer-test_event_missing_0_18 pass
8031 18:37:09.621308 alsa_mixer-test_event_spurious_0_18 pass
8032 18:37:09.624713 alsa_mixer-test_get_value_0_17 pass
8033 18:37:09.627799 alsa_mixer-test_name_0_17 fail
8034 18:37:09.631167 alsa_mixer-test_write_default_0_17 pass
8035 18:37:09.634575 alsa_mixer-test_write_valid_0_17 pass
8036 18:37:09.638086 alsa_mixer-test_write_invalid_0_17 pass
8037 18:37:09.641576 alsa_mixer-test_event_missing_0_17 pass
8038 18:37:09.648031 alsa_mixer-test_event_spurious_0_17 pass
8039 18:37:09.648546 alsa_mixer-test_get_value_0_16 pass
8040 18:37:09.651861 alsa_mixer-test_name_0_16 fail
8041 18:37:09.654759 alsa_mixer-test_write_default_0_16 pass
8042 18:37:09.658653 alsa_mixer-test_write_valid_0_16 pass
8043 18:37:09.664873 alsa_mixer-test_write_invalid_0_16 pass
8044 18:37:09.668000 alsa_mixer-test_event_missing_0_16 pass
8045 18:37:09.671216 alsa_mixer-test_event_spurious_0_16 pass
8046 18:37:09.674822 alsa_mixer-test_get_value_0_15 pass
8047 18:37:09.677707 alsa_mixer-test_name_0_15 fail
8048 18:37:09.680812 alsa_mixer-test_write_default_0_15 pass
8049 18:37:09.684075 alsa_mixer-test_write_valid_0_15 pass
8050 18:37:09.687384 alsa_mixer-test_write_invalid_0_15 pass
8051 18:37:09.690988 alsa_mixer-test_event_missing_0_15 pass
8052 18:37:09.694754 alsa_mixer-test_event_spurious_0_15 pass
8053 18:37:09.697288 alsa_mixer-test_get_value_0_14 pass
8054 18:37:09.700663 alsa_mixer-test_name_0_14 fail
8055 18:37:09.704027 alsa_mixer-test_write_default_0_14 pass
8056 18:37:09.707345 alsa_mixer-test_write_valid_0_14 pass
8057 18:37:09.710797 alsa_mixer-test_write_invalid_0_14 pass
8058 18:37:09.714112 alsa_mixer-test_event_missing_0_14 pass
8059 18:37:09.717011 alsa_mixer-test_event_spurious_0_14 pass
8060 18:37:09.720384 alsa_mixer-test_get_value_0_13 pass
8061 18:37:09.723881 alsa_mixer-test_name_0_13 fail
8062 18:37:09.726848 alsa_mixer-test_write_default_0_13 pass
8063 18:37:09.730138 alsa_mixer-test_write_valid_0_13 pass
8064 18:37:09.733399 alsa_mixer-test_write_invalid_0_13 pass
8065 18:37:09.737121 alsa_mixer-test_event_missing_0_13 pass
8066 18:37:09.740138 alsa_mixer-test_event_spurious_0_13 pass
8067 18:37:09.743715 alsa_mixer-test_get_value_0_12 pass
8068 18:37:09.746975 alsa_mixer-test_name_0_12 fail
8069 18:37:09.749988 alsa_mixer-test_write_default_0_12 pass
8070 18:37:09.753432 alsa_mixer-test_write_valid_0_12 pass
8071 18:37:09.756517 alsa_mixer-test_write_invalid_0_12 pass
8072 18:37:09.759898 alsa_mixer-test_event_missing_0_12 pass
8073 18:37:09.763229 alsa_mixer-test_event_spurious_0_12 pass
8074 18:37:09.766682 alsa_mixer-test_get_value_0_11 pass
8075 18:37:09.769786 alsa_mixer-test_name_0_11 fail
8076 18:37:09.773434 alsa_mixer-test_write_default_0_11 pass
8077 18:37:09.776714 alsa_mixer-test_write_valid_0_11 pass
8078 18:37:09.779657 alsa_mixer-test_write_invalid_0_11 pass
8079 18:37:09.783114 alsa_mixer-test_event_missing_0_11 pass
8080 18:37:09.789679 alsa_mixer-test_event_spurious_0_11 pass
8081 18:37:09.793171 alsa_mixer-test_get_value_0_10 pass
8082 18:37:09.793263 alsa_mixer-test_name_0_10 fail
8083 18:37:09.799726 alsa_mixer-test_write_default_0_10 pass
8084 18:37:09.803048 alsa_mixer-test_write_valid_0_10 pass
8085 18:37:09.806113 alsa_mixer-test_write_invalid_0_10 pass
8086 18:37:09.809551 alsa_mixer-test_event_missing_0_10 pass
8087 18:37:09.813161 alsa_mixer-test_event_spurious_0_10 pass
8088 18:37:09.816272 alsa_mixer-test_get_value_0_9 pass
8089 18:37:09.819908 alsa_mixer-test_name_0_9 fail
8090 18:37:09.823145 alsa_mixer-test_write_default_0_9 pass
8091 18:37:09.826216 alsa_mixer-test_write_valid_0_9 pass
8092 18:37:09.829795 alsa_mixer-test_write_invalid_0_9 pass
8093 18:37:09.833062 alsa_mixer-test_event_missing_0_9 pass
8094 18:37:09.836316 alsa_mixer-test_event_spurious_0_9 pass
8095 18:37:09.839290 alsa_mixer-test_get_value_0_8 pass
8096 18:37:09.842852 alsa_mixer-test_name_0_8 fail
8097 18:37:09.846419 alsa_mixer-test_write_default_0_8 pass
8098 18:37:09.849584 alsa_mixer-test_write_valid_0_8 pass
8099 18:37:09.852477 alsa_mixer-test_write_invalid_0_8 pass
8100 18:37:09.856148 alsa_mixer-test_event_missing_0_8 pass
8101 18:37:09.859004 alsa_mixer-test_event_spurious_0_8 pass
8102 18:37:09.862605 alsa_mixer-test_get_value_0_7 pass
8103 18:37:09.865663 alsa_mixer-test_name_0_7 fail
8104 18:37:09.869120 alsa_mixer-test_write_default_0_7 pass
8105 18:37:09.872787 alsa_mixer-test_write_valid_0_7 pass
8106 18:37:09.875952 alsa_mixer-test_write_invalid_0_7 pass
8107 18:37:09.879253 alsa_mixer-test_event_missing_0_7 pass
8108 18:37:09.882397 alsa_mixer-test_event_spurious_0_7 pass
8109 18:37:09.885733 alsa_mixer-test_get_value_0_6 pass
8110 18:37:09.888885 alsa_mixer-test_name_0_6 fail
8111 18:37:09.892636 alsa_mixer-test_write_default_0_6 pass
8112 18:37:09.896082 alsa_mixer-test_write_valid_0_6 pass
8113 18:37:09.899212 alsa_mixer-test_write_invalid_0_6 pass
8114 18:37:09.902771 alsa_mixer-test_event_missing_0_6 pass
8115 18:37:09.905960 alsa_mixer-test_event_spurious_0_6 pass
8116 18:37:09.909227 alsa_mixer-test_get_value_0_5 pass
8117 18:37:09.912428 alsa_mixer-test_name_0_5 pass
8118 18:37:09.916047 alsa_mixer-test_write_default_0_5 pass
8119 18:37:09.918598 alsa_mixer-test_write_valid_0_5 pass
8120 18:37:09.922479 alsa_mixer-test_write_invalid_0_5 pass
8121 18:37:09.925513 alsa_mixer-test_event_missing_0_5 fail
8122 18:37:09.928888 alsa_mixer-test_event_spurious_0_5 pass
8123 18:37:09.932388 alsa_mixer-test_get_value_0_4 pass
8124 18:37:09.935881 alsa_mixer-test_name_0_4 pass
8125 18:37:09.939119 alsa_mixer-test_write_default_0_4 pass
8126 18:37:09.942000 alsa_mixer-test_write_valid_0_4 pass
8127 18:37:09.945495 alsa_mixer-test_write_invalid_0_4 pass
8128 18:37:09.949087 alsa_mixer-test_event_missing_0_4 fail
8129 18:37:09.952398 alsa_mixer-test_event_spurious_0_4 pass
8130 18:37:09.955428 alsa_mixer-test_get_value_0_3 pass
8131 18:37:09.958466 alsa_mixer-test_name_0_3 pass
8132 18:37:09.961975 alsa_mixer-test_write_default_0_3 pass
8133 18:37:09.965547 alsa_mixer-test_write_valid_0_3 pass
8134 18:37:09.969122 alsa_mixer-test_write_invalid_0_3 pass
8135 18:37:09.971670 alsa_mixer-test_event_missing_0_3 fail
8136 18:37:09.975238 alsa_mixer-test_event_spurious_0_3 pass
8137 18:37:09.978459 alsa_mixer-test_get_value_0_2 pass
8138 18:37:09.981587 alsa_mixer-test_name_0_2 pass
8139 18:37:09.984989 alsa_mixer-test_write_default_0_2 pass
8140 18:37:09.988225 alsa_mixer-test_write_valid_0_2 pass
8141 18:37:09.991958 alsa_mixer-test_write_invalid_0_2 pass
8142 18:37:09.995166 alsa_mixer-test_event_missing_0_2 fail
8143 18:37:09.998529 alsa_mixer-test_event_spurious_0_2 pass
8144 18:37:10.001489 alsa_mixer-test_get_value_0_1 pass
8145 18:37:10.004908 alsa_mixer-test_name_0_1 pass
8146 18:37:10.008074 alsa_mixer-test_write_default_0_1 pass
8147 18:37:10.011484 alsa_mixer-test_write_valid_0_1 pass
8148 18:37:10.014978 alsa_mixer-test_write_invalid_0_1 pass
8149 18:37:10.018531 alsa_mixer-test_event_missing_0_1 fail
8150 18:37:10.021688 alsa_mixer-test_event_spurious_0_1 pass
8151 18:37:10.024597 alsa_mixer-test_get_value_0_0 pass
8152 18:37:10.027952 alsa_mixer-test_name_0_0 pass
8153 18:37:10.031393 alsa_mixer-test_write_default_0_0 pass
8154 18:37:10.034583 alsa_mixer-test_write_valid_0_0 pass
8155 18:37:10.037894 alsa_mixer-test_write_invalid_0_0 pass
8156 18:37:10.041359 alsa_mixer-test_event_missing_0_0 fail
8157 18:37:10.044653 alsa_mixer-test_event_spurious_0_0 pass
8158 18:37:10.047695 alsa_mixer-test pass
8159 18:37:10.051032 + ../../utils/send-to-lava.sh ./output/result.txt
8160 18:37:10.057940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8161 18:37:10.058254 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8163 18:37:10.064673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8164 18:37:10.064937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8166 18:37:10.071532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8167 18:37:10.071795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8169 18:37:10.077938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8170 18:37:10.078202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8172 18:37:10.123246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8173 18:37:10.123524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8175 18:37:10.182794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8176 18:37:10.183109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8178 18:37:10.229465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8179 18:37:10.229747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8181 18:37:10.278908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8182 18:37:10.279197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8184 18:37:10.324369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8185 18:37:10.324676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8187 18:37:10.370656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8188 18:37:10.370964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8190 18:37:10.415757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8191 18:37:10.416054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8193 18:37:10.453657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8194 18:37:10.453945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8196 18:37:10.496488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8197 18:37:10.496764 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8199 18:37:10.538393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8200 18:37:10.538671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8202 18:37:10.586162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8203 18:37:10.586436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8205 18:37:10.627830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8206 18:37:10.628104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8208 18:37:10.664711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8209 18:37:10.664978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8211 18:37:10.712827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8212 18:37:10.713093 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8214 18:37:10.757078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8215 18:37:10.757360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8217 18:37:10.802694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8218 18:37:10.802969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8220 18:37:10.843463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8221 18:37:10.843785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8223 18:37:10.880705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8224 18:37:10.880978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8226 18:37:10.919837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8227 18:37:10.920112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8229 18:37:10.954009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8230 18:37:10.954299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8232 18:37:10.999666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8233 18:37:11.000371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8235 18:37:11.051149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8236 18:37:11.051550 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8238 18:37:11.092374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8239 18:37:11.092661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8241 18:37:11.129377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8242 18:37:11.129666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8244 18:37:11.172723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8245 18:37:11.173005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8247 18:37:11.214663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8248 18:37:11.214970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8250 18:37:11.251491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8251 18:37:11.251825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8253 18:37:11.292187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8254 18:37:11.292458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8256 18:37:11.329876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8257 18:37:11.330146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8259 18:37:11.368523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8260 18:37:11.368838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8262 18:37:11.412067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8263 18:37:11.412347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8265 18:37:11.452132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8266 18:37:11.452435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8268 18:37:11.502399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8269 18:37:11.502712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8271 18:37:11.538930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8272 18:37:11.539205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8274 18:37:11.581804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8275 18:37:11.582075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8277 18:37:11.621634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8278 18:37:11.621909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8280 18:37:11.658993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8281 18:37:11.659275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8283 18:37:11.708731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8284 18:37:11.709006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8286 18:37:11.753438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8287 18:37:11.753749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8289 18:37:11.794286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8290 18:37:11.794596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8292 18:37:11.834482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8293 18:37:11.834844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8295 18:37:11.881174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8296 18:37:11.881487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8298 18:37:11.923866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8299 18:37:11.924189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8301 18:37:11.964645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8302 18:37:11.964981 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8304 18:37:12.015713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8305 18:37:12.016048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8307 18:37:12.064699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8308 18:37:12.065033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8310 18:37:12.110853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8311 18:37:12.111185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8313 18:37:12.148496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8314 18:37:12.148791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8316 18:37:12.190804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8317 18:37:12.191131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8319 18:37:12.230972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8320 18:37:12.231300 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8322 18:37:12.275969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8323 18:37:12.276366 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8325 18:37:12.320937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8326 18:37:12.321834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8328 18:37:12.366951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8329 18:37:12.367856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8331 18:37:12.415679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8332 18:37:12.416559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8334 18:37:12.461391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8335 18:37:12.462324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8337 18:37:12.530783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8338 18:37:12.531522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8340 18:37:12.586879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8341 18:37:12.587532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8343 18:37:12.643265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8344 18:37:12.644058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8346 18:37:12.701530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8347 18:37:12.702225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8349 18:37:12.756193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8350 18:37:12.756906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8352 18:37:12.803540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8353 18:37:12.803847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8355 18:37:12.839112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8356 18:37:12.840020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8358 18:37:12.883924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8359 18:37:12.884226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8361 18:37:12.926339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8362 18:37:12.926731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8364 18:37:12.972870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8365 18:37:12.973723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8367 18:37:13.026375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8368 18:37:13.027235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8370 18:37:13.076042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8371 18:37:13.076772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8373 18:37:13.119791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8374 18:37:13.120062 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8376 18:37:13.155952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8377 18:37:13.156242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8379 18:37:13.201703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8380 18:37:13.201984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8382 18:37:13.246535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8383 18:37:13.246830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8385 18:37:13.297280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8386 18:37:13.297578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8388 18:37:13.340039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8389 18:37:13.340325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8391 18:37:13.405313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8392 18:37:13.405605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8394 18:37:13.447561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8395 18:37:13.447982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8397 18:37:13.489789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8398 18:37:13.490471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8400 18:37:13.547966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8401 18:37:13.548702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8403 18:37:13.600363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8404 18:37:13.601100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8406 18:37:13.651598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8407 18:37:13.652278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8409 18:37:13.695284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8410 18:37:13.695597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8412 18:37:13.737632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8413 18:37:13.737931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8415 18:37:13.777416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8416 18:37:13.777702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8418 18:37:13.812689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8419 18:37:13.812992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8421 18:37:13.860524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8422 18:37:13.861208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8424 18:37:13.915095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8425 18:37:13.915842 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8427 18:37:13.966757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8428 18:37:13.967527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8430 18:37:14.015319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8431 18:37:14.016075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8433 18:37:14.066626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8434 18:37:14.067318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8436 18:37:14.121019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8437 18:37:14.121694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8439 18:37:14.174602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8441 18:37:14.178100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8442 18:37:14.237757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8443 18:37:14.238730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8445 18:37:14.281837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8446 18:37:14.282584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8448 18:37:14.336620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8449 18:37:14.337358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8451 18:37:14.392957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8452 18:37:14.393700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8454 18:37:14.448510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8455 18:37:14.449320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8457 18:37:14.456954 <6>[ 37.990013] vaux18: disabling
8458 18:37:14.461216 <6>[ 37.993821] vio28: disabling
8459 18:37:14.511526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8460 18:37:14.512286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8462 18:37:14.564439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8463 18:37:14.565122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8465 18:37:14.619260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8466 18:37:14.620088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8468 18:37:14.671290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8469 18:37:14.672106 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8471 18:37:14.722887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8472 18:37:14.723578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8474 18:37:14.780219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8475 18:37:14.780902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8477 18:37:14.832227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8478 18:37:14.832522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8480 18:37:14.869993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8481 18:37:14.870279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8483 18:37:14.904341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8484 18:37:14.904613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8486 18:37:14.949007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8487 18:37:14.949297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8489 18:37:14.997980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8490 18:37:14.998289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8492 18:37:15.035275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8493 18:37:15.035557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8495 18:37:15.072365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8496 18:37:15.072636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8498 18:37:15.112511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8499 18:37:15.113244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8501 18:37:15.161227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8502 18:37:15.161950 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8504 18:37:15.214356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8505 18:37:15.215141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8507 18:37:15.268276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8508 18:37:15.269211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8510 18:37:15.320889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8511 18:37:15.321859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8513 18:37:15.390938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8514 18:37:15.391253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8516 18:37:15.438647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8517 18:37:15.438938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8519 18:37:15.479391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8520 18:37:15.480163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8522 18:37:15.531135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8523 18:37:15.531922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8525 18:37:15.580123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8526 18:37:15.580902 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8528 18:37:15.640705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8529 18:37:15.641447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8531 18:37:15.701451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8532 18:37:15.702296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8534 18:37:15.751386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8535 18:37:15.752230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8537 18:37:15.803977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8538 18:37:15.804698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8540 18:37:15.865630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8541 18:37:15.866349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8543 18:37:15.921286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8544 18:37:15.921629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8546 18:37:15.969114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8547 18:37:15.969874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8549 18:37:16.026284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8550 18:37:16.027020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8552 18:37:16.080283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8553 18:37:16.081005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8555 18:37:16.134878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8556 18:37:16.135629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8558 18:37:16.191724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8559 18:37:16.192490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8561 18:37:16.249441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8562 18:37:16.250133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8564 18:37:16.302317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8565 18:37:16.303149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8567 18:37:16.357827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8568 18:37:16.358553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8570 18:37:16.406131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8571 18:37:16.406932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8573 18:37:16.454722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8574 18:37:16.455455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8576 18:37:16.508309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8577 18:37:16.509065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8579 18:37:16.559525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8580 18:37:16.560197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8582 18:37:16.607711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8583 18:37:16.608004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8585 18:37:16.647742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8587 18:37:16.650987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8588 18:37:16.703096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8589 18:37:16.703847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8591 18:37:16.755145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8592 18:37:16.756183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8594 18:37:16.803891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8595 18:37:16.804696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8597 18:37:16.852458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8598 18:37:16.853231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8600 18:37:16.902016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8601 18:37:16.902758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8603 18:37:16.954985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8604 18:37:16.955728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8606 18:37:17.006178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8607 18:37:17.006877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8609 18:37:17.054332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8610 18:37:17.055034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8612 18:37:17.111977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8613 18:37:17.112675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8615 18:37:17.172383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8616 18:37:17.173154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8618 18:37:17.222602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8619 18:37:17.222893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8621 18:37:17.264814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8622 18:37:17.265115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8624 18:37:17.307952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8625 18:37:17.308755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8627 18:37:17.360505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8628 18:37:17.361223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8630 18:37:17.411039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8631 18:37:17.412369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8633 18:37:17.462288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8634 18:37:17.463570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8636 18:37:17.507081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8637 18:37:17.507393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8639 18:37:17.553357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8640 18:37:17.553638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8642 18:37:17.594373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8643 18:37:17.594697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8645 18:37:17.638613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8646 18:37:17.638920 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8648 18:37:17.684094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8649 18:37:17.684369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8651 18:37:17.726401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8652 18:37:17.726766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8654 18:37:17.771872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8655 18:37:17.772259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8657 18:37:17.815174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8658 18:37:17.815930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8660 18:37:17.860412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8661 18:37:17.860761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8663 18:37:17.903563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8664 18:37:17.904299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8666 18:37:17.956131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8667 18:37:17.956979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8669 18:37:18.007225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8670 18:37:18.007540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8672 18:37:18.054159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8673 18:37:18.054864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8675 18:37:18.106697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8676 18:37:18.107401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8678 18:37:18.157921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8679 18:37:18.158783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8681 18:37:18.207285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8682 18:37:18.208048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8684 18:37:18.256931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8685 18:37:18.257734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8687 18:37:18.306509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8688 18:37:18.307348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8690 18:37:18.356896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8691 18:37:18.357756 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8693 18:37:18.403663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8694 18:37:18.404339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8696 18:37:18.460163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8697 18:37:18.460843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8699 18:37:18.513790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8700 18:37:18.514606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8702 18:37:18.560117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8703 18:37:18.560834 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8705 18:37:18.612481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8706 18:37:18.613310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8708 18:37:18.661278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8709 18:37:18.661585 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8711 18:37:18.709039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8712 18:37:18.709328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8714 18:37:18.755384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8715 18:37:18.756117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8717 18:37:18.808611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8718 18:37:18.809315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8720 18:37:18.860126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8721 18:37:18.860823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8723 18:37:18.912427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8724 18:37:18.913196 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8726 18:37:18.966383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8727 18:37:18.967075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8729 18:37:19.018705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8730 18:37:19.019520 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8732 18:37:19.072011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8733 18:37:19.072751 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8735 18:37:19.123174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8736 18:37:19.124003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8738 18:37:19.183089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8739 18:37:19.184002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8741 18:37:19.235097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8742 18:37:19.235851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8744 18:37:19.287784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8745 18:37:19.288515 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8747 18:37:19.338790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8748 18:37:19.339516 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8750 18:37:19.397490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8751 18:37:19.398222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8753 18:37:19.449965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8754 18:37:19.450711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8756 18:37:19.502789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8757 18:37:19.503531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8759 18:37:19.557513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8760 18:37:19.558465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8762 18:37:19.604927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8763 18:37:19.605717 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8765 18:37:19.652733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8766 18:37:19.653140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8768 18:37:19.703924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8769 18:37:19.704306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8771 18:37:19.758149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8772 18:37:19.758631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8774 18:37:19.801689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8775 18:37:19.801966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8777 18:37:19.841076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8778 18:37:19.841362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8780 18:37:19.886384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8781 18:37:19.886832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8783 18:37:19.933791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8784 18:37:19.934090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8786 18:37:19.972096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8787 18:37:19.972435 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8789 18:37:20.012342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8790 18:37:20.012626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8792 18:37:20.057507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8793 18:37:20.057858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8795 18:37:20.101506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8796 18:37:20.101783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8798 18:37:20.142968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8799 18:37:20.143274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8801 18:37:20.194541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8802 18:37:20.194882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8804 18:37:20.245239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8805 18:37:20.245579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8807 18:37:20.297667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8808 18:37:20.298013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8810 18:37:20.346875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8811 18:37:20.347304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8813 18:37:20.394838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8814 18:37:20.395121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8816 18:37:20.441446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8817 18:37:20.441780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8819 18:37:20.487373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8820 18:37:20.488161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8822 18:37:20.542667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8823 18:37:20.543490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8825 18:37:20.598831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8826 18:37:20.599602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8828 18:37:20.651206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8829 18:37:20.652241 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8831 18:37:20.701544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8832 18:37:20.702462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8834 18:37:20.768027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8835 18:37:20.768932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8837 18:37:20.823586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8838 18:37:20.823922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8840 18:37:20.872908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8841 18:37:20.873660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8843 18:37:20.920366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8844 18:37:20.921161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8846 18:37:20.968669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8847 18:37:20.969363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8849 18:37:21.026869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8850 18:37:21.027164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8852 18:37:21.072109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8853 18:37:21.072420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8855 18:37:21.116959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8856 18:37:21.117688 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8858 18:37:21.164788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8859 18:37:21.165250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8861 18:37:21.203630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8862 18:37:21.203972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8864 18:37:21.242866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8865 18:37:21.243209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8867 18:37:21.282277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8868 18:37:21.282629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8870 18:37:21.330802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8871 18:37:21.331167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8873 18:37:21.376144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8874 18:37:21.376527 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8876 18:37:21.415004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8877 18:37:21.415339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8879 18:37:21.455352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8880 18:37:21.455719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8882 18:37:21.492971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8883 18:37:21.493308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8885 18:37:21.540806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8886 18:37:21.541132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8888 18:37:21.584303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8889 18:37:21.585027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8891 18:37:21.636789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8892 18:37:21.637659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8894 18:37:21.688272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8895 18:37:21.688997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8897 18:37:21.740271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8898 18:37:21.741153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8900 18:37:21.787742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8901 18:37:21.788489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8903 18:37:21.836077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8904 18:37:21.836812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8906 18:37:21.887053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8907 18:37:21.887819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8909 18:37:21.940140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8910 18:37:21.940896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8912 18:37:21.996060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8913 18:37:21.996737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8915 18:37:22.047887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8916 18:37:22.048556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8918 18:37:22.099518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8919 18:37:22.100230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8921 18:37:22.152408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8922 18:37:22.153104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8924 18:37:22.202552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8925 18:37:22.203253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8927 18:37:22.258700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8928 18:37:22.259459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8930 18:37:22.311768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8931 18:37:22.312448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8933 18:37:22.363105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8934 18:37:22.363419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8936 18:37:22.407618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8937 18:37:22.408050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8939 18:37:22.456072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8940 18:37:22.456431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8942 18:37:22.501580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8943 18:37:22.502249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8945 18:37:22.552353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8946 18:37:22.553240 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8948 18:37:22.604548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8949 18:37:22.605067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8951 18:37:22.658989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8952 18:37:22.659728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8954 18:37:22.714362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8955 18:37:22.714642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8957 18:37:22.761979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8958 18:37:22.762368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8960 18:37:22.807194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8961 18:37:22.808154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8963 18:37:22.849857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8964 18:37:22.850191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8966 18:37:22.892553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8967 18:37:22.893266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8969 18:37:22.947175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8970 18:37:22.947910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8972 18:37:22.999293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8973 18:37:23.000277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8975 18:37:23.055521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8976 18:37:23.056237 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8978 18:37:23.107980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8979 18:37:23.108705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8981 18:37:23.163914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8982 18:37:23.164713 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8984 18:37:23.212175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8985 18:37:23.212889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8987 18:37:23.259524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8988 18:37:23.260234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
8990 18:37:23.312570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
8991 18:37:23.313465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
8993 18:37:23.360257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
8994 18:37:23.361134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
8996 18:37:23.409293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
8997 18:37:23.410015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
8999 18:37:23.463122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
9000 18:37:23.463985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
9002 18:37:23.519566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
9003 18:37:23.520259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
9005 18:37:23.577128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
9006 18:37:23.577486 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
9008 18:37:23.628852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
9009 18:37:23.629602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
9011 18:37:23.685217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
9012 18:37:23.685912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
9014 18:37:23.745337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
9015 18:37:23.746172 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
9017 18:37:23.804991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
9018 18:37:23.805813 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
9020 18:37:23.860644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
9021 18:37:23.861693 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
9023 18:37:23.912837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
9024 18:37:23.913844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
9026 18:37:23.968611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9027 18:37:23.969421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9029 18:37:24.017516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9030 18:37:24.018305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9032 18:37:24.075844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9033 18:37:24.076546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9035 18:37:24.128749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9036 18:37:24.129454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9038 18:37:24.181996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9039 18:37:24.182691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9041 18:37:24.232076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9042 18:37:24.232742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9044 18:37:24.290756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9045 18:37:24.291479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9047 18:37:24.348107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9048 18:37:24.348914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9050 18:37:24.394793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9051 18:37:24.395458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9053 18:37:24.445995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9054 18:37:24.446780 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9056 18:37:24.499034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9057 18:37:24.499775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9059 18:37:24.550258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9060 18:37:24.550932 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9062 18:37:24.601796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9063 18:37:24.602480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9065 18:37:24.651777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9066 18:37:24.652464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9068 18:37:24.702167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9069 18:37:24.702606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9071 18:37:24.747810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9072 18:37:24.748507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9074 18:37:24.798409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9075 18:37:24.798777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9077 18:37:24.847383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9078 18:37:24.848107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9080 18:37:24.903539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9081 18:37:24.904221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9083 18:37:24.951077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9084 18:37:24.951791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9086 18:37:25.004887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9087 18:37:25.005571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9089 18:37:25.062163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9090 18:37:25.062839 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9092 18:37:25.118169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9093 18:37:25.118855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9095 18:37:25.179963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9096 18:37:25.180660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9098 18:37:25.235788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9099 18:37:25.236557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9101 18:37:25.290300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9102 18:37:25.290993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9104 18:37:25.344706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9105 18:37:25.345488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9107 18:37:25.396339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9108 18:37:25.397022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9110 18:37:25.449872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9111 18:37:25.450548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9113 18:37:25.498790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9114 18:37:25.499497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9116 18:37:25.554465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9117 18:37:25.555262 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9119 18:37:25.604153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9120 18:37:25.604829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9122 18:37:25.654494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9123 18:37:25.655171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9125 18:37:25.705091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9126 18:37:25.705769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9128 18:37:25.758055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9129 18:37:25.758725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9131 18:37:25.817881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9132 18:37:25.818647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9134 18:37:25.874108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9135 18:37:25.874893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9137 18:37:25.927436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9138 18:37:25.928257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9140 18:37:25.979394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9141 18:37:25.980371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9143 18:37:26.032672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9144 18:37:26.033372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9146 18:37:26.088130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9147 18:37:26.088816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9149 18:37:26.143950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9150 18:37:26.144648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9152 18:37:26.200778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9153 18:37:26.201554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9155 18:37:26.247914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9156 18:37:26.248228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9158 18:37:26.294950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9159 18:37:26.295825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9161 18:37:26.347902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9162 18:37:26.348185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9164 18:37:26.389690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9165 18:37:26.390413 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9167 18:37:26.438628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9168 18:37:26.439339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9170 18:37:26.488185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9171 18:37:26.489003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9173 18:37:26.538183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9174 18:37:26.538944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9176 18:37:26.586141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9177 18:37:26.586506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9179 18:37:26.641723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9180 18:37:26.642086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9182 18:37:26.679655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9183 18:37:26.680006 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9185 18:37:26.718168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9186 18:37:26.718999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9188 18:37:26.767370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9189 18:37:26.767837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9191 18:37:26.808337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9192 18:37:26.808755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9194 18:37:26.849936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9195 18:37:26.850348 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9197 18:37:26.889576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9198 18:37:26.889980 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9200 18:37:26.940359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9201 18:37:26.940690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9203 18:37:26.987864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9204 18:37:26.988290 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9206 18:37:27.033459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9207 18:37:27.034182 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9209 18:37:27.074660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9210 18:37:27.075355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9212 18:37:27.127133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9213 18:37:27.127844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9215 18:37:27.178081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9216 18:37:27.178761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9218 18:37:27.228433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9219 18:37:27.229134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9221 18:37:27.282847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9222 18:37:27.283122 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9224 18:37:27.332532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9225 18:37:27.333156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9227 18:37:27.387943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9228 18:37:27.388738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9230 18:37:27.440718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9231 18:37:27.441499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9233 18:37:27.495342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9234 18:37:27.496190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9236 18:37:27.542943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9237 18:37:27.543231 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9239 18:37:27.589148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9240 18:37:27.589587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9242 18:37:27.647830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9243 18:37:27.648790 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9245 18:37:27.702211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9246 18:37:27.703066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9248 18:37:27.755226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9249 18:37:27.756158 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9251 18:37:27.809269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9252 18:37:27.809570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9254 18:37:27.863048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9255 18:37:27.863360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9257 18:37:27.908322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9258 18:37:27.908596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9260 18:37:27.956333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9261 18:37:27.957047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9263 18:37:28.008037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9264 18:37:28.008944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9266 18:37:28.060303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9267 18:37:28.061090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9269 18:37:28.119043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9270 18:37:28.119930 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9272 18:37:28.174650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9273 18:37:28.175507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9275 18:37:28.233060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9276 18:37:28.233912 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9278 18:37:28.285456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9279 18:37:28.286144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9281 18:37:28.334682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9282 18:37:28.335354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9284 18:37:28.393172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9285 18:37:28.394044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9287 18:37:28.447241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9288 18:37:28.448089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9290 18:37:28.503838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9291 18:37:28.504604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9293 18:37:28.557416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9294 18:37:28.558275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9296 18:37:28.611719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9297 18:37:28.612473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9299 18:37:28.668099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9300 18:37:28.668774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9302 18:37:28.721597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9303 18:37:28.722278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9305 18:37:28.780310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9306 18:37:28.781014 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9308 18:37:28.840239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9309 18:37:28.841045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9311 18:37:28.900138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9312 18:37:28.901008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9314 18:37:28.958626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9315 18:37:28.959535 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9317 18:37:29.011988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9318 18:37:29.012872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9320 18:37:29.068486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9321 18:37:29.069363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9323 18:37:29.120689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9324 18:37:29.121579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9326 18:37:29.172968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9327 18:37:29.173969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9329 18:37:29.224640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9330 18:37:29.225510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9332 18:37:29.272758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9333 18:37:29.273059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9335 18:37:29.321464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9336 18:37:29.322354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9338 18:37:29.377594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9339 18:37:29.378509 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9341 18:37:29.426199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9342 18:37:29.427039 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9344 18:37:29.477221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9345 18:37:29.478094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9347 18:37:29.535940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9348 18:37:29.536898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9350 18:37:29.587975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9351 18:37:29.588742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9353 18:37:29.642473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9354 18:37:29.642940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9356 18:37:29.690231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9357 18:37:29.690586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9359 18:37:29.737936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9360 18:37:29.738314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9362 18:37:29.790580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9363 18:37:29.791480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9365 18:37:29.837200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9366 18:37:29.837488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9368 18:37:29.891636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9369 18:37:29.892279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9371 18:37:29.946756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9372 18:37:29.947716 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9374 18:37:30.001074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9375 18:37:30.001917 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9377 18:37:30.056536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9378 18:37:30.057512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9380 18:37:30.112830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9381 18:37:30.113701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9383 18:37:30.172809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9384 18:37:30.173767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9386 18:37:30.219318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9387 18:37:30.220250 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9389 18:37:30.271960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9390 18:37:30.272804 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9392 18:37:30.328764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9393 18:37:30.329685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9395 18:37:30.377832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9396 18:37:30.378722 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9398 18:37:30.431060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9399 18:37:30.432023 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9401 18:37:30.487976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9402 18:37:30.488857 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9404 18:37:30.549762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9405 18:37:30.550536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9407 18:37:30.596466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9408 18:37:30.597242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9410 18:37:30.659982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9411 18:37:30.660752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9413 18:37:30.719506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9414 18:37:30.720235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9416 18:37:30.772603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9417 18:37:30.773410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9419 18:37:30.828324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9420 18:37:30.829140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9422 18:37:30.883235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9423 18:37:30.884103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9425 18:37:30.940881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9426 18:37:30.941803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9428 18:37:30.992796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9429 18:37:30.993654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9431 18:37:31.047896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9432 18:37:31.048855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9434 18:37:31.094983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9435 18:37:31.095919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9437 18:37:31.152530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9438 18:37:31.153398 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9440 18:37:31.206875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9441 18:37:31.207752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9443 18:37:31.261858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9444 18:37:31.262719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9446 18:37:31.311600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9447 18:37:31.312447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9449 18:37:31.365477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9450 18:37:31.366296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9452 18:37:31.418017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9453 18:37:31.418776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9455 18:37:31.470707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9456 18:37:31.471071 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9458 18:37:31.519600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9459 18:37:31.519946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9461 18:37:31.569438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9462 18:37:31.570104 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9464 18:37:31.623575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9465 18:37:31.624497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9467 18:37:31.676415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9468 18:37:31.677304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9470 18:37:31.725462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9471 18:37:31.726343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9473 18:37:31.785340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9474 18:37:31.786308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9476 18:37:31.840510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9477 18:37:31.841402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9479 18:37:31.893168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9480 18:37:31.893909 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9482 18:37:31.947480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9483 18:37:31.948174 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9485 18:37:32.000397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9486 18:37:32.001084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9488 18:37:32.052697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9489 18:37:32.053552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9491 18:37:32.100241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9492 18:37:32.101026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9494 18:37:32.165534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9495 18:37:32.166508 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9497 18:37:32.215978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9498 18:37:32.216338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9500 18:37:32.262636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9501 18:37:32.263545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9503 18:37:32.313844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9504 18:37:32.314744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9506 18:37:32.361386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9507 18:37:32.362249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9509 18:37:32.416965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9510 18:37:32.417672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9512 18:37:32.468785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9513 18:37:32.469074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9515 18:37:32.520551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9516 18:37:32.520928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9518 18:37:32.579128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9519 18:37:32.579878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9521 18:37:32.629922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9522 18:37:32.630293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9524 18:37:32.680667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9525 18:37:32.681581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9527 18:37:32.729768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9528 18:37:32.730214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9530 18:37:32.771354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9531 18:37:32.771645 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9533 18:37:32.809119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9534 18:37:32.809423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9536 18:37:32.855389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9537 18:37:32.855685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9539 18:37:32.899309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9540 18:37:32.900180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9542 18:37:32.953055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9543 18:37:32.954074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9545 18:37:33.004852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9546 18:37:33.005162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9548 18:37:33.055443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9549 18:37:33.056306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9551 18:37:33.107577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9552 18:37:33.107860 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9554 18:37:33.147475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9555 18:37:33.147746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9557 18:37:33.195540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9558 18:37:33.196255 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9560 18:37:33.248374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9561 18:37:33.249084 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9563 18:37:33.302092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9564 18:37:33.302940 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9566 18:37:33.354626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9567 18:37:33.355553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9569 18:37:33.399878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9570 18:37:33.400762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9572 18:37:33.440129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9573 18:37:33.440420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9575 18:37:33.481550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9576 18:37:33.481849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9578 18:37:33.532309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9579 18:37:33.532597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9581 18:37:33.573601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9582 18:37:33.573878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9584 18:37:33.621537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9585 18:37:33.622243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9587 18:37:33.677934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9588 18:37:33.678642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9590 18:37:33.724782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9591 18:37:33.725483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9593 18:37:33.777741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9594 18:37:33.778671 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9596 18:37:33.825563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9597 18:37:33.826279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9599 18:37:33.882697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9600 18:37:33.883454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9602 18:37:33.936606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9603 18:37:33.936996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9605 18:37:33.982990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9606 18:37:33.983278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9608 18:37:34.030234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9609 18:37:34.030956 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9611 18:37:34.085426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9612 18:37:34.086119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9614 18:37:34.139981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9615 18:37:34.140698 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9617 18:37:34.190628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9618 18:37:34.191460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9620 18:37:34.244477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9621 18:37:34.244796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9623 18:37:34.287388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9624 18:37:34.287696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9626 18:37:34.330909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9627 18:37:34.331737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9629 18:37:34.381678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9630 18:37:34.382542 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9632 18:37:34.429211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9633 18:37:34.429737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9635 18:37:34.470992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9636 18:37:34.471302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9638 18:37:34.509279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9639 18:37:34.509582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9641 18:37:34.555288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9642 18:37:34.555604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9644 18:37:34.599143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9645 18:37:34.599429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9647 18:37:34.640870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9648 18:37:34.641144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9650 18:37:34.679225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9651 18:37:34.679522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9653 18:37:34.721342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9654 18:37:34.721621 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9656 18:37:34.758854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9657 18:37:34.759124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9659 18:37:34.796408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9660 18:37:34.796679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9662 18:37:34.840026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9663 18:37:34.840339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9665 18:37:34.878750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9666 18:37:34.879021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9668 18:37:34.922571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9669 18:37:34.922845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9671 18:37:34.962297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9672 18:37:34.962594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9674 18:37:35.003008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9675 18:37:35.003306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9677 18:37:35.040711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9678 18:37:35.041015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9680 18:37:35.080043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9681 18:37:35.080315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9683 18:37:35.127452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9684 18:37:35.127730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9686 18:37:35.167309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9687 18:37:35.167581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9689 18:37:35.206854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9690 18:37:35.207123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9692 18:37:35.247717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9693 18:37:35.248018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9695 18:37:35.289899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9696 18:37:35.290208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9698 18:37:35.333063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9699 18:37:35.333369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9701 18:37:35.367213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9702 18:37:35.367483 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9704 18:37:35.405507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9705 18:37:35.405775 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9707 18:37:35.445829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9708 18:37:35.446133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9710 18:37:35.483872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9711 18:37:35.484153 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9713 18:37:35.523958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9714 18:37:35.524274 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9716 18:37:35.565815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9717 18:37:35.566347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9719 18:37:35.611176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9720 18:37:35.611519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9722 18:37:35.648151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9723 18:37:35.648450 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9725 18:37:35.692069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9726 18:37:35.692338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9728 18:37:35.737393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9729 18:37:35.737675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9731 18:37:35.780856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9732 18:37:35.781147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9734 18:37:35.823144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9735 18:37:35.823431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9737 18:37:35.867010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9738 18:37:35.867282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9740 18:37:35.913861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9741 18:37:35.914166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9743 18:37:35.957953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9744 18:37:35.958224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9746 18:37:36.007893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9747 18:37:36.008165 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9749 18:37:36.051556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9750 18:37:36.051831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9752 18:37:36.093819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9753 18:37:36.094089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9755 18:37:36.141024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9756 18:37:36.141328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9758 18:37:36.186377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9759 18:37:36.186669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9761 18:37:36.227361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9762 18:37:36.227670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9764 18:37:36.267040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9765 18:37:36.267308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9767 18:37:36.317146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9768 18:37:36.317423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9770 18:37:36.359529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9771 18:37:36.359817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9773 18:37:36.400499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9774 18:37:36.400781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9776 18:37:36.449742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9777 18:37:36.450032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9779 18:37:36.495113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9780 18:37:36.495443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9782 18:37:36.543257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9783 18:37:36.543560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9785 18:37:36.579172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9786 18:37:36.579430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9788 18:37:36.627380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9789 18:37:36.627667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9791 18:37:36.671111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9792 18:37:36.671378 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9794 18:37:36.717595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9795 18:37:36.717872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9797 18:37:36.763472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9798 18:37:36.763985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9800 18:37:36.818233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9801 18:37:36.818929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9803 18:37:36.871975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9804 18:37:36.872654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9806 18:37:36.923773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9807 18:37:36.924459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9809 18:37:36.978607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9810 18:37:36.979303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9812 18:37:37.026921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9813 18:37:37.027608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9815 18:37:37.079447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9816 18:37:37.080149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9818 18:37:37.134418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9819 18:37:37.135163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9821 18:37:37.184339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9822 18:37:37.185046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9824 18:37:37.235318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9825 18:37:37.236052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9827 18:37:37.283386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9828 18:37:37.284101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9830 18:37:37.338579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9831 18:37:37.338856 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9833 18:37:37.387334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9834 18:37:37.387662 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9836 18:37:37.434240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9837 18:37:37.434568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9839 18:37:37.480313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9840 18:37:37.480589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9842 18:37:37.524750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9843 18:37:37.525040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9845 18:37:37.571622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9846 18:37:37.572188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9848 18:37:37.611114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9849 18:37:37.611400 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9851 18:37:37.655008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9852 18:37:37.655316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9854 18:37:37.695053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9855 18:37:37.695357 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9857 18:37:37.734474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9858 18:37:37.734753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9860 18:37:37.772292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9861 18:37:37.772563 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9863 18:37:37.811525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9864 18:37:37.811799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9866 18:37:37.850031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9867 18:37:37.850310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9869 18:37:37.883424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9870 18:37:37.883692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9872 18:37:37.923164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9873 18:37:37.923432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9875 18:37:37.957885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9876 18:37:37.958185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9878 18:37:37.991328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9879 18:37:37.991613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9881 18:37:38.026380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9882 18:37:38.026691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9884 18:37:38.061638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9885 18:37:38.061939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9887 18:37:38.096334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9888 18:37:38.096629 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9890 18:37:38.129689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9891 18:37:38.130069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9893 18:37:38.178325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9894 18:37:38.178595 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9896 18:37:38.221092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9897 18:37:38.221811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9899 18:37:38.272993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9900 18:37:38.273835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9902 18:37:38.328216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9903 18:37:38.328939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9905 18:37:38.380210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9906 18:37:38.380908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9908 18:37:38.434995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9909 18:37:38.435806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9911 18:37:38.488321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9912 18:37:38.489063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9914 18:37:38.545817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9915 18:37:38.546545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9917 18:37:38.600078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9918 18:37:38.600848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9920 18:37:38.654457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9921 18:37:38.655556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9923 18:37:38.699736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9924 18:37:38.700487 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9926 18:37:38.749344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9927 18:37:38.749639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9929 18:37:38.794598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9930 18:37:38.794875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9932 18:37:38.837011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9933 18:37:38.837299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9935 18:37:38.885849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9936 18:37:38.886124 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9938 18:37:38.929419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9939 18:37:38.929692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9941 18:37:38.977891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9942 18:37:38.978180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9944 18:37:39.023123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9945 18:37:39.023424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9947 18:37:39.068229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9948 18:37:39.068521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9950 18:37:39.115024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9951 18:37:39.115343 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9953 18:37:39.160784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9954 18:37:39.161057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9956 18:37:39.211033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9957 18:37:39.211303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9959 18:37:39.256172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9960 18:37:39.256440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9962 18:37:39.302901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9963 18:37:39.303171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9965 18:37:39.350915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9966 18:37:39.351190 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9968 18:37:39.401845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9969 18:37:39.402123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9971 18:37:39.450946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9972 18:37:39.451224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9974 18:37:39.489751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9975 18:37:39.490024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9977 18:37:39.552422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9978 18:37:39.553197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9980 18:37:39.611042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9981 18:37:39.611380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9983 18:37:39.661719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9984 18:37:39.661992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9986 18:37:39.708637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9987 18:37:39.708923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9989 18:37:39.756623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
9990 18:37:39.757136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
9992 18:37:39.810774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
9993 18:37:39.811679 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
9995 18:37:39.856954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
9996 18:37:39.857499 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
9998 18:37:39.912526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
9999 18:37:39.913061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
10001 18:37:39.966167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
10002 18:37:39.966881 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
10004 18:37:40.022929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
10005 18:37:40.023676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
10007 18:37:40.078740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
10008 18:37:40.079533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
10010 18:37:40.139286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
10011 18:37:40.140069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
10013 18:37:40.198693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
10014 18:37:40.199474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
10016 18:37:40.254600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
10017 18:37:40.255394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
10019 18:37:40.317822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
10020 18:37:40.318162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
10022 18:37:40.367375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
10023 18:37:40.367656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
10025 18:37:40.413116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
10026 18:37:40.413385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10028 18:37:40.456575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10029 18:37:40.456934 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10031 18:37:40.510353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10032 18:37:40.510998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10034 18:37:40.562504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10035 18:37:40.563233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10037 18:37:40.607101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10038 18:37:40.607388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10040 18:37:40.653928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10041 18:37:40.654701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10043 18:37:40.701718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10044 18:37:40.701986 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10046 18:37:40.746876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10047 18:37:40.747232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10049 18:37:40.794709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10050 18:37:40.794977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10052 18:37:40.834962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10053 18:37:40.835273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10055 18:37:40.872448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10056 18:37:40.872715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10058 18:37:40.911798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10059 18:37:40.912134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10061 18:37:40.965385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10062 18:37:40.966064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10064 18:37:41.016343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10065 18:37:41.016715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10067 18:37:41.067930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10068 18:37:41.068531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10070 18:37:41.122165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10071 18:37:41.122858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10073 18:37:41.181364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10074 18:37:41.182044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10076 18:37:41.236108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10077 18:37:41.236781 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10079 18:37:41.285019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10080 18:37:41.285714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10082 18:37:41.338963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10083 18:37:41.339783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10085 18:37:41.396912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10086 18:37:41.397673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10088 18:37:41.451537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10089 18:37:41.452254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10091 18:37:41.504973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10092 18:37:41.505643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10094 18:37:41.565904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10095 18:37:41.566632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10097 18:37:41.624146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10098 18:37:41.624833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10100 18:37:41.672600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10101 18:37:41.673280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10103 18:37:41.732320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10104 18:37:41.733029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10106 18:37:41.783229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10107 18:37:41.783972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10109 18:37:41.834575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10110 18:37:41.835264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10112 18:37:41.886672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10113 18:37:41.887354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10115 18:37:41.933141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10116 18:37:41.933430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10118 18:37:41.968092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10119 18:37:41.968382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10121 18:37:42.006779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10122 18:37:42.007640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10124 18:37:42.059346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10125 18:37:42.060082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10127 18:37:42.108441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10128 18:37:42.109117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10130 18:37:42.158935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10131 18:37:42.159620 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10133 18:37:42.212778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10134 18:37:42.213561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10136 18:37:42.268044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10137 18:37:42.268730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10139 18:37:42.317601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10140 18:37:42.318019 + set +x
10141 18:37:42.318598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10143 18:37:42.324625 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14291342_1.6.2.3.5>
10144 18:37:42.325391 Received signal: <ENDRUN> 1_kselftest-alsa 14291342_1.6.2.3.5
10145 18:37:42.325771 Ending use of test pattern.
10146 18:37:42.326083 Ending test lava.1_kselftest-alsa (14291342_1.6.2.3.5), duration 45.41
10148 18:37:42.327934 <LAVA_TEST_RUNNER EXIT>
10149 18:37:42.328642 ok: lava_test_shell seems to have completed
10150 18:37:42.345877 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
10151 18:37:42.347856 end: 3.1 lava-test-shell (duration 00:00:46) [common]
10152 18:37:42.348494 end: 3 lava-test-retry (duration 00:00:46) [common]
10153 18:37:42.348943 start: 4 finalize (timeout 00:07:30) [common]
10154 18:37:42.349379 start: 4.1 power-off (timeout 00:00:30) [common]
10155 18:37:42.350129 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
10156 18:37:43.938895 >> Command sent successfully.
10157 18:37:43.941371 Returned 0 in 1 seconds
10158 18:37:44.042185 end: 4.1 power-off (duration 00:00:02) [common]
10160 18:37:44.043540 start: 4.2 read-feedback (timeout 00:07:28) [common]
10161 18:37:44.044881 Listened to connection for namespace 'common' for up to 1s
10162 18:37:45.045440 Finalising connection for namespace 'common'
10163 18:37:45.046060 Disconnecting from shell: Finalise
10164 18:37:45.046490 / #
10165 18:37:45.147480 end: 4.2 read-feedback (duration 00:00:01) [common]
10166 18:37:45.148244 end: 4 finalize (duration 00:00:03) [common]
10167 18:37:45.148872 Cleaning after the job
10168 18:37:45.149407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/ramdisk
10169 18:37:45.158602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/kernel
10170 18:37:45.188509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/dtb
10171 18:37:45.188852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/nfsrootfs
10172 18:37:45.259016 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291342/tftp-deploy-s8lw49u8/modules
10173 18:37:45.265143 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291342
10174 18:37:45.908350 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291342
10175 18:37:45.908547 Job finished correctly