Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 54
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 91
1 18:39:30.186645 lava-dispatcher, installed at version: 2024.03
2 18:39:30.186870 start: 0 validate
3 18:39:30.187022 Start time: 2024-06-11 18:39:30.187014+00:00 (UTC)
4 18:39:30.187165 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:39:30.187424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:39:30.462816 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:39:30.463066 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:39:30.736201 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:39:30.736394 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 18:39:31.009288 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:39:31.009470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:39:31.282115 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:39:31.282321 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:39:31.556637 validate duration: 1.37
16 18:39:31.556948 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:39:31.557066 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:39:31.557162 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:39:31.557299 Not decompressing ramdisk as can be used compressed.
20 18:39:31.557392 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:39:31.557475 saving as /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/ramdisk/initrd.cpio.gz
22 18:39:31.557551 total size: 5628169 (5 MB)
23 18:39:31.558707 progress 0 % (0 MB)
24 18:39:31.560692 progress 5 % (0 MB)
25 18:39:31.562446 progress 10 % (0 MB)
26 18:39:31.564006 progress 15 % (0 MB)
27 18:39:31.565744 progress 20 % (1 MB)
28 18:39:31.567331 progress 25 % (1 MB)
29 18:39:31.569071 progress 30 % (1 MB)
30 18:39:31.570785 progress 35 % (1 MB)
31 18:39:31.572321 progress 40 % (2 MB)
32 18:39:31.574054 progress 45 % (2 MB)
33 18:39:31.575568 progress 50 % (2 MB)
34 18:39:31.577311 progress 55 % (2 MB)
35 18:39:31.579047 progress 60 % (3 MB)
36 18:39:31.580584 progress 65 % (3 MB)
37 18:39:31.582314 progress 70 % (3 MB)
38 18:39:31.583840 progress 75 % (4 MB)
39 18:39:31.585558 progress 80 % (4 MB)
40 18:39:31.587079 progress 85 % (4 MB)
41 18:39:31.588839 progress 90 % (4 MB)
42 18:39:31.590543 progress 95 % (5 MB)
43 18:39:31.592091 progress 100 % (5 MB)
44 18:39:31.592321 5 MB downloaded in 0.03 s (154.36 MB/s)
45 18:39:31.592485 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:39:31.592762 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:39:31.592857 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:39:31.592950 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:39:31.593100 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:39:31.593182 saving as /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/kernel/Image
52 18:39:31.593250 total size: 54813184 (52 MB)
53 18:39:31.593322 No compression specified
54 18:39:31.594551 progress 0 % (0 MB)
55 18:39:31.610014 progress 5 % (2 MB)
56 18:39:31.625538 progress 10 % (5 MB)
57 18:39:31.641024 progress 15 % (7 MB)
58 18:39:31.656729 progress 20 % (10 MB)
59 18:39:31.672305 progress 25 % (13 MB)
60 18:39:31.687694 progress 30 % (15 MB)
61 18:39:31.703318 progress 35 % (18 MB)
62 18:39:31.718877 progress 40 % (20 MB)
63 18:39:31.734304 progress 45 % (23 MB)
64 18:39:31.749896 progress 50 % (26 MB)
65 18:39:31.765532 progress 55 % (28 MB)
66 18:39:31.780767 progress 60 % (31 MB)
67 18:39:31.796181 progress 65 % (34 MB)
68 18:39:31.811468 progress 70 % (36 MB)
69 18:39:31.827005 progress 75 % (39 MB)
70 18:39:31.842592 progress 80 % (41 MB)
71 18:39:31.857979 progress 85 % (44 MB)
72 18:39:31.873615 progress 90 % (47 MB)
73 18:39:31.888903 progress 95 % (49 MB)
74 18:39:31.903907 progress 100 % (52 MB)
75 18:39:31.904172 52 MB downloaded in 0.31 s (168.13 MB/s)
76 18:39:31.904337 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:39:31.904594 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:39:31.904690 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:39:31.904784 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:39:31.904934 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 18:39:31.905011 saving as /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 18:39:31.905078 total size: 57695 (0 MB)
84 18:39:31.905145 No compression specified
85 18:39:31.906392 progress 56 % (0 MB)
86 18:39:31.906696 progress 100 % (0 MB)
87 18:39:31.906921 0 MB downloaded in 0.00 s (29.91 MB/s)
88 18:39:31.907055 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:39:31.907308 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:39:31.907402 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:39:31.907494 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:39:31.907620 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:39:31.907695 saving as /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/nfsrootfs/full.rootfs.tar
95 18:39:31.907762 total size: 120894716 (115 MB)
96 18:39:31.907829 Using unxz to decompress xz
97 18:39:31.912163 progress 0 % (0 MB)
98 18:39:32.292131 progress 5 % (5 MB)
99 18:39:32.683304 progress 10 % (11 MB)
100 18:39:33.074275 progress 15 % (17 MB)
101 18:39:33.436115 progress 20 % (23 MB)
102 18:39:33.761676 progress 25 % (28 MB)
103 18:39:34.162013 progress 30 % (34 MB)
104 18:39:34.538288 progress 35 % (40 MB)
105 18:39:34.721313 progress 40 % (46 MB)
106 18:39:34.918433 progress 45 % (51 MB)
107 18:39:35.259297 progress 50 % (57 MB)
108 18:39:35.671666 progress 55 % (63 MB)
109 18:39:36.049668 progress 60 % (69 MB)
110 18:39:36.424413 progress 65 % (74 MB)
111 18:39:36.804554 progress 70 % (80 MB)
112 18:39:37.197631 progress 75 % (86 MB)
113 18:39:37.572547 progress 80 % (92 MB)
114 18:39:37.946952 progress 85 % (98 MB)
115 18:39:38.343924 progress 90 % (103 MB)
116 18:39:38.702373 progress 95 % (109 MB)
117 18:39:39.093213 progress 100 % (115 MB)
118 18:39:39.099056 115 MB downloaded in 7.19 s (16.03 MB/s)
119 18:39:39.099352 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:39:39.099646 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:39:39.099750 start: 1.5 download-retry (timeout 00:09:52) [common]
123 18:39:39.099846 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 18:39:39.100017 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:39:39.100099 saving as /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/modules/modules.tar
126 18:39:39.100165 total size: 8618176 (8 MB)
127 18:39:39.100236 Using unxz to decompress xz
128 18:39:39.104612 progress 0 % (0 MB)
129 18:39:39.125469 progress 5 % (0 MB)
130 18:39:39.155779 progress 10 % (0 MB)
131 18:39:39.188626 progress 15 % (1 MB)
132 18:39:39.215175 progress 20 % (1 MB)
133 18:39:39.241298 progress 25 % (2 MB)
134 18:39:39.268341 progress 30 % (2 MB)
135 18:39:39.298711 progress 35 % (2 MB)
136 18:39:39.328076 progress 40 % (3 MB)
137 18:39:39.355487 progress 45 % (3 MB)
138 18:39:39.384622 progress 50 % (4 MB)
139 18:39:39.414159 progress 55 % (4 MB)
140 18:39:39.443254 progress 60 % (4 MB)
141 18:39:39.472750 progress 65 % (5 MB)
142 18:39:39.504862 progress 70 % (5 MB)
143 18:39:39.531669 progress 75 % (6 MB)
144 18:39:39.560523 progress 80 % (6 MB)
145 18:39:39.587600 progress 85 % (7 MB)
146 18:39:39.615799 progress 90 % (7 MB)
147 18:39:39.643980 progress 95 % (7 MB)
148 18:39:39.673865 progress 100 % (8 MB)
149 18:39:39.678716 8 MB downloaded in 0.58 s (14.21 MB/s)
150 18:39:39.679002 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:39:39.679300 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:39:39.679405 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:39:39.679510 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:39:43.519211 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs
156 18:39:43.519432 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:39:43.519548 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 18:39:43.519736 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc
159 18:39:43.519881 makedir: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin
160 18:39:43.519993 makedir: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/tests
161 18:39:43.520103 makedir: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/results
162 18:39:43.520214 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-add-keys
163 18:39:43.520373 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-add-sources
164 18:39:43.520516 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-background-process-start
165 18:39:43.520660 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-background-process-stop
166 18:39:43.520800 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-common-functions
167 18:39:43.520939 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-echo-ipv4
168 18:39:43.521079 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-install-packages
169 18:39:43.521219 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-installed-packages
170 18:39:43.521359 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-os-build
171 18:39:43.521604 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-probe-channel
172 18:39:43.521748 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-probe-ip
173 18:39:43.521890 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-target-ip
174 18:39:43.522030 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-target-mac
175 18:39:43.522170 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-target-storage
176 18:39:43.522311 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-case
177 18:39:43.522452 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-event
178 18:39:43.522589 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-feedback
179 18:39:43.522729 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-raise
180 18:39:43.522866 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-reference
181 18:39:43.523007 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-runner
182 18:39:43.523144 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-set
183 18:39:43.523282 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-test-shell
184 18:39:43.523421 Updating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-add-keys (debian)
185 18:39:43.523589 Updating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-add-sources (debian)
186 18:39:43.523754 Updating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-install-packages (debian)
187 18:39:43.523912 Updating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-installed-packages (debian)
188 18:39:43.524067 Updating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/bin/lava-os-build (debian)
189 18:39:43.524199 Creating /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/environment
190 18:39:43.524310 LAVA metadata
191 18:39:43.524383 - LAVA_JOB_ID=14291499
192 18:39:43.524452 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:39:43.524561 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 18:39:43.524634 skipped lava-vland-overlay
195 18:39:43.524715 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:39:43.524803 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 18:39:43.524871 skipped lava-multinode-overlay
198 18:39:43.524950 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:39:43.525034 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 18:39:43.525114 Loading test definitions
201 18:39:43.525210 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 18:39:43.525287 Using /lava-14291499 at stage 0
203 18:39:43.525598 uuid=14291499_1.6.2.3.1 testdef=None
204 18:39:43.525696 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:39:43.525788 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 18:39:43.526294 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:39:43.526538 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 18:39:43.527150 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:39:43.527404 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 18:39:43.527999 runner path: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/0/tests/0_timesync-off test_uuid 14291499_1.6.2.3.1
213 18:39:43.528174 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:39:43.528421 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 18:39:43.528501 Using /lava-14291499 at stage 0
217 18:39:43.528607 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:39:43.528702 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/0/tests/1_kselftest-arm64'
219 18:39:45.529365 Running '/usr/bin/git checkout kernelci.org
220 18:39:45.696975 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 18:39:45.697800 uuid=14291499_1.6.2.3.5 testdef=None
222 18:39:45.697989 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:39:45.698290 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 18:39:45.699146 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:39:45.699409 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 18:39:45.700512 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:39:45.700802 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 18:39:45.701971 runner path: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/0/tests/1_kselftest-arm64 test_uuid 14291499_1.6.2.3.5
232 18:39:45.702074 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 18:39:45.702146 BRANCH='cip'
234 18:39:45.702213 SKIPFILE='/dev/null'
235 18:39:45.702279 SKIP_INSTALL='True'
236 18:39:45.702342 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:39:45.702405 TST_CASENAME=''
238 18:39:45.702474 TST_CMDFILES='arm64'
239 18:39:45.702632 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:39:45.702858 Creating lava-test-runner.conf files
242 18:39:45.702930 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291499/lava-overlay-9bn67atc/lava-14291499/0 for stage 0
243 18:39:45.703033 - 0_timesync-off
244 18:39:45.703107 - 1_kselftest-arm64
245 18:39:45.703214 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:39:45.703317 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 18:39:54.045665 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:39:54.045845 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 18:39:54.045961 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:39:54.046087 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 18:39:54.046203 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 18:39:54.227022 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:39:54.227464 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 18:39:54.227613 extracting modules file /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs
255 18:39:54.464697 extracting modules file /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291499/extract-overlay-ramdisk-4xf9g2nw/ramdisk
256 18:39:54.707947 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:39:54.708137 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 18:39:54.708252 [common] Applying overlay to NFS
259 18:39:54.708333 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291499/compress-overlay-34kyy2rq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs
260 18:39:55.730349 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:39:55.730518 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 18:39:55.730624 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:39:55.730721 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 18:39:55.730813 Building ramdisk /var/lib/lava/dispatcher/tmp/14291499/extract-overlay-ramdisk-4xf9g2nw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291499/extract-overlay-ramdisk-4xf9g2nw/ramdisk
265 18:39:56.091074 >> 130400 blocks
266 18:39:58.316220 rename /var/lib/lava/dispatcher/tmp/14291499/extract-overlay-ramdisk-4xf9g2nw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/ramdisk/ramdisk.cpio.gz
267 18:39:58.316699 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 18:39:58.316837 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 18:39:58.316946 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 18:39:58.317062 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/kernel/Image']
271 18:40:12.596595 Returned 0 in 14 seconds
272 18:40:12.697605 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/kernel/image.itb
273 18:40:13.113471 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:40:13.113927 output: Created: Tue Jun 11 19:40:13 2024
275 18:40:13.114015 output: Image 0 (kernel-1)
276 18:40:13.114091 output: Description:
277 18:40:13.114160 output: Created: Tue Jun 11 19:40:13 2024
278 18:40:13.114231 output: Type: Kernel Image
279 18:40:13.114297 output: Compression: lzma compressed
280 18:40:13.114364 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:40:13.114430 output: Architecture: AArch64
282 18:40:13.114495 output: OS: Linux
283 18:40:13.114557 output: Load Address: 0x00000000
284 18:40:13.114616 output: Entry Point: 0x00000000
285 18:40:13.114675 output: Hash algo: crc32
286 18:40:13.114736 output: Hash value: 7a9e9d3e
287 18:40:13.114795 output: Image 1 (fdt-1)
288 18:40:13.114855 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 18:40:13.114916 output: Created: Tue Jun 11 19:40:13 2024
290 18:40:13.114979 output: Type: Flat Device Tree
291 18:40:13.115038 output: Compression: uncompressed
292 18:40:13.115096 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 18:40:13.115155 output: Architecture: AArch64
294 18:40:13.115213 output: Hash algo: crc32
295 18:40:13.115271 output: Hash value: a9713552
296 18:40:13.115329 output: Image 2 (ramdisk-1)
297 18:40:13.115388 output: Description: unavailable
298 18:40:13.115446 output: Created: Tue Jun 11 19:40:13 2024
299 18:40:13.115504 output: Type: RAMDisk Image
300 18:40:13.115563 output: Compression: Unknown Compression
301 18:40:13.115621 output: Data Size: 18734302 Bytes = 18295.22 KiB = 17.87 MiB
302 18:40:13.115680 output: Architecture: AArch64
303 18:40:13.115737 output: OS: Linux
304 18:40:13.115796 output: Load Address: unavailable
305 18:40:13.115853 output: Entry Point: unavailable
306 18:40:13.115910 output: Hash algo: crc32
307 18:40:13.115967 output: Hash value: afd67aeb
308 18:40:13.116024 output: Default Configuration: 'conf-1'
309 18:40:13.116097 output: Configuration 0 (conf-1)
310 18:40:13.116156 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 18:40:13.116215 output: Kernel: kernel-1
312 18:40:13.116273 output: Init Ramdisk: ramdisk-1
313 18:40:13.116330 output: FDT: fdt-1
314 18:40:13.116389 output: Loadables: kernel-1
315 18:40:13.116447 output:
316 18:40:13.116672 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 18:40:13.116784 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 18:40:13.116909 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 18:40:13.117016 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 18:40:13.117107 No LXC device requested
321 18:40:13.117195 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:40:13.117294 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 18:40:13.117380 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:40:13.117461 Checking files for TFTP limit of 4294967296 bytes.
325 18:40:13.118018 end: 1 tftp-deploy (duration 00:00:42) [common]
326 18:40:13.118134 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:40:13.118236 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:40:13.118378 substitutions:
329 18:40:13.118454 - {DTB}: 14291499/tftp-deploy-p8e8r9bv/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 18:40:13.118526 - {INITRD}: 14291499/tftp-deploy-p8e8r9bv/ramdisk/ramdisk.cpio.gz
331 18:40:13.118592 - {KERNEL}: 14291499/tftp-deploy-p8e8r9bv/kernel/Image
332 18:40:13.118656 - {LAVA_MAC}: None
333 18:40:13.118723 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs
334 18:40:13.118786 - {NFS_SERVER_IP}: 192.168.201.1
335 18:40:13.118847 - {PRESEED_CONFIG}: None
336 18:40:13.118908 - {PRESEED_LOCAL}: None
337 18:40:13.118968 - {RAMDISK}: 14291499/tftp-deploy-p8e8r9bv/ramdisk/ramdisk.cpio.gz
338 18:40:13.119028 - {ROOT_PART}: None
339 18:40:13.119087 - {ROOT}: None
340 18:40:13.119147 - {SERVER_IP}: 192.168.201.1
341 18:40:13.119206 - {TEE}: None
342 18:40:13.119266 Parsed boot commands:
343 18:40:13.119325 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:40:13.119524 Parsed boot commands: tftpboot 192.168.201.1 14291499/tftp-deploy-p8e8r9bv/kernel/image.itb 14291499/tftp-deploy-p8e8r9bv/kernel/cmdline
345 18:40:13.119620 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:40:13.119712 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:40:13.119816 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:40:13.119909 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:40:13.119988 Not connected, no need to disconnect.
350 18:40:13.120068 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:40:13.120161 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:40:13.120235 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-2'
353 18:40:13.124242 Setting prompt string to ['lava-test: # ']
354 18:40:13.124651 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:40:13.124774 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:40:13.124875 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:40:13.124978 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:40:13.125176 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-2']
359 18:40:36.338161 Returned 0 in 23 seconds
360 18:40:36.439198 end: 2.2.2.1 pdu-reboot (duration 00:00:23) [common]
362 18:40:36.440565 end: 2.2.2 reset-device (duration 00:00:23) [common]
363 18:40:36.441047 start: 2.2.3 depthcharge-start (timeout 00:04:37) [common]
364 18:40:36.441527 Setting prompt string to 'Starting depthcharge on Juniper...'
365 18:40:36.441884 Changing prompt to 'Starting depthcharge on Juniper...'
366 18:40:36.442225 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 18:40:36.444008 [Enter `^Ec?' for help]
368 18:40:36.444446 [DL] 00000000 00000000 010701
369 18:40:36.444800
370 18:40:36.445114
371 18:40:36.445423 F0: 102B 0000
372 18:40:36.445768
373 18:40:36.446052 F3: 1006 0033 [0200]
374 18:40:36.446341
375 18:40:36.446627 F3: 4001 00E0 [0200]
376 18:40:36.446902
377 18:40:36.447175 F3: 0000 0000
378 18:40:36.447449
379 18:40:36.447719 V0: 0000 0000 [0001]
380 18:40:36.447988
381 18:40:36.448259 00: 1027 0002
382 18:40:36.448545
383 18:40:36.449010 01: 0000 0000
384 18:40:36.449322
385 18:40:36.449697 BP: 0C00 0251 [0000]
386 18:40:36.449999
387 18:40:36.450275 G0: 1182 0000
388 18:40:36.450546
389 18:40:36.450820 EC: 0004 0000 [0001]
390 18:40:36.451094
391 18:40:36.451365 S7: 0000 0000 [0000]
392 18:40:36.451639
393 18:40:36.451907 CC: 0000 0000 [0001]
394 18:40:36.452179
395 18:40:36.452449 T0: 0000 00DB [000F]
396 18:40:36.452720
397 18:40:36.452990 Jump to BL
398 18:40:36.453260
399 18:40:36.453571
400 18:40:36.453850
401 18:40:36.454123 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 18:40:36.454420 ARM64: Exception handlers installed.
403 18:40:36.454697 ARM64: Testing exception
404 18:40:36.454968 ARM64: Done test exception
405 18:40:36.455238 WDT: Last reset was cold boot
406 18:40:36.455508 SPI0(PAD0) initialized at 992727 Hz
407 18:40:36.455777 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 18:40:36.456051 Manufacturer: ef
409 18:40:36.456322 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 18:40:36.456596 Probing TPM: . done!
411 18:40:36.456865 TPM ready after 0 ms
412 18:40:36.457136 Connected to device vid:did:rid of 1ae0:0028:00
413 18:40:36.457410 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-afa1dd1
414 18:40:36.457723 Initialized TPM device CR50 revision 0
415 18:40:36.457998 tlcl_send_startup: Startup return code is 0
416 18:40:36.458274 TPM: setup succeeded
417 18:40:36.458546 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 18:40:36.458819 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 18:40:36.459093 in-header: 03 19 00 00 08 00 00 00
420 18:40:36.459365 in-data: a2 e0 47 00 13 00 00 00
421 18:40:36.459637 Chrome EC: UHEPI supported
422 18:40:36.459908 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 18:40:36.460184 in-header: 03 a1 00 00 08 00 00 00
424 18:40:36.460454 in-data: 84 60 60 10 00 00 00 00
425 18:40:36.460726 Phase 1
426 18:40:36.460997 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 18:40:36.461272 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 18:40:36.461568 VB2:vb2_check_recovery() Recovery was requested manually
429 18:40:36.461844 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 18:40:36.462119 Recovery requested (1009000e)
431 18:40:36.462389 tlcl_extend: response is 0
432 18:40:36.462659 tlcl_extend: response is 0
433 18:40:36.462927
434 18:40:36.463195
435 18:40:36.463474 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 18:40:36.463754 ARM64: Exception handlers installed.
437 18:40:36.464023 ARM64: Testing exception
438 18:40:36.464291 ARM64: Done test exception
439 18:40:36.464562 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x926b, sec=0x2031
440 18:40:36.464836 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 18:40:36.465106 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 18:40:36.465377 [RTC]rtc_get_frequency_meter,134: input=0xf, output=862
443 18:40:36.465673 [RTC]rtc_get_frequency_meter,134: input=0x7, output=732
444 18:40:36.465946 [RTC]rtc_get_frequency_meter,134: input=0xb, output=796
445 18:40:36.466229 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x926b
446 18:40:36.466503 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
447 18:40:36.466730 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
448 18:40:36.466923 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
449 18:40:36.467114 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
450 18:40:36.467309 in-header: 03 19 00 00 08 00 00 00
451 18:40:36.467502 in-data: a2 e0 47 00 13 00 00 00
452 18:40:36.467693 Chrome EC: UHEPI supported
453 18:40:36.467884 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
454 18:40:36.468079 in-header: 03 a1 00 00 08 00 00 00
455 18:40:36.468272 in-data: 84 60 60 10 00 00 00 00
456 18:40:36.468465 Skip loading cached calibration data
457 18:40:36.468658 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
458 18:40:36.468852 in-header: 03 a1 00 00 08 00 00 00
459 18:40:36.469046 in-data: 84 60 60 10 00 00 00 00
460 18:40:36.469238 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
461 18:40:36.469445 in-header: 03 a1 00 00 08 00 00 00
462 18:40:36.469642 in-data: 84 60 60 10 00 00 00 00
463 18:40:36.469835 ADC[3]: Raw value=216116 ID=1
464 18:40:36.470027 Manufacturer: ef
465 18:40:36.470221 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
466 18:40:36.470416 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
467 18:40:36.470608 CBFS @ 21000 size 3d4000
468 18:40:36.470801 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
469 18:40:36.470996 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
470 18:40:36.471188 CBFS: Found @ offset 3c700 size 44
471 18:40:36.471379 DRAM-K: Full Calibration
472 18:40:36.471573 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
473 18:40:36.471743 CBFS @ 21000 size 3d4000
474 18:40:36.471888 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
475 18:40:36.472034 CBFS: Locating 'fallback/dram'
476 18:40:36.472178 CBFS: Found @ offset 24b00 size 12268
477 18:40:36.472322 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
478 18:40:36.472468 ddr_geometry: 1, config: 0x0
479 18:40:36.472611 header.status = 0x0
480 18:40:36.472756 header.magic = 0x44524d4b (expected: 0x44524d4b)
481 18:40:36.472902 header.version = 0x5 (expected: 0x5)
482 18:40:36.473048 header.size = 0x8f0 (expected: 0x8f0)
483 18:40:36.473192 header.config = 0x0
484 18:40:36.473337 header.flags = 0x0
485 18:40:36.473492 header.checksum = 0x0
486 18:40:36.473638 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
487 18:40:36.473784 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
488 18:40:36.474181 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
489 18:40:36.474353 ddr_geometry:1
490 18:40:36.474508 [EMI] new MDL number = 1
491 18:40:36.474656 dram_cbt_mode_extern: 0
492 18:40:36.474801 dram_cbt_mode [RK0]: 0, [RK1]: 0
493 18:40:36.474947 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
494 18:40:36.475094
495 18:40:36.475240
496 18:40:36.475384 [Bianco] ETT version 0.0.0.1
497 18:40:36.475639 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
498 18:40:36.475827
499 18:40:36.475977 vSetVcoreByFreq with vcore:762500, freq=1600
500 18:40:36.476130
501 18:40:36.476275 [DramcInit]
502 18:40:36.476421 AutoRefreshCKEOff AutoREF OFF
503 18:40:36.476567 DDRPhyPLLSetting-CKEOFF
504 18:40:36.476704 DDRPhyPLLSetting-CKEON
505 18:40:36.476821
506 18:40:36.476936 Enable WDQS
507 18:40:36.477052 [ModeRegInit_LP4] CH0 RK0
508 18:40:36.477169 Write Rank0 MR13 =0x18
509 18:40:36.477284 Write Rank0 MR12 =0x5d
510 18:40:36.477400 Write Rank0 MR1 =0x56
511 18:40:36.477543 Write Rank0 MR2 =0x1a
512 18:40:36.477661 Write Rank0 MR11 =0x0
513 18:40:36.477778 Write Rank0 MR22 =0x38
514 18:40:36.477895 Write Rank0 MR14 =0x5d
515 18:40:36.478012 Write Rank0 MR3 =0x30
516 18:40:36.478128 Write Rank0 MR13 =0x58
517 18:40:36.478244 Write Rank0 MR12 =0x5d
518 18:40:36.478360 Write Rank0 MR1 =0x56
519 18:40:36.478475 Write Rank0 MR2 =0x2d
520 18:40:36.478591 Write Rank0 MR11 =0x23
521 18:40:36.478705 Write Rank0 MR22 =0x34
522 18:40:36.478821 Write Rank0 MR14 =0x10
523 18:40:36.478938 Write Rank0 MR3 =0x30
524 18:40:36.479053 Write Rank0 MR13 =0xd8
525 18:40:36.479169 [ModeRegInit_LP4] CH0 RK1
526 18:40:36.479285 Write Rank1 MR13 =0x18
527 18:40:36.479401 Write Rank1 MR12 =0x5d
528 18:40:36.479516 Write Rank1 MR1 =0x56
529 18:40:36.479632 Write Rank1 MR2 =0x1a
530 18:40:36.479749 Write Rank1 MR11 =0x0
531 18:40:36.479864 Write Rank1 MR22 =0x38
532 18:40:36.479980 Write Rank1 MR14 =0x5d
533 18:40:36.480094 Write Rank1 MR3 =0x30
534 18:40:36.480208 Write Rank1 MR13 =0x58
535 18:40:36.480323 Write Rank1 MR12 =0x5d
536 18:40:36.480439 Write Rank1 MR1 =0x56
537 18:40:36.480554 Write Rank1 MR2 =0x2d
538 18:40:36.480670 Write Rank1 MR11 =0x23
539 18:40:36.480785 Write Rank1 MR22 =0x34
540 18:40:36.480900 Write Rank1 MR14 =0x10
541 18:40:36.481013 Write Rank1 MR3 =0x30
542 18:40:36.481128 Write Rank1 MR13 =0xd8
543 18:40:36.481244 [ModeRegInit_LP4] CH1 RK0
544 18:40:36.481360 Write Rank0 MR13 =0x18
545 18:40:36.481503 Write Rank0 MR12 =0x5d
546 18:40:36.481629 Write Rank0 MR1 =0x56
547 18:40:36.481726 Write Rank0 MR2 =0x1a
548 18:40:36.481823 Write Rank0 MR11 =0x0
549 18:40:36.481919 Write Rank0 MR22 =0x38
550 18:40:36.482015 Write Rank0 MR14 =0x5d
551 18:40:36.482112 Write Rank0 MR3 =0x30
552 18:40:36.482207 Write Rank0 MR13 =0x58
553 18:40:36.482304 Write Rank0 MR12 =0x5d
554 18:40:36.482400 Write Rank0 MR1 =0x56
555 18:40:36.482496 Write Rank0 MR2 =0x2d
556 18:40:36.482593 Write Rank0 MR11 =0x23
557 18:40:36.482690 Write Rank0 MR22 =0x34
558 18:40:36.482786 Write Rank0 MR14 =0x10
559 18:40:36.482883 Write Rank0 MR3 =0x30
560 18:40:36.482979 Write Rank0 MR13 =0xd8
561 18:40:36.483075 [ModeRegInit_LP4] CH1 RK1
562 18:40:36.483173 Write Rank1 MR13 =0x18
563 18:40:36.483270 Write Rank1 MR12 =0x5d
564 18:40:36.483368 Write Rank1 MR1 =0x56
565 18:40:36.483484 Write Rank1 MR2 =0x1a
566 18:40:36.483586 Write Rank1 MR11 =0x0
567 18:40:36.483683 Write Rank1 MR22 =0x38
568 18:40:36.483780 Write Rank1 MR14 =0x5d
569 18:40:36.483877 Write Rank1 MR3 =0x30
570 18:40:36.483974 Write Rank1 MR13 =0x58
571 18:40:36.484071 Write Rank1 MR12 =0x5d
572 18:40:36.484167 Write Rank1 MR1 =0x56
573 18:40:36.484264 Write Rank1 MR2 =0x2d
574 18:40:36.484360 Write Rank1 MR11 =0x23
575 18:40:36.484456 Write Rank1 MR22 =0x34
576 18:40:36.484552 Write Rank1 MR14 =0x10
577 18:40:36.484649 Write Rank1 MR3 =0x30
578 18:40:36.484745 Write Rank1 MR13 =0xd8
579 18:40:36.484842 match AC timing 3
580 18:40:36.484939 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
581 18:40:36.485038 [MiockJmeterHQA]
582 18:40:36.485134 vSetVcoreByFreq with vcore:762500, freq=1600
583 18:40:36.485231
584 18:40:36.485328 MIOCK jitter meter ch=0
585 18:40:36.485427
586 18:40:36.485542 1T = (101-17) = 84 dly cells
587 18:40:36.485644 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 744/100 ps
588 18:40:36.485743 vSetVcoreByFreq with vcore:725000, freq=1200
589 18:40:36.485841
590 18:40:36.485938 MIOCK jitter meter ch=0
591 18:40:36.486035
592 18:40:36.486131 1T = (96-17) = 79 dly cells
593 18:40:36.486231 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
594 18:40:36.486329 vSetVcoreByFreq with vcore:725000, freq=800
595 18:40:36.486426
596 18:40:36.486523 MIOCK jitter meter ch=0
597 18:40:36.486631
598 18:40:36.486714 1T = (96-17) = 79 dly cells
599 18:40:36.486800 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 791/100 ps
600 18:40:36.486884 vSetVcoreByFreq with vcore:762500, freq=1600
601 18:40:36.486968 vSetVcoreByFreq with vcore:762500, freq=1600
602 18:40:36.487050
603 18:40:36.487133 K DRVP
604 18:40:36.487216 1. OCD DRVP=0 CALOUT=0
605 18:40:36.487302 1. OCD DRVP=1 CALOUT=0
606 18:40:36.487387 1. OCD DRVP=2 CALOUT=0
607 18:40:36.487471 1. OCD DRVP=3 CALOUT=0
608 18:40:36.487599 1. OCD DRVP=4 CALOUT=0
609 18:40:36.487719 1. OCD DRVP=5 CALOUT=0
610 18:40:36.487806 1. OCD DRVP=6 CALOUT=0
611 18:40:36.487892 1. OCD DRVP=7 CALOUT=0
612 18:40:36.487977 1. OCD DRVP=8 CALOUT=1
613 18:40:36.488061
614 18:40:36.488146 1. OCD DRVP calibration OK! DRVP=8
615 18:40:36.488231
616 18:40:36.488315
617 18:40:36.488398
618 18:40:36.488480 K ODTN
619 18:40:36.488563 3. OCD ODTN=0 ,CALOUT=1
620 18:40:36.488652 3. OCD ODTN=1 ,CALOUT=1
621 18:40:36.488736 3. OCD ODTN=2 ,CALOUT=1
622 18:40:36.488821 3. OCD ODTN=3 ,CALOUT=1
623 18:40:36.488906 3. OCD ODTN=4 ,CALOUT=1
624 18:40:36.488991 3. OCD ODTN=5 ,CALOUT=1
625 18:40:36.489076 3. OCD ODTN=6 ,CALOUT=1
626 18:40:36.489161 3. OCD ODTN=7 ,CALOUT=0
627 18:40:36.489246
628 18:40:36.489328 3. OCD ODTN calibration OK! ODTN=7
629 18:40:36.489413
630 18:40:36.489509 [SwImpedanceCal] DRVP=8, DRVN=9, ODTN=7
631 18:40:36.489595 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15
632 18:40:36.489680 term_option=0, Reg: DRVP=8, DRVN=7, ODTN=15 (After Adjust)
633 18:40:36.489763
634 18:40:36.489845 K DRVP
635 18:40:36.489927 1. OCD DRVP=0 CALOUT=0
636 18:40:36.490012 1. OCD DRVP=1 CALOUT=0
637 18:40:36.490096 1. OCD DRVP=2 CALOUT=0
638 18:40:36.490180 1. OCD DRVP=3 CALOUT=0
639 18:40:36.490264 1. OCD DRVP=4 CALOUT=0
640 18:40:36.490348 1. OCD DRVP=5 CALOUT=0
641 18:40:36.490432 1. OCD DRVP=6 CALOUT=0
642 18:40:36.490517 1. OCD DRVP=7 CALOUT=0
643 18:40:36.490602 1. OCD DRVP=8 CALOUT=0
644 18:40:36.490686 1. OCD DRVP=9 CALOUT=0
645 18:40:36.490770 1. OCD DRVP=10 CALOUT=1
646 18:40:36.490854
647 18:40:36.490937 1. OCD DRVP calibration OK! DRVP=10
648 18:40:36.491022
649 18:40:36.491104
650 18:40:36.491186
651 18:40:36.491268 K ODTN
652 18:40:36.491351 3. OCD ODTN=0 ,CALOUT=1
653 18:40:36.491435 3. OCD ODTN=1 ,CALOUT=1
654 18:40:36.491519 3. OCD ODTN=2 ,CALOUT=1
655 18:40:36.491603 3. OCD ODTN=3 ,CALOUT=1
656 18:40:36.491691 3. OCD ODTN=4 ,CALOUT=1
657 18:40:36.491765 3. OCD ODTN=5 ,CALOUT=1
658 18:40:36.491839 3. OCD ODTN=6 ,CALOUT=1
659 18:40:36.492115 3. OCD ODTN=7 ,CALOUT=1
660 18:40:36.492198 3. OCD ODTN=8 ,CALOUT=1
661 18:40:36.492273 3. OCD ODTN=9 ,CALOUT=1
662 18:40:36.492348 3. OCD ODTN=10 ,CALOUT=1
663 18:40:36.492423 3. OCD ODTN=11 ,CALOUT=1
664 18:40:36.492497 3. OCD ODTN=12 ,CALOUT=1
665 18:40:36.492572 3. OCD ODTN=13 ,CALOUT=1
666 18:40:36.492646 3. OCD ODTN=14 ,CALOUT=1
667 18:40:36.492721 3. OCD ODTN=15 ,CALOUT=0
668 18:40:36.492796
669 18:40:36.492869 3. OCD ODTN calibration OK! ODTN=15
670 18:40:36.492944
671 18:40:36.493017 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
672 18:40:36.493090 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
673 18:40:36.493164 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
674 18:40:36.493237
675 18:40:36.493310 [DramcInit]
676 18:40:36.493381 AutoRefreshCKEOff AutoREF OFF
677 18:40:36.493465 DDRPhyPLLSetting-CKEOFF
678 18:40:36.493540 DDRPhyPLLSetting-CKEON
679 18:40:36.493612
680 18:40:36.493684 Enable WDQS
681 18:40:36.493756 ==
682 18:40:36.493829 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
683 18:40:36.493902 fsp= 1, odt_onoff= 1, Byte mode= 0
684 18:40:36.493976 ==
685 18:40:36.494048 [Duty_Offset_Calibration]
686 18:40:36.494121
687 18:40:36.494193 ===========================
688 18:40:36.494267 B0:1 B1:-1 CA:0
689 18:40:36.494339 ==
690 18:40:36.494412 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
691 18:40:36.494485 fsp= 1, odt_onoff= 1, Byte mode= 0
692 18:40:36.494558 ==
693 18:40:36.494630 [Duty_Offset_Calibration]
694 18:40:36.494703
695 18:40:36.494776 ===========================
696 18:40:36.494848 B0:0 B1:0 CA:0
697 18:40:36.494921 [ModeRegInit_LP4] CH0 RK0
698 18:40:36.494993 Write Rank0 MR13 =0x18
699 18:40:36.495066 Write Rank0 MR12 =0x5d
700 18:40:36.495137 Write Rank0 MR1 =0x56
701 18:40:36.495209 Write Rank0 MR2 =0x1a
702 18:40:36.495281 Write Rank0 MR11 =0x0
703 18:40:36.495353 Write Rank0 MR22 =0x38
704 18:40:36.495425 Write Rank0 MR14 =0x5d
705 18:40:36.495497 Write Rank0 MR3 =0x30
706 18:40:36.495568 Write Rank0 MR13 =0x58
707 18:40:36.495640 Write Rank0 MR12 =0x5d
708 18:40:36.495712 Write Rank0 MR1 =0x56
709 18:40:36.495783 Write Rank0 MR2 =0x2d
710 18:40:36.495855 Write Rank0 MR11 =0x23
711 18:40:36.495927 Write Rank0 MR22 =0x34
712 18:40:36.495999 Write Rank0 MR14 =0x10
713 18:40:36.496071 Write Rank0 MR3 =0x30
714 18:40:36.496144 Write Rank0 MR13 =0xd8
715 18:40:36.496217 [ModeRegInit_LP4] CH0 RK1
716 18:40:36.496289 Write Rank1 MR13 =0x18
717 18:40:36.496361 Write Rank1 MR12 =0x5d
718 18:40:36.496434 Write Rank1 MR1 =0x56
719 18:40:36.496506 Write Rank1 MR2 =0x1a
720 18:40:36.496579 Write Rank1 MR11 =0x0
721 18:40:36.496661 Write Rank1 MR22 =0x38
722 18:40:36.496725 Write Rank1 MR14 =0x5d
723 18:40:36.496788 Write Rank1 MR3 =0x30
724 18:40:36.496853 Write Rank1 MR13 =0x58
725 18:40:36.496917 Write Rank1 MR12 =0x5d
726 18:40:36.496980 Write Rank1 MR1 =0x56
727 18:40:36.497044 Write Rank1 MR2 =0x2d
728 18:40:36.497108 Write Rank1 MR11 =0x23
729 18:40:36.497171 Write Rank1 MR22 =0x34
730 18:40:36.497236 Write Rank1 MR14 =0x10
731 18:40:36.497299 Write Rank1 MR3 =0x30
732 18:40:36.497363 Write Rank1 MR13 =0xd8
733 18:40:36.497426 [ModeRegInit_LP4] CH1 RK0
734 18:40:36.497503 Write Rank0 MR13 =0x18
735 18:40:36.497568 Write Rank0 MR12 =0x5d
736 18:40:36.497632 Write Rank0 MR1 =0x56
737 18:40:36.497695 Write Rank0 MR2 =0x1a
738 18:40:36.497759 Write Rank0 MR11 =0x0
739 18:40:36.497824 Write Rank0 MR22 =0x38
740 18:40:36.497888 Write Rank0 MR14 =0x5d
741 18:40:36.497951 Write Rank0 MR3 =0x30
742 18:40:36.498015 Write Rank0 MR13 =0x58
743 18:40:36.498079 Write Rank0 MR12 =0x5d
744 18:40:36.498144 Write Rank0 MR1 =0x56
745 18:40:36.498208 Write Rank0 MR2 =0x2d
746 18:40:36.498272 Write Rank0 MR11 =0x23
747 18:40:36.498336 Write Rank0 MR22 =0x34
748 18:40:36.498400 Write Rank0 MR14 =0x10
749 18:40:36.498465 Write Rank0 MR3 =0x30
750 18:40:36.498529 Write Rank0 MR13 =0xd8
751 18:40:36.498593 [ModeRegInit_LP4] CH1 RK1
752 18:40:36.498657 Write Rank1 MR13 =0x18
753 18:40:36.498722 Write Rank1 MR12 =0x5d
754 18:40:36.498786 Write Rank1 MR1 =0x56
755 18:40:36.498850 Write Rank1 MR2 =0x1a
756 18:40:36.498915 Write Rank1 MR11 =0x0
757 18:40:36.498979 Write Rank1 MR22 =0x38
758 18:40:36.499044 Write Rank1 MR14 =0x5d
759 18:40:36.499108 Write Rank1 MR3 =0x30
760 18:40:36.499172 Write Rank1 MR13 =0x58
761 18:40:36.499236 Write Rank1 MR12 =0x5d
762 18:40:36.499300 Write Rank1 MR1 =0x56
763 18:40:36.499364 Write Rank1 MR2 =0x2d
764 18:40:36.499428 Write Rank1 MR11 =0x23
765 18:40:36.499492 Write Rank1 MR22 =0x34
766 18:40:36.499556 Write Rank1 MR14 =0x10
767 18:40:36.499620 Write Rank1 MR3 =0x30
768 18:40:36.499684 Write Rank1 MR13 =0xd8
769 18:40:36.499749 match AC timing 3
770 18:40:36.499813 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
771 18:40:36.499878 DramC Write-DBI off
772 18:40:36.499942 DramC Read-DBI off
773 18:40:36.500007 Write Rank0 MR13 =0x59
774 18:40:36.500070 ==
775 18:40:36.500136 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
776 18:40:36.500200 fsp= 1, odt_onoff= 1, Byte mode= 0
777 18:40:36.500266 ==
778 18:40:36.500329 === u2Vref_new: 0x56 --> 0x2d
779 18:40:36.500394 === u2Vref_new: 0x58 --> 0x38
780 18:40:36.500458 === u2Vref_new: 0x5a --> 0x39
781 18:40:36.500523 === u2Vref_new: 0x5c --> 0x3c
782 18:40:36.500586 === u2Vref_new: 0x5e --> 0x3d
783 18:40:36.500651 === u2Vref_new: 0x60 --> 0xa0
784 18:40:36.500715 [CA 0] Center 34 (5~63) winsize 59
785 18:40:36.500780 [CA 1] Center 35 (7~63) winsize 57
786 18:40:36.500845 [CA 2] Center 28 (-1~58) winsize 60
787 18:40:36.500910 [CA 3] Center 23 (-4~51) winsize 56
788 18:40:36.500974 [CA 4] Center 24 (-4~52) winsize 57
789 18:40:36.501038 [CA 5] Center 29 (0~59) winsize 60
790 18:40:36.501102
791 18:40:36.501166 [CATrainingPosCal] consider 1 rank data
792 18:40:36.501231 u2DelayCellTimex100 = 744/100 ps
793 18:40:36.501296 CA0 delay=34 (5~63),Diff = 11 PI (14 cell)
794 18:40:36.501361 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
795 18:40:36.501425 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
796 18:40:36.501497 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
797 18:40:36.501562 CA4 delay=24 (-4~52),Diff = 1 PI (1 cell)
798 18:40:36.501638 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
799 18:40:36.501696
800 18:40:36.501754 CA PerBit enable=1, Macro0, CA PI delay=23
801 18:40:36.501812 === u2Vref_new: 0x5e --> 0x3d
802 18:40:36.501871
803 18:40:36.501928 Vref(ca) range 1: 30
804 18:40:36.501986
805 18:40:36.502044 CS Dly= 8 (39-0-32)
806 18:40:36.502101 Write Rank0 MR13 =0xd8
807 18:40:36.502159 Write Rank0 MR13 =0xd8
808 18:40:36.502217 Write Rank0 MR12 =0x5e
809 18:40:36.502275 Write Rank1 MR13 =0x59
810 18:40:36.502332 ==
811 18:40:36.502391 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
812 18:40:36.502450 fsp= 1, odt_onoff= 1, Byte mode= 0
813 18:40:36.502509 ==
814 18:40:36.502566 === u2Vref_new: 0x56 --> 0x2d
815 18:40:36.502625 === u2Vref_new: 0x58 --> 0x38
816 18:40:36.502683 === u2Vref_new: 0x5a --> 0x39
817 18:40:36.502741 === u2Vref_new: 0x5c --> 0x3c
818 18:40:36.503012 === u2Vref_new: 0x5e --> 0x3d
819 18:40:36.503081 === u2Vref_new: 0x60 --> 0xa0
820 18:40:36.503142 [CA 0] Center 35 (7~63) winsize 57
821 18:40:36.503201 [CA 1] Center 34 (6~63) winsize 58
822 18:40:36.503260 [CA 2] Center 28 (-2~58) winsize 61
823 18:40:36.503319 [CA 3] Center 22 (-6~51) winsize 58
824 18:40:36.503378 [CA 4] Center 23 (-5~51) winsize 57
825 18:40:36.503436 [CA 5] Center 29 (0~59) winsize 60
826 18:40:36.503494
827 18:40:36.503552 [CATrainingPosCal] consider 2 rank data
828 18:40:36.503612 u2DelayCellTimex100 = 744/100 ps
829 18:40:36.503670 CA0 delay=35 (7~63),Diff = 12 PI (15 cell)
830 18:40:36.503728 CA1 delay=35 (7~63),Diff = 12 PI (15 cell)
831 18:40:36.503787 CA2 delay=28 (-1~58),Diff = 5 PI (6 cell)
832 18:40:36.503846 CA3 delay=23 (-4~51),Diff = 0 PI (0 cell)
833 18:40:36.503904 CA4 delay=23 (-4~51),Diff = 0 PI (0 cell)
834 18:40:36.503963 CA5 delay=29 (0~59),Diff = 6 PI (7 cell)
835 18:40:36.504021
836 18:40:36.504080 CA PerBit enable=1, Macro0, CA PI delay=23
837 18:40:36.504139 === u2Vref_new: 0x5e --> 0x3d
838 18:40:36.504197
839 18:40:36.504255 Vref(ca) range 1: 30
840 18:40:36.504313
841 18:40:36.504370 CS Dly= 5 (36-0-32)
842 18:40:36.504429 Write Rank1 MR13 =0xd8
843 18:40:36.504486 Write Rank1 MR13 =0xd8
844 18:40:36.504544 Write Rank1 MR12 =0x5e
845 18:40:36.504603 [RankSwap] Rank num 2, (Multi 1), Rank 0
846 18:40:36.504661 Write Rank0 MR2 =0xad
847 18:40:36.504719 [Write Leveling]
848 18:40:36.504777 delay byte0 byte1 byte2 byte3
849 18:40:36.504835
850 18:40:36.504894 10 0 0
851 18:40:36.504953 11 0 0
852 18:40:36.505012 12 0 0
853 18:40:36.505071 13 0 0
854 18:40:36.505130 14 0 0
855 18:40:36.505189 15 0 0
856 18:40:36.505248 16 0 0
857 18:40:36.505307 17 0 0
858 18:40:36.505366 18 0 0
859 18:40:36.505425 19 0 0
860 18:40:36.505501 20 0 0
861 18:40:36.505561 21 0 0
862 18:40:36.505620 22 0 0
863 18:40:36.505679 23 0 0
864 18:40:36.505738 24 0 0
865 18:40:36.505796 25 0 ff
866 18:40:36.505855 26 0 ff
867 18:40:36.505914 27 0 ff
868 18:40:36.505973 28 0 ff
869 18:40:36.506032 29 0 ff
870 18:40:36.506091 30 0 ff
871 18:40:36.506149 31 ff ff
872 18:40:36.506208 32 ff ff
873 18:40:36.506267 33 ff ff
874 18:40:36.506326 34 ff ff
875 18:40:36.506385 35 ff ff
876 18:40:36.506444 36 ff ff
877 18:40:36.506503 37 ff ff
878 18:40:36.506562 pass bytecount = 0xff (0xff: all bytes pass)
879 18:40:36.506621
880 18:40:36.506679 DQS0 dly: 31
881 18:40:36.506737 DQS1 dly: 25
882 18:40:36.506796 Write Rank0 MR2 =0x2d
883 18:40:36.506854 [RankSwap] Rank num 2, (Multi 1), Rank 0
884 18:40:36.506913 Write Rank0 MR1 =0xd6
885 18:40:36.506970 [Gating]
886 18:40:36.507028 ==
887 18:40:36.507087 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
888 18:40:36.507145 fsp= 1, odt_onoff= 1, Byte mode= 0
889 18:40:36.507203 ==
890 18:40:36.507261 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
891 18:40:36.507320 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
892 18:40:36.507380 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
893 18:40:36.507439 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
894 18:40:36.507499 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
895 18:40:36.507559 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
896 18:40:36.507617 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
897 18:40:36.507677 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
898 18:40:36.507736 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
899 18:40:36.507795 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
900 18:40:36.507855 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
901 18:40:36.507914 3 2 12 |606 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
902 18:40:36.507974 3 2 16 |3534 404 |(11 11)(11 11) |(0 0)(0 0)| 0
903 18:40:36.508033 3 2 20 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
904 18:40:36.508093 3 2 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
905 18:40:36.508152 3 2 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
906 18:40:36.508212 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
907 18:40:36.508272 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
908 18:40:36.508331 3 3 8 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
909 18:40:36.508390 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
910 18:40:36.508450 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
911 18:40:36.508509 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
912 18:40:36.508573 [Byte 0] Lead/lag Transition tap number (1)
913 18:40:36.508632 [Byte 1] Lead/lag falling Transition (3, 3, 20)
914 18:40:36.508692 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
915 18:40:36.508752 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
916 18:40:36.508811 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
917 18:40:36.508870 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
918 18:40:36.508929 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
919 18:40:36.508988 3 4 12 |504 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
920 18:40:36.509048 3 4 16 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
921 18:40:36.509107 3 4 20 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
922 18:40:36.509166 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 18:40:36.509225 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 18:40:36.509284 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 18:40:36.509343 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 18:40:36.509402 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 18:40:36.509466 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 18:40:36.509526 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 18:40:36.509585 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 18:40:36.509645 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 18:40:36.509703 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 18:40:36.509763 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
933 18:40:36.509823 [Byte 0] Lead/lag falling Transition (3, 6, 0)
934 18:40:36.509881 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
935 18:40:36.509941 [Byte 1] Lead/lag falling Transition (3, 6, 4)
936 18:40:36.509999 3 6 8 |3e3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
937 18:40:36.510058 [Byte 0] Lead/lag Transition tap number (3)
938 18:40:36.510311 3 6 12 |403 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
939 18:40:36.510378 [Byte 1] Lead/lag Transition tap number (3)
940 18:40:36.510438 3 6 16 |4646 1211 |(0 0)(11 11) |(0 0)(0 0)| 0
941 18:40:36.510498 [Byte 0]First pass (3, 6, 16)
942 18:40:36.510557 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
943 18:40:36.510616 [Byte 1]First pass (3, 6, 20)
944 18:40:36.510675 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 18:40:36.510734 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 18:40:36.510794 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 18:40:36.510853 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 18:40:36.510912 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 18:40:36.510972 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 18:40:36.511031 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 18:40:36.511090 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 18:40:36.511149 All bytes gating window > 1UI, Early break!
953 18:40:36.511208
954 18:40:36.511266 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
955 18:40:36.511324
956 18:40:36.511381 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
957 18:40:36.511439
958 18:40:36.511496
959 18:40:36.511553
960 18:40:36.511610 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
961 18:40:36.511668
962 18:40:36.511725 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
963 18:40:36.511783
964 18:40:36.511840
965 18:40:36.511898 Write Rank0 MR1 =0x56
966 18:40:36.511955
967 18:40:36.512013 best RODT dly(2T, 0.5T) = (2, 3)
968 18:40:36.512071
969 18:40:36.512128 best RODT dly(2T, 0.5T) = (2, 3)
970 18:40:36.512186 ==
971 18:40:36.512244 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
972 18:40:36.512302 fsp= 1, odt_onoff= 1, Byte mode= 0
973 18:40:36.512360 ==
974 18:40:36.512418 Start DQ dly to find pass range UseTestEngine =0
975 18:40:36.512476 x-axis: bit #, y-axis: DQ dly (-127~63)
976 18:40:36.512534 RX Vref Scan = 0
977 18:40:36.512591 -26, [0] xxxxxxxx xxxxxxxx [MSB]
978 18:40:36.512654 -25, [0] xxxxxxxx xxxxxxxx [MSB]
979 18:40:36.512714 -24, [0] xxxxxxxx xxxxxxxx [MSB]
980 18:40:36.512772 -23, [0] xxxxxxxx xxxxxxxx [MSB]
981 18:40:36.512831 -22, [0] xxxxxxxx xxxxxxxx [MSB]
982 18:40:36.512890 -21, [0] xxxxxxxx xxxxxxxx [MSB]
983 18:40:36.512949 -20, [0] xxxxxxxx xxxxxxxx [MSB]
984 18:40:36.513009 -19, [0] xxxxxxxx xxxxxxxx [MSB]
985 18:40:36.513068 -18, [0] xxxxxxxx xxxxxxxx [MSB]
986 18:40:36.513127 -17, [0] xxxxxxxx xxxxxxxx [MSB]
987 18:40:36.513186 -16, [0] xxxxxxxx xxxxxxxx [MSB]
988 18:40:36.513245 -15, [0] xxxxxxxx xxxxxxxx [MSB]
989 18:40:36.513303 -14, [0] xxxxxxxx xxxxxxxx [MSB]
990 18:40:36.513362 -13, [0] xxxxxxxx xxxxxxxx [MSB]
991 18:40:36.513421 -12, [0] xxxxxxxx xxxxxxxx [MSB]
992 18:40:36.513494 -11, [0] xxxxxxxx xxxxxxxx [MSB]
993 18:40:36.513554 -10, [0] xxxxxxxx xxxxxxxx [MSB]
994 18:40:36.513613 -9, [0] xxxxxxxx xxxxxxxx [MSB]
995 18:40:36.513672 -8, [0] xxxxxxxx xxxxxxxx [MSB]
996 18:40:36.513731 -7, [0] xxxxxxxx xxxxxxxx [MSB]
997 18:40:36.513791 -6, [0] xxxxxxxx xxxxxxxx [MSB]
998 18:40:36.513849 -5, [0] xxxxxxxx xxxxxxxx [MSB]
999 18:40:36.513908 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1000 18:40:36.513966 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1001 18:40:36.514025 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1002 18:40:36.514083 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1003 18:40:36.514143 0, [0] xxxoxxxx oxxoooxx [MSB]
1004 18:40:36.514202 1, [0] xxxoxoxx ooxoooxx [MSB]
1005 18:40:36.514261 2, [0] xxxoxoox ooxoooox [MSB]
1006 18:40:36.514320 3, [0] xxxoxoox ooxoooox [MSB]
1007 18:40:36.514379 4, [0] xxxoxooo ooxooooo [MSB]
1008 18:40:36.514437 5, [0] oxoooooo ooxooooo [MSB]
1009 18:40:36.514496 6, [0] oooooooo ooxooooo [MSB]
1010 18:40:36.514554 32, [0] oooxoooo oooooooo [MSB]
1011 18:40:36.514614 33, [0] oooxoooo xooooooo [MSB]
1012 18:40:36.514674 34, [0] oooxoooo xooxoooo [MSB]
1013 18:40:36.514734 35, [0] oooxoooo xxoxoooo [MSB]
1014 18:40:36.514793 36, [0] oooxoxoo xxoxxoxo [MSB]
1015 18:40:36.514852 37, [0] oooxoxxx xxoxxxxo [MSB]
1016 18:40:36.514911 38, [0] oooxoxxx xxoxxxxo [MSB]
1017 18:40:36.514971 39, [0] oooxoxxx xxoxxxxx [MSB]
1018 18:40:36.515029 40, [0] oooxxxxx xxoxxxxx [MSB]
1019 18:40:36.515088 41, [0] xxxxxxxx xxoxxxxx [MSB]
1020 18:40:36.515147 42, [0] xxxxxxxx xxxxxxxx [MSB]
1021 18:40:36.515206 iDelay=42, Bit 0, Center 22 (5 ~ 40) 36
1022 18:40:36.515264 iDelay=42, Bit 1, Center 23 (6 ~ 40) 35
1023 18:40:36.515321 iDelay=42, Bit 2, Center 22 (5 ~ 40) 36
1024 18:40:36.515380 iDelay=42, Bit 3, Center 14 (-2 ~ 31) 34
1025 18:40:36.515445 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
1026 18:40:36.515505 iDelay=42, Bit 5, Center 18 (1 ~ 35) 35
1027 18:40:36.515563 iDelay=42, Bit 6, Center 19 (2 ~ 36) 35
1028 18:40:36.515621 iDelay=42, Bit 7, Center 20 (4 ~ 36) 33
1029 18:40:36.515679 iDelay=42, Bit 8, Center 15 (-2 ~ 32) 35
1030 18:40:36.515737 iDelay=42, Bit 9, Center 17 (1 ~ 34) 34
1031 18:40:36.515793 iDelay=42, Bit 10, Center 24 (7 ~ 41) 35
1032 18:40:36.515851 iDelay=42, Bit 11, Center 15 (-2 ~ 33) 36
1033 18:40:36.515908 iDelay=42, Bit 12, Center 17 (0 ~ 35) 36
1034 18:40:36.515965 iDelay=42, Bit 13, Center 18 (0 ~ 36) 37
1035 18:40:36.516022 iDelay=42, Bit 14, Center 18 (2 ~ 35) 34
1036 18:40:36.516079 iDelay=42, Bit 15, Center 21 (4 ~ 38) 35
1037 18:40:36.516136 ==
1038 18:40:36.516193 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1039 18:40:36.516252 fsp= 1, odt_onoff= 1, Byte mode= 0
1040 18:40:36.516309 ==
1041 18:40:36.516367 DQS Delay:
1042 18:40:36.516424 DQS0 = 0, DQS1 = 0
1043 18:40:36.516481 DQM Delay:
1044 18:40:36.516541 DQM0 = 20, DQM1 = 18
1045 18:40:36.516598 DQ Delay:
1046 18:40:36.516655 DQ0 =22, DQ1 =23, DQ2 =22, DQ3 =14
1047 18:40:36.516713 DQ4 =22, DQ5 =18, DQ6 =19, DQ7 =20
1048 18:40:36.516771 DQ8 =15, DQ9 =17, DQ10 =24, DQ11 =15
1049 18:40:36.516828 DQ12 =17, DQ13 =18, DQ14 =18, DQ15 =21
1050 18:40:36.516886
1051 18:40:36.516943
1052 18:40:36.517001 DramC Write-DBI off
1053 18:40:36.517058 ==
1054 18:40:36.517116 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1055 18:40:36.517174 fsp= 1, odt_onoff= 1, Byte mode= 0
1056 18:40:36.517232 ==
1057 18:40:36.517289 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1058 18:40:36.517346
1059 18:40:36.517404 Begin, DQ Scan Range 921~1177
1060 18:40:36.517466
1061 18:40:36.517524
1062 18:40:36.517581 TX Vref Scan disable
1063 18:40:36.517640 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1064 18:40:36.517698 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1065 18:40:36.517756 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1066 18:40:36.517814 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1067 18:40:36.517873 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1068 18:40:36.517931 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1069 18:40:36.518187 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1070 18:40:36.518253 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1071 18:40:36.518312 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1072 18:40:36.518371 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1073 18:40:36.518429 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1074 18:40:36.518488 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1075 18:40:36.518547 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1076 18:40:36.518605 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1077 18:40:36.518664 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1078 18:40:36.518723 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1079 18:40:36.518781 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1080 18:40:36.518840 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1081 18:40:36.518898 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1082 18:40:36.518957 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1083 18:40:36.519015 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1084 18:40:36.519074 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1085 18:40:36.519133 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1086 18:40:36.519191 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1087 18:40:36.519249 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1088 18:40:36.519308 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1089 18:40:36.519367 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1090 18:40:36.519425 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1091 18:40:36.519484 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1092 18:40:36.519542 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1093 18:40:36.519600 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1094 18:40:36.519658 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1095 18:40:36.519717 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1096 18:40:36.519775 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1097 18:40:36.519833 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1098 18:40:36.519891 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1099 18:40:36.519950 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1100 18:40:36.520008 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1101 18:40:36.520067 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1102 18:40:36.520125 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1103 18:40:36.520184 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1104 18:40:36.520242 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1105 18:40:36.520301 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1106 18:40:36.520359 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1107 18:40:36.520418 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1108 18:40:36.520475 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1109 18:40:36.520534 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1110 18:40:36.520592 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1111 18:40:36.520651 969 |3 6 9|[0] xxxxxxxx ooxoxxxx [MSB]
1112 18:40:36.520710 970 |3 6 10|[0] xxxxxxxx ooxooxxx [MSB]
1113 18:40:36.520769 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1114 18:40:36.520828 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1115 18:40:36.520886 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1116 18:40:36.520945 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1117 18:40:36.521002 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1118 18:40:36.521061 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1119 18:40:36.521119 977 |3 6 17|[0] xxxoxoox oooooooo [MSB]
1120 18:40:36.521178 978 |3 6 18|[0] xoxooooo oooooooo [MSB]
1121 18:40:36.521237 979 |3 6 19|[0] xooooooo oooooooo [MSB]
1122 18:40:36.521295 989 |3 6 29|[0] oooooooo oooxoooo [MSB]
1123 18:40:36.521353 990 |3 6 30|[0] oooooooo xooxxxoo [MSB]
1124 18:40:36.521412 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1125 18:40:36.521481 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1126 18:40:36.521539 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1127 18:40:36.521598 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1128 18:40:36.521657 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1129 18:40:36.521715 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1130 18:40:36.521773 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1131 18:40:36.521832 998 |3 6 38|[0] oooxoxxo xxxxxxxx [MSB]
1132 18:40:36.521890 999 |3 6 39|[0] xoxxxxxx xxxxxxxx [MSB]
1133 18:40:36.521947 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1134 18:40:36.522006 Byte0, DQ PI dly=987, DQM PI dly= 987
1135 18:40:36.522063 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1136 18:40:36.522121
1137 18:40:36.522178 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1138 18:40:36.522237
1139 18:40:36.522294 Byte1, DQ PI dly=980, DQM PI dly= 980
1140 18:40:36.522351 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1141 18:40:36.522409
1142 18:40:36.522466 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1143 18:40:36.522524
1144 18:40:36.522581 ==
1145 18:40:36.522640 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1146 18:40:36.522698 fsp= 1, odt_onoff= 1, Byte mode= 0
1147 18:40:36.522756 ==
1148 18:40:36.522813 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1149 18:40:36.522871
1150 18:40:36.522927 Begin, DQ Scan Range 956~1020
1151 18:40:36.522985 Write Rank0 MR14 =0x0
1152 18:40:36.523042
1153 18:40:36.523099 CH=0, VrefRange= 0, VrefLevel = 0
1154 18:40:36.523156 TX Bit0 (983~994) 12 988, Bit8 (970~984) 15 977,
1155 18:40:36.523215 TX Bit1 (980~994) 15 987, Bit9 (972~985) 14 978,
1156 18:40:36.523273 TX Bit2 (982~995) 14 988, Bit10 (976~990) 15 983,
1157 18:40:36.523331 TX Bit3 (976~990) 15 983, Bit11 (971~982) 12 976,
1158 18:40:36.523388 TX Bit4 (980~993) 14 986, Bit12 (975~983) 9 979,
1159 18:40:36.523446 TX Bit5 (978~991) 14 984, Bit13 (975~983) 9 979,
1160 18:40:36.523503 TX Bit6 (978~991) 14 984, Bit14 (975~988) 14 981,
1161 18:40:36.523561 TX Bit7 (980~992) 13 986, Bit15 (976~990) 15 983,
1162 18:40:36.523618
1163 18:40:36.523675 Write Rank0 MR14 =0x2
1164 18:40:36.523732
1165 18:40:36.523789 CH=0, VrefRange= 0, VrefLevel = 2
1166 18:40:36.523846 TX Bit0 (982~995) 14 988, Bit8 (969~984) 16 976,
1167 18:40:36.523905 TX Bit1 (980~995) 16 987, Bit9 (972~986) 15 979,
1168 18:40:36.523962 TX Bit2 (982~996) 15 989, Bit10 (976~990) 15 983,
1169 18:40:36.524020 TX Bit3 (976~991) 16 983, Bit11 (970~982) 13 976,
1170 18:40:36.524078 TX Bit4 (980~993) 14 986, Bit12 (974~984) 11 979,
1171 18:40:36.524135 TX Bit5 (977~992) 16 984, Bit13 (974~984) 11 979,
1172 18:40:36.524193 TX Bit6 (978~991) 14 984, Bit14 (974~989) 16 981,
1173 18:40:36.524250 TX Bit7 (980~993) 14 986, Bit15 (975~990) 16 982,
1174 18:40:36.524308
1175 18:40:36.524364 Write Rank0 MR14 =0x4
1176 18:40:36.524421
1177 18:40:36.524676 CH=0, VrefRange= 0, VrefLevel = 4
1178 18:40:36.524743 TX Bit0 (982~995) 14 988, Bit8 (969~985) 17 977,
1179 18:40:36.524803 TX Bit1 (979~996) 18 987, Bit9 (971~987) 17 979,
1180 18:40:36.524862 TX Bit2 (981~997) 17 989, Bit10 (976~991) 16 983,
1181 18:40:36.524920 TX Bit3 (976~991) 16 983, Bit11 (970~983) 14 976,
1182 18:40:36.524978 TX Bit4 (979~994) 16 986, Bit12 (974~985) 12 979,
1183 18:40:36.525036 TX Bit5 (977~992) 16 984, Bit13 (974~985) 12 979,
1184 18:40:36.525094 TX Bit6 (978~992) 15 985, Bit14 (974~989) 16 981,
1185 18:40:36.525151 TX Bit7 (980~993) 14 986, Bit15 (976~991) 16 983,
1186 18:40:36.525209
1187 18:40:36.525267 Write Rank0 MR14 =0x6
1188 18:40:36.525325
1189 18:40:36.525382 CH=0, VrefRange= 0, VrefLevel = 6
1190 18:40:36.525447 TX Bit0 (982~997) 16 989, Bit8 (968~986) 19 977,
1191 18:40:36.525506 TX Bit1 (979~997) 19 988, Bit9 (971~987) 17 979,
1192 18:40:36.525564 TX Bit2 (980~998) 19 989, Bit10 (976~992) 17 984,
1193 18:40:36.525621 TX Bit3 (976~992) 17 984, Bit11 (969~984) 16 976,
1194 18:40:36.525679 TX Bit4 (979~995) 17 987, Bit12 (973~987) 15 980,
1195 18:40:36.525736 TX Bit5 (977~993) 17 985, Bit13 (974~986) 13 980,
1196 18:40:36.525794 TX Bit6 (977~993) 17 985, Bit14 (973~989) 17 981,
1197 18:40:36.525851 TX Bit7 (979~994) 16 986, Bit15 (975~991) 17 983,
1198 18:40:36.525909
1199 18:40:36.525965 Write Rank0 MR14 =0x8
1200 18:40:36.526022
1201 18:40:36.526080 CH=0, VrefRange= 0, VrefLevel = 8
1202 18:40:36.526138 TX Bit0 (982~998) 17 990, Bit8 (968~987) 20 977,
1203 18:40:36.526195 TX Bit1 (979~998) 20 988, Bit9 (971~988) 18 979,
1204 18:40:36.526254 TX Bit2 (980~998) 19 989, Bit10 (975~993) 19 984,
1205 18:40:36.526311 TX Bit3 (976~992) 17 984, Bit11 (969~985) 17 977,
1206 18:40:36.526369 TX Bit4 (978~996) 19 987, Bit12 (973~988) 16 980,
1207 18:40:36.526427 TX Bit5 (977~993) 17 985, Bit13 (973~987) 15 980,
1208 18:40:36.526485 TX Bit6 (977~993) 17 985, Bit14 (973~990) 18 981,
1209 18:40:36.526543 TX Bit7 (979~995) 17 987, Bit15 (975~992) 18 983,
1210 18:40:36.526600
1211 18:40:36.526657 Write Rank0 MR14 =0xa
1212 18:40:36.526713
1213 18:40:36.526770 CH=0, VrefRange= 0, VrefLevel = 10
1214 18:40:36.526827 TX Bit0 (981~998) 18 989, Bit8 (968~988) 21 978,
1215 18:40:36.526884 TX Bit1 (979~998) 20 988, Bit9 (970~988) 19 979,
1216 18:40:36.526942 TX Bit2 (979~998) 20 988, Bit10 (976~994) 19 985,
1217 18:40:36.526999 TX Bit3 (975~992) 18 983, Bit11 (969~986) 18 977,
1218 18:40:36.527056 TX Bit4 (978~997) 20 987, Bit12 (972~988) 17 980,
1219 18:40:36.527113 TX Bit5 (977~994) 18 985, Bit13 (972~988) 17 980,
1220 18:40:36.527170 TX Bit6 (977~994) 18 985, Bit14 (973~990) 18 981,
1221 18:40:36.527227 TX Bit7 (979~996) 18 987, Bit15 (975~993) 19 984,
1222 18:40:36.527284
1223 18:40:36.527341 Write Rank0 MR14 =0xc
1224 18:40:36.527398
1225 18:40:36.527454 CH=0, VrefRange= 0, VrefLevel = 12
1226 18:40:36.527511 TX Bit0 (981~998) 18 989, Bit8 (968~988) 21 978,
1227 18:40:36.527569 TX Bit1 (978~998) 21 988, Bit9 (970~989) 20 979,
1228 18:40:36.527626 TX Bit2 (979~999) 21 989, Bit10 (975~994) 20 984,
1229 18:40:36.527684 TX Bit3 (975~993) 19 984, Bit11 (969~987) 19 978,
1230 18:40:36.527742 TX Bit4 (978~998) 21 988, Bit12 (972~988) 17 980,
1231 18:40:36.527799 TX Bit5 (977~994) 18 985, Bit13 (972~988) 17 980,
1232 18:40:36.527857 TX Bit6 (977~994) 18 985, Bit14 (973~991) 19 982,
1233 18:40:36.527915 TX Bit7 (978~997) 20 987, Bit15 (975~994) 20 984,
1234 18:40:36.527972
1235 18:40:36.528029 Write Rank0 MR14 =0xe
1236 18:40:36.528086
1237 18:40:36.528143 CH=0, VrefRange= 0, VrefLevel = 14
1238 18:40:36.528200 TX Bit0 (980~999) 20 989, Bit8 (968~989) 22 978,
1239 18:40:36.528257 TX Bit1 (978~999) 22 988, Bit9 (969~989) 21 979,
1240 18:40:36.528314 TX Bit2 (979~999) 21 989, Bit10 (975~995) 21 985,
1241 18:40:36.528372 TX Bit3 (975~993) 19 984, Bit11 (968~987) 20 977,
1242 18:40:36.528429 TX Bit4 (978~998) 21 988, Bit12 (971~989) 19 980,
1243 18:40:36.528486 TX Bit5 (976~995) 20 985, Bit13 (971~989) 19 980,
1244 18:40:36.528544 TX Bit6 (977~995) 19 986, Bit14 (972~991) 20 981,
1245 18:40:36.528601 TX Bit7 (978~998) 21 988, Bit15 (975~994) 20 984,
1246 18:40:36.528659
1247 18:40:36.528716 Write Rank0 MR14 =0x10
1248 18:40:36.528773
1249 18:40:36.528829 CH=0, VrefRange= 0, VrefLevel = 16
1250 18:40:36.528887 TX Bit0 (980~999) 20 989, Bit8 (968~989) 22 978,
1251 18:40:36.528944 TX Bit1 (978~999) 22 988, Bit9 (969~989) 21 979,
1252 18:40:36.529002 TX Bit2 (978~999) 22 988, Bit10 (975~996) 22 985,
1253 18:40:36.529059 TX Bit3 (974~993) 20 983, Bit11 (968~988) 21 978,
1254 18:40:36.529116 TX Bit4 (978~998) 21 988, Bit12 (971~989) 19 980,
1255 18:40:36.529173 TX Bit5 (976~996) 21 986, Bit13 (971~989) 19 980,
1256 18:40:36.529231 TX Bit6 (976~996) 21 986, Bit14 (971~992) 22 981,
1257 18:40:36.529288 TX Bit7 (978~998) 21 988, Bit15 (974~995) 22 984,
1258 18:40:36.529346
1259 18:40:36.529402 Write Rank0 MR14 =0x12
1260 18:40:36.529464
1261 18:40:36.529521 CH=0, VrefRange= 0, VrefLevel = 18
1262 18:40:36.529578 TX Bit0 (979~999) 21 989, Bit8 (967~989) 23 978,
1263 18:40:36.529635 TX Bit1 (978~999) 22 988, Bit9 (969~990) 22 979,
1264 18:40:36.529693 TX Bit2 (978~1000) 23 989, Bit10 (974~996) 23 985,
1265 18:40:36.529750 TX Bit3 (974~994) 21 984, Bit11 (968~988) 21 978,
1266 18:40:36.529808 TX Bit4 (977~999) 23 988, Bit12 (970~990) 21 980,
1267 18:40:36.529865 TX Bit5 (976~996) 21 986, Bit13 (970~989) 20 979,
1268 18:40:36.529923 TX Bit6 (976~996) 21 986, Bit14 (971~992) 22 981,
1269 18:40:36.529981 TX Bit7 (978~999) 22 988, Bit15 (974~996) 23 985,
1270 18:40:36.530039
1271 18:40:36.530096 Write Rank0 MR14 =0x14
1272 18:40:36.530153
1273 18:40:36.530210 CH=0, VrefRange= 0, VrefLevel = 20
1274 18:40:36.530267 TX Bit0 (979~1000) 22 989, Bit8 (967~990) 24 978,
1275 18:40:36.530324 TX Bit1 (978~1000) 23 989, Bit9 (969~990) 22 979,
1276 18:40:36.530381 TX Bit2 (978~1000) 23 989, Bit10 (974~996) 23 985,
1277 18:40:36.530633 TX Bit3 (974~994) 21 984, Bit11 (968~989) 22 978,
1278 18:40:36.530698 TX Bit4 (977~999) 23 988, Bit12 (970~990) 21 980,
1279 18:40:36.530757 TX Bit5 (976~997) 22 986, Bit13 (970~989) 20 979,
1280 18:40:36.530816 TX Bit6 (976~997) 22 986, Bit14 (970~993) 24 981,
1281 18:40:36.530874 TX Bit7 (978~999) 22 988, Bit15 (974~996) 23 985,
1282 18:40:36.530931
1283 18:40:36.530988 Write Rank0 MR14 =0x16
1284 18:40:36.531046
1285 18:40:36.531103 CH=0, VrefRange= 0, VrefLevel = 22
1286 18:40:36.531160 TX Bit0 (978~1000) 23 989, Bit8 (967~990) 24 978,
1287 18:40:36.531218 TX Bit1 (977~1000) 24 988, Bit9 (968~991) 24 979,
1288 18:40:36.531275 TX Bit2 (978~1000) 23 989, Bit10 (974~997) 24 985,
1289 18:40:36.531333 TX Bit3 (974~995) 22 984, Bit11 (968~989) 22 978,
1290 18:40:36.531391 TX Bit4 (977~999) 23 988, Bit12 (969~990) 22 979,
1291 18:40:36.531449 TX Bit5 (976~998) 23 987, Bit13 (969~990) 22 979,
1292 18:40:36.531506 TX Bit6 (976~998) 23 987, Bit14 (970~993) 24 981,
1293 18:40:36.531564 TX Bit7 (977~1000) 24 988, Bit15 (973~996) 24 984,
1294 18:40:36.531621
1295 18:40:36.531678 Write Rank0 MR14 =0x18
1296 18:40:36.531735
1297 18:40:36.531792 CH=0, VrefRange= 0, VrefLevel = 24
1298 18:40:36.531849 TX Bit0 (978~1001) 24 989, Bit8 (967~990) 24 978,
1299 18:40:36.531907 TX Bit1 (977~1000) 24 988, Bit9 (969~991) 23 980,
1300 18:40:36.531966 TX Bit2 (978~1001) 24 989, Bit10 (974~997) 24 985,
1301 18:40:36.532023 TX Bit3 (973~996) 24 984, Bit11 (968~989) 22 978,
1302 18:40:36.532081 TX Bit4 (977~1000) 24 988, Bit12 (969~991) 23 980,
1303 18:40:36.532138 TX Bit5 (975~998) 24 986, Bit13 (969~990) 22 979,
1304 18:40:36.532196 TX Bit6 (976~999) 24 987, Bit14 (970~994) 25 982,
1305 18:40:36.532253 TX Bit7 (977~1000) 24 988, Bit15 (973~997) 25 985,
1306 18:40:36.532310
1307 18:40:36.532367 Write Rank0 MR14 =0x1a
1308 18:40:36.532424
1309 18:40:36.532480 CH=0, VrefRange= 0, VrefLevel = 26
1310 18:40:36.532537 TX Bit0 (978~1001) 24 989, Bit8 (967~990) 24 978,
1311 18:40:36.532595 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1312 18:40:36.532652 TX Bit2 (978~1001) 24 989, Bit10 (973~997) 25 985,
1313 18:40:36.532710 TX Bit3 (973~996) 24 984, Bit11 (967~990) 24 978,
1314 18:40:36.532768 TX Bit4 (977~1000) 24 988, Bit12 (969~991) 23 980,
1315 18:40:36.532825 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1316 18:40:36.532883 TX Bit6 (976~999) 24 987, Bit14 (969~994) 26 981,
1317 18:40:36.532940 TX Bit7 (977~1001) 25 989, Bit15 (973~997) 25 985,
1318 18:40:36.532998
1319 18:40:36.533054 Write Rank0 MR14 =0x1c
1320 18:40:36.533111
1321 18:40:36.533168 CH=0, VrefRange= 0, VrefLevel = 28
1322 18:40:36.533225 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1323 18:40:36.533283 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1324 18:40:36.533340 TX Bit2 (977~1002) 26 989, Bit10 (973~997) 25 985,
1325 18:40:36.533397 TX Bit3 (972~996) 25 984, Bit11 (967~990) 24 978,
1326 18:40:36.533461 TX Bit4 (977~1000) 24 988, Bit12 (968~992) 25 980,
1327 18:40:36.533519 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1328 18:40:36.533577 TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982,
1329 18:40:36.533634 TX Bit7 (977~1001) 25 989, Bit15 (972~997) 26 984,
1330 18:40:36.533690
1331 18:40:36.533747 Write Rank0 MR14 =0x1e
1332 18:40:36.533804
1333 18:40:36.533861 CH=0, VrefRange= 0, VrefLevel = 30
1334 18:40:36.533918 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1335 18:40:36.533976 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1336 18:40:36.534033 TX Bit2 (977~1002) 26 989, Bit10 (973~997) 25 985,
1337 18:40:36.534090 TX Bit3 (972~996) 25 984, Bit11 (967~990) 24 978,
1338 18:40:36.534148 TX Bit4 (977~1000) 24 988, Bit12 (968~992) 25 980,
1339 18:40:36.534205 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1340 18:40:36.534263 TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982,
1341 18:40:36.534321 TX Bit7 (977~1001) 25 989, Bit15 (972~997) 26 984,
1342 18:40:36.534378
1343 18:40:36.534435 Write Rank0 MR14 =0x20
1344 18:40:36.534492
1345 18:40:36.534549 CH=0, VrefRange= 0, VrefLevel = 32
1346 18:40:36.534605 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1347 18:40:36.534663 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1348 18:40:36.534720 TX Bit2 (977~1002) 26 989, Bit10 (973~997) 25 985,
1349 18:40:36.534778 TX Bit3 (972~996) 25 984, Bit11 (967~990) 24 978,
1350 18:40:36.534836 TX Bit4 (977~1000) 24 988, Bit12 (968~992) 25 980,
1351 18:40:36.534893 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1352 18:40:36.534951 TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982,
1353 18:40:36.535008 TX Bit7 (977~1001) 25 989, Bit15 (972~997) 26 984,
1354 18:40:36.535066
1355 18:40:36.535123 Write Rank0 MR14 =0x22
1356 18:40:36.535179
1357 18:40:36.535236 CH=0, VrefRange= 0, VrefLevel = 34
1358 18:40:36.535294 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1359 18:40:36.535351 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1360 18:40:36.535409 TX Bit2 (977~1002) 26 989, Bit10 (973~997) 25 985,
1361 18:40:36.535466 TX Bit3 (972~996) 25 984, Bit11 (967~990) 24 978,
1362 18:40:36.535523 TX Bit4 (977~1000) 24 988, Bit12 (968~992) 25 980,
1363 18:40:36.535581 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1364 18:40:36.535637 TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982,
1365 18:40:36.535694 TX Bit7 (977~1001) 25 989, Bit15 (972~997) 26 984,
1366 18:40:36.535751
1367 18:40:36.535807 Write Rank0 MR14 =0x24
1368 18:40:36.535863
1369 18:40:36.535919 CH=0, VrefRange= 0, VrefLevel = 36
1370 18:40:36.535976 TX Bit0 (978~1002) 25 990, Bit8 (967~989) 23 978,
1371 18:40:36.536033 TX Bit1 (977~1001) 25 989, Bit9 (968~991) 24 979,
1372 18:40:36.536091 TX Bit2 (977~1002) 26 989, Bit10 (973~997) 25 985,
1373 18:40:36.536147 TX Bit3 (972~996) 25 984, Bit11 (967~990) 24 978,
1374 18:40:36.536205 TX Bit4 (977~1000) 24 988, Bit12 (968~992) 25 980,
1375 18:40:36.536262 TX Bit5 (975~999) 25 987, Bit13 (969~991) 23 980,
1376 18:40:36.536510 TX Bit6 (976~999) 24 987, Bit14 (969~995) 27 982,
1377 18:40:36.536574 TX Bit7 (977~1001) 25 989, Bit15 (972~997) 26 984,
1378 18:40:36.536632
1379 18:40:36.536688
1380 18:40:36.536745 TX Vref found, early break! 375< 376
1381 18:40:36.536802 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
1382 18:40:36.536859 u1DelayCellOfst[0]=7 cells (6 PI)
1383 18:40:36.536916 u1DelayCellOfst[1]=6 cells (5 PI)
1384 18:40:36.536973 u1DelayCellOfst[2]=6 cells (5 PI)
1385 18:40:36.537030 u1DelayCellOfst[3]=0 cells (0 PI)
1386 18:40:36.537087 u1DelayCellOfst[4]=5 cells (4 PI)
1387 18:40:36.537144 u1DelayCellOfst[5]=3 cells (3 PI)
1388 18:40:36.537201 u1DelayCellOfst[6]=3 cells (3 PI)
1389 18:40:36.537257 u1DelayCellOfst[7]=6 cells (5 PI)
1390 18:40:36.537314 Byte0, DQ PI dly=984, DQM PI dly= 987
1391 18:40:36.537371 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 24)
1392 18:40:36.537434
1393 18:40:36.537492 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 24)
1394 18:40:36.537549
1395 18:40:36.537606 u1DelayCellOfst[8]=0 cells (0 PI)
1396 18:40:36.537663 u1DelayCellOfst[9]=1 cells (1 PI)
1397 18:40:36.537720 u1DelayCellOfst[10]=9 cells (7 PI)
1398 18:40:36.537783 u1DelayCellOfst[11]=0 cells (0 PI)
1399 18:40:36.537851 u1DelayCellOfst[12]=2 cells (2 PI)
1400 18:40:36.537909 u1DelayCellOfst[13]=2 cells (2 PI)
1401 18:40:36.537966 u1DelayCellOfst[14]=5 cells (4 PI)
1402 18:40:36.538022 u1DelayCellOfst[15]=7 cells (6 PI)
1403 18:40:36.538079 Byte1, DQ PI dly=978, DQM PI dly= 981
1404 18:40:36.538136 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
1405 18:40:36.538193
1406 18:40:36.538249 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
1407 18:40:36.538306
1408 18:40:36.538362 Write Rank0 MR14 =0x1c
1409 18:40:36.538419
1410 18:40:36.538475 Final TX Range 0 Vref 28
1411 18:40:36.538532
1412 18:40:36.538589 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1413 18:40:36.538649
1414 18:40:36.538706 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1415 18:40:36.538763 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1416 18:40:36.538821 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1417 18:40:36.538879 Write Rank0 MR3 =0xb0
1418 18:40:36.538935 DramC Write-DBI on
1419 18:40:36.538991 ==
1420 18:40:36.539048 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1421 18:40:36.539119 fsp= 1, odt_onoff= 1, Byte mode= 0
1422 18:40:36.539179 ==
1423 18:40:36.539236 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1424 18:40:36.539293
1425 18:40:36.539350 Begin, DQ Scan Range 701~765
1426 18:40:36.539407
1427 18:40:36.539463
1428 18:40:36.539519 TX Vref Scan disable
1429 18:40:36.539576 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1430 18:40:36.539635 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1431 18:40:36.539693 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1432 18:40:36.539751 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1433 18:40:36.539808 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1434 18:40:36.539866 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1435 18:40:36.539924 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1436 18:40:36.539982 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1437 18:40:36.540041 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1438 18:40:36.540099 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1439 18:40:36.540157 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1440 18:40:36.540214 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1441 18:40:36.540272 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1442 18:40:36.540330 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1443 18:40:36.540387 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1444 18:40:36.540445 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1445 18:40:36.540503 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1446 18:40:36.540561 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1447 18:40:36.540618 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1448 18:40:36.540677 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1449 18:40:36.540735 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1450 18:40:36.540793 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1451 18:40:36.540851 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1452 18:40:36.540909 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1453 18:40:36.540977 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1454 18:40:36.541051 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1455 18:40:36.541122 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1456 18:40:36.541219 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1457 18:40:36.541329 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1458 18:40:36.541423 Byte0, DQ PI dly=732, DQM PI dly= 732
1459 18:40:36.541514 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1460 18:40:36.541605
1461 18:40:36.541695 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1462 18:40:36.541785
1463 18:40:36.541874 Byte1, DQ PI dly=724, DQM PI dly= 724
1464 18:40:36.541964 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
1465 18:40:36.542054
1466 18:40:36.542143 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
1467 18:40:36.542233
1468 18:40:36.542323 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1469 18:40:36.542414 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1470 18:40:36.542506 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1471 18:40:36.542595 Write Rank0 MR3 =0x30
1472 18:40:36.542684 DramC Write-DBI off
1473 18:40:36.542772
1474 18:40:36.542862 [DATLAT]
1475 18:40:36.542951 Freq=1600, CH0 RK0, use_rxtx_scan=0
1476 18:40:36.543044
1477 18:40:36.543135 DATLAT Default: 0xf
1478 18:40:36.543224 7, 0xFFFF, sum=0
1479 18:40:36.543314 8, 0xFFFF, sum=0
1480 18:40:36.543406 9, 0xFFFF, sum=0
1481 18:40:36.543497 10, 0xFFFF, sum=0
1482 18:40:36.543588 11, 0xFFFF, sum=0
1483 18:40:36.543679 12, 0xFFFF, sum=0
1484 18:40:36.543770 13, 0xFFFF, sum=0
1485 18:40:36.543861 14, 0x0, sum=1
1486 18:40:36.543952 15, 0x0, sum=2
1487 18:40:36.544043 16, 0x0, sum=3
1488 18:40:36.544134 17, 0x0, sum=4
1489 18:40:36.544226 pattern=2 first_step=14 total pass=5 best_step=16
1490 18:40:36.544315 ==
1491 18:40:36.544405 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1492 18:40:36.544494 fsp= 1, odt_onoff= 1, Byte mode= 0
1493 18:40:36.544583 ==
1494 18:40:36.544673 Start DQ dly to find pass range UseTestEngine =1
1495 18:40:36.544763 x-axis: bit #, y-axis: DQ dly (-127~63)
1496 18:40:36.544852 RX Vref Scan = 1
1497 18:40:36.544940
1498 18:40:36.545029 RX Vref found, early break!
1499 18:40:36.545117
1500 18:40:36.545206 Final RX Vref 11, apply to both rank0 and 1
1501 18:40:36.545295 ==
1502 18:40:36.545385 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1503 18:40:36.545678 fsp= 1, odt_onoff= 1, Byte mode= 0
1504 18:40:36.545748 ==
1505 18:40:36.545806 DQS Delay:
1506 18:40:36.545863 DQS0 = 0, DQS1 = 0
1507 18:40:36.545921 DQM Delay:
1508 18:40:36.545978 DQM0 = 19, DQM1 = 17
1509 18:40:36.546034 DQ Delay:
1510 18:40:36.546092 DQ0 =21, DQ1 =22, DQ2 =23, DQ3 =14
1511 18:40:36.546148 DQ4 =22, DQ5 =17, DQ6 =18, DQ7 =20
1512 18:40:36.546206 DQ8 =14, DQ9 =17, DQ10 =23, DQ11 =15
1513 18:40:36.546262 DQ12 =18, DQ13 =16, DQ14 =18, DQ15 =20
1514 18:40:36.546319
1515 18:40:36.546376
1516 18:40:36.546432
1517 18:40:36.546488 [DramC_TX_OE_Calibration] TA2
1518 18:40:36.546545 Original DQ_B0 (3 6) =30, OEN = 27
1519 18:40:36.546603 Original DQ_B1 (3 6) =30, OEN = 27
1520 18:40:36.546660 23, 0x0, End_B0=23 End_B1=23
1521 18:40:36.546718 24, 0x0, End_B0=24 End_B1=24
1522 18:40:36.546776 25, 0x0, End_B0=25 End_B1=25
1523 18:40:36.546833 26, 0x0, End_B0=26 End_B1=26
1524 18:40:36.546891 27, 0x0, End_B0=27 End_B1=27
1525 18:40:36.546949 28, 0x0, End_B0=28 End_B1=28
1526 18:40:36.547006 29, 0x0, End_B0=29 End_B1=29
1527 18:40:36.547064 30, 0x0, End_B0=30 End_B1=30
1528 18:40:36.547121 31, 0xFFFF, End_B0=30 End_B1=30
1529 18:40:36.547179 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1530 18:40:36.547237 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1531 18:40:36.547294
1532 18:40:36.547350
1533 18:40:36.547406 Write Rank0 MR23 =0x3f
1534 18:40:36.547463 [DQSOSC]
1535 18:40:36.547520 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
1536 18:40:36.547578 CH0_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
1537 18:40:36.547636 Write Rank0 MR23 =0x3f
1538 18:40:36.547693 [DQSOSC]
1539 18:40:36.547750 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c0, (MSB)MR19= 0x202, tDQSOscB0 = 447 ps tDQSOscB1 = 447 ps
1540 18:40:36.547808 CH0 RK0: MR19=202, MR18=C0C0
1541 18:40:36.547865 [RankSwap] Rank num 2, (Multi 1), Rank 1
1542 18:40:36.547922 Write Rank0 MR2 =0xad
1543 18:40:36.547979 [Write Leveling]
1544 18:40:36.548035 delay byte0 byte1 byte2 byte3
1545 18:40:36.548092
1546 18:40:36.548149 10 0 0
1547 18:40:36.548207 11 0 0
1548 18:40:36.548264 12 0 0
1549 18:40:36.548322 13 0 0
1550 18:40:36.548380 14 0 0
1551 18:40:36.548438 15 0 0
1552 18:40:36.548495 16 0 0
1553 18:40:36.548553 17 0 0
1554 18:40:36.548610 18 0 0
1555 18:40:36.548668 19 0 0
1556 18:40:36.548726 20 0 0
1557 18:40:36.548782 21 0 0
1558 18:40:36.548840 22 0 0
1559 18:40:36.548898 23 0 0
1560 18:40:36.548976 24 0 ff
1561 18:40:36.549036 25 0 ff
1562 18:40:36.549094 26 ff ff
1563 18:40:36.549151 27 ff ff
1564 18:40:36.549209 28 ff ff
1565 18:40:36.549266 29 ff ff
1566 18:40:36.549324 30 ff ff
1567 18:40:36.549382 31 ff ff
1568 18:40:36.549446 32 ff ff
1569 18:40:36.549505 pass bytecount = 0xff (0xff: all bytes pass)
1570 18:40:36.549562
1571 18:40:36.549619 DQS0 dly: 26
1572 18:40:36.549676 DQS1 dly: 24
1573 18:40:36.549733 Write Rank0 MR2 =0x2d
1574 18:40:36.549789 [RankSwap] Rank num 2, (Multi 1), Rank 0
1575 18:40:36.549846 Write Rank1 MR1 =0xd6
1576 18:40:36.549903 [Gating]
1577 18:40:36.549959 ==
1578 18:40:36.550016 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1579 18:40:36.550072 fsp= 1, odt_onoff= 1, Byte mode= 0
1580 18:40:36.550129 ==
1581 18:40:36.550186 3 1 0 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1582 18:40:36.550245 3 1 4 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1583 18:40:36.550303 3 1 8 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1584 18:40:36.550361 3 1 12 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
1585 18:40:36.550419 3 1 16 |2c2b 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
1586 18:40:36.550478 3 1 20 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1587 18:40:36.550535 3 1 24 |2c2b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
1588 18:40:36.550593 [Byte 0] Lead/lag falling Transition (3, 1, 24)
1589 18:40:36.550650 3 1 28 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1590 18:40:36.550709 3 2 0 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1591 18:40:36.550767 3 2 4 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1592 18:40:36.550824 3 2 8 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1593 18:40:36.550882 3 2 12 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1594 18:40:36.550940 3 2 16 |2c2b 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
1595 18:40:36.550999 [Byte 0] Lead/lag Transition tap number (7)
1596 18:40:36.551074 3 2 20 |2727 2c2b |(11 11)(11 11) |(0 0)(0 0)| 0
1597 18:40:36.551133 3 2 24 |3534 1818 |(11 11)(11 11) |(0 0)(0 0)| 0
1598 18:40:36.551192 3 2 28 |3534 201 |(11 11)(11 11) |(0 0)(0 0)| 0
1599 18:40:36.551251 3 3 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1600 18:40:36.551309 3 3 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1601 18:40:36.551366 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1602 18:40:36.551425 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1603 18:40:36.551483 3 3 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1604 18:40:36.551541 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1605 18:40:36.551599 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1606 18:40:36.551657 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1607 18:40:36.551715 [Byte 1] Lead/lag falling Transition (3, 3, 28)
1608 18:40:36.551772 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1609 18:40:36.551830 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1610 18:40:36.551888 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1611 18:40:36.551946 3 4 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1612 18:40:36.552003 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1613 18:40:36.552060 3 4 20 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1614 18:40:36.552118 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1615 18:40:36.552176 3 4 28 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1616 18:40:36.552233 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 18:40:36.552291 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 18:40:36.552349 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 18:40:36.552407 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 18:40:36.552465 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 18:40:36.552522 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1622 18:40:36.552580 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1623 18:40:36.552638 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1624 18:40:36.552894 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1625 18:40:36.552959 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1626 18:40:36.553018 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1627 18:40:36.553076 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1628 18:40:36.553134 [Byte 0] Lead/lag falling Transition (3, 6, 12)
1629 18:40:36.553191 [Byte 1] Lead/lag falling Transition (3, 6, 12)
1630 18:40:36.553249 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1631 18:40:36.553307 [Byte 0] Lead/lag Transition tap number (2)
1632 18:40:36.553365 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1633 18:40:36.553424 [Byte 1] Lead/lag Transition tap number (3)
1634 18:40:36.553493 3 6 24 |2222 3e3d |(11 11)(11 11) |(0 0)(0 0)| 0
1635 18:40:36.553550 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
1636 18:40:36.553609 [Byte 0]First pass (3, 6, 28)
1637 18:40:36.553665 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1638 18:40:36.553724 [Byte 1]First pass (3, 7, 0)
1639 18:40:36.553780 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 18:40:36.553838 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1641 18:40:36.553900 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1642 18:40:36.553958 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1643 18:40:36.554015 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1644 18:40:36.554082 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1645 18:40:36.554143 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1646 18:40:36.554201 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1647 18:40:36.554268 All bytes gating window > 1UI, Early break!
1648 18:40:36.554327
1649 18:40:36.554384 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 16)
1650 18:40:36.554448
1651 18:40:36.554506 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
1652 18:40:36.554564
1653 18:40:36.554626
1654 18:40:36.554685
1655 18:40:36.554741 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 16)
1656 18:40:36.554802
1657 18:40:36.554864 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
1658 18:40:36.554921
1659 18:40:36.554978
1660 18:40:36.555072 Write Rank1 MR1 =0x56
1661 18:40:36.555180
1662 18:40:36.555270 best RODT dly(2T, 0.5T) = (2, 3)
1663 18:40:36.555361
1664 18:40:36.555451 best RODT dly(2T, 0.5T) = (2, 3)
1665 18:40:36.555541 ==
1666 18:40:36.555631 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1667 18:40:36.555721 fsp= 1, odt_onoff= 1, Byte mode= 0
1668 18:40:36.555810 ==
1669 18:40:36.555900 Start DQ dly to find pass range UseTestEngine =0
1670 18:40:36.555990 x-axis: bit #, y-axis: DQ dly (-127~63)
1671 18:40:36.556079 RX Vref Scan = 0
1672 18:40:36.556170 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1673 18:40:36.556262 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1674 18:40:36.556354 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1675 18:40:36.556445 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1676 18:40:36.556536 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1677 18:40:36.556628 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1678 18:40:36.556719 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1679 18:40:36.556810 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1680 18:40:36.556902 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1681 18:40:36.556993 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1682 18:40:36.557084 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1683 18:40:36.557176 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1684 18:40:36.557267 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1685 18:40:36.557359 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1686 18:40:36.557453 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1687 18:40:36.557515 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1688 18:40:36.557574 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1689 18:40:36.557631 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1690 18:40:36.557689 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1691 18:40:36.557747 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1692 18:40:36.557805 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1693 18:40:36.557863 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1694 18:40:36.557921 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1695 18:40:36.557978 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1696 18:40:36.558036 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1697 18:40:36.558094 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1698 18:40:36.558152 0, [0] xxxoxoxx ooxoooxx [MSB]
1699 18:40:36.558211 1, [0] xxxoxoox ooxoooxx [MSB]
1700 18:40:36.558269 2, [0] xxxoxoox ooxoooxx [MSB]
1701 18:40:36.558326 3, [0] xxxoxooo ooxoooox [MSB]
1702 18:40:36.558384 4, [0] xoxooooo ooxoooox [MSB]
1703 18:40:36.558441 5, [0] ooxooooo ooxooooo [MSB]
1704 18:40:36.558499 32, [0] oooxoooo oooooooo [MSB]
1705 18:40:36.558557 33, [0] oooxoooo oooooooo [MSB]
1706 18:40:36.558614 34, [0] oooxoooo xooooooo [MSB]
1707 18:40:36.558672 35, [0] oooxoooo xxoxoooo [MSB]
1708 18:40:36.558730 36, [0] oooxoxxo xxoxxooo [MSB]
1709 18:40:36.558787 37, [0] oooxoxxx xxoxxxxo [MSB]
1710 18:40:36.558845 38, [0] oooxoxxx xxoxxxxo [MSB]
1711 18:40:36.558903 39, [0] ooxxxxxx xxoxxxxx [MSB]
1712 18:40:36.558961 40, [0] xoxxxxxx xxoxxxxx [MSB]
1713 18:40:36.559018 41, [0] xxxxxxxx xxoxxxxx [MSB]
1714 18:40:36.559076 42, [0] xxxxxxxx xxoxxxxx [MSB]
1715 18:40:36.559133 43, [0] xxxxxxxx xxxxxxxx [MSB]
1716 18:40:36.559190 iDelay=43, Bit 0, Center 22 (5 ~ 39) 35
1717 18:40:36.559247 iDelay=43, Bit 1, Center 22 (4 ~ 40) 37
1718 18:40:36.559304 iDelay=43, Bit 2, Center 22 (6 ~ 38) 33
1719 18:40:36.559360 iDelay=43, Bit 3, Center 14 (-2 ~ 31) 34
1720 18:40:36.559417 iDelay=43, Bit 4, Center 21 (4 ~ 38) 35
1721 18:40:36.559473 iDelay=43, Bit 5, Center 17 (0 ~ 35) 36
1722 18:40:36.559530 iDelay=43, Bit 6, Center 18 (1 ~ 35) 35
1723 18:40:36.559586 iDelay=43, Bit 7, Center 19 (3 ~ 36) 34
1724 18:40:36.559643 iDelay=43, Bit 8, Center 15 (-3 ~ 33) 37
1725 18:40:36.559699 iDelay=43, Bit 9, Center 17 (0 ~ 34) 35
1726 18:40:36.559756 iDelay=43, Bit 10, Center 24 (6 ~ 42) 37
1727 18:40:36.559813 iDelay=43, Bit 11, Center 16 (-2 ~ 34) 37
1728 18:40:36.559869 iDelay=43, Bit 12, Center 17 (0 ~ 35) 36
1729 18:40:36.559926 iDelay=43, Bit 13, Center 18 (0 ~ 36) 37
1730 18:40:36.559983 iDelay=43, Bit 14, Center 19 (3 ~ 36) 34
1731 18:40:36.560039 iDelay=43, Bit 15, Center 21 (5 ~ 38) 34
1732 18:40:36.560096 ==
1733 18:40:36.560152 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1734 18:40:36.560209 fsp= 1, odt_onoff= 1, Byte mode= 0
1735 18:40:36.560266 ==
1736 18:40:36.560322 DQS Delay:
1737 18:40:36.560379 DQS0 = 0, DQS1 = 0
1738 18:40:36.560436 DQM Delay:
1739 18:40:36.560492 DQM0 = 19, DQM1 = 18
1740 18:40:36.560549 DQ Delay:
1741 18:40:36.560605 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1742 18:40:36.560662 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
1743 18:40:36.560718 DQ8 =15, DQ9 =17, DQ10 =24, DQ11 =16
1744 18:40:36.560775 DQ12 =17, DQ13 =18, DQ14 =19, DQ15 =21
1745 18:40:36.560831
1746 18:40:36.560888
1747 18:40:36.560944 DramC Write-DBI off
1748 18:40:36.561000 ==
1749 18:40:36.561255 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1750 18:40:36.561320 fsp= 1, odt_onoff= 1, Byte mode= 0
1751 18:40:36.561379 ==
1752 18:40:36.561446 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1753 18:40:36.561505
1754 18:40:36.561562 Begin, DQ Scan Range 920~1176
1755 18:40:36.561617
1756 18:40:36.561674
1757 18:40:36.561730 TX Vref Scan disable
1758 18:40:36.561787 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1759 18:40:36.561846 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1760 18:40:36.561904 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1761 18:40:36.561962 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1762 18:40:36.562020 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1763 18:40:36.562078 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1764 18:40:36.562136 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1765 18:40:36.562193 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1766 18:40:36.562251 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1767 18:40:36.562308 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1768 18:40:36.562366 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1769 18:40:36.562423 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1770 18:40:36.562481 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1771 18:40:36.562539 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1772 18:40:36.562597 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1773 18:40:36.562654 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1774 18:40:36.562712 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1775 18:40:36.562770 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1776 18:40:36.562828 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1777 18:40:36.562886 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1778 18:40:36.562943 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1779 18:40:36.563001 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1780 18:40:36.563059 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1781 18:40:36.563117 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1782 18:40:36.563175 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1783 18:40:36.563233 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1784 18:40:36.563291 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1785 18:40:36.563348 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1786 18:40:36.563406 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1787 18:40:36.563464 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1788 18:40:36.563521 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1789 18:40:36.563580 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1790 18:40:36.563638 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1791 18:40:36.563695 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1792 18:40:36.563752 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1793 18:40:36.563810 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1794 18:40:36.563868 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1795 18:40:36.563925 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1796 18:40:36.563982 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1797 18:40:36.564040 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1798 18:40:36.564098 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1799 18:40:36.564156 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1800 18:40:36.564214 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1801 18:40:36.564273 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1802 18:40:36.564331 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1803 18:40:36.564388 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1804 18:40:36.564445 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1805 18:40:36.564502 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1806 18:40:36.564560 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1807 18:40:36.564617 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1808 18:40:36.564675 970 |3 6 10|[0] xxxxxxxx oxxoxxxx [MSB]
1809 18:40:36.564732 971 |3 6 11|[0] xxxxxxxx oxxoxxxx [MSB]
1810 18:40:36.564790 972 |3 6 12|[0] xxxxxxxx oxxoxxox [MSB]
1811 18:40:36.564847 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1812 18:40:36.564905 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1813 18:40:36.564963 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1814 18:40:36.565020 976 |3 6 16|[0] xxxoxoox oooooooo [MSB]
1815 18:40:36.565077 977 |3 6 17|[0] ooxooooo oooooooo [MSB]
1816 18:40:36.565135 990 |3 6 30|[0] oooooooo xooxoooo [MSB]
1817 18:40:36.565192 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1818 18:40:36.565250 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1819 18:40:36.565308 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1820 18:40:36.565366 994 |3 6 34|[0] oooxoxoo xxxxxxxx [MSB]
1821 18:40:36.565424 995 |3 6 35|[0] oooxoxoo xxxxxxxx [MSB]
1822 18:40:36.565490 996 |3 6 36|[0] oooxoxxo xxxxxxxx [MSB]
1823 18:40:36.565548 997 |3 6 37|[0] oooxoxxx xxxxxxxx [MSB]
1824 18:40:36.565606 998 |3 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
1825 18:40:36.565665 Byte0, DQ PI dly=985, DQM PI dly= 985
1826 18:40:36.565722 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 25)
1827 18:40:36.565779
1828 18:40:36.565836 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 25)
1829 18:40:36.565892
1830 18:40:36.565949 Byte1, DQ PI dly=981, DQM PI dly= 981
1831 18:40:36.566005 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1832 18:40:36.566062
1833 18:40:36.566118 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1834 18:40:36.566175
1835 18:40:36.566231 ==
1836 18:40:36.566287 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1837 18:40:36.566344 fsp= 1, odt_onoff= 1, Byte mode= 0
1838 18:40:36.566401 ==
1839 18:40:36.566458 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1840 18:40:36.566514
1841 18:40:36.566573 Begin, DQ Scan Range 957~1021
1842 18:40:36.566630 Write Rank1 MR14 =0x0
1843 18:40:36.566686
1844 18:40:36.566743 CH=0, VrefRange= 0, VrefLevel = 0
1845 18:40:36.566811 TX Bit0 (980~992) 13 986, Bit8 (972~984) 13 978,
1846 18:40:36.566869 TX Bit1 (978~992) 15 985, Bit9 (975~984) 10 979,
1847 18:40:36.566927 TX Bit2 (980~991) 12 985, Bit10 (977~991) 15 984,
1848 18:40:36.566995 TX Bit3 (974~986) 13 980, Bit11 (974~982) 9 978,
1849 18:40:36.567054 TX Bit4 (978~992) 15 985, Bit12 (975~984) 10 979,
1850 18:40:36.567112 TX Bit5 (977~988) 12 982, Bit13 (974~985) 12 979,
1851 18:40:36.567178 TX Bit6 (977~991) 15 984, Bit14 (975~990) 16 982,
1852 18:40:36.567236 TX Bit7 (978~992) 15 985, Bit15 (978~990) 13 984,
1853 18:40:36.567296
1854 18:40:36.567353 Write Rank1 MR14 =0x2
1855 18:40:36.567410
1856 18:40:36.567466 CH=0, VrefRange= 0, VrefLevel = 2
1857 18:40:36.567533 TX Bit0 (980~993) 14 986, Bit8 (972~984) 13 978,
1858 18:40:36.567592 TX Bit1 (978~993) 16 985, Bit9 (974~985) 12 979,
1859 18:40:36.567849 TX Bit2 (980~992) 13 986, Bit10 (978~991) 14 984,
1860 18:40:36.567950 TX Bit3 (974~987) 14 980, Bit11 (973~983) 11 978,
1861 18:40:36.568043 TX Bit4 (978~992) 15 985, Bit12 (975~985) 11 980,
1862 18:40:36.568134 TX Bit5 (977~988) 12 982, Bit13 (974~987) 14 980,
1863 18:40:36.568226 TX Bit6 (977~991) 15 984, Bit14 (974~990) 17 982,
1864 18:40:36.568316 TX Bit7 (978~992) 15 985, Bit15 (977~992) 16 984,
1865 18:40:36.568405
1866 18:40:36.568494 Write Rank1 MR14 =0x4
1867 18:40:36.568583
1868 18:40:36.568672 CH=0, VrefRange= 0, VrefLevel = 4
1869 18:40:36.568761 TX Bit0 (979~993) 15 986, Bit8 (972~985) 14 978,
1870 18:40:36.568852 TX Bit1 (978~994) 17 986, Bit9 (974~986) 13 980,
1871 18:40:36.568943 TX Bit2 (979~993) 15 986, Bit10 (977~992) 16 984,
1872 18:40:36.569033 TX Bit3 (974~988) 15 981, Bit11 (973~984) 12 978,
1873 18:40:36.569123 TX Bit4 (978~993) 16 985, Bit12 (975~986) 12 980,
1874 18:40:36.569213 TX Bit5 (976~990) 15 983, Bit13 (974~988) 15 981,
1875 18:40:36.569303 TX Bit6 (977~992) 16 984, Bit14 (974~991) 18 982,
1876 18:40:36.569393 TX Bit7 (978~993) 16 985, Bit15 (977~992) 16 984,
1877 18:40:36.569482
1878 18:40:36.569541 Write Rank1 MR14 =0x6
1879 18:40:36.569598
1880 18:40:36.569655 CH=0, VrefRange= 0, VrefLevel = 6
1881 18:40:36.569713 TX Bit0 (978~994) 17 986, Bit8 (971~986) 16 978,
1882 18:40:36.569770 TX Bit1 (978~994) 17 986, Bit9 (974~987) 14 980,
1883 18:40:36.569828 TX Bit2 (979~993) 15 986, Bit10 (977~992) 16 984,
1884 18:40:36.569886 TX Bit3 (973~989) 17 981, Bit11 (973~984) 12 978,
1885 18:40:36.569944 TX Bit4 (978~993) 16 985, Bit12 (974~987) 14 980,
1886 18:40:36.570001 TX Bit5 (976~991) 16 983, Bit13 (974~988) 15 981,
1887 18:40:36.570058 TX Bit6 (976~992) 17 984, Bit14 (974~991) 18 982,
1888 18:40:36.570115 TX Bit7 (978~993) 16 985, Bit15 (976~993) 18 984,
1889 18:40:36.570172
1890 18:40:36.570229 Write Rank1 MR14 =0x8
1891 18:40:36.570285
1892 18:40:36.570341 CH=0, VrefRange= 0, VrefLevel = 8
1893 18:40:36.570398 TX Bit0 (978~995) 18 986, Bit8 (970~987) 18 978,
1894 18:40:36.570456 TX Bit1 (977~995) 19 986, Bit9 (974~987) 14 980,
1895 18:40:36.570513 TX Bit2 (979~994) 16 986, Bit10 (977~993) 17 985,
1896 18:40:36.570570 TX Bit3 (972~990) 19 981, Bit11 (973~985) 13 979,
1897 18:40:36.570627 TX Bit4 (977~994) 18 985, Bit12 (974~987) 14 980,
1898 18:40:36.570684 TX Bit5 (976~991) 16 983, Bit13 (974~989) 16 981,
1899 18:40:36.570742 TX Bit6 (976~993) 18 984, Bit14 (973~992) 20 982,
1900 18:40:36.570800 TX Bit7 (978~994) 17 986, Bit15 (976~993) 18 984,
1901 18:40:36.570856
1902 18:40:36.570913 Write Rank1 MR14 =0xa
1903 18:40:36.570969
1904 18:40:36.571025 CH=0, VrefRange= 0, VrefLevel = 10
1905 18:40:36.571082 TX Bit0 (978~996) 19 987, Bit8 (970~987) 18 978,
1906 18:40:36.571139 TX Bit1 (978~996) 19 987, Bit9 (973~988) 16 980,
1907 18:40:36.571197 TX Bit2 (979~995) 17 987, Bit10 (976~994) 19 985,
1908 18:40:36.571254 TX Bit3 (972~991) 20 981, Bit11 (972~986) 15 979,
1909 18:40:36.571311 TX Bit4 (977~995) 19 986, Bit12 (973~988) 16 980,
1910 18:40:36.571368 TX Bit5 (976~992) 17 984, Bit13 (973~990) 18 981,
1911 18:40:36.571425 TX Bit6 (976~993) 18 984, Bit14 (974~992) 19 983,
1912 18:40:36.571482 TX Bit7 (977~995) 19 986, Bit15 (976~994) 19 985,
1913 18:40:36.571539
1914 18:40:36.571595 Write Rank1 MR14 =0xc
1915 18:40:36.571652
1916 18:40:36.571708 CH=0, VrefRange= 0, VrefLevel = 12
1917 18:40:36.571765 TX Bit0 (978~996) 19 987, Bit8 (970~989) 20 979,
1918 18:40:36.571822 TX Bit1 (977~997) 21 987, Bit9 (973~989) 17 981,
1919 18:40:36.571878 TX Bit2 (978~995) 18 986, Bit10 (976~995) 20 985,
1920 18:40:36.571936 TX Bit3 (971~991) 21 981, Bit11 (972~986) 15 979,
1921 18:40:36.571993 TX Bit4 (977~995) 19 986, Bit12 (973~989) 17 981,
1922 18:40:36.572050 TX Bit5 (976~992) 17 984, Bit13 (973~990) 18 981,
1923 18:40:36.572107 TX Bit6 (976~994) 19 985, Bit14 (973~993) 21 983,
1924 18:40:36.572164 TX Bit7 (978~995) 18 986, Bit15 (976~995) 20 985,
1925 18:40:36.572220
1926 18:40:36.572276 Write Rank1 MR14 =0xe
1927 18:40:36.572332
1928 18:40:36.572389 CH=0, VrefRange= 0, VrefLevel = 14
1929 18:40:36.572446 TX Bit0 (978~997) 20 987, Bit8 (969~989) 21 979,
1930 18:40:36.572503 TX Bit1 (977~997) 21 987, Bit9 (973~990) 18 981,
1931 18:40:36.572559 TX Bit2 (978~996) 19 987, Bit10 (976~994) 19 985,
1932 18:40:36.572616 TX Bit3 (971~991) 21 981, Bit11 (971~988) 18 979,
1933 18:40:36.572673 TX Bit4 (977~997) 21 987, Bit12 (973~990) 18 981,
1934 18:40:36.572730 TX Bit5 (975~993) 19 984, Bit13 (973~991) 19 982,
1935 18:40:36.572787 TX Bit6 (976~994) 19 985, Bit14 (973~993) 21 983,
1936 18:40:36.572844 TX Bit7 (977~996) 20 986, Bit15 (975~995) 21 985,
1937 18:40:36.572901
1938 18:40:36.572957 Write Rank1 MR14 =0x10
1939 18:40:36.573014
1940 18:40:36.573070 CH=0, VrefRange= 0, VrefLevel = 16
1941 18:40:36.573127 TX Bit0 (978~998) 21 988, Bit8 (969~989) 21 979,
1942 18:40:36.573184 TX Bit1 (977~998) 22 987, Bit9 (972~990) 19 981,
1943 18:40:36.573240 TX Bit2 (978~997) 20 987, Bit10 (976~995) 20 985,
1944 18:40:36.573297 TX Bit3 (971~991) 21 981, Bit11 (971~989) 19 980,
1945 18:40:36.573354 TX Bit4 (977~997) 21 987, Bit12 (973~990) 18 981,
1946 18:40:36.573410 TX Bit5 (975~993) 19 984, Bit13 (972~991) 20 981,
1947 18:40:36.573478 TX Bit6 (975~995) 21 985, Bit14 (973~993) 21 983,
1948 18:40:36.573535 TX Bit7 (978~997) 20 987, Bit15 (975~995) 21 985,
1949 18:40:36.573591
1950 18:40:36.573648 Write Rank1 MR14 =0x12
1951 18:40:36.573704
1952 18:40:36.573760 CH=0, VrefRange= 0, VrefLevel = 18
1953 18:40:36.573816 TX Bit0 (978~999) 22 988, Bit8 (969~990) 22 979,
1954 18:40:36.573873 TX Bit1 (977~998) 22 987, Bit9 (972~990) 19 981,
1955 18:40:36.573930 TX Bit2 (978~998) 21 988, Bit10 (975~997) 23 986,
1956 18:40:36.573987 TX Bit3 (970~992) 23 981, Bit11 (971~989) 19 980,
1957 18:40:36.574043 TX Bit4 (977~998) 22 987, Bit12 (972~990) 19 981,
1958 18:40:36.574101 TX Bit5 (974~994) 21 984, Bit13 (972~991) 20 981,
1959 18:40:36.574350 TX Bit6 (975~995) 21 985, Bit14 (972~994) 23 983,
1960 18:40:36.574415 TX Bit7 (977~997) 21 987, Bit15 (975~996) 22 985,
1961 18:40:36.574474
1962 18:40:36.574531 Write Rank1 MR14 =0x14
1963 18:40:36.574588
1964 18:40:36.574644 CH=0, VrefRange= 0, VrefLevel = 20
1965 18:40:36.574701 TX Bit0 (977~999) 23 988, Bit8 (968~990) 23 979,
1966 18:40:36.574758 TX Bit1 (977~999) 23 988, Bit9 (972~991) 20 981,
1967 18:40:36.574815 TX Bit2 (977~998) 22 987, Bit10 (976~997) 22 986,
1968 18:40:36.574872 TX Bit3 (970~992) 23 981, Bit11 (970~990) 21 980,
1969 18:40:36.574928 TX Bit4 (977~998) 22 987, Bit12 (972~991) 20 981,
1970 18:40:36.574985 TX Bit5 (974~994) 21 984, Bit13 (971~992) 22 981,
1971 18:40:36.864950 TX Bit6 (974~996) 23 985, Bit14 (972~995) 24 983,
1972 18:40:36.865425 TX Bit7 (977~998) 22 987, Bit15 (975~997) 23 986,
1973 18:40:36.865813
1974 18:40:36.866109 Write Rank1 MR14 =0x16
1975 18:40:36.866395
1976 18:40:36.866672 CH=0, VrefRange= 0, VrefLevel = 22
1977 18:40:36.866946 TX Bit0 (977~999) 23 988, Bit8 (968~991) 24 979,
1978 18:40:36.867221 TX Bit1 (977~999) 23 988, Bit9 (971~991) 21 981,
1979 18:40:36.867488 TX Bit2 (977~999) 23 988, Bit10 (975~997) 23 986,
1980 18:40:36.867758 TX Bit3 (970~992) 23 981, Bit11 (969~990) 22 979,
1981 18:40:36.868024 TX Bit4 (976~999) 24 987, Bit12 (972~992) 21 982,
1982 18:40:36.868290 TX Bit5 (974~995) 22 984, Bit13 (972~992) 21 982,
1983 18:40:36.868555 TX Bit6 (974~997) 24 985, Bit14 (971~995) 25 983,
1984 18:40:36.868822 TX Bit7 (977~998) 22 987, Bit15 (975~997) 23 986,
1985 18:40:36.869086
1986 18:40:36.869346 Write Rank1 MR14 =0x18
1987 18:40:36.869638
1988 18:40:36.869901 CH=0, VrefRange= 0, VrefLevel = 24
1989 18:40:36.870165 TX Bit0 (977~999) 23 988, Bit8 (968~991) 24 979,
1990 18:40:36.870431 TX Bit1 (976~999) 24 987, Bit9 (970~991) 22 980,
1991 18:40:36.870694 TX Bit2 (977~999) 23 988, Bit10 (975~997) 23 986,
1992 18:40:36.870958 TX Bit3 (970~992) 23 981, Bit11 (969~991) 23 980,
1993 18:40:36.871221 TX Bit4 (976~999) 24 987, Bit12 (971~992) 22 981,
1994 18:40:36.871482 TX Bit5 (973~995) 23 984, Bit13 (970~993) 24 981,
1995 18:40:36.871746 TX Bit6 (974~998) 25 986, Bit14 (971~996) 26 983,
1996 18:40:36.872009 TX Bit7 (976~999) 24 987, Bit15 (975~997) 23 986,
1997 18:40:36.872271
1998 18:40:36.872530 Write Rank1 MR14 =0x1a
1999 18:40:36.872857
2000 18:40:36.873125 CH=0, VrefRange= 0, VrefLevel = 26
2001 18:40:36.873389 TX Bit0 (977~1000) 24 988, Bit8 (968~992) 25 980,
2002 18:40:36.873692 TX Bit1 (977~1000) 24 988, Bit9 (970~992) 23 981,
2003 18:40:36.873960 TX Bit2 (977~999) 23 988, Bit10 (975~998) 24 986,
2004 18:40:36.874222 TX Bit3 (970~993) 24 981, Bit11 (968~991) 24 979,
2005 18:40:36.874486 TX Bit4 (976~999) 24 987, Bit12 (971~992) 22 981,
2006 18:40:36.874749 TX Bit5 (973~996) 24 984, Bit13 (970~993) 24 981,
2007 18:40:36.875013 TX Bit6 (974~998) 25 986, Bit14 (970~996) 27 983,
2008 18:40:36.875277 TX Bit7 (976~999) 24 987, Bit15 (975~998) 24 986,
2009 18:40:36.875538
2010 18:40:36.875800 Write Rank1 MR14 =0x1c
2011 18:40:36.876058
2012 18:40:36.876316 CH=0, VrefRange= 0, VrefLevel = 28
2013 18:40:36.876572 TX Bit0 (977~1000) 24 988, Bit8 (967~991) 25 979,
2014 18:40:36.876885 TX Bit1 (976~999) 24 987, Bit9 (969~992) 24 980,
2015 18:40:36.877365 TX Bit2 (977~1000) 24 988, Bit10 (974~998) 25 986,
2016 18:40:36.877769 TX Bit3 (970~994) 25 982, Bit11 (968~992) 25 980,
2017 18:40:36.878050 TX Bit4 (976~999) 24 987, Bit12 (970~992) 23 981,
2018 18:40:36.878320 TX Bit5 (972~997) 26 984, Bit13 (970~993) 24 981,
2019 18:40:36.878586 TX Bit6 (974~998) 25 986, Bit14 (970~996) 27 983,
2020 18:40:36.878850 TX Bit7 (976~1000) 25 988, Bit15 (974~998) 25 986,
2021 18:40:36.879114
2022 18:40:36.879373 Write Rank1 MR14 =0x1e
2023 18:40:36.879634
2024 18:40:36.879894 CH=0, VrefRange= 0, VrefLevel = 30
2025 18:40:36.880154 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
2026 18:40:36.880416 TX Bit1 (976~999) 24 987, Bit9 (969~993) 25 981,
2027 18:40:36.880680 TX Bit2 (977~1000) 24 988, Bit10 (975~999) 25 987,
2028 18:40:36.880977 TX Bit3 (970~994) 25 982, Bit11 (968~991) 24 979,
2029 18:40:36.881451 TX Bit4 (976~1000) 25 988, Bit12 (970~993) 24 981,
2030 18:40:36.881762 TX Bit5 (972~996) 25 984, Bit13 (970~993) 24 981,
2031 18:40:36.882029 TX Bit6 (975~998) 24 986, Bit14 (971~995) 25 983,
2032 18:40:36.882294 TX Bit7 (976~1000) 25 988, Bit15 (974~998) 25 986,
2033 18:40:36.882558
2034 18:40:36.882819 Write Rank1 MR14 =0x20
2035 18:40:36.883080
2036 18:40:36.883339 CH=0, VrefRange= 0, VrefLevel = 32
2037 18:40:36.883604 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
2038 18:40:36.883869 TX Bit1 (976~999) 24 987, Bit9 (969~993) 25 981,
2039 18:40:36.884132 TX Bit2 (977~1000) 24 988, Bit10 (975~999) 25 987,
2040 18:40:36.884396 TX Bit3 (970~994) 25 982, Bit11 (968~991) 24 979,
2041 18:40:36.884659 TX Bit4 (976~1000) 25 988, Bit12 (970~993) 24 981,
2042 18:40:36.884924 TX Bit5 (972~996) 25 984, Bit13 (970~993) 24 981,
2043 18:40:36.885187 TX Bit6 (975~998) 24 986, Bit14 (971~995) 25 983,
2044 18:40:36.885480 TX Bit7 (976~1000) 25 988, Bit15 (974~998) 25 986,
2045 18:40:36.885756
2046 18:40:36.886015 Write Rank1 MR14 =0x22
2047 18:40:36.886275
2048 18:40:36.886534 CH=0, VrefRange= 0, VrefLevel = 34
2049 18:40:36.886795 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
2050 18:40:36.887058 TX Bit1 (976~999) 24 987, Bit9 (969~993) 25 981,
2051 18:40:36.887322 TX Bit2 (977~1000) 24 988, Bit10 (975~999) 25 987,
2052 18:40:36.887582 TX Bit3 (970~994) 25 982, Bit11 (968~991) 24 979,
2053 18:40:36.887844 TX Bit4 (976~1000) 25 988, Bit12 (970~993) 24 981,
2054 18:40:36.888107 TX Bit5 (972~996) 25 984, Bit13 (970~993) 24 981,
2055 18:40:36.888369 TX Bit6 (975~998) 24 986, Bit14 (971~995) 25 983,
2056 18:40:36.888629 TX Bit7 (976~1000) 25 988, Bit15 (974~998) 25 986,
2057 18:40:36.888891
2058 18:40:36.889152 Write Rank1 MR14 =0x24
2059 18:40:36.889413
2060 18:40:36.889708 CH=0, VrefRange= 0, VrefLevel = 36
2061 18:40:36.890343 TX Bit0 (977~1001) 25 989, Bit8 (968~991) 24 979,
2062 18:40:36.890642 TX Bit1 (976~999) 24 987, Bit9 (969~993) 25 981,
2063 18:40:36.890913 TX Bit2 (977~1000) 24 988, Bit10 (975~999) 25 987,
2064 18:40:36.891178 TX Bit3 (970~994) 25 982, Bit11 (968~991) 24 979,
2065 18:40:36.891445 TX Bit4 (976~1000) 25 988, Bit12 (970~993) 24 981,
2066 18:40:36.891709 TX Bit5 (972~996) 25 984, Bit13 (970~993) 24 981,
2067 18:40:36.891973 TX Bit6 (975~998) 24 986, Bit14 (971~995) 25 983,
2068 18:40:36.892238 TX Bit7 (976~1000) 25 988, Bit15 (974~998) 25 986,
2069 18:40:36.892502
2070 18:40:36.892763
2071 18:40:36.893023 TX Vref found, early break! 365< 373
2072 18:40:36.893286 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2073 18:40:36.893607 u1DelayCellOfst[0]=9 cells (7 PI)
2074 18:40:36.893802 u1DelayCellOfst[1]=6 cells (5 PI)
2075 18:40:36.893990 u1DelayCellOfst[2]=7 cells (6 PI)
2076 18:40:36.894177 u1DelayCellOfst[3]=0 cells (0 PI)
2077 18:40:36.894363 u1DelayCellOfst[4]=7 cells (6 PI)
2078 18:40:36.894553 u1DelayCellOfst[5]=2 cells (2 PI)
2079 18:40:36.894740 u1DelayCellOfst[6]=5 cells (4 PI)
2080 18:40:36.894931 u1DelayCellOfst[7]=7 cells (6 PI)
2081 18:40:36.895120 Byte0, DQ PI dly=982, DQM PI dly= 985
2082 18:40:36.895311 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2083 18:40:36.895502
2084 18:40:36.895690 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2085 18:40:36.895879
2086 18:40:36.896065 u1DelayCellOfst[8]=0 cells (0 PI)
2087 18:40:36.896252 u1DelayCellOfst[9]=2 cells (2 PI)
2088 18:40:36.896440 u1DelayCellOfst[10]=10 cells (8 PI)
2089 18:40:36.896630 u1DelayCellOfst[11]=0 cells (0 PI)
2090 18:40:36.896818 u1DelayCellOfst[12]=2 cells (2 PI)
2091 18:40:36.897007 u1DelayCellOfst[13]=2 cells (2 PI)
2092 18:40:36.897196 u1DelayCellOfst[14]=5 cells (4 PI)
2093 18:40:36.897385 u1DelayCellOfst[15]=9 cells (7 PI)
2094 18:40:36.897607 Byte1, DQ PI dly=979, DQM PI dly= 983
2095 18:40:36.897799 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2096 18:40:36.897989
2097 18:40:36.898178 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2098 18:40:36.898367
2099 18:40:36.898554 Write Rank1 MR14 =0x1e
2100 18:40:36.898726
2101 18:40:36.898868 Final TX Range 0 Vref 30
2102 18:40:36.899012
2103 18:40:36.899153 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2104 18:40:36.899300
2105 18:40:36.899443 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2106 18:40:36.899586 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2107 18:40:36.899732 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2108 18:40:36.899875 Write Rank1 MR3 =0xb0
2109 18:40:36.900017 DramC Write-DBI on
2110 18:40:36.900159 ==
2111 18:40:36.900299 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2112 18:40:36.900442 fsp= 1, odt_onoff= 1, Byte mode= 0
2113 18:40:36.900585 ==
2114 18:40:36.900727 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2115 18:40:36.900869
2116 18:40:36.901009 Begin, DQ Scan Range 703~767
2117 18:40:36.901151
2118 18:40:36.901291
2119 18:40:36.901440 TX Vref Scan disable
2120 18:40:36.901584 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2121 18:40:36.901730 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2122 18:40:36.901876 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2123 18:40:36.902020 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2124 18:40:36.902164 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2125 18:40:36.902308 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2126 18:40:36.902451 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2127 18:40:36.902595 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2128 18:40:36.902737 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2129 18:40:36.902881 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2130 18:40:36.903024 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2131 18:40:36.903169 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2132 18:40:36.903313 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2133 18:40:36.903456 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2134 18:40:36.903614 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2135 18:40:36.903727 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2136 18:40:36.903843 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2137 18:40:36.903958 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2138 18:40:36.904073 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2139 18:40:36.904188 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2140 18:40:36.904303 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2141 18:40:36.904418 744 |2 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
2142 18:40:36.904531 Byte0, DQ PI dly=730, DQM PI dly= 730
2143 18:40:36.904645 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
2144 18:40:36.904760
2145 18:40:36.904872 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
2146 18:40:36.904985
2147 18:40:36.905098 Byte1, DQ PI dly=724, DQM PI dly= 724
2148 18:40:36.905211 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
2149 18:40:36.905324
2150 18:40:36.905443 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
2151 18:40:36.905558
2152 18:40:36.905671 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2153 18:40:36.905786 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2154 18:40:36.905901 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2155 18:40:36.906015 Write Rank1 MR3 =0x30
2156 18:40:36.906127 DramC Write-DBI off
2157 18:40:36.906240
2158 18:40:36.906352 [DATLAT]
2159 18:40:36.906463 Freq=1600, CH0 RK1, use_rxtx_scan=0
2160 18:40:36.906577
2161 18:40:36.906690 DATLAT Default: 0x10
2162 18:40:36.906803 7, 0xFFFF, sum=0
2163 18:40:36.906926 8, 0xFFFF, sum=0
2164 18:40:36.907041 9, 0xFFFF, sum=0
2165 18:40:36.907155 10, 0xFFFF, sum=0
2166 18:40:36.907270 11, 0xFFFF, sum=0
2167 18:40:36.907385 12, 0xFFFF, sum=0
2168 18:40:36.907499 13, 0xFFFF, sum=0
2169 18:40:36.907614 14, 0x0, sum=1
2170 18:40:36.907729 15, 0x0, sum=2
2171 18:40:36.907845 16, 0x0, sum=3
2172 18:40:36.907960 17, 0x0, sum=4
2173 18:40:36.908075 pattern=2 first_step=14 total pass=5 best_step=16
2174 18:40:36.908188 ==
2175 18:40:36.908301 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2176 18:40:36.908414 fsp= 1, odt_onoff= 1, Byte mode= 0
2177 18:40:36.908528 ==
2178 18:40:36.908644 Start DQ dly to find pass range UseTestEngine =1
2179 18:40:36.908740 x-axis: bit #, y-axis: DQ dly (-127~63)
2180 18:40:36.908833 RX Vref Scan = 0
2181 18:40:36.908940 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2182 18:40:36.909043 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2183 18:40:36.909141 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2184 18:40:36.909237 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2185 18:40:36.909567 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2186 18:40:36.909677 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2187 18:40:36.909775 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2188 18:40:36.909872 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2189 18:40:36.909968 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2190 18:40:36.910065 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2191 18:40:36.910161 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2192 18:40:36.910260 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2193 18:40:36.910357 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2194 18:40:36.910454 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2195 18:40:36.910550 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2196 18:40:36.910646 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2197 18:40:36.910743 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2198 18:40:36.910838 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2199 18:40:36.910935 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2200 18:40:36.911031 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2201 18:40:36.911128 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2202 18:40:36.911225 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2203 18:40:36.911321 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2204 18:40:36.911416 -3, [0] xxxoxxxx xxxxxxxx [MSB]
2205 18:40:36.911512 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2206 18:40:36.911608 -1, [0] xxxoxxxx ooxoxoxx [MSB]
2207 18:40:36.911704 0, [0] xxxoxoxx ooxoooxx [MSB]
2208 18:40:36.911800 1, [0] xxxoxoxx ooxoooxx [MSB]
2209 18:40:36.911897 2, [0] xxxoxoox ooxoooox [MSB]
2210 18:40:36.911993 3, [0] xxxoxooo ooxoooox [MSB]
2211 18:40:36.912090 4, [0] oxxoxooo ooxooooo [MSB]
2212 18:40:36.912186 5, [0] oooooooo ooxooooo [MSB]
2213 18:40:36.912282 32, [0] oooxoooo oooooooo [MSB]
2214 18:40:36.912379 33, [0] oooxoooo xooxoooo [MSB]
2215 18:40:36.912476 34, [0] oooxoooo xooxoooo [MSB]
2216 18:40:36.912572 35, [0] oooxoxoo xxoxxxoo [MSB]
2217 18:40:36.912667 36, [0] oooxoxxo xxoxxxoo [MSB]
2218 18:40:36.912762 37, [0] oooxoxxo xxoxxxxo [MSB]
2219 18:40:36.912857 38, [0] oooxoxxx xxoxxxxo [MSB]
2220 18:40:36.912954 39, [0] oxoxxxxx xxoxxxxx [MSB]
2221 18:40:36.913049 40, [0] xxoxxxxx xxoxxxxx [MSB]
2222 18:40:36.913145 41, [0] xxxxxxxx xxxxxxxx [MSB]
2223 18:40:36.913241 iDelay=41, Bit 0, Center 21 (4 ~ 39) 36
2224 18:40:36.913363 iDelay=41, Bit 1, Center 21 (5 ~ 38) 34
2225 18:40:36.913548 iDelay=41, Bit 2, Center 22 (5 ~ 40) 36
2226 18:40:36.913660 iDelay=41, Bit 3, Center 14 (-3 ~ 31) 35
2227 18:40:36.913743 iDelay=41, Bit 4, Center 21 (5 ~ 38) 34
2228 18:40:36.913826 iDelay=41, Bit 5, Center 17 (0 ~ 34) 35
2229 18:40:36.913920 iDelay=41, Bit 6, Center 18 (2 ~ 35) 34
2230 18:40:36.914003 iDelay=41, Bit 7, Center 20 (3 ~ 37) 35
2231 18:40:36.914085 iDelay=41, Bit 8, Center 15 (-2 ~ 32) 35
2232 18:40:36.914167 iDelay=41, Bit 9, Center 16 (-1 ~ 34) 36
2233 18:40:36.914268 iDelay=41, Bit 10, Center 23 (6 ~ 40) 35
2234 18:40:36.914395 iDelay=41, Bit 11, Center 15 (-2 ~ 32) 35
2235 18:40:36.914529 iDelay=41, Bit 12, Center 17 (0 ~ 34) 35
2236 18:40:36.914617 iDelay=41, Bit 13, Center 16 (-1 ~ 34) 36
2237 18:40:36.914701 iDelay=41, Bit 14, Center 19 (2 ~ 36) 35
2238 18:40:36.914783 iDelay=41, Bit 15, Center 21 (4 ~ 38) 35
2239 18:40:36.914864 ==
2240 18:40:36.914946 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2241 18:40:36.915029 fsp= 1, odt_onoff= 1, Byte mode= 0
2242 18:40:36.915112 ==
2243 18:40:36.915193 DQS Delay:
2244 18:40:36.915275 DQS0 = 0, DQS1 = 0
2245 18:40:36.915355 DQM Delay:
2246 18:40:36.915436 DQM0 = 19, DQM1 = 17
2247 18:40:36.915518 DQ Delay:
2248 18:40:36.915659 DQ0 =21, DQ1 =21, DQ2 =22, DQ3 =14
2249 18:40:36.915789 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =20
2250 18:40:36.915917 DQ8 =15, DQ9 =16, DQ10 =23, DQ11 =15
2251 18:40:36.916045 DQ12 =17, DQ13 =16, DQ14 =19, DQ15 =21
2252 18:40:36.916172
2253 18:40:36.916297
2254 18:40:36.916423
2255 18:40:36.916549 [DramC_TX_OE_Calibration] TA2
2256 18:40:36.916676 Original DQ_B0 (3 6) =30, OEN = 27
2257 18:40:36.916806 Original DQ_B1 (3 6) =30, OEN = 27
2258 18:40:36.916933 23, 0x0, End_B0=23 End_B1=23
2259 18:40:36.917064 24, 0x0, End_B0=24 End_B1=24
2260 18:40:36.917195 25, 0x0, End_B0=25 End_B1=25
2261 18:40:36.917331 26, 0x0, End_B0=26 End_B1=26
2262 18:40:36.917475 27, 0x0, End_B0=27 End_B1=27
2263 18:40:36.917607 28, 0x0, End_B0=28 End_B1=28
2264 18:40:36.917738 29, 0x0, End_B0=29 End_B1=29
2265 18:40:36.917831 30, 0x0, End_B0=30 End_B1=30
2266 18:40:36.917916 31, 0xFFFF, End_B0=30 End_B1=30
2267 18:40:36.918000 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2268 18:40:36.918083 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2269 18:40:36.918165
2270 18:40:36.918247
2271 18:40:36.918328 Write Rank1 MR23 =0x3f
2272 18:40:36.918409 [DQSOSC]
2273 18:40:36.918491 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0x202, tDQSOscB0 = 465 ps tDQSOscB1 = 465 ps
2274 18:40:36.918588 CH0_RK1: MR19=0x202, MR18=0xA4A4, DQSOSC=465, MR23=63, INC=11, DEC=17
2275 18:40:36.918661 Write Rank1 MR23 =0x3f
2276 18:40:36.918732 [DQSOSC]
2277 18:40:36.918804 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0x202, tDQSOscB0 = 465 ps tDQSOscB1 = 465 ps
2278 18:40:36.918877 CH0 RK1: MR19=202, MR18=A4A4
2279 18:40:36.918948 [RxdqsGatingPostProcess] freq 1600
2280 18:40:36.919019 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2281 18:40:36.919130 Rank: 0
2282 18:40:36.919242 best DQS0 dly(2T, 0.5T) = (2, 6)
2283 18:40:36.919363 best DQS1 dly(2T, 0.5T) = (2, 6)
2284 18:40:36.919489 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2285 18:40:36.919567 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2286 18:40:36.919639 Rank: 1
2287 18:40:36.919712 best DQS0 dly(2T, 0.5T) = (2, 6)
2288 18:40:36.919785 best DQS1 dly(2T, 0.5T) = (2, 6)
2289 18:40:36.919856 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2290 18:40:36.919928 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2291 18:40:36.919999 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2292 18:40:36.920072 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2293 18:40:36.920144 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2294 18:40:36.920215 Write Rank0 MR13 =0x59
2295 18:40:36.920286 ==
2296 18:40:36.920357 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2297 18:40:36.920429 fsp= 1, odt_onoff= 1, Byte mode= 0
2298 18:40:36.920501 ==
2299 18:40:36.920572 === u2Vref_new: 0x56 --> 0x3a
2300 18:40:36.920644 === u2Vref_new: 0x58 --> 0x58
2301 18:40:36.920715 === u2Vref_new: 0x5a --> 0x5a
2302 18:40:36.920787 === u2Vref_new: 0x5c --> 0x78
2303 18:40:36.920859 === u2Vref_new: 0x5e --> 0x7a
2304 18:40:36.920930 === u2Vref_new: 0x60 --> 0x90
2305 18:40:36.921002 [CA 0] Center 37 (12~63) winsize 52
2306 18:40:36.921080 [CA 1] Center 37 (11~63) winsize 53
2307 18:40:36.921153 [CA 2] Center 34 (6~63) winsize 58
2308 18:40:36.921461 [CA 3] Center 34 (6~63) winsize 58
2309 18:40:36.921544 [CA 4] Center 34 (6~63) winsize 58
2310 18:40:36.921618 [CA 5] Center 29 (0~58) winsize 59
2311 18:40:36.921689
2312 18:40:36.921760 [CATrainingPosCal] consider 1 rank data
2313 18:40:36.921833 u2DelayCellTimex100 = 744/100 ps
2314 18:40:36.921905 CA0 delay=37 (12~63),Diff = 8 PI (10 cell)
2315 18:40:36.921977 CA1 delay=37 (11~63),Diff = 8 PI (10 cell)
2316 18:40:36.922048 CA2 delay=34 (6~63),Diff = 5 PI (6 cell)
2317 18:40:36.922120 CA3 delay=34 (6~63),Diff = 5 PI (6 cell)
2318 18:40:36.922191 CA4 delay=34 (6~63),Diff = 5 PI (6 cell)
2319 18:40:36.922262 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2320 18:40:36.922333
2321 18:40:36.922404 CA PerBit enable=1, Macro0, CA PI delay=29
2322 18:40:36.922475 === u2Vref_new: 0x60 --> 0x90
2323 18:40:36.922547
2324 18:40:36.922617 Vref(ca) range 1: 32
2325 18:40:36.922688
2326 18:40:36.922759 CS Dly= 11 (42-0-32)
2327 18:40:36.922830 Write Rank0 MR13 =0xd8
2328 18:40:36.922901 Write Rank0 MR13 =0xd8
2329 18:40:36.922971 Write Rank0 MR12 =0x60
2330 18:40:36.923042 Write Rank1 MR13 =0x59
2331 18:40:36.923113 ==
2332 18:40:36.923184 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2333 18:40:36.923256 fsp= 1, odt_onoff= 1, Byte mode= 0
2334 18:40:36.923327 ==
2335 18:40:36.923399 === u2Vref_new: 0x56 --> 0x3a
2336 18:40:36.923470 === u2Vref_new: 0x58 --> 0x58
2337 18:40:36.923541 === u2Vref_new: 0x5a --> 0x5a
2338 18:40:36.923612 === u2Vref_new: 0x5c --> 0x78
2339 18:40:36.923690 === u2Vref_new: 0x5e --> 0x7a
2340 18:40:36.923754 === u2Vref_new: 0x60 --> 0x90
2341 18:40:36.923817 [CA 0] Center 37 (12~63) winsize 52
2342 18:40:36.923880 [CA 1] Center 37 (11~63) winsize 53
2343 18:40:36.923942 [CA 2] Center 34 (5~63) winsize 59
2344 18:40:36.924005 [CA 3] Center 35 (7~63) winsize 57
2345 18:40:36.924068 [CA 4] Center 34 (5~63) winsize 59
2346 18:40:36.924131 [CA 5] Center 29 (0~59) winsize 60
2347 18:40:36.924199
2348 18:40:36.924461 [CATrainingPosCal] consider 2 rank data
2349 18:40:36.927741 u2DelayCellTimex100 = 744/100 ps
2350 18:40:36.931170 CA0 delay=37 (12~63),Diff = 8 PI (10 cell)
2351 18:40:36.934519 CA1 delay=37 (11~63),Diff = 8 PI (10 cell)
2352 18:40:36.937865 CA2 delay=34 (6~63),Diff = 5 PI (6 cell)
2353 18:40:36.944255 CA3 delay=35 (7~63),Diff = 6 PI (7 cell)
2354 18:40:36.947706 CA4 delay=34 (6~63),Diff = 5 PI (6 cell)
2355 18:40:36.950819 CA5 delay=29 (0~58),Diff = 0 PI (0 cell)
2356 18:40:36.950959
2357 18:40:36.954262 CA PerBit enable=1, Macro0, CA PI delay=29
2358 18:40:36.957260 === u2Vref_new: 0x60 --> 0x90
2359 18:40:36.957409
2360 18:40:36.957522 Vref(ca) range 1: 32
2361 18:40:36.957609
2362 18:40:36.960438 CS Dly= 11 (42-0-32)
2363 18:40:36.963814 Write Rank1 MR13 =0xd8
2364 18:40:36.963911 Write Rank1 MR13 =0xd8
2365 18:40:36.966986 Write Rank1 MR12 =0x60
2366 18:40:36.970464 [RankSwap] Rank num 2, (Multi 1), Rank 0
2367 18:40:36.973819 Write Rank0 MR2 =0xad
2368 18:40:36.973969 [Write Leveling]
2369 18:40:36.976944 delay byte0 byte1 byte2 byte3
2370 18:40:36.977100
2371 18:40:36.980147 10 0 0
2372 18:40:36.980255 11 0 0
2373 18:40:36.980326 12 0 0
2374 18:40:36.983627 13 0 0
2375 18:40:36.983799 14 0 0
2376 18:40:36.986849 15 0 0
2377 18:40:36.987025 16 0 0
2378 18:40:36.987108 17 0 0
2379 18:40:36.989901 18 0 0
2380 18:40:36.990017 19 0 0
2381 18:40:36.993301 20 0 0
2382 18:40:36.993406 21 0 0
2383 18:40:36.996498 22 0 0
2384 18:40:36.996614 23 0 0
2385 18:40:36.996705 24 0 0
2386 18:40:37.000072 25 0 0
2387 18:40:37.000280 26 0 ff
2388 18:40:37.003507 27 0 ff
2389 18:40:37.003742 28 0 ff
2390 18:40:37.006552 29 0 ff
2391 18:40:37.006773 30 0 ff
2392 18:40:37.009913 31 0 ff
2393 18:40:37.010168 32 0 ff
2394 18:40:37.010312 33 ff ff
2395 18:40:37.013223 34 ff ff
2396 18:40:37.013486 35 ff ff
2397 18:40:37.016552 36 ff ff
2398 18:40:37.016822 37 ff ff
2399 18:40:37.019581 38 ff ff
2400 18:40:37.019898 39 ff ff
2401 18:40:37.026689 pass bytecount = 0xff (0xff: all bytes pass)
2402 18:40:37.027047
2403 18:40:37.027265 DQS0 dly: 33
2404 18:40:37.027463 DQS1 dly: 26
2405 18:40:37.029819 Write Rank0 MR2 =0x2d
2406 18:40:37.033324 [RankSwap] Rank num 2, (Multi 1), Rank 0
2407 18:40:37.036373 Write Rank0 MR1 =0xd6
2408 18:40:37.036871 [Gating]
2409 18:40:37.037188 ==
2410 18:40:37.039429 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2411 18:40:37.043226 fsp= 1, odt_onoff= 1, Byte mode= 0
2412 18:40:37.046187 ==
2413 18:40:37.049611 3 1 0 |2c2b 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
2414 18:40:37.052992 3 1 4 |2c2b 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
2415 18:40:37.056151 3 1 8 |2c2b 3434 |(11 11)(11 11) |(1 1)(0 0)| 0
2416 18:40:37.062721 3 1 12 |2c2b 3736 |(11 11)(11 11) |(0 0)(0 0)| 0
2417 18:40:37.065970 3 1 16 |2c2b 3636 |(11 11)(0 0) |(1 0)(0 0)| 0
2418 18:40:37.069196 3 1 20 |2c2b 3535 |(11 11)(11 11) |(1 0)(1 1)| 0
2419 18:40:37.075721 3 1 24 |2c2b 3636 |(11 11)(0 0) |(1 0)(1 1)| 0
2420 18:40:37.078751 3 1 28 |2c2b c0c |(11 11)(1 1) |(1 0)(0 1)| 0
2421 18:40:37.082386 3 2 0 |2c2b e0e |(11 11)(11 11) |(1 0)(0 1)| 0
2422 18:40:37.089176 3 2 4 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 1)| 0
2423 18:40:37.092124 3 2 8 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 1)| 0
2424 18:40:37.095634 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
2425 18:40:37.101682 3 2 16 |201 3534 |(11 11)(11 11) |(0 0)(1 0)| 0
2426 18:40:37.105507 3 2 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
2427 18:40:37.108838 3 2 24 |3534 505 |(11 11)(11 11) |(0 0)(1 1)| 0
2428 18:40:37.114731 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2429 18:40:37.118405 3 3 0 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2430 18:40:37.121316 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2431 18:40:37.128234 3 3 8 |3534 2d2c |(11 11)(11 11) |(1 1)(1 1)| 0
2432 18:40:37.131824 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2433 18:40:37.134481 3 3 16 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2434 18:40:37.140828 3 3 20 |3534 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0
2435 18:40:37.144184 [Byte 0] Lead/lag falling Transition (3, 3, 20)
2436 18:40:37.147960 3 3 24 |3534 201 |(11 11)(11 11) |(0 1)(1 1)| 0
2437 18:40:37.154057 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2438 18:40:37.157369 [Byte 1] Lead/lag falling Transition (3, 3, 28)
2439 18:40:37.160858 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2440 18:40:37.163855 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2441 18:40:37.170518 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2442 18:40:37.173840 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2443 18:40:37.177375 3 4 16 |2928 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2444 18:40:37.183874 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2445 18:40:37.186665 3 4 24 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
2446 18:40:37.190489 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2447 18:40:37.196995 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2448 18:40:37.200060 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2449 18:40:37.203398 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2450 18:40:37.209811 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2451 18:40:37.213203 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2452 18:40:37.216452 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2453 18:40:37.223251 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2454 18:40:37.226166 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2455 18:40:37.229326 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2456 18:40:37.236294 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2457 18:40:37.239546 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2458 18:40:37.242532 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2459 18:40:37.249382 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2460 18:40:37.252474 [Byte 0] Lead/lag Transition tap number (2)
2461 18:40:37.255853 [Byte 1] Lead/lag falling Transition (3, 6, 12)
2462 18:40:37.258907 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2463 18:40:37.265645 3 6 20 |4646 3d3d |(10 10)(11 11) |(0 0)(1 0)| 0
2464 18:40:37.268748 [Byte 1] Lead/lag Transition tap number (3)
2465 18:40:37.271983 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2466 18:40:37.275520 [Byte 0]First pass (3, 6, 24)
2467 18:40:37.278482 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2468 18:40:37.282025 [Byte 1]First pass (3, 6, 28)
2469 18:40:37.284964 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2470 18:40:37.291438 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2471 18:40:37.295246 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2472 18:40:37.298312 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2473 18:40:37.301823 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2474 18:40:37.304860 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2475 18:40:37.311044 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2476 18:40:37.314362 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2477 18:40:37.318017 All bytes gating window > 1UI, Early break!
2478 18:40:37.318530
2479 18:40:37.321168 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2480 18:40:37.321728
2481 18:40:37.324321 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 18)
2482 18:40:37.324834
2483 18:40:37.327598
2484 18:40:37.328005
2485 18:40:37.330656 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2486 18:40:37.331062
2487 18:40:37.333987 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 18)
2488 18:40:37.334394
2489 18:40:37.334717
2490 18:40:37.337192 Write Rank0 MR1 =0x56
2491 18:40:37.337628
2492 18:40:37.340843 best RODT dly(2T, 0.5T) = (2, 3)
2493 18:40:37.341248
2494 18:40:37.343993 best RODT dly(2T, 0.5T) = (2, 3)
2495 18:40:37.344505 ==
2496 18:40:37.346981 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2497 18:40:37.350634 fsp= 1, odt_onoff= 1, Byte mode= 0
2498 18:40:37.351044 ==
2499 18:40:37.357240 Start DQ dly to find pass range UseTestEngine =0
2500 18:40:37.360352 x-axis: bit #, y-axis: DQ dly (-127~63)
2501 18:40:37.360765 RX Vref Scan = 0
2502 18:40:37.363924 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2503 18:40:37.366911 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2504 18:40:37.370408 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2505 18:40:37.373822 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2506 18:40:37.376959 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2507 18:40:37.380221 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2508 18:40:37.380733 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2509 18:40:37.383465 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2510 18:40:37.386466 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2511 18:40:37.389548 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2512 18:40:37.392815 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2513 18:40:37.396392 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2514 18:40:37.399767 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2515 18:40:37.402909 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2516 18:40:37.405939 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2517 18:40:37.406362 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2518 18:40:37.409147 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2519 18:40:37.412666 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2520 18:40:37.415899 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2521 18:40:37.419106 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2522 18:40:37.422225 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2523 18:40:37.425242 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2524 18:40:37.428912 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2525 18:40:37.429325 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2526 18:40:37.432010 -2, [0] xxxoxxxx xoxxxxxo [MSB]
2527 18:40:37.435137 -1, [0] xxxoxxxx xoxxxxxo [MSB]
2528 18:40:37.438604 0, [0] xxxoxxxx ooxxxxxo [MSB]
2529 18:40:37.441652 1, [0] xxooxxxo ooxxxxxo [MSB]
2530 18:40:37.444974 2, [0] xxooxxxx ooxxxxxo [MSB]
2531 18:40:37.448289 3, [0] xxooxxxo ooooxxxo [MSB]
2532 18:40:37.448704 4, [0] oooooxxo oooooooo [MSB]
2533 18:40:37.451726 5, [0] oooooxoo oooooooo [MSB]
2534 18:40:37.454712 6, [0] oooooxoo oooooooo [MSB]
2535 18:40:37.458255 32, [0] oooooooo ooooooox [MSB]
2536 18:40:37.461199 33, [0] oooooooo ooooooox [MSB]
2537 18:40:37.464783 34, [0] oooooooo ooooooox [MSB]
2538 18:40:37.468071 35, [0] ooxxoooo oxooooox [MSB]
2539 18:40:37.471357 36, [0] ooxxoooo oxooooox [MSB]
2540 18:40:37.472002 37, [0] ooxxoooo xxooooox [MSB]
2541 18:40:37.474597 38, [0] oxxxoooo xxooooox [MSB]
2542 18:40:37.477900 39, [0] oxxxooox xxxxooox [MSB]
2543 18:40:37.481178 40, [0] oxxxxoxx xxxxxoox [MSB]
2544 18:40:37.484653 41, [0] xxxxxoxx xxxxxxxx [MSB]
2545 18:40:37.487892 42, [0] xxxxxxxx xxxxxxxx [MSB]
2546 18:40:37.490977 iDelay=42, Bit 0, Center 22 (4 ~ 40) 37
2547 18:40:37.494027 iDelay=42, Bit 1, Center 20 (4 ~ 37) 34
2548 18:40:37.497315 iDelay=42, Bit 2, Center 17 (1 ~ 34) 34
2549 18:40:37.501017 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
2550 18:40:37.504150 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
2551 18:40:37.507317 iDelay=42, Bit 5, Center 24 (7 ~ 41) 35
2552 18:40:37.510595 iDelay=42, Bit 6, Center 22 (5 ~ 39) 35
2553 18:40:37.513844 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
2554 18:40:37.517034 iDelay=42, Bit 8, Center 18 (0 ~ 36) 37
2555 18:40:37.523533 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
2556 18:40:37.527045 iDelay=42, Bit 10, Center 20 (3 ~ 38) 36
2557 18:40:37.530200 iDelay=42, Bit 11, Center 20 (3 ~ 38) 36
2558 18:40:37.533258 iDelay=42, Bit 12, Center 21 (4 ~ 39) 36
2559 18:40:37.536600 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
2560 18:40:37.539891 iDelay=42, Bit 14, Center 22 (4 ~ 40) 37
2561 18:40:37.543361 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
2562 18:40:37.543867 ==
2563 18:40:37.549888 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2564 18:40:37.553047 fsp= 1, odt_onoff= 1, Byte mode= 0
2565 18:40:37.553508 ==
2566 18:40:37.553839 DQS Delay:
2567 18:40:37.556273 DQS0 = 0, DQS1 = 0
2568 18:40:37.556791 DQM Delay:
2569 18:40:37.559576 DQM0 = 20, DQM1 = 19
2570 18:40:37.560066 DQ Delay:
2571 18:40:37.562850 DQ0 =22, DQ1 =20, DQ2 =17, DQ3 =16
2572 18:40:37.566085 DQ4 =21, DQ5 =24, DQ6 =22, DQ7 =20
2573 18:40:37.569543 DQ8 =18, DQ9 =16, DQ10 =20, DQ11 =20
2574 18:40:37.572991 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =13
2575 18:40:37.573550
2576 18:40:37.573881
2577 18:40:37.576347 DramC Write-DBI off
2578 18:40:37.576853 ==
2579 18:40:37.579647 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2580 18:40:37.582712 fsp= 1, odt_onoff= 1, Byte mode= 0
2581 18:40:37.583225 ==
2582 18:40:37.589148 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2583 18:40:37.589601
2584 18:40:37.589935 Begin, DQ Scan Range 922~1178
2585 18:40:37.590235
2586 18:40:37.590520
2587 18:40:37.592109 TX Vref Scan disable
2588 18:40:37.595423 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2589 18:40:37.598773 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2590 18:40:37.602082 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2591 18:40:37.605534 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2592 18:40:37.608614 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2593 18:40:37.615281 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2594 18:40:37.618401 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2595 18:40:37.621696 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2596 18:40:37.624822 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2597 18:40:37.628270 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2598 18:40:37.631578 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2599 18:40:37.634752 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2600 18:40:37.638215 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2601 18:40:37.641213 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2602 18:40:37.644807 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2603 18:40:37.647840 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2604 18:40:37.651482 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2605 18:40:37.658112 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2606 18:40:37.661127 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2607 18:40:37.664302 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2608 18:40:37.667880 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2609 18:40:37.671127 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2610 18:40:37.674093 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2611 18:40:37.677786 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2612 18:40:37.681008 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2613 18:40:37.684135 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2614 18:40:37.687130 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2615 18:40:37.690608 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2616 18:40:37.693736 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2617 18:40:37.697334 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2618 18:40:37.703433 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2619 18:40:37.707024 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2620 18:40:37.710328 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2621 18:40:37.713618 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2622 18:40:37.716866 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2623 18:40:37.719779 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2624 18:40:37.723081 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2625 18:40:37.726222 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2626 18:40:37.729914 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2627 18:40:37.733170 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2628 18:40:37.736512 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2629 18:40:37.739777 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2630 18:40:37.742799 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2631 18:40:37.745990 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2632 18:40:37.749242 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2633 18:40:37.756100 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2634 18:40:37.759403 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2635 18:40:37.762427 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2636 18:40:37.765970 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2637 18:40:37.769133 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2638 18:40:37.772538 972 |3 6 12|[0] xxxxxxxx ooxxxxxo [MSB]
2639 18:40:37.775739 973 |3 6 13|[0] xxxxxxxx oooxxxxo [MSB]
2640 18:40:37.778921 974 |3 6 14|[0] xxxxxxxx oooxxxxo [MSB]
2641 18:40:37.782225 975 |3 6 15|[0] xxxxxxxx oooxoxxo [MSB]
2642 18:40:37.785233 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2643 18:40:37.788617 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2644 18:40:37.792407 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2645 18:40:37.795105 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2646 18:40:37.801713 980 |3 6 20|[0] xooooxxo oooooooo [MSB]
2647 18:40:37.804814 981 |3 6 21|[0] xooooxoo oooooooo [MSB]
2648 18:40:37.808213 988 |3 6 28|[0] oooooooo ooooooox [MSB]
2649 18:40:37.811576 989 |3 6 29|[0] oooooooo ooooooox [MSB]
2650 18:40:37.815282 990 |3 6 30|[0] oooooooo ooooooox [MSB]
2651 18:40:37.818036 991 |3 6 31|[0] oooooooo oxooooox [MSB]
2652 18:40:37.821570 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2653 18:40:37.824619 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2654 18:40:37.828174 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2655 18:40:37.834398 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2656 18:40:37.838133 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2657 18:40:37.840946 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2658 18:40:37.844077 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2659 18:40:37.847642 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2660 18:40:37.850988 1000 |3 6 40|[0] ooxxoooo xxxxxxxx [MSB]
2661 18:40:37.854160 1001 |3 6 41|[0] ooxxoooo xxxxxxxx [MSB]
2662 18:40:37.857482 1002 |3 6 42|[0] ooxxxoxx xxxxxxxx [MSB]
2663 18:40:37.860432 1003 |3 6 43|[0] oxxxxxxx xxxxxxxx [MSB]
2664 18:40:37.863894 1004 |3 6 44|[0] xxxxxxxx xxxxxxxx [MSB]
2665 18:40:37.866995 Byte0, DQ PI dly=990, DQM PI dly= 990
2666 18:40:37.873863 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2667 18:40:37.874391
2668 18:40:37.877348 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2669 18:40:37.877908
2670 18:40:37.880486 Byte1, DQ PI dly=981, DQM PI dly= 981
2671 18:40:37.887194 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
2672 18:40:37.887717
2673 18:40:37.890338 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
2674 18:40:37.890769
2675 18:40:37.891199 ==
2676 18:40:37.896993 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2677 18:40:37.897562 fsp= 1, odt_onoff= 1, Byte mode= 0
2678 18:40:37.899789 ==
2679 18:40:37.903343 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2680 18:40:37.903871
2681 18:40:37.906552 Begin, DQ Scan Range 957~1021
2682 18:40:37.907074 Write Rank0 MR14 =0x0
2683 18:40:37.915771
2684 18:40:37.916304 CH=1, VrefRange= 0, VrefLevel = 0
2685 18:40:37.922620 TX Bit0 (984~998) 15 991, Bit8 (975~988) 14 981,
2686 18:40:37.925620 TX Bit1 (983~998) 16 990, Bit9 (975~985) 11 980,
2687 18:40:37.932570 TX Bit2 (981~996) 16 988, Bit10 (976~991) 16 983,
2688 18:40:37.935868 TX Bit3 (978~992) 15 985, Bit11 (978~990) 13 984,
2689 18:40:37.939115 TX Bit4 (982~998) 17 990, Bit12 (977~990) 14 983,
2690 18:40:37.945705 TX Bit5 (985~998) 14 991, Bit13 (978~991) 14 984,
2691 18:40:37.948723 TX Bit6 (984~997) 14 990, Bit14 (977~990) 14 983,
2692 18:40:37.954948 TX Bit7 (984~998) 15 991, Bit15 (972~982) 11 977,
2693 18:40:37.955458
2694 18:40:37.955892 Write Rank0 MR14 =0x2
2695 18:40:37.964617
2696 18:40:37.965153 CH=1, VrefRange= 0, VrefLevel = 2
2697 18:40:37.971182 TX Bit0 (984~999) 16 991, Bit8 (974~988) 15 981,
2698 18:40:37.974385 TX Bit1 (982~999) 18 990, Bit9 (975~986) 12 980,
2699 18:40:37.980964 TX Bit2 (980~997) 18 988, Bit10 (976~990) 15 983,
2700 18:40:37.984137 TX Bit3 (978~993) 16 985, Bit11 (977~990) 14 983,
2701 18:40:37.987525 TX Bit4 (982~998) 17 990, Bit12 (977~990) 14 983,
2702 18:40:37.993575 TX Bit5 (984~998) 15 991, Bit13 (977~991) 15 984,
2703 18:40:37.997340 TX Bit6 (984~998) 15 991, Bit14 (977~990) 14 983,
2704 18:40:38.003854 TX Bit7 (983~998) 16 990, Bit15 (971~983) 13 977,
2705 18:40:38.004379
2706 18:40:38.004816 Write Rank0 MR14 =0x4
2707 18:40:38.013121
2708 18:40:38.013673 CH=1, VrefRange= 0, VrefLevel = 4
2709 18:40:38.019346 TX Bit0 (984~999) 16 991, Bit8 (973~989) 17 981,
2710 18:40:38.022812 TX Bit1 (982~999) 18 990, Bit9 (974~986) 13 980,
2711 18:40:38.029112 TX Bit2 (980~997) 18 988, Bit10 (976~991) 16 983,
2712 18:40:38.032514 TX Bit3 (978~994) 17 986, Bit11 (977~991) 15 984,
2713 18:40:38.035817 TX Bit4 (982~998) 17 990, Bit12 (977~991) 15 984,
2714 18:40:38.042301 TX Bit5 (984~999) 16 991, Bit13 (977~992) 16 984,
2715 18:40:38.045744 TX Bit6 (983~998) 16 990, Bit14 (977~991) 15 984,
2716 18:40:38.051945 TX Bit7 (983~998) 16 990, Bit15 (971~983) 13 977,
2717 18:40:38.052456
2718 18:40:38.052894 Write Rank0 MR14 =0x6
2719 18:40:38.061797
2720 18:40:38.062317 CH=1, VrefRange= 0, VrefLevel = 6
2721 18:40:38.068246 TX Bit0 (984~1000) 17 992, Bit8 (973~990) 18 981,
2722 18:40:38.071686 TX Bit1 (982~999) 18 990, Bit9 (973~988) 16 980,
2723 18:40:38.078271 TX Bit2 (979~998) 20 988, Bit10 (975~991) 17 983,
2724 18:40:38.081618 TX Bit3 (977~994) 18 985, Bit11 (977~991) 15 984,
2725 18:40:38.084995 TX Bit4 (981~999) 19 990, Bit12 (977~991) 15 984,
2726 18:40:38.091351 TX Bit5 (984~999) 16 991, Bit13 (977~992) 16 984,
2727 18:40:38.094388 TX Bit6 (983~999) 17 991, Bit14 (977~991) 15 984,
2728 18:40:38.101036 TX Bit7 (983~999) 17 991, Bit15 (970~984) 15 977,
2729 18:40:38.101592
2730 18:40:38.101921 Write Rank0 MR14 =0x8
2731 18:40:38.110677
2732 18:40:38.111195 CH=1, VrefRange= 0, VrefLevel = 8
2733 18:40:38.116924 TX Bit0 (984~1000) 17 992, Bit8 (972~990) 19 981,
2734 18:40:38.120045 TX Bit1 (981~1000) 20 990, Bit9 (973~988) 16 980,
2735 18:40:38.126894 TX Bit2 (979~998) 20 988, Bit10 (975~992) 18 983,
2736 18:40:38.129940 TX Bit3 (977~996) 20 986, Bit11 (977~992) 16 984,
2737 18:40:38.133395 TX Bit4 (981~999) 19 990, Bit12 (976~992) 17 984,
2738 18:40:38.140229 TX Bit5 (984~1000) 17 992, Bit13 (977~992) 16 984,
2739 18:40:38.142969 TX Bit6 (982~999) 18 990, Bit14 (976~992) 17 984,
2740 18:40:38.149609 TX Bit7 (983~999) 17 991, Bit15 (970~984) 15 977,
2741 18:40:38.150041
2742 18:40:38.150468 Write Rank0 MR14 =0xa
2743 18:40:38.159795
2744 18:40:38.162952 CH=1, VrefRange= 0, VrefLevel = 10
2745 18:40:38.165977 TX Bit0 (984~1001) 18 992, Bit8 (972~991) 20 981,
2746 18:40:38.169536 TX Bit1 (981~1000) 20 990, Bit9 (973~989) 17 981,
2747 18:40:38.176103 TX Bit2 (979~998) 20 988, Bit10 (975~992) 18 983,
2748 18:40:38.179285 TX Bit3 (977~995) 19 986, Bit11 (976~992) 17 984,
2749 18:40:38.186070 TX Bit4 (981~1000) 20 990, Bit12 (976~992) 17 984,
2750 18:40:38.189088 TX Bit5 (983~1001) 19 992, Bit13 (977~993) 17 985,
2751 18:40:38.192180 TX Bit6 (982~1000) 19 991, Bit14 (976~992) 17 984,
2752 18:40:38.198995 TX Bit7 (982~999) 18 990, Bit15 (970~985) 16 977,
2753 18:40:38.199518
2754 18:40:38.199956 Write Rank0 MR14 =0xc
2755 18:40:38.209280
2756 18:40:38.212577 CH=1, VrefRange= 0, VrefLevel = 12
2757 18:40:38.215432 TX Bit0 (983~1002) 20 992, Bit8 (971~991) 21 981,
2758 18:40:38.218909 TX Bit1 (980~1001) 22 990, Bit9 (972~990) 19 981,
2759 18:40:38.225601 TX Bit2 (978~999) 22 988, Bit10 (974~992) 19 983,
2760 18:40:38.228991 TX Bit3 (977~997) 21 987, Bit11 (976~993) 18 984,
2761 18:40:38.235258 TX Bit4 (980~1000) 21 990, Bit12 (976~992) 17 984,
2762 18:40:38.238669 TX Bit5 (983~1001) 19 992, Bit13 (976~993) 18 984,
2763 18:40:38.241941 TX Bit6 (982~1000) 19 991, Bit14 (976~992) 17 984,
2764 18:40:38.248457 TX Bit7 (981~1000) 20 990, Bit15 (969~985) 17 977,
2765 18:40:38.248987
2766 18:40:38.249314 Write Rank0 MR14 =0xe
2767 18:40:38.258961
2768 18:40:38.262425 CH=1, VrefRange= 0, VrefLevel = 14
2769 18:40:38.265088 TX Bit0 (983~1002) 20 992, Bit8 (971~991) 21 981,
2770 18:40:38.268505 TX Bit1 (981~1001) 21 991, Bit9 (971~990) 20 980,
2771 18:40:38.275316 TX Bit2 (979~999) 21 989, Bit10 (974~993) 20 983,
2772 18:40:38.278509 TX Bit3 (977~997) 21 987, Bit11 (976~993) 18 984,
2773 18:40:38.285256 TX Bit4 (979~1001) 23 990, Bit12 (976~993) 18 984,
2774 18:40:38.288427 TX Bit5 (983~1001) 19 992, Bit13 (976~994) 19 985,
2775 18:40:38.291492 TX Bit6 (982~1001) 20 991, Bit14 (976~992) 17 984,
2776 18:40:38.298028 TX Bit7 (981~1001) 21 991, Bit15 (969~986) 18 977,
2777 18:40:38.298548
2778 18:40:38.298871 Write Rank0 MR14 =0x10
2779 18:40:38.308765
2780 18:40:38.312186 CH=1, VrefRange= 0, VrefLevel = 16
2781 18:40:38.315238 TX Bit0 (983~1003) 21 993, Bit8 (971~992) 22 981,
2782 18:40:38.318602 TX Bit1 (980~1002) 23 991, Bit9 (971~990) 20 980,
2783 18:40:38.325339 TX Bit2 (978~999) 22 988, Bit10 (974~994) 21 984,
2784 18:40:38.328609 TX Bit3 (976~998) 23 987, Bit11 (975~994) 20 984,
2785 18:40:38.334718 TX Bit4 (979~1001) 23 990, Bit12 (975~994) 20 984,
2786 18:40:38.338237 TX Bit5 (983~1002) 20 992, Bit13 (976~994) 19 985,
2787 18:40:38.341488 TX Bit6 (980~1001) 22 990, Bit14 (975~993) 19 984,
2788 18:40:38.347767 TX Bit7 (981~1001) 21 991, Bit15 (970~987) 18 978,
2789 18:40:38.348262
2790 18:40:38.348588 Write Rank0 MR14 =0x12
2791 18:40:38.358763
2792 18:40:38.362317 CH=1, VrefRange= 0, VrefLevel = 18
2793 18:40:38.365047 TX Bit0 (983~1003) 21 993, Bit8 (970~992) 23 981,
2794 18:40:38.368611 TX Bit1 (979~1002) 24 990, Bit9 (970~991) 22 980,
2795 18:40:38.375129 TX Bit2 (977~1000) 24 988, Bit10 (973~994) 22 983,
2796 18:40:38.378502 TX Bit3 (976~998) 23 987, Bit11 (975~994) 20 984,
2797 18:40:38.384919 TX Bit4 (979~1001) 23 990, Bit12 (976~994) 19 985,
2798 18:40:38.388139 TX Bit5 (982~1003) 22 992, Bit13 (976~995) 20 985,
2799 18:40:38.391233 TX Bit6 (980~1001) 22 990, Bit14 (975~993) 19 984,
2800 18:40:38.398118 TX Bit7 (980~1001) 22 990, Bit15 (969~988) 20 978,
2801 18:40:38.398628
2802 18:40:38.401018 Write Rank0 MR14 =0x14
2803 18:40:38.408898
2804 18:40:38.411918 CH=1, VrefRange= 0, VrefLevel = 20
2805 18:40:38.415440 TX Bit0 (982~1004) 23 993, Bit8 (970~992) 23 981,
2806 18:40:38.418531 TX Bit1 (979~1003) 25 991, Bit9 (970~991) 22 980,
2807 18:40:38.425264 TX Bit2 (978~1000) 23 989, Bit10 (973~994) 22 983,
2808 18:40:38.428149 TX Bit3 (976~998) 23 987, Bit11 (975~995) 21 985,
2809 18:40:38.434823 TX Bit4 (979~1002) 24 990, Bit12 (975~995) 21 985,
2810 18:40:38.438141 TX Bit5 (982~1004) 23 993, Bit13 (975~995) 21 985,
2811 18:40:38.441328 TX Bit6 (980~1002) 23 991, Bit14 (975~994) 20 984,
2812 18:40:38.447872 TX Bit7 (980~1002) 23 991, Bit15 (969~989) 21 979,
2813 18:40:38.448365
2814 18:40:38.448694 Write Rank0 MR14 =0x16
2815 18:40:38.458777
2816 18:40:38.462329 CH=1, VrefRange= 0, VrefLevel = 22
2817 18:40:38.465642 TX Bit0 (982~1004) 23 993, Bit8 (970~992) 23 981,
2818 18:40:38.468603 TX Bit1 (979~1003) 25 991, Bit9 (970~991) 22 980,
2819 18:40:38.475321 TX Bit2 (977~1001) 25 989, Bit10 (972~995) 24 983,
2820 18:40:38.478334 TX Bit3 (976~999) 24 987, Bit11 (975~995) 21 985,
2821 18:40:38.484990 TX Bit4 (978~1003) 26 990, Bit12 (975~995) 21 985,
2822 18:40:38.488565 TX Bit5 (981~1003) 23 992, Bit13 (975~996) 22 985,
2823 18:40:38.491734 TX Bit6 (980~1003) 24 991, Bit14 (975~994) 20 984,
2824 18:40:38.498306 TX Bit7 (980~1002) 23 991, Bit15 (968~989) 22 978,
2825 18:40:38.498818
2826 18:40:38.501478 Write Rank0 MR14 =0x18
2827 18:40:38.509608
2828 18:40:38.512544 CH=1, VrefRange= 0, VrefLevel = 24
2829 18:40:38.515776 TX Bit0 (981~1005) 25 993, Bit8 (970~993) 24 981,
2830 18:40:38.518763 TX Bit1 (979~1004) 26 991, Bit9 (970~991) 22 980,
2831 18:40:38.525763 TX Bit2 (977~1001) 25 989, Bit10 (972~995) 24 983,
2832 18:40:38.528613 TX Bit3 (976~999) 24 987, Bit11 (975~996) 22 985,
2833 18:40:38.535312 TX Bit4 (978~1003) 26 990, Bit12 (975~996) 22 985,
2834 18:40:38.538752 TX Bit5 (981~1005) 25 993, Bit13 (975~996) 22 985,
2835 18:40:38.541784 TX Bit6 (979~1003) 25 991, Bit14 (974~995) 22 984,
2836 18:40:38.548404 TX Bit7 (979~1003) 25 991, Bit15 (968~990) 23 979,
2837 18:40:38.548908
2838 18:40:38.549234 Write Rank0 MR14 =0x1a
2839 18:40:38.559394
2840 18:40:38.562473 CH=1, VrefRange= 0, VrefLevel = 26
2841 18:40:38.565798 TX Bit0 (982~1005) 24 993, Bit8 (970~993) 24 981,
2842 18:40:38.569170 TX Bit1 (979~1004) 26 991, Bit9 (970~992) 23 981,
2843 18:40:38.576042 TX Bit2 (977~1002) 26 989, Bit10 (971~995) 25 983,
2844 18:40:38.579087 TX Bit3 (975~999) 25 987, Bit11 (974~997) 24 985,
2845 18:40:38.585209 TX Bit4 (978~1004) 27 991, Bit12 (974~997) 24 985,
2846 18:40:38.588816 TX Bit5 (980~1005) 26 992, Bit13 (974~997) 24 985,
2847 18:40:38.591888 TX Bit6 (979~1004) 26 991, Bit14 (974~995) 22 984,
2848 18:40:38.599112 TX Bit7 (979~1004) 26 991, Bit15 (967~990) 24 978,
2849 18:40:38.599782
2850 18:40:38.601718 Write Rank0 MR14 =0x1c
2851 18:40:38.610079
2852 18:40:38.612900 CH=1, VrefRange= 0, VrefLevel = 28
2853 18:40:38.616401 TX Bit0 (981~1006) 26 993, Bit8 (969~993) 25 981,
2854 18:40:38.619843 TX Bit1 (978~1005) 28 991, Bit9 (969~992) 24 980,
2855 18:40:38.626200 TX Bit2 (977~1002) 26 989, Bit10 (972~997) 26 984,
2856 18:40:38.629154 TX Bit3 (975~1000) 26 987, Bit11 (974~997) 24 985,
2857 18:40:38.636367 TX Bit4 (978~1004) 27 991, Bit12 (973~997) 25 985,
2858 18:40:38.639294 TX Bit5 (980~1005) 26 992, Bit13 (974~998) 25 986,
2859 18:40:38.642511 TX Bit6 (980~1005) 26 992, Bit14 (974~996) 23 985,
2860 18:40:38.648864 TX Bit7 (979~1004) 26 991, Bit15 (967~990) 24 978,
2861 18:40:38.649275
2862 18:40:38.652260 Write Rank0 MR14 =0x1e
2863 18:40:38.660760
2864 18:40:38.663177 CH=1, VrefRange= 0, VrefLevel = 30
2865 18:40:38.666796 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2866 18:40:38.670117 TX Bit1 (978~1005) 28 991, Bit9 (969~992) 24 980,
2867 18:40:38.676744 TX Bit2 (977~1002) 26 989, Bit10 (972~997) 26 984,
2868 18:40:38.680108 TX Bit3 (975~999) 25 987, Bit11 (973~998) 26 985,
2869 18:40:38.686472 TX Bit4 (979~1005) 27 992, Bit12 (973~997) 25 985,
2870 18:40:38.689598 TX Bit5 (980~1006) 27 993, Bit13 (974~998) 25 986,
2871 18:40:38.692921 TX Bit6 (978~1005) 28 991, Bit14 (973~997) 25 985,
2872 18:40:38.699306 TX Bit7 (978~1004) 27 991, Bit15 (967~991) 25 979,
2873 18:40:38.699881
2874 18:40:38.700213 Write Rank0 MR14 =0x20
2875 18:40:38.710595
2876 18:40:38.713907 CH=1, VrefRange= 0, VrefLevel = 32
2877 18:40:38.717026 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2878 18:40:38.720311 TX Bit1 (978~1005) 28 991, Bit9 (969~992) 24 980,
2879 18:40:38.726807 TX Bit2 (977~1002) 26 989, Bit10 (972~997) 26 984,
2880 18:40:38.730025 TX Bit3 (975~999) 25 987, Bit11 (973~998) 26 985,
2881 18:40:38.736865 TX Bit4 (979~1005) 27 992, Bit12 (973~997) 25 985,
2882 18:40:38.740213 TX Bit5 (980~1006) 27 993, Bit13 (974~998) 25 986,
2883 18:40:38.743478 TX Bit6 (978~1005) 28 991, Bit14 (973~997) 25 985,
2884 18:40:38.749805 TX Bit7 (978~1004) 27 991, Bit15 (967~991) 25 979,
2885 18:40:38.750214
2886 18:40:38.750527 Write Rank0 MR14 =0x22
2887 18:40:38.760960
2888 18:40:38.764193 CH=1, VrefRange= 0, VrefLevel = 34
2889 18:40:38.767442 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2890 18:40:38.771065 TX Bit1 (978~1005) 28 991, Bit9 (969~992) 24 980,
2891 18:40:38.777581 TX Bit2 (977~1002) 26 989, Bit10 (972~997) 26 984,
2892 18:40:38.780504 TX Bit3 (975~999) 25 987, Bit11 (973~998) 26 985,
2893 18:40:38.787284 TX Bit4 (979~1005) 27 992, Bit12 (973~997) 25 985,
2894 18:40:38.790674 TX Bit5 (980~1006) 27 993, Bit13 (974~998) 25 986,
2895 18:40:38.793638 TX Bit6 (978~1005) 28 991, Bit14 (973~997) 25 985,
2896 18:40:38.800772 TX Bit7 (978~1004) 27 991, Bit15 (967~991) 25 979,
2897 18:40:38.801273
2898 18:40:38.803601 wait MRW command Rank0 MR14 =0x24 fired (1)
2899 18:40:38.806678 Write Rank0 MR14 =0x24
2900 18:40:38.815163
2901 18:40:38.818279 CH=1, VrefRange= 0, VrefLevel = 36
2902 18:40:38.821925 TX Bit0 (980~1006) 27 993, Bit8 (969~993) 25 981,
2903 18:40:38.825042 TX Bit1 (978~1005) 28 991, Bit9 (969~992) 24 980,
2904 18:40:38.831686 TX Bit2 (977~1002) 26 989, Bit10 (972~997) 26 984,
2905 18:40:38.834760 TX Bit3 (975~999) 25 987, Bit11 (973~998) 26 985,
2906 18:40:38.841209 TX Bit4 (979~1005) 27 992, Bit12 (973~997) 25 985,
2907 18:40:38.844795 TX Bit5 (980~1006) 27 993, Bit13 (974~998) 25 986,
2908 18:40:38.848034 TX Bit6 (978~1005) 28 991, Bit14 (973~997) 25 985,
2909 18:40:38.854385 TX Bit7 (978~1004) 27 991, Bit15 (967~991) 25 979,
2910 18:40:38.854828
2911 18:40:38.855247
2912 18:40:38.857882 TX Vref found, early break! 390< 395
2913 18:40:38.861085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
2914 18:40:38.864006 u1DelayCellOfst[0]=7 cells (6 PI)
2915 18:40:38.867736 u1DelayCellOfst[1]=5 cells (4 PI)
2916 18:40:38.870712 u1DelayCellOfst[2]=2 cells (2 PI)
2917 18:40:38.874011 u1DelayCellOfst[3]=0 cells (0 PI)
2918 18:40:38.877258 u1DelayCellOfst[4]=6 cells (5 PI)
2919 18:40:38.880776 u1DelayCellOfst[5]=7 cells (6 PI)
2920 18:40:38.883818 u1DelayCellOfst[6]=5 cells (4 PI)
2921 18:40:38.887275 u1DelayCellOfst[7]=5 cells (4 PI)
2922 18:40:38.890423 Byte0, DQ PI dly=987, DQM PI dly= 990
2923 18:40:38.893800 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2924 18:40:38.894327
2925 18:40:38.897296 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2926 18:40:38.900604
2927 18:40:38.901131 u1DelayCellOfst[8]=2 cells (2 PI)
2928 18:40:38.903616 u1DelayCellOfst[9]=1 cells (1 PI)
2929 18:40:38.907057 u1DelayCellOfst[10]=6 cells (5 PI)
2930 18:40:38.910382 u1DelayCellOfst[11]=7 cells (6 PI)
2931 18:40:38.913488 u1DelayCellOfst[12]=7 cells (6 PI)
2932 18:40:38.916963 u1DelayCellOfst[13]=9 cells (7 PI)
2933 18:40:38.919904 u1DelayCellOfst[14]=7 cells (6 PI)
2934 18:40:38.923198 u1DelayCellOfst[15]=0 cells (0 PI)
2935 18:40:38.926356 Byte1, DQ PI dly=979, DQM PI dly= 982
2936 18:40:38.929640 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2937 18:40:38.932963
2938 18:40:38.935878 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2939 18:40:38.936286
2940 18:40:38.939230 wait MRW command Rank0 MR14 =0x1e fired (1)
2941 18:40:38.942675 Write Rank0 MR14 =0x1e
2942 18:40:38.943209
2943 18:40:38.943538 Final TX Range 0 Vref 30
2944 18:40:38.943841
2945 18:40:38.949033 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2946 18:40:38.952340
2947 18:40:38.955475 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2948 18:40:38.965345 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2949 18:40:38.972007 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2950 18:40:38.972508 Write Rank0 MR3 =0xb0
2951 18:40:38.975328 DramC Write-DBI on
2952 18:40:38.975736 ==
2953 18:40:38.982080 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2954 18:40:38.982597 fsp= 1, odt_onoff= 1, Byte mode= 0
2955 18:40:38.985123 ==
2956 18:40:38.988379 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2957 18:40:38.988791
2958 18:40:38.991485 Begin, DQ Scan Range 702~766
2959 18:40:38.991894
2960 18:40:38.992217
2961 18:40:38.992512 TX Vref Scan disable
2962 18:40:38.994887 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2963 18:40:39.001661 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2964 18:40:39.004952 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2965 18:40:39.008512 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2966 18:40:39.011640 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2967 18:40:39.014745 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2968 18:40:39.018125 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2969 18:40:39.021590 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2970 18:40:39.024761 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2971 18:40:39.027877 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2972 18:40:39.031556 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2973 18:40:39.034155 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2974 18:40:39.037527 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2975 18:40:39.041152 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2976 18:40:39.044138 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2977 18:40:39.047212 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2978 18:40:39.053810 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2979 18:40:39.057276 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2980 18:40:39.060746 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2981 18:40:39.063755 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2982 18:40:39.070229 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2983 18:40:39.073786 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2984 18:40:39.076946 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2985 18:40:39.080354 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2986 18:40:39.083528 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2987 18:40:39.086835 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2988 18:40:39.089793 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2989 18:40:39.093397 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2990 18:40:39.096538 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2991 18:40:39.100059 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2992 18:40:39.103044 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2993 18:40:39.106072 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2994 18:40:39.112609 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
2995 18:40:39.115946 Byte0, DQ PI dly=735, DQM PI dly= 735
2996 18:40:39.119767 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
2997 18:40:39.120274
2998 18:40:39.122439 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
2999 18:40:39.122845
3000 18:40:39.126084 Byte1, DQ PI dly=725, DQM PI dly= 725
3001 18:40:39.132556 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 21)
3002 18:40:39.133065
3003 18:40:39.135778 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 21)
3004 18:40:39.136298
3005 18:40:39.142411 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3006 18:40:39.148805 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3007 18:40:39.155314 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3008 18:40:39.158766 Write Rank0 MR3 =0x30
3009 18:40:39.159278 DramC Write-DBI off
3010 18:40:39.162345
3011 18:40:39.162857 [DATLAT]
3012 18:40:39.165492 Freq=1600, CH1 RK0, use_rxtx_scan=0
3013 18:40:39.166035
3014 18:40:39.166368 DATLAT Default: 0xf
3015 18:40:39.168451 7, 0xFFFF, sum=0
3016 18:40:39.168863 8, 0xFFFF, sum=0
3017 18:40:39.171776 9, 0xFFFF, sum=0
3018 18:40:39.172294 10, 0xFFFF, sum=0
3019 18:40:39.175325 11, 0xFFFF, sum=0
3020 18:40:39.175842 12, 0xFFFF, sum=0
3021 18:40:39.178185 13, 0xFFFF, sum=0
3022 18:40:39.178598 14, 0x0, sum=1
3023 18:40:39.181612 15, 0x0, sum=2
3024 18:40:39.182116 16, 0x0, sum=3
3025 18:40:39.182444 17, 0x0, sum=4
3026 18:40:39.188309 pattern=2 first_step=14 total pass=5 best_step=16
3027 18:40:39.188857 ==
3028 18:40:39.191473 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3029 18:40:39.194709 fsp= 1, odt_onoff= 1, Byte mode= 0
3030 18:40:39.195128 ==
3031 18:40:39.201455 Start DQ dly to find pass range UseTestEngine =1
3032 18:40:39.204687 x-axis: bit #, y-axis: DQ dly (-127~63)
3033 18:40:39.205202 RX Vref Scan = 1
3034 18:40:39.313362
3035 18:40:39.313926 RX Vref found, early break!
3036 18:40:39.314260
3037 18:40:39.319499 Final RX Vref 11, apply to both rank0 and 1
3038 18:40:39.320016 ==
3039 18:40:39.322714 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3040 18:40:39.325894 fsp= 1, odt_onoff= 1, Byte mode= 0
3041 18:40:39.326419 ==
3042 18:40:39.329108 DQS Delay:
3043 18:40:39.329583 DQS0 = 0, DQS1 = 0
3044 18:40:39.329923 DQM Delay:
3045 18:40:39.332532 DQM0 = 20, DQM1 = 18
3046 18:40:39.333204 DQ Delay:
3047 18:40:39.335931 DQ0 =21, DQ1 =21, DQ2 =17, DQ3 =15
3048 18:40:39.339117 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3049 18:40:39.342269 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =20
3050 18:40:39.345466 DQ12 =21, DQ13 =21, DQ14 =21, DQ15 =13
3051 18:40:39.345884
3052 18:40:39.346208
3053 18:40:39.346510
3054 18:40:39.348689 [DramC_TX_OE_Calibration] TA2
3055 18:40:39.352207 Original DQ_B0 (3 6) =30, OEN = 27
3056 18:40:39.355302 Original DQ_B1 (3 6) =30, OEN = 27
3057 18:40:39.358734 23, 0x0, End_B0=23 End_B1=23
3058 18:40:39.361798 24, 0x0, End_B0=24 End_B1=24
3059 18:40:39.362219 25, 0x0, End_B0=25 End_B1=25
3060 18:40:39.365342 26, 0x0, End_B0=26 End_B1=26
3061 18:40:39.368627 27, 0x0, End_B0=27 End_B1=27
3062 18:40:39.371756 28, 0x0, End_B0=28 End_B1=28
3063 18:40:39.375235 29, 0x0, End_B0=29 End_B1=29
3064 18:40:39.375763 30, 0x0, End_B0=30 End_B1=30
3065 18:40:39.378425 31, 0xFFFF, End_B0=30 End_B1=30
3066 18:40:39.384918 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3067 18:40:39.391271 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3068 18:40:39.391693
3069 18:40:39.392019
3070 18:40:39.392322 Write Rank0 MR23 =0x3f
3071 18:40:39.394448 [DQSOSC]
3072 18:40:39.401251 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2b2, (MSB)MR19= 0x202, tDQSOscB0 = 456 ps tDQSOscB1 = 456 ps
3073 18:40:39.408061 CH1_RK0: MR19=0x202, MR18=0xB2B2, DQSOSC=456, MR23=63, INC=11, DEC=17
3074 18:40:39.411356 Write Rank0 MR23 =0x3f
3075 18:40:39.411873 [DQSOSC]
3076 18:40:39.417406 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3b3, (MSB)MR19= 0x202, tDQSOscB0 = 455 ps tDQSOscB1 = 455 ps
3077 18:40:39.421028 CH1 RK0: MR19=202, MR18=B3B3
3078 18:40:39.424223 [RankSwap] Rank num 2, (Multi 1), Rank 1
3079 18:40:39.427371 Write Rank0 MR2 =0xad
3080 18:40:39.427917 [Write Leveling]
3081 18:40:39.430801 delay byte0 byte1 byte2 byte3
3082 18:40:39.431322
3083 18:40:39.433832 10 0 0
3084 18:40:39.434302 11 0 0
3085 18:40:39.437560 12 0 0
3086 18:40:39.438082 13 0 0
3087 18:40:39.438420 14 0 0
3088 18:40:39.440792 15 0 0
3089 18:40:39.441313 16 0 0
3090 18:40:39.444156 17 0 0
3091 18:40:39.444726 18 0 0
3092 18:40:39.445082 19 0 0
3093 18:40:39.446855 20 0 0
3094 18:40:39.447272 21 0 0
3095 18:40:39.450429 22 0 0
3096 18:40:39.450847 23 0 0
3097 18:40:39.453786 24 0 0
3098 18:40:39.454307 25 0 0
3099 18:40:39.454640 26 0 0
3100 18:40:39.456942 27 0 0
3101 18:40:39.457359 28 0 ff
3102 18:40:39.460202 29 0 ff
3103 18:40:39.460620 30 0 ff
3104 18:40:39.463724 31 0 ff
3105 18:40:39.464234 32 0 ff
3106 18:40:39.466732 33 0 ff
3107 18:40:39.467156 34 ff ff
3108 18:40:39.467613 35 ff ff
3109 18:40:39.469819 36 ff ff
3110 18:40:39.470241 37 ff ff
3111 18:40:39.473566 38 ff ff
3112 18:40:39.474076 39 ff ff
3113 18:40:39.476728 40 ff ff
3114 18:40:39.479796 pass bytecount = 0xff (0xff: all bytes pass)
3115 18:40:39.480388
3116 18:40:39.483213 DQS0 dly: 34
3117 18:40:39.483723 DQS1 dly: 28
3118 18:40:39.484051 Write Rank0 MR2 =0x2d
3119 18:40:39.489632 [RankSwap] Rank num 2, (Multi 1), Rank 0
3120 18:40:39.490137 Write Rank1 MR1 =0xd6
3121 18:40:39.490466 [Gating]
3122 18:40:39.492649 ==
3123 18:40:39.496076 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3124 18:40:39.499184 fsp= 1, odt_onoff= 1, Byte mode= 0
3125 18:40:39.499603 ==
3126 18:40:39.502956 3 1 0 |2c2b 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
3127 18:40:39.509328 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3128 18:40:39.512623 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3129 18:40:39.515536 3 1 12 |2c2b 3535 |(11 11)(11 11) |(0 0)(1 1)| 0
3130 18:40:39.522438 3 1 16 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0
3131 18:40:39.526031 3 1 20 |2c2b 3535 |(11 11)(11 11) |(1 0)(0 0)| 0
3132 18:40:39.528535 3 1 24 |2c2b 3535 |(11 11)(0 0) |(1 0)(1 1)| 0
3133 18:40:39.535375 3 1 28 |2c2b 3535 |(11 11)(0 0) |(1 0)(1 1)| 0
3134 18:40:39.538371 3 2 0 |2c2b 1212 |(11 11)(11 11) |(1 0)(0 1)| 0
3135 18:40:39.542032 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 0)| 0
3136 18:40:39.548735 3 2 8 |2c2b 3535 |(11 11)(0 0) |(1 0)(0 1)| 0
3137 18:40:39.551702 3 2 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
3138 18:40:39.555287 3 2 16 |2c2c 3534 |(11 10)(11 11) |(1 0)(0 1)| 0
3139 18:40:39.561781 3 2 20 |201 3433 |(11 11)(11 11) |(0 0)(0 1)| 0
3140 18:40:39.565211 3 2 24 |3534 3433 |(11 11)(11 11) |(0 0)(1 1)| 0
3141 18:40:39.568075 3 2 28 |3534 201 |(11 11)(11 11) |(0 0)(1 1)| 0
3142 18:40:39.575005 3 3 0 |3534 3d3d |(11 11)(0 0) |(0 0)(1 1)| 0
3143 18:40:39.578066 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3144 18:40:39.581351 3 3 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3145 18:40:39.584596 3 3 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3146 18:40:39.591151 3 3 16 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3147 18:40:39.594313 3 3 20 |3534 3c3c |(11 11)(11 11) |(1 1)(1 1)| 0
3148 18:40:39.600848 3 3 24 |3534 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3149 18:40:39.604524 [Byte 0] Lead/lag falling Transition (3, 3, 24)
3150 18:40:39.607802 3 3 28 |3534 303 |(11 11)(11 11) |(0 1)(1 1)| 0
3151 18:40:39.610490 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3152 18:40:39.617331 [Byte 1] Lead/lag falling Transition (3, 4, 0)
3153 18:40:39.620782 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3154 18:40:39.623582 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3155 18:40:39.630726 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3156 18:40:39.634046 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3157 18:40:39.637208 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3158 18:40:39.643495 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3159 18:40:39.646698 3 4 28 |3d3d 3d3d |(11 11)(10 10) |(1 1)(1 1)| 0
3160 18:40:39.649744 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3161 18:40:39.656747 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3162 18:40:39.659662 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3163 18:40:39.663043 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3164 18:40:39.669543 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3165 18:40:39.673167 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3166 18:40:39.676170 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3167 18:40:39.683038 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3168 18:40:39.686105 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3169 18:40:39.689401 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3170 18:40:39.695916 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3171 18:40:39.699228 [Byte 0] Lead/lag falling Transition (3, 6, 8)
3172 18:40:39.702072 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3173 18:40:39.705837 [Byte 0] Lead/lag Transition tap number (2)
3174 18:40:39.712157 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3175 18:40:39.715390 [Byte 1] Lead/lag falling Transition (3, 6, 16)
3176 18:40:39.719107 3 6 20 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3177 18:40:39.725469 [Byte 1] Lead/lag Transition tap number (2)
3178 18:40:39.728665 3 6 24 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
3179 18:40:39.731987 [Byte 0]First pass (3, 6, 24)
3180 18:40:39.734829 3 6 28 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
3181 18:40:39.738141 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3182 18:40:39.741501 [Byte 1]First pass (3, 7, 0)
3183 18:40:39.745044 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3184 18:40:39.748654 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3185 18:40:39.755004 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3186 18:40:39.758138 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3187 18:40:39.761208 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3188 18:40:39.764479 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3189 18:40:39.770994 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3190 18:40:39.774256 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3191 18:40:39.777836 All bytes gating window > 1UI, Early break!
3192 18:40:39.778345
3193 18:40:39.781021 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
3194 18:40:39.781560
3195 18:40:39.784204 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
3196 18:40:39.784709
3197 18:40:39.785034
3198 18:40:39.785333
3199 18:40:39.790587 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3200 18:40:39.791104
3201 18:40:39.793890 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
3202 18:40:39.794306
3203 18:40:39.794631
3204 18:40:39.796549 Write Rank1 MR1 =0x56
3205 18:40:39.796639
3206 18:40:39.799759 best RODT dly(2T, 0.5T) = (2, 3)
3207 18:40:39.799856
3208 18:40:39.799932 best RODT dly(2T, 0.5T) = (2, 3)
3209 18:40:39.803000 ==
3210 18:40:39.806419 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3211 18:40:39.809582 fsp= 1, odt_onoff= 1, Byte mode= 0
3212 18:40:39.809680 ==
3213 18:40:39.813009 Start DQ dly to find pass range UseTestEngine =0
3214 18:40:39.819584 x-axis: bit #, y-axis: DQ dly (-127~63)
3215 18:40:39.819752 RX Vref Scan = 0
3216 18:40:39.823197 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3217 18:40:39.826073 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3218 18:40:39.829334 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3219 18:40:39.832832 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3220 18:40:39.832951 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3221 18:40:39.836132 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3222 18:40:39.839363 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3223 18:40:39.842792 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3224 18:40:39.845919 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3225 18:40:39.849475 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3226 18:40:39.852466 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3227 18:40:39.855996 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3228 18:40:39.859088 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3229 18:40:39.862343 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3230 18:40:39.862715 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3231 18:40:39.866033 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3232 18:40:39.869160 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3233 18:40:39.872428 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3234 18:40:39.875681 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3235 18:40:39.879119 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3236 18:40:39.882142 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3237 18:40:39.885321 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3238 18:40:39.885802 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3239 18:40:39.888693 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3240 18:40:39.891778 -2, [0] xxxxxxxx xxxxxxxo [MSB]
3241 18:40:39.895291 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3242 18:40:39.898701 0, [0] xxxoxxxx ooxxxxxo [MSB]
3243 18:40:39.901732 1, [0] xxxoxxxx ooxxxxxo [MSB]
3244 18:40:39.905223 2, [0] xxooxxxx ooxxoxxo [MSB]
3245 18:40:39.905701 3, [0] xxooxxxo oooxoxxo [MSB]
3246 18:40:39.908169 4, [0] xxooxxxo oooxoxxo [MSB]
3247 18:40:39.911618 32, [0] oooooooo ooooooox [MSB]
3248 18:40:39.915041 33, [0] oooooooo ooooooox [MSB]
3249 18:40:39.918087 34, [0] oooooooo ooooooox [MSB]
3250 18:40:39.921183 35, [0] ooxxoooo oxooooox [MSB]
3251 18:40:39.924441 36, [0] ooxxoooo xxooooox [MSB]
3252 18:40:39.927818 37, [0] ooxxoooo xxooooox [MSB]
3253 18:40:39.928397 38, [0] ooxxoooo xxooooox [MSB]
3254 18:40:39.931605 39, [0] oxxxooox xxooooox [MSB]
3255 18:40:39.934299 40, [0] oxxxooox xxxxooox [MSB]
3256 18:40:39.937865 41, [0] xxxxxoxx xxxxxoox [MSB]
3257 18:40:39.941242 42, [0] xxxxxoxx xxxxxxxx [MSB]
3258 18:40:39.944128 43, [0] xxxxxxxx xxxxxxxx [MSB]
3259 18:40:39.947555 iDelay=43, Bit 0, Center 22 (5 ~ 40) 36
3260 18:40:39.950727 iDelay=43, Bit 1, Center 21 (5 ~ 38) 34
3261 18:40:39.953995 iDelay=43, Bit 2, Center 18 (2 ~ 34) 33
3262 18:40:39.957287 iDelay=43, Bit 3, Center 16 (-1 ~ 34) 36
3263 18:40:39.960687 iDelay=43, Bit 4, Center 22 (5 ~ 40) 36
3264 18:40:39.963711 iDelay=43, Bit 5, Center 23 (5 ~ 42) 38
3265 18:40:39.967058 iDelay=43, Bit 6, Center 22 (5 ~ 40) 36
3266 18:40:39.970369 iDelay=43, Bit 7, Center 20 (3 ~ 38) 36
3267 18:40:39.973824 iDelay=43, Bit 8, Center 17 (0 ~ 35) 36
3268 18:40:39.980341 iDelay=43, Bit 9, Center 16 (-1 ~ 34) 36
3269 18:40:39.983846 iDelay=43, Bit 10, Center 21 (3 ~ 39) 37
3270 18:40:39.986922 iDelay=43, Bit 11, Center 22 (5 ~ 39) 35
3271 18:40:39.990380 iDelay=43, Bit 12, Center 21 (2 ~ 40) 39
3272 18:40:39.993465 iDelay=43, Bit 13, Center 23 (5 ~ 41) 37
3273 18:40:39.996593 iDelay=43, Bit 14, Center 23 (5 ~ 41) 37
3274 18:40:39.999809 iDelay=43, Bit 15, Center 13 (-4 ~ 31) 36
3275 18:40:40.000279 ==
3276 18:40:40.006452 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3277 18:40:40.009666 fsp= 1, odt_onoff= 1, Byte mode= 0
3278 18:40:40.010071 ==
3279 18:40:40.010418 DQS Delay:
3280 18:40:40.012767 DQS0 = 0, DQS1 = 0
3281 18:40:40.013188 DQM Delay:
3282 18:40:40.016598 DQM0 = 20, DQM1 = 19
3283 18:40:40.017092 DQ Delay:
3284 18:40:40.019451 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3285 18:40:40.022681 DQ4 =22, DQ5 =23, DQ6 =22, DQ7 =20
3286 18:40:40.025752 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3287 18:40:40.029314 DQ12 =21, DQ13 =23, DQ14 =23, DQ15 =13
3288 18:40:40.029777
3289 18:40:40.030099
3290 18:40:40.032323 DramC Write-DBI off
3291 18:40:40.032728 ==
3292 18:40:40.035838 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3293 18:40:40.039150 fsp= 1, odt_onoff= 1, Byte mode= 0
3294 18:40:40.039556 ==
3295 18:40:40.042410 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3296 18:40:40.045523
3297 18:40:40.046070 Begin, DQ Scan Range 924~1180
3298 18:40:40.046528
3299 18:40:40.046833
3300 18:40:40.048923 TX Vref Scan disable
3301 18:40:40.051990 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3302 18:40:40.055374 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3303 18:40:40.058526 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3304 18:40:40.062140 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3305 18:40:40.065475 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3306 18:40:40.071566 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3307 18:40:40.075165 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3308 18:40:40.078748 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3309 18:40:40.081591 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3310 18:40:40.084910 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3311 18:40:40.088075 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3312 18:40:40.091284 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3313 18:40:40.095152 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3314 18:40:40.098189 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3315 18:40:40.101563 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3316 18:40:40.104457 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3317 18:40:40.108113 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3318 18:40:40.111027 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3319 18:40:40.117910 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3320 18:40:40.121141 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3321 18:40:40.124156 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3322 18:40:40.127591 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3323 18:40:40.130742 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3324 18:40:40.134182 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3325 18:40:40.137355 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3326 18:40:40.140766 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3327 18:40:40.143735 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3328 18:40:40.147013 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3329 18:40:40.150304 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3330 18:40:40.153728 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3331 18:40:40.160377 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3332 18:40:40.163710 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3333 18:40:40.166824 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3334 18:40:40.170218 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3335 18:40:40.173250 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3336 18:40:40.176881 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3337 18:40:40.179952 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3338 18:40:40.183107 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3339 18:40:40.186782 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3340 18:40:40.189910 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3341 18:40:40.192873 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3342 18:40:40.196311 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3343 18:40:40.199557 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3344 18:40:40.202946 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3345 18:40:40.206082 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3346 18:40:40.209473 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3347 18:40:40.215704 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3348 18:40:40.219156 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3349 18:40:40.222242 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3350 18:40:40.225551 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3351 18:40:40.228979 974 |3 6 14|[0] xxxxxxxx xoxxxxxo [MSB]
3352 18:40:40.232325 975 |3 6 15|[0] xxxxxxxx ooxxxxxo [MSB]
3353 18:40:40.235455 976 |3 6 16|[0] xxxxxxxx oooxxxoo [MSB]
3354 18:40:40.238539 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3355 18:40:40.242015 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
3356 18:40:40.245119 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
3357 18:40:40.248302 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
3358 18:40:40.251830 981 |3 6 21|[0] xxxxxxxx oooooooo [MSB]
3359 18:40:40.255157 982 |3 6 22|[0] xooooxoo oooooooo [MSB]
3360 18:40:40.262679 991 |3 6 31|[0] oooooooo ooooooox [MSB]
3361 18:40:40.266114 992 |3 6 32|[0] oooooooo oxooooox [MSB]
3362 18:40:40.269133 993 |3 6 33|[0] oooooooo xxooooox [MSB]
3363 18:40:40.272472 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3364 18:40:40.275967 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3365 18:40:40.279202 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3366 18:40:40.282501 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3367 18:40:40.285567 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3368 18:40:40.288755 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3369 18:40:40.292703 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
3370 18:40:40.295626 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
3371 18:40:40.301844 1002 |3 6 42|[0] ooxxoooo xxxxxxxx [MSB]
3372 18:40:40.305349 1003 |3 6 43|[0] ooxxooox xxxxxxxx [MSB]
3373 18:40:40.308625 1004 |3 6 44|[0] ooxxooox xxxxxxxx [MSB]
3374 18:40:40.311817 1005 |3 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
3375 18:40:40.315627 Byte0, DQ PI dly=991, DQM PI dly= 991
3376 18:40:40.318295 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 31)
3377 18:40:40.318577
3378 18:40:40.325029 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 31)
3379 18:40:40.325479
3380 18:40:40.328469 Byte1, DQ PI dly=983, DQM PI dly= 983
3381 18:40:40.331380 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3382 18:40:40.331815
3383 18:40:40.334795 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3384 18:40:40.335295
3385 18:40:40.337922 ==
3386 18:40:40.341220 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3387 18:40:40.344860 fsp= 1, odt_onoff= 1, Byte mode= 0
3388 18:40:40.345355 ==
3389 18:40:40.348173 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3390 18:40:40.348672
3391 18:40:40.351090 Begin, DQ Scan Range 959~1023
3392 18:40:40.354368 Write Rank1 MR14 =0x0
3393 18:40:40.362454
3394 18:40:40.362963 CH=1, VrefRange= 0, VrefLevel = 0
3395 18:40:40.369023 TX Bit0 (985~1001) 17 993, Bit8 (977~987) 11 982,
3396 18:40:40.372309 TX Bit1 (984~999) 16 991, Bit9 (976~987) 12 981,
3397 18:40:40.379032 TX Bit2 (983~997) 15 990, Bit10 (978~992) 15 985,
3398 18:40:40.382348 TX Bit3 (979~992) 14 985, Bit11 (979~992) 14 985,
3399 18:40:40.385477 TX Bit4 (984~999) 16 991, Bit12 (979~990) 12 984,
3400 18:40:40.391939 TX Bit5 (985~1000) 16 992, Bit13 (979~993) 15 986,
3401 18:40:40.394991 TX Bit6 (984~999) 16 991, Bit14 (979~991) 13 985,
3402 18:40:40.401791 TX Bit7 (984~998) 15 991, Bit15 (974~984) 11 979,
3403 18:40:40.402307
3404 18:40:40.402628 Write Rank1 MR14 =0x2
3405 18:40:40.411109
3406 18:40:40.411611 CH=1, VrefRange= 0, VrefLevel = 2
3407 18:40:40.417969 TX Bit0 (985~1001) 17 993, Bit8 (977~989) 13 983,
3408 18:40:40.421157 TX Bit1 (984~999) 16 991, Bit9 (976~988) 13 982,
3409 18:40:40.427750 TX Bit2 (983~998) 16 990, Bit10 (977~993) 17 985,
3410 18:40:40.430767 TX Bit3 (980~993) 14 986, Bit11 (978~993) 16 985,
3411 18:40:40.434464 TX Bit4 (983~999) 17 991, Bit12 (980~991) 12 985,
3412 18:40:40.440788 TX Bit5 (985~1001) 17 993, Bit13 (979~993) 15 986,
3413 18:40:40.444173 TX Bit6 (984~999) 16 991, Bit14 (978~991) 14 984,
3414 18:40:40.450539 TX Bit7 (984~998) 15 991, Bit15 (973~985) 13 979,
3415 18:40:40.450948
3416 18:40:40.451260 Write Rank1 MR14 =0x4
3417 18:40:40.460335
3418 18:40:40.460899 CH=1, VrefRange= 0, VrefLevel = 4
3419 18:40:40.467028 TX Bit0 (984~1002) 19 993, Bit8 (977~990) 14 983,
3420 18:40:40.470401 TX Bit1 (984~1000) 17 992, Bit9 (975~989) 15 982,
3421 18:40:40.476906 TX Bit2 (982~998) 17 990, Bit10 (977~994) 18 985,
3422 18:40:40.480116 TX Bit3 (979~995) 17 987, Bit11 (978~993) 16 985,
3423 18:40:40.483424 TX Bit4 (983~1000) 18 991, Bit12 (978~991) 14 984,
3424 18:40:40.489843 TX Bit5 (984~1001) 18 992, Bit13 (979~994) 16 986,
3425 18:40:40.493065 TX Bit6 (984~1000) 17 992, Bit14 (978~991) 14 984,
3426 18:40:40.499357 TX Bit7 (984~998) 15 991, Bit15 (972~986) 15 979,
3427 18:40:40.499798
3428 18:40:40.500122 Write Rank1 MR14 =0x6
3429 18:40:40.509627
3430 18:40:40.512630 CH=1, VrefRange= 0, VrefLevel = 6
3431 18:40:40.516413 TX Bit0 (984~1003) 20 993, Bit8 (976~990) 15 983,
3432 18:40:40.519534 TX Bit1 (984~1000) 17 992, Bit9 (975~989) 15 982,
3433 18:40:40.525771 TX Bit2 (981~998) 18 989, Bit10 (977~994) 18 985,
3434 18:40:40.529142 TX Bit3 (978~995) 18 986, Bit11 (978~994) 17 986,
3435 18:40:40.535876 TX Bit4 (983~1001) 19 992, Bit12 (979~992) 14 985,
3436 18:40:40.538803 TX Bit5 (984~1002) 19 993, Bit13 (978~995) 18 986,
3437 18:40:40.542400 TX Bit6 (984~1000) 17 992, Bit14 (978~992) 15 985,
3438 18:40:40.549047 TX Bit7 (984~999) 16 991, Bit15 (971~987) 17 979,
3439 18:40:40.549606
3440 18:40:40.549939 Write Rank1 MR14 =0x8
3441 18:40:40.559156
3442 18:40:40.559674 CH=1, VrefRange= 0, VrefLevel = 8
3443 18:40:40.565542 TX Bit0 (984~1003) 20 993, Bit8 (976~990) 15 983,
3444 18:40:40.568906 TX Bit1 (983~1001) 19 992, Bit9 (974~990) 17 982,
3445 18:40:40.575236 TX Bit2 (981~999) 19 990, Bit10 (977~995) 19 986,
3446 18:40:40.578687 TX Bit3 (978~996) 19 987, Bit11 (978~995) 18 986,
3447 18:40:40.582307 TX Bit4 (983~1001) 19 992, Bit12 (978~992) 15 985,
3448 18:40:40.588535 TX Bit5 (984~1003) 20 993, Bit13 (978~995) 18 986,
3449 18:40:40.591830 TX Bit6 (983~1001) 19 992, Bit14 (977~993) 17 985,
3450 18:40:40.598204 TX Bit7 (984~1000) 17 992, Bit15 (971~988) 18 979,
3451 18:40:40.598625
3452 18:40:40.598945 Write Rank1 MR14 =0xa
3453 18:40:40.608540
3454 18:40:40.612196 CH=1, VrefRange= 0, VrefLevel = 10
3455 18:40:40.615385 TX Bit0 (984~1004) 21 994, Bit8 (976~991) 16 983,
3456 18:40:40.618391 TX Bit1 (983~1001) 19 992, Bit9 (974~990) 17 982,
3457 18:40:40.625097 TX Bit2 (981~999) 19 990, Bit10 (976~996) 21 986,
3458 18:40:40.628678 TX Bit3 (978~997) 20 987, Bit11 (977~996) 20 986,
3459 18:40:40.634931 TX Bit4 (982~1002) 21 992, Bit12 (978~993) 16 985,
3460 18:40:40.638305 TX Bit5 (984~1004) 21 994, Bit13 (978~997) 20 987,
3461 18:40:40.641162 TX Bit6 (983~1002) 20 992, Bit14 (977~993) 17 985,
3462 18:40:40.647959 TX Bit7 (984~1000) 17 992, Bit15 (971~989) 19 980,
3463 18:40:40.648455
3464 18:40:40.648777 Write Rank1 MR14 =0xc
3465 18:40:40.658610
3466 18:40:40.661726 CH=1, VrefRange= 0, VrefLevel = 12
3467 18:40:40.665176 TX Bit0 (984~1005) 22 994, Bit8 (976~991) 16 983,
3468 18:40:40.668697 TX Bit1 (983~1002) 20 992, Bit9 (974~991) 18 982,
3469 18:40:40.675008 TX Bit2 (981~1000) 20 990, Bit10 (976~997) 22 986,
3470 18:40:40.677941 TX Bit3 (978~997) 20 987, Bit11 (977~997) 21 987,
3471 18:40:40.684624 TX Bit4 (982~1003) 22 992, Bit12 (977~993) 17 985,
3472 18:40:40.688247 TX Bit5 (984~1004) 21 994, Bit13 (978~997) 20 987,
3473 18:40:40.691346 TX Bit6 (983~1002) 20 992, Bit14 (977~994) 18 985,
3474 18:40:40.697743 TX Bit7 (983~1001) 19 992, Bit15 (970~990) 21 980,
3475 18:40:40.698243
3476 18:40:40.698565 Write Rank1 MR14 =0xe
3477 18:40:40.708678
3478 18:40:40.711768 CH=1, VrefRange= 0, VrefLevel = 14
3479 18:40:40.715082 TX Bit0 (984~1005) 22 994, Bit8 (975~991) 17 983,
3480 18:40:40.718021 TX Bit1 (982~1003) 22 992, Bit9 (973~991) 19 982,
3481 18:40:40.724669 TX Bit2 (980~1000) 21 990, Bit10 (976~997) 22 986,
3482 18:40:40.728216 TX Bit3 (978~997) 20 987, Bit11 (977~997) 21 987,
3483 18:40:40.734403 TX Bit4 (982~1003) 22 992, Bit12 (977~994) 18 985,
3484 18:40:40.738145 TX Bit5 (983~1005) 23 994, Bit13 (977~997) 21 987,
3485 18:40:40.740976 TX Bit6 (983~1004) 22 993, Bit14 (977~995) 19 986,
3486 18:40:40.747586 TX Bit7 (983~1001) 19 992, Bit15 (970~990) 21 980,
3487 18:40:40.748102
3488 18:40:40.750683 Write Rank1 MR14 =0x10
3489 18:40:40.758548
3490 18:40:40.761889 CH=1, VrefRange= 0, VrefLevel = 16
3491 18:40:40.765567 TX Bit0 (983~1005) 23 994, Bit8 (974~992) 19 983,
3492 18:40:40.768534 TX Bit1 (982~1004) 23 993, Bit9 (973~991) 19 982,
3493 18:40:40.774794 TX Bit2 (980~1001) 22 990, Bit10 (976~998) 23 987,
3494 18:40:40.778234 TX Bit3 (978~998) 21 988, Bit11 (976~998) 23 987,
3495 18:40:40.784949 TX Bit4 (981~1004) 24 992, Bit12 (977~995) 19 986,
3496 18:40:40.788202 TX Bit5 (983~1005) 23 994, Bit13 (977~998) 22 987,
3497 18:40:40.791327 TX Bit6 (982~1004) 23 993, Bit14 (977~996) 20 986,
3498 18:40:40.797529 TX Bit7 (983~1002) 20 992, Bit15 (970~990) 21 980,
3499 18:40:40.797977
3500 18:40:40.798304 Write Rank1 MR14 =0x12
3501 18:40:40.808865
3502 18:40:40.812157 CH=1, VrefRange= 0, VrefLevel = 18
3503 18:40:40.815112 TX Bit0 (983~1006) 24 994, Bit8 (974~992) 19 983,
3504 18:40:40.818311 TX Bit1 (982~1004) 23 993, Bit9 (973~992) 20 982,
3505 18:40:40.825363 TX Bit2 (980~1002) 23 991, Bit10 (975~998) 24 986,
3506 18:40:40.828269 TX Bit3 (977~998) 22 987, Bit11 (976~998) 23 987,
3507 18:40:40.834900 TX Bit4 (981~1005) 25 993, Bit12 (977~996) 20 986,
3508 18:40:40.838280 TX Bit5 (983~1005) 23 994, Bit13 (977~998) 22 987,
3509 18:40:40.841336 TX Bit6 (982~1005) 24 993, Bit14 (976~997) 22 986,
3510 18:40:40.848011 TX Bit7 (982~1003) 22 992, Bit15 (970~991) 22 980,
3511 18:40:40.848529
3512 18:40:40.848855 Write Rank1 MR14 =0x14
3513 18:40:40.858790
3514 18:40:40.862295 CH=1, VrefRange= 0, VrefLevel = 20
3515 18:40:40.865596 TX Bit0 (983~1006) 24 994, Bit8 (973~992) 20 982,
3516 18:40:40.869004 TX Bit1 (981~1005) 25 993, Bit9 (972~992) 21 982,
3517 18:40:40.875048 TX Bit2 (979~1002) 24 990, Bit10 (975~998) 24 986,
3518 18:40:40.878292 TX Bit3 (977~999) 23 988, Bit11 (976~999) 24 987,
3519 18:40:40.885112 TX Bit4 (981~1005) 25 993, Bit12 (977~997) 21 987,
3520 18:40:40.888387 TX Bit5 (983~1005) 23 994, Bit13 (977~998) 22 987,
3521 18:40:40.891649 TX Bit6 (981~1005) 25 993, Bit14 (976~997) 22 986,
3522 18:40:40.898157 TX Bit7 (982~1004) 23 993, Bit15 (970~991) 22 980,
3523 18:40:40.898668
3524 18:40:40.898996 Write Rank1 MR14 =0x16
3525 18:40:40.909557
3526 18:40:40.912577 CH=1, VrefRange= 0, VrefLevel = 22
3527 18:40:40.915796 TX Bit0 (983~1006) 24 994, Bit8 (973~993) 21 983,
3528 18:40:40.918827 TX Bit1 (983~1005) 23 994, Bit9 (972~992) 21 982,
3529 18:40:40.925576 TX Bit2 (979~1003) 25 991, Bit10 (975~999) 25 987,
3530 18:40:40.928465 TX Bit3 (977~999) 23 988, Bit11 (976~999) 24 987,
3531 18:40:40.935166 TX Bit4 (980~1005) 26 992, Bit12 (976~997) 22 986,
3532 18:40:40.938378 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
3533 18:40:40.941637 TX Bit6 (982~1005) 24 993, Bit14 (976~998) 23 987,
3534 18:40:40.948148 TX Bit7 (981~1005) 25 993, Bit15 (970~991) 22 980,
3535 18:40:40.948679
3536 18:40:40.949015 Write Rank1 MR14 =0x18
3537 18:40:40.959325
3538 18:40:40.962697 CH=1, VrefRange= 0, VrefLevel = 24
3539 18:40:40.965765 TX Bit0 (982~1006) 25 994, Bit8 (973~994) 22 983,
3540 18:40:40.969287 TX Bit1 (982~1005) 24 993, Bit9 (972~993) 22 982,
3541 18:40:40.975929 TX Bit2 (978~1004) 27 991, Bit10 (975~999) 25 987,
3542 18:40:40.978849 TX Bit3 (977~999) 23 988, Bit11 (976~999) 24 987,
3543 18:40:40.985033 TX Bit4 (980~1005) 26 992, Bit12 (976~998) 23 987,
3544 18:40:40.988327 TX Bit5 (982~1006) 25 994, Bit13 (976~999) 24 987,
3545 18:40:40.992097 TX Bit6 (981~1005) 25 993, Bit14 (976~998) 23 987,
3546 18:40:40.998369 TX Bit7 (981~1005) 25 993, Bit15 (970~992) 23 981,
3547 18:40:40.998788
3548 18:40:40.999112 Write Rank1 MR14 =0x1a
3549 18:40:41.009228
3550 18:40:41.012848 CH=1, VrefRange= 0, VrefLevel = 26
3551 18:40:41.016067 TX Bit0 (982~1006) 25 994, Bit8 (972~995) 24 983,
3552 18:40:41.019099 TX Bit1 (981~1006) 26 993, Bit9 (971~994) 24 982,
3553 18:40:41.025901 TX Bit2 (978~1004) 27 991, Bit10 (975~999) 25 987,
3554 18:40:41.029248 TX Bit3 (977~1000) 24 988, Bit11 (975~999) 25 987,
3555 18:40:41.035591 TX Bit4 (979~1006) 28 992, Bit12 (976~998) 23 987,
3556 18:40:41.038983 TX Bit5 (982~1006) 25 994, Bit13 (977~999) 23 988,
3557 18:40:41.041914 TX Bit6 (980~1006) 27 993, Bit14 (975~998) 24 986,
3558 18:40:41.048375 TX Bit7 (980~1005) 26 992, Bit15 (969~992) 24 980,
3559 18:40:41.048795
3560 18:40:41.052015 Write Rank1 MR14 =0x1c
3561 18:40:41.060114
3562 18:40:41.062921 CH=1, VrefRange= 0, VrefLevel = 28
3563 18:40:41.066125 TX Bit0 (982~1006) 25 994, Bit8 (972~995) 24 983,
3564 18:40:41.069837 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3565 18:40:41.076185 TX Bit2 (978~1005) 28 991, Bit10 (975~999) 25 987,
3566 18:40:41.079482 TX Bit3 (977~1000) 24 988, Bit11 (975~999) 25 987,
3567 18:40:41.086182 TX Bit4 (979~1006) 28 992, Bit12 (976~999) 24 987,
3568 18:40:41.089046 TX Bit5 (981~1006) 26 993, Bit13 (976~1000) 25 988,
3569 18:40:41.092433 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
3570 18:40:41.099250 TX Bit7 (980~1006) 27 993, Bit15 (969~992) 24 980,
3571 18:40:41.099788
3572 18:40:41.102122 Write Rank1 MR14 =0x1e
3573 18:40:41.110208
3574 18:40:41.113642 CH=1, VrefRange= 0, VrefLevel = 30
3575 18:40:41.116855 TX Bit0 (981~1007) 27 994, Bit8 (972~995) 24 983,
3576 18:40:41.119653 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3577 18:40:41.126341 TX Bit2 (977~1005) 29 991, Bit10 (975~999) 25 987,
3578 18:40:41.129900 TX Bit3 (976~1001) 26 988, Bit11 (975~999) 25 987,
3579 18:40:41.136671 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3580 18:40:41.139714 TX Bit5 (981~1006) 26 993, Bit13 (975~1000) 26 987,
3581 18:40:41.145971 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
3582 18:40:41.148996 TX Bit7 (980~1006) 27 993, Bit15 (969~993) 25 981,
3583 18:40:41.149407
3584 18:40:41.152588 Write Rank1 MR14 =0x20
3585 18:40:41.160807
3586 18:40:41.163992 CH=1, VrefRange= 0, VrefLevel = 32
3587 18:40:41.167282 TX Bit0 (981~1007) 27 994, Bit8 (972~995) 24 983,
3588 18:40:41.170520 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3589 18:40:41.177384 TX Bit2 (977~1005) 29 991, Bit10 (975~999) 25 987,
3590 18:40:41.180637 TX Bit3 (976~1001) 26 988, Bit11 (975~999) 25 987,
3591 18:40:41.187398 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3592 18:40:41.190246 TX Bit5 (981~1006) 26 993, Bit13 (975~1000) 26 987,
3593 18:40:41.193726 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
3594 18:40:41.200023 TX Bit7 (980~1006) 27 993, Bit15 (969~993) 25 981,
3595 18:40:41.200517
3596 18:40:41.203681 Write Rank1 MR14 =0x22
3597 18:40:41.211555
3598 18:40:41.214153 CH=1, VrefRange= 0, VrefLevel = 34
3599 18:40:41.217933 TX Bit0 (981~1007) 27 994, Bit8 (972~995) 24 983,
3600 18:40:41.221082 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3601 18:40:41.227965 TX Bit2 (977~1005) 29 991, Bit10 (975~999) 25 987,
3602 18:40:41.230676 TX Bit3 (976~1001) 26 988, Bit11 (975~999) 25 987,
3603 18:40:41.237454 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3604 18:40:41.240944 TX Bit5 (981~1006) 26 993, Bit13 (975~1000) 26 987,
3605 18:40:41.243714 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
3606 18:40:41.250226 TX Bit7 (980~1006) 27 993, Bit15 (969~993) 25 981,
3607 18:40:41.250660
3608 18:40:41.253410 Write Rank1 MR14 =0x24
3609 18:40:41.261835
3610 18:40:41.265320 CH=1, VrefRange= 0, VrefLevel = 36
3611 18:40:41.268209 TX Bit0 (981~1007) 27 994, Bit8 (972~995) 24 983,
3612 18:40:41.271373 TX Bit1 (980~1006) 27 993, Bit9 (971~995) 25 983,
3613 18:40:41.277650 TX Bit2 (977~1005) 29 991, Bit10 (975~999) 25 987,
3614 18:40:41.281578 TX Bit3 (976~1001) 26 988, Bit11 (975~999) 25 987,
3615 18:40:41.287881 TX Bit4 (980~1006) 27 993, Bit12 (975~999) 25 987,
3616 18:40:41.291106 TX Bit5 (981~1006) 26 993, Bit13 (975~1000) 26 987,
3617 18:40:41.293997 TX Bit6 (980~1006) 27 993, Bit14 (975~999) 25 987,
3618 18:40:41.300521 TX Bit7 (980~1006) 27 993, Bit15 (969~993) 25 981,
3619 18:40:41.301019
3620 18:40:41.301344
3621 18:40:41.304155 TX Vref found, early break! 389< 395
3622 18:40:41.307503 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =744/100 ps
3623 18:40:41.310981 u1DelayCellOfst[0]=7 cells (6 PI)
3624 18:40:41.313886 u1DelayCellOfst[1]=6 cells (5 PI)
3625 18:40:41.317201 u1DelayCellOfst[2]=3 cells (3 PI)
3626 18:40:41.320297 u1DelayCellOfst[3]=0 cells (0 PI)
3627 18:40:41.323612 u1DelayCellOfst[4]=6 cells (5 PI)
3628 18:40:41.326983 u1DelayCellOfst[5]=6 cells (5 PI)
3629 18:40:41.330188 u1DelayCellOfst[6]=6 cells (5 PI)
3630 18:40:41.333286 u1DelayCellOfst[7]=6 cells (5 PI)
3631 18:40:41.337114 Byte0, DQ PI dly=988, DQM PI dly= 991
3632 18:40:41.340326 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
3633 18:40:41.340848
3634 18:40:41.346307 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
3635 18:40:41.346721
3636 18:40:41.347041 u1DelayCellOfst[8]=2 cells (2 PI)
3637 18:40:41.349722 u1DelayCellOfst[9]=2 cells (2 PI)
3638 18:40:41.353154 u1DelayCellOfst[10]=7 cells (6 PI)
3639 18:40:41.356314 u1DelayCellOfst[11]=7 cells (6 PI)
3640 18:40:41.359414 u1DelayCellOfst[12]=7 cells (6 PI)
3641 18:40:41.362693 u1DelayCellOfst[13]=7 cells (6 PI)
3642 18:40:41.366072 u1DelayCellOfst[14]=7 cells (6 PI)
3643 18:40:41.369502 u1DelayCellOfst[15]=0 cells (0 PI)
3644 18:40:41.372823 Byte1, DQ PI dly=981, DQM PI dly= 984
3645 18:40:41.375939 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
3646 18:40:41.379219
3647 18:40:41.382236 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
3648 18:40:41.382655
3649 18:40:41.382980 Write Rank1 MR14 =0x1e
3650 18:40:41.385812
3651 18:40:41.386237 Final TX Range 0 Vref 30
3652 18:40:41.386566
3653 18:40:41.392369 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3654 18:40:41.392788
3655 18:40:41.398561 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3656 18:40:41.405361 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3657 18:40:41.415309 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3658 18:40:41.415835 Write Rank1 MR3 =0xb0
3659 18:40:41.418428 DramC Write-DBI on
3660 18:40:41.418830 ==
3661 18:40:41.421975 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3662 18:40:41.424874 fsp= 1, odt_onoff= 1, Byte mode= 0
3663 18:40:41.425289 ==
3664 18:40:41.431621 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3665 18:40:41.432034
3666 18:40:41.432356 Begin, DQ Scan Range 704~768
3667 18:40:41.434969
3668 18:40:41.435381
3669 18:40:41.435704 TX Vref Scan disable
3670 18:40:41.437936 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3671 18:40:41.441798 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3672 18:40:41.444819 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3673 18:40:41.448039 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3674 18:40:41.451294 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3675 18:40:41.457737 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3676 18:40:41.460851 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3677 18:40:41.464395 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3678 18:40:41.467533 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3679 18:40:41.470842 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3680 18:40:41.474253 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3681 18:40:41.477174 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3682 18:40:41.480597 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3683 18:40:41.483848 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3684 18:40:41.487488 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3685 18:40:41.490525 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3686 18:40:41.493787 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3687 18:40:41.496783 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3688 18:40:41.500412 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3689 18:40:41.506599 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3690 18:40:41.513491 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3691 18:40:41.516435 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3692 18:40:41.520337 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3693 18:40:41.523287 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3694 18:40:41.526715 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3695 18:40:41.529740 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3696 18:40:41.533481 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3697 18:40:41.536688 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3698 18:40:41.539880 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3699 18:40:41.543233 Byte0, DQ PI dly=737, DQM PI dly= 737
3700 18:40:41.549523 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 33)
3701 18:40:41.550169
3702 18:40:41.552492 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 33)
3703 18:40:41.552906
3704 18:40:41.555671 Byte1, DQ PI dly=728, DQM PI dly= 728
3705 18:40:41.559626 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
3706 18:40:41.560187
3707 18:40:41.566006 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
3708 18:40:41.566527
3709 18:40:41.572538 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3710 18:40:41.578882 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3711 18:40:41.585274 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3712 18:40:41.588972 wait MRW command Rank1 MR3 =0x30 fired (1)
3713 18:40:41.592150 Write Rank1 MR3 =0x30
3714 18:40:41.592663 DramC Write-DBI off
3715 18:40:41.592985
3716 18:40:41.595408 [DATLAT]
3717 18:40:41.598513 Freq=1600, CH1 RK1, use_rxtx_scan=0
3718 18:40:41.599038
3719 18:40:41.599366 DATLAT Default: 0x10
3720 18:40:41.601628 7, 0xFFFF, sum=0
3721 18:40:41.602060 8, 0xFFFF, sum=0
3722 18:40:41.604718 9, 0xFFFF, sum=0
3723 18:40:41.605134 10, 0xFFFF, sum=0
3724 18:40:41.608405 11, 0xFFFF, sum=0
3725 18:40:41.608926 12, 0xFFFF, sum=0
3726 18:40:41.611326 13, 0xFFFF, sum=0
3727 18:40:41.611838 14, 0x0, sum=1
3728 18:40:41.614813 15, 0x0, sum=2
3729 18:40:41.615335 16, 0x0, sum=3
3730 18:40:41.615682 17, 0x0, sum=4
3731 18:40:41.621073 pattern=2 first_step=14 total pass=5 best_step=16
3732 18:40:41.621521 ==
3733 18:40:41.624479 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3734 18:40:41.628018 fsp= 1, odt_onoff= 1, Byte mode= 0
3735 18:40:41.628545 ==
3736 18:40:41.634365 Start DQ dly to find pass range UseTestEngine =1
3737 18:40:41.637879 x-axis: bit #, y-axis: DQ dly (-127~63)
3738 18:40:41.638395 RX Vref Scan = 0
3739 18:40:41.640731 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3740 18:40:41.644425 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3741 18:40:41.647675 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3742 18:40:41.650586 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3743 18:40:41.653987 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3744 18:40:41.657062 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3745 18:40:41.657512 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3746 18:40:41.660591 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3747 18:40:41.663791 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3748 18:40:41.667210 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3749 18:40:41.670492 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3750 18:40:41.673734 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3751 18:40:41.676733 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3752 18:40:41.680418 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3753 18:40:41.683403 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3754 18:40:41.686866 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3755 18:40:41.687394 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3756 18:40:41.689899 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3757 18:40:41.693575 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3758 18:40:41.696837 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3759 18:40:41.700270 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3760 18:40:41.703025 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3761 18:40:41.706418 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3762 18:40:41.709891 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3763 18:40:41.710418 -2, [0] xxxxxxxx xoxxxxxo [MSB]
3764 18:40:41.712793 -1, [0] xxxoxxxx ooxxxxxo [MSB]
3765 18:40:41.716165 0, [0] xxxoxxxx ooxxxxxo [MSB]
3766 18:40:41.719481 1, [0] xxxoxxxx ooxxxxxo [MSB]
3767 18:40:41.723056 2, [0] xxxoxxxx ooxxxxxo [MSB]
3768 18:40:41.725996 3, [0] xxooxxxo oooxoxxo [MSB]
3769 18:40:41.726518 4, [0] ooooxxxo oooooooo [MSB]
3770 18:40:41.729588 5, [0] oooooxxo oooooooo [MSB]
3771 18:40:41.732336 6, [0] oooooxoo oooooooo [MSB]
3772 18:40:41.736820 32, [0] oooooooo ooooooox [MSB]
3773 18:40:41.740453 33, [0] oooooooo ooooooox [MSB]
3774 18:40:41.743200 34, [0] oooxoooo oxooooox [MSB]
3775 18:40:41.746712 35, [0] ooxxoooo oxooooox [MSB]
3776 18:40:41.749680 36, [0] ooxxoooo xxooooox [MSB]
3777 18:40:41.753580 37, [0] ooxxoooo xxooooox [MSB]
3778 18:40:41.756631 38, [0] ooxxoooo xxooxoox [MSB]
3779 18:40:41.757160 39, [0] ooxxooox xxxxxoox [MSB]
3780 18:40:41.760060 40, [0] oxxxxoox xxxxxxox [MSB]
3781 18:40:41.762922 41, [0] xxxxxxxx xxxxxxxx [MSB]
3782 18:40:41.766091 iDelay=41, Bit 0, Center 22 (4 ~ 40) 37
3783 18:40:41.769571 iDelay=41, Bit 1, Center 21 (4 ~ 39) 36
3784 18:40:41.772892 iDelay=41, Bit 2, Center 18 (3 ~ 34) 32
3785 18:40:41.779739 iDelay=41, Bit 3, Center 16 (-1 ~ 33) 35
3786 18:40:41.782984 iDelay=41, Bit 4, Center 22 (5 ~ 39) 35
3787 18:40:41.786374 iDelay=41, Bit 5, Center 23 (7 ~ 40) 34
3788 18:40:41.789514 iDelay=41, Bit 6, Center 23 (6 ~ 40) 35
3789 18:40:41.792597 iDelay=41, Bit 7, Center 20 (3 ~ 38) 36
3790 18:40:41.795648 iDelay=41, Bit 8, Center 17 (-1 ~ 35) 37
3791 18:40:41.798900 iDelay=41, Bit 9, Center 15 (-2 ~ 33) 36
3792 18:40:41.802058 iDelay=41, Bit 10, Center 20 (3 ~ 38) 36
3793 18:40:41.805485 iDelay=41, Bit 11, Center 21 (4 ~ 38) 35
3794 18:40:41.808807 iDelay=41, Bit 12, Center 20 (3 ~ 37) 35
3795 18:40:41.812427 iDelay=41, Bit 13, Center 21 (4 ~ 39) 36
3796 18:40:41.818773 iDelay=41, Bit 14, Center 22 (4 ~ 40) 37
3797 18:40:41.821930 iDelay=41, Bit 15, Center 13 (-4 ~ 31) 36
3798 18:40:41.822342 ==
3799 18:40:41.825489 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3800 18:40:41.828794 fsp= 1, odt_onoff= 1, Byte mode= 0
3801 18:40:41.829301 ==
3802 18:40:41.831854 DQS Delay:
3803 18:40:41.832402 DQS0 = 0, DQS1 = 0
3804 18:40:41.835120 DQM Delay:
3805 18:40:41.835628 DQM0 = 20, DQM1 = 18
3806 18:40:41.835953 DQ Delay:
3807 18:40:41.838308 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3808 18:40:41.841637 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
3809 18:40:41.845009 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =21
3810 18:40:41.848206 DQ12 =20, DQ13 =21, DQ14 =22, DQ15 =13
3811 18:40:41.848767
3812 18:40:41.849114
3813 18:40:41.849415
3814 18:40:41.851197 [DramC_TX_OE_Calibration] TA2
3815 18:40:41.854719 Original DQ_B0 (3 6) =30, OEN = 27
3816 18:40:41.858157 Original DQ_B1 (3 6) =30, OEN = 27
3817 18:40:41.861025 23, 0x0, End_B0=23 End_B1=23
3818 18:40:41.864685 24, 0x0, End_B0=24 End_B1=24
3819 18:40:41.867585 25, 0x0, End_B0=25 End_B1=25
3820 18:40:41.868002 26, 0x0, End_B0=26 End_B1=26
3821 18:40:41.871125 27, 0x0, End_B0=27 End_B1=27
3822 18:40:41.874354 28, 0x0, End_B0=28 End_B1=28
3823 18:40:41.877748 29, 0x0, End_B0=29 End_B1=29
3824 18:40:41.880896 30, 0x0, End_B0=30 End_B1=30
3825 18:40:41.881405 31, 0xFFFF, End_B0=30 End_B1=30
3826 18:40:41.887297 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3827 18:40:41.894059 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3828 18:40:41.894570
3829 18:40:41.894897
3830 18:40:41.897178 Write Rank1 MR23 =0x3f
3831 18:40:41.897763 [DQSOSC]
3832 18:40:41.903572 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0x202, tDQSOscB0 = 452 ps tDQSOscB1 = 452 ps
3833 18:40:41.910229 CH1_RK1: MR19=0x202, MR18=0xB8B8, DQSOSC=452, MR23=63, INC=12, DEC=18
3834 18:40:41.913287 Write Rank1 MR23 =0x3f
3835 18:40:41.913747 [DQSOSC]
3836 18:40:41.920345 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
3837 18:40:41.923612 CH1 RK1: MR19=202, MR18=B6B6
3838 18:40:41.926615 [RxdqsGatingPostProcess] freq 1600
3839 18:40:41.933514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3840 18:40:41.934139 Rank: 0
3841 18:40:41.936718 best DQS0 dly(2T, 0.5T) = (2, 6)
3842 18:40:41.939972 best DQS1 dly(2T, 0.5T) = (2, 6)
3843 18:40:41.942918 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3844 18:40:41.946110 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3845 18:40:41.946696 Rank: 1
3846 18:40:41.949215 best DQS0 dly(2T, 0.5T) = (2, 6)
3847 18:40:41.952651 best DQS1 dly(2T, 0.5T) = (2, 6)
3848 18:40:41.956014 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3849 18:40:41.959036 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3850 18:40:41.962677 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3851 18:40:41.965533 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3852 18:40:41.972315 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3853 18:40:41.972819
3854 18:40:41.973142
3855 18:40:41.975413 [Calibration Summary] Freqency 1600
3856 18:40:41.975824 CH 0, Rank 0
3857 18:40:41.979028 All Pass.
3858 18:40:41.979544
3859 18:40:41.979869 CH 0, Rank 1
3860 18:40:41.980175 All Pass.
3861 18:40:41.980463
3862 18:40:41.982119 CH 1, Rank 0
3863 18:40:41.982528 All Pass.
3864 18:40:41.982850
3865 18:40:41.983149 CH 1, Rank 1
3866 18:40:41.985289 All Pass.
3867 18:40:41.985716
3868 18:40:41.992050 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3869 18:40:41.998704 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3870 18:40:42.005582 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3871 18:40:42.008609 Write Rank0 MR3 =0xb0
3872 18:40:42.015172 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3873 18:40:42.021543 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3874 18:40:42.028165 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3875 18:40:42.031614 Write Rank1 MR3 =0xb0
3876 18:40:42.034687 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3877 18:40:42.044249 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3878 18:40:42.050648 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3879 18:40:42.051112 Write Rank0 MR3 =0xb0
3880 18:40:42.057496 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3881 18:40:42.067324 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3882 18:40:42.073844 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3883 18:40:42.074395 Write Rank1 MR3 =0xb0
3884 18:40:42.076871 DramC Write-DBI on
3885 18:40:42.080184 [GetDramInforAfterCalByMRR] Vendor 6.
3886 18:40:42.083718 [GetDramInforAfterCalByMRR] Revision 505.
3887 18:40:42.084277 MR8 1111
3888 18:40:42.090223 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3889 18:40:42.090732 MR8 1111
3890 18:40:42.093606 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3891 18:40:42.096911 MR8 1111
3892 18:40:42.100003 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3893 18:40:42.100418 MR8 1111
3894 18:40:42.106286 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3895 18:40:42.116586 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3896 18:40:42.117117 Write Rank0 MR13 =0xd0
3897 18:40:42.119885 Write Rank1 MR13 =0xd0
3898 18:40:42.123260 Write Rank0 MR13 =0xd0
3899 18:40:42.123771 Write Rank1 MR13 =0xd0
3900 18:40:42.126122 Save calibration result to emmc
3901 18:40:42.126534
3902 18:40:42.126855
3903 18:40:42.129327 [DramcModeReg_Check] Freq_1600, FSP_1
3904 18:40:42.132746 FSP_1, CH_0, RK0
3905 18:40:42.133163 Write Rank0 MR13 =0xd8
3906 18:40:42.135982 MR12 = 0x5e (global = 0x5e) match
3907 18:40:42.139061 MR14 = 0x1c (global = 0x1c) match
3908 18:40:42.142618 FSP_1, CH_0, RK1
3909 18:40:42.143129 Write Rank1 MR13 =0xd8
3910 18:40:42.145883 MR12 = 0x5e (global = 0x5e) match
3911 18:40:42.148802 MR14 = 0x1e (global = 0x1e) match
3912 18:40:42.152475 FSP_1, CH_1, RK0
3913 18:40:42.152888 Write Rank0 MR13 =0xd8
3914 18:40:42.155532 MR12 = 0x60 (global = 0x60) match
3915 18:40:42.158842 MR14 = 0x1e (global = 0x1e) match
3916 18:40:42.162105 FSP_1, CH_1, RK1
3917 18:40:42.162518 Write Rank1 MR13 =0xd8
3918 18:40:42.165709 MR12 = 0x60 (global = 0x60) match
3919 18:40:42.168602 MR14 = 0x1e (global = 0x1e) match
3920 18:40:42.169016
3921 18:40:42.175435 [MEM_TEST] 02: After DFS, before run time config
3922 18:40:42.185082 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3923 18:40:42.185613
3924 18:40:42.185941 [TA2_TEST]
3925 18:40:42.186244 === TA2 HW
3926 18:40:42.188660 TA2 PAT: XTALK
3927 18:40:42.192027 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3928 18:40:42.198055 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3929 18:40:42.201519 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3930 18:40:42.208348 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3931 18:40:42.208868
3932 18:40:42.209190
3933 18:40:42.209533 Settings after calibration
3934 18:40:42.211243
3935 18:40:42.211650 [DramcRunTimeConfig]
3936 18:40:42.214659 TransferPLLToSPMControl - MODE SW PHYPLL
3937 18:40:42.217644 TX_TRACKING: ON
3938 18:40:42.218062 RX_TRACKING: ON
3939 18:40:42.218381 HW_GATING: ON
3940 18:40:42.221394 HW_GATING DBG: OFF
3941 18:40:42.221955 ddr_geometry:1
3942 18:40:42.224705 ddr_geometry:1
3943 18:40:42.225221 ddr_geometry:1
3944 18:40:42.227793 ddr_geometry:1
3945 18:40:42.228306 ddr_geometry:1
3946 18:40:42.231080 ddr_geometry:1
3947 18:40:42.231594 ddr_geometry:1
3948 18:40:42.231918 ddr_geometry:1
3949 18:40:42.234097 High Freq DUMMY_READ_FOR_TRACKING: ON
3950 18:40:42.237182 ZQCS_ENABLE_LP4: OFF
3951 18:40:42.240689 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3952 18:40:42.243966 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3953 18:40:42.247091 SPM_CONTROL_AFTERK: ON
3954 18:40:42.247528 IMPEDANCE_TRACKING: ON
3955 18:40:42.250216 TEMP_SENSOR: ON
3956 18:40:42.250679 PER_BANK_REFRESH: ON
3957 18:40:42.253597 HW_SAVE_FOR_SR: ON
3958 18:40:42.256897 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 18:40:42.260292 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3960 18:40:42.263455 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3961 18:40:42.263968 Read ODT Tracking: ON
3962 18:40:42.266805 =========================
3963 18:40:42.267215
3964 18:40:42.269954 [TA2_TEST]
3965 18:40:42.270363 === TA2 HW
3966 18:40:42.273313 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3967 18:40:42.280041 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3968 18:40:42.283174 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3969 18:40:42.289513 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3970 18:40:42.290025
3971 18:40:42.292946 [MEM_TEST] 03: After run time config
3972 18:40:42.302920 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3973 18:40:42.306062 [complex_mem_test] start addr:0x40024000, len:131072
3974 18:40:42.510685 1st complex R/W mem test pass
3975 18:40:42.517296 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3976 18:40:42.520460 sync preloader write leveling
3977 18:40:42.523470 sync preloader cbt_mr12
3978 18:40:42.527472 sync preloader cbt_clk_dly
3979 18:40:42.527982 sync preloader cbt_cmd_dly
3980 18:40:42.530347 sync preloader cbt_cs
3981 18:40:42.533780 sync preloader cbt_ca_perbit_delay
3982 18:40:42.536765 sync preloader clk_delay
3983 18:40:42.537175 sync preloader dqs_delay
3984 18:40:42.540062 sync preloader u1Gating2T_Save
3985 18:40:42.543155 sync preloader u1Gating05T_Save
3986 18:40:42.546386 sync preloader u1Gatingfine_tune_Save
3987 18:40:42.549755 sync preloader u1Gatingucpass_count_Save
3988 18:40:42.553197 sync preloader u1TxWindowPerbitVref_Save
3989 18:40:42.556494 sync preloader u1TxCenter_min_Save
3990 18:40:42.559664 sync preloader u1TxCenter_max_Save
3991 18:40:42.562695 sync preloader u1Txwin_center_Save
3992 18:40:42.566077 sync preloader u1Txfirst_pass_Save
3993 18:40:42.569481 sync preloader u1Txlast_pass_Save
3994 18:40:42.572943 sync preloader u1RxDatlat_Save
3995 18:40:42.576129 sync preloader u1RxWinPerbitVref_Save
3996 18:40:42.579457 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3997 18:40:42.582411 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3998 18:40:42.585685 sync preloader delay_cell_unit
3999 18:40:42.592248 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4000 18:40:42.595762 sync preloader write leveling
4001 18:40:42.598775 sync preloader cbt_mr12
4002 18:40:42.599396 sync preloader cbt_clk_dly
4003 18:40:42.602226 sync preloader cbt_cmd_dly
4004 18:40:42.605660 sync preloader cbt_cs
4005 18:40:42.609067 sync preloader cbt_ca_perbit_delay
4006 18:40:42.609851 sync preloader clk_delay
4007 18:40:42.612158 sync preloader dqs_delay
4008 18:40:42.615357 sync preloader u1Gating2T_Save
4009 18:40:42.618517 sync preloader u1Gating05T_Save
4010 18:40:42.621758 sync preloader u1Gatingfine_tune_Save
4011 18:40:42.625096 sync preloader u1Gatingucpass_count_Save
4012 18:40:42.628075 sync preloader u1TxWindowPerbitVref_Save
4013 18:40:42.631561 sync preloader u1TxCenter_min_Save
4014 18:40:42.634804 sync preloader u1TxCenter_max_Save
4015 18:40:42.638221 sync preloader u1Txwin_center_Save
4016 18:40:42.641855 sync preloader u1Txfirst_pass_Save
4017 18:40:42.644751 sync preloader u1Txlast_pass_Save
4018 18:40:42.647962 sync preloader u1RxDatlat_Save
4019 18:40:42.651129 sync preloader u1RxWinPerbitVref_Save
4020 18:40:42.654639 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4021 18:40:42.657696 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4022 18:40:42.661300 sync preloader delay_cell_unit
4023 18:40:42.667456 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4024 18:40:42.671173 sync preloader write leveling
4025 18:40:42.674299 sync preloader cbt_mr12
4026 18:40:42.674675 sync preloader cbt_clk_dly
4027 18:40:42.677315 sync preloader cbt_cmd_dly
4028 18:40:42.681019 sync preloader cbt_cs
4029 18:40:42.684086 sync preloader cbt_ca_perbit_delay
4030 18:40:42.684592 sync preloader clk_delay
4031 18:40:42.687516 sync preloader dqs_delay
4032 18:40:42.690384 sync preloader u1Gating2T_Save
4033 18:40:42.693846 sync preloader u1Gating05T_Save
4034 18:40:42.696937 sync preloader u1Gatingfine_tune_Save
4035 18:40:42.700495 sync preloader u1Gatingucpass_count_Save
4036 18:40:42.703644 sync preloader u1TxWindowPerbitVref_Save
4037 18:40:42.707013 sync preloader u1TxCenter_min_Save
4038 18:40:42.710128 sync preloader u1TxCenter_max_Save
4039 18:40:42.713508 sync preloader u1Txwin_center_Save
4040 18:40:42.716791 sync preloader u1Txfirst_pass_Save
4041 18:40:42.720051 sync preloader u1Txlast_pass_Save
4042 18:40:42.720424 sync preloader u1RxDatlat_Save
4043 18:40:42.723304 sync preloader u1RxWinPerbitVref_Save
4044 18:40:42.729888 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4045 18:40:42.733355 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4046 18:40:42.736598 sync preloader delay_cell_unit
4047 18:40:42.739789 just_for_test_dump_coreboot_params dump all params
4048 18:40:42.742890 dump source = 0x0
4049 18:40:42.743402 dump params frequency:1600
4050 18:40:42.746150 dump params rank number:2
4051 18:40:42.746651
4052 18:40:42.749339 dump params write leveling
4053 18:40:42.752670 write leveling[0][0][0] = 0x1f
4054 18:40:42.756048 write leveling[0][0][1] = 0x19
4055 18:40:42.756455 write leveling[0][1][0] = 0x1a
4056 18:40:42.759346 write leveling[0][1][1] = 0x18
4057 18:40:42.762450 write leveling[1][0][0] = 0x21
4058 18:40:42.765710 write leveling[1][0][1] = 0x1a
4059 18:40:42.769301 write leveling[1][1][0] = 0x22
4060 18:40:42.772451 write leveling[1][1][1] = 0x1c
4061 18:40:42.772963 dump params cbt_cs
4062 18:40:42.775671 cbt_cs[0][0] = 0x6
4063 18:40:42.776186 cbt_cs[0][1] = 0x6
4064 18:40:42.778922 cbt_cs[1][0] = 0xb
4065 18:40:42.779331 cbt_cs[1][1] = 0xb
4066 18:40:42.782099 dump params cbt_mr12
4067 18:40:42.785643 cbt_mr12[0][0] = 0x1e
4068 18:40:42.786147 cbt_mr12[0][1] = 0x1e
4069 18:40:42.788818 cbt_mr12[1][0] = 0x20
4070 18:40:42.789230 cbt_mr12[1][1] = 0x20
4071 18:40:42.792123 dump params tx window
4072 18:40:42.795081 tx_center_min[0][0][0] = 984
4073 18:40:42.798511 tx_center_max[0][0][0] = 990
4074 18:40:42.799029 tx_center_min[0][0][1] = 978
4075 18:40:42.801603 tx_center_max[0][0][1] = 985
4076 18:40:42.805337 tx_center_min[0][1][0] = 982
4077 18:40:42.808156 tx_center_max[0][1][0] = 989
4078 18:40:42.811718 tx_center_min[0][1][1] = 979
4079 18:40:42.812381 tx_center_max[0][1][1] = 987
4080 18:40:42.815095 tx_center_min[1][0][0] = 987
4081 18:40:42.818405 tx_center_max[1][0][0] = 993
4082 18:40:42.821709 tx_center_min[1][0][1] = 979
4083 18:40:42.824989 tx_center_max[1][0][1] = 986
4084 18:40:42.825531 tx_center_min[1][1][0] = 988
4085 18:40:42.828252 tx_center_max[1][1][0] = 994
4086 18:40:42.831356 tx_center_min[1][1][1] = 981
4087 18:40:42.834880 tx_center_max[1][1][1] = 987
4088 18:40:42.835385 dump params tx window
4089 18:40:42.838055 tx_win_center[0][0][0] = 990
4090 18:40:42.841496 tx_first_pass[0][0][0] = 978
4091 18:40:42.844669 tx_last_pass[0][0][0] = 1002
4092 18:40:42.848121 tx_win_center[0][0][1] = 989
4093 18:40:42.848629 tx_first_pass[0][0][1] = 977
4094 18:40:42.850852 tx_last_pass[0][0][1] = 1001
4095 18:40:42.854116 tx_win_center[0][0][2] = 989
4096 18:40:42.857310 tx_first_pass[0][0][2] = 977
4097 18:40:42.861071 tx_last_pass[0][0][2] = 1002
4098 18:40:42.861630 tx_win_center[0][0][3] = 984
4099 18:40:42.864128 tx_first_pass[0][0][3] = 972
4100 18:40:42.867438 tx_last_pass[0][0][3] = 996
4101 18:40:42.870652 tx_win_center[0][0][4] = 988
4102 18:40:42.874426 tx_first_pass[0][0][4] = 977
4103 18:40:42.874932 tx_last_pass[0][0][4] = 1000
4104 18:40:42.877030 tx_win_center[0][0][5] = 987
4105 18:40:42.880603 tx_first_pass[0][0][5] = 975
4106 18:40:42.883929 tx_last_pass[0][0][5] = 999
4107 18:40:42.887169 tx_win_center[0][0][6] = 987
4108 18:40:42.887673 tx_first_pass[0][0][6] = 976
4109 18:40:42.890285 tx_last_pass[0][0][6] = 999
4110 18:40:42.893667 tx_win_center[0][0][7] = 989
4111 18:40:42.896898 tx_first_pass[0][0][7] = 977
4112 18:40:42.897309 tx_last_pass[0][0][7] = 1001
4113 18:40:42.900388 tx_win_center[0][0][8] = 978
4114 18:40:42.903520 tx_first_pass[0][0][8] = 967
4115 18:40:42.906601 tx_last_pass[0][0][8] = 989
4116 18:40:42.909970 tx_win_center[0][0][9] = 979
4117 18:40:42.910481 tx_first_pass[0][0][9] = 968
4118 18:40:42.913344 tx_last_pass[0][0][9] = 991
4119 18:40:42.916552 tx_win_center[0][0][10] = 985
4120 18:40:42.919756 tx_first_pass[0][0][10] = 973
4121 18:40:42.923025 tx_last_pass[0][0][10] = 997
4122 18:40:42.923435 tx_win_center[0][0][11] = 978
4123 18:40:42.926081 tx_first_pass[0][0][11] = 967
4124 18:40:42.930126 tx_last_pass[0][0][11] = 990
4125 18:40:42.933041 tx_win_center[0][0][12] = 980
4126 18:40:42.936170 tx_first_pass[0][0][12] = 968
4127 18:40:42.940051 tx_last_pass[0][0][12] = 992
4128 18:40:42.940558 tx_win_center[0][0][13] = 980
4129 18:40:42.942862 tx_first_pass[0][0][13] = 969
4130 18:40:42.945968 tx_last_pass[0][0][13] = 991
4131 18:40:42.949043 tx_win_center[0][0][14] = 982
4132 18:40:42.952347 tx_first_pass[0][0][14] = 969
4133 18:40:42.952971 tx_last_pass[0][0][14] = 995
4134 18:40:42.955593 tx_win_center[0][0][15] = 984
4135 18:40:42.958847 tx_first_pass[0][0][15] = 972
4136 18:40:42.962082 tx_last_pass[0][0][15] = 997
4137 18:40:42.965531 tx_win_center[0][1][0] = 989
4138 18:40:42.968571 tx_first_pass[0][1][0] = 977
4139 18:40:42.969219 tx_last_pass[0][1][0] = 1001
4140 18:40:42.972246 tx_win_center[0][1][1] = 987
4141 18:40:42.975509 tx_first_pass[0][1][1] = 976
4142 18:40:42.978690 tx_last_pass[0][1][1] = 999
4143 18:40:42.979094 tx_win_center[0][1][2] = 988
4144 18:40:42.982174 tx_first_pass[0][1][2] = 977
4145 18:40:42.985632 tx_last_pass[0][1][2] = 1000
4146 18:40:42.988575 tx_win_center[0][1][3] = 982
4147 18:40:42.991875 tx_first_pass[0][1][3] = 970
4148 18:40:42.992383 tx_last_pass[0][1][3] = 994
4149 18:40:42.995219 tx_win_center[0][1][4] = 988
4150 18:40:42.998149 tx_first_pass[0][1][4] = 976
4151 18:40:43.001743 tx_last_pass[0][1][4] = 1000
4152 18:40:43.004607 tx_win_center[0][1][5] = 984
4153 18:40:43.005016 tx_first_pass[0][1][5] = 972
4154 18:40:43.008245 tx_last_pass[0][1][5] = 996
4155 18:40:43.011814 tx_win_center[0][1][6] = 986
4156 18:40:43.014863 tx_first_pass[0][1][6] = 975
4157 18:40:43.017994 tx_last_pass[0][1][6] = 998
4158 18:40:43.018535 tx_win_center[0][1][7] = 988
4159 18:40:43.021219 tx_first_pass[0][1][7] = 976
4160 18:40:43.024623 tx_last_pass[0][1][7] = 1000
4161 18:40:43.027476 tx_win_center[0][1][8] = 979
4162 18:40:43.031209 tx_first_pass[0][1][8] = 968
4163 18:40:43.031709 tx_last_pass[0][1][8] = 991
4164 18:40:43.034311 tx_win_center[0][1][9] = 981
4165 18:40:43.037702 tx_first_pass[0][1][9] = 969
4166 18:40:43.040986 tx_last_pass[0][1][9] = 993
4167 18:40:43.044177 tx_win_center[0][1][10] = 987
4168 18:40:43.044675 tx_first_pass[0][1][10] = 975
4169 18:40:43.047510 tx_last_pass[0][1][10] = 999
4170 18:40:43.050601 tx_win_center[0][1][11] = 979
4171 18:40:43.053904 tx_first_pass[0][1][11] = 968
4172 18:40:43.057040 tx_last_pass[0][1][11] = 991
4173 18:40:43.057486 tx_win_center[0][1][12] = 981
4174 18:40:43.060498 tx_first_pass[0][1][12] = 970
4175 18:40:43.063702 tx_last_pass[0][1][12] = 993
4176 18:40:43.067495 tx_win_center[0][1][13] = 981
4177 18:40:43.070136 tx_first_pass[0][1][13] = 970
4178 18:40:43.073838 tx_last_pass[0][1][13] = 993
4179 18:40:43.074377 tx_win_center[0][1][14] = 983
4180 18:40:43.076742 tx_first_pass[0][1][14] = 971
4181 18:40:43.080070 tx_last_pass[0][1][14] = 995
4182 18:40:43.083343 tx_win_center[0][1][15] = 986
4183 18:40:43.086888 tx_first_pass[0][1][15] = 974
4184 18:40:43.087505 tx_last_pass[0][1][15] = 998
4185 18:40:43.089801 tx_win_center[1][0][0] = 993
4186 18:40:43.093239 tx_first_pass[1][0][0] = 980
4187 18:40:43.096662 tx_last_pass[1][0][0] = 1006
4188 18:40:43.099766 tx_win_center[1][0][1] = 991
4189 18:40:43.100175 tx_first_pass[1][0][1] = 978
4190 18:40:43.102933 tx_last_pass[1][0][1] = 1005
4191 18:40:43.106331 tx_win_center[1][0][2] = 989
4192 18:40:43.109497 tx_first_pass[1][0][2] = 977
4193 18:40:43.112855 tx_last_pass[1][0][2] = 1002
4194 18:40:43.113410 tx_win_center[1][0][3] = 987
4195 18:40:43.116080 tx_first_pass[1][0][3] = 975
4196 18:40:43.119128 tx_last_pass[1][0][3] = 999
4197 18:40:43.123101 tx_win_center[1][0][4] = 992
4198 18:40:43.125909 tx_first_pass[1][0][4] = 979
4199 18:40:43.126433 tx_last_pass[1][0][4] = 1005
4200 18:40:43.129081 tx_win_center[1][0][5] = 993
4201 18:40:43.132746 tx_first_pass[1][0][5] = 980
4202 18:40:43.135839 tx_last_pass[1][0][5] = 1006
4203 18:40:43.138839 tx_win_center[1][0][6] = 991
4204 18:40:43.139263 tx_first_pass[1][0][6] = 978
4205 18:40:43.142287 tx_last_pass[1][0][6] = 1005
4206 18:40:43.145298 tx_win_center[1][0][7] = 991
4207 18:40:43.148651 tx_first_pass[1][0][7] = 978
4208 18:40:43.151914 tx_last_pass[1][0][7] = 1004
4209 18:40:43.152387 tx_win_center[1][0][8] = 981
4210 18:40:43.155356 tx_first_pass[1][0][8] = 969
4211 18:40:43.158551 tx_last_pass[1][0][8] = 993
4212 18:40:43.162050 tx_win_center[1][0][9] = 980
4213 18:40:43.165297 tx_first_pass[1][0][9] = 969
4214 18:40:43.165741 tx_last_pass[1][0][9] = 992
4215 18:40:43.168687 tx_win_center[1][0][10] = 984
4216 18:40:43.171635 tx_first_pass[1][0][10] = 972
4217 18:40:43.174789 tx_last_pass[1][0][10] = 997
4218 18:40:43.178048 tx_win_center[1][0][11] = 985
4219 18:40:43.178453 tx_first_pass[1][0][11] = 973
4220 18:40:43.181538 tx_last_pass[1][0][11] = 998
4221 18:40:43.185014 tx_win_center[1][0][12] = 985
4222 18:40:43.187886 tx_first_pass[1][0][12] = 973
4223 18:40:43.191633 tx_last_pass[1][0][12] = 997
4224 18:40:43.192136 tx_win_center[1][0][13] = 986
4225 18:40:43.194574 tx_first_pass[1][0][13] = 974
4226 18:40:43.198129 tx_last_pass[1][0][13] = 998
4227 18:40:43.201177 tx_win_center[1][0][14] = 985
4228 18:40:43.204350 tx_first_pass[1][0][14] = 973
4229 18:40:43.207981 tx_last_pass[1][0][14] = 997
4230 18:40:43.208503 tx_win_center[1][0][15] = 979
4231 18:40:43.210896 tx_first_pass[1][0][15] = 967
4232 18:40:43.214243 tx_last_pass[1][0][15] = 991
4233 18:40:43.217394 tx_win_center[1][1][0] = 994
4234 18:40:43.220844 tx_first_pass[1][1][0] = 981
4235 18:40:43.221343 tx_last_pass[1][1][0] = 1007
4236 18:40:43.224149 tx_win_center[1][1][1] = 993
4237 18:40:43.227259 tx_first_pass[1][1][1] = 980
4238 18:40:43.230923 tx_last_pass[1][1][1] = 1006
4239 18:40:43.233921 tx_win_center[1][1][2] = 991
4240 18:40:43.234423 tx_first_pass[1][1][2] = 977
4241 18:40:43.237397 tx_last_pass[1][1][2] = 1005
4242 18:40:43.240341 tx_win_center[1][1][3] = 988
4243 18:40:43.243894 tx_first_pass[1][1][3] = 976
4244 18:40:43.247023 tx_last_pass[1][1][3] = 1001
4245 18:40:43.247523 tx_win_center[1][1][4] = 993
4246 18:40:43.250372 tx_first_pass[1][1][4] = 980
4247 18:40:43.253147 tx_last_pass[1][1][4] = 1006
4248 18:40:43.256595 tx_win_center[1][1][5] = 993
4249 18:40:43.259889 tx_first_pass[1][1][5] = 981
4250 18:40:43.260302 tx_last_pass[1][1][5] = 1006
4251 18:40:43.263231 tx_win_center[1][1][6] = 993
4252 18:40:43.266604 tx_first_pass[1][1][6] = 980
4253 18:40:43.269550 tx_last_pass[1][1][6] = 1006
4254 18:40:43.273386 tx_win_center[1][1][7] = 993
4255 18:40:43.273943 tx_first_pass[1][1][7] = 980
4256 18:40:43.276236 tx_last_pass[1][1][7] = 1006
4257 18:40:43.279592 tx_win_center[1][1][8] = 983
4258 18:40:43.282976 tx_first_pass[1][1][8] = 972
4259 18:40:43.286310 tx_last_pass[1][1][8] = 995
4260 18:40:43.286822 tx_win_center[1][1][9] = 983
4261 18:40:43.289359 tx_first_pass[1][1][9] = 971
4262 18:40:43.292564 tx_last_pass[1][1][9] = 995
4263 18:40:43.296116 tx_win_center[1][1][10] = 987
4264 18:40:43.299390 tx_first_pass[1][1][10] = 975
4265 18:40:43.299819 tx_last_pass[1][1][10] = 999
4266 18:40:43.302524 tx_win_center[1][1][11] = 987
4267 18:40:43.306060 tx_first_pass[1][1][11] = 975
4268 18:40:43.309047 tx_last_pass[1][1][11] = 999
4269 18:40:43.312550 tx_win_center[1][1][12] = 987
4270 18:40:43.313058 tx_first_pass[1][1][12] = 975
4271 18:40:43.315555 tx_last_pass[1][1][12] = 999
4272 18:40:43.318857 tx_win_center[1][1][13] = 987
4273 18:40:43.322306 tx_first_pass[1][1][13] = 975
4274 18:40:43.325273 tx_last_pass[1][1][13] = 1000
4275 18:40:43.328810 tx_win_center[1][1][14] = 987
4276 18:40:43.329312 tx_first_pass[1][1][14] = 975
4277 18:40:43.332140 tx_last_pass[1][1][14] = 999
4278 18:40:43.335158 tx_win_center[1][1][15] = 981
4279 18:40:43.338556 tx_first_pass[1][1][15] = 969
4280 18:40:43.341924 tx_last_pass[1][1][15] = 993
4281 18:40:43.342425 dump params rx window
4282 18:40:43.344957 rx_firspass[0][0][0] = 7
4283 18:40:43.348549 rx_lastpass[0][0][0] = 36
4284 18:40:43.349044 rx_firspass[0][0][1] = 7
4285 18:40:43.351823 rx_lastpass[0][0][1] = 36
4286 18:40:43.354718 rx_firspass[0][0][2] = 5
4287 18:40:43.355130 rx_lastpass[0][0][2] = 39
4288 18:40:43.358011 rx_firspass[0][0][3] = -3
4289 18:40:43.361345 rx_lastpass[0][0][3] = 30
4290 18:40:43.364676 rx_firspass[0][0][4] = 6
4291 18:40:43.365080 rx_lastpass[0][0][4] = 36
4292 18:40:43.367743 rx_firspass[0][0][5] = 2
4293 18:40:43.371362 rx_lastpass[0][0][5] = 33
4294 18:40:43.371870 rx_firspass[0][0][6] = 3
4295 18:40:43.374564 rx_lastpass[0][0][6] = 33
4296 18:40:43.377829 rx_firspass[0][0][7] = 4
4297 18:40:43.380989 rx_lastpass[0][0][7] = 36
4298 18:40:43.381391 rx_firspass[0][0][8] = -1
4299 18:40:43.384578 rx_lastpass[0][0][8] = 30
4300 18:40:43.388107 rx_firspass[0][0][9] = 2
4301 18:40:43.388617 rx_lastpass[0][0][9] = 32
4302 18:40:43.391300 rx_firspass[0][0][10] = 9
4303 18:40:43.394472 rx_lastpass[0][0][10] = 37
4304 18:40:43.397605 rx_firspass[0][0][11] = 1
4305 18:40:43.398010 rx_lastpass[0][0][11] = 30
4306 18:40:43.400722 rx_firspass[0][0][12] = 4
4307 18:40:43.403834 rx_lastpass[0][0][12] = 31
4308 18:40:43.407121 rx_firspass[0][0][13] = 2
4309 18:40:43.407646 rx_lastpass[0][0][13] = 31
4310 18:40:43.410502 rx_firspass[0][0][14] = 1
4311 18:40:43.414121 rx_lastpass[0][0][14] = 35
4312 18:40:43.417166 rx_firspass[0][0][15] = 4
4313 18:40:43.417717 rx_lastpass[0][0][15] = 36
4314 18:40:43.420241 rx_firspass[0][1][0] = 4
4315 18:40:43.423583 rx_lastpass[0][1][0] = 39
4316 18:40:43.423988 rx_firspass[0][1][1] = 5
4317 18:40:43.426592 rx_lastpass[0][1][1] = 38
4318 18:40:43.430041 rx_firspass[0][1][2] = 5
4319 18:40:43.433558 rx_lastpass[0][1][2] = 40
4320 18:40:43.434061 rx_firspass[0][1][3] = -3
4321 18:40:43.436677 rx_lastpass[0][1][3] = 31
4322 18:40:43.440122 rx_firspass[0][1][4] = 5
4323 18:40:43.440645 rx_lastpass[0][1][4] = 38
4324 18:40:43.443271 rx_firspass[0][1][5] = 0
4325 18:40:43.446471 rx_lastpass[0][1][5] = 34
4326 18:40:43.450107 rx_firspass[0][1][6] = 2
4327 18:40:43.450615 rx_lastpass[0][1][6] = 35
4328 18:40:43.452927 rx_firspass[0][1][7] = 3
4329 18:40:43.456248 rx_lastpass[0][1][7] = 37
4330 18:40:43.456660 rx_firspass[0][1][8] = -2
4331 18:40:43.459943 rx_lastpass[0][1][8] = 32
4332 18:40:43.462831 rx_firspass[0][1][9] = -1
4333 18:40:43.466180 rx_lastpass[0][1][9] = 34
4334 18:40:43.466678 rx_firspass[0][1][10] = 6
4335 18:40:43.469497 rx_lastpass[0][1][10] = 40
4336 18:40:43.472735 rx_firspass[0][1][11] = -2
4337 18:40:43.476231 rx_lastpass[0][1][11] = 32
4338 18:40:43.476641 rx_firspass[0][1][12] = 0
4339 18:40:43.479127 rx_lastpass[0][1][12] = 34
4340 18:40:43.482740 rx_firspass[0][1][13] = -1
4341 18:40:43.485758 rx_lastpass[0][1][13] = 34
4342 18:40:43.486267 rx_firspass[0][1][14] = 2
4343 18:40:43.489374 rx_lastpass[0][1][14] = 36
4344 18:40:43.492329 rx_firspass[0][1][15] = 4
4345 18:40:43.495891 rx_lastpass[0][1][15] = 38
4346 18:40:43.496421 rx_firspass[1][0][0] = 5
4347 18:40:43.498824 rx_lastpass[1][0][0] = 36
4348 18:40:43.501916 rx_firspass[1][0][1] = 3
4349 18:40:43.502323 rx_lastpass[1][0][1] = 37
4350 18:40:43.505781 rx_firspass[1][0][2] = 1
4351 18:40:43.508655 rx_lastpass[1][0][2] = 35
4352 18:40:43.512071 rx_firspass[1][0][3] = 0
4353 18:40:43.512580 rx_lastpass[1][0][3] = 31
4354 18:40:43.515656 rx_firspass[1][0][4] = 5
4355 18:40:43.518886 rx_lastpass[1][0][4] = 35
4356 18:40:43.519394 rx_firspass[1][0][5] = 9
4357 18:40:43.521795 rx_lastpass[1][0][5] = 38
4358 18:40:43.524866 rx_firspass[1][0][6] = 5
4359 18:40:43.528436 rx_lastpass[1][0][6] = 38
4360 18:40:43.528992 rx_firspass[1][0][7] = 5
4361 18:40:43.531511 rx_lastpass[1][0][7] = 35
4362 18:40:43.534455 rx_firspass[1][0][8] = 1
4363 18:40:43.534543 rx_lastpass[1][0][8] = 33
4364 18:40:43.537570 rx_firspass[1][0][9] = 0
4365 18:40:43.541242 rx_lastpass[1][0][9] = 32
4366 18:40:43.544367 rx_firspass[1][0][10] = 3
4367 18:40:43.544534 rx_lastpass[1][0][10] = 36
4368 18:40:43.547505 rx_firspass[1][0][11] = 4
4369 18:40:43.550822 rx_lastpass[1][0][11] = 36
4370 18:40:43.550971 rx_firspass[1][0][12] = 6
4371 18:40:43.553830 rx_lastpass[1][0][12] = 35
4372 18:40:43.557336 rx_firspass[1][0][13] = 6
4373 18:40:43.560775 rx_lastpass[1][0][13] = 36
4374 18:40:43.561176 rx_firspass[1][0][14] = 5
4375 18:40:43.564095 rx_lastpass[1][0][14] = 37
4376 18:40:43.567161 rx_firspass[1][0][15] = -3
4377 18:40:43.570813 rx_lastpass[1][0][15] = 29
4378 18:40:43.571321 rx_firspass[1][1][0] = 4
4379 18:40:43.574172 rx_lastpass[1][1][0] = 40
4380 18:40:43.577101 rx_firspass[1][1][1] = 4
4381 18:40:43.580347 rx_lastpass[1][1][1] = 39
4382 18:40:43.580789 rx_firspass[1][1][2] = 3
4383 18:40:43.583712 rx_lastpass[1][1][2] = 34
4384 18:40:43.587289 rx_firspass[1][1][3] = -1
4385 18:40:43.587797 rx_lastpass[1][1][3] = 33
4386 18:40:43.590238 rx_firspass[1][1][4] = 5
4387 18:40:43.593474 rx_lastpass[1][1][4] = 39
4388 18:40:43.596750 rx_firspass[1][1][5] = 7
4389 18:40:43.597152 rx_lastpass[1][1][5] = 40
4390 18:40:43.599942 rx_firspass[1][1][6] = 6
4391 18:40:43.603470 rx_lastpass[1][1][6] = 40
4392 18:40:43.604034 rx_firspass[1][1][7] = 3
4393 18:40:43.606315 rx_lastpass[1][1][7] = 38
4394 18:40:43.609985 rx_firspass[1][1][8] = -1
4395 18:40:43.613232 rx_lastpass[1][1][8] = 35
4396 18:40:43.613823 rx_firspass[1][1][9] = -2
4397 18:40:43.616242 rx_lastpass[1][1][9] = 33
4398 18:40:43.619523 rx_firspass[1][1][10] = 3
4399 18:40:43.619927 rx_lastpass[1][1][10] = 38
4400 18:40:43.623152 rx_firspass[1][1][11] = 4
4401 18:40:43.626030 rx_lastpass[1][1][11] = 38
4402 18:40:43.629572 rx_firspass[1][1][12] = 3
4403 18:40:43.630093 rx_lastpass[1][1][12] = 37
4404 18:40:43.632888 rx_firspass[1][1][13] = 4
4405 18:40:43.636047 rx_lastpass[1][1][13] = 39
4406 18:40:43.639374 rx_firspass[1][1][14] = 4
4407 18:40:43.639877 rx_lastpass[1][1][14] = 40
4408 18:40:43.642599 rx_firspass[1][1][15] = -4
4409 18:40:43.645796 rx_lastpass[1][1][15] = 31
4410 18:40:43.646298 dump params clk_delay
4411 18:40:43.649082 clk_delay[0] = 0
4412 18:40:43.649619 clk_delay[1] = 0
4413 18:40:43.652457 dump params dqs_delay
4414 18:40:43.655794 dqs_delay[0][0] = -1
4415 18:40:43.656267 dqs_delay[0][1] = 0
4416 18:40:43.659264 dqs_delay[1][0] = 0
4417 18:40:43.659665 dqs_delay[1][1] = -1
4418 18:40:43.661907 dump params delay_cell_unit = 744
4419 18:40:43.665264 dump source = 0x0
4420 18:40:43.665708 dump params frequency:1200
4421 18:40:43.668667 dump params rank number:2
4422 18:40:43.669069
4423 18:40:43.671982 dump params write leveling
4424 18:40:43.675576 write leveling[0][0][0] = 0x0
4425 18:40:43.678308 write leveling[0][0][1] = 0x0
4426 18:40:43.678710 write leveling[0][1][0] = 0x0
4427 18:40:43.681842 write leveling[0][1][1] = 0x0
4428 18:40:43.685415 write leveling[1][0][0] = 0x0
4429 18:40:43.688267 write leveling[1][0][1] = 0x0
4430 18:40:43.691664 write leveling[1][1][0] = 0x0
4431 18:40:43.695078 write leveling[1][1][1] = 0x0
4432 18:40:43.695578 dump params cbt_cs
4433 18:40:43.697984 cbt_cs[0][0] = 0x0
4434 18:40:43.698430 cbt_cs[0][1] = 0x0
4435 18:40:43.701584 cbt_cs[1][0] = 0x0
4436 18:40:43.702084 cbt_cs[1][1] = 0x0
4437 18:40:43.704861 dump params cbt_mr12
4438 18:40:43.705356 cbt_mr12[0][0] = 0x0
4439 18:40:43.708384 cbt_mr12[0][1] = 0x0
4440 18:40:43.708884 cbt_mr12[1][0] = 0x0
4441 18:40:43.711173 cbt_mr12[1][1] = 0x0
4442 18:40:43.714470 dump params tx window
4443 18:40:43.714874 tx_center_min[0][0][0] = 0
4444 18:40:43.717982 tx_center_max[0][0][0] = 0
4445 18:40:43.721292 tx_center_min[0][0][1] = 0
4446 18:40:43.724239 tx_center_max[0][0][1] = 0
4447 18:40:43.724648 tx_center_min[0][1][0] = 0
4448 18:40:43.727842 tx_center_max[0][1][0] = 0
4449 18:40:43.731182 tx_center_min[0][1][1] = 0
4450 18:40:43.734174 tx_center_max[0][1][1] = 0
4451 18:40:43.734577 tx_center_min[1][0][0] = 0
4452 18:40:43.737787 tx_center_max[1][0][0] = 0
4453 18:40:43.740783 tx_center_min[1][0][1] = 0
4454 18:40:43.743982 tx_center_max[1][0][1] = 0
4455 18:40:43.744384 tx_center_min[1][1][0] = 0
4456 18:40:43.747286 tx_center_max[1][1][0] = 0
4457 18:40:43.750498 tx_center_min[1][1][1] = 0
4458 18:40:43.753423 tx_center_max[1][1][1] = 0
4459 18:40:43.753849 dump params tx window
4460 18:40:43.756856 tx_win_center[0][0][0] = 0
4461 18:40:43.760806 tx_first_pass[0][0][0] = 0
4462 18:40:43.761304 tx_last_pass[0][0][0] = 0
4463 18:40:43.763881 tx_win_center[0][0][1] = 0
4464 18:40:43.766773 tx_first_pass[0][0][1] = 0
4465 18:40:43.770451 tx_last_pass[0][0][1] = 0
4466 18:40:43.770956 tx_win_center[0][0][2] = 0
4467 18:40:43.773423 tx_first_pass[0][0][2] = 0
4468 18:40:43.776983 tx_last_pass[0][0][2] = 0
4469 18:40:43.780097 tx_win_center[0][0][3] = 0
4470 18:40:43.780539 tx_first_pass[0][0][3] = 0
4471 18:40:43.783347 tx_last_pass[0][0][3] = 0
4472 18:40:43.786682 tx_win_center[0][0][4] = 0
4473 18:40:43.789857 tx_first_pass[0][0][4] = 0
4474 18:40:43.790258 tx_last_pass[0][0][4] = 0
4475 18:40:43.793075 tx_win_center[0][0][5] = 0
4476 18:40:43.796466 tx_first_pass[0][0][5] = 0
4477 18:40:43.799618 tx_last_pass[0][0][5] = 0
4478 18:40:43.800009 tx_win_center[0][0][6] = 0
4479 18:40:43.802942 tx_first_pass[0][0][6] = 0
4480 18:40:43.806278 tx_last_pass[0][0][6] = 0
4481 18:40:43.806651 tx_win_center[0][0][7] = 0
4482 18:40:43.809181 tx_first_pass[0][0][7] = 0
4483 18:40:43.812696 tx_last_pass[0][0][7] = 0
4484 18:40:43.816060 tx_win_center[0][0][8] = 0
4485 18:40:43.816557 tx_first_pass[0][0][8] = 0
4486 18:40:43.819327 tx_last_pass[0][0][8] = 0
4487 18:40:43.822464 tx_win_center[0][0][9] = 0
4488 18:40:43.825664 tx_first_pass[0][0][9] = 0
4489 18:40:43.826126 tx_last_pass[0][0][9] = 0
4490 18:40:43.828965 tx_win_center[0][0][10] = 0
4491 18:40:43.832291 tx_first_pass[0][0][10] = 0
4492 18:40:43.835622 tx_last_pass[0][0][10] = 0
4493 18:40:43.836001 tx_win_center[0][0][11] = 0
4494 18:40:43.838981 tx_first_pass[0][0][11] = 0
4495 18:40:43.842478 tx_last_pass[0][0][11] = 0
4496 18:40:43.845701 tx_win_center[0][0][12] = 0
4497 18:40:43.846079 tx_first_pass[0][0][12] = 0
4498 18:40:43.849023 tx_last_pass[0][0][12] = 0
4499 18:40:43.852079 tx_win_center[0][0][13] = 0
4500 18:40:43.855014 tx_first_pass[0][0][13] = 0
4501 18:40:43.858416 tx_last_pass[0][0][13] = 0
4502 18:40:43.858790 tx_win_center[0][0][14] = 0
4503 18:40:43.862054 tx_first_pass[0][0][14] = 0
4504 18:40:43.864921 tx_last_pass[0][0][14] = 0
4505 18:40:43.868349 tx_win_center[0][0][15] = 0
4506 18:40:43.868725 tx_first_pass[0][0][15] = 0
4507 18:40:43.872135 tx_last_pass[0][0][15] = 0
4508 18:40:43.874903 tx_win_center[0][1][0] = 0
4509 18:40:43.878304 tx_first_pass[0][1][0] = 0
4510 18:40:43.878744 tx_last_pass[0][1][0] = 0
4511 18:40:43.881320 tx_win_center[0][1][1] = 0
4512 18:40:43.884707 tx_first_pass[0][1][1] = 0
4513 18:40:43.887965 tx_last_pass[0][1][1] = 0
4514 18:40:43.888338 tx_win_center[0][1][2] = 0
4515 18:40:43.891207 tx_first_pass[0][1][2] = 0
4516 18:40:43.894842 tx_last_pass[0][1][2] = 0
4517 18:40:43.895317 tx_win_center[0][1][3] = 0
4518 18:40:43.897866 tx_first_pass[0][1][3] = 0
4519 18:40:43.901012 tx_last_pass[0][1][3] = 0
4520 18:40:43.904469 tx_win_center[0][1][4] = 0
4521 18:40:43.904954 tx_first_pass[0][1][4] = 0
4522 18:40:43.907922 tx_last_pass[0][1][4] = 0
4523 18:40:43.910756 tx_win_center[0][1][5] = 0
4524 18:40:43.914331 tx_first_pass[0][1][5] = 0
4525 18:40:43.914799 tx_last_pass[0][1][5] = 0
4526 18:40:43.917382 tx_win_center[0][1][6] = 0
4527 18:40:43.920558 tx_first_pass[0][1][6] = 0
4528 18:40:43.923999 tx_last_pass[0][1][6] = 0
4529 18:40:43.924496 tx_win_center[0][1][7] = 0
4530 18:40:43.927481 tx_first_pass[0][1][7] = 0
4531 18:40:43.931017 tx_last_pass[0][1][7] = 0
4532 18:40:43.933908 tx_win_center[0][1][8] = 0
4533 18:40:43.934320 tx_first_pass[0][1][8] = 0
4534 18:40:43.937296 tx_last_pass[0][1][8] = 0
4535 18:40:43.940450 tx_win_center[0][1][9] = 0
4536 18:40:43.940854 tx_first_pass[0][1][9] = 0
4537 18:40:43.943430 tx_last_pass[0][1][9] = 0
4538 18:40:43.946718 tx_win_center[0][1][10] = 0
4539 18:40:43.950361 tx_first_pass[0][1][10] = 0
4540 18:40:43.950771 tx_last_pass[0][1][10] = 0
4541 18:40:43.953454 tx_win_center[0][1][11] = 0
4542 18:40:43.956668 tx_first_pass[0][1][11] = 0
4543 18:40:43.959838 tx_last_pass[0][1][11] = 0
4544 18:40:43.963190 tx_win_center[0][1][12] = 0
4545 18:40:43.963579 tx_first_pass[0][1][12] = 0
4546 18:40:43.966461 tx_last_pass[0][1][12] = 0
4547 18:40:43.969934 tx_win_center[0][1][13] = 0
4548 18:40:43.972950 tx_first_pass[0][1][13] = 0
4549 18:40:43.973322 tx_last_pass[0][1][13] = 0
4550 18:40:43.976670 tx_win_center[0][1][14] = 0
4551 18:40:43.980079 tx_first_pass[0][1][14] = 0
4552 18:40:43.983324 tx_last_pass[0][1][14] = 0
4553 18:40:43.983824 tx_win_center[0][1][15] = 0
4554 18:40:43.986261 tx_first_pass[0][1][15] = 0
4555 18:40:43.990011 tx_last_pass[0][1][15] = 0
4556 18:40:43.992911 tx_win_center[1][0][0] = 0
4557 18:40:43.993411 tx_first_pass[1][0][0] = 0
4558 18:40:43.996422 tx_last_pass[1][0][0] = 0
4559 18:40:43.999658 tx_win_center[1][0][1] = 0
4560 18:40:44.002805 tx_first_pass[1][0][1] = 0
4561 18:40:44.003314 tx_last_pass[1][0][1] = 0
4562 18:40:44.005843 tx_win_center[1][0][2] = 0
4563 18:40:44.009302 tx_first_pass[1][0][2] = 0
4564 18:40:44.012493 tx_last_pass[1][0][2] = 0
4565 18:40:44.012990 tx_win_center[1][0][3] = 0
4566 18:40:44.015668 tx_first_pass[1][0][3] = 0
4567 18:40:44.019349 tx_last_pass[1][0][3] = 0
4568 18:40:44.022155 tx_win_center[1][0][4] = 0
4569 18:40:44.022562 tx_first_pass[1][0][4] = 0
4570 18:40:44.025491 tx_last_pass[1][0][4] = 0
4571 18:40:44.028835 tx_win_center[1][0][5] = 0
4572 18:40:44.029420 tx_first_pass[1][0][5] = 0
4573 18:40:44.032430 tx_last_pass[1][0][5] = 0
4574 18:40:44.035304 tx_win_center[1][0][6] = 0
4575 18:40:44.038532 tx_first_pass[1][0][6] = 0
4576 18:40:44.039124 tx_last_pass[1][0][6] = 0
4577 18:40:44.041696 tx_win_center[1][0][7] = 0
4578 18:40:44.044870 tx_first_pass[1][0][7] = 0
4579 18:40:44.048495 tx_last_pass[1][0][7] = 0
4580 18:40:44.048869 tx_win_center[1][0][8] = 0
4581 18:40:44.051651 tx_first_pass[1][0][8] = 0
4582 18:40:44.054950 tx_last_pass[1][0][8] = 0
4583 18:40:44.058211 tx_win_center[1][0][9] = 0
4584 18:40:44.058651 tx_first_pass[1][0][9] = 0
4585 18:40:44.061525 tx_last_pass[1][0][9] = 0
4586 18:40:44.065327 tx_win_center[1][0][10] = 0
4587 18:40:44.068008 tx_first_pass[1][0][10] = 0
4588 18:40:44.068418 tx_last_pass[1][0][10] = 0
4589 18:40:44.071621 tx_win_center[1][0][11] = 0
4590 18:40:44.074838 tx_first_pass[1][0][11] = 0
4591 18:40:44.078032 tx_last_pass[1][0][11] = 0
4592 18:40:44.078459 tx_win_center[1][0][12] = 0
4593 18:40:44.081172 tx_first_pass[1][0][12] = 0
4594 18:40:44.084480 tx_last_pass[1][0][12] = 0
4595 18:40:44.088070 tx_win_center[1][0][13] = 0
4596 18:40:44.088580 tx_first_pass[1][0][13] = 0
4597 18:40:44.091015 tx_last_pass[1][0][13] = 0
4598 18:40:44.094385 tx_win_center[1][0][14] = 0
4599 18:40:44.097779 tx_first_pass[1][0][14] = 0
4600 18:40:44.098295 tx_last_pass[1][0][14] = 0
4601 18:40:44.100952 tx_win_center[1][0][15] = 0
4602 18:40:44.104425 tx_first_pass[1][0][15] = 0
4603 18:40:44.107559 tx_last_pass[1][0][15] = 0
4604 18:40:44.110755 tx_win_center[1][1][0] = 0
4605 18:40:44.111269 tx_first_pass[1][1][0] = 0
4606 18:40:44.114307 tx_last_pass[1][1][0] = 0
4607 18:40:44.117404 tx_win_center[1][1][1] = 0
4608 18:40:44.120538 tx_first_pass[1][1][1] = 0
4609 18:40:44.120946 tx_last_pass[1][1][1] = 0
4610 18:40:44.123809 tx_win_center[1][1][2] = 0
4611 18:40:44.126940 tx_first_pass[1][1][2] = 0
4612 18:40:44.127476 tx_last_pass[1][1][2] = 0
4613 18:40:44.130091 tx_win_center[1][1][3] = 0
4614 18:40:44.133525 tx_first_pass[1][1][3] = 0
4615 18:40:44.136723 tx_last_pass[1][1][3] = 0
4616 18:40:44.137267 tx_win_center[1][1][4] = 0
4617 18:40:44.140363 tx_first_pass[1][1][4] = 0
4618 18:40:44.143521 tx_last_pass[1][1][4] = 0
4619 18:40:44.146508 tx_win_center[1][1][5] = 0
4620 18:40:44.147012 tx_first_pass[1][1][5] = 0
4621 18:40:44.149687 tx_last_pass[1][1][5] = 0
4622 18:40:44.153133 tx_win_center[1][1][6] = 0
4623 18:40:44.156344 tx_first_pass[1][1][6] = 0
4624 18:40:44.156785 tx_last_pass[1][1][6] = 0
4625 18:40:44.159531 tx_win_center[1][1][7] = 0
4626 18:40:44.163095 tx_first_pass[1][1][7] = 0
4627 18:40:44.166360 tx_last_pass[1][1][7] = 0
4628 18:40:44.166768 tx_win_center[1][1][8] = 0
4629 18:40:44.169780 tx_first_pass[1][1][8] = 0
4630 18:40:44.172828 tx_last_pass[1][1][8] = 0
4631 18:40:44.173331 tx_win_center[1][1][9] = 0
4632 18:40:44.176301 tx_first_pass[1][1][9] = 0
4633 18:40:44.179200 tx_last_pass[1][1][9] = 0
4634 18:40:44.182690 tx_win_center[1][1][10] = 0
4635 18:40:44.183199 tx_first_pass[1][1][10] = 0
4636 18:40:44.185945 tx_last_pass[1][1][10] = 0
4637 18:40:44.189290 tx_win_center[1][1][11] = 0
4638 18:40:44.192048 tx_first_pass[1][1][11] = 0
4639 18:40:44.195532 tx_last_pass[1][1][11] = 0
4640 18:40:44.196046 tx_win_center[1][1][12] = 0
4641 18:40:44.198912 tx_first_pass[1][1][12] = 0
4642 18:40:44.201929 tx_last_pass[1][1][12] = 0
4643 18:40:44.205653 tx_win_center[1][1][13] = 0
4644 18:40:44.206156 tx_first_pass[1][1][13] = 0
4645 18:40:44.208862 tx_last_pass[1][1][13] = 0
4646 18:40:44.211695 tx_win_center[1][1][14] = 0
4647 18:40:44.215157 tx_first_pass[1][1][14] = 0
4648 18:40:44.215696 tx_last_pass[1][1][14] = 0
4649 18:40:44.218349 tx_win_center[1][1][15] = 0
4650 18:40:44.221650 tx_first_pass[1][1][15] = 0
4651 18:40:44.225340 tx_last_pass[1][1][15] = 0
4652 18:40:44.225897 dump params rx window
4653 18:40:44.228340 rx_firspass[0][0][0] = 0
4654 18:40:44.231925 rx_lastpass[0][0][0] = 0
4655 18:40:44.232585 rx_firspass[0][0][1] = 0
4656 18:40:44.234755 rx_lastpass[0][0][1] = 0
4657 18:40:44.238119 rx_firspass[0][0][2] = 0
4658 18:40:44.238526 rx_lastpass[0][0][2] = 0
4659 18:40:44.241575 rx_firspass[0][0][3] = 0
4660 18:40:44.244853 rx_lastpass[0][0][3] = 0
4661 18:40:44.248244 rx_firspass[0][0][4] = 0
4662 18:40:44.248766 rx_lastpass[0][0][4] = 0
4663 18:40:44.251181 rx_firspass[0][0][5] = 0
4664 18:40:44.254693 rx_lastpass[0][0][5] = 0
4665 18:40:44.255265 rx_firspass[0][0][6] = 0
4666 18:40:44.257748 rx_lastpass[0][0][6] = 0
4667 18:40:44.260718 rx_firspass[0][0][7] = 0
4668 18:40:44.261123 rx_lastpass[0][0][7] = 0
4669 18:40:44.264504 rx_firspass[0][0][8] = 0
4670 18:40:44.267870 rx_lastpass[0][0][8] = 0
4671 18:40:44.270902 rx_firspass[0][0][9] = 0
4672 18:40:44.271309 rx_lastpass[0][0][9] = 0
4673 18:40:44.274368 rx_firspass[0][0][10] = 0
4674 18:40:44.277623 rx_lastpass[0][0][10] = 0
4675 18:40:44.278158 rx_firspass[0][0][11] = 0
4676 18:40:44.280743 rx_lastpass[0][0][11] = 0
4677 18:40:44.284234 rx_firspass[0][0][12] = 0
4678 18:40:44.287401 rx_lastpass[0][0][12] = 0
4679 18:40:44.287909 rx_firspass[0][0][13] = 0
4680 18:40:44.290421 rx_lastpass[0][0][13] = 0
4681 18:40:44.293883 rx_firspass[0][0][14] = 0
4682 18:40:44.297206 rx_lastpass[0][0][14] = 0
4683 18:40:44.297822 rx_firspass[0][0][15] = 0
4684 18:40:44.300515 rx_lastpass[0][0][15] = 0
4685 18:40:44.303220 rx_firspass[0][1][0] = 0
4686 18:40:44.303628 rx_lastpass[0][1][0] = 0
4687 18:40:44.306720 rx_firspass[0][1][1] = 0
4688 18:40:44.310260 rx_lastpass[0][1][1] = 0
4689 18:40:44.310758 rx_firspass[0][1][2] = 0
4690 18:40:44.313145 rx_lastpass[0][1][2] = 0
4691 18:40:44.316581 rx_firspass[0][1][3] = 0
4692 18:40:44.320030 rx_lastpass[0][1][3] = 0
4693 18:40:44.320557 rx_firspass[0][1][4] = 0
4694 18:40:44.322869 rx_lastpass[0][1][4] = 0
4695 18:40:44.326426 rx_firspass[0][1][5] = 0
4696 18:40:44.326926 rx_lastpass[0][1][5] = 0
4697 18:40:44.329338 rx_firspass[0][1][6] = 0
4698 18:40:44.332856 rx_lastpass[0][1][6] = 0
4699 18:40:44.333258 rx_firspass[0][1][7] = 0
4700 18:40:44.336509 rx_lastpass[0][1][7] = 0
4701 18:40:44.339506 rx_firspass[0][1][8] = 0
4702 18:40:44.342830 rx_lastpass[0][1][8] = 0
4703 18:40:44.343335 rx_firspass[0][1][9] = 0
4704 18:40:44.345794 rx_lastpass[0][1][9] = 0
4705 18:40:44.349352 rx_firspass[0][1][10] = 0
4706 18:40:44.349929 rx_lastpass[0][1][10] = 0
4707 18:40:44.352290 rx_firspass[0][1][11] = 0
4708 18:40:44.355552 rx_lastpass[0][1][11] = 0
4709 18:40:44.358910 rx_firspass[0][1][12] = 0
4710 18:40:44.359319 rx_lastpass[0][1][12] = 0
4711 18:40:44.362171 rx_firspass[0][1][13] = 0
4712 18:40:44.365305 rx_lastpass[0][1][13] = 0
4713 18:40:44.365863 rx_firspass[0][1][14] = 0
4714 18:40:44.368870 rx_lastpass[0][1][14] = 0
4715 18:40:44.372346 rx_firspass[0][1][15] = 0
4716 18:40:44.375595 rx_lastpass[0][1][15] = 0
4717 18:40:44.376098 rx_firspass[1][0][0] = 0
4718 18:40:44.378907 rx_lastpass[1][0][0] = 0
4719 18:40:44.381909 rx_firspass[1][0][1] = 0
4720 18:40:44.382320 rx_lastpass[1][0][1] = 0
4721 18:40:44.385485 rx_firspass[1][0][2] = 0
4722 18:40:44.388655 rx_lastpass[1][0][2] = 0
4723 18:40:44.391848 rx_firspass[1][0][3] = 0
4724 18:40:44.392363 rx_lastpass[1][0][3] = 0
4725 18:40:44.394971 rx_firspass[1][0][4] = 0
4726 18:40:44.398309 rx_lastpass[1][0][4] = 0
4727 18:40:44.398811 rx_firspass[1][0][5] = 0
4728 18:40:44.401509 rx_lastpass[1][0][5] = 0
4729 18:40:44.405070 rx_firspass[1][0][6] = 0
4730 18:40:44.405627 rx_lastpass[1][0][6] = 0
4731 18:40:44.408335 rx_firspass[1][0][7] = 0
4732 18:40:44.411575 rx_lastpass[1][0][7] = 0
4733 18:40:44.414902 rx_firspass[1][0][8] = 0
4734 18:40:44.415401 rx_lastpass[1][0][8] = 0
4735 18:40:44.417971 rx_firspass[1][0][9] = 0
4736 18:40:44.421294 rx_lastpass[1][0][9] = 0
4737 18:40:44.421875 rx_firspass[1][0][10] = 0
4738 18:40:44.424221 rx_lastpass[1][0][10] = 0
4739 18:40:44.427621 rx_firspass[1][0][11] = 0
4740 18:40:44.430959 rx_lastpass[1][0][11] = 0
4741 18:40:44.431460 rx_firspass[1][0][12] = 0
4742 18:40:44.434241 rx_lastpass[1][0][12] = 0
4743 18:40:44.437682 rx_firspass[1][0][13] = 0
4744 18:40:44.438184 rx_lastpass[1][0][13] = 0
4745 18:40:44.440937 rx_firspass[1][0][14] = 0
4746 18:40:44.444202 rx_lastpass[1][0][14] = 0
4747 18:40:44.447291 rx_firspass[1][0][15] = 0
4748 18:40:44.447799 rx_lastpass[1][0][15] = 0
4749 18:40:44.451175 rx_firspass[1][1][0] = 0
4750 18:40:44.453827 rx_lastpass[1][1][0] = 0
4751 18:40:44.454431 rx_firspass[1][1][1] = 0
4752 18:40:44.457160 rx_lastpass[1][1][1] = 0
4753 18:40:44.460330 rx_firspass[1][1][2] = 0
4754 18:40:44.463698 rx_lastpass[1][1][2] = 0
4755 18:40:44.464107 rx_firspass[1][1][3] = 0
4756 18:40:44.466963 rx_lastpass[1][1][3] = 0
4757 18:40:44.470112 rx_firspass[1][1][4] = 0
4758 18:40:44.470518 rx_lastpass[1][1][4] = 0
4759 18:40:44.473254 rx_firspass[1][1][5] = 0
4760 18:40:44.476782 rx_lastpass[1][1][5] = 0
4761 18:40:44.477532 rx_firspass[1][1][6] = 0
4762 18:40:44.480146 rx_lastpass[1][1][6] = 0
4763 18:40:44.483018 rx_firspass[1][1][7] = 0
4764 18:40:44.483427 rx_lastpass[1][1][7] = 0
4765 18:40:44.486532 rx_firspass[1][1][8] = 0
4766 18:40:44.489676 rx_lastpass[1][1][8] = 0
4767 18:40:44.493021 rx_firspass[1][1][9] = 0
4768 18:40:44.493578 rx_lastpass[1][1][9] = 0
4769 18:40:44.496168 rx_firspass[1][1][10] = 0
4770 18:40:44.499899 rx_lastpass[1][1][10] = 0
4771 18:40:44.500408 rx_firspass[1][1][11] = 0
4772 18:40:44.502720 rx_lastpass[1][1][11] = 0
4773 18:40:44.506251 rx_firspass[1][1][12] = 0
4774 18:40:44.509745 rx_lastpass[1][1][12] = 0
4775 18:40:44.510270 rx_firspass[1][1][13] = 0
4776 18:40:44.512950 rx_lastpass[1][1][13] = 0
4777 18:40:44.516398 rx_firspass[1][1][14] = 0
4778 18:40:44.519269 rx_lastpass[1][1][14] = 0
4779 18:40:44.519778 rx_firspass[1][1][15] = 0
4780 18:40:44.522663 rx_lastpass[1][1][15] = 0
4781 18:40:44.525887 dump params clk_delay
4782 18:40:44.526395 clk_delay[0] = 0
4783 18:40:44.529168 clk_delay[1] = 0
4784 18:40:44.529730 dump params dqs_delay
4785 18:40:44.532640 dqs_delay[0][0] = 0
4786 18:40:44.533149 dqs_delay[0][1] = 0
4787 18:40:44.535764 dqs_delay[1][0] = 0
4788 18:40:44.536269 dqs_delay[1][1] = 0
4789 18:40:44.538837 dump params delay_cell_unit = 744
4790 18:40:44.541911 dump source = 0x0
4791 18:40:44.542318 dump params frequency:800
4792 18:40:44.545582 dump params rank number:2
4793 18:40:44.546134
4794 18:40:44.549000 dump params write leveling
4795 18:40:44.551792 write leveling[0][0][0] = 0x0
4796 18:40:44.555429 write leveling[0][0][1] = 0x0
4797 18:40:44.555947 write leveling[0][1][0] = 0x0
4798 18:40:44.558661 write leveling[0][1][1] = 0x0
4799 18:40:44.561801 write leveling[1][0][0] = 0x0
4800 18:40:44.565401 write leveling[1][0][1] = 0x0
4801 18:40:44.568764 write leveling[1][1][0] = 0x0
4802 18:40:44.571524 write leveling[1][1][1] = 0x0
4803 18:40:44.571934 dump params cbt_cs
4804 18:40:44.575192 cbt_cs[0][0] = 0x0
4805 18:40:44.575597 cbt_cs[0][1] = 0x0
4806 18:40:44.577920 cbt_cs[1][0] = 0x0
4807 18:40:44.578354 cbt_cs[1][1] = 0x0
4808 18:40:44.581401 dump params cbt_mr12
4809 18:40:44.581844 cbt_mr12[0][0] = 0x0
4810 18:40:44.584766 cbt_mr12[0][1] = 0x0
4811 18:40:44.585240 cbt_mr12[1][0] = 0x0
4812 18:40:44.587921 cbt_mr12[1][1] = 0x0
4813 18:40:44.591150 dump params tx window
4814 18:40:44.591667 tx_center_min[0][0][0] = 0
4815 18:40:44.594745 tx_center_max[0][0][0] = 0
4816 18:40:44.598372 tx_center_min[0][0][1] = 0
4817 18:40:44.601321 tx_center_max[0][0][1] = 0
4818 18:40:44.601890 tx_center_min[0][1][0] = 0
4819 18:40:44.604823 tx_center_max[0][1][0] = 0
4820 18:40:44.607489 tx_center_min[0][1][1] = 0
4821 18:40:44.610838 tx_center_max[0][1][1] = 0
4822 18:40:44.611342 tx_center_min[1][0][0] = 0
4823 18:40:44.614019 tx_center_max[1][0][0] = 0
4824 18:40:44.617314 tx_center_min[1][0][1] = 0
4825 18:40:44.620753 tx_center_max[1][0][1] = 0
4826 18:40:44.621161 tx_center_min[1][1][0] = 0
4827 18:40:44.623935 tx_center_max[1][1][0] = 0
4828 18:40:44.627216 tx_center_min[1][1][1] = 0
4829 18:40:44.630579 tx_center_max[1][1][1] = 0
4830 18:40:44.630987 dump params tx window
4831 18:40:44.633773 tx_win_center[0][0][0] = 0
4832 18:40:44.637054 tx_first_pass[0][0][0] = 0
4833 18:40:44.637500 tx_last_pass[0][0][0] = 0
4834 18:40:44.640352 tx_win_center[0][0][1] = 0
4835 18:40:44.644190 tx_first_pass[0][0][1] = 0
4836 18:40:44.646844 tx_last_pass[0][0][1] = 0
4837 18:40:44.647254 tx_win_center[0][0][2] = 0
4838 18:40:44.650355 tx_first_pass[0][0][2] = 0
4839 18:40:44.653639 tx_last_pass[0][0][2] = 0
4840 18:40:44.656604 tx_win_center[0][0][3] = 0
4841 18:40:44.657016 tx_first_pass[0][0][3] = 0
4842 18:40:44.659986 tx_last_pass[0][0][3] = 0
4843 18:40:44.663244 tx_win_center[0][0][4] = 0
4844 18:40:44.666725 tx_first_pass[0][0][4] = 0
4845 18:40:44.667225 tx_last_pass[0][0][4] = 0
4846 18:40:44.669769 tx_win_center[0][0][5] = 0
4847 18:40:44.673091 tx_first_pass[0][0][5] = 0
4848 18:40:44.676325 tx_last_pass[0][0][5] = 0
4849 18:40:44.676840 tx_win_center[0][0][6] = 0
4850 18:40:44.679379 tx_first_pass[0][0][6] = 0
4851 18:40:44.682737 tx_last_pass[0][0][6] = 0
4852 18:40:44.686016 tx_win_center[0][0][7] = 0
4853 18:40:44.686423 tx_first_pass[0][0][7] = 0
4854 18:40:44.689498 tx_last_pass[0][0][7] = 0
4855 18:40:44.692377 tx_win_center[0][0][8] = 0
4856 18:40:44.695988 tx_first_pass[0][0][8] = 0
4857 18:40:44.696490 tx_last_pass[0][0][8] = 0
4858 18:40:44.699270 tx_win_center[0][0][9] = 0
4859 18:40:44.702070 tx_first_pass[0][0][9] = 0
4860 18:40:44.702483 tx_last_pass[0][0][9] = 0
4861 18:40:44.705457 tx_win_center[0][0][10] = 0
4862 18:40:44.709180 tx_first_pass[0][0][10] = 0
4863 18:40:44.712446 tx_last_pass[0][0][10] = 0
4864 18:40:44.712947 tx_win_center[0][0][11] = 0
4865 18:40:44.715678 tx_first_pass[0][0][11] = 0
4866 18:40:44.718441 tx_last_pass[0][0][11] = 0
4867 18:40:44.722429 tx_win_center[0][0][12] = 0
4868 18:40:44.725610 tx_first_pass[0][0][12] = 0
4869 18:40:44.726115 tx_last_pass[0][0][12] = 0
4870 18:40:44.728782 tx_win_center[0][0][13] = 0
4871 18:40:44.732189 tx_first_pass[0][0][13] = 0
4872 18:40:44.735460 tx_last_pass[0][0][13] = 0
4873 18:40:44.735969 tx_win_center[0][0][14] = 0
4874 18:40:44.738212 tx_first_pass[0][0][14] = 0
4875 18:40:44.741607 tx_last_pass[0][0][14] = 0
4876 18:40:44.744942 tx_win_center[0][0][15] = 0
4877 18:40:44.745496 tx_first_pass[0][0][15] = 0
4878 18:40:44.748507 tx_last_pass[0][0][15] = 0
4879 18:40:44.751523 tx_win_center[0][1][0] = 0
4880 18:40:44.754775 tx_first_pass[0][1][0] = 0
4881 18:40:44.755291 tx_last_pass[0][1][0] = 0
4882 18:40:44.757988 tx_win_center[0][1][1] = 0
4883 18:40:44.761096 tx_first_pass[0][1][1] = 0
4884 18:40:44.764841 tx_last_pass[0][1][1] = 0
4885 18:40:44.765357 tx_win_center[0][1][2] = 0
4886 18:40:44.768109 tx_first_pass[0][1][2] = 0
4887 18:40:44.771218 tx_last_pass[0][1][2] = 0
4888 18:40:44.774299 tx_win_center[0][1][3] = 0
4889 18:40:44.774707 tx_first_pass[0][1][3] = 0
4890 18:40:44.777766 tx_last_pass[0][1][3] = 0
4891 18:40:44.781024 tx_win_center[0][1][4] = 0
4892 18:40:44.784249 tx_first_pass[0][1][4] = 0
4893 18:40:44.784757 tx_last_pass[0][1][4] = 0
4894 18:40:44.787421 tx_win_center[0][1][5] = 0
4895 18:40:44.790605 tx_first_pass[0][1][5] = 0
4896 18:40:44.791011 tx_last_pass[0][1][5] = 0
4897 18:40:44.794179 tx_win_center[0][1][6] = 0
4898 18:40:44.797943 tx_first_pass[0][1][6] = 0
4899 18:40:44.800583 tx_last_pass[0][1][6] = 0
4900 18:40:44.801033 tx_win_center[0][1][7] = 0
4901 18:40:44.803782 tx_first_pass[0][1][7] = 0
4902 18:40:44.807222 tx_last_pass[0][1][7] = 0
4903 18:40:44.810872 tx_win_center[0][1][8] = 0
4904 18:40:44.811382 tx_first_pass[0][1][8] = 0
4905 18:40:44.813943 tx_last_pass[0][1][8] = 0
4906 18:40:44.817219 tx_win_center[0][1][9] = 0
4907 18:40:44.820605 tx_first_pass[0][1][9] = 0
4908 18:40:44.821111 tx_last_pass[0][1][9] = 0
4909 18:40:44.823601 tx_win_center[0][1][10] = 0
4910 18:40:44.826622 tx_first_pass[0][1][10] = 0
4911 18:40:44.830103 tx_last_pass[0][1][10] = 0
4912 18:40:44.830614 tx_win_center[0][1][11] = 0
4913 18:40:44.833942 tx_first_pass[0][1][11] = 0
4914 18:40:44.837141 tx_last_pass[0][1][11] = 0
4915 18:40:44.839701 tx_win_center[0][1][12] = 0
4916 18:40:44.840115 tx_first_pass[0][1][12] = 0
4917 18:40:44.843423 tx_last_pass[0][1][12] = 0
4918 18:40:44.846676 tx_win_center[0][1][13] = 0
4919 18:40:44.849870 tx_first_pass[0][1][13] = 0
4920 18:40:44.850381 tx_last_pass[0][1][13] = 0
4921 18:40:44.852831 tx_win_center[0][1][14] = 0
4922 18:40:44.856225 tx_first_pass[0][1][14] = 0
4923 18:40:44.859630 tx_last_pass[0][1][14] = 0
4924 18:40:44.860041 tx_win_center[0][1][15] = 0
4925 18:40:44.862784 tx_first_pass[0][1][15] = 0
4926 18:40:44.866137 tx_last_pass[0][1][15] = 0
4927 18:40:44.869670 tx_win_center[1][0][0] = 0
4928 18:40:44.872766 tx_first_pass[1][0][0] = 0
4929 18:40:44.873280 tx_last_pass[1][0][0] = 0
4930 18:40:44.875706 tx_win_center[1][0][1] = 0
4931 18:40:44.879258 tx_first_pass[1][0][1] = 0
4932 18:40:44.879670 tx_last_pass[1][0][1] = 0
4933 18:40:44.882591 tx_win_center[1][0][2] = 0
4934 18:40:44.885976 tx_first_pass[1][0][2] = 0
4935 18:40:44.889027 tx_last_pass[1][0][2] = 0
4936 18:40:44.889469 tx_win_center[1][0][3] = 0
4937 18:40:44.892222 tx_first_pass[1][0][3] = 0
4938 18:40:44.895673 tx_last_pass[1][0][3] = 0
4939 18:40:44.898974 tx_win_center[1][0][4] = 0
4940 18:40:44.899493 tx_first_pass[1][0][4] = 0
4941 18:40:44.902410 tx_last_pass[1][0][4] = 0
4942 18:40:44.905577 tx_win_center[1][0][5] = 0
4943 18:40:44.908749 tx_first_pass[1][0][5] = 0
4944 18:40:44.909276 tx_last_pass[1][0][5] = 0
4945 18:40:44.911722 tx_win_center[1][0][6] = 0
4946 18:40:44.915620 tx_first_pass[1][0][6] = 0
4947 18:40:44.916133 tx_last_pass[1][0][6] = 0
4948 18:40:44.918522 tx_win_center[1][0][7] = 0
4949 18:40:44.921871 tx_first_pass[1][0][7] = 0
4950 18:40:44.925037 tx_last_pass[1][0][7] = 0
4951 18:40:44.925646 tx_win_center[1][0][8] = 0
4952 18:40:44.928172 tx_first_pass[1][0][8] = 0
4953 18:40:44.931902 tx_last_pass[1][0][8] = 0
4954 18:40:44.934668 tx_win_center[1][0][9] = 0
4955 18:40:44.935079 tx_first_pass[1][0][9] = 0
4956 18:40:44.938325 tx_last_pass[1][0][9] = 0
4957 18:40:44.941699 tx_win_center[1][0][10] = 0
4958 18:40:44.944901 tx_first_pass[1][0][10] = 0
4959 18:40:44.945404 tx_last_pass[1][0][10] = 0
4960 18:40:44.948077 tx_win_center[1][0][11] = 0
4961 18:40:44.951302 tx_first_pass[1][0][11] = 0
4962 18:40:44.954545 tx_last_pass[1][0][11] = 0
4963 18:40:44.955079 tx_win_center[1][0][12] = 0
4964 18:40:44.957933 tx_first_pass[1][0][12] = 0
4965 18:40:44.960833 tx_last_pass[1][0][12] = 0
4966 18:40:44.964276 tx_win_center[1][0][13] = 0
4967 18:40:44.967925 tx_first_pass[1][0][13] = 0
4968 18:40:44.968434 tx_last_pass[1][0][13] = 0
4969 18:40:44.970969 tx_win_center[1][0][14] = 0
4970 18:40:44.974296 tx_first_pass[1][0][14] = 0
4971 18:40:44.977156 tx_last_pass[1][0][14] = 0
4972 18:40:44.977622 tx_win_center[1][0][15] = 0
4973 18:40:44.980604 tx_first_pass[1][0][15] = 0
4974 18:40:44.983709 tx_last_pass[1][0][15] = 0
4975 18:40:44.987311 tx_win_center[1][1][0] = 0
4976 18:40:44.987722 tx_first_pass[1][1][0] = 0
4977 18:40:44.990357 tx_last_pass[1][1][0] = 0
4978 18:40:44.993715 tx_win_center[1][1][1] = 0
4979 18:40:44.996971 tx_first_pass[1][1][1] = 0
4980 18:40:44.997380 tx_last_pass[1][1][1] = 0
4981 18:40:45.000208 tx_win_center[1][1][2] = 0
4982 18:40:45.003563 tx_first_pass[1][1][2] = 0
4983 18:40:45.003974 tx_last_pass[1][1][2] = 0
4984 18:40:45.006636 tx_win_center[1][1][3] = 0
4985 18:40:45.010110 tx_first_pass[1][1][3] = 0
4986 18:40:45.013366 tx_last_pass[1][1][3] = 0
4987 18:40:45.014055 tx_win_center[1][1][4] = 0
4988 18:40:45.016747 tx_first_pass[1][1][4] = 0
4989 18:40:45.019762 tx_last_pass[1][1][4] = 0
4990 18:40:45.023008 tx_win_center[1][1][5] = 0
4991 18:40:45.023415 tx_first_pass[1][1][5] = 0
4992 18:40:45.026321 tx_last_pass[1][1][5] = 0
4993 18:40:45.029534 tx_win_center[1][1][6] = 0
4994 18:40:45.032941 tx_first_pass[1][1][6] = 0
4995 18:40:45.033489 tx_last_pass[1][1][6] = 0
4996 18:40:45.036319 tx_win_center[1][1][7] = 0
4997 18:40:45.039513 tx_first_pass[1][1][7] = 0
4998 18:40:45.042519 tx_last_pass[1][1][7] = 0
4999 18:40:45.043128 tx_win_center[1][1][8] = 0
5000 18:40:45.045809 tx_first_pass[1][1][8] = 0
5001 18:40:45.049515 tx_last_pass[1][1][8] = 0
5002 18:40:45.050159 tx_win_center[1][1][9] = 0
5003 18:40:45.052411 tx_first_pass[1][1][9] = 0
5004 18:40:45.055861 tx_last_pass[1][1][9] = 0
5005 18:40:45.059212 tx_win_center[1][1][10] = 0
5006 18:40:45.062349 tx_first_pass[1][1][10] = 0
5007 18:40:45.062828 tx_last_pass[1][1][10] = 0
5008 18:40:45.065495 tx_win_center[1][1][11] = 0
5009 18:40:45.069194 tx_first_pass[1][1][11] = 0
5010 18:40:45.072445 tx_last_pass[1][1][11] = 0
5011 18:40:45.072963 tx_win_center[1][1][12] = 0
5012 18:40:45.076183 tx_first_pass[1][1][12] = 0
5013 18:40:45.079310 tx_last_pass[1][1][12] = 0
5014 18:40:45.082139 tx_win_center[1][1][13] = 0
5015 18:40:45.082573 tx_first_pass[1][1][13] = 0
5016 18:40:45.085243 tx_last_pass[1][1][13] = 0
5017 18:40:45.088417 tx_win_center[1][1][14] = 0
5018 18:40:45.092252 tx_first_pass[1][1][14] = 0
5019 18:40:45.092762 tx_last_pass[1][1][14] = 0
5020 18:40:45.095204 tx_win_center[1][1][15] = 0
5021 18:40:45.098390 tx_first_pass[1][1][15] = 0
5022 18:40:45.101710 tx_last_pass[1][1][15] = 0
5023 18:40:45.102353 dump params rx window
5024 18:40:45.104883 rx_firspass[0][0][0] = 0
5025 18:40:45.108017 rx_lastpass[0][0][0] = 0
5026 18:40:45.108439 rx_firspass[0][0][1] = 0
5027 18:40:45.111338 rx_lastpass[0][0][1] = 0
5028 18:40:45.114730 rx_firspass[0][0][2] = 0
5029 18:40:45.117791 rx_lastpass[0][0][2] = 0
5030 18:40:45.118363 rx_firspass[0][0][3] = 0
5031 18:40:45.121400 rx_lastpass[0][0][3] = 0
5032 18:40:45.124333 rx_firspass[0][0][4] = 0
5033 18:40:45.124885 rx_lastpass[0][0][4] = 0
5034 18:40:45.127663 rx_firspass[0][0][5] = 0
5035 18:40:45.130822 rx_lastpass[0][0][5] = 0
5036 18:40:45.131231 rx_firspass[0][0][6] = 0
5037 18:40:45.134306 rx_lastpass[0][0][6] = 0
5038 18:40:45.137466 rx_firspass[0][0][7] = 0
5039 18:40:45.140808 rx_lastpass[0][0][7] = 0
5040 18:40:45.141181 rx_firspass[0][0][8] = 0
5041 18:40:45.144257 rx_lastpass[0][0][8] = 0
5042 18:40:45.147548 rx_firspass[0][0][9] = 0
5043 18:40:45.148024 rx_lastpass[0][0][9] = 0
5044 18:40:45.150738 rx_firspass[0][0][10] = 0
5045 18:40:45.153590 rx_lastpass[0][0][10] = 0
5046 18:40:45.153973 rx_firspass[0][0][11] = 0
5047 18:40:45.156913 rx_lastpass[0][0][11] = 0
5048 18:40:45.160287 rx_firspass[0][0][12] = 0
5049 18:40:45.163517 rx_lastpass[0][0][12] = 0
5050 18:40:45.163928 rx_firspass[0][0][13] = 0
5051 18:40:45.166993 rx_lastpass[0][0][13] = 0
5052 18:40:45.169998 rx_firspass[0][0][14] = 0
5053 18:40:45.173850 rx_lastpass[0][0][14] = 0
5054 18:40:45.174327 rx_firspass[0][0][15] = 0
5055 18:40:45.177100 rx_lastpass[0][0][15] = 0
5056 18:40:45.180195 rx_firspass[0][1][0] = 0
5057 18:40:45.180670 rx_lastpass[0][1][0] = 0
5058 18:40:45.183459 rx_firspass[0][1][1] = 0
5059 18:40:45.186608 rx_lastpass[0][1][1] = 0
5060 18:40:45.186982 rx_firspass[0][1][2] = 0
5061 18:40:45.189998 rx_lastpass[0][1][2] = 0
5062 18:40:45.193209 rx_firspass[0][1][3] = 0
5063 18:40:45.196397 rx_lastpass[0][1][3] = 0
5064 18:40:45.196790 rx_firspass[0][1][4] = 0
5065 18:40:45.199909 rx_lastpass[0][1][4] = 0
5066 18:40:45.202994 rx_firspass[0][1][5] = 0
5067 18:40:45.203372 rx_lastpass[0][1][5] = 0
5068 18:40:45.206124 rx_firspass[0][1][6] = 0
5069 18:40:45.209564 rx_lastpass[0][1][6] = 0
5070 18:40:45.210050 rx_firspass[0][1][7] = 0
5071 18:40:45.212911 rx_lastpass[0][1][7] = 0
5072 18:40:45.216055 rx_firspass[0][1][8] = 0
5073 18:40:45.219355 rx_lastpass[0][1][8] = 0
5074 18:40:45.219760 rx_firspass[0][1][9] = 0
5075 18:40:45.222458 rx_lastpass[0][1][9] = 0
5076 18:40:45.225972 rx_firspass[0][1][10] = 0
5077 18:40:45.226378 rx_lastpass[0][1][10] = 0
5078 18:40:45.229394 rx_firspass[0][1][11] = 0
5079 18:40:45.232231 rx_lastpass[0][1][11] = 0
5080 18:40:45.236076 rx_firspass[0][1][12] = 0
5081 18:40:45.236587 rx_lastpass[0][1][12] = 0
5082 18:40:45.239038 rx_firspass[0][1][13] = 0
5083 18:40:45.242158 rx_lastpass[0][1][13] = 0
5084 18:40:45.242564 rx_firspass[0][1][14] = 0
5085 18:40:45.245321 rx_lastpass[0][1][14] = 0
5086 18:40:45.248918 rx_firspass[0][1][15] = 0
5087 18:40:45.252153 rx_lastpass[0][1][15] = 0
5088 18:40:45.252560 rx_firspass[1][0][0] = 0
5089 18:40:45.255107 rx_lastpass[1][0][0] = 0
5090 18:40:45.258666 rx_firspass[1][0][1] = 0
5091 18:40:45.259071 rx_lastpass[1][0][1] = 0
5092 18:40:45.261976 rx_firspass[1][0][2] = 0
5093 18:40:45.265119 rx_lastpass[1][0][2] = 0
5094 18:40:45.268593 rx_firspass[1][0][3] = 0
5095 18:40:45.269100 rx_lastpass[1][0][3] = 0
5096 18:40:45.271841 rx_firspass[1][0][4] = 0
5097 18:40:45.275211 rx_lastpass[1][0][4] = 0
5098 18:40:45.275719 rx_firspass[1][0][5] = 0
5099 18:40:45.278195 rx_lastpass[1][0][5] = 0
5100 18:40:45.281361 rx_firspass[1][0][6] = 0
5101 18:40:45.281812 rx_lastpass[1][0][6] = 0
5102 18:40:45.284891 rx_firspass[1][0][7] = 0
5103 18:40:45.287957 rx_lastpass[1][0][7] = 0
5104 18:40:45.288451 rx_firspass[1][0][8] = 0
5105 18:40:45.291376 rx_lastpass[1][0][8] = 0
5106 18:40:45.294674 rx_firspass[1][0][9] = 0
5107 18:40:45.297948 rx_lastpass[1][0][9] = 0
5108 18:40:45.298355 rx_firspass[1][0][10] = 0
5109 18:40:45.301246 rx_lastpass[1][0][10] = 0
5110 18:40:45.304459 rx_firspass[1][0][11] = 0
5111 18:40:45.304863 rx_lastpass[1][0][11] = 0
5112 18:40:45.308080 rx_firspass[1][0][12] = 0
5113 18:40:45.310678 rx_lastpass[1][0][12] = 0
5114 18:40:45.314231 rx_firspass[1][0][13] = 0
5115 18:40:45.314637 rx_lastpass[1][0][13] = 0
5116 18:40:45.317479 rx_firspass[1][0][14] = 0
5117 18:40:45.320778 rx_lastpass[1][0][14] = 0
5118 18:40:45.324059 rx_firspass[1][0][15] = 0
5119 18:40:45.324561 rx_lastpass[1][0][15] = 0
5120 18:40:45.327307 rx_firspass[1][1][0] = 0
5121 18:40:45.330584 rx_lastpass[1][1][0] = 0
5122 18:40:45.330992 rx_firspass[1][1][1] = 0
5123 18:40:45.333701 rx_lastpass[1][1][1] = 0
5124 18:40:45.336832 rx_firspass[1][1][2] = 0
5125 18:40:45.340122 rx_lastpass[1][1][2] = 0
5126 18:40:45.340531 rx_firspass[1][1][3] = 0
5127 18:40:45.343487 rx_lastpass[1][1][3] = 0
5128 18:40:45.347136 rx_firspass[1][1][4] = 0
5129 18:40:45.347661 rx_lastpass[1][1][4] = 0
5130 18:40:45.349956 rx_firspass[1][1][5] = 0
5131 18:40:45.353362 rx_lastpass[1][1][5] = 0
5132 18:40:45.353800 rx_firspass[1][1][6] = 0
5133 18:40:45.356346 rx_lastpass[1][1][6] = 0
5134 18:40:45.359834 rx_firspass[1][1][7] = 0
5135 18:40:45.360261 rx_lastpass[1][1][7] = 0
5136 18:40:45.363247 rx_firspass[1][1][8] = 0
5137 18:40:45.366209 rx_lastpass[1][1][8] = 0
5138 18:40:45.369626 rx_firspass[1][1][9] = 0
5139 18:40:45.370036 rx_lastpass[1][1][9] = 0
5140 18:40:45.373047 rx_firspass[1][1][10] = 0
5141 18:40:45.376266 rx_lastpass[1][1][10] = 0
5142 18:40:45.376862 rx_firspass[1][1][11] = 0
5143 18:40:45.379412 rx_lastpass[1][1][11] = 0
5144 18:40:45.382859 rx_firspass[1][1][12] = 0
5145 18:40:45.386184 rx_lastpass[1][1][12] = 0
5146 18:40:45.386603 rx_firspass[1][1][13] = 0
5147 18:40:45.389272 rx_lastpass[1][1][13] = 0
5148 18:40:45.392531 rx_firspass[1][1][14] = 0
5149 18:40:45.395919 rx_lastpass[1][1][14] = 0
5150 18:40:45.396467 rx_firspass[1][1][15] = 0
5151 18:40:45.399204 rx_lastpass[1][1][15] = 0
5152 18:40:45.402266 dump params clk_delay
5153 18:40:45.402637 clk_delay[0] = 0
5154 18:40:45.405751 clk_delay[1] = 0
5155 18:40:45.406157 dump params dqs_delay
5156 18:40:45.408875 dqs_delay[0][0] = 0
5157 18:40:45.409245 dqs_delay[0][1] = 0
5158 18:40:45.412080 dqs_delay[1][0] = 0
5159 18:40:45.412451 dqs_delay[1][1] = 0
5160 18:40:45.415378 dump params delay_cell_unit = 744
5161 18:40:45.418709 mt_set_emi_preloader end
5162 18:40:45.422151 [mt_mem_init] dram size: 0x100000000, rank number: 2
5163 18:40:45.428412 [complex_mem_test] start addr:0x40000000, len:20480
5164 18:40:45.464487 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5165 18:40:45.471374 [complex_mem_test] start addr:0x80000000, len:20480
5166 18:40:45.506647 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5167 18:40:45.513403 [complex_mem_test] start addr:0xc0000000, len:20480
5168 18:40:45.549231 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5169 18:40:45.555668 [complex_mem_test] start addr:0x56000000, len:8192
5170 18:40:45.572521 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5171 18:40:45.576006 ddr_geometry:1
5172 18:40:45.578925 [complex_mem_test] start addr:0x80000000, len:8192
5173 18:40:45.596378 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5174 18:40:45.599785 dram_init: dram init end (result: 0)
5175 18:40:45.606017 Successfully loaded DRAM blobs and ran DRAM calibration
5176 18:40:45.615942 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5177 18:40:45.616452 CBMEM:
5178 18:40:45.619094 IMD: root @ 00000000fffff000 254 entries.
5179 18:40:45.622416 IMD: root @ 00000000ffffec00 62 entries.
5180 18:40:45.629343 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5181 18:40:45.635757 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5182 18:40:45.639165 in-header: 03 a1 00 00 08 00 00 00
5183 18:40:45.642232 in-data: 84 60 60 10 00 00 00 00
5184 18:40:45.645498 Chrome EC: clear events_b mask to 0x0000000020004000
5185 18:40:45.652245 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5186 18:40:45.655805 in-header: 03 fd 00 00 00 00 00 00
5187 18:40:45.659046 in-data:
5188 18:40:45.662211 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5189 18:40:45.665558 CBFS @ 21000 size 3d4000
5190 18:40:45.668949 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5191 18:40:45.672662 CBFS: Locating 'fallback/ramstage'
5192 18:40:45.675834 CBFS: Found @ offset 10d40 size d563
5193 18:40:45.698379 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5194 18:40:45.710153 Accumulated console time in romstage 13444 ms
5195 18:40:45.710664
5196 18:40:45.710985
5197 18:40:45.720229 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5198 18:40:45.723185 ARM64: Exception handlers installed.
5199 18:40:45.723639 ARM64: Testing exception
5200 18:40:45.726864 ARM64: Done test exception
5201 18:40:45.730165 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5202 18:40:45.733168 Manufacturer: ef
5203 18:40:45.739741 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5204 18:40:45.742851 WARNING: RO_VPD is uninitialized or empty.
5205 18:40:45.746025 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5206 18:40:45.749555 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5207 18:40:45.760205 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5208 18:40:45.763131 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5209 18:40:45.769833 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5210 18:40:45.770244 Enumerating buses...
5211 18:40:45.776377 Show all devs... Before device enumeration.
5212 18:40:45.776885 Root Device: enabled 1
5213 18:40:45.779618 CPU_CLUSTER: 0: enabled 1
5214 18:40:45.782885 CPU: 00: enabled 1
5215 18:40:45.783519 Compare with tree...
5216 18:40:45.786025 Root Device: enabled 1
5217 18:40:45.786432 CPU_CLUSTER: 0: enabled 1
5218 18:40:45.789353 CPU: 00: enabled 1
5219 18:40:45.792759 Root Device scanning...
5220 18:40:45.796087 root_dev_scan_bus for Root Device
5221 18:40:45.796594 CPU_CLUSTER: 0 enabled
5222 18:40:45.799499 root_dev_scan_bus for Root Device done
5223 18:40:45.805883 scan_bus: scanning of bus Root Device took 10690 usecs
5224 18:40:45.806299 done
5225 18:40:45.809219 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5226 18:40:45.812203 Allocating resources...
5227 18:40:45.815568 Reading resources...
5228 18:40:45.818959 Root Device read_resources bus 0 link: 0
5229 18:40:45.822385 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5230 18:40:45.825528 CPU: 00 missing read_resources
5231 18:40:45.829069 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5232 18:40:45.831990 Root Device read_resources bus 0 link: 0 done
5233 18:40:45.835460 Done reading resources.
5234 18:40:45.842128 Show resources in subtree (Root Device)...After reading.
5235 18:40:45.845188 Root Device child on link 0 CPU_CLUSTER: 0
5236 18:40:45.848788 CPU_CLUSTER: 0 child on link 0 CPU: 00
5237 18:40:45.858088 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5238 18:40:45.858609 CPU: 00
5239 18:40:45.858935 Setting resources...
5240 18:40:45.864385 Root Device assign_resources, bus 0 link: 0
5241 18:40:45.867848 CPU_CLUSTER: 0 missing set_resources
5242 18:40:45.871394 Root Device assign_resources, bus 0 link: 0
5243 18:40:45.871908 Done setting resources.
5244 18:40:45.877598 Show resources in subtree (Root Device)...After assigning values.
5245 18:40:45.880903 Root Device child on link 0 CPU_CLUSTER: 0
5246 18:40:45.887484 CPU_CLUSTER: 0 child on link 0 CPU: 00
5247 18:40:45.893920 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5248 18:40:45.897162 CPU: 00
5249 18:40:45.897726 Done allocating resources.
5250 18:40:45.903598 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5251 18:40:45.904074 Enabling resources...
5252 18:40:45.907191 done.
5253 18:40:45.910603 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5254 18:40:45.913647 Initializing devices...
5255 18:40:45.914199 Root Device init ...
5256 18:40:45.916942 mainboard_init: Starting display init.
5257 18:40:45.920067 ADC[4]: Raw value=76192 ID=0
5258 18:40:45.942669 anx7625_power_on_init: Init interface.
5259 18:40:45.946126 anx7625_disable_pd_protocol: Disabled PD feature.
5260 18:40:45.952621 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5261 18:40:45.999519 anx7625_start_dp_work: Secure OCM version=00
5262 18:40:46.002496 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5263 18:40:46.020047 sp_tx_get_edid_block: EDID Block = 1
5264 18:40:46.137375 Extracted contents:
5265 18:40:46.140594 header: 00 ff ff ff ff ff ff 00
5266 18:40:46.143390 serial number: 06 af 5c 14 00 00 00 00 00 1a
5267 18:40:46.147271 version: 01 04
5268 18:40:46.149937 basic params: 95 1a 0e 78 02
5269 18:40:46.153687 chroma info: 99 85 95 55 56 92 28 22 50 54
5270 18:40:46.156617 established: 00 00 00
5271 18:40:46.163046 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5272 18:40:46.169574 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5273 18:40:46.175892 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5274 18:40:46.179446 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5275 18:40:46.186003 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5276 18:40:46.189079 extensions: 00
5277 18:40:46.189525 checksum: ae
5278 18:40:46.192842
5279 18:40:46.195993 Manufacturer: AUO Model 145c Serial Number 0
5280 18:40:46.196508 Made week 0 of 2016
5281 18:40:46.199277 EDID version: 1.4
5282 18:40:46.199788 Digital display
5283 18:40:46.202201 6 bits per primary color channel
5284 18:40:46.205666 DisplayPort interface
5285 18:40:46.208823 Maximum image size: 26 cm x 14 cm
5286 18:40:46.209230 Gamma: 220%
5287 18:40:46.212070 Check DPMS levels
5288 18:40:46.212473 Supported color formats: RGB 4:4:4
5289 18:40:46.218869 First detailed timing is preferred timing
5290 18:40:46.219385 Established timings supported:
5291 18:40:46.222043 Standard timings supported:
5292 18:40:46.225244 Detailed timings
5293 18:40:46.228500 Hex of detail: ce1d56ea50001a3030204600009010000018
5294 18:40:46.235130 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5295 18:40:46.238146 0556 0586 05a6 0640 hborder 0
5296 18:40:46.241694 0300 0304 030a 031a vborder 0
5297 18:40:46.245096 -hsync -vsync
5298 18:40:46.245661 Did detailed timing
5299 18:40:46.251408 Hex of detail: 0000000f0000000000000000000000000020
5300 18:40:46.254513 Manufacturer-specified data, tag 15
5301 18:40:46.257641 Hex of detail: 000000fe0041554f0a202020202020202020
5302 18:40:46.261146 ASCII string: AUO
5303 18:40:46.264367 Hex of detail: 000000fe004231313658414230312e34200a
5304 18:40:46.267490 ASCII string: B116XAB01.4
5305 18:40:46.267899 Checksum
5306 18:40:46.271026 Checksum: 0xae (valid)
5307 18:40:46.274107 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5308 18:40:46.277360 DSI data_rate: 457800000 bps
5309 18:40:46.284137 anx7625_parse_edid: set default k value to 0x3d for panel
5310 18:40:46.287220 anx7625_parse_edid: pixelclock(76300).
5311 18:40:46.290580 hactive(1366), hsync(32), hfp(48), hbp(154)
5312 18:40:46.294022 vactive(768), vsync(6), vfp(4), vbp(16)
5313 18:40:46.297117 anx7625_dsi_config: config dsi.
5314 18:40:46.305585 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5315 18:40:46.326211 anx7625_dsi_config: success to config DSI
5316 18:40:46.329776 anx7625_dp_start: MIPI phy setup OK.
5317 18:40:46.332680 [SSUSB] Setting up USB HOST controller...
5318 18:40:46.336245 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5319 18:40:46.339499 [SSUSB] phy power-on done.
5320 18:40:46.343293 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5321 18:40:46.346360 in-header: 03 fc 01 00 00 00 00 00
5322 18:40:46.346774 in-data:
5323 18:40:46.352873 handle_proto3_response: EC response with error code: 1
5324 18:40:46.353386 SPM: pcm index = 1
5325 18:40:46.359620 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5326 18:40:46.360139 CBFS @ 21000 size 3d4000
5327 18:40:46.365814 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5328 18:40:46.368989 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5329 18:40:46.372459 CBFS: Found @ offset 1e7c0 size 1026
5330 18:40:46.379152 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps
5331 18:40:46.382240 SPM: binary array size = 2988
5332 18:40:46.385651 SPM: version = pcm_allinone_v1.17.2_20180829
5333 18:40:46.388738 SPM binary loaded in 32 msecs
5334 18:40:46.397653 spm_kick_im_to_fetch: ptr = 000000004021eec2
5335 18:40:46.400763 spm_kick_im_to_fetch: len = 2988
5336 18:40:46.401296 SPM: spm_kick_pcm_to_run
5337 18:40:46.404115 SPM: spm_kick_pcm_to_run done
5338 18:40:46.407082 SPM: spm_init done in 52 msecs
5339 18:40:46.410643 Root Device init finished in 494993 usecs
5340 18:40:46.413971 CPU_CLUSTER: 0 init ...
5341 18:40:46.423658 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5342 18:40:46.426730 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5343 18:40:46.430224 CBFS @ 21000 size 3d4000
5344 18:40:46.433098 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5345 18:40:46.436941 CBFS: Locating 'sspm.bin'
5346 18:40:46.439968 CBFS: Found @ offset 208c0 size 41cb
5347 18:40:46.450593 read SPI 0x418f8 0x41cb: 5142 us, 3275 KB/s, 26.200 Mbps
5348 18:40:46.458288 CPU_CLUSTER: 0 init finished in 42800 usecs
5349 18:40:46.458730 Devices initialized
5350 18:40:46.461590 Show all devs... After init.
5351 18:40:46.464877 Root Device: enabled 1
5352 18:40:46.465305 CPU_CLUSTER: 0: enabled 1
5353 18:40:46.468181 CPU: 00: enabled 1
5354 18:40:46.471719 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5355 18:40:46.478352 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5356 18:40:46.481581 ELOG: NV offset 0x558000 size 0x1000
5357 18:40:46.484631 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5358 18:40:46.491272 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5359 18:40:46.497954 ELOG: Event(17) added with size 13 at 2024-06-11 18:40:46 UTC
5360 18:40:46.500656 out: cmd=0x121: 03 db 21 01 00 00 00 00
5361 18:40:46.504300 in-header: 03 17 00 00 2c 00 00 00
5362 18:40:46.517234 in-data: 7a 4a 00 00 00 00 00 00 02 10 00 00 06 80 00 00 17 c9 13 00 06 80 00 00 8e b1 14 00 06 80 00 00 be 3e 01 00 06 80 00 00 2f 58 02 00
5363 18:40:46.520652 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5364 18:40:46.523552 in-header: 03 19 00 00 08 00 00 00
5365 18:40:46.526906 in-data: a2 e0 47 00 13 00 00 00
5366 18:40:46.530468 Chrome EC: UHEPI supported
5367 18:40:46.536911 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5368 18:40:46.540271 in-header: 03 e1 00 00 08 00 00 00
5369 18:40:46.543316 in-data: 84 20 60 10 00 00 00 00
5370 18:40:46.546680 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5371 18:40:46.553472 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5372 18:40:46.556412 in-header: 03 e1 00 00 08 00 00 00
5373 18:40:46.559764 in-data: 84 20 60 10 00 00 00 00
5374 18:40:46.566471 ELOG: Event(A1) added with size 10 at 2024-06-11 18:40:46 UTC
5375 18:40:46.572972 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5376 18:40:46.575972 ELOG: Event(A0) added with size 9 at 2024-06-11 18:40:46 UTC
5377 18:40:46.582663 elog_add_boot_reason: Logged dev mode boot
5378 18:40:46.583074 Finalize devices...
5379 18:40:46.586002 Devices finalized
5380 18:40:46.589647 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5381 18:40:46.592737 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5382 18:40:46.599532 ELOG: Event(91) added with size 10 at 2024-06-11 18:40:46 UTC
5383 18:40:46.602728 Writing coreboot table at 0xffeda000
5384 18:40:46.605570 0. 0000000000114000-000000000011efff: RAMSTAGE
5385 18:40:46.612377 1. 0000000040000000-000000004023cfff: RAMSTAGE
5386 18:40:46.615564 2. 000000004023d000-00000000545fffff: RAM
5387 18:40:46.618681 3. 0000000054600000-000000005465ffff: BL31
5388 18:40:46.621888 4. 0000000054660000-00000000ffed9fff: RAM
5389 18:40:46.628516 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5390 18:40:46.631683 6. 0000000100000000-000000013fffffff: RAM
5391 18:40:46.635087 Passing 5 GPIOs to payload:
5392 18:40:46.638386 NAME | PORT | POLARITY | VALUE
5393 18:40:46.645022 write protect | 0x00000096 | low | high
5394 18:40:46.648058 EC in RW | 0x000000b1 | high | undefined
5395 18:40:46.651138 EC interrupt | 0x00000097 | low | undefined
5396 18:40:46.657971 TPM interrupt | 0x00000099 | high | undefined
5397 18:40:46.661025 speaker enable | 0x000000af | high | undefined
5398 18:40:46.664281 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5399 18:40:46.667632 in-header: 03 f7 00 00 02 00 00 00
5400 18:40:46.670666 in-data: 04 00
5401 18:40:46.671068 Board ID: 4
5402 18:40:46.674189 ADC[3]: Raw value=215404 ID=1
5403 18:40:46.674593 RAM code: 1
5404 18:40:46.677842 SKU ID: 16
5405 18:40:46.680864 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5406 18:40:46.683957 CBFS @ 21000 size 3d4000
5407 18:40:46.687082 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5408 18:40:46.693538 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum f82e
5409 18:40:46.697466 coreboot table: 940 bytes.
5410 18:40:46.700397 IMD ROOT 0. 00000000fffff000 00001000
5411 18:40:46.703650 IMD SMALL 1. 00000000ffffe000 00001000
5412 18:40:46.706610 CONSOLE 2. 00000000fffde000 00020000
5413 18:40:46.710314 FMAP 3. 00000000fffdd000 0000047c
5414 18:40:46.716822 TIME STAMP 4. 00000000fffdc000 00000910
5415 18:40:46.719740 RAMOOPS 5. 00000000ffedc000 00100000
5416 18:40:46.723547 COREBOOT 6. 00000000ffeda000 00002000
5417 18:40:46.724070 IMD small region:
5418 18:40:46.726614 IMD ROOT 0. 00000000ffffec00 00000400
5419 18:40:46.733241 VBOOT WORK 1. 00000000ffffeb00 00000100
5420 18:40:46.736654 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5421 18:40:46.739585 VPD 3. 00000000ffffea60 0000006c
5422 18:40:46.743197 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5423 18:40:46.749571 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5424 18:40:46.752871 in-header: 03 e1 00 00 08 00 00 00
5425 18:40:46.756187 in-data: 84 20 60 10 00 00 00 00
5426 18:40:46.762747 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5427 18:40:46.763271 CBFS @ 21000 size 3d4000
5428 18:40:46.769347 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5429 18:40:46.772437 CBFS: Locating 'fallback/payload'
5430 18:40:46.780359 CBFS: Found @ offset dc040 size 439a0
5431 18:40:46.868163 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5432 18:40:46.871351 Checking segment from ROM address 0x0000000040003a00
5433 18:40:46.877898 Checking segment from ROM address 0x0000000040003a1c
5434 18:40:46.881332 Loading segment from ROM address 0x0000000040003a00
5435 18:40:46.884373 code (compression=0)
5436 18:40:46.894472 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5437 18:40:46.900940 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5438 18:40:46.904165 it's not compressed!
5439 18:40:46.907702 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5440 18:40:46.913996 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5441 18:40:46.922674 Loading segment from ROM address 0x0000000040003a1c
5442 18:40:46.925904 Entry Point 0x0000000080000000
5443 18:40:46.926452 Loaded segments
5444 18:40:46.932334 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5445 18:40:46.935656 Jumping to boot code at 0000000080000000(00000000ffeda000)
5446 18:40:46.945007 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5447 18:40:46.951684 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5448 18:40:46.952201 CBFS @ 21000 size 3d4000
5449 18:40:46.958103 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5450 18:40:46.961554 CBFS: Locating 'fallback/bl31'
5451 18:40:46.964677 CBFS: Found @ offset 36dc0 size 5820
5452 18:40:46.976751 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5453 18:40:46.979790 Checking segment from ROM address 0x0000000040003a00
5454 18:40:46.986102 Checking segment from ROM address 0x0000000040003a1c
5455 18:40:46.989497 Loading segment from ROM address 0x0000000040003a00
5456 18:40:46.992968 code (compression=1)
5457 18:40:47.002462 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5458 18:40:47.009164 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5459 18:40:47.009711 using LZMA
5460 18:40:47.018591 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5461 18:40:47.025048 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5462 18:40:47.028488 Loading segment from ROM address 0x0000000040003a1c
5463 18:40:47.031724 Entry Point 0x0000000054601000
5464 18:40:47.032278 Loaded segments
5465 18:40:47.034496 NOTICE: MT8183 bl31_setup
5466 18:40:47.042204 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5467 18:40:47.045420 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5468 18:40:47.048468 INFO: [DEVAPC] dump DEVAPC registers:
5469 18:40:47.058594 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5470 18:40:47.064859 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5471 18:40:47.074617 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5472 18:40:47.081238 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5473 18:40:47.091403 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5474 18:40:47.097724 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5475 18:40:47.107472 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5476 18:40:47.114058 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5477 18:40:47.123683 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5478 18:40:47.130447 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5479 18:40:47.140244 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5480 18:40:47.146634 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5481 18:40:47.156679 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5482 18:40:47.163408 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5483 18:40:47.169820 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5484 18:40:47.179482 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5485 18:40:47.185859 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5486 18:40:47.192613 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5487 18:40:47.199166 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5488 18:40:47.206100 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5489 18:40:47.215403 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5490 18:40:47.222371 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5491 18:40:47.225698 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5492 18:40:47.228923 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5493 18:40:47.232120 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5494 18:40:47.235209 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5495 18:40:47.238440 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5496 18:40:47.245042 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5497 18:40:47.248564 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5498 18:40:47.251813 WARNING: region 0:
5499 18:40:47.254652 WARNING: apc:0x168, sa:0x0, ea:0xfff
5500 18:40:47.257985 WARNING: region 1:
5501 18:40:47.261518 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5502 18:40:47.262045 WARNING: region 2:
5503 18:40:47.264601 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5504 18:40:47.268175 WARNING: region 3:
5505 18:40:47.271457 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5506 18:40:47.271878 WARNING: region 4:
5507 18:40:47.277693 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5508 18:40:47.278113 WARNING: region 5:
5509 18:40:47.281091 WARNING: apc:0x0, sa:0x0, ea:0x0
5510 18:40:47.284259 WARNING: region 6:
5511 18:40:47.287630 WARNING: apc:0x0, sa:0x0, ea:0x0
5512 18:40:47.288047 WARNING: region 7:
5513 18:40:47.290888 WARNING: apc:0x0, sa:0x0, ea:0x0
5514 18:40:47.297328 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5515 18:40:47.300941 INFO: SPM: enable SPMC mode
5516 18:40:47.304323 NOTICE: spm_boot_init() start
5517 18:40:47.307386 NOTICE: spm_boot_init() end
5518 18:40:47.310459 INFO: BL31: Initializing runtime services
5519 18:40:47.317101 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5520 18:40:47.320446 INFO: BL31: Preparing for EL3 exit to normal world
5521 18:40:47.323477 INFO: Entry point address = 0x80000000
5522 18:40:47.327263 INFO: SPSR = 0x8
5523 18:40:47.348806
5524 18:40:47.349319
5525 18:40:47.349695
5526 18:40:47.351306 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5527 18:40:47.351949 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
5528 18:40:47.352364 Setting prompt string to ['jacuzzi:']
5529 18:40:47.352760 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:26)
5530 18:40:47.353405 Starting depthcharge on Juniper...
5531 18:40:47.353801
5532 18:40:47.354944 vboot_handoff: creating legacy vboot_handoff structure
5533 18:40:47.355358
5534 18:40:47.358440 ec_init(0): CrosEC protocol v3 supported (544, 544)
5535 18:40:47.361409
5536 18:40:47.361871 Wipe memory regions:
5537 18:40:47.362213
5538 18:40:47.364674 [0x00000040000000, 0x00000054600000)
5539 18:40:47.408109
5540 18:40:47.408616 [0x00000054660000, 0x00000080000000)
5541 18:40:47.499577
5542 18:40:47.500139 [0x000000811994a0, 0x000000ffeda000)
5543 18:40:47.760171
5544 18:40:47.760673 [0x00000100000000, 0x00000140000000)
5545 18:40:47.893329
5546 18:40:47.896440 Initializing XHCI USB controller at 0x11200000.
5547 18:40:47.920063
5548 18:40:47.922998 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5549 18:40:47.923514
5550 18:40:47.923940
5551 18:40:47.924860 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5553 18:40:48.026395 jacuzzi: tftpboot 192.168.201.1 14291499/tftp-deploy-p8e8r9bv/kernel/image.itb 14291499/tftp-deploy-p8e8r9bv/kernel/cmdline
5554 18:40:48.026989 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5555 18:40:48.027414 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
5556 18:40:48.032110 tftpboot 192.168.201.1 14291499/tftp-deploy-p8e8r9bv/kernel/image.itp-deploy-p8e8r9bv/kernel/cmdline
5557 18:40:48.032630
5558 18:40:48.032960 Waiting for link
5559 18:40:48.433913
5560 18:40:48.434424 R8152: Initializing
5561 18:40:48.434822
5562 18:40:48.437015 Version 9 (ocp_data = 6010)
5563 18:40:48.437644
5564 18:40:48.440373 R8152: Done initializing
5565 18:40:48.440945
5566 18:40:48.441279 Adding net device
5567 18:40:48.826073
5568 18:40:48.826583 done.
5569 18:40:48.826934
5570 18:40:48.827244 MAC: 00:e0:4c:78:85:cb
5571 18:40:48.827541
5572 18:40:48.829163 Sending DHCP discover... done.
5573 18:40:48.829731
5574 18:40:48.832120 Waiting for reply... done.
5575 18:40:48.832538
5576 18:40:48.835319 Sending DHCP request... done.
5577 18:40:48.835822
5578 18:40:48.841667 Waiting for reply... done.
5579 18:40:48.842170
5580 18:40:48.842500 My ip is 192.168.201.22
5581 18:40:48.842805
5582 18:40:48.845121 The DHCP server ip is 192.168.201.1
5583 18:40:48.845675
5584 18:40:48.851411 TFTP server IP predefined by user: 192.168.201.1
5585 18:40:48.851933
5586 18:40:48.858112 Bootfile predefined by user: 14291499/tftp-deploy-p8e8r9bv/kernel/image.itb
5587 18:40:48.858620
5588 18:40:48.861167 Sending tftp read request... done.
5589 18:40:48.861718
5590 18:40:48.867594 Waiting for the transfer...
5591 18:40:48.868103
5592 18:40:49.253098 00000000 ################################################################
5593 18:40:49.253702
5594 18:40:49.635743 00080000 ################################################################
5595 18:40:49.636220
5596 18:40:50.012356 00100000 ################################################################
5597 18:40:50.012817
5598 18:40:50.402153 00180000 ################################################################
5599 18:40:50.402651
5600 18:40:50.676958 00200000 ################################################################
5601 18:40:50.677113
5602 18:40:50.941573 00280000 ################################################################
5603 18:40:50.941760
5604 18:40:51.326147 00300000 ################################################################
5605 18:40:51.326704
5606 18:40:51.726931 00380000 ################################################################
5607 18:40:51.727485
5608 18:40:52.119450 00400000 ################################################################
5609 18:40:52.119955
5610 18:40:52.530374 00480000 ################################################################
5611 18:40:52.530942
5612 18:40:52.922130 00500000 ################################################################
5613 18:40:52.922628
5614 18:40:53.301342 00580000 ################################################################
5615 18:40:53.301876
5616 18:40:53.712233 00600000 ################################################################
5617 18:40:53.712727
5618 18:40:54.115743 00680000 ################################################################
5619 18:40:54.116248
5620 18:40:54.509197 00700000 ################################################################
5621 18:40:54.509734
5622 18:40:54.915094 00780000 ################################################################
5623 18:40:54.915608
5624 18:40:55.310156 00800000 ################################################################
5625 18:40:55.310701
5626 18:40:55.709651 00880000 ################################################################
5627 18:40:55.710363
5628 18:40:56.025625 00900000 ################################################################
5629 18:40:56.025773
5630 18:40:56.411283 00980000 ################################################################
5631 18:40:56.411800
5632 18:40:56.832617 00a00000 ################################################################
5633 18:40:56.833122
5634 18:40:57.257592 00a80000 ################################################################
5635 18:40:57.258097
5636 18:40:57.662601 00b00000 ################################################################
5637 18:40:57.663093
5638 18:40:58.057127 00b80000 ################################################################
5639 18:40:58.057735
5640 18:40:58.444900 00c00000 ################################################################
5641 18:40:58.445623
5642 18:40:58.875977 00c80000 ################################################################
5643 18:40:58.876490
5644 18:40:59.289615 00d00000 ################################################################
5645 18:40:59.290140
5646 18:40:59.643225 00d80000 ################################################################
5647 18:40:59.643376
5648 18:40:59.945397 00e00000 ################################################################
5649 18:40:59.945557
5650 18:41:00.252575 00e80000 ################################################################
5651 18:41:00.252721
5652 18:41:00.671273 00f00000 ################################################################
5653 18:41:00.671866
5654 18:41:00.986492 00f80000 ################################################################
5655 18:41:00.986647
5656 18:41:01.279857 01000000 ################################################################
5657 18:41:01.280086
5658 18:41:01.678789 01080000 ################################################################
5659 18:41:01.679334
5660 18:41:02.076317 01100000 ################################################################
5661 18:41:02.076853
5662 18:41:02.460710 01180000 ################################################################
5663 18:41:02.461252
5664 18:41:02.861936 01200000 ################################################################
5665 18:41:02.862470
5666 18:41:03.253204 01280000 ################################################################
5667 18:41:03.253738
5668 18:41:03.617765 01300000 ################################################################
5669 18:41:03.617923
5670 18:41:03.909947 01380000 ################################################################
5671 18:41:03.910135
5672 18:41:04.213377 01400000 ################################################################
5673 18:41:04.213535
5674 18:41:04.512729 01480000 ################################################################
5675 18:41:04.512877
5676 18:41:04.797696 01500000 ################################################################
5677 18:41:04.797870
5678 18:41:05.151874 01580000 ################################################################
5679 18:41:05.152037
5680 18:41:05.561283 01600000 ################################################################
5681 18:41:05.561866
5682 18:41:05.957976 01680000 ################################################################
5683 18:41:05.958485
5684 18:41:06.378015 01700000 ################################################################
5685 18:41:06.378538
5686 18:41:06.808111 01780000 ################################################################
5687 18:41:06.808675
5688 18:41:07.218370 01800000 ################################################################
5689 18:41:07.218896
5690 18:41:07.620686 01880000 ################################################################
5691 18:41:07.621207
5692 18:41:08.021983 01900000 ################################################################
5693 18:41:08.022495
5694 18:41:08.426425 01980000 ################################################################
5695 18:41:08.427133
5696 18:41:08.712323 01a00000 ################################################################
5697 18:41:08.712479
5698 18:41:09.010059 01a80000 ################################################################
5699 18:41:09.010215
5700 18:41:09.317644 01b00000 ################################################################
5701 18:41:09.317795
5702 18:41:09.617111 01b80000 ################################################################
5703 18:41:09.617272
5704 18:41:09.907440 01c00000 ################################################################
5705 18:41:09.907595
5706 18:41:10.199808 01c80000 ################################################################
5707 18:41:10.199962
5708 18:41:10.489750 01d00000 ################################################################
5709 18:41:10.489900
5710 18:41:10.790451 01d80000 ################################################################
5711 18:41:10.790600
5712 18:41:11.045268 01e00000 ######################################################### done.
5713 18:41:11.045417
5714 18:41:11.048535 The bootfile was 31919150 bytes long.
5715 18:41:11.048634
5716 18:41:11.051781 Sending tftp read request... done.
5717 18:41:11.051887
5718 18:41:11.055123 Waiting for the transfer...
5719 18:41:11.055234
5720 18:41:11.055317 00000000 # done.
5721 18:41:11.055397
5722 18:41:11.064812 Command line loaded dynamically from TFTP file: 14291499/tftp-deploy-p8e8r9bv/kernel/cmdline
5723 18:41:11.065009
5724 18:41:11.091197 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5725 18:41:11.091648
5726 18:41:11.091925 Loading FIT.
5727 18:41:11.092181
5728 18:41:11.094272 Image ramdisk-1 has 18734302 bytes.
5729 18:41:11.094623
5730 18:41:11.097641 Image fdt-1 has 57695 bytes.
5731 18:41:11.098051
5732 18:41:11.100858 Image kernel-1 has 13125101 bytes.
5733 18:41:11.101271
5734 18:41:11.110913 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5735 18:41:11.111332
5736 18:41:11.120545 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5737 18:41:11.120959
5738 18:41:11.127247 Choosing best match conf-1 for compat google,juniper-sku16.
5739 18:41:11.130761
5740 18:41:11.135104 Connected to device vid:did:rid of 1ae0:0028:00
5741 18:41:11.142387
5742 18:41:11.145595 tpm_get_response: command 0x17b, return code 0x0
5743 18:41:11.146031
5744 18:41:11.148728 tpm_cleanup: add release locality here.
5745 18:41:11.149161
5746 18:41:11.152153 Shutting down all USB controllers.
5747 18:41:11.152584
5748 18:41:11.155500 Removing current net device
5749 18:41:11.155932
5750 18:41:11.158665 Exiting depthcharge with code 4 at timestamp: 40839555
5751 18:41:11.159098
5752 18:41:11.165036 LZMA decompressing kernel-1 to 0x80193568
5753 18:41:11.165556
5754 18:41:11.168431 LZMA decompressing kernel-1 to 0x40000000
5755 18:41:13.033659
5756 18:41:13.034194 jumping to kernel
5757 18:41:13.036755 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
5758 18:41:13.037461 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
5759 18:41:13.037998 Setting prompt string to ['Linux version [0-9]']
5760 18:41:13.038533 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5761 18:41:13.039085 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5762 18:41:13.108532
5763 18:41:13.112069 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5764 18:41:13.115655 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
5765 18:41:13.116189 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5766 18:41:13.116616 Setting prompt string to []
5767 18:41:13.117109 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5768 18:41:13.117605 Using line separator: #'\n'#
5769 18:41:13.117985 No login prompt set.
5770 18:41:13.118403 Parsing kernel messages
5771 18:41:13.118781 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5772 18:41:13.119407 [login-action] Waiting for messages, (timeout 00:04:00)
5773 18:41:13.119821 Waiting using forced prompt support (timeout 00:02:00)
5774 18:41:13.134998 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
5775 18:41:13.137865 [ 0.000000] random: crng init done
5776 18:41:13.144775 [ 0.000000] Machine model: Google juniper sku16 board
5777 18:41:13.148101 [ 0.000000] efi: UEFI not found.
5778 18:41:13.154660 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5779 18:41:13.164663 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5780 18:41:13.170680 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5781 18:41:13.174094 [ 0.000000] printk: bootconsole [mtk8250] enabled
5782 18:41:13.183591 [ 0.000000] NUMA: No NUMA configuration found
5783 18:41:13.189620 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5784 18:41:13.196495 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5785 18:41:13.200127 [ 0.000000] Zone ranges:
5786 18:41:13.203237 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5787 18:41:13.206233 [ 0.000000] DMA32 empty
5788 18:41:13.212968 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5789 18:41:13.216269 [ 0.000000] Movable zone start for each node
5790 18:41:13.219838 [ 0.000000] Early memory node ranges
5791 18:41:13.226046 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5792 18:41:13.232602 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5793 18:41:13.238880 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5794 18:41:13.245523 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5795 18:41:13.252272 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5796 18:41:13.258936 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5797 18:41:13.276067 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5798 18:41:13.282601 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5799 18:41:13.289127 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5800 18:41:13.292357 [ 0.000000] psci: probing for conduit method from DT.
5801 18:41:13.298789 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5802 18:41:13.302253 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5803 18:41:13.308462 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5804 18:41:13.311878 [ 0.000000] psci: SMC Calling Convention v1.1
5805 18:41:13.318778 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5806 18:41:13.321618 [ 0.000000] Detected VIPT I-cache on CPU0
5807 18:41:13.328880 [ 0.000000] CPU features: detected: GIC system register CPU interface
5808 18:41:13.335109 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5809 18:41:13.341544 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5810 18:41:13.347956 [ 0.000000] CPU features: detected: ARM erratum 845719
5811 18:41:13.351310 [ 0.000000] alternatives: applying boot alternatives
5812 18:41:13.357720 [ 0.000000] Fallback order for Node 0: 0
5813 18:41:13.364572 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5814 18:41:13.367468 [ 0.000000] Policy zone: Normal
5815 18:41:13.394161 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5816 18:41:13.406651 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5817 18:41:13.413603 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5818 18:41:13.423002 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5819 18:41:13.429499 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5820 18:41:13.432889 <6>[ 0.000000] software IO TLB: area num 8.
5821 18:41:13.459138 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5822 18:41:13.517045 <6>[ 0.000000] Memory: 3896776K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261688K reserved, 32768K cma-reserved)
5823 18:41:13.523426 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5824 18:41:13.530245 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5825 18:41:13.533518 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5826 18:41:13.540075 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5827 18:41:13.546537 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5828 18:41:13.553107 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5829 18:41:13.559747 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5830 18:41:13.566008 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5831 18:41:13.572532 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5832 18:41:13.582644 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5833 18:41:13.588809 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5834 18:41:13.592239 <6>[ 0.000000] GICv3: 640 SPIs implemented
5835 18:41:13.595918 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5836 18:41:13.602152 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5837 18:41:13.605200 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5838 18:41:13.611731 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5839 18:41:13.625034 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5840 18:41:13.635104 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5841 18:41:13.644633 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5842 18:41:13.654113 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5843 18:41:13.667375 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5844 18:41:13.673750 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5845 18:41:13.680946 <6>[ 0.009472] Console: colour dummy device 80x25
5846 18:41:13.684409 <6>[ 0.014516] printk: console [tty1] enabled
5847 18:41:13.697506 <6>[ 0.018904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5848 18:41:13.700772 <6>[ 0.029368] pid_max: default: 32768 minimum: 301
5849 18:41:13.707209 <6>[ 0.034249] LSM: Security Framework initializing
5850 18:41:13.713745 <6>[ 0.039164] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5851 18:41:13.720187 <6>[ 0.046787] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5852 18:41:13.727538 <4>[ 0.055659] cacheinfo: Unable to detect cache hierarchy for CPU 0
5853 18:41:13.737378 <6>[ 0.062287] cblist_init_generic: Setting adjustable number of callback queues.
5854 18:41:13.743594 <6>[ 0.069732] cblist_init_generic: Setting shift to 3 and lim to 1.
5855 18:41:13.750287 <6>[ 0.076085] cblist_init_generic: Setting adjustable number of callback queues.
5856 18:41:13.757076 <6>[ 0.083530] cblist_init_generic: Setting shift to 3 and lim to 1.
5857 18:41:13.760182 <6>[ 0.089927] rcu: Hierarchical SRCU implementation.
5858 18:41:13.766762 <6>[ 0.094954] rcu: Max phase no-delay instances is 1000.
5859 18:41:13.774307 <6>[ 0.102879] EFI services will not be available.
5860 18:41:13.777861 <6>[ 0.107828] smp: Bringing up secondary CPUs ...
5861 18:41:13.788271 <6>[ 0.113113] Detected VIPT I-cache on CPU1
5862 18:41:13.794608 <4>[ 0.113160] cacheinfo: Unable to detect cache hierarchy for CPU 1
5863 18:41:13.801173 <6>[ 0.113168] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5864 18:41:13.808270 <6>[ 0.113198] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5865 18:41:13.811002 <6>[ 0.113683] Detected VIPT I-cache on CPU2
5866 18:41:13.817627 <4>[ 0.113717] cacheinfo: Unable to detect cache hierarchy for CPU 2
5867 18:41:13.824442 <6>[ 0.113722] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5868 18:41:13.830640 <6>[ 0.113734] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5869 18:41:13.837575 <6>[ 0.114179] Detected VIPT I-cache on CPU3
5870 18:41:13.843639 <4>[ 0.114209] cacheinfo: Unable to detect cache hierarchy for CPU 3
5871 18:41:13.850279 <6>[ 0.114214] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5872 18:41:13.856622 <6>[ 0.114225] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5873 18:41:13.859866 <6>[ 0.114800] CPU features: detected: Spectre-v2
5874 18:41:13.866269 <6>[ 0.114810] CPU features: detected: Spectre-BHB
5875 18:41:13.869653 <6>[ 0.114814] CPU features: detected: ARM erratum 858921
5876 18:41:13.876239 <6>[ 0.114819] Detected VIPT I-cache on CPU4
5877 18:41:13.882835 <4>[ 0.114867] cacheinfo: Unable to detect cache hierarchy for CPU 4
5878 18:41:13.889309 <6>[ 0.114875] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5879 18:41:13.896056 <6>[ 0.114883] arch_timer: Enabling local workaround for ARM erratum 858921
5880 18:41:13.902099 <6>[ 0.114894] arch_timer: CPU4: Trapping CNTVCT access
5881 18:41:13.908837 <6>[ 0.114901] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5882 18:41:13.912113 <6>[ 0.115386] Detected VIPT I-cache on CPU5
5883 18:41:13.918697 <4>[ 0.115426] cacheinfo: Unable to detect cache hierarchy for CPU 5
5884 18:41:13.925326 <6>[ 0.115431] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5885 18:41:13.932182 <6>[ 0.115438] arch_timer: Enabling local workaround for ARM erratum 858921
5886 18:41:13.938105 <6>[ 0.115444] arch_timer: CPU5: Trapping CNTVCT access
5887 18:41:13.944918 <6>[ 0.115449] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5888 18:41:13.947884 <6>[ 0.115886] Detected VIPT I-cache on CPU6
5889 18:41:13.954838 <4>[ 0.115933] cacheinfo: Unable to detect cache hierarchy for CPU 6
5890 18:41:13.961494 <6>[ 0.115939] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5891 18:41:13.967594 <6>[ 0.115946] arch_timer: Enabling local workaround for ARM erratum 858921
5892 18:41:13.973969 <6>[ 0.115952] arch_timer: CPU6: Trapping CNTVCT access
5893 18:41:13.981139 <6>[ 0.115957] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5894 18:41:13.984150 <6>[ 0.116486] Detected VIPT I-cache on CPU7
5895 18:41:13.990471 <4>[ 0.116530] cacheinfo: Unable to detect cache hierarchy for CPU 7
5896 18:41:14.000206 <6>[ 0.116536] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5897 18:41:14.006666 <6>[ 0.116543] arch_timer: Enabling local workaround for ARM erratum 858921
5898 18:41:14.009882 <6>[ 0.116549] arch_timer: CPU7: Trapping CNTVCT access
5899 18:41:14.016675 <6>[ 0.116555] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5900 18:41:14.022972 <6>[ 0.116614] smp: Brought up 1 node, 8 CPUs
5901 18:41:14.026302 <6>[ 0.355479] SMP: Total of 8 processors activated.
5902 18:41:14.032899 <6>[ 0.360415] CPU features: detected: 32-bit EL0 Support
5903 18:41:14.039730 <6>[ 0.365785] CPU features: detected: 32-bit EL1 Support
5904 18:41:14.042635 <6>[ 0.371150] CPU features: detected: CRC32 instructions
5905 18:41:14.049477 <6>[ 0.376577] CPU: All CPU(s) started at EL2
5906 18:41:14.052395 <6>[ 0.380915] alternatives: applying system-wide alternatives
5907 18:41:14.060612 <6>[ 0.389031] devtmpfs: initialized
5908 18:41:14.076252 <6>[ 0.397981] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5909 18:41:14.083039 <6>[ 0.407929] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5910 18:41:14.089153 <6>[ 0.415657] pinctrl core: initialized pinctrl subsystem
5911 18:41:14.092698 <6>[ 0.422760] DMI not present or invalid.
5912 18:41:14.099000 <6>[ 0.427131] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5913 18:41:14.109259 <6>[ 0.434039] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5914 18:41:14.115181 <6>[ 0.441564] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5915 18:41:14.125356 <6>[ 0.449814] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5916 18:41:14.131980 <6>[ 0.457991] audit: initializing netlink subsys (disabled)
5917 18:41:14.138336 <5>[ 0.463695] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5918 18:41:14.145066 <6>[ 0.464668] thermal_sys: Registered thermal governor 'step_wise'
5919 18:41:14.151395 <6>[ 0.471661] thermal_sys: Registered thermal governor 'power_allocator'
5920 18:41:14.154876 <6>[ 0.477957] cpuidle: using governor menu
5921 18:41:14.161172 <6>[ 0.488920] NET: Registered PF_QIPCRTR protocol family
5922 18:41:14.167826 <6>[ 0.494415] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5923 18:41:14.174037 <6>[ 0.501510] ASID allocator initialised with 32768 entries
5924 18:41:14.181005 <6>[ 0.508282] Serial: AMBA PL011 UART driver
5925 18:41:14.190208 <4>[ 0.518695] Trying to register duplicate clock ID: 113
5926 18:41:14.249951 <6>[ 0.574861] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5927 18:41:14.263930 <6>[ 0.589204] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5928 18:41:14.267505 <6>[ 0.598953] KASLR enabled
5929 18:41:14.282159 <6>[ 0.606963] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5930 18:41:14.288500 <6>[ 0.613966] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5931 18:41:14.295418 <6>[ 0.620443] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5932 18:41:14.301619 <6>[ 0.627434] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5933 18:41:14.308062 <6>[ 0.633909] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5934 18:41:14.314658 <6>[ 0.640898] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5935 18:41:14.321375 <6>[ 0.647372] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5936 18:41:14.327899 <6>[ 0.654361] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5937 18:41:14.333924 <6>[ 0.661923] ACPI: Interpreter disabled.
5938 18:41:14.341967 <6>[ 0.669910] iommu: Default domain type: Translated
5939 18:41:14.348308 <6>[ 0.675016] iommu: DMA domain TLB invalidation policy: strict mode
5940 18:41:14.351383 <5>[ 0.681645] SCSI subsystem initialized
5941 18:41:14.358015 <6>[ 0.686061] usbcore: registered new interface driver usbfs
5942 18:41:14.364453 <6>[ 0.691788] usbcore: registered new interface driver hub
5943 18:41:14.371140 <6>[ 0.697329] usbcore: registered new device driver usb
5944 18:41:14.374148 <6>[ 0.703634] pps_core: LinuxPPS API ver. 1 registered
5945 18:41:14.384154 <6>[ 0.708819] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
5946 18:41:14.390416 <6>[ 0.718143] PTP clock support registered
5947 18:41:14.393651 <6>[ 0.722396] EDAC MC: Ver: 3.0.0
5948 18:41:14.397121 <6>[ 0.728038] FPGA manager framework
5949 18:41:14.403540 <6>[ 0.731720] Advanced Linux Sound Architecture Driver Initialized.
5950 18:41:14.406890 <6>[ 0.738472] vgaarb: loaded
5951 18:41:14.413614 <6>[ 0.741600] clocksource: Switched to clocksource arch_sys_counter
5952 18:41:14.420337 <5>[ 0.748031] VFS: Disk quotas dquot_6.6.0
5953 18:41:14.426417 <6>[ 0.752207] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
5954 18:41:14.429743 <6>[ 0.759380] pnp: PnP ACPI: disabled
5955 18:41:14.437894 <6>[ 0.766274] NET: Registered PF_INET protocol family
5956 18:41:14.444632 <6>[ 0.771506] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
5957 18:41:14.456742 <6>[ 0.781412] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
5958 18:41:14.466302 <6>[ 0.790166] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
5959 18:41:14.472492 <6>[ 0.798116] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
5960 18:41:14.478950 <6>[ 0.806349] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
5961 18:41:14.489184 <6>[ 0.814443] TCP: Hash tables configured (established 32768 bind 32768)
5962 18:41:14.496314 <6>[ 0.821269] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
5963 18:41:14.502139 <6>[ 0.828240] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
5964 18:41:14.508896 <6>[ 0.835720] NET: Registered PF_UNIX/PF_LOCAL protocol family
5965 18:41:14.515555 <6>[ 0.841813] RPC: Registered named UNIX socket transport module.
5966 18:41:14.519100 <6>[ 0.847956] RPC: Registered udp transport module.
5967 18:41:14.525605 <6>[ 0.852880] RPC: Registered tcp transport module.
5968 18:41:14.532077 <6>[ 0.857804] RPC: Registered tcp NFSv4.1 backchannel transport module.
5969 18:41:14.535117 <6>[ 0.864456] PCI: CLS 0 bytes, default 64
5970 18:41:14.538023 <6>[ 0.868741] Unpacking initramfs...
5971 18:41:14.560977 <6>[ 0.885750] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
5972 18:41:14.570086 <6>[ 0.894489] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
5973 18:41:14.573639 <6>[ 0.903411] kvm [1]: IPA Size Limit: 40 bits
5974 18:41:14.581331 <6>[ 0.909776] kvm [1]: vgic-v2@c420000
5975 18:41:14.588076 <6>[ 0.913610] kvm [1]: GIC system register CPU interface enabled
5976 18:41:14.591320 <6>[ 0.919797] kvm [1]: vgic interrupt IRQ18
5977 18:41:14.597689 <6>[ 0.924168] kvm [1]: Hyp mode initialized successfully
5978 18:41:14.601459 <5>[ 0.930561] Initialise system trusted keyrings
5979 18:41:14.607671 <6>[ 0.935416] workingset: timestamp_bits=42 max_order=20 bucket_order=0
5980 18:41:14.616706 <6>[ 0.945395] squashfs: version 4.0 (2009/01/31) Phillip Lougher
5981 18:41:14.623586 <5>[ 0.951837] NFS: Registering the id_resolver key type
5982 18:41:14.626541 <5>[ 0.957144] Key type id_resolver registered
5983 18:41:14.633199 <5>[ 0.961556] Key type id_legacy registered
5984 18:41:14.639837 <6>[ 0.965867] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
5985 18:41:14.646311 <6>[ 0.972789] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
5986 18:41:14.653204 <6>[ 0.980534] 9p: Installing v9fs 9p2000 file system support
5987 18:41:14.681028 <5>[ 1.009299] Key type asymmetric registered
5988 18:41:14.684259 <5>[ 1.013651] Asymmetric key parser 'x509' registered
5989 18:41:14.694008 <6>[ 1.018807] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
5990 18:41:14.697529 <6>[ 1.026427] io scheduler mq-deadline registered
5991 18:41:14.700806 <6>[ 1.031185] io scheduler kyber registered
5992 18:41:14.723689 <6>[ 1.051998] EINJ: ACPI disabled.
5993 18:41:14.729709 <4>[ 1.055780] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
5994 18:41:14.768536 <6>[ 1.096656] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
5995 18:41:14.776726 <6>[ 1.105112] printk: console [ttyS0] disabled
5996 18:41:14.804846 <6>[ 1.129768] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
5997 18:41:14.811609 <6>[ 1.139241] printk: console [ttyS0] enabled
5998 18:41:14.814471 <6>[ 1.139241] printk: console [ttyS0] enabled
5999 18:41:14.820972 <6>[ 1.148157] printk: bootconsole [mtk8250] disabled
6000 18:41:14.824009 <6>[ 1.148157] printk: bootconsole [mtk8250] disabled
6001 18:41:14.833872 <3>[ 1.158687] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6002 18:41:14.840509 <3>[ 1.167067] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6003 18:41:14.870172 <6>[ 1.195481] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6004 18:41:14.876638 <6>[ 1.205138] serial serial0: tty port ttyS1 registered
6005 18:41:14.883204 <6>[ 1.211702] SuperH (H)SCI(F) driver initialized
6006 18:41:14.889815 <6>[ 1.217197] msm_serial: driver initialized
6007 18:41:14.902236 <6>[ 1.227560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6008 18:41:14.911867 <6>[ 1.236158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6009 18:41:14.918413 <6>[ 1.244738] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6010 18:41:14.928230 <6>[ 1.253309] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6011 18:41:14.938465 <6>[ 1.261966] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6012 18:41:14.944683 <6>[ 1.270629] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6013 18:41:14.954804 <6>[ 1.279366] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6014 18:41:14.964516 <6>[ 1.288103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6015 18:41:14.970737 <6>[ 1.296673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6016 18:41:14.980548 <6>[ 1.305473] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6017 18:41:14.989660 <4>[ 1.317851] cacheinfo: Unable to detect cache hierarchy for CPU 0
6018 18:41:14.998506 <6>[ 1.327211] loop: module loaded
6019 18:41:15.010946 <6>[ 1.339164] vsim1: Bringing 1800000uV into 2700000-2700000uV
6020 18:41:15.028789 <6>[ 1.357111] megasas: 07.719.03.00-rc1
6021 18:41:15.037717 <6>[ 1.365934] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6022 18:41:15.052327 <6>[ 1.376991] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6023 18:41:15.065275 <6>[ 1.393541] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6024 18:41:15.125278 <6>[ 1.447054] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.3.25/cr50_v1.9308_87_mp.398-a
6025 18:41:15.159060 <6>[ 1.487380] Freeing initrd memory: 18292K
6026 18:41:15.172280 <4>[ 1.497289] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6027 18:41:15.178681 <4>[ 1.506522] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6028 18:41:15.185364 <4>[ 1.513219] Hardware name: Google juniper sku16 board (DT)
6029 18:41:15.188753 <4>[ 1.518958] Call trace:
6030 18:41:15.192044 <4>[ 1.521658] dump_backtrace.part.0+0xe0/0xf0
6031 18:41:15.195000 <4>[ 1.526195] show_stack+0x18/0x30
6032 18:41:15.202077 <4>[ 1.529767] dump_stack_lvl+0x68/0x84
6033 18:41:15.205236 <4>[ 1.533688] dump_stack+0x18/0x34
6034 18:41:15.208116 <4>[ 1.537258] sysfs_warn_dup+0x64/0x80
6035 18:41:15.211270 <4>[ 1.541179] sysfs_do_create_link_sd+0xf0/0x100
6036 18:41:15.218237 <4>[ 1.545967] sysfs_create_link+0x20/0x40
6037 18:41:15.221658 <4>[ 1.550146] bus_add_device+0x68/0x10c
6038 18:41:15.224685 <4>[ 1.554152] device_add+0x340/0x7ac
6039 18:41:15.227893 <4>[ 1.557894] of_device_add+0x44/0x60
6040 18:41:15.234500 <4>[ 1.561728] of_platform_device_create_pdata+0x90/0x120
6041 18:41:15.237812 <4>[ 1.567210] of_platform_bus_create+0x170/0x370
6042 18:41:15.243984 <4>[ 1.571997] of_platform_populate+0x50/0xfc
6043 18:41:15.247510 <4>[ 1.576436] parse_mtd_partitions+0x1dc/0x510
6044 18:41:15.253978 <4>[ 1.581048] mtd_device_parse_register+0xf8/0x2e0
6045 18:41:15.257658 <4>[ 1.586007] spi_nor_probe+0x21c/0x2f0
6046 18:41:15.260959 <4>[ 1.590013] spi_mem_probe+0x6c/0xb0
6047 18:41:15.263858 <4>[ 1.593845] spi_probe+0x84/0xe4
6048 18:41:15.267532 <4>[ 1.597327] really_probe+0xbc/0x2e0
6049 18:41:15.273558 <4>[ 1.601157] __driver_probe_device+0x78/0x11c
6050 18:41:15.277079 <4>[ 1.605769] driver_probe_device+0xd8/0x160
6051 18:41:15.280485 <4>[ 1.610207] __device_attach_driver+0xb8/0x134
6052 18:41:15.286978 <4>[ 1.614906] bus_for_each_drv+0x78/0xd0
6053 18:41:15.290006 <4>[ 1.618996] __device_attach+0xa8/0x1c0
6054 18:41:15.293806 <4>[ 1.623087] device_initial_probe+0x14/0x20
6055 18:41:15.300314 <4>[ 1.627525] bus_probe_device+0x9c/0xa4
6056 18:41:15.303097 <4>[ 1.631615] device_add+0x3ac/0x7ac
6057 18:41:15.306477 <4>[ 1.635357] __spi_add_device+0x78/0x120
6058 18:41:15.309891 <4>[ 1.639535] spi_add_device+0x40/0x7c
6059 18:41:15.316326 <4>[ 1.643453] spi_register_controller+0x610/0xad0
6060 18:41:15.319666 <4>[ 1.648326] devm_spi_register_controller+0x4c/0xa4
6061 18:41:15.322769 <4>[ 1.653459] mtk_spi_probe+0x3f8/0x650
6062 18:41:15.329711 <4>[ 1.657464] platform_probe+0x68/0xe0
6063 18:41:15.332963 <4>[ 1.661382] really_probe+0xbc/0x2e0
6064 18:41:15.336271 <4>[ 1.665213] __driver_probe_device+0x78/0x11c
6065 18:41:15.342524 <4>[ 1.669824] driver_probe_device+0xd8/0x160
6066 18:41:15.346165 <4>[ 1.674262] __driver_attach+0x94/0x19c
6067 18:41:15.349543 <4>[ 1.678353] bus_for_each_dev+0x70/0xd0
6068 18:41:15.352400 <4>[ 1.682443] driver_attach+0x24/0x30
6069 18:41:15.356108 <4>[ 1.686272] bus_add_driver+0x154/0x20c
6070 18:41:15.362213 <4>[ 1.690362] driver_register+0x78/0x130
6071 18:41:15.365287 <4>[ 1.694453] __platform_driver_register+0x28/0x34
6072 18:41:15.372019 <4>[ 1.699413] mtk_spi_driver_init+0x1c/0x28
6073 18:41:15.375494 <4>[ 1.703766] do_one_initcall+0x50/0x1d0
6074 18:41:15.378404 <4>[ 1.707856] kernel_init_freeable+0x21c/0x288
6075 18:41:15.381629 <4>[ 1.712470] kernel_init+0x24/0x12c
6076 18:41:15.388290 <4>[ 1.716215] ret_from_fork+0x10/0x20
6077 18:41:15.396962 <6>[ 1.724974] tun: Universal TUN/TAP device driver, 1.6
6078 18:41:15.400041 <6>[ 1.731252] thunder_xcv, ver 1.0
6079 18:41:15.406795 <6>[ 1.734769] thunder_bgx, ver 1.0
6080 18:41:15.407317 <6>[ 1.738273] nicpf, ver 1.0
6081 18:41:15.417600 <6>[ 1.742649] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6082 18:41:15.421168 <6>[ 1.750133] hns3: Copyright (c) 2017 Huawei Corporation.
6083 18:41:15.427502 <6>[ 1.755732] hclge is initializing
6084 18:41:15.430689 <6>[ 1.759317] e1000: Intel(R) PRO/1000 Network Driver
6085 18:41:15.437120 <6>[ 1.764454] e1000: Copyright (c) 1999-2006 Intel Corporation.
6086 18:41:15.443785 <6>[ 1.770477] e1000e: Intel(R) PRO/1000 Network Driver
6087 18:41:15.447048 <6>[ 1.775698] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6088 18:41:15.454027 <6>[ 1.781894] igb: Intel(R) Gigabit Ethernet Network Driver
6089 18:41:15.460297 <6>[ 1.787551] igb: Copyright (c) 2007-2014 Intel Corporation.
6090 18:41:15.466889 <6>[ 1.793394] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6091 18:41:15.473029 <6>[ 1.799918] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6092 18:41:15.476778 <6>[ 1.806467] sky2: driver version 1.30
6093 18:41:15.483682 <6>[ 1.811720] usbcore: registered new device driver r8152-cfgselector
6094 18:41:15.490059 <6>[ 1.818267] usbcore: registered new interface driver r8152
6095 18:41:15.496628 <6>[ 1.824091] VFIO - User Level meta-driver version: 0.3
6096 18:41:15.503856 <6>[ 1.831896] mtu3 11201000.usb: uwk - reg:0x420, version:101
6097 18:41:15.509887 <4>[ 1.837767] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6098 18:41:15.516755 <6>[ 1.845039] mtu3 11201000.usb: dr_mode: 1, drd: auto
6099 18:41:15.523361 <6>[ 1.850265] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6100 18:41:15.526363 <6>[ 1.856441] mtu3 11201000.usb: usb3-drd: 0
6101 18:41:15.537095 <6>[ 1.861998] mtu3 11201000.usb: xHCI platform device register success...
6102 18:41:15.543378 <4>[ 1.870651] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6103 18:41:15.550376 <6>[ 1.878585] xhci-mtk 11200000.usb: xHCI Host Controller
6104 18:41:15.559921 <6>[ 1.884096] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6105 18:41:15.563468 <6>[ 1.891816] xhci-mtk 11200000.usb: USB3 root hub has no ports
6106 18:41:15.573283 <6>[ 1.897842] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6107 18:41:15.579518 <6>[ 1.907260] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6108 18:41:15.585889 <6>[ 1.913344] xhci-mtk 11200000.usb: xHCI Host Controller
6109 18:41:15.592512 <6>[ 1.918834] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6110 18:41:15.599346 <6>[ 1.926491] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6111 18:41:15.602626 <6>[ 1.933305] hub 1-0:1.0: USB hub found
6112 18:41:15.609169 <6>[ 1.937335] hub 1-0:1.0: 1 port detected
6113 18:41:15.618989 <6>[ 1.942700] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6114 18:41:15.622136 <6>[ 1.951342] hub 2-0:1.0: USB hub found
6115 18:41:15.628883 <3>[ 1.955391] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6116 18:41:15.635596 <6>[ 1.963305] usbcore: registered new interface driver usb-storage
6117 18:41:15.641789 <6>[ 1.969894] usbcore: registered new device driver onboard-usb-hub
6118 18:41:15.653056 <4>[ 1.977709] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6119 18:41:15.661643 <6>[ 1.989955] mt6397-rtc mt6358-rtc: registered as rtc0
6120 18:41:15.671258 <6>[ 1.995427] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-11T18:41:15 UTC (1718131275)
6121 18:41:15.678407 <6>[ 2.005316] i2c_dev: i2c /dev entries driver
6122 18:41:15.687759 <6>[ 2.011680] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6123 18:41:15.694318 <6>[ 2.019999] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6124 18:41:15.700935 <6>[ 2.028903] i2c 4-0058: Fixed dependency cycle(s) with /panel
6125 18:41:15.707503 <6>[ 2.034933] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6126 18:41:15.717202 <3>[ 2.042405] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6127 18:41:15.734076 <6>[ 2.062258] cpu cpu0: EM: created perf domain
6128 18:41:15.747383 <6>[ 2.067712] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6129 18:41:15.750219 <6>[ 2.078982] cpu cpu4: EM: created perf domain
6130 18:41:15.757578 <6>[ 2.085643] sdhci: Secure Digital Host Controller Interface driver
6131 18:41:15.764058 <6>[ 2.092083] sdhci: Copyright(c) Pierre Ossman
6132 18:41:15.770566 <6>[ 2.097487] Synopsys Designware Multimedia Card Interface Driver
6133 18:41:15.776945 <6>[ 2.098043] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6134 18:41:15.780494 <6>[ 2.104646] sdhci-pltfm: SDHCI platform and OF driver helper
6135 18:41:15.788960 <6>[ 2.117239] ledtrig-cpu: registered to indicate activity on CPUs
6136 18:41:15.796916 <6>[ 2.124972] usbcore: registered new interface driver usbhid
6137 18:41:15.803151 <6>[ 2.130817] usbhid: USB HID core driver
6138 18:41:15.810352 <6>[ 2.135126] spi_master spi2: will run message pump with realtime priority
6139 18:41:15.817619 <4>[ 2.135386] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6140 18:41:15.823807 <4>[ 2.149489] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6141 18:41:15.837639 <6>[ 2.155037] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6142 18:41:15.854411 <6>[ 2.172560] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6143 18:41:15.861188 <4>[ 2.181999] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6144 18:41:15.867017 <6>[ 2.187163] cros-ec-spi spi2.0: Chrome EC device registered
6145 18:41:15.878317 <4>[ 2.203226] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6146 18:41:15.892965 <4>[ 2.217839] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6147 18:41:15.899869 <6>[ 2.221473] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6148 18:41:15.906133 <4>[ 2.226840] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6149 18:41:15.909393 <6>[ 2.233412] mmc0: new HS400 MMC card at address 0001
6150 18:41:15.915991 <6>[ 2.243934] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6151 18:41:15.922914 <6>[ 2.246978] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6152 18:41:15.929148 <6>[ 2.254005] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6153 18:41:15.938633 <6>[ 2.262490] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6154 18:41:15.941730 <6>[ 2.264697] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6155 18:41:15.955456 <6>[ 2.274929] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6156 18:41:15.958193 <6>[ 2.277977] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6157 18:41:15.965053 <6>[ 2.288706] NET: Registered PF_PACKET protocol family
6158 18:41:15.971384 <6>[ 2.293627] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6159 18:41:15.974468 <6>[ 2.297928] 9pnet: Installing 9P2000 support
6160 18:41:15.987601 <6>[ 2.301828] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6161 18:41:15.997671 <6>[ 2.302135] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6162 18:41:16.001094 <5>[ 2.331116] Key type dns_resolver registered
6163 18:41:16.007838 <6>[ 2.336307] registered taskstats version 1
6164 18:41:16.011185 <5>[ 2.340677] Loading compiled-in X.509 certificates
6165 18:41:16.028392 <6>[ 2.353749] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6166 18:41:16.052080 <3>[ 2.376929] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6167 18:41:16.083763 <6>[ 2.405496] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6168 18:41:16.094752 <6>[ 2.419869] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6169 18:41:16.104554 <6>[ 2.428438] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6170 18:41:16.111288 <6>[ 2.437196] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6171 18:41:16.120928 <6>[ 2.445798] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6172 18:41:16.130724 <6>[ 2.454433] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6173 18:41:16.136968 <6>[ 2.463091] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6174 18:41:16.147256 <6>[ 2.471659] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6175 18:41:16.153354 <6>[ 2.481060] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6176 18:41:16.160243 <6>[ 2.488586] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6177 18:41:16.167880 <6>[ 2.495749] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6178 18:41:16.177758 <6>[ 2.502868] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6179 18:41:16.180829 <6>[ 2.508579] hub 1-1:1.0: USB hub found
6180 18:41:16.187484 <6>[ 2.510210] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6181 18:41:16.190772 <6>[ 2.513955] hub 1-1:1.0: 3 ports detected
6182 18:41:16.197523 <6>[ 2.521612] panfrost 13040000.gpu: clock rate = 511999970
6183 18:41:16.207285 <6>[ 2.530178] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6184 18:41:16.213530 <6>[ 2.540511] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6185 18:41:16.223226 <6>[ 2.548528] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6186 18:41:16.236219 <6>[ 2.556964] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6187 18:41:16.243087 <6>[ 2.569042] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6188 18:41:16.254187 <6>[ 2.579225] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6189 18:41:16.263916 <6>[ 2.587884] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6190 18:41:16.273493 <6>[ 2.597038] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6191 18:41:16.283269 <6>[ 2.606167] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6192 18:41:16.289786 <6>[ 2.615293] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6193 18:41:16.299797 <6>[ 2.624595] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6194 18:41:16.309405 <6>[ 2.633896] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6195 18:41:16.319145 <6>[ 2.643369] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6196 18:41:16.329394 <6>[ 2.652842] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6197 18:41:16.338831 <6>[ 2.661967] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6198 18:41:16.409841 <6>[ 2.734841] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6199 18:41:16.419468 <6>[ 2.743736] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6200 18:41:16.432108 <6>[ 2.756731] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6201 18:41:16.488438 <6>[ 2.813633] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6202 18:41:17.120999 <6>[ 3.006004] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6203 18:41:17.130684 <4>[ 3.122829] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6204 18:41:17.137395 <4>[ 3.122849] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6205 18:41:17.143644 <6>[ 3.159287] r8152 1-1.2:1.0 eth0: v1.12.13
6206 18:41:17.150310 <6>[ 3.237636] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6207 18:41:17.157172 <6>[ 3.429459] Console: switching to colour frame buffer device 170x48
6208 18:41:17.166661 <6>[ 3.490119] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6209 18:41:17.185847 <6>[ 3.507525] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6210 18:41:17.203108 <6>[ 3.524828] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6211 18:41:17.212735 <6>[ 3.537246] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6212 18:41:17.219096 <6>[ 3.545808] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6213 18:41:17.232437 <6>[ 3.554200] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6214 18:41:17.251014 <6>[ 3.572480] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6215 18:41:18.507960 <6>[ 4.835861] r8152 1-1.2:1.0 eth0: carrier on
6216 18:41:21.241516 <5>[ 4.865633] Sending DHCP requests .., OK
6217 18:41:21.247940 <6>[ 7.573941] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.22
6218 18:41:21.250943 <6>[ 7.582374] IP-Config: Complete:
6219 18:41:21.264292 <6>[ 7.585946] device=eth0, hwaddr=00:e0:4c:78:85:cb, ipaddr=192.168.201.22, mask=255.255.255.0, gw=192.168.201.1
6220 18:41:21.274140 <6>[ 7.596847] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2, domain=lava-rack, nis-domain=(none)
6221 18:41:21.286054 <6>[ 7.611124] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6222 18:41:21.294556 <6>[ 7.611135] nameserver0=192.168.201.1
6223 18:41:21.302594 <6>[ 7.630903] clk: Disabling unused clocks
6224 18:41:21.307420 <6>[ 7.638860] ALSA device list:
6225 18:41:21.316783 <6>[ 7.644876] No soundcards found.
6226 18:41:21.325659 <6>[ 7.653819] Freeing unused kernel memory: 8512K
6227 18:41:21.332621 <6>[ 7.660978] Run /init as init process
6228 18:41:21.344487 Loading, please wait...
6229 18:41:21.376672 Starting systemd-udevd version 252.22-1~deb12u1
6230 18:41:21.708430 <3>[ 8.036718] thermal_sys: Failed to find 'trips' node
6231 18:41:21.719486 <6>[ 8.043168] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6232 18:41:21.725823 <3>[ 8.044338] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6233 18:41:21.732328 <4>[ 8.053386] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6234 18:41:21.741985 <3>[ 8.059497] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6235 18:41:21.748918 <4>[ 8.059511] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6236 18:41:21.755553 <6>[ 8.059877] Bluetooth: Core ver 2.22
6237 18:41:21.765096 <3>[ 8.059985] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6238 18:41:21.771404 <3>[ 8.059989] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6239 18:41:21.781780 <3>[ 8.059993] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6240 18:41:21.788084 <3>[ 8.059997] elan_i2c 2-0015: Error applying setting, reverse things back
6241 18:41:21.794244 <3>[ 8.060771] mtk-scp 10500000.scp: invalid resource
6242 18:41:21.800979 <6>[ 8.060824] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6243 18:41:21.807553 <3>[ 8.062486] thermal_sys: Failed to find 'trips' node
6244 18:41:21.813894 <3>[ 8.062495] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6245 18:41:21.823678 <3>[ 8.062506] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6246 18:41:21.830270 <4>[ 8.062511] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6247 18:41:21.840458 <4>[ 8.067429] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6248 18:41:21.846614 <6>[ 8.084440] NET: Registered PF_BLUETOOTH protocol family
6249 18:41:21.853324 <4>[ 8.086843] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6250 18:41:21.859967 <6>[ 8.089508] remoteproc remoteproc0: scp is available
6251 18:41:21.873044 <6>[ 8.090288] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6252 18:41:21.882763 <6>[ 8.096258] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6253 18:41:21.894353 <6>[ 8.097557] Bluetooth: HCI device and connection manager initialized
6254 18:41:21.903896 <4>[ 8.104412] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6255 18:41:21.917048 <3>[ 8.110041] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6256 18:41:21.923552 <6>[ 8.115282] Bluetooth: HCI socket layer initialized
6257 18:41:21.933978 <3>[ 8.115446] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6258 18:41:21.944333 <3>[ 8.115460] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6259 18:41:21.954653 <3>[ 8.115465] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6260 18:41:21.961563 <6>[ 8.122215] remoteproc remoteproc0: powering up scp
6261 18:41:21.968768 <6>[ 8.122240] mc: Linux media interface: v0.10
6262 18:41:21.974892 <6>[ 8.127269] Bluetooth: L2CAP socket layer initialized
6263 18:41:21.985170 <3>[ 8.130091] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6264 18:41:21.995346 <3>[ 8.130104] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6265 18:41:22.005823 <3>[ 8.130109] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6266 18:41:22.015622 <3>[ 8.130116] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6267 18:41:22.026167 <3>[ 8.130121] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6268 18:41:22.036362 <3>[ 8.130161] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6269 18:41:22.046567 <4>[ 8.134830] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6270 18:41:22.053559 <6>[ 8.140041] Bluetooth: SCO socket layer initialized
6271 18:41:22.060690 <3>[ 8.147333] remoteproc remoteproc0: request_firmware failed: -2
6272 18:41:22.072080 <6>[ 8.169670] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6273 18:41:22.081876 <5>[ 8.172343] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6274 18:41:22.088329 <6>[ 8.181505] videodev: Linux video capture interface: v2.00
6275 18:41:22.099173 <5>[ 8.181628] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6276 18:41:22.105296 <6>[ 8.181632] cs_system_cfg: CoreSight Configuration manager initialised
6277 18:41:22.116420 <5>[ 8.182202] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6278 18:41:22.126571 <4>[ 8.182297] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6279 18:41:22.134031 <6>[ 8.182309] cfg80211: failed to load regulatory.db
6280 18:41:22.175712 <3>[ 8.497152] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6281 18:41:22.185875 <6>[ 8.499763] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6282 18:41:22.191929 <3>[ 8.509757] debugfs: File 'Playback' in directory 'dapm' already present!
6283 18:41:22.201989 <6>[ 8.526584] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6284 18:41:22.208803 <3>[ 8.527298] debugfs: File 'Capture' in directory 'dapm' already present!
6285 18:41:22.215443 <6>[ 8.535250] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6286 18:41:22.236394 <6>[ 8.561256] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6287 18:41:22.247778 <6>[ 8.572631] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6288 18:41:22.261077 <6>[ 8.585587] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6289 18:41:22.272284 <6>[ 8.600432] Bluetooth: HCI UART driver ver 2.3
6290 18:41:22.284036 <6>[ 8.608798] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6291 18:41:22.290260 <6>[ 8.609799] Bluetooth: HCI UART protocol H4 registered
6292 18:41:22.302876 <6>[ 8.627998] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6293 18:41:22.316510 <6>[ 8.637135] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6294 18:41:22.322870 <6>[ 8.638603] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6295 18:41:22.330726 <6>[ 8.657099] Bluetooth: HCI UART protocol LL registered
6296 18:41:22.344496 <6>[ 8.672369] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6297 18:41:22.357014 <6>[ 8.681873] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6298 18:41:22.380419 <6>[ 8.706666] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6299 18:41:22.399104 <6>[ 8.726963] Bluetooth: HCI UART protocol Three-wire (H5) registered
6300 18:41:22.414639 <6>[ 8.742811] Bluetooth: HCI UART protocol Broadcom registered
6301 18:41:22.426793 <6>[ 8.754912] Bluetooth: HCI UART protocol QCA registered
6302 18:41:22.434971 <6>[ 8.763196] Bluetooth: HCI UART protocol Marvell registered
6303 18:41:22.447243 <6>[ 8.772182] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6304 18:41:22.462165 <6>[ 8.783592] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6305 18:41:22.472016 <6>[ 8.796770] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6306 18:41:22.487229 <6>[ 8.808768] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6307 18:41:22.500229 <6>[ 8.809027] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6308 18:41:22.506702 <6>[ 8.809776] Bluetooth: hci0: setting up ROME/QCA6390
6309 18:41:22.513339 <6>[ 8.840377] usbcore: registered new interface driver uvcvideo
6310 18:41:22.522893 <6>[ 8.840673] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video3
6311 18:41:22.532873 <4>[ 8.846922] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6312 18:41:22.539598 <4>[ 8.846922] Fallback method does not support PEC.
6313 18:41:22.564887 <3>[ 8.889662] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6314 18:41:22.571553 Begin: Loading essential drivers ... done.
6315 18:41:22.584612 Begin: Running /scri<3>[ 8.907359] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6316 18:41:22.588665 pts/init-premount ... done.
6317 18:41:22.595273 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6318 18:41:22.605231 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6319 18:41:22.608486 Device /sys/class/net/eth0 found
6320 18:41:22.609006 done.
6321 18:41:22.614891 Begin: Waiting up to 180 secs for any network device to become available ... done.
6322 18:41:22.657546 IP-Config: eth0 hardware address 00:e0:4c:78:85:cb mtu 1500 DHCP
6323 18:41:22.666396 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6324 18:41:22.672794 address: 192.168.201.22 broadcast: 192.168.201.255 netmask: 255.255.255.0
6325 18:41:22.679556 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6326 18:41:22.685892 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-2
6327 18:41:22.698937 domain : lava-rack <6>[ 9.023040] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6328 18:41:22.705671 <3>[ 9.029024] Bluetooth: hci0: Frame reassembly failed (-84)
6329 18:41:22.706089
6330 18:41:22.708771 rootserver: 192.168.201.1 rootpath:
6331 18:41:22.711889 filename :
6332 18:41:22.862236 done.
6333 18:41:22.869804 Begin: Running /scripts/nfs-bottom ... done.
6334 18:41:22.883252 Begin: Running /scripts/init-bottom ... done.
6335 18:41:22.990110 <6>[ 9.318110] Bluetooth: hci0: QCA Product ID :0x00000008
6336 18:41:22.997338 <6>[ 9.325150] Bluetooth: hci0: QCA SOC Version :0x00000044
6337 18:41:23.003607 <6>[ 9.331690] Bluetooth: hci0: QCA ROM Version :0x00000302
6338 18:41:23.010086 <6>[ 9.338278] Bluetooth: hci0: QCA Patch Version:0x00000111
6339 18:41:23.016863 <6>[ 9.338286] Bluetooth: hci0: QCA controller version 0x00440302
6340 18:41:23.023043 <6>[ 9.338290] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6341 18:41:23.035556 <4>[ 9.360347] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6342 18:41:23.046701 <3>[ 9.371832] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6343 18:41:23.053721 <3>[ 9.382260] Bluetooth: hci0: QCA Failed to download patch (-2)
6344 18:41:23.094861 <6>[ 9.419777] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6345 18:41:23.119037 <3>[ 9.446926] Bluetooth: hci0: Frame reassembly failed (-84)
6346 18:41:23.125403 <4>[ 9.447094] Bluetooth: hci0: Received unexpected HCI Event 0x00
6347 18:41:23.131829 <3>[ 9.452717] Bluetooth: hci0: Frame reassembly failed (-84)
6348 18:41:23.203547 <4>[ 9.528771] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6349 18:41:23.222429 <4>[ 9.547570] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6350 18:41:23.237082 <4>[ 9.562347] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6351 18:41:23.246903 <4>[ 9.575329] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6352 18:41:24.304898 <6>[ 10.632872] NET: Registered PF_INET6 protocol family
6353 18:41:24.316253 <6>[ 10.644811] Segment Routing with IPv6
6354 18:41:24.324003 <6>[ 10.652752] In-situ OAM (IOAM) with IPv6
6355 18:41:24.512851 <30>[ 10.811327] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6356 18:41:24.529636 <30>[ 10.857875] systemd[1]: Detected architecture arm64.
6357 18:41:24.544396
6358 18:41:24.547528 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6359 18:41:24.547936
6360 18:41:24.570585 <30>[ 10.898816] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6361 18:41:25.133581 <3>[ 11.461815] Bluetooth: hci0: Opcode 0x1002 failed: -110
6362 18:41:25.670109 <30>[ 11.995239] systemd[1]: Queued start job for default target graphical.target.
6363 18:41:25.718244 <30>[ 12.043265] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6364 18:41:25.730963 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6365 18:41:25.750871 <30>[ 12.075883] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6366 18:41:25.764051 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6367 18:41:25.783418 <30>[ 12.108001] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6368 18:41:25.797006 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6369 18:41:25.814118 <30>[ 12.139190] systemd[1]: Created slice user.slice - User and Session Slice.
6370 18:41:25.826272 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6371 18:41:25.848514 <30>[ 12.170187] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6372 18:41:25.861296 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6373 18:41:25.880457 <30>[ 12.202028] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6374 18:41:25.892507 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6375 18:41:25.922232 <30>[ 12.233977] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6376 18:41:25.937677 <30>[ 12.262580] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6377 18:41:25.948682 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6378 18:41:25.964787 <30>[ 12.289816] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6379 18:41:25.977719 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6380 18:41:25.997150 <30>[ 12.321850] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6381 18:41:26.011052 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6382 18:41:26.025915 <30>[ 12.353898] systemd[1]: Reached target paths.target - Path Units.
6383 18:41:26.040115 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6384 18:41:26.056619 <30>[ 12.381792] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6385 18:41:26.069213 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6386 18:41:26.084834 <30>[ 12.409814] systemd[1]: Reached target slices.target - Slice Units.
6387 18:41:26.096337 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6388 18:41:26.109831 <30>[ 12.437840] systemd[1]: Reached target swap.target - Swaps.
6389 18:41:26.120324 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6390 18:41:26.141176 <30>[ 12.465879] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6391 18:41:26.154631 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6392 18:41:26.173636 <30>[ 12.498237] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6393 18:41:26.187291 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6394 18:41:26.208469 <30>[ 12.533053] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6395 18:41:26.221777 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6396 18:41:26.242767 <30>[ 12.567567] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6397 18:41:26.256992 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6398 18:41:26.274136 <30>[ 12.598673] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6399 18:41:26.285972 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6400 18:41:26.306601 <30>[ 12.631629] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6401 18:41:26.321052 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6402 18:41:26.340321 <30>[ 12.665298] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6403 18:41:26.353789 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6404 18:41:26.373509 <30>[ 12.698412] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6405 18:41:26.386650 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6406 18:41:26.429047 <30>[ 12.753978] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6407 18:41:26.441242 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6408 18:41:26.466592 <30>[ 12.791632] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6409 18:41:26.478700 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6410 18:41:26.501370 <30>[ 12.826336] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6411 18:41:26.512828 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6412 18:41:26.535884 <30>[ 12.854312] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6413 18:41:26.578004 <30>[ 12.903201] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6414 18:41:26.591193 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6415 18:41:26.614610 <30>[ 12.939641] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6416 18:41:26.625759 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6417 18:41:26.661338 <30>[ 12.986517] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6418 18:41:26.672801 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6419 18:41:26.693686 <30>[ 13.018951] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6420 18:41:26.706133 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6421 18:41:26.712543 <6>[ 13.037333] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6422 18:41:26.712634
6423 18:41:26.757676 <30>[ 13.082773] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6424 18:41:26.770203 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6425 18:41:26.794762 <30>[ 13.120164] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6426 18:41:26.805796 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6427 18:41:26.834075 <6>[ 13.162095] fuse: init (API version 7.37)
6428 18:41:26.850239 <30>[ 13.175268] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6429 18:41:26.863619 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6430 18:41:26.905911 <30>[ 13.230994] systemd[1]: Starting systemd-journald.service - Journal Service...
6431 18:41:26.916167 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6432 18:41:26.947768 <30>[ 13.272796] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6433 18:41:26.961008 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6434 18:41:26.988223 <30>[ 13.310043] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6435 18:41:27.000294 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6436 18:41:27.041541 <30>[ 13.366742] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6437 18:41:27.055232 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6438 18:41:27.080703 <30>[ 13.406082] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6439 18:41:27.092344 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6440 18:41:27.114259 <30>[ 13.439613] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6441 18:41:27.121153 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6442 18:41:27.140238 <3>[ 13.465049] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6443 18:41:27.150864 <30>[ 13.474437] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6444 18:41:27.157260 <3>[ 13.479548] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6445 18:41:27.168292 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6446 18:41:27.178243 <3>[ 13.502346] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6447 18:41:27.190015 <30>[ 13.514526] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6448 18:41:27.196478 <3>[ 13.517200] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6449 18:41:27.214726 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m<3>[ 13.538068] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6450 18:41:27.215157 - Kernel Debug File System.
6451 18:41:27.228656 <3>[ 13.552881] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6452 18:41:27.239001 <30>[ 13.562777] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6453 18:41:27.245496 <3>[ 13.567708] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6454 18:41:27.258085 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6455 18:41:27.264535 <3>[ 13.591058] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6456 18:41:27.276639 <30>[ 13.600784] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6457 18:41:27.287355 <30>[ 13.610799] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6458 18:41:27.296880 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6459 18:41:27.313852 <30>[ 13.638663] systemd[1]: Started systemd-journald.service - Journal Service.
6460 18:41:27.325283 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6461 18:41:27.347387 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6462 18:41:27.371924 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6463 18:41:27.391758 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6464 18:41:27.411834 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6465 18:41:27.431631 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6466 18:41:27.450384 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6467 18:41:27.470502 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6468 18:41:27.490427 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6469 18:41:27.511573 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6470 18:41:27.565088 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6471 18:41:27.578168 <4>[ 13.906399] power_supply_show_property: 2 callbacks suppressed
6472 18:41:27.588480 <3>[ 13.906410] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6473 18:41:27.595325 <3>[ 13.918935] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6474 18:41:27.612037 <4>[ 13.921528] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6475 18:41:27.622081 <3>[ 13.935628] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6476 18:41:27.628337 <3>[ 13.946087] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6477 18:41:27.642111 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6478 18:41:27.652003 <3>[ 13.976486] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6479 18:41:27.671003 <3>[ 13.996432] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6480 18:41:27.688410 <3>[ 14.013587] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6481 18:41:27.700097 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6482 18:41:27.706537 <3>[ 14.032185] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6483 18:41:27.726398 Starting [0;1;39msystemd-random-se…i<3>[ 14.050897] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6484 18:41:27.729487 ce[0m - Load/Save Random Seed...
6485 18:41:27.744738 <3>[ 14.069384] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6486 18:41:27.762209 <3>[ 14.086850] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6487 18:41:27.768938 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6488 18:41:27.783223 <46>[ 14.108430] systemd-journald[314]: Received client request to flush runtime journal.
6489 18:41:27.799975 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6490 18:41:28.015212 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6491 18:41:28.034774 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6492 18:41:28.054365 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6493 18:41:28.075581 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6494 18:41:28.094067 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6495 18:41:28.904292 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6496 18:41:28.946316 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6497 18:41:29.230429 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6498 18:41:29.341151 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6499 18:41:29.361352 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6500 18:41:29.384827 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6501 18:41:29.449763 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6502 18:41:29.477706 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6503 18:41:29.769454 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6504 18:41:29.832996 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6505 18:41:29.896653 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6506 18:41:30.131515 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6507 18:41:30.252364 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6508 18:41:30.269007 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6509 18:41:30.285147 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6510 18:41:30.330906 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6511 18:41:30.376366 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6512 18:41:30.400855 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6513 18:41:30.453074 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6514 18:41:30.535286 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6515 18:41:30.558440 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6516 18:41:30.572165 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6517 18:41:30.609464 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6518 18:41:30.631496 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6519 18:41:30.657936 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6520 18:41:30.679643 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6521 18:41:30.707241 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6522 18:41:30.732131 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6523 18:41:30.751024 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6524 18:41:30.774854 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6525 18:41:30.795168 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6526 18:41:30.822492 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6527 18:41:30.841924 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6528 18:41:30.861192 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6529 18:41:30.884552 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6530 18:41:30.908176 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6531 18:41:30.925873 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6532 18:41:30.945971 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6533 18:41:30.971648 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6534 18:41:30.989422 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6535 18:41:31.008086 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6536 18:41:31.025652 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6537 18:41:31.042368 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6538 18:41:31.089865 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6539 18:41:31.115199 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6540 18:41:31.201610 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6541 18:41:31.277053 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6542 18:41:31.304312 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6543 18:41:31.330441 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6544 18:41:31.351105 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6545 18:41:31.416284 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6546 18:41:31.468937 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6547 18:41:31.529979 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6548 18:41:31.550009 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6549 18:41:31.567015 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6550 18:41:31.615827 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6551 18:41:31.638493 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6552 18:41:31.660302 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6553 18:41:31.684406 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6554 18:41:31.729155 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6555 18:41:31.803447 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6556 18:41:31.914750
6557 18:41:31.917878 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6558 18:41:31.918298
6559 18:41:31.921169 debian-bookworm-arm64 login: root (automatic login)
6560 18:41:31.921627
6561 18:41:32.246817 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
6562 18:41:32.247332
6563 18:41:32.253411 The programs included with the Debian GNU/Linux system are free software;
6564 18:41:32.259508 the exact distribution terms for each program are described in the
6565 18:41:32.263039 individual files in /usr/share/doc/*/copyright.
6566 18:41:32.263493
6567 18:41:32.269655 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6568 18:41:32.272718 permitted by applicable law.
6569 18:41:33.512219 Matched prompt #10: / #
6571 18:41:33.513421 Setting prompt string to ['/ #']
6572 18:41:33.514023 end: 2.2.5.1 login-action (duration 00:00:20) [common]
6574 18:41:33.515097 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
6575 18:41:33.515535 start: 2.2.6 expect-shell-connection (timeout 00:03:40) [common]
6576 18:41:33.515886 Setting prompt string to ['/ #']
6577 18:41:33.516185 Forcing a shell prompt, looking for ['/ #']
6579 18:41:33.566960 / #
6580 18:41:33.567547 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6581 18:41:33.567961 Waiting using forced prompt support (timeout 00:02:30)
6582 18:41:33.573600
6583 18:41:33.574498 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6584 18:41:33.574969 start: 2.2.7 export-device-env (timeout 00:03:40) [common]
6586 18:41:33.676199 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs'
6587 18:41:33.682849 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291499/extract-nfsrootfs-0oz6ejhs'
6589 18:41:33.784494 / # export NFS_SERVER_IP='192.168.201.1'
6590 18:41:33.790692 export NFS_SERVER_IP='192.168.201.1'
6591 18:41:33.791502 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6592 18:41:33.791959 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
6593 18:41:33.792405 end: 2 depthcharge-action (duration 00:01:21) [common]
6594 18:41:33.792850 start: 3 lava-test-retry (timeout 00:07:58) [common]
6595 18:41:33.793282 start: 3.1 lava-test-shell (timeout 00:07:58) [common]
6596 18:41:33.793675 Using namespace: common
6598 18:41:33.894786 / # #
6599 18:41:33.895374 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6600 18:41:33.900805 #
6601 18:41:33.901607 Using /lava-14291499
6603 18:41:34.002678 / # export SHELL=/bin/bash
6604 18:41:34.008644 export SHELL=/bin/bash
6606 18:41:34.110352 / # . /lava-14291499/environment
6607 18:41:34.116413 . /lava-14291499/environment
6609 18:41:34.223975 / # /lava-14291499/bin/lava-test-runner /lava-14291499/0
6610 18:41:34.224558 Test shell timeout: 10s (minimum of the action and connection timeout)
6611 18:41:34.229975 /lava-14291499/bin/lava-test-runner /lava-14291499/0
6612 18:41:34.514432 + export TESTRUN_ID=0_timesync-off
6613 18:41:34.517611 + TESTRUN_ID=0_timesync-off
6614 18:41:34.520874 + cd /lava-14291499/0/tests/0_timesync-off
6615 18:41:34.524351 ++ cat uuid
6616 18:41:34.524820 + UUID=14291499_1.6.2.3.1
6617 18:41:34.527583 + set +x
6618 18:41:34.530898 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291499_1.6.2.3.1>
6619 18:41:34.531575 Received signal: <STARTRUN> 0_timesync-off 14291499_1.6.2.3.1
6620 18:41:34.531951 Starting test lava.0_timesync-off (14291499_1.6.2.3.1)
6621 18:41:34.532346 Skipping test definition patterns.
6622 18:41:34.534155 + systemctl stop systemd-timesyncd
6623 18:41:34.594940 + set +x
6624 18:41:34.598079 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291499_1.6.2.3.1>
6625 18:41:34.598774 Received signal: <ENDRUN> 0_timesync-off 14291499_1.6.2.3.1
6626 18:41:34.599207 Ending use of test pattern.
6627 18:41:34.599540 Ending test lava.0_timesync-off (14291499_1.6.2.3.1), duration 0.07
6629 18:41:34.685383 + export TESTRUN_ID=1_kselftest-arm64
6630 18:41:34.685969 + TESTRUN_ID=1_kselftest-arm64
6631 18:41:34.691883 + cd /lava-14291499/0/tests/1_kselftest-arm64
6632 18:41:34.692311 ++ cat uuid
6633 18:41:34.695393 + UUID=14291499_1.6.2.3.5
6634 18:41:34.695801 + set +x
6635 18:41:34.701894 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14291499_1.6.2.3.5>
6636 18:41:34.702587 Received signal: <STARTRUN> 1_kselftest-arm64 14291499_1.6.2.3.5
6637 18:41:34.702958 Starting test lava.1_kselftest-arm64 (14291499_1.6.2.3.5)
6638 18:41:34.703354 Skipping test definition patterns.
6639 18:41:34.705072 + cd ./automated/linux/kselftest/
6640 18:41:34.730984 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6641 18:41:34.784497 INFO: install_deps skipped
6642 18:41:35.280896 --2024-06-11 18:41:35-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6643 18:41:35.291831 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6644 18:41:35.427842 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6645 18:41:35.564407 HTTP request sent, awaiting response... 200 OK
6646 18:41:35.567711 Length: 1647744 (1.6M) [application/octet-stream]
6647 18:41:35.570933 Saving to: 'kselftest_armhf.tar.gz'
6648 18:41:35.571434
6649 18:41:35.571769
6650 18:41:35.838274 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6651 18:41:36.110601 kselftest_armhf.tar 2%[ ] 47.81K 175KB/s
6652 18:41:36.430495 kselftest_armhf.tar 13%[=> ] 214.67K 393KB/s
6653 18:41:36.569819 kselftest_armhf.tar 50%[=========> ] 819.89K 947KB/s
6654 18:41:36.576249 kselftest_armhf.tar 100%[===================>] 1.57M 1.56MB/s in 1.0s
6655 18:41:36.576349
6656 18:41:36.722943 2024-06-11 18:41:36 (1.56 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
6657 18:41:36.723425
6658 18:41:40.909609 skiplist:
6659 18:41:40.912983 ========================================
6660 18:41:40.916171 ========================================
6661 18:41:40.957211 arm64:tags_test
6662 18:41:40.960597 arm64:run_tags_test.sh
6663 18:41:40.960703 arm64:fake_sigreturn_bad_magic
6664 18:41:40.964040 arm64:fake_sigreturn_bad_size
6665 18:41:40.966992 arm64:fake_sigreturn_bad_size_for_magic0
6666 18:41:40.970307 arm64:fake_sigreturn_duplicated_fpsimd
6667 18:41:40.973461 arm64:fake_sigreturn_misaligned_sp
6668 18:41:40.977004 arm64:fake_sigreturn_missing_fpsimd
6669 18:41:40.980119 arm64:fake_sigreturn_sme_change_vl
6670 18:41:40.983282 arm64:fake_sigreturn_sve_change_vl
6671 18:41:40.986584 arm64:mangle_pstate_invalid_compat_toggle
6672 18:41:40.989739 arm64:mangle_pstate_invalid_daif_bits
6673 18:41:40.996295 arm64:mangle_pstate_invalid_mode_el1h
6674 18:41:40.999541 arm64:mangle_pstate_invalid_mode_el1t
6675 18:41:41.003029 arm64:mangle_pstate_invalid_mode_el2h
6676 18:41:41.006161 arm64:mangle_pstate_invalid_mode_el2t
6677 18:41:41.009758 arm64:mangle_pstate_invalid_mode_el3h
6678 18:41:41.012748 arm64:mangle_pstate_invalid_mode_el3t
6679 18:41:41.012838 arm64:sme_trap_no_sm
6680 18:41:41.015941 arm64:sme_trap_non_streaming
6681 18:41:41.019492 arm64:sme_trap_za
6682 18:41:41.019595 arm64:sme_vl
6683 18:41:41.019666 arm64:ssve_regs
6684 18:41:41.022758 arm64:sve_regs
6685 18:41:41.022847 arm64:sve_vl
6686 18:41:41.025847 arm64:za_no_regs
6687 18:41:41.025937 arm64:za_regs
6688 18:41:41.026007 arm64:pac
6689 18:41:41.029486 arm64:fp-stress
6690 18:41:41.029898 arm64:sve-ptrace
6691 18:41:41.032716 arm64:sve-probe-vls
6692 18:41:41.033195 arm64:vec-syscfg
6693 18:41:41.036132 arm64:za-fork
6694 18:41:41.036540 arm64:za-ptrace
6695 18:41:41.039370 arm64:check_buffer_fill
6696 18:41:41.042442 arm64:check_child_memory
6697 18:41:41.042853 arm64:check_gcr_el1_cswitch
6698 18:41:41.045666 arm64:check_ksm_options
6699 18:41:41.048912 arm64:check_mmap_options
6700 18:41:41.049372 arm64:check_prctl
6701 18:41:41.052503 arm64:check_tags_inclusion
6702 18:41:41.055596 arm64:check_user_mem
6703 18:41:41.056025 arm64:btitest
6704 18:41:41.056348 arm64:nobtitest
6705 18:41:41.058739 arm64:hwcap
6706 18:41:41.059150 arm64:ptrace
6707 18:41:41.061980 arm64:syscall-abi
6708 18:41:41.062391 arm64:tpidr2
6709 18:41:41.065346 ============== Tests to run ===============
6710 18:41:41.068370 arm64:tags_test
6711 18:41:41.068782 arm64:run_tags_test.sh
6712 18:41:41.071786 arm64:fake_sigreturn_bad_magic
6713 18:41:41.074892 arm64:fake_sigreturn_bad_size
6714 18:41:41.078238 arm64:fake_sigreturn_bad_size_for_magic0
6715 18:41:41.081581 arm64:fake_sigreturn_duplicated_fpsimd
6716 18:41:41.084941 arm64:fake_sigreturn_misaligned_sp
6717 18:41:41.088164 arm64:fake_sigreturn_missing_fpsimd
6718 18:41:41.091088 arm64:fake_sigreturn_sme_change_vl
6719 18:41:41.094741 arm64:fake_sigreturn_sve_change_vl
6720 18:41:41.097798 arm64:mangle_pstate_invalid_compat_toggle
6721 18:41:41.100921 arm64:mangle_pstate_invalid_daif_bits
6722 18:41:41.104112 arm64:mangle_pstate_invalid_mode_el1h
6723 18:41:41.107743 arm64:mangle_pstate_invalid_mode_el1t
6724 18:41:41.110779 arm64:mangle_pstate_invalid_mode_el2h
6725 18:41:41.114004 arm64:mangle_pstate_invalid_mode_el2t
6726 18:41:41.117560 arm64:mangle_pstate_invalid_mode_el3h
6727 18:41:41.123705 arm64:mangle_pstate_invalid_mode_el3t
6728 18:41:41.124119 arm64:sme_trap_no_sm
6729 18:41:41.127188 arm64:sme_trap_non_streaming
6730 18:41:41.127831 arm64:sme_trap_za
6731 18:41:41.130791 arm64:sme_vl
6732 18:41:41.131300 arm64:ssve_regs
6733 18:41:41.133963 arm64:sve_regs
6734 18:41:41.134556 arm64:sve_vl
6735 18:41:41.137184 arm64:za_no_regs
6736 18:41:41.137615 arm64:za_regs
6737 18:41:41.137943 arm64:pac
6738 18:41:41.140305 arm64:fp-stress
6739 18:41:41.140766 arm64:sve-ptrace
6740 18:41:41.143327 arm64:sve-probe-vls
6741 18:41:41.143782 arm64:vec-syscfg
6742 18:41:41.146618 arm64:za-fork
6743 18:41:41.147021 arm64:za-ptrace
6744 18:41:41.150017 arm64:check_buffer_fill
6745 18:41:41.150497 arm64:check_child_memory
6746 18:41:41.153173 arm64:check_gcr_el1_cswitch
6747 18:41:41.156614 arm64:check_ksm_options
6748 18:41:41.159694 arm64:check_mmap_options
6749 18:41:41.160115 arm64:check_prctl
6750 18:41:41.163059 arm64:check_tags_inclusion
6751 18:41:41.163466 arm64:check_user_mem
6752 18:41:41.166268 arm64:btitest
6753 18:41:41.166702 arm64:nobtitest
6754 18:41:41.169562 arm64:hwcap
6755 18:41:41.169973 arm64:ptrace
6756 18:41:41.170288 arm64:syscall-abi
6757 18:41:41.172686 arm64:tpidr2
6758 18:41:41.176212 ===========End Tests to run ===============
6759 18:41:41.179237 shardfile-arm64 pass
6760 18:41:41.439758 <12>[ 27.767864] kselftest: Running tests in arm64
6761 18:41:41.450885 TAP version 13
6762 18:41:41.465953 1..48
6763 18:41:41.483355 # selftests: arm64: tags_test
6764 18:41:41.949001 ok 1 selftests: arm64: tags_test
6765 18:41:41.967241 # selftests: arm64: run_tags_test.sh
6766 18:41:42.026455 # --------------------
6767 18:41:42.029560 # running tags test
6768 18:41:42.030079 # --------------------
6769 18:41:42.032904 # [PASS]
6770 18:41:42.035867 ok 2 selftests: arm64: run_tags_test.sh
6771 18:41:42.052679 # selftests: arm64: fake_sigreturn_bad_magic
6772 18:41:42.124753 # Registered handlers for all signals.
6773 18:41:42.125273 # Detected MINSTKSIGSZ:4720
6774 18:41:42.127588 # Testcase initialized.
6775 18:41:42.130892 # uc context validated.
6776 18:41:42.134187 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6777 18:41:42.137283 # Handled SIG_COPYCTX
6778 18:41:42.140818 # Available space:3568
6779 18:41:42.143931 # Using badly built context - ERR: BAD MAGIC !
6780 18:41:42.153931 # SIG_OK -- SP:0xFFFFF6E10370 si_addr@:0xfffff6e10370 si_code:2 token@:0xfffff6e0f110 offset:-4704
6781 18:41:42.154348 # ==>> completed. PASS(1)
6782 18:41:42.163668 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
6783 18:41:42.169987 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6E0F110
6784 18:41:42.173167 ok 3 selftests: arm64: fake_sigreturn_bad_magic
6785 18:41:42.176479 # selftests: arm64: fake_sigreturn_bad_size
6786 18:41:42.237405 # Registered handlers for all signals.
6787 18:41:42.237987 # Detected MINSTKSIGSZ:4720
6788 18:41:42.240796 # Testcase initialized.
6789 18:41:42.244087 # uc context validated.
6790 18:41:42.247297 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6791 18:41:42.250234 # Handled SIG_COPYCTX
6792 18:41:42.253466 # Available space:3568
6793 18:41:42.253934 # uc context validated.
6794 18:41:42.260246 # Using badly built context - ERR: Bad size for esr_context
6795 18:41:42.270055 # SIG_OK -- SP:0xFFFFEDB0B950 si_addr@:0xffffedb0b950 si_code:2 token@:0xffffedb0a6f0 offset:-4704
6796 18:41:42.270655 # ==>> completed. PASS(1)
6797 18:41:42.279741 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
6798 18:41:42.286118 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEDB0A6F0
6799 18:41:42.289597 ok 4 selftests: arm64: fake_sigreturn_bad_size
6800 18:41:42.292675 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
6801 18:41:42.341499 # Registered handlers for all signals.
6802 18:41:42.342020 # Detected MINSTKSIGSZ:4720
6803 18:41:42.344536 # Testcase initialized.
6804 18:41:42.347977 # uc context validated.
6805 18:41:42.351082 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6806 18:41:42.354255 # Handled SIG_COPYCTX
6807 18:41:42.354665 # Available space:3568
6808 18:41:42.360610 # Using badly built context - ERR: Bad size for terminator
6809 18:41:42.370318 # SIG_OK -- SP:0xFFFFE40C72E0 si_addr@:0xffffe40c72e0 si_code:2 token@:0xffffe40c6080 offset:-4704
6810 18:41:42.373618 # ==>> completed. PASS(1)
6811 18:41:42.380042 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
6812 18:41:42.386713 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE40C6080
6813 18:41:42.393280 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
6814 18:41:42.396428 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
6815 18:41:42.458976 # Registered handlers for all signals.
6816 18:41:42.459588 # Detected MINSTKSIGSZ:4720
6817 18:41:42.462290 # Testcase initialized.
6818 18:41:42.465509 # uc context validated.
6819 18:41:42.468431 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6820 18:41:42.471986 # Handled SIG_COPYCTX
6821 18:41:42.475111 # Available space:3568
6822 18:41:42.478155 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
6823 18:41:42.488167 # SIG_OK -- SP:0xFFFFF34C4D10 si_addr@:0xfffff34c4d10 si_code:2 token@:0xfffff34c3ab0 offset:-4704
6824 18:41:42.491380 # ==>> completed. PASS(1)
6825 18:41:42.498071 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
6826 18:41:42.504436 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF34C3AB0
6827 18:41:42.507960 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
6828 18:41:42.514593 # selftests: arm64: fake_sigreturn_misaligned_sp
6829 18:41:42.574688 # Registered handlers for all signals.
6830 18:41:42.575213 # Detected MINSTKSIGSZ:4720
6831 18:41:42.577661 # Testcase initialized.
6832 18:41:42.580763 # uc context validated.
6833 18:41:42.584247 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6834 18:41:42.587539 # Handled SIG_COPYCTX
6835 18:41:42.597365 # SIG_OK -- SP:0xFFFFFAD4B393 si_addr@:0xfffffad4b393 si_code:2 token@:0xfffffad4b393 offset:0
6836 18:41:42.597858 # ==>> completed. PASS(1)
6837 18:41:42.603790 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
6838 18:41:42.610408 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFAD4B393
6839 18:41:42.616669 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
6840 18:41:42.619879 # selftests: arm64: fake_sigreturn_missing_fpsimd
6841 18:41:42.685273 # Registered handlers for all signals.
6842 18:41:42.685863 # Detected MINSTKSIGSZ:4720
6843 18:41:42.690290 # Testcase initialized.
6844 18:41:42.691358 # uc context validated.
6845 18:41:42.694353 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
6846 18:41:42.697872 # Handled SIG_COPYCTX
6847 18:41:42.700970 # Mangling template header. Spare space:4096
6848 18:41:42.704456 # Using badly built context - ERR: Missing FPSIMD
6849 18:41:42.714175 # SIG_OK -- SP:0xFFFFC8A641F0 si_addr@:0xffffc8a641f0 si_code:2 token@:0xffffc8a62f90 offset:-4704
6850 18:41:42.717254 # ==>> completed. PASS(1)
6851 18:41:42.724074 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
6852 18:41:42.730279 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC8A62F90
6853 18:41:42.737148 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
6854 18:41:42.740314 # selftests: arm64: fake_sigreturn_sme_change_vl
6855 18:41:42.789260 # Registered handlers for all signals.
6856 18:41:42.789828 # Detected MINSTKSIGSZ:4720
6857 18:41:42.792335 # ==>> completed. SKIP.
6858 18:41:42.798876 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
6859 18:41:42.805100 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
6860 18:41:42.808585 # selftests: arm64: fake_sigreturn_sve_change_vl
6861 18:41:42.884863 # Registered handlers for all signals.
6862 18:41:42.885380 # Detected MINSTKSIGSZ:4720
6863 18:41:42.888026 # ==>> completed. SKIP.
6864 18:41:42.894328 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
6865 18:41:42.897660 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
6866 18:41:42.913187 # selftests: arm64: mangle_pstate_invalid_compat_toggle
6867 18:41:42.997798 # Registered handlers for all signals.
6868 18:41:42.998376 # Detected MINSTKSIGSZ:4720
6869 18:41:43.001089 # Testcase initialized.
6870 18:41:43.004332 # uc context validated.
6871 18:41:43.004747 # Handled SIG_TRIG
6872 18:41:43.014143 # SIG_OK -- SP:0xFFFFE98B8ED0 si_addr@:0xffffe98b8ed0 si_code:2 token@:(nil) offset:-281474599980752
6873 18:41:43.017249 # ==>> completed. PASS(1)
6874 18:41:43.023967 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
6875 18:41:43.030166 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
6876 18:41:43.033543 # selftests: arm64: mangle_pstate_invalid_daif_bits
6877 18:41:43.095435 # Registered handlers for all signals.
6878 18:41:43.095962 # Detected MINSTKSIGSZ:4720
6879 18:41:43.098440 # Testcase initialized.
6880 18:41:43.101857 # uc context validated.
6881 18:41:43.102289 # Handled SIG_TRIG
6882 18:41:43.111507 # SIG_OK -- SP:0xFFFFCC866990 si_addr@:0xffffcc866990 si_code:2 token@:(nil) offset:-281474113104272
6883 18:41:43.114874 # ==>> completed. PASS(1)
6884 18:41:43.121590 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
6885 18:41:43.127736 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
6886 18:41:43.131100 # selftests: arm64: mangle_pstate_invalid_mode_el1h
6887 18:41:43.185524 # Registered handlers for all signals.
6888 18:41:43.186050 # Detected MINSTKSIGSZ:4720
6889 18:41:43.188658 # Testcase initialized.
6890 18:41:43.191925 # uc context validated.
6891 18:41:43.192460 # Handled SIG_TRIG
6892 18:41:43.201563 # SIG_OK -- SP:0xFFFFC17E48A0 si_addr@:0xffffc17e48a0 si_code:2 token@:(nil) offset:-281473928022176
6893 18:41:43.204827 # ==>> completed. PASS(1)
6894 18:41:43.211133 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
6895 18:41:43.214409 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
6896 18:41:43.220883 # selftests: arm64: mangle_pstate_invalid_mode_el1t
6897 18:41:43.284281 # Registered handlers for all signals.
6898 18:41:43.284812 # Detected MINSTKSIGSZ:4720
6899 18:41:43.287408 # Testcase initialized.
6900 18:41:43.290640 # uc context validated.
6901 18:41:43.291107 # Handled SIG_TRIG
6902 18:41:43.300630 # SIG_OK -- SP:0xFFFFC7BD3760 si_addr@:0xffffc7bd3760 si_code:2 token@:(nil) offset:-281474032809824
6903 18:41:43.303648 # ==>> completed. PASS(1)
6904 18:41:43.310382 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
6905 18:41:43.313630 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
6906 18:41:43.319998 # selftests: arm64: mangle_pstate_invalid_mode_el2h
6907 18:41:43.376103 # Registered handlers for all signals.
6908 18:41:43.376627 # Detected MINSTKSIGSZ:4720
6909 18:41:43.379362 # Testcase initialized.
6910 18:41:43.382117 # uc context validated.
6911 18:41:43.382537 # Handled SIG_TRIG
6912 18:41:43.392188 # SIG_OK -- SP:0xFFFFE62EA1D0 si_addr@:0xffffe62ea1d0 si_code:2 token@:(nil) offset:-281474543559120
6913 18:41:43.395290 # ==>> completed. PASS(1)
6914 18:41:43.401897 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
6915 18:41:43.405062 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
6916 18:41:43.411451 # selftests: arm64: mangle_pstate_invalid_mode_el2t
6917 18:41:43.486371 # Registered handlers for all signals.
6918 18:41:43.486908 # Detected MINSTKSIGSZ:4720
6919 18:41:43.489556 # Testcase initialized.
6920 18:41:43.492900 # uc context validated.
6921 18:41:43.493460 # Handled SIG_TRIG
6922 18:41:43.502318 # SIG_OK -- SP:0xFFFFF90132E0 si_addr@:0xfffff90132e0 si_code:2 token@:(nil) offset:-281474859348704
6923 18:41:43.505737 # ==>> completed. PASS(1)
6924 18:41:43.512255 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
6925 18:41:43.515614 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
6926 18:41:43.522077 # selftests: arm64: mangle_pstate_invalid_mode_el3h
6927 18:41:43.573275 # Registered handlers for all signals.
6928 18:41:43.573840 # Detected MINSTKSIGSZ:4720
6929 18:41:43.576457 # Testcase initialized.
6930 18:41:43.579981 # uc context validated.
6931 18:41:43.580515 # Handled SIG_TRIG
6932 18:41:43.589332 # SIG_OK -- SP:0xFFFFD569FBF0 si_addr@:0xffffd569fbf0 si_code:2 token@:(nil) offset:-281474262236144
6933 18:41:43.592565 # ==>> completed. PASS(1)
6934 18:41:43.599061 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
6935 18:41:43.602221 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
6936 18:41:43.609014 # selftests: arm64: mangle_pstate_invalid_mode_el3t
6937 18:41:43.681767 # Registered handlers for all signals.
6938 18:41:43.682312 # Detected MINSTKSIGSZ:4720
6939 18:41:43.684820 # Testcase initialized.
6940 18:41:43.688000 # uc context validated.
6941 18:41:43.688420 # Handled SIG_TRIG
6942 18:41:43.697989 # SIG_OK -- SP:0xFFFFD11599F0 si_addr@:0xffffd11599f0 si_code:2 token@:(nil) offset:-281474189597168
6943 18:41:43.701141 # ==>> completed. PASS(1)
6944 18:41:43.707574 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
6945 18:41:43.710752 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
6946 18:41:43.714342 # selftests: arm64: sme_trap_no_sm
6947 18:41:43.786452 # Registered handlers for all signals.
6948 18:41:43.786959 # Detected MINSTKSIGSZ:4720
6949 18:41:43.790195 # ==>> completed. SKIP.
6950 18:41:43.799596 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
6951 18:41:43.802814 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
6952 18:41:43.809533 # selftests: arm64: sme_trap_non_streaming
6953 18:41:43.893746 # Registered handlers for all signals.
6954 18:41:43.894246 # Detected MINSTKSIGSZ:4720
6955 18:41:43.897102 # ==>> completed. SKIP.
6956 18:41:43.906633 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
6957 18:41:43.912941 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
6958 18:41:43.916199 # selftests: arm64: sme_trap_za
6959 18:41:43.990325 # Registered handlers for all signals.
6960 18:41:43.990847 # Detected MINSTKSIGSZ:4720
6961 18:41:43.993733 # Testcase initialized.
6962 18:41:44.003426 # SIG_OK -- SP:0xFFFFF180F710 si_addr@:0xaaaacaf42510 si_code:1 token@:(nil) offset:-187650526160144
6963 18:41:44.006443 # ==>> completed. PASS(1)
6964 18:41:44.013100 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
6965 18:41:44.016561 ok 21 selftests: arm64: sme_trap_za
6966 18:41:44.016978 # selftests: arm64: sme_vl
6967 18:41:44.091618 # Registered handlers for all signals.
6968 18:41:44.092111 # Detected MINSTKSIGSZ:4720
6969 18:41:44.094982 # ==>> completed. SKIP.
6970 18:41:44.101545 # # SME VL :: Check that we get the right SME VL reported
6971 18:41:44.104500 ok 22 selftests: arm64: sme_vl # SKIP
6972 18:41:44.112088 # selftests: arm64: ssve_regs
6973 18:41:44.180008 # Registered handlers for all signals.
6974 18:41:44.180501 # Detected MINSTKSIGSZ:4720
6975 18:41:44.183333 # ==>> completed. SKIP.
6976 18:41:44.190002 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
6977 18:41:44.196310 ok 23 selftests: arm64: ssve_regs # SKIP
6978 18:41:44.200296 # selftests: arm64: sve_regs
6979 18:41:44.277876 # Registered handlers for all signals.
6980 18:41:44.278631 # Detected MINSTKSIGSZ:4720
6981 18:41:44.281131 # ==>> completed. SKIP.
6982 18:41:44.287825 # # SVE registers :: Check that we get the right SVE registers reported
6983 18:41:44.290911 ok 24 selftests: arm64: sve_regs # SKIP
6984 18:41:44.300542 # selftests: arm64: sve_vl
6985 18:41:44.389228 # Registered handlers for all signals.
6986 18:41:44.389775 # Detected MINSTKSIGSZ:4720
6987 18:41:44.392801 # ==>> completed. SKIP.
6988 18:41:44.398777 # # SVE VL :: Check that we get the right SVE VL reported
6989 18:41:44.402117 ok 25 selftests: arm64: sve_vl # SKIP
6990 18:41:44.409036 # selftests: arm64: za_no_regs
6991 18:41:44.490024 # Registered handlers for all signals.
6992 18:41:44.490541 # Detected MINSTKSIGSZ:4720
6993 18:41:44.493294 # ==>> completed. SKIP.
6994 18:41:44.499730 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
6995 18:41:44.502821 ok 26 selftests: arm64: za_no_regs # SKIP
6996 18:41:44.513114 # selftests: arm64: za_regs
6997 18:41:44.592117 # Registered handlers for all signals.
6998 18:41:44.592647 # Detected MINSTKSIGSZ:4720
6999 18:41:44.595337 # ==>> completed. SKIP.
7000 18:41:44.601705 # # ZA register :: Check that we get the right ZA registers reported
7001 18:41:44.604871 ok 27 selftests: arm64: za_regs # SKIP
7002 18:41:44.609338 # selftests: arm64: pac
7003 18:41:44.674057 # TAP version 13
7004 18:41:44.674605 # 1..7
7005 18:41:44.677548 # # Starting 7 tests from 1 test cases.
7006 18:41:44.680470 # # RUN global.corrupt_pac ...
7007 18:41:44.686671 # # SKIP PAUTH not enabled
7008 18:41:44.690077 # # OK global.corrupt_pac
7009 18:41:44.690495 # ok 1 # SKIP PAUTH not enabled
7010 18:41:44.696704 # # RUN global.pac_instructions_not_nop ...
7011 18:41:44.699703 # # SKIP PAUTH not enabled
7012 18:41:44.703027 # # OK global.pac_instructions_not_nop
7013 18:41:44.706326 # ok 2 # SKIP PAUTH not enabled
7014 18:41:44.713035 # # RUN global.pac_instructions_not_nop_generic ...
7015 18:41:44.716090 # # SKIP Generic PAUTH not enabled
7016 18:41:44.722685 # # OK global.pac_instructions_not_nop_generic
7017 18:41:44.725926 # ok 3 # SKIP Generic PAUTH not enabled
7018 18:41:44.729244 # # RUN global.single_thread_different_keys ...
7019 18:41:44.732465 # # SKIP PAUTH not enabled
7020 18:41:44.738932 # # OK global.single_thread_different_keys
7021 18:41:44.742184 # ok 4 # SKIP PAUTH not enabled
7022 18:41:44.745605 # # RUN global.exec_changed_keys ...
7023 18:41:44.748821 # # SKIP PAUTH not enabled
7024 18:41:44.752311 # # OK global.exec_changed_keys
7025 18:41:44.755522 # ok 5 # SKIP PAUTH not enabled
7026 18:41:44.762290 # # RUN global.context_switch_keep_keys ...
7027 18:41:44.765078 # # SKIP PAUTH not enabled
7028 18:41:44.768321 # # OK global.context_switch_keep_keys
7029 18:41:44.772017 # ok 6 # SKIP PAUTH not enabled
7030 18:41:44.778570 # # RUN global.context_switch_keep_keys_generic ...
7031 18:41:44.781693 # # SKIP Generic PAUTH not enabled
7032 18:41:44.784747 # # OK global.context_switch_keep_keys_generic
7033 18:41:44.791629 # ok 7 # SKIP Generic PAUTH not enabled
7034 18:41:44.792144 # # PASSED: 7 / 7 tests passed.
7035 18:41:44.798053 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
7036 18:41:44.801315 ok 28 selftests: arm64: pac
7037 18:41:44.804263 # selftests: arm64: fp-stress
7038 18:41:51.659063 <6>[ 37.989882] vaux18: disabling
7039 18:41:51.662111 <6>[ 37.993259] vio28: disabling
7040 18:41:54.758646 # TAP version 13
7041 18:41:54.759309 # 1..16
7042 18:41:54.761897 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
7043 18:41:54.765338 # # Will run for 10s
7044 18:41:54.765888 # # Started FPSIMD-0-0
7045 18:41:54.768370 # # Started FPSIMD-0-1
7046 18:41:54.771537 # # Started FPSIMD-1-0
7047 18:41:54.771952 # # Started FPSIMD-1-1
7048 18:41:54.775061 # # Started FPSIMD-2-0
7049 18:41:54.778039 # # Started FPSIMD-2-1
7050 18:41:54.778462 # # Started FPSIMD-3-0
7051 18:41:54.781521 # # Started FPSIMD-3-1
7052 18:41:54.784660 # # Started FPSIMD-4-0
7053 18:41:54.785088 # # Started FPSIMD-4-1
7054 18:41:54.787956 # # Started FPSIMD-5-0
7055 18:41:54.791200 # # Started FPSIMD-5-1
7056 18:41:54.791613 # # Started FPSIMD-6-0
7057 18:41:54.794531 # # Started FPSIMD-6-1
7058 18:41:54.794944 # # Started FPSIMD-7-0
7059 18:41:54.797549 # # Started FPSIMD-7-1
7060 18:41:54.800699 # # FPSIMD-0-0: Vector length: 128 bits
7061 18:41:54.803803 # # FPSIMD-0-0: PID: 1182
7062 18:41:54.807224 # # FPSIMD-1-1: Vector length: 128 bits
7063 18:41:54.810314 # # FPSIMD-1-1: PID: 1185
7064 18:41:54.813755 # # FPSIMD-1-0: Vector length: 128 bits
7065 18:41:54.813851 # # FPSIMD-1-0: PID: 1184
7066 18:41:54.820395 # # FPSIMD-0-1: Vector length: 128 bits
7067 18:41:54.820499 # # FPSIMD-0-1: PID: 1183
7068 18:41:54.823664 # # FPSIMD-2-0: Vector length: 128 bits
7069 18:41:54.826958 # # FPSIMD-2-0: PID: 1186
7070 18:41:54.830194 # # FPSIMD-4-1: Vector length: 128 bits
7071 18:41:54.833732 # # FPSIMD-4-1: PID: 1191
7072 18:41:54.837166 # # FPSIMD-3-0: Vector length: 128 bits
7073 18:41:54.839831 # # FPSIMD-3-0: PID: 1188
7074 18:41:54.843181 # # FPSIMD-3-1: Vector length: 128 bits
7075 18:41:54.846820 # # FPSIMD-3-1: PID: 1189
7076 18:41:54.849899 # # FPSIMD-6-0: Vector length: 128 bits
7077 18:41:54.850167 # # FPSIMD-6-0: PID: 1194
7078 18:41:54.856133 # # FPSIMD-5-0: Vector length: 128 bits
7079 18:41:54.856358 # # FPSIMD-5-0: PID: 1192
7080 18:41:54.859200 # # FPSIMD-6-1: Vector length: 128 bits
7081 18:41:54.862639 # # FPSIMD-6-1: PID: 1195
7082 18:41:54.866135 # # FPSIMD-7-1: Vector length: 128 bits
7083 18:41:54.869534 # # FPSIMD-7-1: PID: 1197
7084 18:41:54.872723 # # FPSIMD-2-1: Vector length: 128 bits
7085 18:41:54.876322 # # FPSIMD-2-1: PID: 1187
7086 18:41:54.879446 # # FPSIMD-5-1: Vector length: 128 bits
7087 18:41:54.882423 # # FPSIMD-5-1: PID: 1193
7088 18:41:54.885556 # # FPSIMD-7-0: Vector length: 128 bits
7089 18:41:54.885975 # # FPSIMD-7-0: PID: 1196
7090 18:41:54.889180 # # FPSIMD-4-0: Vector length: 128 bits
7091 18:41:54.892256 # # FPSIMD-4-0: PID: 1190
7092 18:41:54.895728 # # Finishing up...
7093 18:41:54.901897 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=768399, signals=10
7094 18:41:54.908505 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=709759, signals=10
7095 18:41:54.914935 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=708961, signals=10
7096 18:41:54.921532 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=737371, signals=10
7097 18:41:54.931428 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=895029, signals=10
7098 18:41:54.937980 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=725231, signals=10
7099 18:41:54.944850 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=921710, signals=10
7100 18:41:54.948116 # ok 1 FPSIMD-0-0
7101 18:41:54.948636 # ok 2 FPSIMD-0-1
7102 18:41:54.951463 # ok 3 FPSIMD-1-0
7103 18:41:54.951985 # ok 4 FPSIMD-1-1
7104 18:41:54.954275 # ok 5 FPSIMD-2-0
7105 18:41:54.954687 # ok 6 FPSIMD-2-1
7106 18:41:54.957661 # ok 7 FPSIMD-3-0
7107 18:41:54.958079 # ok 8 FPSIMD-3-1
7108 18:41:54.960567 # ok 9 FPSIMD-4-0
7109 18:41:54.960983 # ok 10 FPSIMD-4-1
7110 18:41:54.963856 # ok 11 FPSIMD-5-0
7111 18:41:54.964272 # ok 12 FPSIMD-5-1
7112 18:41:54.967030 # ok 13 FPSIMD-6-0
7113 18:41:54.967446 # ok 14 FPSIMD-6-1
7114 18:41:54.970480 # ok 15 FPSIMD-7-0
7115 18:41:54.970899 # ok 16 FPSIMD-7-1
7116 18:41:54.980784 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=810728, signals=9
7117 18:41:54.986592 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=894310, signals=10
7118 18:41:54.993018 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=704698, signals=10
7119 18:41:54.999570 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=809657, signals=10
7120 18:41:55.006558 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=910565, signals=10
7121 18:41:55.016100 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=703851, signals=10
7122 18:41:55.022606 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=885725, signals=9
7123 18:41:55.029125 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=739373, signals=10
7124 18:41:55.035804 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=813380, signals=10
7125 18:41:55.042424 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
7126 18:41:55.045481 ok 29 selftests: arm64: fp-stress
7127 18:41:55.045939 # selftests: arm64: sve-ptrace
7128 18:41:55.048858 # TAP version 13
7129 18:41:55.049273 # 1..4104
7130 18:41:55.051863 # ok 2 # SKIP SVE not available
7131 18:41:55.055216 # # Planned tests != run tests (4104 != 1)
7132 18:41:55.061857 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7133 18:41:55.064815 ok 30 selftests: arm64: sve-ptrace # SKIP
7134 18:41:55.068211 # selftests: arm64: sve-probe-vls
7135 18:41:55.068625 # TAP version 13
7136 18:41:55.071601 # 1..2
7137 18:41:55.072016 # ok 2 # SKIP SVE not available
7138 18:41:55.078187 # # Planned tests != run tests (2 != 1)
7139 18:41:55.081072 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7140 18:41:55.084549 ok 31 selftests: arm64: sve-probe-vls # SKIP
7141 18:41:55.087658 # selftests: arm64: vec-syscfg
7142 18:41:55.091207 # TAP version 13
7143 18:41:55.091588 # 1..20
7144 18:41:55.094158 # ok 1 # SKIP SVE not supported
7145 18:41:55.097492 # ok 2 # SKIP SVE not supported
7146 18:41:55.101182 # ok 3 # SKIP SVE not supported
7147 18:41:55.101705 # ok 4 # SKIP SVE not supported
7148 18:41:55.104315 # ok 5 # SKIP SVE not supported
7149 18:41:55.107205 # ok 6 # SKIP SVE not supported
7150 18:41:55.110556 # ok 7 # SKIP SVE not supported
7151 18:41:55.113810 # ok 8 # SKIP SVE not supported
7152 18:41:55.117081 # ok 9 # SKIP SVE not supported
7153 18:41:55.120484 # ok 10 # SKIP SVE not supported
7154 18:41:55.124117 # ok 11 # SKIP SME not supported
7155 18:41:55.127036 # ok 12 # SKIP SME not supported
7156 18:41:55.127548 # ok 13 # SKIP SME not supported
7157 18:41:55.130037 # ok 14 # SKIP SME not supported
7158 18:41:55.133571 # ok 15 # SKIP SME not supported
7159 18:41:55.137003 # ok 16 # SKIP SME not supported
7160 18:41:55.139965 # ok 17 # SKIP SME not supported
7161 18:41:55.143364 # ok 18 # SKIP SME not supported
7162 18:41:55.146669 # ok 19 # SKIP SME not supported
7163 18:41:55.149559 # ok 20 # SKIP SME not supported
7164 18:41:55.152860 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
7165 18:41:55.156123 ok 32 selftests: arm64: vec-syscfg
7166 18:41:55.159464 # selftests: arm64: za-fork
7167 18:41:55.162655 # TAP version 13
7168 18:41:55.163127 # 1..1
7169 18:41:55.163462 # # PID: 1275
7170 18:41:55.166041 # # SME support not present
7171 18:41:55.166458 # ok 0 skipped
7172 18:41:55.172544 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7173 18:41:55.175740 ok 33 selftests: arm64: za-fork
7174 18:41:55.178971 # selftests: arm64: za-ptrace
7175 18:41:55.231251 # TAP version 13
7176 18:41:55.231761 # 1..1
7177 18:41:55.234435 # ok 2 # SKIP SME not available
7178 18:41:55.240718 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
7179 18:41:55.243827 ok 34 selftests: arm64: za-ptrace # SKIP
7180 18:41:55.255598 # selftests: arm64: check_buffer_fill
7181 18:41:55.350298 # # SKIP: MTE features unavailable
7182 18:41:55.359891 ok 35 selftests: arm64: check_buffer_fill # SKIP
7183 18:41:55.379341 # selftests: arm64: check_child_memory
7184 18:41:55.456131 # # SKIP: MTE features unavailable
7185 18:41:55.465165 ok 36 selftests: arm64: check_child_memory # SKIP
7186 18:41:55.484301 # selftests: arm64: check_gcr_el1_cswitch
7187 18:41:55.559254 # # SKIP: MTE features unavailable
7188 18:41:55.566921 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
7189 18:41:55.584202 # selftests: arm64: check_ksm_options
7190 18:41:55.657220 # # SKIP: MTE features unavailable
7191 18:41:55.664992 ok 38 selftests: arm64: check_ksm_options # SKIP
7192 18:41:55.680745 # selftests: arm64: check_mmap_options
7193 18:41:55.746068 # # SKIP: MTE features unavailable
7194 18:41:55.752711 ok 39 selftests: arm64: check_mmap_options # SKIP
7195 18:41:55.767621 # selftests: arm64: check_prctl
7196 18:41:55.826536 # TAP version 13
7197 18:41:55.827054 # 1..5
7198 18:41:55.829607 # ok 1 check_basic_read
7199 18:41:55.830102 # ok 2 NONE
7200 18:41:55.832895 # ok 3 # SKIP SYNC
7201 18:41:55.833338 # ok 4 # SKIP ASYNC
7202 18:41:55.836212 # ok 5 # SKIP SYNC+ASYNC
7203 18:41:55.842527 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
7204 18:41:55.845921 ok 40 selftests: arm64: check_prctl
7205 18:41:55.849021 # selftests: arm64: check_tags_inclusion
7206 18:41:55.919613 # # SKIP: MTE features unavailable
7207 18:41:55.928925 ok 41 selftests: arm64: check_tags_inclusion # SKIP
7208 18:41:55.942536 # selftests: arm64: check_user_mem
7209 18:41:56.019497 # # SKIP: MTE features unavailable
7210 18:41:56.028055 ok 42 selftests: arm64: check_user_mem # SKIP
7211 18:41:56.045147 # selftests: arm64: btitest
7212 18:41:56.136660 # TAP version 13
7213 18:41:56.137172 # 1..18
7214 18:41:56.140075 # # HWCAP_PACA not present
7215 18:41:56.143009 # # HWCAP2_BTI not present
7216 18:41:56.148033 # # Test binary built for BTI
7217 18:41:56.149262 # ok 1 nohint_func/call_using_br_x0 # SKIP
7218 18:41:56.152553 # ok 1 nohint_func/call_using_br_x16 # SKIP
7219 18:41:56.156195 # ok 1 nohint_func/call_using_blr # SKIP
7220 18:41:56.159271 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7221 18:41:56.165685 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7222 18:41:56.168884 # ok 1 bti_none_func/call_using_blr # SKIP
7223 18:41:56.172296 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7224 18:41:56.175430 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7225 18:41:56.178661 # ok 1 bti_c_func/call_using_blr # SKIP
7226 18:41:56.181906 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7227 18:41:56.185492 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7228 18:41:56.191762 # ok 1 bti_j_func/call_using_blr # SKIP
7229 18:41:56.195013 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7230 18:41:56.198354 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7231 18:41:56.201773 # ok 1 bti_jc_func/call_using_blr # SKIP
7232 18:41:56.205014 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7233 18:41:56.211428 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7234 18:41:56.214658 # ok 1 paciasp_func/call_using_blr # SKIP
7235 18:41:56.217900 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7236 18:41:56.221411 # # WARNING - EXPECTED TEST COUNT WRONG
7237 18:41:56.224504 ok 43 selftests: arm64: btitest
7238 18:41:56.227401 # selftests: arm64: nobtitest
7239 18:41:56.238439 # TAP version 13
7240 18:41:56.238951 # 1..18
7241 18:41:56.241891 # # HWCAP_PACA not present
7242 18:41:56.244839 # # HWCAP2_BTI not present
7243 18:41:56.247971 # # Test binary not built for BTI
7244 18:41:56.251196 # ok 1 nohint_func/call_using_br_x0 # SKIP
7245 18:41:56.254375 # ok 1 nohint_func/call_using_br_x16 # SKIP
7246 18:41:56.257658 # ok 1 nohint_func/call_using_blr # SKIP
7247 18:41:56.260976 # ok 1 bti_none_func/call_using_br_x0 # SKIP
7248 18:41:56.267560 # ok 1 bti_none_func/call_using_br_x16 # SKIP
7249 18:41:56.270646 # ok 1 bti_none_func/call_using_blr # SKIP
7250 18:41:56.273862 # ok 1 bti_c_func/call_using_br_x0 # SKIP
7251 18:41:56.277111 # ok 1 bti_c_func/call_using_br_x16 # SKIP
7252 18:41:56.280430 # ok 1 bti_c_func/call_using_blr # SKIP
7253 18:41:56.283876 # ok 1 bti_j_func/call_using_br_x0 # SKIP
7254 18:41:56.290243 # ok 1 bti_j_func/call_using_br_x16 # SKIP
7255 18:41:56.293306 # ok 1 bti_j_func/call_using_blr # SKIP
7256 18:41:56.296722 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
7257 18:41:56.300100 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
7258 18:41:56.303535 # ok 1 bti_jc_func/call_using_blr # SKIP
7259 18:41:56.306478 # ok 1 paciasp_func/call_using_br_x0 # SKIP
7260 18:41:56.312913 # ok 1 paciasp_func/call_using_br_x16 # SKIP
7261 18:41:56.316282 # ok 1 paciasp_func/call_using_blr # SKIP
7262 18:41:56.319782 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
7263 18:41:56.323089 # # WARNING - EXPECTED TEST COUNT WRONG
7264 18:41:56.326097 ok 44 selftests: arm64: nobtitest
7265 18:41:56.329401 # selftests: arm64: hwcap
7266 18:41:56.346560 # TAP version 13
7267 18:41:56.347058 # 1..28
7268 18:41:56.350027 # ok 1 cpuinfo_match_RNG
7269 18:41:56.352965 # # SIGILL reported for RNG
7270 18:41:56.353513 # ok 2 # SKIP sigill_RNG
7271 18:41:56.356320 # ok 3 cpuinfo_match_SME
7272 18:41:56.359406 # ok 4 sigill_SME
7273 18:41:56.359811 # ok 5 cpuinfo_match_SVE
7274 18:41:56.362841 # ok 6 sigill_SVE
7275 18:41:56.365902 # ok 7 cpuinfo_match_SVE 2
7276 18:41:56.366321 # # SIGILL reported for SVE 2
7277 18:41:56.369137 # ok 8 # SKIP sigill_SVE 2
7278 18:41:56.372401 # ok 9 cpuinfo_match_SVE AES
7279 18:41:56.375951 # # SIGILL reported for SVE AES
7280 18:41:56.378944 # ok 10 # SKIP sigill_SVE AES
7281 18:41:56.382465 # ok 11 cpuinfo_match_SVE2 PMULL
7282 18:41:56.382876 # # SIGILL reported for SVE2 PMULL
7283 18:41:56.385485 # ok 12 # SKIP sigill_SVE2 PMULL
7284 18:41:56.388895 # ok 13 cpuinfo_match_SVE2 BITPERM
7285 18:41:56.391903 # # SIGILL reported for SVE2 BITPERM
7286 18:41:56.395250 # ok 14 # SKIP sigill_SVE2 BITPERM
7287 18:41:56.398574 # ok 15 cpuinfo_match_SVE2 SHA3
7288 18:41:56.402023 # # SIGILL reported for SVE2 SHA3
7289 18:41:56.405132 # ok 16 # SKIP sigill_SVE2 SHA3
7290 18:41:56.408668 # ok 17 cpuinfo_match_SVE2 SM4
7291 18:41:56.411958 # # SIGILL reported for SVE2 SM4
7292 18:41:56.414939 # ok 18 # SKIP sigill_SVE2 SM4
7293 18:41:56.418275 # ok 19 cpuinfo_match_SVE2 I8MM
7294 18:41:56.418868 # # SIGILL reported for SVE2 I8MM
7295 18:41:56.421555 # ok 20 # SKIP sigill_SVE2 I8MM
7296 18:41:56.424768 # ok 21 cpuinfo_match_SVE2 F32MM
7297 18:41:56.428077 # # SIGILL reported for SVE2 F32MM
7298 18:41:56.431330 # ok 22 # SKIP sigill_SVE2 F32MM
7299 18:41:56.434473 # ok 23 cpuinfo_match_SVE2 F64MM
7300 18:41:56.437598 # # SIGILL reported for SVE2 F64MM
7301 18:41:56.440840 # ok 24 # SKIP sigill_SVE2 F64MM
7302 18:41:56.443970 # ok 25 cpuinfo_match_SVE2 BF16
7303 18:41:56.447352 # # SIGILL reported for SVE2 BF16
7304 18:41:56.451137 # ok 26 # SKIP sigill_SVE2 BF16
7305 18:41:56.454030 # ok 27 cpuinfo_match_SVE2 EBF16
7306 18:41:56.454457 # ok 28 # SKIP sigill_SVE2 EBF16
7307 18:41:56.460621 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
7308 18:41:56.464093 ok 45 selftests: arm64: hwcap
7309 18:41:56.466845 # selftests: arm64: ptrace
7310 18:41:56.467270 # TAP version 13
7311 18:41:56.467693 # 1..7
7312 18:41:56.470224 # # Parent is 1517, child is 1518
7313 18:41:56.473626 # ok 1 read_tpidr_one
7314 18:41:56.476631 # ok 2 write_tpidr_one
7315 18:41:56.477179 # ok 3 verify_tpidr_one
7316 18:41:56.480000 # ok 4 count_tpidrs
7317 18:41:56.480427 # ok 5 tpidr2_write
7318 18:41:56.483180 # ok 6 tpidr2_read
7319 18:41:56.486274 # ok 7 write_tpidr_only
7320 18:41:56.489475 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
7321 18:41:56.493019 ok 46 selftests: arm64: ptrace
7322 18:41:56.496244 # selftests: arm64: syscall-abi
7323 18:41:56.541400 # TAP version 13
7324 18:41:56.541986 # 1..2
7325 18:41:56.544618 # ok 1 getpid() FPSIMD
7326 18:41:56.547915 # ok 2 sched_yield() FPSIMD
7327 18:41:56.551166 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
7328 18:41:56.554945 ok 47 selftests: arm64: syscall-abi
7329 18:41:56.564418 # selftests: arm64: tpidr2
7330 18:41:56.635426 # TAP version 13
7331 18:41:56.635626 # 1..5
7332 18:41:56.638481 # # PID: 1554
7333 18:41:56.638680 # # SME support not present
7334 18:41:56.641599 # ok 0 skipped, TPIDR2 not supported
7335 18:41:56.644887 # ok 1 skipped, TPIDR2 not supported
7336 18:41:56.648173 # ok 2 skipped, TPIDR2 not supported
7337 18:41:56.651497 # ok 3 skipped, TPIDR2 not supported
7338 18:41:56.654845 # ok 4 skipped, TPIDR2 not supported
7339 18:41:56.661055 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
7340 18:41:56.664728 ok 48 selftests: arm64: tpidr2
7341 18:41:58.290184 arm64_tags_test pass
7342 18:41:58.293683 arm64_run_tags_test_sh pass
7343 18:41:58.296743 arm64_fake_sigreturn_bad_magic pass
7344 18:41:58.300110 arm64_fake_sigreturn_bad_size pass
7345 18:41:58.303392 arm64_fake_sigreturn_bad_size_for_magic0 pass
7346 18:41:58.306436 arm64_fake_sigreturn_duplicated_fpsimd pass
7347 18:41:58.309771 arm64_fake_sigreturn_misaligned_sp pass
7348 18:41:58.313220 arm64_fake_sigreturn_missing_fpsimd pass
7349 18:41:58.319579 arm64_fake_sigreturn_sme_change_vl skip
7350 18:41:58.322964 arm64_fake_sigreturn_sve_change_vl skip
7351 18:41:58.326156 arm64_mangle_pstate_invalid_compat_toggle pass
7352 18:41:58.329151 arm64_mangle_pstate_invalid_daif_bits pass
7353 18:41:58.332733 arm64_mangle_pstate_invalid_mode_el1h pass
7354 18:41:58.335962 arm64_mangle_pstate_invalid_mode_el1t pass
7355 18:41:58.342745 arm64_mangle_pstate_invalid_mode_el2h pass
7356 18:41:58.345905 arm64_mangle_pstate_invalid_mode_el2t pass
7357 18:41:58.349220 arm64_mangle_pstate_invalid_mode_el3h pass
7358 18:41:58.352411 arm64_mangle_pstate_invalid_mode_el3t pass
7359 18:41:58.355525 arm64_sme_trap_no_sm skip
7360 18:41:58.358859 arm64_sme_trap_non_streaming skip
7361 18:41:58.359373 arm64_sme_trap_za pass
7362 18:41:58.361857 arm64_sme_vl skip
7363 18:41:58.365515 arm64_ssve_regs skip
7364 18:41:58.366030 arm64_sve_regs skip
7365 18:41:58.368568 arm64_sve_vl skip
7366 18:41:58.368978 arm64_za_no_regs skip
7367 18:41:58.372096 arm64_za_regs skip
7368 18:41:58.374760 arm64_pac_PAUTH_not_enabled skip
7369 18:41:58.378029 arm64_pac_PAUTH_not_enabled_dup2 skip
7370 18:41:58.381651 arm64_pac_Generic_PAUTH_not_enabled skip
7371 18:41:58.384955 arm64_pac_PAUTH_not_enabled_dup3 skip
7372 18:41:58.388039 arm64_pac_PAUTH_not_enabled_dup4 skip
7373 18:41:58.391364 arm64_pac_PAUTH_not_enabled_dup5 skip
7374 18:41:58.394504 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
7375 18:41:58.397537 arm64_pac pass
7376 18:41:58.400929 arm64_fp-stress_FPSIMD-0-0 pass
7377 18:41:58.404491 arm64_fp-stress_FPSIMD-0-1 pass
7378 18:41:58.405007 arm64_fp-stress_FPSIMD-1-0 pass
7379 18:41:58.407641 arm64_fp-stress_FPSIMD-1-1 pass
7380 18:41:58.410761 arm64_fp-stress_FPSIMD-2-0 pass
7381 18:41:58.414263 arm64_fp-stress_FPSIMD-2-1 pass
7382 18:41:58.417265 arm64_fp-stress_FPSIMD-3-0 pass
7383 18:41:58.420518 arm64_fp-stress_FPSIMD-3-1 pass
7384 18:41:58.423881 arm64_fp-stress_FPSIMD-4-0 pass
7385 18:41:58.427111 arm64_fp-stress_FPSIMD-4-1 pass
7386 18:41:58.427592 arm64_fp-stress_FPSIMD-5-0 pass
7387 18:41:58.430430 arm64_fp-stress_FPSIMD-5-1 pass
7388 18:41:58.433543 arm64_fp-stress_FPSIMD-6-0 pass
7389 18:41:58.437180 arm64_fp-stress_FPSIMD-6-1 pass
7390 18:41:58.440150 arm64_fp-stress_FPSIMD-7-0 pass
7391 18:41:58.443877 arm64_fp-stress_FPSIMD-7-1 pass
7392 18:41:58.444391 arm64_fp-stress pass
7393 18:41:58.447193 arm64_sve-ptrace_SVE_not_available skip
7394 18:41:58.450146 arm64_sve-ptrace skip
7395 18:41:58.453186 arm64_sve-probe-vls_SVE_not_available skip
7396 18:41:58.456628 arm64_sve-probe-vls skip
7397 18:41:58.459814 arm64_vec-syscfg_SVE_not_supported skip
7398 18:41:58.463121 arm64_vec-syscfg_SVE_not_supported_dup2 skip
7399 18:41:58.466256 arm64_vec-syscfg_SVE_not_supported_dup3 skip
7400 18:41:58.473059 arm64_vec-syscfg_SVE_not_supported_dup4 skip
7401 18:41:58.476068 arm64_vec-syscfg_SVE_not_supported_dup5 skip
7402 18:41:58.479325 arm64_vec-syscfg_SVE_not_supported_dup6 skip
7403 18:41:58.482770 arm64_vec-syscfg_SVE_not_supported_dup7 skip
7404 18:41:58.489395 arm64_vec-syscfg_SVE_not_supported_dup8 skip
7405 18:41:58.492889 arm64_vec-syscfg_SVE_not_supported_dup9 skip
7406 18:41:58.495930 arm64_vec-syscfg_SVE_not_supported_dup10 skip
7407 18:41:58.499191 arm64_vec-syscfg_SME_not_supported skip
7408 18:41:58.502399 arm64_vec-syscfg_SME_not_supported_dup2 skip
7409 18:41:58.508787 arm64_vec-syscfg_SME_not_supported_dup3 skip
7410 18:41:58.512271 arm64_vec-syscfg_SME_not_supported_dup4 skip
7411 18:41:58.515354 arm64_vec-syscfg_SME_not_supported_dup5 skip
7412 18:41:58.518717 arm64_vec-syscfg_SME_not_supported_dup6 skip
7413 18:41:58.525312 arm64_vec-syscfg_SME_not_supported_dup7 skip
7414 18:41:58.528317 arm64_vec-syscfg_SME_not_supported_dup8 skip
7415 18:41:58.531546 arm64_vec-syscfg_SME_not_supported_dup9 skip
7416 18:41:58.534962 arm64_vec-syscfg_SME_not_supported_dup10 skip
7417 18:41:58.537952 arm64_vec-syscfg pass
7418 18:41:58.541220 arm64_za-fork_skipped pass
7419 18:41:58.541685 arm64_za-fork pass
7420 18:41:58.544567 arm64_za-ptrace_SME_not_available skip
7421 18:41:58.547928 arm64_za-ptrace skip
7422 18:41:58.550933 arm64_check_buffer_fill skip
7423 18:41:58.551339 arm64_check_child_memory skip
7424 18:41:58.554173 arm64_check_gcr_el1_cswitch skip
7425 18:41:58.557727 arm64_check_ksm_options skip
7426 18:41:58.560725 arm64_check_mmap_options skip
7427 18:41:58.564213 arm64_check_prctl_check_basic_read pass
7428 18:41:58.567431 arm64_check_prctl_NONE pass
7429 18:41:58.570634 arm64_check_prctl_SYNC skip
7430 18:41:58.571061 arm64_check_prctl_ASYNC skip
7431 18:41:58.573992 arm64_check_prctl_SYNC_ASYNC skip
7432 18:41:58.576917 arm64_check_prctl pass
7433 18:41:58.580483 arm64_check_tags_inclusion skip
7434 18:41:58.583524 arm64_check_user_mem skip
7435 18:41:58.586974 arm64_btitest_nohint_func_call_using_br_x0 skip
7436 18:41:58.589927 arm64_btitest_nohint_func_call_using_br_x16 skip
7437 18:41:58.593234 arm64_btitest_nohint_func_call_using_blr skip
7438 18:41:58.599620 arm64_btitest_bti_none_func_call_using_br_x0 skip
7439 18:41:58.603301 arm64_btitest_bti_none_func_call_using_br_x16 skip
7440 18:41:58.606379 arm64_btitest_bti_none_func_call_using_blr skip
7441 18:41:58.613047 arm64_btitest_bti_c_func_call_using_br_x0 skip
7442 18:41:58.616584 arm64_btitest_bti_c_func_call_using_br_x16 skip
7443 18:41:58.619892 arm64_btitest_bti_c_func_call_using_blr skip
7444 18:41:58.626355 arm64_btitest_bti_j_func_call_using_br_x0 skip
7445 18:41:58.629454 arm64_btitest_bti_j_func_call_using_br_x16 skip
7446 18:41:58.632644 arm64_btitest_bti_j_func_call_using_blr skip
7447 18:41:58.635695 arm64_btitest_bti_jc_func_call_using_br_x0 skip
7448 18:41:58.642375 arm64_btitest_bti_jc_func_call_using_br_x16 skip
7449 18:41:58.645409 arm64_btitest_bti_jc_func_call_using_blr skip
7450 18:41:58.648490 arm64_btitest_paciasp_func_call_using_br_x0 skip
7451 18:41:58.654952 arm64_btitest_paciasp_func_call_using_br_x16 skip
7452 18:41:58.658181 arm64_btitest_paciasp_func_call_using_blr skip
7453 18:41:58.658272 arm64_btitest pass
7454 18:41:58.664768 arm64_nobtitest_nohint_func_call_using_br_x0 skip
7455 18:41:58.668270 arm64_nobtitest_nohint_func_call_using_br_x16 skip
7456 18:41:58.671334 arm64_nobtitest_nohint_func_call_using_blr skip
7457 18:41:58.677757 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
7458 18:41:58.680960 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
7459 18:41:58.687619 arm64_nobtitest_bti_none_func_call_using_blr skip
7460 18:41:58.691022 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
7461 18:41:58.694184 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
7462 18:41:58.700600 arm64_nobtitest_bti_c_func_call_using_blr skip
7463 18:41:58.703990 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
7464 18:41:58.707473 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
7465 18:41:58.713942 arm64_nobtitest_bti_j_func_call_using_blr skip
7466 18:41:58.717141 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
7467 18:41:58.720535 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
7468 18:41:58.726884 arm64_nobtitest_bti_jc_func_call_using_blr skip
7469 18:41:58.730064 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
7470 18:41:58.733528 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
7471 18:41:58.740482 arm64_nobtitest_paciasp_func_call_using_blr skip
7472 18:41:58.740862 arm64_nobtitest pass
7473 18:41:58.743212 arm64_hwcap_cpuinfo_match_RNG pass
7474 18:41:58.746820 arm64_hwcap_sigill_RNG skip
7475 18:41:58.749900 arm64_hwcap_cpuinfo_match_SME pass
7476 18:41:58.753415 arm64_hwcap_sigill_SME pass
7477 18:41:58.756334 arm64_hwcap_cpuinfo_match_SVE pass
7478 18:41:58.759521 arm64_hwcap_sigill_SVE pass
7479 18:41:58.762896 arm64_hwcap_cpuinfo_match_SVE_2 pass
7480 18:41:58.763275 arm64_hwcap_sigill_SVE_2 skip
7481 18:41:58.766057 arm64_hwcap_cpuinfo_match_SVE_AES pass
7482 18:41:58.769328 arm64_hwcap_sigill_SVE_AES skip
7483 18:41:58.772500 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
7484 18:41:58.776044 arm64_hwcap_sigill_SVE2_PMULL skip
7485 18:41:58.782552 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
7486 18:41:58.785773 arm64_hwcap_sigill_SVE2_BITPERM skip
7487 18:41:58.788786 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
7488 18:41:58.792160 arm64_hwcap_sigill_SVE2_SHA3 skip
7489 18:41:58.795640 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
7490 18:41:58.798755 arm64_hwcap_sigill_SVE2_SM4 skip
7491 18:41:58.802059 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
7492 18:41:58.805230 arm64_hwcap_sigill_SVE2_I8MM skip
7493 18:41:58.808379 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
7494 18:41:58.811535 arm64_hwcap_sigill_SVE2_F32MM skip
7495 18:41:58.814885 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
7496 18:41:58.818069 arm64_hwcap_sigill_SVE2_F64MM skip
7497 18:41:58.821059 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
7498 18:41:58.824604 arm64_hwcap_sigill_SVE2_BF16 skip
7499 18:41:58.827605 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
7500 18:41:58.830879 arm64_hwcap_sigill_SVE2_EBF16 skip
7501 18:41:58.834152 arm64_hwcap pass
7502 18:41:58.837413 arm64_ptrace_read_tpidr_one pass
7503 18:41:58.840642 arm64_ptrace_write_tpidr_one pass
7504 18:41:58.843889 arm64_ptrace_verify_tpidr_one pass
7505 18:41:58.847417 arm64_ptrace_count_tpidrs pass
7506 18:41:58.847511 arm64_ptrace_tpidr2_write pass
7507 18:41:58.850533 arm64_ptrace_tpidr2_read pass
7508 18:41:58.853872 arm64_ptrace_write_tpidr_only pass
7509 18:41:58.857180 arm64_ptrace pass
7510 18:41:58.860168 arm64_syscall-abi_getpid_FPSIMD pass
7511 18:41:58.863401 arm64_syscall-abi_sched_yield_FPSIMD pass
7512 18:41:58.866735 arm64_syscall-abi pass
7513 18:41:58.869910 arm64_tpidr2_skipped_TPIDR2_not_supported pass
7514 18:41:58.873306 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
7515 18:41:58.879558 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
7516 18:41:58.883117 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
7517 18:41:58.889387 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
7518 18:41:58.889506 arm64_tpidr2 pass
7519 18:41:58.892907 + ../../utils/send-to-lava.sh ./output/result.txt
7520 18:41:58.899212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
7521 18:41:58.899504 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
7523 18:41:58.905721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
7524 18:41:58.905986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
7526 18:41:58.912370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
7527 18:41:58.912635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
7529 18:41:58.918820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
7530 18:41:58.919089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
7532 18:41:58.925399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
7533 18:41:58.925681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
7535 18:41:58.931907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
7536 18:41:58.932178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
7538 18:41:58.955704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
7539 18:41:58.956030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
7541 18:41:58.994134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
7542 18:41:58.994454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
7544 18:41:59.031438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
7545 18:41:59.031751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
7547 18:41:59.070589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
7548 18:41:59.070912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
7550 18:41:59.108417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
7551 18:41:59.108748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
7553 18:41:59.140999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
7554 18:41:59.141325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
7556 18:41:59.177640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
7557 18:41:59.178272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
7559 18:41:59.215633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
7560 18:41:59.216303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
7562 18:41:59.260512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
7563 18:41:59.260810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
7565 18:41:59.303197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
7566 18:41:59.303569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
7568 18:41:59.344717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
7569 18:41:59.345395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
7571 18:41:59.390352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
7572 18:41:59.391039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
7574 18:41:59.440172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
7575 18:41:59.440834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
7577 18:41:59.482830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
7578 18:41:59.483525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
7580 18:41:59.530354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
7581 18:41:59.530691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
7583 18:41:59.564560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
7584 18:41:59.564839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
7586 18:41:59.601945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
7587 18:41:59.602726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
7589 18:41:59.646626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
7590 18:41:59.647291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
7592 18:41:59.688836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
7593 18:41:59.689121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
7595 18:41:59.730349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
7596 18:41:59.730746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
7598 18:41:59.771932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
7599 18:41:59.772596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
7601 18:41:59.816610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
7602 18:41:59.816885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
7604 18:41:59.858415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
7606 18:41:59.861366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
7607 18:41:59.906930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
7608 18:41:59.907589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
7610 18:41:59.951809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
7611 18:41:59.952476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
7613 18:42:00.002433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
7614 18:42:00.002834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
7616 18:42:00.050407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
7617 18:42:00.051089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
7619 18:42:00.097070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
7620 18:42:00.097790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
7622 18:42:00.142173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
7623 18:42:00.142842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
7625 18:42:00.184381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
7626 18:42:00.185049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
7628 18:42:00.232665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
7630 18:42:00.235691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
7631 18:42:00.282102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
7633 18:42:00.285528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
7634 18:42:00.333196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
7636 18:42:00.336364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
7637 18:42:00.380935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
7639 18:42:00.384089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
7640 18:42:00.428103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
7642 18:42:00.431229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
7643 18:42:00.474607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
7645 18:42:00.477244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
7646 18:42:00.523533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
7648 18:42:00.526608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
7649 18:42:00.568590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
7651 18:42:00.571423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
7652 18:42:00.610238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
7654 18:42:00.613162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
7655 18:42:00.652684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
7657 18:42:00.655735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
7658 18:42:00.694113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
7660 18:42:00.696882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
7661 18:42:00.737455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
7663 18:42:00.740339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
7664 18:42:00.780869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
7666 18:42:00.783656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
7667 18:42:00.830730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
7669 18:42:00.833657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
7670 18:42:00.882900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
7672 18:42:00.885870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
7673 18:42:00.926055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
7675 18:42:00.929240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
7676 18:42:00.988357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
7677 18:42:00.989046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
7679 18:42:01.041863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
7680 18:42:01.042224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
7682 18:42:01.085603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
7683 18:42:01.085878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
7685 18:42:01.132431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
7686 18:42:01.132699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
7688 18:42:01.175637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
7689 18:42:01.175916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
7691 18:42:01.218867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
7692 18:42:01.219165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
7694 18:42:01.262357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
7695 18:42:01.263037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
7697 18:42:01.306097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
7698 18:42:01.306363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
7700 18:42:01.349011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
7701 18:42:01.349282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
7703 18:42:01.391817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
7704 18:42:01.392109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
7706 18:42:01.438004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
7707 18:42:01.438677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
7709 18:42:01.485081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
7710 18:42:01.485369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
7712 18:42:01.526364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
7713 18:42:01.526636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
7715 18:42:01.568301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
7716 18:42:01.568565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
7718 18:42:01.605273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
7719 18:42:01.605538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
7721 18:42:01.647583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
7722 18:42:01.647982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
7724 18:42:01.695409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
7725 18:42:01.696222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
7727 18:42:01.744960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
7728 18:42:01.745807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
7730 18:42:01.795232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
7731 18:42:01.795918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
7733 18:42:01.845918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
7734 18:42:01.846597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
7736 18:42:01.900019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
7737 18:42:01.900705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
7739 18:42:01.951830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
7740 18:42:01.952601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
7742 18:42:02.008117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
7743 18:42:02.008793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
7745 18:42:02.053379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
7746 18:42:02.053665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
7748 18:42:02.096635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
7749 18:42:02.097235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
7751 18:42:02.144220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
7752 18:42:02.144887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
7754 18:42:02.193704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
7755 18:42:02.194379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
7757 18:42:02.237649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
7758 18:42:02.238318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
7760 18:42:02.285308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
7761 18:42:02.285594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
7763 18:42:02.326530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
7764 18:42:02.326809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
7766 18:42:02.369601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
7767 18:42:02.370193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
7769 18:42:02.419057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
7770 18:42:02.419745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
7772 18:42:02.460736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
7774 18:42:02.463796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
7775 18:42:02.505375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
7776 18:42:02.505768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
7778 18:42:02.550336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
7779 18:42:02.550999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
7781 18:42:02.603884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
7782 18:42:02.604572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
7784 18:42:02.653300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
7785 18:42:02.653614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
7787 18:42:02.703277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
7788 18:42:02.703948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
7790 18:42:02.750900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
7791 18:42:02.751255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
7793 18:42:02.798076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
7794 18:42:02.798345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
7796 18:42:02.834534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
7797 18:42:02.835211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
7799 18:42:02.888154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
7801 18:42:02.890847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
7802 18:42:02.942965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
7803 18:42:02.943669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
7805 18:42:03.006341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
7806 18:42:03.007148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
7808 18:42:03.055734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
7809 18:42:03.056525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
7811 18:42:03.106228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
7812 18:42:03.107022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
7814 18:42:03.154574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
7815 18:42:03.155377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
7817 18:42:03.208356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
7818 18:42:03.209095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
7820 18:42:03.251980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
7821 18:42:03.252280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
7823 18:42:03.291358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
7824 18:42:03.291630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
7826 18:42:03.345878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
7827 18:42:03.346640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
7829 18:42:03.411749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
7830 18:42:03.412500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
7832 18:42:03.473125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
7833 18:42:03.473927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
7835 18:42:03.539238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
7836 18:42:03.539984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
7838 18:42:03.603899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
7839 18:42:03.604580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
7841 18:42:03.661822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7842 18:42:03.662503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
7844 18:42:03.705901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7845 18:42:03.706573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
7847 18:42:03.752423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
7848 18:42:03.753101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
7850 18:42:03.799414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
7851 18:42:03.800161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
7853 18:42:03.845726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
7854 18:42:03.846397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
7856 18:42:03.888938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
7857 18:42:03.889728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
7859 18:42:03.929013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
7860 18:42:03.929856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
7862 18:42:03.973277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
7863 18:42:03.973985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
7865 18:42:04.017995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
7866 18:42:04.018682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
7868 18:42:04.067505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
7869 18:42:04.068235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
7871 18:42:04.115676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
7872 18:42:04.116403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
7874 18:42:04.160440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
7875 18:42:04.161139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
7877 18:42:04.202419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
7878 18:42:04.203230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
7880 18:42:04.252600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
7881 18:42:04.253271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
7883 18:42:04.298566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
7884 18:42:04.299243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
7886 18:42:04.341316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
7887 18:42:04.342035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
7889 18:42:04.389806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
7890 18:42:04.390485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
7892 18:42:04.437761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
7893 18:42:04.438443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
7895 18:42:04.483430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
7896 18:42:04.484113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
7898 18:42:04.536090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
7899 18:42:04.536771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
7901 18:42:04.581376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
7902 18:42:04.581651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
7904 18:42:04.621540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
7905 18:42:04.621813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
7907 18:42:04.665272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
7908 18:42:04.665614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
7910 18:42:04.704888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
7911 18:42:04.705170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
7913 18:42:04.749313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
7914 18:42:04.750029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
7916 18:42:04.790214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
7917 18:42:04.790879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
7919 18:42:04.841304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
7920 18:42:04.841583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
7922 18:42:04.884266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
7923 18:42:04.884535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
7925 18:42:04.931081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
7926 18:42:04.931418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
7928 18:42:04.974043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
7929 18:42:04.974773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
7931 18:42:05.025053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
7932 18:42:05.025340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
7934 18:42:05.060422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
7935 18:42:05.060914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
7937 18:42:05.107872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
7938 18:42:05.108548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
7940 18:42:05.157588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
7941 18:42:05.157869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
7943 18:42:05.207344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
7944 18:42:05.207643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
7946 18:42:05.255792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
7948 18:42:05.258531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
7949 18:42:05.304781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
7950 18:42:05.305550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
7952 18:42:05.353749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
7953 18:42:05.354080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
7955 18:42:05.401280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
7956 18:42:05.401667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
7958 18:42:05.448228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
7959 18:42:05.448892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
7961 18:42:05.498392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
7962 18:42:05.498727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
7964 18:42:05.541700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
7965 18:42:05.541970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
7967 18:42:05.582767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
7968 18:42:05.583110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
7970 18:42:05.624691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
7972 18:42:05.627736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
7973 18:42:05.684553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
7974 18:42:05.685237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
7976 18:42:05.744812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
7977 18:42:05.745537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
7979 18:42:05.794959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
7980 18:42:05.795628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
7982 18:42:05.844756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
7983 18:42:05.845468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
7985 18:42:05.892977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
7986 18:42:05.893649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
7988 18:42:05.940606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
7989 18:42:05.940899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
7991 18:42:05.987222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
7992 18:42:05.987502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
7994 18:42:06.029783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
7995 18:42:06.030282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
7997 18:42:06.081108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
7998 18:42:06.081397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
8000 18:42:06.135477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
8001 18:42:06.136230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
8003 18:42:06.189072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
8004 18:42:06.189792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
8006 18:42:06.238829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
8008 18:42:06.241584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
8009 18:42:06.290608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
8010 18:42:06.291277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
8012 18:42:06.341826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
8013 18:42:06.342501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
8015 18:42:06.385316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
8016 18:42:06.386034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
8018 18:42:06.433328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
8019 18:42:06.434042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
8021 18:42:06.478274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
8022 18:42:06.478948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
8024 18:42:06.524274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
8025 18:42:06.524946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
8027 18:42:06.564555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
8028 18:42:06.565258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
8030 18:42:06.610526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
8031 18:42:06.611247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
8033 18:42:06.656604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
8034 18:42:06.657269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
8036 18:42:06.697339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
8037 18:42:06.698057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
8039 18:42:06.745533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
8040 18:42:06.746332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
8042 18:42:06.788246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
8043 18:42:06.788919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
8045 18:42:06.831668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
8046 18:42:06.832354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
8048 18:42:06.876195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
8049 18:42:06.876890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
8051 18:42:06.919588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
8052 18:42:06.920308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
8054 18:42:06.962681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
8055 18:42:06.962781 + set +x
8056 18:42:06.963025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
8058 18:42:06.969346 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14291499_1.6.2.3.5>
8059 18:42:06.969727 Received signal: <ENDRUN> 1_kselftest-arm64 14291499_1.6.2.3.5
8060 18:42:06.969838 Ending use of test pattern.
8061 18:42:06.969920 Ending test lava.1_kselftest-arm64 (14291499_1.6.2.3.5), duration 32.27
8063 18:42:06.972273 <LAVA_TEST_RUNNER EXIT>
8064 18:42:06.972570 ok: lava_test_shell seems to have completed
8065 18:42:06.973981 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
8066 18:42:06.974184 end: 3.1 lava-test-shell (duration 00:00:33) [common]
8067 18:42:06.974296 end: 3 lava-test-retry (duration 00:00:33) [common]
8068 18:42:06.974405 start: 4 finalize (timeout 00:07:25) [common]
8069 18:42:06.974519 start: 4.1 power-off (timeout 00:00:30) [common]
8070 18:42:06.974718 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-2', '--port=1', '--command=off']
8071 18:42:08.033966 >> Command sent successfully.
8072 18:42:08.044048 Returned 0 in 1 seconds
8073 18:42:08.145521 end: 4.1 power-off (duration 00:00:01) [common]
8075 18:42:08.147045 start: 4.2 read-feedback (timeout 00:07:23) [common]
8076 18:42:08.148441 Listened to connection for namespace 'common' for up to 1s
8077 18:42:09.149115 Finalising connection for namespace 'common'
8078 18:42:09.149837 Disconnecting from shell: Finalise
8079 18:42:09.150281 / #
8080 18:42:09.251389 end: 4.2 read-feedback (duration 00:00:01) [common]
8081 18:42:09.252196 end: 4 finalize (duration 00:00:02) [common]
8082 18:42:09.252844 Cleaning after the job
8083 18:42:09.253389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/ramdisk
8084 18:42:09.258251 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/kernel
8085 18:42:09.269661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/dtb
8086 18:42:09.269838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/nfsrootfs
8087 18:42:09.337655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291499/tftp-deploy-p8e8r9bv/modules
8088 18:42:09.343638 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291499
8089 18:42:09.963880 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291499
8090 18:42:09.964083 Job finished correctly