Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 25
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:04:42.932251 lava-dispatcher, installed at version: 2024.03
2 18:04:42.932464 start: 0 validate
3 18:04:42.932633 Start time: 2024-06-11 18:04:42.932626+00:00 (UTC)
4 18:04:42.932768 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:04:42.932894 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:04:43.199316 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:04:43.199496 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:04:43.466095 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:04:43.466781 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:04:43.737199 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:04:43.737980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:04:44.008019 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:04:44.008829 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:04:44.279086 validate duration: 1.35
16 18:04:44.279359 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:04:44.279460 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:04:44.279546 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:04:44.279673 Not decompressing ramdisk as can be used compressed.
20 18:04:44.279760 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:04:44.279825 saving as /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/ramdisk/initrd.cpio.gz
22 18:04:44.279891 total size: 5628169 (5 MB)
23 18:04:44.281037 progress 0 % (0 MB)
24 18:04:44.282615 progress 5 % (0 MB)
25 18:04:44.284172 progress 10 % (0 MB)
26 18:04:44.285612 progress 15 % (0 MB)
27 18:04:44.287190 progress 20 % (1 MB)
28 18:04:44.288604 progress 25 % (1 MB)
29 18:04:44.290194 progress 30 % (1 MB)
30 18:04:44.291768 progress 35 % (1 MB)
31 18:04:44.293202 progress 40 % (2 MB)
32 18:04:44.294730 progress 45 % (2 MB)
33 18:04:44.296094 progress 50 % (2 MB)
34 18:04:44.297623 progress 55 % (2 MB)
35 18:04:44.299147 progress 60 % (3 MB)
36 18:04:44.300514 progress 65 % (3 MB)
37 18:04:44.302047 progress 70 % (3 MB)
38 18:04:44.303418 progress 75 % (4 MB)
39 18:04:44.304941 progress 80 % (4 MB)
40 18:04:44.306296 progress 85 % (4 MB)
41 18:04:44.307865 progress 90 % (4 MB)
42 18:04:44.309432 progress 95 % (5 MB)
43 18:04:44.310849 progress 100 % (5 MB)
44 18:04:44.311060 5 MB downloaded in 0.03 s (172.21 MB/s)
45 18:04:44.311221 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:04:44.311468 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:04:44.311557 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:04:44.311645 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:04:44.311787 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:04:44.311864 saving as /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/kernel/Image
52 18:04:44.311930 total size: 54813184 (52 MB)
53 18:04:44.311994 No compression specified
54 18:04:44.313136 progress 0 % (0 MB)
55 18:04:44.326944 progress 5 % (2 MB)
56 18:04:44.340924 progress 10 % (5 MB)
57 18:04:44.354895 progress 15 % (7 MB)
58 18:04:44.368935 progress 20 % (10 MB)
59 18:04:44.382889 progress 25 % (13 MB)
60 18:04:44.396690 progress 30 % (15 MB)
61 18:04:44.410582 progress 35 % (18 MB)
62 18:04:44.424598 progress 40 % (20 MB)
63 18:04:44.438462 progress 45 % (23 MB)
64 18:04:44.452903 progress 50 % (26 MB)
65 18:04:44.467017 progress 55 % (28 MB)
66 18:04:44.481035 progress 60 % (31 MB)
67 18:04:44.495078 progress 65 % (34 MB)
68 18:04:44.508960 progress 70 % (36 MB)
69 18:04:44.523055 progress 75 % (39 MB)
70 18:04:44.537139 progress 80 % (41 MB)
71 18:04:44.551224 progress 85 % (44 MB)
72 18:04:44.565346 progress 90 % (47 MB)
73 18:04:44.579332 progress 95 % (49 MB)
74 18:04:44.592885 progress 100 % (52 MB)
75 18:04:44.593156 52 MB downloaded in 0.28 s (185.88 MB/s)
76 18:04:44.593319 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:04:44.593558 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:04:44.593648 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:04:44.593735 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:04:44.593871 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:04:44.593943 saving as /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/dtb/mt8192-asurada-spherion-r0.dtb
83 18:04:44.594007 total size: 47258 (0 MB)
84 18:04:44.594071 No compression specified
85 18:04:44.595215 progress 69 % (0 MB)
86 18:04:44.595515 progress 100 % (0 MB)
87 18:04:44.595674 0 MB downloaded in 0.00 s (27.08 MB/s)
88 18:04:44.595799 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:04:44.596033 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:04:44.596121 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:04:44.596228 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:04:44.596345 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:04:44.596416 saving as /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/nfsrootfs/full.rootfs.tar
95 18:04:44.596479 total size: 120894716 (115 MB)
96 18:04:44.596544 Using unxz to decompress xz
97 18:04:44.600181 progress 0 % (0 MB)
98 18:04:44.944453 progress 5 % (5 MB)
99 18:04:45.303199 progress 10 % (11 MB)
100 18:04:45.650310 progress 15 % (17 MB)
101 18:04:45.981980 progress 20 % (23 MB)
102 18:04:46.282304 progress 25 % (28 MB)
103 18:04:46.656221 progress 30 % (34 MB)
104 18:04:47.010423 progress 35 % (40 MB)
105 18:04:47.183953 progress 40 % (46 MB)
106 18:04:47.370502 progress 45 % (51 MB)
107 18:04:47.692758 progress 50 % (57 MB)
108 18:04:48.072674 progress 55 % (63 MB)
109 18:04:48.445190 progress 60 % (69 MB)
110 18:04:48.811633 progress 65 % (74 MB)
111 18:04:49.189506 progress 70 % (80 MB)
112 18:04:49.573754 progress 75 % (86 MB)
113 18:04:49.941221 progress 80 % (92 MB)
114 18:04:50.297872 progress 85 % (98 MB)
115 18:04:50.666051 progress 90 % (103 MB)
116 18:04:51.008714 progress 95 % (109 MB)
117 18:04:51.399157 progress 100 % (115 MB)
118 18:04:51.404778 115 MB downloaded in 6.81 s (16.93 MB/s)
119 18:04:51.405065 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:04:51.405356 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:04:51.405456 start: 1.5 download-retry (timeout 00:09:53) [common]
123 18:04:51.405550 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 18:04:51.405709 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:04:51.405799 saving as /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/modules/modules.tar
126 18:04:51.405869 total size: 8618176 (8 MB)
127 18:04:51.405940 Using unxz to decompress xz
128 18:04:51.409647 progress 0 % (0 MB)
129 18:04:51.429966 progress 5 % (0 MB)
130 18:04:51.459441 progress 10 % (0 MB)
131 18:04:51.492035 progress 15 % (1 MB)
132 18:04:51.518149 progress 20 % (1 MB)
133 18:04:51.544025 progress 25 % (2 MB)
134 18:04:51.570102 progress 30 % (2 MB)
135 18:04:51.597155 progress 35 % (2 MB)
136 18:04:51.622890 progress 40 % (3 MB)
137 18:04:51.646688 progress 45 % (3 MB)
138 18:04:51.671531 progress 50 % (4 MB)
139 18:04:51.697350 progress 55 % (4 MB)
140 18:04:51.722604 progress 60 % (4 MB)
141 18:04:51.747596 progress 65 % (5 MB)
142 18:04:51.775903 progress 70 % (5 MB)
143 18:04:51.800581 progress 75 % (6 MB)
144 18:04:51.827148 progress 80 % (6 MB)
145 18:04:51.852103 progress 85 % (7 MB)
146 18:04:51.878186 progress 90 % (7 MB)
147 18:04:51.904113 progress 95 % (7 MB)
148 18:04:51.931622 progress 100 % (8 MB)
149 18:04:51.936192 8 MB downloaded in 0.53 s (15.50 MB/s)
150 18:04:51.936502 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:04:51.936827 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:04:51.936930 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:04:51.937028 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:04:55.623295 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1
156 18:04:55.623517 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:04:55.623623 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 18:04:55.623798 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q
159 18:04:55.623928 makedir: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin
160 18:04:55.624030 makedir: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/tests
161 18:04:55.624129 makedir: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/results
162 18:04:55.624233 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-add-keys
163 18:04:55.624374 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-add-sources
164 18:04:55.624503 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-background-process-start
165 18:04:55.624643 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-background-process-stop
166 18:04:55.624769 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-common-functions
167 18:04:55.624895 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-echo-ipv4
168 18:04:55.625018 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-install-packages
169 18:04:55.625139 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-installed-packages
170 18:04:55.625260 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-os-build
171 18:04:55.625382 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-probe-channel
172 18:04:55.625503 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-probe-ip
173 18:04:55.625623 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-target-ip
174 18:04:55.625742 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-target-mac
175 18:04:55.625862 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-target-storage
176 18:04:55.625985 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-case
177 18:04:55.626109 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-event
178 18:04:55.626230 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-feedback
179 18:04:55.626351 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-raise
180 18:04:55.626471 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-reference
181 18:04:55.626594 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-runner
182 18:04:55.626716 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-set
183 18:04:55.626838 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-test-shell
184 18:04:55.626959 Updating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-add-keys (debian)
185 18:04:55.632884 Updating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-add-sources (debian)
186 18:04:55.633139 Updating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-install-packages (debian)
187 18:04:55.633331 Updating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-installed-packages (debian)
188 18:04:55.633509 Updating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/bin/lava-os-build (debian)
189 18:04:55.633678 Creating /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/environment
190 18:04:55.633817 LAVA metadata
191 18:04:55.633922 - LAVA_JOB_ID=14291400
192 18:04:55.634026 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:04:55.634189 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 18:04:55.634296 skipped lava-vland-overlay
195 18:04:55.634420 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:04:55.634546 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 18:04:55.634643 skipped lava-multinode-overlay
198 18:04:55.634751 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:04:55.634875 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 18:04:55.634988 Loading test definitions
201 18:04:55.635128 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 18:04:55.635234 Using /lava-14291400 at stage 0
203 18:04:55.635630 uuid=14291400_1.6.2.3.1 testdef=None
204 18:04:55.635754 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:04:55.635882 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 18:04:55.636539 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:04:55.636925 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 18:04:55.637731 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:04:55.638125 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 18:04:55.641440 runner path: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/0/tests/0_timesync-off test_uuid 14291400_1.6.2.3.1
213 18:04:55.641630 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:04:55.641941 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 18:04:55.642017 Using /lava-14291400 at stage 0
217 18:04:55.642136 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:04:55.642230 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/0/tests/1_kselftest-arm64'
219 18:04:57.735163 Running '/usr/bin/git checkout kernelci.org
220 18:04:57.883857 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 18:04:57.884590 uuid=14291400_1.6.2.3.5 testdef=None
222 18:04:57.884749 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:04:57.885008 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 18:04:57.885774 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:04:57.886013 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 18:04:57.887025 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:04:57.887277 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 18:04:57.888214 runner path: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/0/tests/1_kselftest-arm64 test_uuid 14291400_1.6.2.3.5
232 18:04:57.888311 BOARD='mt8192-asurada-spherion-r0'
233 18:04:57.888379 BRANCH='cip'
234 18:04:57.888443 SKIPFILE='/dev/null'
235 18:04:57.888506 SKIP_INSTALL='True'
236 18:04:57.888576 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:04:57.888637 TST_CASENAME=''
238 18:04:57.888696 TST_CMDFILES='arm64'
239 18:04:57.888837 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:04:57.889052 Creating lava-test-runner.conf files
242 18:04:57.889120 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291400/lava-overlay-mvclot6q/lava-14291400/0 for stage 0
243 18:04:57.889214 - 0_timesync-off
244 18:04:57.889287 - 1_kselftest-arm64
245 18:04:57.889383 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:04:57.889477 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 18:05:05.393798 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:05:05.393962 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 18:05:05.394056 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:05:05.394156 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:05:05.394251 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 18:05:05.553357 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:05:05.553721 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 18:05:05.553838 extracting modules file /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1
255 18:05:05.755140 extracting modules file /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291400/extract-overlay-ramdisk-r9ts1170/ramdisk
256 18:05:05.961945 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:05:05.962130 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 18:05:05.962231 [common] Applying overlay to NFS
259 18:05:05.962309 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291400/compress-overlay-e6qvhm6q/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1
260 18:05:06.863871 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:05:06.864047 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 18:05:06.864148 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:05:06.864240 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 18:05:06.864322 Building ramdisk /var/lib/lava/dispatcher/tmp/14291400/extract-overlay-ramdisk-r9ts1170/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291400/extract-overlay-ramdisk-r9ts1170/ramdisk
265 18:05:07.171553 >> 130400 blocks
266 18:05:09.223101 rename /var/lib/lava/dispatcher/tmp/14291400/extract-overlay-ramdisk-r9ts1170/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/ramdisk/ramdisk.cpio.gz
267 18:05:09.223539 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 18:05:09.223666 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 18:05:09.223782 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 18:05:09.223889 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/kernel/Image']
271 18:05:24.117437 Returned 0 in 14 seconds
272 18:05:24.218358 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/kernel/image.itb
273 18:05:24.623462 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:05:24.623816 output: Created: Tue Jun 11 19:05:24 2024
275 18:05:24.623904 output: Image 0 (kernel-1)
276 18:05:24.623974 output: Description:
277 18:05:24.624041 output: Created: Tue Jun 11 19:05:24 2024
278 18:05:24.624107 output: Type: Kernel Image
279 18:05:24.624170 output: Compression: lzma compressed
280 18:05:24.624230 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:05:24.624291 output: Architecture: AArch64
282 18:05:24.624349 output: OS: Linux
283 18:05:24.624406 output: Load Address: 0x00000000
284 18:05:24.624463 output: Entry Point: 0x00000000
285 18:05:24.624522 output: Hash algo: crc32
286 18:05:24.624627 output: Hash value: 7a9e9d3e
287 18:05:24.624685 output: Image 1 (fdt-1)
288 18:05:24.624743 output: Description: mt8192-asurada-spherion-r0
289 18:05:24.624800 output: Created: Tue Jun 11 19:05:24 2024
290 18:05:24.624855 output: Type: Flat Device Tree
291 18:05:24.624909 output: Compression: uncompressed
292 18:05:24.624968 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 18:05:24.625024 output: Architecture: AArch64
294 18:05:24.625079 output: Hash algo: crc32
295 18:05:24.625133 output: Hash value: 0f8e4d2e
296 18:05:24.625188 output: Image 2 (ramdisk-1)
297 18:05:24.625241 output: Description: unavailable
298 18:05:24.625295 output: Created: Tue Jun 11 19:05:24 2024
299 18:05:24.625349 output: Type: RAMDisk Image
300 18:05:24.625403 output: Compression: Unknown Compression
301 18:05:24.625456 output: Data Size: 18740853 Bytes = 18301.61 KiB = 17.87 MiB
302 18:05:24.625511 output: Architecture: AArch64
303 18:05:24.625565 output: OS: Linux
304 18:05:24.625619 output: Load Address: unavailable
305 18:05:24.625672 output: Entry Point: unavailable
306 18:05:24.625726 output: Hash algo: crc32
307 18:05:24.625779 output: Hash value: f3391c4b
308 18:05:24.625833 output: Default Configuration: 'conf-1'
309 18:05:24.625887 output: Configuration 0 (conf-1)
310 18:05:24.625941 output: Description: mt8192-asurada-spherion-r0
311 18:05:24.625995 output: Kernel: kernel-1
312 18:05:24.626049 output: Init Ramdisk: ramdisk-1
313 18:05:24.626102 output: FDT: fdt-1
314 18:05:24.626155 output: Loadables: kernel-1
315 18:05:24.626209 output:
316 18:05:24.626400 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 18:05:24.626499 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 18:05:24.626614 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 18:05:24.626706 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 18:05:24.626786 No LXC device requested
321 18:05:24.626865 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:05:24.626957 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 18:05:24.627036 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:05:24.627105 Checking files for TFTP limit of 4294967296 bytes.
325 18:05:24.627612 end: 1 tftp-deploy (duration 00:00:40) [common]
326 18:05:24.627724 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:05:24.627817 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:05:24.627942 substitutions:
329 18:05:24.628012 - {DTB}: 14291400/tftp-deploy-hd_dbfq_/dtb/mt8192-asurada-spherion-r0.dtb
330 18:05:24.628078 - {INITRD}: 14291400/tftp-deploy-hd_dbfq_/ramdisk/ramdisk.cpio.gz
331 18:05:24.628138 - {KERNEL}: 14291400/tftp-deploy-hd_dbfq_/kernel/Image
332 18:05:24.628197 - {LAVA_MAC}: None
333 18:05:24.628255 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1
334 18:05:24.628314 - {NFS_SERVER_IP}: 192.168.201.1
335 18:05:24.628371 - {PRESEED_CONFIG}: None
336 18:05:24.628428 - {PRESEED_LOCAL}: None
337 18:05:24.628483 - {RAMDISK}: 14291400/tftp-deploy-hd_dbfq_/ramdisk/ramdisk.cpio.gz
338 18:05:24.628595 - {ROOT_PART}: None
339 18:05:24.628655 - {ROOT}: None
340 18:05:24.628711 - {SERVER_IP}: 192.168.201.1
341 18:05:24.628766 - {TEE}: None
342 18:05:24.628821 Parsed boot commands:
343 18:05:24.628876 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:05:24.629051 Parsed boot commands: tftpboot 192.168.201.1 14291400/tftp-deploy-hd_dbfq_/kernel/image.itb 14291400/tftp-deploy-hd_dbfq_/kernel/cmdline
345 18:05:24.629142 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:05:24.629230 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:05:24.629324 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:05:24.629408 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:05:24.629485 Not connected, no need to disconnect.
350 18:05:24.629562 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:05:24.629649 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:05:24.629721 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 18:05:24.633015 Setting prompt string to ['lava-test: # ']
354 18:05:24.633390 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:05:24.633502 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:05:24.633599 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:05:24.633692 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:05:24.633925 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 18:05:38.261467 Returned 0 in 13 seconds
360 18:05:38.362102 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 18:05:38.362453 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 18:05:38.362574 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 18:05:38.362671 Setting prompt string to 'Starting depthcharge on Spherion...'
365 18:05:38.362772 Changing prompt to 'Starting depthcharge on Spherion...'
366 18:05:38.362844 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 18:05:38.363269 [Enter `^Ec?' for help]
368 18:05:38.363366
369 18:05:38.363437
370 18:05:38.363518 F0: 102B 0000
371 18:05:38.363599
372 18:05:38.363676 F3: 1001 0000 [0200]
373 18:05:38.363769
374 18:05:38.363844 F3: 1001 0000
375 18:05:38.363901
376 18:05:38.363956 F7: 102D 0000
377 18:05:38.364042
378 18:05:38.364098 F1: 0000 0000
379 18:05:38.364154
380 18:05:38.364209 V0: 0000 0000 [0001]
381 18:05:38.364281
382 18:05:38.364364 00: 0007 8000
383 18:05:38.364436
384 18:05:38.364491 01: 0000 0000
385 18:05:38.364569
386 18:05:38.364643 BP: 0C00 0209 [0000]
387 18:05:38.364728
388 18:05:38.364814 G0: 1182 0000
389 18:05:38.364869
390 18:05:38.364924 EC: 0000 0021 [4000]
391 18:05:38.364978
392 18:05:38.365063 S7: 0000 0000 [0000]
393 18:05:38.365119
394 18:05:38.365173 CC: 0000 0000 [0001]
395 18:05:38.365228
396 18:05:38.365299 T0: 0000 0040 [010F]
397 18:05:38.365368
398 18:05:38.365464 Jump to BL
399 18:05:38.365532
400 18:05:38.365587
401 18:05:38.365670
402 18:05:38.365738 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 18:05:38.365827 ARM64: Exception handlers installed.
404 18:05:38.365900 ARM64: Testing exception
405 18:05:38.365955 ARM64: Done test exception
406 18:05:38.366010 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 18:05:38.366066 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 18:05:38.366151 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 18:05:38.366206 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 18:05:38.366262 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 18:05:38.366347 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 18:05:38.366403 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 18:05:38.366459 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 18:05:38.366514 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 18:05:38.366600 WDT: Last reset was cold boot
416 18:05:38.366655 SPI1(PAD0) initialized at 2873684 Hz
417 18:05:38.366710 SPI5(PAD0) initialized at 992727 Hz
418 18:05:38.366765 VBOOT: Loading verstage.
419 18:05:38.366820 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 18:05:38.366903 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 18:05:38.366959 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 18:05:38.367014 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 18:05:38.367070 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 18:05:38.367126 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 18:05:38.367197 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 18:05:38.367266
427 18:05:38.367320
428 18:05:38.367375 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 18:05:38.367431 ARM64: Exception handlers installed.
430 18:05:38.367486 ARM64: Testing exception
431 18:05:38.367541 ARM64: Done test exception
432 18:05:38.367623 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 18:05:38.367678 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 18:05:38.367733 Probing TPM: . done!
435 18:05:38.367788 TPM ready after 0 ms
436 18:05:38.367842 Connected to device vid:did:rid of 1ae0:0028:00
437 18:05:38.367897 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 18:05:38.367953 Initialized TPM device CR50 revision 0
439 18:05:38.368008 tlcl_send_startup: Startup return code is 0
440 18:05:38.368062 TPM: setup succeeded
441 18:05:38.368117 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 18:05:38.368172 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 18:05:38.368227 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 18:05:38.368311 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 18:05:38.368366 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 18:05:38.368421 in-header: 03 07 00 00 08 00 00 00
447 18:05:38.368476 in-data: aa e4 47 04 13 02 00 00
448 18:05:38.368552 Chrome EC: UHEPI supported
449 18:05:38.368622 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 18:05:38.368678 in-header: 03 a9 00 00 08 00 00 00
451 18:05:38.368733 in-data: 84 60 60 08 00 00 00 00
452 18:05:38.368816 Phase 1
453 18:05:38.368871 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 18:05:38.368942 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 18:05:38.368999 VB2:vb2_check_recovery() Recovery was requested manually
456 18:05:38.369055 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 18:05:38.369139 Recovery requested (1009000e)
458 18:05:38.369207 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 18:05:38.369263 tlcl_extend: response is 0
460 18:05:38.369319 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 18:05:38.369374 tlcl_extend: response is 0
462 18:05:38.369429 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 18:05:38.369485 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 18:05:38.369540 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 18:05:38.369596
466 18:05:38.369678
467 18:05:38.369733 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 18:05:38.369789 ARM64: Exception handlers installed.
469 18:05:38.369844 ARM64: Testing exception
470 18:05:38.369899 ARM64: Done test exception
471 18:05:38.369954 pmic_efuse_setting: Set efuses in 11 msecs
472 18:05:38.370009 pmwrap_interface_init: Select PMIF_VLD_RDY
473 18:05:38.370064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 18:05:38.370119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 18:05:38.370372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 18:05:38.370433 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 18:05:38.370489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 18:05:38.370545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 18:05:38.370629 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 18:05:38.370684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 18:05:38.370739 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 18:05:38.370794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 18:05:38.370850 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 18:05:38.370905 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 18:05:38.370959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 18:05:38.371015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 18:05:38.371070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 18:05:38.371125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 18:05:38.371180 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 18:05:38.371263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 18:05:38.371318 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 18:05:38.371373 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 18:05:38.371428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 18:05:38.371499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 18:05:38.371567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 18:05:38.371622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 18:05:38.371677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 18:05:38.371731 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 18:05:38.371786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 18:05:38.371841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 18:05:38.371896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 18:05:38.371951 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 18:05:38.372006 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 18:05:38.372090 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 18:05:38.372174 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 18:05:38.372242 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 18:05:38.372299 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 18:05:38.372383 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 18:05:38.372439 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 18:05:38.372495 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 18:05:38.372558 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 18:05:38.372630 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 18:05:38.372685 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 18:05:38.372740 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 18:05:38.372795 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 18:05:38.372850 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 18:05:38.372935 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 18:05:38.372989 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 18:05:38.373044 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 18:05:38.373131 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 18:05:38.373185 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 18:05:38.373240 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 18:05:38.373295 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 18:05:38.373379 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 18:05:38.373464 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 18:05:38.373520 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 18:05:38.373575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 18:05:38.373631 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 18:05:38.373687 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 18:05:38.373742 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 18:05:38.373796 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 18:05:38.373851 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
533 18:05:38.373906 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 18:05:38.373961 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 18:05:38.374016 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 18:05:38.374071 [RTC]rtc_get_frequency_meter,154: input=15, output=771
537 18:05:38.374127 [RTC]rtc_get_frequency_meter,154: input=23, output=954
538 18:05:38.374182 [RTC]rtc_get_frequency_meter,154: input=19, output=864
539 18:05:38.374237 [RTC]rtc_get_frequency_meter,154: input=17, output=819
540 18:05:38.374291 [RTC]rtc_get_frequency_meter,154: input=16, output=795
541 18:05:38.374401 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 18:05:38.374455 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 18:05:38.374510 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 18:05:38.374565 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 18:05:38.374806 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 18:05:38.374867 ADC[4]: Raw value=902507 ID=7
547 18:05:38.374923 ADC[3]: Raw value=213179 ID=1
548 18:05:38.375008 RAM Code: 0x71
549 18:05:38.375063 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 18:05:38.375120 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 18:05:38.375175 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 18:05:38.375232 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 18:05:38.375288 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 18:05:38.375344 in-header: 03 07 00 00 08 00 00 00
555 18:05:38.375399 in-data: aa e4 47 04 13 02 00 00
556 18:05:38.375513 Chrome EC: UHEPI supported
557 18:05:38.375621 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 18:05:38.375713 in-header: 03 a9 00 00 08 00 00 00
559 18:05:38.375771 in-data: 84 60 60 08 00 00 00 00
560 18:05:38.375839 MRC: failed to locate region type 0.
561 18:05:38.375928 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 18:05:38.376014 DRAM-K: Running full calibration
563 18:05:38.376100 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 18:05:38.376185 header.status = 0x0
565 18:05:38.376274 header.version = 0x6 (expected: 0x6)
566 18:05:38.376388 header.size = 0xd00 (expected: 0xd00)
567 18:05:38.376473 header.flags = 0x0
568 18:05:38.376588 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 18:05:38.376663 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
570 18:05:38.376720 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 18:05:38.376776 dram_init: ddr_geometry: 2
572 18:05:38.376831 [EMI] MDL number = 2
573 18:05:38.376916 [EMI] Get MDL freq = 0
574 18:05:38.376971 dram_init: ddr_type: 0
575 18:05:38.377025 is_discrete_lpddr4: 1
576 18:05:38.377080 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 18:05:38.377135
578 18:05:38.377189
579 18:05:38.377244 [Bian_co] ETT version 0.0.0.1
580 18:05:38.377298 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 18:05:38.377368
582 18:05:38.377438 dramc_set_vcore_voltage set vcore to 650000
583 18:05:38.377493 Read voltage for 800, 4
584 18:05:38.377547 Vio18 = 0
585 18:05:38.377602 Vcore = 650000
586 18:05:38.377656 Vdram = 0
587 18:05:38.377711 Vddq = 0
588 18:05:38.377765 Vmddr = 0
589 18:05:38.377819 dram_init: config_dvfs: 1
590 18:05:38.377874 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 18:05:38.377929 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 18:05:38.377984 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=10
593 18:05:38.378055 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=10
594 18:05:38.378113 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 18:05:38.378170 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 18:05:38.378226 MEM_TYPE=3, freq_sel=18
597 18:05:38.378310 sv_algorithm_assistance_LP4_1600
598 18:05:38.378379 ============ PULL DRAM RESETB DOWN ============
599 18:05:38.378434 ========== PULL DRAM RESETB DOWN end =========
600 18:05:38.378489 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 18:05:38.378544 ===================================
602 18:05:38.378600 LPDDR4 DRAM CONFIGURATION
603 18:05:38.378654 ===================================
604 18:05:38.378708 EX_ROW_EN[0] = 0x0
605 18:05:38.378763 EX_ROW_EN[1] = 0x0
606 18:05:38.378817 LP4Y_EN = 0x0
607 18:05:38.378871 WORK_FSP = 0x0
608 18:05:38.378947 WL = 0x2
609 18:05:38.379018 RL = 0x2
610 18:05:38.379072 BL = 0x2
611 18:05:38.379126 RPST = 0x0
612 18:05:38.379181 RD_PRE = 0x0
613 18:05:38.379235 WR_PRE = 0x1
614 18:05:38.379289 WR_PST = 0x0
615 18:05:38.379361 DBI_WR = 0x0
616 18:05:38.379428 DBI_RD = 0x0
617 18:05:38.379482 OTF = 0x1
618 18:05:38.379538 ===================================
619 18:05:38.379592 ===================================
620 18:05:38.379647 ANA top config
621 18:05:38.379700 ===================================
622 18:05:38.379755 DLL_ASYNC_EN = 0
623 18:05:38.379810 ALL_SLAVE_EN = 1
624 18:05:38.379865 NEW_RANK_MODE = 1
625 18:05:38.379922 DLL_IDLE_MODE = 1
626 18:05:38.379978 LP45_APHY_COMB_EN = 1
627 18:05:38.380046 TX_ODT_DIS = 1
628 18:05:38.380145 NEW_8X_MODE = 1
629 18:05:38.380204 ===================================
630 18:05:38.380260 ===================================
631 18:05:38.380317 data_rate = 1600
632 18:05:38.380373 CKR = 1
633 18:05:38.380429 DQ_P2S_RATIO = 8
634 18:05:38.380485 ===================================
635 18:05:38.380541 CA_P2S_RATIO = 8
636 18:05:38.380626 DQ_CA_OPEN = 0
637 18:05:38.380724 DQ_SEMI_OPEN = 0
638 18:05:38.380780 CA_SEMI_OPEN = 0
639 18:05:38.380835 CA_FULL_RATE = 0
640 18:05:38.380889 DQ_CKDIV4_EN = 1
641 18:05:38.380944 CA_CKDIV4_EN = 1
642 18:05:38.380998 CA_PREDIV_EN = 0
643 18:05:38.381052 PH8_DLY = 0
644 18:05:38.381106 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 18:05:38.381161 DQ_AAMCK_DIV = 4
646 18:05:38.381215 CA_AAMCK_DIV = 4
647 18:05:38.381269 CA_ADMCK_DIV = 4
648 18:05:38.381342 DQ_TRACK_CA_EN = 0
649 18:05:38.381412 CA_PICK = 800
650 18:05:38.381466 CA_MCKIO = 800
651 18:05:38.381521 MCKIO_SEMI = 0
652 18:05:38.381575 PLL_FREQ = 3068
653 18:05:38.381629 DQ_UI_PI_RATIO = 32
654 18:05:38.381683 CA_UI_PI_RATIO = 0
655 18:05:38.381737 ===================================
656 18:05:38.381792 ===================================
657 18:05:38.381846 memory_type:LPDDR4
658 18:05:38.381901 GP_NUM : 10
659 18:05:38.381956 SRAM_EN : 1
660 18:05:38.382011 MD32_EN : 0
661 18:05:38.382065 ===================================
662 18:05:38.382119 [ANA_INIT] >>>>>>>>>>>>>>
663 18:05:38.382174 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 18:05:38.382231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 18:05:38.382287 ===================================
666 18:05:38.382554 data_rate = 1600,PCW = 0X7600
667 18:05:38.382618 ===================================
668 18:05:38.382675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 18:05:38.382732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 18:05:38.382788 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 18:05:38.382844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 18:05:38.382900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 18:05:38.382956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 18:05:38.383012 [ANA_INIT] flow start
675 18:05:38.383066 [ANA_INIT] PLL >>>>>>>>
676 18:05:38.383121 [ANA_INIT] PLL <<<<<<<<
677 18:05:38.383175 [ANA_INIT] MIDPI >>>>>>>>
678 18:05:38.383229 [ANA_INIT] MIDPI <<<<<<<<
679 18:05:38.383296 [ANA_INIT] DLL >>>>>>>>
680 18:05:38.383364 [ANA_INIT] flow end
681 18:05:38.383419 ============ LP4 DIFF to SE enter ============
682 18:05:38.383474 ============ LP4 DIFF to SE exit ============
683 18:05:38.383528 [ANA_INIT] <<<<<<<<<<<<<
684 18:05:38.383583 [Flow] Enable top DCM control >>>>>
685 18:05:38.383637 [Flow] Enable top DCM control <<<<<
686 18:05:38.383692 Enable DLL master slave shuffle
687 18:05:38.383783 ==============================================================
688 18:05:38.383839 Gating Mode config
689 18:05:38.383894 ==============================================================
690 18:05:38.383949 Config description:
691 18:05:38.384003 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 18:05:38.384060 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 18:05:38.384115 SELPH_MODE 0: By rank 1: By Phase
694 18:05:38.384170 ==============================================================
695 18:05:38.384225 GAT_TRACK_EN = 1
696 18:05:38.384280 RX_GATING_MODE = 2
697 18:05:38.384335 RX_GATING_TRACK_MODE = 2
698 18:05:38.384389 SELPH_MODE = 1
699 18:05:38.384445 PICG_EARLY_EN = 1
700 18:05:38.384499 VALID_LAT_VALUE = 1
701 18:05:38.384593 ==============================================================
702 18:05:38.384649 Enter into Gating configuration >>>>
703 18:05:38.384704 Exit from Gating configuration <<<<
704 18:05:38.384759 Enter into DVFS_PRE_config >>>>>
705 18:05:38.384814 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 18:05:38.384871 Exit from DVFS_PRE_config <<<<<
707 18:05:38.384926 Enter into PICG configuration >>>>
708 18:05:38.384981 Exit from PICG configuration <<<<
709 18:05:38.385035 [RX_INPUT] configuration >>>>>
710 18:05:38.385090 [RX_INPUT] configuration <<<<<
711 18:05:38.385144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 18:05:38.385200 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 18:05:38.385255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 18:05:38.385311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 18:05:38.385366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 18:05:38.385422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 18:05:38.385476 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 18:05:38.385532 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 18:05:38.385587 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 18:05:38.385658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 18:05:38.385735 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 18:05:38.385791 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 18:05:38.385846 ===================================
724 18:05:38.385901 LPDDR4 DRAM CONFIGURATION
725 18:05:38.385956 ===================================
726 18:05:38.386011 EX_ROW_EN[0] = 0x0
727 18:05:38.386065 EX_ROW_EN[1] = 0x0
728 18:05:38.386120 LP4Y_EN = 0x0
729 18:05:38.386175 WORK_FSP = 0x0
730 18:05:38.386229 WL = 0x2
731 18:05:38.386283 RL = 0x2
732 18:05:38.386354 BL = 0x2
733 18:05:38.386431 RPST = 0x0
734 18:05:38.386486 RD_PRE = 0x0
735 18:05:38.386556 WR_PRE = 0x1
736 18:05:38.386611 WR_PST = 0x0
737 18:05:38.386680 DBI_WR = 0x0
738 18:05:38.386734 DBI_RD = 0x0
739 18:05:38.386788 OTF = 0x1
740 18:05:38.386843 ===================================
741 18:05:38.386925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 18:05:38.386997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 18:05:38.387053 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 18:05:38.387108 ===================================
745 18:05:38.387163 LPDDR4 DRAM CONFIGURATION
746 18:05:38.387218 ===================================
747 18:05:38.387273 EX_ROW_EN[0] = 0x10
748 18:05:38.387344 EX_ROW_EN[1] = 0x0
749 18:05:38.387429 LP4Y_EN = 0x0
750 18:05:38.387522 WORK_FSP = 0x0
751 18:05:38.387619 WL = 0x2
752 18:05:38.387689 RL = 0x2
753 18:05:38.387774 BL = 0x2
754 18:05:38.387843 RPST = 0x0
755 18:05:38.387914 RD_PRE = 0x0
756 18:05:38.387998 WR_PRE = 0x1
757 18:05:38.388053 WR_PST = 0x0
758 18:05:38.388109 DBI_WR = 0x0
759 18:05:38.388164 DBI_RD = 0x0
760 18:05:38.388232 OTF = 0x1
761 18:05:38.388287 ===================================
762 18:05:38.388342 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 18:05:38.388398 nWR fixed to 40
764 18:05:38.388453 [ModeRegInit_LP4] CH0 RK0
765 18:05:38.388507 [ModeRegInit_LP4] CH0 RK1
766 18:05:38.388612 [ModeRegInit_LP4] CH1 RK0
767 18:05:38.388698 [ModeRegInit_LP4] CH1 RK1
768 18:05:38.388813 match AC timing 13
769 18:05:38.388887 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 18:05:38.388944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 18:05:38.388999 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 18:05:38.389055 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 18:05:38.389304 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 18:05:38.389431 [EMI DOE] emi_dcm 0
775 18:05:38.389552 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 18:05:38.389657 ==
777 18:05:38.389761 Dram Type= 6, Freq= 0, CH_0, rank 0
778 18:05:38.389849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 18:05:38.389935 ==
780 18:05:38.390022 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 18:05:38.390109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 18:05:38.390194 [CA 0] Center 38 (7~69) winsize 63
783 18:05:38.390280 [CA 1] Center 38 (7~69) winsize 63
784 18:05:38.390369 [CA 2] Center 35 (5~66) winsize 62
785 18:05:38.390454 [CA 3] Center 35 (5~66) winsize 62
786 18:05:38.390539 [CA 4] Center 34 (4~65) winsize 62
787 18:05:38.390623 [CA 5] Center 34 (3~65) winsize 63
788 18:05:38.390708
789 18:05:38.390799 [CmdBusTrainingLP45] Vref(ca) range 1: 34
790 18:05:38.390885
791 18:05:38.390970 [CATrainingPosCal] consider 1 rank data
792 18:05:38.391056 u2DelayCellTimex100 = 270/100 ps
793 18:05:38.391141 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
794 18:05:38.391226 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
795 18:05:38.391312 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
796 18:05:38.391397 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
797 18:05:38.391488 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
798 18:05:38.391574 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
799 18:05:38.391658
800 18:05:38.391743 CA PerBit enable=1, Macro0, CA PI delay=34
801 18:05:38.391827
802 18:05:38.391912 [CBTSetCACLKResult] CA Dly = 34
803 18:05:38.392001 CS Dly: 6 (0~37)
804 18:05:38.392120 ==
805 18:05:38.392209 Dram Type= 6, Freq= 0, CH_0, rank 1
806 18:05:38.392295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 18:05:38.392380 ==
808 18:05:38.392490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 18:05:38.392593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 18:05:38.392652 [CA 0] Center 38 (7~69) winsize 63
811 18:05:38.392708 [CA 1] Center 38 (8~69) winsize 62
812 18:05:38.392764 [CA 2] Center 36 (6~67) winsize 62
813 18:05:38.392819 [CA 3] Center 36 (5~67) winsize 63
814 18:05:38.392882 [CA 4] Center 35 (4~66) winsize 63
815 18:05:38.392939 [CA 5] Center 34 (4~65) winsize 62
816 18:05:38.392994
817 18:05:38.393049 [CmdBusTrainingLP45] Vref(ca) range 1: 34
818 18:05:38.393103
819 18:05:38.393178 [CATrainingPosCal] consider 2 rank data
820 18:05:38.393247 u2DelayCellTimex100 = 270/100 ps
821 18:05:38.393302 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 18:05:38.393371 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 18:05:38.393427 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 18:05:38.393482 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 18:05:38.393537 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
826 18:05:38.393592 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
827 18:05:38.393646
828 18:05:38.393701 CA PerBit enable=1, Macro0, CA PI delay=34
829 18:05:38.393756
830 18:05:38.393810 [CBTSetCACLKResult] CA Dly = 34
831 18:05:38.393865 CS Dly: 6 (0~38)
832 18:05:38.393929
833 18:05:38.393984 ----->DramcWriteLeveling(PI) begin...
834 18:05:38.394040 ==
835 18:05:38.394095 Dram Type= 6, Freq= 0, CH_0, rank 0
836 18:05:38.394150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 18:05:38.394205 ==
838 18:05:38.394291 Write leveling (Byte 0): 33 => 33
839 18:05:38.394346 Write leveling (Byte 1): 28 => 28
840 18:05:38.394409 DramcWriteLeveling(PI) end<-----
841 18:05:38.394466
842 18:05:38.394540 ==
843 18:05:38.394606 Dram Type= 6, Freq= 0, CH_0, rank 0
844 18:05:38.394664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 18:05:38.394720 ==
846 18:05:38.394790 [Gating] SW mode calibration
847 18:05:38.394859 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 18:05:38.394956 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 18:05:38.395044 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 18:05:38.395113 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 18:05:38.395169 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 18:05:38.395223 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 18:05:38.395278 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 18:05:38.395332 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 18:05:38.395386 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 18:05:38.395469 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 18:05:38.395526 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 18:05:38.395583 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:05:38.395639 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:05:38.395695 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:05:38.395751 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:05:38.395831 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:05:38.395917 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 18:05:38.396040 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 18:05:38.396125 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 18:05:38.396242 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 18:05:38.396327 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
868 18:05:38.396412 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 18:05:38.396497 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 18:05:38.396619 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 18:05:38.396676 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 18:05:38.396732 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 18:05:38.396787 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 18:05:38.396842 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
875 18:05:38.396897 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
876 18:05:38.396968 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
877 18:05:38.397038 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 18:05:38.397092 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 18:05:38.397148 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 18:05:38.397203 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 18:05:38.397507 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 18:05:38.397586 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
883 18:05:38.397644 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
884 18:05:38.397700 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 18:05:38.397801 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 18:05:38.397891 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 18:05:38.397961 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 18:05:38.398017 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 18:05:38.398072 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 18:05:38.398156 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
891 18:05:38.398211 0 11 8 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
892 18:05:38.398266 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
893 18:05:38.398336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 18:05:38.398404 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 18:05:38.398502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 18:05:38.398570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 18:05:38.398625 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 18:05:38.398693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 18:05:38.398778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 18:05:38.398870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 18:05:38.398970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 18:05:38.399039 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 18:05:38.399108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 18:05:38.399163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 18:05:38.399217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 18:05:38.399272 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 18:05:38.399327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 18:05:38.399381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 18:05:38.399460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 18:05:38.399520 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 18:05:38.399617 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 18:05:38.399676 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 18:05:38.399731 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 18:05:38.399787 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 18:05:38.399841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 18:05:38.399895 Total UI for P1: 0, mck2ui 16
917 18:05:38.399951 best dqsien dly found for B0: ( 0, 14, 4)
918 18:05:38.400030 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 18:05:38.400088 Total UI for P1: 0, mck2ui 16
920 18:05:38.400157 best dqsien dly found for B1: ( 0, 14, 8)
921 18:05:38.400212 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
922 18:05:38.400267 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
923 18:05:38.400322
924 18:05:38.400376 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
925 18:05:38.400452 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
926 18:05:38.400515 [Gating] SW calibration Done
927 18:05:38.400578 ==
928 18:05:38.400635 Dram Type= 6, Freq= 0, CH_0, rank 0
929 18:05:38.400692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 18:05:38.400748 ==
931 18:05:38.400805 RX Vref Scan: 0
932 18:05:38.400861
933 18:05:38.400917 RX Vref 0 -> 0, step: 1
934 18:05:38.400973
935 18:05:38.401038 RX Delay -130 -> 252, step: 16
936 18:05:38.401097 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
937 18:05:38.401157 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 18:05:38.401238 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 18:05:38.401296 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 18:05:38.401353 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 18:05:38.401410 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 18:05:38.401468 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 18:05:38.401533 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 18:05:38.401589 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 18:05:38.401646 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
946 18:05:38.401716 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 18:05:38.401772 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 18:05:38.401827 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
949 18:05:38.401882 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 18:05:38.401966 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 18:05:38.402037 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
952 18:05:38.402091 ==
953 18:05:38.402148 Dram Type= 6, Freq= 0, CH_0, rank 0
954 18:05:38.402203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 18:05:38.402258 ==
956 18:05:38.402314 DQS Delay:
957 18:05:38.402385 DQS0 = 0, DQS1 = 0
958 18:05:38.402441 DQM Delay:
959 18:05:38.402500 DQM0 = 91, DQM1 = 79
960 18:05:38.402564 DQ Delay:
961 18:05:38.402621 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
962 18:05:38.402677 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 18:05:38.402734 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
964 18:05:38.402804 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
965 18:05:38.402858
966 18:05:38.402913
967 18:05:38.402967 ==
968 18:05:38.403022 Dram Type= 6, Freq= 0, CH_0, rank 0
969 18:05:38.403096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 18:05:38.403159 ==
971 18:05:38.403228
972 18:05:38.403282
973 18:05:38.403337 TX Vref Scan disable
974 18:05:38.403391 == TX Byte 0 ==
975 18:05:38.403446 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
976 18:05:38.403502 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
977 18:05:38.403557 == TX Byte 1 ==
978 18:05:38.403611 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
979 18:05:38.403686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
980 18:05:38.403749 ==
981 18:05:38.403819 Dram Type= 6, Freq= 0, CH_0, rank 0
982 18:05:38.403874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 18:05:38.403930 ==
984 18:05:38.403986 TX Vref=22, minBit 8, minWin=26, winSum=440
985 18:05:38.404042 TX Vref=24, minBit 8, minWin=27, winSum=445
986 18:05:38.404119 TX Vref=26, minBit 0, minWin=28, winSum=451
987 18:05:38.404179 TX Vref=28, minBit 13, minWin=27, winSum=453
988 18:05:38.404248 TX Vref=30, minBit 3, minWin=28, winSum=455
989 18:05:38.404510 TX Vref=32, minBit 5, minWin=28, winSum=454
990 18:05:38.404612 [TxChooseVref] Worse bit 3, Min win 28, Win sum 455, Final Vref 30
991 18:05:38.404671
992 18:05:38.404727 Final TX Range 1 Vref 30
993 18:05:38.404783
994 18:05:38.404838 ==
995 18:05:38.404894 Dram Type= 6, Freq= 0, CH_0, rank 0
996 18:05:38.404949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 18:05:38.405005 ==
998 18:05:38.405092
999 18:05:38.405150
1000 18:05:38.405219 TX Vref Scan disable
1001 18:05:38.405274 == TX Byte 0 ==
1002 18:05:38.405330 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1003 18:05:38.405386 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1004 18:05:38.405441 == TX Byte 1 ==
1005 18:05:38.405495 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1006 18:05:38.405550 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1007 18:05:38.405636
1008 18:05:38.405707 [DATLAT]
1009 18:05:38.405763 Freq=800, CH0 RK0
1010 18:05:38.405818
1011 18:05:38.405874 DATLAT Default: 0xa
1012 18:05:38.405930 0, 0xFFFF, sum = 0
1013 18:05:38.406004 1, 0xFFFF, sum = 0
1014 18:05:38.406061 2, 0xFFFF, sum = 0
1015 18:05:38.406133 3, 0xFFFF, sum = 0
1016 18:05:38.406192 4, 0xFFFF, sum = 0
1017 18:05:38.406248 5, 0xFFFF, sum = 0
1018 18:05:38.406305 6, 0xFFFF, sum = 0
1019 18:05:38.406375 7, 0xFFFF, sum = 0
1020 18:05:38.406431 8, 0xFFFF, sum = 0
1021 18:05:38.406487 9, 0x0, sum = 1
1022 18:05:38.406542 10, 0x0, sum = 2
1023 18:05:38.406612 11, 0x0, sum = 3
1024 18:05:38.406681 12, 0x0, sum = 4
1025 18:05:38.406761 best_step = 10
1026 18:05:38.406819
1027 18:05:38.406874 ==
1028 18:05:38.406929 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 18:05:38.406984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 18:05:38.407039 ==
1031 18:05:38.407093 RX Vref Scan: 1
1032 18:05:38.407176
1033 18:05:38.407247 Set Vref Range= 32 -> 127
1034 18:05:38.407302
1035 18:05:38.407355 RX Vref 32 -> 127, step: 1
1036 18:05:38.407409
1037 18:05:38.407463 RX Delay -79 -> 252, step: 8
1038 18:05:38.407518
1039 18:05:38.407571 Set Vref, RX VrefLevel [Byte0]: 32
1040 18:05:38.407626 [Byte1]: 32
1041 18:05:38.407710
1042 18:05:38.407780 Set Vref, RX VrefLevel [Byte0]: 33
1043 18:05:38.407835 [Byte1]: 33
1044 18:05:38.407890
1045 18:05:38.407945 Set Vref, RX VrefLevel [Byte0]: 34
1046 18:05:38.407999 [Byte1]: 34
1047 18:05:38.408053
1048 18:05:38.408107 Set Vref, RX VrefLevel [Byte0]: 35
1049 18:05:38.408162 [Byte1]: 35
1050 18:05:38.408246
1051 18:05:38.408316 Set Vref, RX VrefLevel [Byte0]: 36
1052 18:05:38.408370 [Byte1]: 36
1053 18:05:38.408425
1054 18:05:38.408479 Set Vref, RX VrefLevel [Byte0]: 37
1055 18:05:38.408533 [Byte1]: 37
1056 18:05:38.408614
1057 18:05:38.408669 Set Vref, RX VrefLevel [Byte0]: 38
1058 18:05:38.408737 [Byte1]: 38
1059 18:05:38.408806
1060 18:05:38.408860 Set Vref, RX VrefLevel [Byte0]: 39
1061 18:05:38.408947 [Byte1]: 39
1062 18:05:38.409001
1063 18:05:38.409055 Set Vref, RX VrefLevel [Byte0]: 40
1064 18:05:38.409110 [Byte1]: 40
1065 18:05:38.409164
1066 18:05:38.409248 Set Vref, RX VrefLevel [Byte0]: 41
1067 18:05:38.409319 [Byte1]: 41
1068 18:05:38.409373
1069 18:05:38.409427 Set Vref, RX VrefLevel [Byte0]: 42
1070 18:05:38.409481 [Byte1]: 42
1071 18:05:38.409535
1072 18:05:38.409589 Set Vref, RX VrefLevel [Byte0]: 43
1073 18:05:38.409643 [Byte1]: 43
1074 18:05:38.409697
1075 18:05:38.409750 Set Vref, RX VrefLevel [Byte0]: 44
1076 18:05:38.409830 [Byte1]: 44
1077 18:05:38.409887
1078 18:05:38.409955 Set Vref, RX VrefLevel [Byte0]: 45
1079 18:05:38.410010 [Byte1]: 45
1080 18:05:38.410064
1081 18:05:38.410117 Set Vref, RX VrefLevel [Byte0]: 46
1082 18:05:38.410171 [Byte1]: 46
1083 18:05:38.410225
1084 18:05:38.410279 Set Vref, RX VrefLevel [Byte0]: 47
1085 18:05:38.410333 [Byte1]: 47
1086 18:05:38.410411
1087 18:05:38.410469 Set Vref, RX VrefLevel [Byte0]: 48
1088 18:05:38.410538 [Byte1]: 48
1089 18:05:38.410592
1090 18:05:38.410645 Set Vref, RX VrefLevel [Byte0]: 49
1091 18:05:38.410699 [Byte1]: 49
1092 18:05:38.410753
1093 18:05:38.410807 Set Vref, RX VrefLevel [Byte0]: 50
1094 18:05:38.410861 [Byte1]: 50
1095 18:05:38.410945
1096 18:05:38.411016 Set Vref, RX VrefLevel [Byte0]: 51
1097 18:05:38.411071 [Byte1]: 51
1098 18:05:38.411124
1099 18:05:38.411178 Set Vref, RX VrefLevel [Byte0]: 52
1100 18:05:38.411233 [Byte1]: 52
1101 18:05:38.411287
1102 18:05:38.411341 Set Vref, RX VrefLevel [Byte0]: 53
1103 18:05:38.411421 [Byte1]: 53
1104 18:05:38.411479
1105 18:05:38.411548 Set Vref, RX VrefLevel [Byte0]: 54
1106 18:05:38.411602 [Byte1]: 54
1107 18:05:38.411656
1108 18:05:38.411710 Set Vref, RX VrefLevel [Byte0]: 55
1109 18:05:38.411764 [Byte1]: 55
1110 18:05:38.411819
1111 18:05:38.411893 Set Vref, RX VrefLevel [Byte0]: 56
1112 18:05:38.411954 [Byte1]: 56
1113 18:05:38.412022
1114 18:05:38.412076 Set Vref, RX VrefLevel [Byte0]: 57
1115 18:05:38.412131 [Byte1]: 57
1116 18:05:38.412201
1117 18:05:38.412256 Set Vref, RX VrefLevel [Byte0]: 58
1118 18:05:38.412311 [Byte1]: 58
1119 18:05:38.412379
1120 18:05:38.412436 Set Vref, RX VrefLevel [Byte0]: 59
1121 18:05:38.412493 [Byte1]: 59
1122 18:05:38.412599
1123 18:05:38.412656 Set Vref, RX VrefLevel [Byte0]: 60
1124 18:05:38.412712 [Byte1]: 60
1125 18:05:38.412767
1126 18:05:38.412842 Set Vref, RX VrefLevel [Byte0]: 61
1127 18:05:38.412903 [Byte1]: 61
1128 18:05:38.412972
1129 18:05:38.413026 Set Vref, RX VrefLevel [Byte0]: 62
1130 18:05:38.413080 [Byte1]: 62
1131 18:05:38.413134
1132 18:05:38.413188 Set Vref, RX VrefLevel [Byte0]: 63
1133 18:05:38.413241 [Byte1]: 63
1134 18:05:38.413295
1135 18:05:38.413349 Set Vref, RX VrefLevel [Byte0]: 64
1136 18:05:38.413418 [Byte1]: 64
1137 18:05:38.413485
1138 18:05:38.413555 Set Vref, RX VrefLevel [Byte0]: 65
1139 18:05:38.413609 [Byte1]: 65
1140 18:05:38.413663
1141 18:05:38.413716 Set Vref, RX VrefLevel [Byte0]: 66
1142 18:05:38.413770 [Byte1]: 66
1143 18:05:38.413823
1144 18:05:38.413900 Set Vref, RX VrefLevel [Byte0]: 67
1145 18:05:38.413958 [Byte1]: 67
1146 18:05:38.414026
1147 18:05:38.414079 Set Vref, RX VrefLevel [Byte0]: 68
1148 18:05:38.414132 [Byte1]: 68
1149 18:05:38.414186
1150 18:05:38.414240 Set Vref, RX VrefLevel [Byte0]: 69
1151 18:05:38.414295 [Byte1]: 69
1152 18:05:38.414349
1153 18:05:38.414419 Set Vref, RX VrefLevel [Byte0]: 70
1154 18:05:38.414487 [Byte1]: 70
1155 18:05:38.414557
1156 18:05:38.414610 Set Vref, RX VrefLevel [Byte0]: 71
1157 18:05:38.414665 [Byte1]: 71
1158 18:05:38.414719
1159 18:05:38.414772 Set Vref, RX VrefLevel [Byte0]: 72
1160 18:05:38.415023 [Byte1]: 72
1161 18:05:38.415099
1162 18:05:38.415155 Set Vref, RX VrefLevel [Byte0]: 73
1163 18:05:38.415210 [Byte1]: 73
1164 18:05:38.415264
1165 18:05:38.415318 Set Vref, RX VrefLevel [Byte0]: 74
1166 18:05:38.415373 [Byte1]: 74
1167 18:05:38.415427
1168 18:05:38.415507 Set Vref, RX VrefLevel [Byte0]: 75
1169 18:05:38.415565 [Byte1]: 75
1170 18:05:38.415632
1171 18:05:38.415685 Set Vref, RX VrefLevel [Byte0]: 76
1172 18:05:38.415739 [Byte1]: 76
1173 18:05:38.415794
1174 18:05:38.415847 Set Vref, RX VrefLevel [Byte0]: 77
1175 18:05:38.415901 [Byte1]: 77
1176 18:05:38.415955
1177 18:05:38.416008 Set Vref, RX VrefLevel [Byte0]: 78
1178 18:05:38.416062 [Byte1]: 78
1179 18:05:38.416146
1180 18:05:38.416215 Set Vref, RX VrefLevel [Byte0]: 79
1181 18:05:38.416270 [Byte1]: 79
1182 18:05:38.416324
1183 18:05:38.416391 Set Vref, RX VrefLevel [Byte0]: 80
1184 18:05:38.416446 [Byte1]: 80
1185 18:05:38.416502
1186 18:05:38.416602 Final RX Vref Byte 0 = 63 to rank0
1187 18:05:38.416659 Final RX Vref Byte 1 = 56 to rank0
1188 18:05:38.416713 Final RX Vref Byte 0 = 63 to rank1
1189 18:05:38.416768 Final RX Vref Byte 1 = 56 to rank1==
1190 18:05:38.416823 Dram Type= 6, Freq= 0, CH_0, rank 0
1191 18:05:38.416877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1192 18:05:38.416932 ==
1193 18:05:38.416986 DQS Delay:
1194 18:05:38.417041 DQS0 = 0, DQS1 = 0
1195 18:05:38.417125 DQM Delay:
1196 18:05:38.417196 DQM0 = 93, DQM1 = 81
1197 18:05:38.417250 DQ Delay:
1198 18:05:38.417304 DQ0 =96, DQ1 =96, DQ2 =88, DQ3 =88
1199 18:05:38.417359 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1200 18:05:38.417413 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1201 18:05:38.417467 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1202 18:05:38.417520
1203 18:05:38.417574
1204 18:05:38.417628 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1205 18:05:38.417713 CH0 RK0: MR19=606, MR18=3D39
1206 18:05:38.417784 CH0_RK0: MR19=0x606, MR18=0x3D39, DQSOSC=394, MR23=63, INC=95, DEC=63
1207 18:05:38.417839
1208 18:05:38.417893 ----->DramcWriteLeveling(PI) begin...
1209 18:05:38.417948 ==
1210 18:05:38.418002 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 18:05:38.418056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 18:05:38.418141 ==
1213 18:05:38.418211 Write leveling (Byte 0): 33 => 33
1214 18:05:38.418265 Write leveling (Byte 1): 29 => 29
1215 18:05:38.418320 DramcWriteLeveling(PI) end<-----
1216 18:05:38.418374
1217 18:05:38.418428 ==
1218 18:05:38.418498 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 18:05:38.418586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1220 18:05:38.418684 ==
1221 18:05:38.418768 [Gating] SW mode calibration
1222 18:05:38.418853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1223 18:05:38.418939 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1224 18:05:38.419024 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 18:05:38.419113 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1226 18:05:38.419183 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:05:38.419238 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:05:38.419292 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 18:05:38.419347 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:05:38.419401 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 18:05:38.419455 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 18:05:38.419512 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 18:05:38.419601 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 18:05:38.419700 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 18:05:38.419785 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 18:05:38.419869 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 18:05:38.419926 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 18:05:38.419981 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 18:05:38.420035 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 18:05:38.420115 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 18:05:38.420174 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1242 18:05:38.420243 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1243 18:05:38.420297 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 18:05:38.420351 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 18:05:38.420406 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 18:05:38.420460 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 18:05:38.420530 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 18:05:38.420597 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 18:05:38.420667 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 18:05:38.420723 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1251 18:05:38.420779 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 18:05:38.420877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 18:05:38.420931 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 18:05:38.420986 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 18:05:38.421040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 18:05:38.421094 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 18:05:38.421164 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1258 18:05:38.421232 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1259 18:05:38.421302 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 18:05:38.421356 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 18:05:38.421410 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 18:05:38.421464 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 18:05:38.421518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 18:05:38.421572 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 18:05:38.421627 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1266 18:05:38.421697 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1267 18:05:38.421760 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 18:05:38.421816 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 18:05:38.422064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 18:05:38.422128 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 18:05:38.422185 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 18:05:38.422242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 18:05:38.422298 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 18:05:38.422368 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1275 18:05:38.422422 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 18:05:38.422476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 18:05:38.422530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 18:05:38.422584 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 18:05:38.422638 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 18:05:38.422692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 18:05:38.422746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 18:05:38.422817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 18:05:38.422872 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 18:05:38.422940 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 18:05:38.422993 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 18:05:38.423047 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 18:05:38.423100 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 18:05:38.423154 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 18:05:38.423208 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 18:05:38.423262 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1291 18:05:38.423331 Total UI for P1: 0, mck2ui 16
1292 18:05:38.423387 best dqsien dly found for B0: ( 0, 14, 6)
1293 18:05:38.423443 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1294 18:05:38.423499 Total UI for P1: 0, mck2ui 16
1295 18:05:38.423554 best dqsien dly found for B1: ( 0, 14, 8)
1296 18:05:38.423609 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1297 18:05:38.423665 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1298 18:05:38.423720
1299 18:05:38.423777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1300 18:05:38.423837 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1301 18:05:38.423906 [Gating] SW calibration Done
1302 18:05:38.423960 ==
1303 18:05:38.424014 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 18:05:38.424068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 18:05:38.424123 ==
1306 18:05:38.424178 RX Vref Scan: 0
1307 18:05:38.424231
1308 18:05:38.424284 RX Vref 0 -> 0, step: 1
1309 18:05:38.424338
1310 18:05:38.424421 RX Delay -130 -> 252, step: 16
1311 18:05:38.424508 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1312 18:05:38.424603 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1313 18:05:38.424660 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1314 18:05:38.424715 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1315 18:05:38.424770 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1316 18:05:38.424839 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1317 18:05:38.424910 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1318 18:05:38.424980 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1319 18:05:38.425035 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1320 18:05:38.425089 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1321 18:05:38.425143 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1322 18:05:38.425197 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1323 18:05:38.425252 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1324 18:05:38.425306 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1325 18:05:38.425360 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1326 18:05:38.425414 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1327 18:05:38.425497 ==
1328 18:05:38.425567 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 18:05:38.425622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 18:05:38.425677 ==
1331 18:05:38.425731 DQS Delay:
1332 18:05:38.425785 DQS0 = 0, DQS1 = 0
1333 18:05:38.425838 DQM Delay:
1334 18:05:38.425892 DQM0 = 87, DQM1 = 80
1335 18:05:38.425968 DQ Delay:
1336 18:05:38.426028 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1337 18:05:38.426096 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1338 18:05:38.426150 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1339 18:05:38.426204 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1340 18:05:38.426258
1341 18:05:38.426311
1342 18:05:38.426365 ==
1343 18:05:38.426418 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 18:05:38.426490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 18:05:38.426553 ==
1346 18:05:38.426622
1347 18:05:38.426675
1348 18:05:38.426728 TX Vref Scan disable
1349 18:05:38.426782 == TX Byte 0 ==
1350 18:05:38.426836 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1351 18:05:38.426909 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1352 18:05:38.426972 == TX Byte 1 ==
1353 18:05:38.427040 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1354 18:05:38.427095 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1355 18:05:38.427150 ==
1356 18:05:38.427204 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 18:05:38.427257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 18:05:38.427312 ==
1359 18:05:38.427387 TX Vref=22, minBit 1, minWin=27, winSum=447
1360 18:05:38.427448 TX Vref=24, minBit 8, minWin=27, winSum=451
1361 18:05:38.427516 TX Vref=26, minBit 8, minWin=27, winSum=453
1362 18:05:38.427569 TX Vref=28, minBit 8, minWin=27, winSum=453
1363 18:05:38.427622 TX Vref=30, minBit 9, minWin=27, winSum=457
1364 18:05:38.427675 TX Vref=32, minBit 8, minWin=27, winSum=456
1365 18:05:38.427728 [TxChooseVref] Worse bit 9, Min win 27, Win sum 457, Final Vref 30
1366 18:05:38.427780
1367 18:05:38.427862 Final TX Range 1 Vref 30
1368 18:05:38.427931
1369 18:05:38.427983 ==
1370 18:05:38.428035 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 18:05:38.428088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 18:05:38.428141 ==
1373 18:05:38.428193
1374 18:05:38.428244
1375 18:05:38.428312 TX Vref Scan disable
1376 18:05:38.428378 == TX Byte 0 ==
1377 18:05:38.428433 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1378 18:05:38.428487 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1379 18:05:38.428541 == TX Byte 1 ==
1380 18:05:38.428610 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1381 18:05:38.428664 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1382 18:05:38.428718
1383 18:05:38.428771 [DATLAT]
1384 18:05:38.428824 Freq=800, CH0 RK1
1385 18:05:38.428890
1386 18:05:38.428943 DATLAT Default: 0xa
1387 18:05:38.428997 0, 0xFFFF, sum = 0
1388 18:05:38.429053 1, 0xFFFF, sum = 0
1389 18:05:38.429108 2, 0xFFFF, sum = 0
1390 18:05:38.429163 3, 0xFFFF, sum = 0
1391 18:05:38.429217 4, 0xFFFF, sum = 0
1392 18:05:38.429272 5, 0xFFFF, sum = 0
1393 18:05:38.429524 6, 0xFFFF, sum = 0
1394 18:05:38.429587 7, 0xFFFF, sum = 0
1395 18:05:38.429643 8, 0xFFFF, sum = 0
1396 18:05:38.429698 9, 0x0, sum = 1
1397 18:05:38.429753 10, 0x0, sum = 2
1398 18:05:38.429816 11, 0x0, sum = 3
1399 18:05:38.429873 12, 0x0, sum = 4
1400 18:05:38.429927 best_step = 10
1401 18:05:38.429981
1402 18:05:38.430035 ==
1403 18:05:38.430088 Dram Type= 6, Freq= 0, CH_0, rank 1
1404 18:05:38.430144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 18:05:38.430199 ==
1406 18:05:38.430267 RX Vref Scan: 0
1407 18:05:38.430322
1408 18:05:38.430376 RX Vref 0 -> 0, step: 1
1409 18:05:38.430429
1410 18:05:38.430483 RX Delay -95 -> 252, step: 8
1411 18:05:38.430537 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1412 18:05:38.430591 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1413 18:05:38.430645 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1414 18:05:38.430699 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1415 18:05:38.430754 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1416 18:05:38.430821 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1417 18:05:38.430877 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1418 18:05:38.430945 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1419 18:05:38.431043 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1420 18:05:38.431110 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1421 18:05:38.431162 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1422 18:05:38.431214 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1423 18:05:38.431267 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1424 18:05:38.431319 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1425 18:05:38.431396 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1426 18:05:38.431452 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1427 18:05:38.431520 ==
1428 18:05:38.431572 Dram Type= 6, Freq= 0, CH_0, rank 1
1429 18:05:38.431625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 18:05:38.431677 ==
1431 18:05:38.431730 DQS Delay:
1432 18:05:38.431782 DQS0 = 0, DQS1 = 0
1433 18:05:38.431834 DQM Delay:
1434 18:05:38.431906 DQM0 = 91, DQM1 = 82
1435 18:05:38.431965 DQ Delay:
1436 18:05:38.432032 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1437 18:05:38.432084 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1438 18:05:38.432136 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1439 18:05:38.432205 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1440 18:05:38.432261
1441 18:05:38.432319
1442 18:05:38.432373 [DQSOSCAuto] RK1, (LSB)MR18= 0x441d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1443 18:05:38.432429 CH0 RK1: MR19=606, MR18=441D
1444 18:05:38.432483 CH0_RK1: MR19=0x606, MR18=0x441D, DQSOSC=392, MR23=63, INC=96, DEC=64
1445 18:05:38.432538 [RxdqsGatingPostProcess] freq 800
1446 18:05:38.432601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1447 18:05:38.432656 Pre-setting of DQS Precalculation
1448 18:05:38.432709 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1449 18:05:38.432763 ==
1450 18:05:38.432817 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 18:05:38.432876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 18:05:38.432933 ==
1453 18:05:38.432987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 18:05:38.433044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 18:05:38.433114 [CA 0] Center 36 (6~67) winsize 62
1456 18:05:38.433186 [CA 1] Center 36 (6~67) winsize 62
1457 18:05:38.433241 [CA 2] Center 34 (4~65) winsize 62
1458 18:05:38.433300 [CA 3] Center 34 (3~65) winsize 63
1459 18:05:38.433357 [CA 4] Center 34 (4~65) winsize 62
1460 18:05:38.433411 [CA 5] Center 34 (3~65) winsize 63
1461 18:05:38.433465
1462 18:05:38.433519 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1463 18:05:38.433573
1464 18:05:38.433626 [CATrainingPosCal] consider 1 rank data
1465 18:05:38.433707 u2DelayCellTimex100 = 270/100 ps
1466 18:05:38.433804 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 18:05:38.433887 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1468 18:05:38.433969 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 18:05:38.434052 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1470 18:05:38.434153 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 18:05:38.434251 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1472 18:05:38.434332
1473 18:05:38.434414 CA PerBit enable=1, Macro0, CA PI delay=34
1474 18:05:38.434513
1475 18:05:38.434586 [CBTSetCACLKResult] CA Dly = 34
1476 18:05:38.434656 CS Dly: 4 (0~35)
1477 18:05:38.434709 ==
1478 18:05:38.434778 Dram Type= 6, Freq= 0, CH_1, rank 1
1479 18:05:38.434844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1480 18:05:38.434898 ==
1481 18:05:38.434951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1482 18:05:38.435004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1483 18:05:38.435058 [CA 0] Center 37 (6~68) winsize 63
1484 18:05:38.435147 [CA 1] Center 37 (6~68) winsize 63
1485 18:05:38.435263 [CA 2] Center 35 (4~66) winsize 63
1486 18:05:38.435358 [CA 3] Center 34 (4~65) winsize 62
1487 18:05:38.435453 [CA 4] Center 34 (4~65) winsize 62
1488 18:05:38.435564 [CA 5] Center 34 (4~65) winsize 62
1489 18:05:38.435665
1490 18:05:38.435777 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1491 18:05:38.435874
1492 18:05:38.435969 [CATrainingPosCal] consider 2 rank data
1493 18:05:38.436063 u2DelayCellTimex100 = 270/100 ps
1494 18:05:38.436159 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 18:05:38.436275 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1496 18:05:38.436390 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 18:05:38.436486 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1498 18:05:38.436623 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 18:05:38.436719 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1500 18:05:38.436813
1501 18:05:38.436924 CA PerBit enable=1, Macro0, CA PI delay=34
1502 18:05:38.437022
1503 18:05:38.437138 [CBTSetCACLKResult] CA Dly = 34
1504 18:05:38.437234 CS Dly: 5 (0~38)
1505 18:05:38.437329
1506 18:05:38.437422 ----->DramcWriteLeveling(PI) begin...
1507 18:05:38.437517 ==
1508 18:05:38.437632 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 18:05:38.437747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 18:05:38.437844 ==
1511 18:05:38.437938 Write leveling (Byte 0): 27 => 27
1512 18:05:38.438034 Write leveling (Byte 1): 29 => 29
1513 18:05:38.438148 DramcWriteLeveling(PI) end<-----
1514 18:05:38.438277
1515 18:05:38.438387 ==
1516 18:05:38.438483 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 18:05:38.438578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 18:05:38.438674 ==
1519 18:05:38.438768 [Gating] SW mode calibration
1520 18:05:38.438901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1521 18:05:38.439234 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1522 18:05:38.439335 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1523 18:05:38.439437 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1524 18:05:38.439554 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1525 18:05:38.439680 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 18:05:38.439787 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:05:38.439849 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:05:38.439904 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 18:05:38.439957 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 18:05:38.440011 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 18:05:38.440092 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 18:05:38.440181 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 18:05:38.440241 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 18:05:38.440323 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 18:05:38.440383 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 18:05:38.440462 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 18:05:38.440557 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 18:05:38.440655 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 18:05:38.440739 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1540 18:05:38.440821 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1541 18:05:38.440904 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 18:05:38.440961 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 18:05:38.441015 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 18:05:38.441069 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 18:05:38.441122 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 18:05:38.441175 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 18:05:38.441228 0 9 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1548 18:05:38.441281 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1549 18:05:38.441334 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 18:05:38.441386 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 18:05:38.441453 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 18:05:38.441511 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 18:05:38.441569 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 18:05:38.441624 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1555 18:05:38.441678 0 10 4 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
1556 18:05:38.441731 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 18:05:38.441784 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 18:05:38.441836 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 18:05:38.441889 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 18:05:38.441941 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 18:05:38.441993 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 18:05:38.442068 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 18:05:38.442151 0 11 4 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
1564 18:05:38.442237 0 11 8 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1565 18:05:38.442295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 18:05:38.442348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 18:05:38.442401 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 18:05:38.442454 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 18:05:38.442507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 18:05:38.442573 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1571 18:05:38.442629 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1572 18:05:38.442682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 18:05:38.442735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 18:05:38.442788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 18:05:38.442841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 18:05:38.442893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 18:05:38.442951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 18:05:38.443006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 18:05:38.443059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 18:05:38.443111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 18:05:38.443163 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 18:05:38.443234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 18:05:38.443289 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 18:05:38.443342 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 18:05:38.443406 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 18:05:38.443462 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1587 18:05:38.443528 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1588 18:05:38.443601 Total UI for P1: 0, mck2ui 16
1589 18:05:38.443668 best dqsien dly found for B0: ( 0, 14, 0)
1590 18:05:38.443721 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 18:05:38.443775 Total UI for P1: 0, mck2ui 16
1592 18:05:38.443842 best dqsien dly found for B1: ( 0, 14, 4)
1593 18:05:38.443896 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1594 18:05:38.443949 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1595 18:05:38.444006
1596 18:05:38.444061 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1597 18:05:38.444115 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1598 18:05:38.444178 [Gating] SW calibration Done
1599 18:05:38.444231 ==
1600 18:05:38.444283 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 18:05:38.444336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 18:05:38.444390 ==
1603 18:05:38.444442 RX Vref Scan: 0
1604 18:05:38.444494
1605 18:05:38.444576 RX Vref 0 -> 0, step: 1
1606 18:05:38.444675
1607 18:05:38.444758 RX Delay -130 -> 252, step: 16
1608 18:05:38.444844 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1609 18:05:38.444903 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1610 18:05:38.444957 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1611 18:05:38.445216 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1612 18:05:38.445280 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1613 18:05:38.445335 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1614 18:05:38.445389 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1615 18:05:38.445494 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1616 18:05:38.445595 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1617 18:05:38.445691 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1618 18:05:38.445772 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1619 18:05:38.445825 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1620 18:05:38.445878 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1621 18:05:38.445931 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1622 18:05:38.445983 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1623 18:05:38.446035 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1624 18:05:38.446088 ==
1625 18:05:38.446142 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 18:05:38.446195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 18:05:38.446248 ==
1628 18:05:38.446301 DQS Delay:
1629 18:05:38.446353 DQS0 = 0, DQS1 = 0
1630 18:05:38.446405 DQM Delay:
1631 18:05:38.446456 DQM0 = 87, DQM1 = 80
1632 18:05:38.446509 DQ Delay:
1633 18:05:38.446561 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1634 18:05:38.446613 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1635 18:05:38.446666 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1636 18:05:38.446718 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1637 18:05:38.446770
1638 18:05:38.446823
1639 18:05:38.446873 ==
1640 18:05:38.446926 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 18:05:38.446979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 18:05:38.447031 ==
1643 18:05:38.447084
1644 18:05:38.447179
1645 18:05:38.447232 TX Vref Scan disable
1646 18:05:38.447285 == TX Byte 0 ==
1647 18:05:38.447337 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1648 18:05:38.447390 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1649 18:05:38.447443 == TX Byte 1 ==
1650 18:05:38.447496 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 18:05:38.447548 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 18:05:38.447600 ==
1653 18:05:38.447652 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 18:05:38.447715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 18:05:38.447771 ==
1656 18:05:38.447823 TX Vref=22, minBit 8, minWin=27, winSum=449
1657 18:05:38.447876 TX Vref=24, minBit 15, minWin=27, winSum=452
1658 18:05:38.447929 TX Vref=26, minBit 15, minWin=27, winSum=455
1659 18:05:38.447982 TX Vref=28, minBit 15, minWin=27, winSum=457
1660 18:05:38.448035 TX Vref=30, minBit 15, minWin=27, winSum=457
1661 18:05:38.448088 TX Vref=32, minBit 15, minWin=27, winSum=458
1662 18:05:38.448141 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 32
1663 18:05:38.448194
1664 18:05:38.448246 Final TX Range 1 Vref 32
1665 18:05:38.448304
1666 18:05:38.448357 ==
1667 18:05:38.448410 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 18:05:38.448462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 18:05:38.448515 ==
1670 18:05:38.448590
1671 18:05:38.448674
1672 18:05:38.448728 TX Vref Scan disable
1673 18:05:38.448780 == TX Byte 0 ==
1674 18:05:38.448833 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1675 18:05:38.448887 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1676 18:05:38.448940 == TX Byte 1 ==
1677 18:05:38.448993 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1678 18:05:38.449046 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1679 18:05:38.449099
1680 18:05:38.449151 [DATLAT]
1681 18:05:38.449204 Freq=800, CH1 RK0
1682 18:05:38.449256
1683 18:05:38.449308 DATLAT Default: 0xa
1684 18:05:38.449369 0, 0xFFFF, sum = 0
1685 18:05:38.449454 1, 0xFFFF, sum = 0
1686 18:05:38.449582 2, 0xFFFF, sum = 0
1687 18:05:38.449639 3, 0xFFFF, sum = 0
1688 18:05:38.449693 4, 0xFFFF, sum = 0
1689 18:05:38.449747 5, 0xFFFF, sum = 0
1690 18:05:38.449800 6, 0xFFFF, sum = 0
1691 18:05:38.449854 7, 0xFFFF, sum = 0
1692 18:05:38.449939 8, 0xFFFF, sum = 0
1693 18:05:38.450031 9, 0x0, sum = 1
1694 18:05:38.450114 10, 0x0, sum = 2
1695 18:05:38.450169 11, 0x0, sum = 3
1696 18:05:38.450228 12, 0x0, sum = 4
1697 18:05:38.450282 best_step = 10
1698 18:05:38.450334
1699 18:05:38.450401 ==
1700 18:05:38.450460 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 18:05:38.450535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 18:05:38.450592 ==
1703 18:05:38.450645 RX Vref Scan: 1
1704 18:05:38.450697
1705 18:05:38.450750 Set Vref Range= 32 -> 127
1706 18:05:38.450803
1707 18:05:38.450855 RX Vref 32 -> 127, step: 1
1708 18:05:38.450907
1709 18:05:38.450960 RX Delay -95 -> 252, step: 8
1710 18:05:38.451018
1711 18:05:38.451070 Set Vref, RX VrefLevel [Byte0]: 32
1712 18:05:38.451124 [Byte1]: 32
1713 18:05:38.451176
1714 18:05:38.451228 Set Vref, RX VrefLevel [Byte0]: 33
1715 18:05:38.451281 [Byte1]: 33
1716 18:05:38.451333
1717 18:05:38.451384 Set Vref, RX VrefLevel [Byte0]: 34
1718 18:05:38.451437 [Byte1]: 34
1719 18:05:38.451490
1720 18:05:38.451563 Set Vref, RX VrefLevel [Byte0]: 35
1721 18:05:38.451626 [Byte1]: 35
1722 18:05:38.451679
1723 18:05:38.451732 Set Vref, RX VrefLevel [Byte0]: 36
1724 18:05:38.451785 [Byte1]: 36
1725 18:05:38.451836
1726 18:05:38.451906 Set Vref, RX VrefLevel [Byte0]: 37
1727 18:05:38.451962 [Byte1]: 37
1728 18:05:38.452015
1729 18:05:38.452067 Set Vref, RX VrefLevel [Byte0]: 38
1730 18:05:38.452124 [Byte1]: 38
1731 18:05:38.452178
1732 18:05:38.452230 Set Vref, RX VrefLevel [Byte0]: 39
1733 18:05:38.452282 [Byte1]: 39
1734 18:05:38.452335
1735 18:05:38.452387 Set Vref, RX VrefLevel [Byte0]: 40
1736 18:05:38.452439 [Byte1]: 40
1737 18:05:38.452491
1738 18:05:38.452542 Set Vref, RX VrefLevel [Byte0]: 41
1739 18:05:38.452641 [Byte1]: 41
1740 18:05:38.452695
1741 18:05:38.452747 Set Vref, RX VrefLevel [Byte0]: 42
1742 18:05:38.452799 [Byte1]: 42
1743 18:05:38.452851
1744 18:05:38.452903 Set Vref, RX VrefLevel [Byte0]: 43
1745 18:05:38.452955 [Byte1]: 43
1746 18:05:38.453007
1747 18:05:38.453058 Set Vref, RX VrefLevel [Byte0]: 44
1748 18:05:38.453110 [Byte1]: 44
1749 18:05:38.453168
1750 18:05:38.453220 Set Vref, RX VrefLevel [Byte0]: 45
1751 18:05:38.453273 [Byte1]: 45
1752 18:05:38.453325
1753 18:05:38.453377 Set Vref, RX VrefLevel [Byte0]: 46
1754 18:05:38.453430 [Byte1]: 46
1755 18:05:38.453483
1756 18:05:38.453551 Set Vref, RX VrefLevel [Byte0]: 47
1757 18:05:38.453654 [Byte1]: 47
1758 18:05:38.453717
1759 18:05:38.453771 Set Vref, RX VrefLevel [Byte0]: 48
1760 18:05:38.453854 [Byte1]: 48
1761 18:05:38.453908
1762 18:05:38.453984 Set Vref, RX VrefLevel [Byte0]: 49
1763 18:05:38.454043 [Byte1]: 49
1764 18:05:38.454097
1765 18:05:38.454156 Set Vref, RX VrefLevel [Byte0]: 50
1766 18:05:38.454227 [Byte1]: 50
1767 18:05:38.454282
1768 18:05:38.454529 Set Vref, RX VrefLevel [Byte0]: 51
1769 18:05:38.454595 [Byte1]: 51
1770 18:05:38.454658
1771 18:05:38.454713 Set Vref, RX VrefLevel [Byte0]: 52
1772 18:05:38.454768 [Byte1]: 52
1773 18:05:38.454821
1774 18:05:38.454874 Set Vref, RX VrefLevel [Byte0]: 53
1775 18:05:38.454928 [Byte1]: 53
1776 18:05:38.454981
1777 18:05:38.455033 Set Vref, RX VrefLevel [Byte0]: 54
1778 18:05:38.455086 [Byte1]: 54
1779 18:05:38.455139
1780 18:05:38.455236 Set Vref, RX VrefLevel [Byte0]: 55
1781 18:05:38.455288 [Byte1]: 55
1782 18:05:38.455342
1783 18:05:38.455413 Set Vref, RX VrefLevel [Byte0]: 56
1784 18:05:38.455469 [Byte1]: 56
1785 18:05:38.455522
1786 18:05:38.455576 Set Vref, RX VrefLevel [Byte0]: 57
1787 18:05:38.455629 [Byte1]: 57
1788 18:05:38.455682
1789 18:05:38.455734 Set Vref, RX VrefLevel [Byte0]: 58
1790 18:05:38.455787 [Byte1]: 58
1791 18:05:38.455839
1792 18:05:38.455892 Set Vref, RX VrefLevel [Byte0]: 59
1793 18:05:38.455945 [Byte1]: 59
1794 18:05:38.455998
1795 18:05:38.456050 Set Vref, RX VrefLevel [Byte0]: 60
1796 18:05:38.456104 [Byte1]: 60
1797 18:05:38.456156
1798 18:05:38.456209 Set Vref, RX VrefLevel [Byte0]: 61
1799 18:05:38.456261 [Byte1]: 61
1800 18:05:38.456314
1801 18:05:38.456366 Set Vref, RX VrefLevel [Byte0]: 62
1802 18:05:38.456418 [Byte1]: 62
1803 18:05:38.456471
1804 18:05:38.456523 Set Vref, RX VrefLevel [Byte0]: 63
1805 18:05:38.456619 [Byte1]: 63
1806 18:05:38.456673
1807 18:05:38.456725 Set Vref, RX VrefLevel [Byte0]: 64
1808 18:05:38.456777 [Byte1]: 64
1809 18:05:38.456829
1810 18:05:38.456881 Set Vref, RX VrefLevel [Byte0]: 65
1811 18:05:38.456934 [Byte1]: 65
1812 18:05:38.456987
1813 18:05:38.457039 Set Vref, RX VrefLevel [Byte0]: 66
1814 18:05:38.457092 [Byte1]: 66
1815 18:05:38.457144
1816 18:05:38.457197 Set Vref, RX VrefLevel [Byte0]: 67
1817 18:05:38.457249 [Byte1]: 67
1818 18:05:38.457301
1819 18:05:38.457353 Set Vref, RX VrefLevel [Byte0]: 68
1820 18:05:38.457405 [Byte1]: 68
1821 18:05:38.457457
1822 18:05:38.457509 Set Vref, RX VrefLevel [Byte0]: 69
1823 18:05:38.457562 [Byte1]: 69
1824 18:05:38.457613
1825 18:05:38.457665 Set Vref, RX VrefLevel [Byte0]: 70
1826 18:05:38.457718 [Byte1]: 70
1827 18:05:38.457771
1828 18:05:38.457823 Set Vref, RX VrefLevel [Byte0]: 71
1829 18:05:38.457920 [Byte1]: 71
1830 18:05:38.457973
1831 18:05:38.458026 Set Vref, RX VrefLevel [Byte0]: 72
1832 18:05:38.458078 [Byte1]: 72
1833 18:05:38.458130
1834 18:05:38.458183 Set Vref, RX VrefLevel [Byte0]: 73
1835 18:05:38.458236 [Byte1]: 73
1836 18:05:38.458288
1837 18:05:38.458341 Set Vref, RX VrefLevel [Byte0]: 74
1838 18:05:38.458394 [Byte1]: 74
1839 18:05:38.458446
1840 18:05:38.458498 Set Vref, RX VrefLevel [Byte0]: 75
1841 18:05:38.458551 [Byte1]: 75
1842 18:05:38.458603
1843 18:05:38.458655 Set Vref, RX VrefLevel [Byte0]: 76
1844 18:05:38.458708 [Byte1]: 76
1845 18:05:38.458760
1846 18:05:38.458812 Set Vref, RX VrefLevel [Byte0]: 77
1847 18:05:38.458865 [Byte1]: 77
1848 18:05:38.458917
1849 18:05:38.458969 Set Vref, RX VrefLevel [Byte0]: 78
1850 18:05:38.459021 [Byte1]: 78
1851 18:05:38.459074
1852 18:05:38.459126 Final RX Vref Byte 0 = 52 to rank0
1853 18:05:38.459179 Final RX Vref Byte 1 = 62 to rank0
1854 18:05:38.459232 Final RX Vref Byte 0 = 52 to rank1
1855 18:05:38.459285 Final RX Vref Byte 1 = 62 to rank1==
1856 18:05:38.459338 Dram Type= 6, Freq= 0, CH_1, rank 0
1857 18:05:38.459390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1858 18:05:38.459443 ==
1859 18:05:38.459496 DQS Delay:
1860 18:05:38.459548 DQS0 = 0, DQS1 = 0
1861 18:05:38.459601 DQM Delay:
1862 18:05:38.459653 DQM0 = 92, DQM1 = 81
1863 18:05:38.459705 DQ Delay:
1864 18:05:38.459758 DQ0 =92, DQ1 =88, DQ2 =84, DQ3 =88
1865 18:05:38.459811 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1866 18:05:38.459863 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1867 18:05:38.459915 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1868 18:05:38.459967
1869 18:05:38.460019
1870 18:05:38.460071 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1871 18:05:38.460124 CH1 RK0: MR19=606, MR18=2D4A
1872 18:05:38.460177 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1873 18:05:38.460230
1874 18:05:38.460282 ----->DramcWriteLeveling(PI) begin...
1875 18:05:38.460335 ==
1876 18:05:38.460388 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 18:05:38.460441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 18:05:38.460494 ==
1879 18:05:38.460576 Write leveling (Byte 0): 28 => 28
1880 18:05:38.460645 Write leveling (Byte 1): 29 => 29
1881 18:05:38.460698 DramcWriteLeveling(PI) end<-----
1882 18:05:38.460750
1883 18:05:38.460802 ==
1884 18:05:38.460863 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 18:05:38.460917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 18:05:38.460970 ==
1887 18:05:38.461023 [Gating] SW mode calibration
1888 18:05:38.461075 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1889 18:05:38.461129 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1890 18:05:38.461181 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1891 18:05:38.461234 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1892 18:05:38.461288 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1893 18:05:38.461340 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 18:05:38.461400 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 18:05:38.461453 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:05:38.461506 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 18:05:38.461558 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 18:05:38.461610 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 18:05:38.461663 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 18:05:38.461715 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 18:05:38.461768 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 18:05:38.461820 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 18:05:38.461872 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 18:05:38.461933 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 18:05:38.461986 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 18:05:38.462232 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 18:05:38.462291 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1908 18:05:38.462345 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 18:05:38.462421 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 18:05:38.462477 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 18:05:38.462544 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 18:05:38.462597 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 18:05:38.462649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 18:05:38.462703 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 18:05:38.462755 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 18:05:38.462807 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1917 18:05:38.462859 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 18:05:38.462911 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 18:05:38.462963 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 18:05:38.463016 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 18:05:38.463068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 18:05:38.463120 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 18:05:38.463211 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (1 1) (1 1)
1924 18:05:38.463264 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1925 18:05:38.463318 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 18:05:38.463371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 18:05:38.463423 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 18:05:38.463475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 18:05:38.463528 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 18:05:38.463580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 18:05:38.463632 0 11 4 | B1->B0 | 3535 3232 | 0 0 | (0 0) (0 0)
1932 18:05:38.463684 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 18:05:38.463775 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 18:05:38.463842 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 18:05:38.463895 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 18:05:38.463961 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 18:05:38.464016 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 18:05:38.464069 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 18:05:38.464170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 18:05:38.464224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 18:05:38.464277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 18:05:38.464352 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 18:05:38.464405 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 18:05:38.464458 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 18:05:38.464561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 18:05:38.464655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 18:05:38.464710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 18:05:38.464764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 18:05:38.464824 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 18:05:38.464879 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 18:05:38.464932 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 18:05:38.464984 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 18:05:38.465044 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 18:05:38.465110 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 18:05:38.465163 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1956 18:05:38.465216 Total UI for P1: 0, mck2ui 16
1957 18:05:38.465289 best dqsien dly found for B1: ( 0, 14, 2)
1958 18:05:38.465343 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1959 18:05:38.465396 Total UI for P1: 0, mck2ui 16
1960 18:05:38.465464 best dqsien dly found for B0: ( 0, 14, 4)
1961 18:05:38.465517 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1962 18:05:38.465570 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1963 18:05:38.465621
1964 18:05:38.465673 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1965 18:05:38.465725 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1966 18:05:38.465778 [Gating] SW calibration Done
1967 18:05:38.465830 ==
1968 18:05:38.465882 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 18:05:38.465934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 18:05:38.465987 ==
1971 18:05:38.466038 RX Vref Scan: 0
1972 18:05:38.466090
1973 18:05:38.466142 RX Vref 0 -> 0, step: 1
1974 18:05:38.466194
1975 18:05:38.466246 RX Delay -130 -> 252, step: 16
1976 18:05:38.466299 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1977 18:05:38.466351 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1978 18:05:38.466404 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1979 18:05:38.466456 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1980 18:05:38.466508 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1981 18:05:38.466569 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1982 18:05:38.466622 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1983 18:05:38.466675 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1984 18:05:38.631570 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1985 18:05:38.631700 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1986 18:05:38.631767 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1987 18:05:38.631830 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1988 18:05:38.631890 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1989 18:05:38.631964 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1990 18:05:38.632045 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1991 18:05:38.632104 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1992 18:05:38.632160 ==
1993 18:05:38.632217 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 18:05:38.632274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 18:05:38.632346 ==
1996 18:05:38.632416 DQS Delay:
1997 18:05:38.632472 DQS0 = 0, DQS1 = 0
1998 18:05:38.632527 DQM Delay:
1999 18:05:38.632627 DQM0 = 91, DQM1 = 79
2000 18:05:38.632682 DQ Delay:
2001 18:05:38.632766 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
2002 18:05:38.633072 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
2003 18:05:38.633160 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =77
2004 18:05:38.633250 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2005 18:05:38.633354
2006 18:05:38.633410
2007 18:05:38.633465 ==
2008 18:05:38.633520 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 18:05:38.633574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 18:05:38.633629 ==
2011 18:05:38.633683
2012 18:05:38.633737
2013 18:05:38.633790 TX Vref Scan disable
2014 18:05:38.633844 == TX Byte 0 ==
2015 18:05:38.633899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2016 18:05:38.633953 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2017 18:05:38.634008 == TX Byte 1 ==
2018 18:05:38.634062 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2019 18:05:38.634116 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2020 18:05:38.634170 ==
2021 18:05:38.634225 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 18:05:38.634289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 18:05:38.634353 ==
2024 18:05:38.634408 TX Vref=22, minBit 13, minWin=27, winSum=450
2025 18:05:38.634463 TX Vref=24, minBit 13, minWin=27, winSum=454
2026 18:05:38.634518 TX Vref=26, minBit 3, minWin=28, winSum=458
2027 18:05:38.634573 TX Vref=28, minBit 8, minWin=28, winSum=460
2028 18:05:38.634627 TX Vref=30, minBit 8, minWin=28, winSum=457
2029 18:05:38.634711 TX Vref=32, minBit 8, minWin=28, winSum=458
2030 18:05:38.634765 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
2031 18:05:38.634820
2032 18:05:38.634874 Final TX Range 1 Vref 28
2033 18:05:38.634928
2034 18:05:38.635023 ==
2035 18:05:38.635080 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 18:05:38.635134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 18:05:38.635188 ==
2038 18:05:38.635242
2039 18:05:38.635295
2040 18:05:38.635377 TX Vref Scan disable
2041 18:05:38.635431 == TX Byte 0 ==
2042 18:05:38.635484 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2043 18:05:38.635538 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2044 18:05:38.635592 == TX Byte 1 ==
2045 18:05:38.635661 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2046 18:05:38.635731 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2047 18:05:38.635784
2048 18:05:38.635838 [DATLAT]
2049 18:05:38.635891 Freq=800, CH1 RK1
2050 18:05:38.635945
2051 18:05:38.635997 DATLAT Default: 0xa
2052 18:05:38.636051 0, 0xFFFF, sum = 0
2053 18:05:38.636106 1, 0xFFFF, sum = 0
2054 18:05:38.636161 2, 0xFFFF, sum = 0
2055 18:05:38.636214 3, 0xFFFF, sum = 0
2056 18:05:38.636285 4, 0xFFFF, sum = 0
2057 18:05:38.636354 5, 0xFFFF, sum = 0
2058 18:05:38.636408 6, 0xFFFF, sum = 0
2059 18:05:38.636462 7, 0xFFFF, sum = 0
2060 18:05:38.636517 8, 0xFFFF, sum = 0
2061 18:05:38.636611 9, 0x0, sum = 1
2062 18:05:38.636667 10, 0x0, sum = 2
2063 18:05:38.636722 11, 0x0, sum = 3
2064 18:05:38.636777 12, 0x0, sum = 4
2065 18:05:38.636832 best_step = 10
2066 18:05:38.636885
2067 18:05:38.636939 ==
2068 18:05:38.636992 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 18:05:38.637050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 18:05:38.637105 ==
2071 18:05:38.637158 RX Vref Scan: 0
2072 18:05:38.637212
2073 18:05:38.637265 RX Vref 0 -> 0, step: 1
2074 18:05:38.637318
2075 18:05:38.637371 RX Delay -95 -> 252, step: 8
2076 18:05:38.637446 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2077 18:05:38.637503 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2078 18:05:38.637557 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2079 18:05:38.637612 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2080 18:05:38.637668 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2081 18:05:38.637723 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2082 18:05:38.637779 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2083 18:05:38.637834 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2084 18:05:38.637890 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2085 18:05:38.637960 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2086 18:05:38.638029 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2087 18:05:38.638084 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2088 18:05:38.638140 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2089 18:05:38.638195 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2090 18:05:38.638251 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2091 18:05:38.638306 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2092 18:05:38.638361 ==
2093 18:05:38.638431 Dram Type= 6, Freq= 0, CH_1, rank 1
2094 18:05:38.638502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2095 18:05:38.638558 ==
2096 18:05:38.638613 DQS Delay:
2097 18:05:38.638668 DQS0 = 0, DQS1 = 0
2098 18:05:38.638724 DQM Delay:
2099 18:05:38.638778 DQM0 = 91, DQM1 = 82
2100 18:05:38.638834 DQ Delay:
2101 18:05:38.638889 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2102 18:05:38.638945 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2103 18:05:38.639000 DQ8 =68, DQ9 =76, DQ10 =80, DQ11 =80
2104 18:05:38.639081 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2105 18:05:38.639179
2106 18:05:38.639252
2107 18:05:38.639308 [DQSOSCAuto] RK1, (LSB)MR18= 0x380d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2108 18:05:38.639366 CH1 RK1: MR19=606, MR18=380D
2109 18:05:38.639422 CH1_RK1: MR19=0x606, MR18=0x380D, DQSOSC=395, MR23=63, INC=94, DEC=63
2110 18:05:38.639478 [RxdqsGatingPostProcess] freq 800
2111 18:05:38.639534 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2112 18:05:38.639590 Pre-setting of DQS Precalculation
2113 18:05:38.639646 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2114 18:05:38.639731 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2115 18:05:38.639788 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2116 18:05:38.639843
2117 18:05:38.639898
2118 18:05:38.639953 [Calibration Summary] 1600 Mbps
2119 18:05:38.640008 CH 0, Rank 0
2120 18:05:38.640063 SW Impedance : PASS
2121 18:05:38.640119 DUTY Scan : NO K
2122 18:05:38.640174 ZQ Calibration : PASS
2123 18:05:38.640229 Jitter Meter : NO K
2124 18:05:38.640284 CBT Training : PASS
2125 18:05:38.640339 Write leveling : PASS
2126 18:05:38.640395 RX DQS gating : PASS
2127 18:05:38.640450 RX DQ/DQS(RDDQC) : PASS
2128 18:05:38.640505 TX DQ/DQS : PASS
2129 18:05:38.640598 RX DATLAT : PASS
2130 18:05:38.640655 RX DQ/DQS(Engine): PASS
2131 18:05:38.640730 TX OE : NO K
2132 18:05:38.640788 All Pass.
2133 18:05:38.640843
2134 18:05:38.640899 CH 0, Rank 1
2135 18:05:38.640954 SW Impedance : PASS
2136 18:05:38.641009 DUTY Scan : NO K
2137 18:05:38.641065 ZQ Calibration : PASS
2138 18:05:38.641120 Jitter Meter : NO K
2139 18:05:38.641175 CBT Training : PASS
2140 18:05:38.641231 Write leveling : PASS
2141 18:05:38.641286 RX DQS gating : PASS
2142 18:05:38.641342 RX DQ/DQS(RDDQC) : PASS
2143 18:05:38.641397 TX DQ/DQS : PASS
2144 18:05:38.641453 RX DATLAT : PASS
2145 18:05:38.641509 RX DQ/DQS(Engine): PASS
2146 18:05:38.641564 TX OE : NO K
2147 18:05:38.641619 All Pass.
2148 18:05:38.641674
2149 18:05:38.641729 CH 1, Rank 0
2150 18:05:38.641985 SW Impedance : PASS
2151 18:05:38.642047 DUTY Scan : NO K
2152 18:05:38.642118 ZQ Calibration : PASS
2153 18:05:38.642210 Jitter Meter : NO K
2154 18:05:38.642268 CBT Training : PASS
2155 18:05:38.642324 Write leveling : PASS
2156 18:05:38.642395 RX DQS gating : PASS
2157 18:05:38.642467 RX DQ/DQS(RDDQC) : PASS
2158 18:05:38.642522 TX DQ/DQS : PASS
2159 18:05:38.642579 RX DATLAT : PASS
2160 18:05:38.642634 RX DQ/DQS(Engine): PASS
2161 18:05:38.642689 TX OE : NO K
2162 18:05:38.642745 All Pass.
2163 18:05:38.642800
2164 18:05:38.642855 CH 1, Rank 1
2165 18:05:38.642910 SW Impedance : PASS
2166 18:05:38.642966 DUTY Scan : NO K
2167 18:05:38.643020 ZQ Calibration : PASS
2168 18:05:38.643075 Jitter Meter : NO K
2169 18:05:38.643131 CBT Training : PASS
2170 18:05:38.643186 Write leveling : PASS
2171 18:05:38.643241 RX DQS gating : PASS
2172 18:05:38.643297 RX DQ/DQS(RDDQC) : PASS
2173 18:05:38.643375 TX DQ/DQS : PASS
2174 18:05:38.643446 RX DATLAT : PASS
2175 18:05:38.643502 RX DQ/DQS(Engine): PASS
2176 18:05:38.643556 TX OE : NO K
2177 18:05:38.643611 All Pass.
2178 18:05:38.643681
2179 18:05:38.643751 DramC Write-DBI off
2180 18:05:38.643806 PER_BANK_REFRESH: Hybrid Mode
2181 18:05:38.643862 TX_TRACKING: ON
2182 18:05:38.643917 [GetDramInforAfterCalByMRR] Vendor 6.
2183 18:05:38.643973 [GetDramInforAfterCalByMRR] Revision 606.
2184 18:05:38.644028 [GetDramInforAfterCalByMRR] Revision 2 0.
2185 18:05:38.644084 MR0 0x3b3b
2186 18:05:38.644139 MR8 0x5151
2187 18:05:38.644194 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 18:05:38.644250
2189 18:05:38.644305 MR0 0x3b3b
2190 18:05:38.644361 MR8 0x5151
2191 18:05:38.644425 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2192 18:05:38.644515
2193 18:05:38.644622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2194 18:05:38.644681 [FAST_K] Save calibration result to emmc
2195 18:05:38.644738 [FAST_K] Save calibration result to emmc
2196 18:05:38.644793 dram_init: config_dvfs: 1
2197 18:05:38.644850 dramc_set_vcore_voltage set vcore to 662500
2198 18:05:38.644907 Read voltage for 1200, 2
2199 18:05:38.644962 Vio18 = 0
2200 18:05:38.645017 Vcore = 662500
2201 18:05:38.645072 Vdram = 0
2202 18:05:38.645127 Vddq = 0
2203 18:05:38.645200 Vmddr = 0
2204 18:05:38.645271 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2205 18:05:38.645326 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2206 18:05:38.645382 MEM_TYPE=3, freq_sel=15
2207 18:05:38.645438 sv_algorithm_assistance_LP4_1600
2208 18:05:38.645493 ============ PULL DRAM RESETB DOWN ============
2209 18:05:38.645550 ========== PULL DRAM RESETB DOWN end =========
2210 18:05:38.645623 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2211 18:05:38.645696 ===================================
2212 18:05:38.645752 LPDDR4 DRAM CONFIGURATION
2213 18:05:38.645806 ===================================
2214 18:05:38.645862 EX_ROW_EN[0] = 0x0
2215 18:05:38.645917 EX_ROW_EN[1] = 0x0
2216 18:05:38.645973 LP4Y_EN = 0x0
2217 18:05:38.646028 WORK_FSP = 0x0
2218 18:05:38.646083 WL = 0x4
2219 18:05:38.646139 RL = 0x4
2220 18:05:38.646213 BL = 0x2
2221 18:05:38.646269 RPST = 0x0
2222 18:05:38.646340 RD_PRE = 0x0
2223 18:05:38.646395 WR_PRE = 0x1
2224 18:05:38.646450 WR_PST = 0x0
2225 18:05:38.646508 DBI_WR = 0x0
2226 18:05:38.646581 DBI_RD = 0x0
2227 18:05:38.646637 OTF = 0x1
2228 18:05:38.646693 ===================================
2229 18:05:38.646749 ===================================
2230 18:05:38.646804 ANA top config
2231 18:05:38.646859 ===================================
2232 18:05:38.646914 DLL_ASYNC_EN = 0
2233 18:05:38.646969 ALL_SLAVE_EN = 0
2234 18:05:38.647024 NEW_RANK_MODE = 1
2235 18:05:38.647080 DLL_IDLE_MODE = 1
2236 18:05:38.647136 LP45_APHY_COMB_EN = 1
2237 18:05:38.647191 TX_ODT_DIS = 1
2238 18:05:38.647277 NEW_8X_MODE = 1
2239 18:05:38.647333 ===================================
2240 18:05:38.647388 ===================================
2241 18:05:38.647444 data_rate = 2400
2242 18:05:38.647500 CKR = 1
2243 18:05:38.647555 DQ_P2S_RATIO = 8
2244 18:05:38.647628 ===================================
2245 18:05:38.647720 CA_P2S_RATIO = 8
2246 18:05:38.647778 DQ_CA_OPEN = 0
2247 18:05:38.647834 DQ_SEMI_OPEN = 0
2248 18:05:38.647890 CA_SEMI_OPEN = 0
2249 18:05:38.647945 CA_FULL_RATE = 0
2250 18:05:38.648000 DQ_CKDIV4_EN = 0
2251 18:05:38.648055 CA_CKDIV4_EN = 0
2252 18:05:38.648111 CA_PREDIV_EN = 0
2253 18:05:38.648166 PH8_DLY = 17
2254 18:05:38.648221 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2255 18:05:38.648276 DQ_AAMCK_DIV = 4
2256 18:05:38.648332 CA_AAMCK_DIV = 4
2257 18:05:38.648387 CA_ADMCK_DIV = 4
2258 18:05:38.648443 DQ_TRACK_CA_EN = 0
2259 18:05:38.648498 CA_PICK = 1200
2260 18:05:38.648592 CA_MCKIO = 1200
2261 18:05:38.648667 MCKIO_SEMI = 0
2262 18:05:38.648723 PLL_FREQ = 2366
2263 18:05:38.648779 DQ_UI_PI_RATIO = 32
2264 18:05:38.648835 CA_UI_PI_RATIO = 0
2265 18:05:38.648890 ===================================
2266 18:05:38.648945 ===================================
2267 18:05:38.649001 memory_type:LPDDR4
2268 18:05:38.649056 GP_NUM : 10
2269 18:05:38.649112 SRAM_EN : 1
2270 18:05:38.649166 MD32_EN : 0
2271 18:05:38.649221 ===================================
2272 18:05:38.649276 [ANA_INIT] >>>>>>>>>>>>>>
2273 18:05:38.649331 <<<<<< [CONFIGURE PHASE]: ANA_TX
2274 18:05:38.649386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2275 18:05:38.649441 ===================================
2276 18:05:38.649528 data_rate = 2400,PCW = 0X5b00
2277 18:05:38.649583 ===================================
2278 18:05:38.649639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2279 18:05:38.649694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 18:05:38.649751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2281 18:05:38.649807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2282 18:05:38.649863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2283 18:05:38.649935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2284 18:05:38.649992 [ANA_INIT] flow start
2285 18:05:38.650047 [ANA_INIT] PLL >>>>>>>>
2286 18:05:38.650102 [ANA_INIT] PLL <<<<<<<<
2287 18:05:38.650156 [ANA_INIT] MIDPI >>>>>>>>
2288 18:05:38.650211 [ANA_INIT] MIDPI <<<<<<<<
2289 18:05:38.650461 [ANA_INIT] DLL >>>>>>>>
2290 18:05:38.650568 [ANA_INIT] DLL <<<<<<<<
2291 18:05:38.650674 [ANA_INIT] flow end
2292 18:05:38.650779 ============ LP4 DIFF to SE enter ============
2293 18:05:38.650886 ============ LP4 DIFF to SE exit ============
2294 18:05:38.650979 [ANA_INIT] <<<<<<<<<<<<<
2295 18:05:38.651065 [Flow] Enable top DCM control >>>>>
2296 18:05:38.651150 [Flow] Enable top DCM control <<<<<
2297 18:05:38.651235 Enable DLL master slave shuffle
2298 18:05:38.651321 ==============================================================
2299 18:05:38.651406 Gating Mode config
2300 18:05:38.651522 ==============================================================
2301 18:05:38.651607 Config description:
2302 18:05:38.651693 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2303 18:05:38.651780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2304 18:05:38.651869 SELPH_MODE 0: By rank 1: By Phase
2305 18:05:38.651958 ==============================================================
2306 18:05:38.652016 GAT_TRACK_EN = 1
2307 18:05:38.652073 RX_GATING_MODE = 2
2308 18:05:38.652129 RX_GATING_TRACK_MODE = 2
2309 18:05:38.652185 SELPH_MODE = 1
2310 18:05:38.652240 PICG_EARLY_EN = 1
2311 18:05:38.652296 VALID_LAT_VALUE = 1
2312 18:05:38.652351 ==============================================================
2313 18:05:38.652407 Enter into Gating configuration >>>>
2314 18:05:38.652463 Exit from Gating configuration <<<<
2315 18:05:38.652518 Enter into DVFS_PRE_config >>>>>
2316 18:05:38.652600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2317 18:05:38.652672 Exit from DVFS_PRE_config <<<<<
2318 18:05:38.652728 Enter into PICG configuration >>>>
2319 18:05:38.652784 Exit from PICG configuration <<<<
2320 18:05:38.652839 [RX_INPUT] configuration >>>>>
2321 18:05:38.652895 [RX_INPUT] configuration <<<<<
2322 18:05:38.652950 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2323 18:05:38.653006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2324 18:05:38.653062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 18:05:38.653118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 18:05:38.653175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 18:05:38.653230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 18:05:38.653286 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2329 18:05:38.653341 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2330 18:05:38.653396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2331 18:05:38.653467 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2332 18:05:38.653538 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2333 18:05:38.653593 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2334 18:05:38.653649 ===================================
2335 18:05:38.653705 LPDDR4 DRAM CONFIGURATION
2336 18:05:38.653760 ===================================
2337 18:05:38.653816 EX_ROW_EN[0] = 0x0
2338 18:05:38.653871 EX_ROW_EN[1] = 0x0
2339 18:05:38.653939 LP4Y_EN = 0x0
2340 18:05:38.654000 WORK_FSP = 0x0
2341 18:05:38.654057 WL = 0x4
2342 18:05:38.654112 RL = 0x4
2343 18:05:38.654168 BL = 0x2
2344 18:05:38.654223 RPST = 0x0
2345 18:05:38.654278 RD_PRE = 0x0
2346 18:05:38.654332 WR_PRE = 0x1
2347 18:05:38.654387 WR_PST = 0x0
2348 18:05:38.654442 DBI_WR = 0x0
2349 18:05:38.654497 DBI_RD = 0x0
2350 18:05:38.654551 OTF = 0x1
2351 18:05:38.654607 ===================================
2352 18:05:38.654663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2353 18:05:38.654719 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2354 18:05:38.654775 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2355 18:05:38.654831 ===================================
2356 18:05:38.654887 LPDDR4 DRAM CONFIGURATION
2357 18:05:38.654942 ===================================
2358 18:05:38.654997 EX_ROW_EN[0] = 0x10
2359 18:05:38.655052 EX_ROW_EN[1] = 0x0
2360 18:05:38.655107 LP4Y_EN = 0x0
2361 18:05:38.655161 WORK_FSP = 0x0
2362 18:05:38.655215 WL = 0x4
2363 18:05:38.655268 RL = 0x4
2364 18:05:38.655336 BL = 0x2
2365 18:05:38.655404 RPST = 0x0
2366 18:05:38.655458 RD_PRE = 0x0
2367 18:05:38.655510 WR_PRE = 0x1
2368 18:05:38.655564 WR_PST = 0x0
2369 18:05:38.655617 DBI_WR = 0x0
2370 18:05:38.655671 DBI_RD = 0x0
2371 18:05:38.655723 OTF = 0x1
2372 18:05:38.655777 ===================================
2373 18:05:38.655830 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2374 18:05:38.655902 ==
2375 18:05:38.655987 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 18:05:38.656046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 18:05:38.656101 ==
2378 18:05:38.656155 [Duty_Offset_Calibration]
2379 18:05:38.656210 B0:2 B1:0 CA:1
2380 18:05:38.656263
2381 18:05:38.656317 [DutyScan_Calibration_Flow] k_type=0
2382 18:05:38.656371
2383 18:05:38.656424 ==CLK 0==
2384 18:05:38.656477 Final CLK duty delay cell = -4
2385 18:05:38.656532 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2386 18:05:38.656627 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2387 18:05:38.656682 [-4] AVG Duty = 4953%(X100)
2388 18:05:38.656736
2389 18:05:38.656789 CH0 CLK Duty spec in!! Max-Min= 156%
2390 18:05:38.656843 [DutyScan_Calibration_Flow] ====Done====
2391 18:05:38.656897
2392 18:05:38.656950 [DutyScan_Calibration_Flow] k_type=1
2393 18:05:38.657003
2394 18:05:38.657056 ==DQS 0 ==
2395 18:05:38.657110 Final DQS duty delay cell = 0
2396 18:05:38.657164 [0] MAX Duty = 5156%(X100), DQS PI = 28
2397 18:05:38.657218 [0] MIN Duty = 4938%(X100), DQS PI = 0
2398 18:05:38.657300 [0] AVG Duty = 5047%(X100)
2399 18:05:38.657370
2400 18:05:38.657423 ==DQS 1 ==
2401 18:05:38.657477 Final DQS duty delay cell = -4
2402 18:05:38.657531 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2403 18:05:38.657585 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2404 18:05:38.657641 [-4] AVG Duty = 5031%(X100)
2405 18:05:38.657694
2406 18:05:38.657754 CH0 DQS 0 Duty spec in!! Max-Min= 218%
2407 18:05:38.657808
2408 18:05:38.657914 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2409 18:05:38.658179 [DutyScan_Calibration_Flow] ====Done====
2410 18:05:38.658241
2411 18:05:38.658296 [DutyScan_Calibration_Flow] k_type=3
2412 18:05:38.658351
2413 18:05:38.658405 ==DQM 0 ==
2414 18:05:38.658459 Final DQM duty delay cell = 0
2415 18:05:38.658514 [0] MAX Duty = 5062%(X100), DQS PI = 24
2416 18:05:38.658568 [0] MIN Duty = 4813%(X100), DQS PI = 0
2417 18:05:38.658623 [0] AVG Duty = 4937%(X100)
2418 18:05:38.658677
2419 18:05:38.658730 ==DQM 1 ==
2420 18:05:38.658784 Final DQM duty delay cell = 0
2421 18:05:38.658838 [0] MAX Duty = 5187%(X100), DQS PI = 48
2422 18:05:38.658892 [0] MIN Duty = 4969%(X100), DQS PI = 24
2423 18:05:38.658946 [0] AVG Duty = 5078%(X100)
2424 18:05:38.659000
2425 18:05:38.659054 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2426 18:05:38.659108
2427 18:05:38.659161 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2428 18:05:38.659215 [DutyScan_Calibration_Flow] ====Done====
2429 18:05:38.659269
2430 18:05:38.659322 [DutyScan_Calibration_Flow] k_type=2
2431 18:05:38.659376
2432 18:05:38.659429 ==DQ 0 ==
2433 18:05:38.659482 Final DQ duty delay cell = -4
2434 18:05:38.659536 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2435 18:05:38.659590 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2436 18:05:38.659643 [-4] AVG Duty = 4953%(X100)
2437 18:05:38.659697
2438 18:05:38.659750 ==DQ 1 ==
2439 18:05:38.659803 Final DQ duty delay cell = 4
2440 18:05:38.659858 [4] MAX Duty = 5093%(X100), DQS PI = 4
2441 18:05:38.659911 [4] MIN Duty = 5031%(X100), DQS PI = 0
2442 18:05:38.659965 [4] AVG Duty = 5062%(X100)
2443 18:05:38.660019
2444 18:05:38.660073 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2445 18:05:38.660127
2446 18:05:38.660180 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2447 18:05:38.660235 [DutyScan_Calibration_Flow] ====Done====
2448 18:05:38.660288 ==
2449 18:05:38.660342 Dram Type= 6, Freq= 0, CH_1, rank 0
2450 18:05:38.660396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 18:05:38.660450 ==
2452 18:05:38.660504 [Duty_Offset_Calibration]
2453 18:05:38.660581 B0:0 B1:-1 CA:2
2454 18:05:38.660651
2455 18:05:38.660705 [DutyScan_Calibration_Flow] k_type=0
2456 18:05:38.660758
2457 18:05:38.660811 ==CLK 0==
2458 18:05:38.660864 Final CLK duty delay cell = 0
2459 18:05:38.660918 [0] MAX Duty = 5156%(X100), DQS PI = 18
2460 18:05:38.660973 [0] MIN Duty = 4938%(X100), DQS PI = 44
2461 18:05:38.661050 [0] AVG Duty = 5047%(X100)
2462 18:05:38.661106
2463 18:05:38.661160 CH1 CLK Duty spec in!! Max-Min= 218%
2464 18:05:38.661214 [DutyScan_Calibration_Flow] ====Done====
2465 18:05:38.661267
2466 18:05:38.661319 [DutyScan_Calibration_Flow] k_type=1
2467 18:05:38.661373
2468 18:05:38.661426 ==DQS 0 ==
2469 18:05:38.661480 Final DQS duty delay cell = 0
2470 18:05:38.661534 [0] MAX Duty = 5093%(X100), DQS PI = 22
2471 18:05:38.661588 [0] MIN Duty = 4969%(X100), DQS PI = 0
2472 18:05:38.661641 [0] AVG Duty = 5031%(X100)
2473 18:05:38.661694
2474 18:05:38.661748 ==DQS 1 ==
2475 18:05:38.661801 Final DQS duty delay cell = 0
2476 18:05:38.661892 [0] MAX Duty = 5156%(X100), DQS PI = 0
2477 18:05:38.661946 [0] MIN Duty = 4844%(X100), DQS PI = 36
2478 18:05:38.661999 [0] AVG Duty = 5000%(X100)
2479 18:05:38.662053
2480 18:05:38.662105 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2481 18:05:38.662159
2482 18:05:38.662213 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2483 18:05:38.662266 [DutyScan_Calibration_Flow] ====Done====
2484 18:05:38.662320
2485 18:05:38.662374 [DutyScan_Calibration_Flow] k_type=3
2486 18:05:38.662427
2487 18:05:38.662480 ==DQM 0 ==
2488 18:05:38.662533 Final DQM duty delay cell = 4
2489 18:05:38.662587 [4] MAX Duty = 5093%(X100), DQS PI = 20
2490 18:05:38.662642 [4] MIN Duty = 4938%(X100), DQS PI = 44
2491 18:05:38.662695 [4] AVG Duty = 5015%(X100)
2492 18:05:38.662749
2493 18:05:38.662802 ==DQM 1 ==
2494 18:05:38.662856 Final DQM duty delay cell = -4
2495 18:05:38.662910 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2496 18:05:38.662963 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2497 18:05:38.663017 [-4] AVG Duty = 4860%(X100)
2498 18:05:38.663070
2499 18:05:38.663124 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2500 18:05:38.663178
2501 18:05:38.663231 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2502 18:05:38.663285 [DutyScan_Calibration_Flow] ====Done====
2503 18:05:38.663339
2504 18:05:38.663392 [DutyScan_Calibration_Flow] k_type=2
2505 18:05:38.663446
2506 18:05:38.663499 ==DQ 0 ==
2507 18:05:38.663552 Final DQ duty delay cell = 0
2508 18:05:38.663606 [0] MAX Duty = 5031%(X100), DQS PI = 16
2509 18:05:38.663659 [0] MIN Duty = 4938%(X100), DQS PI = 30
2510 18:05:38.663712 [0] AVG Duty = 4984%(X100)
2511 18:05:38.663765
2512 18:05:38.663819 ==DQ 1 ==
2513 18:05:38.663872 Final DQ duty delay cell = 0
2514 18:05:38.663926 [0] MAX Duty = 5031%(X100), DQS PI = 2
2515 18:05:38.663980 [0] MIN Duty = 4782%(X100), DQS PI = 36
2516 18:05:38.664033 [0] AVG Duty = 4906%(X100)
2517 18:05:38.664088
2518 18:05:38.664140 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2519 18:05:38.664204
2520 18:05:38.664264 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2521 18:05:38.664319 [DutyScan_Calibration_Flow] ====Done====
2522 18:05:38.664372 nWR fixed to 30
2523 18:05:38.664427 [ModeRegInit_LP4] CH0 RK0
2524 18:05:38.664481 [ModeRegInit_LP4] CH0 RK1
2525 18:05:38.664534 [ModeRegInit_LP4] CH1 RK0
2526 18:05:38.664623 [ModeRegInit_LP4] CH1 RK1
2527 18:05:38.664692 match AC timing 7
2528 18:05:38.664745 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2529 18:05:38.664800 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2530 18:05:38.664853 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2531 18:05:38.664907 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2532 18:05:38.664962 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2533 18:05:38.665016 ==
2534 18:05:38.665100 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 18:05:38.665154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 18:05:38.665209 ==
2537 18:05:38.665263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 18:05:38.665317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 18:05:38.665372 [CA 0] Center 38 (8~69) winsize 62
2540 18:05:38.665426 [CA 1] Center 38 (8~69) winsize 62
2541 18:05:38.665479 [CA 2] Center 35 (5~66) winsize 62
2542 18:05:38.665533 [CA 3] Center 35 (4~66) winsize 63
2543 18:05:38.665586 [CA 4] Center 34 (4~65) winsize 62
2544 18:05:38.665639 [CA 5] Center 33 (3~64) winsize 62
2545 18:05:38.665693
2546 18:05:38.665746 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 18:05:38.665799
2548 18:05:38.665852 [CATrainingPosCal] consider 1 rank data
2549 18:05:38.665906 u2DelayCellTimex100 = 270/100 ps
2550 18:05:38.665960 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2551 18:05:38.666013 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2552 18:05:38.666067 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 18:05:38.666121 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2554 18:05:38.666175 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2555 18:05:38.666229 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2556 18:05:38.666283
2557 18:05:38.666336 CA PerBit enable=1, Macro0, CA PI delay=33
2558 18:05:38.666390
2559 18:05:38.666641 [CBTSetCACLKResult] CA Dly = 33
2560 18:05:38.666719 CS Dly: 6 (0~37)
2561 18:05:38.666800 ==
2562 18:05:38.666905 Dram Type= 6, Freq= 0, CH_0, rank 1
2563 18:05:38.667009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 18:05:38.667112 ==
2565 18:05:38.667200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2566 18:05:38.667285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2567 18:05:38.667369 [CA 0] Center 39 (8~70) winsize 63
2568 18:05:38.667442 [CA 1] Center 38 (8~69) winsize 62
2569 18:05:38.667499 [CA 2] Center 35 (5~66) winsize 62
2570 18:05:38.667553 [CA 3] Center 35 (5~66) winsize 62
2571 18:05:38.667607 [CA 4] Center 34 (4~65) winsize 62
2572 18:05:38.667661 [CA 5] Center 34 (4~64) winsize 61
2573 18:05:38.667714
2574 18:05:38.667767 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2575 18:05:38.667821
2576 18:05:38.667874 [CATrainingPosCal] consider 2 rank data
2577 18:05:38.667927 u2DelayCellTimex100 = 270/100 ps
2578 18:05:38.667981 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2579 18:05:38.668035 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2580 18:05:38.668089 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2581 18:05:38.668142 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2582 18:05:38.668202 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2583 18:05:38.668263 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2584 18:05:38.668317
2585 18:05:38.668370 CA PerBit enable=1, Macro0, CA PI delay=34
2586 18:05:38.668424
2587 18:05:38.668477 [CBTSetCACLKResult] CA Dly = 34
2588 18:05:38.668530 CS Dly: 7 (0~39)
2589 18:05:38.668683
2590 18:05:38.668767 ----->DramcWriteLeveling(PI) begin...
2591 18:05:38.668851 ==
2592 18:05:38.668935 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 18:05:38.669019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 18:05:38.669102 ==
2595 18:05:38.669185 Write leveling (Byte 0): 34 => 34
2596 18:05:38.669269 Write leveling (Byte 1): 32 => 32
2597 18:05:38.669352 DramcWriteLeveling(PI) end<-----
2598 18:05:38.669434
2599 18:05:38.669516 ==
2600 18:05:38.669599 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 18:05:38.669683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 18:05:38.669766 ==
2603 18:05:38.669849 [Gating] SW mode calibration
2604 18:05:38.669933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2605 18:05:38.670018 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2606 18:05:38.670101 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2607 18:05:38.670185 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2608 18:05:38.670269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 18:05:38.670354 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 18:05:38.670437 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 18:05:38.670520 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 18:05:38.670604 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2613 18:05:38.670687 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2614 18:05:38.670771 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
2615 18:05:38.670854 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2616 18:05:38.670938 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 18:05:38.671021 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 18:05:38.671105 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 18:05:38.671189 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 18:05:38.671247 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2621 18:05:38.671302 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2622 18:05:38.671356 1 1 0 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
2623 18:05:38.671410 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 18:05:38.671463 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 18:05:38.671517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 18:05:38.671570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 18:05:38.671623 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 18:05:38.671676 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 18:05:38.671730 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2630 18:05:38.671784 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2631 18:05:38.671837 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2632 18:05:38.671890 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 18:05:38.671944 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 18:05:38.671998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 18:05:38.672051 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 18:05:38.672104 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 18:05:38.672158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 18:05:38.672211 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 18:05:38.672265 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 18:05:38.672318 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 18:05:38.672372 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 18:05:38.672427 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 18:05:38.672481 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 18:05:38.672535 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 18:05:38.672629 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2646 18:05:38.672684 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2647 18:05:38.672738 Total UI for P1: 0, mck2ui 16
2648 18:05:38.672792 best dqsien dly found for B0: ( 1, 3, 28)
2649 18:05:38.672847 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 18:05:38.672901 Total UI for P1: 0, mck2ui 16
2651 18:05:38.672954 best dqsien dly found for B1: ( 1, 4, 0)
2652 18:05:38.673008 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2653 18:05:38.673062 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2654 18:05:38.673115
2655 18:05:38.673169 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2656 18:05:38.673222 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2657 18:05:38.673276 [Gating] SW calibration Done
2658 18:05:38.673329 ==
2659 18:05:38.673383 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 18:05:38.673437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 18:05:38.673490 ==
2662 18:05:38.673544 RX Vref Scan: 0
2663 18:05:38.673597
2664 18:05:38.673845 RX Vref 0 -> 0, step: 1
2665 18:05:38.673945
2666 18:05:38.674049 RX Delay -40 -> 252, step: 8
2667 18:05:38.674153 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2668 18:05:38.674257 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2669 18:05:38.674352 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2670 18:05:38.674436 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2671 18:05:38.674523 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2672 18:05:38.674608 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2673 18:05:38.674692 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2674 18:05:38.674776 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2675 18:05:38.674859 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2676 18:05:38.674943 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2677 18:05:38.675027 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2678 18:05:38.675110 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2679 18:05:38.675193 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2680 18:05:38.675278 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2681 18:05:38.675361 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2682 18:05:38.675445 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2683 18:05:38.675527 ==
2684 18:05:38.675610 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 18:05:38.675694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 18:05:38.675776 ==
2687 18:05:38.675859 DQS Delay:
2688 18:05:38.675942 DQS0 = 0, DQS1 = 0
2689 18:05:38.676024 DQM Delay:
2690 18:05:38.676107 DQM0 = 123, DQM1 = 110
2691 18:05:38.676189 DQ Delay:
2692 18:05:38.676272 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2693 18:05:38.676356 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2694 18:05:38.676457 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2695 18:05:38.676543 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2696 18:05:38.676649
2697 18:05:38.676731
2698 18:05:38.676813 ==
2699 18:05:38.676896 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 18:05:38.676979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 18:05:38.677062 ==
2702 18:05:38.677145
2703 18:05:38.677226
2704 18:05:38.677309 TX Vref Scan disable
2705 18:05:38.677391 == TX Byte 0 ==
2706 18:05:38.677475 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2707 18:05:38.677559 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2708 18:05:38.677642 == TX Byte 1 ==
2709 18:05:38.677727 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2710 18:05:38.677811 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2711 18:05:38.677893 ==
2712 18:05:38.677977 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 18:05:38.678060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 18:05:38.678143 ==
2715 18:05:38.678227 TX Vref=22, minBit 0, minWin=24, winSum=408
2716 18:05:38.678310 TX Vref=24, minBit 1, minWin=24, winSum=410
2717 18:05:38.678394 TX Vref=26, minBit 0, minWin=24, winSum=413
2718 18:05:38.678484 TX Vref=28, minBit 5, minWin=24, winSum=414
2719 18:05:38.678542 TX Vref=30, minBit 4, minWin=25, winSum=418
2720 18:05:38.678597 TX Vref=32, minBit 1, minWin=25, winSum=416
2721 18:05:38.678658 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 30
2722 18:05:38.678713
2723 18:05:38.678767 Final TX Range 1 Vref 30
2724 18:05:38.678822
2725 18:05:38.678876 ==
2726 18:05:38.678929 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 18:05:38.678984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 18:05:38.679038 ==
2729 18:05:38.679092
2730 18:05:38.679145
2731 18:05:38.679198 TX Vref Scan disable
2732 18:05:38.679251 == TX Byte 0 ==
2733 18:05:38.679305 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2734 18:05:38.679359 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2735 18:05:38.679413 == TX Byte 1 ==
2736 18:05:38.679466 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2737 18:05:38.679520 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2738 18:05:38.679573
2739 18:05:38.679626 [DATLAT]
2740 18:05:38.679679 Freq=1200, CH0 RK0
2741 18:05:38.679733
2742 18:05:38.679786 DATLAT Default: 0xd
2743 18:05:38.679840 0, 0xFFFF, sum = 0
2744 18:05:38.679894 1, 0xFFFF, sum = 0
2745 18:05:38.679949 2, 0xFFFF, sum = 0
2746 18:05:38.680003 3, 0xFFFF, sum = 0
2747 18:05:38.680057 4, 0xFFFF, sum = 0
2748 18:05:38.680110 5, 0xFFFF, sum = 0
2749 18:05:38.680165 6, 0xFFFF, sum = 0
2750 18:05:38.680219 7, 0xFFFF, sum = 0
2751 18:05:38.680273 8, 0xFFFF, sum = 0
2752 18:05:38.680328 9, 0xFFFF, sum = 0
2753 18:05:38.680383 10, 0xFFFF, sum = 0
2754 18:05:38.680438 11, 0xFFFF, sum = 0
2755 18:05:38.680492 12, 0x0, sum = 1
2756 18:05:38.680550 13, 0x0, sum = 2
2757 18:05:38.680635 14, 0x0, sum = 3
2758 18:05:38.680690 15, 0x0, sum = 4
2759 18:05:38.680744 best_step = 13
2760 18:05:38.680798
2761 18:05:38.680856 ==
2762 18:05:38.680911 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 18:05:38.680964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 18:05:38.681018 ==
2765 18:05:38.681073 RX Vref Scan: 1
2766 18:05:38.681127
2767 18:05:38.681180 Set Vref Range= 32 -> 127
2768 18:05:38.681233
2769 18:05:38.681286 RX Vref 32 -> 127, step: 1
2770 18:05:38.681340
2771 18:05:38.681393 RX Delay -13 -> 252, step: 4
2772 18:05:38.681446
2773 18:05:38.681499 Set Vref, RX VrefLevel [Byte0]: 32
2774 18:05:38.681553 [Byte1]: 32
2775 18:05:38.681607
2776 18:05:38.681659 Set Vref, RX VrefLevel [Byte0]: 33
2777 18:05:38.681713 [Byte1]: 33
2778 18:05:38.681766
2779 18:05:38.681819 Set Vref, RX VrefLevel [Byte0]: 34
2780 18:05:38.681872 [Byte1]: 34
2781 18:05:38.681926
2782 18:05:38.681979 Set Vref, RX VrefLevel [Byte0]: 35
2783 18:05:38.682033 [Byte1]: 35
2784 18:05:38.682086
2785 18:05:38.682139 Set Vref, RX VrefLevel [Byte0]: 36
2786 18:05:38.682192 [Byte1]: 36
2787 18:05:38.682245
2788 18:05:38.682298 Set Vref, RX VrefLevel [Byte0]: 37
2789 18:05:38.682352 [Byte1]: 37
2790 18:05:38.682406
2791 18:05:38.682459 Set Vref, RX VrefLevel [Byte0]: 38
2792 18:05:38.682512 [Byte1]: 38
2793 18:05:38.682566
2794 18:05:38.682619 Set Vref, RX VrefLevel [Byte0]: 39
2795 18:05:38.682673 [Byte1]: 39
2796 18:05:38.682726
2797 18:05:38.682778 Set Vref, RX VrefLevel [Byte0]: 40
2798 18:05:38.682832 [Byte1]: 40
2799 18:05:38.682885
2800 18:05:38.682938 Set Vref, RX VrefLevel [Byte0]: 41
2801 18:05:38.682991 [Byte1]: 41
2802 18:05:38.683045
2803 18:05:38.683098 Set Vref, RX VrefLevel [Byte0]: 42
2804 18:05:38.683151 [Byte1]: 42
2805 18:05:38.683205
2806 18:05:38.683258 Set Vref, RX VrefLevel [Byte0]: 43
2807 18:05:38.683311 [Byte1]: 43
2808 18:05:38.683366
2809 18:05:38.683419 Set Vref, RX VrefLevel [Byte0]: 44
2810 18:05:38.683472 [Byte1]: 44
2811 18:05:38.683525
2812 18:05:38.683577 Set Vref, RX VrefLevel [Byte0]: 45
2813 18:05:38.683631 [Byte1]: 45
2814 18:05:38.683685
2815 18:05:38.683738 Set Vref, RX VrefLevel [Byte0]: 46
2816 18:05:38.683791 [Byte1]: 46
2817 18:05:38.683844
2818 18:05:38.683897 Set Vref, RX VrefLevel [Byte0]: 47
2819 18:05:38.683950 [Byte1]: 47
2820 18:05:38.684004
2821 18:05:38.684255 Set Vref, RX VrefLevel [Byte0]: 48
2822 18:05:38.684347 [Byte1]: 48
2823 18:05:38.684451
2824 18:05:38.684586 Set Vref, RX VrefLevel [Byte0]: 49
2825 18:05:38.684741 [Byte1]: 49
2826 18:05:38.684845
2827 18:05:38.684929 Set Vref, RX VrefLevel [Byte0]: 50
2828 18:05:38.685013 [Byte1]: 50
2829 18:05:38.685096
2830 18:05:38.685180 Set Vref, RX VrefLevel [Byte0]: 51
2831 18:05:38.685263 [Byte1]: 51
2832 18:05:38.685346
2833 18:05:38.685428 Set Vref, RX VrefLevel [Byte0]: 52
2834 18:05:38.685512 [Byte1]: 52
2835 18:05:38.685594
2836 18:05:38.685677 Set Vref, RX VrefLevel [Byte0]: 53
2837 18:05:38.685760 [Byte1]: 53
2838 18:05:38.685843
2839 18:05:38.685925 Set Vref, RX VrefLevel [Byte0]: 54
2840 18:05:38.686009 [Byte1]: 54
2841 18:05:38.686091
2842 18:05:38.686173 Set Vref, RX VrefLevel [Byte0]: 55
2843 18:05:38.686256 [Byte1]: 55
2844 18:05:38.686338
2845 18:05:38.686421 Set Vref, RX VrefLevel [Byte0]: 56
2846 18:05:38.686504 [Byte1]: 56
2847 18:05:38.686586
2848 18:05:38.686669 Set Vref, RX VrefLevel [Byte0]: 57
2849 18:05:38.686752 [Byte1]: 57
2850 18:05:38.686835
2851 18:05:38.686917 Set Vref, RX VrefLevel [Byte0]: 58
2852 18:05:38.687000 [Byte1]: 58
2853 18:05:38.687082
2854 18:05:38.687165 Set Vref, RX VrefLevel [Byte0]: 59
2855 18:05:38.687248 [Byte1]: 59
2856 18:05:38.687330
2857 18:05:38.687413 Set Vref, RX VrefLevel [Byte0]: 60
2858 18:05:38.687496 [Byte1]: 60
2859 18:05:38.687578
2860 18:05:38.687660 Set Vref, RX VrefLevel [Byte0]: 61
2861 18:05:38.687743 [Byte1]: 61
2862 18:05:38.687827
2863 18:05:38.687910 Set Vref, RX VrefLevel [Byte0]: 62
2864 18:05:38.687994 [Byte1]: 62
2865 18:05:38.688076
2866 18:05:38.688159 Set Vref, RX VrefLevel [Byte0]: 63
2867 18:05:38.688242 [Byte1]: 63
2868 18:05:38.688324
2869 18:05:38.688407 Set Vref, RX VrefLevel [Byte0]: 64
2870 18:05:38.688489 [Byte1]: 64
2871 18:05:38.688616
2872 18:05:38.688700 Set Vref, RX VrefLevel [Byte0]: 65
2873 18:05:38.688783 [Byte1]: 65
2874 18:05:38.688865
2875 18:05:38.688948 Set Vref, RX VrefLevel [Byte0]: 66
2876 18:05:38.689031 [Byte1]: 66
2877 18:05:38.689113
2878 18:05:38.689195 Set Vref, RX VrefLevel [Byte0]: 67
2879 18:05:38.689278 [Byte1]: 67
2880 18:05:38.689360
2881 18:05:38.689443 Set Vref, RX VrefLevel [Byte0]: 68
2882 18:05:38.689525 [Byte1]: 68
2883 18:05:38.689607
2884 18:05:38.689690 Set Vref, RX VrefLevel [Byte0]: 69
2885 18:05:38.689773 [Byte1]: 69
2886 18:05:38.689855
2887 18:05:38.689938 Set Vref, RX VrefLevel [Byte0]: 70
2888 18:05:38.690020 [Byte1]: 70
2889 18:05:38.690103
2890 18:05:38.690185 Set Vref, RX VrefLevel [Byte0]: 71
2891 18:05:38.690267 [Byte1]: 71
2892 18:05:38.690351
2893 18:05:38.690433 Set Vref, RX VrefLevel [Byte0]: 72
2894 18:05:38.690516 [Byte1]: 72
2895 18:05:38.690599
2896 18:05:38.690667 Final RX Vref Byte 0 = 57 to rank0
2897 18:05:38.690722 Final RX Vref Byte 1 = 50 to rank0
2898 18:05:38.690777 Final RX Vref Byte 0 = 57 to rank1
2899 18:05:38.690831 Final RX Vref Byte 1 = 50 to rank1==
2900 18:05:38.690885 Dram Type= 6, Freq= 0, CH_0, rank 0
2901 18:05:38.690939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 18:05:38.690994 ==
2903 18:05:38.691052 DQS Delay:
2904 18:05:38.691106 DQS0 = 0, DQS1 = 0
2905 18:05:38.691161 DQM Delay:
2906 18:05:38.691214 DQM0 = 122, DQM1 = 109
2907 18:05:38.691268 DQ Delay:
2908 18:05:38.691321 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2909 18:05:38.691375 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2910 18:05:38.691429 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2911 18:05:38.691483 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2912 18:05:38.691537
2913 18:05:38.691590
2914 18:05:38.691644 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2915 18:05:38.691699 CH0 RK0: MR19=404, MR18=C09
2916 18:05:38.691752 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2917 18:05:38.691806
2918 18:05:38.691859 ----->DramcWriteLeveling(PI) begin...
2919 18:05:38.691920 ==
2920 18:05:38.691992 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 18:05:38.692076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 18:05:38.692160 ==
2923 18:05:38.692243 Write leveling (Byte 0): 34 => 34
2924 18:05:38.692326 Write leveling (Byte 1): 29 => 29
2925 18:05:38.692409 DramcWriteLeveling(PI) end<-----
2926 18:05:38.692491
2927 18:05:38.692636 ==
2928 18:05:38.692700 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 18:05:38.692756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 18:05:38.692811 ==
2931 18:05:38.692864 [Gating] SW mode calibration
2932 18:05:38.692918 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2933 18:05:38.692974 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2934 18:05:38.693028 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2935 18:05:38.693083 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 18:05:38.693137 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 18:05:38.693191 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 18:05:38.693245 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2939 18:05:38.693298 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2940 18:05:38.693351 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2941 18:05:38.693404 0 15 28 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 0)
2942 18:05:38.693459 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 18:05:38.693512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 18:05:38.693566 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 18:05:38.693620 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 18:05:38.693673 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2947 18:05:38.693727 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 18:05:38.693780 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2949 18:05:38.693834 1 0 28 | B1->B0 | 3333 3e3e | 0 0 | (0 0) (0 0)
2950 18:05:38.693887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 18:05:38.693940 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 18:05:38.693994 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 18:05:38.694249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 18:05:38.694343 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 18:05:38.694449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2956 18:05:38.694551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 18:05:38.694694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2958 18:05:38.694788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 18:05:38.694878 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 18:05:38.694975 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 18:05:38.695061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 18:05:38.695145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 18:05:38.695230 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 18:05:38.695318 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 18:05:38.695402 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 18:05:38.695487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 18:05:38.695572 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 18:05:38.695655 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 18:05:38.695739 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 18:05:38.695823 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 18:05:38.695906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 18:05:38.695990 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 18:05:38.696074 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2974 18:05:38.696158 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2975 18:05:38.696241 Total UI for P1: 0, mck2ui 16
2976 18:05:38.696325 best dqsien dly found for B1: ( 1, 3, 28)
2977 18:05:38.696409 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 18:05:38.696492 Total UI for P1: 0, mck2ui 16
2979 18:05:38.696624 best dqsien dly found for B0: ( 1, 3, 30)
2980 18:05:38.696709 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2981 18:05:38.696793 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2982 18:05:38.696876
2983 18:05:38.696945 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2984 18:05:38.697002 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2985 18:05:38.697056 [Gating] SW calibration Done
2986 18:05:38.697110 ==
2987 18:05:38.697164 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 18:05:38.697219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 18:05:38.697273 ==
2990 18:05:38.697335 RX Vref Scan: 0
2991 18:05:38.697424
2992 18:05:38.697508 RX Vref 0 -> 0, step: 1
2993 18:05:38.697590
2994 18:05:38.697672 RX Delay -40 -> 252, step: 8
2995 18:05:38.697756 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2996 18:05:38.697839 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2997 18:05:38.697958 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2998 18:05:38.698042 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2999 18:05:38.698125 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3000 18:05:38.698208 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
3001 18:05:38.698284 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3002 18:05:38.698341 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3003 18:05:38.802737 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3004 18:05:38.802867 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3005 18:05:38.802935 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3006 18:05:38.803007 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3007 18:05:38.803094 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3008 18:05:38.803180 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3009 18:05:38.803242 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3010 18:05:38.803301 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
3011 18:05:38.803359 ==
3012 18:05:38.803416 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 18:05:38.803473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 18:05:38.803528 ==
3015 18:05:38.803583 DQS Delay:
3016 18:05:38.803643 DQS0 = 0, DQS1 = 0
3017 18:05:38.803700 DQM Delay:
3018 18:05:38.803754 DQM0 = 120, DQM1 = 108
3019 18:05:38.803809 DQ Delay:
3020 18:05:38.803863 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3021 18:05:38.803917 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3022 18:05:38.803971 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3023 18:05:38.804025 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3024 18:05:38.804079
3025 18:05:38.804132
3026 18:05:38.804185 ==
3027 18:05:38.804239 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 18:05:38.804293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 18:05:38.804347 ==
3030 18:05:38.804400
3031 18:05:38.804453
3032 18:05:38.804507 TX Vref Scan disable
3033 18:05:38.804589 == TX Byte 0 ==
3034 18:05:38.804659 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3035 18:05:38.804714 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3036 18:05:38.804768 == TX Byte 1 ==
3037 18:05:38.804822 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3038 18:05:38.804876 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3039 18:05:38.804929 ==
3040 18:05:38.804983 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 18:05:38.805037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 18:05:38.805091 ==
3043 18:05:38.805144 TX Vref=22, minBit 0, minWin=25, winSum=412
3044 18:05:38.805199 TX Vref=24, minBit 1, minWin=24, winSum=415
3045 18:05:38.805253 TX Vref=26, minBit 1, minWin=24, winSum=418
3046 18:05:38.805307 TX Vref=28, minBit 1, minWin=25, winSum=423
3047 18:05:38.805361 TX Vref=30, minBit 1, minWin=25, winSum=425
3048 18:05:38.805415 TX Vref=32, minBit 5, minWin=25, winSum=424
3049 18:05:38.805469 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
3050 18:05:38.805524
3051 18:05:38.805578 Final TX Range 1 Vref 30
3052 18:05:38.805637
3053 18:05:38.805696 ==
3054 18:05:38.805750 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 18:05:38.805804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 18:05:38.805859 ==
3057 18:05:38.805912
3058 18:05:38.805965
3059 18:05:38.806018 TX Vref Scan disable
3060 18:05:38.806072 == TX Byte 0 ==
3061 18:05:38.806126 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3062 18:05:38.806180 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3063 18:05:38.806234 == TX Byte 1 ==
3064 18:05:38.806288 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3065 18:05:38.806341 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3066 18:05:38.806395
3067 18:05:38.806448 [DATLAT]
3068 18:05:38.806501 Freq=1200, CH0 RK1
3069 18:05:38.806555
3070 18:05:38.806608 DATLAT Default: 0xd
3071 18:05:38.806661 0, 0xFFFF, sum = 0
3072 18:05:38.806716 1, 0xFFFF, sum = 0
3073 18:05:38.806771 2, 0xFFFF, sum = 0
3074 18:05:38.806825 3, 0xFFFF, sum = 0
3075 18:05:38.806879 4, 0xFFFF, sum = 0
3076 18:05:38.806933 5, 0xFFFF, sum = 0
3077 18:05:38.806987 6, 0xFFFF, sum = 0
3078 18:05:38.807249 7, 0xFFFF, sum = 0
3079 18:05:38.807333 8, 0xFFFF, sum = 0
3080 18:05:38.807456 9, 0xFFFF, sum = 0
3081 18:05:38.807556 10, 0xFFFF, sum = 0
3082 18:05:38.807643 11, 0xFFFF, sum = 0
3083 18:05:38.807728 12, 0x0, sum = 1
3084 18:05:38.807814 13, 0x0, sum = 2
3085 18:05:38.807899 14, 0x0, sum = 3
3086 18:05:38.807983 15, 0x0, sum = 4
3087 18:05:38.808068 best_step = 13
3088 18:05:38.808151
3089 18:05:38.808233 ==
3090 18:05:38.808317 Dram Type= 6, Freq= 0, CH_0, rank 1
3091 18:05:38.808401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 18:05:38.808484 ==
3093 18:05:38.808609 RX Vref Scan: 0
3094 18:05:38.808696
3095 18:05:38.808780 RX Vref 0 -> 0, step: 1
3096 18:05:38.808864
3097 18:05:38.808948 RX Delay -21 -> 252, step: 4
3098 18:05:38.809033 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3099 18:05:38.809119 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3100 18:05:38.809204 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3101 18:05:38.809289 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3102 18:05:38.809374 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3103 18:05:38.809459 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3104 18:05:38.809544 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3105 18:05:38.809629 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3106 18:05:38.809714 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3107 18:05:38.809799 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3108 18:05:38.809884 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3109 18:05:38.809969 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3110 18:05:38.810053 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3111 18:05:38.810138 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3112 18:05:38.810223 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3113 18:05:38.810307 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3114 18:05:38.810391 ==
3115 18:05:38.810475 Dram Type= 6, Freq= 0, CH_0, rank 1
3116 18:05:38.810560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 18:05:38.810645 ==
3118 18:05:38.810771 DQS Delay:
3119 18:05:38.810858 DQS0 = 0, DQS1 = 0
3120 18:05:38.810942 DQM Delay:
3121 18:05:38.811026 DQM0 = 119, DQM1 = 107
3122 18:05:38.811111 DQ Delay:
3123 18:05:38.811195 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3124 18:05:38.811280 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3125 18:05:38.811365 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3126 18:05:38.811450 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3127 18:05:38.811534
3128 18:05:38.811617
3129 18:05:38.811703 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3130 18:05:38.811788 CH0 RK1: MR19=403, MR18=11F8
3131 18:05:38.811874 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3132 18:05:38.811959 [RxdqsGatingPostProcess] freq 1200
3133 18:05:38.812045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3134 18:05:38.812130 best DQS0 dly(2T, 0.5T) = (0, 11)
3135 18:05:38.812214 best DQS1 dly(2T, 0.5T) = (0, 12)
3136 18:05:38.812299 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3137 18:05:38.812383 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3138 18:05:38.812467 best DQS0 dly(2T, 0.5T) = (0, 11)
3139 18:05:38.812554 best DQS1 dly(2T, 0.5T) = (0, 11)
3140 18:05:38.812645 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3141 18:05:38.812701 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3142 18:05:38.812757 Pre-setting of DQS Precalculation
3143 18:05:38.812813 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3144 18:05:38.812869 ==
3145 18:05:38.812925 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 18:05:38.812980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3147 18:05:38.813036 ==
3148 18:05:38.813091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3149 18:05:38.813147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3150 18:05:38.813202 [CA 0] Center 37 (7~68) winsize 62
3151 18:05:38.813257 [CA 1] Center 37 (7~68) winsize 62
3152 18:05:38.813312 [CA 2] Center 35 (5~65) winsize 61
3153 18:05:38.813367 [CA 3] Center 34 (4~65) winsize 62
3154 18:05:38.813422 [CA 4] Center 34 (4~64) winsize 61
3155 18:05:38.813477 [CA 5] Center 33 (3~64) winsize 62
3156 18:05:38.813531
3157 18:05:38.813586 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3158 18:05:38.813642
3159 18:05:38.813696 [CATrainingPosCal] consider 1 rank data
3160 18:05:38.813751 u2DelayCellTimex100 = 270/100 ps
3161 18:05:38.813807 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 18:05:38.813863 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3163 18:05:38.813919 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 18:05:38.813974 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3165 18:05:38.814029 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3166 18:05:38.814096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3167 18:05:38.814159
3168 18:05:38.814214 CA PerBit enable=1, Macro0, CA PI delay=33
3169 18:05:38.814270
3170 18:05:38.814324 [CBTSetCACLKResult] CA Dly = 33
3171 18:05:38.814379 CS Dly: 5 (0~36)
3172 18:05:38.814435 ==
3173 18:05:38.814490 Dram Type= 6, Freq= 0, CH_1, rank 1
3174 18:05:38.814545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 18:05:38.814601 ==
3176 18:05:38.814656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3177 18:05:38.814712 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3178 18:05:38.814768 [CA 0] Center 38 (8~69) winsize 62
3179 18:05:38.814824 [CA 1] Center 38 (7~69) winsize 63
3180 18:05:38.814879 [CA 2] Center 35 (5~66) winsize 62
3181 18:05:38.814933 [CA 3] Center 35 (5~65) winsize 61
3182 18:05:38.814988 [CA 4] Center 34 (4~64) winsize 61
3183 18:05:38.815043 [CA 5] Center 34 (4~64) winsize 61
3184 18:05:38.815098
3185 18:05:38.815153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3186 18:05:38.815208
3187 18:05:38.815263 [CATrainingPosCal] consider 2 rank data
3188 18:05:38.815318 u2DelayCellTimex100 = 270/100 ps
3189 18:05:38.815373 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3190 18:05:38.815429 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3191 18:05:38.815484 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3192 18:05:38.815539 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3193 18:05:38.815594 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3194 18:05:38.815649 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3195 18:05:38.815705
3196 18:05:38.815759 CA PerBit enable=1, Macro0, CA PI delay=34
3197 18:05:38.815814
3198 18:05:38.815869 [CBTSetCACLKResult] CA Dly = 34
3199 18:05:38.815924 CS Dly: 6 (0~39)
3200 18:05:38.815979
3201 18:05:38.816033 ----->DramcWriteLeveling(PI) begin...
3202 18:05:38.816090 ==
3203 18:05:38.816146 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 18:05:38.816201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 18:05:38.816257 ==
3206 18:05:38.816506 Write leveling (Byte 0): 25 => 25
3207 18:05:38.816614 Write leveling (Byte 1): 28 => 28
3208 18:05:38.816673 DramcWriteLeveling(PI) end<-----
3209 18:05:38.816729
3210 18:05:38.816784 ==
3211 18:05:38.816844 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 18:05:38.816900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 18:05:38.816957 ==
3214 18:05:38.817013 [Gating] SW mode calibration
3215 18:05:38.817069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3216 18:05:38.817125 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3217 18:05:38.817181 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 18:05:38.817241 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 18:05:38.817297 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 18:05:38.817353 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 18:05:38.817408 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 18:05:38.817464 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3223 18:05:38.817520 0 15 24 | B1->B0 | 2c2c 2828 | 0 0 | (1 0) (1 0)
3224 18:05:38.817576 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3225 18:05:38.817631 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 18:05:38.817687 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 18:05:38.817742 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 18:05:38.817797 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 18:05:38.817853 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3230 18:05:38.817909 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 18:05:38.817964 1 0 24 | B1->B0 | 3030 4141 | 1 0 | (0 0) (0 0)
3232 18:05:38.818019 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 18:05:38.818074 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 18:05:38.818130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 18:05:38.818186 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 18:05:38.818241 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 18:05:38.818296 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 18:05:38.818352 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3239 18:05:38.818407 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3240 18:05:38.818462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3241 18:05:38.818518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 18:05:38.818574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 18:05:38.818629 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 18:05:38.818684 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 18:05:38.818740 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 18:05:38.818795 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 18:05:38.818850 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 18:05:38.818905 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 18:05:38.818961 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 18:05:38.819016 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 18:05:38.819072 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 18:05:38.819126 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 18:05:38.819181 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 18:05:38.819236 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3255 18:05:38.819292 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3256 18:05:38.819346 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 18:05:38.819401 Total UI for P1: 0, mck2ui 16
3258 18:05:38.819457 best dqsien dly found for B0: ( 1, 3, 22)
3259 18:05:38.819512 Total UI for P1: 0, mck2ui 16
3260 18:05:38.819568 best dqsien dly found for B1: ( 1, 3, 24)
3261 18:05:38.819623 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3262 18:05:38.819678 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3263 18:05:38.819733
3264 18:05:38.819788 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3265 18:05:38.819844 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3266 18:05:38.819900 [Gating] SW calibration Done
3267 18:05:38.819955 ==
3268 18:05:38.820011 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 18:05:38.820066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 18:05:38.820122 ==
3271 18:05:38.820176 RX Vref Scan: 0
3272 18:05:38.820232
3273 18:05:38.820345 RX Vref 0 -> 0, step: 1
3274 18:05:38.820414
3275 18:05:38.820484 RX Delay -40 -> 252, step: 8
3276 18:05:38.820541 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3277 18:05:38.820621 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3278 18:05:38.820678 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3279 18:05:38.820734 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3280 18:05:38.820790 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3281 18:05:38.820845 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3282 18:05:38.820900 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3283 18:05:38.820960 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3284 18:05:38.821016 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3285 18:05:38.821071 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3286 18:05:38.821127 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3287 18:05:38.821182 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3288 18:05:38.821237 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3289 18:05:38.821292 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3290 18:05:38.821348 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3291 18:05:38.821402 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3292 18:05:38.821457 ==
3293 18:05:38.821513 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 18:05:38.821568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 18:05:38.821624 ==
3296 18:05:38.821680 DQS Delay:
3297 18:05:38.821735 DQS0 = 0, DQS1 = 0
3298 18:05:38.821790 DQM Delay:
3299 18:05:38.821846 DQM0 = 120, DQM1 = 113
3300 18:05:38.821901 DQ Delay:
3301 18:05:38.821955 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3302 18:05:38.822010 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3303 18:05:38.822065 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3304 18:05:38.822121 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3305 18:05:38.822176
3306 18:05:38.822230
3307 18:05:38.822285 ==
3308 18:05:38.822340 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 18:05:38.822395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 18:05:38.822644 ==
3311 18:05:38.822707
3312 18:05:38.822763
3313 18:05:38.822818 TX Vref Scan disable
3314 18:05:38.822873 == TX Byte 0 ==
3315 18:05:38.822929 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3316 18:05:38.822986 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3317 18:05:38.823042 == TX Byte 1 ==
3318 18:05:38.823097 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3319 18:05:38.823153 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3320 18:05:38.823209 ==
3321 18:05:38.823264 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 18:05:38.823319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 18:05:38.823375 ==
3324 18:05:38.823431 TX Vref=22, minBit 10, minWin=24, winSum=403
3325 18:05:38.823487 TX Vref=24, minBit 10, minWin=24, winSum=408
3326 18:05:38.823544 TX Vref=26, minBit 9, minWin=25, winSum=419
3327 18:05:38.823600 TX Vref=28, minBit 10, minWin=25, winSum=423
3328 18:05:38.823655 TX Vref=30, minBit 11, minWin=25, winSum=424
3329 18:05:38.823712 TX Vref=32, minBit 9, minWin=25, winSum=423
3330 18:05:38.823767 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 30
3331 18:05:38.823822
3332 18:05:38.823877 Final TX Range 1 Vref 30
3333 18:05:38.823932
3334 18:05:38.823987 ==
3335 18:05:38.824041 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 18:05:38.824097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 18:05:38.824152 ==
3338 18:05:38.824207
3339 18:05:38.824262
3340 18:05:38.824316 TX Vref Scan disable
3341 18:05:38.824372 == TX Byte 0 ==
3342 18:05:38.824427 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3343 18:05:38.824483 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3344 18:05:38.824538 == TX Byte 1 ==
3345 18:05:38.824637 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3346 18:05:38.824703 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3347 18:05:38.824792
3348 18:05:38.824876 [DATLAT]
3349 18:05:38.824960 Freq=1200, CH1 RK0
3350 18:05:38.825045
3351 18:05:38.825129 DATLAT Default: 0xd
3352 18:05:38.825213 0, 0xFFFF, sum = 0
3353 18:05:38.825300 1, 0xFFFF, sum = 0
3354 18:05:38.825386 2, 0xFFFF, sum = 0
3355 18:05:38.825472 3, 0xFFFF, sum = 0
3356 18:05:38.825559 4, 0xFFFF, sum = 0
3357 18:05:38.825645 5, 0xFFFF, sum = 0
3358 18:05:38.825731 6, 0xFFFF, sum = 0
3359 18:05:38.825817 7, 0xFFFF, sum = 0
3360 18:05:38.825903 8, 0xFFFF, sum = 0
3361 18:05:38.825987 9, 0xFFFF, sum = 0
3362 18:05:38.826072 10, 0xFFFF, sum = 0
3363 18:05:38.826156 11, 0xFFFF, sum = 0
3364 18:05:38.826241 12, 0x0, sum = 1
3365 18:05:38.826326 13, 0x0, sum = 2
3366 18:05:38.826411 14, 0x0, sum = 3
3367 18:05:38.826495 15, 0x0, sum = 4
3368 18:05:38.826579 best_step = 13
3369 18:05:38.826661
3370 18:05:38.826743 ==
3371 18:05:38.826827 Dram Type= 6, Freq= 0, CH_1, rank 0
3372 18:05:38.826911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3373 18:05:38.826994 ==
3374 18:05:38.827077 RX Vref Scan: 1
3375 18:05:38.827159
3376 18:05:38.827241 Set Vref Range= 32 -> 127
3377 18:05:38.827324
3378 18:05:38.827406 RX Vref 32 -> 127, step: 1
3379 18:05:38.827488
3380 18:05:38.827563 RX Delay -13 -> 252, step: 4
3381 18:05:38.827618
3382 18:05:38.827677 Set Vref, RX VrefLevel [Byte0]: 32
3383 18:05:38.827731 [Byte1]: 32
3384 18:05:38.827785
3385 18:05:38.827838 Set Vref, RX VrefLevel [Byte0]: 33
3386 18:05:38.827892 [Byte1]: 33
3387 18:05:38.827946
3388 18:05:38.827999 Set Vref, RX VrefLevel [Byte0]: 34
3389 18:05:38.828053 [Byte1]: 34
3390 18:05:38.828106
3391 18:05:38.828159 Set Vref, RX VrefLevel [Byte0]: 35
3392 18:05:38.828213 [Byte1]: 35
3393 18:05:38.828266
3394 18:05:38.828319 Set Vref, RX VrefLevel [Byte0]: 36
3395 18:05:38.828372 [Byte1]: 36
3396 18:05:38.828426
3397 18:05:38.828479 Set Vref, RX VrefLevel [Byte0]: 37
3398 18:05:38.828532 [Byte1]: 37
3399 18:05:38.828604
3400 18:05:38.828657 Set Vref, RX VrefLevel [Byte0]: 38
3401 18:05:38.828711 [Byte1]: 38
3402 18:05:38.828765
3403 18:05:38.828818 Set Vref, RX VrefLevel [Byte0]: 39
3404 18:05:38.828872 [Byte1]: 39
3405 18:05:38.828927
3406 18:05:38.828998 Set Vref, RX VrefLevel [Byte0]: 40
3407 18:05:38.829055 [Byte1]: 40
3408 18:05:38.829109
3409 18:05:38.829162 Set Vref, RX VrefLevel [Byte0]: 41
3410 18:05:38.829216 [Byte1]: 41
3411 18:05:38.829270
3412 18:05:38.829323 Set Vref, RX VrefLevel [Byte0]: 42
3413 18:05:38.829377 [Byte1]: 42
3414 18:05:38.829430
3415 18:05:38.829483 Set Vref, RX VrefLevel [Byte0]: 43
3416 18:05:38.829537 [Byte1]: 43
3417 18:05:38.829591
3418 18:05:38.829644 Set Vref, RX VrefLevel [Byte0]: 44
3419 18:05:38.829698 [Byte1]: 44
3420 18:05:38.829751
3421 18:05:38.829804 Set Vref, RX VrefLevel [Byte0]: 45
3422 18:05:38.829858 [Byte1]: 45
3423 18:05:38.829911
3424 18:05:38.829964 Set Vref, RX VrefLevel [Byte0]: 46
3425 18:05:38.830018 [Byte1]: 46
3426 18:05:38.830071
3427 18:05:38.830125 Set Vref, RX VrefLevel [Byte0]: 47
3428 18:05:38.830178 [Byte1]: 47
3429 18:05:38.830231
3430 18:05:38.830291 Set Vref, RX VrefLevel [Byte0]: 48
3431 18:05:38.830346 [Byte1]: 48
3432 18:05:38.830402
3433 18:05:38.830456 Set Vref, RX VrefLevel [Byte0]: 49
3434 18:05:38.830510 [Byte1]: 49
3435 18:05:38.830564
3436 18:05:38.830617 Set Vref, RX VrefLevel [Byte0]: 50
3437 18:05:38.830670 [Byte1]: 50
3438 18:05:38.830724
3439 18:05:38.830777 Set Vref, RX VrefLevel [Byte0]: 51
3440 18:05:38.830830 [Byte1]: 51
3441 18:05:38.830883
3442 18:05:38.830937 Set Vref, RX VrefLevel [Byte0]: 52
3443 18:05:38.830990 [Byte1]: 52
3444 18:05:38.831044
3445 18:05:38.831097 Set Vref, RX VrefLevel [Byte0]: 53
3446 18:05:38.831150 [Byte1]: 53
3447 18:05:38.831204
3448 18:05:38.831258 Set Vref, RX VrefLevel [Byte0]: 54
3449 18:05:38.831311 [Byte1]: 54
3450 18:05:38.831365
3451 18:05:38.831418 Set Vref, RX VrefLevel [Byte0]: 55
3452 18:05:38.831472 [Byte1]: 55
3453 18:05:38.831525
3454 18:05:38.831578 Set Vref, RX VrefLevel [Byte0]: 56
3455 18:05:38.831632 [Byte1]: 56
3456 18:05:38.831686
3457 18:05:38.831739 Set Vref, RX VrefLevel [Byte0]: 57
3458 18:05:38.831792 [Byte1]: 57
3459 18:05:38.831845
3460 18:05:38.831898 Set Vref, RX VrefLevel [Byte0]: 58
3461 18:05:38.831951 [Byte1]: 58
3462 18:05:38.832004
3463 18:05:38.832056 Set Vref, RX VrefLevel [Byte0]: 59
3464 18:05:38.832109 [Byte1]: 59
3465 18:05:38.832163
3466 18:05:38.832215 Set Vref, RX VrefLevel [Byte0]: 60
3467 18:05:38.832268 [Byte1]: 60
3468 18:05:38.832322
3469 18:05:38.832392 Set Vref, RX VrefLevel [Byte0]: 61
3470 18:05:38.832459 [Byte1]: 61
3471 18:05:38.832513
3472 18:05:38.832602 Set Vref, RX VrefLevel [Byte0]: 62
3473 18:05:38.832657 [Byte1]: 62
3474 18:05:38.832711
3475 18:05:38.832763 Set Vref, RX VrefLevel [Byte0]: 63
3476 18:05:38.833012 [Byte1]: 63
3477 18:05:38.833073
3478 18:05:38.833128 Set Vref, RX VrefLevel [Byte0]: 64
3479 18:05:38.833182 [Byte1]: 64
3480 18:05:38.833236
3481 18:05:38.833290 Set Vref, RX VrefLevel [Byte0]: 65
3482 18:05:38.833343 [Byte1]: 65
3483 18:05:38.833397
3484 18:05:38.833450 Set Vref, RX VrefLevel [Byte0]: 66
3485 18:05:38.833504 [Byte1]: 66
3486 18:05:38.833558
3487 18:05:38.833612 Final RX Vref Byte 0 = 51 to rank0
3488 18:05:38.833670 Final RX Vref Byte 1 = 49 to rank0
3489 18:05:38.833729 Final RX Vref Byte 0 = 51 to rank1
3490 18:05:38.833784 Final RX Vref Byte 1 = 49 to rank1==
3491 18:05:38.833838 Dram Type= 6, Freq= 0, CH_1, rank 0
3492 18:05:38.833893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 18:05:38.833947 ==
3494 18:05:38.834001 DQS Delay:
3495 18:05:38.834054 DQS0 = 0, DQS1 = 0
3496 18:05:38.834108 DQM Delay:
3497 18:05:38.834161 DQM0 = 119, DQM1 = 111
3498 18:05:38.834215 DQ Delay:
3499 18:05:38.834268 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3500 18:05:38.834322 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3501 18:05:38.834375 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3502 18:05:38.834429 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =116
3503 18:05:38.834482
3504 18:05:38.834535
3505 18:05:38.834589 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3506 18:05:38.834644 CH1 RK0: MR19=404, MR18=316
3507 18:05:38.834697 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3508 18:05:38.834751
3509 18:05:38.834805 ----->DramcWriteLeveling(PI) begin...
3510 18:05:38.834860 ==
3511 18:05:38.834913 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 18:05:38.834967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 18:05:38.835021 ==
3514 18:05:38.835075 Write leveling (Byte 0): 25 => 25
3515 18:05:38.835129 Write leveling (Byte 1): 29 => 29
3516 18:05:38.835182 DramcWriteLeveling(PI) end<-----
3517 18:05:38.835235
3518 18:05:38.835288 ==
3519 18:05:38.835351 Dram Type= 6, Freq= 0, CH_1, rank 1
3520 18:05:38.835406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3521 18:05:38.835460 ==
3522 18:05:38.835514 [Gating] SW mode calibration
3523 18:05:38.835568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3524 18:05:38.835622 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3525 18:05:38.835676 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 18:05:38.835730 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 18:05:38.835784 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 18:05:38.835838 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 18:05:38.835892 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 18:05:38.835946 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 18:05:38.836000 0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)
3532 18:05:38.836053 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 0)
3533 18:05:38.836107 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 18:05:38.836161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 18:05:38.836215 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 18:05:38.836268 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 18:05:38.836322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 18:05:38.836376 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 18:05:38.836430 1 0 24 | B1->B0 | 3c3c 2525 | 0 0 | (0 0) (0 0)
3540 18:05:38.836483 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3541 18:05:38.836537 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 18:05:38.836632 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 18:05:38.836686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 18:05:38.836740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 18:05:38.836794 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 18:05:38.836848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 18:05:38.836902 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3548 18:05:38.836955 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3549 18:05:38.837009 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 18:05:38.837067 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 18:05:38.837124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 18:05:38.837178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 18:05:38.837232 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 18:05:38.837286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 18:05:38.837365 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 18:05:38.837442 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 18:05:38.837499 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 18:05:38.837554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 18:05:38.837608 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 18:05:38.837663 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 18:05:38.837718 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 18:05:38.837772 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 18:05:38.837825 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3564 18:05:38.837879 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3565 18:05:38.837933 Total UI for P1: 0, mck2ui 16
3566 18:05:38.837988 best dqsien dly found for B1: ( 1, 3, 24)
3567 18:05:38.838042 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 18:05:38.838096 Total UI for P1: 0, mck2ui 16
3569 18:05:38.838150 best dqsien dly found for B0: ( 1, 3, 26)
3570 18:05:38.838204 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3571 18:05:38.838258 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3572 18:05:38.838311
3573 18:05:38.838365 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3574 18:05:38.838418 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3575 18:05:38.838472 [Gating] SW calibration Done
3576 18:05:38.838525 ==
3577 18:05:38.838579 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 18:05:38.838633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 18:05:38.838687 ==
3580 18:05:38.838740 RX Vref Scan: 0
3581 18:05:38.838794
3582 18:05:38.838847 RX Vref 0 -> 0, step: 1
3583 18:05:38.838901
3584 18:05:38.838954 RX Delay -40 -> 252, step: 8
3585 18:05:38.839007 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3586 18:05:38.839256 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3587 18:05:38.839321 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3588 18:05:38.839379 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3589 18:05:38.839433 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3590 18:05:38.839487 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3591 18:05:38.839541 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3592 18:05:38.839594 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3593 18:05:38.839648 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3594 18:05:38.839703 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3595 18:05:38.839756 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3596 18:05:38.839810 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3597 18:05:38.839864 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3598 18:05:38.839917 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3599 18:05:38.839971 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3600 18:05:38.840025 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3601 18:05:38.840078 ==
3602 18:05:38.840132 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 18:05:38.840192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 18:05:38.840249 ==
3605 18:05:38.840333 DQS Delay:
3606 18:05:38.840417 DQS0 = 0, DQS1 = 0
3607 18:05:38.840499 DQM Delay:
3608 18:05:38.840615 DQM0 = 119, DQM1 = 112
3609 18:05:38.840672 DQ Delay:
3610 18:05:38.840726 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3611 18:05:38.840780 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3612 18:05:38.840835 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3613 18:05:38.840889 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3614 18:05:38.840943
3615 18:05:38.840997
3616 18:05:38.841049 ==
3617 18:05:38.841103 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 18:05:38.841157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 18:05:38.841212 ==
3620 18:05:38.841264
3621 18:05:38.841335
3622 18:05:38.841420 TX Vref Scan disable
3623 18:05:38.841479 == TX Byte 0 ==
3624 18:05:38.841534 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3625 18:05:38.841590 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3626 18:05:38.841645 == TX Byte 1 ==
3627 18:05:38.841698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 18:05:38.841753 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 18:05:38.841807 ==
3630 18:05:38.841861 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 18:05:38.841914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 18:05:38.841969 ==
3633 18:05:38.842022 TX Vref=22, minBit 9, minWin=25, winSum=420
3634 18:05:38.842077 TX Vref=24, minBit 1, minWin=25, winSum=418
3635 18:05:38.842131 TX Vref=26, minBit 3, minWin=26, winSum=425
3636 18:05:38.842185 TX Vref=28, minBit 1, minWin=26, winSum=428
3637 18:05:38.842239 TX Vref=30, minBit 8, minWin=26, winSum=429
3638 18:05:38.842293 TX Vref=32, minBit 1, minWin=26, winSum=426
3639 18:05:38.842347 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3640 18:05:38.842402
3641 18:05:38.842456 Final TX Range 1 Vref 30
3642 18:05:38.842510
3643 18:05:38.842563 ==
3644 18:05:38.842616 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 18:05:38.842670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 18:05:38.842724 ==
3647 18:05:38.842777
3648 18:05:38.842830
3649 18:05:38.842883 TX Vref Scan disable
3650 18:05:38.842937 == TX Byte 0 ==
3651 18:05:38.842991 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3652 18:05:38.843044 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3653 18:05:38.843098 == TX Byte 1 ==
3654 18:05:38.843152 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3655 18:05:38.843205 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3656 18:05:38.843258
3657 18:05:38.843311 [DATLAT]
3658 18:05:38.843396 Freq=1200, CH1 RK1
3659 18:05:38.843467
3660 18:05:38.843520 DATLAT Default: 0xd
3661 18:05:38.843574 0, 0xFFFF, sum = 0
3662 18:05:38.843629 1, 0xFFFF, sum = 0
3663 18:05:38.843684 2, 0xFFFF, sum = 0
3664 18:05:38.843738 3, 0xFFFF, sum = 0
3665 18:05:38.843793 4, 0xFFFF, sum = 0
3666 18:05:38.843847 5, 0xFFFF, sum = 0
3667 18:05:38.843901 6, 0xFFFF, sum = 0
3668 18:05:38.843954 7, 0xFFFF, sum = 0
3669 18:05:38.844009 8, 0xFFFF, sum = 0
3670 18:05:38.844063 9, 0xFFFF, sum = 0
3671 18:05:38.844117 10, 0xFFFF, sum = 0
3672 18:05:38.844171 11, 0xFFFF, sum = 0
3673 18:05:38.844226 12, 0x0, sum = 1
3674 18:05:38.844280 13, 0x0, sum = 2
3675 18:05:38.844334 14, 0x0, sum = 3
3676 18:05:38.844389 15, 0x0, sum = 4
3677 18:05:38.844443 best_step = 13
3678 18:05:38.844497
3679 18:05:38.844554 ==
3680 18:05:38.844643 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 18:05:38.844697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 18:05:38.844752 ==
3683 18:05:38.844805 RX Vref Scan: 0
3684 18:05:38.844859
3685 18:05:38.844912 RX Vref 0 -> 0, step: 1
3686 18:05:38.844965
3687 18:05:38.845017 RX Delay -13 -> 252, step: 4
3688 18:05:38.845070 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3689 18:05:38.845125 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3690 18:05:38.845178 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3691 18:05:38.845232 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3692 18:05:38.845285 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3693 18:05:38.845338 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3694 18:05:38.845392 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3695 18:05:38.845446 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3696 18:05:38.845499 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3697 18:05:38.845552 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3698 18:05:38.845605 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3699 18:05:38.845659 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3700 18:05:38.845713 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3701 18:05:38.845767 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3702 18:05:38.845820 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3703 18:05:38.845874 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3704 18:05:38.845927 ==
3705 18:05:38.845981 Dram Type= 6, Freq= 0, CH_1, rank 1
3706 18:05:38.846035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3707 18:05:38.846089 ==
3708 18:05:38.846143 DQS Delay:
3709 18:05:38.846196 DQS0 = 0, DQS1 = 0
3710 18:05:38.846249 DQM Delay:
3711 18:05:38.846302 DQM0 = 119, DQM1 = 112
3712 18:05:38.846355 DQ Delay:
3713 18:05:38.846409 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3714 18:05:38.846462 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3715 18:05:38.846516 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3716 18:05:38.846569 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =120
3717 18:05:38.846622
3718 18:05:38.846675
3719 18:05:38.846732 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3720 18:05:38.846806 CH1 RK1: MR19=403, MR18=8EC
3721 18:05:38.846862 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3722 18:05:38.846923 [RxdqsGatingPostProcess] freq 1200
3723 18:05:38.847173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3724 18:05:38.847238 best DQS0 dly(2T, 0.5T) = (0, 11)
3725 18:05:38.847302 best DQS1 dly(2T, 0.5T) = (0, 11)
3726 18:05:38.847366 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3727 18:05:38.847451 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3728 18:05:38.847534 best DQS0 dly(2T, 0.5T) = (0, 11)
3729 18:05:38.847618 best DQS1 dly(2T, 0.5T) = (0, 11)
3730 18:05:38.847701 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3731 18:05:38.847784 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3732 18:05:38.847868 Pre-setting of DQS Precalculation
3733 18:05:38.847951 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3734 18:05:38.848036 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3735 18:05:38.848121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3736 18:05:38.848204
3737 18:05:38.848286
3738 18:05:38.848369 [Calibration Summary] 2400 Mbps
3739 18:05:38.848451 CH 0, Rank 0
3740 18:05:38.848534 SW Impedance : PASS
3741 18:05:38.848639 DUTY Scan : NO K
3742 18:05:38.848694 ZQ Calibration : PASS
3743 18:05:38.848748 Jitter Meter : NO K
3744 18:05:38.848802 CBT Training : PASS
3745 18:05:38.848855 Write leveling : PASS
3746 18:05:38.848908 RX DQS gating : PASS
3747 18:05:38.848962 RX DQ/DQS(RDDQC) : PASS
3748 18:05:38.849016 TX DQ/DQS : PASS
3749 18:05:38.849070 RX DATLAT : PASS
3750 18:05:38.849124 RX DQ/DQS(Engine): PASS
3751 18:05:38.849177 TX OE : NO K
3752 18:05:38.849232 All Pass.
3753 18:05:38.849285
3754 18:05:38.849339 CH 0, Rank 1
3755 18:05:38.849392 SW Impedance : PASS
3756 18:05:38.849445 DUTY Scan : NO K
3757 18:05:38.849498 ZQ Calibration : PASS
3758 18:05:38.849552 Jitter Meter : NO K
3759 18:05:38.849604 CBT Training : PASS
3760 18:05:38.849658 Write leveling : PASS
3761 18:05:38.849711 RX DQS gating : PASS
3762 18:05:38.849764 RX DQ/DQS(RDDQC) : PASS
3763 18:05:38.849818 TX DQ/DQS : PASS
3764 18:05:38.849871 RX DATLAT : PASS
3765 18:05:38.849924 RX DQ/DQS(Engine): PASS
3766 18:05:38.849977 TX OE : NO K
3767 18:05:38.850031 All Pass.
3768 18:05:38.850084
3769 18:05:38.850136 CH 1, Rank 0
3770 18:05:38.850189 SW Impedance : PASS
3771 18:05:38.850243 DUTY Scan : NO K
3772 18:05:38.850302 ZQ Calibration : PASS
3773 18:05:38.850356 Jitter Meter : NO K
3774 18:05:38.850415 CBT Training : PASS
3775 18:05:38.850469 Write leveling : PASS
3776 18:05:38.850526 RX DQS gating : PASS
3777 18:05:38.850581 RX DQ/DQS(RDDQC) : PASS
3778 18:05:38.850638 TX DQ/DQS : PASS
3779 18:05:38.850694 RX DATLAT : PASS
3780 18:05:38.850747 RX DQ/DQS(Engine): PASS
3781 18:05:38.850800 TX OE : NO K
3782 18:05:38.850854 All Pass.
3783 18:05:38.850907
3784 18:05:38.850961 CH 1, Rank 1
3785 18:05:38.851014 SW Impedance : PASS
3786 18:05:38.851067 DUTY Scan : NO K
3787 18:05:38.851120 ZQ Calibration : PASS
3788 18:05:38.851174 Jitter Meter : NO K
3789 18:05:38.851227 CBT Training : PASS
3790 18:05:38.851281 Write leveling : PASS
3791 18:05:38.851334 RX DQS gating : PASS
3792 18:05:38.851388 RX DQ/DQS(RDDQC) : PASS
3793 18:05:38.851441 TX DQ/DQS : PASS
3794 18:05:38.851494 RX DATLAT : PASS
3795 18:05:38.851548 RX DQ/DQS(Engine): PASS
3796 18:05:38.851601 TX OE : NO K
3797 18:05:38.851655 All Pass.
3798 18:05:38.851708
3799 18:05:38.851760 DramC Write-DBI off
3800 18:05:38.851814 PER_BANK_REFRESH: Hybrid Mode
3801 18:05:38.851868 TX_TRACKING: ON
3802 18:05:38.851922 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3803 18:05:38.851976 [FAST_K] Save calibration result to emmc
3804 18:05:38.852030 dramc_set_vcore_voltage set vcore to 650000
3805 18:05:38.852084 Read voltage for 600, 5
3806 18:05:38.852138 Vio18 = 0
3807 18:05:38.852192 Vcore = 650000
3808 18:05:38.852245 Vdram = 0
3809 18:05:38.852298 Vddq = 0
3810 18:05:38.852351 Vmddr = 0
3811 18:05:38.852404 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3812 18:05:38.852459 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3813 18:05:38.852513 MEM_TYPE=3, freq_sel=19
3814 18:05:38.852610 sv_algorithm_assistance_LP4_1600
3815 18:05:38.852667 ============ PULL DRAM RESETB DOWN ============
3816 18:05:38.852721 ========== PULL DRAM RESETB DOWN end =========
3817 18:05:38.852776 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3818 18:05:38.852830 ===================================
3819 18:05:38.852883 LPDDR4 DRAM CONFIGURATION
3820 18:05:38.852937 ===================================
3821 18:05:38.852990 EX_ROW_EN[0] = 0x0
3822 18:05:38.853044 EX_ROW_EN[1] = 0x0
3823 18:05:38.853097 LP4Y_EN = 0x0
3824 18:05:38.853151 WORK_FSP = 0x0
3825 18:05:38.853204 WL = 0x2
3826 18:05:38.853257 RL = 0x2
3827 18:05:38.853310 BL = 0x2
3828 18:05:38.853364 RPST = 0x0
3829 18:05:38.853417 RD_PRE = 0x0
3830 18:05:38.853470 WR_PRE = 0x1
3831 18:05:38.853523 WR_PST = 0x0
3832 18:05:38.853576 DBI_WR = 0x0
3833 18:05:38.853629 DBI_RD = 0x0
3834 18:05:38.853682 OTF = 0x1
3835 18:05:38.853736 ===================================
3836 18:05:38.853789 ===================================
3837 18:05:38.853844 ANA top config
3838 18:05:38.853897 ===================================
3839 18:05:38.853950 DLL_ASYNC_EN = 0
3840 18:05:38.854004 ALL_SLAVE_EN = 1
3841 18:05:38.854057 NEW_RANK_MODE = 1
3842 18:05:38.854111 DLL_IDLE_MODE = 1
3843 18:05:38.854165 LP45_APHY_COMB_EN = 1
3844 18:05:38.854218 TX_ODT_DIS = 1
3845 18:05:38.854272 NEW_8X_MODE = 1
3846 18:05:38.854325 ===================================
3847 18:05:38.854380 ===================================
3848 18:05:38.854433 data_rate = 1200
3849 18:05:38.854486 CKR = 1
3850 18:05:38.854539 DQ_P2S_RATIO = 8
3851 18:05:38.854593 ===================================
3852 18:05:38.854646 CA_P2S_RATIO = 8
3853 18:05:38.854699 DQ_CA_OPEN = 0
3854 18:05:38.854752 DQ_SEMI_OPEN = 0
3855 18:05:38.854806 CA_SEMI_OPEN = 0
3856 18:05:38.854859 CA_FULL_RATE = 0
3857 18:05:38.854912 DQ_CKDIV4_EN = 1
3858 18:05:38.854965 CA_CKDIV4_EN = 1
3859 18:05:38.855018 CA_PREDIV_EN = 0
3860 18:05:38.855071 PH8_DLY = 0
3861 18:05:38.855124 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3862 18:05:38.855177 DQ_AAMCK_DIV = 4
3863 18:05:38.855230 CA_AAMCK_DIV = 4
3864 18:05:38.855284 CA_ADMCK_DIV = 4
3865 18:05:38.855336 DQ_TRACK_CA_EN = 0
3866 18:05:38.855402 CA_PICK = 600
3867 18:05:38.855459 CA_MCKIO = 600
3868 18:05:38.855514 MCKIO_SEMI = 0
3869 18:05:38.857396 PLL_FREQ = 2288
3870 18:05:38.860590 DQ_UI_PI_RATIO = 32
3871 18:05:38.863816 CA_UI_PI_RATIO = 0
3872 18:05:38.866864 ===================================
3873 18:05:38.870459 ===================================
3874 18:05:38.873594 memory_type:LPDDR4
3875 18:05:38.873677 GP_NUM : 10
3876 18:05:38.876674 SRAM_EN : 1
3877 18:05:38.880539 MD32_EN : 0
3878 18:05:38.883567 ===================================
3879 18:05:38.883650 [ANA_INIT] >>>>>>>>>>>>>>
3880 18:05:38.886931 <<<<<< [CONFIGURE PHASE]: ANA_TX
3881 18:05:38.890206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3882 18:05:38.893416 ===================================
3883 18:05:38.896839 data_rate = 1200,PCW = 0X5800
3884 18:05:38.900030 ===================================
3885 18:05:38.903120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3886 18:05:38.909974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 18:05:38.913100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3888 18:05:38.920201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3889 18:05:38.923421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3890 18:05:38.926818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3891 18:05:38.929999 [ANA_INIT] flow start
3892 18:05:38.930176 [ANA_INIT] PLL >>>>>>>>
3893 18:05:38.933259 [ANA_INIT] PLL <<<<<<<<
3894 18:05:38.936600 [ANA_INIT] MIDPI >>>>>>>>
3895 18:05:38.936753 [ANA_INIT] MIDPI <<<<<<<<
3896 18:05:38.939703 [ANA_INIT] DLL >>>>>>>>
3897 18:05:38.943352 [ANA_INIT] flow end
3898 18:05:38.946406 ============ LP4 DIFF to SE enter ============
3899 18:05:38.949719 ============ LP4 DIFF to SE exit ============
3900 18:05:38.952973 [ANA_INIT] <<<<<<<<<<<<<
3901 18:05:38.956262 [Flow] Enable top DCM control >>>>>
3902 18:05:38.959909 [Flow] Enable top DCM control <<<<<
3903 18:05:38.963155 Enable DLL master slave shuffle
3904 18:05:38.966372 ==============================================================
3905 18:05:38.969531 Gating Mode config
3906 18:05:38.976513 ==============================================================
3907 18:05:38.976854 Config description:
3908 18:05:38.986800 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3909 18:05:38.993393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3910 18:05:38.996525 SELPH_MODE 0: By rank 1: By Phase
3911 18:05:39.003135 ==============================================================
3912 18:05:39.006354 GAT_TRACK_EN = 1
3913 18:05:39.009992 RX_GATING_MODE = 2
3914 18:05:39.013099 RX_GATING_TRACK_MODE = 2
3915 18:05:39.016298 SELPH_MODE = 1
3916 18:05:39.019453 PICG_EARLY_EN = 1
3917 18:05:39.022841 VALID_LAT_VALUE = 1
3918 18:05:39.026007 ==============================================================
3919 18:05:39.029414 Enter into Gating configuration >>>>
3920 18:05:39.032685 Exit from Gating configuration <<<<
3921 18:05:39.035966 Enter into DVFS_PRE_config >>>>>
3922 18:05:39.049559 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3923 18:05:39.049992 Exit from DVFS_PRE_config <<<<<
3924 18:05:39.052539 Enter into PICG configuration >>>>
3925 18:05:39.056148 Exit from PICG configuration <<<<
3926 18:05:39.059502 [RX_INPUT] configuration >>>>>
3927 18:05:39.063139 [RX_INPUT] configuration <<<<<
3928 18:05:39.069321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3929 18:05:39.072674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3930 18:05:39.079450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3931 18:05:39.085770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3932 18:05:39.092847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3933 18:05:39.099177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3934 18:05:39.102318 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3935 18:05:39.105648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3936 18:05:39.108785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3937 18:05:39.115539 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3938 18:05:39.119008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3939 18:05:39.122130 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3940 18:05:39.125500 ===================================
3941 18:05:39.129130 LPDDR4 DRAM CONFIGURATION
3942 18:05:39.132348 ===================================
3943 18:05:39.135525 EX_ROW_EN[0] = 0x0
3944 18:05:39.136007 EX_ROW_EN[1] = 0x0
3945 18:05:39.138864 LP4Y_EN = 0x0
3946 18:05:39.139291 WORK_FSP = 0x0
3947 18:05:39.142206 WL = 0x2
3948 18:05:39.142647 RL = 0x2
3949 18:05:39.145409 BL = 0x2
3950 18:05:39.145827 RPST = 0x0
3951 18:05:39.148595 RD_PRE = 0x0
3952 18:05:39.149040 WR_PRE = 0x1
3953 18:05:39.152252 WR_PST = 0x0
3954 18:05:39.152882 DBI_WR = 0x0
3955 18:05:39.155499 DBI_RD = 0x0
3956 18:05:39.155934 OTF = 0x1
3957 18:05:39.158542 ===================================
3958 18:05:39.162367 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3959 18:05:39.168596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3960 18:05:39.172011 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3961 18:05:39.175257 ===================================
3962 18:05:39.178489 LPDDR4 DRAM CONFIGURATION
3963 18:05:39.181977 ===================================
3964 18:05:39.182436 EX_ROW_EN[0] = 0x10
3965 18:05:39.185341 EX_ROW_EN[1] = 0x0
3966 18:05:39.188410 LP4Y_EN = 0x0
3967 18:05:39.188788 WORK_FSP = 0x0
3968 18:05:39.191757 WL = 0x2
3969 18:05:39.192162 RL = 0x2
3970 18:05:39.194851 BL = 0x2
3971 18:05:39.195230 RPST = 0x0
3972 18:05:39.198803 RD_PRE = 0x0
3973 18:05:39.199324 WR_PRE = 0x1
3974 18:05:39.201986 WR_PST = 0x0
3975 18:05:39.202504 DBI_WR = 0x0
3976 18:05:39.205438 DBI_RD = 0x0
3977 18:05:39.205895 OTF = 0x1
3978 18:05:39.208674 ===================================
3979 18:05:39.215403 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3980 18:05:39.219475 nWR fixed to 30
3981 18:05:39.223201 [ModeRegInit_LP4] CH0 RK0
3982 18:05:39.223652 [ModeRegInit_LP4] CH0 RK1
3983 18:05:39.226186 [ModeRegInit_LP4] CH1 RK0
3984 18:05:39.229449 [ModeRegInit_LP4] CH1 RK1
3985 18:05:39.229901 match AC timing 17
3986 18:05:39.236051 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3987 18:05:39.239351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3988 18:05:39.242513 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3989 18:05:39.248977 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3990 18:05:39.252297 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3991 18:05:39.252883 ==
3992 18:05:39.255542 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 18:05:39.259113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 18:05:39.259682 ==
3995 18:05:39.265672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 18:05:39.272536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 18:05:39.275932 [CA 0] Center 36 (6~67) winsize 62
3998 18:05:39.279262 [CA 1] Center 36 (6~67) winsize 62
3999 18:05:39.282443 [CA 2] Center 34 (4~65) winsize 62
4000 18:05:39.286032 [CA 3] Center 34 (3~65) winsize 63
4001 18:05:39.289154 [CA 4] Center 33 (3~64) winsize 62
4002 18:05:39.292322 [CA 5] Center 33 (2~64) winsize 63
4003 18:05:39.292879
4004 18:05:39.296135 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 18:05:39.296685
4006 18:05:39.299253 [CATrainingPosCal] consider 1 rank data
4007 18:05:39.302508 u2DelayCellTimex100 = 270/100 ps
4008 18:05:39.305701 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4009 18:05:39.308871 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4010 18:05:39.312076 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4011 18:05:39.315405 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4012 18:05:39.318848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4013 18:05:39.325571 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4014 18:05:39.325971
4015 18:05:39.328629 CA PerBit enable=1, Macro0, CA PI delay=33
4016 18:05:39.329065
4017 18:05:39.331878 [CBTSetCACLKResult] CA Dly = 33
4018 18:05:39.332303 CS Dly: 4 (0~35)
4019 18:05:39.332799 ==
4020 18:05:39.335706 Dram Type= 6, Freq= 0, CH_0, rank 1
4021 18:05:39.338975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 18:05:39.342288 ==
4023 18:05:39.345418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4024 18:05:39.351984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4025 18:05:39.355270 [CA 0] Center 36 (6~67) winsize 62
4026 18:05:39.358755 [CA 1] Center 36 (6~67) winsize 62
4027 18:05:39.362265 [CA 2] Center 35 (4~66) winsize 63
4028 18:05:39.365178 [CA 3] Center 35 (4~66) winsize 63
4029 18:05:39.368861 [CA 4] Center 34 (3~65) winsize 63
4030 18:05:39.371885 [CA 5] Center 34 (3~65) winsize 63
4031 18:05:39.372508
4032 18:05:39.374948 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4033 18:05:39.375579
4034 18:05:39.378579 [CATrainingPosCal] consider 2 rank data
4035 18:05:39.381921 u2DelayCellTimex100 = 270/100 ps
4036 18:05:39.385087 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4037 18:05:39.388912 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4038 18:05:39.392014 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4039 18:05:39.398332 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4040 18:05:39.401489 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4041 18:05:39.405352 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4042 18:05:39.405823
4043 18:05:39.408571 CA PerBit enable=1, Macro0, CA PI delay=33
4044 18:05:39.409016
4045 18:05:39.411862 [CBTSetCACLKResult] CA Dly = 33
4046 18:05:39.412292 CS Dly: 5 (0~37)
4047 18:05:39.412680
4048 18:05:39.415156 ----->DramcWriteLeveling(PI) begin...
4049 18:05:39.415590 ==
4050 18:05:39.418355 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 18:05:39.425014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 18:05:39.425445 ==
4053 18:05:39.428240 Write leveling (Byte 0): 35 => 35
4054 18:05:39.431797 Write leveling (Byte 1): 31 => 31
4055 18:05:39.434918 DramcWriteLeveling(PI) end<-----
4056 18:05:39.435400
4057 18:05:39.435743 ==
4058 18:05:39.437999 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 18:05:39.441200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 18:05:39.441634 ==
4061 18:05:39.444602 [Gating] SW mode calibration
4062 18:05:39.451656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4063 18:05:39.454939 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4064 18:05:39.461175 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 18:05:39.464442 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 18:05:39.468051 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 18:05:39.474980 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 1)
4068 18:05:39.477422 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4069 18:05:39.481130 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 18:05:39.487643 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 18:05:39.491238 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 18:05:39.497735 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 18:05:39.500860 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 18:05:39.503853 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 18:05:39.507900 0 10 12 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (0 0)
4076 18:05:39.514598 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4077 18:05:39.517787 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 18:05:39.520945 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 18:05:39.527856 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 18:05:39.530910 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 18:05:39.534238 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 18:05:39.540851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 18:05:39.544226 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4084 18:05:39.547631 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4085 18:05:39.554039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 18:05:39.557231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 18:05:39.560474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 18:05:39.567432 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 18:05:39.570507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 18:05:39.573528 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 18:05:39.580403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 18:05:39.583613 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 18:05:39.587187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 18:05:39.593429 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 18:05:39.596724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 18:05:39.599897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 18:05:39.607133 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 18:05:39.610031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 18:05:39.613393 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4100 18:05:39.620330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4101 18:05:39.623734 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 18:05:39.626972 Total UI for P1: 0, mck2ui 16
4103 18:05:39.630590 best dqsien dly found for B0: ( 0, 13, 14)
4104 18:05:39.633718 Total UI for P1: 0, mck2ui 16
4105 18:05:39.637101 best dqsien dly found for B1: ( 0, 13, 16)
4106 18:05:39.640080 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4107 18:05:39.643665 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4108 18:05:39.644256
4109 18:05:39.647077 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4110 18:05:39.650049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4111 18:05:39.653444 [Gating] SW calibration Done
4112 18:05:39.654032 ==
4113 18:05:39.656961 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 18:05:39.660770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 18:05:39.663131 ==
4116 18:05:39.663611 RX Vref Scan: 0
4117 18:05:39.663999
4118 18:05:39.666894 RX Vref 0 -> 0, step: 1
4119 18:05:39.667380
4120 18:05:39.670098 RX Delay -230 -> 252, step: 16
4121 18:05:39.673491 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4122 18:05:39.676627 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4123 18:05:39.680068 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4124 18:05:39.686365 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4125 18:05:39.689979 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4126 18:05:39.693251 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4127 18:05:39.696625 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4128 18:05:39.700098 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4129 18:05:39.706779 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4130 18:05:39.709848 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4131 18:05:39.713039 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4132 18:05:39.716666 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4133 18:05:39.723502 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4134 18:05:39.726782 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4135 18:05:39.729908 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4136 18:05:39.733202 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4137 18:05:39.733689 ==
4138 18:05:39.736919 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 18:05:39.743373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 18:05:39.743859 ==
4141 18:05:39.744366 DQS Delay:
4142 18:05:39.744898 DQS0 = 0, DQS1 = 0
4143 18:05:39.746453 DQM Delay:
4144 18:05:39.746951 DQM0 = 51, DQM1 = 39
4145 18:05:39.750002 DQ Delay:
4146 18:05:39.753283 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4147 18:05:39.753766 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4148 18:05:39.756635 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4149 18:05:39.762920 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4150 18:05:39.763489
4151 18:05:39.764064
4152 18:05:39.764572 ==
4153 18:05:39.766209 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 18:05:39.770017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 18:05:39.770769 ==
4156 18:05:39.771386
4157 18:05:39.771806
4158 18:05:39.773517 TX Vref Scan disable
4159 18:05:39.774272 == TX Byte 0 ==
4160 18:05:39.779874 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4161 18:05:39.782948 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4162 18:05:39.783475 == TX Byte 1 ==
4163 18:05:39.789783 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4164 18:05:39.793083 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4165 18:05:39.793544 ==
4166 18:05:39.796048 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 18:05:39.799875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 18:05:39.800329 ==
4169 18:05:39.800921
4170 18:05:39.801345
4171 18:05:39.802768 TX Vref Scan disable
4172 18:05:39.806292 == TX Byte 0 ==
4173 18:05:39.809521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4174 18:05:39.816420 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4175 18:05:39.816923 == TX Byte 1 ==
4176 18:05:39.819644 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4177 18:05:39.826815 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4178 18:05:39.827352
4179 18:05:39.827700 [DATLAT]
4180 18:05:39.828018 Freq=600, CH0 RK0
4181 18:05:39.828328
4182 18:05:39.829765 DATLAT Default: 0x9
4183 18:05:39.830208 0, 0xFFFF, sum = 0
4184 18:05:39.832978 1, 0xFFFF, sum = 0
4185 18:05:39.836315 2, 0xFFFF, sum = 0
4186 18:05:39.836891 3, 0xFFFF, sum = 0
4187 18:05:39.839855 4, 0xFFFF, sum = 0
4188 18:05:39.840294 5, 0xFFFF, sum = 0
4189 18:05:39.842648 6, 0xFFFF, sum = 0
4190 18:05:39.843083 7, 0xFFFF, sum = 0
4191 18:05:39.846062 8, 0x0, sum = 1
4192 18:05:39.846581 9, 0x0, sum = 2
4193 18:05:39.846938 10, 0x0, sum = 3
4194 18:05:39.849197 11, 0x0, sum = 4
4195 18:05:39.849634 best_step = 9
4196 18:05:39.849980
4197 18:05:39.850297 ==
4198 18:05:39.852746 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 18:05:39.859678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 18:05:39.860264 ==
4201 18:05:39.860709 RX Vref Scan: 1
4202 18:05:39.861087
4203 18:05:39.862796 RX Vref 0 -> 0, step: 1
4204 18:05:39.863267
4205 18:05:39.865952 RX Delay -179 -> 252, step: 8
4206 18:05:39.866437
4207 18:05:39.869123 Set Vref, RX VrefLevel [Byte0]: 57
4208 18:05:39.872920 [Byte1]: 50
4209 18:05:39.873403
4210 18:05:39.876651 Final RX Vref Byte 0 = 57 to rank0
4211 18:05:39.879053 Final RX Vref Byte 1 = 50 to rank0
4212 18:05:39.882839 Final RX Vref Byte 0 = 57 to rank1
4213 18:05:39.885869 Final RX Vref Byte 1 = 50 to rank1==
4214 18:05:39.889365 Dram Type= 6, Freq= 0, CH_0, rank 0
4215 18:05:39.892498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 18:05:39.893214 ==
4217 18:05:39.895559 DQS Delay:
4218 18:05:39.896256 DQS0 = 0, DQS1 = 0
4219 18:05:39.899147 DQM Delay:
4220 18:05:39.899741 DQM0 = 49, DQM1 = 40
4221 18:05:39.900306 DQ Delay:
4222 18:05:39.902486 DQ0 =48, DQ1 =52, DQ2 =44, DQ3 =44
4223 18:05:39.905951 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4224 18:05:39.909289 DQ8 =36, DQ9 =28, DQ10 =36, DQ11 =36
4225 18:05:39.912404 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4226 18:05:39.912868
4227 18:05:39.913325
4228 18:05:39.922364 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4229 18:05:39.926137 CH0 RK0: MR19=808, MR18=5D57
4230 18:05:39.932666 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4231 18:05:39.933209
4232 18:05:39.935979 ----->DramcWriteLeveling(PI) begin...
4233 18:05:39.936746 ==
4234 18:05:39.939097 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 18:05:39.942219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 18:05:39.942660 ==
4237 18:05:39.945651 Write leveling (Byte 0): 33 => 33
4238 18:05:39.948786 Write leveling (Byte 1): 30 => 30
4239 18:05:39.952047 DramcWriteLeveling(PI) end<-----
4240 18:05:39.952606
4241 18:05:39.952963 ==
4242 18:05:39.955464 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 18:05:39.958996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 18:05:39.959480 ==
4245 18:05:39.962361 [Gating] SW mode calibration
4246 18:05:39.968812 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4247 18:05:39.975299 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4248 18:05:39.979136 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 18:05:39.982283 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 18:05:39.988892 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 18:05:39.992588 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 1)
4252 18:05:39.995661 0 9 16 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
4253 18:05:40.002441 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 18:05:40.005583 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 18:05:40.008753 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 18:05:40.015583 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 18:05:40.019178 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 18:05:40.022316 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 18:05:40.025237 0 10 12 | B1->B0 | 3131 3333 | 0 1 | (1 1) (0 0)
4260 18:05:40.032189 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 18:05:40.035425 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 18:05:40.039035 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 18:05:40.045260 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 18:05:40.048803 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 18:05:40.052213 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 18:05:40.058657 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 18:05:40.061808 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 18:05:40.065479 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 18:05:40.072360 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 18:05:40.075417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 18:05:40.078587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 18:05:40.085277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 18:05:40.088807 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 18:05:40.092312 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 18:05:40.098343 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 18:05:40.101928 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 18:05:40.105432 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 18:05:40.112252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 18:05:40.115260 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 18:05:40.118779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 18:05:40.125240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 18:05:40.128709 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 18:05:40.131823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4284 18:05:40.135190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 18:05:40.138431 Total UI for P1: 0, mck2ui 16
4286 18:05:40.141689 best dqsien dly found for B0: ( 0, 13, 12)
4287 18:05:40.145361 Total UI for P1: 0, mck2ui 16
4288 18:05:40.148642 best dqsien dly found for B1: ( 0, 13, 14)
4289 18:05:40.152120 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4290 18:05:40.158336 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4291 18:05:40.158913
4292 18:05:40.161975 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 18:05:40.165245 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4294 18:05:40.168282 [Gating] SW calibration Done
4295 18:05:40.168731 ==
4296 18:05:40.171578 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 18:05:40.174723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 18:05:40.175153 ==
4299 18:05:40.178142 RX Vref Scan: 0
4300 18:05:40.178604
4301 18:05:40.179088 RX Vref 0 -> 0, step: 1
4302 18:05:40.179428
4303 18:05:40.181760 RX Delay -230 -> 252, step: 16
4304 18:05:40.185060 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4305 18:05:40.191595 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4306 18:05:40.194908 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4307 18:05:40.198554 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4308 18:05:40.201739 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4309 18:05:40.204771 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4310 18:05:40.211713 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4311 18:05:40.214727 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4312 18:05:40.218161 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4313 18:05:40.221960 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4314 18:05:40.228442 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4315 18:05:40.231583 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4316 18:05:40.234678 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4317 18:05:40.238316 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4318 18:05:40.244911 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4319 18:05:40.248093 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4320 18:05:40.248620 ==
4321 18:05:40.251322 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 18:05:40.254468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 18:05:40.254958 ==
4324 18:05:40.257879 DQS Delay:
4325 18:05:40.258341 DQS0 = 0, DQS1 = 0
4326 18:05:40.258695 DQM Delay:
4327 18:05:40.261184 DQM0 = 50, DQM1 = 44
4328 18:05:40.261620 DQ Delay:
4329 18:05:40.264400 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4330 18:05:40.267604 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4331 18:05:40.271079 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4332 18:05:40.274384 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4333 18:05:40.274874
4334 18:05:40.275229
4335 18:05:40.275611 ==
4336 18:05:40.277597 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 18:05:40.284111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 18:05:40.284725 ==
4339 18:05:40.285432
4340 18:05:40.285940
4341 18:05:40.286520 TX Vref Scan disable
4342 18:05:40.287824 == TX Byte 0 ==
4343 18:05:40.291869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4344 18:05:40.298359 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4345 18:05:40.298820 == TX Byte 1 ==
4346 18:05:40.301720 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4347 18:05:40.308053 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4348 18:05:40.308495 ==
4349 18:05:40.311121 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 18:05:40.314707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 18:05:40.315179 ==
4352 18:05:40.315539
4353 18:05:40.315856
4354 18:05:40.318239 TX Vref Scan disable
4355 18:05:40.321391 == TX Byte 0 ==
4356 18:05:40.324607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4357 18:05:40.327317 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4358 18:05:40.331127 == TX Byte 1 ==
4359 18:05:40.334392 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4360 18:05:40.337379 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4361 18:05:40.337461
4362 18:05:40.337527 [DATLAT]
4363 18:05:40.341104 Freq=600, CH0 RK1
4364 18:05:40.341186
4365 18:05:40.341251 DATLAT Default: 0x9
4366 18:05:40.344263 0, 0xFFFF, sum = 0
4367 18:05:40.347492 1, 0xFFFF, sum = 0
4368 18:05:40.347575 2, 0xFFFF, sum = 0
4369 18:05:40.350788 3, 0xFFFF, sum = 0
4370 18:05:40.350889 4, 0xFFFF, sum = 0
4371 18:05:40.354057 5, 0xFFFF, sum = 0
4372 18:05:40.354140 6, 0xFFFF, sum = 0
4373 18:05:40.357330 7, 0xFFFF, sum = 0
4374 18:05:40.357413 8, 0x0, sum = 1
4375 18:05:40.360592 9, 0x0, sum = 2
4376 18:05:40.360675 10, 0x0, sum = 3
4377 18:05:40.360741 11, 0x0, sum = 4
4378 18:05:40.364016 best_step = 9
4379 18:05:40.364103
4380 18:05:40.364172 ==
4381 18:05:40.367415 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 18:05:40.370691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 18:05:40.370785 ==
4384 18:05:40.373954 RX Vref Scan: 0
4385 18:05:40.374055
4386 18:05:40.374135 RX Vref 0 -> 0, step: 1
4387 18:05:40.377392
4388 18:05:40.377504 RX Delay -163 -> 252, step: 8
4389 18:05:40.384716 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4390 18:05:40.387971 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4391 18:05:40.391386 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4392 18:05:40.394612 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4393 18:05:40.401758 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4394 18:05:40.405096 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4395 18:05:40.408436 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4396 18:05:40.411618 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4397 18:05:40.414873 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4398 18:05:40.421544 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4399 18:05:40.424951 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4400 18:05:40.428077 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4401 18:05:40.431719 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4402 18:05:40.438152 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4403 18:05:40.441334 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4404 18:05:40.444924 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4405 18:05:40.445344 ==
4406 18:05:40.448086 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 18:05:40.451286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 18:05:40.451769 ==
4409 18:05:40.454473 DQS Delay:
4410 18:05:40.454891 DQS0 = 0, DQS1 = 0
4411 18:05:40.457885 DQM Delay:
4412 18:05:40.458303 DQM0 = 47, DQM1 = 39
4413 18:05:40.458636 DQ Delay:
4414 18:05:40.461074 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4415 18:05:40.464283 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4416 18:05:40.467973 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4417 18:05:40.471239 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4418 18:05:40.471668
4419 18:05:40.472054
4420 18:05:40.481369 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4421 18:05:40.484071 CH0 RK1: MR19=808, MR18=6532
4422 18:05:40.491107 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4423 18:05:40.491533 [RxdqsGatingPostProcess] freq 600
4424 18:05:40.497618 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 18:05:40.500899 Pre-setting of DQS Precalculation
4426 18:05:40.504146 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 18:05:40.507472 ==
4428 18:05:40.510773 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 18:05:40.514144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 18:05:40.514707 ==
4431 18:05:40.517605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 18:05:40.523993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4433 18:05:40.527973 [CA 0] Center 35 (5~66) winsize 62
4434 18:05:40.531153 [CA 1] Center 35 (5~66) winsize 62
4435 18:05:40.534750 [CA 2] Center 34 (4~65) winsize 62
4436 18:05:40.537866 [CA 3] Center 33 (3~64) winsize 62
4437 18:05:40.541063 [CA 4] Center 34 (3~65) winsize 63
4438 18:05:40.544365 [CA 5] Center 33 (3~64) winsize 62
4439 18:05:40.544825
4440 18:05:40.547929 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4441 18:05:40.548355
4442 18:05:40.551120 [CATrainingPosCal] consider 1 rank data
4443 18:05:40.554531 u2DelayCellTimex100 = 270/100 ps
4444 18:05:40.557662 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 18:05:40.561270 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 18:05:40.567623 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 18:05:40.571047 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4448 18:05:40.574421 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4449 18:05:40.577654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 18:05:40.578082
4451 18:05:40.581238 CA PerBit enable=1, Macro0, CA PI delay=33
4452 18:05:40.581667
4453 18:05:40.584404 [CBTSetCACLKResult] CA Dly = 33
4454 18:05:40.584874 CS Dly: 4 (0~35)
4455 18:05:40.585220 ==
4456 18:05:40.587642 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 18:05:40.594668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 18:05:40.595144 ==
4459 18:05:40.597933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 18:05:40.604487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4461 18:05:40.607697 [CA 0] Center 35 (5~66) winsize 62
4462 18:05:40.611035 [CA 1] Center 35 (5~66) winsize 62
4463 18:05:40.614416 [CA 2] Center 34 (4~65) winsize 62
4464 18:05:40.617665 [CA 3] Center 34 (4~64) winsize 61
4465 18:05:40.621351 [CA 4] Center 34 (4~65) winsize 62
4466 18:05:40.624418 [CA 5] Center 34 (4~64) winsize 61
4467 18:05:40.624874
4468 18:05:40.628050 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4469 18:05:40.628476
4470 18:05:40.631067 [CATrainingPosCal] consider 2 rank data
4471 18:05:40.634585 u2DelayCellTimex100 = 270/100 ps
4472 18:05:40.637755 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4473 18:05:40.640824 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4474 18:05:40.647850 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4475 18:05:40.650974 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4476 18:05:40.654386 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4477 18:05:40.657670 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4478 18:05:40.658098
4479 18:05:40.661135 CA PerBit enable=1, Macro0, CA PI delay=34
4480 18:05:40.661561
4481 18:05:40.664455 [CBTSetCACLKResult] CA Dly = 34
4482 18:05:40.664918 CS Dly: 5 (0~37)
4483 18:05:40.665262
4484 18:05:40.667675 ----->DramcWriteLeveling(PI) begin...
4485 18:05:40.671350 ==
4486 18:05:40.674649 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 18:05:40.677765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 18:05:40.678308 ==
4489 18:05:40.680799 Write leveling (Byte 0): 27 => 27
4490 18:05:40.684432 Write leveling (Byte 1): 29 => 29
4491 18:05:40.687451 DramcWriteLeveling(PI) end<-----
4492 18:05:40.687879
4493 18:05:40.688215 ==
4494 18:05:40.691234 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 18:05:40.694275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 18:05:40.694706 ==
4497 18:05:40.697747 [Gating] SW mode calibration
4498 18:05:40.704181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 18:05:40.710840 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 18:05:40.713904 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 18:05:40.717172 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 18:05:40.724123 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 18:05:40.727282 0 9 12 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (1 1)
4504 18:05:40.730405 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 18:05:40.737245 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 18:05:40.740671 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 18:05:40.743792 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 18:05:40.747478 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 18:05:40.753850 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 18:05:40.757543 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4511 18:05:40.760705 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
4512 18:05:40.767051 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 18:05:40.770822 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 18:05:40.774074 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 18:05:40.780650 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 18:05:40.783859 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 18:05:40.787506 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 18:05:40.793516 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 18:05:40.797112 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4520 18:05:40.800415 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 18:05:40.807333 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 18:05:40.811143 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 18:05:40.813893 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 18:05:40.820635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 18:05:40.823823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 18:05:40.827169 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 18:05:40.833653 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 18:05:40.837143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 18:05:40.840334 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 18:05:40.846777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 18:05:40.850327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 18:05:40.853495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 18:05:40.856703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 18:05:40.864021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 18:05:40.866709 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4536 18:05:40.870432 Total UI for P1: 0, mck2ui 16
4537 18:05:40.873437 best dqsien dly found for B0: ( 0, 13, 10)
4538 18:05:40.876741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 18:05:40.879917 Total UI for P1: 0, mck2ui 16
4540 18:05:40.883249 best dqsien dly found for B1: ( 0, 13, 12)
4541 18:05:40.886662 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4542 18:05:40.893124 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4543 18:05:40.893823
4544 18:05:40.896792 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4545 18:05:40.899818 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4546 18:05:40.903339 [Gating] SW calibration Done
4547 18:05:40.903805 ==
4548 18:05:40.906676 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 18:05:40.910011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 18:05:40.910449 ==
4551 18:05:40.913227 RX Vref Scan: 0
4552 18:05:40.913662
4553 18:05:40.914011 RX Vref 0 -> 0, step: 1
4554 18:05:40.914453
4555 18:05:40.916587 RX Delay -230 -> 252, step: 16
4556 18:05:40.919736 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4557 18:05:40.926310 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4558 18:05:40.929547 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4559 18:05:40.932966 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4560 18:05:40.936677 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4561 18:05:40.943132 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4562 18:05:40.946103 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4563 18:05:40.949718 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4564 18:05:40.952915 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4565 18:05:40.956089 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4566 18:05:40.962661 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4567 18:05:40.966151 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4568 18:05:40.969385 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4569 18:05:40.973456 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4570 18:05:40.979903 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4571 18:05:40.983173 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4572 18:05:40.983758 ==
4573 18:05:40.986577 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 18:05:40.989583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 18:05:40.990063 ==
4576 18:05:40.992783 DQS Delay:
4577 18:05:40.993446 DQS0 = 0, DQS1 = 0
4578 18:05:40.995926 DQM Delay:
4579 18:05:40.996589 DQM0 = 50, DQM1 = 39
4580 18:05:40.997119 DQ Delay:
4581 18:05:40.999262 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4582 18:05:41.002580 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4583 18:05:41.006063 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =33
4584 18:05:41.009492 DQ12 =57, DQ13 =41, DQ14 =41, DQ15 =41
4585 18:05:41.009966
4586 18:05:41.010339
4587 18:05:41.010689 ==
4588 18:05:41.012835 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 18:05:41.019669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 18:05:41.020249 ==
4591 18:05:41.020679
4592 18:05:41.021043
4593 18:05:41.021377 TX Vref Scan disable
4594 18:05:41.023229 == TX Byte 0 ==
4595 18:05:41.026511 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4596 18:05:41.033139 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4597 18:05:41.033715 == TX Byte 1 ==
4598 18:05:41.036506 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4599 18:05:41.043170 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4600 18:05:41.043753 ==
4601 18:05:41.046424 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 18:05:41.049778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 18:05:41.050363 ==
4604 18:05:41.050860
4605 18:05:41.051227
4606 18:05:41.052830 TX Vref Scan disable
4607 18:05:41.056275 == TX Byte 0 ==
4608 18:05:41.059373 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4609 18:05:41.062635 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4610 18:05:41.065814 == TX Byte 1 ==
4611 18:05:41.069594 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4612 18:05:41.072923 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4613 18:05:41.073509
4614 18:05:41.073894 [DATLAT]
4615 18:05:41.075901 Freq=600, CH1 RK0
4616 18:05:41.076380
4617 18:05:41.076803 DATLAT Default: 0x9
4618 18:05:41.079299 0, 0xFFFF, sum = 0
4619 18:05:41.082734 1, 0xFFFF, sum = 0
4620 18:05:41.083220 2, 0xFFFF, sum = 0
4621 18:05:41.086721 3, 0xFFFF, sum = 0
4622 18:05:41.087301 4, 0xFFFF, sum = 0
4623 18:05:41.089836 5, 0xFFFF, sum = 0
4624 18:05:41.090514 6, 0xFFFF, sum = 0
4625 18:05:41.093010 7, 0xFFFF, sum = 0
4626 18:05:41.093497 8, 0x0, sum = 1
4627 18:05:41.093885 9, 0x0, sum = 2
4628 18:05:41.096669 10, 0x0, sum = 3
4629 18:05:41.097254 11, 0x0, sum = 4
4630 18:05:41.099534 best_step = 9
4631 18:05:41.100013
4632 18:05:41.100393 ==
4633 18:05:41.102651 Dram Type= 6, Freq= 0, CH_1, rank 0
4634 18:05:41.106230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 18:05:41.106808 ==
4636 18:05:41.109913 RX Vref Scan: 1
4637 18:05:41.110489
4638 18:05:41.110881 RX Vref 0 -> 0, step: 1
4639 18:05:41.111245
4640 18:05:41.112850 RX Delay -179 -> 252, step: 8
4641 18:05:41.113331
4642 18:05:41.116232 Set Vref, RX VrefLevel [Byte0]: 51
4643 18:05:41.119775 [Byte1]: 49
4644 18:05:41.123618
4645 18:05:41.124194 Final RX Vref Byte 0 = 51 to rank0
4646 18:05:41.126698 Final RX Vref Byte 1 = 49 to rank0
4647 18:05:41.130203 Final RX Vref Byte 0 = 51 to rank1
4648 18:05:41.133360 Final RX Vref Byte 1 = 49 to rank1==
4649 18:05:41.136933 Dram Type= 6, Freq= 0, CH_1, rank 0
4650 18:05:41.143806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 18:05:41.144389 ==
4652 18:05:41.144835 DQS Delay:
4653 18:05:41.145200 DQS0 = 0, DQS1 = 0
4654 18:05:41.146828 DQM Delay:
4655 18:05:41.147306 DQM0 = 48, DQM1 = 40
4656 18:05:41.150346 DQ Delay:
4657 18:05:41.153254 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4658 18:05:41.157106 DQ4 =48, DQ5 =56, DQ6 =60, DQ7 =44
4659 18:05:41.157736 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =36
4660 18:05:41.163220 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4661 18:05:41.163787
4662 18:05:41.164172
4663 18:05:41.170502 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4664 18:05:41.173589 CH1 RK0: MR19=808, MR18=4E74
4665 18:05:41.179867 CH1_RK0: MR19=0x808, MR18=0x4E74, DQSOSC=388, MR23=63, INC=174, DEC=116
4666 18:05:41.180441
4667 18:05:41.183504 ----->DramcWriteLeveling(PI) begin...
4668 18:05:41.184059 ==
4669 18:05:41.187031 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 18:05:41.189913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 18:05:41.190403 ==
4672 18:05:41.193068 Write leveling (Byte 0): 29 => 29
4673 18:05:41.196753 Write leveling (Byte 1): 29 => 29
4674 18:05:41.199586 DramcWriteLeveling(PI) end<-----
4675 18:05:41.200068
4676 18:05:41.200485 ==
4677 18:05:41.203671 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 18:05:41.206956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 18:05:41.207535 ==
4680 18:05:41.210125 [Gating] SW mode calibration
4681 18:05:41.216538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4682 18:05:41.223697 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4683 18:05:41.226626 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4684 18:05:41.230088 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 18:05:41.236715 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4686 18:05:41.239856 0 9 12 | B1->B0 | 2727 3030 | 1 0 | (0 0) (0 1)
4687 18:05:41.243163 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4688 18:05:41.249763 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 18:05:41.252925 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 18:05:41.256308 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 18:05:41.263118 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 18:05:41.266483 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 18:05:41.269499 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4694 18:05:41.276497 0 10 12 | B1->B0 | 3c3c 2f2f | 0 0 | (0 0) (0 0)
4695 18:05:41.279687 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4696 18:05:41.282716 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 18:05:41.289457 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 18:05:41.292489 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 18:05:41.295823 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 18:05:41.302485 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 18:05:41.305770 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 18:05:41.309156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4703 18:05:41.315464 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 18:05:41.319320 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 18:05:41.322311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 18:05:41.329336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 18:05:41.332680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 18:05:41.335901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 18:05:41.342289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 18:05:41.345401 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 18:05:41.348678 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 18:05:41.355725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 18:05:41.358916 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 18:05:41.362100 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 18:05:41.368911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 18:05:41.371945 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 18:05:41.375383 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 18:05:41.381790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4719 18:05:41.382222 Total UI for P1: 0, mck2ui 16
4720 18:05:41.388585 best dqsien dly found for B1: ( 0, 13, 10)
4721 18:05:41.391713 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 18:05:41.395499 Total UI for P1: 0, mck2ui 16
4723 18:05:41.398704 best dqsien dly found for B0: ( 0, 13, 12)
4724 18:05:41.402034 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4725 18:05:41.405607 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4726 18:05:41.406141
4727 18:05:41.408450 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4728 18:05:41.411911 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4729 18:05:41.415393 [Gating] SW calibration Done
4730 18:05:41.415924 ==
4731 18:05:41.418434 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 18:05:41.421478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 18:05:41.425064 ==
4734 18:05:41.425534 RX Vref Scan: 0
4735 18:05:41.426058
4736 18:05:41.428095 RX Vref 0 -> 0, step: 1
4737 18:05:41.428752
4738 18:05:41.431320 RX Delay -230 -> 252, step: 16
4739 18:05:41.435104 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4740 18:05:41.438445 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4741 18:05:41.441134 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4742 18:05:41.448304 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4743 18:05:41.451440 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4744 18:05:41.454606 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4745 18:05:41.457818 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4746 18:05:41.461190 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4747 18:05:41.468019 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4748 18:05:41.471160 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4749 18:05:41.474733 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4750 18:05:41.477992 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4751 18:05:41.484507 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4752 18:05:41.487667 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4753 18:05:41.490931 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4754 18:05:41.494515 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4755 18:05:41.495098 ==
4756 18:05:41.497723 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 18:05:41.504591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 18:05:41.505068 ==
4759 18:05:41.505422 DQS Delay:
4760 18:05:41.507728 DQS0 = 0, DQS1 = 0
4761 18:05:41.508205 DQM Delay:
4762 18:05:41.508750 DQM0 = 50, DQM1 = 46
4763 18:05:41.511008 DQ Delay:
4764 18:05:41.514296 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4765 18:05:41.517648 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4766 18:05:41.521141 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4767 18:05:41.524412 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4768 18:05:41.525072
4769 18:05:41.525705
4770 18:05:41.526283 ==
4771 18:05:41.527743 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 18:05:41.530845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 18:05:41.531419 ==
4774 18:05:41.531909
4775 18:05:41.532375
4776 18:05:41.534490 TX Vref Scan disable
4777 18:05:41.537926 == TX Byte 0 ==
4778 18:05:41.541074 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4779 18:05:41.544357 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4780 18:05:41.547685 == TX Byte 1 ==
4781 18:05:41.550763 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4782 18:05:41.554483 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4783 18:05:41.555102 ==
4784 18:05:41.557641 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 18:05:41.560792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 18:05:41.561257 ==
4787 18:05:41.563837
4788 18:05:41.564408
4789 18:05:41.564850 TX Vref Scan disable
4790 18:05:41.567726 == TX Byte 0 ==
4791 18:05:41.571172 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4792 18:05:41.574256 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4793 18:05:41.578044 == TX Byte 1 ==
4794 18:05:41.581027 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 18:05:41.584521 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 18:05:41.587858
4797 18:05:41.588286 [DATLAT]
4798 18:05:41.588655 Freq=600, CH1 RK1
4799 18:05:41.588983
4800 18:05:41.590862 DATLAT Default: 0x9
4801 18:05:41.591285 0, 0xFFFF, sum = 0
4802 18:05:41.594622 1, 0xFFFF, sum = 0
4803 18:05:41.595079 2, 0xFFFF, sum = 0
4804 18:05:41.597650 3, 0xFFFF, sum = 0
4805 18:05:41.598096 4, 0xFFFF, sum = 0
4806 18:05:41.601348 5, 0xFFFF, sum = 0
4807 18:05:41.604632 6, 0xFFFF, sum = 0
4808 18:05:41.605128 7, 0xFFFF, sum = 0
4809 18:05:41.605578 8, 0x0, sum = 1
4810 18:05:41.607893 9, 0x0, sum = 2
4811 18:05:41.608339 10, 0x0, sum = 3
4812 18:05:41.611128 11, 0x0, sum = 4
4813 18:05:41.611576 best_step = 9
4814 18:05:41.612017
4815 18:05:41.612529 ==
4816 18:05:41.614302 Dram Type= 6, Freq= 0, CH_1, rank 1
4817 18:05:41.620845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4818 18:05:41.621291 ==
4819 18:05:41.621827 RX Vref Scan: 0
4820 18:05:41.622253
4821 18:05:41.624226 RX Vref 0 -> 0, step: 1
4822 18:05:41.624716
4823 18:05:41.627834 RX Delay -163 -> 252, step: 8
4824 18:05:41.631181 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4825 18:05:41.637679 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4826 18:05:41.640975 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4827 18:05:41.644262 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4828 18:05:41.647488 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4829 18:05:41.650728 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4830 18:05:41.657651 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4831 18:05:41.660847 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4832 18:05:41.664175 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4833 18:05:41.667282 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4834 18:05:41.670580 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4835 18:05:41.677415 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4836 18:05:41.680632 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4837 18:05:41.684124 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4838 18:05:41.687207 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4839 18:05:41.694107 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4840 18:05:41.694558 ==
4841 18:05:41.697170 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 18:05:41.700513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 18:05:41.701033 ==
4844 18:05:41.701520 DQS Delay:
4845 18:05:41.703629 DQS0 = 0, DQS1 = 0
4846 18:05:41.704028 DQM Delay:
4847 18:05:41.707096 DQM0 = 48, DQM1 = 42
4848 18:05:41.707555 DQ Delay:
4849 18:05:41.710635 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4850 18:05:41.714259 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4851 18:05:41.717413 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4852 18:05:41.720445 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4853 18:05:41.721032
4854 18:05:41.721454
4855 18:05:41.727320 [DQSOSCAuto] RK1, (LSB)MR18= 0x5319, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4856 18:05:41.730564 CH1 RK1: MR19=808, MR18=5319
4857 18:05:41.736950 CH1_RK1: MR19=0x808, MR18=0x5319, DQSOSC=394, MR23=63, INC=168, DEC=112
4858 18:05:41.740686 [RxdqsGatingPostProcess] freq 600
4859 18:05:41.747341 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4860 18:05:41.747815 Pre-setting of DQS Precalculation
4861 18:05:41.753992 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4862 18:05:41.760630 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4863 18:05:41.767298 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4864 18:05:41.767741
4865 18:05:41.768083
4866 18:05:41.770685 [Calibration Summary] 1200 Mbps
4867 18:05:41.773730 CH 0, Rank 0
4868 18:05:41.774154 SW Impedance : PASS
4869 18:05:41.776950 DUTY Scan : NO K
4870 18:05:41.777375 ZQ Calibration : PASS
4871 18:05:41.780419 Jitter Meter : NO K
4872 18:05:41.783582 CBT Training : PASS
4873 18:05:41.784008 Write leveling : PASS
4874 18:05:41.787337 RX DQS gating : PASS
4875 18:05:41.790193 RX DQ/DQS(RDDQC) : PASS
4876 18:05:41.790276 TX DQ/DQS : PASS
4877 18:05:41.793733 RX DATLAT : PASS
4878 18:05:41.796955 RX DQ/DQS(Engine): PASS
4879 18:05:41.797065 TX OE : NO K
4880 18:05:41.800045 All Pass.
4881 18:05:41.800147
4882 18:05:41.800238 CH 0, Rank 1
4883 18:05:41.803410 SW Impedance : PASS
4884 18:05:41.803510 DUTY Scan : NO K
4885 18:05:41.807081 ZQ Calibration : PASS
4886 18:05:41.810282 Jitter Meter : NO K
4887 18:05:41.810358 CBT Training : PASS
4888 18:05:41.813287 Write leveling : PASS
4889 18:05:41.816516 RX DQS gating : PASS
4890 18:05:41.816624 RX DQ/DQS(RDDQC) : PASS
4891 18:05:41.819948 TX DQ/DQS : PASS
4892 18:05:41.820020 RX DATLAT : PASS
4893 18:05:41.823651 RX DQ/DQS(Engine): PASS
4894 18:05:41.827000 TX OE : NO K
4895 18:05:41.827074 All Pass.
4896 18:05:41.827138
4897 18:05:41.827197 CH 1, Rank 0
4898 18:05:41.830216 SW Impedance : PASS
4899 18:05:41.833480 DUTY Scan : NO K
4900 18:05:41.833564 ZQ Calibration : PASS
4901 18:05:41.836663 Jitter Meter : NO K
4902 18:05:41.840104 CBT Training : PASS
4903 18:05:41.840187 Write leveling : PASS
4904 18:05:41.843312 RX DQS gating : PASS
4905 18:05:41.846451 RX DQ/DQS(RDDQC) : PASS
4906 18:05:41.846534 TX DQ/DQS : PASS
4907 18:05:41.849828 RX DATLAT : PASS
4908 18:05:41.853132 RX DQ/DQS(Engine): PASS
4909 18:05:41.853207 TX OE : NO K
4910 18:05:41.856319 All Pass.
4911 18:05:41.856422
4912 18:05:41.856521 CH 1, Rank 1
4913 18:05:41.859639 SW Impedance : PASS
4914 18:05:41.859711 DUTY Scan : NO K
4915 18:05:41.863092 ZQ Calibration : PASS
4916 18:05:41.866256 Jitter Meter : NO K
4917 18:05:41.866355 CBT Training : PASS
4918 18:05:41.869554 Write leveling : PASS
4919 18:05:41.872781 RX DQS gating : PASS
4920 18:05:41.872856 RX DQ/DQS(RDDQC) : PASS
4921 18:05:41.876245 TX DQ/DQS : PASS
4922 18:05:41.876318 RX DATLAT : PASS
4923 18:05:41.879465 RX DQ/DQS(Engine): PASS
4924 18:05:41.882647 TX OE : NO K
4925 18:05:41.882718 All Pass.
4926 18:05:41.882780
4927 18:05:41.885999 DramC Write-DBI off
4928 18:05:41.889741 PER_BANK_REFRESH: Hybrid Mode
4929 18:05:41.889826 TX_TRACKING: ON
4930 18:05:41.899526 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4931 18:05:41.902727 [FAST_K] Save calibration result to emmc
4932 18:05:41.906152 dramc_set_vcore_voltage set vcore to 662500
4933 18:05:41.909292 Read voltage for 933, 3
4934 18:05:41.909376 Vio18 = 0
4935 18:05:41.909444 Vcore = 662500
4936 18:05:41.909507 Vdram = 0
4937 18:05:41.912878 Vddq = 0
4938 18:05:41.912988 Vmddr = 0
4939 18:05:41.919206 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4940 18:05:41.922940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4941 18:05:41.926200 MEM_TYPE=3, freq_sel=17
4942 18:05:41.929368 sv_algorithm_assistance_LP4_1600
4943 18:05:41.932504 ============ PULL DRAM RESETB DOWN ============
4944 18:05:41.935960 ========== PULL DRAM RESETB DOWN end =========
4945 18:05:41.942393 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4946 18:05:41.945657 ===================================
4947 18:05:41.945742 LPDDR4 DRAM CONFIGURATION
4948 18:05:41.948806 ===================================
4949 18:05:41.952578 EX_ROW_EN[0] = 0x0
4950 18:05:41.955719 EX_ROW_EN[1] = 0x0
4951 18:05:41.955804 LP4Y_EN = 0x0
4952 18:05:41.958872 WORK_FSP = 0x0
4953 18:05:41.958956 WL = 0x3
4954 18:05:41.962118 RL = 0x3
4955 18:05:41.962202 BL = 0x2
4956 18:05:41.965403 RPST = 0x0
4957 18:05:41.965588 RD_PRE = 0x0
4958 18:05:41.968695 WR_PRE = 0x1
4959 18:05:41.968780 WR_PST = 0x0
4960 18:05:41.971893 DBI_WR = 0x0
4961 18:05:41.971978 DBI_RD = 0x0
4962 18:05:41.975181 OTF = 0x1
4963 18:05:41.979000 ===================================
4964 18:05:41.982316 ===================================
4965 18:05:41.982400 ANA top config
4966 18:05:41.985614 ===================================
4967 18:05:41.988869 DLL_ASYNC_EN = 0
4968 18:05:41.991950 ALL_SLAVE_EN = 1
4969 18:05:41.995599 NEW_RANK_MODE = 1
4970 18:05:41.995687 DLL_IDLE_MODE = 1
4971 18:05:41.998700 LP45_APHY_COMB_EN = 1
4972 18:05:42.001896 TX_ODT_DIS = 1
4973 18:05:42.005053 NEW_8X_MODE = 1
4974 18:05:42.008686 ===================================
4975 18:05:42.011893 ===================================
4976 18:05:42.015048 data_rate = 1866
4977 18:05:42.015132 CKR = 1
4978 18:05:42.018669 DQ_P2S_RATIO = 8
4979 18:05:42.021862 ===================================
4980 18:05:42.025131 CA_P2S_RATIO = 8
4981 18:05:42.028356 DQ_CA_OPEN = 0
4982 18:05:42.031638 DQ_SEMI_OPEN = 0
4983 18:05:42.034923 CA_SEMI_OPEN = 0
4984 18:05:42.035008 CA_FULL_RATE = 0
4985 18:05:42.038197 DQ_CKDIV4_EN = 1
4986 18:05:42.041712 CA_CKDIV4_EN = 1
4987 18:05:42.044915 CA_PREDIV_EN = 0
4988 18:05:42.048195 PH8_DLY = 0
4989 18:05:42.051333 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4990 18:05:42.051444 DQ_AAMCK_DIV = 4
4991 18:05:42.055106 CA_AAMCK_DIV = 4
4992 18:05:42.058255 CA_ADMCK_DIV = 4
4993 18:05:42.061517 DQ_TRACK_CA_EN = 0
4994 18:05:42.064789 CA_PICK = 933
4995 18:05:42.068137 CA_MCKIO = 933
4996 18:05:42.071398 MCKIO_SEMI = 0
4997 18:05:42.071482 PLL_FREQ = 3732
4998 18:05:42.074426 DQ_UI_PI_RATIO = 32
4999 18:05:42.077684 CA_UI_PI_RATIO = 0
5000 18:05:42.081486 ===================================
5001 18:05:42.084783 ===================================
5002 18:05:42.087704 memory_type:LPDDR4
5003 18:05:42.090877 GP_NUM : 10
5004 18:05:42.090960 SRAM_EN : 1
5005 18:05:42.094241 MD32_EN : 0
5006 18:05:42.097889 ===================================
5007 18:05:42.098000 [ANA_INIT] >>>>>>>>>>>>>>
5008 18:05:42.101066 <<<<<< [CONFIGURE PHASE]: ANA_TX
5009 18:05:42.104096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5010 18:05:42.107680 ===================================
5011 18:05:42.110802 data_rate = 1866,PCW = 0X8f00
5012 18:05:42.114107 ===================================
5013 18:05:42.117384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5014 18:05:42.123967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5015 18:05:42.130417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 18:05:42.133661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5017 18:05:42.137033 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5018 18:05:42.140781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5019 18:05:42.144128 [ANA_INIT] flow start
5020 18:05:42.144231 [ANA_INIT] PLL >>>>>>>>
5021 18:05:42.147496 [ANA_INIT] PLL <<<<<<<<
5022 18:05:42.150262 [ANA_INIT] MIDPI >>>>>>>>
5023 18:05:42.150335 [ANA_INIT] MIDPI <<<<<<<<
5024 18:05:42.154114 [ANA_INIT] DLL >>>>>>>>
5025 18:05:42.157205 [ANA_INIT] flow end
5026 18:05:42.160709 ============ LP4 DIFF to SE enter ============
5027 18:05:42.164036 ============ LP4 DIFF to SE exit ============
5028 18:05:42.166912 [ANA_INIT] <<<<<<<<<<<<<
5029 18:05:42.170176 [Flow] Enable top DCM control >>>>>
5030 18:05:42.173582 [Flow] Enable top DCM control <<<<<
5031 18:05:42.177220 Enable DLL master slave shuffle
5032 18:05:42.180579 ==============================================================
5033 18:05:42.183992 Gating Mode config
5034 18:05:42.190468 ==============================================================
5035 18:05:42.190552 Config description:
5036 18:05:42.199902 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5037 18:05:42.206803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5038 18:05:42.213517 SELPH_MODE 0: By rank 1: By Phase
5039 18:05:42.216676 ==============================================================
5040 18:05:42.220029 GAT_TRACK_EN = 1
5041 18:05:42.223188 RX_GATING_MODE = 2
5042 18:05:42.227006 RX_GATING_TRACK_MODE = 2
5043 18:05:42.230279 SELPH_MODE = 1
5044 18:05:42.233381 PICG_EARLY_EN = 1
5045 18:05:42.236574 VALID_LAT_VALUE = 1
5046 18:05:42.240004 ==============================================================
5047 18:05:42.243291 Enter into Gating configuration >>>>
5048 18:05:42.246666 Exit from Gating configuration <<<<
5049 18:05:42.250020 Enter into DVFS_PRE_config >>>>>
5050 18:05:42.263460 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5051 18:05:42.266534 Exit from DVFS_PRE_config <<<<<
5052 18:05:42.270275 Enter into PICG configuration >>>>
5053 18:05:42.270361 Exit from PICG configuration <<<<
5054 18:05:42.273520 [RX_INPUT] configuration >>>>>
5055 18:05:42.276658 [RX_INPUT] configuration <<<<<
5056 18:05:42.282939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5057 18:05:42.286743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5058 18:05:42.293332 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5059 18:05:42.299971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5060 18:05:42.306377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 18:05:42.313081 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 18:05:42.316368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5063 18:05:42.319535 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5064 18:05:42.322647 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5065 18:05:42.329784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5066 18:05:42.332853 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5067 18:05:42.335812 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 18:05:42.339274 ===================================
5069 18:05:42.342613 LPDDR4 DRAM CONFIGURATION
5070 18:05:42.345934 ===================================
5071 18:05:42.349152 EX_ROW_EN[0] = 0x0
5072 18:05:42.349247 EX_ROW_EN[1] = 0x0
5073 18:05:42.352582 LP4Y_EN = 0x0
5074 18:05:42.352667 WORK_FSP = 0x0
5075 18:05:42.355650 WL = 0x3
5076 18:05:42.355735 RL = 0x3
5077 18:05:42.359579 BL = 0x2
5078 18:05:42.359663 RPST = 0x0
5079 18:05:42.362324 RD_PRE = 0x0
5080 18:05:42.362409 WR_PRE = 0x1
5081 18:05:42.365986 WR_PST = 0x0
5082 18:05:42.366096 DBI_WR = 0x0
5083 18:05:42.369152 DBI_RD = 0x0
5084 18:05:42.369227 OTF = 0x1
5085 18:05:42.372743 ===================================
5086 18:05:42.379382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5087 18:05:42.382503 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5088 18:05:42.385891 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 18:05:42.389176 ===================================
5090 18:05:42.392402 LPDDR4 DRAM CONFIGURATION
5091 18:05:42.395623 ===================================
5092 18:05:42.399111 EX_ROW_EN[0] = 0x10
5093 18:05:42.399213 EX_ROW_EN[1] = 0x0
5094 18:05:42.402298 LP4Y_EN = 0x0
5095 18:05:42.402423 WORK_FSP = 0x0
5096 18:05:42.405577 WL = 0x3
5097 18:05:42.405649 RL = 0x3
5098 18:05:42.409301 BL = 0x2
5099 18:05:42.409385 RPST = 0x0
5100 18:05:42.412396 RD_PRE = 0x0
5101 18:05:42.412497 WR_PRE = 0x1
5102 18:05:42.415530 WR_PST = 0x0
5103 18:05:42.415615 DBI_WR = 0x0
5104 18:05:42.419231 DBI_RD = 0x0
5105 18:05:42.419317 OTF = 0x1
5106 18:05:42.422485 ===================================
5107 18:05:42.428889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5108 18:05:42.433808 nWR fixed to 30
5109 18:05:42.437113 [ModeRegInit_LP4] CH0 RK0
5110 18:05:42.437217 [ModeRegInit_LP4] CH0 RK1
5111 18:05:42.440369 [ModeRegInit_LP4] CH1 RK0
5112 18:05:42.443690 [ModeRegInit_LP4] CH1 RK1
5113 18:05:42.443766 match AC timing 9
5114 18:05:42.450247 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5115 18:05:42.453522 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5116 18:05:42.456925 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5117 18:05:42.463627 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5118 18:05:42.466732 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5119 18:05:42.466826 ==
5120 18:05:42.470037 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 18:05:42.473220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 18:05:42.473307 ==
5123 18:05:42.480024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 18:05:42.486441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 18:05:42.490287 [CA 0] Center 38 (7~69) winsize 63
5126 18:05:42.493551 [CA 1] Center 38 (8~69) winsize 62
5127 18:05:42.496329 [CA 2] Center 35 (5~66) winsize 62
5128 18:05:42.499615 [CA 3] Center 35 (5~66) winsize 62
5129 18:05:42.503390 [CA 4] Center 34 (4~65) winsize 62
5130 18:05:42.506683 [CA 5] Center 33 (3~64) winsize 62
5131 18:05:42.506767
5132 18:05:42.509942 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 18:05:42.510025
5134 18:05:42.513083 [CATrainingPosCal] consider 1 rank data
5135 18:05:42.516244 u2DelayCellTimex100 = 270/100 ps
5136 18:05:42.519805 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5137 18:05:42.523261 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5138 18:05:42.526466 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5139 18:05:42.529545 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5140 18:05:42.536327 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5141 18:05:42.539995 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5142 18:05:42.540078
5143 18:05:42.542731 CA PerBit enable=1, Macro0, CA PI delay=33
5144 18:05:42.542816
5145 18:05:42.546290 [CBTSetCACLKResult] CA Dly = 33
5146 18:05:42.546374 CS Dly: 7 (0~38)
5147 18:05:42.546440 ==
5148 18:05:42.549538 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 18:05:42.552712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 18:05:42.556079 ==
5151 18:05:42.559762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5152 18:05:42.566407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5153 18:05:42.569631 [CA 0] Center 38 (8~69) winsize 62
5154 18:05:42.572824 [CA 1] Center 38 (8~69) winsize 62
5155 18:05:42.576571 [CA 2] Center 36 (6~66) winsize 61
5156 18:05:42.579712 [CA 3] Center 35 (5~66) winsize 62
5157 18:05:42.582675 [CA 4] Center 34 (4~65) winsize 62
5158 18:05:42.586099 [CA 5] Center 34 (4~65) winsize 62
5159 18:05:42.586214
5160 18:05:42.589587 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5161 18:05:42.589796
5162 18:05:42.593014 [CATrainingPosCal] consider 2 rank data
5163 18:05:42.596381 u2DelayCellTimex100 = 270/100 ps
5164 18:05:42.599680 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5165 18:05:42.602881 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5166 18:05:42.606212 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5167 18:05:42.612656 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5168 18:05:42.616276 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5169 18:05:42.619362 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5170 18:05:42.619691
5171 18:05:42.622680 CA PerBit enable=1, Macro0, CA PI delay=34
5172 18:05:42.623038
5173 18:05:42.626297 [CBTSetCACLKResult] CA Dly = 34
5174 18:05:42.626699 CS Dly: 7 (0~39)
5175 18:05:42.627040
5176 18:05:42.629218 ----->DramcWriteLeveling(PI) begin...
5177 18:05:42.632968 ==
5178 18:05:42.633482 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 18:05:42.639400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 18:05:42.640002 ==
5181 18:05:42.642941 Write leveling (Byte 0): 32 => 32
5182 18:05:42.646009 Write leveling (Byte 1): 30 => 30
5183 18:05:42.649619 DramcWriteLeveling(PI) end<-----
5184 18:05:42.650054
5185 18:05:42.650401 ==
5186 18:05:42.652800 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 18:05:42.656230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 18:05:42.656810 ==
5189 18:05:42.659359 [Gating] SW mode calibration
5190 18:05:42.665806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5191 18:05:42.672604 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5192 18:05:42.675475 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5193 18:05:42.679190 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 18:05:42.685428 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 18:05:42.688855 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 18:05:42.692120 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 18:05:42.698733 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 18:05:42.701964 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5199 18:05:42.705233 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)
5200 18:05:42.711786 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5201 18:05:42.715025 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 18:05:42.718328 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 18:05:42.725343 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 18:05:42.728424 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 18:05:42.731558 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 18:05:42.735113 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5207 18:05:42.741893 0 15 28 | B1->B0 | 2b2b 4343 | 0 1 | (0 0) (0 0)
5208 18:05:42.744541 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 18:05:42.747855 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 18:05:42.754731 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 18:05:42.757814 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 18:05:42.761035 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 18:05:42.768058 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 18:05:42.771377 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5215 18:05:42.774678 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5216 18:05:42.781038 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5217 18:05:42.784183 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 18:05:42.787988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 18:05:42.794612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 18:05:42.797955 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 18:05:42.801232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 18:05:42.807759 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 18:05:42.811097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 18:05:42.814480 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 18:05:42.820792 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 18:05:42.824197 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 18:05:42.827428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 18:05:42.834456 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 18:05:42.837755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 18:05:42.840988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 18:05:42.847608 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5232 18:05:42.847689 Total UI for P1: 0, mck2ui 16
5233 18:05:42.853836 best dqsien dly found for B0: ( 1, 2, 26)
5234 18:05:42.857201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 18:05:42.861026 Total UI for P1: 0, mck2ui 16
5236 18:05:42.863738 best dqsien dly found for B1: ( 1, 2, 28)
5237 18:05:42.867054 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5238 18:05:42.870433 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5239 18:05:42.870505
5240 18:05:42.873802 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5241 18:05:42.877029 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5242 18:05:42.880407 [Gating] SW calibration Done
5243 18:05:42.880506 ==
5244 18:05:42.883695 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 18:05:42.886996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 18:05:42.890244 ==
5247 18:05:42.890342 RX Vref Scan: 0
5248 18:05:42.890431
5249 18:05:42.893978 RX Vref 0 -> 0, step: 1
5250 18:05:42.894076
5251 18:05:42.894165 RX Delay -80 -> 252, step: 8
5252 18:05:42.900438 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5253 18:05:42.904317 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5254 18:05:42.907463 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5255 18:05:42.910852 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5256 18:05:42.914196 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5257 18:05:42.920748 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5258 18:05:42.923922 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5259 18:05:42.927141 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5260 18:05:42.930405 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5261 18:05:42.934209 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5262 18:05:42.937564 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5263 18:05:42.943847 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5264 18:05:42.946878 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5265 18:05:42.950784 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5266 18:05:42.953621 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5267 18:05:42.957200 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5268 18:05:42.957299 ==
5269 18:05:42.960718 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 18:05:42.967243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 18:05:42.967341 ==
5272 18:05:42.967430 DQS Delay:
5273 18:05:42.967513 DQS0 = 0, DQS1 = 0
5274 18:05:42.970667 DQM Delay:
5275 18:05:42.970754 DQM0 = 106, DQM1 = 90
5276 18:05:42.973901 DQ Delay:
5277 18:05:42.977215 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5278 18:05:42.980393 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5279 18:05:42.983754 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5280 18:05:42.987028 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5281 18:05:42.987109
5282 18:05:42.987176
5283 18:05:42.987238 ==
5284 18:05:42.990341 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 18:05:42.993657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 18:05:42.993777 ==
5287 18:05:42.993874
5288 18:05:42.993970
5289 18:05:42.997008 TX Vref Scan disable
5290 18:05:43.000416 == TX Byte 0 ==
5291 18:05:43.003731 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5292 18:05:43.006955 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5293 18:05:43.010229 == TX Byte 1 ==
5294 18:05:43.013501 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5295 18:05:43.016839 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5296 18:05:43.016923 ==
5297 18:05:43.020187 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 18:05:43.023998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 18:05:43.026785 ==
5300 18:05:43.026869
5301 18:05:43.026935
5302 18:05:43.026996 TX Vref Scan disable
5303 18:05:43.030742 == TX Byte 0 ==
5304 18:05:43.033833 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5305 18:05:43.040440 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5306 18:05:43.040556 == TX Byte 1 ==
5307 18:05:43.043791 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5308 18:05:43.050480 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5309 18:05:43.050565
5310 18:05:43.050631 [DATLAT]
5311 18:05:43.050693 Freq=933, CH0 RK0
5312 18:05:43.050754
5313 18:05:43.053614 DATLAT Default: 0xd
5314 18:05:43.053699 0, 0xFFFF, sum = 0
5315 18:05:43.057249 1, 0xFFFF, sum = 0
5316 18:05:43.057334 2, 0xFFFF, sum = 0
5317 18:05:43.060440 3, 0xFFFF, sum = 0
5318 18:05:43.063675 4, 0xFFFF, sum = 0
5319 18:05:43.063760 5, 0xFFFF, sum = 0
5320 18:05:43.066871 6, 0xFFFF, sum = 0
5321 18:05:43.066956 7, 0xFFFF, sum = 0
5322 18:05:43.070186 8, 0xFFFF, sum = 0
5323 18:05:43.070271 9, 0xFFFF, sum = 0
5324 18:05:43.073395 10, 0x0, sum = 1
5325 18:05:43.073480 11, 0x0, sum = 2
5326 18:05:43.076750 12, 0x0, sum = 3
5327 18:05:43.076840 13, 0x0, sum = 4
5328 18:05:43.076913 best_step = 11
5329 18:05:43.076979
5330 18:05:43.080106 ==
5331 18:05:43.083519 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 18:05:43.086688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 18:05:43.086826 ==
5334 18:05:43.086954 RX Vref Scan: 1
5335 18:05:43.087076
5336 18:05:43.089962 RX Vref 0 -> 0, step: 1
5337 18:05:43.090113
5338 18:05:43.093282 RX Delay -53 -> 252, step: 4
5339 18:05:43.093420
5340 18:05:43.096473 Set Vref, RX VrefLevel [Byte0]: 57
5341 18:05:43.099739 [Byte1]: 50
5342 18:05:43.099823
5343 18:05:43.103521 Final RX Vref Byte 0 = 57 to rank0
5344 18:05:43.106811 Final RX Vref Byte 1 = 50 to rank0
5345 18:05:43.110009 Final RX Vref Byte 0 = 57 to rank1
5346 18:05:43.113377 Final RX Vref Byte 1 = 50 to rank1==
5347 18:05:43.116785 Dram Type= 6, Freq= 0, CH_0, rank 0
5348 18:05:43.120060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 18:05:43.123324 ==
5350 18:05:43.123415 DQS Delay:
5351 18:05:43.123482 DQS0 = 0, DQS1 = 0
5352 18:05:43.126726 DQM Delay:
5353 18:05:43.127159 DQM0 = 107, DQM1 = 92
5354 18:05:43.130088 DQ Delay:
5355 18:05:43.133438 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =104
5356 18:05:43.136987 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5357 18:05:43.140240 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5358 18:05:43.143505 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =100
5359 18:05:43.143933
5360 18:05:43.144373
5361 18:05:43.150098 [DQSOSCAuto] RK0, (LSB)MR18= 0x2522, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5362 18:05:43.153226 CH0 RK0: MR19=505, MR18=2522
5363 18:05:43.159894 CH0_RK0: MR19=0x505, MR18=0x2522, DQSOSC=410, MR23=63, INC=64, DEC=42
5364 18:05:43.160374
5365 18:05:43.163552 ----->DramcWriteLeveling(PI) begin...
5366 18:05:43.163976 ==
5367 18:05:43.166728 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 18:05:43.169736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 18:05:43.170156 ==
5370 18:05:43.173108 Write leveling (Byte 0): 33 => 33
5371 18:05:43.176640 Write leveling (Byte 1): 27 => 27
5372 18:05:43.180270 DramcWriteLeveling(PI) end<-----
5373 18:05:43.180821
5374 18:05:43.181167 ==
5375 18:05:43.183408 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 18:05:43.186660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 18:05:43.190072 ==
5378 18:05:43.190500 [Gating] SW mode calibration
5379 18:05:43.200171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5380 18:05:43.203649 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5381 18:05:43.206716 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 18:05:43.213135 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 18:05:43.216429 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 18:05:43.219722 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 18:05:43.226307 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 18:05:43.229539 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 18:05:43.233005 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5388 18:05:43.239505 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5389 18:05:43.242837 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 18:05:43.246304 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 18:05:43.252742 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 18:05:43.256158 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 18:05:43.259784 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 18:05:43.266558 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 18:05:43.269528 0 15 24 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (1 1)
5396 18:05:43.273185 0 15 28 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
5397 18:05:43.279493 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 18:05:43.282799 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 18:05:43.286050 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 18:05:43.292962 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 18:05:43.295735 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 18:05:43.299002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 18:05:43.305861 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 18:05:43.309089 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5405 18:05:43.312115 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 18:05:43.319216 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 18:05:43.322525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 18:05:43.325780 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 18:05:43.329134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 18:05:43.335517 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 18:05:43.338555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 18:05:43.342362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 18:05:43.349084 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 18:05:43.352156 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 18:05:43.355351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 18:05:43.361885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 18:05:43.365174 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 18:05:43.368597 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 18:05:43.375213 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 18:05:43.378394 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5421 18:05:43.382252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5422 18:05:43.385145 Total UI for P1: 0, mck2ui 16
5423 18:05:43.388537 best dqsien dly found for B1: ( 1, 2, 28)
5424 18:05:43.395347 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 18:05:43.395692 Total UI for P1: 0, mck2ui 16
5426 18:05:43.401829 best dqsien dly found for B0: ( 1, 2, 30)
5427 18:05:43.405172 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5428 18:05:43.408385 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5429 18:05:43.408718
5430 18:05:43.412138 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5431 18:05:43.414871 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5432 18:05:43.418484 [Gating] SW calibration Done
5433 18:05:43.418771 ==
5434 18:05:43.421646 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 18:05:43.424910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 18:05:43.425145 ==
5437 18:05:43.428234 RX Vref Scan: 0
5438 18:05:43.428534
5439 18:05:43.428753 RX Vref 0 -> 0, step: 1
5440 18:05:43.428932
5441 18:05:43.431509 RX Delay -80 -> 252, step: 8
5442 18:05:43.437997 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5443 18:05:43.441655 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5444 18:05:43.445041 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5445 18:05:43.448282 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5446 18:05:43.451540 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5447 18:05:43.454845 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5448 18:05:43.461354 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5449 18:05:43.464675 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5450 18:05:43.467955 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5451 18:05:43.471648 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5452 18:05:43.475008 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5453 18:05:43.478276 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5454 18:05:43.484951 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5455 18:05:43.487847 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5456 18:05:43.491328 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5457 18:05:43.494781 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5458 18:05:43.495016 ==
5459 18:05:43.497920 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 18:05:43.501641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 18:05:43.502006 ==
5462 18:05:43.504761 DQS Delay:
5463 18:05:43.505150 DQS0 = 0, DQS1 = 0
5464 18:05:43.508609 DQM Delay:
5465 18:05:43.509038 DQM0 = 103, DQM1 = 91
5466 18:05:43.509383 DQ Delay:
5467 18:05:43.511842 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5468 18:05:43.514974 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5469 18:05:43.518264 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5470 18:05:43.521439 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5471 18:05:43.524996
5472 18:05:43.525421
5473 18:05:43.525759 ==
5474 18:05:43.528018 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 18:05:43.531502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 18:05:43.531928 ==
5477 18:05:43.532268
5478 18:05:43.532620
5479 18:05:43.534735 TX Vref Scan disable
5480 18:05:43.535158 == TX Byte 0 ==
5481 18:05:43.541335 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5482 18:05:43.544564 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5483 18:05:43.544648 == TX Byte 1 ==
5484 18:05:43.550988 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5485 18:05:43.554244 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5486 18:05:43.554330 ==
5487 18:05:43.557901 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 18:05:43.561168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 18:05:43.561254 ==
5490 18:05:43.561322
5491 18:05:43.561384
5492 18:05:43.564502 TX Vref Scan disable
5493 18:05:43.567772 == TX Byte 0 ==
5494 18:05:43.570933 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5495 18:05:43.574235 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5496 18:05:43.577935 == TX Byte 1 ==
5497 18:05:43.581123 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5498 18:05:43.584780 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5499 18:05:43.584864
5500 18:05:43.587820 [DATLAT]
5501 18:05:43.587902 Freq=933, CH0 RK1
5502 18:05:43.587968
5503 18:05:43.591055 DATLAT Default: 0xb
5504 18:05:43.591138 0, 0xFFFF, sum = 0
5505 18:05:43.594200 1, 0xFFFF, sum = 0
5506 18:05:43.594284 2, 0xFFFF, sum = 0
5507 18:05:43.597689 3, 0xFFFF, sum = 0
5508 18:05:43.597774 4, 0xFFFF, sum = 0
5509 18:05:43.601243 5, 0xFFFF, sum = 0
5510 18:05:43.601328 6, 0xFFFF, sum = 0
5511 18:05:43.604177 7, 0xFFFF, sum = 0
5512 18:05:43.604265 8, 0xFFFF, sum = 0
5513 18:05:43.607337 9, 0xFFFF, sum = 0
5514 18:05:43.607422 10, 0x0, sum = 1
5515 18:05:43.610759 11, 0x0, sum = 2
5516 18:05:43.610843 12, 0x0, sum = 3
5517 18:05:43.614557 13, 0x0, sum = 4
5518 18:05:43.614642 best_step = 11
5519 18:05:43.614708
5520 18:05:43.614771 ==
5521 18:05:43.617821 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 18:05:43.624271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 18:05:43.624356 ==
5524 18:05:43.624441 RX Vref Scan: 0
5525 18:05:43.624505
5526 18:05:43.627436 RX Vref 0 -> 0, step: 1
5527 18:05:43.627519
5528 18:05:43.630710 RX Delay -53 -> 252, step: 4
5529 18:05:43.633934 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5530 18:05:43.637646 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5531 18:05:43.644041 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5532 18:05:43.647292 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5533 18:05:43.650598 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5534 18:05:43.653796 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5535 18:05:43.657093 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5536 18:05:43.663837 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5537 18:05:43.667149 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5538 18:05:43.671018 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5539 18:05:43.674199 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5540 18:05:43.677298 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5541 18:05:43.683851 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5542 18:05:43.687062 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5543 18:05:43.690832 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5544 18:05:43.694081 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5545 18:05:43.694227 ==
5546 18:05:43.697194 Dram Type= 6, Freq= 0, CH_0, rank 1
5547 18:05:43.700804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 18:05:43.704030 ==
5549 18:05:43.704144 DQS Delay:
5550 18:05:43.704234 DQS0 = 0, DQS1 = 0
5551 18:05:43.707461 DQM Delay:
5552 18:05:43.707586 DQM0 = 104, DQM1 = 92
5553 18:05:43.710884 DQ Delay:
5554 18:05:43.714089 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5555 18:05:43.717764 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5556 18:05:43.721035 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5557 18:05:43.724615 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5558 18:05:43.725149
5559 18:05:43.725510
5560 18:05:43.731049 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5561 18:05:43.734526 CH0 RK1: MR19=505, MR18=2708
5562 18:05:43.741164 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5563 18:05:43.744689 [RxdqsGatingPostProcess] freq 933
5564 18:05:43.747750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5565 18:05:43.750981 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 18:05:43.754228 best DQS1 dly(2T, 0.5T) = (0, 10)
5567 18:05:43.757486 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 18:05:43.760826 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5569 18:05:43.764064 best DQS0 dly(2T, 0.5T) = (0, 10)
5570 18:05:43.767414 best DQS1 dly(2T, 0.5T) = (0, 10)
5571 18:05:43.770666 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5572 18:05:43.773929 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5573 18:05:43.777264 Pre-setting of DQS Precalculation
5574 18:05:43.780434 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5575 18:05:43.780913 ==
5576 18:05:43.784091 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 18:05:43.790436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 18:05:43.790866 ==
5579 18:05:43.793962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 18:05:43.800278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5581 18:05:43.803923 [CA 0] Center 37 (7~68) winsize 62
5582 18:05:43.807110 [CA 1] Center 37 (7~68) winsize 62
5583 18:05:43.810372 [CA 2] Center 35 (5~66) winsize 62
5584 18:05:43.813788 [CA 3] Center 34 (4~65) winsize 62
5585 18:05:43.817226 [CA 4] Center 35 (5~66) winsize 62
5586 18:05:43.820454 [CA 5] Center 34 (4~64) winsize 61
5587 18:05:43.820911
5588 18:05:43.824156 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5589 18:05:43.824644
5590 18:05:43.827598 [CATrainingPosCal] consider 1 rank data
5591 18:05:43.830729 u2DelayCellTimex100 = 270/100 ps
5592 18:05:43.833885 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5593 18:05:43.837027 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5594 18:05:43.844198 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5595 18:05:43.847390 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5596 18:05:43.850421 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5597 18:05:43.853856 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5598 18:05:43.854435
5599 18:05:43.857530 CA PerBit enable=1, Macro0, CA PI delay=34
5600 18:05:43.858109
5601 18:05:43.861093 [CBTSetCACLKResult] CA Dly = 34
5602 18:05:43.861673 CS Dly: 7 (0~38)
5603 18:05:43.864326 ==
5604 18:05:43.864971 Dram Type= 6, Freq= 0, CH_1, rank 1
5605 18:05:43.870730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5606 18:05:43.871320 ==
5607 18:05:43.874001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5608 18:05:43.880732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5609 18:05:43.883773 [CA 0] Center 38 (8~68) winsize 61
5610 18:05:43.886868 [CA 1] Center 38 (8~68) winsize 61
5611 18:05:43.890228 [CA 2] Center 36 (6~66) winsize 61
5612 18:05:43.893538 [CA 3] Center 35 (6~65) winsize 60
5613 18:05:43.897152 [CA 4] Center 35 (6~65) winsize 60
5614 18:05:43.900621 [CA 5] Center 35 (5~65) winsize 61
5615 18:05:43.901100
5616 18:05:43.903726 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5617 18:05:43.904208
5618 18:05:43.906999 [CATrainingPosCal] consider 2 rank data
5619 18:05:43.910613 u2DelayCellTimex100 = 270/100 ps
5620 18:05:43.913656 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5621 18:05:43.917104 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5622 18:05:43.923505 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5623 18:05:43.927059 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5624 18:05:43.930308 CA4 delay=35 (6~65),Diff = 1 PI (6 cell)
5625 18:05:43.933642 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5626 18:05:43.934079
5627 18:05:43.936853 CA PerBit enable=1, Macro0, CA PI delay=34
5628 18:05:43.937293
5629 18:05:43.940085 [CBTSetCACLKResult] CA Dly = 34
5630 18:05:43.940520 CS Dly: 7 (0~39)
5631 18:05:43.943555
5632 18:05:43.946986 ----->DramcWriteLeveling(PI) begin...
5633 18:05:43.947429 ==
5634 18:05:43.950370 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 18:05:43.953690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 18:05:43.954130 ==
5637 18:05:43.957044 Write leveling (Byte 0): 27 => 27
5638 18:05:43.960715 Write leveling (Byte 1): 30 => 30
5639 18:05:43.963569 DramcWriteLeveling(PI) end<-----
5640 18:05:43.964132
5641 18:05:43.964536 ==
5642 18:05:43.966846 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 18:05:43.970175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 18:05:43.970604 ==
5645 18:05:43.973351 [Gating] SW mode calibration
5646 18:05:43.980811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5647 18:05:43.987053 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5648 18:05:43.990494 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 18:05:43.993476 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 18:05:44.000331 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 18:05:44.003473 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 18:05:44.006740 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 18:05:44.013629 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5654 18:05:44.016163 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5655 18:05:44.019708 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5656 18:05:44.022763 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 18:05:44.029616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 18:05:44.032740 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 18:05:44.036506 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 18:05:44.043065 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 18:05:44.046209 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 18:05:44.049711 0 15 24 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
5663 18:05:44.056472 0 15 28 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
5664 18:05:44.059893 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 18:05:44.062627 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 18:05:44.069721 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 18:05:44.072974 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 18:05:44.076268 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 18:05:44.082862 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 18:05:44.086505 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5671 18:05:44.089694 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 18:05:44.096797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 18:05:44.099846 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 18:05:44.103085 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 18:05:44.109962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 18:05:44.112951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 18:05:44.116710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 18:05:44.122923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 18:05:44.126515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 18:05:44.129625 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 18:05:44.136449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 18:05:44.140077 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 18:05:44.143209 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 18:05:44.149588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 18:05:44.153260 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5686 18:05:44.156426 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5687 18:05:44.159472 Total UI for P1: 0, mck2ui 16
5688 18:05:44.162871 best dqsien dly found for B1: ( 1, 2, 22)
5689 18:05:44.166142 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5690 18:05:44.169366 Total UI for P1: 0, mck2ui 16
5691 18:05:44.173114 best dqsien dly found for B0: ( 1, 2, 22)
5692 18:05:44.176385 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5693 18:05:44.179551 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5694 18:05:44.182904
5695 18:05:44.186352 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5696 18:05:44.189634 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5697 18:05:44.192856 [Gating] SW calibration Done
5698 18:05:44.193336 ==
5699 18:05:44.196102 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 18:05:44.199315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 18:05:44.199909 ==
5702 18:05:44.200268 RX Vref Scan: 0
5703 18:05:44.202422
5704 18:05:44.202912 RX Vref 0 -> 0, step: 1
5705 18:05:44.203315
5706 18:05:44.206293 RX Delay -80 -> 252, step: 8
5707 18:05:44.209563 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5708 18:05:44.212543 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5709 18:05:44.219344 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5710 18:05:44.222521 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5711 18:05:44.226412 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5712 18:05:44.229403 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5713 18:05:44.232519 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5714 18:05:44.236139 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5715 18:05:44.242582 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5716 18:05:44.246243 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5717 18:05:44.249256 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5718 18:05:44.252474 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5719 18:05:44.255764 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5720 18:05:44.259750 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5721 18:05:44.265968 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5722 18:05:44.269172 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5723 18:05:44.269752 ==
5724 18:05:44.272612 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 18:05:44.275848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 18:05:44.276424 ==
5727 18:05:44.279680 DQS Delay:
5728 18:05:44.280250 DQS0 = 0, DQS1 = 0
5729 18:05:44.280663 DQM Delay:
5730 18:05:44.282910 DQM0 = 102, DQM1 = 95
5731 18:05:44.283491 DQ Delay:
5732 18:05:44.285914 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5733 18:05:44.289205 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5734 18:05:44.292457 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5735 18:05:44.295737 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5736 18:05:44.296211
5737 18:05:44.296609
5738 18:05:44.296960 ==
5739 18:05:44.299040 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 18:05:44.305385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 18:05:44.305950 ==
5742 18:05:44.306333
5743 18:05:44.306700
5744 18:05:44.307043 TX Vref Scan disable
5745 18:05:44.309019 == TX Byte 0 ==
5746 18:05:44.312201 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 18:05:44.319467 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 18:05:44.319940 == TX Byte 1 ==
5749 18:05:44.322475 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5750 18:05:44.329316 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5751 18:05:44.329772 ==
5752 18:05:44.332575 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 18:05:44.335499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 18:05:44.335928 ==
5755 18:05:44.336271
5756 18:05:44.336614
5757 18:05:44.339006 TX Vref Scan disable
5758 18:05:44.339434 == TX Byte 0 ==
5759 18:05:44.345599 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5760 18:05:44.348950 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5761 18:05:44.349377 == TX Byte 1 ==
5762 18:05:44.355575 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5763 18:05:44.358760 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5764 18:05:44.359188
5765 18:05:44.359525 [DATLAT]
5766 18:05:44.362519 Freq=933, CH1 RK0
5767 18:05:44.362946
5768 18:05:44.363281 DATLAT Default: 0xd
5769 18:05:44.365620 0, 0xFFFF, sum = 0
5770 18:05:44.366053 1, 0xFFFF, sum = 0
5771 18:05:44.369091 2, 0xFFFF, sum = 0
5772 18:05:44.369525 3, 0xFFFF, sum = 0
5773 18:05:44.372846 4, 0xFFFF, sum = 0
5774 18:05:44.376019 5, 0xFFFF, sum = 0
5775 18:05:44.376621 6, 0xFFFF, sum = 0
5776 18:05:44.379324 7, 0xFFFF, sum = 0
5777 18:05:44.379906 8, 0xFFFF, sum = 0
5778 18:05:44.382353 9, 0xFFFF, sum = 0
5779 18:05:44.382835 10, 0x0, sum = 1
5780 18:05:44.385719 11, 0x0, sum = 2
5781 18:05:44.386233 12, 0x0, sum = 3
5782 18:05:44.386796 13, 0x0, sum = 4
5783 18:05:44.388913 best_step = 11
5784 18:05:44.389383
5785 18:05:44.389754 ==
5786 18:05:44.392355 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 18:05:44.395553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 18:05:44.395984 ==
5789 18:05:44.398683 RX Vref Scan: 1
5790 18:05:44.399158
5791 18:05:44.399502 RX Vref 0 -> 0, step: 1
5792 18:05:44.402410
5793 18:05:44.402834 RX Delay -53 -> 252, step: 4
5794 18:05:44.403176
5795 18:05:44.405938 Set Vref, RX VrefLevel [Byte0]: 51
5796 18:05:44.408990 [Byte1]: 49
5797 18:05:44.413294
5798 18:05:44.413832 Final RX Vref Byte 0 = 51 to rank0
5799 18:05:44.416508 Final RX Vref Byte 1 = 49 to rank0
5800 18:05:44.419663 Final RX Vref Byte 0 = 51 to rank1
5801 18:05:44.423022 Final RX Vref Byte 1 = 49 to rank1==
5802 18:05:44.426534 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 18:05:44.432825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 18:05:44.433255 ==
5805 18:05:44.433598 DQS Delay:
5806 18:05:44.436377 DQS0 = 0, DQS1 = 0
5807 18:05:44.436837 DQM Delay:
5808 18:05:44.437179 DQM0 = 104, DQM1 = 96
5809 18:05:44.439491 DQ Delay:
5810 18:05:44.443211 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5811 18:05:44.446193 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5812 18:05:44.449524 DQ8 =86, DQ9 =86, DQ10 =100, DQ11 =90
5813 18:05:44.452842 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =102
5814 18:05:44.453270
5815 18:05:44.453607
5816 18:05:44.459375 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5817 18:05:44.462569 CH1 RK0: MR19=505, MR18=162E
5818 18:05:44.469011 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5819 18:05:44.469095
5820 18:05:44.472697 ----->DramcWriteLeveling(PI) begin...
5821 18:05:44.472783 ==
5822 18:05:44.476004 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 18:05:44.479133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 18:05:44.482559 ==
5825 18:05:44.482642 Write leveling (Byte 0): 26 => 26
5826 18:05:44.485948 Write leveling (Byte 1): 26 => 26
5827 18:05:44.489130 DramcWriteLeveling(PI) end<-----
5828 18:05:44.489213
5829 18:05:44.489279 ==
5830 18:05:44.492532 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 18:05:44.499027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 18:05:44.499112 ==
5833 18:05:44.499179 [Gating] SW mode calibration
5834 18:05:44.508730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5835 18:05:44.512228 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5836 18:05:44.519202 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 18:05:44.522389 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 18:05:44.525823 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 18:05:44.532280 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 18:05:44.535462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 18:05:44.538747 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 18:05:44.542399 0 14 24 | B1->B0 | 3131 3333 | 0 1 | (0 1) (1 1)
5843 18:05:44.548690 0 14 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
5844 18:05:44.552359 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 18:05:44.555571 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 18:05:44.562180 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 18:05:44.565537 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 18:05:44.568844 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 18:05:44.575267 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 18:05:44.578524 0 15 24 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
5851 18:05:44.582284 0 15 28 | B1->B0 | 4444 3939 | 1 0 | (0 0) (0 0)
5852 18:05:44.588748 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 18:05:44.591920 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 18:05:44.595132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 18:05:44.601693 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 18:05:44.605015 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 18:05:44.608291 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 18:05:44.615003 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5859 18:05:44.618144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5860 18:05:44.621931 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 18:05:44.628407 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 18:05:44.632387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 18:05:44.635274 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 18:05:44.642171 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 18:05:44.645423 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 18:05:44.648794 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 18:05:44.652047 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 18:05:44.658565 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 18:05:44.661732 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 18:05:44.664935 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 18:05:44.671958 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 18:05:44.675430 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 18:05:44.678832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 18:05:44.685084 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5875 18:05:44.688341 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5876 18:05:44.691619 Total UI for P1: 0, mck2ui 16
5877 18:05:44.695269 best dqsien dly found for B1: ( 1, 2, 24)
5878 18:05:44.698449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 18:05:44.701741 Total UI for P1: 0, mck2ui 16
5880 18:05:44.705035 best dqsien dly found for B0: ( 1, 2, 26)
5881 18:05:44.708175 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5882 18:05:44.715243 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5883 18:05:44.715779
5884 18:05:44.718343 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5885 18:05:44.721424 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5886 18:05:44.724832 [Gating] SW calibration Done
5887 18:05:44.724916 ==
5888 18:05:44.727646 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 18:05:44.730826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 18:05:44.730912 ==
5891 18:05:44.734531 RX Vref Scan: 0
5892 18:05:44.734618
5893 18:05:44.734686 RX Vref 0 -> 0, step: 1
5894 18:05:44.734750
5895 18:05:44.737728 RX Delay -80 -> 252, step: 8
5896 18:05:44.740971 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5897 18:05:44.744500 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5898 18:05:44.750957 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5899 18:05:44.754167 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5900 18:05:44.757932 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5901 18:05:44.761291 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5902 18:05:44.764314 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5903 18:05:44.771447 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5904 18:05:44.774250 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5905 18:05:44.777965 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5906 18:05:44.780543 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5907 18:05:44.784209 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5908 18:05:44.790892 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5909 18:05:44.794559 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5910 18:05:44.797593 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5911 18:05:44.801532 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5912 18:05:44.802329 ==
5913 18:05:44.804465 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 18:05:44.811059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 18:05:44.811632 ==
5916 18:05:44.812021 DQS Delay:
5917 18:05:44.812379 DQS0 = 0, DQS1 = 0
5918 18:05:44.814274 DQM Delay:
5919 18:05:44.814755 DQM0 = 103, DQM1 = 96
5920 18:05:44.817410 DQ Delay:
5921 18:05:44.820807 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5922 18:05:44.823601 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5923 18:05:44.826777 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5924 18:05:44.830605 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5925 18:05:44.830691
5926 18:05:44.830760
5927 18:05:44.830823 ==
5928 18:05:44.833478 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 18:05:44.836999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 18:05:44.837085 ==
5931 18:05:44.837153
5932 18:05:44.837216
5933 18:05:44.840098 TX Vref Scan disable
5934 18:05:44.843289 == TX Byte 0 ==
5935 18:05:44.846867 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5936 18:05:44.849838 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5937 18:05:44.853651 == TX Byte 1 ==
5938 18:05:44.856746 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5939 18:05:44.859902 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5940 18:05:44.860018 ==
5941 18:05:44.863488 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 18:05:44.866625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 18:05:44.870299 ==
5944 18:05:44.870440
5945 18:05:44.870551
5946 18:05:44.870655 TX Vref Scan disable
5947 18:05:44.873909 == TX Byte 0 ==
5948 18:05:44.877110 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5949 18:05:44.883445 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5950 18:05:44.883531 == TX Byte 1 ==
5951 18:05:44.886734 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5952 18:05:44.893624 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5953 18:05:44.893715
5954 18:05:44.893788 [DATLAT]
5955 18:05:44.893856 Freq=933, CH1 RK1
5956 18:05:44.893922
5957 18:05:44.896878 DATLAT Default: 0xb
5958 18:05:44.896968 0, 0xFFFF, sum = 0
5959 18:05:44.900453 1, 0xFFFF, sum = 0
5960 18:05:44.900657 2, 0xFFFF, sum = 0
5961 18:05:44.903701 3, 0xFFFF, sum = 0
5962 18:05:44.907023 4, 0xFFFF, sum = 0
5963 18:05:44.907190 5, 0xFFFF, sum = 0
5964 18:05:44.910440 6, 0xFFFF, sum = 0
5965 18:05:44.910640 7, 0xFFFF, sum = 0
5966 18:05:44.914286 8, 0xFFFF, sum = 0
5967 18:05:44.914497 9, 0xFFFF, sum = 0
5968 18:05:44.916691 10, 0x0, sum = 1
5969 18:05:44.916855 11, 0x0, sum = 2
5970 18:05:44.920194 12, 0x0, sum = 3
5971 18:05:44.920424 13, 0x0, sum = 4
5972 18:05:44.920563 best_step = 11
5973 18:05:44.920685
5974 18:05:44.923992 ==
5975 18:05:44.927157 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 18:05:44.930222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 18:05:44.930492 ==
5978 18:05:44.930648 RX Vref Scan: 0
5979 18:05:44.930828
5980 18:05:44.933654 RX Vref 0 -> 0, step: 1
5981 18:05:44.933959
5982 18:05:44.937438 RX Delay -53 -> 252, step: 4
5983 18:05:44.940433 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5984 18:05:44.947409 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5985 18:05:44.950753 iDelay=199, Bit 2, Center 96 (19 ~ 174) 156
5986 18:05:44.953924 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5987 18:05:44.957440 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5988 18:05:44.960446 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5989 18:05:44.966946 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5990 18:05:44.970680 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5991 18:05:44.973686 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5992 18:05:44.977454 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5993 18:05:44.980640 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5994 18:05:44.983862 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5995 18:05:44.990353 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5996 18:05:44.993901 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5997 18:05:44.997245 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5998 18:05:45.000160 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5999 18:05:45.000246 ==
6000 18:05:45.003452 Dram Type= 6, Freq= 0, CH_1, rank 1
6001 18:05:45.010257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6002 18:05:45.010349 ==
6003 18:05:45.010422 DQS Delay:
6004 18:05:45.013413 DQS0 = 0, DQS1 = 0
6005 18:05:45.013499 DQM Delay:
6006 18:05:45.013567 DQM0 = 105, DQM1 = 97
6007 18:05:45.016591 DQ Delay:
6008 18:05:45.019868 DQ0 =108, DQ1 =100, DQ2 =96, DQ3 =102
6009 18:05:45.023472 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
6010 18:05:45.026723 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
6011 18:05:45.030469 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =106
6012 18:05:45.030904
6013 18:05:45.031306
6014 18:05:45.037069 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
6015 18:05:45.040419 CH1 RK1: MR19=504, MR18=20FE
6016 18:05:45.047057 CH1_RK1: MR19=0x504, MR18=0x20FE, DQSOSC=411, MR23=63, INC=64, DEC=42
6017 18:05:45.050565 [RxdqsGatingPostProcess] freq 933
6018 18:05:45.056765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6019 18:05:45.060262 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 18:05:45.060733 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 18:05:45.063504 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 18:05:45.067295 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 18:05:45.070262 best DQS0 dly(2T, 0.5T) = (0, 10)
6024 18:05:45.073930 best DQS1 dly(2T, 0.5T) = (0, 10)
6025 18:05:45.077068 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6026 18:05:45.080153 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6027 18:05:45.083749 Pre-setting of DQS Precalculation
6028 18:05:45.090184 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6029 18:05:45.096973 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6030 18:05:45.103434 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6031 18:05:45.103930
6032 18:05:45.104282
6033 18:05:45.106656 [Calibration Summary] 1866 Mbps
6034 18:05:45.107211 CH 0, Rank 0
6035 18:05:45.110350 SW Impedance : PASS
6036 18:05:45.113239 DUTY Scan : NO K
6037 18:05:45.113738 ZQ Calibration : PASS
6038 18:05:45.116948 Jitter Meter : NO K
6039 18:05:45.117492 CBT Training : PASS
6040 18:05:45.120344 Write leveling : PASS
6041 18:05:45.123624 RX DQS gating : PASS
6042 18:05:45.124069 RX DQ/DQS(RDDQC) : PASS
6043 18:05:45.126958 TX DQ/DQS : PASS
6044 18:05:45.130271 RX DATLAT : PASS
6045 18:05:45.130728 RX DQ/DQS(Engine): PASS
6046 18:05:45.133534 TX OE : NO K
6047 18:05:45.133994 All Pass.
6048 18:05:45.134354
6049 18:05:45.136636 CH 0, Rank 1
6050 18:05:45.137096 SW Impedance : PASS
6051 18:05:45.139843 DUTY Scan : NO K
6052 18:05:45.142974 ZQ Calibration : PASS
6053 18:05:45.143392 Jitter Meter : NO K
6054 18:05:45.146266 CBT Training : PASS
6055 18:05:45.150163 Write leveling : PASS
6056 18:05:45.150624 RX DQS gating : PASS
6057 18:05:45.153527 RX DQ/DQS(RDDQC) : PASS
6058 18:05:45.156628 TX DQ/DQS : PASS
6059 18:05:45.157121 RX DATLAT : PASS
6060 18:05:45.159728 RX DQ/DQS(Engine): PASS
6061 18:05:45.162931 TX OE : NO K
6062 18:05:45.163384 All Pass.
6063 18:05:45.163760
6064 18:05:45.164101 CH 1, Rank 0
6065 18:05:45.166526 SW Impedance : PASS
6066 18:05:45.169702 DUTY Scan : NO K
6067 18:05:45.170154 ZQ Calibration : PASS
6068 18:05:45.173237 Jitter Meter : NO K
6069 18:05:45.173731 CBT Training : PASS
6070 18:05:45.176275 Write leveling : PASS
6071 18:05:45.179863 RX DQS gating : PASS
6072 18:05:45.180685 RX DQ/DQS(RDDQC) : PASS
6073 18:05:45.182899 TX DQ/DQS : PASS
6074 18:05:45.186575 RX DATLAT : PASS
6075 18:05:45.187205 RX DQ/DQS(Engine): PASS
6076 18:05:45.189866 TX OE : NO K
6077 18:05:45.190561 All Pass.
6078 18:05:45.191139
6079 18:05:45.192925 CH 1, Rank 1
6080 18:05:45.193481 SW Impedance : PASS
6081 18:05:45.196247 DUTY Scan : NO K
6082 18:05:45.199390 ZQ Calibration : PASS
6083 18:05:45.200006 Jitter Meter : NO K
6084 18:05:45.202949 CBT Training : PASS
6085 18:05:45.206170 Write leveling : PASS
6086 18:05:45.206808 RX DQS gating : PASS
6087 18:05:45.209409 RX DQ/DQS(RDDQC) : PASS
6088 18:05:45.212522 TX DQ/DQS : PASS
6089 18:05:45.212985 RX DATLAT : PASS
6090 18:05:45.216301 RX DQ/DQS(Engine): PASS
6091 18:05:45.219507 TX OE : NO K
6092 18:05:45.219776 All Pass.
6093 18:05:45.220018
6094 18:05:45.220248 DramC Write-DBI off
6095 18:05:45.222820 PER_BANK_REFRESH: Hybrid Mode
6096 18:05:45.226215 TX_TRACKING: ON
6097 18:05:45.232681 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6098 18:05:45.235993 [FAST_K] Save calibration result to emmc
6099 18:05:45.242471 dramc_set_vcore_voltage set vcore to 650000
6100 18:05:45.242629 Read voltage for 400, 6
6101 18:05:45.242755 Vio18 = 0
6102 18:05:45.245700 Vcore = 650000
6103 18:05:45.245858 Vdram = 0
6104 18:05:45.245984 Vddq = 0
6105 18:05:45.249322 Vmddr = 0
6106 18:05:45.252540 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6107 18:05:45.258994 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6108 18:05:45.262283 MEM_TYPE=3, freq_sel=20
6109 18:05:45.262441 sv_algorithm_assistance_LP4_800
6110 18:05:45.269051 ============ PULL DRAM RESETB DOWN ============
6111 18:05:45.272662 ========== PULL DRAM RESETB DOWN end =========
6112 18:05:45.276000 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6113 18:05:45.279157 ===================================
6114 18:05:45.282281 LPDDR4 DRAM CONFIGURATION
6115 18:05:45.285741 ===================================
6116 18:05:45.289179 EX_ROW_EN[0] = 0x0
6117 18:05:45.289260 EX_ROW_EN[1] = 0x0
6118 18:05:45.292389 LP4Y_EN = 0x0
6119 18:05:45.292463 WORK_FSP = 0x0
6120 18:05:45.295581 WL = 0x2
6121 18:05:45.295652 RL = 0x2
6122 18:05:45.298796 BL = 0x2
6123 18:05:45.298867 RPST = 0x0
6124 18:05:45.302014 RD_PRE = 0x0
6125 18:05:45.302089 WR_PRE = 0x1
6126 18:05:45.305700 WR_PST = 0x0
6127 18:05:45.305777 DBI_WR = 0x0
6128 18:05:45.308527 DBI_RD = 0x0
6129 18:05:45.308628 OTF = 0x1
6130 18:05:45.312028 ===================================
6131 18:05:45.315668 ===================================
6132 18:05:45.318986 ANA top config
6133 18:05:45.322314 ===================================
6134 18:05:45.325690 DLL_ASYNC_EN = 0
6135 18:05:45.325763 ALL_SLAVE_EN = 1
6136 18:05:45.328843 NEW_RANK_MODE = 1
6137 18:05:45.332040 DLL_IDLE_MODE = 1
6138 18:05:45.335254 LP45_APHY_COMB_EN = 1
6139 18:05:45.338594 TX_ODT_DIS = 1
6140 18:05:45.338669 NEW_8X_MODE = 1
6141 18:05:45.341773 ===================================
6142 18:05:45.345061 ===================================
6143 18:05:45.348355 data_rate = 800
6144 18:05:45.351706 CKR = 1
6145 18:05:45.355369 DQ_P2S_RATIO = 4
6146 18:05:45.358708 ===================================
6147 18:05:45.361846 CA_P2S_RATIO = 4
6148 18:05:45.361919 DQ_CA_OPEN = 0
6149 18:05:45.365115 DQ_SEMI_OPEN = 1
6150 18:05:45.368302 CA_SEMI_OPEN = 1
6151 18:05:45.371752 CA_FULL_RATE = 0
6152 18:05:45.374885 DQ_CKDIV4_EN = 0
6153 18:05:45.378523 CA_CKDIV4_EN = 1
6154 18:05:45.381770 CA_PREDIV_EN = 0
6155 18:05:45.381873 PH8_DLY = 0
6156 18:05:45.385034 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6157 18:05:45.388381 DQ_AAMCK_DIV = 0
6158 18:05:45.391535 CA_AAMCK_DIV = 0
6159 18:05:45.394740 CA_ADMCK_DIV = 4
6160 18:05:45.398391 DQ_TRACK_CA_EN = 0
6161 18:05:45.398467 CA_PICK = 800
6162 18:05:45.401648 CA_MCKIO = 400
6163 18:05:45.404919 MCKIO_SEMI = 400
6164 18:05:45.408152 PLL_FREQ = 3016
6165 18:05:45.411261 DQ_UI_PI_RATIO = 32
6166 18:05:45.414788 CA_UI_PI_RATIO = 32
6167 18:05:45.417958 ===================================
6168 18:05:45.421154 ===================================
6169 18:05:45.424485 memory_type:LPDDR4
6170 18:05:45.424568 GP_NUM : 10
6171 18:05:45.427771 SRAM_EN : 1
6172 18:05:45.427842 MD32_EN : 0
6173 18:05:45.431654 ===================================
6174 18:05:45.434348 [ANA_INIT] >>>>>>>>>>>>>>
6175 18:05:45.438401 <<<<<< [CONFIGURE PHASE]: ANA_TX
6176 18:05:45.441049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6177 18:05:45.444861 ===================================
6178 18:05:45.448143 data_rate = 800,PCW = 0X7400
6179 18:05:45.451417 ===================================
6180 18:05:45.454586 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6181 18:05:45.457693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 18:05:45.471366 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6183 18:05:45.474380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6184 18:05:45.478078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6185 18:05:45.481131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6186 18:05:45.484163 [ANA_INIT] flow start
6187 18:05:45.487951 [ANA_INIT] PLL >>>>>>>>
6188 18:05:45.488034 [ANA_INIT] PLL <<<<<<<<
6189 18:05:45.491298 [ANA_INIT] MIDPI >>>>>>>>
6190 18:05:45.494348 [ANA_INIT] MIDPI <<<<<<<<
6191 18:05:45.494422 [ANA_INIT] DLL >>>>>>>>
6192 18:05:45.497910 [ANA_INIT] flow end
6193 18:05:45.500985 ============ LP4 DIFF to SE enter ============
6194 18:05:45.507755 ============ LP4 DIFF to SE exit ============
6195 18:05:45.507837 [ANA_INIT] <<<<<<<<<<<<<
6196 18:05:45.510801 [Flow] Enable top DCM control >>>>>
6197 18:05:45.514056 [Flow] Enable top DCM control <<<<<
6198 18:05:45.517651 Enable DLL master slave shuffle
6199 18:05:45.524241 ==============================================================
6200 18:05:45.524318 Gating Mode config
6201 18:05:45.530750 ==============================================================
6202 18:05:45.534049 Config description:
6203 18:05:45.540521 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6204 18:05:45.547656 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6205 18:05:45.554084 SELPH_MODE 0: By rank 1: By Phase
6206 18:05:45.560505 ==============================================================
6207 18:05:45.560595 GAT_TRACK_EN = 0
6208 18:05:45.563967 RX_GATING_MODE = 2
6209 18:05:45.567133 RX_GATING_TRACK_MODE = 2
6210 18:05:45.570908 SELPH_MODE = 1
6211 18:05:45.574095 PICG_EARLY_EN = 1
6212 18:05:45.577313 VALID_LAT_VALUE = 1
6213 18:05:45.583942 ==============================================================
6214 18:05:45.587077 Enter into Gating configuration >>>>
6215 18:05:45.590746 Exit from Gating configuration <<<<
6216 18:05:45.594047 Enter into DVFS_PRE_config >>>>>
6217 18:05:45.603692 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6218 18:05:45.606937 Exit from DVFS_PRE_config <<<<<
6219 18:05:45.610184 Enter into PICG configuration >>>>
6220 18:05:45.613480 Exit from PICG configuration <<<<
6221 18:05:45.617207 [RX_INPUT] configuration >>>>>
6222 18:05:45.617287 [RX_INPUT] configuration <<<<<
6223 18:05:45.623906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6224 18:05:45.630554 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6225 18:05:45.633398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 18:05:45.640374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 18:05:45.646882 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6228 18:05:45.653459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6229 18:05:45.657126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6230 18:05:45.660251 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6231 18:05:45.666700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6232 18:05:45.670470 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6233 18:05:45.673778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6234 18:05:45.680225 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 18:05:45.683841 ===================================
6236 18:05:45.683926 LPDDR4 DRAM CONFIGURATION
6237 18:05:45.686774 ===================================
6238 18:05:45.690312 EX_ROW_EN[0] = 0x0
6239 18:05:45.690395 EX_ROW_EN[1] = 0x0
6240 18:05:45.693367 LP4Y_EN = 0x0
6241 18:05:45.693450 WORK_FSP = 0x0
6242 18:05:45.697028 WL = 0x2
6243 18:05:45.697112 RL = 0x2
6244 18:05:45.700264 BL = 0x2
6245 18:05:45.703322 RPST = 0x0
6246 18:05:45.703405 RD_PRE = 0x0
6247 18:05:45.707095 WR_PRE = 0x1
6248 18:05:45.707179 WR_PST = 0x0
6249 18:05:45.710261 DBI_WR = 0x0
6250 18:05:45.710344 DBI_RD = 0x0
6251 18:05:45.713703 OTF = 0x1
6252 18:05:45.716903 ===================================
6253 18:05:45.720174 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6254 18:05:45.723233 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6255 18:05:45.726681 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6256 18:05:45.730303 ===================================
6257 18:05:45.733508 LPDDR4 DRAM CONFIGURATION
6258 18:05:45.736856 ===================================
6259 18:05:45.740181 EX_ROW_EN[0] = 0x10
6260 18:05:45.740268 EX_ROW_EN[1] = 0x0
6261 18:05:45.743381 LP4Y_EN = 0x0
6262 18:05:45.743468 WORK_FSP = 0x0
6263 18:05:45.746678 WL = 0x2
6264 18:05:45.746763 RL = 0x2
6265 18:05:45.750346 BL = 0x2
6266 18:05:45.750431 RPST = 0x0
6267 18:05:45.753123 RD_PRE = 0x0
6268 18:05:45.753209 WR_PRE = 0x1
6269 18:05:45.756746 WR_PST = 0x0
6270 18:05:45.759968 DBI_WR = 0x0
6271 18:05:45.760053 DBI_RD = 0x0
6272 18:05:45.763020 OTF = 0x1
6273 18:05:45.766774 ===================================
6274 18:05:45.769573 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6275 18:05:45.774882 nWR fixed to 30
6276 18:05:45.778617 [ModeRegInit_LP4] CH0 RK0
6277 18:05:45.778703 [ModeRegInit_LP4] CH0 RK1
6278 18:05:45.781861 [ModeRegInit_LP4] CH1 RK0
6279 18:05:45.785453 [ModeRegInit_LP4] CH1 RK1
6280 18:05:45.785538 match AC timing 19
6281 18:05:45.791971 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6282 18:05:45.795045 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6283 18:05:45.798658 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6284 18:05:45.805066 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6285 18:05:45.808761 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6286 18:05:45.808848 ==
6287 18:05:45.811922 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 18:05:45.815022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 18:05:45.815109 ==
6290 18:05:45.821579 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6291 18:05:45.828513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6292 18:05:45.831704 [CA 0] Center 36 (8~64) winsize 57
6293 18:05:45.834788 [CA 1] Center 36 (8~64) winsize 57
6294 18:05:45.838610 [CA 2] Center 36 (8~64) winsize 57
6295 18:05:45.838696 [CA 3] Center 36 (8~64) winsize 57
6296 18:05:45.841914 [CA 4] Center 36 (8~64) winsize 57
6297 18:05:45.845091 [CA 5] Center 36 (8~64) winsize 57
6298 18:05:45.845178
6299 18:05:45.848304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6300 18:05:45.851524
6301 18:05:45.854882 [CATrainingPosCal] consider 1 rank data
6302 18:05:45.854968 u2DelayCellTimex100 = 270/100 ps
6303 18:05:45.861516 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 18:05:45.865210 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 18:05:45.868377 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 18:05:45.871529 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 18:05:45.874900 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 18:05:45.878091 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 18:05:45.878177
6310 18:05:45.881372 CA PerBit enable=1, Macro0, CA PI delay=36
6311 18:05:45.881457
6312 18:05:45.884691 [CBTSetCACLKResult] CA Dly = 36
6313 18:05:45.888357 CS Dly: 1 (0~32)
6314 18:05:45.888441 ==
6315 18:05:45.891445 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 18:05:45.894645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 18:05:45.894731 ==
6318 18:05:45.901307 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6319 18:05:45.904555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6320 18:05:45.908337 [CA 0] Center 36 (8~64) winsize 57
6321 18:05:45.911382 [CA 1] Center 36 (8~64) winsize 57
6322 18:05:45.915022 [CA 2] Center 36 (8~64) winsize 57
6323 18:05:45.918234 [CA 3] Center 36 (8~64) winsize 57
6324 18:05:45.921482 [CA 4] Center 36 (8~64) winsize 57
6325 18:05:45.924864 [CA 5] Center 36 (8~64) winsize 57
6326 18:05:45.924980
6327 18:05:45.928201 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6328 18:05:45.928317
6329 18:05:45.931403 [CATrainingPosCal] consider 2 rank data
6330 18:05:45.934719 u2DelayCellTimex100 = 270/100 ps
6331 18:05:45.937917 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 18:05:45.941659 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 18:05:45.944911 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 18:05:45.951360 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 18:05:45.954678 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 18:05:45.957934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 18:05:45.958183
6338 18:05:45.961672 CA PerBit enable=1, Macro0, CA PI delay=36
6339 18:05:45.961921
6340 18:05:45.965009 [CBTSetCACLKResult] CA Dly = 36
6341 18:05:45.965321 CS Dly: 1 (0~32)
6342 18:05:45.965568
6343 18:05:45.968267 ----->DramcWriteLeveling(PI) begin...
6344 18:05:45.968694 ==
6345 18:05:45.971767 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 18:05:45.978110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 18:05:45.978643 ==
6348 18:05:45.981936 Write leveling (Byte 0): 40 => 8
6349 18:05:45.985227 Write leveling (Byte 1): 32 => 0
6350 18:05:45.985662 DramcWriteLeveling(PI) end<-----
6351 18:05:45.986010
6352 18:05:45.988470 ==
6353 18:05:45.991450 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 18:05:45.995279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 18:05:45.995782 ==
6356 18:05:45.998382 [Gating] SW mode calibration
6357 18:05:46.004792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6358 18:05:46.007795 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6359 18:05:46.014825 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 18:05:46.017954 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6361 18:05:46.021542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 18:05:46.027792 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 18:05:46.031109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 18:05:46.034368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 18:05:46.041169 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 18:05:46.044427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 18:05:46.047681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 18:05:46.050826 Total UI for P1: 0, mck2ui 16
6369 18:05:46.054229 best dqsien dly found for B0: ( 0, 14, 24)
6370 18:05:46.057939 Total UI for P1: 0, mck2ui 16
6371 18:05:46.061180 best dqsien dly found for B1: ( 0, 14, 24)
6372 18:05:46.064528 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6373 18:05:46.068251 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6374 18:05:46.068677
6375 18:05:46.074674 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 18:05:46.078143 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6377 18:05:46.078535 [Gating] SW calibration Done
6378 18:05:46.081363 ==
6379 18:05:46.084582 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 18:05:46.087757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 18:05:46.088184 ==
6382 18:05:46.088517 RX Vref Scan: 0
6383 18:05:46.088932
6384 18:05:46.091072 RX Vref 0 -> 0, step: 1
6385 18:05:46.091496
6386 18:05:46.094490 RX Delay -410 -> 252, step: 16
6387 18:05:46.098092 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6388 18:05:46.101193 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6389 18:05:46.107591 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6390 18:05:46.111005 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6391 18:05:46.114339 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6392 18:05:46.117814 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6393 18:05:46.124457 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6394 18:05:46.127528 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6395 18:05:46.131395 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6396 18:05:46.134092 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6397 18:05:46.141050 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6398 18:05:46.144224 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6399 18:05:46.147937 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6400 18:05:46.151163 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6401 18:05:46.157514 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6402 18:05:46.160721 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6403 18:05:46.161269 ==
6404 18:05:46.164540 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 18:05:46.167843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 18:05:46.168455 ==
6407 18:05:46.171016 DQS Delay:
6408 18:05:46.171456 DQS0 = 27, DQS1 = 43
6409 18:05:46.174177 DQM Delay:
6410 18:05:46.174600 DQM0 = 13, DQM1 = 12
6411 18:05:46.174935 DQ Delay:
6412 18:05:46.177429 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6413 18:05:46.180593 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6414 18:05:46.184345 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6415 18:05:46.187578 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6416 18:05:46.188007
6417 18:05:46.188345
6418 18:05:46.188692 ==
6419 18:05:46.190970 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 18:05:46.197726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 18:05:46.198258 ==
6422 18:05:46.198601
6423 18:05:46.198920
6424 18:05:46.199221 TX Vref Scan disable
6425 18:05:46.200700 == TX Byte 0 ==
6426 18:05:46.204071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 18:05:46.207728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 18:05:46.210534 == TX Byte 1 ==
6429 18:05:46.214145 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6430 18:05:46.217306 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6431 18:05:46.220648 ==
6432 18:05:46.221079 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 18:05:46.227131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 18:05:46.227698 ==
6435 18:05:46.228177
6436 18:05:46.228666
6437 18:05:46.230794 TX Vref Scan disable
6438 18:05:46.231212 == TX Byte 0 ==
6439 18:05:46.233901 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 18:05:46.237261 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 18:05:46.240657 == TX Byte 1 ==
6442 18:05:46.244413 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6443 18:05:46.250382 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6444 18:05:46.250808
6445 18:05:46.251141 [DATLAT]
6446 18:05:46.251453 Freq=400, CH0 RK0
6447 18:05:46.251755
6448 18:05:46.254136 DATLAT Default: 0xf
6449 18:05:46.254626 0, 0xFFFF, sum = 0
6450 18:05:46.257329 1, 0xFFFF, sum = 0
6451 18:05:46.257752 2, 0xFFFF, sum = 0
6452 18:05:46.260479 3, 0xFFFF, sum = 0
6453 18:05:46.263757 4, 0xFFFF, sum = 0
6454 18:05:46.264162 5, 0xFFFF, sum = 0
6455 18:05:46.267063 6, 0xFFFF, sum = 0
6456 18:05:46.267538 7, 0xFFFF, sum = 0
6457 18:05:46.270239 8, 0xFFFF, sum = 0
6458 18:05:46.270870 9, 0xFFFF, sum = 0
6459 18:05:46.273821 10, 0xFFFF, sum = 0
6460 18:05:46.274243 11, 0xFFFF, sum = 0
6461 18:05:46.277044 12, 0xFFFF, sum = 0
6462 18:05:46.277470 13, 0x0, sum = 1
6463 18:05:46.280337 14, 0x0, sum = 2
6464 18:05:46.280839 15, 0x0, sum = 3
6465 18:05:46.283620 16, 0x0, sum = 4
6466 18:05:46.284041 best_step = 14
6467 18:05:46.284263
6468 18:05:46.284322 ==
6469 18:05:46.286481 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 18:05:46.289773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 18:05:46.293020 ==
6472 18:05:46.293124 RX Vref Scan: 1
6473 18:05:46.293192
6474 18:05:46.296708 RX Vref 0 -> 0, step: 1
6475 18:05:46.296789
6476 18:05:46.299978 RX Delay -327 -> 252, step: 8
6477 18:05:46.300059
6478 18:05:46.303227 Set Vref, RX VrefLevel [Byte0]: 57
6479 18:05:46.303309 [Byte1]: 50
6480 18:05:46.308559
6481 18:05:46.308658 Final RX Vref Byte 0 = 57 to rank0
6482 18:05:46.312295 Final RX Vref Byte 1 = 50 to rank0
6483 18:05:46.315769 Final RX Vref Byte 0 = 57 to rank1
6484 18:05:46.319351 Final RX Vref Byte 1 = 50 to rank1==
6485 18:05:46.322517 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 18:05:46.329065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 18:05:46.329516 ==
6488 18:05:46.329857 DQS Delay:
6489 18:05:46.332237 DQS0 = 28, DQS1 = 48
6490 18:05:46.332706 DQM Delay:
6491 18:05:46.333076 DQM0 = 11, DQM1 = 15
6492 18:05:46.335994 DQ Delay:
6493 18:05:46.339092 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6494 18:05:46.339542 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6495 18:05:46.342490 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6496 18:05:46.345741 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6497 18:05:46.346174
6498 18:05:46.349051
6499 18:05:46.355741 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6500 18:05:46.358947 CH0 RK0: MR19=C0C, MR18=ABA3
6501 18:05:46.365572 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6502 18:05:46.366001 ==
6503 18:05:46.369424 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 18:05:46.372543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 18:05:46.373012 ==
6506 18:05:46.375909 [Gating] SW mode calibration
6507 18:05:46.382522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6508 18:05:46.389296 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6509 18:05:46.392525 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 18:05:46.396100 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6511 18:05:46.402314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 18:05:46.405774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 18:05:46.408897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 18:05:46.412316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 18:05:46.419144 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 18:05:46.422411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 18:05:46.426026 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 18:05:46.428902 Total UI for P1: 0, mck2ui 16
6519 18:05:46.432207 best dqsien dly found for B0: ( 0, 14, 24)
6520 18:05:46.435814 Total UI for P1: 0, mck2ui 16
6521 18:05:46.438770 best dqsien dly found for B1: ( 0, 14, 24)
6522 18:05:46.442323 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6523 18:05:46.448791 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6524 18:05:46.449351
6525 18:05:46.452060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 18:05:46.455159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6527 18:05:46.459002 [Gating] SW calibration Done
6528 18:05:46.459574 ==
6529 18:05:46.462216 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 18:05:46.465319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 18:05:46.465812 ==
6532 18:05:46.468450 RX Vref Scan: 0
6533 18:05:46.468999
6534 18:05:46.469372 RX Vref 0 -> 0, step: 1
6535 18:05:46.469728
6536 18:05:46.471754 RX Delay -410 -> 252, step: 16
6537 18:05:46.475090 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6538 18:05:46.481894 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6539 18:05:46.485087 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6540 18:05:46.488638 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6541 18:05:46.491901 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6542 18:05:46.498314 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6543 18:05:46.501652 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6544 18:05:46.505043 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6545 18:05:46.508227 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6546 18:05:46.515246 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6547 18:05:46.518601 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6548 18:05:46.521847 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6549 18:05:46.527990 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6550 18:05:46.531481 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6551 18:05:46.534994 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6552 18:05:46.538084 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6553 18:05:46.538557 ==
6554 18:05:46.541638 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 18:05:46.547918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 18:05:46.548396 ==
6557 18:05:46.548824 DQS Delay:
6558 18:05:46.551628 DQS0 = 27, DQS1 = 43
6559 18:05:46.552054 DQM Delay:
6560 18:05:46.552431 DQM0 = 9, DQM1 = 15
6561 18:05:46.555112 DQ Delay:
6562 18:05:46.558450 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6563 18:05:46.558882 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6564 18:05:46.561635 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6565 18:05:46.564712 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6566 18:05:46.565159
6567 18:05:46.568367
6568 18:05:46.568835 ==
6569 18:05:46.571540 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 18:05:46.574750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 18:05:46.575188 ==
6572 18:05:46.575530
6573 18:05:46.575845
6574 18:05:46.577984 TX Vref Scan disable
6575 18:05:46.578419 == TX Byte 0 ==
6576 18:05:46.581563 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6577 18:05:46.587808 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6578 18:05:46.588081 == TX Byte 1 ==
6579 18:05:46.591024 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6580 18:05:46.598008 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6581 18:05:46.598215 ==
6582 18:05:46.601246 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 18:05:46.604459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 18:05:46.604629 ==
6585 18:05:46.604739
6586 18:05:46.604839
6587 18:05:46.607577 TX Vref Scan disable
6588 18:05:46.607710 == TX Byte 0 ==
6589 18:05:46.610651 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6590 18:05:46.617624 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6591 18:05:46.618006 == TX Byte 1 ==
6592 18:05:46.620881 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6593 18:05:46.628238 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6594 18:05:46.628617
6595 18:05:46.628953 [DATLAT]
6596 18:05:46.629155 Freq=400, CH0 RK1
6597 18:05:46.629359
6598 18:05:46.631497 DATLAT Default: 0xe
6599 18:05:46.634519 0, 0xFFFF, sum = 0
6600 18:05:46.634782 1, 0xFFFF, sum = 0
6601 18:05:46.637586 2, 0xFFFF, sum = 0
6602 18:05:46.637836 3, 0xFFFF, sum = 0
6603 18:05:46.640714 4, 0xFFFF, sum = 0
6604 18:05:46.640965 5, 0xFFFF, sum = 0
6605 18:05:46.644369 6, 0xFFFF, sum = 0
6606 18:05:46.644659 7, 0xFFFF, sum = 0
6607 18:05:46.647911 8, 0xFFFF, sum = 0
6608 18:05:46.648324 9, 0xFFFF, sum = 0
6609 18:05:46.650817 10, 0xFFFF, sum = 0
6610 18:05:46.651228 11, 0xFFFF, sum = 0
6611 18:05:46.654251 12, 0xFFFF, sum = 0
6612 18:05:46.654663 13, 0x0, sum = 1
6613 18:05:46.657742 14, 0x0, sum = 2
6614 18:05:46.658148 15, 0x0, sum = 3
6615 18:05:46.661349 16, 0x0, sum = 4
6616 18:05:46.661756 best_step = 14
6617 18:05:46.662072
6618 18:05:46.662446 ==
6619 18:05:46.664692 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 18:05:46.667872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 18:05:46.670946 ==
6622 18:05:46.671428 RX Vref Scan: 0
6623 18:05:46.671813
6624 18:05:46.674426 RX Vref 0 -> 0, step: 1
6625 18:05:46.675000
6626 18:05:46.677662 RX Delay -327 -> 252, step: 8
6627 18:05:46.684304 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6628 18:05:46.687538 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6629 18:05:46.691501 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6630 18:05:46.694029 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6631 18:05:46.701119 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6632 18:05:46.704249 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6633 18:05:46.707618 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6634 18:05:46.711528 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6635 18:05:46.714437 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6636 18:05:46.720752 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6637 18:05:46.723978 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6638 18:05:46.727816 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6639 18:05:46.730566 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6640 18:05:46.737421 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6641 18:05:46.740608 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6642 18:05:46.743696 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6643 18:05:46.743999 ==
6644 18:05:46.747024 Dram Type= 6, Freq= 0, CH_0, rank 1
6645 18:05:46.753590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 18:05:46.753795 ==
6647 18:05:46.754005 DQS Delay:
6648 18:05:46.756641 DQS0 = 28, DQS1 = 44
6649 18:05:46.756820 DQM Delay:
6650 18:05:46.756994 DQM0 = 10, DQM1 = 14
6651 18:05:46.760074 DQ Delay:
6652 18:05:46.763668 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6653 18:05:46.766766 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6654 18:05:46.766879 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6655 18:05:46.770071 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6656 18:05:46.773822
6657 18:05:46.773907
6658 18:05:46.780094 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6659 18:05:46.783423 CH0 RK1: MR19=C0C, MR18=B86C
6660 18:05:46.790372 CH0_RK1: MR19=0xC0C, MR18=0xB86C, DQSOSC=386, MR23=63, INC=396, DEC=264
6661 18:05:46.793569 [RxdqsGatingPostProcess] freq 400
6662 18:05:46.797117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6663 18:05:46.800179 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 18:05:46.803375 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 18:05:46.806852 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 18:05:46.810464 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 18:05:46.813842 best DQS0 dly(2T, 0.5T) = (0, 10)
6668 18:05:46.817187 best DQS1 dly(2T, 0.5T) = (0, 10)
6669 18:05:46.819782 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6670 18:05:46.823201 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6671 18:05:46.826744 Pre-setting of DQS Precalculation
6672 18:05:46.830193 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6673 18:05:46.830358 ==
6674 18:05:46.833478 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 18:05:46.840407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 18:05:46.840658 ==
6677 18:05:46.843745 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6678 18:05:46.850062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6679 18:05:46.853682 [CA 0] Center 36 (8~64) winsize 57
6680 18:05:46.856655 [CA 1] Center 36 (8~64) winsize 57
6681 18:05:46.859816 [CA 2] Center 36 (8~64) winsize 57
6682 18:05:46.863513 [CA 3] Center 36 (8~64) winsize 57
6683 18:05:46.866532 [CA 4] Center 36 (8~64) winsize 57
6684 18:05:46.869909 [CA 5] Center 36 (8~64) winsize 57
6685 18:05:46.870522
6686 18:05:46.872953 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6687 18:05:46.873602
6688 18:05:46.876300 [CATrainingPosCal] consider 1 rank data
6689 18:05:46.880200 u2DelayCellTimex100 = 270/100 ps
6690 18:05:46.883544 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 18:05:46.886426 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 18:05:46.890235 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 18:05:46.893359 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 18:05:46.896735 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 18:05:46.900167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 18:05:46.900808
6697 18:05:46.906811 CA PerBit enable=1, Macro0, CA PI delay=36
6698 18:05:46.907387
6699 18:05:46.909769 [CBTSetCACLKResult] CA Dly = 36
6700 18:05:46.910318 CS Dly: 1 (0~32)
6701 18:05:46.910706 ==
6702 18:05:46.913068 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 18:05:46.916357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 18:05:46.916870 ==
6705 18:05:46.923656 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6706 18:05:46.929958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6707 18:05:46.933155 [CA 0] Center 36 (8~64) winsize 57
6708 18:05:46.936590 [CA 1] Center 36 (8~64) winsize 57
6709 18:05:46.940132 [CA 2] Center 36 (8~64) winsize 57
6710 18:05:46.943305 [CA 3] Center 36 (8~64) winsize 57
6711 18:05:46.946502 [CA 4] Center 36 (8~64) winsize 57
6712 18:05:46.947079 [CA 5] Center 36 (8~64) winsize 57
6713 18:05:46.949712
6714 18:05:46.952890 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6715 18:05:46.953464
6716 18:05:46.956416 [CATrainingPosCal] consider 2 rank data
6717 18:05:46.959783 u2DelayCellTimex100 = 270/100 ps
6718 18:05:46.962868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 18:05:46.966347 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 18:05:46.969515 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 18:05:46.972959 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 18:05:46.976173 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 18:05:46.979564 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 18:05:46.980240
6725 18:05:46.983051 CA PerBit enable=1, Macro0, CA PI delay=36
6726 18:05:46.983626
6727 18:05:46.985977 [CBTSetCACLKResult] CA Dly = 36
6728 18:05:46.989759 CS Dly: 1 (0~32)
6729 18:05:46.990238
6730 18:05:46.992931 ----->DramcWriteLeveling(PI) begin...
6731 18:05:46.993418 ==
6732 18:05:46.996258 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 18:05:46.999565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 18:05:47.000098 ==
6735 18:05:47.002753 Write leveling (Byte 0): 40 => 8
6736 18:05:47.006640 Write leveling (Byte 1): 32 => 0
6737 18:05:47.009511 DramcWriteLeveling(PI) end<-----
6738 18:05:47.010082
6739 18:05:47.010539 ==
6740 18:05:47.012752 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 18:05:47.016096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 18:05:47.016526 ==
6743 18:05:47.019318 [Gating] SW mode calibration
6744 18:05:47.026245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6745 18:05:47.033040 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6746 18:05:47.036285 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 18:05:47.039567 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6748 18:05:47.045762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 18:05:47.049093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 18:05:47.052337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 18:05:47.059563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 18:05:47.062884 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 18:05:47.066452 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 18:05:47.072720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 18:05:47.073323 Total UI for P1: 0, mck2ui 16
6756 18:05:47.079275 best dqsien dly found for B0: ( 0, 14, 24)
6757 18:05:47.079764 Total UI for P1: 0, mck2ui 16
6758 18:05:47.085823 best dqsien dly found for B1: ( 0, 14, 24)
6759 18:05:47.089279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6760 18:05:47.092751 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6761 18:05:47.093185
6762 18:05:47.095873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 18:05:47.099424 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6764 18:05:47.102532 [Gating] SW calibration Done
6765 18:05:47.102961 ==
6766 18:05:47.105707 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 18:05:47.109718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 18:05:47.110520 ==
6769 18:05:47.112892 RX Vref Scan: 0
6770 18:05:47.113362
6771 18:05:47.113736 RX Vref 0 -> 0, step: 1
6772 18:05:47.114088
6773 18:05:47.116182 RX Delay -410 -> 252, step: 16
6774 18:05:47.122856 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6775 18:05:47.126258 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6776 18:05:47.129270 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6777 18:05:47.132788 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6778 18:05:47.139039 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6779 18:05:47.142560 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6780 18:05:47.145668 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6781 18:05:47.148932 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6782 18:05:47.156035 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6783 18:05:47.159406 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6784 18:05:47.162611 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6785 18:05:47.165868 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6786 18:05:47.172329 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6787 18:05:47.175318 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6788 18:05:47.178846 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6789 18:05:47.182319 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6790 18:05:47.185384 ==
6791 18:05:47.188813 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 18:05:47.191860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 18:05:47.192303 ==
6794 18:05:47.192701 DQS Delay:
6795 18:05:47.195378 DQS0 = 27, DQS1 = 35
6796 18:05:47.195973 DQM Delay:
6797 18:05:47.198821 DQM0 = 8, DQM1 = 10
6798 18:05:47.199257 DQ Delay:
6799 18:05:47.201757 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6800 18:05:47.205282 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6801 18:05:47.208722 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6802 18:05:47.211647 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =16
6803 18:05:47.212085
6804 18:05:47.212428
6805 18:05:47.212806 ==
6806 18:05:47.215605 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 18:05:47.218851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 18:05:47.219285 ==
6809 18:05:47.219631
6810 18:05:47.219949
6811 18:05:47.222054 TX Vref Scan disable
6812 18:05:47.222482 == TX Byte 0 ==
6813 18:05:47.225328 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 18:05:47.231685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 18:05:47.232123 == TX Byte 1 ==
6816 18:05:47.235475 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6817 18:05:47.241899 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6818 18:05:47.242337 ==
6819 18:05:47.245178 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 18:05:47.248667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 18:05:47.249078 ==
6822 18:05:47.249434
6823 18:05:47.249814
6824 18:05:47.251897 TX Vref Scan disable
6825 18:05:47.252456 == TX Byte 0 ==
6826 18:05:47.258878 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 18:05:47.261976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 18:05:47.262510 == TX Byte 1 ==
6829 18:05:47.268493 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6830 18:05:47.272438 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6831 18:05:47.273020
6832 18:05:47.273370 [DATLAT]
6833 18:05:47.275253 Freq=400, CH1 RK0
6834 18:05:47.275785
6835 18:05:47.276129 DATLAT Default: 0xf
6836 18:05:47.278679 0, 0xFFFF, sum = 0
6837 18:05:47.279115 1, 0xFFFF, sum = 0
6838 18:05:47.281922 2, 0xFFFF, sum = 0
6839 18:05:47.282375 3, 0xFFFF, sum = 0
6840 18:05:47.285092 4, 0xFFFF, sum = 0
6841 18:05:47.285521 5, 0xFFFF, sum = 0
6842 18:05:47.288365 6, 0xFFFF, sum = 0
6843 18:05:47.288819 7, 0xFFFF, sum = 0
6844 18:05:47.291475 8, 0xFFFF, sum = 0
6845 18:05:47.291908 9, 0xFFFF, sum = 0
6846 18:05:47.295216 10, 0xFFFF, sum = 0
6847 18:05:47.298251 11, 0xFFFF, sum = 0
6848 18:05:47.298689 12, 0xFFFF, sum = 0
6849 18:05:47.301478 13, 0x0, sum = 1
6850 18:05:47.302025 14, 0x0, sum = 2
6851 18:05:47.302377 15, 0x0, sum = 3
6852 18:05:47.304820 16, 0x0, sum = 4
6853 18:05:47.305249 best_step = 14
6854 18:05:47.305589
6855 18:05:47.308407 ==
6856 18:05:47.309021 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 18:05:47.314652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 18:05:47.315157 ==
6859 18:05:47.315509 RX Vref Scan: 1
6860 18:05:47.315832
6861 18:05:47.317801 RX Vref 0 -> 0, step: 1
6862 18:05:47.318232
6863 18:05:47.321488 RX Delay -311 -> 252, step: 8
6864 18:05:47.321924
6865 18:05:47.324679 Set Vref, RX VrefLevel [Byte0]: 51
6866 18:05:47.327904 [Byte1]: 49
6867 18:05:47.331762
6868 18:05:47.332195 Final RX Vref Byte 0 = 51 to rank0
6869 18:05:47.334951 Final RX Vref Byte 1 = 49 to rank0
6870 18:05:47.338555 Final RX Vref Byte 0 = 51 to rank1
6871 18:05:47.341758 Final RX Vref Byte 1 = 49 to rank1==
6872 18:05:47.345095 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 18:05:47.351719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 18:05:47.352253 ==
6875 18:05:47.352644 DQS Delay:
6876 18:05:47.354835 DQS0 = 32, DQS1 = 40
6877 18:05:47.355369 DQM Delay:
6878 18:05:47.355816 DQM0 = 11, DQM1 = 11
6879 18:05:47.358200 DQ Delay:
6880 18:05:47.361047 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6881 18:05:47.361480 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6882 18:05:47.364904 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6883 18:05:47.368097 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6884 18:05:47.368677
6885 18:05:47.371631
6886 18:05:47.378143 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6887 18:05:47.381410 CH1 RK0: MR19=C0C, MR18=94CF
6888 18:05:47.387669 CH1_RK0: MR19=0xC0C, MR18=0x94CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6889 18:05:47.388235 ==
6890 18:05:47.391154 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 18:05:47.394878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 18:05:47.395452 ==
6893 18:05:47.397949 [Gating] SW mode calibration
6894 18:05:47.405009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6895 18:05:47.411592 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6896 18:05:47.414908 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 18:05:47.417977 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6898 18:05:47.421492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 18:05:47.428031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 18:05:47.430979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 18:05:47.434534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 18:05:47.440764 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 18:05:47.444928 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 18:05:47.448201 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 18:05:47.451300 Total UI for P1: 0, mck2ui 16
6906 18:05:47.454512 best dqsien dly found for B0: ( 0, 14, 24)
6907 18:05:47.458067 Total UI for P1: 0, mck2ui 16
6908 18:05:47.461313 best dqsien dly found for B1: ( 0, 14, 24)
6909 18:05:47.464722 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6910 18:05:47.468091 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6911 18:05:47.471306
6912 18:05:47.474227 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 18:05:47.477461 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6914 18:05:47.481209 [Gating] SW calibration Done
6915 18:05:47.481651 ==
6916 18:05:47.484868 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 18:05:47.487974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 18:05:47.488679 ==
6919 18:05:47.489043 RX Vref Scan: 0
6920 18:05:47.490911
6921 18:05:47.491393 RX Vref 0 -> 0, step: 1
6922 18:05:47.491790
6923 18:05:47.493967 RX Delay -410 -> 252, step: 16
6924 18:05:47.497502 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6925 18:05:47.504176 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6926 18:05:47.507259 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6927 18:05:47.510985 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6928 18:05:47.514145 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6929 18:05:47.521015 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6930 18:05:47.524286 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6931 18:05:47.527386 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6932 18:05:47.531132 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6933 18:05:47.537168 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6934 18:05:47.540640 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6935 18:05:47.544243 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6936 18:05:47.547621 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6937 18:05:47.553862 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6938 18:05:47.557225 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6939 18:05:47.560451 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6940 18:05:47.561041 ==
6941 18:05:47.564297 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 18:05:47.571205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 18:05:47.571747 ==
6944 18:05:47.572096 DQS Delay:
6945 18:05:47.572420 DQS0 = 35, DQS1 = 35
6946 18:05:47.574420 DQM Delay:
6947 18:05:47.574851 DQM0 = 16, DQM1 = 12
6948 18:05:47.577426 DQ Delay:
6949 18:05:47.581062 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6950 18:05:47.581598 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6951 18:05:47.584152 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6952 18:05:47.587418 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6953 18:05:47.587956
6954 18:05:47.590659
6955 18:05:47.591197 ==
6956 18:05:47.594015 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 18:05:47.597271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 18:05:47.597722 ==
6959 18:05:47.598081
6960 18:05:47.598403
6961 18:05:47.600670 TX Vref Scan disable
6962 18:05:47.601202 == TX Byte 0 ==
6963 18:05:47.603666 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6964 18:05:47.610714 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6965 18:05:47.611145 == TX Byte 1 ==
6966 18:05:47.613734 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6967 18:05:47.620311 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6968 18:05:47.620939 ==
6969 18:05:47.623971 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 18:05:47.627073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 18:05:47.627602 ==
6972 18:05:47.627956
6973 18:05:47.628341
6974 18:05:47.630633 TX Vref Scan disable
6975 18:05:47.631089 == TX Byte 0 ==
6976 18:05:47.633673 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6977 18:05:47.640236 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6978 18:05:47.640865 == TX Byte 1 ==
6979 18:05:47.643819 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6980 18:05:47.650258 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6981 18:05:47.650694
6982 18:05:47.651088 [DATLAT]
6983 18:05:47.651420 Freq=400, CH1 RK1
6984 18:05:47.653591
6985 18:05:47.654079 DATLAT Default: 0xe
6986 18:05:47.657115 0, 0xFFFF, sum = 0
6987 18:05:47.657653 1, 0xFFFF, sum = 0
6988 18:05:47.660502 2, 0xFFFF, sum = 0
6989 18:05:47.661218 3, 0xFFFF, sum = 0
6990 18:05:47.663737 4, 0xFFFF, sum = 0
6991 18:05:47.664273 5, 0xFFFF, sum = 0
6992 18:05:47.667076 6, 0xFFFF, sum = 0
6993 18:05:47.667614 7, 0xFFFF, sum = 0
6994 18:05:47.670232 8, 0xFFFF, sum = 0
6995 18:05:47.670767 9, 0xFFFF, sum = 0
6996 18:05:47.673414 10, 0xFFFF, sum = 0
6997 18:05:47.673951 11, 0xFFFF, sum = 0
6998 18:05:47.676827 12, 0xFFFF, sum = 0
6999 18:05:47.677369 13, 0x0, sum = 1
7000 18:05:47.680144 14, 0x0, sum = 2
7001 18:05:47.680726 15, 0x0, sum = 3
7002 18:05:47.683136 16, 0x0, sum = 4
7003 18:05:47.683571 best_step = 14
7004 18:05:47.683912
7005 18:05:47.684230 ==
7006 18:05:47.687229 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 18:05:47.693625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 18:05:47.694164 ==
7009 18:05:47.694535 RX Vref Scan: 0
7010 18:05:47.694871
7011 18:05:47.696818 RX Vref 0 -> 0, step: 1
7012 18:05:47.697346
7013 18:05:47.700067 RX Delay -311 -> 252, step: 8
7014 18:05:47.706737 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7015 18:05:47.709612 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7016 18:05:47.713207 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7017 18:05:47.716478 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7018 18:05:47.723553 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7019 18:05:47.726768 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7020 18:05:47.729750 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7021 18:05:47.733527 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7022 18:05:47.739551 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7023 18:05:47.742842 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7024 18:05:47.746718 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7025 18:05:47.749898 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
7026 18:05:47.756841 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7027 18:05:47.760139 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7028 18:05:47.762951 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7029 18:05:47.766264 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7030 18:05:47.766736 ==
7031 18:05:47.769508 Dram Type= 6, Freq= 0, CH_1, rank 1
7032 18:05:47.776570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7033 18:05:47.777005 ==
7034 18:05:47.777348 DQS Delay:
7035 18:05:47.779810 DQS0 = 32, DQS1 = 36
7036 18:05:47.780237 DQM Delay:
7037 18:05:47.783035 DQM0 = 11, DQM1 = 11
7038 18:05:47.783461 DQ Delay:
7039 18:05:47.786187 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7040 18:05:47.789347 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
7041 18:05:47.792501 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7042 18:05:47.795793 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
7043 18:05:47.796023
7044 18:05:47.796206
7045 18:05:47.802302 [DQSOSCAuto] RK1, (LSB)MR18= 0xa952, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7046 18:05:47.805749 CH1 RK1: MR19=C0C, MR18=A952
7047 18:05:47.812520 CH1_RK1: MR19=0xC0C, MR18=0xA952, DQSOSC=388, MR23=63, INC=392, DEC=261
7048 18:05:47.815541 [RxdqsGatingPostProcess] freq 400
7049 18:05:47.819148 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7050 18:05:47.822310 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 18:05:47.825819 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 18:05:47.829163 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 18:05:47.832215 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 18:05:47.835788 best DQS0 dly(2T, 0.5T) = (0, 10)
7055 18:05:47.839079 best DQS1 dly(2T, 0.5T) = (0, 10)
7056 18:05:47.842301 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7057 18:05:47.845349 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7058 18:05:47.848858 Pre-setting of DQS Precalculation
7059 18:05:47.852198 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7060 18:05:47.862011 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7061 18:05:47.868557 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7062 18:05:47.868646
7063 18:05:47.868713
7064 18:05:47.871838 [Calibration Summary] 800 Mbps
7065 18:05:47.871922 CH 0, Rank 0
7066 18:05:47.875115 SW Impedance : PASS
7067 18:05:47.875199 DUTY Scan : NO K
7068 18:05:47.878814 ZQ Calibration : PASS
7069 18:05:47.881994 Jitter Meter : NO K
7070 18:05:47.882081 CBT Training : PASS
7071 18:05:47.885249 Write leveling : PASS
7072 18:05:47.888520 RX DQS gating : PASS
7073 18:05:47.888684 RX DQ/DQS(RDDQC) : PASS
7074 18:05:47.891885 TX DQ/DQS : PASS
7075 18:05:47.892020 RX DATLAT : PASS
7076 18:05:47.895165 RX DQ/DQS(Engine): PASS
7077 18:05:47.898897 TX OE : NO K
7078 18:05:47.899056 All Pass.
7079 18:05:47.899151
7080 18:05:47.902233 CH 0, Rank 1
7081 18:05:47.902365 SW Impedance : PASS
7082 18:05:47.905472 DUTY Scan : NO K
7083 18:05:47.905580 ZQ Calibration : PASS
7084 18:05:47.908472 Jitter Meter : NO K
7085 18:05:47.911770 CBT Training : PASS
7086 18:05:47.911876 Write leveling : NO K
7087 18:05:47.915052 RX DQS gating : PASS
7088 18:05:47.918645 RX DQ/DQS(RDDQC) : PASS
7089 18:05:47.918731 TX DQ/DQS : PASS
7090 18:05:47.921798 RX DATLAT : PASS
7091 18:05:47.925106 RX DQ/DQS(Engine): PASS
7092 18:05:47.925192 TX OE : NO K
7093 18:05:47.928993 All Pass.
7094 18:05:47.929617
7095 18:05:47.930162 CH 1, Rank 0
7096 18:05:47.931882 SW Impedance : PASS
7097 18:05:47.932349 DUTY Scan : NO K
7098 18:05:47.935774 ZQ Calibration : PASS
7099 18:05:47.938564 Jitter Meter : NO K
7100 18:05:47.938997 CBT Training : PASS
7101 18:05:47.942251 Write leveling : PASS
7102 18:05:47.945230 RX DQS gating : PASS
7103 18:05:47.945658 RX DQ/DQS(RDDQC) : PASS
7104 18:05:47.948332 TX DQ/DQS : PASS
7105 18:05:47.951756 RX DATLAT : PASS
7106 18:05:47.952386 RX DQ/DQS(Engine): PASS
7107 18:05:47.955035 TX OE : NO K
7108 18:05:47.955496 All Pass.
7109 18:05:47.956187
7110 18:05:47.958357 CH 1, Rank 1
7111 18:05:47.958798 SW Impedance : PASS
7112 18:05:47.961554 DUTY Scan : NO K
7113 18:05:47.961991 ZQ Calibration : PASS
7114 18:05:47.965081 Jitter Meter : NO K
7115 18:05:47.968282 CBT Training : PASS
7116 18:05:47.968970 Write leveling : NO K
7117 18:05:47.971528 RX DQS gating : PASS
7118 18:05:47.975026 RX DQ/DQS(RDDQC) : PASS
7119 18:05:47.975603 TX DQ/DQS : PASS
7120 18:05:47.978192 RX DATLAT : PASS
7121 18:05:47.981897 RX DQ/DQS(Engine): PASS
7122 18:05:47.982210 TX OE : NO K
7123 18:05:47.984638 All Pass.
7124 18:05:47.984979
7125 18:05:47.985235 DramC Write-DBI off
7126 18:05:47.988436 PER_BANK_REFRESH: Hybrid Mode
7127 18:05:47.988757 TX_TRACKING: ON
7128 18:05:47.998115 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7129 18:05:48.001472 [FAST_K] Save calibration result to emmc
7130 18:05:48.004608 dramc_set_vcore_voltage set vcore to 725000
7131 18:05:48.008338 Read voltage for 1600, 0
7132 18:05:48.008458 Vio18 = 0
7133 18:05:48.011571 Vcore = 725000
7134 18:05:48.011678 Vdram = 0
7135 18:05:48.011762 Vddq = 0
7136 18:05:48.014753 Vmddr = 0
7137 18:05:48.018003 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7138 18:05:48.024659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7139 18:05:48.024758 MEM_TYPE=3, freq_sel=13
7140 18:05:48.027725 sv_algorithm_assistance_LP4_3733
7141 18:05:48.034581 ============ PULL DRAM RESETB DOWN ============
7142 18:05:48.037685 ========== PULL DRAM RESETB DOWN end =========
7143 18:05:48.041321 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7144 18:05:48.044428 ===================================
7145 18:05:48.048125 LPDDR4 DRAM CONFIGURATION
7146 18:05:48.051094 ===================================
7147 18:05:48.051190 EX_ROW_EN[0] = 0x0
7148 18:05:48.054579 EX_ROW_EN[1] = 0x0
7149 18:05:48.058159 LP4Y_EN = 0x0
7150 18:05:48.058248 WORK_FSP = 0x1
7151 18:05:48.061414 WL = 0x5
7152 18:05:48.061501 RL = 0x5
7153 18:05:48.064569 BL = 0x2
7154 18:05:48.064656 RPST = 0x0
7155 18:05:48.067933 RD_PRE = 0x0
7156 18:05:48.068019 WR_PRE = 0x1
7157 18:05:48.071234 WR_PST = 0x1
7158 18:05:48.071320 DBI_WR = 0x0
7159 18:05:48.074484 DBI_RD = 0x0
7160 18:05:48.074571 OTF = 0x1
7161 18:05:48.077742 ===================================
7162 18:05:48.081548 ===================================
7163 18:05:48.084810 ANA top config
7164 18:05:48.088019 ===================================
7165 18:05:48.088108 DLL_ASYNC_EN = 0
7166 18:05:48.091281 ALL_SLAVE_EN = 0
7167 18:05:48.094628 NEW_RANK_MODE = 1
7168 18:05:48.097946 DLL_IDLE_MODE = 1
7169 18:05:48.101360 LP45_APHY_COMB_EN = 1
7170 18:05:48.101460 TX_ODT_DIS = 0
7171 18:05:48.104441 NEW_8X_MODE = 1
7172 18:05:48.107745 ===================================
7173 18:05:48.110967 ===================================
7174 18:05:48.114317 data_rate = 3200
7175 18:05:48.117467 CKR = 1
7176 18:05:48.121287 DQ_P2S_RATIO = 8
7177 18:05:48.124446 ===================================
7178 18:05:48.124591 CA_P2S_RATIO = 8
7179 18:05:48.127548 DQ_CA_OPEN = 0
7180 18:05:48.130696 DQ_SEMI_OPEN = 0
7181 18:05:48.134338 CA_SEMI_OPEN = 0
7182 18:05:48.137447 CA_FULL_RATE = 0
7183 18:05:48.141049 DQ_CKDIV4_EN = 0
7184 18:05:48.141135 CA_CKDIV4_EN = 0
7185 18:05:48.144239 CA_PREDIV_EN = 0
7186 18:05:48.147422 PH8_DLY = 12
7187 18:05:48.150981 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7188 18:05:48.154101 DQ_AAMCK_DIV = 4
7189 18:05:48.157173 CA_AAMCK_DIV = 4
7190 18:05:48.157262 CA_ADMCK_DIV = 4
7191 18:05:48.160895 DQ_TRACK_CA_EN = 0
7192 18:05:48.164060 CA_PICK = 1600
7193 18:05:48.167442 CA_MCKIO = 1600
7194 18:05:48.170568 MCKIO_SEMI = 0
7195 18:05:48.173854 PLL_FREQ = 3068
7196 18:05:48.177130 DQ_UI_PI_RATIO = 32
7197 18:05:48.180351 CA_UI_PI_RATIO = 0
7198 18:05:48.183677 ===================================
7199 18:05:48.186949 ===================================
7200 18:05:48.187038 memory_type:LPDDR4
7201 18:05:48.190135 GP_NUM : 10
7202 18:05:48.193481 SRAM_EN : 1
7203 18:05:48.193565 MD32_EN : 0
7204 18:05:48.196754 ===================================
7205 18:05:48.200107 [ANA_INIT] >>>>>>>>>>>>>>
7206 18:05:48.203294 <<<<<< [CONFIGURE PHASE]: ANA_TX
7207 18:05:48.206704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7208 18:05:48.210317 ===================================
7209 18:05:48.213516 data_rate = 3200,PCW = 0X7600
7210 18:05:48.216789 ===================================
7211 18:05:48.220130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7212 18:05:48.223241 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 18:05:48.230001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7214 18:05:48.233586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7215 18:05:48.236669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7216 18:05:48.240008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7217 18:05:48.243082 [ANA_INIT] flow start
7218 18:05:48.246684 [ANA_INIT] PLL >>>>>>>>
7219 18:05:48.246763 [ANA_INIT] PLL <<<<<<<<
7220 18:05:48.249859 [ANA_INIT] MIDPI >>>>>>>>
7221 18:05:48.253105 [ANA_INIT] MIDPI <<<<<<<<
7222 18:05:48.256386 [ANA_INIT] DLL >>>>>>>>
7223 18:05:48.256471 [ANA_INIT] DLL <<<<<<<<
7224 18:05:48.259951 [ANA_INIT] flow end
7225 18:05:48.263414 ============ LP4 DIFF to SE enter ============
7226 18:05:48.266593 ============ LP4 DIFF to SE exit ============
7227 18:05:48.269976 [ANA_INIT] <<<<<<<<<<<<<
7228 18:05:48.273290 [Flow] Enable top DCM control >>>>>
7229 18:05:48.276511 [Flow] Enable top DCM control <<<<<
7230 18:05:48.279863 Enable DLL master slave shuffle
7231 18:05:48.283042 ==============================================================
7232 18:05:48.286383 Gating Mode config
7233 18:05:48.293014 ==============================================================
7234 18:05:48.293100 Config description:
7235 18:05:48.303379 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7236 18:05:48.309857 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7237 18:05:48.316193 SELPH_MODE 0: By rank 1: By Phase
7238 18:05:48.319442 ==============================================================
7239 18:05:48.323246 GAT_TRACK_EN = 1
7240 18:05:48.326349 RX_GATING_MODE = 2
7241 18:05:48.329531 RX_GATING_TRACK_MODE = 2
7242 18:05:48.332801 SELPH_MODE = 1
7243 18:05:48.336297 PICG_EARLY_EN = 1
7244 18:05:48.339451 VALID_LAT_VALUE = 1
7245 18:05:48.343107 ==============================================================
7246 18:05:48.346210 Enter into Gating configuration >>>>
7247 18:05:48.349786 Exit from Gating configuration <<<<
7248 18:05:48.352858 Enter into DVFS_PRE_config >>>>>
7249 18:05:48.366014 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7250 18:05:48.369618 Exit from DVFS_PRE_config <<<<<
7251 18:05:48.372859 Enter into PICG configuration >>>>
7252 18:05:48.372944 Exit from PICG configuration <<<<
7253 18:05:48.376156 [RX_INPUT] configuration >>>>>
7254 18:05:48.379597 [RX_INPUT] configuration <<<<<
7255 18:05:48.385927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7256 18:05:48.389181 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7257 18:05:48.395778 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 18:05:48.402988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 18:05:48.409501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7260 18:05:48.415934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7261 18:05:48.419057 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7262 18:05:48.422560 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7263 18:05:48.425748 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7264 18:05:48.432643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7265 18:05:48.435761 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7266 18:05:48.439300 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 18:05:48.442473 ===================================
7268 18:05:48.445638 LPDDR4 DRAM CONFIGURATION
7269 18:05:48.449088 ===================================
7270 18:05:48.452313 EX_ROW_EN[0] = 0x0
7271 18:05:48.452397 EX_ROW_EN[1] = 0x0
7272 18:05:48.455995 LP4Y_EN = 0x0
7273 18:05:48.456103 WORK_FSP = 0x1
7274 18:05:48.459055 WL = 0x5
7275 18:05:48.459153 RL = 0x5
7276 18:05:48.462235 BL = 0x2
7277 18:05:48.462354 RPST = 0x0
7278 18:05:48.465835 RD_PRE = 0x0
7279 18:05:48.465919 WR_PRE = 0x1
7280 18:05:48.468841 WR_PST = 0x1
7281 18:05:48.468925 DBI_WR = 0x0
7282 18:05:48.471950 DBI_RD = 0x0
7283 18:05:48.472060 OTF = 0x1
7284 18:05:48.475600 ===================================
7285 18:05:48.482235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7286 18:05:48.485489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7287 18:05:48.488860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7288 18:05:48.492139 ===================================
7289 18:05:48.495491 LPDDR4 DRAM CONFIGURATION
7290 18:05:48.498798 ===================================
7291 18:05:48.502092 EX_ROW_EN[0] = 0x10
7292 18:05:48.502178 EX_ROW_EN[1] = 0x0
7293 18:05:48.505407 LP4Y_EN = 0x0
7294 18:05:48.505492 WORK_FSP = 0x1
7295 18:05:48.508693 WL = 0x5
7296 18:05:48.508778 RL = 0x5
7297 18:05:48.512092 BL = 0x2
7298 18:05:48.512177 RPST = 0x0
7299 18:05:48.515304 RD_PRE = 0x0
7300 18:05:48.515390 WR_PRE = 0x1
7301 18:05:48.518647 WR_PST = 0x1
7302 18:05:48.518732 DBI_WR = 0x0
7303 18:05:48.521853 DBI_RD = 0x0
7304 18:05:48.521938 OTF = 0x1
7305 18:05:48.525126 ===================================
7306 18:05:48.531620 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7307 18:05:48.531707 ==
7308 18:05:48.535391 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 18:05:48.541928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 18:05:48.542015 ==
7311 18:05:48.542084 [Duty_Offset_Calibration]
7312 18:05:48.545065 B0:2 B1:0 CA:1
7313 18:05:48.545150
7314 18:05:48.548508 [DutyScan_Calibration_Flow] k_type=0
7315 18:05:48.556993
7316 18:05:48.557077 ==CLK 0==
7317 18:05:48.560060 Final CLK duty delay cell = -4
7318 18:05:48.563186 [-4] MAX Duty = 5000%(X100), DQS PI = 34
7319 18:05:48.566829 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7320 18:05:48.570003 [-4] AVG Duty = 4906%(X100)
7321 18:05:48.570089
7322 18:05:48.573143 CH0 CLK Duty spec in!! Max-Min= 187%
7323 18:05:48.576938 [DutyScan_Calibration_Flow] ====Done====
7324 18:05:48.577023
7325 18:05:48.580066 [DutyScan_Calibration_Flow] k_type=1
7326 18:05:48.596291
7327 18:05:48.596374 ==DQS 0 ==
7328 18:05:48.599574 Final DQS duty delay cell = 0
7329 18:05:48.602757 [0] MAX Duty = 5249%(X100), DQS PI = 32
7330 18:05:48.606150 [0] MIN Duty = 4938%(X100), DQS PI = 0
7331 18:05:48.606233 [0] AVG Duty = 5093%(X100)
7332 18:05:48.609392
7333 18:05:48.609468 ==DQS 1 ==
7334 18:05:48.612698 Final DQS duty delay cell = -4
7335 18:05:48.616002 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7336 18:05:48.619259 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7337 18:05:48.622998 [-4] AVG Duty = 4969%(X100)
7338 18:05:48.623086
7339 18:05:48.626329 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7340 18:05:48.626417
7341 18:05:48.629671 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7342 18:05:48.632935 [DutyScan_Calibration_Flow] ====Done====
7343 18:05:48.633021
7344 18:05:48.636014 [DutyScan_Calibration_Flow] k_type=3
7345 18:05:48.653535
7346 18:05:48.653617 ==DQM 0 ==
7347 18:05:48.657132 Final DQM duty delay cell = 0
7348 18:05:48.660254 [0] MAX Duty = 5093%(X100), DQS PI = 26
7349 18:05:48.663494 [0] MIN Duty = 4813%(X100), DQS PI = 50
7350 18:05:48.667144 [0] AVG Duty = 4953%(X100)
7351 18:05:48.667233
7352 18:05:48.667297 ==DQM 1 ==
7353 18:05:48.670436 Final DQM duty delay cell = 0
7354 18:05:48.673536 [0] MAX Duty = 5249%(X100), DQS PI = 44
7355 18:05:48.676602 [0] MIN Duty = 5000%(X100), DQS PI = 18
7356 18:05:48.680278 [0] AVG Duty = 5124%(X100)
7357 18:05:48.680352
7358 18:05:48.683567 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7359 18:05:48.683642
7360 18:05:48.686856 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7361 18:05:48.690126 [DutyScan_Calibration_Flow] ====Done====
7362 18:05:48.690193
7363 18:05:48.693381 [DutyScan_Calibration_Flow] k_type=2
7364 18:05:48.710818
7365 18:05:48.710892 ==DQ 0 ==
7366 18:05:48.713990 Final DQ duty delay cell = 0
7367 18:05:48.717740 [0] MAX Duty = 5124%(X100), DQS PI = 34
7368 18:05:48.721050 [0] MIN Duty = 5000%(X100), DQS PI = 0
7369 18:05:48.721128 [0] AVG Duty = 5062%(X100)
7370 18:05:48.724263
7371 18:05:48.724363 ==DQ 1 ==
7372 18:05:48.727443 Final DQ duty delay cell = 0
7373 18:05:48.730717 [0] MAX Duty = 4969%(X100), DQS PI = 44
7374 18:05:48.733915 [0] MIN Duty = 4875%(X100), DQS PI = 10
7375 18:05:48.733990 [0] AVG Duty = 4922%(X100)
7376 18:05:48.734066
7377 18:05:48.737135 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7378 18:05:48.740459
7379 18:05:48.744212 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7380 18:05:48.747347 [DutyScan_Calibration_Flow] ====Done====
7381 18:05:48.747452 ==
7382 18:05:48.750623 Dram Type= 6, Freq= 0, CH_1, rank 0
7383 18:05:48.754083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7384 18:05:48.754161 ==
7385 18:05:48.757205 [Duty_Offset_Calibration]
7386 18:05:48.757280 B0:0 B1:-1 CA:2
7387 18:05:48.757347
7388 18:05:48.760292 [DutyScan_Calibration_Flow] k_type=0
7389 18:05:48.770988
7390 18:05:48.771082 ==CLK 0==
7391 18:05:48.774552 Final CLK duty delay cell = 0
7392 18:05:48.777537 [0] MAX Duty = 5156%(X100), DQS PI = 42
7393 18:05:48.780721 [0] MIN Duty = 4906%(X100), DQS PI = 12
7394 18:05:48.784442 [0] AVG Duty = 5031%(X100)
7395 18:05:48.784551
7396 18:05:48.787657 CH1 CLK Duty spec in!! Max-Min= 250%
7397 18:05:48.790860 [DutyScan_Calibration_Flow] ====Done====
7398 18:05:48.790965
7399 18:05:48.794157 [DutyScan_Calibration_Flow] k_type=1
7400 18:05:48.810645
7401 18:05:48.810750 ==DQS 0 ==
7402 18:05:48.813936 Final DQS duty delay cell = 0
7403 18:05:48.817412 [0] MAX Duty = 5062%(X100), DQS PI = 8
7404 18:05:48.820775 [0] MIN Duty = 4969%(X100), DQS PI = 50
7405 18:05:48.820851 [0] AVG Duty = 5015%(X100)
7406 18:05:48.824006
7407 18:05:48.824080 ==DQS 1 ==
7408 18:05:48.827295 Final DQS duty delay cell = 0
7409 18:05:48.830825 [0] MAX Duty = 5218%(X100), DQS PI = 32
7410 18:05:48.834149 [0] MIN Duty = 4813%(X100), DQS PI = 4
7411 18:05:48.837349 [0] AVG Duty = 5015%(X100)
7412 18:05:48.837427
7413 18:05:48.840657 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7414 18:05:48.840735
7415 18:05:48.843880 CH1 DQS 1 Duty spec in!! Max-Min= 405%
7416 18:05:48.847496 [DutyScan_Calibration_Flow] ====Done====
7417 18:05:48.847581
7418 18:05:48.850743 [DutyScan_Calibration_Flow] k_type=3
7419 18:05:48.868449
7420 18:05:48.868534 ==DQM 0 ==
7421 18:05:48.871629 Final DQM duty delay cell = 4
7422 18:05:48.874714 [4] MAX Duty = 5125%(X100), DQS PI = 22
7423 18:05:48.878516 [4] MIN Duty = 4969%(X100), DQS PI = 0
7424 18:05:48.878595 [4] AVG Duty = 5047%(X100)
7425 18:05:48.881726
7426 18:05:48.881816 ==DQM 1 ==
7427 18:05:48.884926 Final DQM duty delay cell = 0
7428 18:05:48.888110 [0] MAX Duty = 5281%(X100), DQS PI = 26
7429 18:05:48.891796 [0] MIN Duty = 4875%(X100), DQS PI = 2
7430 18:05:48.891876 [0] AVG Duty = 5078%(X100)
7431 18:05:48.895113
7432 18:05:48.898458 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7433 18:05:48.898530
7434 18:05:48.901670 CH1 DQM 1 Duty spec in!! Max-Min= 406%
7435 18:05:48.904990 [DutyScan_Calibration_Flow] ====Done====
7436 18:05:48.905061
7437 18:05:48.908218 [DutyScan_Calibration_Flow] k_type=2
7438 18:05:48.924984
7439 18:05:48.925068 ==DQ 0 ==
7440 18:05:48.928282 Final DQ duty delay cell = 0
7441 18:05:48.931574 [0] MAX Duty = 5093%(X100), DQS PI = 22
7442 18:05:48.934875 [0] MIN Duty = 4938%(X100), DQS PI = 0
7443 18:05:48.934950 [0] AVG Duty = 5015%(X100)
7444 18:05:48.935013
7445 18:05:48.938511 ==DQ 1 ==
7446 18:05:48.941774 Final DQ duty delay cell = 0
7447 18:05:48.945154 [0] MAX Duty = 5094%(X100), DQS PI = 32
7448 18:05:48.948241 [0] MIN Duty = 4813%(X100), DQS PI = 0
7449 18:05:48.948311 [0] AVG Duty = 4953%(X100)
7450 18:05:48.948385
7451 18:05:48.951594 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7452 18:05:48.954726
7453 18:05:48.958310 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7454 18:05:48.961436 [DutyScan_Calibration_Flow] ====Done====
7455 18:05:48.964702 nWR fixed to 30
7456 18:05:48.964787 [ModeRegInit_LP4] CH0 RK0
7457 18:05:48.968160 [ModeRegInit_LP4] CH0 RK1
7458 18:05:48.971317 [ModeRegInit_LP4] CH1 RK0
7459 18:05:48.971400 [ModeRegInit_LP4] CH1 RK1
7460 18:05:48.974656 match AC timing 5
7461 18:05:48.978195 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7462 18:05:48.984927 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7463 18:05:48.988138 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7464 18:05:48.991155 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7465 18:05:48.997816 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7466 18:05:48.997931 [MiockJmeterHQA]
7467 18:05:48.998028
7468 18:05:49.001170 [DramcMiockJmeter] u1RxGatingPI = 0
7469 18:05:49.004922 0 : 4252, 4027
7470 18:05:49.005004 4 : 4258, 4030
7471 18:05:49.005073 8 : 4257, 4029
7472 18:05:49.007766 12 : 4255, 4029
7473 18:05:49.007841 16 : 4252, 4027
7474 18:05:49.011550 20 : 4253, 4027
7475 18:05:49.011657 24 : 4252, 4027
7476 18:05:49.014789 28 : 4363, 4137
7477 18:05:49.014907 32 : 4252, 4027
7478 18:05:49.018079 36 : 4253, 4027
7479 18:05:49.018187 40 : 4252, 4027
7480 18:05:49.018282 44 : 4258, 4031
7481 18:05:49.021343 48 : 4253, 4027
7482 18:05:49.021445 52 : 4363, 4137
7483 18:05:49.024713 56 : 4363, 4138
7484 18:05:49.024790 60 : 4250, 4027
7485 18:05:49.027866 64 : 4250, 4027
7486 18:05:49.027940 68 : 4253, 4027
7487 18:05:49.031145 72 : 4250, 4027
7488 18:05:49.031254 76 : 4250, 4027
7489 18:05:49.031355 80 : 4361, 4137
7490 18:05:49.034554 84 : 4250, 4027
7491 18:05:49.034654 88 : 4252, 3228
7492 18:05:49.037696 92 : 4250, 0
7493 18:05:49.037794 96 : 4250, 0
7494 18:05:49.037885 100 : 4250, 0
7495 18:05:49.040865 104 : 4252, 0
7496 18:05:49.040964 108 : 4250, 0
7497 18:05:49.044192 112 : 4250, 0
7498 18:05:49.044289 116 : 4250, 0
7499 18:05:49.044379 120 : 4363, 0
7500 18:05:49.047469 124 : 4361, 0
7501 18:05:49.047540 128 : 4360, 0
7502 18:05:49.051220 132 : 4250, 0
7503 18:05:49.051290 136 : 4250, 0
7504 18:05:49.051352 140 : 4250, 0
7505 18:05:49.054046 144 : 4250, 0
7506 18:05:49.054116 148 : 4250, 0
7507 18:05:49.057293 152 : 4250, 0
7508 18:05:49.057398 156 : 4250, 0
7509 18:05:49.057493 160 : 4250, 0
7510 18:05:49.061071 164 : 4250, 0
7511 18:05:49.061173 168 : 4250, 0
7512 18:05:49.061265 172 : 4361, 0
7513 18:05:49.064210 176 : 4361, 0
7514 18:05:49.064309 180 : 4360, 0
7515 18:05:49.067808 184 : 4250, 0
7516 18:05:49.067909 188 : 4250, 0
7517 18:05:49.068001 192 : 4250, 0
7518 18:05:49.070814 196 : 4249, 0
7519 18:05:49.070890 200 : 4250, 5
7520 18:05:49.074356 204 : 4250, 2746
7521 18:05:49.074433 208 : 4253, 4027
7522 18:05:49.077420 212 : 4363, 4137
7523 18:05:49.077494 216 : 4250, 4026
7524 18:05:49.080929 220 : 4250, 4027
7525 18:05:49.081002 224 : 4361, 4137
7526 18:05:49.081097 228 : 4250, 4027
7527 18:05:49.084108 232 : 4249, 4027
7528 18:05:49.084211 236 : 4360, 4138
7529 18:05:49.087251 240 : 4250, 4027
7530 18:05:49.087350 244 : 4250, 4027
7531 18:05:49.090890 248 : 4249, 4027
7532 18:05:49.090966 252 : 4250, 4027
7533 18:05:49.093967 256 : 4250, 4027
7534 18:05:49.094039 260 : 4250, 4027
7535 18:05:49.097161 264 : 4360, 4138
7536 18:05:49.097233 268 : 4250, 4027
7537 18:05:49.100916 272 : 4250, 4027
7538 18:05:49.100991 276 : 4361, 4137
7539 18:05:49.104121 280 : 4250, 4027
7540 18:05:49.104235 284 : 4250, 4027
7541 18:05:49.107387 288 : 4360, 4138
7542 18:05:49.107490 292 : 4250, 4027
7543 18:05:49.107585 296 : 4250, 4027
7544 18:05:49.110610 300 : 4250, 4027
7545 18:05:49.110687 304 : 4250, 4027
7546 18:05:49.113902 308 : 4250, 4027
7547 18:05:49.113973 312 : 4250, 3901
7548 18:05:49.117214 316 : 4360, 2066
7549 18:05:49.117301
7550 18:05:49.120494 MIOCK jitter meter ch=0
7551 18:05:49.120606
7552 18:05:49.120670 1T = (316-92) = 224 dly cells
7553 18:05:49.127005 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7554 18:05:49.127090 ==
7555 18:05:49.130202 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 18:05:49.133562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 18:05:49.133648 ==
7558 18:05:49.140228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 18:05:49.143895 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 18:05:49.150046 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 18:05:49.153673 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 18:05:49.163978 [CA 0] Center 43 (13~73) winsize 61
7563 18:05:49.166870 [CA 1] Center 43 (13~73) winsize 61
7564 18:05:49.170414 [CA 2] Center 38 (8~68) winsize 61
7565 18:05:49.173564 [CA 3] Center 37 (8~67) winsize 60
7566 18:05:49.176997 [CA 4] Center 36 (6~66) winsize 61
7567 18:05:49.180439 [CA 5] Center 35 (5~65) winsize 61
7568 18:05:49.180540
7569 18:05:49.183848 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 18:05:49.183952
7571 18:05:49.186895 [CATrainingPosCal] consider 1 rank data
7572 18:05:49.190060 u2DelayCellTimex100 = 290/100 ps
7573 18:05:49.193734 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7574 18:05:49.200190 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7575 18:05:49.203661 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7576 18:05:49.206953 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7577 18:05:49.210217 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7578 18:05:49.213500 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7579 18:05:49.213577
7580 18:05:49.216753 CA PerBit enable=1, Macro0, CA PI delay=35
7581 18:05:49.216838
7582 18:05:49.220146 [CBTSetCACLKResult] CA Dly = 35
7583 18:05:49.223439 CS Dly: 9 (0~40)
7584 18:05:49.226663 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 18:05:49.229953 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 18:05:49.230041 ==
7587 18:05:49.233260 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 18:05:49.237074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 18:05:49.240335 ==
7590 18:05:49.243645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 18:05:49.246918 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 18:05:49.253434 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 18:05:49.256692 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 18:05:49.267116 [CA 0] Center 43 (13~74) winsize 62
7595 18:05:49.270371 [CA 1] Center 43 (13~73) winsize 61
7596 18:05:49.273678 [CA 2] Center 38 (9~68) winsize 60
7597 18:05:49.276891 [CA 3] Center 38 (9~68) winsize 60
7598 18:05:49.280579 [CA 4] Center 37 (7~67) winsize 61
7599 18:05:49.283587 [CA 5] Center 36 (6~66) winsize 61
7600 18:05:49.283671
7601 18:05:49.287378 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 18:05:49.287498
7603 18:05:49.290466 [CATrainingPosCal] consider 2 rank data
7604 18:05:49.293692 u2DelayCellTimex100 = 290/100 ps
7605 18:05:49.297393 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7606 18:05:49.303719 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7607 18:05:49.306876 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7608 18:05:49.310517 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7609 18:05:49.313637 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7610 18:05:49.316925 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7611 18:05:49.317013
7612 18:05:49.320229 CA PerBit enable=1, Macro0, CA PI delay=35
7613 18:05:49.320349
7614 18:05:49.323476 [CBTSetCACLKResult] CA Dly = 35
7615 18:05:49.326864 CS Dly: 10 (0~43)
7616 18:05:49.330053 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 18:05:49.333212 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 18:05:49.333289
7619 18:05:49.337162 ----->DramcWriteLeveling(PI) begin...
7620 18:05:49.337281 ==
7621 18:05:49.340312 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 18:05:49.346687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 18:05:49.346798 ==
7624 18:05:49.349984 Write leveling (Byte 0): 36 => 36
7625 18:05:49.353132 Write leveling (Byte 1): 30 => 30
7626 18:05:49.353242 DramcWriteLeveling(PI) end<-----
7627 18:05:49.353339
7628 18:05:49.356315 ==
7629 18:05:49.359832 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 18:05:49.363446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 18:05:49.363554 ==
7632 18:05:49.366753 [Gating] SW mode calibration
7633 18:05:49.372896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 18:05:49.376699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 18:05:49.382967 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 18:05:49.386637 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 18:05:49.389777 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7638 18:05:49.396205 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7639 18:05:49.399874 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7640 18:05:49.403070 1 4 20 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
7641 18:05:49.409823 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 18:05:49.412918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 18:05:49.416078 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 18:05:49.422725 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 18:05:49.426060 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7646 18:05:49.429323 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7647 18:05:49.436438 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7648 18:05:49.439736 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7649 18:05:49.443102 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 18:05:49.449574 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 18:05:49.452820 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 18:05:49.456108 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 18:05:49.459429 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7654 18:05:49.465970 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7655 18:05:49.469202 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7656 18:05:49.473091 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7657 18:05:49.479496 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 18:05:49.482727 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 18:05:49.485888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 18:05:49.492614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 18:05:49.496134 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 18:05:49.499229 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 18:05:49.505986 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 18:05:49.509002 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7665 18:05:49.512513 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 18:05:49.519229 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 18:05:49.522354 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 18:05:49.525656 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 18:05:49.532376 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 18:05:49.535541 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 18:05:49.538866 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 18:05:49.545865 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 18:05:49.549085 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 18:05:49.552319 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 18:05:49.558870 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 18:05:49.562056 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 18:05:49.565348 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7678 18:05:49.572276 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7679 18:05:49.575499 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7680 18:05:49.578798 Total UI for P1: 0, mck2ui 16
7681 18:05:49.582208 best dqsien dly found for B0: ( 1, 9, 10)
7682 18:05:49.585373 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7683 18:05:49.592249 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7684 18:05:49.592353 Total UI for P1: 0, mck2ui 16
7685 18:05:49.598497 best dqsien dly found for B1: ( 1, 9, 18)
7686 18:05:49.602121 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7687 18:05:49.605241 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7688 18:05:49.605315
7689 18:05:49.608716 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7690 18:05:49.611870 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7691 18:05:49.615421 [Gating] SW calibration Done
7692 18:05:49.615521 ==
7693 18:05:49.618508 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 18:05:49.622071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 18:05:49.622148 ==
7696 18:05:49.625105 RX Vref Scan: 0
7697 18:05:49.625177
7698 18:05:49.625240 RX Vref 0 -> 0, step: 1
7699 18:05:49.625301
7700 18:05:49.628411 RX Delay 0 -> 252, step: 8
7701 18:05:49.631687 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7702 18:05:49.638611 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7703 18:05:49.641982 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7704 18:05:49.645247 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7705 18:05:49.648480 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7706 18:05:49.651740 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7707 18:05:49.654967 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7708 18:05:49.662044 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7709 18:05:49.665277 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7710 18:05:49.668455 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7711 18:05:49.671810 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7712 18:05:49.678352 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7713 18:05:49.681347 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7714 18:05:49.685068 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7715 18:05:49.688404 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7716 18:05:49.691582 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7717 18:05:49.691686 ==
7718 18:05:49.694683 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 18:05:49.701480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 18:05:49.701566 ==
7721 18:05:49.701633 DQS Delay:
7722 18:05:49.704509 DQS0 = 0, DQS1 = 0
7723 18:05:49.704637 DQM Delay:
7724 18:05:49.708253 DQM0 = 138, DQM1 = 127
7725 18:05:49.708338 DQ Delay:
7726 18:05:49.711370 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7727 18:05:49.714561 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7728 18:05:49.718203 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7729 18:05:49.721291 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7730 18:05:49.721376
7731 18:05:49.721443
7732 18:05:49.721506 ==
7733 18:05:49.724944 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 18:05:49.731187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 18:05:49.731299 ==
7736 18:05:49.731395
7737 18:05:49.731492
7738 18:05:49.731582 TX Vref Scan disable
7739 18:05:49.734945 == TX Byte 0 ==
7740 18:05:49.738175 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7741 18:05:49.744762 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7742 18:05:49.744839 == TX Byte 1 ==
7743 18:05:49.748070 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7744 18:05:49.751859 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7745 18:05:49.755070 ==
7746 18:05:49.758332 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 18:05:49.761574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 18:05:49.761686 ==
7749 18:05:49.775075
7750 18:05:49.778852 TX Vref early break, caculate TX vref
7751 18:05:49.782138 TX Vref=16, minBit 7, minWin=22, winSum=375
7752 18:05:49.785242 TX Vref=18, minBit 2, minWin=23, winSum=384
7753 18:05:49.788352 TX Vref=20, minBit 12, minWin=23, winSum=395
7754 18:05:49.792094 TX Vref=22, minBit 4, minWin=24, winSum=407
7755 18:05:49.795253 TX Vref=24, minBit 2, minWin=25, winSum=414
7756 18:05:49.801888 TX Vref=26, minBit 2, minWin=25, winSum=420
7757 18:05:49.805009 TX Vref=28, minBit 0, minWin=26, winSum=430
7758 18:05:49.808686 TX Vref=30, minBit 2, minWin=25, winSum=422
7759 18:05:49.811789 TX Vref=32, minBit 0, minWin=25, winSum=414
7760 18:05:49.815078 TX Vref=34, minBit 0, minWin=25, winSum=408
7761 18:05:49.818169 TX Vref=36, minBit 0, minWin=24, winSum=391
7762 18:05:49.824930 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7763 18:05:49.825012
7764 18:05:49.828141 Final TX Range 0 Vref 28
7765 18:05:49.828237
7766 18:05:49.828315 ==
7767 18:05:49.831829 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 18:05:49.834787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 18:05:49.834873 ==
7770 18:05:49.834941
7771 18:05:49.838449
7772 18:05:49.838533 TX Vref Scan disable
7773 18:05:49.845085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7774 18:05:49.845171 == TX Byte 0 ==
7775 18:05:49.848361 u2DelayCellOfst[0]=10 cells (3 PI)
7776 18:05:49.851457 u2DelayCellOfst[1]=16 cells (5 PI)
7777 18:05:49.854771 u2DelayCellOfst[2]=10 cells (3 PI)
7778 18:05:49.858135 u2DelayCellOfst[3]=10 cells (3 PI)
7779 18:05:49.861303 u2DelayCellOfst[4]=6 cells (2 PI)
7780 18:05:49.864532 u2DelayCellOfst[5]=0 cells (0 PI)
7781 18:05:49.868263 u2DelayCellOfst[6]=16 cells (5 PI)
7782 18:05:49.871620 u2DelayCellOfst[7]=13 cells (4 PI)
7783 18:05:49.874872 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7784 18:05:49.878075 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7785 18:05:49.881244 == TX Byte 1 ==
7786 18:05:49.884460 u2DelayCellOfst[8]=0 cells (0 PI)
7787 18:05:49.887715 u2DelayCellOfst[9]=0 cells (0 PI)
7788 18:05:49.891097 u2DelayCellOfst[10]=6 cells (2 PI)
7789 18:05:49.891184 u2DelayCellOfst[11]=3 cells (1 PI)
7790 18:05:49.894871 u2DelayCellOfst[12]=13 cells (4 PI)
7791 18:05:49.898043 u2DelayCellOfst[13]=13 cells (4 PI)
7792 18:05:49.901327 u2DelayCellOfst[14]=13 cells (4 PI)
7793 18:05:49.904413 u2DelayCellOfst[15]=10 cells (3 PI)
7794 18:05:49.911166 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7795 18:05:49.914742 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7796 18:05:49.914845 DramC Write-DBI on
7797 18:05:49.914944 ==
7798 18:05:49.918004 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 18:05:49.924274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 18:05:49.924378 ==
7801 18:05:49.924471
7802 18:05:49.924599
7803 18:05:49.924663 TX Vref Scan disable
7804 18:05:49.928480 == TX Byte 0 ==
7805 18:05:49.932153 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7806 18:05:49.935326 == TX Byte 1 ==
7807 18:05:49.938427 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7808 18:05:49.942273 DramC Write-DBI off
7809 18:05:49.942358
7810 18:05:49.942425 [DATLAT]
7811 18:05:49.942496 Freq=1600, CH0 RK0
7812 18:05:49.942558
7813 18:05:49.945388 DATLAT Default: 0xf
7814 18:05:49.945477 0, 0xFFFF, sum = 0
7815 18:05:49.948427 1, 0xFFFF, sum = 0
7816 18:05:49.948545 2, 0xFFFF, sum = 0
7817 18:05:49.951789 3, 0xFFFF, sum = 0
7818 18:05:49.955182 4, 0xFFFF, sum = 0
7819 18:05:49.955314 5, 0xFFFF, sum = 0
7820 18:05:49.958437 6, 0xFFFF, sum = 0
7821 18:05:49.958564 7, 0xFFFF, sum = 0
7822 18:05:49.961781 8, 0xFFFF, sum = 0
7823 18:05:49.961898 9, 0xFFFF, sum = 0
7824 18:05:49.965062 10, 0xFFFF, sum = 0
7825 18:05:49.965176 11, 0xFFFF, sum = 0
7826 18:05:49.968766 12, 0xFFFF, sum = 0
7827 18:05:49.968896 13, 0xFFFF, sum = 0
7828 18:05:49.971555 14, 0x0, sum = 1
7829 18:05:49.971660 15, 0x0, sum = 2
7830 18:05:49.974878 16, 0x0, sum = 3
7831 18:05:49.974954 17, 0x0, sum = 4
7832 18:05:49.978584 best_step = 15
7833 18:05:49.978661
7834 18:05:49.978732 ==
7835 18:05:49.981817 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 18:05:49.985260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 18:05:49.985369 ==
7838 18:05:49.988322 RX Vref Scan: 1
7839 18:05:49.988441
7840 18:05:49.988509 Set Vref Range= 24 -> 127
7841 18:05:49.988618
7842 18:05:49.991517 RX Vref 24 -> 127, step: 1
7843 18:05:49.991601
7844 18:05:49.994823 RX Delay 19 -> 252, step: 4
7845 18:05:49.994936
7846 18:05:49.998209 Set Vref, RX VrefLevel [Byte0]: 24
7847 18:05:50.001468 [Byte1]: 24
7848 18:05:50.001554
7849 18:05:50.005286 Set Vref, RX VrefLevel [Byte0]: 25
7850 18:05:50.008445 [Byte1]: 25
7851 18:05:50.011558
7852 18:05:50.011642 Set Vref, RX VrefLevel [Byte0]: 26
7853 18:05:50.014570 [Byte1]: 26
7854 18:05:50.019126
7855 18:05:50.019211 Set Vref, RX VrefLevel [Byte0]: 27
7856 18:05:50.022171 [Byte1]: 27
7857 18:05:50.026792
7858 18:05:50.026877 Set Vref, RX VrefLevel [Byte0]: 28
7859 18:05:50.029955 [Byte1]: 28
7860 18:05:50.034151
7861 18:05:50.034236 Set Vref, RX VrefLevel [Byte0]: 29
7862 18:05:50.037337 [Byte1]: 29
7863 18:05:50.041639
7864 18:05:50.041724 Set Vref, RX VrefLevel [Byte0]: 30
7865 18:05:50.044885 [Byte1]: 30
7866 18:05:50.049140
7867 18:05:50.049228 Set Vref, RX VrefLevel [Byte0]: 31
7868 18:05:50.052470 [Byte1]: 31
7869 18:05:50.056959
7870 18:05:50.057071 Set Vref, RX VrefLevel [Byte0]: 32
7871 18:05:50.060074 [Byte1]: 32
7872 18:05:50.064338
7873 18:05:50.064420 Set Vref, RX VrefLevel [Byte0]: 33
7874 18:05:50.067702 [Byte1]: 33
7875 18:05:50.071974
7876 18:05:50.072058 Set Vref, RX VrefLevel [Byte0]: 34
7877 18:05:50.075177 [Byte1]: 34
7878 18:05:50.079403
7879 18:05:50.079488 Set Vref, RX VrefLevel [Byte0]: 35
7880 18:05:50.082665 [Byte1]: 35
7881 18:05:50.087027
7882 18:05:50.087112 Set Vref, RX VrefLevel [Byte0]: 36
7883 18:05:50.090273 [Byte1]: 36
7884 18:05:50.094709
7885 18:05:50.094793 Set Vref, RX VrefLevel [Byte0]: 37
7886 18:05:50.097915 [Byte1]: 37
7887 18:05:50.102157
7888 18:05:50.102242 Set Vref, RX VrefLevel [Byte0]: 38
7889 18:05:50.105430 [Byte1]: 38
7890 18:05:50.109803
7891 18:05:50.109887 Set Vref, RX VrefLevel [Byte0]: 39
7892 18:05:50.112927 [Byte1]: 39
7893 18:05:50.117176
7894 18:05:50.117261 Set Vref, RX VrefLevel [Byte0]: 40
7895 18:05:50.120838 [Byte1]: 40
7896 18:05:50.125007
7897 18:05:50.125091 Set Vref, RX VrefLevel [Byte0]: 41
7898 18:05:50.128325 [Byte1]: 41
7899 18:05:50.132706
7900 18:05:50.132790 Set Vref, RX VrefLevel [Byte0]: 42
7901 18:05:50.135791 [Byte1]: 42
7902 18:05:50.139881
7903 18:05:50.139961 Set Vref, RX VrefLevel [Byte0]: 43
7904 18:05:50.143155 [Byte1]: 43
7905 18:05:50.147861
7906 18:05:50.147937 Set Vref, RX VrefLevel [Byte0]: 44
7907 18:05:50.150930 [Byte1]: 44
7908 18:05:50.155246
7909 18:05:50.155331 Set Vref, RX VrefLevel [Byte0]: 45
7910 18:05:50.158444 [Byte1]: 45
7911 18:05:50.162661
7912 18:05:50.162746 Set Vref, RX VrefLevel [Byte0]: 46
7913 18:05:50.165785 [Byte1]: 46
7914 18:05:50.170509
7915 18:05:50.170594 Set Vref, RX VrefLevel [Byte0]: 47
7916 18:05:50.173788 [Byte1]: 47
7917 18:05:50.178126
7918 18:05:50.178241 Set Vref, RX VrefLevel [Byte0]: 48
7919 18:05:50.181378 [Byte1]: 48
7920 18:05:50.185583
7921 18:05:50.185672 Set Vref, RX VrefLevel [Byte0]: 49
7922 18:05:50.188868 [Byte1]: 49
7923 18:05:50.193206
7924 18:05:50.193290 Set Vref, RX VrefLevel [Byte0]: 50
7925 18:05:50.196433 [Byte1]: 50
7926 18:05:50.200785
7927 18:05:50.200870 Set Vref, RX VrefLevel [Byte0]: 51
7928 18:05:50.203910 [Byte1]: 51
7929 18:05:50.208406
7930 18:05:50.208521 Set Vref, RX VrefLevel [Byte0]: 52
7931 18:05:50.211784 [Byte1]: 52
7932 18:05:50.216120
7933 18:05:50.216204 Set Vref, RX VrefLevel [Byte0]: 53
7934 18:05:50.219272 [Byte1]: 53
7935 18:05:50.223486
7936 18:05:50.223597 Set Vref, RX VrefLevel [Byte0]: 54
7937 18:05:50.226580 [Byte1]: 54
7938 18:05:50.231118
7939 18:05:50.231225 Set Vref, RX VrefLevel [Byte0]: 55
7940 18:05:50.234245 [Byte1]: 55
7941 18:05:50.238355
7942 18:05:50.238452 Set Vref, RX VrefLevel [Byte0]: 56
7943 18:05:50.241855 [Byte1]: 56
7944 18:05:50.246122
7945 18:05:50.246231 Set Vref, RX VrefLevel [Byte0]: 57
7946 18:05:50.249236 [Byte1]: 57
7947 18:05:50.253867
7948 18:05:50.253971 Set Vref, RX VrefLevel [Byte0]: 58
7949 18:05:50.257136 [Byte1]: 58
7950 18:05:50.261462
7951 18:05:50.261565 Set Vref, RX VrefLevel [Byte0]: 59
7952 18:05:50.265036 [Byte1]: 59
7953 18:05:50.269010
7954 18:05:50.269095 Set Vref, RX VrefLevel [Byte0]: 60
7955 18:05:50.272335 [Byte1]: 60
7956 18:05:50.276534
7957 18:05:50.276642 Set Vref, RX VrefLevel [Byte0]: 61
7958 18:05:50.280035 [Byte1]: 61
7959 18:05:50.283946
7960 18:05:50.284030 Set Vref, RX VrefLevel [Byte0]: 62
7961 18:05:50.287076 [Byte1]: 62
7962 18:05:50.291476
7963 18:05:50.291560 Set Vref, RX VrefLevel [Byte0]: 63
7964 18:05:50.294686 [Byte1]: 63
7965 18:05:50.299062
7966 18:05:50.299147 Set Vref, RX VrefLevel [Byte0]: 64
7967 18:05:50.302266 [Byte1]: 64
7968 18:05:50.306470
7969 18:05:50.306557 Set Vref, RX VrefLevel [Byte0]: 65
7970 18:05:50.309848 [Byte1]: 65
7971 18:05:50.314205
7972 18:05:50.314290 Set Vref, RX VrefLevel [Byte0]: 66
7973 18:05:50.317535 [Byte1]: 66
7974 18:05:50.321892
7975 18:05:50.321977 Set Vref, RX VrefLevel [Byte0]: 67
7976 18:05:50.325081 [Byte1]: 67
7977 18:05:50.329643
7978 18:05:50.329727 Set Vref, RX VrefLevel [Byte0]: 68
7979 18:05:50.332790 [Byte1]: 68
7980 18:05:50.337065
7981 18:05:50.337150 Set Vref, RX VrefLevel [Byte0]: 69
7982 18:05:50.340223 [Byte1]: 69
7983 18:05:50.344753
7984 18:05:50.344855 Set Vref, RX VrefLevel [Byte0]: 70
7985 18:05:50.347965 [Byte1]: 70
7986 18:05:50.352052
7987 18:05:50.352137 Set Vref, RX VrefLevel [Byte0]: 71
7988 18:05:50.355530 [Byte1]: 71
7989 18:05:50.359828
7990 18:05:50.359912 Set Vref, RX VrefLevel [Byte0]: 72
7991 18:05:50.363135 [Byte1]: 72
7992 18:05:50.367406
7993 18:05:50.367493 Set Vref, RX VrefLevel [Byte0]: 73
7994 18:05:50.370586 [Byte1]: 73
7995 18:05:50.374986
7996 18:05:50.375071 Set Vref, RX VrefLevel [Byte0]: 74
7997 18:05:50.378156 [Byte1]: 74
7998 18:05:50.382331
7999 18:05:50.385611 Set Vref, RX VrefLevel [Byte0]: 75
8000 18:05:50.385696 [Byte1]: 75
8001 18:05:50.389979
8002 18:05:50.390062 Set Vref, RX VrefLevel [Byte0]: 76
8003 18:05:50.393304 [Byte1]: 76
8004 18:05:50.397563
8005 18:05:50.397648 Final RX Vref Byte 0 = 60 to rank0
8006 18:05:50.400885 Final RX Vref Byte 1 = 61 to rank0
8007 18:05:50.404274 Final RX Vref Byte 0 = 60 to rank1
8008 18:05:50.407485 Final RX Vref Byte 1 = 61 to rank1==
8009 18:05:50.410751 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 18:05:50.417294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 18:05:50.417412 ==
8012 18:05:50.417552 DQS Delay:
8013 18:05:50.417646 DQS0 = 0, DQS1 = 0
8014 18:05:50.421029 DQM Delay:
8015 18:05:50.421114 DQM0 = 135, DQM1 = 124
8016 18:05:50.424236 DQ Delay:
8017 18:05:50.427352 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =132
8018 18:05:50.430550 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
8019 18:05:50.434133 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8020 18:05:50.437254 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =134
8021 18:05:50.437367
8022 18:05:50.437472
8023 18:05:50.437574
8024 18:05:50.440948 [DramC_TX_OE_Calibration] TA2
8025 18:05:50.444130 Original DQ_B0 (3 6) =30, OEN = 27
8026 18:05:50.447351 Original DQ_B1 (3 6) =30, OEN = 27
8027 18:05:50.450514 24, 0x0, End_B0=24 End_B1=24
8028 18:05:50.450601 25, 0x0, End_B0=25 End_B1=25
8029 18:05:50.454079 26, 0x0, End_B0=26 End_B1=26
8030 18:05:50.457398 27, 0x0, End_B0=27 End_B1=27
8031 18:05:50.460929 28, 0x0, End_B0=28 End_B1=28
8032 18:05:50.461015 29, 0x0, End_B0=29 End_B1=29
8033 18:05:50.464114 30, 0x0, End_B0=30 End_B1=30
8034 18:05:50.467433 31, 0x4141, End_B0=30 End_B1=30
8035 18:05:50.470647 Byte0 end_step=30 best_step=27
8036 18:05:50.474032 Byte1 end_step=30 best_step=27
8037 18:05:50.477287 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 18:05:50.477372 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 18:05:50.480971
8040 18:05:50.481057
8041 18:05:50.487441 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8042 18:05:50.490585 CH0 RK0: MR19=303, MR18=1D1B
8043 18:05:50.497150 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8044 18:05:50.497236
8045 18:05:50.500980 ----->DramcWriteLeveling(PI) begin...
8046 18:05:50.501075 ==
8047 18:05:50.504219 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 18:05:50.507416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 18:05:50.507502 ==
8050 18:05:50.510534 Write leveling (Byte 0): 38 => 38
8051 18:05:50.513823 Write leveling (Byte 1): 29 => 29
8052 18:05:50.517048 DramcWriteLeveling(PI) end<-----
8053 18:05:50.517133
8054 18:05:50.517200 ==
8055 18:05:50.520292 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 18:05:50.523992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 18:05:50.524077 ==
8058 18:05:50.527264 [Gating] SW mode calibration
8059 18:05:50.533752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 18:05:50.540367 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 18:05:50.543579 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 18:05:50.547080 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 18:05:50.553832 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8064 18:05:50.556954 1 4 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
8065 18:05:50.560050 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8066 18:05:50.567047 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 18:05:50.570234 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 18:05:50.573545 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 18:05:50.580163 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 18:05:50.583452 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 18:05:50.586737 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8072 18:05:50.593663 1 5 12 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
8073 18:05:50.596934 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8074 18:05:50.600085 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 18:05:50.606644 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 18:05:50.609841 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 18:05:50.612975 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 18:05:50.620133 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 18:05:50.623377 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8080 18:05:50.626527 1 6 12 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
8081 18:05:50.633123 1 6 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8082 18:05:50.636376 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 18:05:50.640056 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 18:05:50.646369 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 18:05:50.649841 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 18:05:50.653015 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 18:05:50.659380 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 18:05:50.662647 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 18:05:50.666273 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 18:05:50.672874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 18:05:50.676278 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 18:05:50.679488 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 18:05:50.685901 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 18:05:50.689735 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 18:05:50.692473 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 18:05:50.699763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 18:05:50.702962 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 18:05:50.706243 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 18:05:50.709444 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 18:05:50.716017 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 18:05:50.719312 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 18:05:50.722600 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 18:05:50.729165 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 18:05:50.732802 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8105 18:05:50.736138 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 18:05:50.739288 Total UI for P1: 0, mck2ui 16
8107 18:05:50.742529 best dqsien dly found for B0: ( 1, 9, 10)
8108 18:05:50.749124 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 18:05:50.752787 Total UI for P1: 0, mck2ui 16
8110 18:05:50.756021 best dqsien dly found for B1: ( 1, 9, 14)
8111 18:05:50.759294 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8112 18:05:50.762477 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8113 18:05:50.762556
8114 18:05:50.765694 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8115 18:05:50.769052 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8116 18:05:50.772148 [Gating] SW calibration Done
8117 18:05:50.772223 ==
8118 18:05:50.775749 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 18:05:50.778895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 18:05:50.778971 ==
8121 18:05:50.782160 RX Vref Scan: 0
8122 18:05:50.782245
8123 18:05:50.785438 RX Vref 0 -> 0, step: 1
8124 18:05:50.785524
8125 18:05:50.785591 RX Delay 0 -> 252, step: 8
8126 18:05:50.792446 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8127 18:05:50.795648 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8128 18:05:50.798937 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8129 18:05:50.802287 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8130 18:05:50.805530 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8131 18:05:50.808799 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8132 18:05:50.815593 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8133 18:05:50.818971 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8134 18:05:50.822177 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8135 18:05:50.825462 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8136 18:05:50.831869 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8137 18:05:50.835253 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8138 18:05:50.838609 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8139 18:05:50.841890 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8140 18:05:50.845190 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8141 18:05:50.852004 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8142 18:05:50.852090 ==
8143 18:05:50.855231 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 18:05:50.858701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 18:05:50.858813 ==
8146 18:05:50.858909 DQS Delay:
8147 18:05:50.861926 DQS0 = 0, DQS1 = 0
8148 18:05:50.862011 DQM Delay:
8149 18:05:50.865075 DQM0 = 135, DQM1 = 124
8150 18:05:50.865159 DQ Delay:
8151 18:05:50.868708 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8152 18:05:50.871850 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8153 18:05:50.875231 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8154 18:05:50.878314 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8155 18:05:50.878408
8156 18:05:50.881763
8157 18:05:50.881876 ==
8158 18:05:50.885113 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 18:05:50.888299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 18:05:50.888404 ==
8161 18:05:50.888497
8162 18:05:50.888631
8163 18:05:50.891607 TX Vref Scan disable
8164 18:05:50.891680 == TX Byte 0 ==
8165 18:05:50.898176 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8166 18:05:50.901443 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8167 18:05:50.901533 == TX Byte 1 ==
8168 18:05:50.908045 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8169 18:05:50.911666 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8170 18:05:50.911751 ==
8171 18:05:50.914565 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 18:05:50.918279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 18:05:50.918364 ==
8174 18:05:50.934020
8175 18:05:50.937265 TX Vref early break, caculate TX vref
8176 18:05:50.940610 TX Vref=16, minBit 0, minWin=23, winSum=388
8177 18:05:50.943937 TX Vref=18, minBit 12, minWin=23, winSum=397
8178 18:05:50.947209 TX Vref=20, minBit 8, minWin=24, winSum=408
8179 18:05:50.950382 TX Vref=22, minBit 0, minWin=25, winSum=418
8180 18:05:50.953543 TX Vref=24, minBit 0, minWin=26, winSum=422
8181 18:05:50.960142 TX Vref=26, minBit 0, minWin=26, winSum=429
8182 18:05:50.963894 TX Vref=28, minBit 0, minWin=26, winSum=431
8183 18:05:50.967127 TX Vref=30, minBit 0, minWin=26, winSum=428
8184 18:05:50.970195 TX Vref=32, minBit 0, minWin=26, winSum=418
8185 18:05:50.973724 TX Vref=34, minBit 2, minWin=24, winSum=411
8186 18:05:50.976806 TX Vref=36, minBit 2, minWin=24, winSum=400
8187 18:05:50.983593 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8188 18:05:50.983680
8189 18:05:50.986725 Final TX Range 0 Vref 28
8190 18:05:50.986811
8191 18:05:50.986879 ==
8192 18:05:50.989934 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 18:05:50.993554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 18:05:50.993641 ==
8195 18:05:50.993710
8196 18:05:50.996910
8197 18:05:50.996994 TX Vref Scan disable
8198 18:05:51.003459 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8199 18:05:51.003562 == TX Byte 0 ==
8200 18:05:51.006706 u2DelayCellOfst[0]=13 cells (4 PI)
8201 18:05:51.010481 u2DelayCellOfst[1]=20 cells (6 PI)
8202 18:05:51.013833 u2DelayCellOfst[2]=13 cells (4 PI)
8203 18:05:51.017110 u2DelayCellOfst[3]=16 cells (5 PI)
8204 18:05:51.020332 u2DelayCellOfst[4]=10 cells (3 PI)
8205 18:05:51.023649 u2DelayCellOfst[5]=0 cells (0 PI)
8206 18:05:51.026934 u2DelayCellOfst[6]=20 cells (6 PI)
8207 18:05:51.030153 u2DelayCellOfst[7]=20 cells (6 PI)
8208 18:05:51.033481 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8209 18:05:51.036674 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8210 18:05:51.040090 == TX Byte 1 ==
8211 18:05:51.043305 u2DelayCellOfst[8]=3 cells (1 PI)
8212 18:05:51.046671 u2DelayCellOfst[9]=0 cells (0 PI)
8213 18:05:51.046757 u2DelayCellOfst[10]=6 cells (2 PI)
8214 18:05:51.049939 u2DelayCellOfst[11]=3 cells (1 PI)
8215 18:05:51.053222 u2DelayCellOfst[12]=13 cells (4 PI)
8216 18:05:51.056845 u2DelayCellOfst[13]=10 cells (3 PI)
8217 18:05:51.059860 u2DelayCellOfst[14]=13 cells (4 PI)
8218 18:05:51.063404 u2DelayCellOfst[15]=10 cells (3 PI)
8219 18:05:51.070161 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8220 18:05:51.073139 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8221 18:05:51.073225 DramC Write-DBI on
8222 18:05:51.073292 ==
8223 18:05:51.076688 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 18:05:51.083402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 18:05:51.083491 ==
8226 18:05:51.083559
8227 18:05:51.083621
8228 18:05:51.083682 TX Vref Scan disable
8229 18:05:51.087475 == TX Byte 0 ==
8230 18:05:51.091004 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8231 18:05:51.094159 == TX Byte 1 ==
8232 18:05:51.097408 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8233 18:05:51.100798 DramC Write-DBI off
8234 18:05:51.100883
8235 18:05:51.100950 [DATLAT]
8236 18:05:51.101013 Freq=1600, CH0 RK1
8237 18:05:51.101075
8238 18:05:51.103957 DATLAT Default: 0xf
8239 18:05:51.104043 0, 0xFFFF, sum = 0
8240 18:05:51.107192 1, 0xFFFF, sum = 0
8241 18:05:51.111067 2, 0xFFFF, sum = 0
8242 18:05:51.111153 3, 0xFFFF, sum = 0
8243 18:05:51.113870 4, 0xFFFF, sum = 0
8244 18:05:51.113956 5, 0xFFFF, sum = 0
8245 18:05:51.117081 6, 0xFFFF, sum = 0
8246 18:05:51.117168 7, 0xFFFF, sum = 0
8247 18:05:51.120806 8, 0xFFFF, sum = 0
8248 18:05:51.120893 9, 0xFFFF, sum = 0
8249 18:05:51.124038 10, 0xFFFF, sum = 0
8250 18:05:51.124124 11, 0xFFFF, sum = 0
8251 18:05:51.127164 12, 0xFFFF, sum = 0
8252 18:05:51.127250 13, 0xFFFF, sum = 0
8253 18:05:51.130436 14, 0x0, sum = 1
8254 18:05:51.130523 15, 0x0, sum = 2
8255 18:05:51.134154 16, 0x0, sum = 3
8256 18:05:51.134240 17, 0x0, sum = 4
8257 18:05:51.137453 best_step = 15
8258 18:05:51.137538
8259 18:05:51.137605 ==
8260 18:05:51.140682 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 18:05:51.144007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 18:05:51.144093 ==
8263 18:05:51.147195 RX Vref Scan: 0
8264 18:05:51.147281
8265 18:05:51.147349 RX Vref 0 -> 0, step: 1
8266 18:05:51.147412
8267 18:05:51.150559 RX Delay 11 -> 252, step: 4
8268 18:05:51.153806 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8269 18:05:51.160238 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8270 18:05:51.163798 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8271 18:05:51.166848 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8272 18:05:51.170567 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8273 18:05:51.173665 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8274 18:05:51.180600 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8275 18:05:51.183673 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8276 18:05:51.187349 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8277 18:05:51.190597 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8278 18:05:51.193590 iDelay=191, Bit 10, Center 122 (75 ~ 170) 96
8279 18:05:51.200059 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8280 18:05:51.203927 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8281 18:05:51.206648 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8282 18:05:51.210516 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8283 18:05:51.213663 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8284 18:05:51.217006 ==
8285 18:05:51.220157 Dram Type= 6, Freq= 0, CH_0, rank 1
8286 18:05:51.223313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 18:05:51.223425 ==
8288 18:05:51.223523 DQS Delay:
8289 18:05:51.226602 DQS0 = 0, DQS1 = 0
8290 18:05:51.226703 DQM Delay:
8291 18:05:51.229916 DQM0 = 132, DQM1 = 122
8292 18:05:51.230022 DQ Delay:
8293 18:05:51.233238 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8294 18:05:51.236916 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8295 18:05:51.240188 DQ8 =116, DQ9 =110, DQ10 =122, DQ11 =120
8296 18:05:51.243503 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8297 18:05:51.243603
8298 18:05:51.243697
8299 18:05:51.243787
8300 18:05:51.246855 [DramC_TX_OE_Calibration] TA2
8301 18:05:51.250149 Original DQ_B0 (3 6) =30, OEN = 27
8302 18:05:51.253441 Original DQ_B1 (3 6) =30, OEN = 27
8303 18:05:51.256693 24, 0x0, End_B0=24 End_B1=24
8304 18:05:51.259950 25, 0x0, End_B0=25 End_B1=25
8305 18:05:51.260069 26, 0x0, End_B0=26 End_B1=26
8306 18:05:51.263046 27, 0x0, End_B0=27 End_B1=27
8307 18:05:51.266352 28, 0x0, End_B0=28 End_B1=28
8308 18:05:51.269901 29, 0x0, End_B0=29 End_B1=29
8309 18:05:51.269979 30, 0x0, End_B0=30 End_B1=30
8310 18:05:51.273097 31, 0x4141, End_B0=30 End_B1=30
8311 18:05:51.276404 Byte0 end_step=30 best_step=27
8312 18:05:51.279699 Byte1 end_step=30 best_step=27
8313 18:05:51.283060 Byte0 TX OE(2T, 0.5T) = (3, 3)
8314 18:05:51.286192 Byte1 TX OE(2T, 0.5T) = (3, 3)
8315 18:05:51.286298
8316 18:05:51.286391
8317 18:05:51.293238 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8318 18:05:51.296445 CH0 RK1: MR19=303, MR18=210E
8319 18:05:51.303129 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8320 18:05:51.306260 [RxdqsGatingPostProcess] freq 1600
8321 18:05:51.312944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8322 18:05:51.313023 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 18:05:51.316123 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 18:05:51.319255 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 18:05:51.322576 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 18:05:51.326263 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 18:05:51.329512 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 18:05:51.332923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 18:05:51.336202 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 18:05:51.339472 Pre-setting of DQS Precalculation
8331 18:05:51.342714 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8332 18:05:51.342814 ==
8333 18:05:51.345980 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 18:05:51.352484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 18:05:51.352587 ==
8336 18:05:51.355803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 18:05:51.362725 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 18:05:51.365978 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 18:05:51.372560 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 18:05:51.380535 [CA 0] Center 42 (12~72) winsize 61
8341 18:05:51.383607 [CA 1] Center 42 (12~72) winsize 61
8342 18:05:51.386887 [CA 2] Center 38 (9~68) winsize 60
8343 18:05:51.390351 [CA 3] Center 37 (8~67) winsize 60
8344 18:05:51.393469 [CA 4] Center 37 (8~67) winsize 60
8345 18:05:51.396990 [CA 5] Center 37 (7~67) winsize 61
8346 18:05:51.397074
8347 18:05:51.399979 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 18:05:51.400063
8349 18:05:51.403485 [CATrainingPosCal] consider 1 rank data
8350 18:05:51.407006 u2DelayCellTimex100 = 290/100 ps
8351 18:05:51.410121 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8352 18:05:51.416556 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8353 18:05:51.420324 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8354 18:05:51.423143 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8355 18:05:51.426471 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 18:05:51.430242 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8357 18:05:51.430325
8358 18:05:51.433463 CA PerBit enable=1, Macro0, CA PI delay=37
8359 18:05:51.433547
8360 18:05:51.436630 [CBTSetCACLKResult] CA Dly = 37
8361 18:05:51.439891 CS Dly: 8 (0~39)
8362 18:05:51.443703 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 18:05:51.446827 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 18:05:51.446910 ==
8365 18:05:51.450132 Dram Type= 6, Freq= 0, CH_1, rank 1
8366 18:05:51.453376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 18:05:51.453466 ==
8368 18:05:51.460100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 18:05:51.463304 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 18:05:51.469763 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 18:05:51.473442 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 18:05:51.483401 [CA 0] Center 42 (13~72) winsize 60
8373 18:05:51.486637 [CA 1] Center 42 (12~72) winsize 61
8374 18:05:51.490392 [CA 2] Center 38 (9~68) winsize 60
8375 18:05:51.493267 [CA 3] Center 37 (8~67) winsize 60
8376 18:05:51.496448 [CA 4] Center 38 (9~67) winsize 59
8377 18:05:51.500121 [CA 5] Center 37 (8~67) winsize 60
8378 18:05:51.500228
8379 18:05:51.503684 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 18:05:51.503766
8381 18:05:51.506751 [CATrainingPosCal] consider 2 rank data
8382 18:05:51.509937 u2DelayCellTimex100 = 290/100 ps
8383 18:05:51.513512 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8384 18:05:51.519930 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8385 18:05:51.523578 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8386 18:05:51.526770 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8387 18:05:51.529948 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8388 18:05:51.533253 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8389 18:05:51.533334
8390 18:05:51.536475 CA PerBit enable=1, Macro0, CA PI delay=37
8391 18:05:51.536582
8392 18:05:51.539704 [CBTSetCACLKResult] CA Dly = 37
8393 18:05:51.543015 CS Dly: 9 (0~42)
8394 18:05:51.546729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 18:05:51.550069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 18:05:51.550151
8397 18:05:51.553184 ----->DramcWriteLeveling(PI) begin...
8398 18:05:51.553267 ==
8399 18:05:51.556442 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 18:05:51.559708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 18:05:51.563019 ==
8402 18:05:51.563100 Write leveling (Byte 0): 23 => 23
8403 18:05:51.566308 Write leveling (Byte 1): 27 => 27
8404 18:05:51.569533 DramcWriteLeveling(PI) end<-----
8405 18:05:51.569614
8406 18:05:51.569678 ==
8407 18:05:51.572838 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 18:05:51.579531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 18:05:51.579613 ==
8410 18:05:51.583158 [Gating] SW mode calibration
8411 18:05:51.589603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8412 18:05:51.592883 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8413 18:05:51.599603 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 18:05:51.602856 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 18:05:51.606040 1 4 8 | B1->B0 | 2727 2c2c | 1 0 | (0 0) (0 0)
8416 18:05:51.612583 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8417 18:05:51.615637 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 18:05:51.619259 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 18:05:51.626068 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 18:05:51.628821 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 18:05:51.632118 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 18:05:51.639139 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8423 18:05:51.642264 1 5 8 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (1 0)
8424 18:05:51.645540 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8425 18:05:51.651974 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 18:05:51.655220 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 18:05:51.659163 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 18:05:51.665714 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 18:05:51.669091 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 18:05:51.672270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 18:05:51.675543 1 6 8 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
8432 18:05:51.682064 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 18:05:51.685276 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 18:05:51.688792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 18:05:51.695122 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 18:05:51.698628 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 18:05:51.705099 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 18:05:51.708382 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8439 18:05:51.711613 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8440 18:05:51.715014 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8441 18:05:51.721755 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 18:05:51.724745 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 18:05:51.728293 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 18:05:51.734737 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 18:05:51.737912 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 18:05:51.741209 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 18:05:51.748138 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 18:05:51.751505 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 18:05:51.754355 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 18:05:51.761256 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 18:05:51.764624 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 18:05:51.767809 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 18:05:51.774411 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 18:05:51.778270 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8455 18:05:51.781011 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8456 18:05:51.784759 Total UI for P1: 0, mck2ui 16
8457 18:05:51.787701 best dqsien dly found for B0: ( 1, 9, 4)
8458 18:05:51.794307 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8459 18:05:51.797576 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 18:05:51.800881 Total UI for P1: 0, mck2ui 16
8461 18:05:51.804660 best dqsien dly found for B1: ( 1, 9, 10)
8462 18:05:51.807667 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8463 18:05:51.810809 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8464 18:05:51.810894
8465 18:05:51.814660 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8466 18:05:51.817716 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8467 18:05:51.820933 [Gating] SW calibration Done
8468 18:05:51.821018 ==
8469 18:05:51.824482 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 18:05:51.830835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 18:05:51.830920 ==
8472 18:05:51.830988 RX Vref Scan: 0
8473 18:05:51.831049
8474 18:05:51.834005 RX Vref 0 -> 0, step: 1
8475 18:05:51.834090
8476 18:05:51.837696 RX Delay 0 -> 252, step: 8
8477 18:05:51.840968 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8478 18:05:51.844296 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8479 18:05:51.847581 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8480 18:05:51.850611 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8481 18:05:51.857164 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8482 18:05:51.860466 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8483 18:05:51.863721 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8484 18:05:51.867070 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8485 18:05:51.870845 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8486 18:05:51.877437 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8487 18:05:51.880211 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8488 18:05:51.883998 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8489 18:05:51.887031 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8490 18:05:51.890252 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8491 18:05:51.896868 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8492 18:05:51.900128 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8493 18:05:51.900263 ==
8494 18:05:51.903379 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 18:05:51.907013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 18:05:51.907159 ==
8497 18:05:51.910494 DQS Delay:
8498 18:05:51.910695 DQS0 = 0, DQS1 = 0
8499 18:05:51.910836 DQM Delay:
8500 18:05:51.913748 DQM0 = 136, DQM1 = 131
8501 18:05:51.913888 DQ Delay:
8502 18:05:51.917048 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8503 18:05:51.920260 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8504 18:05:51.923475 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8505 18:05:51.930126 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
8506 18:05:51.930302
8507 18:05:51.930408
8508 18:05:51.930502 ==
8509 18:05:51.933266 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 18:05:51.936951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 18:05:51.937126 ==
8512 18:05:51.937239
8513 18:05:51.937334
8514 18:05:51.939994 TX Vref Scan disable
8515 18:05:51.940106 == TX Byte 0 ==
8516 18:05:51.946342 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8517 18:05:51.950239 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8518 18:05:51.950389 == TX Byte 1 ==
8519 18:05:51.956865 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8520 18:05:51.960002 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8521 18:05:51.960154 ==
8522 18:05:51.963179 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 18:05:51.966451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 18:05:51.966626 ==
8525 18:05:51.980664
8526 18:05:51.983758 TX Vref early break, caculate TX vref
8527 18:05:51.987044 TX Vref=16, minBit 10, minWin=21, winSum=371
8528 18:05:51.990181 TX Vref=18, minBit 10, minWin=22, winSum=382
8529 18:05:51.993814 TX Vref=20, minBit 10, minWin=23, winSum=392
8530 18:05:51.997217 TX Vref=22, minBit 10, minWin=23, winSum=400
8531 18:05:52.003958 TX Vref=24, minBit 10, minWin=24, winSum=410
8532 18:05:52.007150 TX Vref=26, minBit 15, minWin=25, winSum=422
8533 18:05:52.010213 TX Vref=28, minBit 12, minWin=25, winSum=423
8534 18:05:52.013485 TX Vref=30, minBit 9, minWin=25, winSum=417
8535 18:05:52.017181 TX Vref=32, minBit 8, minWin=25, winSum=412
8536 18:05:52.020168 TX Vref=34, minBit 10, minWin=23, winSum=397
8537 18:05:52.027023 [TxChooseVref] Worse bit 12, Min win 25, Win sum 423, Final Vref 28
8538 18:05:52.027142
8539 18:05:52.030067 Final TX Range 0 Vref 28
8540 18:05:52.030147
8541 18:05:52.030214 ==
8542 18:05:52.033720 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 18:05:52.036746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 18:05:52.036835 ==
8545 18:05:52.036911
8546 18:05:52.040341
8547 18:05:52.040455 TX Vref Scan disable
8548 18:05:52.047100 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8549 18:05:52.047197 == TX Byte 0 ==
8550 18:05:52.050377 u2DelayCellOfst[0]=16 cells (5 PI)
8551 18:05:52.053574 u2DelayCellOfst[1]=10 cells (3 PI)
8552 18:05:52.056775 u2DelayCellOfst[2]=0 cells (0 PI)
8553 18:05:52.059984 u2DelayCellOfst[3]=6 cells (2 PI)
8554 18:05:52.063406 u2DelayCellOfst[4]=6 cells (2 PI)
8555 18:05:52.066647 u2DelayCellOfst[5]=20 cells (6 PI)
8556 18:05:52.069945 u2DelayCellOfst[6]=16 cells (5 PI)
8557 18:05:52.073791 u2DelayCellOfst[7]=3 cells (1 PI)
8558 18:05:52.076431 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8559 18:05:52.079992 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8560 18:05:52.083638 == TX Byte 1 ==
8561 18:05:52.086885 u2DelayCellOfst[8]=0 cells (0 PI)
8562 18:05:52.090325 u2DelayCellOfst[9]=3 cells (1 PI)
8563 18:05:52.090425 u2DelayCellOfst[10]=10 cells (3 PI)
8564 18:05:52.093952 u2DelayCellOfst[11]=3 cells (1 PI)
8565 18:05:52.096780 u2DelayCellOfst[12]=16 cells (5 PI)
8566 18:05:52.099945 u2DelayCellOfst[13]=16 cells (5 PI)
8567 18:05:52.103463 u2DelayCellOfst[14]=20 cells (6 PI)
8568 18:05:52.106723 u2DelayCellOfst[15]=16 cells (5 PI)
8569 18:05:52.113427 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8570 18:05:52.116450 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 18:05:52.116591 DramC Write-DBI on
8572 18:05:52.116660 ==
8573 18:05:52.119774 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 18:05:52.126416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 18:05:52.126502 ==
8576 18:05:52.126570
8577 18:05:52.126631
8578 18:05:52.126691 TX Vref Scan disable
8579 18:05:52.130809 == TX Byte 0 ==
8580 18:05:52.134031 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8581 18:05:52.136991 == TX Byte 1 ==
8582 18:05:52.140731 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8583 18:05:52.140816 DramC Write-DBI off
8584 18:05:52.143827
8585 18:05:52.143911 [DATLAT]
8586 18:05:52.143979 Freq=1600, CH1 RK0
8587 18:05:52.144042
8588 18:05:52.147409 DATLAT Default: 0xf
8589 18:05:52.147494 0, 0xFFFF, sum = 0
8590 18:05:52.150474 1, 0xFFFF, sum = 0
8591 18:05:52.150561 2, 0xFFFF, sum = 0
8592 18:05:52.153844 3, 0xFFFF, sum = 0
8593 18:05:52.157011 4, 0xFFFF, sum = 0
8594 18:05:52.157097 5, 0xFFFF, sum = 0
8595 18:05:52.160322 6, 0xFFFF, sum = 0
8596 18:05:52.160408 7, 0xFFFF, sum = 0
8597 18:05:52.163619 8, 0xFFFF, sum = 0
8598 18:05:52.163705 9, 0xFFFF, sum = 0
8599 18:05:52.166999 10, 0xFFFF, sum = 0
8600 18:05:52.167086 11, 0xFFFF, sum = 0
8601 18:05:52.170301 12, 0xFFFF, sum = 0
8602 18:05:52.170388 13, 0xFFFF, sum = 0
8603 18:05:52.173974 14, 0x0, sum = 1
8604 18:05:52.174061 15, 0x0, sum = 2
8605 18:05:52.177164 16, 0x0, sum = 3
8606 18:05:52.177250 17, 0x0, sum = 4
8607 18:05:52.180317 best_step = 15
8608 18:05:52.180402
8609 18:05:52.180470 ==
8610 18:05:52.183623 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 18:05:52.186899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 18:05:52.186985 ==
8613 18:05:52.187052 RX Vref Scan: 1
8614 18:05:52.190211
8615 18:05:52.190295 Set Vref Range= 24 -> 127
8616 18:05:52.190363
8617 18:05:52.193970 RX Vref 24 -> 127, step: 1
8618 18:05:52.194055
8619 18:05:52.196816 RX Delay 19 -> 252, step: 4
8620 18:05:52.196902
8621 18:05:52.200427 Set Vref, RX VrefLevel [Byte0]: 24
8622 18:05:52.204132 [Byte1]: 24
8623 18:05:52.204225
8624 18:05:52.206999 Set Vref, RX VrefLevel [Byte0]: 25
8625 18:05:52.210521 [Byte1]: 25
8626 18:05:52.210638
8627 18:05:52.213855 Set Vref, RX VrefLevel [Byte0]: 26
8628 18:05:52.217213 [Byte1]: 26
8629 18:05:52.220980
8630 18:05:52.221066 Set Vref, RX VrefLevel [Byte0]: 27
8631 18:05:52.224231 [Byte1]: 27
8632 18:05:52.228264
8633 18:05:52.228376 Set Vref, RX VrefLevel [Byte0]: 28
8634 18:05:52.231959 [Byte1]: 28
8635 18:05:52.236284
8636 18:05:52.236369 Set Vref, RX VrefLevel [Byte0]: 29
8637 18:05:52.239435 [Byte1]: 29
8638 18:05:52.243662
8639 18:05:52.243749 Set Vref, RX VrefLevel [Byte0]: 30
8640 18:05:52.246861 [Byte1]: 30
8641 18:05:52.251026
8642 18:05:52.251135 Set Vref, RX VrefLevel [Byte0]: 31
8643 18:05:52.254213 [Byte1]: 31
8644 18:05:52.258562
8645 18:05:52.258639 Set Vref, RX VrefLevel [Byte0]: 32
8646 18:05:52.261940 [Byte1]: 32
8647 18:05:52.266305
8648 18:05:52.266391 Set Vref, RX VrefLevel [Byte0]: 33
8649 18:05:52.269548 [Byte1]: 33
8650 18:05:52.274033
8651 18:05:52.274118 Set Vref, RX VrefLevel [Byte0]: 34
8652 18:05:52.277217 [Byte1]: 34
8653 18:05:52.281501
8654 18:05:52.281586 Set Vref, RX VrefLevel [Byte0]: 35
8655 18:05:52.284791 [Byte1]: 35
8656 18:05:52.289128
8657 18:05:52.289213 Set Vref, RX VrefLevel [Byte0]: 36
8658 18:05:52.292353 [Byte1]: 36
8659 18:05:52.296732
8660 18:05:52.296839 Set Vref, RX VrefLevel [Byte0]: 37
8661 18:05:52.299956 [Byte1]: 37
8662 18:05:52.303897
8663 18:05:52.304005 Set Vref, RX VrefLevel [Byte0]: 38
8664 18:05:52.307190 [Byte1]: 38
8665 18:05:52.311905
8666 18:05:52.312006 Set Vref, RX VrefLevel [Byte0]: 39
8667 18:05:52.315072 [Byte1]: 39
8668 18:05:52.319312
8669 18:05:52.319416 Set Vref, RX VrefLevel [Byte0]: 40
8670 18:05:52.322713 [Byte1]: 40
8671 18:05:52.326746
8672 18:05:52.326858 Set Vref, RX VrefLevel [Byte0]: 41
8673 18:05:52.330039 [Byte1]: 41
8674 18:05:52.334169
8675 18:05:52.334272 Set Vref, RX VrefLevel [Byte0]: 42
8676 18:05:52.337538 [Byte1]: 42
8677 18:05:52.341870
8678 18:05:52.341979 Set Vref, RX VrefLevel [Byte0]: 43
8679 18:05:52.345065 [Byte1]: 43
8680 18:05:52.349691
8681 18:05:52.349792 Set Vref, RX VrefLevel [Byte0]: 44
8682 18:05:52.352780 [Byte1]: 44
8683 18:05:52.356954
8684 18:05:52.357058 Set Vref, RX VrefLevel [Byte0]: 45
8685 18:05:52.360217 [Byte1]: 45
8686 18:05:52.364935
8687 18:05:52.365010 Set Vref, RX VrefLevel [Byte0]: 46
8688 18:05:52.367779 [Byte1]: 46
8689 18:05:52.372037
8690 18:05:52.372137 Set Vref, RX VrefLevel [Byte0]: 47
8691 18:05:52.375357 [Byte1]: 47
8692 18:05:52.379599
8693 18:05:52.379702 Set Vref, RX VrefLevel [Byte0]: 48
8694 18:05:52.383374 [Byte1]: 48
8695 18:05:52.387240
8696 18:05:52.387349 Set Vref, RX VrefLevel [Byte0]: 49
8697 18:05:52.390527 [Byte1]: 49
8698 18:05:52.395236
8699 18:05:52.395344 Set Vref, RX VrefLevel [Byte0]: 50
8700 18:05:52.398037 [Byte1]: 50
8701 18:05:52.402305
8702 18:05:52.402416 Set Vref, RX VrefLevel [Byte0]: 51
8703 18:05:52.406189 [Byte1]: 51
8704 18:05:52.409862
8705 18:05:52.409964 Set Vref, RX VrefLevel [Byte0]: 52
8706 18:05:52.413623 [Byte1]: 52
8707 18:05:52.417639
8708 18:05:52.417808 Set Vref, RX VrefLevel [Byte0]: 53
8709 18:05:52.421178 [Byte1]: 53
8710 18:05:52.425173
8711 18:05:52.425253 Set Vref, RX VrefLevel [Byte0]: 54
8712 18:05:52.428567 [Byte1]: 54
8713 18:05:52.432944
8714 18:05:52.433034 Set Vref, RX VrefLevel [Byte0]: 55
8715 18:05:52.435975 [Byte1]: 55
8716 18:05:52.440361
8717 18:05:52.440463 Set Vref, RX VrefLevel [Byte0]: 56
8718 18:05:52.443662 [Byte1]: 56
8719 18:05:52.447936
8720 18:05:52.448037 Set Vref, RX VrefLevel [Byte0]: 57
8721 18:05:52.451130 [Byte1]: 57
8722 18:05:52.455737
8723 18:05:52.455837 Set Vref, RX VrefLevel [Byte0]: 58
8724 18:05:52.458921 [Byte1]: 58
8725 18:05:52.463113
8726 18:05:52.463212 Set Vref, RX VrefLevel [Byte0]: 59
8727 18:05:52.466398 [Byte1]: 59
8728 18:05:52.470713
8729 18:05:52.470817 Set Vref, RX VrefLevel [Byte0]: 60
8730 18:05:52.473992 [Byte1]: 60
8731 18:05:52.478286
8732 18:05:52.478391 Set Vref, RX VrefLevel [Byte0]: 61
8733 18:05:52.481508 [Byte1]: 61
8734 18:05:52.485977
8735 18:05:52.486061 Set Vref, RX VrefLevel [Byte0]: 62
8736 18:05:52.489153 [Byte1]: 62
8737 18:05:52.493616
8738 18:05:52.493713 Set Vref, RX VrefLevel [Byte0]: 63
8739 18:05:52.496843 [Byte1]: 63
8740 18:05:52.501087
8741 18:05:52.501176 Set Vref, RX VrefLevel [Byte0]: 64
8742 18:05:52.504222 [Byte1]: 64
8743 18:05:52.508577
8744 18:05:52.508655 Set Vref, RX VrefLevel [Byte0]: 65
8745 18:05:52.512000 [Byte1]: 65
8746 18:05:52.516298
8747 18:05:52.516382 Set Vref, RX VrefLevel [Byte0]: 66
8748 18:05:52.519512 [Byte1]: 66
8749 18:05:52.523697
8750 18:05:52.523786 Set Vref, RX VrefLevel [Byte0]: 67
8751 18:05:52.529999 [Byte1]: 67
8752 18:05:52.530181
8753 18:05:52.533466 Set Vref, RX VrefLevel [Byte0]: 68
8754 18:05:52.536609 [Byte1]: 68
8755 18:05:52.536695
8756 18:05:52.540213 Set Vref, RX VrefLevel [Byte0]: 69
8757 18:05:52.543411 [Byte1]: 69
8758 18:05:52.543497
8759 18:05:52.546985 Set Vref, RX VrefLevel [Byte0]: 70
8760 18:05:52.550239 [Byte1]: 70
8761 18:05:52.553934
8762 18:05:52.554019 Set Vref, RX VrefLevel [Byte0]: 71
8763 18:05:52.557143 [Byte1]: 71
8764 18:05:52.561744
8765 18:05:52.561829 Set Vref, RX VrefLevel [Byte0]: 72
8766 18:05:52.564875 [Byte1]: 72
8767 18:05:52.569289
8768 18:05:52.569377 Final RX Vref Byte 0 = 55 to rank0
8769 18:05:52.572455 Final RX Vref Byte 1 = 60 to rank0
8770 18:05:52.575744 Final RX Vref Byte 0 = 55 to rank1
8771 18:05:52.579079 Final RX Vref Byte 1 = 60 to rank1==
8772 18:05:52.582271 Dram Type= 6, Freq= 0, CH_1, rank 0
8773 18:05:52.588753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 18:05:52.588841 ==
8775 18:05:52.588909 DQS Delay:
8776 18:05:52.591958 DQS0 = 0, DQS1 = 0
8777 18:05:52.592035 DQM Delay:
8778 18:05:52.592098 DQM0 = 133, DQM1 = 129
8779 18:05:52.595260 DQ Delay:
8780 18:05:52.599037 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8781 18:05:52.602292 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8782 18:05:52.605677 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8783 18:05:52.608933 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8784 18:05:52.609004
8785 18:05:52.609067
8786 18:05:52.609125
8787 18:05:52.612150 [DramC_TX_OE_Calibration] TA2
8788 18:05:52.615395 Original DQ_B0 (3 6) =30, OEN = 27
8789 18:05:52.618667 Original DQ_B1 (3 6) =30, OEN = 27
8790 18:05:52.622373 24, 0x0, End_B0=24 End_B1=24
8791 18:05:52.622468 25, 0x0, End_B0=25 End_B1=25
8792 18:05:52.625684 26, 0x0, End_B0=26 End_B1=26
8793 18:05:52.628967 27, 0x0, End_B0=27 End_B1=27
8794 18:05:52.632111 28, 0x0, End_B0=28 End_B1=28
8795 18:05:52.635198 29, 0x0, End_B0=29 End_B1=29
8796 18:05:52.635289 30, 0x0, End_B0=30 End_B1=30
8797 18:05:52.638663 31, 0x4141, End_B0=30 End_B1=30
8798 18:05:52.641825 Byte0 end_step=30 best_step=27
8799 18:05:52.645407 Byte1 end_step=30 best_step=27
8800 18:05:52.648966 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 18:05:52.652177 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 18:05:52.652248
8803 18:05:52.652309
8804 18:05:52.658529 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8805 18:05:52.661724 CH1 RK0: MR19=303, MR18=1725
8806 18:05:52.668708 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8807 18:05:52.668793
8808 18:05:52.671703 ----->DramcWriteLeveling(PI) begin...
8809 18:05:52.671785 ==
8810 18:05:52.675483 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 18:05:52.678741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 18:05:52.678819 ==
8813 18:05:52.681933 Write leveling (Byte 0): 25 => 25
8814 18:05:52.685119 Write leveling (Byte 1): 30 => 30
8815 18:05:52.688415 DramcWriteLeveling(PI) end<-----
8816 18:05:52.688525
8817 18:05:52.688602 ==
8818 18:05:52.691680 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 18:05:52.695385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 18:05:52.695470 ==
8821 18:05:52.698704 [Gating] SW mode calibration
8822 18:05:52.705240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8823 18:05:52.711760 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8824 18:05:52.715091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 18:05:52.718341 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 18:05:52.725281 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8827 18:05:52.728429 1 4 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
8828 18:05:52.731688 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 18:05:52.738508 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 18:05:52.741585 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 18:05:52.744808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 18:05:52.751944 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 18:05:52.754924 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
8834 18:05:52.758515 1 5 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)
8835 18:05:52.765002 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (1 0)
8836 18:05:52.768589 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 18:05:52.771849 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 18:05:52.778222 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 18:05:52.781518 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 18:05:52.785295 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 18:05:52.791603 1 6 4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8842 18:05:52.794897 1 6 8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)
8843 18:05:52.798038 1 6 12 | B1->B0 | 4646 3938 | 0 1 | (0 0) (0 0)
8844 18:05:52.804713 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 18:05:52.808009 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 18:05:52.811747 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 18:05:52.818200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 18:05:52.821524 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 18:05:52.824750 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 18:05:52.831354 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8851 18:05:52.834504 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 18:05:52.838157 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 18:05:52.844926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 18:05:52.848118 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 18:05:52.851142 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 18:05:52.854707 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 18:05:52.861387 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 18:05:52.864483 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 18:05:52.868209 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 18:05:52.874405 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 18:05:52.878038 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 18:05:52.881166 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 18:05:52.887657 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 18:05:52.891465 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 18:05:52.894810 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 18:05:52.901300 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8867 18:05:52.904385 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8868 18:05:52.907623 Total UI for P1: 0, mck2ui 16
8869 18:05:52.911340 best dqsien dly found for B1: ( 1, 9, 8)
8870 18:05:52.914731 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 18:05:52.918063 Total UI for P1: 0, mck2ui 16
8872 18:05:52.921355 best dqsien dly found for B0: ( 1, 9, 10)
8873 18:05:52.924482 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8874 18:05:52.927754 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8875 18:05:52.927829
8876 18:05:52.934367 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8877 18:05:52.937669 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8878 18:05:52.937753 [Gating] SW calibration Done
8879 18:05:52.941352 ==
8880 18:05:52.941438 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 18:05:52.947479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 18:05:52.947563 ==
8883 18:05:52.947631 RX Vref Scan: 0
8884 18:05:52.947694
8885 18:05:52.951249 RX Vref 0 -> 0, step: 1
8886 18:05:52.951360
8887 18:05:52.954573 RX Delay 0 -> 252, step: 8
8888 18:05:52.957654 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8889 18:05:52.961383 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8890 18:05:52.964471 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8891 18:05:52.971201 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8892 18:05:52.974351 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8893 18:05:52.977543 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8894 18:05:52.981214 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8895 18:05:52.984235 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8896 18:05:52.990779 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8897 18:05:52.994156 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8898 18:05:52.997876 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8899 18:05:53.001159 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8900 18:05:53.004310 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8901 18:05:53.010959 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8902 18:05:53.014260 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8903 18:05:53.017410 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8904 18:05:53.017494 ==
8905 18:05:53.020705 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 18:05:53.023985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 18:05:53.024070 ==
8908 18:05:53.027704 DQS Delay:
8909 18:05:53.027788 DQS0 = 0, DQS1 = 0
8910 18:05:53.031030 DQM Delay:
8911 18:05:53.031114 DQM0 = 136, DQM1 = 132
8912 18:05:53.034191 DQ Delay:
8913 18:05:53.037395 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8914 18:05:53.040723 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8915 18:05:53.044472 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8916 18:05:53.047658 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8917 18:05:53.047742
8918 18:05:53.047808
8919 18:05:53.047870 ==
8920 18:05:53.050621 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 18:05:53.053926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 18:05:53.054011 ==
8923 18:05:53.054078
8924 18:05:53.054140
8925 18:05:53.057560 TX Vref Scan disable
8926 18:05:53.060819 == TX Byte 0 ==
8927 18:05:53.064455 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8928 18:05:53.067667 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8929 18:05:53.070941 == TX Byte 1 ==
8930 18:05:53.074049 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8931 18:05:53.077197 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8932 18:05:53.077281 ==
8933 18:05:53.080890 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 18:05:53.084269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 18:05:53.087291 ==
8936 18:05:53.098502
8937 18:05:53.101858 TX Vref early break, caculate TX vref
8938 18:05:53.105013 TX Vref=16, minBit 8, minWin=22, winSum=379
8939 18:05:53.108891 TX Vref=18, minBit 9, minWin=22, winSum=389
8940 18:05:53.112177 TX Vref=20, minBit 8, minWin=23, winSum=395
8941 18:05:53.114930 TX Vref=22, minBit 8, minWin=23, winSum=403
8942 18:05:53.118251 TX Vref=24, minBit 8, minWin=24, winSum=411
8943 18:05:53.125257 TX Vref=26, minBit 9, minWin=24, winSum=415
8944 18:05:53.128586 TX Vref=28, minBit 8, minWin=25, winSum=418
8945 18:05:53.131949 TX Vref=30, minBit 8, minWin=24, winSum=412
8946 18:05:53.135117 TX Vref=32, minBit 8, minWin=24, winSum=407
8947 18:05:53.138420 TX Vref=34, minBit 9, minWin=23, winSum=394
8948 18:05:53.145011 [TxChooseVref] Worse bit 8, Min win 25, Win sum 418, Final Vref 28
8949 18:05:53.145097
8950 18:05:53.148217 Final TX Range 0 Vref 28
8951 18:05:53.148303
8952 18:05:53.148370 ==
8953 18:05:53.151863 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 18:05:53.154818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 18:05:53.154904 ==
8956 18:05:53.154971
8957 18:05:53.155035
8958 18:05:53.158105 TX Vref Scan disable
8959 18:05:53.165152 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8960 18:05:53.165237 == TX Byte 0 ==
8961 18:05:53.168380 u2DelayCellOfst[0]=13 cells (4 PI)
8962 18:05:53.171505 u2DelayCellOfst[1]=10 cells (3 PI)
8963 18:05:53.174684 u2DelayCellOfst[2]=0 cells (0 PI)
8964 18:05:53.178117 u2DelayCellOfst[3]=3 cells (1 PI)
8965 18:05:53.181254 u2DelayCellOfst[4]=6 cells (2 PI)
8966 18:05:53.184782 u2DelayCellOfst[5]=16 cells (5 PI)
8967 18:05:53.187797 u2DelayCellOfst[6]=16 cells (5 PI)
8968 18:05:53.191394 u2DelayCellOfst[7]=3 cells (1 PI)
8969 18:05:53.194595 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8970 18:05:53.197789 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8971 18:05:53.201095 == TX Byte 1 ==
8972 18:05:53.201206 u2DelayCellOfst[8]=0 cells (0 PI)
8973 18:05:53.204563 u2DelayCellOfst[9]=3 cells (1 PI)
8974 18:05:53.207914 u2DelayCellOfst[10]=10 cells (3 PI)
8975 18:05:53.211124 u2DelayCellOfst[11]=3 cells (1 PI)
8976 18:05:53.214409 u2DelayCellOfst[12]=13 cells (4 PI)
8977 18:05:53.218269 u2DelayCellOfst[13]=16 cells (5 PI)
8978 18:05:53.220921 u2DelayCellOfst[14]=20 cells (6 PI)
8979 18:05:53.224736 u2DelayCellOfst[15]=20 cells (6 PI)
8980 18:05:53.228116 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8981 18:05:53.234577 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8982 18:05:53.234662 DramC Write-DBI on
8983 18:05:53.234729 ==
8984 18:05:53.237861 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 18:05:53.244225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 18:05:53.244310 ==
8987 18:05:53.244377
8988 18:05:53.244438
8989 18:05:53.244507 TX Vref Scan disable
8990 18:05:53.248016 == TX Byte 0 ==
8991 18:05:53.251200 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8992 18:05:53.254404 == TX Byte 1 ==
8993 18:05:53.258090 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8994 18:05:53.261197 DramC Write-DBI off
8995 18:05:53.261281
8996 18:05:53.261347 [DATLAT]
8997 18:05:53.261409 Freq=1600, CH1 RK1
8998 18:05:53.261470
8999 18:05:53.264499 DATLAT Default: 0xf
9000 18:05:53.264604 0, 0xFFFF, sum = 0
9001 18:05:53.267729 1, 0xFFFF, sum = 0
9002 18:05:53.270945 2, 0xFFFF, sum = 0
9003 18:05:53.271030 3, 0xFFFF, sum = 0
9004 18:05:53.274569 4, 0xFFFF, sum = 0
9005 18:05:53.274673 5, 0xFFFF, sum = 0
9006 18:05:53.277853 6, 0xFFFF, sum = 0
9007 18:05:53.277938 7, 0xFFFF, sum = 0
9008 18:05:53.281000 8, 0xFFFF, sum = 0
9009 18:05:53.281086 9, 0xFFFF, sum = 0
9010 18:05:53.284653 10, 0xFFFF, sum = 0
9011 18:05:53.284763 11, 0xFFFF, sum = 0
9012 18:05:53.287700 12, 0xFFFF, sum = 0
9013 18:05:53.287786 13, 0xFFFF, sum = 0
9014 18:05:53.290875 14, 0x0, sum = 1
9015 18:05:53.290961 15, 0x0, sum = 2
9016 18:05:53.294503 16, 0x0, sum = 3
9017 18:05:53.294588 17, 0x0, sum = 4
9018 18:05:53.297897 best_step = 15
9019 18:05:53.297982
9020 18:05:53.298048 ==
9021 18:05:53.301068 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 18:05:53.304413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 18:05:53.304529 ==
9024 18:05:53.307697 RX Vref Scan: 0
9025 18:05:53.307784
9026 18:05:53.307855 RX Vref 0 -> 0, step: 1
9027 18:05:53.307923
9028 18:05:53.310920 RX Delay 19 -> 252, step: 4
9029 18:05:53.314200 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9030 18:05:53.321209 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9031 18:05:53.324525 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9032 18:05:53.327883 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9033 18:05:53.331194 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9034 18:05:53.334499 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9035 18:05:53.337713 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9036 18:05:53.344371 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9037 18:05:53.347743 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9038 18:05:53.350899 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9039 18:05:53.354178 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9040 18:05:53.357377 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9041 18:05:53.364243 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9042 18:05:53.367436 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9043 18:05:53.370620 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9044 18:05:53.374270 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9045 18:05:53.374356 ==
9046 18:05:53.377456 Dram Type= 6, Freq= 0, CH_1, rank 1
9047 18:05:53.384271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9048 18:05:53.384357 ==
9049 18:05:53.384425 DQS Delay:
9050 18:05:53.387197 DQS0 = 0, DQS1 = 0
9051 18:05:53.387282 DQM Delay:
9052 18:05:53.390410 DQM0 = 133, DQM1 = 130
9053 18:05:53.390495 DQ Delay:
9054 18:05:53.393932 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9055 18:05:53.397119 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9056 18:05:53.400673 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9057 18:05:53.403782 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9058 18:05:53.403867
9059 18:05:53.403934
9060 18:05:53.403995
9061 18:05:53.407153 [DramC_TX_OE_Calibration] TA2
9062 18:05:53.410343 Original DQ_B0 (3 6) =30, OEN = 27
9063 18:05:53.414087 Original DQ_B1 (3 6) =30, OEN = 27
9064 18:05:53.417325 24, 0x0, End_B0=24 End_B1=24
9065 18:05:53.417411 25, 0x0, End_B0=25 End_B1=25
9066 18:05:53.420432 26, 0x0, End_B0=26 End_B1=26
9067 18:05:53.423678 27, 0x0, End_B0=27 End_B1=27
9068 18:05:53.426910 28, 0x0, End_B0=28 End_B1=28
9069 18:05:53.430254 29, 0x0, End_B0=29 End_B1=29
9070 18:05:53.430341 30, 0x0, End_B0=30 End_B1=30
9071 18:05:53.433994 31, 0x4141, End_B0=30 End_B1=30
9072 18:05:53.437208 Byte0 end_step=30 best_step=27
9073 18:05:53.440376 Byte1 end_step=30 best_step=27
9074 18:05:53.443674 Byte0 TX OE(2T, 0.5T) = (3, 3)
9075 18:05:53.447064 Byte1 TX OE(2T, 0.5T) = (3, 3)
9076 18:05:53.447149
9077 18:05:53.447216
9078 18:05:53.453476 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9079 18:05:53.456869 CH1 RK1: MR19=303, MR18=1E08
9080 18:05:53.463609 CH1_RK1: MR19=0x303, MR18=0x1E08, DQSOSC=394, MR23=63, INC=23, DEC=15
9081 18:05:53.466655 [RxdqsGatingPostProcess] freq 1600
9082 18:05:53.470103 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9083 18:05:53.473695 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 18:05:53.476953 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 18:05:53.480201 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 18:05:53.483450 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 18:05:53.487102 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 18:05:53.490242 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 18:05:53.493452 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 18:05:53.496747 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 18:05:53.499911 Pre-setting of DQS Precalculation
9092 18:05:53.503564 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9093 18:05:53.510350 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9094 18:05:53.520064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 18:05:53.520149
9096 18:05:53.520217
9097 18:05:53.523246 [Calibration Summary] 3200 Mbps
9098 18:05:53.523331 CH 0, Rank 0
9099 18:05:53.526335 SW Impedance : PASS
9100 18:05:53.526430 DUTY Scan : NO K
9101 18:05:53.529610 ZQ Calibration : PASS
9102 18:05:53.533581 Jitter Meter : NO K
9103 18:05:53.533667 CBT Training : PASS
9104 18:05:53.536708 Write leveling : PASS
9105 18:05:53.536794 RX DQS gating : PASS
9106 18:05:53.539872 RX DQ/DQS(RDDQC) : PASS
9107 18:05:53.543091 TX DQ/DQS : PASS
9108 18:05:53.543177 RX DATLAT : PASS
9109 18:05:53.546457 RX DQ/DQS(Engine): PASS
9110 18:05:53.549755 TX OE : PASS
9111 18:05:53.549842 All Pass.
9112 18:05:53.549920
9113 18:05:53.550016 CH 0, Rank 1
9114 18:05:53.553103 SW Impedance : PASS
9115 18:05:53.556153 DUTY Scan : NO K
9116 18:05:53.556259 ZQ Calibration : PASS
9117 18:05:53.559871 Jitter Meter : NO K
9118 18:05:53.563151 CBT Training : PASS
9119 18:05:53.563276 Write leveling : PASS
9120 18:05:53.566486 RX DQS gating : PASS
9121 18:05:53.569569 RX DQ/DQS(RDDQC) : PASS
9122 18:05:53.569653 TX DQ/DQS : PASS
9123 18:05:53.572723 RX DATLAT : PASS
9124 18:05:53.576211 RX DQ/DQS(Engine): PASS
9125 18:05:53.576297 TX OE : PASS
9126 18:05:53.579273 All Pass.
9127 18:05:53.579401
9128 18:05:53.579498 CH 1, Rank 0
9129 18:05:53.582533 SW Impedance : PASS
9130 18:05:53.582657 DUTY Scan : NO K
9131 18:05:53.585765 ZQ Calibration : PASS
9132 18:05:53.589372 Jitter Meter : NO K
9133 18:05:53.589462 CBT Training : PASS
9134 18:05:53.592574 Write leveling : PASS
9135 18:05:53.595663 RX DQS gating : PASS
9136 18:05:53.595748 RX DQ/DQS(RDDQC) : PASS
9137 18:05:53.599111 TX DQ/DQS : PASS
9138 18:05:53.602803 RX DATLAT : PASS
9139 18:05:53.602910 RX DQ/DQS(Engine): PASS
9140 18:05:53.605870 TX OE : PASS
9141 18:05:53.605970 All Pass.
9142 18:05:53.606037
9143 18:05:53.608921 CH 1, Rank 1
9144 18:05:53.609006 SW Impedance : PASS
9145 18:05:53.612415 DUTY Scan : NO K
9146 18:05:53.612526 ZQ Calibration : PASS
9147 18:05:53.615619 Jitter Meter : NO K
9148 18:05:53.619251 CBT Training : PASS
9149 18:05:53.619326 Write leveling : PASS
9150 18:05:53.622068 RX DQS gating : PASS
9151 18:05:53.625455 RX DQ/DQS(RDDQC) : PASS
9152 18:05:53.625532 TX DQ/DQS : PASS
9153 18:05:53.628714 RX DATLAT : PASS
9154 18:05:53.632460 RX DQ/DQS(Engine): PASS
9155 18:05:53.632534 TX OE : PASS
9156 18:05:53.635707 All Pass.
9157 18:05:53.635779
9158 18:05:53.635842 DramC Write-DBI on
9159 18:05:53.639090 PER_BANK_REFRESH: Hybrid Mode
9160 18:05:53.639203 TX_TRACKING: ON
9161 18:05:53.648377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9162 18:05:53.658552 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9163 18:05:53.665033 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9164 18:05:53.668234 [FAST_K] Save calibration result to emmc
9165 18:05:53.671599 sync common calibartion params.
9166 18:05:53.671677 sync cbt_mode0:1, 1:1
9167 18:05:53.675288 dram_init: ddr_geometry: 2
9168 18:05:53.678565 dram_init: ddr_geometry: 2
9169 18:05:53.681987 dram_init: ddr_geometry: 2
9170 18:05:53.682091 0:dram_rank_size:100000000
9171 18:05:53.685191 1:dram_rank_size:100000000
9172 18:05:53.691963 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9173 18:05:53.692043 DFS_SHUFFLE_HW_MODE: ON
9174 18:05:53.698379 dramc_set_vcore_voltage set vcore to 725000
9175 18:05:53.698461 Read voltage for 1600, 0
9176 18:05:53.698527 Vio18 = 0
9177 18:05:53.701587 Vcore = 725000
9178 18:05:53.701667 Vdram = 0
9179 18:05:53.701730 Vddq = 0
9180 18:05:53.705084 Vmddr = 0
9181 18:05:53.705184 switch to 3200 Mbps bootup
9182 18:05:53.708385 [DramcRunTimeConfig]
9183 18:05:53.708459 PHYPLL
9184 18:05:53.711598 DPM_CONTROL_AFTERK: ON
9185 18:05:53.711703 PER_BANK_REFRESH: ON
9186 18:05:53.714611 REFRESH_OVERHEAD_REDUCTION: ON
9187 18:05:53.718208 CMD_PICG_NEW_MODE: OFF
9188 18:05:53.718285 XRTWTW_NEW_MODE: ON
9189 18:05:53.721620 XRTRTR_NEW_MODE: ON
9190 18:05:53.721723 TX_TRACKING: ON
9191 18:05:53.724994 RDSEL_TRACKING: OFF
9192 18:05:53.728244 DQS Precalculation for DVFS: ON
9193 18:05:53.728349 RX_TRACKING: OFF
9194 18:05:53.731364 HW_GATING DBG: ON
9195 18:05:53.731442 ZQCS_ENABLE_LP4: ON
9196 18:05:53.734603 RX_PICG_NEW_MODE: ON
9197 18:05:53.734679 TX_PICG_NEW_MODE: ON
9198 18:05:53.738013 ENABLE_RX_DCM_DPHY: ON
9199 18:05:53.741242 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9200 18:05:53.744531 DUMMY_READ_FOR_TRACKING: OFF
9201 18:05:53.747786 !!! SPM_CONTROL_AFTERK: OFF
9202 18:05:53.747874 !!! SPM could not control APHY
9203 18:05:53.751041 IMPEDANCE_TRACKING: ON
9204 18:05:53.751117 TEMP_SENSOR: ON
9205 18:05:53.754455 HW_SAVE_FOR_SR: OFF
9206 18:05:53.757762 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9207 18:05:53.760955 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9208 18:05:53.764795 Read ODT Tracking: ON
9209 18:05:53.764877 Refresh Rate DeBounce: ON
9210 18:05:53.768047 DFS_NO_QUEUE_FLUSH: ON
9211 18:05:53.771338 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9212 18:05:53.774513 ENABLE_DFS_RUNTIME_MRW: OFF
9213 18:05:53.774599 DDR_RESERVE_NEW_MODE: ON
9214 18:05:53.777613 MR_CBT_SWITCH_FREQ: ON
9215 18:05:53.780810 =========================
9216 18:05:53.799008 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9217 18:05:53.801917 dram_init: ddr_geometry: 2
9218 18:05:53.820424 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9219 18:05:53.823567 dram_init: dram init end (result: 0)
9220 18:05:53.830462 DRAM-K: Full calibration passed in 24516 msecs
9221 18:05:53.833755 MRC: failed to locate region type 0.
9222 18:05:53.833840 DRAM rank0 size:0x100000000,
9223 18:05:53.837100 DRAM rank1 size=0x100000000
9224 18:05:53.846981 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9225 18:05:53.853524 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9226 18:05:53.860156 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9227 18:05:53.866496 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9228 18:05:53.870292 DRAM rank0 size:0x100000000,
9229 18:05:53.873088 DRAM rank1 size=0x100000000
9230 18:05:53.873170 CBMEM:
9231 18:05:53.876726 IMD: root @ 0xfffff000 254 entries.
9232 18:05:53.879985 IMD: root @ 0xffffec00 62 entries.
9233 18:05:53.883078 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9234 18:05:53.889880 WARNING: RO_VPD is uninitialized or empty.
9235 18:05:53.893140 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9236 18:05:53.900555 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9237 18:05:53.913332 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9238 18:05:53.924860 BS: romstage times (exec / console): total (unknown) / 24015 ms
9239 18:05:53.924948
9240 18:05:53.925017
9241 18:05:53.934899 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9242 18:05:53.938045 ARM64: Exception handlers installed.
9243 18:05:53.941251 ARM64: Testing exception
9244 18:05:53.944629 ARM64: Done test exception
9245 18:05:53.944702 Enumerating buses...
9246 18:05:53.947835 Show all devs... Before device enumeration.
9247 18:05:53.951177 Root Device: enabled 1
9248 18:05:53.954378 CPU_CLUSTER: 0: enabled 1
9249 18:05:53.954483 CPU: 00: enabled 1
9250 18:05:53.957654 Compare with tree...
9251 18:05:53.957726 Root Device: enabled 1
9252 18:05:53.960933 CPU_CLUSTER: 0: enabled 1
9253 18:05:53.964043 CPU: 00: enabled 1
9254 18:05:53.964122 Root Device scanning...
9255 18:05:53.967773 scan_static_bus for Root Device
9256 18:05:53.971028 CPU_CLUSTER: 0 enabled
9257 18:05:53.974207 scan_static_bus for Root Device done
9258 18:05:53.977475 scan_bus: bus Root Device finished in 8 msecs
9259 18:05:53.977582 done
9260 18:05:53.984062 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9261 18:05:53.987753 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9262 18:05:53.994037 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9263 18:05:53.997871 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9264 18:05:54.001026 Allocating resources...
9265 18:05:54.004132 Reading resources...
9266 18:05:54.007631 Root Device read_resources bus 0 link: 0
9267 18:05:54.007710 DRAM rank0 size:0x100000000,
9268 18:05:54.010792 DRAM rank1 size=0x100000000
9269 18:05:54.013983 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9270 18:05:54.017561 CPU: 00 missing read_resources
9271 18:05:54.023891 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9272 18:05:54.027700 Root Device read_resources bus 0 link: 0 done
9273 18:05:54.027796 Done reading resources.
9274 18:05:54.034145 Show resources in subtree (Root Device)...After reading.
9275 18:05:54.037332 Root Device child on link 0 CPU_CLUSTER: 0
9276 18:05:54.040631 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 18:05:54.051091 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 18:05:54.051199 CPU: 00
9279 18:05:54.054264 Root Device assign_resources, bus 0 link: 0
9280 18:05:54.057636 CPU_CLUSTER: 0 missing set_resources
9281 18:05:54.060935 Root Device assign_resources, bus 0 link: 0 done
9282 18:05:54.064237 Done setting resources.
9283 18:05:54.071139 Show resources in subtree (Root Device)...After assigning values.
9284 18:05:54.074289 Root Device child on link 0 CPU_CLUSTER: 0
9285 18:05:54.077541 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 18:05:54.087312 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 18:05:54.087421 CPU: 00
9288 18:05:54.090616 Done allocating resources.
9289 18:05:54.093913 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9290 18:05:54.097552 Enabling resources...
9291 18:05:54.097654 done.
9292 18:05:54.104000 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9293 18:05:54.104105 Initializing devices...
9294 18:05:54.107246 Root Device init
9295 18:05:54.107346 init hardware done!
9296 18:05:54.110481 0x00000018: ctrlr->caps
9297 18:05:54.113661 52.000 MHz: ctrlr->f_max
9298 18:05:54.113742 0.400 MHz: ctrlr->f_min
9299 18:05:54.116940 0x40ff8080: ctrlr->voltages
9300 18:05:54.117016 sclk: 390625
9301 18:05:54.120622 Bus Width = 1
9302 18:05:54.120722 sclk: 390625
9303 18:05:54.123589 Bus Width = 1
9304 18:05:54.123667 Early init status = 3
9305 18:05:54.130301 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9306 18:05:54.133700 in-header: 03 fc 00 00 01 00 00 00
9307 18:05:54.133834 in-data: 00
9308 18:05:54.140341 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9309 18:05:54.143829 in-header: 03 fd 00 00 00 00 00 00
9310 18:05:54.147164 in-data:
9311 18:05:54.150417 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9312 18:05:54.154361 in-header: 03 fc 00 00 01 00 00 00
9313 18:05:54.157576 in-data: 00
9314 18:05:54.160893 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9315 18:05:54.166345 in-header: 03 fd 00 00 00 00 00 00
9316 18:05:54.170082 in-data:
9317 18:05:54.173319 [SSUSB] Setting up USB HOST controller...
9318 18:05:54.176481 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 18:05:54.179681 [SSUSB] phy power-on done.
9320 18:05:54.182946 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 18:05:54.189368 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 18:05:54.193086 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 18:05:54.199574 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 18:05:54.206437 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 18:05:54.212908 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 18:05:54.219317 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 18:05:54.225975 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 18:05:54.229163 SPM: binary array size = 0x9dc
9329 18:05:54.232751 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 18:05:54.239410 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 18:05:54.246199 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 18:05:54.252816 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 18:05:54.255951 configure_display: Starting display init
9334 18:05:54.290059 anx7625_power_on_init: Init interface.
9335 18:05:54.293253 anx7625_disable_pd_protocol: Disabled PD feature.
9336 18:05:54.296528 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 18:05:54.324093 anx7625_start_dp_work: Secure OCM version=00
9338 18:05:54.327687 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 18:05:54.342315 sp_tx_get_edid_block: EDID Block = 1
9340 18:05:54.444817 Extracted contents:
9341 18:05:54.448196 header: 00 ff ff ff ff ff ff 00
9342 18:05:54.451193 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 18:05:54.454983 version: 01 04
9344 18:05:54.458268 basic params: 95 1f 11 78 0a
9345 18:05:54.461576 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 18:05:54.464866 established: 00 00 00
9347 18:05:54.471422 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 18:05:54.474617 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 18:05:54.481510 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 18:05:54.488038 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 18:05:54.494495 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 18:05:54.497738 extensions: 00
9353 18:05:54.497819 checksum: fb
9354 18:05:54.497885
9355 18:05:54.501065 Manufacturer: IVO Model 57d Serial Number 0
9356 18:05:54.504317 Made week 0 of 2020
9357 18:05:54.504417 EDID version: 1.4
9358 18:05:54.507489 Digital display
9359 18:05:54.510822 6 bits per primary color channel
9360 18:05:54.510925 DisplayPort interface
9361 18:05:54.514111 Maximum image size: 31 cm x 17 cm
9362 18:05:54.517795 Gamma: 220%
9363 18:05:54.517898 Check DPMS levels
9364 18:05:54.521202 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 18:05:54.527693 First detailed timing is preferred timing
9366 18:05:54.527800 Established timings supported:
9367 18:05:54.530902 Standard timings supported:
9368 18:05:54.534057 Detailed timings
9369 18:05:54.537570 Hex of detail: 383680a07038204018303c0035ae10000019
9370 18:05:54.540651 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 18:05:54.547609 0780 0798 07c8 0820 hborder 0
9372 18:05:54.550737 0438 043b 0447 0458 vborder 0
9373 18:05:54.553970 -hsync -vsync
9374 18:05:54.554068 Did detailed timing
9375 18:05:54.560699 Hex of detail: 000000000000000000000000000000000000
9376 18:05:54.560798 Manufacturer-specified data, tag 0
9377 18:05:54.567431 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 18:05:54.570635 ASCII string: InfoVision
9379 18:05:54.574372 Hex of detail: 000000fe00523134304e574635205248200a
9380 18:05:54.577161 ASCII string: R140NWF5 RH
9381 18:05:54.577257 Checksum
9382 18:05:54.580909 Checksum: 0xfb (valid)
9383 18:05:54.584191 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 18:05:54.587470 DSI data_rate: 832800000 bps
9385 18:05:54.594017 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 18:05:54.597253 anx7625_parse_edid: pixelclock(138800).
9387 18:05:54.600468 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 18:05:54.603773 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 18:05:54.607058 anx7625_dsi_config: config dsi.
9390 18:05:54.614111 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 18:05:54.626842 anx7625_dsi_config: success to config DSI
9392 18:05:54.629956 anx7625_dp_start: MIPI phy setup OK.
9393 18:05:54.633617 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 18:05:54.636763 mtk_ddp_mode_set invalid vrefresh 60
9395 18:05:54.639953 main_disp_path_setup
9396 18:05:54.640024 ovl_layer_smi_id_en
9397 18:05:54.643538 ovl_layer_smi_id_en
9398 18:05:54.643614 ccorr_config
9399 18:05:54.643678 aal_config
9400 18:05:54.646633 gamma_config
9401 18:05:54.646706 postmask_config
9402 18:05:54.650327 dither_config
9403 18:05:54.653368 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 18:05:54.660221 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 18:05:54.663328 Root Device init finished in 553 msecs
9406 18:05:54.666612 CPU_CLUSTER: 0 init
9407 18:05:54.673230 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 18:05:54.676527 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 18:05:54.679734 APU_MBOX 0x190000b0 = 0x10001
9410 18:05:54.683534 APU_MBOX 0x190001b0 = 0x10001
9411 18:05:54.686806 APU_MBOX 0x190005b0 = 0x10001
9412 18:05:54.690086 APU_MBOX 0x190006b0 = 0x10001
9413 18:05:54.693270 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 18:05:54.705655 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9415 18:05:54.718253 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 18:05:54.725122 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 18:05:54.736507 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9418 18:05:54.745722 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 18:05:54.748868 CPU_CLUSTER: 0 init finished in 81 msecs
9420 18:05:54.752032 Devices initialized
9421 18:05:54.755519 Show all devs... After init.
9422 18:05:54.755620 Root Device: enabled 1
9423 18:05:54.758833 CPU_CLUSTER: 0: enabled 1
9424 18:05:54.761975 CPU: 00: enabled 1
9425 18:05:54.765650 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9426 18:05:54.768948 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 18:05:54.772194 ELOG: NV offset 0x57f000 size 0x1000
9428 18:05:54.778986 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9429 18:05:54.785479 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 18:05:54.788858 ELOG: Event(17) added with size 13 at 2024-06-11 18:04:29 UTC
9431 18:05:54.792046 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 18:05:54.795763 in-header: 03 28 00 00 2c 00 00 00
9433 18:05:54.809275 in-data: 16 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 18:05:54.815658 ELOG: Event(A1) added with size 10 at 2024-06-11 18:04:29 UTC
9435 18:05:54.822652 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9436 18:05:54.829144 ELOG: Event(A0) added with size 9 at 2024-06-11 18:04:29 UTC
9437 18:05:54.832288 elog_add_boot_reason: Logged dev mode boot
9438 18:05:54.835502 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9439 18:05:54.839243 Finalize devices...
9440 18:05:54.839344 Devices finalized
9441 18:05:54.845602 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 18:05:54.848716 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9443 18:05:54.852457 in-header: 03 07 00 00 08 00 00 00
9444 18:05:54.855595 in-data: aa e4 47 04 13 02 00 00
9445 18:05:54.858770 Chrome EC: UHEPI supported
9446 18:05:54.865223 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9447 18:05:54.868882 in-header: 03 a9 00 00 08 00 00 00
9448 18:05:54.872035 in-data: 84 60 60 08 00 00 00 00
9449 18:05:54.875490 ELOG: Event(91) added with size 10 at 2024-06-11 18:04:29 UTC
9450 18:05:54.881712 Chrome EC: clear events_b mask to 0x0000000020004000
9451 18:05:54.888654 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9452 18:05:54.892032 in-header: 03 fd 00 00 00 00 00 00
9453 18:05:54.892136 in-data:
9454 18:05:54.898711 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9455 18:05:54.901973 Writing coreboot table at 0xffe64000
9456 18:05:54.905672 0. 000000000010a000-0000000000113fff: RAMSTAGE
9457 18:05:54.908981 1. 0000000040000000-00000000400fffff: RAM
9458 18:05:54.912212 2. 0000000040100000-000000004032afff: RAMSTAGE
9459 18:05:54.918841 3. 000000004032b000-00000000545fffff: RAM
9460 18:05:54.922022 4. 0000000054600000-000000005465ffff: BL31
9461 18:05:54.925286 5. 0000000054660000-00000000ffe63fff: RAM
9462 18:05:54.929058 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9463 18:05:54.935433 7. 0000000100000000-000000023fffffff: RAM
9464 18:05:54.935542 Passing 5 GPIOs to payload:
9465 18:05:54.941926 NAME | PORT | POLARITY | VALUE
9466 18:05:54.945421 EC in RW | 0x000000aa | low | undefined
9467 18:05:54.951981 EC interrupt | 0x00000005 | low | undefined
9468 18:05:54.955235 TPM interrupt | 0x000000ab | high | undefined
9469 18:05:54.958860 SD card detect | 0x00000011 | high | undefined
9470 18:05:54.965478 speaker enable | 0x00000093 | high | undefined
9471 18:05:54.968847 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9472 18:05:54.971964 in-header: 03 f9 00 00 02 00 00 00
9473 18:05:54.972065 in-data: 02 00
9474 18:05:54.975018 ADC[4]: Raw value=901032 ID=7
9475 18:05:54.978924 ADC[3]: Raw value=213179 ID=1
9476 18:05:54.979028 RAM Code: 0x71
9477 18:05:54.982271 ADC[6]: Raw value=74502 ID=0
9478 18:05:54.984888 ADC[5]: Raw value=212441 ID=1
9479 18:05:54.984992 SKU Code: 0x1
9480 18:05:54.991828 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 96a6
9481 18:05:54.995076 coreboot table: 964 bytes.
9482 18:05:54.998295 IMD ROOT 0. 0xfffff000 0x00001000
9483 18:05:55.001508 IMD SMALL 1. 0xffffe000 0x00001000
9484 18:05:55.005279 RO MCACHE 2. 0xffffc000 0x00001104
9485 18:05:55.008457 CONSOLE 3. 0xfff7c000 0x00080000
9486 18:05:55.011777 FMAP 4. 0xfff7b000 0x00000452
9487 18:05:55.015080 TIME STAMP 5. 0xfff7a000 0x00000910
9488 18:05:55.018273 VBOOT WORK 6. 0xfff66000 0x00014000
9489 18:05:55.021497 RAMOOPS 7. 0xffe66000 0x00100000
9490 18:05:55.024789 COREBOOT 8. 0xffe64000 0x00002000
9491 18:05:55.024874 IMD small region:
9492 18:05:55.028045 IMD ROOT 0. 0xffffec00 0x00000400
9493 18:05:55.031372 VPD 1. 0xffffeb80 0x0000006c
9494 18:05:55.034712 MMC STATUS 2. 0xffffeb60 0x00000004
9495 18:05:55.041524 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9496 18:05:55.047882 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9497 18:05:55.087965 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9498 18:05:55.091181 Checking segment from ROM address 0x40100000
9499 18:05:55.094364 Checking segment from ROM address 0x4010001c
9500 18:05:55.100972 Loading segment from ROM address 0x40100000
9501 18:05:55.101058 code (compression=0)
9502 18:05:55.110986 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9503 18:05:55.117574 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9504 18:05:55.117654 it's not compressed!
9505 18:05:55.124089 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9506 18:05:55.127877 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9507 18:05:55.148058 Loading segment from ROM address 0x4010001c
9508 18:05:55.148140 Entry Point 0x80000000
9509 18:05:55.151231 Loaded segments
9510 18:05:55.154434 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9511 18:05:55.161077 Jumping to boot code at 0x80000000(0xffe64000)
9512 18:05:55.168138 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9513 18:05:55.174708 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9514 18:05:55.182479 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9515 18:05:55.185718 Checking segment from ROM address 0x40100000
9516 18:05:55.188930 Checking segment from ROM address 0x4010001c
9517 18:05:55.196001 Loading segment from ROM address 0x40100000
9518 18:05:55.196079 code (compression=1)
9519 18:05:55.202711 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9520 18:05:55.212639 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9521 18:05:55.212722 using LZMA
9522 18:05:55.220857 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9523 18:05:55.227450 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9524 18:05:55.230672 Loading segment from ROM address 0x4010001c
9525 18:05:55.233994 Entry Point 0x54601000
9526 18:05:55.234065 Loaded segments
9527 18:05:55.237094 NOTICE: MT8192 bl31_setup
9528 18:05:55.244216 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9529 18:05:55.247778 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9530 18:05:55.250993 WARNING: region 0:
9531 18:05:55.254241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 18:05:55.254312 WARNING: region 1:
9533 18:05:55.261246 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9534 18:05:55.264382 WARNING: region 2:
9535 18:05:55.267641 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9536 18:05:55.270892 WARNING: region 3:
9537 18:05:55.274423 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 18:05:55.277511 WARNING: region 4:
9539 18:05:55.284296 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 18:05:55.284371 WARNING: region 5:
9541 18:05:55.287434 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 18:05:55.290666 WARNING: region 6:
9543 18:05:55.293844 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 18:05:55.297628 WARNING: region 7:
9545 18:05:55.300963 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 18:05:55.307182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9547 18:05:55.310923 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9548 18:05:55.314095 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9549 18:05:55.320543 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9550 18:05:55.323868 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9551 18:05:55.327628 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9552 18:05:55.334113 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9553 18:05:55.337364 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9554 18:05:55.343765 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9555 18:05:55.347553 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9556 18:05:55.350651 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9557 18:05:55.357291 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9558 18:05:55.360533 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9559 18:05:55.363864 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9560 18:05:55.370400 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9561 18:05:55.373584 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9562 18:05:55.380366 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9563 18:05:55.383577 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9564 18:05:55.387386 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9565 18:05:55.393442 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9566 18:05:55.397291 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9567 18:05:55.403662 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9568 18:05:55.407423 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9569 18:05:55.410563 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9570 18:05:55.417076 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9571 18:05:55.420268 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9572 18:05:55.426729 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9573 18:05:55.430143 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9574 18:05:55.433934 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9575 18:05:55.440493 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9576 18:05:55.443835 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9577 18:05:55.450577 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9578 18:05:55.453869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9579 18:05:55.456923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9580 18:05:55.460245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9581 18:05:55.466830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9582 18:05:55.470106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9583 18:05:55.473283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9584 18:05:55.476509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9585 18:05:55.483365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9586 18:05:55.486466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9587 18:05:55.490203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9588 18:05:55.493189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9589 18:05:55.500022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9590 18:05:55.503287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9591 18:05:55.506507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9592 18:05:55.509662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9593 18:05:55.516278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9594 18:05:55.520087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9595 18:05:55.526620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9596 18:05:55.529387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9597 18:05:55.536075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9598 18:05:55.539291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9599 18:05:55.543111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9600 18:05:55.549701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9601 18:05:55.552980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9602 18:05:55.559179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9603 18:05:55.562982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9604 18:05:55.566229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9605 18:05:55.572644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9606 18:05:55.576374 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9607 18:05:55.582657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9608 18:05:55.585850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9609 18:05:55.592824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9610 18:05:55.596284 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9611 18:05:55.602527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9612 18:05:55.605931 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9613 18:05:55.609543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9614 18:05:55.616079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9615 18:05:55.619151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9616 18:05:55.625670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9617 18:05:55.628960 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9618 18:05:55.636083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9619 18:05:55.639359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9620 18:05:55.642584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9621 18:05:55.649204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9622 18:05:55.652460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9623 18:05:55.658935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9624 18:05:55.662547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9625 18:05:55.669453 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9626 18:05:55.672329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9627 18:05:55.679119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9628 18:05:55.682392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9629 18:05:55.686071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9630 18:05:55.692464 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9631 18:05:55.695687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9632 18:05:55.702326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9633 18:05:55.705520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9634 18:05:55.712210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9635 18:05:55.715849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9636 18:05:55.719053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9637 18:05:55.725470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9638 18:05:55.728809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9639 18:05:55.735378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9640 18:05:55.738683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9641 18:05:55.745654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9642 18:05:55.749105 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9643 18:05:55.751867 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9644 18:05:55.755170 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9645 18:05:55.762249 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9646 18:05:55.765354 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9647 18:05:55.768572 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9648 18:05:55.775756 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9649 18:05:55.778943 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9650 18:05:55.785403 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9651 18:05:55.788597 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9652 18:05:55.792168 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9653 18:05:55.798850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9654 18:05:55.801956 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9655 18:05:55.808875 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9656 18:05:55.811979 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9657 18:05:55.815707 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9658 18:05:55.821870 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9659 18:05:55.825559 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9660 18:05:55.832132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9661 18:05:55.835368 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9662 18:05:55.838644 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9663 18:05:55.841914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9664 18:05:55.848411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9665 18:05:55.851777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9666 18:05:55.855155 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9667 18:05:55.858416 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9668 18:05:55.864982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9669 18:05:55.868683 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9670 18:05:55.871831 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9671 18:05:55.878229 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9672 18:05:55.882074 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9673 18:05:55.888106 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9674 18:05:55.891424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9675 18:05:55.895162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9676 18:05:55.901430 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9677 18:05:55.905137 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9678 18:05:55.911431 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9679 18:05:55.915075 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9680 18:05:55.918222 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9681 18:05:55.924813 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9682 18:05:55.927950 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9683 18:05:55.935015 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9684 18:05:55.938257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9685 18:05:55.941607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9686 18:05:55.948002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9687 18:05:55.951154 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9688 18:05:55.957668 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9689 18:05:55.961076 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9690 18:05:55.964352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9691 18:05:55.971456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9692 18:05:55.974734 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9693 18:05:55.977916 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9694 18:05:55.984444 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9695 18:05:55.987793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9696 18:05:55.994778 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9697 18:05:55.997915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9698 18:05:56.001156 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9699 18:05:56.007976 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9700 18:05:56.011139 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9701 18:05:56.017646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9702 18:05:56.020788 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9703 18:05:56.024425 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9704 18:05:56.030955 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9705 18:05:56.034078 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9706 18:05:56.041101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9707 18:05:56.044304 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9708 18:05:56.047562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9709 18:05:56.054107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9710 18:05:56.057853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9711 18:05:56.061054 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9712 18:05:56.067628 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9713 18:05:56.071000 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9714 18:05:56.077442 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9715 18:05:56.081273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9716 18:05:56.084395 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9717 18:05:56.090898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9718 18:05:56.094056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9719 18:05:56.100680 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9720 18:05:56.104250 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9721 18:05:56.107453 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9722 18:05:56.114118 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9723 18:05:56.117345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9724 18:05:56.124219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9725 18:05:56.127233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9726 18:05:56.130845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9727 18:05:56.137482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9728 18:05:56.140774 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9729 18:05:56.143995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9730 18:05:56.150475 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9731 18:05:56.153907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9732 18:05:56.160388 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9733 18:05:56.163694 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9734 18:05:56.166938 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9735 18:05:56.174026 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9736 18:05:56.177416 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9737 18:05:56.183607 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9738 18:05:56.187279 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9739 18:05:56.193689 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9740 18:05:56.197067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9741 18:05:56.200224 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9742 18:05:56.206819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9743 18:05:56.210240 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9744 18:05:56.216969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9745 18:05:56.220494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9746 18:05:56.223704 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9747 18:05:56.230177 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9748 18:05:56.233743 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9749 18:05:56.240318 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9750 18:05:56.243428 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9751 18:05:56.250102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9752 18:05:56.253915 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9753 18:05:56.257171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9754 18:05:56.263834 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9755 18:05:56.266974 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9756 18:05:56.273399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9757 18:05:56.276799 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9758 18:05:56.280107 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9759 18:05:56.287033 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9760 18:05:56.290221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9761 18:05:56.296783 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9762 18:05:56.299956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9763 18:05:56.306505 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9764 18:05:56.310177 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9765 18:05:56.313357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9766 18:05:56.320158 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9767 18:05:56.323135 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9768 18:05:56.329914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9769 18:05:56.333412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9770 18:05:56.336535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9771 18:05:56.343084 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9772 18:05:56.346632 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9773 18:05:56.352924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9774 18:05:56.356325 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9775 18:05:56.359667 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9776 18:05:56.366311 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9777 18:05:56.369596 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9778 18:05:56.373477 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9779 18:05:56.376707 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9780 18:05:56.383316 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9781 18:05:56.386494 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9782 18:05:56.389730 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9783 18:05:56.396535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9784 18:05:56.399848 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9785 18:05:56.403077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9786 18:05:56.409533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9787 18:05:56.412914 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9788 18:05:56.419786 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9789 18:05:56.422951 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9790 18:05:56.426146 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9791 18:05:56.432892 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9792 18:05:56.436493 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9793 18:05:56.439324 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9794 18:05:56.446032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9795 18:05:56.449522 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9796 18:05:56.452754 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9797 18:05:56.459238 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9798 18:05:56.462553 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9799 18:05:56.465843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9800 18:05:56.472949 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9801 18:05:56.476181 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9802 18:05:56.482851 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9803 18:05:56.486101 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9804 18:05:56.489436 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9805 18:05:56.495910 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9806 18:05:56.499137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9807 18:05:56.505704 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9808 18:05:56.508941 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9809 18:05:56.512724 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9810 18:05:56.519082 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9811 18:05:56.522435 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9812 18:05:56.525983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9813 18:05:56.532378 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9814 18:05:56.536002 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9815 18:05:56.539160 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9816 18:05:56.542244 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9817 18:05:56.548920 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9818 18:05:56.552414 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9819 18:05:56.555412 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9820 18:05:56.558724 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9821 18:05:56.565863 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9822 18:05:56.569055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9823 18:05:56.572382 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9824 18:05:56.575696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9825 18:05:56.582174 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9826 18:05:56.585501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9827 18:05:56.588701 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9828 18:05:56.595743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9829 18:05:56.599029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9830 18:05:56.602065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9831 18:05:56.609054 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9832 18:05:56.612315 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9833 18:05:56.618892 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9834 18:05:56.622164 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9835 18:05:56.625289 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9836 18:05:56.631818 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9837 18:05:56.635307 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9838 18:05:56.642070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9839 18:05:56.645319 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9840 18:05:56.652140 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9841 18:05:56.655204 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9842 18:05:56.658735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9843 18:05:56.664973 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9844 18:05:56.668239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9845 18:05:56.674853 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9846 18:05:56.678237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9847 18:05:56.681483 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9848 18:05:56.688411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9849 18:05:56.691690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9850 18:05:56.698618 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9851 18:05:56.701871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9852 18:05:56.705041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9853 18:05:56.711729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9854 18:05:56.715038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9855 18:05:56.721535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9856 18:05:56.724873 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9857 18:05:56.731660 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9858 18:05:56.735216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9859 18:05:56.738448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9860 18:05:56.744802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9861 18:05:56.748477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9862 18:05:56.754829 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9863 18:05:56.758528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9864 18:05:56.761527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9865 18:05:56.767997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9866 18:05:56.771573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9867 18:05:56.778149 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9868 18:05:56.781468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9869 18:05:56.784686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9870 18:05:56.791242 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9871 18:05:56.794601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9872 18:05:56.801477 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9873 18:05:56.804852 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9874 18:05:56.811324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9875 18:05:56.814607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9876 18:05:56.817887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9877 18:05:56.824905 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9878 18:05:56.828294 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9879 18:05:56.831364 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9880 18:05:56.838325 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9881 18:05:56.841315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9882 18:05:56.847708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9883 18:05:56.851318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9884 18:05:56.854444 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9885 18:05:56.861329 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9886 18:05:56.864410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9887 18:05:56.871180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9888 18:05:56.874453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9889 18:05:56.881212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9890 18:05:56.884427 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9891 18:05:56.887638 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9892 18:05:56.894180 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9893 18:05:56.897528 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9894 18:05:56.904254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9895 18:05:56.907507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9896 18:05:56.910850 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9897 18:05:56.917470 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9898 18:05:56.920872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9899 18:05:56.927498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9900 18:05:56.930769 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9901 18:05:56.937194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9902 18:05:56.940917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9903 18:05:56.944048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9904 18:05:56.950831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9905 18:05:56.954269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9906 18:05:56.960428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9907 18:05:56.964172 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9908 18:05:56.967442 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9909 18:05:56.974054 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9910 18:05:56.977438 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9911 18:05:56.984173 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9912 18:05:56.987426 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9913 18:05:56.993979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9914 18:05:56.997190 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9915 18:05:57.003833 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9916 18:05:57.007047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9917 18:05:57.010307 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9918 18:05:57.017133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9919 18:05:57.020182 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9920 18:05:57.026807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9921 18:05:57.030510 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9922 18:05:57.037041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9923 18:05:57.040117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9924 18:05:57.043333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9925 18:05:57.050164 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9926 18:05:57.053860 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9927 18:05:57.059994 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9928 18:05:57.063540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9929 18:05:57.069768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9930 18:05:57.073459 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9931 18:05:57.079782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9932 18:05:57.083587 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9933 18:05:57.086813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9934 18:05:57.093383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9935 18:05:57.096760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9936 18:05:57.103407 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9937 18:05:57.106633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9938 18:05:57.113330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9939 18:05:57.116584 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9940 18:05:57.119787 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9941 18:05:57.126642 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9942 18:05:57.129896 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9943 18:05:57.136706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9944 18:05:57.140072 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9945 18:05:57.146429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9946 18:05:57.149661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9947 18:05:57.153214 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9948 18:05:57.159802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9949 18:05:57.162985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9950 18:05:57.169724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9951 18:05:57.172772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9952 18:05:57.179623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9953 18:05:57.182928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9954 18:05:57.189514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9955 18:05:57.192905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9956 18:05:57.199631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9957 18:05:57.202995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9958 18:05:57.209559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9959 18:05:57.212778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9960 18:05:57.216033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9961 18:05:57.222748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9962 18:05:57.225956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9963 18:05:57.232873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9964 18:05:57.235969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9965 18:05:57.243062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9966 18:05:57.246238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9967 18:05:57.252976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9968 18:05:57.256254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9969 18:05:57.262565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9970 18:05:57.266213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9971 18:05:57.272669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9972 18:05:57.275958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9973 18:05:57.282753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9974 18:05:57.285834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9975 18:05:57.292405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9976 18:05:57.296143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9977 18:05:57.302731 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9978 18:05:57.305583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9979 18:05:57.312269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9980 18:05:57.315597 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9981 18:05:57.318925 INFO: [APUAPC] vio 0
9982 18:05:57.322163 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9983 18:05:57.328745 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9984 18:05:57.332330 INFO: [APUAPC] D0_APC_0: 0x400510
9985 18:05:57.335676 INFO: [APUAPC] D0_APC_1: 0x0
9986 18:05:57.335754 INFO: [APUAPC] D0_APC_2: 0x1540
9987 18:05:57.338944 INFO: [APUAPC] D0_APC_3: 0x0
9988 18:05:57.342107 INFO: [APUAPC] D1_APC_0: 0xffffffff
9989 18:05:57.345387 INFO: [APUAPC] D1_APC_1: 0xffffffff
9990 18:05:57.349170 INFO: [APUAPC] D1_APC_2: 0x3fffff
9991 18:05:57.352338 INFO: [APUAPC] D1_APC_3: 0x0
9992 18:05:57.355878 INFO: [APUAPC] D2_APC_0: 0xffffffff
9993 18:05:57.359191 INFO: [APUAPC] D2_APC_1: 0xffffffff
9994 18:05:57.362469 INFO: [APUAPC] D2_APC_2: 0x3fffff
9995 18:05:57.365476 INFO: [APUAPC] D2_APC_3: 0x0
9996 18:05:57.368908 INFO: [APUAPC] D3_APC_0: 0xffffffff
9997 18:05:57.372251 INFO: [APUAPC] D3_APC_1: 0xffffffff
9998 18:05:57.375916 INFO: [APUAPC] D3_APC_2: 0x3fffff
9999 18:05:57.379130 INFO: [APUAPC] D3_APC_3: 0x0
10000 18:05:57.382291 INFO: [APUAPC] D4_APC_0: 0xffffffff
10001 18:05:57.385446 INFO: [APUAPC] D4_APC_1: 0xffffffff
10002 18:05:57.388977 INFO: [APUAPC] D4_APC_2: 0x3fffff
10003 18:05:57.392110 INFO: [APUAPC] D4_APC_3: 0x0
10004 18:05:57.395371 INFO: [APUAPC] D5_APC_0: 0xffffffff
10005 18:05:57.398593 INFO: [APUAPC] D5_APC_1: 0xffffffff
10006 18:05:57.402329 INFO: [APUAPC] D5_APC_2: 0x3fffff
10007 18:05:57.405663 INFO: [APUAPC] D5_APC_3: 0x0
10008 18:05:57.408947 INFO: [APUAPC] D6_APC_0: 0xffffffff
10009 18:05:57.412213 INFO: [APUAPC] D6_APC_1: 0xffffffff
10010 18:05:57.415507 INFO: [APUAPC] D6_APC_2: 0x3fffff
10011 18:05:57.418849 INFO: [APUAPC] D6_APC_3: 0x0
10012 18:05:57.422140 INFO: [APUAPC] D7_APC_0: 0xffffffff
10013 18:05:57.425551 INFO: [APUAPC] D7_APC_1: 0xffffffff
10014 18:05:57.428895 INFO: [APUAPC] D7_APC_2: 0x3fffff
10015 18:05:57.432101 INFO: [APUAPC] D7_APC_3: 0x0
10016 18:05:57.435189 INFO: [APUAPC] D8_APC_0: 0xffffffff
10017 18:05:57.438575 INFO: [APUAPC] D8_APC_1: 0xffffffff
10018 18:05:57.441815 INFO: [APUAPC] D8_APC_2: 0x3fffff
10019 18:05:57.445074 INFO: [APUAPC] D8_APC_3: 0x0
10020 18:05:57.448707 INFO: [APUAPC] D9_APC_0: 0xffffffff
10021 18:05:57.452059 INFO: [APUAPC] D9_APC_1: 0xffffffff
10022 18:05:57.455230 INFO: [APUAPC] D9_APC_2: 0x3fffff
10023 18:05:57.458418 INFO: [APUAPC] D9_APC_3: 0x0
10024 18:05:57.461965 INFO: [APUAPC] D10_APC_0: 0xffffffff
10025 18:05:57.465145 INFO: [APUAPC] D10_APC_1: 0xffffffff
10026 18:05:57.468666 INFO: [APUAPC] D10_APC_2: 0x3fffff
10027 18:05:57.472113 INFO: [APUAPC] D10_APC_3: 0x0
10028 18:05:57.475256 INFO: [APUAPC] D11_APC_0: 0xffffffff
10029 18:05:57.478354 INFO: [APUAPC] D11_APC_1: 0xffffffff
10030 18:05:57.481903 INFO: [APUAPC] D11_APC_2: 0x3fffff
10031 18:05:57.485148 INFO: [APUAPC] D11_APC_3: 0x0
10032 18:05:57.488661 INFO: [APUAPC] D12_APC_0: 0xffffffff
10033 18:05:57.491678 INFO: [APUAPC] D12_APC_1: 0xffffffff
10034 18:05:57.495384 INFO: [APUAPC] D12_APC_2: 0x3fffff
10035 18:05:57.498623 INFO: [APUAPC] D12_APC_3: 0x0
10036 18:05:57.501911 INFO: [APUAPC] D13_APC_0: 0xffffffff
10037 18:05:57.505126 INFO: [APUAPC] D13_APC_1: 0xffffffff
10038 18:05:57.508363 INFO: [APUAPC] D13_APC_2: 0x3fffff
10039 18:05:57.512194 INFO: [APUAPC] D13_APC_3: 0x0
10040 18:05:57.515349 INFO: [APUAPC] D14_APC_0: 0xffffffff
10041 18:05:57.518684 INFO: [APUAPC] D14_APC_1: 0xffffffff
10042 18:05:57.521933 INFO: [APUAPC] D14_APC_2: 0x3fffff
10043 18:05:57.525297 INFO: [APUAPC] D14_APC_3: 0x0
10044 18:05:57.528536 INFO: [APUAPC] D15_APC_0: 0xffffffff
10045 18:05:57.531953 INFO: [APUAPC] D15_APC_1: 0xffffffff
10046 18:05:57.535279 INFO: [APUAPC] D15_APC_2: 0x3fffff
10047 18:05:57.538388 INFO: [APUAPC] D15_APC_3: 0x0
10048 18:05:57.538466 INFO: [APUAPC] APC_CON: 0x4
10049 18:05:57.541625 INFO: [NOCDAPC] D0_APC_0: 0x0
10050 18:05:57.544924 INFO: [NOCDAPC] D0_APC_1: 0x0
10051 18:05:57.548186 INFO: [NOCDAPC] D1_APC_0: 0x0
10052 18:05:57.551795 INFO: [NOCDAPC] D1_APC_1: 0xfff
10053 18:05:57.554903 INFO: [NOCDAPC] D2_APC_0: 0x0
10054 18:05:57.558630 INFO: [NOCDAPC] D2_APC_1: 0xfff
10055 18:05:57.561972 INFO: [NOCDAPC] D3_APC_0: 0x0
10056 18:05:57.565080 INFO: [NOCDAPC] D3_APC_1: 0xfff
10057 18:05:57.568102 INFO: [NOCDAPC] D4_APC_0: 0x0
10058 18:05:57.571446 INFO: [NOCDAPC] D4_APC_1: 0xfff
10059 18:05:57.571522 INFO: [NOCDAPC] D5_APC_0: 0x0
10060 18:05:57.574654 INFO: [NOCDAPC] D5_APC_1: 0xfff
10061 18:05:57.578218 INFO: [NOCDAPC] D6_APC_0: 0x0
10062 18:05:57.581565 INFO: [NOCDAPC] D6_APC_1: 0xfff
10063 18:05:57.584660 INFO: [NOCDAPC] D7_APC_0: 0x0
10064 18:05:57.588318 INFO: [NOCDAPC] D7_APC_1: 0xfff
10065 18:05:57.591407 INFO: [NOCDAPC] D8_APC_0: 0x0
10066 18:05:57.594594 INFO: [NOCDAPC] D8_APC_1: 0xfff
10067 18:05:57.598231 INFO: [NOCDAPC] D9_APC_0: 0x0
10068 18:05:57.601532 INFO: [NOCDAPC] D9_APC_1: 0xfff
10069 18:05:57.601617 INFO: [NOCDAPC] D10_APC_0: 0x0
10070 18:05:57.604799 INFO: [NOCDAPC] D10_APC_1: 0xfff
10071 18:05:57.608123 INFO: [NOCDAPC] D11_APC_0: 0x0
10072 18:05:57.611467 INFO: [NOCDAPC] D11_APC_1: 0xfff
10073 18:05:57.614698 INFO: [NOCDAPC] D12_APC_0: 0x0
10074 18:05:57.617863 INFO: [NOCDAPC] D12_APC_1: 0xfff
10075 18:05:57.621629 INFO: [NOCDAPC] D13_APC_0: 0x0
10076 18:05:57.624945 INFO: [NOCDAPC] D13_APC_1: 0xfff
10077 18:05:57.628170 INFO: [NOCDAPC] D14_APC_0: 0x0
10078 18:05:57.631498 INFO: [NOCDAPC] D14_APC_1: 0xfff
10079 18:05:57.634796 INFO: [NOCDAPC] D15_APC_0: 0x0
10080 18:05:57.638160 INFO: [NOCDAPC] D15_APC_1: 0xfff
10081 18:05:57.641378 INFO: [NOCDAPC] APC_CON: 0x4
10082 18:05:57.644410 INFO: [APUAPC] set_apusys_apc done
10083 18:05:57.647718 INFO: [DEVAPC] devapc_init done
10084 18:05:57.651044 INFO: GICv3 without legacy support detected.
10085 18:05:57.654826 INFO: ARM GICv3 driver initialized in EL3
10086 18:05:57.657988 INFO: Maximum SPI INTID supported: 639
10087 18:05:57.661208 INFO: BL31: Initializing runtime services
10088 18:05:57.668212 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10089 18:05:57.671309 INFO: SPM: enable CPC mode
10090 18:05:57.677802 INFO: mcdi ready for mcusys-off-idle and system suspend
10091 18:05:57.681364 INFO: BL31: Preparing for EL3 exit to normal world
10092 18:05:57.684417 INFO: Entry point address = 0x80000000
10093 18:05:57.687656 INFO: SPSR = 0x8
10094 18:05:57.692398
10095 18:05:57.692503
10096 18:05:57.692603
10097 18:05:57.695537 Starting depthcharge on Spherion...
10098 18:05:57.695619
10099 18:05:57.695682 Wipe memory regions:
10100 18:05:57.695741
10101 18:05:57.696437 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10102 18:05:57.696604 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10103 18:05:57.696738 Setting prompt string to ['asurada:']
10104 18:05:57.696851 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10105 18:05:57.698746 [0x00000040000000, 0x00000054600000)
10106 18:05:57.821436
10107 18:05:57.821587 [0x00000054660000, 0x00000080000000)
10108 18:05:58.081610
10109 18:05:58.081759 [0x000000821a7280, 0x000000ffe64000)
10110 18:05:58.827260
10111 18:05:58.827558 [0x00000100000000, 0x00000240000000)
10112 18:06:00.717145
10113 18:06:00.720108 Initializing XHCI USB controller at 0x11200000.
10114 18:06:01.758429
10115 18:06:01.761577 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10116 18:06:01.761672
10117 18:06:01.761740
10118 18:06:01.762026 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 18:06:01.862408 asurada: tftpboot 192.168.201.1 14291400/tftp-deploy-hd_dbfq_/kernel/image.itb 14291400/tftp-deploy-hd_dbfq_/kernel/cmdline
10121 18:06:01.862575 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 18:06:01.862658 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10123 18:06:01.866550 tftpboot 192.168.201.1 14291400/tftp-deploy-hd_dbfq_/kernel/image.itp-deploy-hd_dbfq_/kernel/cmdline
10124 18:06:01.866636
10125 18:06:01.866704 Waiting for link
10126 18:06:02.025070
10127 18:06:02.025239 R8152: Initializing
10128 18:06:02.025320
10129 18:06:02.028287 Version 9 (ocp_data = 6010)
10130 18:06:02.028399
10131 18:06:02.031528 R8152: Done initializing
10132 18:06:02.031654
10133 18:06:02.031733 Adding net device
10134 18:06:03.906909
10135 18:06:03.907084 done.
10136 18:06:03.907170
10137 18:06:03.907263 MAC: 00:e0:4c:72:2d:d6
10138 18:06:03.907353
10139 18:06:03.910159 Sending DHCP discover... done.
10140 18:06:03.910239
10141 18:06:03.913137 Waiting for reply... done.
10142 18:06:03.913239
10143 18:06:03.916761 Sending DHCP request... done.
10144 18:06:03.916852
10145 18:06:03.916919 Waiting for reply... done.
10146 18:06:03.916990
10147 18:06:03.919904 My ip is 192.168.201.21
10148 18:06:03.919979
10149 18:06:03.923042 The DHCP server ip is 192.168.201.1
10150 18:06:03.923117
10151 18:06:03.926200 TFTP server IP predefined by user: 192.168.201.1
10152 18:06:03.926276
10153 18:06:03.933176 Bootfile predefined by user: 14291400/tftp-deploy-hd_dbfq_/kernel/image.itb
10154 18:06:03.933292
10155 18:06:03.936415 Sending tftp read request... done.
10156 18:06:03.936516
10157 18:06:03.939570 Waiting for the transfer...
10158 18:06:03.939686
10159 18:06:04.191397 00000000 ################################################################
10160 18:06:04.191564
10161 18:06:04.444290 00080000 ################################################################
10162 18:06:04.444463
10163 18:06:04.696649 00100000 ################################################################
10164 18:06:04.696830
10165 18:06:04.957773 00180000 ################################################################
10166 18:06:04.957950
10167 18:06:05.210154 00200000 ################################################################
10168 18:06:05.210288
10169 18:06:05.468784 00280000 ################################################################
10170 18:06:05.468934
10171 18:06:05.723494 00300000 ################################################################
10172 18:06:05.723635
10173 18:06:05.984792 00380000 ################################################################
10174 18:06:05.984982
10175 18:06:06.241859 00400000 ################################################################
10176 18:06:06.242045
10177 18:06:06.493024 00480000 ################################################################
10178 18:06:06.493196
10179 18:06:06.771190 00500000 ################################################################
10180 18:06:06.771375
10181 18:06:07.030339 00580000 ################################################################
10182 18:06:07.030514
10183 18:06:07.284098 00600000 ################################################################
10184 18:06:07.284277
10185 18:06:07.540227 00680000 ################################################################
10186 18:06:07.540397
10187 18:06:07.801226 00700000 ################################################################
10188 18:06:07.801377
10189 18:06:08.052726 00780000 ################################################################
10190 18:06:08.052899
10191 18:06:08.306693 00800000 ################################################################
10192 18:06:08.306837
10193 18:06:08.556936 00880000 ################################################################
10194 18:06:08.557073
10195 18:06:08.841298 00900000 ################################################################
10196 18:06:08.841429
10197 18:06:09.117522 00980000 ################################################################
10198 18:06:09.117687
10199 18:06:09.380106 00a00000 ################################################################
10200 18:06:09.380282
10201 18:06:09.633330 00a80000 ################################################################
10202 18:06:09.633465
10203 18:06:09.903115 00b00000 ################################################################
10204 18:06:09.903287
10205 18:06:10.161169 00b80000 ################################################################
10206 18:06:10.161345
10207 18:06:10.419517 00c00000 ################################################################
10208 18:06:10.419677
10209 18:06:10.673529 00c80000 ################################################################
10210 18:06:10.673669
10211 18:06:10.938425 00d00000 ################################################################
10212 18:06:10.938557
10213 18:06:11.207108 00d80000 ################################################################
10214 18:06:11.207246
10215 18:06:11.478803 00e00000 ################################################################
10216 18:06:11.478940
10217 18:06:11.756690 00e80000 ################################################################
10218 18:06:11.756825
10219 18:06:12.046501 00f00000 ################################################################
10220 18:06:12.046661
10221 18:06:12.341875 00f80000 ################################################################
10222 18:06:12.342017
10223 18:06:12.629632 01000000 ################################################################
10224 18:06:12.629772
10225 18:06:12.921015 01080000 ################################################################
10226 18:06:12.921157
10227 18:06:13.221847 01100000 ################################################################
10228 18:06:13.222088
10229 18:06:13.606344 01180000 ################################################################
10230 18:06:13.606728
10231 18:06:13.944347 01200000 ################################################################
10232 18:06:13.944490
10233 18:06:14.197408 01280000 ################################################################
10234 18:06:14.197550
10235 18:06:14.452347 01300000 ################################################################
10236 18:06:14.452513
10237 18:06:14.722779 01380000 ################################################################
10238 18:06:14.722946
10239 18:06:14.991890 01400000 ################################################################
10240 18:06:14.992061
10241 18:06:15.258138 01480000 ################################################################
10242 18:06:15.258326
10243 18:06:15.523713 01500000 ################################################################
10244 18:06:15.523859
10245 18:06:15.777027 01580000 ################################################################
10246 18:06:15.777168
10247 18:06:16.039432 01600000 ################################################################
10248 18:06:16.039566
10249 18:06:16.303463 01680000 ################################################################
10250 18:06:16.303599
10251 18:06:16.555388 01700000 ################################################################
10252 18:06:16.555566
10253 18:06:16.807358 01780000 ################################################################
10254 18:06:16.807499
10255 18:06:17.070906 01800000 ################################################################
10256 18:06:17.071072
10257 18:06:17.326512 01880000 ################################################################
10258 18:06:17.326654
10259 18:06:17.579687 01900000 ################################################################
10260 18:06:17.579827
10261 18:06:17.843876 01980000 ################################################################
10262 18:06:17.844036
10263 18:06:18.103540 01a00000 ################################################################
10264 18:06:18.103686
10265 18:06:18.367198 01a80000 ################################################################
10266 18:06:18.367336
10267 18:06:18.639126 01b00000 ################################################################
10268 18:06:18.639266
10269 18:06:18.903295 01b80000 ################################################################
10270 18:06:18.903432
10271 18:06:19.167662 01c00000 ################################################################
10272 18:06:19.167854
10273 18:06:19.430648 01c80000 ################################################################
10274 18:06:19.430788
10275 18:06:19.680560 01d00000 ################################################################
10276 18:06:19.680701
10277 18:06:19.944865 01d80000 ################################################################
10278 18:06:19.945028
10279 18:06:20.174695 01e00000 ######################################################## done.
10280 18:06:20.174850
10281 18:06:20.178293 The bootfile was 31915250 bytes long.
10282 18:06:20.178416
10283 18:06:20.181511 Sending tftp read request... done.
10284 18:06:20.181597
10285 18:06:20.181674 Waiting for the transfer...
10286 18:06:20.181739
10287 18:06:20.185236 00000000 # done.
10288 18:06:20.185311
10289 18:06:20.191361 Command line loaded dynamically from TFTP file: 14291400/tftp-deploy-hd_dbfq_/kernel/cmdline
10290 18:06:20.191447
10291 18:06:20.215135 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10292 18:06:20.215220
10293 18:06:20.215293 Loading FIT.
10294 18:06:20.215355
10295 18:06:20.218357 Image ramdisk-1 has 18740853 bytes.
10296 18:06:20.218429
10297 18:06:20.221487 Image fdt-1 has 47258 bytes.
10298 18:06:20.221561
10299 18:06:20.224791 Image kernel-1 has 13125101 bytes.
10300 18:06:20.224863
10301 18:06:20.235254 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10302 18:06:20.235332
10303 18:06:20.251699 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10304 18:06:20.251785
10305 18:06:20.254796 Choosing best match conf-1 for compat google,spherion-rev2.
10306 18:06:20.258273
10307 18:06:20.261802 Connected to device vid:did:rid of 1ae0:0028:00
10308 18:06:20.272170
10309 18:06:20.275641 tpm_get_response: command 0x17b, return code 0x0
10310 18:06:20.275725
10311 18:06:20.278666 ec_init: CrosEC protocol v3 supported (256, 248)
10312 18:06:20.283252
10313 18:06:20.287036 tpm_cleanup: add release locality here.
10314 18:06:20.287111
10315 18:06:20.287181 Shutting down all USB controllers.
10316 18:06:20.290068
10317 18:06:20.290141 Removing current net device
10318 18:06:20.290203
10319 18:06:20.296858 Exiting depthcharge with code 4 at timestamp: 51942996
10320 18:06:20.296934
10321 18:06:20.300277 LZMA decompressing kernel-1 to 0x821a6718
10322 18:06:20.300351
10323 18:06:20.303477 LZMA decompressing kernel-1 to 0x40000000
10324 18:06:21.921101
10325 18:06:21.921673 jumping to kernel
10326 18:06:21.923533 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10327 18:06:21.924211 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10328 18:06:21.924901 Setting prompt string to ['Linux version [0-9]']
10329 18:06:21.925548 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10330 18:06:21.925953 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10331 18:06:22.003235
10332 18:06:22.006334 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10333 18:06:22.010322 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10334 18:06:22.010891 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10335 18:06:22.011310 Setting prompt string to []
10336 18:06:22.011745 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10337 18:06:22.012148 Using line separator: #'\n'#
10338 18:06:22.012524 No login prompt set.
10339 18:06:22.012934 Parsing kernel messages
10340 18:06:22.013264 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10341 18:06:22.013857 [login-action] Waiting for messages, (timeout 00:04:03)
10342 18:06:22.014236 Waiting using forced prompt support (timeout 00:02:01)
10343 18:06:22.029473 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10344 18:06:22.032814 [ 0.000000] random: crng init done
10345 18:06:22.039622 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 18:06:22.042841 [ 0.000000] efi: UEFI not found.
10347 18:06:22.049481 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 18:06:22.056244 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 18:06:22.066144 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 18:06:22.076073 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 18:06:22.082805 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 18:06:22.086348 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 18:06:22.094957 [ 0.000000] NUMA: No NUMA configuration found
10354 18:06:22.101371 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 18:06:22.108280 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10356 18:06:22.108754 [ 0.000000] Zone ranges:
10357 18:06:22.115136 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 18:06:22.118306 [ 0.000000] DMA32 empty
10359 18:06:22.125022 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 18:06:22.128096 [ 0.000000] Movable zone start for each node
10361 18:06:22.131849 [ 0.000000] Early memory node ranges
10362 18:06:22.138307 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 18:06:22.145120 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 18:06:22.151629 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 18:06:22.158468 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 18:06:22.164958 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 18:06:22.171477 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 18:06:22.227712 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 18:06:22.234433 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 18:06:22.241251 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 18:06:22.244660 [ 0.000000] psci: probing for conduit method from DT.
10372 18:06:22.251250 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 18:06:22.254773 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 18:06:22.261459 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 18:06:22.264523 [ 0.000000] psci: SMC Calling Convention v1.2
10376 18:06:22.271623 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10377 18:06:22.274773 [ 0.000000] Detected VIPT I-cache on CPU0
10378 18:06:22.281707 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 18:06:22.288128 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 18:06:22.294937 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 18:06:22.301803 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 18:06:22.308674 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 18:06:22.314998 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 18:06:22.321852 [ 0.000000] alternatives: applying boot alternatives
10385 18:06:22.325030 [ 0.000000] Fallback order for Node 0: 0
10386 18:06:22.331659 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 18:06:22.334895 [ 0.000000] Policy zone: Normal
10388 18:06:22.358238 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10389 18:06:22.368080 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 18:06:22.379895 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 18:06:22.390121 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 18:06:22.396508 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10393 18:06:22.400133 <6>[ 0.000000] software IO TLB: area num 8.
10394 18:06:22.456114 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 18:06:22.605294 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10396 18:06:22.612169 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 18:06:22.618963 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 18:06:22.622055 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 18:06:22.628878 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 18:06:22.635655 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 18:06:22.638868 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 18:06:22.649461 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 18:06:22.655932 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 18:06:22.659201 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 18:06:22.666738 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 18:06:22.670334 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 18:06:22.676646 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 18:06:22.680482 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 18:06:22.683428 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 18:06:22.693258 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 18:06:22.703200 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 18:06:22.716603 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 18:06:22.723243 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 18:06:22.732297 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 18:06:22.745586 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 18:06:22.751853 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 18:06:22.758836 <6>[ 0.009236] Console: colour dummy device 80x25
10418 18:06:22.768993 <6>[ 0.013965] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 18:06:22.775807 <6>[ 0.024407] pid_max: default: 32768 minimum: 301
10420 18:06:22.778854 <6>[ 0.029308] LSM: Security Framework initializing
10421 18:06:22.785723 <6>[ 0.034277] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 18:06:22.795355 <6>[ 0.042089] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 18:06:22.801846 <6>[ 0.051558] cblist_init_generic: Setting adjustable number of callback queues.
10424 18:06:22.808731 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 18:06:22.818692 <6>[ 0.065340] cblist_init_generic: Setting adjustable number of callback queues.
10426 18:06:22.822128 <6>[ 0.072767] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 18:06:22.828975 <6>[ 0.079168] rcu: Hierarchical SRCU implementation.
10428 18:06:22.835640 <6>[ 0.084182] rcu: Max phase no-delay instances is 1000.
10429 18:06:22.841716 <6>[ 0.091220] EFI services will not be available.
10430 18:06:22.844970 <6>[ 0.096176] smp: Bringing up secondary CPUs ...
10431 18:06:22.853066 <6>[ 0.101255] Detected VIPT I-cache on CPU1
10432 18:06:22.859521 <6>[ 0.101326] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 18:06:22.866431 <6>[ 0.101358] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 18:06:22.869759 <6>[ 0.101695] Detected VIPT I-cache on CPU2
10435 18:06:22.876497 <6>[ 0.101747] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 18:06:22.882874 <6>[ 0.101766] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 18:06:22.889935 <6>[ 0.102026] Detected VIPT I-cache on CPU3
10438 18:06:22.896371 <6>[ 0.102074] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 18:06:22.902739 <6>[ 0.102088] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 18:06:22.906595 <6>[ 0.102393] CPU features: detected: Spectre-v4
10441 18:06:22.912989 <6>[ 0.102399] CPU features: detected: Spectre-BHB
10442 18:06:22.916381 <6>[ 0.102404] Detected PIPT I-cache on CPU4
10443 18:06:22.922787 <6>[ 0.102461] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 18:06:22.929704 <6>[ 0.102477] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 18:06:22.932850 <6>[ 0.102769] Detected PIPT I-cache on CPU5
10446 18:06:22.943180 <6>[ 0.102831] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 18:06:22.949981 <6>[ 0.102847] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 18:06:22.952657 <6>[ 0.103129] Detected PIPT I-cache on CPU6
10449 18:06:22.959651 <6>[ 0.103194] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 18:06:22.966403 <6>[ 0.103210] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 18:06:22.969578 <6>[ 0.103506] Detected PIPT I-cache on CPU7
10452 18:06:22.979712 <6>[ 0.103571] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 18:06:22.986076 <6>[ 0.103588] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 18:06:22.989573 <6>[ 0.103634] smp: Brought up 1 node, 8 CPUs
10455 18:06:22.992608 <6>[ 0.245063] SMP: Total of 8 processors activated.
10456 18:06:22.999374 <6>[ 0.249984] CPU features: detected: 32-bit EL0 Support
10457 18:06:23.009647 <6>[ 0.255381] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 18:06:23.016256 <6>[ 0.264181] CPU features: detected: Common not Private translations
10459 18:06:23.019784 <6>[ 0.270657] CPU features: detected: CRC32 instructions
10460 18:06:23.026266 <6>[ 0.276008] CPU features: detected: RCpc load-acquire (LDAPR)
10461 18:06:23.032748 <6>[ 0.281968] CPU features: detected: LSE atomic instructions
10462 18:06:23.039592 <6>[ 0.287750] CPU features: detected: Privileged Access Never
10463 18:06:23.042958 <6>[ 0.293529] CPU features: detected: RAS Extension Support
10464 18:06:23.049969 <6>[ 0.299138] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 18:06:23.056188 <6>[ 0.306360] CPU: All CPU(s) started at EL2
10466 18:06:23.059430 <6>[ 0.310703] alternatives: applying system-wide alternatives
10467 18:06:23.070835 <6>[ 0.321549] devtmpfs: initialized
10468 18:06:23.082901 <6>[ 0.330268] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 18:06:23.092772 <6>[ 0.340230] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 18:06:23.099416 <6>[ 0.348250] pinctrl core: initialized pinctrl subsystem
10471 18:06:23.102636 <6>[ 0.354945] DMI not present or invalid.
10472 18:06:23.109326 <6>[ 0.359361] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 18:06:23.119162 <6>[ 0.366217] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 18:06:23.126267 <6>[ 0.373807] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 18:06:23.136136 <6>[ 0.382026] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 18:06:23.139277 <6>[ 0.390268] audit: initializing netlink subsys (disabled)
10477 18:06:23.149737 <5>[ 0.395959] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10478 18:06:23.152816 <6>[ 0.396682] thermal_sys: Registered thermal governor 'step_wise'
10479 18:06:23.159846 <6>[ 0.403925] thermal_sys: Registered thermal governor 'power_allocator'
10480 18:06:23.166256 <6>[ 0.410177] cpuidle: using governor menu
10481 18:06:23.169514 <6>[ 0.421140] NET: Registered PF_QIPCRTR protocol family
10482 18:06:23.179530 <6>[ 0.426627] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 18:06:23.182486 <6>[ 0.433732] ASID allocator initialised with 32768 entries
10484 18:06:23.189438 <6>[ 0.440316] Serial: AMBA PL011 UART driver
10485 18:06:23.198376 <4>[ 0.449203] Trying to register duplicate clock ID: 134
10486 18:06:23.257080 <6>[ 0.510912] KASLR enabled
10487 18:06:23.271083 <6>[ 0.518628] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 18:06:23.278078 <6>[ 0.525639] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 18:06:23.284437 <6>[ 0.532129] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 18:06:23.291264 <6>[ 0.539136] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 18:06:23.297912 <6>[ 0.545625] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 18:06:23.304912 <6>[ 0.552631] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 18:06:23.311325 <6>[ 0.559120] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 18:06:23.317973 <6>[ 0.566126] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 18:06:23.320799 <6>[ 0.573650] ACPI: Interpreter disabled.
10496 18:06:23.329379 <6>[ 0.580098] iommu: Default domain type: Translated
10497 18:06:23.336247 <6>[ 0.585212] iommu: DMA domain TLB invalidation policy: strict mode
10498 18:06:23.339246 <5>[ 0.591875] SCSI subsystem initialized
10499 18:06:23.346132 <6>[ 0.596044] usbcore: registered new interface driver usbfs
10500 18:06:23.353186 <6>[ 0.601776] usbcore: registered new interface driver hub
10501 18:06:23.356386 <6>[ 0.607327] usbcore: registered new device driver usb
10502 18:06:23.362858 <6>[ 0.613429] pps_core: LinuxPPS API ver. 1 registered
10503 18:06:23.372657 <6>[ 0.618622] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 18:06:23.375856 <6>[ 0.627968] PTP clock support registered
10505 18:06:23.378918 <6>[ 0.632212] EDAC MC: Ver: 3.0.0
10506 18:06:23.386693 <6>[ 0.637366] FPGA manager framework
10507 18:06:23.393129 <6>[ 0.641053] Advanced Linux Sound Architecture Driver Initialized.
10508 18:06:23.396292 <6>[ 0.647826] vgaarb: loaded
10509 18:06:23.403413 <6>[ 0.650984] clocksource: Switched to clocksource arch_sys_counter
10510 18:06:23.406366 <5>[ 0.657427] VFS: Disk quotas dquot_6.6.0
10511 18:06:23.412711 <6>[ 0.661615] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 18:06:23.416027 <6>[ 0.668805] pnp: PnP ACPI: disabled
10513 18:06:23.425263 <6>[ 0.675529] NET: Registered PF_INET protocol family
10514 18:06:23.434872 <6>[ 0.681130] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 18:06:23.446415 <6>[ 0.693460] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 18:06:23.456031 <6>[ 0.702270] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 18:06:23.462440 <6>[ 0.710245] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 18:06:23.472385 <6>[ 0.718946] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 18:06:23.479390 <6>[ 0.728705] TCP: Hash tables configured (established 65536 bind 65536)
10520 18:06:23.485895 <6>[ 0.735571] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 18:06:23.495659 <6>[ 0.742770] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 18:06:23.502024 <6>[ 0.750476] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 18:06:23.508883 <6>[ 0.756631] RPC: Registered named UNIX socket transport module.
10524 18:06:23.511881 <6>[ 0.762783] RPC: Registered udp transport module.
10525 18:06:23.518696 <6>[ 0.767717] RPC: Registered tcp transport module.
10526 18:06:23.525130 <6>[ 0.772646] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 18:06:23.528745 <6>[ 0.779312] PCI: CLS 0 bytes, default 64
10528 18:06:23.531784 <6>[ 0.783648] Unpacking initramfs...
10529 18:06:23.555645 <6>[ 0.803074] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 18:06:23.565707 <6>[ 0.811728] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 18:06:23.568761 <6>[ 0.820572] kvm [1]: IPA Size Limit: 40 bits
10532 18:06:23.575510 <6>[ 0.825099] kvm [1]: GICv3: no GICV resource entry
10533 18:06:23.578682 <6>[ 0.830121] kvm [1]: disabling GICv2 emulation
10534 18:06:23.585675 <6>[ 0.834808] kvm [1]: GIC system register CPU interface enabled
10535 18:06:23.588993 <6>[ 0.840968] kvm [1]: vgic interrupt IRQ18
10536 18:06:23.595375 <6>[ 0.845316] kvm [1]: VHE mode initialized successfully
10537 18:06:23.601919 <5>[ 0.851716] Initialise system trusted keyrings
10538 18:06:23.608654 <6>[ 0.856519] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 18:06:23.615986 <6>[ 0.866478] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 18:06:23.622361 <5>[ 0.872942] NFS: Registering the id_resolver key type
10541 18:06:23.625589 <5>[ 0.878251] Key type id_resolver registered
10542 18:06:23.632199 <5>[ 0.882667] Key type id_legacy registered
10543 18:06:23.639396 <6>[ 0.886942] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 18:06:23.645798 <6>[ 0.893862] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 18:06:23.652047 <6>[ 0.901626] 9p: Installing v9fs 9p2000 file system support
10546 18:06:23.689251 <5>[ 0.939843] Key type asymmetric registered
10547 18:06:23.692347 <5>[ 0.944173] Asymmetric key parser 'x509' registered
10548 18:06:23.702829 <6>[ 0.949317] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 18:06:23.705783 <6>[ 0.956936] io scheduler mq-deadline registered
10550 18:06:23.708937 <6>[ 0.961726] io scheduler kyber registered
10551 18:06:23.728356 <6>[ 0.978786] EINJ: ACPI disabled.
10552 18:06:23.760804 <4>[ 1.005102] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 18:06:23.770646 <4>[ 1.015750] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 18:06:23.786171 <6>[ 1.037159] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 18:06:23.794463 <6>[ 1.045308] printk: console [ttyS0] disabled
10556 18:06:23.822222 <6>[ 1.069945] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 18:06:23.829195 <6>[ 1.079421] printk: console [ttyS0] enabled
10558 18:06:23.832345 <6>[ 1.079421] printk: console [ttyS0] enabled
10559 18:06:23.839120 <6>[ 1.088317] printk: bootconsole [mtk8250] disabled
10560 18:06:23.842230 <6>[ 1.088317] printk: bootconsole [mtk8250] disabled
10561 18:06:23.849031 <6>[ 1.099584] SuperH (H)SCI(F) driver initialized
10562 18:06:23.852453 <6>[ 1.104853] msm_serial: driver initialized
10563 18:06:23.866639 <6>[ 1.113796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 18:06:23.876035 <6>[ 1.122343] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 18:06:23.882942 <6>[ 1.130885] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 18:06:23.893248 <6>[ 1.139512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 18:06:23.899670 <6>[ 1.148220] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 18:06:23.909694 <6>[ 1.156934] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 18:06:23.919188 <6>[ 1.165484] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 18:06:23.925976 <6>[ 1.174292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 18:06:23.935851 <6>[ 1.182834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 18:06:23.944109 <6>[ 1.198348] loop: module loaded
10573 18:06:23.953449 <6>[ 1.204409] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 18:06:23.977306 <4>[ 1.228015] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 18:06:23.984387 <6>[ 1.234852] megasas: 07.719.03.00-rc1
10576 18:06:23.994115 <6>[ 1.244478] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 18:06:24.001013 <6>[ 1.246369] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 18:06:24.016083 <6>[ 1.266383] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 18:06:24.072204 <6>[ 1.316535] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10580 18:06:24.323302 <6>[ 1.574483] Freeing initrd memory: 18296K
10581 18:06:24.335549 <6>[ 1.586224] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 18:06:24.346177 <6>[ 1.597121] tun: Universal TUN/TAP device driver, 1.6
10583 18:06:24.349829 <6>[ 1.603190] thunder_xcv, ver 1.0
10584 18:06:24.353038 <6>[ 1.606685] thunder_bgx, ver 1.0
10585 18:06:24.356622 <6>[ 1.610185] nicpf, ver 1.0
10586 18:06:24.367072 <6>[ 1.614203] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 18:06:24.370216 <6>[ 1.621679] hns3: Copyright (c) 2017 Huawei Corporation.
10588 18:06:24.376631 <6>[ 1.627267] hclge is initializing
10589 18:06:24.380009 <6>[ 1.630845] e1000: Intel(R) PRO/1000 Network Driver
10590 18:06:24.386713 <6>[ 1.635976] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 18:06:24.390264 <6>[ 1.641988] e1000e: Intel(R) PRO/1000 Network Driver
10592 18:06:24.397010 <6>[ 1.647203] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 18:06:24.403182 <6>[ 1.653388] igb: Intel(R) Gigabit Ethernet Network Driver
10594 18:06:24.409845 <6>[ 1.659038] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 18:06:24.416507 <6>[ 1.664874] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 18:06:24.423343 <6>[ 1.671392] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 18:06:24.426631 <6>[ 1.677856] sky2: driver version 1.30
10598 18:06:24.432866 <6>[ 1.682777] usbcore: registered new device driver r8152-cfgselector
10599 18:06:24.439708 <6>[ 1.689314] usbcore: registered new interface driver r8152
10600 18:06:24.445934 <6>[ 1.695126] VFIO - User Level meta-driver version: 0.3
10601 18:06:24.452872 <6>[ 1.703368] usbcore: registered new interface driver usb-storage
10602 18:06:24.459229 <6>[ 1.709809] usbcore: registered new device driver onboard-usb-hub
10603 18:06:24.468455 <6>[ 1.718937] mt6397-rtc mt6359-rtc: registered as rtc0
10604 18:06:24.478072 <6>[ 1.724400] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:04:58 UTC (1718129098)
10605 18:06:24.481161 <6>[ 1.733959] i2c_dev: i2c /dev entries driver
10606 18:06:24.495313 <4>[ 1.745969] cpu cpu0: supply cpu not found, using dummy regulator
10607 18:06:24.501665 <4>[ 1.752410] cpu cpu1: supply cpu not found, using dummy regulator
10608 18:06:24.508574 <4>[ 1.758815] cpu cpu2: supply cpu not found, using dummy regulator
10609 18:06:24.515098 <4>[ 1.765219] cpu cpu3: supply cpu not found, using dummy regulator
10610 18:06:24.522062 <4>[ 1.771615] cpu cpu4: supply cpu not found, using dummy regulator
10611 18:06:24.528396 <4>[ 1.778022] cpu cpu5: supply cpu not found, using dummy regulator
10612 18:06:24.535123 <4>[ 1.784419] cpu cpu6: supply cpu not found, using dummy regulator
10613 18:06:24.541997 <4>[ 1.790835] cpu cpu7: supply cpu not found, using dummy regulator
10614 18:06:24.561881 <6>[ 1.812497] cpu cpu0: EM: created perf domain
10615 18:06:24.565012 <6>[ 1.817417] cpu cpu4: EM: created perf domain
10616 18:06:24.572205 <6>[ 1.823010] sdhci: Secure Digital Host Controller Interface driver
10617 18:06:24.578603 <6>[ 1.829439] sdhci: Copyright(c) Pierre Ossman
10618 18:06:24.585273 <6>[ 1.834391] Synopsys Designware Multimedia Card Interface Driver
10619 18:06:24.591736 <6>[ 1.841030] sdhci-pltfm: SDHCI platform and OF driver helper
10620 18:06:24.595442 <6>[ 1.841069] mmc0: CQHCI version 5.10
10621 18:06:24.601636 <6>[ 1.851282] ledtrig-cpu: registered to indicate activity on CPUs
10622 18:06:24.608449 <6>[ 1.858369] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 18:06:24.615144 <6>[ 1.865441] usbcore: registered new interface driver usbhid
10624 18:06:24.618513 <6>[ 1.871262] usbhid: USB HID core driver
10625 18:06:24.625345 <6>[ 1.875465] spi_master spi0: will run message pump with realtime priority
10626 18:06:24.670831 <6>[ 1.914818] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 18:06:24.688438 <6>[ 1.929728] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10628 18:06:24.692145 <3>[ 1.939244] mtk-msdc 11f60000.mmc: phase error: [map:0]
10629 18:06:24.698981 <3>[ 1.948663] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10630 18:06:24.705652 <3>[ 1.954613] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10631 18:06:24.709343 <3>[ 1.960984] mmc0: error -5 whilst initialising MMC card
10632 18:06:24.715306 <6>[ 1.966682] cros-ec-spi spi0.0: Chrome EC device registered
10633 18:06:24.738686 <6>[ 1.986137] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10634 18:06:24.746036 <6>[ 1.996933] NET: Registered PF_PACKET protocol family
10635 18:06:24.749159 <6>[ 2.002337] 9pnet: Installing 9P2000 support
10636 18:06:24.756049 <5>[ 2.006902] Key type dns_resolver registered
10637 18:06:24.759025 <6>[ 2.011938] registered taskstats version 1
10638 18:06:24.765902 <5>[ 2.016319] Loading compiled-in X.509 certificates
10639 18:06:24.797668 <4>[ 2.042312] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10640 18:06:24.807911 <4>[ 2.053170] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 18:06:24.824420 <6>[ 2.075556] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10642 18:06:24.831272 <6>[ 2.076019] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10643 18:06:24.837903 <6>[ 2.087958] mmc0: Command Queue Engine enabled
10644 18:06:24.841054 <6>[ 2.088586] xhci-mtk 11200000.usb: xHCI Host Controller
10645 18:06:24.847794 <6>[ 2.092675] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10646 18:06:24.857921 <6>[ 2.098159] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 18:06:24.861038 <6>[ 2.105391] mmcblk0: mmc0:0001 DA4128 116 GiB
10648 18:06:24.870975 <6>[ 2.112686] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 18:06:24.877799 <6>[ 2.123760] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10650 18:06:24.880882 <6>[ 2.126540] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10651 18:06:24.887755 <6>[ 2.133326] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10652 18:06:24.894149 <6>[ 2.138488] xhci-mtk 11200000.usb: xHCI Host Controller
10653 18:06:24.897674 <6>[ 2.144206] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10654 18:06:24.904504 <6>[ 2.149104] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10655 18:06:24.914520 <6>[ 2.149116] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10656 18:06:24.921358 <6>[ 2.154834] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10657 18:06:24.924176 <6>[ 2.162370] hub 1-0:1.0: USB hub found
10658 18:06:24.927801 <6>[ 2.179792] hub 1-0:1.0: 1 port detected
10659 18:06:24.937520 <6>[ 2.184068] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10660 18:06:24.941144 <6>[ 2.192750] hub 2-0:1.0: USB hub found
10661 18:06:24.944542 <6>[ 2.196769] hub 2-0:1.0: 1 port detected
10662 18:06:24.953411 <6>[ 2.204550] mtk-msdc 11f70000.mmc: Got CD GPIO
10663 18:06:24.966008 <6>[ 2.213677] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 18:06:24.972913 <6>[ 2.222057] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 18:06:24.983005 <6>[ 2.230397] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 18:06:24.989198 <6>[ 2.238743] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 18:06:24.999037 <6>[ 2.247080] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 18:06:25.009173 <6>[ 2.255419] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 18:06:25.016012 <6>[ 2.263757] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 18:06:25.026063 <6>[ 2.272095] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 18:06:25.032612 <6>[ 2.280434] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 18:06:25.042470 <6>[ 2.288771] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 18:06:25.049181 <6>[ 2.297108] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 18:06:25.059076 <6>[ 2.305455] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 18:06:25.065758 <6>[ 2.313794] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 18:06:25.075436 <6>[ 2.322132] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 18:06:25.082266 <6>[ 2.330470] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 18:06:25.088664 <6>[ 2.339287] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 18:06:25.095316 <6>[ 2.346492] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 18:06:25.102155 <6>[ 2.353261] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 18:06:25.112223 <6>[ 2.360076] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 18:06:25.119028 <6>[ 2.367013] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 18:06:25.125691 <6>[ 2.373882] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 18:06:25.135384 <6>[ 2.383020] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 18:06:25.145077 <6>[ 2.392139] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 18:06:25.155191 <6>[ 2.401433] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 18:06:25.165313 <6>[ 2.410899] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 18:06:25.175277 <6>[ 2.420367] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 18:06:25.181581 <6>[ 2.429486] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 18:06:25.191258 <6>[ 2.438952] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 18:06:25.201202 <6>[ 2.448073] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 18:06:25.211079 <6>[ 2.457367] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 18:06:25.221347 <6>[ 2.467527] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 18:06:25.231759 <6>[ 2.479628] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 18:06:25.239686 <6>[ 2.490693] Trying to probe devices needed for running init ...
10696 18:06:25.250204 <3>[ 2.497955] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10697 18:06:25.359518 <6>[ 2.607273] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 18:06:25.514118 <6>[ 2.765068] hub 1-1:1.0: USB hub found
10699 18:06:25.517133 <6>[ 2.769591] hub 1-1:1.0: 4 ports detected
10700 18:06:25.529802 <6>[ 2.780981] hub 1-1:1.0: USB hub found
10701 18:06:25.533016 <6>[ 2.785419] hub 1-1:1.0: 4 ports detected
10702 18:06:25.639532 <6>[ 2.887457] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10703 18:06:25.665963 <6>[ 2.917074] hub 2-1:1.0: USB hub found
10704 18:06:25.669029 <6>[ 2.921603] hub 2-1:1.0: 3 ports detected
10705 18:06:25.679657 <6>[ 2.930811] hub 2-1:1.0: USB hub found
10706 18:06:25.682843 <6>[ 2.935237] hub 2-1:1.0: 3 ports detected
10707 18:06:25.855871 <6>[ 3.103304] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10708 18:06:25.988389 <6>[ 3.239192] hub 1-1.4:1.0: USB hub found
10709 18:06:25.991533 <6>[ 3.243868] hub 1-1.4:1.0: 2 ports detected
10710 18:06:26.003280 <6>[ 3.254649] hub 1-1.4:1.0: USB hub found
10711 18:06:26.006898 <6>[ 3.259227] hub 1-1.4:1.0: 2 ports detected
10712 18:06:26.075449 <6>[ 3.323513] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10713 18:06:26.184257 <6>[ 3.431945] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10714 18:06:26.219784 <4>[ 3.467272] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10715 18:06:26.229857 <4>[ 3.476399] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10716 18:06:26.269640 <6>[ 3.520607] r8152 2-1.3:1.0 eth0: v1.12.13
10717 18:06:26.311592 <6>[ 3.559059] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10718 18:06:26.503784 <6>[ 3.751303] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10719 18:06:27.891364 <6>[ 5.142775] r8152 2-1.3:1.0 eth0: carrier on
10720 18:06:30.155636 <5>[ 5.167053] Sending DHCP requests .., OK
10721 18:06:30.162059 <6>[ 7.411533] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10722 18:06:30.165782 <6>[ 7.419880] IP-Config: Complete:
10723 18:06:30.178880 <6>[ 7.423373] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10724 18:06:30.185457 <6>[ 7.434085] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10725 18:06:30.195312 <6>[ 7.442703] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10726 18:06:30.198447 <6>[ 7.442713] nameserver0=192.168.201.1
10727 18:06:30.201855 <6>[ 7.454879] clk: Disabling unused clocks
10728 18:06:30.205949 <6>[ 7.460403] ALSA device list:
10729 18:06:30.212189 <6>[ 7.463667] No soundcards found.
10730 18:06:30.219766 <6>[ 7.471213] Freeing unused kernel memory: 8512K
10731 18:06:30.222862 <6>[ 7.476116] Run /init as init process
10732 18:06:30.232188 Loading, please wait...
10733 18:06:30.261295 Starting systemd-udevd version 252.22-1~deb12u1
10734 18:06:30.530727 <6>[ 7.779163] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10735 18:06:30.537333 <6>[ 7.779730] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10736 18:06:30.547330 <6>[ 7.786777] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10737 18:06:30.553663 <6>[ 7.787541] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10738 18:06:30.560813 <6>[ 7.790261] remoteproc remoteproc0: scp is available
10739 18:06:30.563980 <6>[ 7.790337] remoteproc remoteproc0: powering up scp
10740 18:06:30.573726 <6>[ 7.790343] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10741 18:06:30.577394 <6>[ 7.790358] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10742 18:06:30.587059 <6>[ 7.807055] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10743 18:06:30.593495 <6>[ 7.810899] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10744 18:06:30.603760 <6>[ 7.816131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10745 18:06:30.606866 <6>[ 7.852773] mc: Linux media interface: v0.10
10746 18:06:30.613363 <4>[ 7.858407] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10747 18:06:30.623839 <4>[ 7.859933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10748 18:06:30.633663 <3>[ 7.864743] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 18:06:30.639950 <4>[ 7.871712] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10750 18:06:30.646683 <6>[ 7.872151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10751 18:06:30.656812 <6>[ 7.872154] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10752 18:06:30.663308 <6>[ 7.872741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10753 18:06:30.672998 <6>[ 7.872753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10754 18:06:30.680147 <6>[ 7.872757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10755 18:06:30.689818 <6>[ 7.872763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10756 18:06:30.696178 <6>[ 7.878787] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 18:06:30.702917 <3>[ 7.880667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 18:06:30.713232 <3>[ 7.880672] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 18:06:30.719783 <3>[ 7.880756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 18:06:30.729761 <3>[ 7.880761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 18:06:30.736633 <3>[ 7.880765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 18:06:30.746167 <3>[ 7.880771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 18:06:30.752856 <3>[ 7.880775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 18:06:30.763187 <3>[ 7.880812] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 18:06:30.769739 <3>[ 7.880857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 18:06:30.776250 <3>[ 7.880863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 18:06:30.786470 <3>[ 7.880867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 18:06:30.792893 <3>[ 7.880908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 18:06:30.802578 <3>[ 7.880914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 18:06:30.809235 <3>[ 7.880917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 18:06:30.819290 <3>[ 7.880925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 18:06:30.826137 <3>[ 7.880931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 18:06:30.835827 <3>[ 7.880950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 18:06:30.842487 <6>[ 7.944292] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10775 18:06:30.849144 <6>[ 7.945762] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10776 18:06:30.855729 <6>[ 7.945789] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10777 18:06:30.862331 <6>[ 7.945797] remoteproc remoteproc0: remote processor scp is now up
10778 18:06:30.868731 <6>[ 7.953328] pci_bus 0000:00: root bus resource [bus 00-ff]
10779 18:06:30.875619 <6>[ 7.953334] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10780 18:06:30.885493 <6>[ 7.953336] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10781 18:06:30.891728 <6>[ 7.953366] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10782 18:06:30.901840 <6>[ 7.964978] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10783 18:06:30.908512 <6>[ 7.969982] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10784 18:06:30.918098 <6>[ 7.978307] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10785 18:06:30.924954 <6>[ 7.986230] pci 0000:00:00.0: supports D1 D2
10786 18:06:30.931173 <6>[ 7.994991] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10787 18:06:30.937896 <6>[ 8.002059] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 18:06:30.947907 <6>[ 8.012948] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10789 18:06:30.954488 <6>[ 8.019195] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10790 18:06:30.964487 <6>[ 8.081869] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10791 18:06:30.970891 <6>[ 8.083124] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10792 18:06:30.977926 <4>[ 8.092338] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10793 18:06:30.984316 <4>[ 8.092338] Fallback method does not support PEC.
10794 18:06:30.990512 <6>[ 8.097819] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10795 18:06:31.000309 <6>[ 8.097842] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10796 18:06:31.004354 <6>[ 8.098948] videodev: Linux video capture interface: v2.00
10797 18:06:31.007588 <6>[ 8.120307] Bluetooth: Core ver 2.22
10798 18:06:31.017401 <6>[ 8.125572] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10799 18:06:31.020517 <6>[ 8.132755] NET: Registered PF_BLUETOOTH protocol family
10800 18:06:31.027263 <6>[ 8.142697] pci 0000:01:00.0: supports D1 D2
10801 18:06:31.033799 <6>[ 8.148840] Bluetooth: HCI device and connection manager initialized
10802 18:06:31.040787 <6>[ 8.158913] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 18:06:31.043968 <6>[ 8.166398] Bluetooth: HCI socket layer initialized
10804 18:06:31.050700 <6>[ 8.168099] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10805 18:06:31.063683 <6>[ 8.169501] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10806 18:06:31.069994 <6>[ 8.169597] usbcore: registered new interface driver uvcvideo
10807 18:06:31.076484 <6>[ 8.187157] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10808 18:06:31.083573 <6>[ 8.188188] Bluetooth: L2CAP socket layer initialized
10809 18:06:31.089851 <6>[ 8.195079] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10810 18:06:31.096446 <6>[ 8.203314] Bluetooth: SCO socket layer initialized
10811 18:06:31.103559 <6>[ 8.211557] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10812 18:06:31.109992 <6>[ 8.212069] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10813 18:06:31.116515 <6>[ 8.273190] usbcore: registered new interface driver btusb
10814 18:06:31.126795 <4>[ 8.274139] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10815 18:06:31.133088 <3>[ 8.274156] Bluetooth: hci0: Failed to load firmware file (-2)
10816 18:06:31.136225 <3>[ 8.274163] Bluetooth: hci0: Failed to set up firmware (-2)
10817 18:06:31.149588 <4>[ 8.274170] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10818 18:06:31.156413 <6>[ 8.278267] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10819 18:06:31.162749 <6>[ 8.413215] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10820 18:06:31.172661 <6>[ 8.421219] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10821 18:06:31.175942 <6>[ 8.429219] pci 0000:00:00.0: PCI bridge to [bus 01]
10822 18:06:31.185936 <6>[ 8.434435] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10823 18:06:31.192573 <6>[ 8.442571] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10824 18:06:31.199652 <6>[ 8.449390] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10825 18:06:31.206127 <6>[ 8.456189] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10826 18:06:31.221662 <5>[ 8.470002] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10827 18:06:31.242974 <5>[ 8.491222] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10828 18:06:31.249334 <5>[ 8.498617] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10829 18:06:31.259403 <4>[ 8.507106] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10830 18:06:31.262411 <6>[ 8.515995] cfg80211: failed to load regulatory.db
10831 18:06:31.311846 <6>[ 8.560603] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10832 18:06:31.318771 <6>[ 8.568104] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10833 18:06:31.343514 <6>[ 8.594746] mt7921e 0000:01:00.0: ASIC revision: 79610010
10834 18:06:31.447158 <6>[ 8.695068] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10835 18:06:31.450328 <6>[ 8.695068]
10836 18:06:31.464637 Begin: Loading essential drivers ... done.
10837 18:06:31.467673 Begin: Running /scripts/init-premount ... done.
10838 18:06:31.474185 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10839 18:06:31.484324 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10840 18:06:31.487633 Device /sys/class/net/eth0 found
10841 18:06:31.488074 done.
10842 18:06:31.494257 Begin: Waiting up to 180 secs for any network device to become available ... done.
10843 18:06:31.559657 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10844 18:06:31.566430 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10845 18:06:31.572711 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10846 18:06:31.579688 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10847 18:06:31.585918 host : mt8192-asurada-spherion-r0-cbg-1
10848 18:06:31.592412 domain : lava-rack
10849 18:06:31.596030 rootserver: 192.168.201.1 rootpath:
10850 18:06:31.596265 filename :
10851 18:06:31.714505 <6>[ 8.962926] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10852 18:06:31.728309 done.
10853 18:06:31.736056 Begin: Running /scripts/nfs-bottom ... done.
10854 18:06:31.748086 Begin: Running /scripts/init-bottom ... done.
10855 18:06:33.066579 <6>[ 10.318433] NET: Registered PF_INET6 protocol family
10856 18:06:33.073947 <6>[ 10.325503] Segment Routing with IPv6
10857 18:06:33.076967 <6>[ 10.329503] In-situ OAM (IOAM) with IPv6
10858 18:06:33.244247 <30>[ 10.469476] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10859 18:06:33.251045 <30>[ 10.503170] systemd[1]: Detected architecture arm64.
10860 18:06:33.258487
10861 18:06:33.262014 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10862 18:06:33.262322
10863 18:06:33.288461 <30>[ 10.540228] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10864 18:06:34.319654 <30>[ 11.568523] systemd[1]: Queued start job for default target graphical.target.
10865 18:06:34.371872 <30>[ 11.620630] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10866 18:06:34.378178 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10867 18:06:34.399873 <30>[ 11.649073] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10868 18:06:34.409938 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10869 18:06:34.428227 <30>[ 11.676980] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10870 18:06:34.438362 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10871 18:06:34.456597 <30>[ 11.705358] systemd[1]: Created slice user.slice - User and Session Slice.
10872 18:06:34.463301 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10873 18:06:34.486501 <30>[ 11.732163] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10874 18:06:34.496431 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10875 18:06:34.514223 <30>[ 11.759524] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10876 18:06:34.520993 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10877 18:06:34.549575 <30>[ 11.787936] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10878 18:06:34.559500 <30>[ 11.807895] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10879 18:06:34.568416 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10880 18:06:34.582617 <30>[ 11.831313] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10881 18:06:34.589147 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10882 18:06:34.606250 <30>[ 11.855352] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10883 18:06:34.616413 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10884 18:06:34.631016 <30>[ 11.883388] systemd[1]: Reached target paths.target - Path Units.
10885 18:06:34.641137 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10886 18:06:34.659035 <30>[ 11.907719] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10887 18:06:34.665566 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10888 18:06:34.678985 <30>[ 11.931269] systemd[1]: Reached target slices.target - Slice Units.
10889 18:06:34.689638 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10890 18:06:34.703702 <30>[ 11.955339] systemd[1]: Reached target swap.target - Swaps.
10891 18:06:34.710431 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10892 18:06:34.735024 <30>[ 11.983361] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10893 18:06:34.744810 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10894 18:06:34.764117 <30>[ 12.012238] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10895 18:06:34.773714 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10896 18:06:34.794096 <30>[ 12.042745] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10897 18:06:34.804678 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10898 18:06:34.820573 <30>[ 12.068918] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10899 18:06:34.830331 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10900 18:06:34.848214 <30>[ 12.096642] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10901 18:06:34.855134 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10902 18:06:34.876759 <30>[ 12.125009] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10903 18:06:34.886378 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10904 18:06:34.906453 <30>[ 12.154549] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10905 18:06:34.915531 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10906 18:06:34.931212 <30>[ 12.179765] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10907 18:06:34.940849 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10908 18:06:34.995106 <30>[ 12.243489] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10909 18:06:35.001374 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10910 18:06:35.023301 <30>[ 12.272055] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10911 18:06:35.029927 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10912 18:06:35.087137 <30>[ 12.335761] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10913 18:06:35.093745 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10914 18:06:35.121920 <30>[ 12.363498] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10915 18:06:35.136825 <30>[ 12.385625] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10916 18:06:35.146670 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10917 18:06:35.172648 <30>[ 12.421277] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10918 18:06:35.179229 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10919 18:06:35.207985 <30>[ 12.456748] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10920 18:06:35.214585 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10921 18:06:35.244352 <30>[ 12.493183] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10922 18:06:35.251057 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10923 18:06:35.260603 <6>[ 12.508647] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10924 18:06:35.260837
10925 18:06:35.301075 <30>[ 12.536873] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10926 18:06:35.301360 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10927 18:06:35.322692 <30>[ 12.571711] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10928 18:06:35.329620 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10929 18:06:35.357264 <30>[ 12.605774] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10930 18:06:35.367289 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.617501] fuse: init (API version 7.37)
10931 18:06:35.370277 [0m - Load Kernel Module loop...
10932 18:06:35.394724 <30>[ 12.643298] systemd[1]: Starting systemd-journald.service - Journal Service...
10933 18:06:35.400910 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10934 18:06:35.436042 <30>[ 12.684766] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10935 18:06:35.442527 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10936 18:06:35.471273 <30>[ 12.716314] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10937 18:06:35.477983 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10938 18:06:35.505938 <30>[ 12.754553] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10939 18:06:35.515610 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10940 18:06:35.540967 <30>[ 12.790035] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10941 18:06:35.547718 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10942 18:06:35.574747 <30>[ 12.823714] systemd[1]: Started systemd-journald.service - Journal Service.
10943 18:06:35.581399 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10944 18:06:35.603058 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10945 18:06:35.619015 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10946 18:06:35.639392 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10947 18:06:35.660106 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10948 18:06:35.681023 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10949 18:06:35.700843 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10950 18:06:35.723609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10951 18:06:35.743498 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10952 18:06:35.768913 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10953 18:06:35.789063 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10954 18:06:35.808109 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10955 18:06:35.828436 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10956 18:06:35.848591 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10957 18:06:35.869146 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10958 18:06:35.924380 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10959 18:06:35.950061 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10960 18:06:35.975477 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10961 18:06:35.997981 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10962 18:06:36.026510 Starting [0;1;39msyste<46>[ 13.274910] systemd-journald[307]: Received client request to flush runtime journal.
10963 18:06:36.030184 md-sysctl.se…ce[0m - Apply Kernel Variables...
10964 18:06:36.091531 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10965 18:06:36.348898 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10966 18:06:36.367291 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10967 18:06:36.387185 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10968 18:06:36.407382 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10969 18:06:36.809714 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10970 18:06:37.430331 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10971 18:06:37.447492 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10972 18:06:37.488479 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10973 18:06:37.577400 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10974 18:06:37.595869 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10975 18:06:37.615408 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10976 18:06:37.672144 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10977 18:06:37.698430 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10978 18:06:37.938972 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10979 18:06:37.980411 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10980 18:06:38.070850 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10981 18:06:38.327464 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10982 18:06:38.400116 Startin<6>[ 15.650136] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10983 18:06:38.406266 g [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10984 18:06:38.430839 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10985 18:06:38.527884 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10986 18:06:38.547149 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10987 18:06:38.593164 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10988 18:06:38.610675 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10989 18:06:38.643432 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10990 18:06:38.666632 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10991 18:06:38.719328 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10992 18:06:38.739269 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10993 18:06:38.763696 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10994 18:06:38.784116 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10995 18:06:38.803875 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10996 18:06:38.827685 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10997 18:06:38.846701 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10998 18:06:38.862081 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10999 18:06:38.885038 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11000 18:06:38.935173 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11001 18:06:38.954726 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11002 18:06:38.973511 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11003 18:06:38.993544 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11004 18:06:39.008866 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11005 18:06:39.026546 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11006 18:06:39.044116 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11007 18:06:39.060016 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11008 18:06:39.118092 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11009 18:06:39.153228 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11010 18:06:39.233085 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11011 18:06:39.258380 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11012 18:06:39.310456 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11013 18:06:39.348043 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11014 18:06:39.394175 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11015 18:06:39.412580 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11016 18:06:39.428383 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11017 18:06:39.459011 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11018 18:06:39.571012 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11019 18:06:39.591259 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11020 18:06:39.612408 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11021 18:06:39.656770 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11022 18:06:39.707465 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11023 18:06:39.780416
11024 18:06:39.783467 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11025 18:06:39.783901
11026 18:06:39.786850 debian-bookworm-arm64 login: root (automatic login)
11027 18:06:39.787280
11028 18:06:40.068086 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11029 18:06:40.068241
11030 18:06:40.074451 The programs included with the Debian GNU/Linux system are free software;
11031 18:06:40.081191 the exact distribution terms for each program are described in the
11032 18:06:40.084361 individual files in /usr/share/doc/*/copyright.
11033 18:06:40.084447
11034 18:06:40.090950 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11035 18:06:40.094629 permitted by applicable law.
11036 18:06:41.071638 Matched prompt #10: / #
11038 18:06:41.072870 Setting prompt string to ['/ #']
11039 18:06:41.073320 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11041 18:06:41.074332 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11042 18:06:41.074788 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
11043 18:06:41.075162 Setting prompt string to ['/ #']
11044 18:06:41.075487 Forcing a shell prompt, looking for ['/ #']
11046 18:06:41.126307 / #
11047 18:06:41.126921 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11048 18:06:41.127308 Waiting using forced prompt support (timeout 00:02:30)
11049 18:06:41.132131
11050 18:06:41.133092 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11051 18:06:41.133674 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
11053 18:06:41.234953 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1'
11054 18:06:41.240972 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291400/extract-nfsrootfs-tnl6nif1'
11056 18:06:41.342352 / # export NFS_SERVER_IP='192.168.201.1'
11057 18:06:41.348770 export NFS_SERVER_IP='192.168.201.1'
11058 18:06:41.349699 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 18:06:41.350239 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
11060 18:06:41.350739 end: 2 depthcharge-action (duration 00:01:17) [common]
11061 18:06:41.351252 start: 3 lava-test-retry (timeout 00:08:03) [common]
11062 18:06:41.351741 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11063 18:06:41.352161 Using namespace: common
11065 18:06:41.453531 / # #
11066 18:06:41.454210 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11067 18:06:41.460431 #
11068 18:06:41.461311 Using /lava-14291400
11070 18:06:41.562461 / # export SHELL=/bin/bash
11071 18:06:41.568710 export SHELL=/bin/bash
11073 18:06:41.670397 / # . /lava-14291400/environment
11074 18:06:41.676729 . /lava-14291400/environment
11076 18:06:41.783624 / # /lava-14291400/bin/lava-test-runner /lava-14291400/0
11077 18:06:41.784657 Test shell timeout: 10s (minimum of the action and connection timeout)
11078 18:06:41.790164 /lava-14291400/bin/lava-test-runner /lava-14291400/0
11079 18:06:42.023884 + export TESTRUN_ID=0_timesync-off
11080 18:06:42.027044 + TESTRUN_ID=0_timesync-off
11081 18:06:42.030027 + cd /lava-14291400/0/tests/0_timesync-off
11082 18:06:42.033702 ++ cat uuid
11083 18:06:42.037284 + UUID=14291400_1.6.2.3.1
11084 18:06:42.037871 + set +x
11085 18:06:42.044019 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291400_1.6.2.3.1>
11086 18:06:42.044788 Received signal: <STARTRUN> 0_timesync-off 14291400_1.6.2.3.1
11087 18:06:42.045207 Starting test lava.0_timesync-off (14291400_1.6.2.3.1)
11088 18:06:42.045736 Skipping test definition patterns.
11089 18:06:42.047284 + systemctl stop systemd-timesyncd
11090 18:06:42.099557 + set +x
11091 18:06:42.103091 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291400_1.6.2.3.1>
11092 18:06:42.103412 Received signal: <ENDRUN> 0_timesync-off 14291400_1.6.2.3.1
11093 18:06:42.103552 Ending use of test pattern.
11094 18:06:42.103653 Ending test lava.0_timesync-off (14291400_1.6.2.3.1), duration 0.06
11096 18:06:42.175528 + export TESTRUN_ID=1_kselftest-arm64
11097 18:06:42.176150 + TESTRUN_ID=1_kselftest-arm64
11098 18:06:42.182237 + cd /lava-14291400/0/tests/1_kselftest-arm64
11099 18:06:42.182680 ++ cat uuid
11100 18:06:42.185452 + UUID=14291400_1.6.2.3.5
11101 18:06:42.185890 + set +x
11102 18:06:42.192141 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14291400_1.6.2.3.5>
11103 18:06:42.192859 Received signal: <STARTRUN> 1_kselftest-arm64 14291400_1.6.2.3.5
11104 18:06:42.193225 Starting test lava.1_kselftest-arm64 (14291400_1.6.2.3.5)
11105 18:06:42.193529 Skipping test definition patterns.
11106 18:06:42.194970 + cd ./automated/linux/kselftest/
11107 18:06:42.221374 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11108 18:06:42.261080 INFO: install_deps skipped
11109 18:06:42.756081 --2024-06-11 18:05:16-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11110 18:06:42.763197 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11111 18:06:42.896020 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11112 18:06:43.029614 HTTP request sent, awaiting response... 200 OK
11113 18:06:43.032947 Length: 1647744 (1.6M) [application/octet-stream]
11114 18:06:43.035640 Saving to: 'kselftest_armhf.tar.gz'
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11122 18:06:44.101987
11123 18:06:44.248862 2024-06-11 18:05:18 (1.44 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
11124 18:06:44.249013
11125 18:06:48.289390 skiplist:
11126 18:06:48.292764 ========================================
11127 18:06:48.295809 ========================================
11128 18:06:48.337249 arm64:tags_test
11129 18:06:48.340186 arm64:run_tags_test.sh
11130 18:06:48.340270 arm64:fake_sigreturn_bad_magic
11131 18:06:48.343653 arm64:fake_sigreturn_bad_size
11132 18:06:48.347024 arm64:fake_sigreturn_bad_size_for_magic0
11133 18:06:48.350518 arm64:fake_sigreturn_duplicated_fpsimd
11134 18:06:48.353542 arm64:fake_sigreturn_misaligned_sp
11135 18:06:48.357032 arm64:fake_sigreturn_missing_fpsimd
11136 18:06:48.360194 arm64:fake_sigreturn_sme_change_vl
11137 18:06:48.363799 arm64:fake_sigreturn_sve_change_vl
11138 18:06:48.366882 arm64:mangle_pstate_invalid_compat_toggle
11139 18:06:48.370370 arm64:mangle_pstate_invalid_daif_bits
11140 18:06:48.373403 arm64:mangle_pstate_invalid_mode_el1h
11141 18:06:48.376990 arm64:mangle_pstate_invalid_mode_el1t
11142 18:06:48.380520 arm64:mangle_pstate_invalid_mode_el2h
11143 18:06:48.383471 arm64:mangle_pstate_invalid_mode_el2t
11144 18:06:48.386935 arm64:mangle_pstate_invalid_mode_el3h
11145 18:06:48.389951 arm64:mangle_pstate_invalid_mode_el3t
11146 18:06:48.393526 arm64:sme_trap_no_sm
11147 18:06:48.396514 arm64:sme_trap_non_streaming
11148 18:06:48.396646 arm64:sme_trap_za
11149 18:06:48.400069 arm64:sme_vl
11150 18:06:48.400153 arm64:ssve_regs
11151 18:06:48.403120 arm64:sve_regs
11152 18:06:48.403204 arm64:sve_vl
11153 18:06:48.403270 arm64:za_no_regs
11154 18:06:48.406495 arm64:za_regs
11155 18:06:48.406606 arm64:pac
11156 18:06:48.409993 arm64:fp-stress
11157 18:06:48.410096 arm64:sve-ptrace
11158 18:06:48.413235 arm64:sve-probe-vls
11159 18:06:48.413338 arm64:vec-syscfg
11160 18:06:48.413420 arm64:za-fork
11161 18:06:48.416204 arm64:za-ptrace
11162 18:06:48.419758 arm64:check_buffer_fill
11163 18:06:48.419849 arm64:check_child_memory
11164 18:06:48.422848 arm64:check_gcr_el1_cswitch
11165 18:06:48.426223 arm64:check_ksm_options
11166 18:06:48.426301 arm64:check_mmap_options
11167 18:06:48.429599 arm64:check_prctl
11168 18:06:48.433010 arm64:check_tags_inclusion
11169 18:06:48.433115 arm64:check_user_mem
11170 18:06:48.436369 arm64:btitest
11171 18:06:48.436471 arm64:nobtitest
11172 18:06:48.436569 arm64:hwcap
11173 18:06:48.439826 arm64:ptrace
11174 18:06:48.439901 arm64:syscall-abi
11175 18:06:48.442903 arm64:tpidr2
11176 18:06:48.446444 ============== Tests to run ===============
11177 18:06:48.446530 arm64:tags_test
11178 18:06:48.449850 arm64:run_tags_test.sh
11179 18:06:48.452728 arm64:fake_sigreturn_bad_magic
11180 18:06:48.452815 arm64:fake_sigreturn_bad_size
11181 18:06:48.459389 arm64:fake_sigreturn_bad_size_for_magic0
11182 18:06:48.462875 arm64:fake_sigreturn_duplicated_fpsimd
11183 18:06:48.465993 arm64:fake_sigreturn_misaligned_sp
11184 18:06:48.466078 arm64:fake_sigreturn_missing_fpsimd
11185 18:06:48.469555 arm64:fake_sigreturn_sme_change_vl
11186 18:06:48.472520 arm64:fake_sigreturn_sve_change_vl
11187 18:06:48.476055 arm64:mangle_pstate_invalid_compat_toggle
11188 18:06:48.482619 arm64:mangle_pstate_invalid_daif_bits
11189 18:06:48.485887 arm64:mangle_pstate_invalid_mode_el1h
11190 18:06:48.489227 arm64:mangle_pstate_invalid_mode_el1t
11191 18:06:48.492793 arm64:mangle_pstate_invalid_mode_el2h
11192 18:06:48.495650 arm64:mangle_pstate_invalid_mode_el2t
11193 18:06:48.499323 arm64:mangle_pstate_invalid_mode_el3h
11194 18:06:48.502700 arm64:mangle_pstate_invalid_mode_el3t
11195 18:06:48.502785 arm64:sme_trap_no_sm
11196 18:06:48.505882 arm64:sme_trap_non_streaming
11197 18:06:48.509274 arm64:sme_trap_za
11198 18:06:48.509359 arm64:sme_vl
11199 18:06:48.509426 arm64:ssve_regs
11200 18:06:48.512627 arm64:sve_regs
11201 18:06:48.512711 arm64:sve_vl
11202 18:06:48.515592 arm64:za_no_regs
11203 18:06:48.515676 arm64:za_regs
11204 18:06:48.515743 arm64:pac
11205 18:06:48.518912 arm64:fp-stress
11206 18:06:48.518996 arm64:sve-ptrace
11207 18:06:48.522392 arm64:sve-probe-vls
11208 18:06:48.522476 arm64:vec-syscfg
11209 18:06:48.525884 arm64:za-fork
11210 18:06:48.525968 arm64:za-ptrace
11211 18:06:48.528921 arm64:check_buffer_fill
11212 18:06:48.529005 arm64:check_child_memory
11213 18:06:48.532402 arm64:check_gcr_el1_cswitch
11214 18:06:48.535713 arm64:check_ksm_options
11215 18:06:48.538708 arm64:check_mmap_options
11216 18:06:48.538865 arm64:check_prctl
11217 18:06:48.542073 arm64:check_tags_inclusion
11218 18:06:48.542214 arm64:check_user_mem
11219 18:06:48.545581 arm64:btitest
11220 18:06:48.545710 arm64:nobtitest
11221 18:06:48.545812 arm64:hwcap
11222 18:06:48.548847 arm64:ptrace
11223 18:06:48.548967 arm64:syscall-abi
11224 18:06:48.552204 arm64:tpidr2
11225 18:06:48.555472 ===========End Tests to run ===============
11226 18:06:48.555592 shardfile-arm64 pass
11227 18:06:48.715854 <12>[ 25.969789] kselftest: Running tests in arm64
11228 18:06:48.724663 TAP version 13
11229 18:06:48.737314 1..48
11230 18:06:48.751597 # selftests: arm64: tags_test
11231 18:06:49.186639 ok 1 selftests: arm64: tags_test
11232 18:06:49.200824 # selftests: arm64: run_tags_test.sh
11233 18:06:49.254829 # --------------------
11234 18:06:49.257936 # running tags test
11235 18:06:49.258022 # --------------------
11236 18:06:49.261402 # [PASS]
11237 18:06:49.264205 ok 2 selftests: arm64: run_tags_test.sh
11238 18:06:49.275632 # selftests: arm64: fake_sigreturn_bad_magic
11239 18:06:49.335838 # Registered handlers for all signals.
11240 18:06:49.335978 # Detected MINSTKSIGSZ:4720
11241 18:06:49.339324 # Testcase initialized.
11242 18:06:49.342402 # uc context validated.
11243 18:06:49.345846 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11244 18:06:49.349310 # Handled SIG_COPYCTX
11245 18:06:49.349394 # Available space:3568
11246 18:06:49.355769 # Using badly built context - ERR: BAD MAGIC !
11247 18:06:49.362222 # SIG_OK -- SP:0xFFFFE5B5AF10 si_addr@:0xffffe5b5af10 si_code:2 token@:0xffffe5b59cb0 offset:-4704
11248 18:06:49.365718 # ==>> completed. PASS(1)
11249 18:06:49.372195 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11250 18:06:49.378971 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE5B59CB0
11251 18:06:49.385152 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11252 18:06:49.388652 # selftests: arm64: fake_sigreturn_bad_size
11253 18:06:49.409438 # Registered handlers for all signals.
11254 18:06:49.409536 # Detected MINSTKSIGSZ:4720
11255 18:06:49.413050 # Testcase initialized.
11256 18:06:49.415930 # uc context validated.
11257 18:06:49.419412 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11258 18:06:49.422557 # Handled SIG_COPYCTX
11259 18:06:49.422641 # Available space:3568
11260 18:06:49.426117 # uc context validated.
11261 18:06:49.432500 # Using badly built context - ERR: Bad size for esr_context
11262 18:06:49.439360 # SIG_OK -- SP:0xFFFFEC186D80 si_addr@:0xffffec186d80 si_code:2 token@:0xffffec185b20 offset:-4704
11263 18:06:49.442819 # ==>> completed. PASS(1)
11264 18:06:49.449104 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11265 18:06:49.455536 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEC185B20
11266 18:06:49.458893 ok 4 selftests: arm64: fake_sigreturn_bad_size
11267 18:06:49.465950 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11268 18:06:49.490139 # Registered handlers for all signals.
11269 18:06:49.490243 # Detected MINSTKSIGSZ:4720
11270 18:06:49.493546 # Testcase initialized.
11271 18:06:49.497092 # uc context validated.
11272 18:06:49.500535 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11273 18:06:49.503546 # Handled SIG_COPYCTX
11274 18:06:49.503630 # Available space:3568
11275 18:06:49.509994 # Using badly built context - ERR: Bad size for terminator
11276 18:06:49.520182 # SIG_OK -- SP:0xFFFFED2BD110 si_addr@:0xffffed2bd110 si_code:2 token@:0xffffed2bbeb0 offset:-4704
11277 18:06:49.520269 # ==>> completed. PASS(1)
11278 18:06:49.529898 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11279 18:06:49.536434 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFED2BBEB0
11280 18:06:49.539834 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11281 18:06:49.546768 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11282 18:06:49.564320 # Registered handlers for all signals.
11283 18:06:49.564447 # Detected MINSTKSIGSZ:4720
11284 18:06:49.567361 # Testcase initialized.
11285 18:06:49.570800 # uc context validated.
11286 18:06:49.574282 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11287 18:06:49.577302 # Handled SIG_COPYCTX
11288 18:06:49.577387 # Available space:3568
11289 18:06:49.583917 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11290 18:06:49.593813 # SIG_OK -- SP:0xFFFFF6C8FA70 si_addr@:0xfffff6c8fa70 si_code:2 token@:0xfffff6c8e810 offset:-4704
11291 18:06:49.593930 # ==>> completed. PASS(1)
11292 18:06:49.603893 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11293 18:06:49.610557 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6C8E810
11294 18:06:49.613697 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11295 18:06:49.617268 # selftests: arm64: fake_sigreturn_misaligned_sp
11296 18:06:49.624833 # Registered handlers for all signals.
11297 18:06:49.624920 # Detected MINSTKSIGSZ:4720
11298 18:06:49.627947 # Testcase initialized.
11299 18:06:49.631427 # uc context validated.
11300 18:06:49.634529 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11301 18:06:49.638040 # Handled SIG_COPYCTX
11302 18:06:49.644910 # SIG_OK -- SP:0xFFFFFEA68503 si_addr@:0xfffffea68503 si_code:2 token@:0xfffffea68503 offset:0
11303 18:06:49.648240 # ==>> completed. PASS(1)
11304 18:06:49.654497 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11305 18:06:49.661607 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFEA68503
11306 18:06:49.667859 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11307 18:06:49.670923 # selftests: arm64: fake_sigreturn_missing_fpsimd
11308 18:06:49.697187 # Registered handlers for all signals.
11309 18:06:49.697286 # Detected MINSTKSIGSZ:4720
11310 18:06:49.700529 # Testcase initialized.
11311 18:06:49.703959 # uc context validated.
11312 18:06:49.707559 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11313 18:06:49.710536 # Handled SIG_COPYCTX
11314 18:06:49.714145 # Mangling template header. Spare space:4096
11315 18:06:49.717342 # Using badly built context - ERR: Missing FPSIMD
11316 18:06:49.727048 # SIG_OK -- SP:0xFFFFE0F47210 si_addr@:0xffffe0f47210 si_code:2 token@:0xffffe0f45fb0 offset:-4704
11317 18:06:49.730788 # ==>> completed. PASS(1)
11318 18:06:49.737007 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11319 18:06:49.743966 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE0F45FB0
11320 18:06:49.747033 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11321 18:06:49.753187 # selftests: arm64: fake_sigreturn_sme_change_vl
11322 18:06:49.769409 # Registered handlers for all signals.
11323 18:06:49.769499 # Detected MINSTKSIGSZ:4720
11324 18:06:49.772714 # ==>> completed. SKIP.
11325 18:06:49.779623 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11326 18:06:49.782807 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11327 18:06:49.789211 # selftests: arm64: fake_sigreturn_sve_change_vl
11328 18:06:49.841032 # Registered handlers for all signals.
11329 18:06:49.841173 # Detected MINSTKSIGSZ:4720
11330 18:06:49.844519 # ==>> completed. SKIP.
11331 18:06:49.850805 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11332 18:06:49.854327 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11333 18:06:49.860523 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11334 18:06:49.910710 # Registered handlers for all signals.
11335 18:06:49.910867 # Detected MINSTKSIGSZ:4720
11336 18:06:49.913696 # Testcase initialized.
11337 18:06:49.917463 # uc context validated.
11338 18:06:49.917548 # Handled SIG_TRIG
11339 18:06:49.927351 # SIG_OK -- SP:0xFFFFF9221AB0 si_addr@:0xfffff9221ab0 si_code:2 token@:(nil) offset:-281474861505200
11340 18:06:49.930500 # ==>> completed. PASS(1)
11341 18:06:49.937175 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11342 18:06:49.943765 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11343 18:06:49.946821 # selftests: arm64: mangle_pstate_invalid_daif_bits
11344 18:06:49.980914 # Registered handlers for all signals.
11345 18:06:49.981026 # Detected MINSTKSIGSZ:4720
11346 18:06:49.983889 # Testcase initialized.
11347 18:06:49.987203 # uc context validated.
11348 18:06:49.987288 # Handled SIG_TRIG
11349 18:06:49.997478 # SIG_OK -- SP:0xFFFFEC7B2FD0 si_addr@:0xffffec7b2fd0 si_code:2 token@:(nil) offset:-281474649239504
11350 18:06:50.000911 # ==>> completed. PASS(1)
11351 18:06:50.007271 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11352 18:06:50.010233 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11353 18:06:50.016912 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11354 18:06:50.037883 # Registered handlers for all signals.
11355 18:06:50.037974 # Detected MINSTKSIGSZ:4720
11356 18:06:50.040933 # Testcase initialized.
11357 18:06:50.044454 # uc context validated.
11358 18:06:50.044561 # Handled SIG_TRIG
11359 18:06:50.054256 # SIG_OK -- SP:0xFFFFE4799C00 si_addr@:0xffffe4799c00 si_code:2 token@:(nil) offset:-281474514918400
11360 18:06:50.057805 # ==>> completed. PASS(1)
11361 18:06:50.064178 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11362 18:06:50.067529 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11363 18:06:50.073960 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11364 18:06:50.115248 # Registered handlers for all signals.
11365 18:06:50.115390 # Detected MINSTKSIGSZ:4720
11366 18:06:50.118545 # Testcase initialized.
11367 18:06:50.121965 # uc context validated.
11368 18:06:50.122051 # Handled SIG_TRIG
11369 18:06:50.132151 # SIG_OK -- SP:0xFFFFFAFD95C0 si_addr@:0xfffffafd95c0 si_code:2 token@:(nil) offset:-281474892666304
11370 18:06:50.135235 # ==>> completed. PASS(1)
11371 18:06:50.141919 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11372 18:06:50.144912 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11373 18:06:50.151627 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11374 18:06:50.187529 # Registered handlers for all signals.
11375 18:06:50.187665 # Detected MINSTKSIGSZ:4720
11376 18:06:50.190935 # Testcase initialized.
11377 18:06:50.194279 # uc context validated.
11378 18:06:50.194365 # Handled SIG_TRIG
11379 18:06:50.204240 # SIG_OK -- SP:0xFFFFEAFDD210 si_addr@:0xffffeafdd210 si_code:2 token@:(nil) offset:-281474624246288
11380 18:06:50.207355 # ==>> completed. PASS(1)
11381 18:06:50.214215 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11382 18:06:50.217200 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11383 18:06:50.223992 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11384 18:06:50.262959 # Registered handlers for all signals.
11385 18:06:50.263085 # Detected MINSTKSIGSZ:4720
11386 18:06:50.266525 # Testcase initialized.
11387 18:06:50.269437 # uc context validated.
11388 18:06:50.269522 # Handled SIG_TRIG
11389 18:06:50.279437 # SIG_OK -- SP:0xFFFFD0E49C90 si_addr@:0xffffd0e49c90 si_code:2 token@:(nil) offset:-281474186386576
11390 18:06:50.282906 # ==>> completed. PASS(1)
11391 18:06:50.289442 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11392 18:06:50.292812 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11393 18:06:50.299556 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11394 18:06:50.342616 # Registered handlers for all signals.
11395 18:06:50.342743 # Detected MINSTKSIGSZ:4720
11396 18:06:50.346028 # Testcase initialized.
11397 18:06:50.349626 # uc context validated.
11398 18:06:50.349710 # Handled SIG_TRIG
11399 18:06:50.359541 # SIG_OK -- SP:0xFFFFC8A12280 si_addr@:0xffffc8a12280 si_code:2 token@:(nil) offset:-281474047746688
11400 18:06:50.362692 # ==>> completed. PASS(1)
11401 18:06:50.369363 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11402 18:06:50.372389 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11403 18:06:50.378990 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11404 18:06:50.407134 # Registered handlers for all signals.
11405 18:06:50.407237 # Detected MINSTKSIGSZ:4720
11406 18:06:50.410654 # Testcase initialized.
11407 18:06:50.413699 # uc context validated.
11408 18:06:50.413782 # Handled SIG_TRIG
11409 18:06:50.423689 # SIG_OK -- SP:0xFFFFCADE4F00 si_addr@:0xffffcade4f00 si_code:2 token@:(nil) offset:-281474085310208
11410 18:06:50.427219 # ==>> completed. PASS(1)
11411 18:06:50.433506 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11412 18:06:50.437040 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11413 18:06:50.439977 # selftests: arm64: sme_trap_no_sm
11414 18:06:50.478595 # Registered handlers for all signals.
11415 18:06:50.478742 # Detected MINSTKSIGSZ:4720
11416 18:06:50.482248 # ==>> completed. SKIP.
11417 18:06:50.491894 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11418 18:06:50.495368 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11419 18:06:50.498914 # selftests: arm64: sme_trap_non_streaming
11420 18:06:50.551365 # Registered handlers for all signals.
11421 18:06:50.551495 # Detected MINSTKSIGSZ:4720
11422 18:06:50.554930 # ==>> completed. SKIP.
11423 18:06:50.564861 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11424 18:06:50.571096 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11425 18:06:50.574847 # selftests: arm64: sme_trap_za
11426 18:06:50.608199 # Registered handlers for all signals.
11427 18:06:50.608322 # Detected MINSTKSIGSZ:4720
11428 18:06:50.611715 # Testcase initialized.
11429 18:06:50.621630 # SIG_OK -- SP:0xFFFFF2F0ADF0 si_addr@:0xaaaacb062510 si_code:1 token@:(nil) offset:-187650527339792
11430 18:06:50.621718 # ==>> completed. PASS(1)
11431 18:06:50.631146 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11432 18:06:50.631260 ok 21 selftests: arm64: sme_trap_za
11433 18:06:50.634361 # selftests: arm64: sme_vl
11434 18:06:50.680726 # Registered handlers for all signals.
11435 18:06:50.680853 # Detected MINSTKSIGSZ:4720
11436 18:06:50.683865 # ==>> completed. SKIP.
11437 18:06:50.690785 # # SME VL :: Check that we get the right SME VL reported
11438 18:06:50.694323 ok 22 selftests: arm64: sme_vl # SKIP
11439 18:06:50.694411 # selftests: arm64: ssve_regs
11440 18:06:50.747740 # Registered handlers for all signals.
11441 18:06:50.747879 # Detected MINSTKSIGSZ:4720
11442 18:06:50.751257 # ==>> completed. SKIP.
11443 18:06:50.757593 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11444 18:06:50.764024 ok 23 selftests: arm64: ssve_regs # SKIP
11445 18:06:50.764112 # selftests: arm64: sve_regs
11446 18:06:50.826288 # Registered handlers for all signals.
11447 18:06:50.826422 # Detected MINSTKSIGSZ:4720
11448 18:06:50.829274 # ==>> completed. SKIP.
11449 18:06:50.836366 # # SVE registers :: Check that we get the right SVE registers reported
11450 18:06:50.839091 ok 24 selftests: arm64: sve_regs # SKIP
11451 18:06:50.842920 # selftests: arm64: sve_vl
11452 18:06:50.889914 # Registered handlers for all signals.
11453 18:06:50.890043 # Detected MINSTKSIGSZ:4720
11454 18:06:50.893269 # ==>> completed. SKIP.
11455 18:06:50.896339 # # SVE VL :: Check that we get the right SVE VL reported
11456 18:06:50.899858 ok 25 selftests: arm64: sve_vl # SKIP
11457 18:06:50.906266 # selftests: arm64: za_no_regs
11458 18:06:50.960505 # Registered handlers for all signals.
11459 18:06:50.960679 # Detected MINSTKSIGSZ:4720
11460 18:06:50.963626 # ==>> completed. SKIP.
11461 18:06:50.970294 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11462 18:06:50.973373 ok 26 selftests: arm64: za_no_regs # SKIP
11463 18:06:50.976844 # selftests: arm64: za_regs
11464 18:06:51.025334 # Registered handlers for all signals.
11465 18:06:51.025461 # Detected MINSTKSIGSZ:4720
11466 18:06:51.028770 # ==>> completed. SKIP.
11467 18:06:51.035240 # # ZA register :: Check that we get the right ZA registers reported
11468 18:06:51.038810 ok 27 selftests: arm64: za_regs # SKIP
11469 18:06:51.041895 # selftests: arm64: pac
11470 18:06:51.083769 # TAP version 13
11471 18:06:51.083897 # 1..7
11472 18:06:51.086928 # # Starting 7 tests from 1 test cases.
11473 18:06:51.090392 # # RUN global.corrupt_pac ...
11474 18:06:51.093522 # # SKIP PAUTH not enabled
11475 18:06:51.096862 # # OK global.corrupt_pac
11476 18:06:51.100434 # ok 1 # SKIP PAUTH not enabled
11477 18:06:51.107045 # # RUN global.pac_instructions_not_nop ...
11478 18:06:51.110573 # # SKIP PAUTH not enabled
11479 18:06:51.113445 # # OK global.pac_instructions_not_nop
11480 18:06:51.116904 # ok 2 # SKIP PAUTH not enabled
11481 18:06:51.123186 # # RUN global.pac_instructions_not_nop_generic ...
11482 18:06:51.126557 # # SKIP Generic PAUTH not enabled
11483 18:06:51.130107 # # OK global.pac_instructions_not_nop_generic
11484 18:06:51.133056 # ok 3 # SKIP Generic PAUTH not enabled
11485 18:06:51.139950 # # RUN global.single_thread_different_keys ...
11486 18:06:51.142978 # # SKIP PAUTH not enabled
11487 18:06:51.149520 # # OK global.single_thread_different_keys
11488 18:06:51.149607 # ok 4 # SKIP PAUTH not enabled
11489 18:06:51.156301 # # RUN global.exec_changed_keys ...
11490 18:06:51.159797 # # SKIP PAUTH not enabled
11491 18:06:51.162768 # # OK global.exec_changed_keys
11492 18:06:51.166269 # ok 5 # SKIP PAUTH not enabled
11493 18:06:51.169821 # # RUN global.context_switch_keep_keys ...
11494 18:06:51.172798 # # SKIP PAUTH not enabled
11495 18:06:51.179435 # # OK global.context_switch_keep_keys
11496 18:06:51.179522 # ok 6 # SKIP PAUTH not enabled
11497 18:06:51.186186 # # RUN global.context_switch_keep_keys_generic ...
11498 18:06:51.189307 # # SKIP Generic PAUTH not enabled
11499 18:06:51.195896 # # OK global.context_switch_keep_keys_generic
11500 18:06:51.199328 # ok 7 # SKIP Generic PAUTH not enabled
11501 18:06:51.202916 # # PASSED: 7 / 7 tests passed.
11502 18:06:51.205795 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11503 18:06:51.209386 ok 28 selftests: arm64: pac
11504 18:06:51.212416 # selftests: arm64: fp-stress
11505 18:07:00.396227 <6>[ 37.653712] vpu: disabling
11506 18:07:00.399067 <6>[ 37.656764] vproc2: disabling
11507 18:07:00.402405 <6>[ 37.660394] vproc1: disabling
11508 18:07:00.405755 <6>[ 37.664032] vaud18: disabling
11509 18:07:00.412967 <6>[ 37.667559] vsram_others: disabling
11510 18:07:00.416517 <6>[ 37.671532] va09: disabling
11511 18:07:00.419633 <6>[ 37.674734] vsram_md: disabling
11512 18:07:00.422668 <6>[ 37.678325] Vgpu: disabling
11513 18:07:01.099416 # TAP version 13
11514 18:07:01.100061 # 1..16
11515 18:07:01.102418 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11516 18:07:01.106568 # # Will run for 10s
11517 18:07:01.107097 # # Started FPSIMD-0-0
11518 18:07:01.109302 # # Started FPSIMD-0-1
11519 18:07:01.113561 # # Started FPSIMD-1-0
11520 18:07:01.114104 # # Started FPSIMD-1-1
11521 18:07:01.116080 # # Started FPSIMD-2-0
11522 18:07:01.116673 # # Started FPSIMD-2-1
11523 18:07:01.119251 # # Started FPSIMD-3-0
11524 18:07:01.122481 # # Started FPSIMD-3-1
11525 18:07:01.123017 # # Started FPSIMD-4-0
11526 18:07:01.126108 # # Started FPSIMD-4-1
11527 18:07:01.129328 # # Started FPSIMD-5-0
11528 18:07:01.129759 # # Started FPSIMD-5-1
11529 18:07:01.132533 # # Started FPSIMD-6-0
11530 18:07:01.133009 # # Started FPSIMD-6-1
11531 18:07:01.135554 # # Started FPSIMD-7-0
11532 18:07:01.138715 # # Started FPSIMD-7-1
11533 18:07:01.142261 # # FPSIMD-0-0: Vector length: 128 bits
11534 18:07:01.142707 # # FPSIMD-0-0: PID: 1167
11535 18:07:01.148964 # # FPSIMD-1-0: Vector length: 128 bits
11536 18:07:01.149395 # # FPSIMD-1-0: PID: 1169
11537 18:07:01.152022 # # FPSIMD-2-1: Vector length: 128 bits
11538 18:07:01.155895 # # FPSIMD-2-1: PID: 1172
11539 18:07:01.159081 # # FPSIMD-0-1: Vector length: 128 bits
11540 18:07:01.162173 # # FPSIMD-0-1: PID: 1168
11541 18:07:01.165594 # # FPSIMD-2-0: Vector length: 128 bits
11542 18:07:01.168510 # # FPSIMD-2-0: PID: 1171
11543 18:07:01.171888 # # FPSIMD-1-1: Vector length: 128 bits
11544 18:07:01.172322 # # FPSIMD-1-1: PID: 1170
11545 18:07:01.178787 # # FPSIMD-4-1: Vector length: 128 bits
11546 18:07:01.179225 # # FPSIMD-4-1: PID: 1176
11547 18:07:01.181708 # # FPSIMD-5-1: Vector length: 128 bits
11548 18:07:01.185177 # # FPSIMD-5-1: PID: 1178
11549 18:07:01.188892 # # FPSIMD-3-1: Vector length: 128 bits
11550 18:07:01.191840 # # FPSIMD-3-1: PID: 1174
11551 18:07:01.195229 # # FPSIMD-5-0: Vector length: 128 bits
11552 18:07:01.198682 # # FPSIMD-5-0: PID: 1177
11553 18:07:01.201844 # # FPSIMD-3-0: Vector length: 128 bits
11554 18:07:01.202287 # # FPSIMD-3-0: PID: 1173
11555 18:07:01.205064 # # FPSIMD-7-0: Vector length: 128 bits
11556 18:07:01.208810 # # FPSIMD-7-0: PID: 1181
11557 18:07:01.211878 # # FPSIMD-6-1: Vector length: 128 bits
11558 18:07:01.215146 # # FPSIMD-6-1: PID: 1180
11559 18:07:01.218651 # # FPSIMD-7-1: Vector length: 128 bits
11560 18:07:01.221844 # # FPSIMD-7-1: PID: 1182
11561 18:07:01.224909 # # FPSIMD-6-0: Vector length: 128 bits
11562 18:07:01.225328 # # FPSIMD-6-0: PID: 1179
11563 18:07:01.231968 # # FPSIMD-4-0: Vector length: 128 bits
11564 18:07:01.232489 # # FPSIMD-4-0: PID: 1175
11565 18:07:01.235156 # # Finishing up...
11566 18:07:01.241475 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1160316, signals=10
11567 18:07:01.248333 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1435105, signals=10
11568 18:07:01.255154 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1452053, signals=10
11569 18:07:01.261520 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1217131, signals=10
11570 18:07:01.271484 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1007530, signals=10
11571 18:07:01.277890 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=873615, signals=10
11572 18:07:01.284428 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1050469, signals=10
11573 18:07:01.284903 # ok 1 FPSIMD-0-0
11574 18:07:01.288021 # ok 2 FPSIMD-0-1
11575 18:07:01.288444 # ok 3 FPSIMD-1-0
11576 18:07:01.291572 # ok 4 FPSIMD-1-1
11577 18:07:01.292000 # ok 5 FPSIMD-2-0
11578 18:07:01.294385 # ok 6 FPSIMD-2-1
11579 18:07:01.294878 # ok 7 FPSIMD-3-0
11580 18:07:01.298434 # ok 8 FPSIMD-3-1
11581 18:07:01.298963 # ok 9 FPSIMD-4-0
11582 18:07:01.301725 # ok 10 FPSIMD-4-1
11583 18:07:01.304641 # ok 11 FPSIMD-5-0
11584 18:07:01.305071 # ok 12 FPSIMD-5-1
11585 18:07:01.307887 # ok 13 FPSIMD-6-0
11586 18:07:01.308417 # ok 14 FPSIMD-6-1
11587 18:07:01.311286 # ok 15 FPSIMD-7-0
11588 18:07:01.311714 # ok 16 FPSIMD-7-1
11589 18:07:01.317708 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=798063, signals=9
11590 18:07:01.324260 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1174235, signals=10
11591 18:07:01.334577 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1217862, signals=10
11592 18:07:01.340675 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=832802, signals=9
11593 18:07:01.347325 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1555545, signals=10
11594 18:07:01.354083 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1521841, signals=10
11595 18:07:01.360344 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1327823, signals=10
11596 18:07:01.367079 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1416201, signals=9
11597 18:07:01.377004 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1036682, signals=10
11598 18:07:01.380520 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11599 18:07:01.383866 ok 29 selftests: arm64: fp-stress
11600 18:07:01.387039 # selftests: arm64: sve-ptrace
11601 18:07:01.387480 # TAP version 13
11602 18:07:01.390351 # 1..4104
11603 18:07:01.394125 # ok 2 # SKIP SVE not available
11604 18:07:01.396949 # # Planned tests != run tests (4104 != 1)
11605 18:07:01.400855 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11606 18:07:01.403636 ok 30 selftests: arm64: sve-ptrace # SKIP
11607 18:07:01.407061 # selftests: arm64: sve-probe-vls
11608 18:07:01.410284 # TAP version 13
11609 18:07:01.410873 # 1..2
11610 18:07:01.413576 # ok 2 # SKIP SVE not available
11611 18:07:01.417174 # # Planned tests != run tests (2 != 1)
11612 18:07:01.420318 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11613 18:07:01.427090 ok 31 selftests: arm64: sve-probe-vls # SKIP
11614 18:07:01.427712 # selftests: arm64: vec-syscfg
11615 18:07:01.430201 # TAP version 13
11616 18:07:01.430733 # 1..20
11617 18:07:01.433314 # ok 1 # SKIP SVE not supported
11618 18:07:01.436510 # ok 2 # SKIP SVE not supported
11619 18:07:01.440290 # ok 3 # SKIP SVE not supported
11620 18:07:01.443462 # ok 4 # SKIP SVE not supported
11621 18:07:01.446959 # ok 5 # SKIP SVE not supported
11622 18:07:01.447528 # ok 6 # SKIP SVE not supported
11623 18:07:01.450625 # ok 7 # SKIP SVE not supported
11624 18:07:01.453458 # ok 8 # SKIP SVE not supported
11625 18:07:01.456852 # ok 9 # SKIP SVE not supported
11626 18:07:01.460492 # ok 10 # SKIP SVE not supported
11627 18:07:01.463402 # ok 11 # SKIP SME not supported
11628 18:07:01.466447 # ok 12 # SKIP SME not supported
11629 18:07:01.470277 # ok 13 # SKIP SME not supported
11630 18:07:01.470812 # ok 14 # SKIP SME not supported
11631 18:07:01.473148 # ok 15 # SKIP SME not supported
11632 18:07:01.476644 # ok 16 # SKIP SME not supported
11633 18:07:01.479897 # ok 17 # SKIP SME not supported
11634 18:07:01.482866 # ok 18 # SKIP SME not supported
11635 18:07:01.486416 # ok 19 # SKIP SME not supported
11636 18:07:01.489824 # ok 20 # SKIP SME not supported
11637 18:07:01.493502 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11638 18:07:01.496326 ok 32 selftests: arm64: vec-syscfg
11639 18:07:01.499793 # selftests: arm64: za-fork
11640 18:07:01.500408 # TAP version 13
11641 18:07:01.503347 # 1..1
11642 18:07:01.503922 # # PID: 1259
11643 18:07:01.506403 # # SME support not present
11644 18:07:01.506973 # ok 0 skipped
11645 18:07:01.512858 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11646 18:07:01.515909 ok 33 selftests: arm64: za-fork
11647 18:07:01.516521 # selftests: arm64: za-ptrace
11648 18:07:01.519453 # TAP version 13
11649 18:07:01.519968 # 1..1
11650 18:07:01.522883 # ok 2 # SKIP SME not available
11651 18:07:01.529123 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11652 18:07:01.532735 ok 34 selftests: arm64: za-ptrace # SKIP
11653 18:07:01.535712 # selftests: arm64: check_buffer_fill
11654 18:07:01.566710 # # SKIP: MTE features unavailable
11655 18:07:01.574364 ok 35 selftests: arm64: check_buffer_fill # SKIP
11656 18:07:01.589880 # selftests: arm64: check_child_memory
11657 18:07:01.645729 # # SKIP: MTE features unavailable
11658 18:07:01.653813 ok 36 selftests: arm64: check_child_memory # SKIP
11659 18:07:01.667908 # selftests: arm64: check_gcr_el1_cswitch
11660 18:07:01.728336 # # SKIP: MTE features unavailable
11661 18:07:01.735315 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11662 18:07:01.753187 # selftests: arm64: check_ksm_options
11663 18:07:01.789751 # # SKIP: MTE features unavailable
11664 18:07:01.796649 ok 38 selftests: arm64: check_ksm_options # SKIP
11665 18:07:01.815735 # selftests: arm64: check_mmap_options
11666 18:07:01.893809 # # SKIP: MTE features unavailable
11667 18:07:01.901921 ok 39 selftests: arm64: check_mmap_options # SKIP
11668 18:07:01.916155 # selftests: arm64: check_prctl
11669 18:07:01.970646 # TAP version 13
11670 18:07:01.971164 # 1..5
11671 18:07:01.974132 # ok 1 check_basic_read
11672 18:07:01.974755 # ok 2 NONE
11673 18:07:01.977474 # ok 3 # SKIP SYNC
11674 18:07:01.978059 # ok 4 # SKIP ASYNC
11675 18:07:01.980635 # ok 5 # SKIP SYNC+ASYNC
11676 18:07:01.984079 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11677 18:07:01.987401 ok 40 selftests: arm64: check_prctl
11678 18:07:01.994460 # selftests: arm64: check_tags_inclusion
11679 18:07:02.062168 # # SKIP: MTE features unavailable
11680 18:07:02.071411 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11681 18:07:02.083359 # selftests: arm64: check_user_mem
11682 18:07:02.138413 # # SKIP: MTE features unavailable
11683 18:07:02.145397 ok 42 selftests: arm64: check_user_mem # SKIP
11684 18:07:02.160846 # selftests: arm64: btitest
11685 18:07:02.202495 # TAP version 13
11686 18:07:02.203030 # 1..18
11687 18:07:02.205097 # # HWCAP_PACA not present
11688 18:07:02.208660 # # HWCAP2_BTI not present
11689 18:07:02.209147 # # Test binary built for BTI
11690 18:07:02.215100 # ok 1 nohint_func/call_using_br_x0 # SKIP
11691 18:07:02.218520 # ok 1 nohint_func/call_using_br_x16 # SKIP
11692 18:07:02.222159 # ok 1 nohint_func/call_using_blr # SKIP
11693 18:07:02.225070 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11694 18:07:02.228505 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11695 18:07:02.231949 # ok 1 bti_none_func/call_using_blr # SKIP
11696 18:07:02.238603 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11697 18:07:02.242142 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11698 18:07:02.245185 # ok 1 bti_c_func/call_using_blr # SKIP
11699 18:07:02.248419 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11700 18:07:02.251745 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11701 18:07:02.255233 # ok 1 bti_j_func/call_using_blr # SKIP
11702 18:07:02.258256 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11703 18:07:02.262027 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11704 18:07:02.268264 # ok 1 bti_jc_func/call_using_blr # SKIP
11705 18:07:02.271788 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11706 18:07:02.274821 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11707 18:07:02.278413 # ok 1 paciasp_func/call_using_blr # SKIP
11708 18:07:02.284606 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11709 18:07:02.288351 # # WARNING - EXPECTED TEST COUNT WRONG
11710 18:07:02.291393 ok 43 selftests: arm64: btitest
11711 18:07:02.291961 # selftests: arm64: nobtitest
11712 18:07:02.294628 # TAP version 13
11713 18:07:02.295062 # 1..18
11714 18:07:02.298319 # # HWCAP_PACA not present
11715 18:07:02.301502 # # HWCAP2_BTI not present
11716 18:07:02.304627 # # Test binary not built for BTI
11717 18:07:02.308116 # ok 1 nohint_func/call_using_br_x0 # SKIP
11718 18:07:02.311204 # ok 1 nohint_func/call_using_br_x16 # SKIP
11719 18:07:02.314929 # ok 1 nohint_func/call_using_blr # SKIP
11720 18:07:02.318289 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11721 18:07:02.321241 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11722 18:07:02.327724 # ok 1 bti_none_func/call_using_blr # SKIP
11723 18:07:02.331200 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11724 18:07:02.334215 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11725 18:07:02.338011 # ok 1 bti_c_func/call_using_blr # SKIP
11726 18:07:02.340808 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11727 18:07:02.344618 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11728 18:07:02.347586 # ok 1 bti_j_func/call_using_blr # SKIP
11729 18:07:02.351182 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11730 18:07:02.357434 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11731 18:07:02.360931 # ok 1 bti_jc_func/call_using_blr # SKIP
11732 18:07:02.364151 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11733 18:07:02.367228 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11734 18:07:02.370729 # ok 1 paciasp_func/call_using_blr # SKIP
11735 18:07:02.377196 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11736 18:07:02.380982 # # WARNING - EXPECTED TEST COUNT WRONG
11737 18:07:02.384060 ok 44 selftests: arm64: nobtitest
11738 18:07:02.384788 # selftests: arm64: hwcap
11739 18:07:02.387666 # TAP version 13
11740 18:07:02.388188 # 1..28
11741 18:07:02.390752 # ok 1 cpuinfo_match_RNG
11742 18:07:02.394325 # # SIGILL reported for RNG
11743 18:07:02.394865 # ok 2 # SKIP sigill_RNG
11744 18:07:02.397265 # ok 3 cpuinfo_match_SME
11745 18:07:02.397700 # ok 4 sigill_SME
11746 18:07:02.400526 # ok 5 cpuinfo_match_SVE
11747 18:07:02.403963 # ok 6 sigill_SVE
11748 18:07:02.404395 # ok 7 cpuinfo_match_SVE 2
11749 18:07:02.407182 # # SIGILL reported for SVE 2
11750 18:07:02.410916 # ok 8 # SKIP sigill_SVE 2
11751 18:07:02.413943 # ok 9 cpuinfo_match_SVE AES
11752 18:07:02.417072 # # SIGILL reported for SVE AES
11753 18:07:02.417505 # ok 10 # SKIP sigill_SVE AES
11754 18:07:02.420403 # ok 11 cpuinfo_match_SVE2 PMULL
11755 18:07:02.424087 # # SIGILL reported for SVE2 PMULL
11756 18:07:02.427172 # ok 12 # SKIP sigill_SVE2 PMULL
11757 18:07:02.430591 # ok 13 cpuinfo_match_SVE2 BITPERM
11758 18:07:02.433482 # # SIGILL reported for SVE2 BITPERM
11759 18:07:02.437013 # ok 14 # SKIP sigill_SVE2 BITPERM
11760 18:07:02.440277 # ok 15 cpuinfo_match_SVE2 SHA3
11761 18:07:02.443598 # # SIGILL reported for SVE2 SHA3
11762 18:07:02.447171 # ok 16 # SKIP sigill_SVE2 SHA3
11763 18:07:02.447605 # ok 17 cpuinfo_match_SVE2 SM4
11764 18:07:02.450152 # # SIGILL reported for SVE2 SM4
11765 18:07:02.453566 # ok 18 # SKIP sigill_SVE2 SM4
11766 18:07:02.457017 # ok 19 cpuinfo_match_SVE2 I8MM
11767 18:07:02.460133 # # SIGILL reported for SVE2 I8MM
11768 18:07:02.463461 # ok 20 # SKIP sigill_SVE2 I8MM
11769 18:07:02.466700 # ok 21 cpuinfo_match_SVE2 F32MM
11770 18:07:02.470361 # # SIGILL reported for SVE2 F32MM
11771 18:07:02.473490 # ok 22 # SKIP sigill_SVE2 F32MM
11772 18:07:02.476704 # ok 23 cpuinfo_match_SVE2 F64MM
11773 18:07:02.477136 # # SIGILL reported for SVE2 F64MM
11774 18:07:02.480236 # ok 24 # SKIP sigill_SVE2 F64MM
11775 18:07:02.483292 # ok 25 cpuinfo_match_SVE2 BF16
11776 18:07:02.486418 # # SIGILL reported for SVE2 BF16
11777 18:07:02.490440 # ok 26 # SKIP sigill_SVE2 BF16
11778 18:07:02.493258 # ok 27 cpuinfo_match_SVE2 EBF16
11779 18:07:02.496470 # ok 28 # SKIP sigill_SVE2 EBF16
11780 18:07:02.499558 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11781 18:07:02.503207 ok 45 selftests: arm64: hwcap
11782 18:07:02.506468 # selftests: arm64: ptrace
11783 18:07:02.507002 # TAP version 13
11784 18:07:02.509928 # 1..7
11785 18:07:02.513080 # # Parent is 1501, child is 1502
11786 18:07:02.513512 # ok 1 read_tpidr_one
11787 18:07:02.516270 # ok 2 write_tpidr_one
11788 18:07:02.516742 # ok 3 verify_tpidr_one
11789 18:07:02.519779 # ok 4 count_tpidrs
11790 18:07:02.522782 # ok 5 tpidr2_write
11791 18:07:02.523209 # ok 6 tpidr2_read
11792 18:07:02.526228 # ok 7 write_tpidr_only
11793 18:07:02.529724 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11794 18:07:02.532720 ok 46 selftests: arm64: ptrace
11795 18:07:02.536276 # selftests: arm64: syscall-abi
11796 18:07:02.536738 # TAP version 13
11797 18:07:02.539360 # 1..2
11798 18:07:02.539789 # ok 1 getpid() FPSIMD
11799 18:07:02.542962 # ok 2 sched_yield() FPSIMD
11800 18:07:02.549470 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11801 18:07:02.549922 ok 47 selftests: arm64: syscall-abi
11802 18:07:02.552996 # selftests: arm64: tpidr2
11803 18:07:02.590675 # TAP version 13
11804 18:07:02.591212 # 1..5
11805 18:07:02.593352 # # PID: 1538
11806 18:07:02.593786 # # SME support not present
11807 18:07:02.597230 # ok 0 skipped, TPIDR2 not supported
11808 18:07:02.600242 # ok 1 skipped, TPIDR2 not supported
11809 18:07:02.603651 # ok 2 skipped, TPIDR2 not supported
11810 18:07:02.606739 # ok 3 skipped, TPIDR2 not supported
11811 18:07:02.609841 # ok 4 skipped, TPIDR2 not supported
11812 18:07:02.616607 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11813 18:07:02.620093 ok 48 selftests: arm64: tpidr2
11814 18:07:04.123075 arm64_tags_test pass
11815 18:07:04.125973 arm64_run_tags_test_sh pass
11816 18:07:04.129446 arm64_fake_sigreturn_bad_magic pass
11817 18:07:04.132773 arm64_fake_sigreturn_bad_size pass
11818 18:07:04.135972 arm64_fake_sigreturn_bad_size_for_magic0 pass
11819 18:07:04.139109 arm64_fake_sigreturn_duplicated_fpsimd pass
11820 18:07:04.142548 arm64_fake_sigreturn_misaligned_sp pass
11821 18:07:04.146529 arm64_fake_sigreturn_missing_fpsimd pass
11822 18:07:04.149161 arm64_fake_sigreturn_sme_change_vl skip
11823 18:07:04.156479 arm64_fake_sigreturn_sve_change_vl skip
11824 18:07:04.159668 arm64_mangle_pstate_invalid_compat_toggle pass
11825 18:07:04.162422 arm64_mangle_pstate_invalid_daif_bits pass
11826 18:07:04.166204 arm64_mangle_pstate_invalid_mode_el1h pass
11827 18:07:04.169312 arm64_mangle_pstate_invalid_mode_el1t pass
11828 18:07:04.172481 arm64_mangle_pstate_invalid_mode_el2h pass
11829 18:07:04.179310 arm64_mangle_pstate_invalid_mode_el2t pass
11830 18:07:04.182840 arm64_mangle_pstate_invalid_mode_el3h pass
11831 18:07:04.185524 arm64_mangle_pstate_invalid_mode_el3t pass
11832 18:07:04.189354 arm64_sme_trap_no_sm skip
11833 18:07:04.189793 arm64_sme_trap_non_streaming skip
11834 18:07:04.192418 arm64_sme_trap_za pass
11835 18:07:04.195563 arm64_sme_vl skip
11836 18:07:04.195993 arm64_ssve_regs skip
11837 18:07:04.199138 arm64_sve_regs skip
11838 18:07:04.199588 arm64_sve_vl skip
11839 18:07:04.202151 arm64_za_no_regs skip
11840 18:07:04.202610 arm64_za_regs skip
11841 18:07:04.205600 arm64_pac_PAUTH_not_enabled skip
11842 18:07:04.209192 arm64_pac_PAUTH_not_enabled_dup2 skip
11843 18:07:04.212506 arm64_pac_Generic_PAUTH_not_enabled skip
11844 18:07:04.215635 arm64_pac_PAUTH_not_enabled_dup3 skip
11845 18:07:04.219334 arm64_pac_PAUTH_not_enabled_dup4 skip
11846 18:07:04.222519 arm64_pac_PAUTH_not_enabled_dup5 skip
11847 18:07:04.228957 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11848 18:07:04.229447 arm64_pac pass
11849 18:07:04.231996 arm64_fp-stress_FPSIMD-0-0 pass
11850 18:07:04.235412 arm64_fp-stress_FPSIMD-0-1 pass
11851 18:07:04.239230 arm64_fp-stress_FPSIMD-1-0 pass
11852 18:07:04.242055 arm64_fp-stress_FPSIMD-1-1 pass
11853 18:07:04.242625 arm64_fp-stress_FPSIMD-2-0 pass
11854 18:07:04.245581 arm64_fp-stress_FPSIMD-2-1 pass
11855 18:07:04.248651 arm64_fp-stress_FPSIMD-3-0 pass
11856 18:07:04.252467 arm64_fp-stress_FPSIMD-3-1 pass
11857 18:07:04.255635 arm64_fp-stress_FPSIMD-4-0 pass
11858 18:07:04.258801 arm64_fp-stress_FPSIMD-4-1 pass
11859 18:07:04.262013 arm64_fp-stress_FPSIMD-5-0 pass
11860 18:07:04.265293 arm64_fp-stress_FPSIMD-5-1 pass
11861 18:07:04.265724 arm64_fp-stress_FPSIMD-6-0 pass
11862 18:07:04.268752 arm64_fp-stress_FPSIMD-6-1 pass
11863 18:07:04.271904 arm64_fp-stress_FPSIMD-7-0 pass
11864 18:07:04.275663 arm64_fp-stress_FPSIMD-7-1 pass
11865 18:07:04.278732 arm64_fp-stress pass
11866 18:07:04.281557 arm64_sve-ptrace_SVE_not_available skip
11867 18:07:04.282091 arm64_sve-ptrace skip
11868 18:07:04.285263 arm64_sve-probe-vls_SVE_not_available skip
11869 18:07:04.288199 arm64_sve-probe-vls skip
11870 18:07:04.291820 arm64_vec-syscfg_SVE_not_supported skip
11871 18:07:04.294921 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11872 18:07:04.301920 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11873 18:07:04.304873 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11874 18:07:04.308466 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11875 18:07:04.311305 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11876 18:07:04.314848 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11877 18:07:04.321258 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11878 18:07:04.324662 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11879 18:07:04.327759 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11880 18:07:04.331209 arm64_vec-syscfg_SME_not_supported skip
11881 18:07:04.334925 arm64_vec-syscfg_SME_not_supported_dup2 skip
11882 18:07:04.341123 arm64_vec-syscfg_SME_not_supported_dup3 skip
11883 18:07:04.344707 arm64_vec-syscfg_SME_not_supported_dup4 skip
11884 18:07:04.347883 arm64_vec-syscfg_SME_not_supported_dup5 skip
11885 18:07:04.351211 arm64_vec-syscfg_SME_not_supported_dup6 skip
11886 18:07:04.354358 arm64_vec-syscfg_SME_not_supported_dup7 skip
11887 18:07:04.361317 arm64_vec-syscfg_SME_not_supported_dup8 skip
11888 18:07:04.364469 arm64_vec-syscfg_SME_not_supported_dup9 skip
11889 18:07:04.367358 arm64_vec-syscfg_SME_not_supported_dup10 skip
11890 18:07:04.371243 arm64_vec-syscfg pass
11891 18:07:04.371770 arm64_za-fork_skipped pass
11892 18:07:04.374160 arm64_za-fork pass
11893 18:07:04.377431 arm64_za-ptrace_SME_not_available skip
11894 18:07:04.381105 arm64_za-ptrace skip
11895 18:07:04.381632 arm64_check_buffer_fill skip
11896 18:07:04.384292 arm64_check_child_memory skip
11897 18:07:04.387440 arm64_check_gcr_el1_cswitch skip
11898 18:07:04.390732 arm64_check_ksm_options skip
11899 18:07:04.394172 arm64_check_mmap_options skip
11900 18:07:04.397387 arm64_check_prctl_check_basic_read pass
11901 18:07:04.397821 arm64_check_prctl_NONE pass
11902 18:07:04.400515 arm64_check_prctl_SYNC skip
11903 18:07:04.403855 arm64_check_prctl_ASYNC skip
11904 18:07:04.407428 arm64_check_prctl_SYNC_ASYNC skip
11905 18:07:04.411036 arm64_check_prctl pass
11906 18:07:04.411571 arm64_check_tags_inclusion skip
11907 18:07:04.413873 arm64_check_user_mem skip
11908 18:07:04.417241 arm64_btitest_nohint_func_call_using_br_x0 skip
11909 18:07:04.424328 arm64_btitest_nohint_func_call_using_br_x16 skip
11910 18:07:04.427112 arm64_btitest_nohint_func_call_using_blr skip
11911 18:07:04.430189 arm64_btitest_bti_none_func_call_using_br_x0 skip
11912 18:07:04.436603 arm64_btitest_bti_none_func_call_using_br_x16 skip
11913 18:07:04.439968 arm64_btitest_bti_none_func_call_using_blr skip
11914 18:07:04.443583 arm64_btitest_bti_c_func_call_using_br_x0 skip
11915 18:07:04.450098 arm64_btitest_bti_c_func_call_using_br_x16 skip
11916 18:07:04.453814 arm64_btitest_bti_c_func_call_using_blr skip
11917 18:07:04.456758 arm64_btitest_bti_j_func_call_using_br_x0 skip
11918 18:07:04.460169 arm64_btitest_bti_j_func_call_using_br_x16 skip
11919 18:07:04.466369 arm64_btitest_bti_j_func_call_using_blr skip
11920 18:07:04.470106 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11921 18:07:04.473145 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11922 18:07:04.476620 arm64_btitest_bti_jc_func_call_using_blr skip
11923 18:07:04.482690 arm64_btitest_paciasp_func_call_using_br_x0 skip
11924 18:07:04.486159 arm64_btitest_paciasp_func_call_using_br_x16 skip
11925 18:07:04.489146 arm64_btitest_paciasp_func_call_using_blr skip
11926 18:07:04.492765 arm64_btitest pass
11927 18:07:04.495948 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11928 18:07:04.502763 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11929 18:07:04.505863 arm64_nobtitest_nohint_func_call_using_blr skip
11930 18:07:04.509068 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11931 18:07:04.515633 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11932 18:07:04.518970 arm64_nobtitest_bti_none_func_call_using_blr skip
11933 18:07:04.522018 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11934 18:07:04.528717 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11935 18:07:04.532129 arm64_nobtitest_bti_c_func_call_using_blr skip
11936 18:07:04.535643 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11937 18:07:04.542575 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11938 18:07:04.545384 arm64_nobtitest_bti_j_func_call_using_blr skip
11939 18:07:04.548521 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11940 18:07:04.551891 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11941 18:07:04.558671 arm64_nobtitest_bti_jc_func_call_using_blr skip
11942 18:07:04.561768 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11943 18:07:04.568388 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11944 18:07:04.571598 arm64_nobtitest_paciasp_func_call_using_blr skip
11945 18:07:04.571703 arm64_nobtitest pass
11946 18:07:04.575121 arm64_hwcap_cpuinfo_match_RNG pass
11947 18:07:04.578344 arm64_hwcap_sigill_RNG skip
11948 18:07:04.581942 arm64_hwcap_cpuinfo_match_SME pass
11949 18:07:04.584925 arm64_hwcap_sigill_SME pass
11950 18:07:04.588514 arm64_hwcap_cpuinfo_match_SVE pass
11951 18:07:04.591816 arm64_hwcap_sigill_SVE pass
11952 18:07:04.594833 arm64_hwcap_cpuinfo_match_SVE_2 pass
11953 18:07:04.595012 arm64_hwcap_sigill_SVE_2 skip
11954 18:07:04.598047 arm64_hwcap_cpuinfo_match_SVE_AES pass
11955 18:07:04.601755 arm64_hwcap_sigill_SVE_AES skip
11956 18:07:04.604897 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11957 18:07:04.608517 arm64_hwcap_sigill_SVE2_PMULL skip
11958 18:07:04.614910 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11959 18:07:04.618463 arm64_hwcap_sigill_SVE2_BITPERM skip
11960 18:07:04.621813 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11961 18:07:04.625347 arm64_hwcap_sigill_SVE2_SHA3 skip
11962 18:07:04.628370 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11963 18:07:04.631650 arm64_hwcap_sigill_SVE2_SM4 skip
11964 18:07:04.634826 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11965 18:07:04.638166 arm64_hwcap_sigill_SVE2_I8MM skip
11966 18:07:04.641602 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11967 18:07:04.644688 arm64_hwcap_sigill_SVE2_F32MM skip
11968 18:07:04.648155 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11969 18:07:04.651564 arm64_hwcap_sigill_SVE2_F64MM skip
11970 18:07:04.654637 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11971 18:07:04.658050 arm64_hwcap_sigill_SVE2_BF16 skip
11972 18:07:04.661314 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11973 18:07:04.664701 arm64_hwcap_sigill_SVE2_EBF16 skip
11974 18:07:04.665362 arm64_hwcap pass
11975 18:07:04.668085 arm64_ptrace_read_tpidr_one pass
11976 18:07:04.671197 arm64_ptrace_write_tpidr_one pass
11977 18:07:04.674724 arm64_ptrace_verify_tpidr_one pass
11978 18:07:04.677988 arm64_ptrace_count_tpidrs pass
11979 18:07:04.681110 arm64_ptrace_tpidr2_write pass
11980 18:07:04.684720 arm64_ptrace_tpidr2_read pass
11981 18:07:04.685373 arm64_ptrace_write_tpidr_only pass
11982 18:07:04.687991 arm64_ptrace pass
11983 18:07:04.690940 arm64_syscall-abi_getpid_FPSIMD pass
11984 18:07:04.694515 arm64_syscall-abi_sched_yield_FPSIMD pass
11985 18:07:04.697481 arm64_syscall-abi pass
11986 18:07:04.701158 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11987 18:07:04.704177 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11988 18:07:04.710957 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11989 18:07:04.714035 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11990 18:07:04.720589 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11991 18:07:04.721036 arm64_tpidr2 pass
11992 18:07:04.724241 + ../../utils/send-to-lava.sh ./output/result.txt
11993 18:07:04.730704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11994 18:07:04.731554 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11996 18:07:04.737210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11997 18:07:04.737887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11999 18:07:04.743956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12000 18:07:04.744710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12002 18:07:04.750417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12003 18:07:04.751099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12005 18:07:04.757505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12006 18:07:04.758180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12008 18:07:04.764091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12009 18:07:04.764834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12011 18:07:04.790115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12012 18:07:04.790786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12014 18:07:04.834269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12015 18:07:04.835085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12017 18:07:04.885546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12018 18:07:04.886166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12020 18:07:04.927931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12021 18:07:04.928678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12023 18:07:04.974690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12024 18:07:04.975370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12026 18:07:05.021536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12027 18:07:05.022217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12029 18:07:05.069316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12030 18:07:05.069997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12032 18:07:05.121016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12033 18:07:05.121696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12035 18:07:05.172375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12036 18:07:05.173119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12038 18:07:05.219773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12039 18:07:05.220048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12041 18:07:05.266290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12042 18:07:05.266975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12044 18:07:05.313907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12045 18:07:05.314167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12047 18:07:05.359992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12048 18:07:05.360662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12050 18:07:05.398004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12051 18:07:05.398710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12053 18:07:05.450701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12055 18:07:05.453392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12056 18:07:05.499651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12057 18:07:05.500603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12059 18:07:05.551902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12060 18:07:05.552607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12062 18:07:05.596946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12063 18:07:05.597630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12065 18:07:05.644366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12066 18:07:05.645097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12068 18:07:05.696319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12069 18:07:05.697043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12071 18:07:05.743010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12072 18:07:05.743705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12074 18:07:05.792582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12075 18:07:05.793266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12077 18:07:05.844358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12079 18:07:05.847207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12080 18:07:05.886192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12081 18:07:05.886454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12083 18:07:05.916558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12084 18:07:05.916843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12086 18:07:05.951965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12087 18:07:05.952221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12089 18:07:05.991721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12090 18:07:05.991992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12092 18:07:06.041010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12093 18:07:06.041289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12095 18:07:06.085413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12096 18:07:06.085870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12098 18:07:06.126783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12099 18:07:06.127063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12101 18:07:06.168529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12102 18:07:06.169256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12104 18:07:06.214746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12105 18:07:06.215435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12107 18:07:06.263821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12108 18:07:06.264523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12110 18:07:06.311865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12111 18:07:06.312584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12113 18:07:06.359581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12114 18:07:06.360263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12116 18:07:06.413919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12117 18:07:06.414607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12119 18:07:06.458779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12120 18:07:06.459044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12122 18:07:06.508303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12123 18:07:06.508829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12125 18:07:06.555374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12126 18:07:06.556151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12128 18:07:06.604245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12129 18:07:06.605252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12131 18:07:06.646236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12132 18:07:06.646645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12134 18:07:06.690753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12135 18:07:06.691497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12137 18:07:06.736755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12138 18:07:06.737462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12140 18:07:06.783564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12141 18:07:06.784107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12143 18:07:06.822730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12144 18:07:06.823005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12146 18:07:06.858404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12147 18:07:06.858668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12149 18:07:06.898959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12150 18:07:06.899644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12152 18:07:06.942201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12153 18:07:06.942925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12155 18:07:06.987312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12156 18:07:06.988077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12158 18:07:07.035813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12159 18:07:07.036649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12161 18:07:07.079159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12162 18:07:07.079428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12164 18:07:07.114575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12165 18:07:07.114832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12167 18:07:07.151439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12168 18:07:07.151710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12170 18:07:07.184915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12171 18:07:07.185283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12173 18:07:07.225991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12174 18:07:07.226668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12176 18:07:07.276410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12177 18:07:07.276672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12179 18:07:07.317421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12180 18:07:07.318100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12182 18:07:07.365531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12183 18:07:07.366217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12185 18:07:07.412239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12186 18:07:07.412515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12188 18:07:07.456930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12189 18:07:07.457614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12191 18:07:07.507573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12192 18:07:07.508373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12194 18:07:07.556541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12195 18:07:07.557243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12197 18:07:07.600857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12198 18:07:07.601538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12200 18:07:07.651007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12201 18:07:07.651696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12203 18:07:07.701006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12204 18:07:07.701277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12206 18:07:07.749711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12207 18:07:07.750396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12209 18:07:07.799784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12210 18:07:07.800468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12212 18:07:07.851242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12213 18:07:07.852044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12215 18:07:07.898156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12216 18:07:07.898433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12218 18:07:07.933194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12219 18:07:07.933459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12221 18:07:07.969367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12222 18:07:07.969709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12224 18:07:08.005405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12225 18:07:08.005672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12227 18:07:08.038363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12228 18:07:08.038637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12230 18:07:08.072655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12231 18:07:08.072914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12233 18:07:08.113851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12234 18:07:08.114131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12236 18:07:08.149738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12237 18:07:08.150047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12239 18:07:08.189179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12240 18:07:08.189445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12242 18:07:08.227999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12243 18:07:08.228266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12245 18:07:08.265246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12246 18:07:08.265514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12248 18:07:08.300132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12249 18:07:08.300388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12251 18:07:08.335195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12252 18:07:08.335467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12254 18:07:08.373785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12255 18:07:08.374042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12257 18:07:08.404983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12258 18:07:08.405249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12260 18:07:08.440078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12261 18:07:08.440355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12263 18:07:08.472353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12264 18:07:08.472649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12266 18:07:08.513318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12268 18:07:08.515977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12269 18:07:08.549019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12270 18:07:08.549311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12272 18:07:08.584680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12273 18:07:08.584940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12275 18:07:08.621929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12276 18:07:08.622199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12278 18:07:08.666421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12279 18:07:08.666712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12281 18:07:08.704739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12282 18:07:08.705020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12284 18:07:08.738509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12285 18:07:08.738769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12287 18:07:08.773835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12288 18:07:08.774087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12290 18:07:08.815061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12291 18:07:08.815321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12293 18:07:08.852481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12294 18:07:08.852774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12296 18:07:08.889011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12297 18:07:08.889273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12299 18:07:08.925987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12300 18:07:08.926239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12302 18:07:08.963824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12303 18:07:08.964130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12305 18:07:08.999774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12306 18:07:09.000028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12308 18:07:09.032272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12309 18:07:09.032529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12311 18:07:09.066274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12312 18:07:09.066538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12314 18:07:09.107046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12315 18:07:09.107319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12317 18:07:09.145118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12318 18:07:09.145378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12320 18:07:09.182021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12321 18:07:09.182284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12323 18:07:09.218995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12324 18:07:09.219253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12326 18:07:09.253121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12327 18:07:09.253378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12329 18:07:09.294141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12330 18:07:09.294407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12332 18:07:09.328464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12333 18:07:09.328746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12335 18:07:09.372300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12336 18:07:09.372564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12338 18:07:09.407317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12339 18:07:09.407574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12341 18:07:09.442878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12342 18:07:09.443141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12344 18:07:09.477200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12345 18:07:09.477460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12347 18:07:09.511820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12348 18:07:09.512089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12350 18:07:09.547486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12351 18:07:09.547743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12353 18:07:09.578972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12354 18:07:09.579230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12356 18:07:09.619273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12357 18:07:09.619544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12359 18:07:09.658098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12360 18:07:09.658355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12362 18:07:09.695943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12363 18:07:09.696200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12365 18:07:09.734420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12366 18:07:09.734690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12368 18:07:09.767102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12369 18:07:09.767357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12371 18:07:09.802167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12372 18:07:09.802456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12374 18:07:09.839414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12375 18:07:09.839702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12377 18:07:09.876911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12378 18:07:09.877167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12380 18:07:09.918388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12381 18:07:09.918655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12383 18:07:09.957457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12384 18:07:09.957711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12386 18:07:09.997606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12387 18:07:09.997866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12389 18:07:10.028257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12390 18:07:10.028544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12392 18:07:10.071237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12393 18:07:10.071516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12395 18:07:10.105372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12396 18:07:10.105677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12398 18:07:10.143962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12399 18:07:10.144265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12401 18:07:10.175549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12402 18:07:10.175830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12404 18:07:10.211610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12405 18:07:10.211909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12407 18:07:10.247121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12408 18:07:10.247412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12410 18:07:10.291183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12411 18:07:10.291466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12413 18:07:10.326040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12414 18:07:10.326334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12416 18:07:10.363086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12417 18:07:10.363371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12419 18:07:10.396653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12420 18:07:10.396936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12422 18:07:10.438194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12423 18:07:10.438505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12425 18:07:10.470871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12427 18:07:10.473736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12428 18:07:10.512455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12429 18:07:10.512774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12431 18:07:10.553701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12432 18:07:10.553962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12434 18:07:10.592859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12435 18:07:10.593140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12437 18:07:10.627600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12439 18:07:10.630330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12440 18:07:10.670156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12441 18:07:10.670451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12443 18:07:10.705801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12445 18:07:10.709491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12446 18:07:10.746871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12447 18:07:10.747172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12449 18:07:10.786396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12451 18:07:10.789199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12452 18:07:10.825589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12453 18:07:10.825855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12455 18:07:10.859226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12456 18:07:10.859516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12458 18:07:10.893843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12459 18:07:10.894130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12461 18:07:10.928854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12462 18:07:10.929115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12464 18:07:10.966699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12465 18:07:10.966988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12467 18:07:10.999512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12469 18:07:11.002713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12470 18:07:11.037684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12471 18:07:11.037966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12473 18:07:11.069293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12474 18:07:11.069572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12476 18:07:11.097709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12477 18:07:11.097989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12479 18:07:11.131338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12481 18:07:11.134712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12482 18:07:11.169435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12484 18:07:11.172207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12485 18:07:11.208794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12486 18:07:11.209097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12488 18:07:11.244041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12489 18:07:11.244327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12491 18:07:11.278888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12492 18:07:11.279174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12494 18:07:11.315127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12495 18:07:11.315389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12497 18:07:11.354605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12498 18:07:11.354885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12500 18:07:11.384767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12501 18:07:11.385036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12503 18:07:11.419882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12504 18:07:11.420169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12506 18:07:11.454191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12507 18:07:11.454482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12509 18:07:11.489203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12510 18:07:11.489500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12512 18:07:11.524261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12513 18:07:11.524543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12515 18:07:11.553093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12516 18:07:11.553350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12518 18:07:11.587223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12519 18:07:11.587513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12521 18:07:11.624141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12522 18:07:11.624436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12524 18:07:11.660639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12525 18:07:11.660920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12527 18:07:11.689578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12528 18:07:11.689688 + set +x
12529 18:07:11.689956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12531 18:07:11.696432 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14291400_1.6.2.3.5>
12532 18:07:11.696705 Received signal: <ENDRUN> 1_kselftest-arm64 14291400_1.6.2.3.5
12533 18:07:11.696814 Ending use of test pattern.
12534 18:07:11.696907 Ending test lava.1_kselftest-arm64 (14291400_1.6.2.3.5), duration 29.50
12536 18:07:11.699530 <LAVA_TEST_RUNNER EXIT>
12537 18:07:11.699802 ok: lava_test_shell seems to have completed
12538 18:07:11.701478 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12539 18:07:11.701644 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12540 18:07:11.701763 end: 3 lava-test-retry (duration 00:00:30) [common]
12541 18:07:11.701888 start: 4 finalize (timeout 00:07:33) [common]
12542 18:07:11.702010 start: 4.1 power-off (timeout 00:00:30) [common]
12543 18:07:11.702306 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
12544 18:07:11.899760 >> Command sent successfully.
12545 18:07:11.902117 Returned 0 in 0 seconds
12546 18:07:12.002488 end: 4.1 power-off (duration 00:00:00) [common]
12548 18:07:12.002892 start: 4.2 read-feedback (timeout 00:07:32) [common]
12549 18:07:12.003189 Listened to connection for namespace 'common' for up to 1s
12550 18:07:13.004147 Finalising connection for namespace 'common'
12551 18:07:13.004318 Disconnecting from shell: Finalise
12552 18:07:13.004435 / #
12553 18:07:13.104754 end: 4.2 read-feedback (duration 00:00:01) [common]
12554 18:07:13.104917 end: 4 finalize (duration 00:00:01) [common]
12555 18:07:13.105039 Cleaning after the job
12556 18:07:13.105148 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/ramdisk
12557 18:07:13.107289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/kernel
12558 18:07:13.117938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/dtb
12559 18:07:13.118159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/nfsrootfs
12560 18:07:13.180984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291400/tftp-deploy-hd_dbfq_/modules
12561 18:07:13.186447 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291400
12562 18:07:13.725795 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291400
12563 18:07:13.725981 Job finished correctly