Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 18:13:02.325121 lava-dispatcher, installed at version: 2024.03
2 18:13:02.325315 start: 0 validate
3 18:13:02.325452 Start time: 2024-06-11 18:13:02.325445+00:00 (UTC)
4 18:13:02.325576 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:13:02.325711 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:13:02.600375 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:13:02.600654 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:13:02.867092 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:13:02.867759 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:13:03.137757 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:13:03.138365 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:13:03.407030 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:13:03.407208 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:13:03.681189 validate duration: 1.36
16 18:13:03.682560 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:13:03.683153 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:13:03.683648 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:13:03.684302 Not decompressing ramdisk as can be used compressed.
20 18:13:03.684842 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:13:03.685236 saving as /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/ramdisk/initrd.cpio.gz
22 18:13:03.685599 total size: 5628169 (5 MB)
23 18:13:03.691142 progress 0 % (0 MB)
24 18:13:03.699684 progress 5 % (0 MB)
25 18:13:03.705107 progress 10 % (0 MB)
26 18:13:03.708967 progress 15 % (0 MB)
27 18:13:03.712681 progress 20 % (1 MB)
28 18:13:03.715475 progress 25 % (1 MB)
29 18:13:03.718437 progress 30 % (1 MB)
30 18:13:03.721051 progress 35 % (1 MB)
31 18:13:03.723263 progress 40 % (2 MB)
32 18:13:03.725586 progress 45 % (2 MB)
33 18:13:03.727607 progress 50 % (2 MB)
34 18:13:03.729561 progress 55 % (2 MB)
35 18:13:03.731504 progress 60 % (3 MB)
36 18:13:03.733191 progress 65 % (3 MB)
37 18:13:03.734966 progress 70 % (3 MB)
38 18:13:03.736474 progress 75 % (4 MB)
39 18:13:03.738024 progress 80 % (4 MB)
40 18:13:03.739408 progress 85 % (4 MB)
41 18:13:03.741024 progress 90 % (4 MB)
42 18:13:03.742565 progress 95 % (5 MB)
43 18:13:03.743961 progress 100 % (5 MB)
44 18:13:03.744173 5 MB downloaded in 0.06 s (91.61 MB/s)
45 18:13:03.744333 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:13:03.744635 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:13:03.744721 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:13:03.744813 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:13:03.744950 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:13:03.745030 saving as /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/kernel/Image
52 18:13:03.745091 total size: 54813184 (52 MB)
53 18:13:03.745152 No compression specified
54 18:13:03.746235 progress 0 % (0 MB)
55 18:13:03.760473 progress 5 % (2 MB)
56 18:13:03.775135 progress 10 % (5 MB)
57 18:13:03.790371 progress 15 % (7 MB)
58 18:13:03.805389 progress 20 % (10 MB)
59 18:13:03.819979 progress 25 % (13 MB)
60 18:13:03.834490 progress 30 % (15 MB)
61 18:13:03.849316 progress 35 % (18 MB)
62 18:13:03.864715 progress 40 % (20 MB)
63 18:13:03.879853 progress 45 % (23 MB)
64 18:13:03.895510 progress 50 % (26 MB)
65 18:13:03.910750 progress 55 % (28 MB)
66 18:13:03.925575 progress 60 % (31 MB)
67 18:13:03.940569 progress 65 % (34 MB)
68 18:13:03.955094 progress 70 % (36 MB)
69 18:13:03.969792 progress 75 % (39 MB)
70 18:13:03.984213 progress 80 % (41 MB)
71 18:13:03.998467 progress 85 % (44 MB)
72 18:13:04.012942 progress 90 % (47 MB)
73 18:13:04.027312 progress 95 % (49 MB)
74 18:13:04.041328 progress 100 % (52 MB)
75 18:13:04.041592 52 MB downloaded in 0.30 s (176.31 MB/s)
76 18:13:04.041755 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:13:04.041993 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:13:04.042078 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:13:04.042167 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:13:04.042307 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:13:04.042375 saving as /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/dtb/mt8192-asurada-spherion-r0.dtb
83 18:13:04.042443 total size: 47258 (0 MB)
84 18:13:04.042504 No compression specified
85 18:13:04.043617 progress 69 % (0 MB)
86 18:13:04.043889 progress 100 % (0 MB)
87 18:13:04.044041 0 MB downloaded in 0.00 s (28.25 MB/s)
88 18:13:04.044168 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:13:04.044446 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:13:04.044531 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:13:04.044621 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:13:04.044733 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:13:04.044806 saving as /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/nfsrootfs/full.rootfs.tar
95 18:13:04.044868 total size: 120894716 (115 MB)
96 18:13:04.044928 Using unxz to decompress xz
97 18:13:04.049229 progress 0 % (0 MB)
98 18:13:04.411565 progress 5 % (5 MB)
99 18:13:04.780118 progress 10 % (11 MB)
100 18:13:05.142144 progress 15 % (17 MB)
101 18:13:05.497515 progress 20 % (23 MB)
102 18:13:05.800534 progress 25 % (28 MB)
103 18:13:06.176479 progress 30 % (34 MB)
104 18:13:06.522252 progress 35 % (40 MB)
105 18:13:06.691857 progress 40 % (46 MB)
106 18:13:06.872663 progress 45 % (51 MB)
107 18:13:07.193229 progress 50 % (57 MB)
108 18:13:07.581620 progress 55 % (63 MB)
109 18:13:07.947315 progress 60 % (69 MB)
110 18:13:08.303379 progress 65 % (74 MB)
111 18:13:08.658268 progress 70 % (80 MB)
112 18:13:09.041642 progress 75 % (86 MB)
113 18:13:09.399242 progress 80 % (92 MB)
114 18:13:09.754133 progress 85 % (98 MB)
115 18:13:10.120860 progress 90 % (103 MB)
116 18:13:10.462994 progress 95 % (109 MB)
117 18:13:10.827653 progress 100 % (115 MB)
118 18:13:10.833298 115 MB downloaded in 6.79 s (16.98 MB/s)
119 18:13:10.833653 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:13:10.834069 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:13:10.834202 start: 1.5 download-retry (timeout 00:09:53) [common]
123 18:13:10.834335 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 18:13:10.834541 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:13:10.834652 saving as /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/modules/modules.tar
126 18:13:10.834746 total size: 8618176 (8 MB)
127 18:13:10.834847 Using unxz to decompress xz
128 18:13:10.839712 progress 0 % (0 MB)
129 18:13:10.858957 progress 5 % (0 MB)
130 18:13:10.886321 progress 10 % (0 MB)
131 18:13:10.916366 progress 15 % (1 MB)
132 18:13:10.944572 progress 20 % (1 MB)
133 18:13:10.969043 progress 25 % (2 MB)
134 18:13:10.993557 progress 30 % (2 MB)
135 18:13:11.020691 progress 35 % (2 MB)
136 18:13:11.046165 progress 40 % (3 MB)
137 18:13:11.070751 progress 45 % (3 MB)
138 18:13:11.095597 progress 50 % (4 MB)
139 18:13:11.121195 progress 55 % (4 MB)
140 18:13:11.147564 progress 60 % (4 MB)
141 18:13:11.173417 progress 65 % (5 MB)
142 18:13:11.202065 progress 70 % (5 MB)
143 18:13:11.227700 progress 75 % (6 MB)
144 18:13:11.254623 progress 80 % (6 MB)
145 18:13:11.279655 progress 85 % (7 MB)
146 18:13:11.305397 progress 90 % (7 MB)
147 18:13:11.333992 progress 95 % (7 MB)
148 18:13:11.363536 progress 100 % (8 MB)
149 18:13:11.367916 8 MB downloaded in 0.53 s (15.42 MB/s)
150 18:13:11.368229 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:13:11.368575 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:13:11.368677 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:13:11.368773 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:13:15.164571 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg
156 18:13:15.164823 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:13:15.164969 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 18:13:15.171473 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej
159 18:13:15.171676 makedir: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin
160 18:13:15.171802 makedir: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/tests
161 18:13:15.171962 makedir: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/results
162 18:13:15.172122 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-add-keys
163 18:13:15.172347 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-add-sources
164 18:13:15.172591 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-background-process-start
165 18:13:15.172809 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-background-process-stop
166 18:13:15.173011 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-common-functions
167 18:13:15.173205 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-echo-ipv4
168 18:13:15.173404 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-install-packages
169 18:13:15.173601 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-installed-packages
170 18:13:15.173756 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-os-build
171 18:13:15.173886 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-probe-channel
172 18:13:15.174015 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-probe-ip
173 18:13:15.174144 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-target-ip
174 18:13:15.174268 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-target-mac
175 18:13:15.174392 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-target-storage
176 18:13:15.174518 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-case
177 18:13:15.174642 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-event
178 18:13:15.174766 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-feedback
179 18:13:15.174891 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-raise
180 18:13:15.175019 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-reference
181 18:13:15.175145 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-runner
182 18:13:15.175270 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-set
183 18:13:15.175396 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-test-shell
184 18:13:15.175522 Updating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-add-keys (debian)
185 18:13:15.175674 Updating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-add-sources (debian)
186 18:13:15.175813 Updating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-install-packages (debian)
187 18:13:15.175949 Updating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-installed-packages (debian)
188 18:13:15.176085 Updating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/bin/lava-os-build (debian)
189 18:13:15.176213 Creating /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/environment
190 18:13:15.176321 LAVA metadata
191 18:13:15.176580 - LAVA_JOB_ID=14291475
192 18:13:15.176669 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:13:15.176789 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 18:13:15.176860 skipped lava-vland-overlay
195 18:13:15.176939 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:13:15.177020 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 18:13:15.177082 skipped lava-multinode-overlay
198 18:13:15.177154 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:13:15.177232 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 18:13:15.177308 Loading test definitions
201 18:13:15.177412 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 18:13:15.177486 Using /lava-14291475 at stage 0
203 18:13:15.177777 uuid=14291475_1.6.2.3.1 testdef=None
204 18:13:15.177866 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:13:15.177950 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 18:13:15.178403 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:13:15.178622 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 18:13:15.179175 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:13:15.179405 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 18:13:15.179934 runner path: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/0/tests/0_timesync-off test_uuid 14291475_1.6.2.3.1
213 18:13:15.180092 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:13:15.180320 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 18:13:15.180434 Using /lava-14291475 at stage 0
217 18:13:15.180539 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:13:15.180629 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/0/tests/1_kselftest-dt'
219 18:13:17.148807 Running '/usr/bin/git checkout kernelci.org
220 18:13:17.265453 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 18:13:17.266244 uuid=14291475_1.6.2.3.5 testdef=None
222 18:13:17.266412 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:13:17.266668 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 18:13:17.267423 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:13:17.267658 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 18:13:17.268669 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:13:17.268915 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 18:13:17.269862 runner path: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/0/tests/1_kselftest-dt test_uuid 14291475_1.6.2.3.5
232 18:13:17.269956 BOARD='mt8192-asurada-spherion-r0'
233 18:13:17.270022 BRANCH='cip'
234 18:13:17.270083 SKIPFILE='/dev/null'
235 18:13:17.270143 SKIP_INSTALL='True'
236 18:13:17.270201 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:13:17.270261 TST_CASENAME=''
238 18:13:17.270318 TST_CMDFILES='dt'
239 18:13:17.270463 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:13:17.270677 Creating lava-test-runner.conf files
242 18:13:17.270742 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291475/lava-overlay-yagkvdej/lava-14291475/0 for stage 0
243 18:13:17.270835 - 0_timesync-off
244 18:13:17.270905 - 1_kselftest-dt
245 18:13:17.271003 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:13:17.271090 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 18:13:25.090757 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:13:25.090911 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 18:13:25.091009 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:13:25.091109 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:13:25.091202 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 18:13:25.265796 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:13:25.266234 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 18:13:25.266432 extracting modules file /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg
255 18:13:25.497580 extracting modules file /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291475/extract-overlay-ramdisk-m34m6boi/ramdisk
256 18:13:25.723763 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:13:25.723923 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 18:13:25.724022 [common] Applying overlay to NFS
259 18:13:25.724096 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291475/compress-overlay-22zokstn/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg
260 18:13:26.667136 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:13:26.667299 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 18:13:26.667389 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:13:26.667479 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 18:13:26.667562 Building ramdisk /var/lib/lava/dispatcher/tmp/14291475/extract-overlay-ramdisk-m34m6boi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291475/extract-overlay-ramdisk-m34m6boi/ramdisk
265 18:13:26.991385 >> 130400 blocks
266 18:13:29.058823 rename /var/lib/lava/dispatcher/tmp/14291475/extract-overlay-ramdisk-m34m6boi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/ramdisk/ramdisk.cpio.gz
267 18:13:29.059463 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 18:13:29.059637 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 18:13:29.059783 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 18:13:29.059993 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/kernel/Image']
271 18:13:44.200378 Returned 0 in 15 seconds
272 18:13:44.301016 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/kernel/image.itb
273 18:13:44.652616 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:13:44.652995 output: Created: Tue Jun 11 19:13:44 2024
275 18:13:44.653083 output: Image 0 (kernel-1)
276 18:13:44.653230 output: Description:
277 18:13:44.653302 output: Created: Tue Jun 11 19:13:44 2024
278 18:13:44.653366 output: Type: Kernel Image
279 18:13:44.653428 output: Compression: lzma compressed
280 18:13:44.653487 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:13:44.653544 output: Architecture: AArch64
282 18:13:44.653602 output: OS: Linux
283 18:13:44.653657 output: Load Address: 0x00000000
284 18:13:44.653712 output: Entry Point: 0x00000000
285 18:13:44.653765 output: Hash algo: crc32
286 18:13:44.653820 output: Hash value: 7a9e9d3e
287 18:13:44.653874 output: Image 1 (fdt-1)
288 18:13:44.653926 output: Description: mt8192-asurada-spherion-r0
289 18:13:44.653979 output: Created: Tue Jun 11 19:13:44 2024
290 18:13:44.654032 output: Type: Flat Device Tree
291 18:13:44.654085 output: Compression: uncompressed
292 18:13:44.654171 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 18:13:44.654229 output: Architecture: AArch64
294 18:13:44.654282 output: Hash algo: crc32
295 18:13:44.654336 output: Hash value: 0f8e4d2e
296 18:13:44.654388 output: Image 2 (ramdisk-1)
297 18:13:44.654441 output: Description: unavailable
298 18:13:44.654493 output: Created: Tue Jun 11 19:13:44 2024
299 18:13:44.654546 output: Type: RAMDisk Image
300 18:13:44.654599 output: Compression: Unknown Compression
301 18:13:44.654651 output: Data Size: 18737083 Bytes = 18297.93 KiB = 17.87 MiB
302 18:13:44.654704 output: Architecture: AArch64
303 18:13:44.654757 output: OS: Linux
304 18:13:44.654808 output: Load Address: unavailable
305 18:13:44.654860 output: Entry Point: unavailable
306 18:13:44.654912 output: Hash algo: crc32
307 18:13:44.654964 output: Hash value: 913189ff
308 18:13:44.655015 output: Default Configuration: 'conf-1'
309 18:13:44.655121 output: Configuration 0 (conf-1)
310 18:13:44.655177 output: Description: mt8192-asurada-spherion-r0
311 18:13:44.655229 output: Kernel: kernel-1
312 18:13:44.655282 output: Init Ramdisk: ramdisk-1
313 18:13:44.655334 output: FDT: fdt-1
314 18:13:44.655385 output: Loadables: kernel-1
315 18:13:44.655468 output:
316 18:13:44.655692 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 18:13:44.655813 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 18:13:44.655924 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 18:13:44.656019 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 18:13:44.656099 No LXC device requested
321 18:13:44.656177 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:13:44.656264 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 18:13:44.656370 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:13:44.656480 Checking files for TFTP limit of 4294967296 bytes.
325 18:13:44.656998 end: 1 tftp-deploy (duration 00:00:41) [common]
326 18:13:44.657168 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:13:44.657342 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:13:44.657502 substitutions:
329 18:13:44.657577 - {DTB}: 14291475/tftp-deploy-mf64n40c/dtb/mt8192-asurada-spherion-r0.dtb
330 18:13:44.657716 - {INITRD}: 14291475/tftp-deploy-mf64n40c/ramdisk/ramdisk.cpio.gz
331 18:13:44.657846 - {KERNEL}: 14291475/tftp-deploy-mf64n40c/kernel/Image
332 18:13:44.657943 - {LAVA_MAC}: None
333 18:13:44.658044 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg
334 18:13:44.658140 - {NFS_SERVER_IP}: 192.168.201.1
335 18:13:44.658264 - {PRESEED_CONFIG}: None
336 18:13:44.658359 - {PRESEED_LOCAL}: None
337 18:13:44.658454 - {RAMDISK}: 14291475/tftp-deploy-mf64n40c/ramdisk/ramdisk.cpio.gz
338 18:13:44.658580 - {ROOT_PART}: None
339 18:13:44.658674 - {ROOT}: None
340 18:13:44.658798 - {SERVER_IP}: 192.168.201.1
341 18:13:44.658892 - {TEE}: None
342 18:13:44.658985 Parsed boot commands:
343 18:13:44.659077 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:13:44.659322 Parsed boot commands: tftpboot 192.168.201.1 14291475/tftp-deploy-mf64n40c/kernel/image.itb 14291475/tftp-deploy-mf64n40c/kernel/cmdline
345 18:13:44.659449 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:13:44.659569 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:13:44.659694 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:13:44.659813 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:13:44.659915 Not connected, no need to disconnect.
350 18:13:44.660019 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:13:44.660131 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:13:44.660225 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 18:13:44.664588 Setting prompt string to ['lava-test: # ']
354 18:13:44.665200 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:13:44.665415 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:13:44.665569 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:13:44.665736 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:13:44.666101 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 18:13:49.801081 >> Command sent successfully.
360 18:13:49.803547 Returned 0 in 5 seconds
361 18:13:49.903937 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 18:13:49.904263 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 18:13:49.904373 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 18:13:49.904463 Setting prompt string to 'Starting depthcharge on Spherion...'
366 18:13:49.904534 Changing prompt to 'Starting depthcharge on Spherion...'
367 18:13:49.904605 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 18:13:49.904998 [Enter `^Ec?' for help]
369 18:13:50.077832
370 18:13:50.077975
371 18:13:50.078050 F0: 102B 0000
372 18:13:50.078139
373 18:13:50.078235 F3: 1001 0000 [0200]
374 18:13:50.078325
375 18:13:50.081748 F3: 1001 0000
376 18:13:50.081863
377 18:13:50.081957 F7: 102D 0000
378 18:13:50.082060
379 18:13:50.082159 F1: 0000 0000
380 18:13:50.082248
381 18:13:50.084835 V0: 0000 0000 [0001]
382 18:13:50.084912
383 18:13:50.084997 00: 0007 8000
384 18:13:50.085075
385 18:13:50.088629 01: 0000 0000
386 18:13:50.088732
387 18:13:50.088803 BP: 0C00 0209 [0000]
388 18:13:50.088866
389 18:13:50.088931 G0: 1182 0000
390 18:13:50.089033
391 18:13:50.092448 EC: 0000 0021 [4000]
392 18:13:50.092533
393 18:13:50.096241 S7: 0000 0000 [0000]
394 18:13:50.096355
395 18:13:50.096423 CC: 0000 0000 [0001]
396 18:13:50.096484
397 18:13:50.099251 T0: 0000 0040 [010F]
398 18:13:50.099343
399 18:13:50.099462 Jump to BL
400 18:13:50.099560
401 18:13:50.124295
402 18:13:50.124457
403 18:13:50.131785 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 18:13:50.135608 ARM64: Exception handlers installed.
405 18:13:50.138871 ARM64: Testing exception
406 18:13:50.142746 ARM64: Done test exception
407 18:13:50.150685 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 18:13:50.157159 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 18:13:50.164668 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 18:13:50.174755 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 18:13:50.181484 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 18:13:50.191836 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 18:13:50.202124 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 18:13:50.208952 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 18:13:50.226606 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 18:13:50.230072 WDT: Last reset was cold boot
417 18:13:50.233647 SPI1(PAD0) initialized at 2873684 Hz
418 18:13:50.237151 SPI5(PAD0) initialized at 992727 Hz
419 18:13:50.240138 VBOOT: Loading verstage.
420 18:13:50.246950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 18:13:50.250666 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 18:13:50.253429 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 18:13:50.256988 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 18:13:50.264446 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 18:13:50.270863 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 18:13:50.282224 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 18:13:50.282331
428 18:13:50.282402
429 18:13:50.292587 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 18:13:50.295659 ARM64: Exception handlers installed.
431 18:13:50.299206 ARM64: Testing exception
432 18:13:50.299291 ARM64: Done test exception
433 18:13:50.305930 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 18:13:50.309460 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 18:13:50.322819 Probing TPM: . done!
436 18:13:50.322918 TPM ready after 0 ms
437 18:13:50.330271 Connected to device vid:did:rid of 1ae0:0028:00
438 18:13:50.336733 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 18:13:50.395339 Initialized TPM device CR50 revision 0
440 18:13:50.407619 tlcl_send_startup: Startup return code is 0
441 18:13:50.407758 TPM: setup succeeded
442 18:13:50.419036 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 18:13:50.427870 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 18:13:50.439931 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 18:13:50.449332 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 18:13:50.452857 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 18:13:50.456962 in-header: 03 07 00 00 08 00 00 00
448 18:13:50.460740 in-data: aa e4 47 04 13 02 00 00
449 18:13:50.460842 Chrome EC: UHEPI supported
450 18:13:50.467990 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 18:13:50.471707 in-header: 03 95 00 00 08 00 00 00
452 18:13:50.475674 in-data: 18 20 20 08 00 00 00 00
453 18:13:50.475765 Phase 1
454 18:13:50.479032 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 18:13:50.486485 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 18:13:50.493354 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 18:13:50.493494 Recovery requested (1009000e)
458 18:13:50.506584 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 18:13:50.510407 tlcl_extend: response is 0
460 18:13:50.519303 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 18:13:50.524711 tlcl_extend: response is 0
462 18:13:50.531378 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 18:13:50.551745 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 18:13:50.558357 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 18:13:50.558460
466 18:13:50.558530
467 18:13:50.568132 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 18:13:50.571559 ARM64: Exception handlers installed.
469 18:13:50.575275 ARM64: Testing exception
470 18:13:50.575360 ARM64: Done test exception
471 18:13:50.597028 pmic_efuse_setting: Set efuses in 11 msecs
472 18:13:50.600574 pmwrap_interface_init: Select PMIF_VLD_RDY
473 18:13:50.607430 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 18:13:50.610093 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 18:13:50.617784 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 18:13:50.621321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 18:13:50.625086 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 18:13:50.632003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 18:13:50.635656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 18:13:50.639419 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 18:13:50.643138 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 18:13:50.741628 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 18:13:50.742327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 18:13:50.742841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 18:13:50.743498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 18:13:50.744087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 18:13:50.744736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 18:13:50.745596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 18:13:50.746160 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 18:13:50.746898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 18:13:50.747663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 18:13:50.748415 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 18:13:50.749315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 18:13:50.750051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 18:13:50.750596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 18:13:50.751355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 18:13:50.751703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 18:13:50.752086 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 18:13:50.752713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 18:13:50.753137 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 18:13:50.753527 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 18:13:50.757660 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 18:13:50.761825 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 18:13:50.765372 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 18:13:50.772242 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 18:13:50.776007 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 18:13:50.779702 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 18:13:50.788563 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 18:13:50.791192 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 18:13:50.794631 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 18:13:50.804349 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 18:13:50.806154 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 18:13:50.809103 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 18:13:50.813015 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 18:13:50.817107 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 18:13:50.824329 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 18:13:50.828070 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 18:13:50.831688 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 18:13:50.835370 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 18:13:50.839261 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 18:13:50.842915 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 18:13:50.846671 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 18:13:50.853426 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 18:13:50.861370 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 18:13:50.868841 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 18:13:50.872411 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 18:13:50.879729 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 18:13:50.890813 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 18:13:50.894175 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 18:13:50.897714 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 18:13:50.901426 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 18:13:50.910666 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xd
533 18:13:50.914172 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 18:13:50.919194 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 18:13:50.925693 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 18:13:50.934657 [RTC]rtc_get_frequency_meter,154: input=15, output=759
537 18:13:50.943800 [RTC]rtc_get_frequency_meter,154: input=23, output=941
538 18:13:50.954139 [RTC]rtc_get_frequency_meter,154: input=19, output=851
539 18:13:50.962866 [RTC]rtc_get_frequency_meter,154: input=17, output=804
540 18:13:50.972636 [RTC]rtc_get_frequency_meter,154: input=16, output=782
541 18:13:50.982359 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 18:13:50.992134 [RTC]rtc_get_frequency_meter,154: input=17, output=804
543 18:13:50.995868 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 18:13:50.999446 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 18:13:51.003514 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 18:13:51.011125 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 18:13:51.014775 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 18:13:51.018518 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 18:13:51.022290 ADC[4]: Raw value=905834 ID=7
550 18:13:51.022471 ADC[3]: Raw value=213441 ID=1
551 18:13:51.025692 RAM Code: 0x71
552 18:13:51.029799 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 18:13:51.032953 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 18:13:51.044913 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 18:13:51.047867 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 18:13:51.052203 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 18:13:51.055796 in-header: 03 07 00 00 08 00 00 00
558 18:13:51.059182 in-data: aa e4 47 04 13 02 00 00
559 18:13:51.064138 Chrome EC: UHEPI supported
560 18:13:51.066606 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 18:13:51.070457 in-header: 03 95 00 00 08 00 00 00
562 18:13:51.074665 in-data: 18 20 20 08 00 00 00 00
563 18:13:51.078351 MRC: failed to locate region type 0.
564 18:13:51.085495 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 18:13:51.089691 DRAM-K: Running full calibration
566 18:13:51.093088 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 18:13:51.096810 header.status = 0x0
568 18:13:51.100968 header.version = 0x6 (expected: 0x6)
569 18:13:51.104156 header.size = 0xd00 (expected: 0xd00)
570 18:13:51.104271 header.flags = 0x0
571 18:13:51.111458 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 18:13:51.129157 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 18:13:51.136543 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 18:13:51.136650 dram_init: ddr_geometry: 2
575 18:13:51.140079 [EMI] MDL number = 2
576 18:13:51.143738 [EMI] Get MDL freq = 0
577 18:13:51.143822 dram_init: ddr_type: 0
578 18:13:51.147668 is_discrete_lpddr4: 1
579 18:13:51.147755 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 18:13:51.151079
581 18:13:51.151163
582 18:13:51.151235 [Bian_co] ETT version 0.0.0.1
583 18:13:51.159074 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 18:13:51.159164
585 18:13:51.162617 dramc_set_vcore_voltage set vcore to 650000
586 18:13:51.162703 Read voltage for 800, 4
587 18:13:51.162770 Vio18 = 0
588 18:13:51.166374 Vcore = 650000
589 18:13:51.166464 Vdram = 0
590 18:13:51.166540 Vddq = 0
591 18:13:51.166604 Vmddr = 0
592 18:13:51.170705 dram_init: config_dvfs: 1
593 18:13:51.173645 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 18:13:51.181396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 18:13:51.185132 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 18:13:51.188813 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 18:13:51.192324 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 18:13:51.195955 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 18:13:51.198722 MEM_TYPE=3, freq_sel=18
600 18:13:51.202136 sv_algorithm_assistance_LP4_1600
601 18:13:51.205779 ============ PULL DRAM RESETB DOWN ============
602 18:13:51.208725 ========== PULL DRAM RESETB DOWN end =========
603 18:13:51.213066 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 18:13:51.215992 ===================================
605 18:13:51.219634 LPDDR4 DRAM CONFIGURATION
606 18:13:51.223091 ===================================
607 18:13:51.227289 EX_ROW_EN[0] = 0x0
608 18:13:51.227400 EX_ROW_EN[1] = 0x0
609 18:13:51.230761 LP4Y_EN = 0x0
610 18:13:51.230846 WORK_FSP = 0x0
611 18:13:51.230912 WL = 0x2
612 18:13:51.234305 RL = 0x2
613 18:13:51.234427 BL = 0x2
614 18:13:51.238232 RPST = 0x0
615 18:13:51.238340 RD_PRE = 0x0
616 18:13:51.240949 WR_PRE = 0x1
617 18:13:51.241039 WR_PST = 0x0
618 18:13:51.244572 DBI_WR = 0x0
619 18:13:51.247406 DBI_RD = 0x0
620 18:13:51.247520 OTF = 0x1
621 18:13:51.251238 ===================================
622 18:13:51.254050 ===================================
623 18:13:51.254178 ANA top config
624 18:13:51.257872 ===================================
625 18:13:51.261952 DLL_ASYNC_EN = 0
626 18:13:51.265454 ALL_SLAVE_EN = 1
627 18:13:51.265587 NEW_RANK_MODE = 1
628 18:13:51.268899 DLL_IDLE_MODE = 1
629 18:13:51.272087 LP45_APHY_COMB_EN = 1
630 18:13:51.275518 TX_ODT_DIS = 1
631 18:13:51.278513 NEW_8X_MODE = 1
632 18:13:51.282228 ===================================
633 18:13:51.282315 ===================================
634 18:13:51.285897 data_rate = 1600
635 18:13:51.289513 CKR = 1
636 18:13:51.292446 DQ_P2S_RATIO = 8
637 18:13:51.296058 ===================================
638 18:13:51.299032 CA_P2S_RATIO = 8
639 18:13:51.299121 DQ_CA_OPEN = 0
640 18:13:51.302466 DQ_SEMI_OPEN = 0
641 18:13:51.306027 CA_SEMI_OPEN = 0
642 18:13:51.309515 CA_FULL_RATE = 0
643 18:13:51.312487 DQ_CKDIV4_EN = 1
644 18:13:51.316120 CA_CKDIV4_EN = 1
645 18:13:51.316205 CA_PREDIV_EN = 0
646 18:13:51.319796 PH8_DLY = 0
647 18:13:51.322778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 18:13:51.326426 DQ_AAMCK_DIV = 4
649 18:13:51.329256 CA_AAMCK_DIV = 4
650 18:13:51.332834 CA_ADMCK_DIV = 4
651 18:13:51.332919 DQ_TRACK_CA_EN = 0
652 18:13:51.336288 CA_PICK = 800
653 18:13:51.339797 CA_MCKIO = 800
654 18:13:51.343286 MCKIO_SEMI = 0
655 18:13:51.346388 PLL_FREQ = 3068
656 18:13:51.350053 DQ_UI_PI_RATIO = 32
657 18:13:51.350137 CA_UI_PI_RATIO = 0
658 18:13:51.353537 ===================================
659 18:13:51.357371 ===================================
660 18:13:51.361083 memory_type:LPDDR4
661 18:13:51.361189 GP_NUM : 10
662 18:13:51.365479 SRAM_EN : 1
663 18:13:51.365563 MD32_EN : 0
664 18:13:51.369055 ===================================
665 18:13:51.372843 [ANA_INIT] >>>>>>>>>>>>>>
666 18:13:51.376653 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 18:13:51.380144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 18:13:51.380233 ===================================
669 18:13:51.383468 data_rate = 1600,PCW = 0X7600
670 18:13:51.386750 ===================================
671 18:13:51.390084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 18:13:51.396891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 18:13:51.403176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 18:13:51.406649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 18:13:51.409683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 18:13:51.413146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 18:13:51.416694 [ANA_INIT] flow start
678 18:13:51.416788 [ANA_INIT] PLL >>>>>>>>
679 18:13:51.420016 [ANA_INIT] PLL <<<<<<<<
680 18:13:51.423417 [ANA_INIT] MIDPI >>>>>>>>
681 18:13:51.426438 [ANA_INIT] MIDPI <<<<<<<<
682 18:13:51.426521 [ANA_INIT] DLL >>>>>>>>
683 18:13:51.430184 [ANA_INIT] flow end
684 18:13:51.433055 ============ LP4 DIFF to SE enter ============
685 18:13:51.436855 ============ LP4 DIFF to SE exit ============
686 18:13:51.439663 [ANA_INIT] <<<<<<<<<<<<<
687 18:13:51.443284 [Flow] Enable top DCM control >>>>>
688 18:13:51.446385 [Flow] Enable top DCM control <<<<<
689 18:13:51.450112 Enable DLL master slave shuffle
690 18:13:51.453045 ==============================================================
691 18:13:51.456769 Gating Mode config
692 18:13:51.463245 ==============================================================
693 18:13:51.463330 Config description:
694 18:13:51.473383 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 18:13:51.479902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 18:13:51.486540 SELPH_MODE 0: By rank 1: By Phase
697 18:13:51.490073 ==============================================================
698 18:13:51.493482 GAT_TRACK_EN = 1
699 18:13:51.496279 RX_GATING_MODE = 2
700 18:13:51.499721 RX_GATING_TRACK_MODE = 2
701 18:13:51.503240 SELPH_MODE = 1
702 18:13:51.506350 PICG_EARLY_EN = 1
703 18:13:51.509792 VALID_LAT_VALUE = 1
704 18:13:51.513267 ==============================================================
705 18:13:51.516279 Enter into Gating configuration >>>>
706 18:13:51.519778 Exit from Gating configuration <<<<
707 18:13:51.523218 Enter into DVFS_PRE_config >>>>>
708 18:13:51.536621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 18:13:51.536725 Exit from DVFS_PRE_config <<<<<
710 18:13:51.539584 Enter into PICG configuration >>>>
711 18:13:51.543246 Exit from PICG configuration <<<<
712 18:13:51.546360 [RX_INPUT] configuration >>>>>
713 18:13:51.549630 [RX_INPUT] configuration <<<<<
714 18:13:51.556532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 18:13:51.559719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 18:13:51.566122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 18:13:51.573334 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 18:13:51.579700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 18:13:51.586205 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 18:13:51.589888 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 18:13:51.592922 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 18:13:51.596491 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 18:13:51.602791 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 18:13:51.606297 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 18:13:51.609393 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 18:13:51.612850 ===================================
727 18:13:51.616548 LPDDR4 DRAM CONFIGURATION
728 18:13:51.619598 ===================================
729 18:13:51.619705 EX_ROW_EN[0] = 0x0
730 18:13:51.623195 EX_ROW_EN[1] = 0x0
731 18:13:51.626512 LP4Y_EN = 0x0
732 18:13:51.626607 WORK_FSP = 0x0
733 18:13:51.629735 WL = 0x2
734 18:13:51.629852 RL = 0x2
735 18:13:51.633189 BL = 0x2
736 18:13:51.633298 RPST = 0x0
737 18:13:51.636457 RD_PRE = 0x0
738 18:13:51.636535 WR_PRE = 0x1
739 18:13:51.639796 WR_PST = 0x0
740 18:13:51.639878 DBI_WR = 0x0
741 18:13:51.642923 DBI_RD = 0x0
742 18:13:51.643033 OTF = 0x1
743 18:13:51.646456 ===================================
744 18:13:51.649877 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 18:13:51.656445 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 18:13:51.659842 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 18:13:51.663305 ===================================
748 18:13:51.666671 LPDDR4 DRAM CONFIGURATION
749 18:13:51.670141 ===================================
750 18:13:51.670231 EX_ROW_EN[0] = 0x10
751 18:13:51.673039 EX_ROW_EN[1] = 0x0
752 18:13:51.673122 LP4Y_EN = 0x0
753 18:13:51.676727 WORK_FSP = 0x0
754 18:13:51.676810 WL = 0x2
755 18:13:51.680254 RL = 0x2
756 18:13:51.680424 BL = 0x2
757 18:13:51.683170 RPST = 0x0
758 18:13:51.683275 RD_PRE = 0x0
759 18:13:51.686731 WR_PRE = 0x1
760 18:13:51.686816 WR_PST = 0x0
761 18:13:51.690260 DBI_WR = 0x0
762 18:13:51.690344 DBI_RD = 0x0
763 18:13:51.693312 OTF = 0x1
764 18:13:51.696941 ===================================
765 18:13:51.703712 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 18:13:51.706626 nWR fixed to 40
767 18:13:51.710117 [ModeRegInit_LP4] CH0 RK0
768 18:13:51.710202 [ModeRegInit_LP4] CH0 RK1
769 18:13:51.713761 [ModeRegInit_LP4] CH1 RK0
770 18:13:51.716776 [ModeRegInit_LP4] CH1 RK1
771 18:13:51.716860 match AC timing 13
772 18:13:51.723486 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 18:13:51.727273 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 18:13:51.730195 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 18:13:51.736471 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 18:13:51.739949 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 18:13:51.740034 [EMI DOE] emi_dcm 0
778 18:13:51.746954 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 18:13:51.747039 ==
780 18:13:51.750428 Dram Type= 6, Freq= 0, CH_0, rank 0
781 18:13:51.753980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 18:13:51.754120 ==
783 18:13:51.760196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 18:13:51.763466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 18:13:51.774123 [CA 0] Center 36 (6~67) winsize 62
786 18:13:51.777452 [CA 1] Center 36 (6~67) winsize 62
787 18:13:51.780903 [CA 2] Center 34 (4~65) winsize 62
788 18:13:51.783827 [CA 3] Center 34 (4~64) winsize 61
789 18:13:51.787438 [CA 4] Center 33 (3~63) winsize 61
790 18:13:51.790471 [CA 5] Center 32 (2~62) winsize 61
791 18:13:51.790556
792 18:13:51.793832 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 18:13:51.793916
794 18:13:51.797528 [CATrainingPosCal] consider 1 rank data
795 18:13:51.800525 u2DelayCellTimex100 = 270/100 ps
796 18:13:51.804151 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 18:13:51.807091 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 18:13:51.813615 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 18:13:51.817857 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
800 18:13:51.820667 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
801 18:13:51.824368 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
802 18:13:51.824466
803 18:13:51.827257 CA PerBit enable=1, Macro0, CA PI delay=32
804 18:13:51.827341
805 18:13:51.830946 [CBTSetCACLKResult] CA Dly = 32
806 18:13:51.831030 CS Dly: 5 (0~36)
807 18:13:51.831097 ==
808 18:13:51.833915 Dram Type= 6, Freq= 0, CH_0, rank 1
809 18:13:51.841085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 18:13:51.841170 ==
811 18:13:51.843980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 18:13:51.850633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 18:13:51.860322 [CA 0] Center 36 (6~67) winsize 62
814 18:13:51.863212 [CA 1] Center 36 (6~67) winsize 62
815 18:13:51.866638 [CA 2] Center 34 (4~65) winsize 62
816 18:13:51.870019 [CA 3] Center 34 (4~65) winsize 62
817 18:13:51.873401 [CA 4] Center 33 (2~64) winsize 63
818 18:13:51.877031 [CA 5] Center 32 (2~63) winsize 62
819 18:13:51.877116
820 18:13:51.880051 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 18:13:51.880135
822 18:13:51.883644 [CATrainingPosCal] consider 2 rank data
823 18:13:51.887140 u2DelayCellTimex100 = 270/100 ps
824 18:13:51.890513 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 18:13:51.894093 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 18:13:51.896866 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 18:13:51.904056 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
828 18:13:51.907058 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
829 18:13:51.910663 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
830 18:13:51.910746
831 18:13:51.913565 CA PerBit enable=1, Macro0, CA PI delay=32
832 18:13:51.913648
833 18:13:51.917220 [CBTSetCACLKResult] CA Dly = 32
834 18:13:51.917304 CS Dly: 5 (0~36)
835 18:13:51.917370
836 18:13:51.920205 ----->DramcWriteLeveling(PI) begin...
837 18:13:51.923820 ==
838 18:13:51.923903 Dram Type= 6, Freq= 0, CH_0, rank 0
839 18:13:51.931882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 18:13:51.931969 ==
841 18:13:51.932036 Write leveling (Byte 0): 33 => 33
842 18:13:51.934960 Write leveling (Byte 1): 30 => 30
843 18:13:51.938488 DramcWriteLeveling(PI) end<-----
844 18:13:51.938572
845 18:13:51.938639 ==
846 18:13:51.942298 Dram Type= 6, Freq= 0, CH_0, rank 0
847 18:13:51.945976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 18:13:51.946060 ==
849 18:13:51.948736 [Gating] SW mode calibration
850 18:13:51.956224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 18:13:51.963489 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 18:13:51.966919 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 18:13:51.969771 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 18:13:51.976927 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
855 18:13:51.979694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 18:13:51.982961 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 18:13:51.986392 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 18:13:51.993514 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:13:51.996365 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:13:51.999716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:13:52.006974 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:13:52.009970 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:13:52.012969 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 18:13:52.020362 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 18:13:52.023282 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 18:13:52.027029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 18:13:52.033302 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 18:13:52.036841 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 18:13:52.039892 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 18:13:52.046420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 18:13:52.050075 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 18:13:52.053013 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 18:13:52.059646 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 18:13:52.063103 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 18:13:52.066842 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 18:13:52.069777 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 18:13:52.076976 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 18:13:52.080328 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (1 1) (1 1)
879 18:13:52.083243 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
880 18:13:52.090219 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 18:13:52.093619 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 18:13:52.097003 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 18:13:52.103200 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 18:13:52.106822 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 18:13:52.110037 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
886 18:13:52.116791 0 10 8 | B1->B0 | 3232 2929 | 1 0 | (1 0) (1 0)
887 18:13:52.119787 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 18:13:52.123445 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 18:13:52.129942 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 18:13:52.133596 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 18:13:52.136390 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 18:13:52.143391 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 18:13:52.146474 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
894 18:13:52.149986 0 11 8 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (0 0)
895 18:13:52.153770 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
896 18:13:52.160074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 18:13:52.163765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 18:13:52.166912 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 18:13:52.173461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 18:13:52.176348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 18:13:52.180081 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 18:13:52.186954 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 18:13:52.190265 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 18:13:52.193793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 18:13:52.200136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 18:13:52.203797 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 18:13:52.207263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 18:13:52.213655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 18:13:52.217109 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 18:13:52.220431 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 18:13:52.227050 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 18:13:52.230194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 18:13:52.233575 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 18:13:52.240413 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 18:13:52.243335 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 18:13:52.246869 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 18:13:52.249921 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 18:13:52.256708 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 18:13:52.260335 Total UI for P1: 0, mck2ui 16
920 18:13:52.263254 best dqsien dly found for B0: ( 0, 14, 4)
921 18:13:52.267092 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
922 18:13:52.270117 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 18:13:52.273585 Total UI for P1: 0, mck2ui 16
924 18:13:52.277241 best dqsien dly found for B1: ( 0, 14, 10)
925 18:13:52.280390 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 18:13:52.283937 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 18:13:52.284021
928 18:13:52.286967 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 18:13:52.294193 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 18:13:52.294282 [Gating] SW calibration Done
931 18:13:52.294348 ==
932 18:13:52.297201 Dram Type= 6, Freq= 0, CH_0, rank 0
933 18:13:52.304103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 18:13:52.304219 ==
935 18:13:52.304314 RX Vref Scan: 0
936 18:13:52.304427
937 18:13:52.307164 RX Vref 0 -> 0, step: 1
938 18:13:52.307245
939 18:13:52.310731 RX Delay -130 -> 252, step: 16
940 18:13:52.314176 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 18:13:52.317044 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 18:13:52.320693 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 18:13:52.327355 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 18:13:52.330197 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 18:13:52.333830 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 18:13:52.337477 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 18:13:52.340827 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 18:13:52.346971 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 18:13:52.350437 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 18:13:52.353882 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 18:13:52.357276 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 18:13:52.360248 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 18:13:52.367435 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 18:13:52.371034 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 18:13:52.374026 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 18:13:52.374109 ==
957 18:13:52.377723 Dram Type= 6, Freq= 0, CH_0, rank 0
958 18:13:52.380520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 18:13:52.380602 ==
960 18:13:52.384272 DQS Delay:
961 18:13:52.384411 DQS0 = 0, DQS1 = 0
962 18:13:52.387200 DQM Delay:
963 18:13:52.387283 DQM0 = 89, DQM1 = 80
964 18:13:52.387348 DQ Delay:
965 18:13:52.391028 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 18:13:52.393861 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 18:13:52.397215 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
968 18:13:52.400809 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 18:13:52.400894
970 18:13:52.400980
971 18:13:52.401061 ==
972 18:13:52.403748 Dram Type= 6, Freq= 0, CH_0, rank 0
973 18:13:52.410943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 18:13:52.411031 ==
975 18:13:52.411117
976 18:13:52.411198
977 18:13:52.411276 TX Vref Scan disable
978 18:13:52.414465 == TX Byte 0 ==
979 18:13:52.417799 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 18:13:52.421256 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 18:13:52.424815 == TX Byte 1 ==
982 18:13:52.427673 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
983 18:13:52.431257 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
984 18:13:52.434889 ==
985 18:13:52.438519 Dram Type= 6, Freq= 0, CH_0, rank 0
986 18:13:52.441592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 18:13:52.441678 ==
988 18:13:52.453655 TX Vref=22, minBit 9, minWin=27, winSum=450
989 18:13:52.457300 TX Vref=24, minBit 8, minWin=27, winSum=451
990 18:13:52.460904 TX Vref=26, minBit 0, minWin=28, winSum=455
991 18:13:52.463841 TX Vref=28, minBit 0, minWin=28, winSum=459
992 18:13:52.467043 TX Vref=30, minBit 8, minWin=28, winSum=460
993 18:13:52.470335 TX Vref=32, minBit 5, minWin=28, winSum=457
994 18:13:52.477320 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
995 18:13:52.477408
996 18:13:52.480254 Final TX Range 1 Vref 30
997 18:13:52.480372
998 18:13:52.480459 ==
999 18:13:52.484089 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 18:13:52.487063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 18:13:52.487149 ==
1002 18:13:52.487235
1003 18:13:52.490540
1004 18:13:52.490624 TX Vref Scan disable
1005 18:13:52.494200 == TX Byte 0 ==
1006 18:13:52.497093 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 18:13:52.500724 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 18:13:52.503761 == TX Byte 1 ==
1009 18:13:52.507539 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 18:13:52.510461 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 18:13:52.513993
1012 18:13:52.514098 [DATLAT]
1013 18:13:52.514179 Freq=800, CH0 RK0
1014 18:13:52.514240
1015 18:13:52.517024 DATLAT Default: 0xa
1016 18:13:52.517105 0, 0xFFFF, sum = 0
1017 18:13:52.520710 1, 0xFFFF, sum = 0
1018 18:13:52.520793 2, 0xFFFF, sum = 0
1019 18:13:52.524080 3, 0xFFFF, sum = 0
1020 18:13:52.524163 4, 0xFFFF, sum = 0
1021 18:13:52.527414 5, 0xFFFF, sum = 0
1022 18:13:52.527500 6, 0xFFFF, sum = 0
1023 18:13:52.530796 7, 0xFFFF, sum = 0
1024 18:13:52.530880 8, 0xFFFF, sum = 0
1025 18:13:52.534014 9, 0x0, sum = 1
1026 18:13:52.534099 10, 0x0, sum = 2
1027 18:13:52.537516 11, 0x0, sum = 3
1028 18:13:52.537598 12, 0x0, sum = 4
1029 18:13:52.541046 best_step = 10
1030 18:13:52.541127
1031 18:13:52.541190 ==
1032 18:13:52.544602 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 18:13:52.547475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 18:13:52.547557 ==
1035 18:13:52.550576 RX Vref Scan: 1
1036 18:13:52.550658
1037 18:13:52.550722 Set Vref Range= 32 -> 127
1038 18:13:52.550783
1039 18:13:52.554177 RX Vref 32 -> 127, step: 1
1040 18:13:52.554259
1041 18:13:52.557688 RX Delay -95 -> 252, step: 8
1042 18:13:52.557770
1043 18:13:52.561193 Set Vref, RX VrefLevel [Byte0]: 32
1044 18:13:52.564132 [Byte1]: 32
1045 18:13:52.564212
1046 18:13:52.567788 Set Vref, RX VrefLevel [Byte0]: 33
1047 18:13:52.570707 [Byte1]: 33
1048 18:13:52.574207
1049 18:13:52.574290 Set Vref, RX VrefLevel [Byte0]: 34
1050 18:13:52.577729 [Byte1]: 34
1051 18:13:52.581934
1052 18:13:52.582015 Set Vref, RX VrefLevel [Byte0]: 35
1053 18:13:52.584990 [Byte1]: 35
1054 18:13:52.590399
1055 18:13:52.590480 Set Vref, RX VrefLevel [Byte0]: 36
1056 18:13:52.593339 [Byte1]: 36
1057 18:13:52.597820
1058 18:13:52.597924 Set Vref, RX VrefLevel [Byte0]: 37
1059 18:13:52.600760 [Byte1]: 37
1060 18:13:52.605007
1061 18:13:52.605091 Set Vref, RX VrefLevel [Byte0]: 38
1062 18:13:52.608664 [Byte1]: 38
1063 18:13:52.612389
1064 18:13:52.612474 Set Vref, RX VrefLevel [Byte0]: 39
1065 18:13:52.616231 [Byte1]: 39
1066 18:13:52.619957
1067 18:13:52.620070 Set Vref, RX VrefLevel [Byte0]: 40
1068 18:13:52.623520 [Byte1]: 40
1069 18:13:52.627230
1070 18:13:52.627324 Set Vref, RX VrefLevel [Byte0]: 41
1071 18:13:52.630925 [Byte1]: 41
1072 18:13:52.635256
1073 18:13:52.635340 Set Vref, RX VrefLevel [Byte0]: 42
1074 18:13:52.638175 [Byte1]: 42
1075 18:13:52.642240
1076 18:13:52.642325 Set Vref, RX VrefLevel [Byte0]: 43
1077 18:13:52.645949 [Byte1]: 43
1078 18:13:52.650469
1079 18:13:52.650555 Set Vref, RX VrefLevel [Byte0]: 44
1080 18:13:52.653714 [Byte1]: 44
1081 18:13:52.657726
1082 18:13:52.657811 Set Vref, RX VrefLevel [Byte0]: 45
1083 18:13:52.661159 [Byte1]: 45
1084 18:13:52.665453
1085 18:13:52.665539 Set Vref, RX VrefLevel [Byte0]: 46
1086 18:13:52.669071 [Byte1]: 46
1087 18:13:52.672908
1088 18:13:52.672995 Set Vref, RX VrefLevel [Byte0]: 47
1089 18:13:52.676661 [Byte1]: 47
1090 18:13:52.680764
1091 18:13:52.680875 Set Vref, RX VrefLevel [Byte0]: 48
1092 18:13:52.683727 [Byte1]: 48
1093 18:13:52.688195
1094 18:13:52.688276 Set Vref, RX VrefLevel [Byte0]: 49
1095 18:13:52.691449 [Byte1]: 49
1096 18:13:52.696330
1097 18:13:52.696448 Set Vref, RX VrefLevel [Byte0]: 50
1098 18:13:52.699128 [Byte1]: 50
1099 18:13:52.703766
1100 18:13:52.703853 Set Vref, RX VrefLevel [Byte0]: 51
1101 18:13:52.706745 [Byte1]: 51
1102 18:13:52.711080
1103 18:13:52.711164 Set Vref, RX VrefLevel [Byte0]: 52
1104 18:13:52.714051 [Byte1]: 52
1105 18:13:52.718488
1106 18:13:52.718578 Set Vref, RX VrefLevel [Byte0]: 53
1107 18:13:52.722094 [Byte1]: 53
1108 18:13:52.726187
1109 18:13:52.726274 Set Vref, RX VrefLevel [Byte0]: 54
1110 18:13:52.729108 [Byte1]: 54
1111 18:13:52.733537
1112 18:13:52.733625 Set Vref, RX VrefLevel [Byte0]: 55
1113 18:13:52.737218 [Byte1]: 55
1114 18:13:52.741735
1115 18:13:52.741974 Set Vref, RX VrefLevel [Byte0]: 56
1116 18:13:52.744663 [Byte1]: 56
1117 18:13:52.748894
1118 18:13:52.748997 Set Vref, RX VrefLevel [Byte0]: 57
1119 18:13:52.752385 [Byte1]: 57
1120 18:13:52.756738
1121 18:13:52.756831 Set Vref, RX VrefLevel [Byte0]: 58
1122 18:13:52.759683 [Byte1]: 58
1123 18:13:52.764446
1124 18:13:52.764532 Set Vref, RX VrefLevel [Byte0]: 59
1125 18:13:52.767255 [Byte1]: 59
1126 18:13:52.772000
1127 18:13:52.772089 Set Vref, RX VrefLevel [Byte0]: 60
1128 18:13:52.775543 [Byte1]: 60
1129 18:13:52.779388
1130 18:13:52.779501 Set Vref, RX VrefLevel [Byte0]: 61
1131 18:13:52.782680 [Byte1]: 61
1132 18:13:52.787113
1133 18:13:52.787202 Set Vref, RX VrefLevel [Byte0]: 62
1134 18:13:52.789938 [Byte1]: 62
1135 18:13:52.794792
1136 18:13:52.794906 Set Vref, RX VrefLevel [Byte0]: 63
1137 18:13:52.797601 [Byte1]: 63
1138 18:13:52.802395
1139 18:13:52.802474 Set Vref, RX VrefLevel [Byte0]: 64
1140 18:13:52.805810 [Byte1]: 64
1141 18:13:52.810181
1142 18:13:52.810260 Set Vref, RX VrefLevel [Byte0]: 65
1143 18:13:52.813034 [Byte1]: 65
1144 18:13:52.817460
1145 18:13:52.817571 Set Vref, RX VrefLevel [Byte0]: 66
1146 18:13:52.821010 [Byte1]: 66
1147 18:13:52.824718
1148 18:13:52.824886 Set Vref, RX VrefLevel [Byte0]: 67
1149 18:13:52.828386 [Byte1]: 67
1150 18:13:52.832837
1151 18:13:52.832967 Set Vref, RX VrefLevel [Byte0]: 68
1152 18:13:52.835649 [Byte1]: 68
1153 18:13:52.839917
1154 18:13:52.840059 Set Vref, RX VrefLevel [Byte0]: 69
1155 18:13:52.843707 [Byte1]: 69
1156 18:13:52.847707
1157 18:13:52.847909 Set Vref, RX VrefLevel [Byte0]: 70
1158 18:13:52.851278 [Byte1]: 70
1159 18:13:52.855698
1160 18:13:52.855821 Set Vref, RX VrefLevel [Byte0]: 71
1161 18:13:52.858649 [Byte1]: 71
1162 18:13:52.862931
1163 18:13:52.863016 Set Vref, RX VrefLevel [Byte0]: 72
1164 18:13:52.866037 [Byte1]: 72
1165 18:13:52.870348
1166 18:13:52.870506 Set Vref, RX VrefLevel [Byte0]: 73
1167 18:13:52.874106 [Byte1]: 73
1168 18:13:52.877901
1169 18:13:52.877991 Set Vref, RX VrefLevel [Byte0]: 74
1170 18:13:52.881330 [Byte1]: 74
1171 18:13:52.886149
1172 18:13:52.886231 Final RX Vref Byte 0 = 59 to rank0
1173 18:13:52.889474 Final RX Vref Byte 1 = 59 to rank0
1174 18:13:52.892662 Final RX Vref Byte 0 = 59 to rank1
1175 18:13:52.895703 Final RX Vref Byte 1 = 59 to rank1==
1176 18:13:52.898905 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 18:13:52.905749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 18:13:52.905843 ==
1179 18:13:52.905909 DQS Delay:
1180 18:13:52.905970 DQS0 = 0, DQS1 = 0
1181 18:13:52.909201 DQM Delay:
1182 18:13:52.909285 DQM0 = 92, DQM1 = 85
1183 18:13:52.912647 DQ Delay:
1184 18:13:52.915527 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1185 18:13:52.919309 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1186 18:13:52.919398 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1187 18:13:52.926172 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1188 18:13:52.926260
1189 18:13:52.926326
1190 18:13:52.932783 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a40, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1191 18:13:52.935761 CH0 RK0: MR19=606, MR18=4A40
1192 18:13:52.942170 CH0_RK0: MR19=0x606, MR18=0x4A40, DQSOSC=391, MR23=63, INC=96, DEC=64
1193 18:13:52.942259
1194 18:13:52.945683 ----->DramcWriteLeveling(PI) begin...
1195 18:13:52.945770 ==
1196 18:13:52.949395 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 18:13:52.952237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 18:13:52.952321 ==
1199 18:13:52.955688 Write leveling (Byte 0): 32 => 32
1200 18:13:52.959218 Write leveling (Byte 1): 31 => 31
1201 18:13:52.962259 DramcWriteLeveling(PI) end<-----
1202 18:13:52.962344
1203 18:13:52.962409 ==
1204 18:13:52.965922 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 18:13:52.968866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 18:13:52.968950 ==
1207 18:13:52.972409 [Gating] SW mode calibration
1208 18:13:52.978962 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 18:13:52.986218 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 18:13:52.989027 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 18:13:52.992744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 18:13:53.036308 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1213 18:13:53.036736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1214 18:13:53.036824 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 18:13:53.036902 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 18:13:53.036977 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 18:13:53.037035 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 18:13:53.037151 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 18:13:53.037255 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 18:13:53.037315 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 18:13:53.037372 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 18:13:53.058505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 18:13:53.059312 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 18:13:53.059675 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 18:13:53.059750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 18:13:53.059813 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:13:53.063075 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:13:53.070047 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1229 18:13:53.073022 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:13:53.076818 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 18:13:53.083206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 18:13:53.086215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 18:13:53.089830 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 18:13:53.096316 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 18:13:53.099928 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1236 18:13:53.102824 0 9 8 | B1->B0 | 2d2d 2b2b | 1 0 | (1 1) (1 1)
1237 18:13:53.106625 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 18:13:53.113100 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 18:13:53.116772 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 18:13:53.119910 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 18:13:53.126471 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 18:13:53.129422 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 18:13:53.133034 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 18:13:53.139615 0 10 8 | B1->B0 | 2626 2b2b | 0 0 | (1 0) (0 0)
1245 18:13:53.143040 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 18:13:53.146293 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 18:13:53.153336 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 18:13:53.156646 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 18:13:53.159620 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 18:13:53.166414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 18:13:53.170342 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1252 18:13:53.173809 0 11 8 | B1->B0 | 3b3b 3a3a | 0 1 | (0 0) (0 0)
1253 18:13:53.177648 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 18:13:53.181306 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 18:13:53.187990 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 18:13:53.191349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 18:13:53.194856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 18:13:53.201685 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 18:13:53.205273 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 18:13:53.208250 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 18:13:53.212046 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 18:13:53.218732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 18:13:53.221823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 18:13:53.225422 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 18:13:53.232174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 18:13:53.235036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 18:13:53.238645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 18:13:53.245199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 18:13:53.248953 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 18:13:53.251866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 18:13:53.258457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 18:13:53.262128 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 18:13:53.264917 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 18:13:53.272159 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 18:13:53.275022 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 18:13:53.278667 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1277 18:13:53.285118 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 18:13:53.285229 Total UI for P1: 0, mck2ui 16
1279 18:13:53.288508 best dqsien dly found for B0: ( 0, 14, 8)
1280 18:13:53.292049 Total UI for P1: 0, mck2ui 16
1281 18:13:53.295523 best dqsien dly found for B1: ( 0, 14, 8)
1282 18:13:53.298543 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1283 18:13:53.304966 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1284 18:13:53.305078
1285 18:13:53.308186 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1286 18:13:53.311650 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 18:13:53.315025 [Gating] SW calibration Done
1288 18:13:53.315112 ==
1289 18:13:53.318177 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 18:13:53.321524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 18:13:53.321641 ==
1292 18:13:53.321756 RX Vref Scan: 0
1293 18:13:53.321848
1294 18:13:53.325470 RX Vref 0 -> 0, step: 1
1295 18:13:53.325584
1296 18:13:53.328379 RX Delay -130 -> 252, step: 16
1297 18:13:53.332204 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1298 18:13:53.335132 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1299 18:13:53.341666 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1300 18:13:53.345192 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1301 18:13:53.348875 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1302 18:13:53.351779 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1303 18:13:53.355487 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1304 18:13:53.359010 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1305 18:13:53.365654 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1306 18:13:53.368480 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1307 18:13:53.372051 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1308 18:13:53.375640 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1309 18:13:53.378597 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1310 18:13:53.385843 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1311 18:13:53.388883 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1312 18:13:53.392439 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1313 18:13:53.392517 ==
1314 18:13:53.395756 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 18:13:53.399292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 18:13:53.402119 ==
1317 18:13:53.402225 DQS Delay:
1318 18:13:53.402290 DQS0 = 0, DQS1 = 0
1319 18:13:53.405855 DQM Delay:
1320 18:13:53.405938 DQM0 = 91, DQM1 = 80
1321 18:13:53.406004 DQ Delay:
1322 18:13:53.408604 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1323 18:13:53.412321 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1324 18:13:53.415371 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1325 18:13:53.419059 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1326 18:13:53.419171
1327 18:13:53.419270
1328 18:13:53.422430 ==
1329 18:13:53.426030 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 18:13:53.428703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 18:13:53.428820 ==
1332 18:13:53.428887
1333 18:13:53.428947
1334 18:13:53.431983 TX Vref Scan disable
1335 18:13:53.432090 == TX Byte 0 ==
1336 18:13:53.438932 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1337 18:13:53.442161 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1338 18:13:53.442250 == TX Byte 1 ==
1339 18:13:53.449175 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1340 18:13:53.452119 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1341 18:13:53.452205 ==
1342 18:13:53.455407 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 18:13:53.458892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 18:13:53.459002 ==
1345 18:13:53.472647 TX Vref=22, minBit 8, minWin=27, winSum=447
1346 18:13:53.475559 TX Vref=24, minBit 0, minWin=28, winSum=452
1347 18:13:53.479106 TX Vref=26, minBit 5, minWin=28, winSum=458
1348 18:13:53.482732 TX Vref=28, minBit 11, minWin=28, winSum=460
1349 18:13:53.485495 TX Vref=30, minBit 7, minWin=28, winSum=457
1350 18:13:53.492032 TX Vref=32, minBit 8, minWin=27, winSum=451
1351 18:13:53.495739 [TxChooseVref] Worse bit 11, Min win 28, Win sum 460, Final Vref 28
1352 18:13:53.495870
1353 18:13:53.498778 Final TX Range 1 Vref 28
1354 18:13:53.498890
1355 18:13:53.498983 ==
1356 18:13:53.502532 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 18:13:53.505879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 18:13:53.505957 ==
1359 18:13:53.508836
1360 18:13:53.508938
1361 18:13:53.509039 TX Vref Scan disable
1362 18:13:53.512483 == TX Byte 0 ==
1363 18:13:53.516111 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1364 18:13:53.519135 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1365 18:13:53.522299 == TX Byte 1 ==
1366 18:13:53.525790 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1367 18:13:53.528792 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1368 18:13:53.532515
1369 18:13:53.532622 [DATLAT]
1370 18:13:53.532713 Freq=800, CH0 RK1
1371 18:13:53.532809
1372 18:13:53.535453 DATLAT Default: 0xa
1373 18:13:53.535531 0, 0xFFFF, sum = 0
1374 18:13:53.539239 1, 0xFFFF, sum = 0
1375 18:13:53.539361 2, 0xFFFF, sum = 0
1376 18:13:53.542636 3, 0xFFFF, sum = 0
1377 18:13:53.542712 4, 0xFFFF, sum = 0
1378 18:13:53.545556 5, 0xFFFF, sum = 0
1379 18:13:53.545661 6, 0xFFFF, sum = 0
1380 18:13:53.549095 7, 0xFFFF, sum = 0
1381 18:13:53.552067 8, 0xFFFF, sum = 0
1382 18:13:53.552169 9, 0x0, sum = 1
1383 18:13:53.552269 10, 0x0, sum = 2
1384 18:13:53.555814 11, 0x0, sum = 3
1385 18:13:53.555895 12, 0x0, sum = 4
1386 18:13:53.559320 best_step = 10
1387 18:13:53.559420
1388 18:13:53.559516 ==
1389 18:13:53.562248 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 18:13:53.565848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 18:13:53.565922 ==
1392 18:13:53.569174 RX Vref Scan: 0
1393 18:13:53.569256
1394 18:13:53.569362 RX Vref 0 -> 0, step: 1
1395 18:13:53.569449
1396 18:13:53.572544 RX Delay -95 -> 252, step: 8
1397 18:13:53.579047 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1398 18:13:53.582768 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1399 18:13:53.585715 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1400 18:13:53.589058 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1401 18:13:53.592349 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1402 18:13:53.599103 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1403 18:13:53.602297 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1404 18:13:53.606046 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1405 18:13:53.609421 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1406 18:13:53.612150 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1407 18:13:53.619682 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1408 18:13:53.622666 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1409 18:13:53.625807 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1410 18:13:53.629211 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1411 18:13:53.632911 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1412 18:13:53.639027 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1413 18:13:53.639112 ==
1414 18:13:53.643221 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 18:13:53.646105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 18:13:53.646201 ==
1417 18:13:53.646279 DQS Delay:
1418 18:13:53.649663 DQS0 = 0, DQS1 = 0
1419 18:13:53.649743 DQM Delay:
1420 18:13:53.652502 DQM0 = 93, DQM1 = 82
1421 18:13:53.652608 DQ Delay:
1422 18:13:53.656198 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1423 18:13:53.659132 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1424 18:13:53.662686 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1425 18:13:53.666372 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1426 18:13:53.666521
1427 18:13:53.666584
1428 18:13:53.672997 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
1429 18:13:53.676009 CH0 RK1: MR19=606, MR18=3F0F
1430 18:13:53.682681 CH0_RK1: MR19=0x606, MR18=0x3F0F, DQSOSC=393, MR23=63, INC=95, DEC=63
1431 18:13:53.686459 [RxdqsGatingPostProcess] freq 800
1432 18:13:53.693043 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 18:13:53.693131 Pre-setting of DQS Precalculation
1434 18:13:53.699469 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 18:13:53.699589 ==
1436 18:13:53.702776 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 18:13:53.706208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 18:13:53.706292 ==
1439 18:13:53.713000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 18:13:53.719288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 18:13:53.727390 [CA 0] Center 36 (6~67) winsize 62
1442 18:13:53.731129 [CA 1] Center 36 (6~67) winsize 62
1443 18:13:53.734174 [CA 2] Center 35 (5~66) winsize 62
1444 18:13:53.737465 [CA 3] Center 34 (4~65) winsize 62
1445 18:13:53.741000 [CA 4] Center 34 (4~65) winsize 62
1446 18:13:53.743690 [CA 5] Center 33 (3~64) winsize 62
1447 18:13:53.743799
1448 18:13:53.747455 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 18:13:53.747612
1450 18:13:53.750826 [CATrainingPosCal] consider 1 rank data
1451 18:13:53.754582 u2DelayCellTimex100 = 270/100 ps
1452 18:13:53.757136 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1453 18:13:53.760811 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1454 18:13:53.767389 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1455 18:13:53.770912 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1456 18:13:53.774653 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 18:13:53.777509 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1458 18:13:53.777615
1459 18:13:53.781115 CA PerBit enable=1, Macro0, CA PI delay=33
1460 18:13:53.781219
1461 18:13:53.784097 [CBTSetCACLKResult] CA Dly = 33
1462 18:13:53.784198 CS Dly: 6 (0~37)
1463 18:13:53.784288 ==
1464 18:13:53.787779 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 18:13:53.794527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 18:13:53.794636 ==
1467 18:13:53.797606 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 18:13:53.804766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 18:13:53.813563 [CA 0] Center 36 (6~67) winsize 62
1470 18:13:53.817165 [CA 1] Center 37 (6~68) winsize 63
1471 18:13:53.820136 [CA 2] Center 35 (5~66) winsize 62
1472 18:13:53.823755 [CA 3] Center 34 (4~65) winsize 62
1473 18:13:53.826619 [CA 4] Center 35 (4~66) winsize 63
1474 18:13:53.830272 [CA 5] Center 34 (4~65) winsize 62
1475 18:13:53.830376
1476 18:13:53.833809 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 18:13:53.833912
1478 18:13:53.838170 [CATrainingPosCal] consider 2 rank data
1479 18:13:53.841731 u2DelayCellTimex100 = 270/100 ps
1480 18:13:53.845479 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 18:13:53.849646 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 18:13:53.853485 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1483 18:13:53.856982 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 18:13:53.860890 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 18:13:53.864175 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1486 18:13:53.864277
1487 18:13:53.867546 CA PerBit enable=1, Macro0, CA PI delay=34
1488 18:13:53.867632
1489 18:13:53.871138 [CBTSetCACLKResult] CA Dly = 34
1490 18:13:53.871221 CS Dly: 6 (0~38)
1491 18:13:53.871287
1492 18:13:53.874193 ----->DramcWriteLeveling(PI) begin...
1493 18:13:53.874310 ==
1494 18:13:53.877860 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 18:13:53.884543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 18:13:53.884661 ==
1497 18:13:53.887669 Write leveling (Byte 0): 29 => 29
1498 18:13:53.887779 Write leveling (Byte 1): 27 => 27
1499 18:13:53.891017 DramcWriteLeveling(PI) end<-----
1500 18:13:53.891124
1501 18:13:53.891218 ==
1502 18:13:53.894562 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 18:13:53.900827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 18:13:53.900924 ==
1505 18:13:53.904366 [Gating] SW mode calibration
1506 18:13:53.911020 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 18:13:53.914568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 18:13:53.921228 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 18:13:53.924172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1510 18:13:53.927740 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 18:13:53.931454 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 18:13:53.938061 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 18:13:53.941066 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 18:13:53.944710 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 18:13:53.951619 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 18:13:53.954380 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 18:13:53.957920 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 18:13:53.964608 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 18:13:53.967562 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 18:13:53.970926 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 18:13:53.977544 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 18:13:53.980913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 18:13:53.984170 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 18:13:53.990710 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1525 18:13:53.994751 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 18:13:53.997496 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:13:54.004303 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:13:54.007852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 18:13:54.010999 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 18:13:54.017812 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 18:13:54.021054 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 18:13:54.024479 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 18:13:54.028078 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1534 18:13:54.034690 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1535 18:13:54.037652 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 18:13:54.041321 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 18:13:54.047986 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 18:13:54.050929 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 18:13:54.054637 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 18:13:54.061315 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1541 18:13:54.064271 0 10 4 | B1->B0 | 3131 2a2a | 0 1 | (1 1) (1 0)
1542 18:13:54.067928 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 18:13:54.074547 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 18:13:54.077538 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 18:13:54.081243 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 18:13:54.087668 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 18:13:54.091288 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 18:13:54.094500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 18:13:54.097988 0 11 4 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
1550 18:13:54.104472 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1551 18:13:54.107629 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 18:13:54.111059 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 18:13:54.117610 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 18:13:54.121193 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 18:13:54.124597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 18:13:54.131472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 18:13:54.134648 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1558 18:13:54.137621 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 18:13:54.144229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 18:13:54.148186 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 18:13:54.151200 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 18:13:54.157819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 18:13:54.161409 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 18:13:54.164322 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 18:13:54.170944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 18:13:54.174616 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 18:13:54.177513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 18:13:54.184763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 18:13:54.187634 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 18:13:54.191573 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 18:13:54.198124 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 18:13:54.201417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 18:13:54.204200 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1574 18:13:54.207823 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 18:13:54.211318 Total UI for P1: 0, mck2ui 16
1576 18:13:54.214850 best dqsien dly found for B0: ( 0, 14, 4)
1577 18:13:54.218056 Total UI for P1: 0, mck2ui 16
1578 18:13:54.221397 best dqsien dly found for B1: ( 0, 14, 4)
1579 18:13:54.224217 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1580 18:13:54.227886 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1581 18:13:54.230888
1582 18:13:54.234474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 18:13:54.238128 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 18:13:54.240985 [Gating] SW calibration Done
1585 18:13:54.241098 ==
1586 18:13:54.244574 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 18:13:54.248038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 18:13:54.248154 ==
1589 18:13:54.248253 RX Vref Scan: 0
1590 18:13:54.248352
1591 18:13:54.251349 RX Vref 0 -> 0, step: 1
1592 18:13:54.251446
1593 18:13:54.254390 RX Delay -130 -> 252, step: 16
1594 18:13:54.258156 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1595 18:13:54.260981 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1596 18:13:54.267637 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1597 18:13:54.270995 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1598 18:13:54.274579 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1599 18:13:54.277807 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1600 18:13:54.281509 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1601 18:13:54.284581 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1602 18:13:54.291129 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1603 18:13:54.295276 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1604 18:13:54.297776 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1605 18:13:54.301472 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1606 18:13:54.304408 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1607 18:13:54.311107 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1608 18:13:54.314630 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1609 18:13:54.318125 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1610 18:13:54.318216 ==
1611 18:13:54.321047 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 18:13:54.324628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 18:13:54.328071 ==
1614 18:13:54.328155 DQS Delay:
1615 18:13:54.328222 DQS0 = 0, DQS1 = 0
1616 18:13:54.331407 DQM Delay:
1617 18:13:54.331491 DQM0 = 94, DQM1 = 92
1618 18:13:54.334845 DQ Delay:
1619 18:13:54.334928 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1620 18:13:54.337683 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1621 18:13:54.341369 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1622 18:13:54.348023 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1623 18:13:54.348146
1624 18:13:54.348215
1625 18:13:54.348277 ==
1626 18:13:54.351705 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 18:13:54.355140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 18:13:54.355253 ==
1629 18:13:54.355321
1630 18:13:54.355388
1631 18:13:54.358034 TX Vref Scan disable
1632 18:13:54.358142 == TX Byte 0 ==
1633 18:13:54.364750 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1634 18:13:54.367823 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1635 18:13:54.367907 == TX Byte 1 ==
1636 18:13:54.375023 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1637 18:13:54.378014 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1638 18:13:54.378099 ==
1639 18:13:54.381497 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 18:13:54.384357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 18:13:54.384441 ==
1642 18:13:54.398894 TX Vref=22, minBit 0, minWin=27, winSum=442
1643 18:13:54.401709 TX Vref=24, minBit 0, minWin=27, winSum=443
1644 18:13:54.405676 TX Vref=26, minBit 1, minWin=27, winSum=448
1645 18:13:54.408714 TX Vref=28, minBit 2, minWin=27, winSum=449
1646 18:13:54.412163 TX Vref=30, minBit 3, minWin=27, winSum=451
1647 18:13:54.415917 TX Vref=32, minBit 0, minWin=27, winSum=446
1648 18:13:54.423137 [TxChooseVref] Worse bit 3, Min win 27, Win sum 451, Final Vref 30
1649 18:13:54.423257
1650 18:13:54.426109 Final TX Range 1 Vref 30
1651 18:13:54.426245
1652 18:13:54.426382 ==
1653 18:13:54.429786 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 18:13:54.432723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 18:13:54.432831 ==
1656 18:13:54.432924
1657 18:13:54.433008
1658 18:13:54.436257 TX Vref Scan disable
1659 18:13:54.439887 == TX Byte 0 ==
1660 18:13:54.442574 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1661 18:13:54.446051 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1662 18:13:54.449754 == TX Byte 1 ==
1663 18:13:54.452923 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1664 18:13:54.456226 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1665 18:13:54.456336
1666 18:13:54.456426 [DATLAT]
1667 18:13:54.459784 Freq=800, CH1 RK0
1668 18:13:54.459865
1669 18:13:54.462654 DATLAT Default: 0xa
1670 18:13:54.462761 0, 0xFFFF, sum = 0
1671 18:13:54.466220 1, 0xFFFF, sum = 0
1672 18:13:54.466334 2, 0xFFFF, sum = 0
1673 18:13:54.469960 3, 0xFFFF, sum = 0
1674 18:13:54.470045 4, 0xFFFF, sum = 0
1675 18:13:54.472924 5, 0xFFFF, sum = 0
1676 18:13:54.473009 6, 0xFFFF, sum = 0
1677 18:13:54.476676 7, 0xFFFF, sum = 0
1678 18:13:54.476759 8, 0xFFFF, sum = 0
1679 18:13:54.479442 9, 0x0, sum = 1
1680 18:13:54.479525 10, 0x0, sum = 2
1681 18:13:54.483132 11, 0x0, sum = 3
1682 18:13:54.483215 12, 0x0, sum = 4
1683 18:13:54.483281 best_step = 10
1684 18:13:54.486150
1685 18:13:54.486232 ==
1686 18:13:54.489761 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 18:13:54.492709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 18:13:54.492791 ==
1689 18:13:54.492855 RX Vref Scan: 1
1690 18:13:54.492919
1691 18:13:54.496165 Set Vref Range= 32 -> 127
1692 18:13:54.496276
1693 18:13:54.499799 RX Vref 32 -> 127, step: 1
1694 18:13:54.499909
1695 18:13:54.502769 RX Delay -79 -> 252, step: 8
1696 18:13:54.502852
1697 18:13:54.506519 Set Vref, RX VrefLevel [Byte0]: 32
1698 18:13:54.509648 [Byte1]: 32
1699 18:13:54.509758
1700 18:13:54.513106 Set Vref, RX VrefLevel [Byte0]: 33
1701 18:13:54.516785 [Byte1]: 33
1702 18:13:54.516868
1703 18:13:54.519439 Set Vref, RX VrefLevel [Byte0]: 34
1704 18:13:54.522929 [Byte1]: 34
1705 18:13:54.526527
1706 18:13:54.526610 Set Vref, RX VrefLevel [Byte0]: 35
1707 18:13:54.529699 [Byte1]: 35
1708 18:13:54.534014
1709 18:13:54.534113 Set Vref, RX VrefLevel [Byte0]: 36
1710 18:13:54.537470 [Byte1]: 36
1711 18:13:54.541127
1712 18:13:54.541238 Set Vref, RX VrefLevel [Byte0]: 37
1713 18:13:54.544723 [Byte1]: 37
1714 18:13:54.549023
1715 18:13:54.549131 Set Vref, RX VrefLevel [Byte0]: 38
1716 18:13:54.552540 [Byte1]: 38
1717 18:13:54.556835
1718 18:13:54.556941 Set Vref, RX VrefLevel [Byte0]: 39
1719 18:13:54.559904 [Byte1]: 39
1720 18:13:54.564060
1721 18:13:54.564139 Set Vref, RX VrefLevel [Byte0]: 40
1722 18:13:54.567839 [Byte1]: 40
1723 18:13:54.571513
1724 18:13:54.571622 Set Vref, RX VrefLevel [Byte0]: 41
1725 18:13:54.574956 [Byte1]: 41
1726 18:13:54.579207
1727 18:13:54.579293 Set Vref, RX VrefLevel [Byte0]: 42
1728 18:13:54.582297 [Byte1]: 42
1729 18:13:54.586656
1730 18:13:54.586753 Set Vref, RX VrefLevel [Byte0]: 43
1731 18:13:54.589805 [Byte1]: 43
1732 18:13:54.594412
1733 18:13:54.594497 Set Vref, RX VrefLevel [Byte0]: 44
1734 18:13:54.597883 [Byte1]: 44
1735 18:13:54.601523
1736 18:13:54.601609 Set Vref, RX VrefLevel [Byte0]: 45
1737 18:13:54.605277 [Byte1]: 45
1738 18:13:54.609677
1739 18:13:54.609788 Set Vref, RX VrefLevel [Byte0]: 46
1740 18:13:54.612582 [Byte1]: 46
1741 18:13:54.616912
1742 18:13:54.616998 Set Vref, RX VrefLevel [Byte0]: 47
1743 18:13:54.620241 [Byte1]: 47
1744 18:13:54.624437
1745 18:13:54.624523 Set Vref, RX VrefLevel [Byte0]: 48
1746 18:13:54.627666 [Byte1]: 48
1747 18:13:54.632107
1748 18:13:54.632226 Set Vref, RX VrefLevel [Byte0]: 49
1749 18:13:54.635494 [Byte1]: 49
1750 18:13:54.639959
1751 18:13:54.640046 Set Vref, RX VrefLevel [Byte0]: 50
1752 18:13:54.643122 [Byte1]: 50
1753 18:13:54.647110
1754 18:13:54.647197 Set Vref, RX VrefLevel [Byte0]: 51
1755 18:13:54.650007 [Byte1]: 51
1756 18:13:54.654894
1757 18:13:54.654980 Set Vref, RX VrefLevel [Byte0]: 52
1758 18:13:54.657691 [Byte1]: 52
1759 18:13:54.661890
1760 18:13:54.662003 Set Vref, RX VrefLevel [Byte0]: 53
1761 18:13:54.665538 [Byte1]: 53
1762 18:13:54.669718
1763 18:13:54.669801 Set Vref, RX VrefLevel [Byte0]: 54
1764 18:13:54.673430 [Byte1]: 54
1765 18:13:54.677099
1766 18:13:54.677186 Set Vref, RX VrefLevel [Byte0]: 55
1767 18:13:54.680748 [Byte1]: 55
1768 18:13:54.685164
1769 18:13:54.685271 Set Vref, RX VrefLevel [Byte0]: 56
1770 18:13:54.688166 [Byte1]: 56
1771 18:13:54.692629
1772 18:13:54.692704 Set Vref, RX VrefLevel [Byte0]: 57
1773 18:13:54.695599 [Byte1]: 57
1774 18:13:54.700092
1775 18:13:54.700176 Set Vref, RX VrefLevel [Byte0]: 58
1776 18:13:54.703694 [Byte1]: 58
1777 18:13:54.707274
1778 18:13:54.707358 Set Vref, RX VrefLevel [Byte0]: 59
1779 18:13:54.711041 [Byte1]: 59
1780 18:13:54.714748
1781 18:13:54.714831 Set Vref, RX VrefLevel [Byte0]: 60
1782 18:13:54.718281 [Byte1]: 60
1783 18:13:54.722617
1784 18:13:54.722726 Set Vref, RX VrefLevel [Byte0]: 61
1785 18:13:54.725618 [Byte1]: 61
1786 18:13:54.729956
1787 18:13:54.730059 Set Vref, RX VrefLevel [Byte0]: 62
1788 18:13:54.733526 [Byte1]: 62
1789 18:13:54.737554
1790 18:13:54.737662 Set Vref, RX VrefLevel [Byte0]: 63
1791 18:13:54.741036 [Byte1]: 63
1792 18:13:54.745032
1793 18:13:54.745143 Set Vref, RX VrefLevel [Byte0]: 64
1794 18:13:54.748483 [Byte1]: 64
1795 18:13:54.752433
1796 18:13:54.752525 Set Vref, RX VrefLevel [Byte0]: 65
1797 18:13:54.755858 [Byte1]: 65
1798 18:13:54.760236
1799 18:13:54.760354 Set Vref, RX VrefLevel [Byte0]: 66
1800 18:13:54.763553 [Byte1]: 66
1801 18:13:54.767874
1802 18:13:54.767968 Set Vref, RX VrefLevel [Byte0]: 67
1803 18:13:54.771071 [Byte1]: 67
1804 18:13:54.775419
1805 18:13:54.775530 Set Vref, RX VrefLevel [Byte0]: 68
1806 18:13:54.778747 [Byte1]: 68
1807 18:13:54.783358
1808 18:13:54.783446 Set Vref, RX VrefLevel [Byte0]: 69
1809 18:13:54.786033 [Byte1]: 69
1810 18:13:54.790605
1811 18:13:54.790695 Set Vref, RX VrefLevel [Byte0]: 70
1812 18:13:54.794053 [Byte1]: 70
1813 18:13:54.797814
1814 18:13:54.797900 Set Vref, RX VrefLevel [Byte0]: 71
1815 18:13:54.801551 [Byte1]: 71
1816 18:13:54.805815
1817 18:13:54.805933 Set Vref, RX VrefLevel [Byte0]: 72
1818 18:13:54.808857 [Byte1]: 72
1819 18:13:54.813098
1820 18:13:54.813212 Final RX Vref Byte 0 = 56 to rank0
1821 18:13:54.816691 Final RX Vref Byte 1 = 51 to rank0
1822 18:13:54.819589 Final RX Vref Byte 0 = 56 to rank1
1823 18:13:54.823196 Final RX Vref Byte 1 = 51 to rank1==
1824 18:13:54.826693 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 18:13:54.833360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 18:13:54.833449 ==
1827 18:13:54.833544 DQS Delay:
1828 18:13:54.833633 DQS0 = 0, DQS1 = 0
1829 18:13:54.836426 DQM Delay:
1830 18:13:54.836502 DQM0 = 96, DQM1 = 90
1831 18:13:54.840068 DQ Delay:
1832 18:13:54.843060 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1833 18:13:54.846768 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1834 18:13:54.850244 DQ8 =76, DQ9 =76, DQ10 =92, DQ11 =84
1835 18:13:54.853000 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
1836 18:13:54.853081
1837 18:13:54.853146
1838 18:13:54.859976 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1839 18:13:54.863138 CH1 RK0: MR19=606, MR18=2945
1840 18:13:54.870100 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1841 18:13:54.870216
1842 18:13:54.872927 ----->DramcWriteLeveling(PI) begin...
1843 18:13:54.873028 ==
1844 18:13:54.876139 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 18:13:54.880045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 18:13:54.880156 ==
1847 18:13:54.883224 Write leveling (Byte 0): 29 => 29
1848 18:13:54.886407 Write leveling (Byte 1): 29 => 29
1849 18:13:54.889624 DramcWriteLeveling(PI) end<-----
1850 18:13:54.889711
1851 18:13:54.889786 ==
1852 18:13:54.892842 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 18:13:54.896847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 18:13:54.896954 ==
1855 18:13:54.900104 [Gating] SW mode calibration
1856 18:13:54.906625 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 18:13:54.913564 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 18:13:54.916457 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1859 18:13:54.919509 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1860 18:13:54.926938 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 18:13:54.929888 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 18:13:54.933616 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 18:13:54.940170 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 18:13:54.943202 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 18:13:54.946894 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 18:13:54.953596 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 18:13:54.956587 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 18:13:54.960141 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 18:13:54.966741 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 18:13:54.970637 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 18:13:54.973447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 18:13:54.980049 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 18:13:54.983256 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1874 18:13:54.986740 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1875 18:13:54.990141 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1876 18:13:54.996593 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 18:13:55.000066 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 18:13:55.003637 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 18:13:55.010095 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 18:13:55.013427 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 18:13:55.016656 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 18:13:55.023378 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 18:13:55.026546 0 9 4 | B1->B0 | 2727 2323 | 1 0 | (1 1) (0 0)
1884 18:13:55.030176 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1885 18:13:55.036775 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 18:13:55.040377 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 18:13:55.044059 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 18:13:55.050032 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 18:13:55.053789 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 18:13:55.057419 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1891 18:13:55.060278 0 10 4 | B1->B0 | 2626 3131 | 0 1 | (1 0) (1 0)
1892 18:13:55.066698 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1893 18:13:55.070303 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 18:13:55.073925 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 18:13:55.080791 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:13:55.083802 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 18:13:55.087235 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 18:13:55.094178 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 18:13:55.097265 0 11 4 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (0 0)
1900 18:13:55.100510 0 11 8 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
1901 18:13:55.107025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 18:13:55.110592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 18:13:55.113623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 18:13:55.120299 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 18:13:55.123613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 18:13:55.127009 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 18:13:55.133276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1908 18:13:55.136871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 18:13:55.140655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 18:13:55.146659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 18:13:55.150163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 18:13:55.153767 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 18:13:55.156826 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 18:13:55.163567 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 18:13:55.167284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 18:13:55.170171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 18:13:55.177345 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 18:13:55.180290 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 18:13:55.184043 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 18:13:55.190034 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 18:13:55.193730 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 18:13:55.196847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 18:13:55.204030 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1924 18:13:55.206963 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1925 18:13:55.210549 Total UI for P1: 0, mck2ui 16
1926 18:13:55.213940 best dqsien dly found for B1: ( 0, 14, 4)
1927 18:13:55.216679 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 18:13:55.220139 Total UI for P1: 0, mck2ui 16
1929 18:13:55.223943 best dqsien dly found for B0: ( 0, 14, 6)
1930 18:13:55.227062 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1931 18:13:55.230473 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1932 18:13:55.230585
1933 18:13:55.233937 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1934 18:13:55.240329 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 18:13:55.240460 [Gating] SW calibration Done
1936 18:13:55.240547 ==
1937 18:13:55.243762 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 18:13:55.250421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 18:13:55.250522 ==
1940 18:13:55.250590 RX Vref Scan: 0
1941 18:13:55.250650
1942 18:13:55.253584 RX Vref 0 -> 0, step: 1
1943 18:13:55.253665
1944 18:13:55.257307 RX Delay -130 -> 252, step: 16
1945 18:13:55.260747 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1946 18:13:55.263399 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1947 18:13:55.267140 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1948 18:13:55.273517 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1949 18:13:55.277150 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1950 18:13:55.280234 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1951 18:13:55.283917 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1952 18:13:55.286978 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1953 18:13:55.290637 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1954 18:13:55.297244 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1955 18:13:55.300202 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1956 18:13:55.303287 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1957 18:13:55.306941 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1958 18:13:55.313763 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1959 18:13:55.316620 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1960 18:13:55.320131 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1961 18:13:55.320219 ==
1962 18:13:55.323692 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 18:13:55.327060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 18:13:55.327148 ==
1965 18:13:55.329910 DQS Delay:
1966 18:13:55.330022 DQS0 = 0, DQS1 = 0
1967 18:13:55.332935 DQM Delay:
1968 18:13:55.333021 DQM0 = 92, DQM1 = 89
1969 18:13:55.333107 DQ Delay:
1970 18:13:55.336310 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1971 18:13:55.340446 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1972 18:13:55.343116 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1973 18:13:55.346622 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1974 18:13:55.346721
1975 18:13:55.350157
1976 18:13:55.350241 ==
1977 18:13:55.353663 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 18:13:55.356592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 18:13:55.356693 ==
1980 18:13:55.356759
1981 18:13:55.356818
1982 18:13:55.360123 TX Vref Scan disable
1983 18:13:55.360205 == TX Byte 0 ==
1984 18:13:55.366964 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1985 18:13:55.369904 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1986 18:13:55.369983 == TX Byte 1 ==
1987 18:13:55.376836 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1988 18:13:55.380048 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1989 18:13:55.380167 ==
1990 18:13:55.383291 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 18:13:55.386624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 18:13:55.386764 ==
1993 18:13:55.400405 TX Vref=22, minBit 1, minWin=27, winSum=443
1994 18:13:55.403437 TX Vref=24, minBit 1, minWin=27, winSum=446
1995 18:13:55.407255 TX Vref=26, minBit 1, minWin=27, winSum=453
1996 18:13:55.410283 TX Vref=28, minBit 0, minWin=28, winSum=458
1997 18:13:55.413984 TX Vref=30, minBit 1, minWin=27, winSum=456
1998 18:13:55.417014 TX Vref=32, minBit 1, minWin=27, winSum=450
1999 18:13:55.423402 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
2000 18:13:55.423511
2001 18:13:55.426923 Final TX Range 1 Vref 28
2002 18:13:55.427013
2003 18:13:55.427080 ==
2004 18:13:55.430430 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 18:13:55.433959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 18:13:55.434052 ==
2007 18:13:55.434120
2008 18:13:55.436907
2009 18:13:55.436996 TX Vref Scan disable
2010 18:13:55.440389 == TX Byte 0 ==
2011 18:13:55.443926 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2012 18:13:55.446766 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2013 18:13:55.450338 == TX Byte 1 ==
2014 18:13:55.453959 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2015 18:13:55.457335 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2016 18:13:55.457450
2017 18:13:55.460654 [DATLAT]
2018 18:13:55.460752 Freq=800, CH1 RK1
2019 18:13:55.460833
2020 18:13:55.463641 DATLAT Default: 0xa
2021 18:13:55.463729 0, 0xFFFF, sum = 0
2022 18:13:55.467085 1, 0xFFFF, sum = 0
2023 18:13:55.467206 2, 0xFFFF, sum = 0
2024 18:13:55.470495 3, 0xFFFF, sum = 0
2025 18:13:55.470613 4, 0xFFFF, sum = 0
2026 18:13:55.473887 5, 0xFFFF, sum = 0
2027 18:13:55.473982 6, 0xFFFF, sum = 0
2028 18:13:55.476791 7, 0xFFFF, sum = 0
2029 18:13:55.476911 8, 0xFFFF, sum = 0
2030 18:13:55.480449 9, 0x0, sum = 1
2031 18:13:55.480537 10, 0x0, sum = 2
2032 18:13:55.483563 11, 0x0, sum = 3
2033 18:13:55.483648 12, 0x0, sum = 4
2034 18:13:55.487059 best_step = 10
2035 18:13:55.487170
2036 18:13:55.487265 ==
2037 18:13:55.490659 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 18:13:55.493484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 18:13:55.493570 ==
2040 18:13:55.496873 RX Vref Scan: 0
2041 18:13:55.496957
2042 18:13:55.497022 RX Vref 0 -> 0, step: 1
2043 18:13:55.497082
2044 18:13:55.500058 RX Delay -79 -> 252, step: 8
2045 18:13:55.506852 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2046 18:13:55.510530 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2047 18:13:55.513407 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2048 18:13:55.516953 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2049 18:13:55.520672 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2050 18:13:55.523499 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2051 18:13:55.530226 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2052 18:13:55.533697 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2053 18:13:55.537395 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2054 18:13:55.540360 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2055 18:13:55.543911 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2056 18:13:55.550399 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2057 18:13:55.554054 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2058 18:13:55.556908 iDelay=209, Bit 13, Center 104 (9 ~ 200) 192
2059 18:13:55.560592 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2060 18:13:55.564200 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2061 18:13:55.564328 ==
2062 18:13:55.567355 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 18:13:55.573886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 18:13:55.574040 ==
2065 18:13:55.574149 DQS Delay:
2066 18:13:55.577410 DQS0 = 0, DQS1 = 0
2067 18:13:55.577524 DQM Delay:
2068 18:13:55.577626 DQM0 = 97, DQM1 = 91
2069 18:13:55.580802 DQ Delay:
2070 18:13:55.583644 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2071 18:13:55.587288 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =92
2072 18:13:55.590865 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2073 18:13:55.593860 DQ12 =100, DQ13 =104, DQ14 =96, DQ15 =96
2074 18:13:55.593962
2075 18:13:55.594057
2076 18:13:55.600512 [DQSOSCAuto] RK1, (LSB)MR18= 0x4812, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2077 18:13:55.603427 CH1 RK1: MR19=606, MR18=4812
2078 18:13:55.610361 CH1_RK1: MR19=0x606, MR18=0x4812, DQSOSC=391, MR23=63, INC=96, DEC=64
2079 18:13:55.613900 [RxdqsGatingPostProcess] freq 800
2080 18:13:55.616656 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 18:13:55.620015 Pre-setting of DQS Precalculation
2082 18:13:55.627015 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 18:13:55.633602 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 18:13:55.640225 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 18:13:55.640410
2086 18:13:55.640481
2087 18:13:55.644050 [Calibration Summary] 1600 Mbps
2088 18:13:55.644142 CH 0, Rank 0
2089 18:13:55.646869 SW Impedance : PASS
2090 18:13:55.650264 DUTY Scan : NO K
2091 18:13:55.650356 ZQ Calibration : PASS
2092 18:13:55.653919 Jitter Meter : NO K
2093 18:13:55.657560 CBT Training : PASS
2094 18:13:55.657649 Write leveling : PASS
2095 18:13:55.660504 RX DQS gating : PASS
2096 18:13:55.664177 RX DQ/DQS(RDDQC) : PASS
2097 18:13:55.664261 TX DQ/DQS : PASS
2098 18:13:55.667724 RX DATLAT : PASS
2099 18:13:55.670767 RX DQ/DQS(Engine): PASS
2100 18:13:55.670844 TX OE : NO K
2101 18:13:55.670909 All Pass.
2102 18:13:55.670981
2103 18:13:55.674184 CH 0, Rank 1
2104 18:13:55.674285 SW Impedance : PASS
2105 18:13:55.677594 DUTY Scan : NO K
2106 18:13:55.680642 ZQ Calibration : PASS
2107 18:13:55.680723 Jitter Meter : NO K
2108 18:13:55.684309 CBT Training : PASS
2109 18:13:55.687094 Write leveling : PASS
2110 18:13:55.687207 RX DQS gating : PASS
2111 18:13:55.690520 RX DQ/DQS(RDDQC) : PASS
2112 18:13:55.694065 TX DQ/DQS : PASS
2113 18:13:55.694211 RX DATLAT : PASS
2114 18:13:55.697030 RX DQ/DQS(Engine): PASS
2115 18:13:55.700934 TX OE : NO K
2116 18:13:55.701079 All Pass.
2117 18:13:55.701176
2118 18:13:55.701281 CH 1, Rank 0
2119 18:13:55.703615 SW Impedance : PASS
2120 18:13:55.707238 DUTY Scan : NO K
2121 18:13:55.707361 ZQ Calibration : PASS
2122 18:13:55.711074 Jitter Meter : NO K
2123 18:13:55.713872 CBT Training : PASS
2124 18:13:55.713967 Write leveling : PASS
2125 18:13:55.717527 RX DQS gating : PASS
2126 18:13:55.717630 RX DQ/DQS(RDDQC) : PASS
2127 18:13:55.720525 TX DQ/DQS : PASS
2128 18:13:55.724054 RX DATLAT : PASS
2129 18:13:55.724152 RX DQ/DQS(Engine): PASS
2130 18:13:55.727384 TX OE : NO K
2131 18:13:55.727477 All Pass.
2132 18:13:55.727565
2133 18:13:55.730791 CH 1, Rank 1
2134 18:13:55.730908 SW Impedance : PASS
2135 18:13:55.734286 DUTY Scan : NO K
2136 18:13:55.737518 ZQ Calibration : PASS
2137 18:13:55.737644 Jitter Meter : NO K
2138 18:13:55.740877 CBT Training : PASS
2139 18:13:55.744477 Write leveling : PASS
2140 18:13:55.744584 RX DQS gating : PASS
2141 18:13:55.747091 RX DQ/DQS(RDDQC) : PASS
2142 18:13:55.750465 TX DQ/DQS : PASS
2143 18:13:55.750598 RX DATLAT : PASS
2144 18:13:55.754148 RX DQ/DQS(Engine): PASS
2145 18:13:55.754294 TX OE : NO K
2146 18:13:55.757907 All Pass.
2147 18:13:55.758028
2148 18:13:55.758139 DramC Write-DBI off
2149 18:13:55.760532 PER_BANK_REFRESH: Hybrid Mode
2150 18:13:55.763937 TX_TRACKING: ON
2151 18:13:55.767551 [GetDramInforAfterCalByMRR] Vendor 6.
2152 18:13:55.770514 [GetDramInforAfterCalByMRR] Revision 606.
2153 18:13:55.774316 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 18:13:55.774406 MR0 0x3b3b
2155 18:13:55.774473 MR8 0x5151
2156 18:13:55.780706 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 18:13:55.780817
2158 18:13:55.780887 MR0 0x3b3b
2159 18:13:55.780948 MR8 0x5151
2160 18:13:55.784208 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 18:13:55.784287
2162 18:13:55.794132 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 18:13:55.797755 [FAST_K] Save calibration result to emmc
2164 18:13:55.801109 [FAST_K] Save calibration result to emmc
2165 18:13:55.804049 dram_init: config_dvfs: 1
2166 18:13:55.807711 dramc_set_vcore_voltage set vcore to 662500
2167 18:13:55.810676 Read voltage for 1200, 2
2168 18:13:55.810779 Vio18 = 0
2169 18:13:55.810846 Vcore = 662500
2170 18:13:55.814354 Vdram = 0
2171 18:13:55.814443 Vddq = 0
2172 18:13:55.814510 Vmddr = 0
2173 18:13:55.820832 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 18:13:55.824629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 18:13:55.827592 MEM_TYPE=3, freq_sel=15
2176 18:13:55.830562 sv_algorithm_assistance_LP4_1600
2177 18:13:55.834013 ============ PULL DRAM RESETB DOWN ============
2178 18:13:55.837435 ========== PULL DRAM RESETB DOWN end =========
2179 18:13:55.843892 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 18:13:55.847521 ===================================
2181 18:13:55.850970 LPDDR4 DRAM CONFIGURATION
2182 18:13:55.851062 ===================================
2183 18:13:55.854405 EX_ROW_EN[0] = 0x0
2184 18:13:55.857325 EX_ROW_EN[1] = 0x0
2185 18:13:55.857414 LP4Y_EN = 0x0
2186 18:13:55.860494 WORK_FSP = 0x0
2187 18:13:55.860584 WL = 0x4
2188 18:13:55.864139 RL = 0x4
2189 18:13:55.864257 BL = 0x2
2190 18:13:55.867597 RPST = 0x0
2191 18:13:55.867692 RD_PRE = 0x0
2192 18:13:55.871065 WR_PRE = 0x1
2193 18:13:55.871169 WR_PST = 0x0
2194 18:13:55.873741 DBI_WR = 0x0
2195 18:13:55.873860 DBI_RD = 0x0
2196 18:13:55.877337 OTF = 0x1
2197 18:13:55.880899 ===================================
2198 18:13:55.883891 ===================================
2199 18:13:55.883994 ANA top config
2200 18:13:55.887316 ===================================
2201 18:13:55.890935 DLL_ASYNC_EN = 0
2202 18:13:55.894554 ALL_SLAVE_EN = 0
2203 18:13:55.897496 NEW_RANK_MODE = 1
2204 18:13:55.897599 DLL_IDLE_MODE = 1
2205 18:13:55.901105 LP45_APHY_COMB_EN = 1
2206 18:13:55.903851 TX_ODT_DIS = 1
2207 18:13:55.907325 NEW_8X_MODE = 1
2208 18:13:55.911058 ===================================
2209 18:13:55.914087 ===================================
2210 18:13:55.917632 data_rate = 2400
2211 18:13:55.917743 CKR = 1
2212 18:13:55.920580 DQ_P2S_RATIO = 8
2213 18:13:55.924334 ===================================
2214 18:13:55.927245 CA_P2S_RATIO = 8
2215 18:13:55.931028 DQ_CA_OPEN = 0
2216 18:13:55.933915 DQ_SEMI_OPEN = 0
2217 18:13:55.934037 CA_SEMI_OPEN = 0
2218 18:13:55.937621 CA_FULL_RATE = 0
2219 18:13:55.941205 DQ_CKDIV4_EN = 0
2220 18:13:55.944077 CA_CKDIV4_EN = 0
2221 18:13:55.947851 CA_PREDIV_EN = 0
2222 18:13:55.950808 PH8_DLY = 17
2223 18:13:55.950902 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 18:13:55.954293 DQ_AAMCK_DIV = 4
2225 18:13:55.957921 CA_AAMCK_DIV = 4
2226 18:13:55.961223 CA_ADMCK_DIV = 4
2227 18:13:55.964102 DQ_TRACK_CA_EN = 0
2228 18:13:55.967692 CA_PICK = 1200
2229 18:13:55.971238 CA_MCKIO = 1200
2230 18:13:55.971328 MCKIO_SEMI = 0
2231 18:13:55.974050 PLL_FREQ = 2366
2232 18:13:55.977695 DQ_UI_PI_RATIO = 32
2233 18:13:55.981234 CA_UI_PI_RATIO = 0
2234 18:13:55.984010 ===================================
2235 18:13:55.987586 ===================================
2236 18:13:55.991006 memory_type:LPDDR4
2237 18:13:55.991098 GP_NUM : 10
2238 18:13:55.993964 SRAM_EN : 1
2239 18:13:55.997470 MD32_EN : 0
2240 18:13:56.000976 ===================================
2241 18:13:56.001071 [ANA_INIT] >>>>>>>>>>>>>>
2242 18:13:56.004735 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 18:13:56.007459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 18:13:56.011010 ===================================
2245 18:13:56.014443 data_rate = 2400,PCW = 0X5b00
2246 18:13:56.017271 ===================================
2247 18:13:56.021135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 18:13:56.027572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 18:13:56.030556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 18:13:56.037312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 18:13:56.040962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 18:13:56.043813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 18:13:56.043970 [ANA_INIT] flow start
2254 18:13:56.047521 [ANA_INIT] PLL >>>>>>>>
2255 18:13:56.050538 [ANA_INIT] PLL <<<<<<<<
2256 18:13:56.050687 [ANA_INIT] MIDPI >>>>>>>>
2257 18:13:56.054116 [ANA_INIT] MIDPI <<<<<<<<
2258 18:13:56.057843 [ANA_INIT] DLL >>>>>>>>
2259 18:13:56.057956 [ANA_INIT] DLL <<<<<<<<
2260 18:13:56.060897 [ANA_INIT] flow end
2261 18:13:56.064262 ============ LP4 DIFF to SE enter ============
2262 18:13:56.067330 ============ LP4 DIFF to SE exit ============
2263 18:13:56.070938 [ANA_INIT] <<<<<<<<<<<<<
2264 18:13:56.073915 [Flow] Enable top DCM control >>>>>
2265 18:13:56.077932 [Flow] Enable top DCM control <<<<<
2266 18:13:56.080959 Enable DLL master slave shuffle
2267 18:13:56.087549 ==============================================================
2268 18:13:56.087668 Gating Mode config
2269 18:13:56.094664 ==============================================================
2270 18:13:56.094752 Config description:
2271 18:13:56.103976 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 18:13:56.110962 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 18:13:56.117796 SELPH_MODE 0: By rank 1: By Phase
2274 18:13:56.121117 ==============================================================
2275 18:13:56.124059 GAT_TRACK_EN = 1
2276 18:13:56.127810 RX_GATING_MODE = 2
2277 18:13:56.131412 RX_GATING_TRACK_MODE = 2
2278 18:13:56.134314 SELPH_MODE = 1
2279 18:13:56.137854 PICG_EARLY_EN = 1
2280 18:13:56.140932 VALID_LAT_VALUE = 1
2281 18:13:56.144566 ==============================================================
2282 18:13:56.147667 Enter into Gating configuration >>>>
2283 18:13:56.151103 Exit from Gating configuration <<<<
2284 18:13:56.154706 Enter into DVFS_PRE_config >>>>>
2285 18:13:56.167900 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 18:13:56.171538 Exit from DVFS_PRE_config <<<<<
2287 18:13:56.174155 Enter into PICG configuration >>>>
2288 18:13:56.174237 Exit from PICG configuration <<<<
2289 18:13:56.177915 [RX_INPUT] configuration >>>>>
2290 18:13:56.181382 [RX_INPUT] configuration <<<<<
2291 18:13:56.187987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 18:13:56.191537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 18:13:56.198131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 18:13:56.204531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 18:13:56.211380 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 18:13:56.217770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 18:13:56.221356 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 18:13:56.224917 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 18:13:56.228204 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 18:13:56.234963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 18:13:56.237588 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 18:13:56.241345 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 18:13:56.244294 ===================================
2304 18:13:56.248014 LPDDR4 DRAM CONFIGURATION
2305 18:13:56.250969 ===================================
2306 18:13:56.251079 EX_ROW_EN[0] = 0x0
2307 18:13:56.254560 EX_ROW_EN[1] = 0x0
2308 18:13:56.257563 LP4Y_EN = 0x0
2309 18:13:56.257649 WORK_FSP = 0x0
2310 18:13:56.261260 WL = 0x4
2311 18:13:56.261351 RL = 0x4
2312 18:13:56.264793 BL = 0x2
2313 18:13:56.264911 RPST = 0x0
2314 18:13:56.267487 RD_PRE = 0x0
2315 18:13:56.267576 WR_PRE = 0x1
2316 18:13:56.271062 WR_PST = 0x0
2317 18:13:56.271161 DBI_WR = 0x0
2318 18:13:56.274823 DBI_RD = 0x0
2319 18:13:56.274906 OTF = 0x1
2320 18:13:56.278015 ===================================
2321 18:13:56.281540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 18:13:56.287984 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 18:13:56.291605 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 18:13:56.294607 ===================================
2325 18:13:56.298103 LPDDR4 DRAM CONFIGURATION
2326 18:13:56.301135 ===================================
2327 18:13:56.301279 EX_ROW_EN[0] = 0x10
2328 18:13:56.304739 EX_ROW_EN[1] = 0x0
2329 18:13:56.304822 LP4Y_EN = 0x0
2330 18:13:56.308271 WORK_FSP = 0x0
2331 18:13:56.308416 WL = 0x4
2332 18:13:56.311072 RL = 0x4
2333 18:13:56.314566 BL = 0x2
2334 18:13:56.314647 RPST = 0x0
2335 18:13:56.318266 RD_PRE = 0x0
2336 18:13:56.318363 WR_PRE = 0x1
2337 18:13:56.321164 WR_PST = 0x0
2338 18:13:56.321245 DBI_WR = 0x0
2339 18:13:56.324933 DBI_RD = 0x0
2340 18:13:56.325078 OTF = 0x1
2341 18:13:56.328713 ===================================
2342 18:13:56.334421 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 18:13:56.334596 ==
2344 18:13:56.338120 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 18:13:56.341546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 18:13:56.341652 ==
2347 18:13:56.344382 [Duty_Offset_Calibration]
2348 18:13:56.344475 B0:2 B1:1 CA:1
2349 18:13:56.347735
2350 18:13:56.351015 [DutyScan_Calibration_Flow] k_type=0
2351 18:13:56.358901
2352 18:13:56.359113 ==CLK 0==
2353 18:13:56.362359 Final CLK duty delay cell = 0
2354 18:13:56.366036 [0] MAX Duty = 5187%(X100), DQS PI = 24
2355 18:13:56.368799 [0] MIN Duty = 4875%(X100), DQS PI = 0
2356 18:13:56.368889 [0] AVG Duty = 5031%(X100)
2357 18:13:56.372433
2358 18:13:56.372530 CH0 CLK Duty spec in!! Max-Min= 312%
2359 18:13:56.378982 [DutyScan_Calibration_Flow] ====Done====
2360 18:13:56.379104
2361 18:13:56.381870 [DutyScan_Calibration_Flow] k_type=1
2362 18:13:56.397799
2363 18:13:56.397931 ==DQS 0 ==
2364 18:13:56.400567 Final DQS duty delay cell = -4
2365 18:13:56.403918 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2366 18:13:56.407721 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2367 18:13:56.410736 [-4] AVG Duty = 4937%(X100)
2368 18:13:56.410857
2369 18:13:56.410952 ==DQS 1 ==
2370 18:13:56.414538 Final DQS duty delay cell = 0
2371 18:13:56.417285 [0] MAX Duty = 5156%(X100), DQS PI = 12
2372 18:13:56.420909 [0] MIN Duty = 5031%(X100), DQS PI = 32
2373 18:13:56.424670 [0] AVG Duty = 5093%(X100)
2374 18:13:56.424756
2375 18:13:56.427638 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2376 18:13:56.427720
2377 18:13:56.431299 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2378 18:13:56.434140 [DutyScan_Calibration_Flow] ====Done====
2379 18:13:56.434223
2380 18:13:56.437730 [DutyScan_Calibration_Flow] k_type=3
2381 18:13:56.454244
2382 18:13:56.454400 ==DQM 0 ==
2383 18:13:56.457718 Final DQM duty delay cell = 0
2384 18:13:56.461046 [0] MAX Duty = 5156%(X100), DQS PI = 30
2385 18:13:56.464427 [0] MIN Duty = 4875%(X100), DQS PI = 58
2386 18:13:56.468024 [0] AVG Duty = 5015%(X100)
2387 18:13:56.468141
2388 18:13:56.468244 ==DQM 1 ==
2389 18:13:56.471386 Final DQM duty delay cell = 0
2390 18:13:56.474868 [0] MAX Duty = 5093%(X100), DQS PI = 0
2391 18:13:56.477736 [0] MIN Duty = 5031%(X100), DQS PI = 14
2392 18:13:56.477826 [0] AVG Duty = 5062%(X100)
2393 18:13:56.481222
2394 18:13:56.484201 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2395 18:13:56.484313
2396 18:13:56.487850 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2397 18:13:56.491383 [DutyScan_Calibration_Flow] ====Done====
2398 18:13:56.491469
2399 18:13:56.494283 [DutyScan_Calibration_Flow] k_type=2
2400 18:13:56.511178
2401 18:13:56.511334 ==DQ 0 ==
2402 18:13:56.514044 Final DQ duty delay cell = 0
2403 18:13:56.517820 [0] MAX Duty = 5062%(X100), DQS PI = 32
2404 18:13:56.520555 [0] MIN Duty = 4844%(X100), DQS PI = 62
2405 18:13:56.520658 [0] AVG Duty = 4953%(X100)
2406 18:13:56.524030
2407 18:13:56.524139 ==DQ 1 ==
2408 18:13:56.527851 Final DQ duty delay cell = 0
2409 18:13:56.530823 [0] MAX Duty = 5093%(X100), DQS PI = 24
2410 18:13:56.534619 [0] MIN Duty = 4907%(X100), DQS PI = 36
2411 18:13:56.534742 [0] AVG Duty = 5000%(X100)
2412 18:13:56.534836
2413 18:13:56.537583 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2414 18:13:56.540600
2415 18:13:56.544206 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2416 18:13:56.547829 [DutyScan_Calibration_Flow] ====Done====
2417 18:13:56.547953 ==
2418 18:13:56.550735 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 18:13:56.554345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 18:13:56.554458 ==
2421 18:13:56.557343 [Duty_Offset_Calibration]
2422 18:13:56.557445 B0:1 B1:0 CA:0
2423 18:13:56.557536
2424 18:13:56.560901 [DutyScan_Calibration_Flow] k_type=0
2425 18:13:56.570208
2426 18:13:56.570327 ==CLK 0==
2427 18:13:56.573818 Final CLK duty delay cell = -4
2428 18:13:56.576595 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2429 18:13:56.580442 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2430 18:13:56.583675 [-4] AVG Duty = 4969%(X100)
2431 18:13:56.583757
2432 18:13:56.586883 CH1 CLK Duty spec in!! Max-Min= 124%
2433 18:13:56.590297 [DutyScan_Calibration_Flow] ====Done====
2434 18:13:56.590376
2435 18:13:56.593728 [DutyScan_Calibration_Flow] k_type=1
2436 18:13:56.609617
2437 18:13:56.609748 ==DQS 0 ==
2438 18:13:56.613000 Final DQS duty delay cell = 0
2439 18:13:56.616438 [0] MAX Duty = 5062%(X100), DQS PI = 22
2440 18:13:56.620072 [0] MIN Duty = 4844%(X100), DQS PI = 0
2441 18:13:56.620156 [0] AVG Duty = 4953%(X100)
2442 18:13:56.623689
2443 18:13:56.623767 ==DQS 1 ==
2444 18:13:56.626981 Final DQS duty delay cell = 0
2445 18:13:56.629952 [0] MAX Duty = 5187%(X100), DQS PI = 18
2446 18:13:56.633569 [0] MIN Duty = 4938%(X100), DQS PI = 10
2447 18:13:56.633674 [0] AVG Duty = 5062%(X100)
2448 18:13:56.633765
2449 18:13:56.640028 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2450 18:13:56.640136
2451 18:13:56.643161 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2452 18:13:56.646739 [DutyScan_Calibration_Flow] ====Done====
2453 18:13:56.646844
2454 18:13:56.649683 [DutyScan_Calibration_Flow] k_type=3
2455 18:13:56.666664
2456 18:13:56.666825 ==DQM 0 ==
2457 18:13:56.669363 Final DQM duty delay cell = 0
2458 18:13:56.673034 [0] MAX Duty = 5156%(X100), DQS PI = 6
2459 18:13:56.675945 [0] MIN Duty = 5031%(X100), DQS PI = 0
2460 18:13:56.676028 [0] AVG Duty = 5093%(X100)
2461 18:13:56.679377
2462 18:13:56.679466 ==DQM 1 ==
2463 18:13:56.683045 Final DQM duty delay cell = 0
2464 18:13:56.686726 [0] MAX Duty = 5031%(X100), DQS PI = 26
2465 18:13:56.689718 [0] MIN Duty = 4875%(X100), DQS PI = 52
2466 18:13:56.689798 [0] AVG Duty = 4953%(X100)
2467 18:13:56.689862
2468 18:13:56.696740 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2469 18:13:56.696827
2470 18:13:56.699827 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2471 18:13:56.702891 [DutyScan_Calibration_Flow] ====Done====
2472 18:13:56.702980
2473 18:13:56.706691 [DutyScan_Calibration_Flow] k_type=2
2474 18:13:56.722484
2475 18:13:56.722598 ==DQ 0 ==
2476 18:13:56.725087 Final DQ duty delay cell = -4
2477 18:13:56.728522 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2478 18:13:56.732069 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2479 18:13:56.735618 [-4] AVG Duty = 5000%(X100)
2480 18:13:56.735733
2481 18:13:56.735834 ==DQ 1 ==
2482 18:13:56.738457 Final DQ duty delay cell = 0
2483 18:13:56.742559 [0] MAX Duty = 5125%(X100), DQS PI = 20
2484 18:13:56.745434 [0] MIN Duty = 4969%(X100), DQS PI = 12
2485 18:13:56.745514 [0] AVG Duty = 5047%(X100)
2486 18:13:56.749101
2487 18:13:56.751863 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2488 18:13:56.751973
2489 18:13:56.756295 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2490 18:13:56.759140 [DutyScan_Calibration_Flow] ====Done====
2491 18:13:56.762035 nWR fixed to 30
2492 18:13:56.762139 [ModeRegInit_LP4] CH0 RK0
2493 18:13:56.765856 [ModeRegInit_LP4] CH0 RK1
2494 18:13:56.768753 [ModeRegInit_LP4] CH1 RK0
2495 18:13:56.768829 [ModeRegInit_LP4] CH1 RK1
2496 18:13:56.772520 match AC timing 7
2497 18:13:56.775387 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 18:13:56.778995 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 18:13:56.785589 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 18:13:56.789271 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 18:13:56.795905 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 18:13:56.796016 ==
2503 18:13:56.798917 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 18:13:56.802043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 18:13:56.802149 ==
2506 18:13:56.809223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 18:13:56.811932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 18:13:56.822482 [CA 0] Center 39 (8~70) winsize 63
2509 18:13:56.825566 [CA 1] Center 39 (8~70) winsize 63
2510 18:13:56.828753 [CA 2] Center 35 (5~66) winsize 62
2511 18:13:56.832471 [CA 3] Center 34 (4~65) winsize 62
2512 18:13:56.835650 [CA 4] Center 33 (3~64) winsize 62
2513 18:13:56.839020 [CA 5] Center 32 (3~62) winsize 60
2514 18:13:56.839125
2515 18:13:56.842601 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2516 18:13:56.842694
2517 18:13:56.846087 [CATrainingPosCal] consider 1 rank data
2518 18:13:56.848951 u2DelayCellTimex100 = 270/100 ps
2519 18:13:56.852142 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2520 18:13:56.856030 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2521 18:13:56.862589 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2522 18:13:56.865525 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2523 18:13:56.869157 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2524 18:13:56.872043 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2525 18:13:56.872118
2526 18:13:56.875747 CA PerBit enable=1, Macro0, CA PI delay=32
2527 18:13:56.875854
2528 18:13:56.879424 [CBTSetCACLKResult] CA Dly = 32
2529 18:13:56.879527 CS Dly: 6 (0~37)
2530 18:13:56.879625 ==
2531 18:13:56.882396 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 18:13:56.888988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 18:13:56.889080 ==
2534 18:13:56.892682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 18:13:56.898633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2536 18:13:56.908316 [CA 0] Center 38 (8~69) winsize 62
2537 18:13:56.911342 [CA 1] Center 38 (8~69) winsize 62
2538 18:13:56.915178 [CA 2] Center 35 (4~66) winsize 63
2539 18:13:56.918067 [CA 3] Center 34 (4~65) winsize 62
2540 18:13:56.921139 [CA 4] Center 33 (3~64) winsize 62
2541 18:13:56.924757 [CA 5] Center 32 (3~62) winsize 60
2542 18:13:56.924844
2543 18:13:56.928373 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 18:13:56.928450
2545 18:13:56.931128 [CATrainingPosCal] consider 2 rank data
2546 18:13:56.934710 u2DelayCellTimex100 = 270/100 ps
2547 18:13:56.937908 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2548 18:13:56.941380 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2549 18:13:56.947881 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2550 18:13:56.951241 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2551 18:13:56.954932 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2552 18:13:56.958502 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2553 18:13:56.958589
2554 18:13:56.961067 CA PerBit enable=1, Macro0, CA PI delay=32
2555 18:13:56.961161
2556 18:13:56.965054 [CBTSetCACLKResult] CA Dly = 32
2557 18:13:56.965138 CS Dly: 6 (0~38)
2558 18:13:56.965223
2559 18:13:56.968184 ----->DramcWriteLeveling(PI) begin...
2560 18:13:56.971260 ==
2561 18:13:56.974396 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 18:13:56.978089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 18:13:56.978177 ==
2564 18:13:56.981124 Write leveling (Byte 0): 35 => 35
2565 18:13:56.984437 Write leveling (Byte 1): 30 => 30
2566 18:13:56.987818 DramcWriteLeveling(PI) end<-----
2567 18:13:56.987901
2568 18:13:56.987973 ==
2569 18:13:56.991577 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 18:13:56.994320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 18:13:56.994408 ==
2572 18:13:56.997941 [Gating] SW mode calibration
2573 18:13:57.004389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 18:13:57.011168 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 18:13:57.014103 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2576 18:13:57.017944 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2577 18:13:57.024624 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 18:13:57.027713 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 18:13:57.031322 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 18:13:57.034281 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 18:13:57.041388 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2582 18:13:57.044160 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
2583 18:13:57.047544 1 0 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2584 18:13:57.054876 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 18:13:57.058109 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 18:13:57.061405 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 18:13:57.067638 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 18:13:57.071407 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 18:13:57.074254 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2590 18:13:57.081157 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2591 18:13:57.084962 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2592 18:13:57.087640 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 18:13:57.094590 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 18:13:57.098044 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 18:13:57.101552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 18:13:57.107979 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 18:13:57.111160 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 18:13:57.114863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 18:13:57.121375 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 18:13:57.124467 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 18:13:57.128162 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 18:13:57.131122 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 18:13:57.137770 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 18:13:57.141587 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 18:13:57.144590 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 18:13:57.151161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 18:13:57.154597 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 18:13:57.157496 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 18:13:57.164915 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 18:13:57.167611 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 18:13:57.171058 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 18:13:57.178120 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 18:13:57.180964 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 18:13:57.184297 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2615 18:13:57.191345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2616 18:13:57.191472 Total UI for P1: 0, mck2ui 16
2617 18:13:57.194426 best dqsien dly found for B0: ( 1, 3, 28)
2618 18:13:57.201534 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 18:13:57.204535 Total UI for P1: 0, mck2ui 16
2620 18:13:57.208105 best dqsien dly found for B1: ( 1, 3, 30)
2621 18:13:57.210928 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2622 18:13:57.214535 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2623 18:13:57.214640
2624 18:13:57.218081 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2625 18:13:57.221547 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2626 18:13:57.224831 [Gating] SW calibration Done
2627 18:13:57.224918 ==
2628 18:13:57.228047 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 18:13:57.231540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 18:13:57.231624 ==
2631 18:13:57.234751 RX Vref Scan: 0
2632 18:13:57.234835
2633 18:13:57.234909 RX Vref 0 -> 0, step: 1
2634 18:13:57.238396
2635 18:13:57.238498 RX Delay -40 -> 252, step: 8
2636 18:13:57.244556 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2637 18:13:57.247990 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2638 18:13:57.251539 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2639 18:13:57.255224 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2640 18:13:57.258055 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2641 18:13:57.261701 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2642 18:13:57.267980 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2643 18:13:57.271656 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2644 18:13:57.274522 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2645 18:13:57.278108 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2646 18:13:57.281574 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2647 18:13:57.287730 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2648 18:13:57.291082 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2649 18:13:57.294853 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2650 18:13:57.297724 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2651 18:13:57.304947 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2652 18:13:57.305067 ==
2653 18:13:57.307705 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 18:13:57.311513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 18:13:57.311612 ==
2656 18:13:57.311707 DQS Delay:
2657 18:13:57.314590 DQS0 = 0, DQS1 = 0
2658 18:13:57.314670 DQM Delay:
2659 18:13:57.317964 DQM0 = 121, DQM1 = 113
2660 18:13:57.318070 DQ Delay:
2661 18:13:57.321640 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2662 18:13:57.324603 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2663 18:13:57.328564 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2664 18:13:57.331507 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2665 18:13:57.331588
2666 18:13:57.331653
2667 18:13:57.331711 ==
2668 18:13:57.335011 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 18:13:57.341235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 18:13:57.341323 ==
2671 18:13:57.341390
2672 18:13:57.341457
2673 18:13:57.341520 TX Vref Scan disable
2674 18:13:57.344815 == TX Byte 0 ==
2675 18:13:57.348207 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2676 18:13:57.355270 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2677 18:13:57.355385 == TX Byte 1 ==
2678 18:13:57.358125 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2679 18:13:57.361919 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2680 18:13:57.364855 ==
2681 18:13:57.368379 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 18:13:57.371903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 18:13:57.372025 ==
2684 18:13:57.383233 TX Vref=22, minBit 1, minWin=24, winSum=403
2685 18:13:57.386735 TX Vref=24, minBit 1, minWin=25, winSum=408
2686 18:13:57.389527 TX Vref=26, minBit 13, minWin=25, winSum=419
2687 18:13:57.392872 TX Vref=28, minBit 12, minWin=25, winSum=421
2688 18:13:57.396461 TX Vref=30, minBit 5, minWin=25, winSum=420
2689 18:13:57.403449 TX Vref=32, minBit 4, minWin=25, winSum=419
2690 18:13:57.406294 [TxChooseVref] Worse bit 12, Min win 25, Win sum 421, Final Vref 28
2691 18:13:57.406382
2692 18:13:57.409784 Final TX Range 1 Vref 28
2693 18:13:57.409865
2694 18:13:57.409943 ==
2695 18:13:57.413443 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 18:13:57.416298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 18:13:57.420011 ==
2698 18:13:57.420090
2699 18:13:57.420154
2700 18:13:57.420244 TX Vref Scan disable
2701 18:13:57.423503 == TX Byte 0 ==
2702 18:13:57.426515 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2703 18:13:57.430206 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2704 18:13:57.433143 == TX Byte 1 ==
2705 18:13:57.436170 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2706 18:13:57.439851 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2707 18:13:57.443345
2708 18:13:57.443427 [DATLAT]
2709 18:13:57.443491 Freq=1200, CH0 RK0
2710 18:13:57.443551
2711 18:13:57.446275 DATLAT Default: 0xd
2712 18:13:57.446360 0, 0xFFFF, sum = 0
2713 18:13:57.450003 1, 0xFFFF, sum = 0
2714 18:13:57.450097 2, 0xFFFF, sum = 0
2715 18:13:57.453591 3, 0xFFFF, sum = 0
2716 18:13:57.456423 4, 0xFFFF, sum = 0
2717 18:13:57.456509 5, 0xFFFF, sum = 0
2718 18:13:57.459695 6, 0xFFFF, sum = 0
2719 18:13:57.459786 7, 0xFFFF, sum = 0
2720 18:13:57.462876 8, 0xFFFF, sum = 0
2721 18:13:57.462958 9, 0xFFFF, sum = 0
2722 18:13:57.466283 10, 0xFFFF, sum = 0
2723 18:13:57.466381 11, 0xFFFF, sum = 0
2724 18:13:57.469520 12, 0x0, sum = 1
2725 18:13:57.469602 13, 0x0, sum = 2
2726 18:13:57.473202 14, 0x0, sum = 3
2727 18:13:57.473279 15, 0x0, sum = 4
2728 18:13:57.473343 best_step = 13
2729 18:13:57.473420
2730 18:13:57.476754 ==
2731 18:13:57.479754 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 18:13:57.483374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 18:13:57.483457 ==
2734 18:13:57.483527 RX Vref Scan: 1
2735 18:13:57.483617
2736 18:13:57.486755 Set Vref Range= 32 -> 127
2737 18:13:57.486830
2738 18:13:57.490203 RX Vref 32 -> 127, step: 1
2739 18:13:57.490284
2740 18:13:57.493127 RX Delay -13 -> 252, step: 4
2741 18:13:57.493209
2742 18:13:57.496699 Set Vref, RX VrefLevel [Byte0]: 32
2743 18:13:57.499592 [Byte1]: 32
2744 18:13:57.499673
2745 18:13:57.503195 Set Vref, RX VrefLevel [Byte0]: 33
2746 18:13:57.506853 [Byte1]: 33
2747 18:13:57.506945
2748 18:13:57.510053 Set Vref, RX VrefLevel [Byte0]: 34
2749 18:13:57.513243 [Byte1]: 34
2750 18:13:57.517755
2751 18:13:57.517839 Set Vref, RX VrefLevel [Byte0]: 35
2752 18:13:57.521056 [Byte1]: 35
2753 18:13:57.525360
2754 18:13:57.525441 Set Vref, RX VrefLevel [Byte0]: 36
2755 18:13:57.528992 [Byte1]: 36
2756 18:13:57.533278
2757 18:13:57.533354 Set Vref, RX VrefLevel [Byte0]: 37
2758 18:13:57.536324 [Byte1]: 37
2759 18:13:57.541546
2760 18:13:57.541629 Set Vref, RX VrefLevel [Byte0]: 38
2761 18:13:57.544605 [Byte1]: 38
2762 18:13:57.548954
2763 18:13:57.549036 Set Vref, RX VrefLevel [Byte0]: 39
2764 18:13:57.552015 [Byte1]: 39
2765 18:13:57.557237
2766 18:13:57.557318 Set Vref, RX VrefLevel [Byte0]: 40
2767 18:13:57.560127 [Byte1]: 40
2768 18:13:57.564766
2769 18:13:57.564848 Set Vref, RX VrefLevel [Byte0]: 41
2770 18:13:57.568301 [Byte1]: 41
2771 18:13:57.572936
2772 18:13:57.573046 Set Vref, RX VrefLevel [Byte0]: 42
2773 18:13:57.575613 [Byte1]: 42
2774 18:13:57.580268
2775 18:13:57.580393 Set Vref, RX VrefLevel [Byte0]: 43
2776 18:13:57.583744 [Byte1]: 43
2777 18:13:57.588782
2778 18:13:57.588866 Set Vref, RX VrefLevel [Byte0]: 44
2779 18:13:57.591726 [Byte1]: 44
2780 18:13:57.596630
2781 18:13:57.596712 Set Vref, RX VrefLevel [Byte0]: 45
2782 18:13:57.599410 [Byte1]: 45
2783 18:13:57.604074
2784 18:13:57.604188 Set Vref, RX VrefLevel [Byte0]: 46
2785 18:13:57.607700 [Byte1]: 46
2786 18:13:57.612015
2787 18:13:57.612100 Set Vref, RX VrefLevel [Byte0]: 47
2788 18:13:57.615831 [Byte1]: 47
2789 18:13:57.620082
2790 18:13:57.620161 Set Vref, RX VrefLevel [Byte0]: 48
2791 18:13:57.623507 [Byte1]: 48
2792 18:13:57.628141
2793 18:13:57.628222 Set Vref, RX VrefLevel [Byte0]: 49
2794 18:13:57.631314 [Byte1]: 49
2795 18:13:57.635927
2796 18:13:57.636010 Set Vref, RX VrefLevel [Byte0]: 50
2797 18:13:57.639051 [Byte1]: 50
2798 18:13:57.644004
2799 18:13:57.644113 Set Vref, RX VrefLevel [Byte0]: 51
2800 18:13:57.646873 [Byte1]: 51
2801 18:13:57.651521
2802 18:13:57.651594 Set Vref, RX VrefLevel [Byte0]: 52
2803 18:13:57.654961 [Byte1]: 52
2804 18:13:57.659363
2805 18:13:57.659444 Set Vref, RX VrefLevel [Byte0]: 53
2806 18:13:57.663016 [Byte1]: 53
2807 18:13:57.667360
2808 18:13:57.667441 Set Vref, RX VrefLevel [Byte0]: 54
2809 18:13:57.670929 [Byte1]: 54
2810 18:13:57.675134
2811 18:13:57.675239 Set Vref, RX VrefLevel [Byte0]: 55
2812 18:13:57.678792 [Byte1]: 55
2813 18:13:57.683001
2814 18:13:57.683081 Set Vref, RX VrefLevel [Byte0]: 56
2815 18:13:57.686691 [Byte1]: 56
2816 18:13:57.691361
2817 18:13:57.691445 Set Vref, RX VrefLevel [Byte0]: 57
2818 18:13:57.694723 [Byte1]: 57
2819 18:13:57.698828
2820 18:13:57.698905 Set Vref, RX VrefLevel [Byte0]: 58
2821 18:13:57.701944 [Byte1]: 58
2822 18:13:57.707127
2823 18:13:57.707206 Set Vref, RX VrefLevel [Byte0]: 59
2824 18:13:57.709870 [Byte1]: 59
2825 18:13:57.714373
2826 18:13:57.714449 Set Vref, RX VrefLevel [Byte0]: 60
2827 18:13:57.717778 [Byte1]: 60
2828 18:13:57.722988
2829 18:13:57.723088 Set Vref, RX VrefLevel [Byte0]: 61
2830 18:13:57.725916 [Byte1]: 61
2831 18:13:57.730207
2832 18:13:57.730308 Set Vref, RX VrefLevel [Byte0]: 62
2833 18:13:57.733975 [Byte1]: 62
2834 18:13:57.738346
2835 18:13:57.738425 Set Vref, RX VrefLevel [Byte0]: 63
2836 18:13:57.741959 [Byte1]: 63
2837 18:13:57.746145
2838 18:13:57.746243 Set Vref, RX VrefLevel [Byte0]: 64
2839 18:13:57.749362 [Byte1]: 64
2840 18:13:57.754410
2841 18:13:57.754493 Set Vref, RX VrefLevel [Byte0]: 65
2842 18:13:57.757741 [Byte1]: 65
2843 18:13:57.762239
2844 18:13:57.762322 Set Vref, RX VrefLevel [Byte0]: 66
2845 18:13:57.765266 [Byte1]: 66
2846 18:13:57.769732
2847 18:13:57.769813 Set Vref, RX VrefLevel [Byte0]: 67
2848 18:13:57.773355 [Byte1]: 67
2849 18:13:57.777925
2850 18:13:57.778006 Set Vref, RX VrefLevel [Byte0]: 68
2851 18:13:57.780845 [Byte1]: 68
2852 18:13:57.786022
2853 18:13:57.786103 Set Vref, RX VrefLevel [Byte0]: 69
2854 18:13:57.788898 [Byte1]: 69
2855 18:13:57.793875
2856 18:13:57.793956 Final RX Vref Byte 0 = 57 to rank0
2857 18:13:57.796743 Final RX Vref Byte 1 = 45 to rank0
2858 18:13:57.800107 Final RX Vref Byte 0 = 57 to rank1
2859 18:13:57.803801 Final RX Vref Byte 1 = 45 to rank1==
2860 18:13:57.806628 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 18:13:57.813424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 18:13:57.813507 ==
2863 18:13:57.813572 DQS Delay:
2864 18:13:57.813633 DQS0 = 0, DQS1 = 0
2865 18:13:57.816905 DQM Delay:
2866 18:13:57.816987 DQM0 = 121, DQM1 = 110
2867 18:13:57.820443 DQ Delay:
2868 18:13:57.823481 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2869 18:13:57.826864 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2870 18:13:57.830331 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2871 18:13:57.833599 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2872 18:13:57.833686
2873 18:13:57.833773
2874 18:13:57.840097 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2875 18:13:57.843881 CH0 RK0: MR19=404, MR18=160F
2876 18:13:57.850469 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2877 18:13:57.850555
2878 18:13:57.853350 ----->DramcWriteLeveling(PI) begin...
2879 18:13:57.853429 ==
2880 18:13:57.856868 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 18:13:57.860324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 18:13:57.860457 ==
2883 18:13:57.863843 Write leveling (Byte 0): 36 => 36
2884 18:13:57.866737 Write leveling (Byte 1): 28 => 28
2885 18:13:57.870203 DramcWriteLeveling(PI) end<-----
2886 18:13:57.870299
2887 18:13:57.870391 ==
2888 18:13:57.873372 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 18:13:57.879989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 18:13:57.880081 ==
2891 18:13:57.880147 [Gating] SW mode calibration
2892 18:13:57.890368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 18:13:57.893305 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 18:13:57.896742 0 15 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2895 18:13:57.904021 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 18:13:57.907107 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 18:13:57.910039 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 18:13:57.916604 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 18:13:57.920172 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 18:13:57.923703 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 18:13:57.930295 0 15 28 | B1->B0 | 2c2c 2929 | 0 0 | (1 0) (1 0)
2902 18:13:57.933767 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2903 18:13:57.937183 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 18:13:57.943296 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 18:13:57.947188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 18:13:57.950764 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 18:13:57.957066 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 18:13:57.960571 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 18:13:57.963438 1 0 28 | B1->B0 | 3737 3535 | 0 0 | (1 1) (0 0)
2910 18:13:57.969986 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 18:13:57.973809 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 18:13:57.976617 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 18:13:57.980059 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 18:13:57.986836 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 18:13:57.990076 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 18:13:57.993727 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 18:13:58.000333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 18:13:58.003257 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2919 18:13:58.007013 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 18:13:58.013599 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 18:13:58.016665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 18:13:58.020359 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 18:13:58.026942 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 18:13:58.029861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 18:13:58.033266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 18:13:58.040311 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 18:13:58.043297 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 18:13:58.046738 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 18:13:58.053738 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 18:13:58.056526 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 18:13:58.060363 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 18:13:58.066772 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2933 18:13:58.070407 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 18:13:58.073672 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2935 18:13:58.080636 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 18:13:58.080726 Total UI for P1: 0, mck2ui 16
2937 18:13:58.083608 best dqsien dly found for B0: ( 1, 3, 30)
2938 18:13:58.087187 Total UI for P1: 0, mck2ui 16
2939 18:13:58.090145 best dqsien dly found for B1: ( 1, 3, 28)
2940 18:13:58.093854 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2941 18:13:58.096824 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2942 18:13:58.100221
2943 18:13:58.103486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2944 18:13:58.106859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2945 18:13:58.110499 [Gating] SW calibration Done
2946 18:13:58.110592 ==
2947 18:13:58.113272 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 18:13:58.116913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 18:13:58.116997 ==
2950 18:13:58.117063 RX Vref Scan: 0
2951 18:13:58.117125
2952 18:13:58.120771 RX Vref 0 -> 0, step: 1
2953 18:13:58.120854
2954 18:13:58.123598 RX Delay -40 -> 252, step: 8
2955 18:13:58.127489 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2956 18:13:58.130250 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2957 18:13:58.136773 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2958 18:13:58.140318 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2959 18:13:58.143987 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2960 18:13:58.146912 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2961 18:13:58.150610 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2962 18:13:58.153375 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2963 18:13:58.159939 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2964 18:13:58.163589 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2965 18:13:58.167291 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2966 18:13:58.170548 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2967 18:13:58.173467 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2968 18:13:58.180271 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2969 18:13:58.183843 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2970 18:13:58.187270 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2971 18:13:58.187372 ==
2972 18:13:58.190557 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 18:13:58.193895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 18:13:58.194004 ==
2975 18:13:58.197633 DQS Delay:
2976 18:13:58.197741 DQS0 = 0, DQS1 = 0
2977 18:13:58.200668 DQM Delay:
2978 18:13:58.200741 DQM0 = 122, DQM1 = 112
2979 18:13:58.203612 DQ Delay:
2980 18:13:58.207187 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2981 18:13:58.210772 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2982 18:13:58.214236 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2983 18:13:58.217347 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2984 18:13:58.217425
2985 18:13:58.217487
2986 18:13:58.217552 ==
2987 18:13:58.220463 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 18:13:58.224297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 18:13:58.224416 ==
2990 18:13:58.224510
2991 18:13:58.224608
2992 18:13:58.227304 TX Vref Scan disable
2993 18:13:58.230357 == TX Byte 0 ==
2994 18:13:58.234100 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2995 18:13:58.237017 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2996 18:13:58.240638 == TX Byte 1 ==
2997 18:13:58.244127 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2998 18:13:58.246959 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2999 18:13:58.247078 ==
3000 18:13:58.250607 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 18:13:58.253611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 18:13:58.257249 ==
3003 18:13:58.268093 TX Vref=22, minBit 1, minWin=25, winSum=412
3004 18:13:58.271052 TX Vref=24, minBit 3, minWin=25, winSum=420
3005 18:13:58.274786 TX Vref=26, minBit 3, minWin=25, winSum=420
3006 18:13:58.278303 TX Vref=28, minBit 5, minWin=25, winSum=421
3007 18:13:58.281633 TX Vref=30, minBit 5, minWin=25, winSum=424
3008 18:13:58.284414 TX Vref=32, minBit 5, minWin=25, winSum=429
3009 18:13:58.290949 [TxChooseVref] Worse bit 5, Min win 25, Win sum 429, Final Vref 32
3010 18:13:58.291063
3011 18:13:58.294625 Final TX Range 1 Vref 32
3012 18:13:58.294744
3013 18:13:58.294839 ==
3014 18:13:58.298042 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 18:13:58.301567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 18:13:58.301694 ==
3017 18:13:58.301801
3018 18:13:58.304324
3019 18:13:58.304443 TX Vref Scan disable
3020 18:13:58.308049 == TX Byte 0 ==
3021 18:13:58.311701 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3022 18:13:58.314513 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3023 18:13:58.318136 == TX Byte 1 ==
3024 18:13:58.321080 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3025 18:13:58.324537 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3026 18:13:58.324631
3027 18:13:58.327978 [DATLAT]
3028 18:13:58.328069 Freq=1200, CH0 RK1
3029 18:13:58.328136
3030 18:13:58.331252 DATLAT Default: 0xd
3031 18:13:58.331337 0, 0xFFFF, sum = 0
3032 18:13:58.334579 1, 0xFFFF, sum = 0
3033 18:13:58.334667 2, 0xFFFF, sum = 0
3034 18:13:58.337966 3, 0xFFFF, sum = 0
3035 18:13:58.338048 4, 0xFFFF, sum = 0
3036 18:13:58.341602 5, 0xFFFF, sum = 0
3037 18:13:58.341686 6, 0xFFFF, sum = 0
3038 18:13:58.344524 7, 0xFFFF, sum = 0
3039 18:13:58.344607 8, 0xFFFF, sum = 0
3040 18:13:58.348038 9, 0xFFFF, sum = 0
3041 18:13:58.348123 10, 0xFFFF, sum = 0
3042 18:13:58.351688 11, 0xFFFF, sum = 0
3043 18:13:58.354568 12, 0x0, sum = 1
3044 18:13:58.354651 13, 0x0, sum = 2
3045 18:13:58.354717 14, 0x0, sum = 3
3046 18:13:58.358399 15, 0x0, sum = 4
3047 18:13:58.358472 best_step = 13
3048 18:13:58.358532
3049 18:13:58.358588 ==
3050 18:13:58.361302 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 18:13:58.368435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 18:13:58.368519 ==
3053 18:13:58.368584 RX Vref Scan: 0
3054 18:13:58.368644
3055 18:13:58.371410 RX Vref 0 -> 0, step: 1
3056 18:13:58.371491
3057 18:13:58.375027 RX Delay -13 -> 252, step: 4
3058 18:13:58.378102 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3059 18:13:58.381858 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3060 18:13:58.388267 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3061 18:13:58.391111 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3062 18:13:58.395110 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3063 18:13:58.398624 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3064 18:13:58.401620 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3065 18:13:58.405332 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3066 18:13:58.411861 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3067 18:13:58.414828 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3068 18:13:58.418656 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3069 18:13:58.421588 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3070 18:13:58.425376 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3071 18:13:58.431900 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3072 18:13:58.434957 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3073 18:13:58.438612 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3074 18:13:58.438695 ==
3075 18:13:58.442005 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 18:13:58.444817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 18:13:58.448603 ==
3078 18:13:58.448686 DQS Delay:
3079 18:13:58.448751 DQS0 = 0, DQS1 = 0
3080 18:13:58.451877 DQM Delay:
3081 18:13:58.451963 DQM0 = 120, DQM1 = 109
3082 18:13:58.455134 DQ Delay:
3083 18:13:58.458292 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3084 18:13:58.461776 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3085 18:13:58.464956 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3086 18:13:58.468835 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3087 18:13:58.468920
3088 18:13:58.468984
3089 18:13:58.475314 [DQSOSCAuto] RK1, (LSB)MR18= 0xbec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3090 18:13:58.478342 CH0 RK1: MR19=403, MR18=BEC
3091 18:13:58.484899 CH0_RK1: MR19=0x403, MR18=0xBEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3092 18:13:58.488581 [RxdqsGatingPostProcess] freq 1200
3093 18:13:58.492248 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 18:13:58.495333 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 18:13:58.498677 best DQS1 dly(2T, 0.5T) = (0, 11)
3096 18:13:58.501575 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 18:13:58.505162 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3098 18:13:58.508819 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 18:13:58.511693 best DQS1 dly(2T, 0.5T) = (0, 11)
3100 18:13:58.515069 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 18:13:58.518417 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3102 18:13:58.521869 Pre-setting of DQS Precalculation
3103 18:13:58.524748 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 18:13:58.528448 ==
3105 18:13:58.531315 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 18:13:58.535140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 18:13:58.535226 ==
3108 18:13:58.538287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 18:13:58.545078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 18:13:58.553902 [CA 0] Center 37 (7~68) winsize 62
3111 18:13:58.557322 [CA 1] Center 37 (7~68) winsize 62
3112 18:13:58.560944 [CA 2] Center 35 (5~65) winsize 61
3113 18:13:58.564301 [CA 3] Center 34 (4~64) winsize 61
3114 18:13:58.567772 [CA 4] Center 34 (4~64) winsize 61
3115 18:13:58.570938 [CA 5] Center 33 (3~63) winsize 61
3116 18:13:58.571018
3117 18:13:58.574321 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3118 18:13:58.574402
3119 18:13:58.577850 [CATrainingPosCal] consider 1 rank data
3120 18:13:58.580695 u2DelayCellTimex100 = 270/100 ps
3121 18:13:58.584293 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 18:13:58.587854 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 18:13:58.593917 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 18:13:58.597517 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 18:13:58.600573 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 18:13:58.604346 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 18:13:58.604443
3128 18:13:58.607353 CA PerBit enable=1, Macro0, CA PI delay=33
3129 18:13:58.607459
3130 18:13:58.611213 [CBTSetCACLKResult] CA Dly = 33
3131 18:13:58.611320 CS Dly: 7 (0~38)
3132 18:13:58.611415 ==
3133 18:13:58.614233 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 18:13:58.620920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 18:13:58.621002 ==
3136 18:13:58.624281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 18:13:58.631051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 18:13:58.639554 [CA 0] Center 37 (7~68) winsize 62
3139 18:13:58.643367 [CA 1] Center 37 (7~68) winsize 62
3140 18:13:58.646282 [CA 2] Center 35 (5~65) winsize 61
3141 18:13:58.649985 [CA 3] Center 35 (5~65) winsize 61
3142 18:13:58.653052 [CA 4] Center 34 (4~65) winsize 62
3143 18:13:58.656756 [CA 5] Center 34 (4~64) winsize 61
3144 18:13:58.656843
3145 18:13:58.659696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3146 18:13:58.659791
3147 18:13:58.663326 [CATrainingPosCal] consider 2 rank data
3148 18:13:58.666424 u2DelayCellTimex100 = 270/100 ps
3149 18:13:58.669987 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 18:13:58.672916 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 18:13:58.680124 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3152 18:13:58.682942 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3153 18:13:58.686349 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 18:13:58.689679 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3155 18:13:58.689760
3156 18:13:58.693117 CA PerBit enable=1, Macro0, CA PI delay=33
3157 18:13:58.693197
3158 18:13:58.696595 [CBTSetCACLKResult] CA Dly = 33
3159 18:13:58.696701 CS Dly: 8 (0~40)
3160 18:13:58.696792
3161 18:13:58.699588 ----->DramcWriteLeveling(PI) begin...
3162 18:13:58.699669 ==
3163 18:13:58.703081 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 18:13:58.709828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 18:13:58.709911 ==
3166 18:13:58.713481 Write leveling (Byte 0): 25 => 25
3167 18:13:58.716536 Write leveling (Byte 1): 27 => 27
3168 18:13:58.716619 DramcWriteLeveling(PI) end<-----
3169 18:13:58.719662
3170 18:13:58.719742 ==
3171 18:13:58.723371 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 18:13:58.726399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 18:13:58.726480 ==
3174 18:13:58.730207 [Gating] SW mode calibration
3175 18:13:58.736731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 18:13:58.740160 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 18:13:58.746940 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 18:13:58.749728 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 18:13:58.753535 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 18:13:58.759985 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 18:13:58.763523 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 18:13:58.766394 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 18:13:58.773004 0 15 24 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 0)
3184 18:13:58.776626 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3185 18:13:58.780180 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 18:13:58.786613 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 18:13:58.790285 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 18:13:58.793300 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 18:13:58.799695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 18:13:58.803113 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3191 18:13:58.806524 1 0 24 | B1->B0 | 3232 4040 | 0 1 | (0 0) (0 0)
3192 18:13:58.810312 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 18:13:58.817080 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 18:13:58.820354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 18:13:58.823367 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 18:13:58.830020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 18:13:58.833803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 18:13:58.836848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 18:13:58.843400 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 18:13:58.847020 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 18:13:58.850438 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 18:13:58.857081 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 18:13:58.860198 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 18:13:58.863708 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 18:13:58.870285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 18:13:58.873217 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 18:13:58.876887 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 18:13:58.880638 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 18:13:58.887071 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 18:13:58.889903 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 18:13:58.893772 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 18:13:58.900594 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 18:13:58.903348 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 18:13:58.907109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 18:13:58.913801 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 18:13:58.916646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 18:13:58.920062 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 18:13:58.923578 Total UI for P1: 0, mck2ui 16
3219 18:13:58.926871 best dqsien dly found for B0: ( 1, 3, 26)
3220 18:13:58.930221 Total UI for P1: 0, mck2ui 16
3221 18:13:58.933473 best dqsien dly found for B1: ( 1, 3, 26)
3222 18:13:58.937087 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3223 18:13:58.940643 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3224 18:13:58.940728
3225 18:13:58.947131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 18:13:58.950042 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3227 18:13:58.950124 [Gating] SW calibration Done
3228 18:13:58.953725 ==
3229 18:13:58.956701 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 18:13:58.960289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 18:13:58.960422 ==
3232 18:13:58.960488 RX Vref Scan: 0
3233 18:13:58.960548
3234 18:13:58.963281 RX Vref 0 -> 0, step: 1
3235 18:13:58.963361
3236 18:13:58.967110 RX Delay -40 -> 252, step: 8
3237 18:13:58.970222 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3238 18:13:58.973131 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3239 18:13:58.976591 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3240 18:13:58.983413 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3241 18:13:58.986796 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3242 18:13:58.990181 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3243 18:13:58.993527 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3244 18:13:58.996814 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3245 18:13:59.003387 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3246 18:13:59.006581 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3247 18:13:59.010270 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3248 18:13:59.013334 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3249 18:13:59.017177 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3250 18:13:59.023797 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3251 18:13:59.026762 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3252 18:13:59.030359 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3253 18:13:59.030439 ==
3254 18:13:59.033434 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 18:13:59.037191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 18:13:59.037274 ==
3257 18:13:59.040678 DQS Delay:
3258 18:13:59.040760 DQS0 = 0, DQS1 = 0
3259 18:13:59.043957 DQM Delay:
3260 18:13:59.044037 DQM0 = 119, DQM1 = 116
3261 18:13:59.044101 DQ Delay:
3262 18:13:59.047289 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3263 18:13:59.050265 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3264 18:13:59.056935 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3265 18:13:59.060630 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3266 18:13:59.060710
3267 18:13:59.060775
3268 18:13:59.060835 ==
3269 18:13:59.064074 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 18:13:59.066938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 18:13:59.067054 ==
3272 18:13:59.067174
3273 18:13:59.067293
3274 18:13:59.070446 TX Vref Scan disable
3275 18:13:59.070548 == TX Byte 0 ==
3276 18:13:59.077037 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3277 18:13:59.080855 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3278 18:13:59.080969 == TX Byte 1 ==
3279 18:13:59.087264 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3280 18:13:59.090936 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3281 18:13:59.091017 ==
3282 18:13:59.094392 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 18:13:59.096991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 18:13:59.097072 ==
3285 18:13:59.109984 TX Vref=22, minBit 11, minWin=24, winSum=412
3286 18:13:59.113283 TX Vref=24, minBit 9, minWin=25, winSum=418
3287 18:13:59.116859 TX Vref=26, minBit 10, minWin=25, winSum=424
3288 18:13:59.119778 TX Vref=28, minBit 2, minWin=26, winSum=427
3289 18:13:59.123336 TX Vref=30, minBit 1, minWin=26, winSum=430
3290 18:13:59.130025 TX Vref=32, minBit 11, minWin=25, winSum=426
3291 18:13:59.133680 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3292 18:13:59.133760
3293 18:13:59.136532 Final TX Range 1 Vref 30
3294 18:13:59.136612
3295 18:13:59.136675 ==
3296 18:13:59.140259 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 18:13:59.143231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 18:13:59.143311 ==
3299 18:13:59.146933
3300 18:13:59.147012
3301 18:13:59.147075 TX Vref Scan disable
3302 18:13:59.149859 == TX Byte 0 ==
3303 18:13:59.153475 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3304 18:13:59.157293 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3305 18:13:59.160116 == TX Byte 1 ==
3306 18:13:59.163667 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 18:13:59.166995 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 18:13:59.167090
3309 18:13:59.170220 [DATLAT]
3310 18:13:59.170351 Freq=1200, CH1 RK0
3311 18:13:59.170416
3312 18:13:59.173603 DATLAT Default: 0xd
3313 18:13:59.173683 0, 0xFFFF, sum = 0
3314 18:13:59.176519 1, 0xFFFF, sum = 0
3315 18:13:59.176602 2, 0xFFFF, sum = 0
3316 18:13:59.179893 3, 0xFFFF, sum = 0
3317 18:13:59.180013 4, 0xFFFF, sum = 0
3318 18:13:59.183360 5, 0xFFFF, sum = 0
3319 18:13:59.183463 6, 0xFFFF, sum = 0
3320 18:13:59.187176 7, 0xFFFF, sum = 0
3321 18:13:59.187264 8, 0xFFFF, sum = 0
3322 18:13:59.190228 9, 0xFFFF, sum = 0
3323 18:13:59.193279 10, 0xFFFF, sum = 0
3324 18:13:59.193362 11, 0xFFFF, sum = 0
3325 18:13:59.196952 12, 0x0, sum = 1
3326 18:13:59.197042 13, 0x0, sum = 2
3327 18:13:59.197138 14, 0x0, sum = 3
3328 18:13:59.200529 15, 0x0, sum = 4
3329 18:13:59.200612 best_step = 13
3330 18:13:59.200676
3331 18:13:59.203443 ==
3332 18:13:59.203555 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 18:13:59.209855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 18:13:59.209938 ==
3335 18:13:59.210001 RX Vref Scan: 1
3336 18:13:59.210061
3337 18:13:59.213415 Set Vref Range= 32 -> 127
3338 18:13:59.213545
3339 18:13:59.216886 RX Vref 32 -> 127, step: 1
3340 18:13:59.216967
3341 18:13:59.220251 RX Delay -5 -> 252, step: 4
3342 18:13:59.220333
3343 18:13:59.223509 Set Vref, RX VrefLevel [Byte0]: 32
3344 18:13:59.226882 [Byte1]: 32
3345 18:13:59.226963
3346 18:13:59.230171 Set Vref, RX VrefLevel [Byte0]: 33
3347 18:13:59.233879 [Byte1]: 33
3348 18:13:59.233962
3349 18:13:59.236761 Set Vref, RX VrefLevel [Byte0]: 34
3350 18:13:59.240080 [Byte1]: 34
3351 18:13:59.243918
3352 18:13:59.244000 Set Vref, RX VrefLevel [Byte0]: 35
3353 18:13:59.247727 [Byte1]: 35
3354 18:13:59.252131
3355 18:13:59.252243 Set Vref, RX VrefLevel [Byte0]: 36
3356 18:13:59.255007 [Byte1]: 36
3357 18:13:59.260046
3358 18:13:59.260128 Set Vref, RX VrefLevel [Byte0]: 37
3359 18:13:59.262876 [Byte1]: 37
3360 18:13:59.267430
3361 18:13:59.267512 Set Vref, RX VrefLevel [Byte0]: 38
3362 18:13:59.271138 [Byte1]: 38
3363 18:13:59.275578
3364 18:13:59.275659 Set Vref, RX VrefLevel [Byte0]: 39
3365 18:13:59.278436 [Byte1]: 39
3366 18:13:59.283532
3367 18:13:59.283613 Set Vref, RX VrefLevel [Byte0]: 40
3368 18:13:59.286354 [Byte1]: 40
3369 18:13:59.291288
3370 18:13:59.291368 Set Vref, RX VrefLevel [Byte0]: 41
3371 18:13:59.294187 [Byte1]: 41
3372 18:13:59.298834
3373 18:13:59.298914 Set Vref, RX VrefLevel [Byte0]: 42
3374 18:13:59.302439 [Byte1]: 42
3375 18:13:59.306637
3376 18:13:59.306723 Set Vref, RX VrefLevel [Byte0]: 43
3377 18:13:59.310149 [Byte1]: 43
3378 18:13:59.314652
3379 18:13:59.314726 Set Vref, RX VrefLevel [Byte0]: 44
3380 18:13:59.318368 [Byte1]: 44
3381 18:13:59.322515
3382 18:13:59.322596 Set Vref, RX VrefLevel [Byte0]: 45
3383 18:13:59.326328 [Byte1]: 45
3384 18:13:59.330582
3385 18:13:59.330663 Set Vref, RX VrefLevel [Byte0]: 46
3386 18:13:59.333462 [Byte1]: 46
3387 18:13:59.338371
3388 18:13:59.338452 Set Vref, RX VrefLevel [Byte0]: 47
3389 18:13:59.341870 [Byte1]: 47
3390 18:13:59.345923
3391 18:13:59.346004 Set Vref, RX VrefLevel [Byte0]: 48
3392 18:13:59.349260 [Byte1]: 48
3393 18:13:59.354115
3394 18:13:59.354193 Set Vref, RX VrefLevel [Byte0]: 49
3395 18:13:59.357068 [Byte1]: 49
3396 18:13:59.361674
3397 18:13:59.361755 Set Vref, RX VrefLevel [Byte0]: 50
3398 18:13:59.365418 [Byte1]: 50
3399 18:13:59.369691
3400 18:13:59.369772 Set Vref, RX VrefLevel [Byte0]: 51
3401 18:13:59.372581 [Byte1]: 51
3402 18:13:59.377783
3403 18:13:59.377864 Set Vref, RX VrefLevel [Byte0]: 52
3404 18:13:59.380681 [Byte1]: 52
3405 18:13:59.385033
3406 18:13:59.385113 Set Vref, RX VrefLevel [Byte0]: 53
3407 18:13:59.388641 [Byte1]: 53
3408 18:13:59.392985
3409 18:13:59.393065 Set Vref, RX VrefLevel [Byte0]: 54
3410 18:13:59.396418 [Byte1]: 54
3411 18:13:59.400960
3412 18:13:59.401040 Set Vref, RX VrefLevel [Byte0]: 55
3413 18:13:59.404015 [Byte1]: 55
3414 18:13:59.408628
3415 18:13:59.408709 Set Vref, RX VrefLevel [Byte0]: 56
3416 18:13:59.412049 [Byte1]: 56
3417 18:13:59.416463
3418 18:13:59.416543 Set Vref, RX VrefLevel [Byte0]: 57
3419 18:13:59.420234 [Byte1]: 57
3420 18:13:59.424657
3421 18:13:59.424737 Set Vref, RX VrefLevel [Byte0]: 58
3422 18:13:59.428260 [Byte1]: 58
3423 18:13:59.432559
3424 18:13:59.432640 Set Vref, RX VrefLevel [Byte0]: 59
3425 18:13:59.435408 [Byte1]: 59
3426 18:13:59.440599
3427 18:13:59.440680 Set Vref, RX VrefLevel [Byte0]: 60
3428 18:13:59.443423 [Byte1]: 60
3429 18:13:59.448003
3430 18:13:59.448117 Set Vref, RX VrefLevel [Byte0]: 61
3431 18:13:59.451630 [Byte1]: 61
3432 18:13:59.456023
3433 18:13:59.456105 Set Vref, RX VrefLevel [Byte0]: 62
3434 18:13:59.459727 [Byte1]: 62
3435 18:13:59.463592
3436 18:13:59.463674 Set Vref, RX VrefLevel [Byte0]: 63
3437 18:13:59.466934 [Byte1]: 63
3438 18:13:59.471554
3439 18:13:59.471637 Set Vref, RX VrefLevel [Byte0]: 64
3440 18:13:59.474734 [Byte1]: 64
3441 18:13:59.479545
3442 18:13:59.479627 Set Vref, RX VrefLevel [Byte0]: 65
3443 18:13:59.482844 [Byte1]: 65
3444 18:13:59.487684
3445 18:13:59.487766 Set Vref, RX VrefLevel [Byte0]: 66
3446 18:13:59.490545 [Byte1]: 66
3447 18:13:59.494913
3448 18:13:59.494988 Set Vref, RX VrefLevel [Byte0]: 67
3449 18:13:59.498445 [Byte1]: 67
3450 18:13:59.503347
3451 18:13:59.503419 Set Vref, RX VrefLevel [Byte0]: 68
3452 18:13:59.506157 [Byte1]: 68
3453 18:13:59.511047
3454 18:13:59.511139 Final RX Vref Byte 0 = 53 to rank0
3455 18:13:59.514875 Final RX Vref Byte 1 = 53 to rank0
3456 18:13:59.517607 Final RX Vref Byte 0 = 53 to rank1
3457 18:13:59.521275 Final RX Vref Byte 1 = 53 to rank1==
3458 18:13:59.524171 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 18:13:59.527920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 18:13:59.530900 ==
3461 18:13:59.530975 DQS Delay:
3462 18:13:59.531038 DQS0 = 0, DQS1 = 0
3463 18:13:59.534535 DQM Delay:
3464 18:13:59.534612 DQM0 = 120, DQM1 = 117
3465 18:13:59.537455 DQ Delay:
3466 18:13:59.541028 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3467 18:13:59.544700 DQ4 =118, DQ5 =130, DQ6 =128, DQ7 =120
3468 18:13:59.547749 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3469 18:13:59.550651 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3470 18:13:59.550721
3471 18:13:59.550782
3472 18:13:59.561014 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3473 18:13:59.561102 CH1 RK0: MR19=304, MR18=FE11
3474 18:13:59.567856 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3475 18:13:59.567957
3476 18:13:59.570719 ----->DramcWriteLeveling(PI) begin...
3477 18:13:59.570802 ==
3478 18:13:59.574185 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 18:13:59.577915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 18:13:59.580921 ==
3481 18:13:59.581027 Write leveling (Byte 0): 25 => 25
3482 18:13:59.584222 Write leveling (Byte 1): 29 => 29
3483 18:13:59.587536 DramcWriteLeveling(PI) end<-----
3484 18:13:59.587611
3485 18:13:59.587692 ==
3486 18:13:59.590877 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 18:13:59.597689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 18:13:59.597769 ==
3489 18:13:59.597833 [Gating] SW mode calibration
3490 18:13:59.608021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 18:13:59.610986 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 18:13:59.614677 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 18:13:59.620992 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 18:13:59.624403 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 18:13:59.628169 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 18:13:59.634780 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 18:13:59.637803 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3498 18:13:59.641332 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (1 0) (0 0)
3499 18:13:59.648083 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3500 18:13:59.651030 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 18:13:59.654838 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 18:13:59.661041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 18:13:59.664637 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 18:13:59.667704 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 18:13:59.674289 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3506 18:13:59.677812 1 0 24 | B1->B0 | 4646 2c2c | 0 1 | (0 0) (0 0)
3507 18:13:59.681435 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3508 18:13:59.687571 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 18:13:59.691255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 18:13:59.694045 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 18:13:59.701000 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 18:13:59.704557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 18:13:59.708197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 18:13:59.711277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3515 18:13:59.717577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3516 18:13:59.720657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 18:13:59.724017 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 18:13:59.731219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 18:13:59.734053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 18:13:59.737493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 18:13:59.744184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 18:13:59.747915 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 18:13:59.750656 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 18:13:59.757327 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 18:13:59.761060 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 18:13:59.763860 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 18:13:59.770547 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 18:13:59.774269 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 18:13:59.777458 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3530 18:13:59.784379 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3531 18:13:59.787108 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3532 18:13:59.790869 Total UI for P1: 0, mck2ui 16
3533 18:13:59.794003 best dqsien dly found for B1: ( 1, 3, 22)
3534 18:13:59.797634 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 18:13:59.800691 Total UI for P1: 0, mck2ui 16
3536 18:13:59.804369 best dqsien dly found for B0: ( 1, 3, 26)
3537 18:13:59.807019 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3538 18:13:59.810486 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3539 18:13:59.810569
3540 18:13:59.814215 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3541 18:13:59.820802 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3542 18:13:59.820884 [Gating] SW calibration Done
3543 18:13:59.824092 ==
3544 18:13:59.824212 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 18:13:59.830436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 18:13:59.830519 ==
3547 18:13:59.830583 RX Vref Scan: 0
3548 18:13:59.830643
3549 18:13:59.833682 RX Vref 0 -> 0, step: 1
3550 18:13:59.833764
3551 18:13:59.836981 RX Delay -40 -> 252, step: 8
3552 18:13:59.840777 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3553 18:13:59.844081 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3554 18:13:59.846789 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3555 18:13:59.853464 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3556 18:13:59.856748 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3557 18:13:59.860351 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3558 18:13:59.863621 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3559 18:13:59.867168 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3560 18:13:59.873768 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3561 18:13:59.876656 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3562 18:13:59.880331 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3563 18:13:59.883564 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3564 18:13:59.890070 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3565 18:13:59.893674 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3566 18:13:59.896500 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3567 18:13:59.900148 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3568 18:13:59.900230 ==
3569 18:13:59.903182 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 18:13:59.906876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 18:13:59.909905 ==
3572 18:13:59.910003 DQS Delay:
3573 18:13:59.910083 DQS0 = 0, DQS1 = 0
3574 18:13:59.913531 DQM Delay:
3575 18:13:59.913612 DQM0 = 119, DQM1 = 117
3576 18:13:59.916386 DQ Delay:
3577 18:13:59.919810 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3578 18:13:59.923435 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3579 18:13:59.926469 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3580 18:13:59.930114 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3581 18:13:59.930196
3582 18:13:59.930259
3583 18:13:59.930319 ==
3584 18:13:59.933125 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 18:13:59.936464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 18:13:59.936573 ==
3587 18:13:59.940111
3588 18:13:59.940233
3589 18:13:59.940354 TX Vref Scan disable
3590 18:13:59.943107 == TX Byte 0 ==
3591 18:13:59.946122 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 18:13:59.949583 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 18:13:59.952882 == TX Byte 1 ==
3594 18:13:59.956121 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 18:13:59.959748 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 18:13:59.963417 ==
3597 18:13:59.963498 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 18:13:59.969527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 18:13:59.969610 ==
3600 18:13:59.980992 TX Vref=22, minBit 1, minWin=25, winSum=419
3601 18:13:59.983856 TX Vref=24, minBit 9, minWin=25, winSum=424
3602 18:13:59.987591 TX Vref=26, minBit 2, minWin=26, winSum=430
3603 18:13:59.990605 TX Vref=28, minBit 9, minWin=26, winSum=431
3604 18:13:59.994231 TX Vref=30, minBit 9, minWin=26, winSum=435
3605 18:13:59.997381 TX Vref=32, minBit 9, minWin=26, winSum=436
3606 18:14:00.003739 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3607 18:14:00.003822
3608 18:14:00.007506 Final TX Range 1 Vref 32
3609 18:14:00.007619
3610 18:14:00.007718 ==
3611 18:14:00.010388 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 18:14:00.014039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 18:14:00.014122 ==
3614 18:14:00.014186
3615 18:14:00.017012
3616 18:14:00.017093 TX Vref Scan disable
3617 18:14:00.020738 == TX Byte 0 ==
3618 18:14:00.023678 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 18:14:00.027185 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 18:14:00.030806 == TX Byte 1 ==
3621 18:14:00.033809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 18:14:00.037033 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 18:14:00.037106
3624 18:14:00.040548 [DATLAT]
3625 18:14:00.040629 Freq=1200, CH1 RK1
3626 18:14:00.040693
3627 18:14:00.044029 DATLAT Default: 0xd
3628 18:14:00.044110 0, 0xFFFF, sum = 0
3629 18:14:00.047209 1, 0xFFFF, sum = 0
3630 18:14:00.047292 2, 0xFFFF, sum = 0
3631 18:14:00.050615 3, 0xFFFF, sum = 0
3632 18:14:00.050724 4, 0xFFFF, sum = 0
3633 18:14:00.053451 5, 0xFFFF, sum = 0
3634 18:14:00.053534 6, 0xFFFF, sum = 0
3635 18:14:00.057014 7, 0xFFFF, sum = 0
3636 18:14:00.060291 8, 0xFFFF, sum = 0
3637 18:14:00.060411 9, 0xFFFF, sum = 0
3638 18:14:00.063810 10, 0xFFFF, sum = 0
3639 18:14:00.063892 11, 0xFFFF, sum = 0
3640 18:14:00.067085 12, 0x0, sum = 1
3641 18:14:00.067167 13, 0x0, sum = 2
3642 18:14:00.070477 14, 0x0, sum = 3
3643 18:14:00.070560 15, 0x0, sum = 4
3644 18:14:00.070626 best_step = 13
3645 18:14:00.070686
3646 18:14:00.074007 ==
3647 18:14:00.076787 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 18:14:00.080678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 18:14:00.080759 ==
3650 18:14:00.080823 RX Vref Scan: 0
3651 18:14:00.080882
3652 18:14:00.084146 RX Vref 0 -> 0, step: 1
3653 18:14:00.084226
3654 18:14:00.086840 RX Delay -5 -> 252, step: 4
3655 18:14:00.090643 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3656 18:14:00.097307 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3657 18:14:00.100251 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3658 18:14:00.103977 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3659 18:14:00.106885 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3660 18:14:00.109907 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3661 18:14:00.113343 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3662 18:14:00.120128 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3663 18:14:00.123893 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3664 18:14:00.126831 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3665 18:14:00.129778 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3666 18:14:00.133284 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3667 18:14:00.140641 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3668 18:14:00.143706 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3669 18:14:00.146798 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3670 18:14:00.150227 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3671 18:14:00.150308 ==
3672 18:14:00.153980 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 18:14:00.160211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 18:14:00.160299 ==
3675 18:14:00.160381 DQS Delay:
3676 18:14:00.163627 DQS0 = 0, DQS1 = 0
3677 18:14:00.163721 DQM Delay:
3678 18:14:00.163795 DQM0 = 120, DQM1 = 118
3679 18:14:00.167185 DQ Delay:
3680 18:14:00.169992 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3681 18:14:00.173635 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3682 18:14:00.177176 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3683 18:14:00.179999 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3684 18:14:00.180120
3685 18:14:00.180215
3686 18:14:00.190173 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3687 18:14:00.190328 CH1 RK1: MR19=403, MR18=EEB
3688 18:14:00.196980 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3689 18:14:00.200643 [RxdqsGatingPostProcess] freq 1200
3690 18:14:00.207294 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 18:14:00.210219 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 18:14:00.213899 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 18:14:00.216936 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 18:14:00.220500 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 18:14:00.223384 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 18:14:00.223855 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 18:14:00.227250 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 18:14:00.230209 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 18:14:00.233217 Pre-setting of DQS Precalculation
3700 18:14:00.240478 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 18:14:00.246559 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 18:14:00.253254 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 18:14:00.253806
3704 18:14:00.254264
3705 18:14:00.256871 [Calibration Summary] 2400 Mbps
3706 18:14:00.257248 CH 0, Rank 0
3707 18:14:00.259592 SW Impedance : PASS
3708 18:14:00.263341 DUTY Scan : NO K
3709 18:14:00.263563 ZQ Calibration : PASS
3710 18:14:00.266693 Jitter Meter : NO K
3711 18:14:00.269508 CBT Training : PASS
3712 18:14:00.269720 Write leveling : PASS
3713 18:14:00.272989 RX DQS gating : PASS
3714 18:14:00.276261 RX DQ/DQS(RDDQC) : PASS
3715 18:14:00.276473 TX DQ/DQS : PASS
3716 18:14:00.279898 RX DATLAT : PASS
3717 18:14:00.283300 RX DQ/DQS(Engine): PASS
3718 18:14:00.283478 TX OE : NO K
3719 18:14:00.286781 All Pass.
3720 18:14:00.286960
3721 18:14:00.287099 CH 0, Rank 1
3722 18:14:00.289603 SW Impedance : PASS
3723 18:14:00.289783 DUTY Scan : NO K
3724 18:14:00.293057 ZQ Calibration : PASS
3725 18:14:00.296426 Jitter Meter : NO K
3726 18:14:00.296606 CBT Training : PASS
3727 18:14:00.299649 Write leveling : PASS
3728 18:14:00.303124 RX DQS gating : PASS
3729 18:14:00.303302 RX DQ/DQS(RDDQC) : PASS
3730 18:14:00.306875 TX DQ/DQS : PASS
3731 18:14:00.307088 RX DATLAT : PASS
3732 18:14:00.309951 RX DQ/DQS(Engine): PASS
3733 18:14:00.313352 TX OE : NO K
3734 18:14:00.313609 All Pass.
3735 18:14:00.313811
3736 18:14:00.314007 CH 1, Rank 0
3737 18:14:00.316102 SW Impedance : PASS
3738 18:14:00.319769 DUTY Scan : NO K
3739 18:14:00.320023 ZQ Calibration : PASS
3740 18:14:00.323324 Jitter Meter : NO K
3741 18:14:00.326561 CBT Training : PASS
3742 18:14:00.326815 Write leveling : PASS
3743 18:14:00.330046 RX DQS gating : PASS
3744 18:14:00.332900 RX DQ/DQS(RDDQC) : PASS
3745 18:14:00.333155 TX DQ/DQS : PASS
3746 18:14:00.335977 RX DATLAT : PASS
3747 18:14:00.339883 RX DQ/DQS(Engine): PASS
3748 18:14:00.340324 TX OE : NO K
3749 18:14:00.342676 All Pass.
3750 18:14:00.343024
3751 18:14:00.343283 CH 1, Rank 1
3752 18:14:00.346373 SW Impedance : PASS
3753 18:14:00.346788 DUTY Scan : NO K
3754 18:14:00.349508 ZQ Calibration : PASS
3755 18:14:00.352817 Jitter Meter : NO K
3756 18:14:00.353152 CBT Training : PASS
3757 18:14:00.356416 Write leveling : PASS
3758 18:14:00.359511 RX DQS gating : PASS
3759 18:14:00.359946 RX DQ/DQS(RDDQC) : PASS
3760 18:14:00.362438 TX DQ/DQS : PASS
3761 18:14:00.366179 RX DATLAT : PASS
3762 18:14:00.366518 RX DQ/DQS(Engine): PASS
3763 18:14:00.369232 TX OE : NO K
3764 18:14:00.369729 All Pass.
3765 18:14:00.370041
3766 18:14:00.372953 DramC Write-DBI off
3767 18:14:00.375927 PER_BANK_REFRESH: Hybrid Mode
3768 18:14:00.376488 TX_TRACKING: ON
3769 18:14:00.385882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 18:14:00.389514 [FAST_K] Save calibration result to emmc
3771 18:14:00.392297 dramc_set_vcore_voltage set vcore to 650000
3772 18:14:00.392639 Read voltage for 600, 5
3773 18:14:00.395803 Vio18 = 0
3774 18:14:00.396069 Vcore = 650000
3775 18:14:00.396303 Vdram = 0
3776 18:14:00.398976 Vddq = 0
3777 18:14:00.399209 Vmddr = 0
3778 18:14:00.405752 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 18:14:00.409310 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 18:14:00.412177 MEM_TYPE=3, freq_sel=19
3781 18:14:00.416039 sv_algorithm_assistance_LP4_1600
3782 18:14:00.419081 ============ PULL DRAM RESETB DOWN ============
3783 18:14:00.422605 ========== PULL DRAM RESETB DOWN end =========
3784 18:14:00.429061 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 18:14:00.432535 ===================================
3786 18:14:00.432772 LPDDR4 DRAM CONFIGURATION
3787 18:14:00.435982 ===================================
3788 18:14:00.439435 EX_ROW_EN[0] = 0x0
3789 18:14:00.442300 EX_ROW_EN[1] = 0x0
3790 18:14:00.442603 LP4Y_EN = 0x0
3791 18:14:00.446046 WORK_FSP = 0x0
3792 18:14:00.446320 WL = 0x2
3793 18:14:00.449107 RL = 0x2
3794 18:14:00.449398 BL = 0x2
3795 18:14:00.452499 RPST = 0x0
3796 18:14:00.452876 RD_PRE = 0x0
3797 18:14:00.455802 WR_PRE = 0x1
3798 18:14:00.456175 WR_PST = 0x0
3799 18:14:00.459253 DBI_WR = 0x0
3800 18:14:00.459755 DBI_RD = 0x0
3801 18:14:00.462187 OTF = 0x1
3802 18:14:00.466052 ===================================
3803 18:14:00.469057 ===================================
3804 18:14:00.469434 ANA top config
3805 18:14:00.472154 ===================================
3806 18:14:00.475856 DLL_ASYNC_EN = 0
3807 18:14:00.478813 ALL_SLAVE_EN = 1
3808 18:14:00.479193 NEW_RANK_MODE = 1
3809 18:14:00.482234 DLL_IDLE_MODE = 1
3810 18:14:00.485774 LP45_APHY_COMB_EN = 1
3811 18:14:00.488562 TX_ODT_DIS = 1
3812 18:14:00.492265 NEW_8X_MODE = 1
3813 18:14:00.495210 ===================================
3814 18:14:00.499037 ===================================
3815 18:14:00.499500 data_rate = 1200
3816 18:14:00.502486 CKR = 1
3817 18:14:00.505414 DQ_P2S_RATIO = 8
3818 18:14:00.508490 ===================================
3819 18:14:00.512155 CA_P2S_RATIO = 8
3820 18:14:00.515346 DQ_CA_OPEN = 0
3821 18:14:00.518764 DQ_SEMI_OPEN = 0
3822 18:14:00.519089 CA_SEMI_OPEN = 0
3823 18:14:00.522111 CA_FULL_RATE = 0
3824 18:14:00.525002 DQ_CKDIV4_EN = 1
3825 18:14:00.528366 CA_CKDIV4_EN = 1
3826 18:14:00.531338 CA_PREDIV_EN = 0
3827 18:14:00.534863 PH8_DLY = 0
3828 18:14:00.535048 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 18:14:00.538402 DQ_AAMCK_DIV = 4
3830 18:14:00.541859 CA_AAMCK_DIV = 4
3831 18:14:00.544679 CA_ADMCK_DIV = 4
3832 18:14:00.548245 DQ_TRACK_CA_EN = 0
3833 18:14:00.551772 CA_PICK = 600
3834 18:14:00.554764 CA_MCKIO = 600
3835 18:14:00.554946 MCKIO_SEMI = 0
3836 18:14:00.557774 PLL_FREQ = 2288
3837 18:14:00.561305 DQ_UI_PI_RATIO = 32
3838 18:14:00.564849 CA_UI_PI_RATIO = 0
3839 18:14:00.568468 ===================================
3840 18:14:00.571493 ===================================
3841 18:14:00.574593 memory_type:LPDDR4
3842 18:14:00.574667 GP_NUM : 10
3843 18:14:00.578168 SRAM_EN : 1
3844 18:14:00.581332 MD32_EN : 0
3845 18:14:00.584714 ===================================
3846 18:14:00.584787 [ANA_INIT] >>>>>>>>>>>>>>
3847 18:14:00.588362 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 18:14:00.591237 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 18:14:00.594864 ===================================
3850 18:14:00.597768 data_rate = 1200,PCW = 0X5800
3851 18:14:00.601462 ===================================
3852 18:14:00.604573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 18:14:00.611116 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 18:14:00.614810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 18:14:00.621351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 18:14:00.624168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 18:14:00.627496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 18:14:00.627574 [ANA_INIT] flow start
3859 18:14:00.630965 [ANA_INIT] PLL >>>>>>>>
3860 18:14:00.634301 [ANA_INIT] PLL <<<<<<<<
3861 18:14:00.634378 [ANA_INIT] MIDPI >>>>>>>>
3862 18:14:00.637604 [ANA_INIT] MIDPI <<<<<<<<
3863 18:14:00.640934 [ANA_INIT] DLL >>>>>>>>
3864 18:14:00.641038 [ANA_INIT] flow end
3865 18:14:00.647503 ============ LP4 DIFF to SE enter ============
3866 18:14:00.651147 ============ LP4 DIFF to SE exit ============
3867 18:14:00.653973 [ANA_INIT] <<<<<<<<<<<<<
3868 18:14:00.657759 [Flow] Enable top DCM control >>>>>
3869 18:14:00.661233 [Flow] Enable top DCM control <<<<<
3870 18:14:00.661321 Enable DLL master slave shuffle
3871 18:14:00.667438 ==============================================================
3872 18:14:00.670950 Gating Mode config
3873 18:14:00.674686 ==============================================================
3874 18:14:00.677541 Config description:
3875 18:14:00.687337 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 18:14:00.694490 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 18:14:00.697270 SELPH_MODE 0: By rank 1: By Phase
3878 18:14:00.703803 ==============================================================
3879 18:14:00.707742 GAT_TRACK_EN = 1
3880 18:14:00.710518 RX_GATING_MODE = 2
3881 18:14:00.714067 RX_GATING_TRACK_MODE = 2
3882 18:14:00.717139 SELPH_MODE = 1
3883 18:14:00.717243 PICG_EARLY_EN = 1
3884 18:14:00.720949 VALID_LAT_VALUE = 1
3885 18:14:00.727354 ==============================================================
3886 18:14:00.730909 Enter into Gating configuration >>>>
3887 18:14:00.733710 Exit from Gating configuration <<<<
3888 18:14:00.737191 Enter into DVFS_PRE_config >>>>>
3889 18:14:00.747577 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 18:14:00.750941 Exit from DVFS_PRE_config <<<<<
3891 18:14:00.753849 Enter into PICG configuration >>>>
3892 18:14:00.757691 Exit from PICG configuration <<<<
3893 18:14:00.760447 [RX_INPUT] configuration >>>>>
3894 18:14:00.763877 [RX_INPUT] configuration <<<<<
3895 18:14:00.767614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 18:14:00.773934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 18:14:00.780957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 18:14:00.786935 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 18:14:00.793716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 18:14:00.797306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 18:14:00.803581 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 18:14:00.807199 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 18:14:00.810218 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 18:14:00.813920 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 18:14:00.820396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 18:14:00.823447 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 18:14:00.827124 ===================================
3908 18:14:00.830174 LPDDR4 DRAM CONFIGURATION
3909 18:14:00.833849 ===================================
3910 18:14:00.833930 EX_ROW_EN[0] = 0x0
3911 18:14:00.836720 EX_ROW_EN[1] = 0x0
3912 18:14:00.836800 LP4Y_EN = 0x0
3913 18:14:00.840383 WORK_FSP = 0x0
3914 18:14:00.840477 WL = 0x2
3915 18:14:00.843857 RL = 0x2
3916 18:14:00.843938 BL = 0x2
3917 18:14:00.846727 RPST = 0x0
3918 18:14:00.846808 RD_PRE = 0x0
3919 18:14:00.850521 WR_PRE = 0x1
3920 18:14:00.850602 WR_PST = 0x0
3921 18:14:00.853326 DBI_WR = 0x0
3922 18:14:00.856906 DBI_RD = 0x0
3923 18:14:00.856989 OTF = 0x1
3924 18:14:00.860437 ===================================
3925 18:14:00.863387 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 18:14:00.866963 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 18:14:00.873251 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 18:14:00.876930 ===================================
3929 18:14:00.880635 LPDDR4 DRAM CONFIGURATION
3930 18:14:00.880709 ===================================
3931 18:14:00.883244 EX_ROW_EN[0] = 0x10
3932 18:14:00.886699 EX_ROW_EN[1] = 0x0
3933 18:14:00.886772 LP4Y_EN = 0x0
3934 18:14:00.890196 WORK_FSP = 0x0
3935 18:14:00.890278 WL = 0x2
3936 18:14:00.893818 RL = 0x2
3937 18:14:00.893898 BL = 0x2
3938 18:14:00.896898 RPST = 0x0
3939 18:14:00.896974 RD_PRE = 0x0
3940 18:14:00.900354 WR_PRE = 0x1
3941 18:14:00.900460 WR_PST = 0x0
3942 18:14:00.903218 DBI_WR = 0x0
3943 18:14:00.903290 DBI_RD = 0x0
3944 18:14:00.906983 OTF = 0x1
3945 18:14:00.909849 ===================================
3946 18:14:00.917143 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 18:14:00.920240 nWR fixed to 30
3948 18:14:00.923184 [ModeRegInit_LP4] CH0 RK0
3949 18:14:00.923266 [ModeRegInit_LP4] CH0 RK1
3950 18:14:00.926738 [ModeRegInit_LP4] CH1 RK0
3951 18:14:00.930355 [ModeRegInit_LP4] CH1 RK1
3952 18:14:00.930443 match AC timing 17
3953 18:14:00.937012 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 18:14:00.940629 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 18:14:00.943375 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 18:14:00.950574 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 18:14:00.953236 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 18:14:00.953351 ==
3959 18:14:00.956922 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 18:14:00.959941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 18:14:00.960025 ==
3962 18:14:00.966339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 18:14:00.973380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3964 18:14:00.976172 [CA 0] Center 35 (5~66) winsize 62
3965 18:14:00.979843 [CA 1] Center 36 (5~67) winsize 63
3966 18:14:00.982802 [CA 2] Center 34 (3~65) winsize 63
3967 18:14:00.986673 [CA 3] Center 34 (3~65) winsize 63
3968 18:14:00.990000 [CA 4] Center 33 (2~64) winsize 63
3969 18:14:00.992946 [CA 5] Center 32 (2~63) winsize 62
3970 18:14:00.993024
3971 18:14:00.996489 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3972 18:14:00.996572
3973 18:14:00.999354 [CATrainingPosCal] consider 1 rank data
3974 18:14:01.003103 u2DelayCellTimex100 = 270/100 ps
3975 18:14:01.006652 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3976 18:14:01.009675 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3977 18:14:01.013186 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3978 18:14:01.016174 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
3979 18:14:01.020056 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3980 18:14:01.023216 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3981 18:14:01.026545
3982 18:14:01.029551 CA PerBit enable=1, Macro0, CA PI delay=32
3983 18:14:01.029633
3984 18:14:01.033095 [CBTSetCACLKResult] CA Dly = 32
3985 18:14:01.033175 CS Dly: 3 (0~34)
3986 18:14:01.033238 ==
3987 18:14:01.035960 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 18:14:01.039712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 18:14:01.039808 ==
3990 18:14:01.046179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 18:14:01.052531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 18:14:01.055893 [CA 0] Center 35 (5~66) winsize 62
3993 18:14:01.059806 [CA 1] Center 36 (5~67) winsize 63
3994 18:14:01.062566 [CA 2] Center 34 (3~65) winsize 63
3995 18:14:01.066489 [CA 3] Center 34 (3~65) winsize 63
3996 18:14:01.069233 [CA 4] Center 33 (2~64) winsize 63
3997 18:14:01.072901 [CA 5] Center 32 (2~63) winsize 62
3998 18:14:01.073006
3999 18:14:01.075780 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 18:14:01.075860
4001 18:14:01.079201 [CATrainingPosCal] consider 2 rank data
4002 18:14:01.083028 u2DelayCellTimex100 = 270/100 ps
4003 18:14:01.085979 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4004 18:14:01.089579 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4005 18:14:01.092508 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4006 18:14:01.099486 CA3 delay=34 (3~65),Diff = 2 PI (19 cell)
4007 18:14:01.102324 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4008 18:14:01.106040 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4009 18:14:01.106126
4010 18:14:01.108857 CA PerBit enable=1, Macro0, CA PI delay=32
4011 18:14:01.108945
4012 18:14:01.112453 [CBTSetCACLKResult] CA Dly = 32
4013 18:14:01.112538 CS Dly: 4 (0~36)
4014 18:14:01.112606
4015 18:14:01.115446 ----->DramcWriteLeveling(PI) begin...
4016 18:14:01.115548 ==
4017 18:14:01.119067 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 18:14:01.125891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 18:14:01.125971 ==
4020 18:14:01.128856 Write leveling (Byte 0): 35 => 35
4021 18:14:01.132533 Write leveling (Byte 1): 30 => 30
4022 18:14:01.132618 DramcWriteLeveling(PI) end<-----
4023 18:14:01.132684
4024 18:14:01.135448 ==
4025 18:14:01.139254 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 18:14:01.142271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 18:14:01.142363 ==
4028 18:14:01.145914 [Gating] SW mode calibration
4029 18:14:01.152386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 18:14:01.155325 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 18:14:01.162198 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 18:14:01.165726 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 18:14:01.169151 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 18:14:01.175623 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4035 18:14:01.179075 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4036 18:14:01.182629 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 18:14:01.188816 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 18:14:01.192321 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 18:14:01.195862 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 18:14:01.202091 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 18:14:01.205736 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 18:14:01.209207 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4043 18:14:01.215392 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4044 18:14:01.218866 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 18:14:01.222298 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 18:14:01.229152 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 18:14:01.232098 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 18:14:01.235662 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 18:14:01.238604 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 18:14:01.245298 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4051 18:14:01.249147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 18:14:01.252159 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 18:14:01.259005 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 18:14:01.262053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 18:14:01.265836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 18:14:01.271818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 18:14:01.275720 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 18:14:01.278607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 18:14:01.285599 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 18:14:01.288431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 18:14:01.291755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 18:14:01.298820 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 18:14:01.302177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 18:14:01.305384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 18:14:01.312074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 18:14:01.315175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 18:14:01.318334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4068 18:14:01.325069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 18:14:01.325161 Total UI for P1: 0, mck2ui 16
4070 18:14:01.331678 best dqsien dly found for B0: ( 0, 13, 14)
4071 18:14:01.331768 Total UI for P1: 0, mck2ui 16
4072 18:14:01.338398 best dqsien dly found for B1: ( 0, 13, 18)
4073 18:14:01.341510 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4074 18:14:01.344930 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4075 18:14:01.345015
4076 18:14:01.348088 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 18:14:01.351991 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4078 18:14:01.355074 [Gating] SW calibration Done
4079 18:14:01.355149 ==
4080 18:14:01.358065 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 18:14:01.362024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 18:14:01.362101 ==
4083 18:14:01.365155 RX Vref Scan: 0
4084 18:14:01.365254
4085 18:14:01.365344 RX Vref 0 -> 0, step: 1
4086 18:14:01.365448
4087 18:14:01.368206 RX Delay -230 -> 252, step: 16
4088 18:14:01.375001 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4089 18:14:01.378162 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4090 18:14:01.381783 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4091 18:14:01.384927 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4092 18:14:01.388080 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4093 18:14:01.395040 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4094 18:14:01.398074 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 18:14:01.401762 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 18:14:01.404762 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4097 18:14:01.411323 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4098 18:14:01.415150 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4099 18:14:01.418201 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4100 18:14:01.421064 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4101 18:14:01.428063 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4102 18:14:01.430994 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4103 18:14:01.434506 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4104 18:14:01.434596 ==
4105 18:14:01.437355 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 18:14:01.441117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 18:14:01.444525 ==
4108 18:14:01.444601 DQS Delay:
4109 18:14:01.444670 DQS0 = 0, DQS1 = 0
4110 18:14:01.447898 DQM Delay:
4111 18:14:01.448014 DQM0 = 52, DQM1 = 48
4112 18:14:01.451167 DQ Delay:
4113 18:14:01.451310 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4114 18:14:01.454346 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4115 18:14:01.457849 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4116 18:14:01.460933 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4117 18:14:01.461047
4118 18:14:01.461187
4119 18:14:01.463981 ==
4120 18:14:01.467713 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 18:14:01.470622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 18:14:01.470700 ==
4123 18:14:01.470785
4124 18:14:01.470865
4125 18:14:01.474251 TX Vref Scan disable
4126 18:14:01.474324 == TX Byte 0 ==
4127 18:14:01.481051 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4128 18:14:01.483980 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4129 18:14:01.484058 == TX Byte 1 ==
4130 18:14:01.490964 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4131 18:14:01.493997 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4132 18:14:01.494077 ==
4133 18:14:01.497229 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 18:14:01.500496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 18:14:01.500572 ==
4136 18:14:01.500660
4137 18:14:01.500747
4138 18:14:01.503486 TX Vref Scan disable
4139 18:14:01.507246 == TX Byte 0 ==
4140 18:14:01.510198 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4141 18:14:01.513935 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4142 18:14:01.517418 == TX Byte 1 ==
4143 18:14:01.520335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4144 18:14:01.524228 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4145 18:14:01.526869
4146 18:14:01.526947 [DATLAT]
4147 18:14:01.527038 Freq=600, CH0 RK0
4148 18:14:01.527143
4149 18:14:01.530650 DATLAT Default: 0x9
4150 18:14:01.530732 0, 0xFFFF, sum = 0
4151 18:14:01.533361 1, 0xFFFF, sum = 0
4152 18:14:01.533467 2, 0xFFFF, sum = 0
4153 18:14:01.536883 3, 0xFFFF, sum = 0
4154 18:14:01.536996 4, 0xFFFF, sum = 0
4155 18:14:01.540286 5, 0xFFFF, sum = 0
4156 18:14:01.543498 6, 0xFFFF, sum = 0
4157 18:14:01.543585 7, 0xFFFF, sum = 0
4158 18:14:01.543669 8, 0x0, sum = 1
4159 18:14:01.546929 9, 0x0, sum = 2
4160 18:14:01.547028 10, 0x0, sum = 3
4161 18:14:01.550397 11, 0x0, sum = 4
4162 18:14:01.550483 best_step = 9
4163 18:14:01.550575
4164 18:14:01.550655 ==
4165 18:14:01.553339 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 18:14:01.560560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 18:14:01.560646 ==
4168 18:14:01.560715 RX Vref Scan: 1
4169 18:14:01.560775
4170 18:14:01.563947 RX Vref 0 -> 0, step: 1
4171 18:14:01.564030
4172 18:14:01.566917 RX Delay -147 -> 252, step: 8
4173 18:14:01.567051
4174 18:14:01.570055 Set Vref, RX VrefLevel [Byte0]: 57
4175 18:14:01.573854 [Byte1]: 45
4176 18:14:01.573971
4177 18:14:01.576947 Final RX Vref Byte 0 = 57 to rank0
4178 18:14:01.580242 Final RX Vref Byte 1 = 45 to rank0
4179 18:14:01.583898 Final RX Vref Byte 0 = 57 to rank1
4180 18:14:01.586951 Final RX Vref Byte 1 = 45 to rank1==
4181 18:14:01.589840 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 18:14:01.593402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 18:14:01.593492 ==
4184 18:14:01.596990 DQS Delay:
4185 18:14:01.597077 DQS0 = 0, DQS1 = 0
4186 18:14:01.597142 DQM Delay:
4187 18:14:01.600120 DQM0 = 53, DQM1 = 47
4188 18:14:01.600194 DQ Delay:
4189 18:14:01.603124 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4190 18:14:01.606723 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4191 18:14:01.610272 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4192 18:14:01.613345 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =56
4193 18:14:01.613425
4194 18:14:01.613491
4195 18:14:01.623473 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4196 18:14:01.623562 CH0 RK0: MR19=808, MR18=6A5D
4197 18:14:01.630038 CH0_RK0: MR19=0x808, MR18=0x6A5D, DQSOSC=389, MR23=63, INC=173, DEC=115
4198 18:14:01.630128
4199 18:14:01.633658 ----->DramcWriteLeveling(PI) begin...
4200 18:14:01.636736 ==
4201 18:14:01.640282 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 18:14:01.643295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 18:14:01.643374 ==
4204 18:14:01.647075 Write leveling (Byte 0): 33 => 33
4205 18:14:01.649753 Write leveling (Byte 1): 31 => 31
4206 18:14:01.653380 DramcWriteLeveling(PI) end<-----
4207 18:14:01.653462
4208 18:14:01.653526 ==
4209 18:14:01.656951 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 18:14:01.660120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 18:14:01.660192 ==
4212 18:14:01.663490 [Gating] SW mode calibration
4213 18:14:01.669828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 18:14:01.676621 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 18:14:01.679629 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 18:14:01.683109 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 18:14:01.689766 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 18:14:01.692957 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (0 0) (1 0)
4219 18:14:01.696006 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
4220 18:14:01.699556 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 18:14:01.705863 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 18:14:01.709699 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 18:14:01.713103 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 18:14:01.719354 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 18:14:01.723003 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 18:14:01.725883 0 10 12 | B1->B0 | 2727 2b2b | 0 1 | (0 0) (0 0)
4227 18:14:01.732945 0 10 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
4228 18:14:01.735936 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 18:14:01.739563 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 18:14:01.746368 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 18:14:01.749184 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 18:14:01.752866 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 18:14:01.759627 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 18:14:01.762544 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4235 18:14:01.766273 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 18:14:01.772559 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 18:14:01.776174 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 18:14:01.779284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 18:14:01.785683 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 18:14:01.789315 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 18:14:01.793148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 18:14:01.799700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 18:14:01.802364 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 18:14:01.805943 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 18:14:01.812196 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 18:14:01.815561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 18:14:01.818906 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 18:14:01.825717 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 18:14:01.828956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4250 18:14:01.832494 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4251 18:14:01.835989 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 18:14:01.839197 Total UI for P1: 0, mck2ui 16
4253 18:14:01.842676 best dqsien dly found for B0: ( 0, 13, 12)
4254 18:14:01.845565 Total UI for P1: 0, mck2ui 16
4255 18:14:01.849258 best dqsien dly found for B1: ( 0, 13, 10)
4256 18:14:01.852198 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 18:14:01.859099 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4258 18:14:01.859182
4259 18:14:01.862539 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 18:14:01.866199 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4261 18:14:01.869224 [Gating] SW calibration Done
4262 18:14:01.869360 ==
4263 18:14:01.872812 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 18:14:01.875877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 18:14:01.875981 ==
4266 18:14:01.876109 RX Vref Scan: 0
4267 18:14:01.878814
4268 18:14:01.878887 RX Vref 0 -> 0, step: 1
4269 18:14:01.878948
4270 18:14:01.882712 RX Delay -230 -> 252, step: 16
4271 18:14:01.885355 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4272 18:14:01.892253 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4273 18:14:01.895553 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4274 18:14:01.899124 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4275 18:14:01.902145 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4276 18:14:01.908733 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4277 18:14:01.911675 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 18:14:01.915337 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 18:14:01.918380 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4280 18:14:01.922032 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4281 18:14:01.928173 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4282 18:14:01.931526 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4283 18:14:01.935137 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4284 18:14:01.938511 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4285 18:14:01.945181 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4286 18:14:01.948671 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4287 18:14:01.948755 ==
4288 18:14:01.951543 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 18:14:01.955096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 18:14:01.955174 ==
4291 18:14:01.958128 DQS Delay:
4292 18:14:01.958200 DQS0 = 0, DQS1 = 0
4293 18:14:01.958270 DQM Delay:
4294 18:14:01.961780 DQM0 = 50, DQM1 = 44
4295 18:14:01.961852 DQ Delay:
4296 18:14:01.964622 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4297 18:14:01.968299 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4298 18:14:01.971238 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4299 18:14:01.974991 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4300 18:14:01.975078
4301 18:14:01.975143
4302 18:14:01.975202 ==
4303 18:14:01.977973 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 18:14:01.984826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 18:14:01.984912 ==
4306 18:14:01.984975
4307 18:14:01.985034
4308 18:14:01.985098 TX Vref Scan disable
4309 18:14:01.988567 == TX Byte 0 ==
4310 18:14:01.991597 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4311 18:14:01.998899 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4312 18:14:01.998982 == TX Byte 1 ==
4313 18:14:02.001862 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4314 18:14:02.008444 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4315 18:14:02.008522 ==
4316 18:14:02.011565 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 18:14:02.015743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 18:14:02.015823 ==
4319 18:14:02.015887
4320 18:14:02.015947
4321 18:14:02.018371 TX Vref Scan disable
4322 18:14:02.021916 == TX Byte 0 ==
4323 18:14:02.025490 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4324 18:14:02.028493 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4325 18:14:02.032173 == TX Byte 1 ==
4326 18:14:02.035069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 18:14:02.038633 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 18:14:02.038718
4329 18:14:02.038782 [DATLAT]
4330 18:14:02.041636 Freq=600, CH0 RK1
4331 18:14:02.041710
4332 18:14:02.041771 DATLAT Default: 0x9
4333 18:14:02.045355 0, 0xFFFF, sum = 0
4334 18:14:02.048213 1, 0xFFFF, sum = 0
4335 18:14:02.048316 2, 0xFFFF, sum = 0
4336 18:14:02.051603 3, 0xFFFF, sum = 0
4337 18:14:02.051679 4, 0xFFFF, sum = 0
4338 18:14:02.055042 5, 0xFFFF, sum = 0
4339 18:14:02.055117 6, 0xFFFF, sum = 0
4340 18:14:02.057959 7, 0xFFFF, sum = 0
4341 18:14:02.058034 8, 0x0, sum = 1
4342 18:14:02.061558 9, 0x0, sum = 2
4343 18:14:02.061640 10, 0x0, sum = 3
4344 18:14:02.061704 11, 0x0, sum = 4
4345 18:14:02.065076 best_step = 9
4346 18:14:02.065148
4347 18:14:02.065208 ==
4348 18:14:02.068580 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 18:14:02.071365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 18:14:02.071446 ==
4351 18:14:02.075099 RX Vref Scan: 0
4352 18:14:02.075188
4353 18:14:02.075255 RX Vref 0 -> 0, step: 1
4354 18:14:02.078122
4355 18:14:02.078196 RX Delay -163 -> 252, step: 8
4356 18:14:02.085437 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4357 18:14:02.089182 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4358 18:14:02.092168 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4359 18:14:02.095846 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4360 18:14:02.099350 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4361 18:14:02.105343 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4362 18:14:02.109123 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4363 18:14:02.112782 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4364 18:14:02.115773 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4365 18:14:02.119262 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4366 18:14:02.125279 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4367 18:14:02.129214 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4368 18:14:02.132432 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4369 18:14:02.135397 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4370 18:14:02.139099 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4371 18:14:02.145353 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4372 18:14:02.145436 ==
4373 18:14:02.148880 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 18:14:02.151787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 18:14:02.151868 ==
4376 18:14:02.151933 DQS Delay:
4377 18:14:02.155275 DQS0 = 0, DQS1 = 0
4378 18:14:02.155377 DQM Delay:
4379 18:14:02.158696 DQM0 = 54, DQM1 = 46
4380 18:14:02.158772 DQ Delay:
4381 18:14:02.162368 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4382 18:14:02.165475 DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =60
4383 18:14:02.168515 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4384 18:14:02.171984 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4385 18:14:02.172068
4386 18:14:02.172132
4387 18:14:02.181879 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4388 18:14:02.181958 CH0 RK1: MR19=808, MR18=6425
4389 18:14:02.188596 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4390 18:14:02.191540 [RxdqsGatingPostProcess] freq 600
4391 18:14:02.198362 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 18:14:02.201918 Pre-setting of DQS Precalculation
4393 18:14:02.204906 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 18:14:02.204986 ==
4395 18:14:02.208676 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 18:14:02.211649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 18:14:02.215545 ==
4398 18:14:02.218399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 18:14:02.225169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4400 18:14:02.228180 [CA 0] Center 35 (5~66) winsize 62
4401 18:14:02.231856 [CA 1] Center 36 (5~67) winsize 63
4402 18:14:02.234855 [CA 2] Center 34 (4~65) winsize 62
4403 18:14:02.238628 [CA 3] Center 34 (4~65) winsize 62
4404 18:14:02.241548 [CA 4] Center 34 (4~65) winsize 62
4405 18:14:02.245065 [CA 5] Center 33 (3~64) winsize 62
4406 18:14:02.245144
4407 18:14:02.248557 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4408 18:14:02.248636
4409 18:14:02.251858 [CATrainingPosCal] consider 1 rank data
4410 18:14:02.255029 u2DelayCellTimex100 = 270/100 ps
4411 18:14:02.258324 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 18:14:02.261485 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4413 18:14:02.265276 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 18:14:02.268597 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 18:14:02.275488 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 18:14:02.278658 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 18:14:02.278740
4418 18:14:02.281740 CA PerBit enable=1, Macro0, CA PI delay=33
4419 18:14:02.281824
4420 18:14:02.285416 [CBTSetCACLKResult] CA Dly = 33
4421 18:14:02.285499 CS Dly: 6 (0~37)
4422 18:14:02.285563 ==
4423 18:14:02.288515 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 18:14:02.295015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 18:14:02.295097 ==
4426 18:14:02.298692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 18:14:02.305288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4428 18:14:02.308196 [CA 0] Center 36 (5~67) winsize 63
4429 18:14:02.311354 [CA 1] Center 36 (5~67) winsize 63
4430 18:14:02.314958 [CA 2] Center 35 (4~66) winsize 63
4431 18:14:02.317977 [CA 3] Center 35 (4~66) winsize 63
4432 18:14:02.321651 [CA 4] Center 35 (4~66) winsize 63
4433 18:14:02.324659 [CA 5] Center 34 (3~65) winsize 63
4434 18:14:02.324749
4435 18:14:02.327751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4436 18:14:02.327823
4437 18:14:02.331430 [CATrainingPosCal] consider 2 rank data
4438 18:14:02.335006 u2DelayCellTimex100 = 270/100 ps
4439 18:14:02.338207 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 18:14:02.341762 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4441 18:14:02.347675 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 18:14:02.351319 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 18:14:02.354232 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 18:14:02.357750 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 18:14:02.357863
4446 18:14:02.361586 CA PerBit enable=1, Macro0, CA PI delay=33
4447 18:14:02.361693
4448 18:14:02.364262 [CBTSetCACLKResult] CA Dly = 33
4449 18:14:02.364353 CS Dly: 6 (0~37)
4450 18:14:02.368037
4451 18:14:02.370925 ----->DramcWriteLeveling(PI) begin...
4452 18:14:02.371008 ==
4453 18:14:02.374631 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 18:14:02.377363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 18:14:02.377444 ==
4456 18:14:02.380941 Write leveling (Byte 0): 31 => 31
4457 18:14:02.384288 Write leveling (Byte 1): 30 => 30
4458 18:14:02.387667 DramcWriteLeveling(PI) end<-----
4459 18:14:02.387750
4460 18:14:02.387814 ==
4461 18:14:02.390822 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 18:14:02.393843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 18:14:02.393933 ==
4464 18:14:02.397238 [Gating] SW mode calibration
4465 18:14:02.403964 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 18:14:02.411064 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 18:14:02.413770 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 18:14:02.417190 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 18:14:02.424173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 18:14:02.427758 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4471 18:14:02.430673 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 18:14:02.437387 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 18:14:02.440323 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 18:14:02.444063 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 18:14:02.450889 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 18:14:02.453871 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 18:14:02.457557 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4478 18:14:02.460478 0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (1 1)
4479 18:14:02.467024 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 18:14:02.470736 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 18:14:02.473717 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 18:14:02.480381 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 18:14:02.484189 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 18:14:02.487120 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 18:14:02.493784 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4486 18:14:02.496794 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4487 18:14:02.500248 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 18:14:02.506900 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 18:14:02.510364 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 18:14:02.513214 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 18:14:02.520325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 18:14:02.523533 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 18:14:02.526772 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 18:14:02.533371 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 18:14:02.536827 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 18:14:02.540651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 18:14:02.546464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 18:14:02.550577 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 18:14:02.553196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 18:14:02.559924 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 18:14:02.563496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 18:14:02.567073 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4503 18:14:02.569953 Total UI for P1: 0, mck2ui 16
4504 18:14:02.573519 best dqsien dly found for B0: ( 0, 13, 10)
4505 18:14:02.580117 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 18:14:02.580236 Total UI for P1: 0, mck2ui 16
4507 18:14:02.583075 best dqsien dly found for B1: ( 0, 13, 12)
4508 18:14:02.590360 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4509 18:14:02.593415 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 18:14:02.593489
4511 18:14:02.597017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4512 18:14:02.599983 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 18:14:02.603612 [Gating] SW calibration Done
4514 18:14:02.603700 ==
4515 18:14:02.607112 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 18:14:02.610049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 18:14:02.610176 ==
4518 18:14:02.613066 RX Vref Scan: 0
4519 18:14:02.613194
4520 18:14:02.613317 RX Vref 0 -> 0, step: 1
4521 18:14:02.613417
4522 18:14:02.616868 RX Delay -230 -> 252, step: 16
4523 18:14:02.619870 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4524 18:14:02.626566 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 18:14:02.630136 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4526 18:14:02.632988 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 18:14:02.636521 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 18:14:02.643053 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 18:14:02.646381 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4530 18:14:02.649729 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 18:14:02.653219 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4532 18:14:02.656114 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4533 18:14:02.663181 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4534 18:14:02.666595 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4535 18:14:02.669764 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4536 18:14:02.673058 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4537 18:14:02.680137 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4538 18:14:02.683421 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4539 18:14:02.683561 ==
4540 18:14:02.686197 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 18:14:02.689807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 18:14:02.689917 ==
4543 18:14:02.692780 DQS Delay:
4544 18:14:02.692862 DQS0 = 0, DQS1 = 0
4545 18:14:02.692926 DQM Delay:
4546 18:14:02.696552 DQM0 = 46, DQM1 = 46
4547 18:14:02.696635 DQ Delay:
4548 18:14:02.699652 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4549 18:14:02.703313 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4550 18:14:02.706410 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4551 18:14:02.709411 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4552 18:14:02.709508
4553 18:14:02.709579
4554 18:14:02.709640 ==
4555 18:14:02.713045 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 18:14:02.719827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 18:14:02.719911 ==
4558 18:14:02.719976
4559 18:14:02.720037
4560 18:14:02.720094 TX Vref Scan disable
4561 18:14:02.723691 == TX Byte 0 ==
4562 18:14:02.726656 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4563 18:14:02.733147 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4564 18:14:02.733230 == TX Byte 1 ==
4565 18:14:02.736706 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 18:14:02.742900 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 18:14:02.742983 ==
4568 18:14:02.746532 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 18:14:02.750073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 18:14:02.750166 ==
4571 18:14:02.750246
4572 18:14:02.750332
4573 18:14:02.752972 TX Vref Scan disable
4574 18:14:02.756200 == TX Byte 0 ==
4575 18:14:02.759681 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4576 18:14:02.763118 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4577 18:14:02.766187 == TX Byte 1 ==
4578 18:14:02.769903 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 18:14:02.772824 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 18:14:02.772907
4581 18:14:02.772971 [DATLAT]
4582 18:14:02.776663 Freq=600, CH1 RK0
4583 18:14:02.776746
4584 18:14:02.776811 DATLAT Default: 0x9
4585 18:14:02.779475 0, 0xFFFF, sum = 0
4586 18:14:02.783130 1, 0xFFFF, sum = 0
4587 18:14:02.783215 2, 0xFFFF, sum = 0
4588 18:14:02.786033 3, 0xFFFF, sum = 0
4589 18:14:02.786116 4, 0xFFFF, sum = 0
4590 18:14:02.789519 5, 0xFFFF, sum = 0
4591 18:14:02.789603 6, 0xFFFF, sum = 0
4592 18:14:02.793023 7, 0xFFFF, sum = 0
4593 18:14:02.793106 8, 0x0, sum = 1
4594 18:14:02.796176 9, 0x0, sum = 2
4595 18:14:02.796287 10, 0x0, sum = 3
4596 18:14:02.796383 11, 0x0, sum = 4
4597 18:14:02.799813 best_step = 9
4598 18:14:02.799894
4599 18:14:02.799959 ==
4600 18:14:02.802855 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 18:14:02.805786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 18:14:02.805869 ==
4603 18:14:02.809884 RX Vref Scan: 1
4604 18:14:02.809967
4605 18:14:02.812607 RX Vref 0 -> 0, step: 1
4606 18:14:02.812691
4607 18:14:02.812756 RX Delay -163 -> 252, step: 8
4608 18:14:02.812817
4609 18:14:02.816161 Set Vref, RX VrefLevel [Byte0]: 53
4610 18:14:02.819101 [Byte1]: 53
4611 18:14:02.823580
4612 18:14:02.823663 Final RX Vref Byte 0 = 53 to rank0
4613 18:14:02.827277 Final RX Vref Byte 1 = 53 to rank0
4614 18:14:02.830311 Final RX Vref Byte 0 = 53 to rank1
4615 18:14:02.833290 Final RX Vref Byte 1 = 53 to rank1==
4616 18:14:02.837060 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 18:14:02.843891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 18:14:02.844002 ==
4619 18:14:02.844096 DQS Delay:
4620 18:14:02.844193 DQS0 = 0, DQS1 = 0
4621 18:14:02.846692 DQM Delay:
4622 18:14:02.846774 DQM0 = 48, DQM1 = 46
4623 18:14:02.850183 DQ Delay:
4624 18:14:02.853778 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4625 18:14:02.857221 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4626 18:14:02.859993 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4627 18:14:02.863713 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =60
4628 18:14:02.863795
4629 18:14:02.863860
4630 18:14:02.870136 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4631 18:14:02.873579 CH1 RK0: MR19=808, MR18=4A70
4632 18:14:02.880121 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4633 18:14:02.880207
4634 18:14:02.883763 ----->DramcWriteLeveling(PI) begin...
4635 18:14:02.883848 ==
4636 18:14:02.886785 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 18:14:02.890516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 18:14:02.890599 ==
4639 18:14:02.893541 Write leveling (Byte 0): 30 => 30
4640 18:14:02.896501 Write leveling (Byte 1): 33 => 33
4641 18:14:02.900157 DramcWriteLeveling(PI) end<-----
4642 18:14:02.900240
4643 18:14:02.900305 ==
4644 18:14:02.903178 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 18:14:02.906935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 18:14:02.907019 ==
4647 18:14:02.909779 [Gating] SW mode calibration
4648 18:14:02.916605 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 18:14:02.922902 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 18:14:02.926721 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 18:14:02.932913 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 18:14:02.936075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 18:14:02.939592 0 9 12 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
4654 18:14:02.946697 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 18:14:02.949689 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 18:14:02.952738 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 18:14:02.959398 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 18:14:02.962827 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 18:14:02.966417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 18:14:02.969893 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 18:14:02.976098 0 10 12 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
4662 18:14:02.979707 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 18:14:02.983000 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 18:14:02.989885 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 18:14:02.992783 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 18:14:02.996728 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 18:14:03.002501 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 18:14:03.006286 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4669 18:14:03.009305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4670 18:14:03.016096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 18:14:03.019142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 18:14:03.022869 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 18:14:03.029399 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 18:14:03.033147 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 18:14:03.036078 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 18:14:03.042419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 18:14:03.045820 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 18:14:03.049285 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 18:14:03.056058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 18:14:03.059179 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 18:14:03.062564 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 18:14:03.069228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 18:14:03.072772 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 18:14:03.075640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 18:14:03.082559 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 18:14:03.082643 Total UI for P1: 0, mck2ui 16
4687 18:14:03.088762 best dqsien dly found for B0: ( 0, 13, 10)
4688 18:14:03.088845 Total UI for P1: 0, mck2ui 16
4689 18:14:03.092388 best dqsien dly found for B1: ( 0, 13, 10)
4690 18:14:03.098856 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4691 18:14:03.102789 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 18:14:03.102870
4693 18:14:03.105643 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4694 18:14:03.109242 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 18:14:03.112086 [Gating] SW calibration Done
4696 18:14:03.112170 ==
4697 18:14:03.115784 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 18:14:03.118713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 18:14:03.118797 ==
4700 18:14:03.122314 RX Vref Scan: 0
4701 18:14:03.122393
4702 18:14:03.122461 RX Vref 0 -> 0, step: 1
4703 18:14:03.122527
4704 18:14:03.125358 RX Delay -230 -> 252, step: 16
4705 18:14:03.128958 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4706 18:14:03.135821 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4707 18:14:03.138988 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4708 18:14:03.142464 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4709 18:14:03.145916 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4710 18:14:03.152574 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4711 18:14:03.155325 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4712 18:14:03.159089 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4713 18:14:03.162094 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4714 18:14:03.165642 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4715 18:14:03.172271 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4716 18:14:03.175657 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4717 18:14:03.178784 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4718 18:14:03.182096 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4719 18:14:03.188616 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4720 18:14:03.191787 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4721 18:14:03.191868 ==
4722 18:14:03.195082 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 18:14:03.198463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 18:14:03.198547 ==
4725 18:14:03.202168 DQS Delay:
4726 18:14:03.202250 DQS0 = 0, DQS1 = 0
4727 18:14:03.202316 DQM Delay:
4728 18:14:03.205241 DQM0 = 50, DQM1 = 50
4729 18:14:03.205324 DQ Delay:
4730 18:14:03.208606 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4731 18:14:03.212067 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4732 18:14:03.215388 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4733 18:14:03.219187 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4734 18:14:03.219271
4735 18:14:03.219336
4736 18:14:03.219397 ==
4737 18:14:03.221977 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 18:14:03.228670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 18:14:03.228754 ==
4740 18:14:03.228819
4741 18:14:03.228879
4742 18:14:03.228937 TX Vref Scan disable
4743 18:14:03.232349 == TX Byte 0 ==
4744 18:14:03.235935 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 18:14:03.238876 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 18:14:03.242663 == TX Byte 1 ==
4747 18:14:03.245804 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4748 18:14:03.249272 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4749 18:14:03.252182 ==
4750 18:14:03.255837 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 18:14:03.258689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 18:14:03.258772 ==
4753 18:14:03.258837
4754 18:14:03.258897
4755 18:14:03.262305 TX Vref Scan disable
4756 18:14:03.265471 == TX Byte 0 ==
4757 18:14:03.268485 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4758 18:14:03.272082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4759 18:14:03.275233 == TX Byte 1 ==
4760 18:14:03.279024 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4761 18:14:03.282344 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4762 18:14:03.282427
4763 18:14:03.282492 [DATLAT]
4764 18:14:03.285170 Freq=600, CH1 RK1
4765 18:14:03.285254
4766 18:14:03.285320 DATLAT Default: 0x9
4767 18:14:03.288737 0, 0xFFFF, sum = 0
4768 18:14:03.288841 1, 0xFFFF, sum = 0
4769 18:14:03.292256 2, 0xFFFF, sum = 0
4770 18:14:03.295682 3, 0xFFFF, sum = 0
4771 18:14:03.295774 4, 0xFFFF, sum = 0
4772 18:14:03.298602 5, 0xFFFF, sum = 0
4773 18:14:03.298686 6, 0xFFFF, sum = 0
4774 18:14:03.302214 7, 0xFFFF, sum = 0
4775 18:14:03.302299 8, 0x0, sum = 1
4776 18:14:03.305100 9, 0x0, sum = 2
4777 18:14:03.305185 10, 0x0, sum = 3
4778 18:14:03.305252 11, 0x0, sum = 4
4779 18:14:03.308799 best_step = 9
4780 18:14:03.308882
4781 18:14:03.308948 ==
4782 18:14:03.311780 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 18:14:03.315295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 18:14:03.315379 ==
4785 18:14:03.319120 RX Vref Scan: 0
4786 18:14:03.319229
4787 18:14:03.319322 RX Vref 0 -> 0, step: 1
4788 18:14:03.321525
4789 18:14:03.321608 RX Delay -163 -> 252, step: 8
4790 18:14:03.329276 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4791 18:14:03.332384 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4792 18:14:03.336085 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4793 18:14:03.339407 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4794 18:14:03.345906 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4795 18:14:03.348900 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4796 18:14:03.352496 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4797 18:14:03.355509 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4798 18:14:03.359286 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4799 18:14:03.365934 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4800 18:14:03.368929 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4801 18:14:03.372746 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4802 18:14:03.375691 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4803 18:14:03.379323 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4804 18:14:03.385889 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4805 18:14:03.388944 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4806 18:14:03.389028 ==
4807 18:14:03.392629 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 18:14:03.395501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 18:14:03.395611 ==
4810 18:14:03.399270 DQS Delay:
4811 18:14:03.399365 DQS0 = 0, DQS1 = 0
4812 18:14:03.399457 DQM Delay:
4813 18:14:03.402227 DQM0 = 49, DQM1 = 45
4814 18:14:03.402308 DQ Delay:
4815 18:14:03.405885 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4816 18:14:03.408864 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4817 18:14:03.412280 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4818 18:14:03.415731 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4819 18:14:03.415829
4820 18:14:03.415913
4821 18:14:03.425310 [DQSOSCAuto] RK1, (LSB)MR18= 0x671e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4822 18:14:03.425473 CH1 RK1: MR19=808, MR18=671E
4823 18:14:03.432111 CH1_RK1: MR19=0x808, MR18=0x671E, DQSOSC=390, MR23=63, INC=172, DEC=114
4824 18:14:03.435664 [RxdqsGatingPostProcess] freq 600
4825 18:14:03.442152 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 18:14:03.445695 Pre-setting of DQS Precalculation
4827 18:14:03.448780 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 18:14:03.455544 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 18:14:03.466215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 18:14:03.466309
4831 18:14:03.466375
4832 18:14:03.469148 [Calibration Summary] 1200 Mbps
4833 18:14:03.469261 CH 0, Rank 0
4834 18:14:03.472118 SW Impedance : PASS
4835 18:14:03.472232 DUTY Scan : NO K
4836 18:14:03.475732 ZQ Calibration : PASS
4837 18:14:03.475808 Jitter Meter : NO K
4838 18:14:03.478722 CBT Training : PASS
4839 18:14:03.482631 Write leveling : PASS
4840 18:14:03.482737 RX DQS gating : PASS
4841 18:14:03.485561 RX DQ/DQS(RDDQC) : PASS
4842 18:14:03.488661 TX DQ/DQS : PASS
4843 18:14:03.488778 RX DATLAT : PASS
4844 18:14:03.492143 RX DQ/DQS(Engine): PASS
4845 18:14:03.495210 TX OE : NO K
4846 18:14:03.495295 All Pass.
4847 18:14:03.495396
4848 18:14:03.495490 CH 0, Rank 1
4849 18:14:03.499035 SW Impedance : PASS
4850 18:14:03.501917 DUTY Scan : NO K
4851 18:14:03.502001 ZQ Calibration : PASS
4852 18:14:03.505609 Jitter Meter : NO K
4853 18:14:03.508562 CBT Training : PASS
4854 18:14:03.508646 Write leveling : PASS
4855 18:14:03.512144 RX DQS gating : PASS
4856 18:14:03.515030 RX DQ/DQS(RDDQC) : PASS
4857 18:14:03.515145 TX DQ/DQS : PASS
4858 18:14:03.518888 RX DATLAT : PASS
4859 18:14:03.522321 RX DQ/DQS(Engine): PASS
4860 18:14:03.522430 TX OE : NO K
4861 18:14:03.522514 All Pass.
4862 18:14:03.522577
4863 18:14:03.525122 CH 1, Rank 0
4864 18:14:03.525205 SW Impedance : PASS
4865 18:14:03.528625 DUTY Scan : NO K
4866 18:14:03.532080 ZQ Calibration : PASS
4867 18:14:03.532188 Jitter Meter : NO K
4868 18:14:03.535648 CBT Training : PASS
4869 18:14:03.538974 Write leveling : PASS
4870 18:14:03.539058 RX DQS gating : PASS
4871 18:14:03.542397 RX DQ/DQS(RDDQC) : PASS
4872 18:14:03.545406 TX DQ/DQS : PASS
4873 18:14:03.545490 RX DATLAT : PASS
4874 18:14:03.549158 RX DQ/DQS(Engine): PASS
4875 18:14:03.552044 TX OE : NO K
4876 18:14:03.552130 All Pass.
4877 18:14:03.552211
4878 18:14:03.552274 CH 1, Rank 1
4879 18:14:03.555798 SW Impedance : PASS
4880 18:14:03.558517 DUTY Scan : NO K
4881 18:14:03.558595 ZQ Calibration : PASS
4882 18:14:03.562207 Jitter Meter : NO K
4883 18:14:03.565018 CBT Training : PASS
4884 18:14:03.565101 Write leveling : PASS
4885 18:14:03.568443 RX DQS gating : PASS
4886 18:14:03.571821 RX DQ/DQS(RDDQC) : PASS
4887 18:14:03.571912 TX DQ/DQS : PASS
4888 18:14:03.574952 RX DATLAT : PASS
4889 18:14:03.575042 RX DQ/DQS(Engine): PASS
4890 18:14:03.578539 TX OE : NO K
4891 18:14:03.578622 All Pass.
4892 18:14:03.578689
4893 18:14:03.581509 DramC Write-DBI off
4894 18:14:03.585336 PER_BANK_REFRESH: Hybrid Mode
4895 18:14:03.585410 TX_TRACKING: ON
4896 18:14:03.595006 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 18:14:03.598589 [FAST_K] Save calibration result to emmc
4898 18:14:03.601620 dramc_set_vcore_voltage set vcore to 662500
4899 18:14:03.605436 Read voltage for 933, 3
4900 18:14:03.605520 Vio18 = 0
4901 18:14:03.608309 Vcore = 662500
4902 18:14:03.608400 Vdram = 0
4903 18:14:03.608466 Vddq = 0
4904 18:14:03.608527 Vmddr = 0
4905 18:14:03.614995 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 18:14:03.618008 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 18:14:03.621952 MEM_TYPE=3, freq_sel=17
4908 18:14:03.624897 sv_algorithm_assistance_LP4_1600
4909 18:14:03.627886 ============ PULL DRAM RESETB DOWN ============
4910 18:14:03.635051 ========== PULL DRAM RESETB DOWN end =========
4911 18:14:03.637931 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 18:14:03.641561 ===================================
4913 18:14:03.645032 LPDDR4 DRAM CONFIGURATION
4914 18:14:03.647867 ===================================
4915 18:14:03.647950 EX_ROW_EN[0] = 0x0
4916 18:14:03.651412 EX_ROW_EN[1] = 0x0
4917 18:14:03.651495 LP4Y_EN = 0x0
4918 18:14:03.655038 WORK_FSP = 0x0
4919 18:14:03.655121 WL = 0x3
4920 18:14:03.657983 RL = 0x3
4921 18:14:03.658070 BL = 0x2
4922 18:14:03.661429 RPST = 0x0
4923 18:14:03.664972 RD_PRE = 0x0
4924 18:14:03.665073 WR_PRE = 0x1
4925 18:14:03.667799 WR_PST = 0x0
4926 18:14:03.667877 DBI_WR = 0x0
4927 18:14:03.671557 DBI_RD = 0x0
4928 18:14:03.671664 OTF = 0x1
4929 18:14:03.674490 ===================================
4930 18:14:03.678150 ===================================
4931 18:14:03.681075 ANA top config
4932 18:14:03.681203 ===================================
4933 18:14:03.684896 DLL_ASYNC_EN = 0
4934 18:14:03.688179 ALL_SLAVE_EN = 1
4935 18:14:03.691038 NEW_RANK_MODE = 1
4936 18:14:03.694792 DLL_IDLE_MODE = 1
4937 18:14:03.694899 LP45_APHY_COMB_EN = 1
4938 18:14:03.697708 TX_ODT_DIS = 1
4939 18:14:03.701419 NEW_8X_MODE = 1
4940 18:14:03.704268 ===================================
4941 18:14:03.708186 ===================================
4942 18:14:03.711063 data_rate = 1866
4943 18:14:03.714678 CKR = 1
4944 18:14:03.714768 DQ_P2S_RATIO = 8
4945 18:14:03.717544 ===================================
4946 18:14:03.721213 CA_P2S_RATIO = 8
4947 18:14:03.724103 DQ_CA_OPEN = 0
4948 18:14:03.727795 DQ_SEMI_OPEN = 0
4949 18:14:03.730798 CA_SEMI_OPEN = 0
4950 18:14:03.734593 CA_FULL_RATE = 0
4951 18:14:03.734699 DQ_CKDIV4_EN = 1
4952 18:14:03.737390 CA_CKDIV4_EN = 1
4953 18:14:03.741083 CA_PREDIV_EN = 0
4954 18:14:03.743986 PH8_DLY = 0
4955 18:14:03.747750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 18:14:03.750682 DQ_AAMCK_DIV = 4
4957 18:14:03.750778 CA_AAMCK_DIV = 4
4958 18:14:03.754364 CA_ADMCK_DIV = 4
4959 18:14:03.757254 DQ_TRACK_CA_EN = 0
4960 18:14:03.760865 CA_PICK = 933
4961 18:14:03.764209 CA_MCKIO = 933
4962 18:14:03.767756 MCKIO_SEMI = 0
4963 18:14:03.770509 PLL_FREQ = 3732
4964 18:14:03.770593 DQ_UI_PI_RATIO = 32
4965 18:14:03.773884 CA_UI_PI_RATIO = 0
4966 18:14:03.777556 ===================================
4967 18:14:03.780532 ===================================
4968 18:14:03.783983 memory_type:LPDDR4
4969 18:14:03.787774 GP_NUM : 10
4970 18:14:03.787882 SRAM_EN : 1
4971 18:14:03.790731 MD32_EN : 0
4972 18:14:03.794190 ===================================
4973 18:14:03.797489 [ANA_INIT] >>>>>>>>>>>>>>
4974 18:14:03.797604 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 18:14:03.800352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 18:14:03.803743 ===================================
4977 18:14:03.807398 data_rate = 1866,PCW = 0X8f00
4978 18:14:03.810367 ===================================
4979 18:14:03.814179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 18:14:03.820979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 18:14:03.827318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 18:14:03.830330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 18:14:03.834043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 18:14:03.837055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 18:14:03.840745 [ANA_INIT] flow start
4986 18:14:03.840823 [ANA_INIT] PLL >>>>>>>>
4987 18:14:03.843806 [ANA_INIT] PLL <<<<<<<<
4988 18:14:03.847313 [ANA_INIT] MIDPI >>>>>>>>
4989 18:14:03.850358 [ANA_INIT] MIDPI <<<<<<<<
4990 18:14:03.850462 [ANA_INIT] DLL >>>>>>>>
4991 18:14:03.853342 [ANA_INIT] flow end
4992 18:14:03.857275 ============ LP4 DIFF to SE enter ============
4993 18:14:03.860207 ============ LP4 DIFF to SE exit ============
4994 18:14:03.864010 [ANA_INIT] <<<<<<<<<<<<<
4995 18:14:03.866697 [Flow] Enable top DCM control >>>>>
4996 18:14:03.870235 [Flow] Enable top DCM control <<<<<
4997 18:14:03.873874 Enable DLL master slave shuffle
4998 18:14:03.877371 ==============================================================
4999 18:14:03.880540 Gating Mode config
5000 18:14:03.887286 ==============================================================
5001 18:14:03.887370 Config description:
5002 18:14:03.897176 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 18:14:03.903506 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 18:14:03.910617 SELPH_MODE 0: By rank 1: By Phase
5005 18:14:03.913219 ==============================================================
5006 18:14:03.917143 GAT_TRACK_EN = 1
5007 18:14:03.920128 RX_GATING_MODE = 2
5008 18:14:03.924011 RX_GATING_TRACK_MODE = 2
5009 18:14:03.926876 SELPH_MODE = 1
5010 18:14:03.929774 PICG_EARLY_EN = 1
5011 18:14:03.933470 VALID_LAT_VALUE = 1
5012 18:14:03.937075 ==============================================================
5013 18:14:03.940014 Enter into Gating configuration >>>>
5014 18:14:03.943044 Exit from Gating configuration <<<<
5015 18:14:03.946713 Enter into DVFS_PRE_config >>>>>
5016 18:14:03.960045 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 18:14:03.963067 Exit from DVFS_PRE_config <<<<<
5018 18:14:03.966817 Enter into PICG configuration >>>>
5019 18:14:03.966931 Exit from PICG configuration <<<<
5020 18:14:03.969816 [RX_INPUT] configuration >>>>>
5021 18:14:03.972895 [RX_INPUT] configuration <<<<<
5022 18:14:03.979576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 18:14:03.983371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 18:14:03.989959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 18:14:03.996401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 18:14:04.003245 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 18:14:04.009690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 18:14:04.012935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 18:14:04.016391 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 18:14:04.019552 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 18:14:04.026157 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 18:14:04.029499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 18:14:04.032698 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 18:14:04.036274 ===================================
5035 18:14:04.039522 LPDDR4 DRAM CONFIGURATION
5036 18:14:04.043090 ===================================
5037 18:14:04.045981 EX_ROW_EN[0] = 0x0
5038 18:14:04.046086 EX_ROW_EN[1] = 0x0
5039 18:14:04.049157 LP4Y_EN = 0x0
5040 18:14:04.049259 WORK_FSP = 0x0
5041 18:14:04.052820 WL = 0x3
5042 18:14:04.052920 RL = 0x3
5043 18:14:04.055842 BL = 0x2
5044 18:14:04.055942 RPST = 0x0
5045 18:14:04.059485 RD_PRE = 0x0
5046 18:14:04.059584 WR_PRE = 0x1
5047 18:14:04.062354 WR_PST = 0x0
5048 18:14:04.062488 DBI_WR = 0x0
5049 18:14:04.066148 DBI_RD = 0x0
5050 18:14:04.066265 OTF = 0x1
5051 18:14:04.069098 ===================================
5052 18:14:04.075650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 18:14:04.078849 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 18:14:04.082663 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 18:14:04.085539 ===================================
5056 18:14:04.089174 LPDDR4 DRAM CONFIGURATION
5057 18:14:04.093262 ===================================
5058 18:14:04.095838 EX_ROW_EN[0] = 0x10
5059 18:14:04.095947 EX_ROW_EN[1] = 0x0
5060 18:14:04.098797 LP4Y_EN = 0x0
5061 18:14:04.098898 WORK_FSP = 0x0
5062 18:14:04.102456 WL = 0x3
5063 18:14:04.102568 RL = 0x3
5064 18:14:04.105535 BL = 0x2
5065 18:14:04.105633 RPST = 0x0
5066 18:14:04.109137 RD_PRE = 0x0
5067 18:14:04.109236 WR_PRE = 0x1
5068 18:14:04.112068 WR_PST = 0x0
5069 18:14:04.112166 DBI_WR = 0x0
5070 18:14:04.115661 DBI_RD = 0x0
5071 18:14:04.115743 OTF = 0x1
5072 18:14:04.118611 ===================================
5073 18:14:04.125591 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 18:14:04.130198 nWR fixed to 30
5075 18:14:04.133533 [ModeRegInit_LP4] CH0 RK0
5076 18:14:04.133631 [ModeRegInit_LP4] CH0 RK1
5077 18:14:04.136951 [ModeRegInit_LP4] CH1 RK0
5078 18:14:04.140210 [ModeRegInit_LP4] CH1 RK1
5079 18:14:04.140317 match AC timing 9
5080 18:14:04.146939 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 18:14:04.150221 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 18:14:04.153839 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 18:14:04.160312 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 18:14:04.164015 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 18:14:04.164114 ==
5086 18:14:04.166803 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 18:14:04.170420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 18:14:04.170502 ==
5089 18:14:04.177250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 18:14:04.183716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5091 18:14:04.186693 [CA 0] Center 37 (6~68) winsize 63
5092 18:14:04.190325 [CA 1] Center 37 (6~68) winsize 63
5093 18:14:04.194024 [CA 2] Center 34 (4~65) winsize 62
5094 18:14:04.196942 [CA 3] Center 34 (3~65) winsize 63
5095 18:14:04.200592 [CA 4] Center 33 (3~64) winsize 62
5096 18:14:04.203456 [CA 5] Center 32 (2~62) winsize 61
5097 18:14:04.203568
5098 18:14:04.207038 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5099 18:14:04.207133
5100 18:14:04.209971 [CATrainingPosCal] consider 1 rank data
5101 18:14:04.213726 u2DelayCellTimex100 = 270/100 ps
5102 18:14:04.216760 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5103 18:14:04.220216 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5104 18:14:04.223237 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 18:14:04.226812 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5106 18:14:04.229881 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5107 18:14:04.233670 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5108 18:14:04.233782
5109 18:14:04.240400 CA PerBit enable=1, Macro0, CA PI delay=32
5110 18:14:04.240486
5111 18:14:04.243196 [CBTSetCACLKResult] CA Dly = 32
5112 18:14:04.243277 CS Dly: 5 (0~36)
5113 18:14:04.243346 ==
5114 18:14:04.246883 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 18:14:04.250401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 18:14:04.250492 ==
5117 18:14:04.256435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 18:14:04.263241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 18:14:04.266744 [CA 0] Center 37 (7~68) winsize 62
5120 18:14:04.270318 [CA 1] Center 37 (7~68) winsize 62
5121 18:14:04.273503 [CA 2] Center 34 (4~65) winsize 62
5122 18:14:04.276877 [CA 3] Center 34 (3~65) winsize 63
5123 18:14:04.279967 [CA 4] Center 32 (2~63) winsize 62
5124 18:14:04.283254 [CA 5] Center 32 (2~62) winsize 61
5125 18:14:04.283330
5126 18:14:04.286487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 18:14:04.286565
5128 18:14:04.290096 [CATrainingPosCal] consider 2 rank data
5129 18:14:04.293118 u2DelayCellTimex100 = 270/100 ps
5130 18:14:04.296163 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5131 18:14:04.299933 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 18:14:04.303523 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5133 18:14:04.306475 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5134 18:14:04.309898 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5135 18:14:04.316370 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5136 18:14:04.316459
5137 18:14:04.319497 CA PerBit enable=1, Macro0, CA PI delay=32
5138 18:14:04.319570
5139 18:14:04.323150 [CBTSetCACLKResult] CA Dly = 32
5140 18:14:04.323235 CS Dly: 5 (0~37)
5141 18:14:04.323328
5142 18:14:04.326146 ----->DramcWriteLeveling(PI) begin...
5143 18:14:04.326226 ==
5144 18:14:04.329983 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 18:14:04.336698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 18:14:04.336781 ==
5147 18:14:04.339579 Write leveling (Byte 0): 34 => 34
5148 18:14:04.339664 Write leveling (Byte 1): 28 => 28
5149 18:14:04.343351 DramcWriteLeveling(PI) end<-----
5150 18:14:04.343467
5151 18:14:04.343573 ==
5152 18:14:04.346034 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 18:14:04.352874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 18:14:04.352989 ==
5155 18:14:04.355883 [Gating] SW mode calibration
5156 18:14:04.363010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 18:14:04.366093 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 18:14:04.372896 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5159 18:14:04.375812 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 18:14:04.379518 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 18:14:04.386141 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 18:14:04.389127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 18:14:04.392665 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 18:14:04.399618 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5165 18:14:04.402863 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
5166 18:14:04.405754 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
5167 18:14:04.409469 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 18:14:04.416022 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 18:14:04.419591 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 18:14:04.422551 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 18:14:04.429204 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 18:14:04.432862 0 15 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5173 18:14:04.435771 0 15 28 | B1->B0 | 2525 3838 | 0 1 | (0 0) (0 0)
5174 18:14:04.442481 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5175 18:14:04.446137 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 18:14:04.449034 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 18:14:04.455808 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 18:14:04.458810 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 18:14:04.462716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 18:14:04.469440 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 18:14:04.472102 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5182 18:14:04.475555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 18:14:04.482331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 18:14:04.485765 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 18:14:04.488611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 18:14:04.495999 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 18:14:04.498959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 18:14:04.502572 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 18:14:04.508752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 18:14:04.512192 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 18:14:04.515901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 18:14:04.522269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 18:14:04.525890 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 18:14:04.528947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 18:14:04.535771 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 18:14:04.538848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 18:14:04.542340 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5198 18:14:04.549091 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5199 18:14:04.552224 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 18:14:04.555590 Total UI for P1: 0, mck2ui 16
5201 18:14:04.558575 best dqsien dly found for B0: ( 1, 2, 30)
5202 18:14:04.562185 Total UI for P1: 0, mck2ui 16
5203 18:14:04.565329 best dqsien dly found for B1: ( 1, 3, 0)
5204 18:14:04.569118 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5205 18:14:04.572141 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5206 18:14:04.572216
5207 18:14:04.575768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5208 18:14:04.578824 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5209 18:14:04.581795 [Gating] SW calibration Done
5210 18:14:04.581869 ==
5211 18:14:04.585507 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 18:14:04.588992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 18:14:04.589081 ==
5214 18:14:04.592518 RX Vref Scan: 0
5215 18:14:04.592623
5216 18:14:04.592708 RX Vref 0 -> 0, step: 1
5217 18:14:04.592785
5218 18:14:04.595243 RX Delay -80 -> 252, step: 8
5219 18:14:04.601814 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5220 18:14:04.605160 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5221 18:14:04.608690 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5222 18:14:04.612322 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5223 18:14:04.615275 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5224 18:14:04.618878 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5225 18:14:04.625195 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5226 18:14:04.628517 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5227 18:14:04.631838 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5228 18:14:04.635201 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5229 18:14:04.638779 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5230 18:14:04.645006 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5231 18:14:04.648620 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5232 18:14:04.651895 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5233 18:14:04.654784 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5234 18:14:04.658265 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5235 18:14:04.658388 ==
5236 18:14:04.661978 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 18:14:04.668632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 18:14:04.668713 ==
5239 18:14:04.668793 DQS Delay:
5240 18:14:04.668855 DQS0 = 0, DQS1 = 0
5241 18:14:04.671607 DQM Delay:
5242 18:14:04.671711 DQM0 = 104, DQM1 = 93
5243 18:14:04.675515 DQ Delay:
5244 18:14:04.678478 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5245 18:14:04.681611 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5246 18:14:04.685226 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5247 18:14:04.688072 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5248 18:14:04.688170
5249 18:14:04.688271
5250 18:14:04.688396 ==
5251 18:14:04.691605 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 18:14:04.695194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 18:14:04.695279 ==
5254 18:14:04.695350
5255 18:14:04.695410
5256 18:14:04.698292 TX Vref Scan disable
5257 18:14:04.701869 == TX Byte 0 ==
5258 18:14:04.704831 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5259 18:14:04.708417 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5260 18:14:04.711810 == TX Byte 1 ==
5261 18:14:04.715211 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5262 18:14:04.718281 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5263 18:14:04.718362 ==
5264 18:14:04.721512 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 18:14:04.725177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 18:14:04.725324 ==
5267 18:14:04.728114
5268 18:14:04.728219
5269 18:14:04.728313 TX Vref Scan disable
5270 18:14:04.731666 == TX Byte 0 ==
5271 18:14:04.734592 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5272 18:14:04.738197 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5273 18:14:04.741653 == TX Byte 1 ==
5274 18:14:04.744872 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5275 18:14:04.748314 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5276 18:14:04.751958
5277 18:14:04.752061 [DATLAT]
5278 18:14:04.752164 Freq=933, CH0 RK0
5279 18:14:04.752258
5280 18:14:04.754884 DATLAT Default: 0xd
5281 18:14:04.754974 0, 0xFFFF, sum = 0
5282 18:14:04.758228 1, 0xFFFF, sum = 0
5283 18:14:04.758349 2, 0xFFFF, sum = 0
5284 18:14:04.761631 3, 0xFFFF, sum = 0
5285 18:14:04.761710 4, 0xFFFF, sum = 0
5286 18:14:04.765066 5, 0xFFFF, sum = 0
5287 18:14:04.768558 6, 0xFFFF, sum = 0
5288 18:14:04.768636 7, 0xFFFF, sum = 0
5289 18:14:04.771877 8, 0xFFFF, sum = 0
5290 18:14:04.771961 9, 0xFFFF, sum = 0
5291 18:14:04.774771 10, 0x0, sum = 1
5292 18:14:04.774880 11, 0x0, sum = 2
5293 18:14:04.774976 12, 0x0, sum = 3
5294 18:14:04.777805 13, 0x0, sum = 4
5295 18:14:04.777879 best_step = 11
5296 18:14:04.777942
5297 18:14:04.781334 ==
5298 18:14:04.784335 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 18:14:04.787796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 18:14:04.787895 ==
5301 18:14:04.787991 RX Vref Scan: 1
5302 18:14:04.788087
5303 18:14:04.791708 RX Vref 0 -> 0, step: 1
5304 18:14:04.791809
5305 18:14:04.794550 RX Delay -53 -> 252, step: 4
5306 18:14:04.794657
5307 18:14:04.798170 Set Vref, RX VrefLevel [Byte0]: 57
5308 18:14:04.800998 [Byte1]: 45
5309 18:14:04.801099
5310 18:14:04.804614 Final RX Vref Byte 0 = 57 to rank0
5311 18:14:04.807592 Final RX Vref Byte 1 = 45 to rank0
5312 18:14:04.811168 Final RX Vref Byte 0 = 57 to rank1
5313 18:14:04.814243 Final RX Vref Byte 1 = 45 to rank1==
5314 18:14:04.817685 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 18:14:04.821301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 18:14:04.824371 ==
5317 18:14:04.824448 DQS Delay:
5318 18:14:04.824511 DQS0 = 0, DQS1 = 0
5319 18:14:04.827921 DQM Delay:
5320 18:14:04.827998 DQM0 = 104, DQM1 = 94
5321 18:14:04.830815 DQ Delay:
5322 18:14:04.834478 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5323 18:14:04.837341 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5324 18:14:04.841231 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =88
5325 18:14:04.844009 DQ12 =100, DQ13 =98, DQ14 =108, DQ15 =100
5326 18:14:04.844110
5327 18:14:04.844213
5328 18:14:04.851098 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5329 18:14:04.854372 CH0 RK0: MR19=505, MR18=2F27
5330 18:14:04.860910 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5331 18:14:04.861070
5332 18:14:04.864489 ----->DramcWriteLeveling(PI) begin...
5333 18:14:04.864572 ==
5334 18:14:04.867421 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 18:14:04.870902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 18:14:04.871006 ==
5337 18:14:04.874533 Write leveling (Byte 0): 32 => 32
5338 18:14:04.877333 Write leveling (Byte 1): 29 => 29
5339 18:14:04.881054 DramcWriteLeveling(PI) end<-----
5340 18:14:04.881165
5341 18:14:04.881260 ==
5342 18:14:04.883966 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 18:14:04.887895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 18:14:04.887997 ==
5345 18:14:04.890902 [Gating] SW mode calibration
5346 18:14:04.897786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 18:14:04.904444 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 18:14:04.907457 0 14 0 | B1->B0 | 3232 3131 | 0 1 | (0 0) (1 1)
5349 18:14:04.913996 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 18:14:04.917798 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 18:14:04.920640 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 18:14:04.927669 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 18:14:04.930547 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 18:14:04.934150 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5355 18:14:04.940722 0 14 28 | B1->B0 | 2c2c 2b2b | 0 0 | (0 0) (1 0)
5356 18:14:04.944266 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5357 18:14:04.947959 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 18:14:04.950893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 18:14:04.957362 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 18:14:04.960998 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 18:14:04.963993 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 18:14:04.970559 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5363 18:14:04.974290 0 15 28 | B1->B0 | 3939 3535 | 0 0 | (0 0) (1 1)
5364 18:14:04.977569 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
5365 18:14:04.983987 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 18:14:04.987365 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 18:14:04.990917 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 18:14:04.997693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 18:14:05.000619 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 18:14:05.004524 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 18:14:05.011143 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 18:14:05.014215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 18:14:05.017651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 18:14:05.024110 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 18:14:05.027745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 18:14:05.030561 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 18:14:05.037016 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 18:14:05.040657 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 18:14:05.044308 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 18:14:05.050674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 18:14:05.054350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 18:14:05.057190 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 18:14:05.063953 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 18:14:05.067461 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 18:14:05.070236 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 18:14:05.077049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 18:14:05.080549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 18:14:05.083931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 18:14:05.086796 Total UI for P1: 0, mck2ui 16
5390 18:14:05.090235 best dqsien dly found for B0: ( 1, 2, 30)
5391 18:14:05.093448 Total UI for P1: 0, mck2ui 16
5392 18:14:05.096832 best dqsien dly found for B1: ( 1, 2, 30)
5393 18:14:05.100053 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5394 18:14:05.103940 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5395 18:14:05.104049
5396 18:14:05.106687 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5397 18:14:05.113826 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5398 18:14:05.113910 [Gating] SW calibration Done
5399 18:14:05.113975 ==
5400 18:14:05.116723 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 18:14:05.123449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 18:14:05.123560 ==
5403 18:14:05.123672 RX Vref Scan: 0
5404 18:14:05.123763
5405 18:14:05.127113 RX Vref 0 -> 0, step: 1
5406 18:14:05.127215
5407 18:14:05.130059 RX Delay -80 -> 252, step: 8
5408 18:14:05.133617 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5409 18:14:05.137120 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5410 18:14:05.140156 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5411 18:14:05.143649 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5412 18:14:05.150269 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5413 18:14:05.153315 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5414 18:14:05.156975 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5415 18:14:05.159820 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5416 18:14:05.163303 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5417 18:14:05.166744 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5418 18:14:05.173364 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5419 18:14:05.176476 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5420 18:14:05.180051 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5421 18:14:05.183149 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5422 18:14:05.186630 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5423 18:14:05.193311 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5424 18:14:05.193391 ==
5425 18:14:05.196280 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 18:14:05.199818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 18:14:05.199926 ==
5428 18:14:05.200025 DQS Delay:
5429 18:14:05.202695 DQS0 = 0, DQS1 = 0
5430 18:14:05.202773 DQM Delay:
5431 18:14:05.206447 DQM0 = 105, DQM1 = 94
5432 18:14:05.206558 DQ Delay:
5433 18:14:05.209840 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5434 18:14:05.213112 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5435 18:14:05.216438 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5436 18:14:05.219546 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5437 18:14:05.219623
5438 18:14:05.219707
5439 18:14:05.219771 ==
5440 18:14:05.222731 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 18:14:05.229528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 18:14:05.229613 ==
5443 18:14:05.229698
5444 18:14:05.229761
5445 18:14:05.229823 TX Vref Scan disable
5446 18:14:05.233008 == TX Byte 0 ==
5447 18:14:05.236560 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5448 18:14:05.243032 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5449 18:14:05.243111 == TX Byte 1 ==
5450 18:14:05.245849 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5451 18:14:05.253048 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5452 18:14:05.253155 ==
5453 18:14:05.255969 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 18:14:05.259763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 18:14:05.259843 ==
5456 18:14:05.259907
5457 18:14:05.259983
5458 18:14:05.262682 TX Vref Scan disable
5459 18:14:05.262783 == TX Byte 0 ==
5460 18:14:05.269952 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5461 18:14:05.273073 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5462 18:14:05.273181 == TX Byte 1 ==
5463 18:14:05.279444 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 18:14:05.282477 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 18:14:05.282560
5466 18:14:05.282625 [DATLAT]
5467 18:14:05.286295 Freq=933, CH0 RK1
5468 18:14:05.286378
5469 18:14:05.286442 DATLAT Default: 0xb
5470 18:14:05.289255 0, 0xFFFF, sum = 0
5471 18:14:05.289340 1, 0xFFFF, sum = 0
5472 18:14:05.292938 2, 0xFFFF, sum = 0
5473 18:14:05.293022 3, 0xFFFF, sum = 0
5474 18:14:05.295960 4, 0xFFFF, sum = 0
5475 18:14:05.296044 5, 0xFFFF, sum = 0
5476 18:14:05.299729 6, 0xFFFF, sum = 0
5477 18:14:05.302642 7, 0xFFFF, sum = 0
5478 18:14:05.302726 8, 0xFFFF, sum = 0
5479 18:14:05.306210 9, 0xFFFF, sum = 0
5480 18:14:05.306293 10, 0x0, sum = 1
5481 18:14:05.309194 11, 0x0, sum = 2
5482 18:14:05.309276 12, 0x0, sum = 3
5483 18:14:05.309342 13, 0x0, sum = 4
5484 18:14:05.312824 best_step = 11
5485 18:14:05.312911
5486 18:14:05.313011 ==
5487 18:14:05.315883 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 18:14:05.318927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 18:14:05.319039 ==
5490 18:14:05.322769 RX Vref Scan: 0
5491 18:14:05.322877
5492 18:14:05.322979 RX Vref 0 -> 0, step: 1
5493 18:14:05.326395
5494 18:14:05.326480 RX Delay -45 -> 252, step: 4
5495 18:14:05.333247 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5496 18:14:05.336485 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5497 18:14:05.339682 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5498 18:14:05.342793 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5499 18:14:05.346809 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5500 18:14:05.353120 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5501 18:14:05.356308 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5502 18:14:05.360078 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5503 18:14:05.363104 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5504 18:14:05.366306 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5505 18:14:05.373005 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5506 18:14:05.376545 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5507 18:14:05.379282 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5508 18:14:05.383032 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5509 18:14:05.385955 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5510 18:14:05.392603 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5511 18:14:05.392690 ==
5512 18:14:05.395979 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 18:14:05.399669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 18:14:05.399780 ==
5515 18:14:05.399883 DQS Delay:
5516 18:14:05.402673 DQS0 = 0, DQS1 = 0
5517 18:14:05.402771 DQM Delay:
5518 18:14:05.406312 DQM0 = 104, DQM1 = 93
5519 18:14:05.406417 DQ Delay:
5520 18:14:05.409895 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5521 18:14:05.412763 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5522 18:14:05.416518 DQ8 =82, DQ9 =82, DQ10 =96, DQ11 =88
5523 18:14:05.419512 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =100
5524 18:14:05.419618
5525 18:14:05.419723
5526 18:14:05.429765 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5527 18:14:05.429857 CH0 RK1: MR19=505, MR18=2B04
5528 18:14:05.436453 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5529 18:14:05.439424 [RxdqsGatingPostProcess] freq 933
5530 18:14:05.445825 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 18:14:05.449405 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 18:14:05.453136 best DQS1 dly(2T, 0.5T) = (0, 11)
5533 18:14:05.456534 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 18:14:05.459386 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5535 18:14:05.462952 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 18:14:05.465725 best DQS1 dly(2T, 0.5T) = (0, 10)
5537 18:14:05.469142 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 18:14:05.472481 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5539 18:14:05.472557 Pre-setting of DQS Precalculation
5540 18:14:05.478856 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 18:14:05.478929 ==
5542 18:14:05.482525 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 18:14:05.485650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 18:14:05.485726 ==
5545 18:14:05.492602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 18:14:05.498979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5547 18:14:05.502371 [CA 0] Center 36 (6~67) winsize 62
5548 18:14:05.505700 [CA 1] Center 36 (6~67) winsize 62
5549 18:14:05.508693 [CA 2] Center 34 (4~65) winsize 62
5550 18:14:05.512357 [CA 3] Center 34 (4~65) winsize 62
5551 18:14:05.515480 [CA 4] Center 34 (4~65) winsize 62
5552 18:14:05.518558 [CA 5] Center 33 (3~64) winsize 62
5553 18:14:05.518653
5554 18:14:05.522252 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5555 18:14:05.522329
5556 18:14:05.525240 [CATrainingPosCal] consider 1 rank data
5557 18:14:05.529054 u2DelayCellTimex100 = 270/100 ps
5558 18:14:05.531954 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 18:14:05.535739 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 18:14:05.538600 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 18:14:05.542272 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 18:14:05.545832 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 18:14:05.548759 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 18:14:05.548835
5565 18:14:05.555386 CA PerBit enable=1, Macro0, CA PI delay=33
5566 18:14:05.555465
5567 18:14:05.559083 [CBTSetCACLKResult] CA Dly = 33
5568 18:14:05.559165 CS Dly: 7 (0~38)
5569 18:14:05.559229 ==
5570 18:14:05.562071 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 18:14:05.565136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 18:14:05.565208 ==
5573 18:14:05.571764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 18:14:05.579129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5575 18:14:05.582125 [CA 0] Center 37 (6~68) winsize 63
5576 18:14:05.585013 [CA 1] Center 37 (7~68) winsize 62
5577 18:14:05.588696 [CA 2] Center 35 (5~66) winsize 62
5578 18:14:05.592063 [CA 3] Center 34 (4~65) winsize 62
5579 18:14:05.595024 [CA 4] Center 34 (4~65) winsize 62
5580 18:14:05.598789 [CA 5] Center 34 (4~64) winsize 61
5581 18:14:05.598862
5582 18:14:05.601587 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5583 18:14:05.601655
5584 18:14:05.605264 [CATrainingPosCal] consider 2 rank data
5585 18:14:05.608746 u2DelayCellTimex100 = 270/100 ps
5586 18:14:05.612026 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5587 18:14:05.615194 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5588 18:14:05.618146 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5589 18:14:05.621521 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5590 18:14:05.625341 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5591 18:14:05.631566 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5592 18:14:05.631642
5593 18:14:05.635389 CA PerBit enable=1, Macro0, CA PI delay=34
5594 18:14:05.635458
5595 18:14:05.638304 [CBTSetCACLKResult] CA Dly = 34
5596 18:14:05.638374 CS Dly: 8 (0~40)
5597 18:14:05.638435
5598 18:14:05.641960 ----->DramcWriteLeveling(PI) begin...
5599 18:14:05.642027 ==
5600 18:14:05.645030 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 18:14:05.648740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 18:14:05.651601 ==
5603 18:14:05.655258 Write leveling (Byte 0): 23 => 23
5604 18:14:05.655330 Write leveling (Byte 1): 25 => 25
5605 18:14:05.658158 DramcWriteLeveling(PI) end<-----
5606 18:14:05.658252
5607 18:14:05.658352 ==
5608 18:14:05.661776 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 18:14:05.668504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 18:14:05.668582 ==
5611 18:14:05.671561 [Gating] SW mode calibration
5612 18:14:05.678131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 18:14:05.681829 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 18:14:05.687998 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 18:14:05.691709 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 18:14:05.694772 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 18:14:05.701563 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 18:14:05.705177 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 18:14:05.708065 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5620 18:14:05.711797 0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 1)
5621 18:14:05.718261 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
5622 18:14:05.721932 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 18:14:05.724792 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 18:14:05.731969 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 18:14:05.734593 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 18:14:05.738146 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 18:14:05.744961 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 18:14:05.748685 0 15 24 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5629 18:14:05.751175 0 15 28 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5630 18:14:05.758208 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 18:14:05.761495 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 18:14:05.764467 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 18:14:05.771091 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 18:14:05.774743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 18:14:05.777663 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 18:14:05.784860 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5637 18:14:05.787811 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5638 18:14:05.791068 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 18:14:05.797719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 18:14:05.801424 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 18:14:05.804274 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 18:14:05.810936 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 18:14:05.814521 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 18:14:05.817519 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 18:14:05.824103 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 18:14:05.827670 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 18:14:05.830478 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 18:14:05.837269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 18:14:05.840362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 18:14:05.843946 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 18:14:05.851058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 18:14:05.853924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5653 18:14:05.857356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5654 18:14:05.860811 Total UI for P1: 0, mck2ui 16
5655 18:14:05.864201 best dqsien dly found for B1: ( 1, 2, 24)
5656 18:14:05.870923 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 18:14:05.871036 Total UI for P1: 0, mck2ui 16
5658 18:14:05.874257 best dqsien dly found for B0: ( 1, 2, 26)
5659 18:14:05.880274 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5660 18:14:05.884169 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5661 18:14:05.884298
5662 18:14:05.887007 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5663 18:14:05.890153 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5664 18:14:05.893606 [Gating] SW calibration Done
5665 18:14:05.893710 ==
5666 18:14:05.896897 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 18:14:05.900440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 18:14:05.900520 ==
5669 18:14:05.904219 RX Vref Scan: 0
5670 18:14:05.904318
5671 18:14:05.904397 RX Vref 0 -> 0, step: 1
5672 18:14:05.904458
5673 18:14:05.907087 RX Delay -80 -> 252, step: 8
5674 18:14:05.910753 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5675 18:14:05.917099 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5676 18:14:05.920318 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5677 18:14:05.924060 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5678 18:14:05.927006 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5679 18:14:05.930626 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5680 18:14:05.933598 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 18:14:05.937076 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5682 18:14:05.943561 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5683 18:14:05.947349 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5684 18:14:05.950312 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5685 18:14:05.954062 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5686 18:14:05.957138 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5687 18:14:05.960708 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5688 18:14:05.966929 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5689 18:14:05.970360 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5690 18:14:05.970437 ==
5691 18:14:05.974049 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 18:14:05.977025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 18:14:05.977128 ==
5694 18:14:05.980816 DQS Delay:
5695 18:14:05.980895 DQS0 = 0, DQS1 = 0
5696 18:14:05.980962 DQM Delay:
5697 18:14:05.983653 DQM0 = 102, DQM1 = 98
5698 18:14:05.983727 DQ Delay:
5699 18:14:05.987032 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5700 18:14:05.990608 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5701 18:14:05.993774 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5702 18:14:05.996803 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5703 18:14:06.000348
5704 18:14:06.000431
5705 18:14:06.000514 ==
5706 18:14:06.003945 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 18:14:06.006673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 18:14:06.006748 ==
5709 18:14:06.006832
5710 18:14:06.006911
5711 18:14:06.010043 TX Vref Scan disable
5712 18:14:06.010127 == TX Byte 0 ==
5713 18:14:06.016995 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5714 18:14:06.020545 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5715 18:14:06.020625 == TX Byte 1 ==
5716 18:14:06.026931 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5717 18:14:06.030165 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5718 18:14:06.030249 ==
5719 18:14:06.033735 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 18:14:06.036573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 18:14:06.036656 ==
5722 18:14:06.036721
5723 18:14:06.036781
5724 18:14:06.040276 TX Vref Scan disable
5725 18:14:06.043271 == TX Byte 0 ==
5726 18:14:06.047042 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5727 18:14:06.050048 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5728 18:14:06.053681 == TX Byte 1 ==
5729 18:14:06.056768 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5730 18:14:06.060382 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5731 18:14:06.060492
5732 18:14:06.063400 [DATLAT]
5733 18:14:06.063481 Freq=933, CH1 RK0
5734 18:14:06.063546
5735 18:14:06.067038 DATLAT Default: 0xd
5736 18:14:06.067127 0, 0xFFFF, sum = 0
5737 18:14:06.069843 1, 0xFFFF, sum = 0
5738 18:14:06.069923 2, 0xFFFF, sum = 0
5739 18:14:06.073505 3, 0xFFFF, sum = 0
5740 18:14:06.073589 4, 0xFFFF, sum = 0
5741 18:14:06.076557 5, 0xFFFF, sum = 0
5742 18:14:06.076655 6, 0xFFFF, sum = 0
5743 18:14:06.080045 7, 0xFFFF, sum = 0
5744 18:14:06.080133 8, 0xFFFF, sum = 0
5745 18:14:06.082972 9, 0xFFFF, sum = 0
5746 18:14:06.083050 10, 0x0, sum = 1
5747 18:14:06.086619 11, 0x0, sum = 2
5748 18:14:06.086699 12, 0x0, sum = 3
5749 18:14:06.089664 13, 0x0, sum = 4
5750 18:14:06.089742 best_step = 11
5751 18:14:06.089836
5752 18:14:06.089914 ==
5753 18:14:06.093303 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 18:14:06.099960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 18:14:06.100055 ==
5756 18:14:06.100137 RX Vref Scan: 1
5757 18:14:06.100233
5758 18:14:06.103172 RX Vref 0 -> 0, step: 1
5759 18:14:06.103246
5760 18:14:06.106717 RX Delay -45 -> 252, step: 4
5761 18:14:06.106792
5762 18:14:06.109810 Set Vref, RX VrefLevel [Byte0]: 53
5763 18:14:06.112604 [Byte1]: 53
5764 18:14:06.112686
5765 18:14:06.116294 Final RX Vref Byte 0 = 53 to rank0
5766 18:14:06.119899 Final RX Vref Byte 1 = 53 to rank0
5767 18:14:06.123189 Final RX Vref Byte 0 = 53 to rank1
5768 18:14:06.126633 Final RX Vref Byte 1 = 53 to rank1==
5769 18:14:06.129918 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 18:14:06.133354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 18:14:06.133436 ==
5772 18:14:06.136209 DQS Delay:
5773 18:14:06.136334 DQS0 = 0, DQS1 = 0
5774 18:14:06.136421 DQM Delay:
5775 18:14:06.139763 DQM0 = 102, DQM1 = 99
5776 18:14:06.139879 DQ Delay:
5777 18:14:06.142853 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5778 18:14:06.146686 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5779 18:14:06.149630 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5780 18:14:06.152807 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5781 18:14:06.152888
5782 18:14:06.156418
5783 18:14:06.163113 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5784 18:14:06.166189 CH1 RK0: MR19=505, MR18=1830
5785 18:14:06.172932 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5786 18:14:06.173022
5787 18:14:06.175879 ----->DramcWriteLeveling(PI) begin...
5788 18:14:06.175956 ==
5789 18:14:06.179653 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 18:14:06.182559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 18:14:06.182651 ==
5792 18:14:06.186360 Write leveling (Byte 0): 24 => 24
5793 18:14:06.189143 Write leveling (Byte 1): 26 => 26
5794 18:14:06.192913 DramcWriteLeveling(PI) end<-----
5795 18:14:06.192989
5796 18:14:06.193101 ==
5797 18:14:06.195867 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 18:14:06.199546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 18:14:06.199658 ==
5800 18:14:06.202586 [Gating] SW mode calibration
5801 18:14:06.209126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 18:14:06.216316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 18:14:06.219049 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 18:14:06.222865 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 18:14:06.229423 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 18:14:06.232925 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 18:14:06.235603 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 18:14:06.242294 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 18:14:06.245891 0 14 24 | B1->B0 | 2f2f 3333 | 0 0 | (0 1) (0 1)
5810 18:14:06.248790 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5811 18:14:06.255638 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 18:14:06.259279 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 18:14:06.262641 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 18:14:06.269391 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 18:14:06.272347 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 18:14:06.276112 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 18:14:06.282635 0 15 24 | B1->B0 | 3232 2626 | 0 1 | (0 0) (0 0)
5818 18:14:06.285518 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5819 18:14:06.289148 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 18:14:06.295927 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 18:14:06.298891 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 18:14:06.302614 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 18:14:06.309270 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 18:14:06.312230 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 18:14:06.315959 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5826 18:14:06.318970 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5827 18:14:06.325435 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 18:14:06.329041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 18:14:06.332206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 18:14:06.338694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 18:14:06.342250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 18:14:06.345782 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 18:14:06.352095 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 18:14:06.355517 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 18:14:06.358480 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 18:14:06.365732 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 18:14:06.368487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 18:14:06.372219 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 18:14:06.378838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 18:14:06.382131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 18:14:06.385375 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5842 18:14:06.391718 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5843 18:14:06.395375 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 18:14:06.398323 Total UI for P1: 0, mck2ui 16
5845 18:14:06.402026 best dqsien dly found for B0: ( 1, 2, 28)
5846 18:14:06.404825 Total UI for P1: 0, mck2ui 16
5847 18:14:06.408705 best dqsien dly found for B1: ( 1, 2, 26)
5848 18:14:06.411522 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5849 18:14:06.415375 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5850 18:14:06.415451
5851 18:14:06.418316 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5852 18:14:06.422286 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 18:14:06.425173 [Gating] SW calibration Done
5854 18:14:06.425246 ==
5855 18:14:06.428154 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 18:14:06.434762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 18:14:06.434862 ==
5858 18:14:06.434962 RX Vref Scan: 0
5859 18:14:06.435050
5860 18:14:06.438571 RX Vref 0 -> 0, step: 1
5861 18:14:06.438676
5862 18:14:06.441378 RX Delay -80 -> 252, step: 8
5863 18:14:06.444906 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5864 18:14:06.448190 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5865 18:14:06.451588 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5866 18:14:06.455107 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5867 18:14:06.457826 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5868 18:14:06.464659 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5869 18:14:06.468114 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5870 18:14:06.471627 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5871 18:14:06.474334 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5872 18:14:06.478040 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5873 18:14:06.481110 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5874 18:14:06.487736 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5875 18:14:06.491228 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5876 18:14:06.494789 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5877 18:14:06.498184 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5878 18:14:06.500918 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5879 18:14:06.504852 ==
5880 18:14:06.504924 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 18:14:06.511189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 18:14:06.511268 ==
5883 18:14:06.511335 DQS Delay:
5884 18:14:06.515060 DQS0 = 0, DQS1 = 0
5885 18:14:06.515135 DQM Delay:
5886 18:14:06.517938 DQM0 = 103, DQM1 = 98
5887 18:14:06.518011 DQ Delay:
5888 18:14:06.520950 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5889 18:14:06.524535 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5890 18:14:06.528169 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5891 18:14:06.531129 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5892 18:14:06.531266
5893 18:14:06.531349
5894 18:14:06.531413 ==
5895 18:14:06.534088 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 18:14:06.537972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 18:14:06.538044 ==
5898 18:14:06.538105
5899 18:14:06.540966
5900 18:14:06.541038 TX Vref Scan disable
5901 18:14:06.544580 == TX Byte 0 ==
5902 18:14:06.547483 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5903 18:14:06.550960 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5904 18:14:06.554559 == TX Byte 1 ==
5905 18:14:06.557328 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5906 18:14:06.560716 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5907 18:14:06.560800 ==
5908 18:14:06.564353 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 18:14:06.570839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 18:14:06.570926 ==
5911 18:14:06.570994
5912 18:14:06.571058
5913 18:14:06.571120 TX Vref Scan disable
5914 18:14:06.575217 == TX Byte 0 ==
5915 18:14:06.578158 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5916 18:14:06.581597 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5917 18:14:06.584986 == TX Byte 1 ==
5918 18:14:06.588667 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5919 18:14:06.595410 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5920 18:14:06.595501
5921 18:14:06.595567 [DATLAT]
5922 18:14:06.595647 Freq=933, CH1 RK1
5923 18:14:06.595708
5924 18:14:06.598343 DATLAT Default: 0xb
5925 18:14:06.598427 0, 0xFFFF, sum = 0
5926 18:14:06.601508 1, 0xFFFF, sum = 0
5927 18:14:06.601608 2, 0xFFFF, sum = 0
5928 18:14:06.605070 3, 0xFFFF, sum = 0
5929 18:14:06.607978 4, 0xFFFF, sum = 0
5930 18:14:06.608062 5, 0xFFFF, sum = 0
5931 18:14:06.611432 6, 0xFFFF, sum = 0
5932 18:14:06.611516 7, 0xFFFF, sum = 0
5933 18:14:06.614807 8, 0xFFFF, sum = 0
5934 18:14:06.614917 9, 0xFFFF, sum = 0
5935 18:14:06.618113 10, 0x0, sum = 1
5936 18:14:06.618231 11, 0x0, sum = 2
5937 18:14:06.618350 12, 0x0, sum = 3
5938 18:14:06.621300 13, 0x0, sum = 4
5939 18:14:06.621405 best_step = 11
5940 18:14:06.621484
5941 18:14:06.624542 ==
5942 18:14:06.627850 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 18:14:06.631544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 18:14:06.631632 ==
5945 18:14:06.631780 RX Vref Scan: 0
5946 18:14:06.631859
5947 18:14:06.634369 RX Vref 0 -> 0, step: 1
5948 18:14:06.634448
5949 18:14:06.638119 RX Delay -45 -> 252, step: 4
5950 18:14:06.641207 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5951 18:14:06.647811 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5952 18:14:06.651542 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5953 18:14:06.654505 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5954 18:14:06.658145 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5955 18:14:06.661184 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5956 18:14:06.668013 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5957 18:14:06.670733 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5958 18:14:06.674284 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5959 18:14:06.677991 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5960 18:14:06.680950 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5961 18:14:06.687558 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5962 18:14:06.691107 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5963 18:14:06.694685 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5964 18:14:06.697903 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5965 18:14:06.700614 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5966 18:14:06.704175 ==
5967 18:14:06.704287 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 18:14:06.710926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 18:14:06.711039 ==
5970 18:14:06.711139 DQS Delay:
5971 18:14:06.714701 DQS0 = 0, DQS1 = 0
5972 18:14:06.714806 DQM Delay:
5973 18:14:06.717568 DQM0 = 104, DQM1 = 100
5974 18:14:06.717649 DQ Delay:
5975 18:14:06.721277 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5976 18:14:06.724175 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5977 18:14:06.727674 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5978 18:14:06.730602 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5979 18:14:06.730680
5980 18:14:06.730745
5981 18:14:06.740852 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5982 18:14:06.740938 CH1 RK1: MR19=504, MR18=2BFE
5983 18:14:06.747989 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5984 18:14:06.750930 [RxdqsGatingPostProcess] freq 933
5985 18:14:06.757760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 18:14:06.760612 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 18:14:06.764144 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 18:14:06.767118 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 18:14:06.771009 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 18:14:06.771093 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 18:14:06.774595 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 18:14:06.777348 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 18:14:06.780541 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 18:14:06.784077 Pre-setting of DQS Precalculation
5995 18:14:06.790686 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 18:14:06.797152 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 18:14:06.804278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 18:14:06.804411
5999 18:14:06.804478
6000 18:14:06.807122 [Calibration Summary] 1866 Mbps
6001 18:14:06.807204 CH 0, Rank 0
6002 18:14:06.810519 SW Impedance : PASS
6003 18:14:06.813891 DUTY Scan : NO K
6004 18:14:06.813998 ZQ Calibration : PASS
6005 18:14:06.816940 Jitter Meter : NO K
6006 18:14:06.820540 CBT Training : PASS
6007 18:14:06.820648 Write leveling : PASS
6008 18:14:06.824246 RX DQS gating : PASS
6009 18:14:06.827271 RX DQ/DQS(RDDQC) : PASS
6010 18:14:06.827377 TX DQ/DQS : PASS
6011 18:14:06.830839 RX DATLAT : PASS
6012 18:14:06.833718 RX DQ/DQS(Engine): PASS
6013 18:14:06.833826 TX OE : NO K
6014 18:14:06.833919 All Pass.
6015 18:14:06.834007
6016 18:14:06.837517 CH 0, Rank 1
6017 18:14:06.840528 SW Impedance : PASS
6018 18:14:06.840609 DUTY Scan : NO K
6019 18:14:06.844039 ZQ Calibration : PASS
6020 18:14:06.844133 Jitter Meter : NO K
6021 18:14:06.846880 CBT Training : PASS
6022 18:14:06.850218 Write leveling : PASS
6023 18:14:06.850355 RX DQS gating : PASS
6024 18:14:06.853509 RX DQ/DQS(RDDQC) : PASS
6025 18:14:06.856947 TX DQ/DQS : PASS
6026 18:14:06.857055 RX DATLAT : PASS
6027 18:14:06.860243 RX DQ/DQS(Engine): PASS
6028 18:14:06.863656 TX OE : NO K
6029 18:14:06.863751 All Pass.
6030 18:14:06.863829
6031 18:14:06.863890 CH 1, Rank 0
6032 18:14:06.866997 SW Impedance : PASS
6033 18:14:06.870604 DUTY Scan : NO K
6034 18:14:06.870684 ZQ Calibration : PASS
6035 18:14:06.873593 Jitter Meter : NO K
6036 18:14:06.877126 CBT Training : PASS
6037 18:14:06.877207 Write leveling : PASS
6038 18:14:06.880170 RX DQS gating : PASS
6039 18:14:06.883953 RX DQ/DQS(RDDQC) : PASS
6040 18:14:06.884030 TX DQ/DQS : PASS
6041 18:14:06.886846 RX DATLAT : PASS
6042 18:14:06.886944 RX DQ/DQS(Engine): PASS
6043 18:14:06.890042 TX OE : NO K
6044 18:14:06.890141 All Pass.
6045 18:14:06.890230
6046 18:14:06.893354 CH 1, Rank 1
6047 18:14:06.893432 SW Impedance : PASS
6048 18:14:06.897133 DUTY Scan : NO K
6049 18:14:06.899964 ZQ Calibration : PASS
6050 18:14:06.900070 Jitter Meter : NO K
6051 18:14:06.903614 CBT Training : PASS
6052 18:14:06.907203 Write leveling : PASS
6053 18:14:06.907306 RX DQS gating : PASS
6054 18:14:06.910109 RX DQ/DQS(RDDQC) : PASS
6055 18:14:06.914019 TX DQ/DQS : PASS
6056 18:14:06.914098 RX DATLAT : PASS
6057 18:14:06.916926 RX DQ/DQS(Engine): PASS
6058 18:14:06.920390 TX OE : NO K
6059 18:14:06.920475 All Pass.
6060 18:14:06.920540
6061 18:14:06.920601 DramC Write-DBI off
6062 18:14:06.923897 PER_BANK_REFRESH: Hybrid Mode
6063 18:14:06.927291 TX_TRACKING: ON
6064 18:14:06.933843 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 18:14:06.936715 [FAST_K] Save calibration result to emmc
6066 18:14:06.943336 dramc_set_vcore_voltage set vcore to 650000
6067 18:14:06.943419 Read voltage for 400, 6
6068 18:14:06.947067 Vio18 = 0
6069 18:14:06.947170 Vcore = 650000
6070 18:14:06.947262 Vdram = 0
6071 18:14:06.947350 Vddq = 0
6072 18:14:06.950700 Vmddr = 0
6073 18:14:06.953664 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 18:14:06.960225 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 18:14:06.964011 MEM_TYPE=3, freq_sel=20
6076 18:14:06.964086 sv_algorithm_assistance_LP4_800
6077 18:14:06.970230 ============ PULL DRAM RESETB DOWN ============
6078 18:14:06.973607 ========== PULL DRAM RESETB DOWN end =========
6079 18:14:06.976890 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 18:14:06.980160 ===================================
6081 18:14:06.983506 LPDDR4 DRAM CONFIGURATION
6082 18:14:06.987261 ===================================
6083 18:14:06.990127 EX_ROW_EN[0] = 0x0
6084 18:14:06.990229 EX_ROW_EN[1] = 0x0
6085 18:14:06.993142 LP4Y_EN = 0x0
6086 18:14:06.993213 WORK_FSP = 0x0
6087 18:14:06.996693 WL = 0x2
6088 18:14:06.996766 RL = 0x2
6089 18:14:07.000454 BL = 0x2
6090 18:14:07.000555 RPST = 0x0
6091 18:14:07.003031 RD_PRE = 0x0
6092 18:14:07.003134 WR_PRE = 0x1
6093 18:14:07.006371 WR_PST = 0x0
6094 18:14:07.006472 DBI_WR = 0x0
6095 18:14:07.009822 DBI_RD = 0x0
6096 18:14:07.009924 OTF = 0x1
6097 18:14:07.013307 ===================================
6098 18:14:07.016913 ===================================
6099 18:14:07.019896 ANA top config
6100 18:14:07.023527 ===================================
6101 18:14:07.026565 DLL_ASYNC_EN = 0
6102 18:14:07.026672 ALL_SLAVE_EN = 1
6103 18:14:07.030082 NEW_RANK_MODE = 1
6104 18:14:07.032905 DLL_IDLE_MODE = 1
6105 18:14:07.036795 LP45_APHY_COMB_EN = 1
6106 18:14:07.039562 TX_ODT_DIS = 1
6107 18:14:07.039663 NEW_8X_MODE = 1
6108 18:14:07.043339 ===================================
6109 18:14:07.046293 ===================================
6110 18:14:07.049997 data_rate = 800
6111 18:14:07.052986 CKR = 1
6112 18:14:07.056705 DQ_P2S_RATIO = 4
6113 18:14:07.059649 ===================================
6114 18:14:07.063424 CA_P2S_RATIO = 4
6115 18:14:07.066516 DQ_CA_OPEN = 0
6116 18:14:07.066601 DQ_SEMI_OPEN = 1
6117 18:14:07.069404 CA_SEMI_OPEN = 1
6118 18:14:07.072908 CA_FULL_RATE = 0
6119 18:14:07.076830 DQ_CKDIV4_EN = 0
6120 18:14:07.079641 CA_CKDIV4_EN = 1
6121 18:14:07.083093 CA_PREDIV_EN = 0
6122 18:14:07.083169 PH8_DLY = 0
6123 18:14:07.085892 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 18:14:07.089514 DQ_AAMCK_DIV = 0
6125 18:14:07.092775 CA_AAMCK_DIV = 0
6126 18:14:07.096116 CA_ADMCK_DIV = 4
6127 18:14:07.099844 DQ_TRACK_CA_EN = 0
6128 18:14:07.099923 CA_PICK = 800
6129 18:14:07.102853 CA_MCKIO = 400
6130 18:14:07.105810 MCKIO_SEMI = 400
6131 18:14:07.109549 PLL_FREQ = 3016
6132 18:14:07.113100 DQ_UI_PI_RATIO = 32
6133 18:14:07.115756 CA_UI_PI_RATIO = 32
6134 18:14:07.119158 ===================================
6135 18:14:07.122508 ===================================
6136 18:14:07.122610 memory_type:LPDDR4
6137 18:14:07.125731 GP_NUM : 10
6138 18:14:07.129276 SRAM_EN : 1
6139 18:14:07.129387 MD32_EN : 0
6140 18:14:07.132319 ===================================
6141 18:14:07.136037 [ANA_INIT] >>>>>>>>>>>>>>
6142 18:14:07.138949 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 18:14:07.142575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 18:14:07.145938 ===================================
6145 18:14:07.149366 data_rate = 800,PCW = 0X7400
6146 18:14:07.152778 ===================================
6147 18:14:07.155636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 18:14:07.159448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 18:14:07.172836 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 18:14:07.175646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 18:14:07.179315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 18:14:07.182233 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 18:14:07.185773 [ANA_INIT] flow start
6154 18:14:07.189527 [ANA_INIT] PLL >>>>>>>>
6155 18:14:07.189644 [ANA_INIT] PLL <<<<<<<<
6156 18:14:07.192419 [ANA_INIT] MIDPI >>>>>>>>
6157 18:14:07.196110 [ANA_INIT] MIDPI <<<<<<<<
6158 18:14:07.196207 [ANA_INIT] DLL >>>>>>>>
6159 18:14:07.199054 [ANA_INIT] flow end
6160 18:14:07.202630 ============ LP4 DIFF to SE enter ============
6161 18:14:07.205994 ============ LP4 DIFF to SE exit ============
6162 18:14:07.209316 [ANA_INIT] <<<<<<<<<<<<<
6163 18:14:07.212179 [Flow] Enable top DCM control >>>>>
6164 18:14:07.215831 [Flow] Enable top DCM control <<<<<
6165 18:14:07.218888 Enable DLL master slave shuffle
6166 18:14:07.225888 ==============================================================
6167 18:14:07.225994 Gating Mode config
6168 18:14:07.232277 ==============================================================
6169 18:14:07.232398 Config description:
6170 18:14:07.242516 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 18:14:07.249115 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 18:14:07.255777 SELPH_MODE 0: By rank 1: By Phase
6173 18:14:07.258643 ==============================================================
6174 18:14:07.262113 GAT_TRACK_EN = 0
6175 18:14:07.265561 RX_GATING_MODE = 2
6176 18:14:07.268986 RX_GATING_TRACK_MODE = 2
6177 18:14:07.272038 SELPH_MODE = 1
6178 18:14:07.275794 PICG_EARLY_EN = 1
6179 18:14:07.278830 VALID_LAT_VALUE = 1
6180 18:14:07.285372 ==============================================================
6181 18:14:07.289014 Enter into Gating configuration >>>>
6182 18:14:07.291812 Exit from Gating configuration <<<<
6183 18:14:07.295615 Enter into DVFS_PRE_config >>>>>
6184 18:14:07.305113 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 18:14:07.308708 Exit from DVFS_PRE_config <<<<<
6186 18:14:07.311723 Enter into PICG configuration >>>>
6187 18:14:07.315222 Exit from PICG configuration <<<<
6188 18:14:07.318194 [RX_INPUT] configuration >>>>>
6189 18:14:07.318290 [RX_INPUT] configuration <<<<<
6190 18:14:07.325331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 18:14:07.332082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 18:14:07.335217 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 18:14:07.341610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 18:14:07.348006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 18:14:07.355310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 18:14:07.358223 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 18:14:07.361928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 18:14:07.368557 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 18:14:07.371884 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 18:14:07.375361 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 18:14:07.378619 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 18:14:07.381977 ===================================
6203 18:14:07.384817 LPDDR4 DRAM CONFIGURATION
6204 18:14:07.388319 ===================================
6205 18:14:07.391196 EX_ROW_EN[0] = 0x0
6206 18:14:07.391295 EX_ROW_EN[1] = 0x0
6207 18:14:07.394784 LP4Y_EN = 0x0
6208 18:14:07.394865 WORK_FSP = 0x0
6209 18:14:07.398274 WL = 0x2
6210 18:14:07.398355 RL = 0x2
6211 18:14:07.401249 BL = 0x2
6212 18:14:07.405020 RPST = 0x0
6213 18:14:07.405101 RD_PRE = 0x0
6214 18:14:07.407989 WR_PRE = 0x1
6215 18:14:07.408070 WR_PST = 0x0
6216 18:14:07.411853 DBI_WR = 0x0
6217 18:14:07.411934 DBI_RD = 0x0
6218 18:14:07.414861 OTF = 0x1
6219 18:14:07.417836 ===================================
6220 18:14:07.421568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 18:14:07.424690 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 18:14:07.428228 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 18:14:07.431107 ===================================
6224 18:14:07.434455 LPDDR4 DRAM CONFIGURATION
6225 18:14:07.437867 ===================================
6226 18:14:07.441446 EX_ROW_EN[0] = 0x10
6227 18:14:07.441602 EX_ROW_EN[1] = 0x0
6228 18:14:07.445138 LP4Y_EN = 0x0
6229 18:14:07.445248 WORK_FSP = 0x0
6230 18:14:07.448227 WL = 0x2
6231 18:14:07.448309 RL = 0x2
6232 18:14:07.451214 BL = 0x2
6233 18:14:07.451306 RPST = 0x0
6234 18:14:07.454880 RD_PRE = 0x0
6235 18:14:07.454960 WR_PRE = 0x1
6236 18:14:07.458653 WR_PST = 0x0
6237 18:14:07.458733 DBI_WR = 0x0
6238 18:14:07.461456 DBI_RD = 0x0
6239 18:14:07.464872 OTF = 0x1
6240 18:14:07.468159 ===================================
6241 18:14:07.471008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 18:14:07.476297 nWR fixed to 30
6243 18:14:07.479847 [ModeRegInit_LP4] CH0 RK0
6244 18:14:07.479969 [ModeRegInit_LP4] CH0 RK1
6245 18:14:07.482851 [ModeRegInit_LP4] CH1 RK0
6246 18:14:07.486517 [ModeRegInit_LP4] CH1 RK1
6247 18:14:07.486596 match AC timing 19
6248 18:14:07.493208 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 18:14:07.496615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 18:14:07.500092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 18:14:07.506385 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 18:14:07.509812 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 18:14:07.509896 ==
6254 18:14:07.513599 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 18:14:07.516394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 18:14:07.516476 ==
6257 18:14:07.523083 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 18:14:07.529821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 18:14:07.532760 [CA 0] Center 36 (8~64) winsize 57
6260 18:14:07.536516 [CA 1] Center 36 (8~64) winsize 57
6261 18:14:07.539530 [CA 2] Center 36 (8~64) winsize 57
6262 18:14:07.539611 [CA 3] Center 36 (8~64) winsize 57
6263 18:14:07.543135 [CA 4] Center 36 (8~64) winsize 57
6264 18:14:07.546636 [CA 5] Center 36 (8~64) winsize 57
6265 18:14:07.546716
6266 18:14:07.552883 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 18:14:07.552964
6268 18:14:07.556275 [CATrainingPosCal] consider 1 rank data
6269 18:14:07.559626 u2DelayCellTimex100 = 270/100 ps
6270 18:14:07.562893 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 18:14:07.565955 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 18:14:07.569898 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 18:14:07.572679 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 18:14:07.576155 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 18:14:07.579530 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 18:14:07.579611
6277 18:14:07.582145 CA PerBit enable=1, Macro0, CA PI delay=36
6278 18:14:07.582226
6279 18:14:07.585830 [CBTSetCACLKResult] CA Dly = 36
6280 18:14:07.588749 CS Dly: 1 (0~32)
6281 18:14:07.588830 ==
6282 18:14:07.592491 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 18:14:07.595605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 18:14:07.595687 ==
6285 18:14:07.602233 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 18:14:07.608758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 18:14:07.608840 [CA 0] Center 36 (8~64) winsize 57
6288 18:14:07.612330 [CA 1] Center 36 (8~64) winsize 57
6289 18:14:07.615056 [CA 2] Center 36 (8~64) winsize 57
6290 18:14:07.618650 [CA 3] Center 36 (8~64) winsize 57
6291 18:14:07.622016 [CA 4] Center 36 (8~64) winsize 57
6292 18:14:07.625098 [CA 5] Center 36 (8~64) winsize 57
6293 18:14:07.625213
6294 18:14:07.628576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 18:14:07.628656
6296 18:14:07.635202 [CATrainingPosCal] consider 2 rank data
6297 18:14:07.635283 u2DelayCellTimex100 = 270/100 ps
6298 18:14:07.641892 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 18:14:07.644812 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 18:14:07.648574 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 18:14:07.651539 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 18:14:07.655232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 18:14:07.658156 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 18:14:07.658246
6305 18:14:07.661862 CA PerBit enable=1, Macro0, CA PI delay=36
6306 18:14:07.661978
6307 18:14:07.664738 [CBTSetCACLKResult] CA Dly = 36
6308 18:14:07.668309 CS Dly: 1 (0~32)
6309 18:14:07.668434
6310 18:14:07.671084 ----->DramcWriteLeveling(PI) begin...
6311 18:14:07.671170 ==
6312 18:14:07.674588 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 18:14:07.677993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 18:14:07.678075 ==
6315 18:14:07.681347 Write leveling (Byte 0): 40 => 8
6316 18:14:07.684510 Write leveling (Byte 1): 40 => 8
6317 18:14:07.688091 DramcWriteLeveling(PI) end<-----
6318 18:14:07.688170
6319 18:14:07.688233 ==
6320 18:14:07.691316 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 18:14:07.694341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 18:14:07.694465 ==
6323 18:14:07.698157 [Gating] SW mode calibration
6324 18:14:07.704667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 18:14:07.711193 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 18:14:07.714212 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 18:14:07.717903 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 18:14:07.724830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 18:14:07.727557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 18:14:07.731320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 18:14:07.737273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 18:14:07.741317 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 18:14:07.744546 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 18:14:07.750784 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 18:14:07.754449 Total UI for P1: 0, mck2ui 16
6336 18:14:07.757339 best dqsien dly found for B0: ( 0, 14, 24)
6337 18:14:07.757411 Total UI for P1: 0, mck2ui 16
6338 18:14:07.764140 best dqsien dly found for B1: ( 0, 14, 24)
6339 18:14:07.767060 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 18:14:07.770801 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 18:14:07.770896
6342 18:14:07.773787 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 18:14:07.777509 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 18:14:07.780442 [Gating] SW calibration Done
6345 18:14:07.780544 ==
6346 18:14:07.784020 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 18:14:07.786875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 18:14:07.786952 ==
6349 18:14:07.790248 RX Vref Scan: 0
6350 18:14:07.790349
6351 18:14:07.790441 RX Vref 0 -> 0, step: 1
6352 18:14:07.793735
6353 18:14:07.793817 RX Delay -410 -> 252, step: 16
6354 18:14:07.800069 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6355 18:14:07.803417 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6356 18:14:07.807329 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6357 18:14:07.810046 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6358 18:14:07.816904 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6359 18:14:07.820496 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6360 18:14:07.823474 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6361 18:14:07.827166 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6362 18:14:07.833166 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6363 18:14:07.836950 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6364 18:14:07.839944 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6365 18:14:07.843756 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6366 18:14:07.850155 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6367 18:14:07.853149 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6368 18:14:07.857077 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6369 18:14:07.863566 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6370 18:14:07.863687 ==
6371 18:14:07.866494 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 18:14:07.870027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 18:14:07.870136 ==
6374 18:14:07.870231 DQS Delay:
6375 18:14:07.873712 DQS0 = 27, DQS1 = 35
6376 18:14:07.873823 DQM Delay:
6377 18:14:07.876692 DQM0 = 9, DQM1 = 11
6378 18:14:07.876812 DQ Delay:
6379 18:14:07.880331 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6380 18:14:07.883435 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6381 18:14:07.886387 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6382 18:14:07.890014 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6383 18:14:07.890114
6384 18:14:07.890205
6385 18:14:07.890296 ==
6386 18:14:07.893045 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 18:14:07.896591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 18:14:07.896674 ==
6389 18:14:07.896768
6390 18:14:07.896858
6391 18:14:07.900138 TX Vref Scan disable
6392 18:14:07.900235 == TX Byte 0 ==
6393 18:14:07.906937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 18:14:07.909565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 18:14:07.909664 == TX Byte 1 ==
6396 18:14:07.916645 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 18:14:07.920109 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 18:14:07.920218 ==
6399 18:14:07.922968 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 18:14:07.926245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 18:14:07.926352 ==
6402 18:14:07.926447
6403 18:14:07.926537
6404 18:14:07.929724 TX Vref Scan disable
6405 18:14:07.929825 == TX Byte 0 ==
6406 18:14:07.936287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 18:14:07.939417 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 18:14:07.939500 == TX Byte 1 ==
6409 18:14:07.946084 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 18:14:07.949765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 18:14:07.949867
6412 18:14:07.949958 [DATLAT]
6413 18:14:07.952703 Freq=400, CH0 RK0
6414 18:14:07.952777
6415 18:14:07.952843 DATLAT Default: 0xf
6416 18:14:07.956355 0, 0xFFFF, sum = 0
6417 18:14:07.956425 1, 0xFFFF, sum = 0
6418 18:14:07.959289 2, 0xFFFF, sum = 0
6419 18:14:07.959384 3, 0xFFFF, sum = 0
6420 18:14:07.962917 4, 0xFFFF, sum = 0
6421 18:14:07.963021 5, 0xFFFF, sum = 0
6422 18:14:07.966637 6, 0xFFFF, sum = 0
6423 18:14:07.969238 7, 0xFFFF, sum = 0
6424 18:14:07.969343 8, 0xFFFF, sum = 0
6425 18:14:07.972897 9, 0xFFFF, sum = 0
6426 18:14:07.972973 10, 0xFFFF, sum = 0
6427 18:14:07.976201 11, 0xFFFF, sum = 0
6428 18:14:07.976301 12, 0xFFFF, sum = 0
6429 18:14:07.979414 13, 0x0, sum = 1
6430 18:14:07.979513 14, 0x0, sum = 2
6431 18:14:07.983043 15, 0x0, sum = 3
6432 18:14:07.983123 16, 0x0, sum = 4
6433 18:14:07.983187 best_step = 14
6434 18:14:07.985765
6435 18:14:07.985838 ==
6436 18:14:07.989238 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 18:14:07.992951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 18:14:07.993025 ==
6439 18:14:07.993091 RX Vref Scan: 1
6440 18:14:07.993181
6441 18:14:07.995840 RX Vref 0 -> 0, step: 1
6442 18:14:07.995920
6443 18:14:07.999588 RX Delay -311 -> 252, step: 8
6444 18:14:07.999659
6445 18:14:08.002583 Set Vref, RX VrefLevel [Byte0]: 57
6446 18:14:08.005523 [Byte1]: 45
6447 18:14:08.009919
6448 18:14:08.009989 Final RX Vref Byte 0 = 57 to rank0
6449 18:14:08.012769 Final RX Vref Byte 1 = 45 to rank0
6450 18:14:08.016175 Final RX Vref Byte 0 = 57 to rank1
6451 18:14:08.019548 Final RX Vref Byte 1 = 45 to rank1==
6452 18:14:08.022977 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 18:14:08.029714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 18:14:08.029820 ==
6455 18:14:08.029913 DQS Delay:
6456 18:14:08.033074 DQS0 = 28, DQS1 = 36
6457 18:14:08.033168 DQM Delay:
6458 18:14:08.033259 DQM0 = 10, DQM1 = 13
6459 18:14:08.036652 DQ Delay:
6460 18:14:08.039992 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6461 18:14:08.040145 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6462 18:14:08.042623 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6463 18:14:08.046024 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6464 18:14:08.046153
6465 18:14:08.046292
6466 18:14:08.056305 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6467 18:14:08.059328 CH0 RK0: MR19=C0C, MR18=CCB9
6468 18:14:08.066102 CH0_RK0: MR19=0xC0C, MR18=0xCCB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6469 18:14:08.066205 ==
6470 18:14:08.069767 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 18:14:08.072928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 18:14:08.073011 ==
6473 18:14:08.076374 [Gating] SW mode calibration
6474 18:14:08.082844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 18:14:08.086469 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 18:14:08.092789 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 18:14:08.096263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 18:14:08.099404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 18:14:08.105925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 18:14:08.109694 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 18:14:08.112587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 18:14:08.119155 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 18:14:08.122809 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 18:14:08.125706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 18:14:08.129222 Total UI for P1: 0, mck2ui 16
6486 18:14:08.132529 best dqsien dly found for B0: ( 0, 14, 24)
6487 18:14:08.136082 Total UI for P1: 0, mck2ui 16
6488 18:14:08.138791 best dqsien dly found for B1: ( 0, 14, 24)
6489 18:14:08.142212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 18:14:08.149121 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 18:14:08.149205
6492 18:14:08.151931 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 18:14:08.155414 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 18:14:08.158697 [Gating] SW calibration Done
6495 18:14:08.158777 ==
6496 18:14:08.162287 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 18:14:08.165298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 18:14:08.165398 ==
6499 18:14:08.169144 RX Vref Scan: 0
6500 18:14:08.169284
6501 18:14:08.169374 RX Vref 0 -> 0, step: 1
6502 18:14:08.169460
6503 18:14:08.172013 RX Delay -410 -> 252, step: 16
6504 18:14:08.175792 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6505 18:14:08.182374 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6506 18:14:08.185294 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6507 18:14:08.189048 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6508 18:14:08.191922 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6509 18:14:08.198527 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6510 18:14:08.201950 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6511 18:14:08.205582 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6512 18:14:08.208347 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6513 18:14:08.215157 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6514 18:14:08.218816 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6515 18:14:08.221843 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6516 18:14:08.224799 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6517 18:14:08.231506 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6518 18:14:08.235109 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6519 18:14:08.238862 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6520 18:14:08.238964 ==
6521 18:14:08.241641 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 18:14:08.248762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 18:14:08.248843 ==
6524 18:14:08.248907 DQS Delay:
6525 18:14:08.251626 DQS0 = 27, DQS1 = 35
6526 18:14:08.251700 DQM Delay:
6527 18:14:08.251761 DQM0 = 12, DQM1 = 13
6528 18:14:08.255085 DQ Delay:
6529 18:14:08.258133 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6530 18:14:08.258237 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6531 18:14:08.261886 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6532 18:14:08.264766 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6533 18:14:08.264841
6534 18:14:08.268166
6535 18:14:08.268265 ==
6536 18:14:08.271631 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 18:14:08.275026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 18:14:08.275128 ==
6539 18:14:08.275219
6540 18:14:08.275307
6541 18:14:08.277960 TX Vref Scan disable
6542 18:14:08.278033 == TX Byte 0 ==
6543 18:14:08.281740 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6544 18:14:08.288194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6545 18:14:08.288303 == TX Byte 1 ==
6546 18:14:08.291772 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6547 18:14:08.298293 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6548 18:14:08.298376 ==
6549 18:14:08.301241 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 18:14:08.304651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 18:14:08.304755 ==
6552 18:14:08.304846
6553 18:14:08.304934
6554 18:14:08.308226 TX Vref Scan disable
6555 18:14:08.308332 == TX Byte 0 ==
6556 18:14:08.311123 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6557 18:14:08.318273 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6558 18:14:08.318358 == TX Byte 1 ==
6559 18:14:08.321281 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6560 18:14:08.328165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6561 18:14:08.328270
6562 18:14:08.328404 [DATLAT]
6563 18:14:08.328497 Freq=400, CH0 RK1
6564 18:14:08.328585
6565 18:14:08.331156 DATLAT Default: 0xe
6566 18:14:08.334972 0, 0xFFFF, sum = 0
6567 18:14:08.335090 1, 0xFFFF, sum = 0
6568 18:14:08.338027 2, 0xFFFF, sum = 0
6569 18:14:08.338112 3, 0xFFFF, sum = 0
6570 18:14:08.341100 4, 0xFFFF, sum = 0
6571 18:14:08.341183 5, 0xFFFF, sum = 0
6572 18:14:08.344927 6, 0xFFFF, sum = 0
6573 18:14:08.345009 7, 0xFFFF, sum = 0
6574 18:14:08.347747 8, 0xFFFF, sum = 0
6575 18:14:08.347829 9, 0xFFFF, sum = 0
6576 18:14:08.351326 10, 0xFFFF, sum = 0
6577 18:14:08.351408 11, 0xFFFF, sum = 0
6578 18:14:08.354748 12, 0xFFFF, sum = 0
6579 18:14:08.354830 13, 0x0, sum = 1
6580 18:14:08.357632 14, 0x0, sum = 2
6581 18:14:08.357714 15, 0x0, sum = 3
6582 18:14:08.361150 16, 0x0, sum = 4
6583 18:14:08.361232 best_step = 14
6584 18:14:08.361295
6585 18:14:08.361354 ==
6586 18:14:08.364795 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 18:14:08.367833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 18:14:08.371574 ==
6589 18:14:08.371655 RX Vref Scan: 0
6590 18:14:08.371718
6591 18:14:08.374616 RX Vref 0 -> 0, step: 1
6592 18:14:08.374696
6593 18:14:08.378128 RX Delay -311 -> 252, step: 8
6594 18:14:08.381769 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6595 18:14:08.387901 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6596 18:14:08.391384 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6597 18:14:08.394247 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6598 18:14:08.397988 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6599 18:14:08.404679 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6600 18:14:08.407581 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6601 18:14:08.410917 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6602 18:14:08.414400 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6603 18:14:08.420873 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6604 18:14:08.424509 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6605 18:14:08.427592 iDelay=217, Bit 11, Center -32 (-247 ~ 184) 432
6606 18:14:08.431278 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6607 18:14:08.438137 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6608 18:14:08.440959 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6609 18:14:08.444649 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6610 18:14:08.444730 ==
6611 18:14:08.447693 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 18:14:08.454540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 18:14:08.454623 ==
6614 18:14:08.454687 DQS Delay:
6615 18:14:08.457340 DQS0 = 24, DQS1 = 40
6616 18:14:08.457436 DQM Delay:
6617 18:14:08.457514 DQM0 = 8, DQM1 = 14
6618 18:14:08.460893 DQ Delay:
6619 18:14:08.464453 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6620 18:14:08.464534 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6621 18:14:08.467160 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6622 18:14:08.470599 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6623 18:14:08.470680
6624 18:14:08.474229
6625 18:14:08.480926 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6626 18:14:08.483936 CH0 RK1: MR19=C0C, MR18=B959
6627 18:14:08.490584 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6628 18:14:08.493989 [RxdqsGatingPostProcess] freq 400
6629 18:14:08.497675 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 18:14:08.501107 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 18:14:08.504401 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 18:14:08.507680 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 18:14:08.510405 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 18:14:08.514188 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 18:14:08.517031 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 18:14:08.520759 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 18:14:08.523709 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 18:14:08.527314 Pre-setting of DQS Precalculation
6639 18:14:08.530759 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 18:14:08.530840 ==
6641 18:14:08.533654 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 18:14:08.537204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 18:14:08.540851 ==
6644 18:14:08.543776 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 18:14:08.550535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6646 18:14:08.554093 [CA 0] Center 36 (8~64) winsize 57
6647 18:14:08.556990 [CA 1] Center 36 (8~64) winsize 57
6648 18:14:08.560664 [CA 2] Center 36 (8~64) winsize 57
6649 18:14:08.563618 [CA 3] Center 36 (8~64) winsize 57
6650 18:14:08.567342 [CA 4] Center 36 (8~64) winsize 57
6651 18:14:08.570290 [CA 5] Center 36 (8~64) winsize 57
6652 18:14:08.570372
6653 18:14:08.573930 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6654 18:14:08.574012
6655 18:14:08.577303 [CATrainingPosCal] consider 1 rank data
6656 18:14:08.580093 u2DelayCellTimex100 = 270/100 ps
6657 18:14:08.583763 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 18:14:08.586783 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 18:14:08.590448 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 18:14:08.593341 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 18:14:08.596998 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 18:14:08.599789 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 18:14:08.599871
6664 18:14:08.606610 CA PerBit enable=1, Macro0, CA PI delay=36
6665 18:14:08.606692
6666 18:14:08.610191 [CBTSetCACLKResult] CA Dly = 36
6667 18:14:08.610273 CS Dly: 1 (0~32)
6668 18:14:08.610337 ==
6669 18:14:08.613072 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 18:14:08.616549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 18:14:08.616631 ==
6672 18:14:08.623248 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 18:14:08.630018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 18:14:08.633469 [CA 0] Center 36 (8~64) winsize 57
6675 18:14:08.636266 [CA 1] Center 36 (8~64) winsize 57
6676 18:14:08.639798 [CA 2] Center 36 (8~64) winsize 57
6677 18:14:08.643210 [CA 3] Center 36 (8~64) winsize 57
6678 18:14:08.646674 [CA 4] Center 36 (8~64) winsize 57
6679 18:14:08.646790 [CA 5] Center 36 (8~64) winsize 57
6680 18:14:08.646878
6681 18:14:08.653202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 18:14:08.653285
6683 18:14:08.656938 [CATrainingPosCal] consider 2 rank data
6684 18:14:08.659943 u2DelayCellTimex100 = 270/100 ps
6685 18:14:08.663593 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 18:14:08.666649 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 18:14:08.669408 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 18:14:08.673147 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 18:14:08.676063 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 18:14:08.680021 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 18:14:08.680102
6692 18:14:08.682823 CA PerBit enable=1, Macro0, CA PI delay=36
6693 18:14:08.682904
6694 18:14:08.686114 [CBTSetCACLKResult] CA Dly = 36
6695 18:14:08.689526 CS Dly: 1 (0~32)
6696 18:14:08.689608
6697 18:14:08.692607 ----->DramcWriteLeveling(PI) begin...
6698 18:14:08.692689 ==
6699 18:14:08.696257 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 18:14:08.699384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 18:14:08.699514 ==
6702 18:14:08.703205 Write leveling (Byte 0): 40 => 8
6703 18:14:08.706062 Write leveling (Byte 1): 40 => 8
6704 18:14:08.709773 DramcWriteLeveling(PI) end<-----
6705 18:14:08.709856
6706 18:14:08.709942 ==
6707 18:14:08.712790 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 18:14:08.716445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 18:14:08.716531 ==
6710 18:14:08.719897 [Gating] SW mode calibration
6711 18:14:08.726390 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 18:14:08.732844 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 18:14:08.736290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 18:14:08.739141 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 18:14:08.746424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 18:14:08.749347 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 18:14:08.752994 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 18:14:08.759115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 18:14:08.762667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 18:14:08.766293 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 18:14:08.772875 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 18:14:08.772960 Total UI for P1: 0, mck2ui 16
6723 18:14:08.779525 best dqsien dly found for B0: ( 0, 14, 24)
6724 18:14:08.779640 Total UI for P1: 0, mck2ui 16
6725 18:14:08.786210 best dqsien dly found for B1: ( 0, 14, 24)
6726 18:14:08.789270 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 18:14:08.792748 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 18:14:08.792832
6729 18:14:08.796164 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 18:14:08.798890 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 18:14:08.802319 [Gating] SW calibration Done
6732 18:14:08.802403 ==
6733 18:14:08.806032 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 18:14:08.809554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 18:14:08.809639 ==
6736 18:14:08.812376 RX Vref Scan: 0
6737 18:14:08.812498
6738 18:14:08.812565 RX Vref 0 -> 0, step: 1
6739 18:14:08.812625
6740 18:14:08.816043 RX Delay -410 -> 252, step: 16
6741 18:14:08.822887 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6742 18:14:08.825825 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6743 18:14:08.828828 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6744 18:14:08.832638 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6745 18:14:08.838921 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6746 18:14:08.842033 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6747 18:14:08.845741 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6748 18:14:08.848637 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6749 18:14:08.855417 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6750 18:14:08.858586 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6751 18:14:08.862268 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6752 18:14:08.865887 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6753 18:14:08.872432 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6754 18:14:08.875270 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6755 18:14:08.879076 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6756 18:14:08.885165 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6757 18:14:08.885253 ==
6758 18:14:08.888934 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 18:14:08.892017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 18:14:08.892133 ==
6761 18:14:08.892235 DQS Delay:
6762 18:14:08.895081 DQS0 = 35, DQS1 = 35
6763 18:14:08.895163 DQM Delay:
6764 18:14:08.898994 DQM0 = 18, DQM1 = 12
6765 18:14:08.899075 DQ Delay:
6766 18:14:08.902367 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6767 18:14:08.905115 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6768 18:14:08.908786 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6769 18:14:08.911589 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6770 18:14:08.911701
6771 18:14:08.911803
6772 18:14:08.911915 ==
6773 18:14:08.914931 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 18:14:08.918401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 18:14:08.918488 ==
6776 18:14:08.918573
6777 18:14:08.918653
6778 18:14:08.921629 TX Vref Scan disable
6779 18:14:08.921715 == TX Byte 0 ==
6780 18:14:08.928567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 18:14:08.932120 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 18:14:08.932236 == TX Byte 1 ==
6783 18:14:08.938805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 18:14:08.941809 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 18:14:08.941895 ==
6786 18:14:08.945340 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 18:14:08.948082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 18:14:08.948192 ==
6789 18:14:08.948293
6790 18:14:08.948419
6791 18:14:08.951686 TX Vref Scan disable
6792 18:14:08.955177 == TX Byte 0 ==
6793 18:14:08.958677 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 18:14:08.961529 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 18:14:08.965146 == TX Byte 1 ==
6796 18:14:08.968067 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 18:14:08.971795 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 18:14:08.971880
6799 18:14:08.971966 [DATLAT]
6800 18:14:08.974616 Freq=400, CH1 RK0
6801 18:14:08.974725
6802 18:14:08.974826 DATLAT Default: 0xf
6803 18:14:08.978242 0, 0xFFFF, sum = 0
6804 18:14:08.978352 1, 0xFFFF, sum = 0
6805 18:14:08.981342 2, 0xFFFF, sum = 0
6806 18:14:08.985193 3, 0xFFFF, sum = 0
6807 18:14:08.985275 4, 0xFFFF, sum = 0
6808 18:14:08.987987 5, 0xFFFF, sum = 0
6809 18:14:08.988069 6, 0xFFFF, sum = 0
6810 18:14:08.991644 7, 0xFFFF, sum = 0
6811 18:14:08.991754 8, 0xFFFF, sum = 0
6812 18:14:08.994639 9, 0xFFFF, sum = 0
6813 18:14:08.994721 10, 0xFFFF, sum = 0
6814 18:14:08.998273 11, 0xFFFF, sum = 0
6815 18:14:08.998356 12, 0xFFFF, sum = 0
6816 18:14:09.001170 13, 0x0, sum = 1
6817 18:14:09.001257 14, 0x0, sum = 2
6818 18:14:09.004959 15, 0x0, sum = 3
6819 18:14:09.005056 16, 0x0, sum = 4
6820 18:14:09.007947 best_step = 14
6821 18:14:09.008045
6822 18:14:09.008136 ==
6823 18:14:09.011419 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 18:14:09.014994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 18:14:09.015068 ==
6826 18:14:09.015156 RX Vref Scan: 1
6827 18:14:09.015244
6828 18:14:09.017848 RX Vref 0 -> 0, step: 1
6829 18:14:09.017917
6830 18:14:09.021639 RX Delay -311 -> 252, step: 8
6831 18:14:09.021715
6832 18:14:09.024522 Set Vref, RX VrefLevel [Byte0]: 53
6833 18:14:09.028245 [Byte1]: 53
6834 18:14:09.031657
6835 18:14:09.031725 Final RX Vref Byte 0 = 53 to rank0
6836 18:14:09.035020 Final RX Vref Byte 1 = 53 to rank0
6837 18:14:09.038435 Final RX Vref Byte 0 = 53 to rank1
6838 18:14:09.041710 Final RX Vref Byte 1 = 53 to rank1==
6839 18:14:09.045227 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 18:14:09.051788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 18:14:09.051859 ==
6842 18:14:09.051920 DQS Delay:
6843 18:14:09.055382 DQS0 = 32, DQS1 = 32
6844 18:14:09.055488 DQM Delay:
6845 18:14:09.055550 DQM0 = 13, DQM1 = 10
6846 18:14:09.058332 DQ Delay:
6847 18:14:09.062153 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6848 18:14:09.065070 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6849 18:14:09.065163 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6850 18:14:09.068650 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6851 18:14:09.071956
6852 18:14:09.072054
6853 18:14:09.078325 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6854 18:14:09.082078 CH1 RK0: MR19=C0C, MR18=8FC7
6855 18:14:09.088503 CH1_RK0: MR19=0xC0C, MR18=0x8FC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6856 18:14:09.088678 ==
6857 18:14:09.091394 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 18:14:09.095123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 18:14:09.095329 ==
6860 18:14:09.098166 [Gating] SW mode calibration
6861 18:14:09.104707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 18:14:09.111373 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 18:14:09.115179 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 18:14:09.118794 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 18:14:09.125271 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 18:14:09.128102 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 18:14:09.131732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 18:14:09.138406 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 18:14:09.142198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 18:14:09.145094 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 18:14:09.148561 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 18:14:09.151882 Total UI for P1: 0, mck2ui 16
6873 18:14:09.155217 best dqsien dly found for B0: ( 0, 14, 24)
6874 18:14:09.158099 Total UI for P1: 0, mck2ui 16
6875 18:14:09.161923 best dqsien dly found for B1: ( 0, 14, 24)
6876 18:14:09.165405 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 18:14:09.171462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 18:14:09.171901
6879 18:14:09.175098 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 18:14:09.178104 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 18:14:09.181607 [Gating] SW calibration Done
6882 18:14:09.182041 ==
6883 18:14:09.185169 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 18:14:09.188681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 18:14:09.189118 ==
6886 18:14:09.191458 RX Vref Scan: 0
6887 18:14:09.191889
6888 18:14:09.192326 RX Vref 0 -> 0, step: 1
6889 18:14:09.192788
6890 18:14:09.194673 RX Delay -410 -> 252, step: 16
6891 18:14:09.198234 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6892 18:14:09.204953 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6893 18:14:09.207954 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6894 18:14:09.211640 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6895 18:14:09.214740 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6896 18:14:09.221363 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6897 18:14:09.224877 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6898 18:14:09.227972 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6899 18:14:09.231623 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6900 18:14:09.238054 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6901 18:14:09.241008 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6902 18:14:09.244577 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6903 18:14:09.248214 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6904 18:14:09.254551 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6905 18:14:09.257564 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6906 18:14:09.261142 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6907 18:14:09.261786 ==
6908 18:14:09.264708 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 18:14:09.271251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 18:14:09.271843 ==
6911 18:14:09.272334 DQS Delay:
6912 18:14:09.274759 DQS0 = 35, DQS1 = 35
6913 18:14:09.275180 DQM Delay:
6914 18:14:09.275549 DQM0 = 18, DQM1 = 15
6915 18:14:09.277691 DQ Delay:
6916 18:14:09.280881 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6917 18:14:09.284283 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6918 18:14:09.284571 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6919 18:14:09.290381 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6920 18:14:09.290575
6921 18:14:09.290743
6922 18:14:09.290910 ==
6923 18:14:09.294047 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 18:14:09.297631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 18:14:09.297801 ==
6926 18:14:09.297946
6927 18:14:09.298076
6928 18:14:09.301197 TX Vref Scan disable
6929 18:14:09.301324 == TX Byte 0 ==
6930 18:14:09.303930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6931 18:14:09.310502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6932 18:14:09.310665 == TX Byte 1 ==
6933 18:14:09.314068 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6934 18:14:09.320723 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6935 18:14:09.320844 ==
6936 18:14:09.323821 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 18:14:09.327712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 18:14:09.327826 ==
6939 18:14:09.327922
6940 18:14:09.328012
6941 18:14:09.330533 TX Vref Scan disable
6942 18:14:09.330687 == TX Byte 0 ==
6943 18:14:09.334174 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6944 18:14:09.340826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6945 18:14:09.341014 == TX Byte 1 ==
6946 18:14:09.343791 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6947 18:14:09.350573 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6948 18:14:09.350848
6949 18:14:09.351063 [DATLAT]
6950 18:14:09.351268 Freq=400, CH1 RK1
6951 18:14:09.354333
6952 18:14:09.354664 DATLAT Default: 0xe
6953 18:14:09.357302 0, 0xFFFF, sum = 0
6954 18:14:09.357663 1, 0xFFFF, sum = 0
6955 18:14:09.361104 2, 0xFFFF, sum = 0
6956 18:14:09.361656 3, 0xFFFF, sum = 0
6957 18:14:09.364240 4, 0xFFFF, sum = 0
6958 18:14:09.364692 5, 0xFFFF, sum = 0
6959 18:14:09.367633 6, 0xFFFF, sum = 0
6960 18:14:09.368181 7, 0xFFFF, sum = 0
6961 18:14:09.370493 8, 0xFFFF, sum = 0
6962 18:14:09.370919 9, 0xFFFF, sum = 0
6963 18:14:09.374115 10, 0xFFFF, sum = 0
6964 18:14:09.374534 11, 0xFFFF, sum = 0
6965 18:14:09.376887 12, 0xFFFF, sum = 0
6966 18:14:09.377335 13, 0x0, sum = 1
6967 18:14:09.380597 14, 0x0, sum = 2
6968 18:14:09.381037 15, 0x0, sum = 3
6969 18:14:09.383853 16, 0x0, sum = 4
6970 18:14:09.384277 best_step = 14
6971 18:14:09.384679
6972 18:14:09.384996 ==
6973 18:14:09.387254 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 18:14:09.394193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 18:14:09.394629 ==
6976 18:14:09.394967 RX Vref Scan: 0
6977 18:14:09.395278
6978 18:14:09.397842 RX Vref 0 -> 0, step: 1
6979 18:14:09.398259
6980 18:14:09.400675 RX Delay -311 -> 252, step: 8
6981 18:14:09.407234 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6982 18:14:09.410649 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6983 18:14:09.413932 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6984 18:14:09.417299 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6985 18:14:09.424191 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6986 18:14:09.428079 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6987 18:14:09.430401 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6988 18:14:09.434199 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6989 18:14:09.440784 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6990 18:14:09.443679 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6991 18:14:09.446929 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6992 18:14:09.450456 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6993 18:14:09.457015 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6994 18:14:09.459972 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6995 18:14:09.463773 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6996 18:14:09.466635 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6997 18:14:09.470484 ==
6998 18:14:09.470932 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 18:14:09.476839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 18:14:09.477353 ==
7001 18:14:09.477690 DQS Delay:
7002 18:14:09.479772 DQS0 = 28, DQS1 = 36
7003 18:14:09.480184 DQM Delay:
7004 18:14:09.483430 DQM0 = 10, DQM1 = 14
7005 18:14:09.483919 DQ Delay:
7006 18:14:09.486764 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7007 18:14:09.489702 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7008 18:14:09.493442 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7009 18:14:09.496643 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7010 18:14:09.497064
7011 18:14:09.497427
7012 18:14:09.502933 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf4f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7013 18:14:09.506349 CH1 RK1: MR19=C0C, MR18=BF4F
7014 18:14:09.513269 CH1_RK1: MR19=0xC0C, MR18=0xBF4F, DQSOSC=386, MR23=63, INC=396, DEC=264
7015 18:14:09.517085 [RxdqsGatingPostProcess] freq 400
7016 18:14:09.519747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 18:14:09.523331 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 18:14:09.526522 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 18:14:09.530048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 18:14:09.533482 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 18:14:09.536941 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 18:14:09.539788 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 18:14:09.543557 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 18:14:09.546507 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 18:14:09.550217 Pre-setting of DQS Precalculation
7026 18:14:09.553334 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 18:14:09.562988 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 18:14:09.569902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 18:14:09.570338
7030 18:14:09.570774
7031 18:14:09.572777 [Calibration Summary] 800 Mbps
7032 18:14:09.573224 CH 0, Rank 0
7033 18:14:09.576605 SW Impedance : PASS
7034 18:14:09.577054 DUTY Scan : NO K
7035 18:14:09.579617 ZQ Calibration : PASS
7036 18:14:09.583047 Jitter Meter : NO K
7037 18:14:09.583522 CBT Training : PASS
7038 18:14:09.585972 Write leveling : PASS
7039 18:14:09.589757 RX DQS gating : PASS
7040 18:14:09.590178 RX DQ/DQS(RDDQC) : PASS
7041 18:14:09.593143 TX DQ/DQS : PASS
7042 18:14:09.596229 RX DATLAT : PASS
7043 18:14:09.596701 RX DQ/DQS(Engine): PASS
7044 18:14:09.599982 TX OE : NO K
7045 18:14:09.600439 All Pass.
7046 18:14:09.600772
7047 18:14:09.601074 CH 0, Rank 1
7048 18:14:09.603089 SW Impedance : PASS
7049 18:14:09.605963 DUTY Scan : NO K
7050 18:14:09.606418 ZQ Calibration : PASS
7051 18:14:09.609702 Jitter Meter : NO K
7052 18:14:09.612866 CBT Training : PASS
7053 18:14:09.613290 Write leveling : NO K
7054 18:14:09.616460 RX DQS gating : PASS
7055 18:14:09.619631 RX DQ/DQS(RDDQC) : PASS
7056 18:14:09.620234 TX DQ/DQS : PASS
7057 18:14:09.623143 RX DATLAT : PASS
7058 18:14:09.626077 RX DQ/DQS(Engine): PASS
7059 18:14:09.626493 TX OE : NO K
7060 18:14:09.629682 All Pass.
7061 18:14:09.630097
7062 18:14:09.630423 CH 1, Rank 0
7063 18:14:09.632770 SW Impedance : PASS
7064 18:14:09.633185 DUTY Scan : NO K
7065 18:14:09.636091 ZQ Calibration : PASS
7066 18:14:09.639538 Jitter Meter : NO K
7067 18:14:09.640071 CBT Training : PASS
7068 18:14:09.642320 Write leveling : PASS
7069 18:14:09.645781 RX DQS gating : PASS
7070 18:14:09.646364 RX DQ/DQS(RDDQC) : PASS
7071 18:14:09.649459 TX DQ/DQS : PASS
7072 18:14:09.649921 RX DATLAT : PASS
7073 18:14:09.652425 RX DQ/DQS(Engine): PASS
7074 18:14:09.656123 TX OE : NO K
7075 18:14:09.656682 All Pass.
7076 18:14:09.657026
7077 18:14:09.657578 CH 1, Rank 1
7078 18:14:09.659163 SW Impedance : PASS
7079 18:14:09.662355 DUTY Scan : NO K
7080 18:14:09.662921 ZQ Calibration : PASS
7081 18:14:09.665985 Jitter Meter : NO K
7082 18:14:09.668898 CBT Training : PASS
7083 18:14:09.669313 Write leveling : NO K
7084 18:14:09.672598 RX DQS gating : PASS
7085 18:14:09.675701 RX DQ/DQS(RDDQC) : PASS
7086 18:14:09.676114 TX DQ/DQS : PASS
7087 18:14:09.679601 RX DATLAT : PASS
7088 18:14:09.682532 RX DQ/DQS(Engine): PASS
7089 18:14:09.682945 TX OE : NO K
7090 18:14:09.686251 All Pass.
7091 18:14:09.686665
7092 18:14:09.686993 DramC Write-DBI off
7093 18:14:09.689392 PER_BANK_REFRESH: Hybrid Mode
7094 18:14:09.689907 TX_TRACKING: ON
7095 18:14:09.699436 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 18:14:09.702426 [FAST_K] Save calibration result to emmc
7097 18:14:09.706173 dramc_set_vcore_voltage set vcore to 725000
7098 18:14:09.709281 Read voltage for 1600, 0
7099 18:14:09.709700 Vio18 = 0
7100 18:14:09.712122 Vcore = 725000
7101 18:14:09.712610 Vdram = 0
7102 18:14:09.712949 Vddq = 0
7103 18:14:09.715833 Vmddr = 0
7104 18:14:09.719098 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 18:14:09.725447 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 18:14:09.725868 MEM_TYPE=3, freq_sel=13
7107 18:14:09.729098 sv_algorithm_assistance_LP4_3733
7108 18:14:09.735729 ============ PULL DRAM RESETB DOWN ============
7109 18:14:09.738749 ========== PULL DRAM RESETB DOWN end =========
7110 18:14:09.742261 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 18:14:09.745723 ===================================
7112 18:14:09.749435 LPDDR4 DRAM CONFIGURATION
7113 18:14:09.752385 ===================================
7114 18:14:09.752841 EX_ROW_EN[0] = 0x0
7115 18:14:09.755639 EX_ROW_EN[1] = 0x0
7116 18:14:09.759154 LP4Y_EN = 0x0
7117 18:14:09.759568 WORK_FSP = 0x1
7118 18:14:09.762425 WL = 0x5
7119 18:14:09.762837 RL = 0x5
7120 18:14:09.765815 BL = 0x2
7121 18:14:09.766227 RPST = 0x0
7122 18:14:09.769013 RD_PRE = 0x0
7123 18:14:09.769634 WR_PRE = 0x1
7124 18:14:09.771799 WR_PST = 0x1
7125 18:14:09.772211 DBI_WR = 0x0
7126 18:14:09.775400 DBI_RD = 0x0
7127 18:14:09.775851 OTF = 0x1
7128 18:14:09.779099 ===================================
7129 18:14:09.781934 ===================================
7130 18:14:09.785632 ANA top config
7131 18:14:09.788564 ===================================
7132 18:14:09.788985 DLL_ASYNC_EN = 0
7133 18:14:09.792319 ALL_SLAVE_EN = 0
7134 18:14:09.795128 NEW_RANK_MODE = 1
7135 18:14:09.798873 DLL_IDLE_MODE = 1
7136 18:14:09.802444 LP45_APHY_COMB_EN = 1
7137 18:14:09.802867 TX_ODT_DIS = 0
7138 18:14:09.805148 NEW_8X_MODE = 1
7139 18:14:09.808673 ===================================
7140 18:14:09.811648 ===================================
7141 18:14:09.815039 data_rate = 3200
7142 18:14:09.818774 CKR = 1
7143 18:14:09.821938 DQ_P2S_RATIO = 8
7144 18:14:09.824947 ===================================
7145 18:14:09.825364 CA_P2S_RATIO = 8
7146 18:14:09.828642 DQ_CA_OPEN = 0
7147 18:14:09.831741 DQ_SEMI_OPEN = 0
7148 18:14:09.835684 CA_SEMI_OPEN = 0
7149 18:14:09.838646 CA_FULL_RATE = 0
7150 18:14:09.841648 DQ_CKDIV4_EN = 0
7151 18:14:09.842076 CA_CKDIV4_EN = 0
7152 18:14:09.845170 CA_PREDIV_EN = 0
7153 18:14:09.848539 PH8_DLY = 12
7154 18:14:09.852387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 18:14:09.855293 DQ_AAMCK_DIV = 4
7156 18:14:09.858885 CA_AAMCK_DIV = 4
7157 18:14:09.859393 CA_ADMCK_DIV = 4
7158 18:14:09.861591 DQ_TRACK_CA_EN = 0
7159 18:14:09.865282 CA_PICK = 1600
7160 18:14:09.868366 CA_MCKIO = 1600
7161 18:14:09.872115 MCKIO_SEMI = 0
7162 18:14:09.875156 PLL_FREQ = 3068
7163 18:14:09.878540 DQ_UI_PI_RATIO = 32
7164 18:14:09.878956 CA_UI_PI_RATIO = 0
7165 18:14:09.882054 ===================================
7166 18:14:09.884830 ===================================
7167 18:14:09.888278 memory_type:LPDDR4
7168 18:14:09.891191 GP_NUM : 10
7169 18:14:09.894788 SRAM_EN : 1
7170 18:14:09.895218 MD32_EN : 0
7171 18:14:09.897826 ===================================
7172 18:14:09.901449 [ANA_INIT] >>>>>>>>>>>>>>
7173 18:14:09.905013 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 18:14:09.908026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 18:14:09.911642 ===================================
7176 18:14:09.914356 data_rate = 3200,PCW = 0X7600
7177 18:14:09.918030 ===================================
7178 18:14:09.921017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 18:14:09.924479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 18:14:09.931429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 18:14:09.934394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 18:14:09.937796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 18:14:09.940967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 18:14:09.944768 [ANA_INIT] flow start
7185 18:14:09.947517 [ANA_INIT] PLL >>>>>>>>
7186 18:14:09.948005 [ANA_INIT] PLL <<<<<<<<
7187 18:14:09.951444 [ANA_INIT] MIDPI >>>>>>>>
7188 18:14:09.954110 [ANA_INIT] MIDPI <<<<<<<<
7189 18:14:09.954544 [ANA_INIT] DLL >>>>>>>>
7190 18:14:09.957696 [ANA_INIT] DLL <<<<<<<<
7191 18:14:09.961029 [ANA_INIT] flow end
7192 18:14:09.964605 ============ LP4 DIFF to SE enter ============
7193 18:14:09.967776 ============ LP4 DIFF to SE exit ============
7194 18:14:09.971439 [ANA_INIT] <<<<<<<<<<<<<
7195 18:14:09.974201 [Flow] Enable top DCM control >>>>>
7196 18:14:09.977974 [Flow] Enable top DCM control <<<<<
7197 18:14:09.981073 Enable DLL master slave shuffle
7198 18:14:09.984577 ==============================================================
7199 18:14:09.987661 Gating Mode config
7200 18:14:09.994712 ==============================================================
7201 18:14:09.995132 Config description:
7202 18:14:10.004456 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 18:14:10.011110 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 18:14:10.014607 SELPH_MODE 0: By rank 1: By Phase
7205 18:14:10.021384 ==============================================================
7206 18:14:10.024120 GAT_TRACK_EN = 1
7207 18:14:10.027780 RX_GATING_MODE = 2
7208 18:14:10.031387 RX_GATING_TRACK_MODE = 2
7209 18:14:10.034409 SELPH_MODE = 1
7210 18:14:10.037390 PICG_EARLY_EN = 1
7211 18:14:10.040934 VALID_LAT_VALUE = 1
7212 18:14:10.043941 ==============================================================
7213 18:14:10.047606 Enter into Gating configuration >>>>
7214 18:14:10.050782 Exit from Gating configuration <<<<
7215 18:14:10.054408 Enter into DVFS_PRE_config >>>>>
7216 18:14:10.067721 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 18:14:10.068247 Exit from DVFS_PRE_config <<<<<
7218 18:14:10.070438 Enter into PICG configuration >>>>
7219 18:14:10.073636 Exit from PICG configuration <<<<
7220 18:14:10.077107 [RX_INPUT] configuration >>>>>
7221 18:14:10.081041 [RX_INPUT] configuration <<<<<
7222 18:14:10.087091 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 18:14:10.090528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 18:14:10.097289 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 18:14:10.103780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 18:14:10.110801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 18:14:10.116914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 18:14:10.120474 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 18:14:10.123968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 18:14:10.126662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 18:14:10.133485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 18:14:10.136950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 18:14:10.140297 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 18:14:10.143380 ===================================
7235 18:14:10.147072 LPDDR4 DRAM CONFIGURATION
7236 18:14:10.150146 ===================================
7237 18:14:10.153831 EX_ROW_EN[0] = 0x0
7238 18:14:10.154246 EX_ROW_EN[1] = 0x0
7239 18:14:10.156925 LP4Y_EN = 0x0
7240 18:14:10.157338 WORK_FSP = 0x1
7241 18:14:10.160602 WL = 0x5
7242 18:14:10.161028 RL = 0x5
7243 18:14:10.163583 BL = 0x2
7244 18:14:10.164095 RPST = 0x0
7245 18:14:10.166555 RD_PRE = 0x0
7246 18:14:10.167089 WR_PRE = 0x1
7247 18:14:10.169975 WR_PST = 0x1
7248 18:14:10.170387 DBI_WR = 0x0
7249 18:14:10.173648 DBI_RD = 0x0
7250 18:14:10.174194 OTF = 0x1
7251 18:14:10.177213 ===================================
7252 18:14:10.180019 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 18:14:10.186851 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 18:14:10.189858 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 18:14:10.193499 ===================================
7256 18:14:10.196967 LPDDR4 DRAM CONFIGURATION
7257 18:14:10.200047 ===================================
7258 18:14:10.200529 EX_ROW_EN[0] = 0x10
7259 18:14:10.203100 EX_ROW_EN[1] = 0x0
7260 18:14:10.206992 LP4Y_EN = 0x0
7261 18:14:10.207408 WORK_FSP = 0x1
7262 18:14:10.209898 WL = 0x5
7263 18:14:10.210311 RL = 0x5
7264 18:14:10.213586 BL = 0x2
7265 18:14:10.213997 RPST = 0x0
7266 18:14:10.216716 RD_PRE = 0x0
7267 18:14:10.217176 WR_PRE = 0x1
7268 18:14:10.219577 WR_PST = 0x1
7269 18:14:10.219989 DBI_WR = 0x0
7270 18:14:10.223340 DBI_RD = 0x0
7271 18:14:10.223753 OTF = 0x1
7272 18:14:10.226251 ===================================
7273 18:14:10.233432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 18:14:10.233889 ==
7275 18:14:10.236379 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 18:14:10.240069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 18:14:10.242845 ==
7278 18:14:10.243257 [Duty_Offset_Calibration]
7279 18:14:10.246898 B0:2 B1:1 CA:1
7280 18:14:10.247309
7281 18:14:10.249454 [DutyScan_Calibration_Flow] k_type=0
7282 18:14:10.258263
7283 18:14:10.258736 ==CLK 0==
7284 18:14:10.262305 Final CLK duty delay cell = 0
7285 18:14:10.265192 [0] MAX Duty = 5156%(X100), DQS PI = 22
7286 18:14:10.268979 [0] MIN Duty = 4876%(X100), DQS PI = 48
7287 18:14:10.269397 [0] AVG Duty = 5016%(X100)
7288 18:14:10.271797
7289 18:14:10.275358 CH0 CLK Duty spec in!! Max-Min= 280%
7290 18:14:10.278776 [DutyScan_Calibration_Flow] ====Done====
7291 18:14:10.279317
7292 18:14:10.281827 [DutyScan_Calibration_Flow] k_type=1
7293 18:14:10.298012
7294 18:14:10.298624 ==DQS 0 ==
7295 18:14:10.301392 Final DQS duty delay cell = -4
7296 18:14:10.304211 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7297 18:14:10.307878 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7298 18:14:10.310993 [-4] AVG Duty = 4891%(X100)
7299 18:14:10.311466
7300 18:14:10.311905 ==DQS 1 ==
7301 18:14:10.314610 Final DQS duty delay cell = 0
7302 18:14:10.317511 [0] MAX Duty = 5187%(X100), DQS PI = 20
7303 18:14:10.321159 [0] MIN Duty = 5031%(X100), DQS PI = 52
7304 18:14:10.324246 [0] AVG Duty = 5109%(X100)
7305 18:14:10.324716
7306 18:14:10.327814 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7307 18:14:10.328240
7308 18:14:10.330882 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 18:14:10.334555 [DutyScan_Calibration_Flow] ====Done====
7310 18:14:10.334983
7311 18:14:10.337525 [DutyScan_Calibration_Flow] k_type=3
7312 18:14:10.355647
7313 18:14:10.356105 ==DQM 0 ==
7314 18:14:10.358391 Final DQM duty delay cell = 0
7315 18:14:10.361655 [0] MAX Duty = 5187%(X100), DQS PI = 32
7316 18:14:10.364903 [0] MIN Duty = 4907%(X100), DQS PI = 0
7317 18:14:10.365318 [0] AVG Duty = 5047%(X100)
7318 18:14:10.368535
7319 18:14:10.368944 ==DQM 1 ==
7320 18:14:10.371560 Final DQM duty delay cell = 0
7321 18:14:10.375345 [0] MAX Duty = 5187%(X100), DQS PI = 8
7322 18:14:10.378329 [0] MIN Duty = 5031%(X100), DQS PI = 48
7323 18:14:10.381954 [0] AVG Duty = 5109%(X100)
7324 18:14:10.382362
7325 18:14:10.385347 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7326 18:14:10.385762
7327 18:14:10.388397 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7328 18:14:10.391867 [DutyScan_Calibration_Flow] ====Done====
7329 18:14:10.392382
7330 18:14:10.395309 [DutyScan_Calibration_Flow] k_type=2
7331 18:14:10.412401
7332 18:14:10.412819 ==DQ 0 ==
7333 18:14:10.415933 Final DQ duty delay cell = 0
7334 18:14:10.418739 [0] MAX Duty = 5062%(X100), DQS PI = 26
7335 18:14:10.422456 [0] MIN Duty = 4907%(X100), DQS PI = 0
7336 18:14:10.422873 [0] AVG Duty = 4984%(X100)
7337 18:14:10.423198
7338 18:14:10.425291 ==DQ 1 ==
7339 18:14:10.429028 Final DQ duty delay cell = 0
7340 18:14:10.432014 [0] MAX Duty = 5125%(X100), DQS PI = 22
7341 18:14:10.435817 [0] MIN Duty = 4907%(X100), DQS PI = 34
7342 18:14:10.436324 [0] AVG Duty = 5016%(X100)
7343 18:14:10.436711
7344 18:14:10.438668 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7345 18:14:10.442371
7346 18:14:10.445363 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7347 18:14:10.448786 [DutyScan_Calibration_Flow] ====Done====
7348 18:14:10.449383 ==
7349 18:14:10.451858 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 18:14:10.455585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 18:14:10.456220 ==
7352 18:14:10.458474 [Duty_Offset_Calibration]
7353 18:14:10.458977 B0:1 B1:0 CA:0
7354 18:14:10.459504
7355 18:14:10.462218 [DutyScan_Calibration_Flow] k_type=0
7356 18:14:10.471619
7357 18:14:10.472036 ==CLK 0==
7358 18:14:10.475238 Final CLK duty delay cell = -4
7359 18:14:10.478431 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7360 18:14:10.481382 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7361 18:14:10.485085 [-4] AVG Duty = 4922%(X100)
7362 18:14:10.485500
7363 18:14:10.488737 CH1 CLK Duty spec in!! Max-Min= 156%
7364 18:14:10.491280 [DutyScan_Calibration_Flow] ====Done====
7365 18:14:10.491693
7366 18:14:10.494736 [DutyScan_Calibration_Flow] k_type=1
7367 18:14:10.511663
7368 18:14:10.511966 ==DQS 0 ==
7369 18:14:10.514615 Final DQS duty delay cell = 0
7370 18:14:10.518277 [0] MAX Duty = 5062%(X100), DQS PI = 24
7371 18:14:10.521802 [0] MIN Duty = 4844%(X100), DQS PI = 2
7372 18:14:10.522098 [0] AVG Duty = 4953%(X100)
7373 18:14:10.524617
7374 18:14:10.524911 ==DQS 1 ==
7375 18:14:10.528114 Final DQS duty delay cell = 0
7376 18:14:10.531527 [0] MAX Duty = 5249%(X100), DQS PI = 16
7377 18:14:10.534670 [0] MIN Duty = 4938%(X100), DQS PI = 8
7378 18:14:10.534957 [0] AVG Duty = 5093%(X100)
7379 18:14:10.537968
7380 18:14:10.541709 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7381 18:14:10.541999
7382 18:14:10.544749 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7383 18:14:10.548461 [DutyScan_Calibration_Flow] ====Done====
7384 18:14:10.548808
7385 18:14:10.551398 [DutyScan_Calibration_Flow] k_type=3
7386 18:14:10.568436
7387 18:14:10.568847 ==DQM 0 ==
7388 18:14:10.572105 Final DQM duty delay cell = 0
7389 18:14:10.575143 [0] MAX Duty = 5187%(X100), DQS PI = 8
7390 18:14:10.578584 [0] MIN Duty = 4969%(X100), DQS PI = 46
7391 18:14:10.579109 [0] AVG Duty = 5078%(X100)
7392 18:14:10.582221
7393 18:14:10.582754 ==DQM 1 ==
7394 18:14:10.585000 Final DQM duty delay cell = 0
7395 18:14:10.588471 [0] MAX Duty = 5062%(X100), DQS PI = 14
7396 18:14:10.591495 [0] MIN Duty = 4907%(X100), DQS PI = 34
7397 18:14:10.595073 [0] AVG Duty = 4984%(X100)
7398 18:14:10.595489
7399 18:14:10.598606 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7400 18:14:10.599162
7401 18:14:10.601267 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7402 18:14:10.605218 [DutyScan_Calibration_Flow] ====Done====
7403 18:14:10.605738
7404 18:14:10.608539 [DutyScan_Calibration_Flow] k_type=2
7405 18:14:10.624801
7406 18:14:10.625318 ==DQ 0 ==
7407 18:14:10.628093 Final DQ duty delay cell = -4
7408 18:14:10.631648 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7409 18:14:10.634348 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7410 18:14:10.637971 [-4] AVG Duty = 4953%(X100)
7411 18:14:10.638530
7412 18:14:10.639035 ==DQ 1 ==
7413 18:14:10.641526 Final DQ duty delay cell = 0
7414 18:14:10.644470 [0] MAX Duty = 5156%(X100), DQS PI = 18
7415 18:14:10.647903 [0] MIN Duty = 4938%(X100), DQS PI = 8
7416 18:14:10.648410 [0] AVG Duty = 5047%(X100)
7417 18:14:10.651484
7418 18:14:10.655178 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7419 18:14:10.655614
7420 18:14:10.658133 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7421 18:14:10.661582 [DutyScan_Calibration_Flow] ====Done====
7422 18:14:10.664584 nWR fixed to 30
7423 18:14:10.665201 [ModeRegInit_LP4] CH0 RK0
7424 18:14:10.667499 [ModeRegInit_LP4] CH0 RK1
7425 18:14:10.671372 [ModeRegInit_LP4] CH1 RK0
7426 18:14:10.674964 [ModeRegInit_LP4] CH1 RK1
7427 18:14:10.675621 match AC timing 5
7428 18:14:10.681244 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 18:14:10.683998 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 18:14:10.687378 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 18:14:10.694514 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 18:14:10.697342 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 18:14:10.698048 [MiockJmeterHQA]
7434 18:14:10.698425
7435 18:14:10.701172 [DramcMiockJmeter] u1RxGatingPI = 0
7436 18:14:10.704094 0 : 4253, 4026
7437 18:14:10.704556 4 : 4252, 4027
7438 18:14:10.707500 8 : 4253, 4026
7439 18:14:10.708138 12 : 4253, 4027
7440 18:14:10.708804 16 : 4253, 4026
7441 18:14:10.710317 20 : 4252, 4027
7442 18:14:10.710783 24 : 4255, 4029
7443 18:14:10.714063 28 : 4363, 4137
7444 18:14:10.714620 32 : 4253, 4026
7445 18:14:10.717082 36 : 4252, 4027
7446 18:14:10.717648 40 : 4252, 4027
7447 18:14:10.720614 44 : 4255, 4029
7448 18:14:10.721033 48 : 4252, 4027
7449 18:14:10.721367 52 : 4363, 4140
7450 18:14:10.724332 56 : 4361, 4137
7451 18:14:10.724926 60 : 4252, 4030
7452 18:14:10.727328 64 : 4253, 4026
7453 18:14:10.727927 68 : 4250, 4027
7454 18:14:10.730837 72 : 4250, 4027
7455 18:14:10.731412 76 : 4253, 4029
7456 18:14:10.733950 80 : 4360, 4138
7457 18:14:10.734471 84 : 4250, 4026
7458 18:14:10.734933 88 : 4250, 241
7459 18:14:10.737029 92 : 4360, 0
7460 18:14:10.737610 96 : 4252, 0
7461 18:14:10.740785 100 : 4249, 0
7462 18:14:10.741235 104 : 4250, 0
7463 18:14:10.741567 108 : 4250, 0
7464 18:14:10.743787 112 : 4250, 0
7465 18:14:10.744442 116 : 4250, 0
7466 18:14:10.744990 120 : 4250, 0
7467 18:14:10.747518 124 : 4250, 0
7468 18:14:10.748069 128 : 4250, 0
7469 18:14:10.750508 132 : 4253, 0
7470 18:14:10.750924 136 : 4249, 0
7471 18:14:10.751256 140 : 4250, 0
7472 18:14:10.754084 144 : 4253, 0
7473 18:14:10.754643 148 : 4360, 0
7474 18:14:10.756962 152 : 4360, 0
7475 18:14:10.757400 156 : 4363, 0
7476 18:14:10.757969 160 : 4250, 0
7477 18:14:10.760640 164 : 4250, 0
7478 18:14:10.761090 168 : 4250, 0
7479 18:14:10.761430 172 : 4250, 0
7480 18:14:10.764309 176 : 4250, 0
7481 18:14:10.764760 180 : 4250, 0
7482 18:14:10.766997 184 : 4250, 0
7483 18:14:10.767423 188 : 4250, 0
7484 18:14:10.767824 192 : 4250, 0
7485 18:14:10.770866 196 : 4253, 0
7486 18:14:10.771478 200 : 4360, 0
7487 18:14:10.773727 204 : 4360, 1144
7488 18:14:10.774147 208 : 4249, 3945
7489 18:14:10.776853 212 : 4250, 4026
7490 18:14:10.777272 216 : 4361, 4137
7491 18:14:10.780459 220 : 4250, 4027
7492 18:14:10.781069 224 : 4249, 4027
7493 18:14:10.783335 228 : 4250, 4026
7494 18:14:10.783767 232 : 4253, 4029
7495 18:14:10.784099 236 : 4250, 4027
7496 18:14:10.787392 240 : 4249, 4027
7497 18:14:10.788005 244 : 4360, 4137
7498 18:14:10.790307 248 : 4250, 4027
7499 18:14:10.790726 252 : 4250, 4027
7500 18:14:10.793707 256 : 4360, 4138
7501 18:14:10.794325 260 : 4250, 4027
7502 18:14:10.797095 264 : 4250, 4026
7503 18:14:10.797658 268 : 4363, 4140
7504 18:14:10.800040 272 : 4250, 4027
7505 18:14:10.800517 276 : 4249, 4027
7506 18:14:10.803681 280 : 4250, 4026
7507 18:14:10.804190 284 : 4253, 4029
7508 18:14:10.807279 288 : 4250, 4027
7509 18:14:10.807727 292 : 4249, 4027
7510 18:14:10.808061 296 : 4360, 4137
7511 18:14:10.810338 300 : 4250, 4027
7512 18:14:10.810767 304 : 4250, 4027
7513 18:14:10.813617 308 : 4361, 4085
7514 18:14:10.814056 312 : 4250, 2199
7515 18:14:10.817302 316 : 4252, 20
7516 18:14:10.817726
7517 18:14:10.818055 MIOCK jitter meter ch=0
7518 18:14:10.819968
7519 18:14:10.820575 1T = (316-88) = 228 dly cells
7520 18:14:10.827164 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7521 18:14:10.827637 ==
7522 18:14:10.829887 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 18:14:10.833817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 18:14:10.834266 ==
7525 18:14:10.840368 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 18:14:10.843345 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 18:14:10.849978 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 18:14:10.853611 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 18:14:10.863421 [CA 0] Center 42 (12~73) winsize 62
7530 18:14:10.867258 [CA 1] Center 42 (12~73) winsize 62
7531 18:14:10.870090 [CA 2] Center 38 (8~68) winsize 61
7532 18:14:10.873670 [CA 3] Center 37 (8~67) winsize 60
7533 18:14:10.877296 [CA 4] Center 36 (6~66) winsize 61
7534 18:14:10.880284 [CA 5] Center 35 (6~64) winsize 59
7535 18:14:10.880735
7536 18:14:10.883213 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7537 18:14:10.883625
7538 18:14:10.886811 [CATrainingPosCal] consider 1 rank data
7539 18:14:10.889943 u2DelayCellTimex100 = 285/100 ps
7540 18:14:10.893784 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7541 18:14:10.899804 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7542 18:14:10.903387 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7543 18:14:10.907067 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7544 18:14:10.909743 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7545 18:14:10.913291 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7546 18:14:10.913709
7547 18:14:10.916940 CA PerBit enable=1, Macro0, CA PI delay=35
7548 18:14:10.917353
7549 18:14:10.920477 [CBTSetCACLKResult] CA Dly = 35
7550 18:14:10.923824 CS Dly: 9 (0~40)
7551 18:14:10.926706 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 18:14:10.930279 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 18:14:10.930721 ==
7554 18:14:10.933889 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 18:14:10.936518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 18:14:10.939720 ==
7557 18:14:10.943309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 18:14:10.946310 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 18:14:10.953123 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 18:14:10.956896 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 18:14:10.966625 [CA 0] Center 42 (12~73) winsize 62
7562 18:14:10.970447 [CA 1] Center 42 (12~73) winsize 62
7563 18:14:10.973263 [CA 2] Center 38 (8~68) winsize 61
7564 18:14:10.976846 [CA 3] Center 37 (7~67) winsize 61
7565 18:14:10.980401 [CA 4] Center 36 (6~66) winsize 61
7566 18:14:10.983730 [CA 5] Center 35 (5~65) winsize 61
7567 18:14:10.984145
7568 18:14:10.986708 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 18:14:10.987120
7570 18:14:10.990395 [CATrainingPosCal] consider 2 rank data
7571 18:14:10.993343 u2DelayCellTimex100 = 285/100 ps
7572 18:14:10.997188 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7573 18:14:11.003088 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7574 18:14:11.006825 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7575 18:14:11.009638 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7576 18:14:11.013271 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7577 18:14:11.016846 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7578 18:14:11.017376
7579 18:14:11.019623 CA PerBit enable=1, Macro0, CA PI delay=35
7580 18:14:11.020054
7581 18:14:11.023444 [CBTSetCACLKResult] CA Dly = 35
7582 18:14:11.026869 CS Dly: 10 (0~42)
7583 18:14:11.029525 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 18:14:11.033079 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 18:14:11.033508
7586 18:14:11.036240 ----->DramcWriteLeveling(PI) begin...
7587 18:14:11.036744 ==
7588 18:14:11.039872 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 18:14:11.046550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 18:14:11.046972 ==
7591 18:14:11.049926 Write leveling (Byte 0): 37 => 37
7592 18:14:11.050383 Write leveling (Byte 1): 29 => 29
7593 18:14:11.053220 DramcWriteLeveling(PI) end<-----
7594 18:14:11.053634
7595 18:14:11.053959 ==
7596 18:14:11.056581 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 18:14:11.063004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 18:14:11.063425 ==
7599 18:14:11.066063 [Gating] SW mode calibration
7600 18:14:11.072707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 18:14:11.076417 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 18:14:11.083074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 18:14:11.086192 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 18:14:11.089860 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7605 18:14:11.096396 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7606 18:14:11.099206 1 4 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7607 18:14:11.103121 1 4 20 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7608 18:14:11.106034 1 4 24 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7609 18:14:11.112760 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7610 18:14:11.116290 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7611 18:14:11.119300 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7612 18:14:11.126628 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 0)
7613 18:14:11.129541 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7614 18:14:11.133235 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7615 18:14:11.140078 1 5 20 | B1->B0 | 2323 2e2d | 0 1 | (1 0) (0 0)
7616 18:14:11.142861 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7617 18:14:11.145865 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
7618 18:14:11.152621 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7619 18:14:11.156114 1 6 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7620 18:14:11.159552 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7621 18:14:11.166062 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7622 18:14:11.169433 1 6 16 | B1->B0 | 2828 4645 | 1 1 | (0 0) (0 0)
7623 18:14:11.173232 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7624 18:14:11.179790 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
7625 18:14:11.182693 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 18:14:11.186444 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 18:14:11.193085 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 18:14:11.196003 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 18:14:11.199634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 18:14:11.206176 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 18:14:11.209153 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 18:14:11.212928 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 18:14:11.219590 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 18:14:11.222571 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 18:14:11.226214 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 18:14:11.233032 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 18:14:11.235957 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 18:14:11.239387 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 18:14:11.246250 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 18:14:11.249352 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 18:14:11.252068 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 18:14:11.255609 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 18:14:11.262686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 18:14:11.265591 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 18:14:11.269375 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 18:14:11.275630 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 18:14:11.278689 Total UI for P1: 0, mck2ui 16
7648 18:14:11.282101 best dqsien dly found for B0: ( 1, 9, 10)
7649 18:14:11.285558 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 18:14:11.288327 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 18:14:11.292054 Total UI for P1: 0, mck2ui 16
7652 18:14:11.294942 best dqsien dly found for B1: ( 1, 9, 20)
7653 18:14:11.298748 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7654 18:14:11.302310 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7655 18:14:11.305232
7656 18:14:11.308698 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7657 18:14:11.311592 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7658 18:14:11.315373 [Gating] SW calibration Done
7659 18:14:11.315588 ==
7660 18:14:11.318338 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 18:14:11.322045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 18:14:11.322176 ==
7663 18:14:11.325225 RX Vref Scan: 0
7664 18:14:11.325354
7665 18:14:11.325477 RX Vref 0 -> 0, step: 1
7666 18:14:11.325584
7667 18:14:11.328282 RX Delay 0 -> 252, step: 8
7668 18:14:11.332062 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7669 18:14:11.335165 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7670 18:14:11.341795 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7671 18:14:11.345306 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7672 18:14:11.348634 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7673 18:14:11.351411 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7674 18:14:11.355439 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7675 18:14:11.361860 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7676 18:14:11.365316 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7677 18:14:11.368471 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7678 18:14:11.371504 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7679 18:14:11.375039 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7680 18:14:11.381590 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7681 18:14:11.384897 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7682 18:14:11.388479 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7683 18:14:11.391844 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7684 18:14:11.392315 ==
7685 18:14:11.395022 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 18:14:11.401649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 18:14:11.402067 ==
7688 18:14:11.402471 DQS Delay:
7689 18:14:11.402961 DQS0 = 0, DQS1 = 0
7690 18:14:11.404713 DQM Delay:
7691 18:14:11.405256 DQM0 = 137, DQM1 = 130
7692 18:14:11.408308 DQ Delay:
7693 18:14:11.411356 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7694 18:14:11.414981 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7695 18:14:11.418635 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7696 18:14:11.421517 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7697 18:14:11.422088
7698 18:14:11.422602
7699 18:14:11.423095 ==
7700 18:14:11.424589 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 18:14:11.428419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 18:14:11.431462 ==
7703 18:14:11.431904
7704 18:14:11.432227
7705 18:14:11.432606 TX Vref Scan disable
7706 18:14:11.435107 == TX Byte 0 ==
7707 18:14:11.438164 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7708 18:14:11.441242 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7709 18:14:11.444421 == TX Byte 1 ==
7710 18:14:11.448458 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7711 18:14:11.451456 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7712 18:14:11.454641 ==
7713 18:14:11.455219 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 18:14:11.461434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 18:14:11.461910 ==
7716 18:14:11.473985
7717 18:14:11.477510 TX Vref early break, caculate TX vref
7718 18:14:11.480809 TX Vref=16, minBit 7, minWin=22, winSum=378
7719 18:14:11.483686 TX Vref=18, minBit 0, minWin=23, winSum=382
7720 18:14:11.487380 TX Vref=20, minBit 0, minWin=23, winSum=396
7721 18:14:11.490959 TX Vref=22, minBit 4, minWin=23, winSum=406
7722 18:14:11.493891 TX Vref=24, minBit 3, minWin=24, winSum=415
7723 18:14:11.500615 TX Vref=26, minBit 0, minWin=25, winSum=424
7724 18:14:11.503632 TX Vref=28, minBit 1, minWin=24, winSum=420
7725 18:14:11.507343 TX Vref=30, minBit 1, minWin=24, winSum=416
7726 18:14:11.510669 TX Vref=32, minBit 0, minWin=24, winSum=403
7727 18:14:11.514101 TX Vref=34, minBit 1, minWin=23, winSum=394
7728 18:14:11.520631 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
7729 18:14:11.521056
7730 18:14:11.523545 Final TX Range 0 Vref 26
7731 18:14:11.523978
7732 18:14:11.524306 ==
7733 18:14:11.527385 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 18:14:11.530478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 18:14:11.530899 ==
7736 18:14:11.531485
7737 18:14:11.531919
7738 18:14:11.533643 TX Vref Scan disable
7739 18:14:11.540270 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7740 18:14:11.540718 == TX Byte 0 ==
7741 18:14:11.543753 u2DelayCellOfst[0]=13 cells (4 PI)
7742 18:14:11.546827 u2DelayCellOfst[1]=17 cells (5 PI)
7743 18:14:11.550445 u2DelayCellOfst[2]=13 cells (4 PI)
7744 18:14:11.554126 u2DelayCellOfst[3]=10 cells (3 PI)
7745 18:14:11.557172 u2DelayCellOfst[4]=10 cells (3 PI)
7746 18:14:11.560144 u2DelayCellOfst[5]=0 cells (0 PI)
7747 18:14:11.563932 u2DelayCellOfst[6]=17 cells (5 PI)
7748 18:14:11.566803 u2DelayCellOfst[7]=17 cells (5 PI)
7749 18:14:11.570434 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7750 18:14:11.573871 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7751 18:14:11.576979 == TX Byte 1 ==
7752 18:14:11.577568 u2DelayCellOfst[8]=3 cells (1 PI)
7753 18:14:11.580434 u2DelayCellOfst[9]=0 cells (0 PI)
7754 18:14:11.583379 u2DelayCellOfst[10]=6 cells (2 PI)
7755 18:14:11.587138 u2DelayCellOfst[11]=3 cells (1 PI)
7756 18:14:11.590149 u2DelayCellOfst[12]=10 cells (3 PI)
7757 18:14:11.594158 u2DelayCellOfst[13]=13 cells (4 PI)
7758 18:14:11.596849 u2DelayCellOfst[14]=17 cells (5 PI)
7759 18:14:11.599975 u2DelayCellOfst[15]=10 cells (3 PI)
7760 18:14:11.603747 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7761 18:14:11.609973 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7762 18:14:11.610487 DramC Write-DBI on
7763 18:14:11.610827 ==
7764 18:14:11.613207 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 18:14:11.616995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 18:14:11.620390 ==
7767 18:14:11.620831
7768 18:14:11.621162
7769 18:14:11.621483 TX Vref Scan disable
7770 18:14:11.623732 == TX Byte 0 ==
7771 18:14:11.626700 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7772 18:14:11.630406 == TX Byte 1 ==
7773 18:14:11.633355 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7774 18:14:11.636899 DramC Write-DBI off
7775 18:14:11.637306
7776 18:14:11.637747 [DATLAT]
7777 18:14:11.638112 Freq=1600, CH0 RK0
7778 18:14:11.638449
7779 18:14:11.639872 DATLAT Default: 0xf
7780 18:14:11.640241 0, 0xFFFF, sum = 0
7781 18:14:11.643179 1, 0xFFFF, sum = 0
7782 18:14:11.646760 2, 0xFFFF, sum = 0
7783 18:14:11.647149 3, 0xFFFF, sum = 0
7784 18:14:11.650259 4, 0xFFFF, sum = 0
7785 18:14:11.650542 5, 0xFFFF, sum = 0
7786 18:14:11.652909 6, 0xFFFF, sum = 0
7787 18:14:11.653224 7, 0xFFFF, sum = 0
7788 18:14:11.656917 8, 0xFFFF, sum = 0
7789 18:14:11.657101 9, 0xFFFF, sum = 0
7790 18:14:11.659995 10, 0xFFFF, sum = 0
7791 18:14:11.660179 11, 0xFFFF, sum = 0
7792 18:14:11.662864 12, 0xFFFF, sum = 0
7793 18:14:11.663049 13, 0xFFFF, sum = 0
7794 18:14:11.666499 14, 0x0, sum = 1
7795 18:14:11.666683 15, 0x0, sum = 2
7796 18:14:11.669552 16, 0x0, sum = 3
7797 18:14:11.669735 17, 0x0, sum = 4
7798 18:14:11.672848 best_step = 15
7799 18:14:11.673102
7800 18:14:11.673319 ==
7801 18:14:11.676576 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 18:14:11.679664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 18:14:11.679849 ==
7804 18:14:11.682973 RX Vref Scan: 1
7805 18:14:11.683152
7806 18:14:11.683294 Set Vref Range= 24 -> 127
7807 18:14:11.683428
7808 18:14:11.686617 RX Vref 24 -> 127, step: 1
7809 18:14:11.686854
7810 18:14:11.689507 RX Delay 27 -> 252, step: 4
7811 18:14:11.689688
7812 18:14:11.693265 Set Vref, RX VrefLevel [Byte0]: 24
7813 18:14:11.696044 [Byte1]: 24
7814 18:14:11.696283
7815 18:14:11.699577 Set Vref, RX VrefLevel [Byte0]: 25
7816 18:14:11.703167 [Byte1]: 25
7817 18:14:11.703392
7818 18:14:11.706160 Set Vref, RX VrefLevel [Byte0]: 26
7819 18:14:11.709337 [Byte1]: 26
7820 18:14:11.713263
7821 18:14:11.713442 Set Vref, RX VrefLevel [Byte0]: 27
7822 18:14:11.717167 [Byte1]: 27
7823 18:14:11.721128
7824 18:14:11.721305 Set Vref, RX VrefLevel [Byte0]: 28
7825 18:14:11.724306 [Byte1]: 28
7826 18:14:11.728980
7827 18:14:11.729172 Set Vref, RX VrefLevel [Byte0]: 29
7828 18:14:11.731969 [Byte1]: 29
7829 18:14:11.735801
7830 18:14:11.735991 Set Vref, RX VrefLevel [Byte0]: 30
7831 18:14:11.739698 [Byte1]: 30
7832 18:14:11.743689
7833 18:14:11.743883 Set Vref, RX VrefLevel [Byte0]: 31
7834 18:14:11.746724 [Byte1]: 31
7835 18:14:11.751151
7836 18:14:11.751402 Set Vref, RX VrefLevel [Byte0]: 32
7837 18:14:11.754228 [Byte1]: 32
7838 18:14:11.758862
7839 18:14:11.759105 Set Vref, RX VrefLevel [Byte0]: 33
7840 18:14:11.761902 [Byte1]: 33
7841 18:14:11.766558
7842 18:14:11.766758 Set Vref, RX VrefLevel [Byte0]: 34
7843 18:14:11.770136 [Byte1]: 34
7844 18:14:11.773568
7845 18:14:11.773843 Set Vref, RX VrefLevel [Byte0]: 35
7846 18:14:11.777488 [Byte1]: 35
7847 18:14:11.781281
7848 18:14:11.781467 Set Vref, RX VrefLevel [Byte0]: 36
7849 18:14:11.784599 [Byte1]: 36
7850 18:14:11.788911
7851 18:14:11.789116 Set Vref, RX VrefLevel [Byte0]: 37
7852 18:14:11.792027 [Byte1]: 37
7853 18:14:11.796335
7854 18:14:11.796539 Set Vref, RX VrefLevel [Byte0]: 38
7855 18:14:11.799430 [Byte1]: 38
7856 18:14:11.803960
7857 18:14:11.804142 Set Vref, RX VrefLevel [Byte0]: 39
7858 18:14:11.806955 [Byte1]: 39
7859 18:14:11.811119
7860 18:14:11.811299 Set Vref, RX VrefLevel [Byte0]: 40
7861 18:14:11.814694 [Byte1]: 40
7862 18:14:11.819046
7863 18:14:11.819238 Set Vref, RX VrefLevel [Byte0]: 41
7864 18:14:11.822119 [Byte1]: 41
7865 18:14:11.826071
7866 18:14:11.826155 Set Vref, RX VrefLevel [Byte0]: 42
7867 18:14:11.829891 [Byte1]: 42
7868 18:14:11.833692
7869 18:14:11.833780 Set Vref, RX VrefLevel [Byte0]: 43
7870 18:14:11.837566 [Byte1]: 43
7871 18:14:11.841308
7872 18:14:11.841409 Set Vref, RX VrefLevel [Byte0]: 44
7873 18:14:11.845108 [Byte1]: 44
7874 18:14:11.849164
7875 18:14:11.849268 Set Vref, RX VrefLevel [Byte0]: 45
7876 18:14:11.852193 [Byte1]: 45
7877 18:14:11.856710
7878 18:14:11.856827 Set Vref, RX VrefLevel [Byte0]: 46
7879 18:14:11.859704 [Byte1]: 46
7880 18:14:11.864156
7881 18:14:11.864329 Set Vref, RX VrefLevel [Byte0]: 47
7882 18:14:11.867298 [Byte1]: 47
7883 18:14:11.871925
7884 18:14:11.872087 Set Vref, RX VrefLevel [Byte0]: 48
7885 18:14:11.874898 [Byte1]: 48
7886 18:14:11.879271
7887 18:14:11.879472 Set Vref, RX VrefLevel [Byte0]: 49
7888 18:14:11.882292 [Byte1]: 49
7889 18:14:11.886593
7890 18:14:11.886851 Set Vref, RX VrefLevel [Byte0]: 50
7891 18:14:11.890279 [Byte1]: 50
7892 18:14:11.894346
7893 18:14:11.894632 Set Vref, RX VrefLevel [Byte0]: 51
7894 18:14:11.897845 [Byte1]: 51
7895 18:14:11.901929
7896 18:14:11.902187 Set Vref, RX VrefLevel [Byte0]: 52
7897 18:14:11.905077 [Byte1]: 52
7898 18:14:11.909658
7899 18:14:11.909918 Set Vref, RX VrefLevel [Byte0]: 53
7900 18:14:11.913070 [Byte1]: 53
7901 18:14:11.916909
7902 18:14:11.917167 Set Vref, RX VrefLevel [Byte0]: 54
7903 18:14:11.920472 [Byte1]: 54
7904 18:14:11.924690
7905 18:14:11.924990 Set Vref, RX VrefLevel [Byte0]: 55
7906 18:14:11.928218 [Byte1]: 55
7907 18:14:11.931835
7908 18:14:11.932169 Set Vref, RX VrefLevel [Byte0]: 56
7909 18:14:11.934992 [Byte1]: 56
7910 18:14:11.939669
7911 18:14:11.939932 Set Vref, RX VrefLevel [Byte0]: 57
7912 18:14:11.942901 [Byte1]: 57
7913 18:14:11.947374
7914 18:14:11.947627 Set Vref, RX VrefLevel [Byte0]: 58
7915 18:14:11.950483 [Byte1]: 58
7916 18:14:11.954486
7917 18:14:11.954804 Set Vref, RX VrefLevel [Byte0]: 59
7918 18:14:11.958243 [Byte1]: 59
7919 18:14:11.962024
7920 18:14:11.965673 Set Vref, RX VrefLevel [Byte0]: 60
7921 18:14:11.968399 [Byte1]: 60
7922 18:14:11.968696
7923 18:14:11.972256 Set Vref, RX VrefLevel [Byte0]: 61
7924 18:14:11.975274 [Byte1]: 61
7925 18:14:11.975532
7926 18:14:11.978296 Set Vref, RX VrefLevel [Byte0]: 62
7927 18:14:11.982244 [Byte1]: 62
7928 18:14:11.982608
7929 18:14:11.985320 Set Vref, RX VrefLevel [Byte0]: 63
7930 18:14:11.988424 [Byte1]: 63
7931 18:14:11.992362
7932 18:14:11.992754 Set Vref, RX VrefLevel [Byte0]: 64
7933 18:14:11.995311 [Byte1]: 64
7934 18:14:11.999955
7935 18:14:12.000302 Set Vref, RX VrefLevel [Byte0]: 65
7936 18:14:12.003059 [Byte1]: 65
7937 18:14:12.007719
7938 18:14:12.008067 Set Vref, RX VrefLevel [Byte0]: 66
7939 18:14:12.010632 [Byte1]: 66
7940 18:14:12.015179
7941 18:14:12.015499 Set Vref, RX VrefLevel [Byte0]: 67
7942 18:14:12.018195 [Byte1]: 67
7943 18:14:12.022272
7944 18:14:12.022526 Set Vref, RX VrefLevel [Byte0]: 68
7945 18:14:12.025514 [Byte1]: 68
7946 18:14:12.030284
7947 18:14:12.030646 Set Vref, RX VrefLevel [Byte0]: 69
7948 18:14:12.032857 [Byte1]: 69
7949 18:14:12.037447
7950 18:14:12.037772 Set Vref, RX VrefLevel [Byte0]: 70
7951 18:14:12.040651 [Byte1]: 70
7952 18:14:12.045028
7953 18:14:12.045292 Set Vref, RX VrefLevel [Byte0]: 71
7954 18:14:12.048526 [Byte1]: 71
7955 18:14:12.052616
7956 18:14:12.052878 Set Vref, RX VrefLevel [Byte0]: 72
7957 18:14:12.055591 [Byte1]: 72
7958 18:14:12.060235
7959 18:14:12.060531 Set Vref, RX VrefLevel [Byte0]: 73
7960 18:14:12.063384 [Byte1]: 73
7961 18:14:12.067203
7962 18:14:12.067535 Set Vref, RX VrefLevel [Byte0]: 74
7963 18:14:12.071335 [Byte1]: 74
7964 18:14:12.075361
7965 18:14:12.075618 Final RX Vref Byte 0 = 57 to rank0
7966 18:14:12.078189 Final RX Vref Byte 1 = 63 to rank0
7967 18:14:12.081820 Final RX Vref Byte 0 = 57 to rank1
7968 18:14:12.084919 Final RX Vref Byte 1 = 63 to rank1==
7969 18:14:12.088644 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 18:14:12.094818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 18:14:12.095161 ==
7972 18:14:12.095465 DQS Delay:
7973 18:14:12.098390 DQS0 = 0, DQS1 = 0
7974 18:14:12.098700 DQM Delay:
7975 18:14:12.098962 DQM0 = 134, DQM1 = 128
7976 18:14:12.101360 DQ Delay:
7977 18:14:12.105106 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7978 18:14:12.108172 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =140
7979 18:14:12.111712 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7980 18:14:12.114958 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7981 18:14:12.115244
7982 18:14:12.115507
7983 18:14:12.115755
7984 18:14:12.117907 [DramC_TX_OE_Calibration] TA2
7985 18:14:12.121649 Original DQ_B0 (3 6) =30, OEN = 27
7986 18:14:12.124650 Original DQ_B1 (3 6) =30, OEN = 27
7987 18:14:12.128450 24, 0x0, End_B0=24 End_B1=24
7988 18:14:12.128802 25, 0x0, End_B0=25 End_B1=25
7989 18:14:12.131146 26, 0x0, End_B0=26 End_B1=26
7990 18:14:12.134779 27, 0x0, End_B0=27 End_B1=27
7991 18:14:12.137748 28, 0x0, End_B0=28 End_B1=28
7992 18:14:12.141421 29, 0x0, End_B0=29 End_B1=29
7993 18:14:12.141677 30, 0x0, End_B0=30 End_B1=30
7994 18:14:12.145073 31, 0x4141, End_B0=30 End_B1=30
7995 18:14:12.148008 Byte0 end_step=30 best_step=27
7996 18:14:12.151004 Byte1 end_step=30 best_step=27
7997 18:14:12.154403 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 18:14:12.157948 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 18:14:12.158266
8000 18:14:12.158577
8001 18:14:12.164262 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8002 18:14:12.167389 CH0 RK0: MR19=303, MR18=2420
8003 18:14:12.174040 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
8004 18:14:12.174341
8005 18:14:12.177795 ----->DramcWriteLeveling(PI) begin...
8006 18:14:12.178075 ==
8007 18:14:12.181291 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 18:14:12.183910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 18:14:12.184169 ==
8010 18:14:12.187243 Write leveling (Byte 0): 33 => 33
8011 18:14:12.190850 Write leveling (Byte 1): 27 => 27
8012 18:14:12.194258 DramcWriteLeveling(PI) end<-----
8013 18:14:12.194452
8014 18:14:12.194586 ==
8015 18:14:12.197167 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 18:14:12.200942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 18:14:12.201099 ==
8018 18:14:12.204073 [Gating] SW mode calibration
8019 18:14:12.210770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 18:14:12.217688 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 18:14:12.220745 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8022 18:14:12.227701 1 4 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8023 18:14:12.230657 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8024 18:14:12.233779 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8025 18:14:12.240277 1 4 16 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (1 1)
8026 18:14:12.244116 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8027 18:14:12.246981 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8028 18:14:12.250732 1 4 28 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (0 0)
8029 18:14:12.256958 1 5 0 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8030 18:14:12.260842 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8031 18:14:12.263943 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8032 18:14:12.270198 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8033 18:14:12.274143 1 5 16 | B1->B0 | 2e2e 2827 | 0 1 | (0 0) (0 0)
8034 18:14:12.277068 1 5 20 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8035 18:14:12.283931 1 5 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8036 18:14:12.287386 1 5 28 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8037 18:14:12.290010 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8038 18:14:12.296981 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8039 18:14:12.300204 1 6 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8040 18:14:12.303579 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8041 18:14:12.310309 1 6 16 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
8042 18:14:12.313795 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 18:14:12.317147 1 6 24 | B1->B0 | 4646 4646 | 0 1 | (0 0) (0 0)
8044 18:14:12.323934 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 18:14:12.327087 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 18:14:12.330202 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 18:14:12.336985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 18:14:12.340760 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 18:14:12.343727 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 18:14:12.350468 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 18:14:12.353514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 18:14:12.357281 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 18:14:12.363495 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 18:14:12.367320 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 18:14:12.370632 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 18:14:12.376817 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 18:14:12.379897 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 18:14:12.383741 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 18:14:12.390445 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 18:14:12.393326 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 18:14:12.397057 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 18:14:12.403165 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 18:14:12.406987 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 18:14:12.409960 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 18:14:12.413805 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8066 18:14:12.420367 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 18:14:12.422980 Total UI for P1: 0, mck2ui 16
8068 18:14:12.426453 best dqsien dly found for B0: ( 1, 9, 14)
8069 18:14:12.429957 Total UI for P1: 0, mck2ui 16
8070 18:14:12.433083 best dqsien dly found for B1: ( 1, 9, 14)
8071 18:14:12.436539 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8072 18:14:12.440141 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8073 18:14:12.440567
8074 18:14:12.443071 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8075 18:14:12.446882 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8076 18:14:12.449868 [Gating] SW calibration Done
8077 18:14:12.450266 ==
8078 18:14:12.453330 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 18:14:12.456582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 18:14:12.456807 ==
8081 18:14:12.459454 RX Vref Scan: 0
8082 18:14:12.459674
8083 18:14:12.463556 RX Vref 0 -> 0, step: 1
8084 18:14:12.463778
8085 18:14:12.463951 RX Delay 0 -> 252, step: 8
8086 18:14:12.469769 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8087 18:14:12.472838 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8088 18:14:12.476696 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8089 18:14:12.479701 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8090 18:14:12.482848 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8091 18:14:12.489855 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8092 18:14:12.492860 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8093 18:14:12.496024 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8094 18:14:12.499824 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8095 18:14:12.502765 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8096 18:14:12.509529 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8097 18:14:12.512675 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8098 18:14:12.516327 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8099 18:14:12.519543 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8100 18:14:12.523275 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 18:14:12.529448 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8102 18:14:12.529877 ==
8103 18:14:12.532839 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 18:14:12.536325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 18:14:12.536796 ==
8106 18:14:12.537163 DQS Delay:
8107 18:14:12.539293 DQS0 = 0, DQS1 = 0
8108 18:14:12.539709 DQM Delay:
8109 18:14:12.542391 DQM0 = 137, DQM1 = 128
8110 18:14:12.542970 DQ Delay:
8111 18:14:12.546165 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8112 18:14:12.549256 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8113 18:14:12.552252 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8114 18:14:12.555959 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8115 18:14:12.558911
8116 18:14:12.559216
8117 18:14:12.559477 ==
8118 18:14:12.562491 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 18:14:12.565979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 18:14:12.566132 ==
8121 18:14:12.566262
8122 18:14:12.566427
8123 18:14:12.568879 TX Vref Scan disable
8124 18:14:12.569090 == TX Byte 0 ==
8125 18:14:12.575881 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8126 18:14:12.578943 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8127 18:14:12.579096 == TX Byte 1 ==
8128 18:14:12.585854 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8129 18:14:12.589025 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8130 18:14:12.589184 ==
8131 18:14:12.592115 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 18:14:12.595957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 18:14:12.596112 ==
8134 18:14:12.610201
8135 18:14:12.613065 TX Vref early break, caculate TX vref
8136 18:14:12.616194 TX Vref=16, minBit 1, minWin=23, winSum=391
8137 18:14:12.619972 TX Vref=18, minBit 1, minWin=24, winSum=398
8138 18:14:12.622968 TX Vref=20, minBit 1, minWin=24, winSum=406
8139 18:14:12.626095 TX Vref=22, minBit 1, minWin=25, winSum=415
8140 18:14:12.629925 TX Vref=24, minBit 1, minWin=25, winSum=426
8141 18:14:12.636179 TX Vref=26, minBit 1, minWin=25, winSum=426
8142 18:14:12.639828 TX Vref=28, minBit 1, minWin=26, winSum=432
8143 18:14:12.642763 TX Vref=30, minBit 1, minWin=25, winSum=419
8144 18:14:12.646298 TX Vref=32, minBit 0, minWin=25, winSum=410
8145 18:14:12.649453 TX Vref=34, minBit 0, minWin=24, winSum=402
8146 18:14:12.656179 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 28
8147 18:14:12.656498
8148 18:14:12.659909 Final TX Range 0 Vref 28
8149 18:14:12.660221
8150 18:14:12.660520 ==
8151 18:14:12.662808 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 18:14:12.666631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 18:14:12.666875 ==
8154 18:14:12.667067
8155 18:14:12.667243
8156 18:14:12.669711 TX Vref Scan disable
8157 18:14:12.676020 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8158 18:14:12.676263 == TX Byte 0 ==
8159 18:14:12.679371 u2DelayCellOfst[0]=13 cells (4 PI)
8160 18:14:12.682760 u2DelayCellOfst[1]=13 cells (4 PI)
8161 18:14:12.686508 u2DelayCellOfst[2]=13 cells (4 PI)
8162 18:14:12.689477 u2DelayCellOfst[3]=10 cells (3 PI)
8163 18:14:12.692612 u2DelayCellOfst[4]=10 cells (3 PI)
8164 18:14:12.696685 u2DelayCellOfst[5]=0 cells (0 PI)
8165 18:14:12.699504 u2DelayCellOfst[6]=17 cells (5 PI)
8166 18:14:12.703387 u2DelayCellOfst[7]=17 cells (5 PI)
8167 18:14:12.706203 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8168 18:14:12.710072 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8169 18:14:12.710312 == TX Byte 1 ==
8170 18:14:12.713139 u2DelayCellOfst[8]=0 cells (0 PI)
8171 18:14:12.716167 u2DelayCellOfst[9]=0 cells (0 PI)
8172 18:14:12.719864 u2DelayCellOfst[10]=6 cells (2 PI)
8173 18:14:12.722623 u2DelayCellOfst[11]=6 cells (2 PI)
8174 18:14:12.726225 u2DelayCellOfst[12]=13 cells (4 PI)
8175 18:14:12.729413 u2DelayCellOfst[13]=13 cells (4 PI)
8176 18:14:12.733242 u2DelayCellOfst[14]=13 cells (4 PI)
8177 18:14:12.736405 u2DelayCellOfst[15]=10 cells (3 PI)
8178 18:14:12.739459 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8179 18:14:12.745862 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8180 18:14:12.746023 DramC Write-DBI on
8181 18:14:12.746148 ==
8182 18:14:12.749602 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 18:14:12.752378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 18:14:12.755990 ==
8185 18:14:12.756148
8186 18:14:12.756273
8187 18:14:12.756410 TX Vref Scan disable
8188 18:14:12.759160 == TX Byte 0 ==
8189 18:14:12.763021 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8190 18:14:12.766097 == TX Byte 1 ==
8191 18:14:12.769830 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8192 18:14:12.772980 DramC Write-DBI off
8193 18:14:12.773149
8194 18:14:12.773274 [DATLAT]
8195 18:14:12.773390 Freq=1600, CH0 RK1
8196 18:14:12.773504
8197 18:14:12.776116 DATLAT Default: 0xf
8198 18:14:12.776274 0, 0xFFFF, sum = 0
8199 18:14:12.779292 1, 0xFFFF, sum = 0
8200 18:14:12.779452 2, 0xFFFF, sum = 0
8201 18:14:12.783244 3, 0xFFFF, sum = 0
8202 18:14:12.786120 4, 0xFFFF, sum = 0
8203 18:14:12.786279 5, 0xFFFF, sum = 0
8204 18:14:12.789686 6, 0xFFFF, sum = 0
8205 18:14:12.789846 7, 0xFFFF, sum = 0
8206 18:14:12.793225 8, 0xFFFF, sum = 0
8207 18:14:12.793384 9, 0xFFFF, sum = 0
8208 18:14:12.796056 10, 0xFFFF, sum = 0
8209 18:14:12.796217 11, 0xFFFF, sum = 0
8210 18:14:12.799411 12, 0xFFFF, sum = 0
8211 18:14:12.799571 13, 0xFFFF, sum = 0
8212 18:14:12.803128 14, 0x0, sum = 1
8213 18:14:12.803289 15, 0x0, sum = 2
8214 18:14:12.806223 16, 0x0, sum = 3
8215 18:14:12.806389 17, 0x0, sum = 4
8216 18:14:12.809150 best_step = 15
8217 18:14:12.809306
8218 18:14:12.809430 ==
8219 18:14:12.812887 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 18:14:12.815891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 18:14:12.816049 ==
8222 18:14:12.816174 RX Vref Scan: 0
8223 18:14:12.819681
8224 18:14:12.819837 RX Vref 0 -> 0, step: 1
8225 18:14:12.819963
8226 18:14:12.822701 RX Delay 19 -> 252, step: 4
8227 18:14:12.825733 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8228 18:14:12.832927 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8229 18:14:12.835950 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8230 18:14:12.839683 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8231 18:14:12.842792 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8232 18:14:12.845829 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8233 18:14:12.852584 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8234 18:14:12.856053 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8235 18:14:12.859136 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8236 18:14:12.862771 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8237 18:14:12.865823 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8238 18:14:12.872149 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8239 18:14:12.876001 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8240 18:14:12.879280 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8241 18:14:12.882344 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8242 18:14:12.886248 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8243 18:14:12.889297 ==
8244 18:14:12.889456 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 18:14:12.896021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 18:14:12.896180 ==
8247 18:14:12.896331 DQS Delay:
8248 18:14:12.899139 DQS0 = 0, DQS1 = 0
8249 18:14:12.899302 DQM Delay:
8250 18:14:12.902230 DQM0 = 134, DQM1 = 127
8251 18:14:12.902385 DQ Delay:
8252 18:14:12.905583 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8253 18:14:12.909196 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8254 18:14:12.912079 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8255 18:14:12.915427 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8256 18:14:12.915509
8257 18:14:12.915573
8258 18:14:12.915632
8259 18:14:12.919219 [DramC_TX_OE_Calibration] TA2
8260 18:14:12.922257 Original DQ_B0 (3 6) =30, OEN = 27
8261 18:14:12.925628 Original DQ_B1 (3 6) =30, OEN = 27
8262 18:14:12.929250 24, 0x0, End_B0=24 End_B1=24
8263 18:14:12.932420 25, 0x0, End_B0=25 End_B1=25
8264 18:14:12.932519 26, 0x0, End_B0=26 End_B1=26
8265 18:14:12.936019 27, 0x0, End_B0=27 End_B1=27
8266 18:14:12.938910 28, 0x0, End_B0=28 End_B1=28
8267 18:14:12.942513 29, 0x0, End_B0=29 End_B1=29
8268 18:14:12.942597 30, 0x0, End_B0=30 End_B1=30
8269 18:14:12.945591 31, 0x4141, End_B0=30 End_B1=30
8270 18:14:12.948706 Byte0 end_step=30 best_step=27
8271 18:14:12.952794 Byte1 end_step=30 best_step=27
8272 18:14:12.955872 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 18:14:12.959067 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 18:14:12.959149
8275 18:14:12.959213
8276 18:14:12.965888 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8277 18:14:12.968698 CH0 RK1: MR19=303, MR18=1E06
8278 18:14:12.975330 CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15
8279 18:14:12.978980 [RxdqsGatingPostProcess] freq 1600
8280 18:14:12.982315 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 18:14:12.985333 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 18:14:12.988861 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 18:14:12.992353 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 18:14:12.995527 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 18:14:12.998546 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 18:14:13.002493 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 18:14:13.005585 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 18:14:13.009327 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 18:14:13.012307 Pre-setting of DQS Precalculation
8290 18:14:13.015547 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 18:14:13.015787 ==
8292 18:14:13.019081 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 18:14:13.021893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 18:14:13.025372 ==
8295 18:14:13.028780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 18:14:13.032067 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 18:14:13.038884 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 18:14:13.045549 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 18:14:13.052204 [CA 0] Center 42 (13~72) winsize 60
8300 18:14:13.055914 [CA 1] Center 42 (13~72) winsize 60
8301 18:14:13.058849 [CA 2] Center 39 (10~68) winsize 59
8302 18:14:13.062728 [CA 3] Center 39 (10~68) winsize 59
8303 18:14:13.065628 [CA 4] Center 38 (9~68) winsize 60
8304 18:14:13.069213 [CA 5] Center 37 (8~67) winsize 60
8305 18:14:13.069410
8306 18:14:13.072302 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 18:14:13.072527
8308 18:14:13.075462 [CATrainingPosCal] consider 1 rank data
8309 18:14:13.079102 u2DelayCellTimex100 = 285/100 ps
8310 18:14:13.085459 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8311 18:14:13.089167 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8312 18:14:13.092177 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8313 18:14:13.095836 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8314 18:14:13.098711 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8315 18:14:13.102221 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8316 18:14:13.102421
8317 18:14:13.105787 CA PerBit enable=1, Macro0, CA PI delay=37
8318 18:14:13.106057
8319 18:14:13.108783 [CBTSetCACLKResult] CA Dly = 37
8320 18:14:13.112612 CS Dly: 11 (0~42)
8321 18:14:13.115785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 18:14:13.118906 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 18:14:13.119129 ==
8324 18:14:13.122751 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 18:14:13.125828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 18:14:13.129205 ==
8327 18:14:13.132649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 18:14:13.135621 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 18:14:13.142214 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 18:14:13.149125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 18:14:13.156144 [CA 0] Center 42 (13~72) winsize 60
8332 18:14:13.159198 [CA 1] Center 42 (12~72) winsize 61
8333 18:14:13.162718 [CA 2] Center 38 (9~68) winsize 60
8334 18:14:13.165914 [CA 3] Center 38 (8~68) winsize 61
8335 18:14:13.169333 [CA 4] Center 38 (8~69) winsize 62
8336 18:14:13.172734 [CA 5] Center 37 (7~67) winsize 61
8337 18:14:13.172931
8338 18:14:13.175824 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 18:14:13.176026
8340 18:14:13.178875 [CATrainingPosCal] consider 2 rank data
8341 18:14:13.182856 u2DelayCellTimex100 = 285/100 ps
8342 18:14:13.185711 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8343 18:14:13.192498 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8344 18:14:13.196084 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8345 18:14:13.199026 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8346 18:14:13.202735 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8347 18:14:13.205779 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8348 18:14:13.205976
8349 18:14:13.209554 CA PerBit enable=1, Macro0, CA PI delay=37
8350 18:14:13.209751
8351 18:14:13.212438 [CBTSetCACLKResult] CA Dly = 37
8352 18:14:13.216174 CS Dly: 12 (0~45)
8353 18:14:13.219055 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 18:14:13.222839 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 18:14:13.223044
8356 18:14:13.225819 ----->DramcWriteLeveling(PI) begin...
8357 18:14:13.226018 ==
8358 18:14:13.228884 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 18:14:13.232643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 18:14:13.235541 ==
8361 18:14:13.239212 Write leveling (Byte 0): 27 => 27
8362 18:14:13.239470 Write leveling (Byte 1): 30 => 30
8363 18:14:13.242398 DramcWriteLeveling(PI) end<-----
8364 18:14:13.242595
8365 18:14:13.242749 ==
8366 18:14:13.246355 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 18:14:13.252275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 18:14:13.252500 ==
8369 18:14:13.255381 [Gating] SW mode calibration
8370 18:14:13.262574 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 18:14:13.265340 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 18:14:13.272406 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 18:14:13.275654 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 18:14:13.278975 1 4 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
8375 18:14:13.285063 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8376 18:14:13.288309 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 18:14:13.291899 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 18:14:13.298736 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 18:14:13.301715 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 18:14:13.305526 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 18:14:13.311549 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 18:14:13.315435 1 5 8 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 0)
8383 18:14:13.318553 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
8384 18:14:13.322360 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 18:14:13.328554 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 18:14:13.331612 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 18:14:13.335441 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 18:14:13.341487 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 18:14:13.345399 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 18:14:13.348283 1 6 8 | B1->B0 | 2828 4444 | 0 1 | (0 0) (0 0)
8391 18:14:13.355410 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 18:14:13.358431 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 18:14:13.361526 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 18:14:13.368505 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 18:14:13.371529 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 18:14:13.375328 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 18:14:13.381359 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 18:14:13.384960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 18:14:13.388253 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 18:14:13.394709 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 18:14:13.398568 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 18:14:13.401838 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 18:14:13.408132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 18:14:13.411821 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 18:14:13.415184 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 18:14:13.421470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 18:14:13.425211 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 18:14:13.428311 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 18:14:13.434658 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 18:14:13.438458 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 18:14:13.442233 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 18:14:13.445061 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 18:14:13.452133 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 18:14:13.455046 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 18:14:13.458242 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 18:14:13.465157 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 18:14:13.468034 Total UI for P1: 0, mck2ui 16
8418 18:14:13.471937 best dqsien dly found for B0: ( 1, 9, 10)
8419 18:14:13.475006 Total UI for P1: 0, mck2ui 16
8420 18:14:13.478064 best dqsien dly found for B1: ( 1, 9, 10)
8421 18:14:13.482002 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8422 18:14:13.484919 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8423 18:14:13.485119
8424 18:14:13.487860 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 18:14:13.491548 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 18:14:13.494558 [Gating] SW calibration Done
8427 18:14:13.494758 ==
8428 18:14:13.498257 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 18:14:13.501567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 18:14:13.501780 ==
8431 18:14:13.505096 RX Vref Scan: 0
8432 18:14:13.505309
8433 18:14:13.508119 RX Vref 0 -> 0, step: 1
8434 18:14:13.508373
8435 18:14:13.508540 RX Delay 0 -> 252, step: 8
8436 18:14:13.514821 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8437 18:14:13.518376 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8438 18:14:13.521192 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8439 18:14:13.524466 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8440 18:14:13.527751 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8441 18:14:13.531223 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 18:14:13.537701 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 18:14:13.541509 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8444 18:14:13.545138 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8445 18:14:13.547919 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8446 18:14:13.551298 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 18:14:13.557948 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8448 18:14:13.561032 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8449 18:14:13.564922 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8450 18:14:13.567807 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8451 18:14:13.574860 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8452 18:14:13.575064 ==
8453 18:14:13.577792 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 18:14:13.581081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 18:14:13.581284 ==
8456 18:14:13.581442 DQS Delay:
8457 18:14:13.584803 DQS0 = 0, DQS1 = 0
8458 18:14:13.585004 DQM Delay:
8459 18:14:13.587797 DQM0 = 136, DQM1 = 133
8460 18:14:13.587997 DQ Delay:
8461 18:14:13.591510 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8462 18:14:13.594514 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8463 18:14:13.597657 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8464 18:14:13.601463 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8465 18:14:13.601762
8466 18:14:13.601999
8467 18:14:13.602218 ==
8468 18:14:13.604633 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 18:14:13.611668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 18:14:13.612117 ==
8471 18:14:13.612478
8472 18:14:13.612844
8473 18:14:13.613139 TX Vref Scan disable
8474 18:14:13.615209 == TX Byte 0 ==
8475 18:14:13.618289 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8476 18:14:13.622211 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8477 18:14:13.625351 == TX Byte 1 ==
8478 18:14:13.628272 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8479 18:14:13.634866 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8480 18:14:13.635109 ==
8481 18:14:13.638464 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 18:14:13.641386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 18:14:13.641621 ==
8484 18:14:13.654046
8485 18:14:13.657504 TX Vref early break, caculate TX vref
8486 18:14:13.660619 TX Vref=16, minBit 0, minWin=22, winSum=373
8487 18:14:13.663846 TX Vref=18, minBit 1, minWin=23, winSum=382
8488 18:14:13.666914 TX Vref=20, minBit 1, minWin=24, winSum=396
8489 18:14:13.670241 TX Vref=22, minBit 0, minWin=24, winSum=406
8490 18:14:13.673959 TX Vref=24, minBit 1, minWin=25, winSum=416
8491 18:14:13.680646 TX Vref=26, minBit 1, minWin=25, winSum=422
8492 18:14:13.683685 TX Vref=28, minBit 0, minWin=25, winSum=423
8493 18:14:13.686691 TX Vref=30, minBit 0, minWin=25, winSum=417
8494 18:14:13.690552 TX Vref=32, minBit 6, minWin=24, winSum=408
8495 18:14:13.693654 TX Vref=34, minBit 2, minWin=23, winSum=397
8496 18:14:13.700377 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8497 18:14:13.700524
8498 18:14:13.703405 Final TX Range 0 Vref 28
8499 18:14:13.703549
8500 18:14:13.703662 ==
8501 18:14:13.706579 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 18:14:13.710364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 18:14:13.710510 ==
8504 18:14:13.710688
8505 18:14:13.710851
8506 18:14:13.713322 TX Vref Scan disable
8507 18:14:13.719984 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8508 18:14:13.720212 == TX Byte 0 ==
8509 18:14:13.723381 u2DelayCellOfst[0]=17 cells (5 PI)
8510 18:14:13.726416 u2DelayCellOfst[1]=10 cells (3 PI)
8511 18:14:13.730167 u2DelayCellOfst[2]=0 cells (0 PI)
8512 18:14:13.733245 u2DelayCellOfst[3]=6 cells (2 PI)
8513 18:14:13.736839 u2DelayCellOfst[4]=10 cells (3 PI)
8514 18:14:13.739948 u2DelayCellOfst[5]=17 cells (5 PI)
8515 18:14:13.743261 u2DelayCellOfst[6]=17 cells (5 PI)
8516 18:14:13.747007 u2DelayCellOfst[7]=6 cells (2 PI)
8517 18:14:13.749911 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8518 18:14:13.753074 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8519 18:14:13.756869 == TX Byte 1 ==
8520 18:14:13.759619 u2DelayCellOfst[8]=0 cells (0 PI)
8521 18:14:13.760037 u2DelayCellOfst[9]=3 cells (1 PI)
8522 18:14:13.763454 u2DelayCellOfst[10]=10 cells (3 PI)
8523 18:14:13.766362 u2DelayCellOfst[11]=3 cells (1 PI)
8524 18:14:13.769879 u2DelayCellOfst[12]=13 cells (4 PI)
8525 18:14:13.773560 u2DelayCellOfst[13]=13 cells (4 PI)
8526 18:14:13.776476 u2DelayCellOfst[14]=17 cells (5 PI)
8527 18:14:13.780175 u2DelayCellOfst[15]=17 cells (5 PI)
8528 18:14:13.783072 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8529 18:14:13.789763 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8530 18:14:13.790225 DramC Write-DBI on
8531 18:14:13.790737 ==
8532 18:14:13.793358 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 18:14:13.799722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 18:14:13.800156 ==
8535 18:14:13.800567
8536 18:14:13.800886
8537 18:14:13.801263 TX Vref Scan disable
8538 18:14:13.803441 == TX Byte 0 ==
8539 18:14:13.806478 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8540 18:14:13.810299 == TX Byte 1 ==
8541 18:14:13.813501 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8542 18:14:13.816377 DramC Write-DBI off
8543 18:14:13.816808
8544 18:14:13.817224 [DATLAT]
8545 18:14:13.817599 Freq=1600, CH1 RK0
8546 18:14:13.817911
8547 18:14:13.820159 DATLAT Default: 0xf
8548 18:14:13.823190 0, 0xFFFF, sum = 0
8549 18:14:13.823607 1, 0xFFFF, sum = 0
8550 18:14:13.826737 2, 0xFFFF, sum = 0
8551 18:14:13.827189 3, 0xFFFF, sum = 0
8552 18:14:13.829586 4, 0xFFFF, sum = 0
8553 18:14:13.830027 5, 0xFFFF, sum = 0
8554 18:14:13.833198 6, 0xFFFF, sum = 0
8555 18:14:13.833643 7, 0xFFFF, sum = 0
8556 18:14:13.836598 8, 0xFFFF, sum = 0
8557 18:14:13.837012 9, 0xFFFF, sum = 0
8558 18:14:13.840161 10, 0xFFFF, sum = 0
8559 18:14:13.840627 11, 0xFFFF, sum = 0
8560 18:14:13.843082 12, 0xFFFF, sum = 0
8561 18:14:13.843497 13, 0xFFFF, sum = 0
8562 18:14:13.846718 14, 0x0, sum = 1
8563 18:14:13.847333 15, 0x0, sum = 2
8564 18:14:13.849566 16, 0x0, sum = 3
8565 18:14:13.849981 17, 0x0, sum = 4
8566 18:14:13.853306 best_step = 15
8567 18:14:13.853750
8568 18:14:13.854184 ==
8569 18:14:13.856096 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 18:14:13.859992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 18:14:13.860461 ==
8572 18:14:13.863007 RX Vref Scan: 1
8573 18:14:13.863432
8574 18:14:13.863862 Set Vref Range= 24 -> 127
8575 18:14:13.864271
8576 18:14:13.866159 RX Vref 24 -> 127, step: 1
8577 18:14:13.866582
8578 18:14:13.869895 RX Delay 27 -> 252, step: 4
8579 18:14:13.870306
8580 18:14:13.872821 Set Vref, RX VrefLevel [Byte0]: 24
8581 18:14:13.876470 [Byte1]: 24
8582 18:14:13.876879
8583 18:14:13.879567 Set Vref, RX VrefLevel [Byte0]: 25
8584 18:14:13.883227 [Byte1]: 25
8585 18:14:13.883637
8586 18:14:13.886413 Set Vref, RX VrefLevel [Byte0]: 26
8587 18:14:13.889232 [Byte1]: 26
8588 18:14:13.893741
8589 18:14:13.894148 Set Vref, RX VrefLevel [Byte0]: 27
8590 18:14:13.897140 [Byte1]: 27
8591 18:14:13.901337
8592 18:14:13.901773 Set Vref, RX VrefLevel [Byte0]: 28
8593 18:14:13.904853 [Byte1]: 28
8594 18:14:13.908912
8595 18:14:13.909320 Set Vref, RX VrefLevel [Byte0]: 29
8596 18:14:13.912205 [Byte1]: 29
8597 18:14:13.915921
8598 18:14:13.916397 Set Vref, RX VrefLevel [Byte0]: 30
8599 18:14:13.919251 [Byte1]: 30
8600 18:14:13.923725
8601 18:14:13.924240 Set Vref, RX VrefLevel [Byte0]: 31
8602 18:14:13.926690 [Byte1]: 31
8603 18:14:13.931022
8604 18:14:13.931449 Set Vref, RX VrefLevel [Byte0]: 32
8605 18:14:13.934638 [Byte1]: 32
8606 18:14:13.939057
8607 18:14:13.939510 Set Vref, RX VrefLevel [Byte0]: 33
8608 18:14:13.941895 [Byte1]: 33
8609 18:14:13.946122
8610 18:14:13.946536 Set Vref, RX VrefLevel [Byte0]: 34
8611 18:14:13.949502 [Byte1]: 34
8612 18:14:13.953720
8613 18:14:13.954302 Set Vref, RX VrefLevel [Byte0]: 35
8614 18:14:13.957241 [Byte1]: 35
8615 18:14:13.961628
8616 18:14:13.962196 Set Vref, RX VrefLevel [Byte0]: 36
8617 18:14:13.964398 [Byte1]: 36
8618 18:14:13.968854
8619 18:14:13.969265 Set Vref, RX VrefLevel [Byte0]: 37
8620 18:14:13.972479 [Byte1]: 37
8621 18:14:13.976174
8622 18:14:13.976616 Set Vref, RX VrefLevel [Byte0]: 38
8623 18:14:13.979867 [Byte1]: 38
8624 18:14:13.984076
8625 18:14:13.984556 Set Vref, RX VrefLevel [Byte0]: 39
8626 18:14:13.987022 [Byte1]: 39
8627 18:14:13.991637
8628 18:14:13.992044 Set Vref, RX VrefLevel [Byte0]: 40
8629 18:14:13.994608 [Byte1]: 40
8630 18:14:13.999220
8631 18:14:13.999773 Set Vref, RX VrefLevel [Byte0]: 41
8632 18:14:14.002443 [Byte1]: 41
8633 18:14:14.006857
8634 18:14:14.007461 Set Vref, RX VrefLevel [Byte0]: 42
8635 18:14:14.009852 [Byte1]: 42
8636 18:14:14.014318
8637 18:14:14.014726 Set Vref, RX VrefLevel [Byte0]: 43
8638 18:14:14.017322 [Byte1]: 43
8639 18:14:14.021773
8640 18:14:14.022194 Set Vref, RX VrefLevel [Byte0]: 44
8641 18:14:14.024623 [Byte1]: 44
8642 18:14:14.029425
8643 18:14:14.029863 Set Vref, RX VrefLevel [Byte0]: 45
8644 18:14:14.032246 [Byte1]: 45
8645 18:14:14.036569
8646 18:14:14.036983 Set Vref, RX VrefLevel [Byte0]: 46
8647 18:14:14.039722 [Byte1]: 46
8648 18:14:14.044268
8649 18:14:14.044730 Set Vref, RX VrefLevel [Byte0]: 47
8650 18:14:14.047460 [Byte1]: 47
8651 18:14:14.051571
8652 18:14:14.051874 Set Vref, RX VrefLevel [Byte0]: 48
8653 18:14:14.054673 [Byte1]: 48
8654 18:14:14.059016
8655 18:14:14.059238 Set Vref, RX VrefLevel [Byte0]: 49
8656 18:14:14.062626 [Byte1]: 49
8657 18:14:14.066807
8658 18:14:14.066969 Set Vref, RX VrefLevel [Byte0]: 50
8659 18:14:14.069763 [Byte1]: 50
8660 18:14:14.074123
8661 18:14:14.074257 Set Vref, RX VrefLevel [Byte0]: 51
8662 18:14:14.077099 [Byte1]: 51
8663 18:14:14.081713
8664 18:14:14.081812 Set Vref, RX VrefLevel [Byte0]: 52
8665 18:14:14.084840 [Byte1]: 52
8666 18:14:14.088709
8667 18:14:14.088810 Set Vref, RX VrefLevel [Byte0]: 53
8668 18:14:14.092485 [Byte1]: 53
8669 18:14:14.096734
8670 18:14:14.096834 Set Vref, RX VrefLevel [Byte0]: 54
8671 18:14:14.099958 [Byte1]: 54
8672 18:14:14.103830
8673 18:14:14.103929 Set Vref, RX VrefLevel [Byte0]: 55
8674 18:14:14.107842 [Byte1]: 55
8675 18:14:14.111673
8676 18:14:14.111776 Set Vref, RX VrefLevel [Byte0]: 56
8677 18:14:14.114720 [Byte1]: 56
8678 18:14:14.119354
8679 18:14:14.119454 Set Vref, RX VrefLevel [Byte0]: 57
8680 18:14:14.122361 [Byte1]: 57
8681 18:14:14.127027
8682 18:14:14.127126 Set Vref, RX VrefLevel [Byte0]: 58
8683 18:14:14.130162 [Byte1]: 58
8684 18:14:14.134564
8685 18:14:14.134663 Set Vref, RX VrefLevel [Byte0]: 59
8686 18:14:14.137697 [Byte1]: 59
8687 18:14:14.141552
8688 18:14:14.141653 Set Vref, RX VrefLevel [Byte0]: 60
8689 18:14:14.145141 [Byte1]: 60
8690 18:14:14.149409
8691 18:14:14.149544 Set Vref, RX VrefLevel [Byte0]: 61
8692 18:14:14.152441 [Byte1]: 61
8693 18:14:14.157143
8694 18:14:14.157279 Set Vref, RX VrefLevel [Byte0]: 62
8695 18:14:14.159937 [Byte1]: 62
8696 18:14:14.164211
8697 18:14:14.164316 Set Vref, RX VrefLevel [Byte0]: 63
8698 18:14:14.167669 [Byte1]: 63
8699 18:14:14.171967
8700 18:14:14.172069 Set Vref, RX VrefLevel [Byte0]: 64
8701 18:14:14.175294 [Byte1]: 64
8702 18:14:14.179457
8703 18:14:14.179558 Set Vref, RX VrefLevel [Byte0]: 65
8704 18:14:14.182764 [Byte1]: 65
8705 18:14:14.186853
8706 18:14:14.186985 Set Vref, RX VrefLevel [Byte0]: 66
8707 18:14:14.190326 [Byte1]: 66
8708 18:14:14.194365
8709 18:14:14.194465 Set Vref, RX VrefLevel [Byte0]: 67
8710 18:14:14.198082 [Byte1]: 67
8711 18:14:14.201932
8712 18:14:14.202031 Set Vref, RX VrefLevel [Byte0]: 68
8713 18:14:14.205100 [Byte1]: 68
8714 18:14:14.209677
8715 18:14:14.209777 Set Vref, RX VrefLevel [Byte0]: 69
8716 18:14:14.212797 [Byte1]: 69
8717 18:14:14.217249
8718 18:14:14.217349 Set Vref, RX VrefLevel [Byte0]: 70
8719 18:14:14.220256 [Byte1]: 70
8720 18:14:14.224860
8721 18:14:14.224971 Set Vref, RX VrefLevel [Byte0]: 71
8722 18:14:14.227977 [Byte1]: 71
8723 18:14:14.231797
8724 18:14:14.231888 Set Vref, RX VrefLevel [Byte0]: 72
8725 18:14:14.235708 [Byte1]: 72
8726 18:14:14.239504
8727 18:14:14.239583 Set Vref, RX VrefLevel [Byte0]: 73
8728 18:14:14.243180 [Byte1]: 73
8729 18:14:14.247120
8730 18:14:14.247209 Set Vref, RX VrefLevel [Byte0]: 74
8731 18:14:14.250751 [Byte1]: 74
8732 18:14:14.254518
8733 18:14:14.254625 Set Vref, RX VrefLevel [Byte0]: 75
8734 18:14:14.258343 [Byte1]: 75
8735 18:14:14.262135
8736 18:14:14.262231 Set Vref, RX VrefLevel [Byte0]: 76
8737 18:14:14.265813 [Byte1]: 76
8738 18:14:14.269601
8739 18:14:14.269706 Final RX Vref Byte 0 = 57 to rank0
8740 18:14:14.273203 Final RX Vref Byte 1 = 55 to rank0
8741 18:14:14.276843 Final RX Vref Byte 0 = 57 to rank1
8742 18:14:14.279970 Final RX Vref Byte 1 = 55 to rank1==
8743 18:14:14.283065 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 18:14:14.289881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 18:14:14.289966 ==
8746 18:14:14.290030 DQS Delay:
8747 18:14:14.290106 DQS0 = 0, DQS1 = 0
8748 18:14:14.292936 DQM Delay:
8749 18:14:14.293016 DQM0 = 134, DQM1 = 131
8750 18:14:14.296579 DQ Delay:
8751 18:14:14.300042 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8752 18:14:14.302820 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8753 18:14:14.306414 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8754 18:14:14.309836 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8755 18:14:14.309915
8756 18:14:14.309978
8757 18:14:14.310036
8758 18:14:14.312884 [DramC_TX_OE_Calibration] TA2
8759 18:14:14.316657 Original DQ_B0 (3 6) =30, OEN = 27
8760 18:14:14.319878 Original DQ_B1 (3 6) =30, OEN = 27
8761 18:14:14.322799 24, 0x0, End_B0=24 End_B1=24
8762 18:14:14.322881 25, 0x0, End_B0=25 End_B1=25
8763 18:14:14.326696 26, 0x0, End_B0=26 End_B1=26
8764 18:14:14.329861 27, 0x0, End_B0=27 End_B1=27
8765 18:14:14.332973 28, 0x0, End_B0=28 End_B1=28
8766 18:14:14.333055 29, 0x0, End_B0=29 End_B1=29
8767 18:14:14.336007 30, 0x0, End_B0=30 End_B1=30
8768 18:14:14.339836 31, 0x4141, End_B0=30 End_B1=30
8769 18:14:14.342817 Byte0 end_step=30 best_step=27
8770 18:14:14.346088 Byte1 end_step=30 best_step=27
8771 18:14:14.350171 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 18:14:14.350252 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 18:14:14.353250
8774 18:14:14.353330
8775 18:14:14.359198 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8776 18:14:14.363076 CH1 RK0: MR19=303, MR18=1725
8777 18:14:14.369725 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8778 18:14:14.369882
8779 18:14:14.373281 ----->DramcWriteLeveling(PI) begin...
8780 18:14:14.373417 ==
8781 18:14:14.376326 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 18:14:14.379169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 18:14:14.379273 ==
8784 18:14:14.383214 Write leveling (Byte 0): 25 => 25
8785 18:14:14.386232 Write leveling (Byte 1): 28 => 28
8786 18:14:14.389207 DramcWriteLeveling(PI) end<-----
8787 18:14:14.389396
8788 18:14:14.389561 ==
8789 18:14:14.392721 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 18:14:14.395731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 18:14:14.395882 ==
8792 18:14:14.399341 [Gating] SW mode calibration
8793 18:14:14.406185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 18:14:14.412742 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 18:14:14.415681 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 18:14:14.419367 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 18:14:14.425848 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8798 18:14:14.428986 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8799 18:14:14.432761 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 18:14:14.438772 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 18:14:14.442665 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 18:14:14.445828 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 18:14:14.452541 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 18:14:14.455436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 18:14:14.459202 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8806 18:14:14.465403 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8807 18:14:14.469411 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 18:14:14.472375 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 18:14:14.479096 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 18:14:14.482038 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 18:14:14.485557 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 18:14:14.492118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 18:14:14.495777 1 6 8 | B1->B0 | 3333 2424 | 0 0 | (0 0) (0 0)
8814 18:14:14.498860 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8815 18:14:14.505380 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 18:14:14.509010 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 18:14:14.512551 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 18:14:14.519095 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 18:14:14.522370 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 18:14:14.525228 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8821 18:14:14.532229 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 18:14:14.535871 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 18:14:14.538877 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 18:14:14.545470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 18:14:14.548509 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 18:14:14.552125 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 18:14:14.559048 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 18:14:14.562029 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 18:14:14.565712 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 18:14:14.568621 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 18:14:14.575558 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 18:14:14.578821 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 18:14:14.581744 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 18:14:14.588108 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 18:14:14.591979 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 18:14:14.595452 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 18:14:14.601782 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 18:14:14.604915 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8839 18:14:14.608568 Total UI for P1: 0, mck2ui 16
8840 18:14:14.611628 best dqsien dly found for B1: ( 1, 9, 6)
8841 18:14:14.615155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 18:14:14.618666 Total UI for P1: 0, mck2ui 16
8843 18:14:14.621593 best dqsien dly found for B0: ( 1, 9, 12)
8844 18:14:14.624781 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8845 18:14:14.628554 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8846 18:14:14.628849
8847 18:14:14.635414 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 18:14:14.638384 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8849 18:14:14.642025 [Gating] SW calibration Done
8850 18:14:14.642430 ==
8851 18:14:14.645025 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 18:14:14.648694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 18:14:14.648990 ==
8854 18:14:14.649256 RX Vref Scan: 0
8855 18:14:14.649635
8856 18:14:14.651983 RX Vref 0 -> 0, step: 1
8857 18:14:14.652387
8858 18:14:14.654878 RX Delay 0 -> 252, step: 8
8859 18:14:14.658137 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8860 18:14:14.661977 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8861 18:14:14.664944 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8862 18:14:14.671566 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8863 18:14:14.674725 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8864 18:14:14.678476 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8865 18:14:14.681843 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8866 18:14:14.684945 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8867 18:14:14.691572 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8868 18:14:14.694573 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8869 18:14:14.698511 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8870 18:14:14.701628 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8871 18:14:14.704692 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8872 18:14:14.711318 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8873 18:14:14.714925 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8874 18:14:14.718128 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8875 18:14:14.718280 ==
8876 18:14:14.721120 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 18:14:14.724479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 18:14:14.727931 ==
8879 18:14:14.728075 DQS Delay:
8880 18:14:14.728190 DQS0 = 0, DQS1 = 0
8881 18:14:14.731582 DQM Delay:
8882 18:14:14.731769 DQM0 = 136, DQM1 = 133
8883 18:14:14.734725 DQ Delay:
8884 18:14:14.737622 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8885 18:14:14.741534 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8886 18:14:14.744564 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8887 18:14:14.747585 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8888 18:14:14.747742
8889 18:14:14.747860
8890 18:14:14.747970 ==
8891 18:14:14.751275 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 18:14:14.754810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 18:14:14.754974 ==
8894 18:14:14.755094
8895 18:14:14.757893
8896 18:14:14.758060 TX Vref Scan disable
8897 18:14:14.761160 == TX Byte 0 ==
8898 18:14:14.764152 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 18:14:14.768045 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 18:14:14.770918 == TX Byte 1 ==
8901 18:14:14.774633 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8902 18:14:14.777525 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8903 18:14:14.777698 ==
8904 18:14:14.781314 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 18:14:14.787872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 18:14:14.788022 ==
8907 18:14:14.799934
8908 18:14:14.803917 TX Vref early break, caculate TX vref
8909 18:14:14.807006 TX Vref=16, minBit 0, minWin=23, winSum=381
8910 18:14:14.810108 TX Vref=18, minBit 0, minWin=23, winSum=396
8911 18:14:14.813742 TX Vref=20, minBit 1, minWin=23, winSum=397
8912 18:14:14.816777 TX Vref=22, minBit 0, minWin=25, winSum=409
8913 18:14:14.820404 TX Vref=24, minBit 0, minWin=25, winSum=419
8914 18:14:14.826979 TX Vref=26, minBit 0, minWin=25, winSum=423
8915 18:14:14.830070 TX Vref=28, minBit 0, minWin=25, winSum=426
8916 18:14:14.833663 TX Vref=30, minBit 6, minWin=25, winSum=421
8917 18:14:14.837156 TX Vref=32, minBit 0, minWin=24, winSum=410
8918 18:14:14.840099 TX Vref=34, minBit 0, minWin=24, winSum=406
8919 18:14:14.843444 TX Vref=36, minBit 0, minWin=24, winSum=399
8920 18:14:14.850188 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8921 18:14:14.850366
8922 18:14:14.853893 Final TX Range 0 Vref 28
8923 18:14:14.854066
8924 18:14:14.854199 ==
8925 18:14:14.856904 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 18:14:14.860392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 18:14:14.860621 ==
8928 18:14:14.860816
8929 18:14:14.861001
8930 18:14:14.863060 TX Vref Scan disable
8931 18:14:14.870187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8932 18:14:14.870359 == TX Byte 0 ==
8933 18:14:14.873156 u2DelayCellOfst[0]=20 cells (6 PI)
8934 18:14:14.877106 u2DelayCellOfst[1]=10 cells (3 PI)
8935 18:14:14.880048 u2DelayCellOfst[2]=0 cells (0 PI)
8936 18:14:14.883487 u2DelayCellOfst[3]=6 cells (2 PI)
8937 18:14:14.886756 u2DelayCellOfst[4]=10 cells (3 PI)
8938 18:14:14.889855 u2DelayCellOfst[5]=17 cells (5 PI)
8939 18:14:14.893532 u2DelayCellOfst[6]=17 cells (5 PI)
8940 18:14:14.896894 u2DelayCellOfst[7]=6 cells (2 PI)
8941 18:14:14.900203 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8942 18:14:14.903613 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8943 18:14:14.906656 == TX Byte 1 ==
8944 18:14:14.909827 u2DelayCellOfst[8]=0 cells (0 PI)
8945 18:14:14.910000 u2DelayCellOfst[9]=3 cells (1 PI)
8946 18:14:14.913474 u2DelayCellOfst[10]=10 cells (3 PI)
8947 18:14:14.916438 u2DelayCellOfst[11]=3 cells (1 PI)
8948 18:14:14.920225 u2DelayCellOfst[12]=13 cells (4 PI)
8949 18:14:14.923086 u2DelayCellOfst[13]=17 cells (5 PI)
8950 18:14:14.926884 u2DelayCellOfst[14]=13 cells (4 PI)
8951 18:14:14.929699 u2DelayCellOfst[15]=17 cells (5 PI)
8952 18:14:14.933571 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8953 18:14:14.940227 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8954 18:14:14.940456 DramC Write-DBI on
8955 18:14:14.940603 ==
8956 18:14:14.943163 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 18:14:14.949726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 18:14:14.949958 ==
8959 18:14:14.950104
8960 18:14:14.950231
8961 18:14:14.950352 TX Vref Scan disable
8962 18:14:14.953553 == TX Byte 0 ==
8963 18:14:14.957164 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8964 18:14:14.960284 == TX Byte 1 ==
8965 18:14:14.963298 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8966 18:14:14.966721 DramC Write-DBI off
8967 18:14:14.967063
8968 18:14:14.967289 [DATLAT]
8969 18:14:14.967491 Freq=1600, CH1 RK1
8970 18:14:14.967757
8971 18:14:14.970240 DATLAT Default: 0xf
8972 18:14:14.970568 0, 0xFFFF, sum = 0
8973 18:14:14.973685 1, 0xFFFF, sum = 0
8974 18:14:14.976867 2, 0xFFFF, sum = 0
8975 18:14:14.977225 3, 0xFFFF, sum = 0
8976 18:14:14.979883 4, 0xFFFF, sum = 0
8977 18:14:14.980311 5, 0xFFFF, sum = 0
8978 18:14:14.983719 6, 0xFFFF, sum = 0
8979 18:14:14.984123 7, 0xFFFF, sum = 0
8980 18:14:14.986700 8, 0xFFFF, sum = 0
8981 18:14:14.987102 9, 0xFFFF, sum = 0
8982 18:14:14.990303 10, 0xFFFF, sum = 0
8983 18:14:14.990706 11, 0xFFFF, sum = 0
8984 18:14:14.993262 12, 0xFFFF, sum = 0
8985 18:14:14.993653 13, 0xFFFF, sum = 0
8986 18:14:14.996977 14, 0x0, sum = 1
8987 18:14:14.997370 15, 0x0, sum = 2
8988 18:14:15.000722 16, 0x0, sum = 3
8989 18:14:15.001128 17, 0x0, sum = 4
8990 18:14:15.003878 best_step = 15
8991 18:14:15.004289
8992 18:14:15.004655 ==
8993 18:14:15.006547 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 18:14:15.010348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 18:14:15.010737 ==
8996 18:14:15.013368 RX Vref Scan: 0
8997 18:14:15.013753
8998 18:14:15.014058 RX Vref 0 -> 0, step: 1
8999 18:14:15.014346
9000 18:14:15.017324 RX Delay 19 -> 252, step: 4
9001 18:14:15.020110 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9002 18:14:15.026908 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9003 18:14:15.030242 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9004 18:14:15.033093 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9005 18:14:15.036845 iDelay=195, Bit 4, Center 128 (79 ~ 178) 100
9006 18:14:15.040420 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9007 18:14:15.046578 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9008 18:14:15.050319 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9009 18:14:15.053181 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9010 18:14:15.056611 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9011 18:14:15.059866 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9012 18:14:15.066380 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9013 18:14:15.070154 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9014 18:14:15.072981 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
9015 18:14:15.076665 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9016 18:14:15.079761 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9017 18:14:15.083224 ==
9018 18:14:15.086661 Dram Type= 6, Freq= 0, CH_1, rank 1
9019 18:14:15.089976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9020 18:14:15.090429 ==
9021 18:14:15.090781 DQS Delay:
9022 18:14:15.093278 DQS0 = 0, DQS1 = 0
9023 18:14:15.093717 DQM Delay:
9024 18:14:15.096161 DQM0 = 133, DQM1 = 130
9025 18:14:15.096621 DQ Delay:
9026 18:14:15.099247 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9027 18:14:15.102790 DQ4 =128, DQ5 =146, DQ6 =144, DQ7 =134
9028 18:14:15.106508 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9029 18:14:15.109854 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
9030 18:14:15.110463
9031 18:14:15.110809
9032 18:14:15.111117
9033 18:14:15.113132 [DramC_TX_OE_Calibration] TA2
9034 18:14:15.116316 Original DQ_B0 (3 6) =30, OEN = 27
9035 18:14:15.119290 Original DQ_B1 (3 6) =30, OEN = 27
9036 18:14:15.122390 24, 0x0, End_B0=24 End_B1=24
9037 18:14:15.125969 25, 0x0, End_B0=25 End_B1=25
9038 18:14:15.129701 26, 0x0, End_B0=26 End_B1=26
9039 18:14:15.130188 27, 0x0, End_B0=27 End_B1=27
9040 18:14:15.132820 28, 0x0, End_B0=28 End_B1=28
9041 18:14:15.135762 29, 0x0, End_B0=29 End_B1=29
9042 18:14:15.139235 30, 0x0, End_B0=30 End_B1=30
9043 18:14:15.139675 31, 0x4545, End_B0=30 End_B1=30
9044 18:14:15.142215 Byte0 end_step=30 best_step=27
9045 18:14:15.145721 Byte1 end_step=30 best_step=27
9046 18:14:15.149318 Byte0 TX OE(2T, 0.5T) = (3, 3)
9047 18:14:15.152453 Byte1 TX OE(2T, 0.5T) = (3, 3)
9048 18:14:15.152955
9049 18:14:15.153323
9050 18:14:15.158893 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9051 18:14:15.162467 CH1 RK1: MR19=303, MR18=2006
9052 18:14:15.168689 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
9053 18:14:15.172629 [RxdqsGatingPostProcess] freq 1600
9054 18:14:15.178710 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9055 18:14:15.182446 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 18:14:15.182866 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 18:14:15.185619 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 18:14:15.188613 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 18:14:15.192282 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 18:14:15.195188 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 18:14:15.198621 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 18:14:15.202016 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 18:14:15.205214 Pre-setting of DQS Precalculation
9064 18:14:15.208688 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9065 18:14:15.218804 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9066 18:14:15.224798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 18:14:15.225037
9068 18:14:15.225215
9069 18:14:15.228584 [Calibration Summary] 3200 Mbps
9070 18:14:15.228770 CH 0, Rank 0
9071 18:14:15.231655 SW Impedance : PASS
9072 18:14:15.231807 DUTY Scan : NO K
9073 18:14:15.235226 ZQ Calibration : PASS
9074 18:14:15.238271 Jitter Meter : NO K
9075 18:14:15.238402 CBT Training : PASS
9076 18:14:15.241940 Write leveling : PASS
9077 18:14:15.244826 RX DQS gating : PASS
9078 18:14:15.244959 RX DQ/DQS(RDDQC) : PASS
9079 18:14:15.248357 TX DQ/DQS : PASS
9080 18:14:15.251305 RX DATLAT : PASS
9081 18:14:15.251481 RX DQ/DQS(Engine): PASS
9082 18:14:15.255098 TX OE : PASS
9083 18:14:15.255272 All Pass.
9084 18:14:15.255419
9085 18:14:15.258156 CH 0, Rank 1
9086 18:14:15.258287 SW Impedance : PASS
9087 18:14:15.261798 DUTY Scan : NO K
9088 18:14:15.264747 ZQ Calibration : PASS
9089 18:14:15.264878 Jitter Meter : NO K
9090 18:14:15.268224 CBT Training : PASS
9091 18:14:15.271174 Write leveling : PASS
9092 18:14:15.271304 RX DQS gating : PASS
9093 18:14:15.274890 RX DQ/DQS(RDDQC) : PASS
9094 18:14:15.275022 TX DQ/DQS : PASS
9095 18:14:15.278757 RX DATLAT : PASS
9096 18:14:15.281694 RX DQ/DQS(Engine): PASS
9097 18:14:15.282167 TX OE : PASS
9098 18:14:15.285383 All Pass.
9099 18:14:15.285801
9100 18:14:15.286130 CH 1, Rank 0
9101 18:14:15.288202 SW Impedance : PASS
9102 18:14:15.288682 DUTY Scan : NO K
9103 18:14:15.291955 ZQ Calibration : PASS
9104 18:14:15.294723 Jitter Meter : NO K
9105 18:14:15.295173 CBT Training : PASS
9106 18:14:15.298558 Write leveling : PASS
9107 18:14:15.301416 RX DQS gating : PASS
9108 18:14:15.301835 RX DQ/DQS(RDDQC) : PASS
9109 18:14:15.305074 TX DQ/DQS : PASS
9110 18:14:15.308469 RX DATLAT : PASS
9111 18:14:15.309052 RX DQ/DQS(Engine): PASS
9112 18:14:15.312056 TX OE : PASS
9113 18:14:15.312518 All Pass.
9114 18:14:15.312855
9115 18:14:15.314703 CH 1, Rank 1
9116 18:14:15.315141 SW Impedance : PASS
9117 18:14:15.318317 DUTY Scan : NO K
9118 18:14:15.321628 ZQ Calibration : PASS
9119 18:14:15.322047 Jitter Meter : NO K
9120 18:14:15.324742 CBT Training : PASS
9121 18:14:15.328330 Write leveling : PASS
9122 18:14:15.328857 RX DQS gating : PASS
9123 18:14:15.331682 RX DQ/DQS(RDDQC) : PASS
9124 18:14:15.332061 TX DQ/DQS : PASS
9125 18:14:15.335102 RX DATLAT : PASS
9126 18:14:15.338486 RX DQ/DQS(Engine): PASS
9127 18:14:15.339085 TX OE : PASS
9128 18:14:15.341814 All Pass.
9129 18:14:15.342386
9130 18:14:15.342921 DramC Write-DBI on
9131 18:14:15.344715 PER_BANK_REFRESH: Hybrid Mode
9132 18:14:15.345276 TX_TRACKING: ON
9133 18:14:15.355021 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9134 18:14:15.364715 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9135 18:14:15.371303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9136 18:14:15.375001 [FAST_K] Save calibration result to emmc
9137 18:14:15.378247 sync common calibartion params.
9138 18:14:15.378785 sync cbt_mode0:1, 1:1
9139 18:14:15.381742 dram_init: ddr_geometry: 2
9140 18:14:15.384616 dram_init: ddr_geometry: 2
9141 18:14:15.385029 dram_init: ddr_geometry: 2
9142 18:14:15.388085 0:dram_rank_size:100000000
9143 18:14:15.391688 1:dram_rank_size:100000000
9144 18:14:15.398061 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9145 18:14:15.398481 DFS_SHUFFLE_HW_MODE: ON
9146 18:14:15.401313 dramc_set_vcore_voltage set vcore to 725000
9147 18:14:15.404864 Read voltage for 1600, 0
9148 18:14:15.405279 Vio18 = 0
9149 18:14:15.408210 Vcore = 725000
9150 18:14:15.408782 Vdram = 0
9151 18:14:15.409130 Vddq = 0
9152 18:14:15.411954 Vmddr = 0
9153 18:14:15.412521 switch to 3200 Mbps bootup
9154 18:14:15.414738 [DramcRunTimeConfig]
9155 18:14:15.415152 PHYPLL
9156 18:14:15.417815 DPM_CONTROL_AFTERK: ON
9157 18:14:15.418229 PER_BANK_REFRESH: ON
9158 18:14:15.421636 REFRESH_OVERHEAD_REDUCTION: ON
9159 18:14:15.424438 CMD_PICG_NEW_MODE: OFF
9160 18:14:15.424857 XRTWTW_NEW_MODE: ON
9161 18:14:15.427974 XRTRTR_NEW_MODE: ON
9162 18:14:15.428431 TX_TRACKING: ON
9163 18:14:15.431709 RDSEL_TRACKING: OFF
9164 18:14:15.434416 DQS Precalculation for DVFS: ON
9165 18:14:15.434828 RX_TRACKING: OFF
9166 18:14:15.437982 HW_GATING DBG: ON
9167 18:14:15.438396 ZQCS_ENABLE_LP4: ON
9168 18:14:15.441464 RX_PICG_NEW_MODE: ON
9169 18:14:15.441876 TX_PICG_NEW_MODE: ON
9170 18:14:15.444785 ENABLE_RX_DCM_DPHY: ON
9171 18:14:15.448281 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9172 18:14:15.450978 DUMMY_READ_FOR_TRACKING: OFF
9173 18:14:15.451398 !!! SPM_CONTROL_AFTERK: OFF
9174 18:14:15.454915 !!! SPM could not control APHY
9175 18:14:15.458041 IMPEDANCE_TRACKING: ON
9176 18:14:15.458457 TEMP_SENSOR: ON
9177 18:14:15.461235 HW_SAVE_FOR_SR: OFF
9178 18:14:15.464133 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9179 18:14:15.468180 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9180 18:14:15.468738 Read ODT Tracking: ON
9181 18:14:15.471522 Refresh Rate DeBounce: ON
9182 18:14:15.474347 DFS_NO_QUEUE_FLUSH: ON
9183 18:14:15.477864 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9184 18:14:15.480884 ENABLE_DFS_RUNTIME_MRW: OFF
9185 18:14:15.481299 DDR_RESERVE_NEW_MODE: ON
9186 18:14:15.484725 MR_CBT_SWITCH_FREQ: ON
9187 18:14:15.487512 =========================
9188 18:14:15.505146 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9189 18:14:15.508922 dram_init: ddr_geometry: 2
9190 18:14:15.527182 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9191 18:14:15.529926 dram_init: dram init end (result: 0)
9192 18:14:15.536615 DRAM-K: Full calibration passed in 24436 msecs
9193 18:14:15.539994 MRC: failed to locate region type 0.
9194 18:14:15.540556 DRAM rank0 size:0x100000000,
9195 18:14:15.543598 DRAM rank1 size=0x100000000
9196 18:14:15.552991 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9197 18:14:15.559799 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9198 18:14:15.566928 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9199 18:14:15.572711 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9200 18:14:15.576459 DRAM rank0 size:0x100000000,
9201 18:14:15.579808 DRAM rank1 size=0x100000000
9202 18:14:15.580298 CBMEM:
9203 18:14:15.582877 IMD: root @ 0xfffff000 254 entries.
9204 18:14:15.586071 IMD: root @ 0xffffec00 62 entries.
9205 18:14:15.589765 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9206 18:14:15.596474 WARNING: RO_VPD is uninitialized or empty.
9207 18:14:15.599552 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9208 18:14:15.606768 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9209 18:14:15.619564 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9210 18:14:15.630961 BS: romstage times (exec / console): total (unknown) / 23971 ms
9211 18:14:15.631441
9212 18:14:15.631770
9213 18:14:15.640675 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9214 18:14:15.644328 ARM64: Exception handlers installed.
9215 18:14:15.647204 ARM64: Testing exception
9216 18:14:15.650983 ARM64: Done test exception
9217 18:14:15.651400 Enumerating buses...
9218 18:14:15.654233 Show all devs... Before device enumeration.
9219 18:14:15.657061 Root Device: enabled 1
9220 18:14:15.660912 CPU_CLUSTER: 0: enabled 1
9221 18:14:15.661417 CPU: 00: enabled 1
9222 18:14:15.663860 Compare with tree...
9223 18:14:15.664399 Root Device: enabled 1
9224 18:14:15.667927 CPU_CLUSTER: 0: enabled 1
9225 18:14:15.670309 CPU: 00: enabled 1
9226 18:14:15.670722 Root Device scanning...
9227 18:14:15.679958 scan_static_bus for Root Device
9228 18:14:15.680580 CPU_CLUSTER: 0 enabled
9229 18:14:15.681467 scan_static_bus for Root Device done
9230 18:14:15.683495 scan_bus: bus Root Device finished in 8 msecs
9231 18:14:15.684000 done
9232 18:14:15.690127 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9233 18:14:15.693975 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9234 18:14:15.700543 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9235 18:14:15.704128 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9236 18:14:15.706950 Allocating resources...
9237 18:14:15.710634 Reading resources...
9238 18:14:15.713366 Root Device read_resources bus 0 link: 0
9239 18:14:15.713780 DRAM rank0 size:0x100000000,
9240 18:14:15.716804 DRAM rank1 size=0x100000000
9241 18:14:15.720077 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9242 18:14:15.723282 CPU: 00 missing read_resources
9243 18:14:15.730321 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9244 18:14:15.733356 Root Device read_resources bus 0 link: 0 done
9245 18:14:15.733788 Done reading resources.
9246 18:14:15.739868 Show resources in subtree (Root Device)...After reading.
9247 18:14:15.743048 Root Device child on link 0 CPU_CLUSTER: 0
9248 18:14:15.746706 CPU_CLUSTER: 0 child on link 0 CPU: 00
9249 18:14:15.756203 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9250 18:14:15.756726 CPU: 00
9251 18:14:15.759894 Root Device assign_resources, bus 0 link: 0
9252 18:14:15.762921 CPU_CLUSTER: 0 missing set_resources
9253 18:14:15.769730 Root Device assign_resources, bus 0 link: 0 done
9254 18:14:15.770212 Done setting resources.
9255 18:14:15.776639 Show resources in subtree (Root Device)...After assigning values.
9256 18:14:15.780416 Root Device child on link 0 CPU_CLUSTER: 0
9257 18:14:15.783277 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 18:14:15.792818 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 18:14:15.793329 CPU: 00
9260 18:14:15.796678 Done allocating resources.
9261 18:14:15.799560 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9262 18:14:15.803359 Enabling resources...
9263 18:14:15.803820 done.
9264 18:14:15.809688 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9265 18:14:15.810110 Initializing devices...
9266 18:14:15.813211 Root Device init
9267 18:14:15.813631 init hardware done!
9268 18:14:15.816393 0x00000018: ctrlr->caps
9269 18:14:15.819295 52.000 MHz: ctrlr->f_max
9270 18:14:15.819722 0.400 MHz: ctrlr->f_min
9271 18:14:15.823154 0x40ff8080: ctrlr->voltages
9272 18:14:15.826669 sclk: 390625
9273 18:14:15.827092 Bus Width = 1
9274 18:14:15.827423 sclk: 390625
9275 18:14:15.829549 Bus Width = 1
9276 18:14:15.829968 Early init status = 3
9277 18:14:15.836241 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9278 18:14:15.839877 in-header: 03 fc 00 00 01 00 00 00
9279 18:14:15.840297 in-data: 00
9280 18:14:15.846191 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9281 18:14:15.849744 in-header: 03 fd 00 00 00 00 00 00
9282 18:14:15.852623 in-data:
9283 18:14:15.856194 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 18:14:15.859821 in-header: 03 fc 00 00 01 00 00 00
9285 18:14:15.863316 in-data: 00
9286 18:14:15.866184 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9287 18:14:15.871507 in-header: 03 fd 00 00 00 00 00 00
9288 18:14:15.874669 in-data:
9289 18:14:15.878029 [SSUSB] Setting up USB HOST controller...
9290 18:14:15.881670 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9291 18:14:15.884540 [SSUSB] phy power-on done.
9292 18:14:15.887777 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9293 18:14:15.894587 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9294 18:14:15.897560 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9295 18:14:15.904113 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9296 18:14:15.910789 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9297 18:14:15.917579 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9298 18:14:15.924485 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9299 18:14:15.931252 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9300 18:14:15.934015 SPM: binary array size = 0x9dc
9301 18:14:15.937636 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9302 18:14:15.944324 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9303 18:14:15.950503 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9304 18:14:15.957084 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9305 18:14:15.960482 configure_display: Starting display init
9306 18:14:15.994800 anx7625_power_on_init: Init interface.
9307 18:14:15.998050 anx7625_disable_pd_protocol: Disabled PD feature.
9308 18:14:16.000989 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9309 18:14:16.028878 anx7625_start_dp_work: Secure OCM version=00
9310 18:14:16.032317 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9311 18:14:16.047063 sp_tx_get_edid_block: EDID Block = 1
9312 18:14:16.149534 Extracted contents:
9313 18:14:16.153103 header: 00 ff ff ff ff ff ff 00
9314 18:14:16.156159 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9315 18:14:16.159995 version: 01 04
9316 18:14:16.162894 basic params: 95 1f 11 78 0a
9317 18:14:16.166450 chroma info: 76 90 94 55 54 90 27 21 50 54
9318 18:14:16.169497 established: 00 00 00
9319 18:14:16.176313 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9320 18:14:16.179281 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9321 18:14:16.186101 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9322 18:14:16.192392 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9323 18:14:16.199010 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9324 18:14:16.202614 extensions: 00
9325 18:14:16.202881 checksum: fb
9326 18:14:16.203058
9327 18:14:16.205481 Manufacturer: IVO Model 57d Serial Number 0
9328 18:14:16.209283 Made week 0 of 2020
9329 18:14:16.209495 EDID version: 1.4
9330 18:14:16.212146 Digital display
9331 18:14:16.215872 6 bits per primary color channel
9332 18:14:16.216055 DisplayPort interface
9333 18:14:16.218768 Maximum image size: 31 cm x 17 cm
9334 18:14:16.222339 Gamma: 220%
9335 18:14:16.222488 Check DPMS levels
9336 18:14:16.225812 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9337 18:14:16.232068 First detailed timing is preferred timing
9338 18:14:16.232280 Established timings supported:
9339 18:14:16.235460 Standard timings supported:
9340 18:14:16.238861 Detailed timings
9341 18:14:16.242121 Hex of detail: 383680a07038204018303c0035ae10000019
9342 18:14:16.245296 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9343 18:14:16.252093 0780 0798 07c8 0820 hborder 0
9344 18:14:16.255497 0438 043b 0447 0458 vborder 0
9345 18:14:16.259144 -hsync -vsync
9346 18:14:16.259303 Did detailed timing
9347 18:14:16.265429 Hex of detail: 000000000000000000000000000000000000
9348 18:14:16.265590 Manufacturer-specified data, tag 0
9349 18:14:16.271628 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9350 18:14:16.275431 ASCII string: InfoVision
9351 18:14:16.278344 Hex of detail: 000000fe00523134304e574635205248200a
9352 18:14:16.282243 ASCII string: R140NWF5 RH
9353 18:14:16.282403 Checksum
9354 18:14:16.285023 Checksum: 0xfb (valid)
9355 18:14:16.288659 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9356 18:14:16.291536 DSI data_rate: 832800000 bps
9357 18:14:16.298209 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9358 18:14:16.301772 anx7625_parse_edid: pixelclock(138800).
9359 18:14:16.305195 hactive(1920), hsync(48), hfp(24), hbp(88)
9360 18:14:16.308597 vactive(1080), vsync(12), vfp(3), vbp(17)
9361 18:14:16.311448 anx7625_dsi_config: config dsi.
9362 18:14:16.318008 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9363 18:14:16.331174 anx7625_dsi_config: success to config DSI
9364 18:14:16.334838 anx7625_dp_start: MIPI phy setup OK.
9365 18:14:16.337901 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9366 18:14:16.341648 mtk_ddp_mode_set invalid vrefresh 60
9367 18:14:16.344486 main_disp_path_setup
9368 18:14:16.344646 ovl_layer_smi_id_en
9369 18:14:16.348310 ovl_layer_smi_id_en
9370 18:14:16.348486 ccorr_config
9371 18:14:16.348627 aal_config
9372 18:14:16.351138 gamma_config
9373 18:14:16.351290 postmask_config
9374 18:14:16.354673 dither_config
9375 18:14:16.357684 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9376 18:14:16.364293 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9377 18:14:16.367552 Root Device init finished in 552 msecs
9378 18:14:16.370719 CPU_CLUSTER: 0 init
9379 18:14:16.377929 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9380 18:14:16.381201 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9381 18:14:16.384375 APU_MBOX 0x190000b0 = 0x10001
9382 18:14:16.388025 APU_MBOX 0x190001b0 = 0x10001
9383 18:14:16.390813 APU_MBOX 0x190005b0 = 0x10001
9384 18:14:16.394170 APU_MBOX 0x190006b0 = 0x10001
9385 18:14:16.397919 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9386 18:14:16.410782 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9387 18:14:16.423098 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9388 18:14:16.429891 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9389 18:14:16.441195 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9390 18:14:16.450255 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9391 18:14:16.453316 CPU_CLUSTER: 0 init finished in 81 msecs
9392 18:14:16.457239 Devices initialized
9393 18:14:16.460211 Show all devs... After init.
9394 18:14:16.460393 Root Device: enabled 1
9395 18:14:16.463260 CPU_CLUSTER: 0: enabled 1
9396 18:14:16.467207 CPU: 00: enabled 1
9397 18:14:16.470161 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9398 18:14:16.473237 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9399 18:14:16.476746 ELOG: NV offset 0x57f000 size 0x1000
9400 18:14:16.483488 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9401 18:14:16.490451 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9402 18:14:16.493100 ELOG: Event(17) added with size 13 at 2024-06-11 18:09:33 UTC
9403 18:14:16.496603 out: cmd=0x121: 03 db 21 01 00 00 00 00
9404 18:14:16.500823 in-header: 03 f5 00 00 2c 00 00 00
9405 18:14:16.514334 in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9406 18:14:16.520858 ELOG: Event(A1) added with size 10 at 2024-06-11 18:09:33 UTC
9407 18:14:16.527191 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9408 18:14:16.534005 ELOG: Event(A0) added with size 9 at 2024-06-11 18:09:33 UTC
9409 18:14:16.537774 elog_add_boot_reason: Logged dev mode boot
9410 18:14:16.540655 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9411 18:14:16.544374 Finalize devices...
9412 18:14:16.544805 Devices finalized
9413 18:14:16.550760 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9414 18:14:16.553938 Writing coreboot table at 0xffe64000
9415 18:14:16.557672 0. 000000000010a000-0000000000113fff: RAMSTAGE
9416 18:14:16.560542 1. 0000000040000000-00000000400fffff: RAM
9417 18:14:16.564182 2. 0000000040100000-000000004032afff: RAMSTAGE
9418 18:14:16.570140 3. 000000004032b000-00000000545fffff: RAM
9419 18:14:16.574116 4. 0000000054600000-000000005465ffff: BL31
9420 18:14:16.577056 5. 0000000054660000-00000000ffe63fff: RAM
9421 18:14:16.583676 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9422 18:14:16.587421 7. 0000000100000000-000000023fffffff: RAM
9423 18:14:16.587839 Passing 5 GPIOs to payload:
9424 18:14:16.593443 NAME | PORT | POLARITY | VALUE
9425 18:14:16.596974 EC in RW | 0x000000aa | low | undefined
9426 18:14:16.603154 EC interrupt | 0x00000005 | low | undefined
9427 18:14:16.607159 TPM interrupt | 0x000000ab | high | undefined
9428 18:14:16.610488 SD card detect | 0x00000011 | high | undefined
9429 18:14:16.616931 speaker enable | 0x00000093 | high | undefined
9430 18:14:16.620009 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9431 18:14:16.623993 in-header: 03 f9 00 00 02 00 00 00
9432 18:14:16.624451 in-data: 02 00
9433 18:14:16.626847 ADC[4]: Raw value=904726 ID=7
9434 18:14:16.630545 ADC[3]: Raw value=213441 ID=1
9435 18:14:16.633418 RAM Code: 0x71
9436 18:14:16.633846 ADC[6]: Raw value=75701 ID=0
9437 18:14:16.636947 ADC[5]: Raw value=213072 ID=1
9438 18:14:16.640128 SKU Code: 0x1
9439 18:14:16.643871 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f641
9440 18:14:16.646711 coreboot table: 964 bytes.
9441 18:14:16.650177 IMD ROOT 0. 0xfffff000 0x00001000
9442 18:14:16.653697 IMD SMALL 1. 0xffffe000 0x00001000
9443 18:14:16.656629 RO MCACHE 2. 0xffffc000 0x00001104
9444 18:14:16.660569 CONSOLE 3. 0xfff7c000 0x00080000
9445 18:14:16.663325 FMAP 4. 0xfff7b000 0x00000452
9446 18:14:16.667000 TIME STAMP 5. 0xfff7a000 0x00000910
9447 18:14:16.669976 VBOOT WORK 6. 0xfff66000 0x00014000
9448 18:14:16.672859 RAMOOPS 7. 0xffe66000 0x00100000
9449 18:14:16.676746 COREBOOT 8. 0xffe64000 0x00002000
9450 18:14:16.677173 IMD small region:
9451 18:14:16.679724 IMD ROOT 0. 0xffffec00 0x00000400
9452 18:14:16.683369 VPD 1. 0xffffeb80 0x0000006c
9453 18:14:16.686493 MMC STATUS 2. 0xffffeb60 0x00000004
9454 18:14:16.693011 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9455 18:14:16.696674 Probing TPM: done!
9456 18:14:16.699640 Connected to device vid:did:rid of 1ae0:0028:00
9457 18:14:16.709641 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9458 18:14:16.713338 Initialized TPM device CR50 revision 0
9459 18:14:16.717050 Checking cr50 for pending updates
9460 18:14:16.720725 Reading cr50 TPM mode
9461 18:14:16.729369 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9462 18:14:16.735711 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9463 18:14:16.775953 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9464 18:14:16.779713 Checking segment from ROM address 0x40100000
9465 18:14:16.782824 Checking segment from ROM address 0x4010001c
9466 18:14:16.789247 Loading segment from ROM address 0x40100000
9467 18:14:16.789667 code (compression=0)
9468 18:14:16.799394 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9469 18:14:16.805826 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9470 18:14:16.806320 it's not compressed!
9471 18:14:16.812572 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9472 18:14:16.816253 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9473 18:14:16.836562 Loading segment from ROM address 0x4010001c
9474 18:14:16.837013 Entry Point 0x80000000
9475 18:14:16.839741 Loaded segments
9476 18:14:16.842699 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9477 18:14:16.849612 Jumping to boot code at 0x80000000(0xffe64000)
9478 18:14:16.856450 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9479 18:14:16.862611 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9480 18:14:16.870951 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9481 18:14:16.874160 Checking segment from ROM address 0x40100000
9482 18:14:16.877128 Checking segment from ROM address 0x4010001c
9483 18:14:16.883999 Loading segment from ROM address 0x40100000
9484 18:14:16.884473 code (compression=1)
9485 18:14:16.890533 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9486 18:14:16.900503 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9487 18:14:16.900925 using LZMA
9488 18:14:16.909338 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9489 18:14:16.915772 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9490 18:14:16.919517 Loading segment from ROM address 0x4010001c
9491 18:14:16.919995 Entry Point 0x54601000
9492 18:14:16.922384 Loaded segments
9493 18:14:16.926023 NOTICE: MT8192 bl31_setup
9494 18:14:16.932588 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9495 18:14:16.936265 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9496 18:14:16.939191 WARNING: region 0:
9497 18:14:16.942734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 18:14:16.943161 WARNING: region 1:
9499 18:14:16.949428 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9500 18:14:16.952497 WARNING: region 2:
9501 18:14:16.956125 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9502 18:14:16.959116 WARNING: region 3:
9503 18:14:16.962818 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 18:14:16.965985 WARNING: region 4:
9505 18:14:16.972709 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 18:14:16.973170 WARNING: region 5:
9507 18:14:16.976419 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 18:14:16.979301 WARNING: region 6:
9509 18:14:16.982997 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 18:14:16.986028 WARNING: region 7:
9511 18:14:16.989448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 18:14:16.996234 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9513 18:14:16.999634 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9514 18:14:17.002930 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9515 18:14:17.009448 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9516 18:14:17.012713 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9517 18:14:17.016092 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9518 18:14:17.022569 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9519 18:14:17.025954 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9520 18:14:17.032707 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9521 18:14:17.036181 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9522 18:14:17.039243 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9523 18:14:17.046581 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9524 18:14:17.049503 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9525 18:14:17.052742 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9526 18:14:17.059359 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9527 18:14:17.063027 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9528 18:14:17.065999 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9529 18:14:17.073150 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9530 18:14:17.076545 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9531 18:14:17.083184 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9532 18:14:17.086020 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9533 18:14:17.089698 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9534 18:14:17.096175 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9535 18:14:17.099316 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9536 18:14:17.106498 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9537 18:14:17.109343 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9538 18:14:17.112956 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9539 18:14:17.119658 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9540 18:14:17.122858 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9541 18:14:17.125981 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9542 18:14:17.132445 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9543 18:14:17.135986 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9544 18:14:17.142793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9545 18:14:17.146028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9546 18:14:17.149238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9547 18:14:17.152906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9548 18:14:17.159505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9549 18:14:17.162710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9550 18:14:17.165923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9551 18:14:17.169607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9552 18:14:17.172487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9553 18:14:17.179075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9554 18:14:17.182770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9555 18:14:17.186266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9556 18:14:17.189685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9557 18:14:17.196022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9558 18:14:17.199825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9559 18:14:17.202963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9560 18:14:17.209435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9561 18:14:17.213099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9562 18:14:17.216728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9563 18:14:17.223196 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9564 18:14:17.226080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9565 18:14:17.233330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9566 18:14:17.236242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9567 18:14:17.242876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9568 18:14:17.246608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9569 18:14:17.249757 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9570 18:14:17.256418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9571 18:14:17.260084 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9572 18:14:17.266329 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9573 18:14:17.269707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9574 18:14:17.276718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9575 18:14:17.279482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9576 18:14:17.286384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9577 18:14:17.289359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9578 18:14:17.293254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9579 18:14:17.299627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9580 18:14:17.303076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9581 18:14:17.309983 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9582 18:14:17.312729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9583 18:14:17.316330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9584 18:14:17.323127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9585 18:14:17.326288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9586 18:14:17.332855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9587 18:14:17.336205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9588 18:14:17.342832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9589 18:14:17.346479 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9590 18:14:17.353027 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9591 18:14:17.356060 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9592 18:14:17.359605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9593 18:14:17.366391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9594 18:14:17.369433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9595 18:14:17.375963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9596 18:14:17.379612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9597 18:14:17.386396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9598 18:14:17.389289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9599 18:14:17.392906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9600 18:14:17.399381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9601 18:14:17.402819 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9602 18:14:17.409507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9603 18:14:17.412911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9604 18:14:17.419616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9605 18:14:17.422980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9606 18:14:17.429485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9607 18:14:17.433142 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9608 18:14:17.436043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9609 18:14:17.439570 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9610 18:14:17.446790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9611 18:14:17.449693 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9612 18:14:17.453502 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9613 18:14:17.459392 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9614 18:14:17.463088 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9615 18:14:17.466093 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9616 18:14:17.472946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9617 18:14:17.476636 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9618 18:14:17.480156 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9619 18:14:17.486655 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9620 18:14:17.490202 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9621 18:14:17.496741 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9622 18:14:17.499571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9623 18:14:17.503376 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9624 18:14:17.510079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9625 18:14:17.513071 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9626 18:14:17.520232 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9627 18:14:17.523053 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9628 18:14:17.526796 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9629 18:14:17.533394 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9630 18:14:17.536441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9631 18:14:17.539902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9632 18:14:17.543216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9633 18:14:17.549776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9634 18:14:17.552928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9635 18:14:17.556520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9636 18:14:17.562959 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9637 18:14:17.566271 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9638 18:14:17.569612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9639 18:14:17.576851 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9640 18:14:17.580051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9641 18:14:17.583611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9642 18:14:17.589632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9643 18:14:17.593097 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9644 18:14:17.599685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9645 18:14:17.603471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9646 18:14:17.606319 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9647 18:14:17.613062 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9648 18:14:17.616694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9649 18:14:17.620077 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9650 18:14:17.626694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9651 18:14:17.630325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9652 18:14:17.636267 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9653 18:14:17.639708 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9654 18:14:17.643289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9655 18:14:17.649910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9656 18:14:17.653582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9657 18:14:17.659708 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9658 18:14:17.663466 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9659 18:14:17.666402 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9660 18:14:17.673036 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9661 18:14:17.676418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9662 18:14:17.683432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9663 18:14:17.686755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9664 18:14:17.689720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9665 18:14:17.696544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9666 18:14:17.700183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9667 18:14:17.703040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9668 18:14:17.709533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9669 18:14:17.713171 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9670 18:14:17.720047 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9671 18:14:17.723134 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9672 18:14:17.726175 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9673 18:14:17.733497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9674 18:14:17.736693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9675 18:14:17.743317 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9676 18:14:17.746128 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9677 18:14:17.749801 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9678 18:14:17.756416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9679 18:14:17.759557 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9680 18:14:17.763368 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9681 18:14:17.769537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9682 18:14:17.773319 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9683 18:14:17.779946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9684 18:14:17.783043 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9685 18:14:17.786255 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9686 18:14:17.792609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9687 18:14:17.796205 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9688 18:14:17.802984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9689 18:14:17.806113 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9690 18:14:17.809175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9691 18:14:17.815703 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9692 18:14:17.819242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9693 18:14:17.825910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9694 18:14:17.829328 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9695 18:14:17.832793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9696 18:14:17.839395 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9697 18:14:17.842785 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9698 18:14:17.849449 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9699 18:14:17.852466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9700 18:14:17.855453 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9701 18:14:17.861919 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9702 18:14:17.865531 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9703 18:14:17.872320 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9704 18:14:17.875438 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9705 18:14:17.882065 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9706 18:14:17.886006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9707 18:14:17.888940 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9708 18:14:17.895596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9709 18:14:17.899321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9710 18:14:17.905356 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9711 18:14:17.909231 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9712 18:14:17.911936 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9713 18:14:17.919308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9714 18:14:17.922037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9715 18:14:17.928878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9716 18:14:17.932370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9717 18:14:17.938641 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9718 18:14:17.941776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9719 18:14:17.945678 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9720 18:14:17.952023 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9721 18:14:17.955310 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9722 18:14:17.961882 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9723 18:14:17.965020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9724 18:14:17.968308 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9725 18:14:17.975201 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9726 18:14:17.978869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9727 18:14:17.985063 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9728 18:14:17.988693 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9729 18:14:17.995430 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9730 18:14:17.998555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9731 18:14:18.001393 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9732 18:14:18.008291 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9733 18:14:18.011936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9734 18:14:18.018438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9735 18:14:18.022145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9736 18:14:18.025346 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9737 18:14:18.031645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9738 18:14:18.035417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9739 18:14:18.042049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9740 18:14:18.044708 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9741 18:14:18.048114 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9742 18:14:18.051642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9743 18:14:18.057979 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9744 18:14:18.061691 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9745 18:14:18.064646 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9746 18:14:18.071880 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9747 18:14:18.074662 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9748 18:14:18.078006 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9749 18:14:18.084835 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9750 18:14:18.087968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9751 18:14:18.091738 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9752 18:14:18.098275 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9753 18:14:18.101297 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9754 18:14:18.107841 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9755 18:14:18.111666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9756 18:14:18.114658 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9757 18:14:18.121238 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9758 18:14:18.124846 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9759 18:14:18.127765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9760 18:14:18.134182 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9761 18:14:18.137673 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9762 18:14:18.141108 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9763 18:14:18.147676 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9764 18:14:18.151038 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9765 18:14:18.154615 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9766 18:14:18.160735 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9767 18:14:18.164014 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9768 18:14:18.171341 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9769 18:14:18.174313 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9770 18:14:18.177763 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9771 18:14:18.184258 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9772 18:14:18.187298 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9773 18:14:18.194459 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9774 18:14:18.197264 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9775 18:14:18.200679 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9776 18:14:18.207330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9777 18:14:18.211023 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9778 18:14:18.213964 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9779 18:14:18.220776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9780 18:14:18.224012 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9781 18:14:18.227582 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9782 18:14:18.230502 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9783 18:14:18.236984 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9784 18:14:18.240765 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9785 18:14:18.243802 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9786 18:14:18.247409 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9787 18:14:18.253863 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9788 18:14:18.257357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9789 18:14:18.260451 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9790 18:14:18.263522 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9791 18:14:18.270007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9792 18:14:18.273514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9793 18:14:18.277016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9794 18:14:18.283702 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9795 18:14:18.286686 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9796 18:14:18.293458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9797 18:14:18.297231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9798 18:14:18.300163 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9799 18:14:18.306884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9800 18:14:18.309835 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9801 18:14:18.316203 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9802 18:14:18.319542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9803 18:14:18.323169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9804 18:14:18.329961 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9805 18:14:18.332739 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9806 18:14:18.339637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9807 18:14:18.343316 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9808 18:14:18.349861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9809 18:14:18.352966 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9810 18:14:18.355741 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9811 18:14:18.362524 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9812 18:14:18.366188 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9813 18:14:18.372707 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9814 18:14:18.375884 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9815 18:14:18.382589 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9816 18:14:18.386075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9817 18:14:18.388980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9818 18:14:18.396285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9819 18:14:18.399156 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9820 18:14:18.402983 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9821 18:14:18.409458 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9822 18:14:18.413136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9823 18:14:18.419090 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9824 18:14:18.422752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9825 18:14:18.425686 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9826 18:14:18.432296 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9827 18:14:18.436082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9828 18:14:18.442547 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9829 18:14:18.445608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9830 18:14:18.452283 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9831 18:14:18.455569 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9832 18:14:18.458957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9833 18:14:18.465968 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9834 18:14:18.469317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9835 18:14:18.475757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9836 18:14:18.478867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9837 18:14:18.482526 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9838 18:14:18.489012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9839 18:14:18.492513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9840 18:14:18.499120 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9841 18:14:18.502513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9842 18:14:18.505516 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9843 18:14:18.512170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9844 18:14:18.515849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9845 18:14:18.521675 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9846 18:14:18.525323 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9847 18:14:18.531968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9848 18:14:18.535639 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9849 18:14:18.538644 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9850 18:14:18.545445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9851 18:14:18.548698 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9852 18:14:18.555157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9853 18:14:18.558744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9854 18:14:18.561818 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9855 18:14:18.568637 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9856 18:14:18.572305 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9857 18:14:18.578733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9858 18:14:18.581789 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9859 18:14:18.585358 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9860 18:14:18.592139 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9861 18:14:18.595297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9862 18:14:18.602017 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9863 18:14:18.605506 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9864 18:14:18.611623 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9865 18:14:18.614824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9866 18:14:18.618277 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9867 18:14:18.625169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9868 18:14:18.628416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9869 18:14:18.634691 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9870 18:14:18.637940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9871 18:14:18.644910 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9872 18:14:18.647873 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9873 18:14:18.650883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9874 18:14:18.657857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9875 18:14:18.661160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9876 18:14:18.667929 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9877 18:14:18.671298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9878 18:14:18.677886 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9879 18:14:18.681115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9880 18:14:18.684564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9881 18:14:18.691094 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9882 18:14:18.694752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9883 18:14:18.700793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9884 18:14:18.704134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9885 18:14:18.710928 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9886 18:14:18.714648 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9887 18:14:18.717471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9888 18:14:18.724300 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9889 18:14:18.727925 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9890 18:14:18.734358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9891 18:14:18.737834 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9892 18:14:18.743814 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9893 18:14:18.747531 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9894 18:14:18.750698 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9895 18:14:18.757273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9896 18:14:18.761092 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9897 18:14:18.767128 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9898 18:14:18.770837 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9899 18:14:18.777206 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9900 18:14:18.780637 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9901 18:14:18.783962 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9902 18:14:18.790602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9903 18:14:18.794034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9904 18:14:18.800580 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9905 18:14:18.804193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9906 18:14:18.811132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9907 18:14:18.814142 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9908 18:14:18.820929 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9909 18:14:18.823984 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9910 18:14:18.827491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9911 18:14:18.833540 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9912 18:14:18.836951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9913 18:14:18.843600 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9914 18:14:18.847160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9915 18:14:18.849964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9916 18:14:18.857017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9917 18:14:18.860596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9918 18:14:18.866551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9919 18:14:18.870396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9920 18:14:18.876807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9921 18:14:18.879739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9922 18:14:18.886370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9923 18:14:18.889727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9924 18:14:18.896291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9925 18:14:18.900130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9926 18:14:18.906598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9927 18:14:18.910011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9928 18:14:18.916606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9929 18:14:18.920051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9930 18:14:18.926628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9931 18:14:18.929645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9932 18:14:18.936337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9933 18:14:18.939821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9934 18:14:18.946124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9935 18:14:18.949625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9936 18:14:18.956191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9937 18:14:18.959905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9938 18:14:18.966118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9939 18:14:18.969449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9940 18:14:18.976021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9941 18:14:18.979693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9942 18:14:18.986299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9943 18:14:18.989463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9944 18:14:18.996098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9945 18:14:18.999757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9946 18:14:19.002646 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9947 18:14:19.006242 INFO: [APUAPC] vio 0
9948 18:14:19.012998 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9949 18:14:19.015932 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9950 18:14:19.019745 INFO: [APUAPC] D0_APC_0: 0x400510
9951 18:14:19.022419 INFO: [APUAPC] D0_APC_1: 0x0
9952 18:14:19.025858 INFO: [APUAPC] D0_APC_2: 0x1540
9953 18:14:19.029113 INFO: [APUAPC] D0_APC_3: 0x0
9954 18:14:19.032351 INFO: [APUAPC] D1_APC_0: 0xffffffff
9955 18:14:19.036085 INFO: [APUAPC] D1_APC_1: 0xffffffff
9956 18:14:19.039123 INFO: [APUAPC] D1_APC_2: 0x3fffff
9957 18:14:19.042765 INFO: [APUAPC] D1_APC_3: 0x0
9958 18:14:19.045825 INFO: [APUAPC] D2_APC_0: 0xffffffff
9959 18:14:19.048877 INFO: [APUAPC] D2_APC_1: 0xffffffff
9960 18:14:19.052455 INFO: [APUAPC] D2_APC_2: 0x3fffff
9961 18:14:19.052536 INFO: [APUAPC] D2_APC_3: 0x0
9962 18:14:19.058722 INFO: [APUAPC] D3_APC_0: 0xffffffff
9963 18:14:19.062521 INFO: [APUAPC] D3_APC_1: 0xffffffff
9964 18:14:19.065576 INFO: [APUAPC] D3_APC_2: 0x3fffff
9965 18:14:19.065658 INFO: [APUAPC] D3_APC_3: 0x0
9966 18:14:19.069268 INFO: [APUAPC] D4_APC_0: 0xffffffff
9967 18:14:19.072219 INFO: [APUAPC] D4_APC_1: 0xffffffff
9968 18:14:19.075884 INFO: [APUAPC] D4_APC_2: 0x3fffff
9969 18:14:19.078722 INFO: [APUAPC] D4_APC_3: 0x0
9970 18:14:19.082290 INFO: [APUAPC] D5_APC_0: 0xffffffff
9971 18:14:19.085811 INFO: [APUAPC] D5_APC_1: 0xffffffff
9972 18:14:19.089275 INFO: [APUAPC] D5_APC_2: 0x3fffff
9973 18:14:19.092373 INFO: [APUAPC] D5_APC_3: 0x0
9974 18:14:19.095467 INFO: [APUAPC] D6_APC_0: 0xffffffff
9975 18:14:19.099269 INFO: [APUAPC] D6_APC_1: 0xffffffff
9976 18:14:19.102217 INFO: [APUAPC] D6_APC_2: 0x3fffff
9977 18:14:19.105955 INFO: [APUAPC] D6_APC_3: 0x0
9978 18:14:19.108862 INFO: [APUAPC] D7_APC_0: 0xffffffff
9979 18:14:19.112468 INFO: [APUAPC] D7_APC_1: 0xffffffff
9980 18:14:19.116229 INFO: [APUAPC] D7_APC_2: 0x3fffff
9981 18:14:19.118624 INFO: [APUAPC] D7_APC_3: 0x0
9982 18:14:19.121986 INFO: [APUAPC] D8_APC_0: 0xffffffff
9983 18:14:19.125570 INFO: [APUAPC] D8_APC_1: 0xffffffff
9984 18:14:19.129149 INFO: [APUAPC] D8_APC_2: 0x3fffff
9985 18:14:19.132057 INFO: [APUAPC] D8_APC_3: 0x0
9986 18:14:19.135163 INFO: [APUAPC] D9_APC_0: 0xffffffff
9987 18:14:19.138641 INFO: [APUAPC] D9_APC_1: 0xffffffff
9988 18:14:19.142499 INFO: [APUAPC] D9_APC_2: 0x3fffff
9989 18:14:19.145362 INFO: [APUAPC] D9_APC_3: 0x0
9990 18:14:19.149206 INFO: [APUAPC] D10_APC_0: 0xffffffff
9991 18:14:19.152117 INFO: [APUAPC] D10_APC_1: 0xffffffff
9992 18:14:19.155916 INFO: [APUAPC] D10_APC_2: 0x3fffff
9993 18:14:19.158851 INFO: [APUAPC] D10_APC_3: 0x0
9994 18:14:19.162406 INFO: [APUAPC] D11_APC_0: 0xffffffff
9995 18:14:19.165188 INFO: [APUAPC] D11_APC_1: 0xffffffff
9996 18:14:19.168805 INFO: [APUAPC] D11_APC_2: 0x3fffff
9997 18:14:19.171800 INFO: [APUAPC] D11_APC_3: 0x0
9998 18:14:19.175422 INFO: [APUAPC] D12_APC_0: 0xffffffff
9999 18:14:19.178295 INFO: [APUAPC] D12_APC_1: 0xffffffff
10000 18:14:19.181969 INFO: [APUAPC] D12_APC_2: 0x3fffff
10001 18:14:19.184890 INFO: [APUAPC] D12_APC_3: 0x0
10002 18:14:19.188590 INFO: [APUAPC] D13_APC_0: 0xffffffff
10003 18:14:19.192125 INFO: [APUAPC] D13_APC_1: 0xffffffff
10004 18:14:19.195574 INFO: [APUAPC] D13_APC_2: 0x3fffff
10005 18:14:19.198419 INFO: [APUAPC] D13_APC_3: 0x0
10006 18:14:19.202205 INFO: [APUAPC] D14_APC_0: 0xffffffff
10007 18:14:19.205187 INFO: [APUAPC] D14_APC_1: 0xffffffff
10008 18:14:19.208219 INFO: [APUAPC] D14_APC_2: 0x3fffff
10009 18:14:19.212008 INFO: [APUAPC] D14_APC_3: 0x0
10010 18:14:19.214926 INFO: [APUAPC] D15_APC_0: 0xffffffff
10011 18:14:19.218521 INFO: [APUAPC] D15_APC_1: 0xffffffff
10012 18:14:19.222145 INFO: [APUAPC] D15_APC_2: 0x3fffff
10013 18:14:19.225043 INFO: [APUAPC] D15_APC_3: 0x0
10014 18:14:19.228734 INFO: [APUAPC] APC_CON: 0x4
10015 18:14:19.231488 INFO: [NOCDAPC] D0_APC_0: 0x0
10016 18:14:19.234957 INFO: [NOCDAPC] D0_APC_1: 0x0
10017 18:14:19.235043 INFO: [NOCDAPC] D1_APC_0: 0x0
10018 18:14:19.238691 INFO: [NOCDAPC] D1_APC_1: 0xfff
10019 18:14:19.241579 INFO: [NOCDAPC] D2_APC_0: 0x0
10020 18:14:19.245041 INFO: [NOCDAPC] D2_APC_1: 0xfff
10021 18:14:19.248171 INFO: [NOCDAPC] D3_APC_0: 0x0
10022 18:14:19.251800 INFO: [NOCDAPC] D3_APC_1: 0xfff
10023 18:14:19.255012 INFO: [NOCDAPC] D4_APC_0: 0x0
10024 18:14:19.258517 INFO: [NOCDAPC] D4_APC_1: 0xfff
10025 18:14:19.261881 INFO: [NOCDAPC] D5_APC_0: 0x0
10026 18:14:19.264948 INFO: [NOCDAPC] D5_APC_1: 0xfff
10027 18:14:19.268316 INFO: [NOCDAPC] D6_APC_0: 0x0
10028 18:14:19.268441 INFO: [NOCDAPC] D6_APC_1: 0xfff
10029 18:14:19.271858 INFO: [NOCDAPC] D7_APC_0: 0x0
10030 18:14:19.274620 INFO: [NOCDAPC] D7_APC_1: 0xfff
10031 18:14:19.278097 INFO: [NOCDAPC] D8_APC_0: 0x0
10032 18:14:19.281706 INFO: [NOCDAPC] D8_APC_1: 0xfff
10033 18:14:19.284631 INFO: [NOCDAPC] D9_APC_0: 0x0
10034 18:14:19.288304 INFO: [NOCDAPC] D9_APC_1: 0xfff
10035 18:14:19.291281 INFO: [NOCDAPC] D10_APC_0: 0x0
10036 18:14:19.294976 INFO: [NOCDAPC] D10_APC_1: 0xfff
10037 18:14:19.298074 INFO: [NOCDAPC] D11_APC_0: 0x0
10038 18:14:19.301643 INFO: [NOCDAPC] D11_APC_1: 0xfff
10039 18:14:19.305146 INFO: [NOCDAPC] D12_APC_0: 0x0
10040 18:14:19.308116 INFO: [NOCDAPC] D12_APC_1: 0xfff
10041 18:14:19.308198 INFO: [NOCDAPC] D13_APC_0: 0x0
10042 18:14:19.311801 INFO: [NOCDAPC] D13_APC_1: 0xfff
10043 18:14:19.314873 INFO: [NOCDAPC] D14_APC_0: 0x0
10044 18:14:19.317886 INFO: [NOCDAPC] D14_APC_1: 0xfff
10045 18:14:19.321602 INFO: [NOCDAPC] D15_APC_0: 0x0
10046 18:14:19.324552 INFO: [NOCDAPC] D15_APC_1: 0xfff
10047 18:14:19.328330 INFO: [NOCDAPC] APC_CON: 0x4
10048 18:14:19.331469 INFO: [APUAPC] set_apusys_apc done
10049 18:14:19.335120 INFO: [DEVAPC] devapc_init done
10050 18:14:19.338001 INFO: GICv3 without legacy support detected.
10051 18:14:19.341474 INFO: ARM GICv3 driver initialized in EL3
10052 18:14:19.348234 INFO: Maximum SPI INTID supported: 639
10053 18:14:19.351121 INFO: BL31: Initializing runtime services
10054 18:14:19.354813 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10055 18:14:19.357931 INFO: SPM: enable CPC mode
10056 18:14:19.364462 INFO: mcdi ready for mcusys-off-idle and system suspend
10057 18:14:19.368058 INFO: BL31: Preparing for EL3 exit to normal world
10058 18:14:19.371666 INFO: Entry point address = 0x80000000
10059 18:14:19.374970 INFO: SPSR = 0x8
10060 18:14:19.380111
10061 18:14:19.380210
10062 18:14:19.380309
10063 18:14:19.383584 Starting depthcharge on Spherion...
10064 18:14:19.383667
10065 18:14:19.383728 Wipe memory regions:
10066 18:14:19.383786
10067 18:14:19.384572 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10068 18:14:19.384678 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10069 18:14:19.384771 Setting prompt string to ['asurada:']
10070 18:14:19.384891 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10071 18:14:19.386954 [0x00000040000000, 0x00000054600000)
10072 18:14:19.509387
10073 18:14:19.509523 [0x00000054660000, 0x00000080000000)
10074 18:14:19.770101
10075 18:14:19.770256 [0x000000821a7280, 0x000000ffe64000)
10076 18:14:20.514846
10077 18:14:20.515004 [0x00000100000000, 0x00000240000000)
10078 18:14:22.404644
10079 18:14:22.408376 Initializing XHCI USB controller at 0x11200000.
10080 18:14:23.447013
10081 18:14:23.449996 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10082 18:14:23.450136
10083 18:14:23.450259
10084 18:14:23.450597 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 18:14:23.551067 asurada: tftpboot 192.168.201.1 14291475/tftp-deploy-mf64n40c/kernel/image.itb 14291475/tftp-deploy-mf64n40c/kernel/cmdline
10087 18:14:23.551258 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 18:14:23.551401 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 18:14:23.555407 tftpboot 192.168.201.1 14291475/tftp-deploy-mf64n40c/kernel/image.itb tp-deploy-mf64n40c/kernel/cmdline
10090 18:14:23.555569
10091 18:14:23.555711 Waiting for link
10092 18:14:23.715669
10093 18:14:23.715837 R8152: Initializing
10094 18:14:23.715946
10095 18:14:23.719125 Version 9 (ocp_data = 6010)
10096 18:14:23.719249
10097 18:14:23.722578 R8152: Done initializing
10098 18:14:23.722696
10099 18:14:23.722795 Adding net device
10100 18:14:25.669010
10101 18:14:25.669209 done.
10102 18:14:25.669280
10103 18:14:25.669379 MAC: 00:e0:4c:78:7a:aa
10104 18:14:25.669455
10105 18:14:25.672018 Sending DHCP discover... done.
10106 18:14:25.672098
10107 18:14:25.674969 Waiting for reply... done.
10108 18:14:25.675049
10109 18:14:25.678279 Sending DHCP request... done.
10110 18:14:25.678405
10111 18:14:25.688175 Waiting for reply... done.
10112 18:14:25.688273
10113 18:14:25.688359 My ip is 192.168.201.12
10114 18:14:25.688443
10115 18:14:25.691124 The DHCP server ip is 192.168.201.1
10116 18:14:25.691195
10117 18:14:25.698153 TFTP server IP predefined by user: 192.168.201.1
10118 18:14:25.698285
10119 18:14:25.704895 Bootfile predefined by user: 14291475/tftp-deploy-mf64n40c/kernel/image.itb
10120 18:14:25.704976
10121 18:14:25.707896 Sending tftp read request... done.
10122 18:14:25.707976
10123 18:14:25.711772 Waiting for the transfer...
10124 18:14:25.711863
10125 18:14:25.972210 00000000 ################################################################
10126 18:14:25.972365
10127 18:14:26.225426 00080000 ################################################################
10128 18:14:26.225592
10129 18:14:26.477745 00100000 ################################################################
10130 18:14:26.477907
10131 18:14:26.727368 00180000 ################################################################
10132 18:14:26.727502
10133 18:14:26.981165 00200000 ################################################################
10134 18:14:26.981336
10135 18:14:27.229152 00280000 ################################################################
10136 18:14:27.229304
10137 18:14:27.476708 00300000 ################################################################
10138 18:14:27.476878
10139 18:14:27.726359 00380000 ################################################################
10140 18:14:27.726496
10141 18:14:27.985593 00400000 ################################################################
10142 18:14:27.985742
10143 18:14:28.245142 00480000 ################################################################
10144 18:14:28.245272
10145 18:14:28.493965 00500000 ################################################################
10146 18:14:28.494131
10147 18:14:28.739998 00580000 ################################################################
10148 18:14:28.740165
10149 18:14:28.985893 00600000 ################################################################
10150 18:14:28.986032
10151 18:14:29.234239 00680000 ################################################################
10152 18:14:29.234376
10153 18:14:29.487251 00700000 ################################################################
10154 18:14:29.487423
10155 18:14:29.738480 00780000 ################################################################
10156 18:14:29.738611
10157 18:14:29.991294 00800000 ################################################################
10158 18:14:29.991430
10159 18:14:30.248218 00880000 ################################################################
10160 18:14:30.248414
10161 18:14:30.511740 00900000 ################################################################
10162 18:14:30.511933
10163 18:14:30.773180 00980000 ################################################################
10164 18:14:30.773314
10165 18:14:31.028028 00a00000 ################################################################
10166 18:14:31.028186
10167 18:14:31.285397 00a80000 ################################################################
10168 18:14:31.285543
10169 18:14:31.544023 00b00000 ################################################################
10170 18:14:31.544211
10171 18:14:31.789614 00b80000 ################################################################
10172 18:14:31.789751
10173 18:14:32.036250 00c00000 ################################################################
10174 18:14:32.036466
10175 18:14:32.294057 00c80000 ################################################################
10176 18:14:32.294194
10177 18:14:32.563267 00d00000 ################################################################
10178 18:14:32.563403
10179 18:14:32.828970 00d80000 ################################################################
10180 18:14:32.829132
10181 18:14:33.097064 00e00000 ################################################################
10182 18:14:33.097243
10183 18:14:33.363025 00e80000 ################################################################
10184 18:14:33.363215
10185 18:14:33.634487 00f00000 ################################################################
10186 18:14:33.634641
10187 18:14:33.898648 00f80000 ################################################################
10188 18:14:33.898792
10189 18:14:34.156978 01000000 ################################################################
10190 18:14:34.157150
10191 18:14:34.422563 01080000 ################################################################
10192 18:14:34.422709
10193 18:14:34.680729 01100000 ################################################################
10194 18:14:34.680920
10195 18:14:34.939031 01180000 ################################################################
10196 18:14:34.939206
10197 18:14:35.193248 01200000 ################################################################
10198 18:14:35.193385
10199 18:14:35.452218 01280000 ################################################################
10200 18:14:35.452365
10201 18:14:35.711036 01300000 ################################################################
10202 18:14:35.711211
10203 18:14:35.966426 01380000 ################################################################
10204 18:14:35.966606
10205 18:14:36.221220 01400000 ################################################################
10206 18:14:36.221366
10207 18:14:36.480214 01480000 ################################################################
10208 18:14:36.480404
10209 18:14:36.743081 01500000 ################################################################
10210 18:14:36.743253
10211 18:14:37.008825 01580000 ################################################################
10212 18:14:37.008975
10213 18:14:37.274668 01600000 ################################################################
10214 18:14:37.274867
10215 18:14:37.528949 01680000 ################################################################
10216 18:14:37.529130
10217 18:14:37.784003 01700000 ################################################################
10218 18:14:37.784186
10219 18:14:38.037389 01780000 ################################################################
10220 18:14:38.037593
10221 18:14:38.281695 01800000 ################################################################
10222 18:14:38.281861
10223 18:14:38.540052 01880000 ################################################################
10224 18:14:38.540229
10225 18:14:38.804686 01900000 ################################################################
10226 18:14:38.804827
10227 18:14:39.062895 01980000 ################################################################
10228 18:14:39.063047
10229 18:14:39.317012 01a00000 ################################################################
10230 18:14:39.317197
10231 18:14:39.568361 01a80000 ################################################################
10232 18:14:39.568514
10233 18:14:39.823455 01b00000 ################################################################
10234 18:14:39.823614
10235 18:14:40.076248 01b80000 ################################################################
10236 18:14:40.076428
10237 18:14:40.343541 01c00000 ################################################################
10238 18:14:40.343698
10239 18:14:40.607928 01c80000 ################################################################
10240 18:14:40.608109
10241 18:14:40.872041 01d00000 ################################################################
10242 18:14:40.872210
10243 18:14:41.136627 01d80000 ################################################################
10244 18:14:41.136761
10245 18:14:41.376746 01e00000 ######################################################## done.
10246 18:14:41.376884
10247 18:14:41.380539 The bootfile was 31911478 bytes long.
10248 18:14:41.380622
10249 18:14:41.383438 Sending tftp read request... done.
10250 18:14:41.383546
10251 18:14:41.386482 Waiting for the transfer...
10252 18:14:41.386591
10253 18:14:41.386682 00000000 # done.
10254 18:14:41.390128
10255 18:14:41.396773 Command line loaded dynamically from TFTP file: 14291475/tftp-deploy-mf64n40c/kernel/cmdline
10256 18:14:41.396882
10257 18:14:41.420181 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10258 18:14:41.420309
10259 18:14:41.420443 Loading FIT.
10260 18:14:41.420538
10261 18:14:41.423084 Image ramdisk-1 has 18737083 bytes.
10262 18:14:41.423184
10263 18:14:41.426471 Image fdt-1 has 47258 bytes.
10264 18:14:41.426568
10265 18:14:41.429713 Image kernel-1 has 13125101 bytes.
10266 18:14:41.429790
10267 18:14:41.436190 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 18:14:41.436282
10269 18:14:41.456581 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 18:14:41.456714
10271 18:14:41.459446 Choosing best match conf-1 for compat google,spherion-rev2.
10272 18:14:41.464540
10273 18:14:41.469494 Connected to device vid:did:rid of 1ae0:0028:00
10274 18:14:41.476184
10275 18:14:41.479186 tpm_get_response: command 0x17b, return code 0x0
10276 18:14:41.479293
10277 18:14:41.482989 ec_init: CrosEC protocol v3 supported (256, 248)
10278 18:14:41.488302
10279 18:14:41.491541 tpm_cleanup: add release locality here.
10280 18:14:41.491648
10281 18:14:41.491715 Shutting down all USB controllers.
10282 18:14:41.494795
10283 18:14:41.494905 Removing current net device
10284 18:14:41.494999
10285 18:14:41.501397 Exiting depthcharge with code 4 at timestamp: 51373353
10286 18:14:41.501506
10287 18:14:41.504552 LZMA decompressing kernel-1 to 0x821a6718
10288 18:14:41.504629
10289 18:14:41.508053 LZMA decompressing kernel-1 to 0x40000000
10290 18:14:43.125936
10291 18:14:43.126436 jumping to kernel
10292 18:14:43.128146 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10293 18:14:43.128791 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10294 18:14:43.129324 Setting prompt string to ['Linux version [0-9]']
10295 18:14:43.129721 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 18:14:43.130068 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 18:14:43.207689
10298 18:14:43.211554 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 18:14:43.214552 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10300 18:14:43.214646 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 18:14:43.214717 Setting prompt string to []
10302 18:14:43.214793 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 18:14:43.214866 Using line separator: #'\n'#
10304 18:14:43.214924 No login prompt set.
10305 18:14:43.214984 Parsing kernel messages
10306 18:14:43.215037 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 18:14:43.215136 [login-action] Waiting for messages, (timeout 00:04:01)
10308 18:14:43.215200 Waiting using forced prompt support (timeout 00:02:01)
10309 18:14:43.234774 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10310 18:14:43.237811 [ 0.000000] random: crng init done
10311 18:14:43.244530 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 18:14:43.248225 [ 0.000000] efi: UEFI not found.
10313 18:14:43.254116 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 18:14:43.261250 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 18:14:43.270983 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 18:14:43.281107 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 18:14:43.287733 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 18:14:43.294531 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 18:14:43.300534 [ 0.000000] NUMA: No NUMA configuration found
10320 18:14:43.307257 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 18:14:43.310897 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10322 18:14:43.313685 [ 0.000000] Zone ranges:
10323 18:14:43.320612 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 18:14:43.323737 [ 0.000000] DMA32 empty
10325 18:14:43.330712 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 18:14:43.333726 [ 0.000000] Movable zone start for each node
10327 18:14:43.337241 [ 0.000000] Early memory node ranges
10328 18:14:43.344143 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 18:14:43.350673 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 18:14:43.357241 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 18:14:43.360281 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 18:14:43.367169 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 18:14:43.373572 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 18:14:43.432683 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 18:14:43.439594 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 18:14:43.445404 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 18:14:43.448887 [ 0.000000] psci: probing for conduit method from DT.
10338 18:14:43.456008 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 18:14:43.458618 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 18:14:43.465773 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 18:14:43.468718 [ 0.000000] psci: SMC Calling Convention v1.2
10342 18:14:43.475586 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10343 18:14:43.478678 [ 0.000000] Detected VIPT I-cache on CPU0
10344 18:14:43.485293 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 18:14:43.492160 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 18:14:43.499032 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 18:14:43.505116 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 18:14:43.512549 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 18:14:43.518466 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 18:14:43.525448 [ 0.000000] alternatives: applying boot alternatives
10351 18:14:43.528547 [ 0.000000] Fallback order for Node 0: 0
10352 18:14:43.535533 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 18:14:43.538713 [ 0.000000] Policy zone: Normal
10354 18:14:43.562339 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10355 18:14:43.575677 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 18:14:43.585916 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 18:14:43.595369 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 18:14:43.602467 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 18:14:43.605503 <6>[ 0.000000] software IO TLB: area num 8.
10360 18:14:43.662862 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 18:14:43.811585 <6>[ 0.000000] Memory: 7945764K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407004K reserved, 32768K cma-reserved)
10362 18:14:43.818856 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 18:14:43.825053 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 18:14:43.828807 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 18:14:43.834947 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 18:14:43.841756 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 18:14:43.845170 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 18:14:43.855212 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 18:14:43.861918 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 18:14:43.867790 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 18:14:43.874836 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 18:14:43.877920 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 18:14:43.881809 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 18:14:43.887972 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 18:14:43.891625 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 18:14:43.898339 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 18:14:43.911293 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 18:14:43.921418 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 18:14:43.931329 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 18:14:43.938867 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 18:14:43.951832 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 18:14:43.958608 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 18:14:43.965481 <6>[ 0.009186] Console: colour dummy device 80x25
10384 18:14:43.975114 <6>[ 0.013945] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 18:14:43.978190 <6>[ 0.024387] pid_max: default: 32768 minimum: 301
10386 18:14:43.984858 <6>[ 0.029288] LSM: Security Framework initializing
10387 18:14:43.991702 <6>[ 0.034254] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 18:14:44.001770 <6>[ 0.042068] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 18:14:44.007816 <6>[ 0.051472] cblist_init_generic: Setting adjustable number of callback queues.
10390 18:14:44.014711 <6>[ 0.058914] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 18:14:44.024487 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10392 18:14:44.031410 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 18:14:44.034577 <6>[ 0.079121] rcu: Hierarchical SRCU implementation.
10394 18:14:44.041817 <6>[ 0.084166] rcu: Max phase no-delay instances is 1000.
10395 18:14:44.047649 <6>[ 0.091200] EFI services will not be available.
10396 18:14:44.051390 <6>[ 0.096154] smp: Bringing up secondary CPUs ...
10397 18:14:44.059223 <6>[ 0.101204] Detected VIPT I-cache on CPU1
10398 18:14:44.065689 <6>[ 0.101275] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10399 18:14:44.072303 <6>[ 0.101306] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10400 18:14:44.076046 <6>[ 0.101644] Detected VIPT I-cache on CPU2
10401 18:14:44.082873 <6>[ 0.101695] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10402 18:14:44.089606 <6>[ 0.101713] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10403 18:14:44.095624 <6>[ 0.101971] Detected VIPT I-cache on CPU3
10404 18:14:44.102693 <6>[ 0.102017] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10405 18:14:44.109386 <6>[ 0.102031] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10406 18:14:44.112434 <6>[ 0.102337] CPU features: detected: Spectre-v4
10407 18:14:44.119287 <6>[ 0.102342] CPU features: detected: Spectre-BHB
10408 18:14:44.122275 <6>[ 0.102347] Detected PIPT I-cache on CPU4
10409 18:14:44.129028 <6>[ 0.102408] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10410 18:14:44.135809 <6>[ 0.102425] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10411 18:14:44.142546 <6>[ 0.102716] Detected PIPT I-cache on CPU5
10412 18:14:44.148939 <6>[ 0.102780] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10413 18:14:44.155699 <6>[ 0.102797] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10414 18:14:44.158645 <6>[ 0.103078] Detected PIPT I-cache on CPU6
10415 18:14:44.165450 <6>[ 0.103145] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10416 18:14:44.171923 <6>[ 0.103162] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10417 18:14:44.179140 <6>[ 0.103456] Detected PIPT I-cache on CPU7
10418 18:14:44.185901 <6>[ 0.103520] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10419 18:14:44.192367 <6>[ 0.103536] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10420 18:14:44.195759 <6>[ 0.103583] smp: Brought up 1 node, 8 CPUs
10421 18:14:44.201759 <6>[ 0.244961] SMP: Total of 8 processors activated.
10422 18:14:44.205530 <6>[ 0.249882] CPU features: detected: 32-bit EL0 Support
10423 18:14:44.215535 <6>[ 0.255279] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10424 18:14:44.221871 <6>[ 0.264079] CPU features: detected: Common not Private translations
10425 18:14:44.225523 <6>[ 0.270554] CPU features: detected: CRC32 instructions
10426 18:14:44.232018 <6>[ 0.275939] CPU features: detected: RCpc load-acquire (LDAPR)
10427 18:14:44.238477 <6>[ 0.281899] CPU features: detected: LSE atomic instructions
10428 18:14:44.245395 <6>[ 0.287716] CPU features: detected: Privileged Access Never
10429 18:14:44.248293 <6>[ 0.293496] CPU features: detected: RAS Extension Support
10430 18:14:44.258744 <6>[ 0.299105] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10431 18:14:44.261461 <6>[ 0.306323] CPU: All CPU(s) started at EL2
10432 18:14:44.268259 <6>[ 0.310666] alternatives: applying system-wide alternatives
10433 18:14:44.277039 <6>[ 0.321509] devtmpfs: initialized
10434 18:14:44.289436 <6>[ 0.330406] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10435 18:14:44.299530 <6>[ 0.340366] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10436 18:14:44.306098 <6>[ 0.348379] pinctrl core: initialized pinctrl subsystem
10437 18:14:44.309065 <6>[ 0.355075] DMI not present or invalid.
10438 18:14:44.315563 <6>[ 0.359492] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10439 18:14:44.326121 <6>[ 0.366354] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10440 18:14:44.332208 <6>[ 0.373947] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10441 18:14:44.342456 <6>[ 0.382166] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10442 18:14:44.345168 <6>[ 0.390406] audit: initializing netlink subsys (disabled)
10443 18:14:44.355902 <5>[ 0.396100] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10444 18:14:44.362083 <6>[ 0.396823] thermal_sys: Registered thermal governor 'step_wise'
10445 18:14:44.368428 <6>[ 0.404066] thermal_sys: Registered thermal governor 'power_allocator'
10446 18:14:44.372347 <6>[ 0.410321] cpuidle: using governor menu
10447 18:14:44.378696 <6>[ 0.421283] NET: Registered PF_QIPCRTR protocol family
10448 18:14:44.385656 <6>[ 0.426772] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10449 18:14:44.392125 <6>[ 0.433877] ASID allocator initialised with 32768 entries
10450 18:14:44.394904 <6>[ 0.440468] Serial: AMBA PL011 UART driver
10451 18:14:44.405268 <4>[ 0.449339] Trying to register duplicate clock ID: 134
10452 18:14:44.464887 <6>[ 0.512589] KASLR enabled
10453 18:14:44.479539 <6>[ 0.520291] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10454 18:14:44.485781 <6>[ 0.527301] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10455 18:14:44.492724 <6>[ 0.533789] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10456 18:14:44.499722 <6>[ 0.540794] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10457 18:14:44.506007 <6>[ 0.547279] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10458 18:14:44.512316 <6>[ 0.554284] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10459 18:14:44.518990 <6>[ 0.560768] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10460 18:14:44.525952 <6>[ 0.567774] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10461 18:14:44.528964 <6>[ 0.575249] ACPI: Interpreter disabled.
10462 18:14:44.537904 <6>[ 0.581680] iommu: Default domain type: Translated
10463 18:14:44.543980 <6>[ 0.586830] iommu: DMA domain TLB invalidation policy: strict mode
10464 18:14:44.547855 <5>[ 0.593460] SCSI subsystem initialized
10465 18:14:44.553876 <6>[ 0.597713] usbcore: registered new interface driver usbfs
10466 18:14:44.560397 <6>[ 0.603444] usbcore: registered new interface driver hub
10467 18:14:44.563889 <6>[ 0.608994] usbcore: registered new device driver usb
10468 18:14:44.570586 <6>[ 0.615117] pps_core: LinuxPPS API ver. 1 registered
10469 18:14:44.580477 <6>[ 0.620311] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10470 18:14:44.583885 <6>[ 0.629654] PTP clock support registered
10471 18:14:44.587506 <6>[ 0.633895] EDAC MC: Ver: 3.0.0
10472 18:14:44.595036 <6>[ 0.639083] FPGA manager framework
10473 18:14:44.598100 <6>[ 0.642761] Advanced Linux Sound Architecture Driver Initialized.
10474 18:14:44.601818 <6>[ 0.649544] vgaarb: loaded
10475 18:14:44.608213 <6>[ 0.652699] clocksource: Switched to clocksource arch_sys_counter
10476 18:14:44.614833 <5>[ 0.659144] VFS: Disk quotas dquot_6.6.0
10477 18:14:44.621996 <6>[ 0.663331] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10478 18:14:44.625527 <6>[ 0.670524] pnp: PnP ACPI: disabled
10479 18:14:44.633006 <6>[ 0.677236] NET: Registered PF_INET protocol family
10480 18:14:44.643051 <6>[ 0.682827] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10481 18:14:44.654417 <6>[ 0.695152] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10482 18:14:44.664132 <6>[ 0.703966] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10483 18:14:44.670928 <6>[ 0.711936] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10484 18:14:44.677556 <6>[ 0.720636] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10485 18:14:44.689502 <6>[ 0.730388] TCP: Hash tables configured (established 65536 bind 65536)
10486 18:14:44.696413 <6>[ 0.737258] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 18:14:44.703167 <6>[ 0.744458] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10488 18:14:44.709426 <6>[ 0.752168] NET: Registered PF_UNIX/PF_LOCAL protocol family
10489 18:14:44.715909 <6>[ 0.758311] RPC: Registered named UNIX socket transport module.
10490 18:14:44.719655 <6>[ 0.764465] RPC: Registered udp transport module.
10491 18:14:44.726145 <6>[ 0.769396] RPC: Registered tcp transport module.
10492 18:14:44.732310 <6>[ 0.774325] RPC: Registered tcp NFSv4.1 backchannel transport module.
10493 18:14:44.736096 <6>[ 0.780992] PCI: CLS 0 bytes, default 64
10494 18:14:44.738918 <6>[ 0.785354] Unpacking initramfs...
10495 18:14:44.749220 <6>[ 0.789073] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10496 18:14:44.756077 <6>[ 0.797694] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10497 18:14:44.762164 <6>[ 0.806485] kvm [1]: IPA Size Limit: 40 bits
10498 18:14:44.765759 <6>[ 0.811004] kvm [1]: GICv3: no GICV resource entry
10499 18:14:44.772245 <6>[ 0.816026] kvm [1]: disabling GICv2 emulation
10500 18:14:44.778620 <6>[ 0.820711] kvm [1]: GIC system register CPU interface enabled
10501 18:14:44.782172 <6>[ 0.826876] kvm [1]: vgic interrupt IRQ18
10502 18:14:44.788922 <6>[ 0.832763] kvm [1]: VHE mode initialized successfully
10503 18:14:44.796023 <5>[ 0.839180] Initialise system trusted keyrings
10504 18:14:44.802557 <6>[ 0.843975] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10505 18:14:44.809504 <6>[ 0.853987] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10506 18:14:44.816250 <5>[ 0.860360] NFS: Registering the id_resolver key type
10507 18:14:44.819877 <5>[ 0.865660] Key type id_resolver registered
10508 18:14:44.826507 <5>[ 0.870074] Key type id_legacy registered
10509 18:14:44.833385 <6>[ 0.874356] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10510 18:14:44.839625 <6>[ 0.881276] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10511 18:14:44.846314 <6>[ 0.888986] 9p: Installing v9fs 9p2000 file system support
10512 18:14:44.882031 <5>[ 0.926386] Key type asymmetric registered
10513 18:14:44.885850 <5>[ 0.930715] Asymmetric key parser 'x509' registered
10514 18:14:44.895273 <6>[ 0.935850] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10515 18:14:44.898806 <6>[ 0.943462] io scheduler mq-deadline registered
10516 18:14:44.901681 <6>[ 0.948224] io scheduler kyber registered
10517 18:14:44.920677 <6>[ 0.965190] EINJ: ACPI disabled.
10518 18:14:44.954219 <4>[ 0.991750] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 18:14:44.964134 <4>[ 1.002364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10520 18:14:44.978874 <6>[ 1.023317] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10521 18:14:44.987409 <6>[ 1.031229] printk: console [ttyS0] disabled
10522 18:14:45.014989 <6>[ 1.055858] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10523 18:14:45.021583 <6>[ 1.065331] printk: console [ttyS0] enabled
10524 18:14:45.024757 <6>[ 1.065331] printk: console [ttyS0] enabled
10525 18:14:45.031617 <6>[ 1.074225] printk: bootconsole [mtk8250] disabled
10526 18:14:45.034816 <6>[ 1.074225] printk: bootconsole [mtk8250] disabled
10527 18:14:45.041677 <6>[ 1.085240] SuperH (H)SCI(F) driver initialized
10528 18:14:45.044600 <6>[ 1.090496] msm_serial: driver initialized
10529 18:14:45.058636 <6>[ 1.099384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10530 18:14:45.068764 <6>[ 1.107929] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10531 18:14:45.074735 <6>[ 1.116474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10532 18:14:45.084640 <6>[ 1.125102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10533 18:14:45.092110 <6>[ 1.133808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10534 18:14:45.101641 <6>[ 1.142527] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10535 18:14:45.111472 <6>[ 1.151068] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10536 18:14:45.118444 <6>[ 1.159866] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10537 18:14:45.127729 <6>[ 1.168407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10538 18:14:45.139344 <6>[ 1.183831] loop: module loaded
10539 18:14:45.146017 <6>[ 1.189804] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10540 18:14:45.168597 <4>[ 1.213138] mtk-pmic-keys: Failed to locate of_node [id: -1]
10541 18:14:45.175619 <6>[ 1.219930] megasas: 07.719.03.00-rc1
10542 18:14:45.184870 <6>[ 1.229652] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10543 18:14:45.196161 <6>[ 1.240070] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10544 18:14:45.211473 <6>[ 1.255942] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10545 18:14:45.267220 <6>[ 1.305075] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10546 18:14:45.533190 <6>[ 1.577384] Freeing initrd memory: 18292K
10547 18:14:45.545025 <6>[ 1.589051] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10548 18:14:45.555072 <6>[ 1.599862] tun: Universal TUN/TAP device driver, 1.6
10549 18:14:45.558523 <6>[ 1.605938] thunder_xcv, ver 1.0
10550 18:14:45.561959 <6>[ 1.609442] thunder_bgx, ver 1.0
10551 18:14:45.565079 <6>[ 1.612940] nicpf, ver 1.0
10552 18:14:45.575946 <6>[ 1.616972] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10553 18:14:45.579792 <6>[ 1.624448] hns3: Copyright (c) 2017 Huawei Corporation.
10554 18:14:45.582896 <6>[ 1.630036] hclge is initializing
10555 18:14:45.589539 <6>[ 1.633612] e1000: Intel(R) PRO/1000 Network Driver
10556 18:14:45.596022 <6>[ 1.638741] e1000: Copyright (c) 1999-2006 Intel Corporation.
10557 18:14:45.599064 <6>[ 1.644753] e1000e: Intel(R) PRO/1000 Network Driver
10558 18:14:45.605609 <6>[ 1.649968] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10559 18:14:45.612309 <6>[ 1.656155] igb: Intel(R) Gigabit Ethernet Network Driver
10560 18:14:45.619446 <6>[ 1.661805] igb: Copyright (c) 2007-2014 Intel Corporation.
10561 18:14:45.625626 <6>[ 1.667641] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10562 18:14:45.632267 <6>[ 1.674159] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10563 18:14:45.635913 <6>[ 1.680619] sky2: driver version 1.30
10564 18:14:45.642658 <6>[ 1.685562] usbcore: registered new device driver r8152-cfgselector
10565 18:14:45.648903 <6>[ 1.692097] usbcore: registered new interface driver r8152
10566 18:14:45.652712 <6>[ 1.697920] VFIO - User Level meta-driver version: 0.3
10567 18:14:45.661691 <6>[ 1.706161] usbcore: registered new interface driver usb-storage
10568 18:14:45.668819 <6>[ 1.712606] usbcore: registered new device driver onboard-usb-hub
10569 18:14:45.677579 <6>[ 1.721811] mt6397-rtc mt6359-rtc: registered as rtc0
10570 18:14:45.687082 <6>[ 1.727279] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:10:02 UTC (1718129402)
10571 18:14:45.690759 <6>[ 1.736855] i2c_dev: i2c /dev entries driver
10572 18:14:45.704759 <4>[ 1.748978] cpu cpu0: supply cpu not found, using dummy regulator
10573 18:14:45.711566 <4>[ 1.755416] cpu cpu1: supply cpu not found, using dummy regulator
10574 18:14:45.718332 <4>[ 1.761824] cpu cpu2: supply cpu not found, using dummy regulator
10575 18:14:45.724459 <4>[ 1.768234] cpu cpu3: supply cpu not found, using dummy regulator
10576 18:14:45.731438 <4>[ 1.774634] cpu cpu4: supply cpu not found, using dummy regulator
10577 18:14:45.738076 <4>[ 1.781034] cpu cpu5: supply cpu not found, using dummy regulator
10578 18:14:45.744998 <4>[ 1.787444] cpu cpu6: supply cpu not found, using dummy regulator
10579 18:14:45.751137 <4>[ 1.793843] cpu cpu7: supply cpu not found, using dummy regulator
10580 18:14:45.770206 <6>[ 1.814472] cpu cpu0: EM: created perf domain
10581 18:14:45.773197 <6>[ 1.819384] cpu cpu4: EM: created perf domain
10582 18:14:45.780743 <6>[ 1.824990] sdhci: Secure Digital Host Controller Interface driver
10583 18:14:45.787057 <6>[ 1.831418] sdhci: Copyright(c) Pierre Ossman
10584 18:14:45.793891 <6>[ 1.836376] Synopsys Designware Multimedia Card Interface Driver
10585 18:14:45.800480 <6>[ 1.843012] sdhci-pltfm: SDHCI platform and OF driver helper
10586 18:14:45.803895 <6>[ 1.843171] mmc0: CQHCI version 5.10
10587 18:14:45.810815 <6>[ 1.852973] ledtrig-cpu: registered to indicate activity on CPUs
10588 18:14:45.817471 <6>[ 1.859877] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10589 18:14:45.824508 <6>[ 1.866904] usbcore: registered new interface driver usbhid
10590 18:14:45.827273 <6>[ 1.872727] usbhid: USB HID core driver
10591 18:14:45.833845 <6>[ 1.876931] spi_master spi0: will run message pump with realtime priority
10592 18:14:45.877081 <6>[ 1.914625] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10593 18:14:45.896016 <6>[ 1.930452] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10594 18:14:45.902913 <6>[ 1.946357] cros-ec-spi spi0.0: Chrome EC device registered
10595 18:14:45.909219 <6>[ 1.946432] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10596 18:14:45.917666 <6>[ 1.962321] mmc0: Command Queue Engine enabled
10597 18:14:45.924706 <6>[ 1.967042] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10598 18:14:45.931552 <6>[ 1.974471] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 18:14:45.938066 <6>[ 1.982495] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 18:14:45.948229 <6>[ 1.987599] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10601 18:14:45.954605 <6>[ 1.989786] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10602 18:14:45.957898 <6>[ 1.998946] NET: Registered PF_PACKET protocol family
10603 18:14:45.964841 <6>[ 2.003613] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10604 18:14:45.967975 <6>[ 2.008323] 9pnet: Installing 9P2000 support
10605 18:14:45.974889 <6>[ 2.014110] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10606 18:14:45.977870 <5>[ 2.017996] Key type dns_resolver registered
10607 18:14:45.985389 <6>[ 2.029480] registered taskstats version 1
10608 18:14:45.988456 <5>[ 2.033856] Loading compiled-in X.509 certificates
10609 18:14:46.017632 <4>[ 2.055260] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 18:14:46.027684 <4>[ 2.065980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 18:14:46.041321 <6>[ 2.085973] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10612 18:14:46.048631 <6>[ 2.092716] xhci-mtk 11200000.usb: xHCI Host Controller
10613 18:14:46.055165 <6>[ 2.098228] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10614 18:14:46.065141 <6>[ 2.106097] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10615 18:14:46.071624 <6>[ 2.115541] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10616 18:14:46.078485 <6>[ 2.121633] xhci-mtk 11200000.usb: xHCI Host Controller
10617 18:14:46.084774 <6>[ 2.127118] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10618 18:14:46.091592 <6>[ 2.134869] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10619 18:14:46.098415 <6>[ 2.142903] hub 1-0:1.0: USB hub found
10620 18:14:46.101522 <6>[ 2.146932] hub 1-0:1.0: 1 port detected
10621 18:14:46.111603 <6>[ 2.151239] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10622 18:14:46.115527 <6>[ 2.160066] hub 2-0:1.0: USB hub found
10623 18:14:46.118383 <6>[ 2.164086] hub 2-0:1.0: 1 port detected
10624 18:14:46.126874 <6>[ 2.171680] mtk-msdc 11f70000.mmc: Got CD GPIO
10625 18:14:46.141928 <6>[ 2.182616] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10626 18:14:46.151126 <6>[ 2.191136] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10627 18:14:46.157964 <6>[ 2.199481] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10628 18:14:46.168190 <6>[ 2.207832] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10629 18:14:46.175044 <6>[ 2.216171] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10630 18:14:46.185269 <6>[ 2.224522] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10631 18:14:46.191675 <6>[ 2.232861] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10632 18:14:46.201286 <6>[ 2.241211] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10633 18:14:46.207794 <6>[ 2.249551] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10634 18:14:46.218292 <6>[ 2.257899] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10635 18:14:46.225167 <6>[ 2.266236] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10636 18:14:46.235042 <6>[ 2.274585] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10637 18:14:46.241512 <6>[ 2.282923] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10638 18:14:46.251739 <6>[ 2.291272] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10639 18:14:46.258164 <6>[ 2.299610] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10640 18:14:46.264481 <6>[ 2.308350] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10641 18:14:46.271126 <6>[ 2.315558] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10642 18:14:46.278082 <6>[ 2.322386] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10643 18:14:46.287926 <6>[ 2.329164] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10644 18:14:46.294714 <6>[ 2.336104] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10645 18:14:46.301338 <6>[ 2.342975] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10646 18:14:46.311250 <6>[ 2.352106] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10647 18:14:46.321215 <6>[ 2.361226] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10648 18:14:46.331642 <6>[ 2.370520] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10649 18:14:46.341338 <6>[ 2.379986] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10650 18:14:46.347467 <6>[ 2.389453] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10651 18:14:46.357640 <6>[ 2.398573] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10652 18:14:46.367341 <6>[ 2.408039] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10653 18:14:46.377875 <6>[ 2.417159] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10654 18:14:46.387547 <6>[ 2.426452] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10655 18:14:46.397417 <6>[ 2.436614] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10656 18:14:46.406948 <6>[ 2.448129] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10657 18:14:46.415134 <6>[ 2.459342] Trying to probe devices needed for running init ...
10658 18:14:46.425394 <3>[ 2.466603] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10659 18:14:46.508042 <6>[ 2.549261] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10660 18:14:46.536616 <6>[ 2.581120] hub 2-1:1.0: USB hub found
10661 18:14:46.540191 <6>[ 2.585638] hub 2-1:1.0: 3 ports detected
10662 18:14:46.550838 <6>[ 2.595312] hub 2-1:1.0: USB hub found
10663 18:14:46.554101 <6>[ 2.599716] hub 2-1:1.0: 3 ports detected
10664 18:14:46.660230 <6>[ 2.700981] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 18:14:46.814591 <6>[ 2.858871] hub 1-1:1.0: USB hub found
10666 18:14:46.818210 <6>[ 2.863343] hub 1-1:1.0: 4 ports detected
10667 18:14:46.830144 <6>[ 2.874181] hub 1-1:1.0: USB hub found
10668 18:14:46.833538 <6>[ 2.878763] hub 1-1:1.0: 4 ports detected
10669 18:14:46.900729 <6>[ 2.941225] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10670 18:14:47.008709 <6>[ 3.049664] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10671 18:14:47.044576 <4>[ 3.085751] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10672 18:14:47.054260 <4>[ 3.094827] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10673 18:14:47.097458 <6>[ 3.142284] r8152 2-1.3:1.0 eth0: v1.12.13
10674 18:14:47.155785 <6>[ 3.197016] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10675 18:14:47.289142 <6>[ 3.333170] hub 1-1.4:1.0: USB hub found
10676 18:14:47.292545 <6>[ 3.337857] hub 1-1.4:1.0: 2 ports detected
10677 18:14:47.305366 <6>[ 3.349689] hub 1-1.4:1.0: USB hub found
10678 18:14:47.308533 <6>[ 3.354284] hub 1-1.4:1.0: 2 ports detected
10679 18:14:47.603944 <6>[ 3.644863] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10680 18:14:47.800204 <6>[ 3.841026] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10681 18:14:48.775111 <6>[ 4.819396] r8152 2-1.3:1.0 eth0: carrier on
10682 18:14:51.243784 <5>[ 4.848835] Sending DHCP requests .., OK
10683 18:14:51.250729 <6>[ 7.293094] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10684 18:14:51.253733 <6>[ 7.301388] IP-Config: Complete:
10685 18:14:51.267380 <6>[ 7.304883] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10686 18:14:51.273450 <6>[ 7.315600] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10687 18:14:51.280188 <6>[ 7.324220] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10688 18:14:51.286798 <6>[ 7.324231] nameserver0=192.168.201.1
10689 18:14:51.290142 <6>[ 7.336394] clk: Disabling unused clocks
10690 18:14:51.293670 <6>[ 7.342001] ALSA device list:
10691 18:14:51.300462 <6>[ 7.345283] No soundcards found.
10692 18:14:51.307931 <6>[ 7.353078] Freeing unused kernel memory: 8512K
10693 18:14:51.311721 <6>[ 7.357995] Run /init as init process
10694 18:14:51.320580 Loading, please wait...
10695 18:14:51.350913 Starting systemd-udevd version 252.22-1~deb12u1
10696 18:14:51.662265 <6>[ 7.703728] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10697 18:14:51.669251 <6>[ 7.703740] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10698 18:14:51.678775 <6>[ 7.703778] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10699 18:14:51.691832 <6>[ 7.733772] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10700 18:14:51.701968 <6>[ 7.733947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10701 18:14:51.708561 <6>[ 7.734600] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 18:14:51.715285 <3>[ 7.734963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 18:14:51.725710 <3>[ 7.734991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 18:14:51.731633 <3>[ 7.734999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 18:14:51.741655 <3>[ 7.735099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 18:14:51.748876 <3>[ 7.735109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 18:14:51.755060 <3>[ 7.735116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 18:14:51.765255 <3>[ 7.735129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 18:14:51.772282 <3>[ 7.735136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 18:14:51.782481 <3>[ 7.735181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 18:14:51.788499 <3>[ 7.735244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10712 18:14:51.798894 <3>[ 7.735252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 18:14:51.805386 <3>[ 7.735259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 18:14:51.812925 <3>[ 7.735315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 18:14:51.822389 <3>[ 7.735323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 18:14:51.829806 <3>[ 7.735332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 18:14:51.836556 <3>[ 7.735340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 18:14:51.846165 <3>[ 7.735346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 18:14:51.853254 <3>[ 7.735429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 18:14:51.859505 <6>[ 7.738843] remoteproc remoteproc0: scp is available
10721 18:14:51.863228 <6>[ 7.738934] remoteproc remoteproc0: powering up scp
10722 18:14:51.873250 <6>[ 7.738940] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10723 18:14:51.879957 <6>[ 7.738955] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10724 18:14:51.886217 <4>[ 7.751810] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10725 18:14:51.892760 <6>[ 7.757912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10726 18:14:51.902587 <4>[ 7.758291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10727 18:14:51.909188 <4>[ 7.766439] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10728 18:14:51.919314 <6>[ 7.775145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10729 18:14:51.922233 <6>[ 7.778843] mc: Linux media interface: v0.10
10730 18:14:51.928994 <6>[ 7.800028] videodev: Linux video capture interface: v2.00
10731 18:14:51.935974 <6>[ 7.807590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10732 18:14:51.946134 <6>[ 7.812424] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10733 18:14:51.952724 <4>[ 7.835887] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10734 18:14:51.959159 <4>[ 7.835887] Fallback method does not support PEC.
10735 18:14:51.965541 <6>[ 7.839905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10736 18:14:51.972466 <6>[ 7.862115] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10737 18:14:51.978626 <6>[ 7.863972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10738 18:14:51.988763 <3>[ 7.864682] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10739 18:14:51.998778 <6>[ 7.865648] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10740 18:14:52.005544 <6>[ 7.865656] remoteproc remoteproc0: remote processor scp is now up
10741 18:14:52.012296 <6>[ 7.865657] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10742 18:14:52.015267 <6>[ 7.872050] pci_bus 0000:00: root bus resource [bus 00-ff]
10743 18:14:52.025584 <6>[ 7.873406] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10744 18:14:52.031773 <6>[ 7.875881] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10745 18:14:52.041554 <6>[ 7.880129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10746 18:14:52.048203 <3>[ 7.885659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10747 18:14:52.058504 <6>[ 7.888200] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10748 18:14:52.068539 <6>[ 7.888615] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10749 18:14:52.074767 <6>[ 7.889037] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10750 18:14:52.085226 <6>[ 7.895307] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10751 18:14:52.094726 <6>[ 7.896585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10752 18:14:52.104655 <6>[ 7.904358] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10753 18:14:52.111275 <6>[ 7.904414] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10754 18:14:52.115082 <6>[ 7.936642] Bluetooth: Core ver 2.22
10755 18:14:52.121092 <6>[ 7.943995] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10756 18:14:52.127594 <6>[ 7.953137] NET: Registered PF_BLUETOOTH protocol family
10757 18:14:52.134384 <6>[ 7.954359] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10758 18:14:52.147592 <6>[ 7.955468] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10759 18:14:52.154715 <6>[ 7.955591] usbcore: registered new interface driver uvcvideo
10760 18:14:52.157723 <6>[ 7.960641] pci 0000:00:00.0: supports D1 D2
10761 18:14:52.164196 <6>[ 7.968483] Bluetooth: HCI device and connection manager initialized
10762 18:14:52.167822 <6>[ 7.968500] Bluetooth: HCI socket layer initialized
10763 18:14:52.177907 <6>[ 7.973004] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 18:14:52.180863 <6>[ 7.978741] Bluetooth: L2CAP socket layer initialized
10765 18:14:52.190629 <6>[ 7.987619] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10766 18:14:52.194456 <6>[ 7.994300] Bluetooth: SCO socket layer initialized
10767 18:14:52.200306 <6>[ 7.994744] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10768 18:14:52.206938 <6>[ 8.008020] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10769 18:14:52.213642 <6>[ 8.061840] usbcore: registered new interface driver btusb
10770 18:14:52.223504 <4>[ 8.062939] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10771 18:14:52.230189 <3>[ 8.062955] Bluetooth: hci0: Failed to load firmware file (-2)
10772 18:14:52.236828 <3>[ 8.062962] Bluetooth: hci0: Failed to set up firmware (-2)
10773 18:14:52.246815 <4>[ 8.062969] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10774 18:14:52.253596 <6>[ 8.067019] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10775 18:14:52.260216 <6>[ 8.303723] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10776 18:14:52.270101 <6>[ 8.311209] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10777 18:14:52.273972 <6>[ 8.318785] pci 0000:01:00.0: supports D1 D2
10778 18:14:52.279662 <6>[ 8.323304] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10779 18:14:52.303105 <6>[ 8.344908] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10780 18:14:52.309499 <6>[ 8.351826] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10781 18:14:52.316859 <6>[ 8.359906] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10782 18:14:52.326171 <6>[ 8.367906] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10783 18:14:52.332982 <6>[ 8.375907] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10784 18:14:52.342630 <6>[ 8.383908] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10785 18:14:52.346420 <6>[ 8.391909] pci 0000:00:00.0: PCI bridge to [bus 01]
10786 18:14:52.356321 <6>[ 8.397125] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10787 18:14:52.362976 <6>[ 8.405250] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10788 18:14:52.369060 <6>[ 8.412079] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10789 18:14:52.375498 <6>[ 8.418885] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10790 18:14:52.391052 <5>[ 8.433103] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10791 18:14:52.417444 <5>[ 8.459256] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10792 18:14:52.424200 <5>[ 8.466676] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10793 18:14:52.433865 <4>[ 8.475116] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10794 18:14:52.437750 <6>[ 8.484005] cfg80211: failed to load regulatory.db
10795 18:14:52.488998 <6>[ 8.530827] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10796 18:14:52.495691 <6>[ 8.538354] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10797 18:14:52.519764 <6>[ 8.565098] mt7921e 0000:01:00.0: ASIC revision: 79610010
10798 18:14:52.623671 <6>[ 8.665578] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10799 18:14:52.627269 <6>[ 8.665578]
10800 18:14:52.656552 Begin: Loading essential drivers ... done.
10801 18:14:52.659951 Begin: Running /scripts/init-premount ... done.
10802 18:14:52.667075 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10803 18:14:52.676821 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10804 18:14:52.679905 Device /sys/class/net/eth0 found
10805 18:14:52.679987 done.
10806 18:14:52.711687 Begin: Waiting up to 180 secs for any network device to become available ... done.
10807 18:14:52.771514 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10808 18:14:52.778979 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10809 18:14:52.785461 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10810 18:14:52.792285 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10811 18:14:52.799012 host : mt8192-asurada-spherion-r0-cbg-0
10812 18:14:52.805583 domain : lava-rack
10813 18:14:52.808536 rootserver: 192.168.201.1 rootpath:
10814 18:14:52.811741 filename :
10815 18:14:52.894399 <6>[ 8.936084] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10816 18:14:53.000766 done.
10817 18:14:53.004490 Begin: Running /scripts/nfs-bottom ... done.
10818 18:14:53.026243 Begin: Running /scripts/init-bottom ... done.
10819 18:14:54.332482 <6>[ 10.377996] NET: Registered PF_INET6 protocol family
10820 18:14:54.340219 <6>[ 10.385678] Segment Routing with IPv6
10821 18:14:54.343756 <6>[ 10.389671] In-situ OAM (IOAM) with IPv6
10822 18:14:54.513133 <30>[ 10.531990] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10823 18:14:54.519831 <30>[ 10.565132] systemd[1]: Detected architecture arm64.
10824 18:14:54.527541
10825 18:14:54.530320 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10826 18:14:54.530419
10827 18:14:54.557053 <30>[ 10.602623] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10828 18:14:55.641627 <30>[ 11.683439] systemd[1]: Queued start job for default target graphical.target.
10829 18:14:55.685658 <30>[ 11.727052] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10830 18:14:55.691733 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10831 18:14:55.712951 <30>[ 11.755022] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10832 18:14:55.723620 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10833 18:14:55.741457 <30>[ 11.783007] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10834 18:14:55.750862 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10835 18:14:55.769234 <30>[ 11.810577] systemd[1]: Created slice user.slice - User and Session Slice.
10836 18:14:55.775441 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10837 18:14:55.799821 <30>[ 11.837940] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10838 18:14:55.809510 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10839 18:14:55.831171 <30>[ 11.869901] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10840 18:14:55.837596 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10841 18:14:55.865145 <30>[ 11.897237] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10842 18:14:55.875013 <30>[ 11.917131] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10843 18:14:55.881682 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10844 18:14:55.899869 <30>[ 11.941439] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10845 18:14:55.909030 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10846 18:14:55.927169 <30>[ 11.969171] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10847 18:14:55.936728 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10848 18:14:55.952290 <30>[ 11.997597] systemd[1]: Reached target paths.target - Path Units.
10849 18:14:55.962569 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10850 18:14:55.979732 <30>[ 12.021463] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10851 18:14:55.986263 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10852 18:14:56.000115 <30>[ 12.045015] systemd[1]: Reached target slices.target - Slice Units.
10853 18:14:56.010051 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10854 18:14:56.024132 <30>[ 12.069525] systemd[1]: Reached target swap.target - Swaps.
10855 18:14:56.031107 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10856 18:14:56.051599 <30>[ 12.093534] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10857 18:14:56.061416 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10858 18:14:56.079320 <30>[ 12.121227] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10859 18:14:56.089103 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10860 18:14:56.110363 <30>[ 12.152413] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10861 18:14:56.120300 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10862 18:14:56.136780 <30>[ 12.178474] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10863 18:14:56.146405 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10864 18:14:56.163679 <30>[ 12.205740] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10865 18:14:56.170545 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10866 18:14:56.188262 <30>[ 12.230496] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10867 18:14:56.198298 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10868 18:14:56.217904 <30>[ 12.259631] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10869 18:14:56.227520 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10870 18:14:56.244024 <30>[ 12.285619] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10871 18:14:56.253597 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10872 18:14:56.307204 <30>[ 12.349216] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10873 18:14:56.313724 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10874 18:14:56.336553 <30>[ 12.378268] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10875 18:14:56.342716 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10876 18:14:56.368375 <30>[ 12.410426] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10877 18:14:56.374594 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10878 18:14:56.402502 <30>[ 12.437676] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10879 18:14:56.417626 <30>[ 12.459817] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10880 18:14:56.427341 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10881 18:14:56.449041 <30>[ 12.491354] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10882 18:14:56.455541 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10883 18:14:56.481424 <30>[ 12.523271] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10884 18:14:56.487933 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10885 18:14:56.511651 <30>[ 12.553424] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10886 18:14:56.521483 Starting [0;1;39mmodpr<6>[ 12.564100] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10887 18:14:56.527839 obe@drm.service[0m - Load Kernel Module drm...
10888 18:14:56.556680 <30>[ 12.599071] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10889 18:14:56.566805 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10890 18:14:56.589350 <30>[ 12.631315] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10891 18:14:56.595938 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10892 18:14:56.621057 <30>[ 12.662903] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10893 18:14:56.631185 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 12.675395] fuse: init (API version 7.37)
10894 18:14:56.633664 [0m - Load Kernel Module loop...
10895 18:14:56.661376 <30>[ 12.703827] systemd[1]: Starting systemd-journald.service - Journal Service...
10896 18:14:56.668190 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10897 18:14:56.692709 <30>[ 12.734690] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10898 18:14:56.699528 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10899 18:14:56.728230 <30>[ 12.766834] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10900 18:14:56.734891 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10901 18:14:56.765088 <30>[ 12.807283] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10902 18:14:56.775043 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10903 18:14:56.796035 <30>[ 12.837969] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10904 18:14:56.802129 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10905 18:14:56.825665 <3>[ 12.867874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 18:14:56.832050 <30>[ 12.870232] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10907 18:14:56.842372 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10908 18:14:56.857440 <3>[ 12.899789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 18:14:56.867680 <30>[ 12.909661] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10910 18:14:56.874480 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10911 18:14:56.895433 <30>[ 12.937261] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10912 18:14:56.902221 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10913 18:14:56.912272 <3>[ 12.952939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 18:14:56.922153 <30>[ 12.963793] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10915 18:14:56.929080 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10916 18:14:56.943161 <3>[ 12.985405] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 18:14:56.954062 <30>[ 12.996390] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10918 18:14:56.964368 <30>[ 13.005098] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10919 18:14:56.974776 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 13.017271] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 18:14:56.981693 onfigfs…[0m - Load Kernel Module configfs.
10921 18:14:56.998107 <30>[ 13.042734] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10922 18:14:57.008168 <3>[ 13.050037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 18:14:57.017857 <30>[ 13.050622] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10924 18:14:57.024844 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10925 18:14:57.039448 <3>[ 13.080834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 18:14:57.049829 <30>[ 13.091422] systemd[1]: modprobe@drm.service: Deactivated successfully.
10927 18:14:57.056289 <30>[ 13.099187] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10928 18:14:57.069801 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 13.111096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 18:14:57.073245 rm.service[0m - Load Kernel Module drm.
10930 18:14:57.093616 <30>[ 13.134811] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10931 18:14:57.100176 <30>[ 13.142925] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10932 18:14:57.110300 <3>[ 13.149483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 18:14:57.119758 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10934 18:14:57.137358 <30>[ 13.178797] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10935 18:14:57.143271 <3>[ 13.180976] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 18:14:57.153674 <30>[ 13.186684] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10937 18:14:57.160286 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10938 18:14:57.180455 <30>[ 13.222298] systemd[1]: modprobe@loop.service: Deactivated successfully.
10939 18:14:57.187262 <30>[ 13.230243] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10940 18:14:57.196935 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10941 18:14:57.216223 <30>[ 13.258129] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10942 18:14:57.232762 <4>[ 13.259976] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10943 18:14:57.239401 <3>[ 13.281867] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10944 18:14:57.245918 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10945 18:14:57.268050 <30>[ 13.309945] systemd[1]: Started systemd-journald.service - Journal Service.
10946 18:14:57.274493 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10947 18:14:57.295878 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10948 18:14:57.316913 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10949 18:14:57.336837 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10950 18:14:57.358164 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10951 18:14:57.416225 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10952 18:14:57.437311 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10953 18:14:57.464982 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10954 18:14:57.493122 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10955 18:14:57.523830 <46>[ 13.565841] systemd-journald[301]: Received client request to flush runtime journal.
10956 18:14:57.530221 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10957 18:14:57.562238 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10958 18:14:57.854798 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10959 18:14:57.875495 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10960 18:14:57.894954 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10961 18:14:58.303434 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10962 18:14:58.658648 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10963 18:14:58.711672 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10964 18:14:58.966265 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10965 18:14:59.065930 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10966 18:14:59.083009 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10967 18:14:59.098992 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10968 18:14:59.147839 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10969 18:14:59.175358 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10970 18:14:59.397617 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10971 18:14:59.444620 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10972 18:14:59.547790 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10973 18:14:59.758338 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10974 18:14:59.815966 <6>[ 15.861494] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10975 18:14:59.827833 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10976 18:14:59.856222 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10977 18:14:59.974008 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10978 18:14:59.991896 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10979 18:15:00.042956 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10980 18:15:00.063560 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10981 18:15:00.120454 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10982 18:15:00.140127 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10983 18:15:00.164874 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10984 18:15:00.188080 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10985 18:15:00.211682 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10986 18:15:00.240796 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10987 18:15:00.259844 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10988 18:15:00.278852 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10989 18:15:00.303562 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10990 18:15:00.321767 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10991 18:15:00.339233 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10992 18:15:00.358870 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10993 18:15:00.379237 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10994 18:15:00.394763 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10995 18:15:00.412823 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10996 18:15:00.430734 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10997 18:15:00.447335 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10998 18:15:00.500152 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10999 18:15:00.535404 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11000 18:15:00.596202 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11001 18:15:00.625133 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11002 18:15:00.655714 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11003 18:15:00.707150 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11004 18:15:00.774303 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11005 18:15:00.811203 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11006 18:15:00.828039 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11007 18:15:00.843865 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11008 18:15:00.864159 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11009 18:15:00.909869 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11010 18:15:01.013615 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11011 18:15:01.033997 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11012 18:15:01.054228 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11013 18:15:01.100575 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11014 18:15:01.166066 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11015 18:15:01.256997
11016 18:15:01.259913 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11017 18:15:01.260117
11018 18:15:01.264011 debian-bookworm-arm64 login: root (automatic login)
11019 18:15:01.264210
11020 18:15:01.543188 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11021 18:15:01.543633
11022 18:15:01.550227 The programs included with the Debian GNU/Linux system are free software;
11023 18:15:01.556809 the exact distribution terms for each program are described in the
11024 18:15:01.559712 individual files in /usr/share/doc/*/copyright.
11025 18:15:01.560098
11026 18:15:01.566347 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11027 18:15:01.569812 permitted by applicable law.
11028 18:15:02.606702 Matched prompt #10: / #
11030 18:15:02.607527 Setting prompt string to ['/ #']
11031 18:15:02.607873 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11033 18:15:02.608606 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11034 18:15:02.608922 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11035 18:15:02.609234 Setting prompt string to ['/ #']
11036 18:15:02.609571 Forcing a shell prompt, looking for ['/ #']
11038 18:15:02.660425 / #
11039 18:15:02.660845 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11040 18:15:02.661110 Waiting using forced prompt support (timeout 00:02:30)
11041 18:15:02.666352
11042 18:15:02.666940 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11043 18:15:02.667271 start: 2.2.7 export-device-env (timeout 00:03:42) [common]
11045 18:15:02.768155 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg'
11046 18:15:02.774660 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291475/extract-nfsrootfs-80k5o2fg'
11048 18:15:02.876280 / # export NFS_SERVER_IP='192.168.201.1'
11049 18:15:02.881431 export NFS_SERVER_IP='192.168.201.1'
11050 18:15:02.881781 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11051 18:15:02.881932 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11052 18:15:02.882074 end: 2 depthcharge-action (duration 00:01:18) [common]
11053 18:15:02.882204 start: 3 lava-test-retry (timeout 00:08:01) [common]
11054 18:15:02.882330 start: 3.1 lava-test-shell (timeout 00:08:01) [common]
11055 18:15:02.882443 Using namespace: common
11057 18:15:02.982971 / # #
11058 18:15:02.983538 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11059 18:15:02.989067 #
11060 18:15:02.989764 Using /lava-14291475
11062 18:15:03.090827 / # export SHELL=/bin/bash
11063 18:15:03.097194 export SHELL=/bin/bash
11065 18:15:03.198539 / # . /lava-14291475/environment
11066 18:15:03.204508 . /lava-14291475/environment
11068 18:15:03.349284 / # /lava-14291475/bin/lava-test-runner /lava-14291475/0
11069 18:15:03.350030 Test shell timeout: 10s (minimum of the action and connection timeout)
11070 18:15:03.355848 /lava-14291475/bin/lava-test-runner /lava-14291475/0
11071 18:15:03.601199 + export TESTRUN_ID=0_timesync-off
11072 18:15:03.604611 + TESTRUN_ID=0_timesync-off
11073 18:15:03.607443 + cd /lava-14291475/0/tests/0_timesync-off
11074 18:15:03.610966 ++ cat uuid
11075 18:15:03.611125 + UUID=14291475_1.6.2.3.1
11076 18:15:03.614413 + set +x
11077 18:15:03.617126 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291475_1.6.2.3.1>
11078 18:15:03.617439 Received signal: <STARTRUN> 0_timesync-off 14291475_1.6.2.3.1
11079 18:15:03.617557 Starting test lava.0_timesync-off (14291475_1.6.2.3.1)
11080 18:15:03.617698 Skipping test definition patterns.
11081 18:15:03.621089 + systemctl stop systemd-timesyncd
11082 18:15:03.680549 + set +x
11083 18:15:03.683921 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291475_1.6.2.3.1>
11084 18:15:03.684191 Received signal: <ENDRUN> 0_timesync-off 14291475_1.6.2.3.1
11085 18:15:03.684276 Ending use of test pattern.
11086 18:15:03.684364 Ending test lava.0_timesync-off (14291475_1.6.2.3.1), duration 0.07
11088 18:15:03.742841 + export TESTRUN_ID=1_kselftest-dt
11089 18:15:03.746111 + TESTRUN_ID=1_kselftest-dt
11090 18:15:03.749748 + cd /lava-14291475/0/tests/1_kselftest-dt
11091 18:15:03.752750 ++ cat uuid
11092 18:15:03.756585 + UUID=14291475_1.6.2.3.5
11093 18:15:03.756713 + set +x
11094 18:15:03.763128 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14291475_1.6.2.3.5>
11095 18:15:03.763223 + cd ./automated/linux/kselftest/
11096 18:15:03.763479 Received signal: <STARTRUN> 1_kselftest-dt 14291475_1.6.2.3.5
11097 18:15:03.763551 Starting test lava.1_kselftest-dt (14291475_1.6.2.3.5)
11098 18:15:03.763633 Skipping test definition patterns.
11099 18:15:03.789102 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11100 18:15:03.821247 INFO: install_deps skipped
11101 18:15:04.318944 --2024-06-11 18:10:21-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11102 18:15:04.328933 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11103 18:15:04.462021 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11104 18:15:04.595878 HTTP request sent, awaiting response... 200 OK
11105 18:15:04.599310 Length: 1647744 (1.6M) [application/octet-stream]
11106 18:15:04.602607 Saving to: 'kselftest_armhf.tar.gz'
11107 18:15:04.603197
11108 18:15:04.603586
11109 18:15:04.862594 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11110 18:15:05.128272 kselftest_armhf.tar 2%[ ] 47.81K 180KB/s
11111 18:15:05.441365 kselftest_armhf.tar 13%[=> ] 217.50K 409KB/s
11112 18:15:05.578245 kselftest_armhf.tar 51%[=========> ] 822.71K 973KB/s
11113 18:15:05.584747 kselftest_armhf.tar 100%[===================>] 1.57M 1.60MB/s in 1.0s
11114 18:15:05.585287
11115 18:15:05.729518 2024-06-11 18:10:22 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
11116 18:15:05.729654
11117 18:15:09.799101 skiplist:
11118 18:15:09.802704 ========================================
11119 18:15:09.806169 ========================================
11120 18:15:09.864902 ============== Tests to run ===============
11121 18:15:09.867735 ===========End Tests to run ===============
11122 18:15:09.871109 shardfile-dt fail
11123 18:15:09.892574 ./kselftest.sh: 131: cannot open /lava-14291475/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11124 18:15:09.895274 + ../../utils/send-to-lava.sh ./output/result.txt
11125 18:15:09.944183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11126 18:15:09.944390 + set +x
11127 18:15:09.944677 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11129 18:15:09.951545 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14291475_1.6.2.3.5>
11130 18:15:09.951684 <LAVA_TEST_RUNNER EXIT>
11131 18:15:09.951975 Received signal: <ENDRUN> 1_kselftest-dt 14291475_1.6.2.3.5
11132 18:15:09.952092 Ending use of test pattern.
11133 18:15:09.952226 Ending test lava.1_kselftest-dt (14291475_1.6.2.3.5), duration 6.19
11135 18:15:09.952636 ok: lava_test_shell seems to have completed
11136 18:15:09.952790 shardfile-dt: fail
11137 18:15:09.952925 end: 3.1 lava-test-shell (duration 00:00:07) [common]
11138 18:15:09.953059 end: 3 lava-test-retry (duration 00:00:07) [common]
11139 18:15:09.953199 start: 4 finalize (timeout 00:07:54) [common]
11140 18:15:09.953348 start: 4.1 power-off (timeout 00:00:30) [common]
11141 18:15:09.953586 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11142 18:15:10.050708 >> Command sent successfully.
11143 18:15:10.056863 Returned 0 in 0 seconds
11144 18:15:10.157783 end: 4.1 power-off (duration 00:00:00) [common]
11146 18:15:10.158896 start: 4.2 read-feedback (timeout 00:07:54) [common]
11147 18:15:10.159960 Listened to connection for namespace 'common' for up to 1s
11148 18:15:10.160825 Listened to connection for namespace 'common' for up to 1s
11149 18:15:11.160515 Finalising connection for namespace 'common'
11150 18:15:11.161030 Disconnecting from shell: Finalise
11151 18:15:11.161340 / #
11152 18:15:11.261916 end: 4.2 read-feedback (duration 00:00:01) [common]
11153 18:15:11.262208 end: 4 finalize (duration 00:00:01) [common]
11154 18:15:11.262477 Cleaning after the job
11155 18:15:11.262705 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/ramdisk
11156 18:15:11.266804 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/kernel
11157 18:15:11.287205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/dtb
11158 18:15:11.287529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/nfsrootfs
11159 18:15:11.355958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291475/tftp-deploy-mf64n40c/modules
11160 18:15:11.361275 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291475
11161 18:15:11.921130 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291475
11162 18:15:11.921299 Job finished correctly