Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 17:59:29.450712 lava-dispatcher, installed at version: 2024.03
2 17:59:29.450912 start: 0 validate
3 17:59:29.451027 Start time: 2024-06-11 17:59:29.451022+00:00 (UTC)
4 17:59:29.451160 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:59:29.451298 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:59:29.722448 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:59:29.723198 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:59:29.994730 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:59:29.995584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:00:30.288203 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:00:30.288343 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:00:30.817634 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:00:30.817819 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:00:31.087954 validate duration: 61.64
16 18:00:31.088204 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:00:31.088313 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:00:31.088402 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:00:31.088551 Not decompressing ramdisk as can be used compressed.
20 18:00:31.088642 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:00:31.088711 saving as /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/ramdisk/initrd.cpio.gz
22 18:00:31.088774 total size: 5628169 (5 MB)
23 18:00:33.884600 progress 0 % (0 MB)
24 18:00:33.886392 progress 5 % (0 MB)
25 18:00:33.888144 progress 10 % (0 MB)
26 18:00:33.889527 progress 15 % (0 MB)
27 18:00:33.891158 progress 20 % (1 MB)
28 18:00:33.892578 progress 25 % (1 MB)
29 18:00:33.894223 progress 30 % (1 MB)
30 18:00:33.895776 progress 35 % (1 MB)
31 18:00:33.897204 progress 40 % (2 MB)
32 18:00:33.898863 progress 45 % (2 MB)
33 18:00:33.900340 progress 50 % (2 MB)
34 18:00:33.901935 progress 55 % (2 MB)
35 18:00:33.903490 progress 60 % (3 MB)
36 18:00:33.904876 progress 65 % (3 MB)
37 18:00:33.906582 progress 70 % (3 MB)
38 18:00:33.908068 progress 75 % (4 MB)
39 18:00:33.909704 progress 80 % (4 MB)
40 18:00:33.911191 progress 85 % (4 MB)
41 18:00:33.912787 progress 90 % (4 MB)
42 18:00:33.914550 progress 95 % (5 MB)
43 18:00:33.916035 progress 100 % (5 MB)
44 18:00:33.916300 5 MB downloaded in 2.83 s (1.90 MB/s)
45 18:00:33.916521 end: 1.1.1 http-download (duration 00:00:03) [common]
47 18:00:33.916923 end: 1.1 download-retry (duration 00:00:03) [common]
48 18:00:33.917068 start: 1.2 download-retry (timeout 00:09:57) [common]
49 18:00:33.917203 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 18:00:33.917416 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:00:33.917486 saving as /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/kernel/Image
52 18:00:33.917542 total size: 54813184 (52 MB)
53 18:00:33.917598 No compression specified
54 18:01:06.198804 progress 0 % (0 MB)
55 18:01:06.244238 progress 5 % (2 MB)
56 18:01:06.257952 progress 10 % (5 MB)
57 18:01:06.271973 progress 15 % (7 MB)
58 18:01:06.285722 progress 20 % (10 MB)
59 18:01:06.299502 progress 25 % (13 MB)
60 18:01:06.313008 progress 30 % (15 MB)
61 18:01:06.326842 progress 35 % (18 MB)
62 18:01:06.340509 progress 40 % (20 MB)
63 18:01:06.353991 progress 45 % (23 MB)
64 18:01:06.367748 progress 50 % (26 MB)
65 18:01:06.381467 progress 55 % (28 MB)
66 18:01:06.395078 progress 60 % (31 MB)
67 18:01:06.408690 progress 65 % (34 MB)
68 18:01:06.422319 progress 70 % (36 MB)
69 18:01:06.435967 progress 75 % (39 MB)
70 18:01:06.449526 progress 80 % (41 MB)
71 18:01:06.462895 progress 85 % (44 MB)
72 18:01:06.476498 progress 90 % (47 MB)
73 18:01:06.489993 progress 95 % (49 MB)
74 18:01:06.503378 progress 100 % (52 MB)
75 18:01:06.503598 52 MB downloaded in 32.59 s (1.60 MB/s)
76 18:01:06.503741 end: 1.2.1 http-download (duration 00:00:33) [common]
78 18:01:06.503953 end: 1.2 download-retry (duration 00:00:33) [common]
79 18:01:06.504047 start: 1.3 download-retry (timeout 00:09:25) [common]
80 18:01:06.504124 start: 1.3.1 http-download (timeout 00:09:25) [common]
81 18:01:06.504258 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:01:06.504320 saving as /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/dtb/mt8192-asurada-spherion-r0.dtb
83 18:01:06.504374 total size: 47258 (0 MB)
84 18:01:06.504427 No compression specified
85 18:01:06.769446 progress 69 % (0 MB)
86 18:01:06.769745 progress 100 % (0 MB)
87 18:01:06.769900 0 MB downloaded in 0.27 s (0.17 MB/s)
88 18:01:06.770044 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:01:06.770287 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:01:06.770365 start: 1.4 download-retry (timeout 00:09:24) [common]
92 18:01:06.770442 start: 1.4.1 http-download (timeout 00:09:24) [common]
93 18:01:06.770567 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:01:06.770626 saving as /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/nfsrootfs/full.rootfs.tar
95 18:01:06.770678 total size: 120894716 (115 MB)
96 18:01:06.770732 Using unxz to decompress xz
97 18:01:07.037207 progress 0 % (0 MB)
98 18:01:07.423145 progress 5 % (5 MB)
99 18:01:07.791469 progress 10 % (11 MB)
100 18:01:08.152891 progress 15 % (17 MB)
101 18:01:08.492627 progress 20 % (23 MB)
102 18:01:08.802455 progress 25 % (28 MB)
103 18:01:09.150838 progress 30 % (34 MB)
104 18:01:09.481521 progress 35 % (40 MB)
105 18:01:09.654022 progress 40 % (46 MB)
106 18:01:09.834428 progress 45 % (51 MB)
107 18:01:10.146084 progress 50 % (57 MB)
108 18:01:10.519280 progress 55 % (63 MB)
109 18:01:10.876609 progress 60 % (69 MB)
110 18:01:11.235360 progress 65 % (74 MB)
111 18:01:11.584698 progress 70 % (80 MB)
112 18:01:11.939025 progress 75 % (86 MB)
113 18:01:12.276320 progress 80 % (92 MB)
114 18:01:12.620398 progress 85 % (98 MB)
115 18:01:12.975546 progress 90 % (103 MB)
116 18:01:13.303449 progress 95 % (109 MB)
117 18:01:13.668868 progress 100 % (115 MB)
118 18:01:13.674447 115 MB downloaded in 6.90 s (16.70 MB/s)
119 18:01:13.674618 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:01:13.674860 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:01:13.674955 start: 1.5 download-retry (timeout 00:09:17) [common]
123 18:01:13.675048 start: 1.5.1 http-download (timeout 00:09:17) [common]
124 18:01:13.675191 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:01:13.675258 saving as /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/modules/modules.tar
126 18:01:13.675348 total size: 8618176 (8 MB)
127 18:01:13.675440 Using unxz to decompress xz
128 18:01:13.941922 progress 0 % (0 MB)
129 18:01:13.961887 progress 5 % (0 MB)
130 18:01:13.989135 progress 10 % (0 MB)
131 18:01:14.018074 progress 15 % (1 MB)
132 18:01:14.044360 progress 20 % (1 MB)
133 18:01:14.070139 progress 25 % (2 MB)
134 18:01:14.095206 progress 30 % (2 MB)
135 18:01:14.121937 progress 35 % (2 MB)
136 18:01:14.147930 progress 40 % (3 MB)
137 18:01:14.172418 progress 45 % (3 MB)
138 18:01:14.197677 progress 50 % (4 MB)
139 18:01:14.223923 progress 55 % (4 MB)
140 18:01:14.249680 progress 60 % (4 MB)
141 18:01:14.274697 progress 65 % (5 MB)
142 18:01:14.302201 progress 70 % (5 MB)
143 18:01:14.327469 progress 75 % (6 MB)
144 18:01:14.354638 progress 80 % (6 MB)
145 18:01:14.379853 progress 85 % (7 MB)
146 18:01:14.406526 progress 90 % (7 MB)
147 18:01:14.432867 progress 95 % (7 MB)
148 18:01:14.461234 progress 100 % (8 MB)
149 18:01:14.465821 8 MB downloaded in 0.79 s (10.40 MB/s)
150 18:01:14.465985 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:01:14.466219 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:01:14.466302 start: 1.6 prepare-tftp-overlay (timeout 00:09:17) [common]
154 18:01:14.466389 start: 1.6.1 extract-nfsrootfs (timeout 00:09:17) [common]
155 18:01:18.076788 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr
156 18:01:18.076944 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 18:01:18.077032 start: 1.6.2 lava-overlay (timeout 00:09:13) [common]
158 18:01:18.077193 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m
159 18:01:18.077312 makedir: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin
160 18:01:18.077402 makedir: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/tests
161 18:01:18.077488 makedir: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/results
162 18:01:18.077571 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-add-keys
163 18:01:18.077736 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-add-sources
164 18:01:18.077857 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-background-process-start
165 18:01:18.077974 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-background-process-stop
166 18:01:18.078097 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-common-functions
167 18:01:18.078308 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-echo-ipv4
168 18:01:18.078426 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-install-packages
169 18:01:18.078539 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-installed-packages
170 18:01:18.078650 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-os-build
171 18:01:18.078769 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-probe-channel
172 18:01:18.078881 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-probe-ip
173 18:01:18.078993 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-target-ip
174 18:01:18.079103 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-target-mac
175 18:01:18.079215 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-target-storage
176 18:01:18.079327 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-case
177 18:01:18.079436 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-event
178 18:01:18.079545 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-feedback
179 18:01:18.079654 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-raise
180 18:01:18.079761 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-reference
181 18:01:18.079870 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-runner
182 18:01:18.079979 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-set
183 18:01:18.080086 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-test-shell
184 18:01:18.080199 Updating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-add-keys (debian)
185 18:01:18.080336 Updating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-add-sources (debian)
186 18:01:18.080458 Updating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-install-packages (debian)
187 18:01:18.080586 Updating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-installed-packages (debian)
188 18:01:18.080707 Updating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/bin/lava-os-build (debian)
189 18:01:18.080818 Creating /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/environment
190 18:01:18.080903 LAVA metadata
191 18:01:18.080970 - LAVA_JOB_ID=14291331
192 18:01:18.081024 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:01:18.081113 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:13) [common]
194 18:01:18.081169 skipped lava-vland-overlay
195 18:01:18.081234 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:01:18.081304 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:13) [common]
197 18:01:18.081357 skipped lava-multinode-overlay
198 18:01:18.081420 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:01:18.081488 start: 1.6.2.3 test-definition (timeout 00:09:13) [common]
200 18:01:18.081550 Loading test definitions
201 18:01:18.081623 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:13) [common]
202 18:01:18.081691 Using /lava-14291331 at stage 0
203 18:01:18.081963 uuid=14291331_1.6.2.3.1 testdef=None
204 18:01:18.082042 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:01:18.082115 start: 1.6.2.3.2 test-overlay (timeout 00:09:13) [common]
206 18:01:18.082551 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:01:18.082749 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:13) [common]
209 18:01:18.083243 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:01:18.083448 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:13) [common]
212 18:01:18.083932 runner path: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/0/tests/0_timesync-off test_uuid 14291331_1.6.2.3.1
213 18:01:18.084075 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:01:18.084274 start: 1.6.2.3.5 git-repo-action (timeout 00:09:13) [common]
216 18:01:18.084338 Using /lava-14291331 at stage 0
217 18:01:18.084425 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:01:18.084501 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/0/tests/1_kselftest-rtc'
219 18:01:21.102765 Running '/usr/bin/git checkout kernelci.org
220 18:01:21.192281 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 18:01:21.192668 uuid=14291331_1.6.2.3.5 testdef=None
222 18:01:21.192778 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 18:01:21.193004 start: 1.6.2.3.6 test-overlay (timeout 00:09:10) [common]
225 18:01:21.193688 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:01:21.193918 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:10) [common]
228 18:01:21.194938 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:01:21.195180 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:10) [common]
231 18:01:21.196052 runner path: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/0/tests/1_kselftest-rtc test_uuid 14291331_1.6.2.3.5
232 18:01:21.196138 BOARD='mt8192-asurada-spherion-r0'
233 18:01:21.196208 BRANCH='cip'
234 18:01:21.196280 SKIPFILE='/dev/null'
235 18:01:21.196350 SKIP_INSTALL='True'
236 18:01:21.196437 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:01:21.196526 TST_CASENAME=''
238 18:01:21.196612 TST_CMDFILES='rtc'
239 18:01:21.196794 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:01:21.197117 Creating lava-test-runner.conf files
242 18:01:21.197207 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291331/lava-overlay-zlldr38m/lava-14291331/0 for stage 0
243 18:01:21.197331 - 0_timesync-off
244 18:01:21.197420 - 1_kselftest-rtc
245 18:01:21.197549 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 18:01:21.197660 start: 1.6.2.4 compress-overlay (timeout 00:09:10) [common]
247 18:01:28.295423 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 18:01:28.295551 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:03) [common]
249 18:01:28.295636 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:01:28.295718 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:01:28.295799 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:03) [common]
252 18:01:31.355757 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:03) [common]
253 18:01:31.355925 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
254 18:01:31.356005 extracting modules file /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr
255 18:01:31.571909 extracting modules file /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291331/extract-overlay-ramdisk-q1hnvbzm/ramdisk
256 18:01:31.802477 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:01:31.802621 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
258 18:01:31.802701 [common] Applying overlay to NFS
259 18:01:31.802763 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291331/compress-overlay-ppgpqm4i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr
260 18:01:32.704919 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:01:32.705052 start: 1.6.6 configure-preseed-file (timeout 00:08:58) [common]
262 18:01:32.705140 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:01:32.705221 start: 1.6.7 compress-ramdisk (timeout 00:08:58) [common]
264 18:01:32.705297 Building ramdisk /var/lib/lava/dispatcher/tmp/14291331/extract-overlay-ramdisk-q1hnvbzm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291331/extract-overlay-ramdisk-q1hnvbzm/ramdisk
265 18:01:33.004762 >> 130400 blocks
266 18:01:35.098892 rename /var/lib/lava/dispatcher/tmp/14291331/extract-overlay-ramdisk-q1hnvbzm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/ramdisk/ramdisk.cpio.gz
267 18:01:35.099064 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 18:01:35.099154 start: 1.6.8 prepare-kernel (timeout 00:08:56) [common]
269 18:01:35.099233 start: 1.6.8.1 prepare-fit (timeout 00:08:56) [common]
270 18:01:35.099312 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/kernel/Image']
271 18:01:48.788128 Returned 0 in 13 seconds
272 18:01:48.888659 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/kernel/image.itb
273 18:01:49.287320 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:01:49.287474 output: Created: Tue Jun 11 19:01:49 2024
275 18:01:49.287542 output: Image 0 (kernel-1)
276 18:01:49.287631 output: Description:
277 18:01:49.287719 output: Created: Tue Jun 11 19:01:49 2024
278 18:01:49.287786 output: Type: Kernel Image
279 18:01:49.287856 output: Compression: lzma compressed
280 18:01:49.287944 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:01:49.288028 output: Architecture: AArch64
282 18:01:49.288078 output: OS: Linux
283 18:01:49.288130 output: Load Address: 0x00000000
284 18:01:49.288181 output: Entry Point: 0x00000000
285 18:01:49.288233 output: Hash algo: crc32
286 18:01:49.288300 output: Hash value: 7a9e9d3e
287 18:01:49.288358 output: Image 1 (fdt-1)
288 18:01:49.288423 output: Description: mt8192-asurada-spherion-r0
289 18:01:49.288478 output: Created: Tue Jun 11 19:01:49 2024
290 18:01:49.288532 output: Type: Flat Device Tree
291 18:01:49.288588 output: Compression: uncompressed
292 18:01:49.288685 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 18:01:49.288741 output: Architecture: AArch64
294 18:01:49.288798 output: Hash algo: crc32
295 18:01:49.288851 output: Hash value: 0f8e4d2e
296 18:01:49.288904 output: Image 2 (ramdisk-1)
297 18:01:49.288974 output: Description: unavailable
298 18:01:49.289075 output: Created: Tue Jun 11 19:01:49 2024
299 18:01:49.289170 output: Type: RAMDisk Image
300 18:01:49.289236 output: Compression: uncompressed
301 18:01:49.289284 output: Data Size: 18732804 Bytes = 18293.75 KiB = 17.86 MiB
302 18:01:49.289332 output: Architecture: AArch64
303 18:01:49.289380 output: OS: Linux
304 18:01:49.289426 output: Load Address: unavailable
305 18:01:49.289474 output: Entry Point: unavailable
306 18:01:49.289522 output: Hash algo: crc32
307 18:01:49.289568 output: Hash value: 6ecb7125
308 18:01:49.289615 output: Default Configuration: 'conf-1'
309 18:01:49.289662 output: Configuration 0 (conf-1)
310 18:01:49.289709 output: Description: mt8192-asurada-spherion-r0
311 18:01:49.289756 output: Kernel: kernel-1
312 18:01:49.289804 output: Init Ramdisk: ramdisk-1
313 18:01:49.289851 output: FDT: fdt-1
314 18:01:49.289898 output: Loadables: kernel-1
315 18:01:49.289946 output:
316 18:01:49.290104 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 18:01:49.290199 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 18:01:49.290320 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 18:01:49.290404 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
320 18:01:49.290472 No LXC device requested
321 18:01:49.290542 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:01:49.290618 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
323 18:01:49.290689 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:01:49.290752 Checking files for TFTP limit of 4294967296 bytes.
325 18:01:49.291197 end: 1 tftp-deploy (duration 00:01:18) [common]
326 18:01:49.291299 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:01:49.291382 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:01:49.291494 substitutions:
329 18:01:49.291556 - {DTB}: 14291331/tftp-deploy-q2673t4g/dtb/mt8192-asurada-spherion-r0.dtb
330 18:01:49.291613 - {INITRD}: 14291331/tftp-deploy-q2673t4g/ramdisk/ramdisk.cpio.gz
331 18:01:49.291666 - {KERNEL}: 14291331/tftp-deploy-q2673t4g/kernel/Image
332 18:01:49.291715 - {LAVA_MAC}: None
333 18:01:49.291765 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr
334 18:01:49.291815 - {NFS_SERVER_IP}: 192.168.201.1
335 18:01:49.291863 - {PRESEED_CONFIG}: None
336 18:01:49.291918 - {PRESEED_LOCAL}: None
337 18:01:49.291969 - {RAMDISK}: 14291331/tftp-deploy-q2673t4g/ramdisk/ramdisk.cpio.gz
338 18:01:49.292018 - {ROOT_PART}: None
339 18:01:49.292067 - {ROOT}: None
340 18:01:49.292115 - {SERVER_IP}: 192.168.201.1
341 18:01:49.292178 - {TEE}: None
342 18:01:49.292258 Parsed boot commands:
343 18:01:49.292306 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:01:49.292481 Parsed boot commands: tftpboot 192.168.201.1 14291331/tftp-deploy-q2673t4g/kernel/image.itb 14291331/tftp-deploy-q2673t4g/kernel/cmdline
345 18:01:49.292566 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:01:49.292640 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:01:49.292717 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:01:49.292794 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:01:49.292857 Not connected, no need to disconnect.
350 18:01:49.292923 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:01:49.292993 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:01:49.293056 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 18:01:49.296593 Setting prompt string to ['lava-test: # ']
354 18:01:49.296975 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:01:49.297081 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:01:49.297178 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:01:49.297262 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:01:49.297425 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-4']
359 18:02:02.886812 Returned 0 in 13 seconds
360 18:02:02.987879 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 18:02:02.989136 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 18:02:02.989600 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 18:02:02.990026 Setting prompt string to 'Starting depthcharge on Spherion...'
365 18:02:02.990371 Changing prompt to 'Starting depthcharge on Spherion...'
366 18:02:02.990706 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 18:02:02.992365 [Enter `^Ec?' for help]
368 18:02:02.992729
369 18:02:02.993036
370 18:02:02.993313 F0: 102B 0000
371 18:02:02.993586
372 18:02:02.993864 F3: 1001 0000 [0200]
373 18:02:02.994140
374 18:02:02.994524 F3: 1001 0000
375 18:02:02.994813
376 18:02:02.995091 F7: 102D 0000
377 18:02:02.995364
378 18:02:02.995645 F1: 0000 0000
379 18:02:02.995936
380 18:02:02.996223 V0: 0000 0000 [0001]
381 18:02:02.996516
382 18:02:02.996811 00: 0007 8000
383 18:02:02.997110
384 18:02:02.997425 01: 0000 0000
385 18:02:02.997723
386 18:02:02.997997 BP: 0C00 0209 [0000]
387 18:02:02.998289
388 18:02:02.998542 G0: 1182 0000
389 18:02:02.998794
390 18:02:02.999044 EC: 0000 0021 [4000]
391 18:02:02.999296
392 18:02:02.999545 S7: 0000 0000 [0000]
393 18:02:02.999792
394 18:02:03.000042 CC: 0000 0000 [0001]
395 18:02:03.000307
396 18:02:03.000555 T0: 0000 0040 [010F]
397 18:02:03.000804
398 18:02:03.001053 Jump to BL
399 18:02:03.001305
400 18:02:03.001635
401 18:02:03.001898
402 18:02:03.002149 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 18:02:03.002465 ARM64: Exception handlers installed.
404 18:02:03.002725 ARM64: Testing exception
405 18:02:03.002973 ARM64: Done test exception
406 18:02:03.003221 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 18:02:03.003478 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 18:02:03.003743 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 18:02:03.004002 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 18:02:03.004258 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 18:02:03.004512 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 18:02:03.004767 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 18:02:03.005020 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 18:02:03.005271 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 18:02:03.005585 WDT: Last reset was cold boot
416 18:02:03.006033 SPI1(PAD0) initialized at 2873684 Hz
417 18:02:03.006358 SPI5(PAD0) initialized at 992727 Hz
418 18:02:03.006620 VBOOT: Loading verstage.
419 18:02:03.006875 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 18:02:03.007132 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 18:02:03.007389 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 18:02:03.007644 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 18:02:03.007900 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 18:02:03.008157 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 18:02:03.008411 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 18:02:03.008662
427 18:02:03.008909
428 18:02:03.009158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 18:02:03.009419 ARM64: Exception handlers installed.
430 18:02:03.009669 ARM64: Testing exception
431 18:02:03.009920 ARM64: Done test exception
432 18:02:03.010167 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 18:02:03.010453 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 18:02:03.010710 Probing TPM: . done!
435 18:02:03.010962 TPM ready after 0 ms
436 18:02:03.011216 Connected to device vid:did:rid of 1ae0:0028:00
437 18:02:03.011471 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
438 18:02:03.011782 Initialized TPM device CR50 revision 0
439 18:02:03.012043 tlcl_send_startup: Startup return code is 0
440 18:02:03.012342 TPM: setup succeeded
441 18:02:03.012605 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 18:02:03.012860 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 18:02:03.013114 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 18:02:03.013367 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 18:02:03.013619 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 18:02:03.013871 in-header: 03 07 00 00 08 00 00 00
447 18:02:03.014120 in-data: aa e4 47 04 13 02 00 00
448 18:02:03.014393 Chrome EC: UHEPI supported
449 18:02:03.014649 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 18:02:03.014904 in-header: 03 a9 00 00 08 00 00 00
451 18:02:03.015152 in-data: 84 60 60 08 00 00 00 00
452 18:02:03.015402 Phase 1
453 18:02:03.015651 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 18:02:03.015923 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 18:02:03.016284 VB2:vb2_check_recovery() Recovery was requested manually
456 18:02:03.016604 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 18:02:03.016795 Recovery requested (1009000e)
458 18:02:03.016976 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 18:02:03.017159 tlcl_extend: response is 0
460 18:02:03.017340 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 18:02:03.017522 tlcl_extend: response is 0
462 18:02:03.017701 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 18:02:03.017882 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 18:02:03.018063 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 18:02:03.018260
466 18:02:03.018440
467 18:02:03.018621 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 18:02:03.018804 ARM64: Exception handlers installed.
469 18:02:03.018983 ARM64: Testing exception
470 18:02:03.019161 ARM64: Done test exception
471 18:02:03.019341 pmic_efuse_setting: Set efuses in 11 msecs
472 18:02:03.019520 pmwrap_interface_init: Select PMIF_VLD_RDY
473 18:02:03.019699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 18:02:03.019879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 18:02:03.020352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 18:02:03.020574 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 18:02:03.020761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 18:02:03.020944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 18:02:03.021125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 18:02:03.021304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 18:02:03.021480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 18:02:03.021616 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 18:02:03.021753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 18:02:03.021887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 18:02:03.022024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 18:02:03.022158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 18:02:03.022324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 18:02:03.022461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 18:02:03.022595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 18:02:03.022732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 18:02:03.022867 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 18:02:03.023001 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 18:02:03.023138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 18:02:03.023275 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 18:02:03.023412 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 18:02:03.023547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 18:02:03.023682 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 18:02:03.023819 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 18:02:03.023958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 18:02:03.024095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 18:02:03.024230 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 18:02:03.024365 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 18:02:03.024500 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 18:02:03.024635 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 18:02:03.024769 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 18:02:03.024904 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 18:02:03.025039 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 18:02:03.025174 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 18:02:03.025308 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 18:02:03.025447 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 18:02:03.025584 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 18:02:03.025720 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 18:02:03.025857 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 18:02:03.025992 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 18:02:03.026128 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 18:02:03.026274 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 18:02:03.026412 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 18:02:03.026543 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 18:02:03.026651 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 18:02:03.026758 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 18:02:03.026870 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 18:02:03.026978 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 18:02:03.027091 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 18:02:03.027199 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 18:02:03.027309 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 18:02:03.027419 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 18:02:03.027528 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 18:02:03.027639 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 18:02:03.027749 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 18:02:03.027858 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 18:02:03.027967 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 18:02:03.028076 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
533 18:02:03.028185 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 18:02:03.028295 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 18:02:03.028404 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 18:02:03.028514 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 18:02:03.028624 [RTC]rtc_get_frequency_meter,154: input=23, output=949
538 18:02:03.028732 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 18:02:03.028841 [RTC]rtc_get_frequency_meter,154: input=17, output=811
540 18:02:03.028948 [RTC]rtc_get_frequency_meter,154: input=16, output=786
541 18:02:03.029056 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 18:02:03.029165 [RTC]rtc_get_frequency_meter,154: input=17, output=810
543 18:02:03.029272 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 18:02:03.029380 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 18:02:03.029718 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 18:02:03.029847 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 18:02:03.029959 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 18:02:03.030071 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 18:02:03.030180 ADC[4]: Raw value=669695 ID=5
550 18:02:03.030305 ADC[3]: Raw value=212549 ID=1
551 18:02:03.030416 RAM Code: 0x51
552 18:02:03.030525 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 18:02:03.030636 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 18:02:03.030748 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 18:02:03.030860 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 18:02:03.030972 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 18:02:03.031080 in-header: 03 07 00 00 08 00 00 00
558 18:02:03.031186 in-data: aa e4 47 04 13 02 00 00
559 18:02:03.031293 Chrome EC: UHEPI supported
560 18:02:03.031402 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 18:02:03.031511 in-header: 03 a9 00 00 08 00 00 00
562 18:02:03.031601 in-data: 84 60 60 08 00 00 00 00
563 18:02:03.031692 MRC: failed to locate region type 0.
564 18:02:03.031782 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 18:02:03.031873 DRAM-K: Running full calibration
566 18:02:03.031963 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 18:02:03.032052 header.status = 0x0
568 18:02:03.032142 header.version = 0x6 (expected: 0x6)
569 18:02:03.032233 header.size = 0xd00 (expected: 0xd00)
570 18:02:03.032323 header.flags = 0x0
571 18:02:03.032412 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 18:02:03.032504 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 18:02:03.032595 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 18:02:03.032686 dram_init: ddr_geometry: 0
575 18:02:03.032775 [EMI] MDL number = 0
576 18:02:03.032864 [EMI] Get MDL freq = 0
577 18:02:03.032954 dram_init: ddr_type: 0
578 18:02:03.033043 is_discrete_lpddr4: 1
579 18:02:03.033134 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 18:02:03.033225
581 18:02:03.033314
582 18:02:03.033404 [Bian_co] ETT version 0.0.0.1
583 18:02:03.033496 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 18:02:03.033587
585 18:02:03.033677 dramc_set_vcore_voltage set vcore to 650000
586 18:02:03.033768 Read voltage for 800, 4
587 18:02:03.033859 Vio18 = 0
588 18:02:03.033950 Vcore = 650000
589 18:02:03.034040 Vdram = 0
590 18:02:03.034129 Vddq = 0
591 18:02:03.034227 Vmddr = 0
592 18:02:03.034319 dram_init: config_dvfs: 1
593 18:02:03.034410 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 18:02:03.034501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 18:02:03.034592 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 18:02:03.034683 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 18:02:03.034775 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 18:02:03.034869 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 18:02:03.034961 MEM_TYPE=3, freq_sel=18
600 18:02:03.035051 sv_algorithm_assistance_LP4_1600
601 18:02:03.035142 ============ PULL DRAM RESETB DOWN ============
602 18:02:03.035237 ========== PULL DRAM RESETB DOWN end =========
603 18:02:03.035328 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 18:02:03.035419 ===================================
605 18:02:03.035509 LPDDR4 DRAM CONFIGURATION
606 18:02:03.035599 ===================================
607 18:02:03.035690 EX_ROW_EN[0] = 0x0
608 18:02:03.035780 EX_ROW_EN[1] = 0x0
609 18:02:03.035870 LP4Y_EN = 0x0
610 18:02:03.035960 WORK_FSP = 0x0
611 18:02:03.036051 WL = 0x2
612 18:02:03.036141 RL = 0x2
613 18:02:03.036231 BL = 0x2
614 18:02:03.036320 RPST = 0x0
615 18:02:03.036410 RD_PRE = 0x0
616 18:02:03.036505 WR_PRE = 0x1
617 18:02:03.036581 WR_PST = 0x0
618 18:02:03.036656 DBI_WR = 0x0
619 18:02:03.036732 DBI_RD = 0x0
620 18:02:03.036809 OTF = 0x1
621 18:02:03.036891 ===================================
622 18:02:03.036968 ===================================
623 18:02:03.037045 ANA top config
624 18:02:03.037121 ===================================
625 18:02:03.037198 DLL_ASYNC_EN = 0
626 18:02:03.037275 ALL_SLAVE_EN = 1
627 18:02:03.037353 NEW_RANK_MODE = 1
628 18:02:03.037430 DLL_IDLE_MODE = 1
629 18:02:03.037507 LP45_APHY_COMB_EN = 1
630 18:02:03.037584 TX_ODT_DIS = 1
631 18:02:03.037661 NEW_8X_MODE = 1
632 18:02:03.037739 ===================================
633 18:02:03.037817 ===================================
634 18:02:03.037894 data_rate = 1600
635 18:02:03.037973 CKR = 1
636 18:02:03.038051 DQ_P2S_RATIO = 8
637 18:02:03.038128 ===================================
638 18:02:03.038206 CA_P2S_RATIO = 8
639 18:02:03.038296 DQ_CA_OPEN = 0
640 18:02:03.038375 DQ_SEMI_OPEN = 0
641 18:02:03.038452 CA_SEMI_OPEN = 0
642 18:02:03.038562 CA_FULL_RATE = 0
643 18:02:03.038644 DQ_CKDIV4_EN = 1
644 18:02:03.038723 CA_CKDIV4_EN = 1
645 18:02:03.038800 CA_PREDIV_EN = 0
646 18:02:03.038876 PH8_DLY = 0
647 18:02:03.038953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 18:02:03.039029 DQ_AAMCK_DIV = 4
649 18:02:03.039106 CA_AAMCK_DIV = 4
650 18:02:03.039182 CA_ADMCK_DIV = 4
651 18:02:03.039258 DQ_TRACK_CA_EN = 0
652 18:02:03.039335 CA_PICK = 800
653 18:02:03.039413 CA_MCKIO = 800
654 18:02:03.039491 MCKIO_SEMI = 0
655 18:02:03.039568 PLL_FREQ = 3068
656 18:02:03.039646 DQ_UI_PI_RATIO = 32
657 18:02:03.039723 CA_UI_PI_RATIO = 0
658 18:02:03.039799 ===================================
659 18:02:03.039877 ===================================
660 18:02:03.039955 memory_type:LPDDR4
661 18:02:03.040032 GP_NUM : 10
662 18:02:03.040110 SRAM_EN : 1
663 18:02:03.040188 MD32_EN : 0
664 18:02:03.040265 ===================================
665 18:02:03.040580 [ANA_INIT] >>>>>>>>>>>>>>
666 18:02:03.040675 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 18:02:03.040762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 18:02:03.040841 ===================================
669 18:02:03.040921 data_rate = 1600,PCW = 0X7600
670 18:02:03.040999 ===================================
671 18:02:03.041077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 18:02:03.041156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 18:02:03.041235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 18:02:03.041314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 18:02:03.041392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 18:02:03.041479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 18:02:03.041547 [ANA_INIT] flow start
678 18:02:03.041615 [ANA_INIT] PLL >>>>>>>>
679 18:02:03.041683 [ANA_INIT] PLL <<<<<<<<
680 18:02:03.041751 [ANA_INIT] MIDPI >>>>>>>>
681 18:02:03.041820 [ANA_INIT] MIDPI <<<<<<<<
682 18:02:03.041888 [ANA_INIT] DLL >>>>>>>>
683 18:02:03.041956 [ANA_INIT] flow end
684 18:02:03.042023 ============ LP4 DIFF to SE enter ============
685 18:02:03.042092 ============ LP4 DIFF to SE exit ============
686 18:02:03.042160 [ANA_INIT] <<<<<<<<<<<<<
687 18:02:03.042242 [Flow] Enable top DCM control >>>>>
688 18:02:03.042313 [Flow] Enable top DCM control <<<<<
689 18:02:03.042382 Enable DLL master slave shuffle
690 18:02:03.042450 ==============================================================
691 18:02:03.042519 Gating Mode config
692 18:02:03.042610 ==============================================================
693 18:02:03.042680 Config description:
694 18:02:03.042748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 18:02:03.042818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 18:02:03.042888 SELPH_MODE 0: By rank 1: By Phase
697 18:02:03.042956 ==============================================================
698 18:02:03.043025 GAT_TRACK_EN = 1
699 18:02:03.043092 RX_GATING_MODE = 2
700 18:02:03.043159 RX_GATING_TRACK_MODE = 2
701 18:02:03.043227 SELPH_MODE = 1
702 18:02:03.043295 PICG_EARLY_EN = 1
703 18:02:03.043362 VALID_LAT_VALUE = 1
704 18:02:03.043430 ==============================================================
705 18:02:03.043499 Enter into Gating configuration >>>>
706 18:02:03.043567 Exit from Gating configuration <<<<
707 18:02:03.043635 Enter into DVFS_PRE_config >>>>>
708 18:02:03.043703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 18:02:03.043777 Exit from DVFS_PRE_config <<<<<
710 18:02:03.043844 Enter into PICG configuration >>>>
711 18:02:03.043912 Exit from PICG configuration <<<<
712 18:02:03.043979 [RX_INPUT] configuration >>>>>
713 18:02:03.044047 [RX_INPUT] configuration <<<<<
714 18:02:03.044114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 18:02:03.044182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 18:02:03.044251 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 18:02:03.044320 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 18:02:03.044387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 18:02:03.044455 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 18:02:03.044528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 18:02:03.044599 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 18:02:03.044668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 18:02:03.044737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 18:02:03.044804 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 18:02:03.044873 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 18:02:03.044941 ===================================
727 18:02:03.045009 LPDDR4 DRAM CONFIGURATION
728 18:02:03.045076 ===================================
729 18:02:03.045144 EX_ROW_EN[0] = 0x0
730 18:02:03.045212 EX_ROW_EN[1] = 0x0
731 18:02:03.045280 LP4Y_EN = 0x0
732 18:02:03.045347 WORK_FSP = 0x0
733 18:02:03.045414 WL = 0x2
734 18:02:03.045481 RL = 0x2
735 18:02:03.045548 BL = 0x2
736 18:02:03.045615 RPST = 0x0
737 18:02:03.045682 RD_PRE = 0x0
738 18:02:03.045750 WR_PRE = 0x1
739 18:02:03.045817 WR_PST = 0x0
740 18:02:03.045884 DBI_WR = 0x0
741 18:02:03.045951 DBI_RD = 0x0
742 18:02:03.046020 OTF = 0x1
743 18:02:03.046088 ===================================
744 18:02:03.046156 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 18:02:03.046234 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 18:02:03.046304 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 18:02:03.046372 ===================================
748 18:02:03.046450 LPDDR4 DRAM CONFIGURATION
749 18:02:03.046511 ===================================
750 18:02:03.046591 EX_ROW_EN[0] = 0x10
751 18:02:03.046700 EX_ROW_EN[1] = 0x0
752 18:02:03.046768 LP4Y_EN = 0x0
753 18:02:03.046829 WORK_FSP = 0x0
754 18:02:03.046890 WL = 0x2
755 18:02:03.046951 RL = 0x2
756 18:02:03.047012 BL = 0x2
757 18:02:03.047072 RPST = 0x0
758 18:02:03.047132 RD_PRE = 0x0
759 18:02:03.047192 WR_PRE = 0x1
760 18:02:03.047252 WR_PST = 0x0
761 18:02:03.047312 DBI_WR = 0x0
762 18:02:03.047372 DBI_RD = 0x0
763 18:02:03.047431 OTF = 0x1
764 18:02:03.047491 ===================================
765 18:02:03.047552 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 18:02:03.047614 nWR fixed to 40
767 18:02:03.047675 [ModeRegInit_LP4] CH0 RK0
768 18:02:03.047735 [ModeRegInit_LP4] CH0 RK1
769 18:02:03.047795 [ModeRegInit_LP4] CH1 RK0
770 18:02:03.047855 [ModeRegInit_LP4] CH1 RK1
771 18:02:03.047915 match AC timing 12
772 18:02:03.047975 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 18:02:03.048036 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 18:02:03.048298 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 18:02:03.048371 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 18:02:03.048434 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 18:02:03.048497 [EMI DOE] emi_dcm 0
778 18:02:03.048562 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 18:02:03.048623 ==
780 18:02:03.048684 Dram Type= 6, Freq= 0, CH_0, rank 0
781 18:02:03.048745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 18:02:03.048806 ==
783 18:02:03.048866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 18:02:03.048928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 18:02:03.048989 [CA 0] Center 37 (7~68) winsize 62
786 18:02:03.049050 [CA 1] Center 37 (7~68) winsize 62
787 18:02:03.049110 [CA 2] Center 35 (5~66) winsize 62
788 18:02:03.049170 [CA 3] Center 35 (4~66) winsize 63
789 18:02:03.049230 [CA 4] Center 34 (4~65) winsize 62
790 18:02:03.049291 [CA 5] Center 34 (3~65) winsize 63
791 18:02:03.049351
792 18:02:03.049411 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 18:02:03.049472
794 18:02:03.049532 [CATrainingPosCal] consider 1 rank data
795 18:02:03.049593 u2DelayCellTimex100 = 270/100 ps
796 18:02:03.049653 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 18:02:03.049713 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
798 18:02:03.049774 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 18:02:03.049836 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
800 18:02:03.049896 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 18:02:03.049957 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
802 18:02:03.050017
803 18:02:03.050077 CA PerBit enable=1, Macro0, CA PI delay=34
804 18:02:03.050138
805 18:02:03.050196 [CBTSetCACLKResult] CA Dly = 34
806 18:02:03.050270 CS Dly: 5 (0~36)
807 18:02:03.050332 ==
808 18:02:03.050393 Dram Type= 6, Freq= 0, CH_0, rank 1
809 18:02:03.050454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 18:02:03.050515 ==
811 18:02:03.050576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 18:02:03.050637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 18:02:03.050699 [CA 0] Center 37 (6~68) winsize 63
814 18:02:03.050759 [CA 1] Center 37 (6~68) winsize 63
815 18:02:03.050823 [CA 2] Center 35 (4~66) winsize 63
816 18:02:03.050891 [CA 3] Center 34 (4~65) winsize 62
817 18:02:03.050953 [CA 4] Center 33 (3~64) winsize 62
818 18:02:03.051013 [CA 5] Center 33 (3~64) winsize 62
819 18:02:03.051074
820 18:02:03.051135 [CmdBusTrainingLP45] Vref(ca) range 1: 32
821 18:02:03.051196
822 18:02:03.051256 [CATrainingPosCal] consider 2 rank data
823 18:02:03.051316 u2DelayCellTimex100 = 270/100 ps
824 18:02:03.051377 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 18:02:03.051449 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 18:02:03.051503 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
827 18:02:03.051557 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 18:02:03.051611 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
829 18:02:03.051666 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 18:02:03.051720
831 18:02:03.051775 CA PerBit enable=1, Macro0, CA PI delay=33
832 18:02:03.051829
833 18:02:03.051882 [CBTSetCACLKResult] CA Dly = 33
834 18:02:03.051936 CS Dly: 6 (0~38)
835 18:02:03.051991
836 18:02:03.052045 ----->DramcWriteLeveling(PI) begin...
837 18:02:03.052100 ==
838 18:02:03.052155 Dram Type= 6, Freq= 0, CH_0, rank 0
839 18:02:03.052209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 18:02:03.052264 ==
841 18:02:03.052319 Write leveling (Byte 0): 30 => 30
842 18:02:03.052373 Write leveling (Byte 1): 29 => 29
843 18:02:03.052427 DramcWriteLeveling(PI) end<-----
844 18:02:03.052481
845 18:02:03.052535 ==
846 18:02:03.052590 Dram Type= 6, Freq= 0, CH_0, rank 0
847 18:02:03.052645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 18:02:03.052700 ==
849 18:02:03.052755 [Gating] SW mode calibration
850 18:02:03.052810 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 18:02:03.052866 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 18:02:03.052921 0 6 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
853 18:02:03.052975 0 6 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
854 18:02:03.053030 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 18:02:03.053084 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 18:02:03.053139 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 18:02:03.053193 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 18:02:03.053247 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:02:03.053302 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:02:03.053356 0 7 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
861 18:02:03.053410 0 7 4 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
862 18:02:03.053464 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 18:02:03.053519 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 18:02:03.053573 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 18:02:03.053628 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 18:02:03.053682 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 18:02:03.053737 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 18:02:03.053791 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
869 18:02:03.053846 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 18:02:03.053900 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 18:02:03.053955 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 18:02:03.054010 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 18:02:03.054064 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 18:02:03.054119 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 18:02:03.054173 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 18:02:03.054246 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 18:02:03.054334 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 18:02:03.054421 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 18:02:03.054490 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 18:02:03.054546 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 18:02:03.054813 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 18:02:03.054887 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 18:02:03.054983 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 18:02:03.055042 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 18:02:03.055100 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 18:02:03.055155 Total UI for P1: 0, mck2ui 16
887 18:02:03.055211 best dqsien dly found for B0: ( 0, 10, 2)
888 18:02:03.055267 Total UI for P1: 0, mck2ui 16
889 18:02:03.055322 best dqsien dly found for B1: ( 0, 10, 2)
890 18:02:03.055377 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
891 18:02:03.055432 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
892 18:02:03.055487
893 18:02:03.055554 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
894 18:02:03.055610 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 18:02:03.055666 [Gating] SW calibration Done
896 18:02:03.055720 ==
897 18:02:03.055775 Dram Type= 6, Freq= 0, CH_0, rank 0
898 18:02:03.055830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 18:02:03.055885 ==
900 18:02:03.055940 RX Vref Scan: 0
901 18:02:03.055994
902 18:02:03.056048 RX Vref 0 -> 0, step: 1
903 18:02:03.056102
904 18:02:03.056155 RX Delay -130 -> 252, step: 16
905 18:02:03.056210 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 18:02:03.056265 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 18:02:03.056320 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 18:02:03.056374 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 18:02:03.056442 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 18:02:03.056491 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 18:02:03.056540 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 18:02:03.056590 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 18:02:03.056639 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 18:02:03.056688 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 18:02:03.056737 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 18:02:03.056786 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 18:02:03.056836 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
918 18:02:03.056885 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
919 18:02:03.056935 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 18:02:03.056985 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 18:02:03.057034 ==
922 18:02:03.057083 Dram Type= 6, Freq= 0, CH_0, rank 0
923 18:02:03.057132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 18:02:03.057182 ==
925 18:02:03.057231 DQS Delay:
926 18:02:03.057281 DQS0 = 0, DQS1 = 0
927 18:02:03.057330 DQM Delay:
928 18:02:03.057380 DQM0 = 82, DQM1 = 72
929 18:02:03.057429 DQ Delay:
930 18:02:03.057478 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 18:02:03.057528 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 18:02:03.057577 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 18:02:03.057627 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
934 18:02:03.057676
935 18:02:03.057726
936 18:02:03.057774 ==
937 18:02:03.057824 Dram Type= 6, Freq= 0, CH_0, rank 0
938 18:02:03.057873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 18:02:03.057923 ==
940 18:02:03.057972
941 18:02:03.058020
942 18:02:03.058068 TX Vref Scan disable
943 18:02:03.058117 == TX Byte 0 ==
944 18:02:03.058166 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
945 18:02:03.058224 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
946 18:02:03.058276 == TX Byte 1 ==
947 18:02:03.058337 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
948 18:02:03.058388 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
949 18:02:03.058438 ==
950 18:02:03.058488 Dram Type= 6, Freq= 0, CH_0, rank 0
951 18:02:03.058538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 18:02:03.058587 ==
953 18:02:03.058638 TX Vref=22, minBit 0, minWin=27, winSum=441
954 18:02:03.058688 TX Vref=24, minBit 4, minWin=27, winSum=448
955 18:02:03.058739 TX Vref=26, minBit 4, minWin=27, winSum=454
956 18:02:03.058789 TX Vref=28, minBit 2, minWin=28, winSum=457
957 18:02:03.058839 TX Vref=30, minBit 0, minWin=28, winSum=457
958 18:02:03.058889 TX Vref=32, minBit 0, minWin=28, winSum=453
959 18:02:03.058938 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 28
960 18:02:03.058988
961 18:02:03.059040 Final TX Range 1 Vref 28
962 18:02:03.059091
963 18:02:03.059140 ==
964 18:02:03.059189 Dram Type= 6, Freq= 0, CH_0, rank 0
965 18:02:03.059239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 18:02:03.059289 ==
967 18:02:03.059338
968 18:02:03.059387
969 18:02:03.059436 TX Vref Scan disable
970 18:02:03.059485 == TX Byte 0 ==
971 18:02:03.059534 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
972 18:02:03.059585 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
973 18:02:03.059634 == TX Byte 1 ==
974 18:02:03.059682 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
975 18:02:03.059733 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
976 18:02:03.059782
977 18:02:03.059831 [DATLAT]
978 18:02:03.059880 Freq=800, CH0 RK0
979 18:02:03.059930
980 18:02:03.059979 DATLAT Default: 0xa
981 18:02:03.060029 0, 0xFFFF, sum = 0
982 18:02:03.060079 1, 0xFFFF, sum = 0
983 18:02:03.060130 2, 0xFFFF, sum = 0
984 18:02:03.060179 3, 0xFFFF, sum = 0
985 18:02:03.060231 4, 0xFFFF, sum = 0
986 18:02:03.060281 5, 0xFFFF, sum = 0
987 18:02:03.060340 6, 0xFFFF, sum = 0
988 18:02:03.060405 7, 0xFFFF, sum = 0
989 18:02:03.060492 8, 0x0, sum = 1
990 18:02:03.060546 9, 0x0, sum = 2
991 18:02:03.060597 10, 0x0, sum = 3
992 18:02:03.060648 11, 0x0, sum = 4
993 18:02:03.060698 best_step = 9
994 18:02:03.060748
995 18:02:03.060797 ==
996 18:02:03.060847 Dram Type= 6, Freq= 0, CH_0, rank 0
997 18:02:03.060896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 18:02:03.060947 ==
999 18:02:03.060996 RX Vref Scan: 1
1000 18:02:03.061044
1001 18:02:03.061093 Set Vref Range= 32 -> 127
1002 18:02:03.061141
1003 18:02:03.061191 RX Vref 32 -> 127, step: 1
1004 18:02:03.061260
1005 18:02:03.061351 RX Delay -111 -> 252, step: 8
1006 18:02:03.061406
1007 18:02:03.061456 Set Vref, RX VrefLevel [Byte0]: 32
1008 18:02:03.061519 [Byte1]: 32
1009 18:02:03.061568
1010 18:02:03.061617 Set Vref, RX VrefLevel [Byte0]: 33
1011 18:02:03.061667 [Byte1]: 33
1012 18:02:03.061716
1013 18:02:03.061763 Set Vref, RX VrefLevel [Byte0]: 34
1014 18:02:03.061812 [Byte1]: 34
1015 18:02:03.061860
1016 18:02:03.061908 Set Vref, RX VrefLevel [Byte0]: 35
1017 18:02:03.061957 [Byte1]: 35
1018 18:02:03.062006
1019 18:02:03.062054 Set Vref, RX VrefLevel [Byte0]: 36
1020 18:02:03.062102 [Byte1]: 36
1021 18:02:03.062152
1022 18:02:03.062202 Set Vref, RX VrefLevel [Byte0]: 37
1023 18:02:03.062294 [Byte1]: 37
1024 18:02:03.062344
1025 18:02:03.062392 Set Vref, RX VrefLevel [Byte0]: 38
1026 18:02:03.062441 [Byte1]: 38
1027 18:02:03.062490
1028 18:02:03.062538 Set Vref, RX VrefLevel [Byte0]: 39
1029 18:02:03.062587 [Byte1]: 39
1030 18:02:03.062635
1031 18:02:03.062875 Set Vref, RX VrefLevel [Byte0]: 40
1032 18:02:03.062933 [Byte1]: 40
1033 18:02:03.062983
1034 18:02:03.063031 Set Vref, RX VrefLevel [Byte0]: 41
1035 18:02:03.063080 [Byte1]: 41
1036 18:02:03.063128
1037 18:02:03.063177 Set Vref, RX VrefLevel [Byte0]: 42
1038 18:02:03.063227 [Byte1]: 42
1039 18:02:03.063275
1040 18:02:03.063324 Set Vref, RX VrefLevel [Byte0]: 43
1041 18:02:03.063373 [Byte1]: 43
1042 18:02:03.063422
1043 18:02:03.063470 Set Vref, RX VrefLevel [Byte0]: 44
1044 18:02:03.063518 [Byte1]: 44
1045 18:02:03.063567
1046 18:02:03.063615 Set Vref, RX VrefLevel [Byte0]: 45
1047 18:02:03.063664 [Byte1]: 45
1048 18:02:03.063712
1049 18:02:03.063760 Set Vref, RX VrefLevel [Byte0]: 46
1050 18:02:03.063808 [Byte1]: 46
1051 18:02:03.063857
1052 18:02:03.063905 Set Vref, RX VrefLevel [Byte0]: 47
1053 18:02:03.063954 [Byte1]: 47
1054 18:02:03.064002
1055 18:02:03.064049 Set Vref, RX VrefLevel [Byte0]: 48
1056 18:02:03.064098 [Byte1]: 48
1057 18:02:03.064146
1058 18:02:03.064194 Set Vref, RX VrefLevel [Byte0]: 49
1059 18:02:03.064243 [Byte1]: 49
1060 18:02:03.064292
1061 18:02:03.064340 Set Vref, RX VrefLevel [Byte0]: 50
1062 18:02:03.064388 [Byte1]: 50
1063 18:02:03.064435
1064 18:02:03.064483 Set Vref, RX VrefLevel [Byte0]: 51
1065 18:02:03.064531 [Byte1]: 51
1066 18:02:03.064578
1067 18:02:03.064627 Set Vref, RX VrefLevel [Byte0]: 52
1068 18:02:03.064675 [Byte1]: 52
1069 18:02:03.064723
1070 18:02:03.064771 Set Vref, RX VrefLevel [Byte0]: 53
1071 18:02:03.064819 [Byte1]: 53
1072 18:02:03.064867
1073 18:02:03.064915 Set Vref, RX VrefLevel [Byte0]: 54
1074 18:02:03.064980 [Byte1]: 54
1075 18:02:03.065043
1076 18:02:03.065091 Set Vref, RX VrefLevel [Byte0]: 55
1077 18:02:03.065140 [Byte1]: 55
1078 18:02:03.065189
1079 18:02:03.065237 Set Vref, RX VrefLevel [Byte0]: 56
1080 18:02:03.065285 [Byte1]: 56
1081 18:02:03.065334
1082 18:02:03.065382 Set Vref, RX VrefLevel [Byte0]: 57
1083 18:02:03.065430 [Byte1]: 57
1084 18:02:03.065478
1085 18:02:03.065526 Set Vref, RX VrefLevel [Byte0]: 58
1086 18:02:03.065574 [Byte1]: 58
1087 18:02:03.065623
1088 18:02:03.065671 Set Vref, RX VrefLevel [Byte0]: 59
1089 18:02:03.065720 [Byte1]: 59
1090 18:02:03.065768
1091 18:02:03.065816 Set Vref, RX VrefLevel [Byte0]: 60
1092 18:02:03.065864 [Byte1]: 60
1093 18:02:03.065912
1094 18:02:03.065959 Set Vref, RX VrefLevel [Byte0]: 61
1095 18:02:03.066007 [Byte1]: 61
1096 18:02:03.066056
1097 18:02:03.066103 Set Vref, RX VrefLevel [Byte0]: 62
1098 18:02:03.066151 [Byte1]: 62
1099 18:02:03.066200
1100 18:02:03.066292 Set Vref, RX VrefLevel [Byte0]: 63
1101 18:02:03.066343 [Byte1]: 63
1102 18:02:03.066391
1103 18:02:03.066439 Set Vref, RX VrefLevel [Byte0]: 64
1104 18:02:03.066487 [Byte1]: 64
1105 18:02:03.066535
1106 18:02:03.066583 Set Vref, RX VrefLevel [Byte0]: 65
1107 18:02:03.066632 [Byte1]: 65
1108 18:02:03.066680
1109 18:02:03.066728 Set Vref, RX VrefLevel [Byte0]: 66
1110 18:02:03.066777 [Byte1]: 66
1111 18:02:03.066825
1112 18:02:03.066873 Set Vref, RX VrefLevel [Byte0]: 67
1113 18:02:03.066920 [Byte1]: 67
1114 18:02:03.066968
1115 18:02:03.067016 Set Vref, RX VrefLevel [Byte0]: 68
1116 18:02:03.067064 [Byte1]: 68
1117 18:02:03.067113
1118 18:02:03.067161 Set Vref, RX VrefLevel [Byte0]: 69
1119 18:02:03.067210 [Byte1]: 69
1120 18:02:03.067257
1121 18:02:03.067305 Set Vref, RX VrefLevel [Byte0]: 70
1122 18:02:03.067353 [Byte1]: 70
1123 18:02:03.067401
1124 18:02:03.067448 Set Vref, RX VrefLevel [Byte0]: 71
1125 18:02:03.067496 [Byte1]: 71
1126 18:02:03.067544
1127 18:02:03.067592 Set Vref, RX VrefLevel [Byte0]: 72
1128 18:02:03.067640 [Byte1]: 72
1129 18:02:03.067689
1130 18:02:03.067737 Final RX Vref Byte 0 = 50 to rank0
1131 18:02:03.067786 Final RX Vref Byte 1 = 54 to rank0
1132 18:02:03.067836 Final RX Vref Byte 0 = 50 to rank1
1133 18:02:03.067884 Final RX Vref Byte 1 = 54 to rank1==
1134 18:02:03.067932 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 18:02:03.067981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1136 18:02:03.068030 ==
1137 18:02:03.068079 DQS Delay:
1138 18:02:03.068126 DQS0 = 0, DQS1 = 0
1139 18:02:03.068175 DQM Delay:
1140 18:02:03.068223 DQM0 = 84, DQM1 = 73
1141 18:02:03.068271 DQ Delay:
1142 18:02:03.068319 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1143 18:02:03.068368 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1144 18:02:03.068416 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1145 18:02:03.068464 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1146 18:02:03.068512
1147 18:02:03.068559
1148 18:02:03.068607 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1149 18:02:03.068657 CH0 RK0: MR19=606, MR18=3838
1150 18:02:03.068705 CH0_RK0: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1151 18:02:03.068754
1152 18:02:03.068801 ----->DramcWriteLeveling(PI) begin...
1153 18:02:03.068850 ==
1154 18:02:03.068898 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 18:02:03.068947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1156 18:02:03.068995 ==
1157 18:02:03.069044 Write leveling (Byte 0): 30 => 30
1158 18:02:03.069092 Write leveling (Byte 1): 28 => 28
1159 18:02:03.069140 DramcWriteLeveling(PI) end<-----
1160 18:02:03.069188
1161 18:02:03.069236 ==
1162 18:02:03.069283 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 18:02:03.069332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1164 18:02:03.069381 ==
1165 18:02:03.069429 [Gating] SW mode calibration
1166 18:02:03.069478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 18:02:03.069527 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 18:02:03.069577 0 6 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
1169 18:02:03.069626 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 18:02:03.069674 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:02:03.069723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:02:03.069771 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:02:03.069821 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:02:03.069870 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:02:03.069918 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 18:02:03.070154 0 7 0 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
1177 18:02:03.070235 0 7 4 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
1178 18:02:03.070303 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1179 18:02:03.070353 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1180 18:02:03.070402 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 18:02:03.070469 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 18:02:03.070533 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 18:02:03.070581 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 18:02:03.070647 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1185 18:02:03.070712 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1186 18:02:03.070792 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1187 18:02:03.070841 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 18:02:03.070890 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 18:02:03.070938 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 18:02:03.070987 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 18:02:03.071035 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 18:02:03.071084 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 18:02:03.071132 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 18:02:03.071181 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 18:02:03.071229 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 18:02:03.071278 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 18:02:03.071326 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 18:02:03.071374 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 18:02:03.071424 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 18:02:03.071473 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 18:02:03.071521 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 18:02:03.071569 Total UI for P1: 0, mck2ui 16
1203 18:02:03.071618 best dqsien dly found for B0: ( 0, 10, 2)
1204 18:02:03.071667 Total UI for P1: 0, mck2ui 16
1205 18:02:03.071716 best dqsien dly found for B1: ( 0, 10, 2)
1206 18:02:03.071765 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1207 18:02:03.071813 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1208 18:02:03.071861
1209 18:02:03.071910 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1210 18:02:03.071958 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1211 18:02:03.072006 [Gating] SW calibration Done
1212 18:02:03.072054 ==
1213 18:02:03.072103 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 18:02:03.072152 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1215 18:02:03.072201 ==
1216 18:02:03.072249 RX Vref Scan: 0
1217 18:02:03.072297
1218 18:02:03.072346 RX Vref 0 -> 0, step: 1
1219 18:02:03.072394
1220 18:02:03.072442 RX Delay -130 -> 252, step: 16
1221 18:02:03.072491 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1222 18:02:03.072541 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1223 18:02:03.072589 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1224 18:02:03.072638 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1225 18:02:03.072686 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1226 18:02:03.072735 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1227 18:02:03.072784 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1228 18:02:03.072832 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1229 18:02:03.072880 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1230 18:02:03.072928 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1231 18:02:03.072977 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1232 18:02:03.073026 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1233 18:02:03.073074 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1234 18:02:03.073122 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1235 18:02:03.073171 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1236 18:02:03.073220 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1237 18:02:03.073268 ==
1238 18:02:03.073315 Dram Type= 6, Freq= 0, CH_0, rank 1
1239 18:02:03.073363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1240 18:02:03.073412 ==
1241 18:02:03.073460 DQS Delay:
1242 18:02:03.073508 DQS0 = 0, DQS1 = 0
1243 18:02:03.073557 DQM Delay:
1244 18:02:03.073605 DQM0 = 82, DQM1 = 74
1245 18:02:03.073653 DQ Delay:
1246 18:02:03.073702 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1247 18:02:03.073750 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1248 18:02:03.073798 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1249 18:02:03.073846 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1250 18:02:03.073895
1251 18:02:03.073942
1252 18:02:03.073990 ==
1253 18:02:03.074038 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 18:02:03.074086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1255 18:02:03.074135 ==
1256 18:02:03.074184
1257 18:02:03.074272
1258 18:02:03.074321 TX Vref Scan disable
1259 18:02:03.074370 == TX Byte 0 ==
1260 18:02:03.074419 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1261 18:02:03.074468 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1262 18:02:03.074517 == TX Byte 1 ==
1263 18:02:03.074565 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1264 18:02:03.074614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1265 18:02:03.074663 ==
1266 18:02:03.074711 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 18:02:03.074759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1268 18:02:03.074807 ==
1269 18:02:03.074856 TX Vref=22, minBit 0, minWin=27, winSum=445
1270 18:02:03.074905 TX Vref=24, minBit 2, minWin=28, winSum=455
1271 18:02:03.074954 TX Vref=26, minBit 0, minWin=27, winSum=451
1272 18:02:03.075003 TX Vref=28, minBit 0, minWin=28, winSum=456
1273 18:02:03.075052 TX Vref=30, minBit 2, minWin=28, winSum=458
1274 18:02:03.075101 TX Vref=32, minBit 2, minWin=28, winSum=459
1275 18:02:03.075150 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1276 18:02:03.075198
1277 18:02:03.075247 Final TX Range 1 Vref 32
1278 18:02:03.075295
1279 18:02:03.075343 ==
1280 18:02:03.075391 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 18:02:03.075439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1282 18:02:03.075487 ==
1283 18:02:03.075536
1284 18:02:03.075584
1285 18:02:03.075631 TX Vref Scan disable
1286 18:02:03.075680 == TX Byte 0 ==
1287 18:02:03.075728 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1288 18:02:03.075777 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1289 18:02:03.075827 == TX Byte 1 ==
1290 18:02:03.075875 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1291 18:02:03.075924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1292 18:02:03.075973
1293 18:02:03.076021 [DATLAT]
1294 18:02:03.076069 Freq=800, CH0 RK1
1295 18:02:03.076117
1296 18:02:03.076359 DATLAT Default: 0x9
1297 18:02:03.076415 0, 0xFFFF, sum = 0
1298 18:02:03.076470 1, 0xFFFF, sum = 0
1299 18:02:03.076520 2, 0xFFFF, sum = 0
1300 18:02:03.076570 3, 0xFFFF, sum = 0
1301 18:02:03.076619 4, 0xFFFF, sum = 0
1302 18:02:03.076668 5, 0xFFFF, sum = 0
1303 18:02:03.076717 6, 0xFFFF, sum = 0
1304 18:02:03.076768 7, 0xFFFF, sum = 0
1305 18:02:03.076817 8, 0x0, sum = 1
1306 18:02:03.076867 9, 0x0, sum = 2
1307 18:02:03.076916 10, 0x0, sum = 3
1308 18:02:03.076966 11, 0x0, sum = 4
1309 18:02:03.077014 best_step = 9
1310 18:02:03.077063
1311 18:02:03.077111 ==
1312 18:02:03.077160 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 18:02:03.077209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1314 18:02:03.077259 ==
1315 18:02:03.077307 RX Vref Scan: 0
1316 18:02:03.077355
1317 18:02:03.077403 RX Vref 0 -> 0, step: 1
1318 18:02:03.077450
1319 18:02:03.077498 RX Delay -111 -> 252, step: 8
1320 18:02:03.077546 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1321 18:02:03.077595 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1322 18:02:03.077644 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1323 18:02:03.077692 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1324 18:02:03.077740 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1325 18:02:03.077789 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1326 18:02:03.077837 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1327 18:02:03.077885 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1328 18:02:03.077933 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1329 18:02:03.077982 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1330 18:02:03.078030 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1331 18:02:03.078079 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1332 18:02:03.078128 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1333 18:02:03.078177 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1334 18:02:03.078258 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1335 18:02:03.078323 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1336 18:02:03.078370 ==
1337 18:02:03.078418 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 18:02:03.078466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1339 18:02:03.078516 ==
1340 18:02:03.078565 DQS Delay:
1341 18:02:03.078613 DQS0 = 0, DQS1 = 0
1342 18:02:03.078661 DQM Delay:
1343 18:02:03.078709 DQM0 = 86, DQM1 = 74
1344 18:02:03.078757 DQ Delay:
1345 18:02:03.078805 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1346 18:02:03.078853 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1347 18:02:03.078900 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1348 18:02:03.078948 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1349 18:02:03.078996
1350 18:02:03.079044
1351 18:02:03.079092 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1352 18:02:03.079141 CH0 RK1: MR19=606, MR18=4747
1353 18:02:03.079190 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1354 18:02:03.079239 [RxdqsGatingPostProcess] freq 800
1355 18:02:03.079287 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1356 18:02:03.079336 Pre-setting of DQS Precalculation
1357 18:02:03.079384 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1358 18:02:03.079433 ==
1359 18:02:03.079481 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 18:02:03.079530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 18:02:03.079578 ==
1362 18:02:03.079626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1363 18:02:03.079674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1364 18:02:03.079721 [CA 0] Center 36 (6~67) winsize 62
1365 18:02:03.079769 [CA 1] Center 36 (5~67) winsize 63
1366 18:02:03.079816 [CA 2] Center 34 (4~65) winsize 62
1367 18:02:03.079864 [CA 3] Center 34 (4~64) winsize 61
1368 18:02:03.079912 [CA 4] Center 33 (2~64) winsize 63
1369 18:02:03.079959 [CA 5] Center 33 (3~64) winsize 62
1370 18:02:03.080006
1371 18:02:03.080053 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1372 18:02:03.080101
1373 18:02:03.080148 [CATrainingPosCal] consider 1 rank data
1374 18:02:03.080196 u2DelayCellTimex100 = 270/100 ps
1375 18:02:03.080243 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1376 18:02:03.080291 CA1 delay=36 (5~67),Diff = 3 PI (21 cell)
1377 18:02:03.080339 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1378 18:02:03.080387 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1379 18:02:03.080434 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1380 18:02:03.080482 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1381 18:02:03.080530
1382 18:02:03.080577 CA PerBit enable=1, Macro0, CA PI delay=33
1383 18:02:03.080624
1384 18:02:03.080671 [CBTSetCACLKResult] CA Dly = 33
1385 18:02:03.080719 CS Dly: 4 (0~35)
1386 18:02:03.080767 ==
1387 18:02:03.080815 Dram Type= 6, Freq= 0, CH_1, rank 1
1388 18:02:03.080863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1389 18:02:03.080911 ==
1390 18:02:03.080959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 18:02:03.081008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 18:02:03.081056 [CA 0] Center 36 (6~67) winsize 62
1393 18:02:03.081104 [CA 1] Center 36 (6~67) winsize 62
1394 18:02:03.081151 [CA 2] Center 34 (4~65) winsize 62
1395 18:02:03.081199 [CA 3] Center 34 (3~65) winsize 63
1396 18:02:03.081247 [CA 4] Center 33 (3~64) winsize 62
1397 18:02:03.081295 [CA 5] Center 33 (3~64) winsize 62
1398 18:02:03.081342
1399 18:02:03.081389 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1400 18:02:03.081438
1401 18:02:03.081485 [CATrainingPosCal] consider 2 rank data
1402 18:02:03.081533 u2DelayCellTimex100 = 270/100 ps
1403 18:02:03.081581 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1404 18:02:03.081629 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1405 18:02:03.081677 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1406 18:02:03.081725 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1407 18:02:03.081773 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1408 18:02:03.081820 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1409 18:02:03.081867
1410 18:02:03.081915 CA PerBit enable=1, Macro0, CA PI delay=33
1411 18:02:03.081962
1412 18:02:03.082009 [CBTSetCACLKResult] CA Dly = 33
1413 18:02:03.082057 CS Dly: 4 (0~36)
1414 18:02:03.082104
1415 18:02:03.082151 ----->DramcWriteLeveling(PI) begin...
1416 18:02:03.082199 ==
1417 18:02:03.082291 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 18:02:03.082339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1419 18:02:03.082388 ==
1420 18:02:03.082436 Write leveling (Byte 0): 22 => 22
1421 18:02:03.082484 Write leveling (Byte 1): 22 => 22
1422 18:02:03.082531 DramcWriteLeveling(PI) end<-----
1423 18:02:03.082579
1424 18:02:03.082627 ==
1425 18:02:03.082674 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 18:02:03.082722 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1427 18:02:03.082770 ==
1428 18:02:03.082818 [Gating] SW mode calibration
1429 18:02:03.083056 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1430 18:02:03.083114 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1431 18:02:03.083207 0 6 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
1432 18:02:03.083256 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1433 18:02:03.083305 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1434 18:02:03.083354 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1435 18:02:03.083402 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1436 18:02:03.083450 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1437 18:02:03.083499 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 18:02:03.083547 0 6 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
1439 18:02:03.083658 0 7 0 | B1->B0 | 3131 4343 | 0 1 | (0 0) (0 0)
1440 18:02:03.083707 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1441 18:02:03.083755 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1442 18:02:03.083803 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1443 18:02:03.083851 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1444 18:02:03.083899 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1445 18:02:03.083948 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1446 18:02:03.083995 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1447 18:02:03.084043 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1448 18:02:03.084091 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1449 18:02:03.084139 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1450 18:02:03.084187 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1451 18:02:03.084235 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1452 18:02:03.084283 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1453 18:02:03.084330 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 18:02:03.084378 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 18:02:03.084425 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 18:02:03.084473 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 18:02:03.084521 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 18:02:03.084569 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 18:02:03.084617 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 18:02:03.084665 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 18:02:03.084714 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 18:02:03.084761 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1463 18:02:03.084809 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1464 18:02:03.084857 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1465 18:02:03.084905 Total UI for P1: 0, mck2ui 16
1466 18:02:03.084954 best dqsien dly found for B0: ( 0, 9, 30)
1467 18:02:03.085001 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1468 18:02:03.085049 Total UI for P1: 0, mck2ui 16
1469 18:02:03.085097 best dqsien dly found for B1: ( 0, 10, 2)
1470 18:02:03.085145 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1471 18:02:03.085200 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1472 18:02:03.085257
1473 18:02:03.085307 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1474 18:02:03.085356 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1475 18:02:03.085404 [Gating] SW calibration Done
1476 18:02:03.085452 ==
1477 18:02:03.085499 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 18:02:03.085547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1479 18:02:03.085596 ==
1480 18:02:03.085643 RX Vref Scan: 0
1481 18:02:03.085690
1482 18:02:03.085738 RX Vref 0 -> 0, step: 1
1483 18:02:03.085785
1484 18:02:03.085833 RX Delay -130 -> 252, step: 16
1485 18:02:03.085881 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1486 18:02:03.085929 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1487 18:02:03.085977 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1488 18:02:03.086025 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1489 18:02:03.086072 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1490 18:02:03.086119 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1491 18:02:03.086166 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1492 18:02:03.086223 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1493 18:02:03.086306 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1494 18:02:03.086355 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1495 18:02:03.086403 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1496 18:02:03.086451 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1497 18:02:03.086500 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1498 18:02:03.086547 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1499 18:02:03.086594 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1500 18:02:03.086642 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1501 18:02:03.086690 ==
1502 18:02:03.086737 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 18:02:03.086799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1504 18:02:03.086850 ==
1505 18:02:03.086897 DQS Delay:
1506 18:02:03.086945 DQS0 = 0, DQS1 = 0
1507 18:02:03.086993 DQM Delay:
1508 18:02:03.087040 DQM0 = 80, DQM1 = 70
1509 18:02:03.087088 DQ Delay:
1510 18:02:03.087136 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1511 18:02:03.087184 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1512 18:02:03.087232 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1513 18:02:03.087280 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1514 18:02:03.087328
1515 18:02:03.087375
1516 18:02:03.087423 ==
1517 18:02:03.087470 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 18:02:03.087517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 18:02:03.087564 ==
1520 18:02:03.087612
1521 18:02:03.087659
1522 18:02:03.087707 TX Vref Scan disable
1523 18:02:03.087754 == TX Byte 0 ==
1524 18:02:03.087801 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1525 18:02:03.087850 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1526 18:02:03.087897 == TX Byte 1 ==
1527 18:02:03.087944 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1528 18:02:03.087992 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1529 18:02:03.088040 ==
1530 18:02:03.088087 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 18:02:03.088135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1532 18:02:03.088183 ==
1533 18:02:03.088230 TX Vref=22, minBit 0, minWin=28, winSum=457
1534 18:02:03.088279 TX Vref=24, minBit 1, minWin=28, winSum=459
1535 18:02:03.088328 TX Vref=26, minBit 3, minWin=28, winSum=461
1536 18:02:03.088562 TX Vref=28, minBit 3, minWin=28, winSum=462
1537 18:02:03.088616 TX Vref=30, minBit 9, minWin=28, winSum=465
1538 18:02:03.088666 TX Vref=32, minBit 6, minWin=28, winSum=463
1539 18:02:03.088715 [TxChooseVref] Worse bit 9, Min win 28, Win sum 465, Final Vref 30
1540 18:02:03.088764
1541 18:02:03.088815 Final TX Range 1 Vref 30
1542 18:02:03.088895
1543 18:02:03.088962 ==
1544 18:02:03.089012 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 18:02:03.089061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1546 18:02:03.089110 ==
1547 18:02:03.089157
1548 18:02:03.089205
1549 18:02:03.089253 TX Vref Scan disable
1550 18:02:03.089300 == TX Byte 0 ==
1551 18:02:03.089348 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1552 18:02:03.089396 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1553 18:02:03.089444 == TX Byte 1 ==
1554 18:02:03.089492 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1555 18:02:03.089541 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1556 18:02:03.089589
1557 18:02:03.089637 [DATLAT]
1558 18:02:03.089684 Freq=800, CH1 RK0
1559 18:02:03.089731
1560 18:02:03.089778 DATLAT Default: 0xa
1561 18:02:03.089827 0, 0xFFFF, sum = 0
1562 18:02:03.089876 1, 0xFFFF, sum = 0
1563 18:02:03.089925 2, 0xFFFF, sum = 0
1564 18:02:03.089973 3, 0xFFFF, sum = 0
1565 18:02:03.090022 4, 0xFFFF, sum = 0
1566 18:02:03.090070 5, 0xFFFF, sum = 0
1567 18:02:03.090119 6, 0xFFFF, sum = 0
1568 18:02:03.090167 7, 0xFFFF, sum = 0
1569 18:02:03.090225 8, 0x0, sum = 1
1570 18:02:03.090276 9, 0x0, sum = 2
1571 18:02:03.090326 10, 0x0, sum = 3
1572 18:02:03.090374 11, 0x0, sum = 4
1573 18:02:03.090422 best_step = 9
1574 18:02:03.090469
1575 18:02:03.090516 ==
1576 18:02:03.090562 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 18:02:03.090610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1578 18:02:03.090659 ==
1579 18:02:03.090707 RX Vref Scan: 1
1580 18:02:03.090755
1581 18:02:03.090802 Set Vref Range= 32 -> 127
1582 18:02:03.090849
1583 18:02:03.090897 RX Vref 32 -> 127, step: 1
1584 18:02:03.090944
1585 18:02:03.090992 RX Delay -111 -> 252, step: 8
1586 18:02:03.091040
1587 18:02:03.091087 Set Vref, RX VrefLevel [Byte0]: 32
1588 18:02:03.091135 [Byte1]: 32
1589 18:02:03.091182
1590 18:02:03.091230 Set Vref, RX VrefLevel [Byte0]: 33
1591 18:02:03.091278 [Byte1]: 33
1592 18:02:03.091326
1593 18:02:03.091373 Set Vref, RX VrefLevel [Byte0]: 34
1594 18:02:03.091421 [Byte1]: 34
1595 18:02:03.091469
1596 18:02:03.091516 Set Vref, RX VrefLevel [Byte0]: 35
1597 18:02:03.091563 [Byte1]: 35
1598 18:02:03.091610
1599 18:02:03.091657 Set Vref, RX VrefLevel [Byte0]: 36
1600 18:02:03.091705 [Byte1]: 36
1601 18:02:03.091753
1602 18:02:03.091801 Set Vref, RX VrefLevel [Byte0]: 37
1603 18:02:03.091848 [Byte1]: 37
1604 18:02:03.091895
1605 18:02:03.091943 Set Vref, RX VrefLevel [Byte0]: 38
1606 18:02:03.091991 [Byte1]: 38
1607 18:02:03.092037
1608 18:02:03.092084 Set Vref, RX VrefLevel [Byte0]: 39
1609 18:02:03.092131 [Byte1]: 39
1610 18:02:03.092179
1611 18:02:03.092226 Set Vref, RX VrefLevel [Byte0]: 40
1612 18:02:03.092274 [Byte1]: 40
1613 18:02:03.092322
1614 18:02:03.092369 Set Vref, RX VrefLevel [Byte0]: 41
1615 18:02:03.092416 [Byte1]: 41
1616 18:02:03.092464
1617 18:02:03.092511 Set Vref, RX VrefLevel [Byte0]: 42
1618 18:02:03.092558 [Byte1]: 42
1619 18:02:03.092606
1620 18:02:03.092653 Set Vref, RX VrefLevel [Byte0]: 43
1621 18:02:03.092701 [Byte1]: 43
1622 18:02:03.092749
1623 18:02:03.092796 Set Vref, RX VrefLevel [Byte0]: 44
1624 18:02:03.092843 [Byte1]: 44
1625 18:02:03.092891
1626 18:02:03.092938 Set Vref, RX VrefLevel [Byte0]: 45
1627 18:02:03.092986 [Byte1]: 45
1628 18:02:03.093033
1629 18:02:03.093080 Set Vref, RX VrefLevel [Byte0]: 46
1630 18:02:03.093128 [Byte1]: 46
1631 18:02:03.093176
1632 18:02:03.093223 Set Vref, RX VrefLevel [Byte0]: 47
1633 18:02:03.093271 [Byte1]: 47
1634 18:02:03.093319
1635 18:02:03.093366 Set Vref, RX VrefLevel [Byte0]: 48
1636 18:02:03.093414 [Byte1]: 48
1637 18:02:03.093461
1638 18:02:03.093508 Set Vref, RX VrefLevel [Byte0]: 49
1639 18:02:03.093555 [Byte1]: 49
1640 18:02:03.093603
1641 18:02:03.093651 Set Vref, RX VrefLevel [Byte0]: 50
1642 18:02:03.093699 [Byte1]: 50
1643 18:02:03.093747
1644 18:02:03.093794 Set Vref, RX VrefLevel [Byte0]: 51
1645 18:02:03.093841 [Byte1]: 51
1646 18:02:03.093888
1647 18:02:03.093936 Set Vref, RX VrefLevel [Byte0]: 52
1648 18:02:03.093983 [Byte1]: 52
1649 18:02:03.094030
1650 18:02:03.094076 Set Vref, RX VrefLevel [Byte0]: 53
1651 18:02:03.094123 [Byte1]: 53
1652 18:02:03.094170
1653 18:02:03.094221 Set Vref, RX VrefLevel [Byte0]: 54
1654 18:02:03.094310 [Byte1]: 54
1655 18:02:03.094357
1656 18:02:03.094404 Set Vref, RX VrefLevel [Byte0]: 55
1657 18:02:03.094452 [Byte1]: 55
1658 18:02:03.094499
1659 18:02:03.094546 Set Vref, RX VrefLevel [Byte0]: 56
1660 18:02:03.094593 [Byte1]: 56
1661 18:02:03.094641
1662 18:02:03.094688 Set Vref, RX VrefLevel [Byte0]: 57
1663 18:02:03.094736 [Byte1]: 57
1664 18:02:03.094783
1665 18:02:03.094831 Set Vref, RX VrefLevel [Byte0]: 58
1666 18:02:03.094878 [Byte1]: 58
1667 18:02:03.094925
1668 18:02:03.094972 Set Vref, RX VrefLevel [Byte0]: 59
1669 18:02:03.095019 [Byte1]: 59
1670 18:02:03.095065
1671 18:02:03.095112 Set Vref, RX VrefLevel [Byte0]: 60
1672 18:02:03.095160 [Byte1]: 60
1673 18:02:03.095207
1674 18:02:03.095254 Set Vref, RX VrefLevel [Byte0]: 61
1675 18:02:03.095303 [Byte1]: 61
1676 18:02:03.095350
1677 18:02:03.095397 Set Vref, RX VrefLevel [Byte0]: 62
1678 18:02:03.095443 [Byte1]: 62
1679 18:02:03.095490
1680 18:02:03.095537 Set Vref, RX VrefLevel [Byte0]: 63
1681 18:02:03.095584 [Byte1]: 63
1682 18:02:03.095632
1683 18:02:03.095680 Set Vref, RX VrefLevel [Byte0]: 64
1684 18:02:03.095728 [Byte1]: 64
1685 18:02:03.095776
1686 18:02:03.095822 Set Vref, RX VrefLevel [Byte0]: 65
1687 18:02:03.095870 [Byte1]: 65
1688 18:02:03.095917
1689 18:02:03.095965 Set Vref, RX VrefLevel [Byte0]: 66
1690 18:02:03.096012 [Byte1]: 66
1691 18:02:03.096059
1692 18:02:03.096106 Set Vref, RX VrefLevel [Byte0]: 67
1693 18:02:03.096153 [Byte1]: 67
1694 18:02:03.096201
1695 18:02:03.096248 Set Vref, RX VrefLevel [Byte0]: 68
1696 18:02:03.096295 [Byte1]: 68
1697 18:02:03.096343
1698 18:02:03.096390 Set Vref, RX VrefLevel [Byte0]: 69
1699 18:02:03.096437 [Byte1]: 69
1700 18:02:03.096484
1701 18:02:03.096531 Set Vref, RX VrefLevel [Byte0]: 70
1702 18:02:03.096578 [Byte1]: 70
1703 18:02:03.096626
1704 18:02:03.096674 Set Vref, RX VrefLevel [Byte0]: 71
1705 18:02:03.096910 [Byte1]: 71
1706 18:02:03.096964
1707 18:02:03.097012 Set Vref, RX VrefLevel [Byte0]: 72
1708 18:02:03.097060 [Byte1]: 72
1709 18:02:03.097107
1710 18:02:03.097155 Set Vref, RX VrefLevel [Byte0]: 73
1711 18:02:03.097203 [Byte1]: 73
1712 18:02:03.097251
1713 18:02:03.097298 Set Vref, RX VrefLevel [Byte0]: 74
1714 18:02:03.097346 [Byte1]: 74
1715 18:02:03.097394
1716 18:02:03.097442 Final RX Vref Byte 0 = 59 to rank0
1717 18:02:03.097491 Final RX Vref Byte 1 = 52 to rank0
1718 18:02:03.097539 Final RX Vref Byte 0 = 59 to rank1
1719 18:02:03.097586 Final RX Vref Byte 1 = 52 to rank1==
1720 18:02:03.097634 Dram Type= 6, Freq= 0, CH_1, rank 0
1721 18:02:03.097682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1722 18:02:03.097731 ==
1723 18:02:03.097778 DQS Delay:
1724 18:02:03.097826 DQS0 = 0, DQS1 = 0
1725 18:02:03.097874 DQM Delay:
1726 18:02:03.097922 DQM0 = 79, DQM1 = 71
1727 18:02:03.097970 DQ Delay:
1728 18:02:03.098017 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1729 18:02:03.098064 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1730 18:02:03.098111 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1731 18:02:03.098160 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1732 18:02:03.098208
1733 18:02:03.098261
1734 18:02:03.098309 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1735 18:02:03.098358 CH1 RK0: MR19=606, MR18=4B4B
1736 18:02:03.098406 CH1_RK0: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1737 18:02:03.098453
1738 18:02:03.098500 ----->DramcWriteLeveling(PI) begin...
1739 18:02:03.098549 ==
1740 18:02:03.098597 Dram Type= 6, Freq= 0, CH_1, rank 1
1741 18:02:03.098645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 18:02:03.098693 ==
1743 18:02:03.098740 Write leveling (Byte 0): 25 => 25
1744 18:02:03.098788 Write leveling (Byte 1): 25 => 25
1745 18:02:03.098836 DramcWriteLeveling(PI) end<-----
1746 18:02:03.098883
1747 18:02:03.098930 ==
1748 18:02:03.098977 Dram Type= 6, Freq= 0, CH_1, rank 1
1749 18:02:03.099025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1750 18:02:03.099073 ==
1751 18:02:03.099121 [Gating] SW mode calibration
1752 18:02:03.099169 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1753 18:02:03.099218 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1754 18:02:03.099266 0 6 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
1755 18:02:03.099315 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1756 18:02:03.099362 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1757 18:02:03.099410 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1758 18:02:03.099457 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1759 18:02:03.099506 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1760 18:02:03.099554 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1761 18:02:03.099602 0 6 28 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
1762 18:02:03.099650 0 7 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1763 18:02:03.099698 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1764 18:02:03.099746 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1765 18:02:03.099793 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1766 18:02:03.099841 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1767 18:02:03.099889 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1768 18:02:03.099938 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1769 18:02:03.099985 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1770 18:02:03.100033 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1771 18:02:03.100081 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1772 18:02:03.100129 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1773 18:02:03.100176 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1774 18:02:03.100224 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1775 18:02:03.100272 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1776 18:02:03.100319 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1777 18:02:03.100368 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 18:02:03.100415 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 18:02:03.100463 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 18:02:03.100512 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 18:02:03.100560 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 18:02:03.100607 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 18:02:03.100655 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 18:02:03.100703 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 18:02:03.100751 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1786 18:02:03.100799 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1787 18:02:03.100848 Total UI for P1: 0, mck2ui 16
1788 18:02:03.100896 best dqsien dly found for B0: ( 0, 9, 28)
1789 18:02:03.100944 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1790 18:02:03.100991 Total UI for P1: 0, mck2ui 16
1791 18:02:03.101039 best dqsien dly found for B1: ( 0, 10, 0)
1792 18:02:03.101086 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1793 18:02:03.101134 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1794 18:02:03.101182
1795 18:02:03.101229 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1796 18:02:03.101278 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1797 18:02:03.101325 [Gating] SW calibration Done
1798 18:02:03.101373 ==
1799 18:02:03.101421 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 18:02:03.101468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1801 18:02:03.101517 ==
1802 18:02:03.101564 RX Vref Scan: 0
1803 18:02:03.101611
1804 18:02:03.101658 RX Vref 0 -> 0, step: 1
1805 18:02:03.101706
1806 18:02:03.101753 RX Delay -130 -> 252, step: 16
1807 18:02:03.101800 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1808 18:02:03.101848 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1809 18:02:03.101896 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1810 18:02:03.101943 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1811 18:02:03.101991 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1812 18:02:03.102038 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1813 18:02:03.102086 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1814 18:02:03.102133 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1815 18:02:03.102181 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1816 18:02:03.102456 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1817 18:02:03.102514 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1818 18:02:03.102563 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1819 18:02:03.102612 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1820 18:02:03.102660 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1821 18:02:03.102708 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1822 18:02:03.102757 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1823 18:02:03.102804 ==
1824 18:02:03.102852 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 18:02:03.102901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1826 18:02:03.102948 ==
1827 18:02:03.102996 DQS Delay:
1828 18:02:03.103044 DQS0 = 0, DQS1 = 0
1829 18:02:03.103092 DQM Delay:
1830 18:02:03.103140 DQM0 = 80, DQM1 = 70
1831 18:02:03.103188 DQ Delay:
1832 18:02:03.103236 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1833 18:02:03.103284 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1834 18:02:03.103331 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =69
1835 18:02:03.103380 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1836 18:02:03.103427
1837 18:02:03.103475
1838 18:02:03.103522 ==
1839 18:02:03.103571 Dram Type= 6, Freq= 0, CH_1, rank 1
1840 18:02:03.103619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1841 18:02:03.103668 ==
1842 18:02:03.103715
1843 18:02:03.103763
1844 18:02:03.103811 TX Vref Scan disable
1845 18:02:03.103860 == TX Byte 0 ==
1846 18:02:03.103907 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1847 18:02:03.103955 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1848 18:02:03.104003 == TX Byte 1 ==
1849 18:02:03.104050 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1850 18:02:03.104098 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1851 18:02:03.104146 ==
1852 18:02:03.104195 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 18:02:03.104243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1854 18:02:03.104291 ==
1855 18:02:03.104339 TX Vref=22, minBit 13, minWin=27, winSum=449
1856 18:02:03.104387 TX Vref=24, minBit 0, minWin=28, winSum=455
1857 18:02:03.104435 TX Vref=26, minBit 1, minWin=28, winSum=456
1858 18:02:03.104483 TX Vref=28, minBit 0, minWin=28, winSum=458
1859 18:02:03.104532 TX Vref=30, minBit 0, minWin=28, winSum=457
1860 18:02:03.104580 TX Vref=32, minBit 0, minWin=28, winSum=454
1861 18:02:03.104627 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1862 18:02:03.104676
1863 18:02:03.104724 Final TX Range 1 Vref 28
1864 18:02:03.104771
1865 18:02:03.104818 ==
1866 18:02:03.104865 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 18:02:03.104913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1868 18:02:03.104961 ==
1869 18:02:03.105009
1870 18:02:03.105055
1871 18:02:03.105103 TX Vref Scan disable
1872 18:02:03.105151 == TX Byte 0 ==
1873 18:02:03.105199 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1874 18:02:03.105247 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1875 18:02:03.105294 == TX Byte 1 ==
1876 18:02:03.105341 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1877 18:02:03.105390 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1878 18:02:03.105438
1879 18:02:03.105485 [DATLAT]
1880 18:02:03.105533 Freq=800, CH1 RK1
1881 18:02:03.105580
1882 18:02:03.105627 DATLAT Default: 0x9
1883 18:02:03.105674 0, 0xFFFF, sum = 0
1884 18:02:03.105723 1, 0xFFFF, sum = 0
1885 18:02:03.105771 2, 0xFFFF, sum = 0
1886 18:02:03.105843 3, 0xFFFF, sum = 0
1887 18:02:03.105922 4, 0xFFFF, sum = 0
1888 18:02:03.105999 5, 0xFFFF, sum = 0
1889 18:02:03.106050 6, 0xFFFF, sum = 0
1890 18:02:03.106099 7, 0xFFFF, sum = 0
1891 18:02:03.106148 8, 0x0, sum = 1
1892 18:02:03.106197 9, 0x0, sum = 2
1893 18:02:03.106256 10, 0x0, sum = 3
1894 18:02:03.106307 11, 0x0, sum = 4
1895 18:02:03.106356 best_step = 9
1896 18:02:03.106404
1897 18:02:03.106451 ==
1898 18:02:03.106499 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 18:02:03.106548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1900 18:02:03.106596 ==
1901 18:02:03.106648 RX Vref Scan: 0
1902 18:02:03.106697
1903 18:02:03.106745 RX Vref 0 -> 0, step: 1
1904 18:02:03.106793
1905 18:02:03.106840 RX Delay -111 -> 252, step: 8
1906 18:02:03.106888 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1907 18:02:03.106936 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1908 18:02:03.106984 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1909 18:02:03.107032 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1910 18:02:03.107079 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1911 18:02:03.107127 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1912 18:02:03.107175 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1913 18:02:03.107223 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1914 18:02:03.107271 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1915 18:02:03.107318 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1916 18:02:03.107366 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1917 18:02:03.107414 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1918 18:02:03.107462 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1919 18:02:03.107509 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1920 18:02:03.107557 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1921 18:02:03.107606 iDelay=217, Bit 15, Center 76 (-39 ~ 192) 232
1922 18:02:03.107654 ==
1923 18:02:03.107703 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 18:02:03.107751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1925 18:02:03.107799 ==
1926 18:02:03.107847 DQS Delay:
1927 18:02:03.107896 DQS0 = 0, DQS1 = 0
1928 18:02:03.107944 DQM Delay:
1929 18:02:03.107992 DQM0 = 82, DQM1 = 71
1930 18:02:03.108040 DQ Delay:
1931 18:02:03.108088 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1932 18:02:03.108136 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1933 18:02:03.108184 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1934 18:02:03.108232 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =76
1935 18:02:03.108280
1936 18:02:03.108328
1937 18:02:03.108375 [DQSOSCAuto] RK1, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1938 18:02:03.108423 CH1 RK1: MR19=606, MR18=3737
1939 18:02:03.108471 CH1_RK1: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1940 18:02:03.108519 [RxdqsGatingPostProcess] freq 800
1941 18:02:03.108568 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1942 18:02:03.108617 Pre-setting of DQS Precalculation
1943 18:02:03.108684 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1944 18:02:03.108735 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1945 18:02:03.108785 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1946 18:02:03.108833
1947 18:02:03.108881
1948 18:02:03.108928 [Calibration Summary] 1600 Mbps
1949 18:02:03.108976 CH 0, Rank 0
1950 18:02:03.109025 SW Impedance : PASS
1951 18:02:03.109072 DUTY Scan : NO K
1952 18:02:03.109120 ZQ Calibration : PASS
1953 18:02:03.109167 Jitter Meter : NO K
1954 18:02:03.109214 CBT Training : PASS
1955 18:02:03.109448 Write leveling : PASS
1956 18:02:03.109502 RX DQS gating : PASS
1957 18:02:03.109552 RX DQ/DQS(RDDQC) : PASS
1958 18:02:03.109600 TX DQ/DQS : PASS
1959 18:02:03.109648 RX DATLAT : PASS
1960 18:02:03.109695 RX DQ/DQS(Engine): PASS
1961 18:02:03.109744 TX OE : NO K
1962 18:02:03.109792 All Pass.
1963 18:02:03.109840
1964 18:02:03.109887 CH 0, Rank 1
1965 18:02:03.109935 SW Impedance : PASS
1966 18:02:03.109983 DUTY Scan : NO K
1967 18:02:03.110031 ZQ Calibration : PASS
1968 18:02:03.110078 Jitter Meter : NO K
1969 18:02:03.110126 CBT Training : PASS
1970 18:02:03.110174 Write leveling : PASS
1971 18:02:03.110233 RX DQS gating : PASS
1972 18:02:03.110283 RX DQ/DQS(RDDQC) : PASS
1973 18:02:03.110332 TX DQ/DQS : PASS
1974 18:02:03.110380 RX DATLAT : PASS
1975 18:02:03.110427 RX DQ/DQS(Engine): PASS
1976 18:02:03.110475 TX OE : NO K
1977 18:02:03.110523 All Pass.
1978 18:02:03.110571
1979 18:02:03.110618 CH 1, Rank 0
1980 18:02:03.110666 SW Impedance : PASS
1981 18:02:03.110713 DUTY Scan : NO K
1982 18:02:03.110761 ZQ Calibration : PASS
1983 18:02:03.110809 Jitter Meter : NO K
1984 18:02:03.110856 CBT Training : PASS
1985 18:02:03.110903 Write leveling : PASS
1986 18:02:03.110950 RX DQS gating : PASS
1987 18:02:03.110997 RX DQ/DQS(RDDQC) : PASS
1988 18:02:03.111045 TX DQ/DQS : PASS
1989 18:02:03.111094 RX DATLAT : PASS
1990 18:02:03.111141 RX DQ/DQS(Engine): PASS
1991 18:02:03.111189 TX OE : NO K
1992 18:02:03.111236 All Pass.
1993 18:02:03.111283
1994 18:02:03.111331 CH 1, Rank 1
1995 18:02:03.111378 SW Impedance : PASS
1996 18:02:03.111425 DUTY Scan : NO K
1997 18:02:03.111473 ZQ Calibration : PASS
1998 18:02:03.111520 Jitter Meter : NO K
1999 18:02:03.111568 CBT Training : PASS
2000 18:02:03.111615 Write leveling : PASS
2001 18:02:03.111663 RX DQS gating : PASS
2002 18:02:03.111710 RX DQ/DQS(RDDQC) : PASS
2003 18:02:03.111758 TX DQ/DQS : PASS
2004 18:02:03.111805 RX DATLAT : PASS
2005 18:02:03.267305 RX DQ/DQS(Engine): PASS
2006 18:02:03.267763 TX OE : NO K
2007 18:02:03.268063 All Pass.
2008 18:02:03.268347
2009 18:02:03.268617 DramC Write-DBI off
2010 18:02:03.268880 PER_BANK_REFRESH: Hybrid Mode
2011 18:02:03.269145 TX_TRACKING: ON
2012 18:02:03.269404 [GetDramInforAfterCalByMRR] Vendor 6.
2013 18:02:03.269661 [GetDramInforAfterCalByMRR] Revision 606.
2014 18:02:03.269916 [GetDramInforAfterCalByMRR] Revision 2 0.
2015 18:02:03.270171 MR0 0x3939
2016 18:02:03.270476 MR8 0x1111
2017 18:02:03.270729 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2018 18:02:03.270980
2019 18:02:03.271232 MR0 0x3939
2020 18:02:03.271482 MR8 0x1111
2021 18:02:03.271758 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2022 18:02:03.272023
2023 18:02:03.272272 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2024 18:02:03.272528 [FAST_K] Save calibration result to emmc
2025 18:02:03.272783 [FAST_K] Save calibration result to emmc
2026 18:02:03.273030 dram_init: config_dvfs: 1
2027 18:02:03.273279 dramc_set_vcore_voltage set vcore to 662500
2028 18:02:03.273528 Read voltage for 1200, 2
2029 18:02:03.273779 Vio18 = 0
2030 18:02:03.274028 Vcore = 662500
2031 18:02:03.274312 Vdram = 0
2032 18:02:03.274576 Vddq = 0
2033 18:02:03.274827 Vmddr = 0
2034 18:02:03.275078 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2035 18:02:03.275327 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2036 18:02:03.275577 MEM_TYPE=3, freq_sel=15
2037 18:02:03.275822 sv_algorithm_assistance_LP4_1600
2038 18:02:03.276199 ============ PULL DRAM RESETB DOWN ============
2039 18:02:03.276598 ========== PULL DRAM RESETB DOWN end =========
2040 18:02:03.276865 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2041 18:02:03.277121 ===================================
2042 18:02:03.277375 LPDDR4 DRAM CONFIGURATION
2043 18:02:03.277627 ===================================
2044 18:02:03.277901 EX_ROW_EN[0] = 0x0
2045 18:02:03.278396 EX_ROW_EN[1] = 0x0
2046 18:02:03.278744 LP4Y_EN = 0x0
2047 18:02:03.279006 WORK_FSP = 0x0
2048 18:02:03.279258 WL = 0x4
2049 18:02:03.279511 RL = 0x4
2050 18:02:03.279761 BL = 0x2
2051 18:02:03.280007 RPST = 0x0
2052 18:02:03.280252 RD_PRE = 0x0
2053 18:02:03.280502 WR_PRE = 0x1
2054 18:02:03.280747 WR_PST = 0x0
2055 18:02:03.280994 DBI_WR = 0x0
2056 18:02:03.281239 DBI_RD = 0x0
2057 18:02:03.281481 OTF = 0x1
2058 18:02:03.281726 ===================================
2059 18:02:03.281975 ===================================
2060 18:02:03.282252 ANA top config
2061 18:02:03.282518 ===================================
2062 18:02:03.282766 DLL_ASYNC_EN = 0
2063 18:02:03.283015 ALL_SLAVE_EN = 0
2064 18:02:03.283261 NEW_RANK_MODE = 1
2065 18:02:03.283522 DLL_IDLE_MODE = 1
2066 18:02:03.283765 LP45_APHY_COMB_EN = 1
2067 18:02:03.284011 TX_ODT_DIS = 1
2068 18:02:03.284255 NEW_8X_MODE = 1
2069 18:02:03.284503 ===================================
2070 18:02:03.284753 ===================================
2071 18:02:03.284997 data_rate = 2400
2072 18:02:03.285242 CKR = 1
2073 18:02:03.285489 DQ_P2S_RATIO = 8
2074 18:02:03.285825 ===================================
2075 18:02:03.286082 CA_P2S_RATIO = 8
2076 18:02:03.286376 DQ_CA_OPEN = 0
2077 18:02:03.286586 DQ_SEMI_OPEN = 0
2078 18:02:03.286763 CA_SEMI_OPEN = 0
2079 18:02:03.286937 CA_FULL_RATE = 0
2080 18:02:03.287112 DQ_CKDIV4_EN = 0
2081 18:02:03.287289 CA_CKDIV4_EN = 0
2082 18:02:03.287464 CA_PREDIV_EN = 0
2083 18:02:03.287640 PH8_DLY = 17
2084 18:02:03.287815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2085 18:02:03.287989 DQ_AAMCK_DIV = 4
2086 18:02:03.288163 CA_AAMCK_DIV = 4
2087 18:02:03.288337 CA_ADMCK_DIV = 4
2088 18:02:03.288513 DQ_TRACK_CA_EN = 0
2089 18:02:03.288689 CA_PICK = 1200
2090 18:02:03.288866 CA_MCKIO = 1200
2091 18:02:03.289041 MCKIO_SEMI = 0
2092 18:02:03.289215 PLL_FREQ = 2366
2093 18:02:03.289393 DQ_UI_PI_RATIO = 32
2094 18:02:03.289566 CA_UI_PI_RATIO = 0
2095 18:02:03.289742 ===================================
2096 18:02:03.289918 ===================================
2097 18:02:03.290095 memory_type:LPDDR4
2098 18:02:03.290296 GP_NUM : 10
2099 18:02:03.290477 SRAM_EN : 1
2100 18:02:03.290651 MD32_EN : 0
2101 18:02:03.290826 ===================================
2102 18:02:03.291002 [ANA_INIT] >>>>>>>>>>>>>>
2103 18:02:03.291179 <<<<<< [CONFIGURE PHASE]: ANA_TX
2104 18:02:03.291358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2105 18:02:03.291790 ===================================
2106 18:02:03.291942 data_rate = 2400,PCW = 0X5b00
2107 18:02:03.292079 ===================================
2108 18:02:03.292216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2109 18:02:03.292356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2110 18:02:03.292494 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2111 18:02:03.292631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2112 18:02:03.292769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2113 18:02:03.292904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2114 18:02:03.293040 [ANA_INIT] flow start
2115 18:02:03.293175 [ANA_INIT] PLL >>>>>>>>
2116 18:02:03.293309 [ANA_INIT] PLL <<<<<<<<
2117 18:02:03.293443 [ANA_INIT] MIDPI >>>>>>>>
2118 18:02:03.293577 [ANA_INIT] MIDPI <<<<<<<<
2119 18:02:03.293710 [ANA_INIT] DLL >>>>>>>>
2120 18:02:03.293842 [ANA_INIT] DLL <<<<<<<<
2121 18:02:03.293974 [ANA_INIT] flow end
2122 18:02:03.294106 ============ LP4 DIFF to SE enter ============
2123 18:02:03.294278 ============ LP4 DIFF to SE exit ============
2124 18:02:03.294511 [ANA_INIT] <<<<<<<<<<<<<
2125 18:02:03.294738 [Flow] Enable top DCM control >>>>>
2126 18:02:03.294971 [Flow] Enable top DCM control <<<<<
2127 18:02:03.295192 Enable DLL master slave shuffle
2128 18:02:03.295403 ==============================================================
2129 18:02:03.295616 Gating Mode config
2130 18:02:03.295825 ==============================================================
2131 18:02:03.296034 Config description:
2132 18:02:03.296244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2133 18:02:03.296470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2134 18:02:03.296641 SELPH_MODE 0: By rank 1: By Phase
2135 18:02:03.296809 ==============================================================
2136 18:02:03.296979 GAT_TRACK_EN = 1
2137 18:02:03.297144 RX_GATING_MODE = 2
2138 18:02:03.297325 RX_GATING_TRACK_MODE = 2
2139 18:02:03.297517 SELPH_MODE = 1
2140 18:02:03.297714 PICG_EARLY_EN = 1
2141 18:02:03.297909 VALID_LAT_VALUE = 1
2142 18:02:03.298111 ==============================================================
2143 18:02:03.298332 Enter into Gating configuration >>>>
2144 18:02:03.298462 Exit from Gating configuration <<<<
2145 18:02:03.298581 Enter into DVFS_PRE_config >>>>>
2146 18:02:03.298695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2147 18:02:03.298809 Exit from DVFS_PRE_config <<<<<
2148 18:02:03.298920 Enter into PICG configuration >>>>
2149 18:02:03.299031 Exit from PICG configuration <<<<
2150 18:02:03.299141 [RX_INPUT] configuration >>>>>
2151 18:02:03.299251 [RX_INPUT] configuration <<<<<
2152 18:02:03.299358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2153 18:02:03.299467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2154 18:02:03.299575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2155 18:02:03.299684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2156 18:02:03.299793 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2157 18:02:03.299903 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2158 18:02:03.300011 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2159 18:02:03.300120 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2160 18:02:03.300227 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2161 18:02:03.300336 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2162 18:02:03.300443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2163 18:02:03.300549 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 18:02:03.300656 ===================================
2165 18:02:03.300765 LPDDR4 DRAM CONFIGURATION
2166 18:02:03.300874 ===================================
2167 18:02:03.300982 EX_ROW_EN[0] = 0x0
2168 18:02:03.301090 EX_ROW_EN[1] = 0x0
2169 18:02:03.301198 LP4Y_EN = 0x0
2170 18:02:03.301306 WORK_FSP = 0x0
2171 18:02:03.301412 WL = 0x4
2172 18:02:03.301517 RL = 0x4
2173 18:02:03.301605 BL = 0x2
2174 18:02:03.301694 RPST = 0x0
2175 18:02:03.301784 RD_PRE = 0x0
2176 18:02:03.301873 WR_PRE = 0x1
2177 18:02:03.301963 WR_PST = 0x0
2178 18:02:03.302052 DBI_WR = 0x0
2179 18:02:03.302142 DBI_RD = 0x0
2180 18:02:03.302244 OTF = 0x1
2181 18:02:03.302340 ===================================
2182 18:02:03.302430 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2183 18:02:03.302520 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2184 18:02:03.302610 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2185 18:02:03.302700 ===================================
2186 18:02:03.302791 LPDDR4 DRAM CONFIGURATION
2187 18:02:03.302881 ===================================
2188 18:02:03.302971 EX_ROW_EN[0] = 0x10
2189 18:02:03.303061 EX_ROW_EN[1] = 0x0
2190 18:02:03.303151 LP4Y_EN = 0x0
2191 18:02:03.303239 WORK_FSP = 0x0
2192 18:02:03.303328 WL = 0x4
2193 18:02:03.303417 RL = 0x4
2194 18:02:03.303506 BL = 0x2
2195 18:02:03.303597 RPST = 0x0
2196 18:02:03.303687 RD_PRE = 0x0
2197 18:02:03.303776 WR_PRE = 0x1
2198 18:02:03.303866 WR_PST = 0x0
2199 18:02:03.303955 DBI_WR = 0x0
2200 18:02:03.304045 DBI_RD = 0x0
2201 18:02:03.304134 OTF = 0x1
2202 18:02:03.304224 ===================================
2203 18:02:03.304314 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2204 18:02:03.304404 ==
2205 18:02:03.304496 Dram Type= 6, Freq= 0, CH_0, rank 0
2206 18:02:03.304586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2207 18:02:03.304678 ==
2208 18:02:03.304768 [Duty_Offset_Calibration]
2209 18:02:03.304858 B0:0 B1:2 CA:1
2210 18:02:03.304949
2211 18:02:03.305038 [DutyScan_Calibration_Flow] k_type=0
2212 18:02:03.305127
2213 18:02:03.305216 ==CLK 0==
2214 18:02:03.305307 Final CLK duty delay cell = 0
2215 18:02:03.305400 [0] MAX Duty = 5093%(X100), DQS PI = 12
2216 18:02:03.305491 [0] MIN Duty = 4938%(X100), DQS PI = 52
2217 18:02:03.305809 [0] AVG Duty = 5015%(X100)
2218 18:02:03.305910
2219 18:02:03.306003 CH0 CLK Duty spec in!! Max-Min= 155%
2220 18:02:03.306096 [DutyScan_Calibration_Flow] ====Done====
2221 18:02:03.306235
2222 18:02:03.306335 [DutyScan_Calibration_Flow] k_type=1
2223 18:02:03.306429
2224 18:02:03.306522 ==DQS 0 ==
2225 18:02:03.306601 Final DQS duty delay cell = 0
2226 18:02:03.306681 [0] MAX Duty = 5125%(X100), DQS PI = 32
2227 18:02:03.306761 [0] MIN Duty = 5031%(X100), DQS PI = 6
2228 18:02:03.306841 [0] AVG Duty = 5078%(X100)
2229 18:02:03.306919
2230 18:02:03.306997 ==DQS 1 ==
2231 18:02:03.307076 Final DQS duty delay cell = 0
2232 18:02:03.307155 [0] MAX Duty = 5031%(X100), DQS PI = 54
2233 18:02:03.307233 [0] MIN Duty = 4875%(X100), DQS PI = 20
2234 18:02:03.307311 [0] AVG Duty = 4953%(X100)
2235 18:02:03.307389
2236 18:02:03.307467 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2237 18:02:03.307545
2238 18:02:03.307621 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2239 18:02:03.307700 [DutyScan_Calibration_Flow] ====Done====
2240 18:02:03.307778
2241 18:02:03.307856 [DutyScan_Calibration_Flow] k_type=3
2242 18:02:03.307934
2243 18:02:03.308011 ==DQM 0 ==
2244 18:02:03.308089 Final DQM duty delay cell = 0
2245 18:02:03.308167 [0] MAX Duty = 5124%(X100), DQS PI = 20
2246 18:02:03.308244 [0] MIN Duty = 4969%(X100), DQS PI = 40
2247 18:02:03.308321 [0] AVG Duty = 5046%(X100)
2248 18:02:03.308397
2249 18:02:03.308474 ==DQM 1 ==
2250 18:02:03.308552 Final DQM duty delay cell = 0
2251 18:02:03.308631 [0] MAX Duty = 4969%(X100), DQS PI = 52
2252 18:02:03.308708 [0] MIN Duty = 4813%(X100), DQS PI = 24
2253 18:02:03.308785 [0] AVG Duty = 4891%(X100)
2254 18:02:03.308862
2255 18:02:03.308939 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2256 18:02:03.309018
2257 18:02:03.309095 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2258 18:02:03.309173 [DutyScan_Calibration_Flow] ====Done====
2259 18:02:03.309250
2260 18:02:03.309326 [DutyScan_Calibration_Flow] k_type=2
2261 18:02:03.309405
2262 18:02:03.309482 ==DQ 0 ==
2263 18:02:03.309561 Final DQ duty delay cell = -4
2264 18:02:03.309640 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2265 18:02:03.309718 [-4] MIN Duty = 4813%(X100), DQS PI = 6
2266 18:02:03.309797 [-4] AVG Duty = 4937%(X100)
2267 18:02:03.309874
2268 18:02:03.309950 ==DQ 1 ==
2269 18:02:03.310027 Final DQ duty delay cell = -4
2270 18:02:03.310106 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2271 18:02:03.310185 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2272 18:02:03.310281 [-4] AVG Duty = 4969%(X100)
2273 18:02:03.310360
2274 18:02:03.310439 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2275 18:02:03.310517
2276 18:02:03.310594 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2277 18:02:03.310673 [DutyScan_Calibration_Flow] ====Done====
2278 18:02:03.310750 ==
2279 18:02:03.310828 Dram Type= 6, Freq= 0, CH_1, rank 0
2280 18:02:03.310907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2281 18:02:03.310987 ==
2282 18:02:03.311065 [Duty_Offset_Calibration]
2283 18:02:03.311143 B0:0 B1:4 CA:-5
2284 18:02:03.311220
2285 18:02:03.311297 [DutyScan_Calibration_Flow] k_type=0
2286 18:02:03.311374
2287 18:02:03.311464 ==CLK 0==
2288 18:02:03.311532 Final CLK duty delay cell = 0
2289 18:02:03.311600 [0] MAX Duty = 5094%(X100), DQS PI = 24
2290 18:02:03.311669 [0] MIN Duty = 4876%(X100), DQS PI = 52
2291 18:02:03.311737 [0] AVG Duty = 4985%(X100)
2292 18:02:03.311804
2293 18:02:03.311872 CH1 CLK Duty spec in!! Max-Min= 218%
2294 18:02:03.311941 [DutyScan_Calibration_Flow] ====Done====
2295 18:02:03.312009
2296 18:02:03.312077 [DutyScan_Calibration_Flow] k_type=1
2297 18:02:03.312145
2298 18:02:03.312212 ==DQS 0 ==
2299 18:02:03.312280 Final DQS duty delay cell = 0
2300 18:02:03.312350 [0] MAX Duty = 5125%(X100), DQS PI = 16
2301 18:02:03.312419 [0] MIN Duty = 4875%(X100), DQS PI = 40
2302 18:02:03.312486 [0] AVG Duty = 5000%(X100)
2303 18:02:03.312554
2304 18:02:03.312622 ==DQS 1 ==
2305 18:02:03.312691 Final DQS duty delay cell = -4
2306 18:02:03.312778 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2307 18:02:03.312848 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2308 18:02:03.312917 [-4] AVG Duty = 4953%(X100)
2309 18:02:03.312985
2310 18:02:03.313054 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2311 18:02:03.313145
2312 18:02:03.313217 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2313 18:02:03.313287 [DutyScan_Calibration_Flow] ====Done====
2314 18:02:03.313356
2315 18:02:03.313424 [DutyScan_Calibration_Flow] k_type=3
2316 18:02:03.313492
2317 18:02:03.313560 ==DQM 0 ==
2318 18:02:03.313628 Final DQM duty delay cell = -4
2319 18:02:03.313699 [-4] MAX Duty = 5125%(X100), DQS PI = 32
2320 18:02:03.313767 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2321 18:02:03.313836 [-4] AVG Duty = 4984%(X100)
2322 18:02:03.313903
2323 18:02:03.313971 ==DQM 1 ==
2324 18:02:03.314039 Final DQM duty delay cell = -4
2325 18:02:03.314108 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2326 18:02:03.314176 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2327 18:02:03.314256 [-4] AVG Duty = 4968%(X100)
2328 18:02:03.314326
2329 18:02:03.314394 CH1 DQM 0 Duty spec in!! Max-Min= 281%
2330 18:02:03.314462
2331 18:02:03.314530 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2332 18:02:03.314598 [DutyScan_Calibration_Flow] ====Done====
2333 18:02:03.314668
2334 18:02:03.314735 [DutyScan_Calibration_Flow] k_type=2
2335 18:02:03.314803
2336 18:02:03.314871 ==DQ 0 ==
2337 18:02:03.314939 Final DQ duty delay cell = 0
2338 18:02:03.315008 [0] MAX Duty = 5062%(X100), DQS PI = 0
2339 18:02:03.315076 [0] MIN Duty = 4938%(X100), DQS PI = 44
2340 18:02:03.315144 [0] AVG Duty = 5000%(X100)
2341 18:02:03.315212
2342 18:02:03.315280 ==DQ 1 ==
2343 18:02:03.315348 Final DQ duty delay cell = 0
2344 18:02:03.315417 [0] MAX Duty = 5031%(X100), DQS PI = 8
2345 18:02:03.315484 [0] MIN Duty = 4875%(X100), DQS PI = 16
2346 18:02:03.315552 [0] AVG Duty = 4953%(X100)
2347 18:02:03.315622
2348 18:02:03.315690 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2349 18:02:03.315759
2350 18:02:03.315826 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2351 18:02:03.315894 [DutyScan_Calibration_Flow] ====Done====
2352 18:02:03.315961 nWR fixed to 30
2353 18:02:03.316029 [ModeRegInit_LP4] CH0 RK0
2354 18:02:03.316096 [ModeRegInit_LP4] CH0 RK1
2355 18:02:03.316163 [ModeRegInit_LP4] CH1 RK0
2356 18:02:03.316231 [ModeRegInit_LP4] CH1 RK1
2357 18:02:03.316298 match AC timing 6
2358 18:02:03.316366 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2359 18:02:03.316435 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2360 18:02:03.316511 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2361 18:02:03.316572 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2362 18:02:03.316633 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2363 18:02:03.316693 ==
2364 18:02:03.316752 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 18:02:03.316812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2366 18:02:03.316872 ==
2367 18:02:03.316933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2368 18:02:03.316993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2369 18:02:03.317054 [CA 0] Center 39 (9~70) winsize 62
2370 18:02:03.317114 [CA 1] Center 39 (8~70) winsize 63
2371 18:02:03.317374 [CA 2] Center 36 (5~67) winsize 63
2372 18:02:03.317442 [CA 3] Center 35 (4~66) winsize 63
2373 18:02:03.317504 [CA 4] Center 34 (3~65) winsize 63
2374 18:02:03.317564 [CA 5] Center 33 (3~64) winsize 62
2375 18:02:03.317624
2376 18:02:03.317684 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2377 18:02:03.317745
2378 18:02:03.317805 [CATrainingPosCal] consider 1 rank data
2379 18:02:03.317866 u2DelayCellTimex100 = 270/100 ps
2380 18:02:03.317926 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2381 18:02:03.317986 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2382 18:02:03.318045 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2383 18:02:03.318105 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2384 18:02:03.318165 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2385 18:02:03.318237 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2386 18:02:03.318299
2387 18:02:03.318359 CA PerBit enable=1, Macro0, CA PI delay=33
2388 18:02:03.318419
2389 18:02:03.318479 [CBTSetCACLKResult] CA Dly = 33
2390 18:02:03.318540 CS Dly: 7 (0~38)
2391 18:02:03.318599 ==
2392 18:02:03.318659 Dram Type= 6, Freq= 0, CH_0, rank 1
2393 18:02:03.318720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2394 18:02:03.318780 ==
2395 18:02:03.318840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2396 18:02:03.318901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2397 18:02:03.318962 [CA 0] Center 39 (9~70) winsize 62
2398 18:02:03.319022 [CA 1] Center 39 (8~70) winsize 63
2399 18:02:03.319082 [CA 2] Center 36 (5~67) winsize 63
2400 18:02:03.319142 [CA 3] Center 35 (4~66) winsize 63
2401 18:02:03.319201 [CA 4] Center 33 (3~64) winsize 62
2402 18:02:03.319261 [CA 5] Center 34 (3~65) winsize 63
2403 18:02:03.319321
2404 18:02:03.319381 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2405 18:02:03.319441
2406 18:02:03.319501 [CATrainingPosCal] consider 2 rank data
2407 18:02:03.319561 u2DelayCellTimex100 = 270/100 ps
2408 18:02:03.319621 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2409 18:02:03.319681 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2410 18:02:03.319739 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2411 18:02:03.319799 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2412 18:02:03.319858 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2413 18:02:03.319917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2414 18:02:03.319976
2415 18:02:03.320036 CA PerBit enable=1, Macro0, CA PI delay=33
2416 18:02:03.320096
2417 18:02:03.320157 [CBTSetCACLKResult] CA Dly = 33
2418 18:02:03.320216 CS Dly: 7 (0~39)
2419 18:02:03.320275
2420 18:02:03.320334 ----->DramcWriteLeveling(PI) begin...
2421 18:02:03.320395 ==
2422 18:02:03.320454 Dram Type= 6, Freq= 0, CH_0, rank 0
2423 18:02:03.320514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2424 18:02:03.320574 ==
2425 18:02:03.320633 Write leveling (Byte 0): 27 => 27
2426 18:02:03.320693 Write leveling (Byte 1): 25 => 25
2427 18:02:03.320753 DramcWriteLeveling(PI) end<-----
2428 18:02:03.320811
2429 18:02:03.320870 ==
2430 18:02:03.320928 Dram Type= 6, Freq= 0, CH_0, rank 0
2431 18:02:03.320989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2432 18:02:03.321050 ==
2433 18:02:03.321110 [Gating] SW mode calibration
2434 18:02:03.321170 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2435 18:02:03.321232 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2436 18:02:03.321291 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2437 18:02:03.321351 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2438 18:02:03.321410 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2439 18:02:03.321480 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2440 18:02:03.321535 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2441 18:02:03.321589 0 11 20 | B1->B0 | 2c2c 2b2b | 0 0 | (1 0) (0 1)
2442 18:02:03.321642 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2443 18:02:03.321696 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2444 18:02:03.321750 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2445 18:02:03.321804 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2446 18:02:03.321858 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2447 18:02:03.321911 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2448 18:02:03.321964 0 12 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2449 18:02:03.322017 0 12 20 | B1->B0 | 3b3b 4241 | 1 1 | (0 0) (0 0)
2450 18:02:03.322072 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2451 18:02:03.322126 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2452 18:02:03.322179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2453 18:02:03.322237 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2454 18:02:03.322292 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2455 18:02:03.322346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2456 18:02:03.322399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2457 18:02:03.322452 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2458 18:02:03.322506 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2459 18:02:03.322561 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2460 18:02:03.322615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2461 18:02:03.322668 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2462 18:02:03.322721 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2463 18:02:03.322774 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2464 18:02:03.322827 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2465 18:02:03.322882 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 18:02:03.322935 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 18:02:03.322989 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 18:02:03.323043 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 18:02:03.323097 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 18:02:03.323151 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 18:02:03.323205 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 18:02:03.323260 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2473 18:02:03.323337 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2474 18:02:03.323405 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2475 18:02:03.323494 Total UI for P1: 0, mck2ui 16
2476 18:02:03.323552 best dqsien dly found for B0: ( 0, 15, 18)
2477 18:02:03.323799 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 18:02:03.323860 Total UI for P1: 0, mck2ui 16
2479 18:02:03.323917 best dqsien dly found for B1: ( 0, 15, 22)
2480 18:02:03.323972 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2481 18:02:03.324027 best DQS1 dly(MCK, UI, PI) = (0, 15, 22)
2482 18:02:03.324081
2483 18:02:03.324135 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2484 18:02:03.324190 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 22)
2485 18:02:03.324243 [Gating] SW calibration Done
2486 18:02:03.324296 ==
2487 18:02:03.324350 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 18:02:03.324404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2489 18:02:03.324459 ==
2490 18:02:03.324512 RX Vref Scan: 0
2491 18:02:03.324566
2492 18:02:03.324619 RX Vref 0 -> 0, step: 1
2493 18:02:03.324673
2494 18:02:03.324727 RX Delay -40 -> 252, step: 8
2495 18:02:03.324780 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2496 18:02:03.324874 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2497 18:02:03.324931 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2498 18:02:03.324985 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2499 18:02:03.325039 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2500 18:02:03.325092 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2501 18:02:03.325146 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2502 18:02:03.325200 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2503 18:02:03.325253 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2504 18:02:03.325306 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2505 18:02:03.325359 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2506 18:02:03.325413 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2507 18:02:03.325467 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2508 18:02:03.325521 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2509 18:02:03.325574 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2510 18:02:03.325629 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2511 18:02:03.325682 ==
2512 18:02:03.325736 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 18:02:03.325789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2514 18:02:03.325842 ==
2515 18:02:03.325896 DQS Delay:
2516 18:02:03.325950 DQS0 = 0, DQS1 = 0
2517 18:02:03.326004 DQM Delay:
2518 18:02:03.326057 DQM0 = 115, DQM1 = 106
2519 18:02:03.326111 DQ Delay:
2520 18:02:03.326164 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2521 18:02:03.326232 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2522 18:02:03.326290 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2523 18:02:03.326344 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2524 18:02:03.326397
2525 18:02:03.326464
2526 18:02:03.326512 ==
2527 18:02:03.326560 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 18:02:03.326609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 18:02:03.326659 ==
2530 18:02:03.326707
2531 18:02:03.326754
2532 18:02:03.326802 TX Vref Scan disable
2533 18:02:03.326851 == TX Byte 0 ==
2534 18:02:03.326899 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2535 18:02:03.326948 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2536 18:02:03.326998 == TX Byte 1 ==
2537 18:02:03.327047 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2538 18:02:03.327096 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2539 18:02:03.327145 ==
2540 18:02:03.327194 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 18:02:03.327243 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 18:02:03.327292 ==
2543 18:02:03.327341 TX Vref=22, minBit 8, minWin=25, winSum=412
2544 18:02:03.327390 TX Vref=24, minBit 8, minWin=25, winSum=417
2545 18:02:03.327439 TX Vref=26, minBit 10, minWin=25, winSum=428
2546 18:02:03.327488 TX Vref=28, minBit 5, minWin=26, winSum=432
2547 18:02:03.327537 TX Vref=30, minBit 13, minWin=25, winSum=433
2548 18:02:03.327586 TX Vref=32, minBit 5, minWin=26, winSum=431
2549 18:02:03.327635 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2550 18:02:03.327684
2551 18:02:03.327734 Final TX Range 1 Vref 28
2552 18:02:03.327783
2553 18:02:03.327831 ==
2554 18:02:03.327879 Dram Type= 6, Freq= 0, CH_0, rank 0
2555 18:02:03.327928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2556 18:02:03.327977 ==
2557 18:02:03.328026
2558 18:02:03.328075
2559 18:02:03.328123 TX Vref Scan disable
2560 18:02:03.328171 == TX Byte 0 ==
2561 18:02:03.328220 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2562 18:02:03.328269 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2563 18:02:03.328317 == TX Byte 1 ==
2564 18:02:03.328365 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2565 18:02:03.328414 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2566 18:02:03.328463
2567 18:02:03.328511 [DATLAT]
2568 18:02:03.328558 Freq=1200, CH0 RK0
2569 18:02:03.328606
2570 18:02:03.328653 DATLAT Default: 0xd
2571 18:02:03.328702 0, 0xFFFF, sum = 0
2572 18:02:03.328753 1, 0xFFFF, sum = 0
2573 18:02:03.328801 2, 0xFFFF, sum = 0
2574 18:02:03.328850 3, 0xFFFF, sum = 0
2575 18:02:03.328900 4, 0xFFFF, sum = 0
2576 18:02:03.328949 5, 0xFFFF, sum = 0
2577 18:02:03.328997 6, 0xFFFF, sum = 0
2578 18:02:03.329046 7, 0xFFFF, sum = 0
2579 18:02:03.329096 8, 0xFFFF, sum = 0
2580 18:02:03.329144 9, 0xFFFF, sum = 0
2581 18:02:03.329193 10, 0xFFFF, sum = 0
2582 18:02:03.329242 11, 0x0, sum = 1
2583 18:02:03.329290 12, 0x0, sum = 2
2584 18:02:03.329339 13, 0x0, sum = 3
2585 18:02:03.329388 14, 0x0, sum = 4
2586 18:02:03.329437 best_step = 12
2587 18:02:03.329486
2588 18:02:03.329533 ==
2589 18:02:03.329582 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 18:02:03.329631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2591 18:02:03.329681 ==
2592 18:02:03.329730 RX Vref Scan: 1
2593 18:02:03.329779
2594 18:02:03.329827 Set Vref Range= 32 -> 127
2595 18:02:03.329876
2596 18:02:03.329924 RX Vref 32 -> 127, step: 1
2597 18:02:03.329973
2598 18:02:03.330021 RX Delay -21 -> 252, step: 4
2599 18:02:03.330070
2600 18:02:03.330118 Set Vref, RX VrefLevel [Byte0]: 32
2601 18:02:03.330167 [Byte1]: 32
2602 18:02:03.330223
2603 18:02:03.330273 Set Vref, RX VrefLevel [Byte0]: 33
2604 18:02:03.330322 [Byte1]: 33
2605 18:02:03.330371
2606 18:02:03.330420 Set Vref, RX VrefLevel [Byte0]: 34
2607 18:02:03.330469 [Byte1]: 34
2608 18:02:03.330518
2609 18:02:03.330565 Set Vref, RX VrefLevel [Byte0]: 35
2610 18:02:03.330614 [Byte1]: 35
2611 18:02:03.330662
2612 18:02:03.330710 Set Vref, RX VrefLevel [Byte0]: 36
2613 18:02:03.330760 [Byte1]: 36
2614 18:02:03.330809
2615 18:02:03.330857 Set Vref, RX VrefLevel [Byte0]: 37
2616 18:02:03.330905 [Byte1]: 37
2617 18:02:03.330954
2618 18:02:03.331002 Set Vref, RX VrefLevel [Byte0]: 38
2619 18:02:03.331050 [Byte1]: 38
2620 18:02:03.331098
2621 18:02:03.331146 Set Vref, RX VrefLevel [Byte0]: 39
2622 18:02:03.331196 [Byte1]: 39
2623 18:02:03.331244
2624 18:02:03.331292 Set Vref, RX VrefLevel [Byte0]: 40
2625 18:02:03.331341 [Byte1]: 40
2626 18:02:03.331389
2627 18:02:03.331437 Set Vref, RX VrefLevel [Byte0]: 41
2628 18:02:03.331518 [Byte1]: 41
2629 18:02:03.331567
2630 18:02:03.331614 Set Vref, RX VrefLevel [Byte0]: 42
2631 18:02:03.331852 [Byte1]: 42
2632 18:02:03.331906
2633 18:02:03.331955 Set Vref, RX VrefLevel [Byte0]: 43
2634 18:02:03.332003 [Byte1]: 43
2635 18:02:03.332051
2636 18:02:03.332099 Set Vref, RX VrefLevel [Byte0]: 44
2637 18:02:03.332147 [Byte1]: 44
2638 18:02:03.332194
2639 18:02:03.332242 Set Vref, RX VrefLevel [Byte0]: 45
2640 18:02:03.332290 [Byte1]: 45
2641 18:02:03.332338
2642 18:02:03.332386 Set Vref, RX VrefLevel [Byte0]: 46
2643 18:02:03.332434 [Byte1]: 46
2644 18:02:03.332482
2645 18:02:03.332529 Set Vref, RX VrefLevel [Byte0]: 47
2646 18:02:03.332576 [Byte1]: 47
2647 18:02:03.332623
2648 18:02:03.332670 Set Vref, RX VrefLevel [Byte0]: 48
2649 18:02:03.332718 [Byte1]: 48
2650 18:02:03.332765
2651 18:02:03.332812 Set Vref, RX VrefLevel [Byte0]: 49
2652 18:02:03.332860 [Byte1]: 49
2653 18:02:03.332907
2654 18:02:03.332954 Set Vref, RX VrefLevel [Byte0]: 50
2655 18:02:03.333003 [Byte1]: 50
2656 18:02:03.333051
2657 18:02:03.333097 Set Vref, RX VrefLevel [Byte0]: 51
2658 18:02:03.333145 [Byte1]: 51
2659 18:02:03.333192
2660 18:02:03.333240 Set Vref, RX VrefLevel [Byte0]: 52
2661 18:02:03.333297 [Byte1]: 52
2662 18:02:03.333346
2663 18:02:03.333394 Set Vref, RX VrefLevel [Byte0]: 53
2664 18:02:03.333442 [Byte1]: 53
2665 18:02:03.333490
2666 18:02:03.333538 Set Vref, RX VrefLevel [Byte0]: 54
2667 18:02:03.333585 [Byte1]: 54
2668 18:02:03.333632
2669 18:02:03.333680 Set Vref, RX VrefLevel [Byte0]: 55
2670 18:02:03.333727 [Byte1]: 55
2671 18:02:03.333775
2672 18:02:03.333822 Set Vref, RX VrefLevel [Byte0]: 56
2673 18:02:03.333869 [Byte1]: 56
2674 18:02:03.333917
2675 18:02:03.333964 Set Vref, RX VrefLevel [Byte0]: 57
2676 18:02:03.334011 [Byte1]: 57
2677 18:02:03.334059
2678 18:02:03.334105 Set Vref, RX VrefLevel [Byte0]: 58
2679 18:02:03.334153 [Byte1]: 58
2680 18:02:03.334200
2681 18:02:03.334284 Set Vref, RX VrefLevel [Byte0]: 59
2682 18:02:03.334333 [Byte1]: 59
2683 18:02:03.334382
2684 18:02:03.334429 Set Vref, RX VrefLevel [Byte0]: 60
2685 18:02:03.334477 [Byte1]: 60
2686 18:02:03.334524
2687 18:02:03.334571 Set Vref, RX VrefLevel [Byte0]: 61
2688 18:02:03.334619 [Byte1]: 61
2689 18:02:03.334666
2690 18:02:03.334713 Set Vref, RX VrefLevel [Byte0]: 62
2691 18:02:03.334760 [Byte1]: 62
2692 18:02:03.334808
2693 18:02:03.334855 Set Vref, RX VrefLevel [Byte0]: 63
2694 18:02:03.334903 [Byte1]: 63
2695 18:02:03.334950
2696 18:02:03.334997 Set Vref, RX VrefLevel [Byte0]: 64
2697 18:02:03.335046 [Byte1]: 64
2698 18:02:03.335094
2699 18:02:03.335140 Set Vref, RX VrefLevel [Byte0]: 65
2700 18:02:03.335188 [Byte1]: 65
2701 18:02:03.335235
2702 18:02:03.335282 Set Vref, RX VrefLevel [Byte0]: 66
2703 18:02:03.335329 [Byte1]: 66
2704 18:02:03.335376
2705 18:02:03.335423 Final RX Vref Byte 0 = 46 to rank0
2706 18:02:03.335471 Final RX Vref Byte 1 = 48 to rank0
2707 18:02:03.335519 Final RX Vref Byte 0 = 46 to rank1
2708 18:02:03.335567 Final RX Vref Byte 1 = 48 to rank1==
2709 18:02:03.335614 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 18:02:03.335662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2711 18:02:03.335710 ==
2712 18:02:03.335757 DQS Delay:
2713 18:02:03.335805 DQS0 = 0, DQS1 = 0
2714 18:02:03.335852 DQM Delay:
2715 18:02:03.335900 DQM0 = 114, DQM1 = 105
2716 18:02:03.335948 DQ Delay:
2717 18:02:03.335995 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2718 18:02:03.336044 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2719 18:02:03.336091 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2720 18:02:03.336139 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2721 18:02:03.336186
2722 18:02:03.336233
2723 18:02:03.336280 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2724 18:02:03.336330 CH0 RK0: MR19=404, MR18=505
2725 18:02:03.336378 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2726 18:02:03.336427
2727 18:02:03.336474 ----->DramcWriteLeveling(PI) begin...
2728 18:02:03.336523 ==
2729 18:02:03.336569 Dram Type= 6, Freq= 0, CH_0, rank 1
2730 18:02:03.336618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2731 18:02:03.336666 ==
2732 18:02:03.336714 Write leveling (Byte 0): 27 => 27
2733 18:02:03.336762 Write leveling (Byte 1): 24 => 24
2734 18:02:03.336809 DramcWriteLeveling(PI) end<-----
2735 18:02:03.336857
2736 18:02:03.336904 ==
2737 18:02:03.336951 Dram Type= 6, Freq= 0, CH_0, rank 1
2738 18:02:03.336998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2739 18:02:03.337046 ==
2740 18:02:03.337092 [Gating] SW mode calibration
2741 18:02:03.337140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2742 18:02:03.337189 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2743 18:02:03.337237 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2744 18:02:03.337294 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2745 18:02:03.337343 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2746 18:02:03.337391 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2747 18:02:03.337439 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2748 18:02:03.337487 0 11 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2749 18:02:03.337535 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2750 18:02:03.337583 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2751 18:02:03.337631 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2752 18:02:03.337679 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2753 18:02:03.337727 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2754 18:02:03.337775 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2755 18:02:03.337823 0 12 16 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2756 18:02:03.337871 0 12 20 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2757 18:02:03.337918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2758 18:02:03.337966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2759 18:02:03.338014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2760 18:02:03.338062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2761 18:02:03.338110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2762 18:02:03.338158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 18:02:03.338395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2764 18:02:03.338450 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2765 18:02:03.338499 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2766 18:02:03.338547 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2767 18:02:03.338595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2768 18:02:03.338643 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2769 18:02:03.338691 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2770 18:02:03.338739 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 18:02:03.338787 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 18:02:03.338835 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 18:02:03.338882 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 18:02:03.338930 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 18:02:03.338978 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 18:02:03.339026 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 18:02:03.339074 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 18:02:03.339121 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 18:02:03.339169 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2780 18:02:03.339216 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2781 18:02:03.339264 Total UI for P1: 0, mck2ui 16
2782 18:02:03.339312 best dqsien dly found for B0: ( 0, 15, 16)
2783 18:02:03.339360 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2784 18:02:03.339408 Total UI for P1: 0, mck2ui 16
2785 18:02:03.339455 best dqsien dly found for B1: ( 0, 15, 18)
2786 18:02:03.339503 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2787 18:02:03.339550 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2788 18:02:03.339597
2789 18:02:03.339644 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2790 18:02:03.339692 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2791 18:02:03.339739 [Gating] SW calibration Done
2792 18:02:03.339787 ==
2793 18:02:03.339834 Dram Type= 6, Freq= 0, CH_0, rank 1
2794 18:02:03.339882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2795 18:02:03.339932 ==
2796 18:02:03.339980 RX Vref Scan: 0
2797 18:02:03.340028
2798 18:02:03.340075 RX Vref 0 -> 0, step: 1
2799 18:02:03.340122
2800 18:02:03.340168 RX Delay -40 -> 252, step: 8
2801 18:02:03.340216 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2802 18:02:03.340264 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2803 18:02:03.340312 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2804 18:02:03.340361 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2805 18:02:03.340408 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2806 18:02:03.340456 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2807 18:02:03.340504 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2808 18:02:03.340551 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2809 18:02:03.340599 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2810 18:02:03.340646 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2811 18:02:03.340694 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2812 18:02:03.340742 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2813 18:02:03.340790 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2814 18:02:03.340837 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2815 18:02:03.340885 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2816 18:02:03.340933 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2817 18:02:03.340980 ==
2818 18:02:03.341027 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 18:02:03.341076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2820 18:02:03.341124 ==
2821 18:02:03.341171 DQS Delay:
2822 18:02:03.341219 DQS0 = 0, DQS1 = 0
2823 18:02:03.341268 DQM Delay:
2824 18:02:03.341333 DQM0 = 114, DQM1 = 107
2825 18:02:03.341381 DQ Delay:
2826 18:02:03.341429 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2827 18:02:03.341477 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2828 18:02:03.341524 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2829 18:02:03.341571 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2830 18:02:03.341619
2831 18:02:03.341667
2832 18:02:03.341714 ==
2833 18:02:03.341760 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 18:02:03.341808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 18:02:03.341857 ==
2836 18:02:03.341904
2837 18:02:03.341951
2838 18:02:03.341997 TX Vref Scan disable
2839 18:02:03.342044 == TX Byte 0 ==
2840 18:02:03.342092 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2841 18:02:03.342140 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2842 18:02:03.342187 == TX Byte 1 ==
2843 18:02:03.342282 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2844 18:02:03.342331 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2845 18:02:03.342378 ==
2846 18:02:03.342426 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 18:02:03.342474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2848 18:02:03.342521 ==
2849 18:02:03.342569 TX Vref=22, minBit 8, minWin=25, winSum=415
2850 18:02:03.342617 TX Vref=24, minBit 8, minWin=25, winSum=420
2851 18:02:03.342667 TX Vref=26, minBit 8, minWin=25, winSum=426
2852 18:02:03.342715 TX Vref=28, minBit 1, minWin=26, winSum=425
2853 18:02:03.342764 TX Vref=30, minBit 5, minWin=26, winSum=431
2854 18:02:03.342811 TX Vref=32, minBit 8, minWin=25, winSum=427
2855 18:02:03.342859 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 30
2856 18:02:03.342907
2857 18:02:03.342954 Final TX Range 1 Vref 30
2858 18:02:03.343001
2859 18:02:03.343049 ==
2860 18:02:03.343097 Dram Type= 6, Freq= 0, CH_0, rank 1
2861 18:02:03.343145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2862 18:02:03.343193 ==
2863 18:02:03.343241
2864 18:02:03.343295
2865 18:02:03.343344 TX Vref Scan disable
2866 18:02:03.343392 == TX Byte 0 ==
2867 18:02:03.343440 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2868 18:02:03.343489 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2869 18:02:03.343537 == TX Byte 1 ==
2870 18:02:03.343584 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2871 18:02:03.343633 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2872 18:02:03.343680
2873 18:02:03.343728 [DATLAT]
2874 18:02:03.343775 Freq=1200, CH0 RK1
2875 18:02:03.343823
2876 18:02:03.343870 DATLAT Default: 0xc
2877 18:02:03.343918 0, 0xFFFF, sum = 0
2878 18:02:03.343966 1, 0xFFFF, sum = 0
2879 18:02:03.344015 2, 0xFFFF, sum = 0
2880 18:02:03.344064 3, 0xFFFF, sum = 0
2881 18:02:03.344113 4, 0xFFFF, sum = 0
2882 18:02:03.344161 5, 0xFFFF, sum = 0
2883 18:02:03.344209 6, 0xFFFF, sum = 0
2884 18:02:03.344256 7, 0xFFFF, sum = 0
2885 18:02:03.344305 8, 0xFFFF, sum = 0
2886 18:02:03.344354 9, 0xFFFF, sum = 0
2887 18:02:03.344403 10, 0xFFFF, sum = 0
2888 18:02:03.344451 11, 0x0, sum = 1
2889 18:02:03.344499 12, 0x0, sum = 2
2890 18:02:03.344547 13, 0x0, sum = 3
2891 18:02:03.344595 14, 0x0, sum = 4
2892 18:02:03.344642 best_step = 12
2893 18:02:03.344689
2894 18:02:03.344737 ==
2895 18:02:03.344972 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 18:02:03.345027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2897 18:02:03.345077 ==
2898 18:02:03.345125 RX Vref Scan: 0
2899 18:02:03.345173
2900 18:02:03.345221 RX Vref 0 -> 0, step: 1
2901 18:02:03.345269
2902 18:02:03.345316 RX Delay -21 -> 252, step: 4
2903 18:02:03.345365 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2904 18:02:03.345413 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2905 18:02:03.345461 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2906 18:02:03.345509 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2907 18:02:03.345557 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2908 18:02:03.345605 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2909 18:02:03.345653 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2910 18:02:03.345700 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2911 18:02:03.345748 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2912 18:02:03.345796 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2913 18:02:03.345843 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2914 18:02:03.345891 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2915 18:02:03.345939 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2916 18:02:03.345986 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2917 18:02:03.346033 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2918 18:02:03.346081 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2919 18:02:03.346128 ==
2920 18:02:03.346176 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 18:02:03.346251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2922 18:02:03.346316 ==
2923 18:02:03.346364 DQS Delay:
2924 18:02:03.346412 DQS0 = 0, DQS1 = 0
2925 18:02:03.346459 DQM Delay:
2926 18:02:03.346507 DQM0 = 114, DQM1 = 105
2927 18:02:03.346554 DQ Delay:
2928 18:02:03.346601 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2929 18:02:03.346648 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2930 18:02:03.346696 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2931 18:02:03.346744 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2932 18:02:03.346792
2933 18:02:03.346838
2934 18:02:03.346886 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2935 18:02:03.346935 CH0 RK1: MR19=404, MR18=F0F
2936 18:02:03.346983 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2937 18:02:03.347031 [RxdqsGatingPostProcess] freq 1200
2938 18:02:03.347079 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2939 18:02:03.347126 Pre-setting of DQS Precalculation
2940 18:02:03.347174 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2941 18:02:03.347222 ==
2942 18:02:03.347274 Dram Type= 6, Freq= 0, CH_1, rank 0
2943 18:02:03.347324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2944 18:02:03.347373 ==
2945 18:02:03.347421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2946 18:02:03.347469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2947 18:02:03.347517 [CA 0] Center 37 (7~68) winsize 62
2948 18:02:03.347565 [CA 1] Center 37 (7~68) winsize 62
2949 18:02:03.347613 [CA 2] Center 34 (4~65) winsize 62
2950 18:02:03.347661 [CA 3] Center 33 (3~64) winsize 62
2951 18:02:03.347709 [CA 4] Center 32 (1~63) winsize 63
2952 18:02:03.347757 [CA 5] Center 32 (2~63) winsize 62
2953 18:02:03.347804
2954 18:02:03.347852 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2955 18:02:03.347900
2956 18:02:03.347946 [CATrainingPosCal] consider 1 rank data
2957 18:02:03.347995 u2DelayCellTimex100 = 270/100 ps
2958 18:02:03.348044 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2959 18:02:03.348091 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2960 18:02:03.348139 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2961 18:02:03.348187 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2962 18:02:03.348235 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2963 18:02:03.348283 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2964 18:02:03.348329
2965 18:02:03.348377 CA PerBit enable=1, Macro0, CA PI delay=32
2966 18:02:03.348424
2967 18:02:03.348471 [CBTSetCACLKResult] CA Dly = 32
2968 18:02:03.348519 CS Dly: 5 (0~36)
2969 18:02:03.348566 ==
2970 18:02:03.348614 Dram Type= 6, Freq= 0, CH_1, rank 1
2971 18:02:03.348662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2972 18:02:03.348710 ==
2973 18:02:03.348757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2974 18:02:03.348805 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2975 18:02:03.348852 [CA 0] Center 37 (7~68) winsize 62
2976 18:02:03.348900 [CA 1] Center 37 (6~68) winsize 63
2977 18:02:03.348948 [CA 2] Center 34 (3~65) winsize 63
2978 18:02:03.348995 [CA 3] Center 33 (3~64) winsize 62
2979 18:02:03.349043 [CA 4] Center 32 (2~63) winsize 62
2980 18:02:03.349090 [CA 5] Center 32 (1~63) winsize 63
2981 18:02:03.349137
2982 18:02:03.349184 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2983 18:02:03.349231
2984 18:02:03.349287 [CATrainingPosCal] consider 2 rank data
2985 18:02:03.349397 u2DelayCellTimex100 = 270/100 ps
2986 18:02:03.349459 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2987 18:02:03.349509 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2988 18:02:03.349557 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2989 18:02:03.349605 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2990 18:02:03.349652 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2991 18:02:03.349700 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2992 18:02:03.349747
2993 18:02:03.349794 CA PerBit enable=1, Macro0, CA PI delay=32
2994 18:02:03.349842
2995 18:02:03.349889 [CBTSetCACLKResult] CA Dly = 32
2996 18:02:03.579653 CS Dly: 6 (0~38)
2997 18:02:03.580131
2998 18:02:03.580458 ----->DramcWriteLeveling(PI) begin...
2999 18:02:03.580855 ==
3000 18:02:03.581187 Dram Type= 6, Freq= 0, CH_1, rank 0
3001 18:02:03.581596 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3002 18:02:03.581899 ==
3003 18:02:03.582185 Write leveling (Byte 0): 21 => 21
3004 18:02:03.582519 Write leveling (Byte 1): 20 => 20
3005 18:02:03.582803 DramcWriteLeveling(PI) end<-----
3006 18:02:03.583076
3007 18:02:03.583352 ==
3008 18:02:03.583632 Dram Type= 6, Freq= 0, CH_1, rank 0
3009 18:02:03.584014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3010 18:02:03.584285 ==
3011 18:02:03.584539 [Gating] SW mode calibration
3012 18:02:03.584837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3013 18:02:03.585145 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3014 18:02:03.585400 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3015 18:02:03.585653 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3016 18:02:03.586310 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 18:02:03.586637 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 18:02:03.586900 0 11 16 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (1 0)
3019 18:02:03.587279 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3020 18:02:03.587710 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3021 18:02:03.588035 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3022 18:02:03.588368 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 18:02:03.588628 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 18:02:03.588880 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 18:02:03.589129 0 12 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
3026 18:02:03.589384 0 12 16 | B1->B0 | 3131 4242 | 0 0 | (0 0) (0 0)
3027 18:02:03.589638 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3028 18:02:03.589888 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3029 18:02:03.590139 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3030 18:02:03.590528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 18:02:03.590788 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 18:02:03.591041 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 18:02:03.591389 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3034 18:02:03.591663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3035 18:02:03.591915 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3036 18:02:03.592163 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3037 18:02:03.592410 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 18:02:03.592657 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 18:02:03.592905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 18:02:03.593154 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 18:02:03.593402 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 18:02:03.593743 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 18:02:03.594018 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 18:02:03.594307 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 18:02:03.594576 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 18:02:03.594928 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 18:02:03.595188 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 18:02:03.595438 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 18:02:03.595688 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 18:02:03.595937 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3051 18:02:03.596183 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3052 18:02:03.596429 Total UI for P1: 0, mck2ui 16
3053 18:02:03.596678 best dqsien dly found for B0: ( 0, 15, 16)
3054 18:02:03.596928 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3055 18:02:03.597179 Total UI for P1: 0, mck2ui 16
3056 18:02:03.597470 best dqsien dly found for B1: ( 0, 15, 18)
3057 18:02:03.597785 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3058 18:02:03.598059 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3059 18:02:03.598441
3060 18:02:03.598700 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3061 18:02:03.598953 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3062 18:02:03.599203 [Gating] SW calibration Done
3063 18:02:03.599451 ==
3064 18:02:03.599700 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 18:02:03.599951 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3066 18:02:03.600201 ==
3067 18:02:03.600446 RX Vref Scan: 0
3068 18:02:03.600692
3069 18:02:03.600978 RX Vref 0 -> 0, step: 1
3070 18:02:03.601380
3071 18:02:03.601603 RX Delay -40 -> 252, step: 8
3072 18:02:03.601785 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3073 18:02:03.601965 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3074 18:02:03.602140 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3075 18:02:03.602361 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3076 18:02:03.602544 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3077 18:02:03.602722 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3078 18:02:03.602899 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3079 18:02:03.603075 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3080 18:02:03.603251 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3081 18:02:03.603427 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3082 18:02:03.603601 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3083 18:02:03.603874 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3084 18:02:03.604061 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3085 18:02:03.604241 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3086 18:02:03.604432 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3087 18:02:03.604678 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3088 18:02:03.604863 ==
3089 18:02:03.605049 Dram Type= 6, Freq= 0, CH_1, rank 0
3090 18:02:03.605229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3091 18:02:03.605410 ==
3092 18:02:03.605588 DQS Delay:
3093 18:02:03.605768 DQS0 = 0, DQS1 = 0
3094 18:02:03.605947 DQM Delay:
3095 18:02:03.606126 DQM0 = 115, DQM1 = 106
3096 18:02:03.606339 DQ Delay:
3097 18:02:03.606516 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3098 18:02:03.606651 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3099 18:02:03.606815 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =95
3100 18:02:03.606963 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3101 18:02:03.607098
3102 18:02:03.607233
3103 18:02:03.607367 ==
3104 18:02:03.607501 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 18:02:03.607706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 18:02:03.607849 ==
3107 18:02:03.608023
3108 18:02:03.608169
3109 18:02:03.608304 TX Vref Scan disable
3110 18:02:03.608439 == TX Byte 0 ==
3111 18:02:03.608575 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3112 18:02:03.608713 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3113 18:02:03.608849 == TX Byte 1 ==
3114 18:02:03.608983 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3115 18:02:03.609117 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3116 18:02:03.609250 ==
3117 18:02:03.609385 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 18:02:03.609519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3119 18:02:03.609655 ==
3120 18:02:03.609789 TX Vref=22, minBit 5, minWin=25, winSum=412
3121 18:02:03.609925 TX Vref=24, minBit 3, minWin=25, winSum=417
3122 18:02:03.610059 TX Vref=26, minBit 9, minWin=25, winSum=422
3123 18:02:03.610195 TX Vref=28, minBit 0, minWin=26, winSum=430
3124 18:02:03.610608 TX Vref=30, minBit 0, minWin=26, winSum=427
3125 18:02:03.610828 TX Vref=32, minBit 9, minWin=26, winSum=431
3126 18:02:03.611033 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 32
3127 18:02:03.611180
3128 18:02:03.611317 Final TX Range 1 Vref 32
3129 18:02:03.611460
3130 18:02:03.611567 ==
3131 18:02:03.611677 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 18:02:03.611787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3133 18:02:03.611898 ==
3134 18:02:03.612005
3135 18:02:03.612112
3136 18:02:03.612217 TX Vref Scan disable
3137 18:02:03.612325 == TX Byte 0 ==
3138 18:02:03.612433 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3139 18:02:03.612542 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3140 18:02:03.612650 == TX Byte 1 ==
3141 18:02:03.612757 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3142 18:02:03.612865 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3143 18:02:03.612972
3144 18:02:03.613078 [DATLAT]
3145 18:02:03.613187 Freq=1200, CH1 RK0
3146 18:02:03.613322
3147 18:02:03.613432 DATLAT Default: 0xd
3148 18:02:03.613540 0, 0xFFFF, sum = 0
3149 18:02:03.613651 1, 0xFFFF, sum = 0
3150 18:02:03.613760 2, 0xFFFF, sum = 0
3151 18:02:03.613871 3, 0xFFFF, sum = 0
3152 18:02:03.613981 4, 0xFFFF, sum = 0
3153 18:02:03.614091 5, 0xFFFF, sum = 0
3154 18:02:03.614292 6, 0xFFFF, sum = 0
3155 18:02:03.614411 7, 0xFFFF, sum = 0
3156 18:02:03.614523 8, 0xFFFF, sum = 0
3157 18:02:03.614635 9, 0xFFFF, sum = 0
3158 18:02:03.614746 10, 0xFFFF, sum = 0
3159 18:02:03.614856 11, 0x0, sum = 1
3160 18:02:03.614966 12, 0x0, sum = 2
3161 18:02:03.615075 13, 0x0, sum = 3
3162 18:02:03.615184 14, 0x0, sum = 4
3163 18:02:03.615292 best_step = 12
3164 18:02:03.615399
3165 18:02:03.615506 ==
3166 18:02:03.615613 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 18:02:03.615721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3168 18:02:03.615829 ==
3169 18:02:03.615936 RX Vref Scan: 1
3170 18:02:03.616043
3171 18:02:03.616148 Set Vref Range= 32 -> 127
3172 18:02:03.616254
3173 18:02:03.616362 RX Vref 32 -> 127, step: 1
3174 18:02:03.616475
3175 18:02:03.616563 RX Delay -29 -> 252, step: 4
3176 18:02:03.616654
3177 18:02:03.616741 Set Vref, RX VrefLevel [Byte0]: 32
3178 18:02:03.616831 [Byte1]: 32
3179 18:02:03.616920
3180 18:02:03.617009 Set Vref, RX VrefLevel [Byte0]: 33
3181 18:02:03.617098 [Byte1]: 33
3182 18:02:03.617185
3183 18:02:03.617288 Set Vref, RX VrefLevel [Byte0]: 34
3184 18:02:03.617406 [Byte1]: 34
3185 18:02:03.617499
3186 18:02:03.617590 Set Vref, RX VrefLevel [Byte0]: 35
3187 18:02:03.617689 [Byte1]: 35
3188 18:02:03.617812
3189 18:02:03.617905 Set Vref, RX VrefLevel [Byte0]: 36
3190 18:02:03.617996 [Byte1]: 36
3191 18:02:03.618087
3192 18:02:03.618177 Set Vref, RX VrefLevel [Byte0]: 37
3193 18:02:03.618283 [Byte1]: 37
3194 18:02:03.618375
3195 18:02:03.618465 Set Vref, RX VrefLevel [Byte0]: 38
3196 18:02:03.618554 [Byte1]: 38
3197 18:02:03.618644
3198 18:02:03.618731 Set Vref, RX VrefLevel [Byte0]: 39
3199 18:02:03.618820 [Byte1]: 39
3200 18:02:03.618909
3201 18:02:03.618999 Set Vref, RX VrefLevel [Byte0]: 40
3202 18:02:03.619089 [Byte1]: 40
3203 18:02:03.619179
3204 18:02:03.619268 Set Vref, RX VrefLevel [Byte0]: 41
3205 18:02:03.619357 [Byte1]: 41
3206 18:02:03.619446
3207 18:02:03.619535 Set Vref, RX VrefLevel [Byte0]: 42
3208 18:02:03.619625 [Byte1]: 42
3209 18:02:03.619714
3210 18:02:03.619803 Set Vref, RX VrefLevel [Byte0]: 43
3211 18:02:03.619892 [Byte1]: 43
3212 18:02:03.619981
3213 18:02:03.620070 Set Vref, RX VrefLevel [Byte0]: 44
3214 18:02:03.620160 [Byte1]: 44
3215 18:02:03.620249
3216 18:02:03.620387 Set Vref, RX VrefLevel [Byte0]: 45
3217 18:02:03.620483 [Byte1]: 45
3218 18:02:03.620574
3219 18:02:03.620665 Set Vref, RX VrefLevel [Byte0]: 46
3220 18:02:03.620757 [Byte1]: 46
3221 18:02:03.620891
3222 18:02:03.620988 Set Vref, RX VrefLevel [Byte0]: 47
3223 18:02:03.621080 [Byte1]: 47
3224 18:02:03.621172
3225 18:02:03.621260 Set Vref, RX VrefLevel [Byte0]: 48
3226 18:02:03.621350 [Byte1]: 48
3227 18:02:03.621448
3228 18:02:03.621524 Set Vref, RX VrefLevel [Byte0]: 49
3229 18:02:03.621603 [Byte1]: 49
3230 18:02:03.621680
3231 18:02:03.621757 Set Vref, RX VrefLevel [Byte0]: 50
3232 18:02:03.621834 [Byte1]: 50
3233 18:02:03.621910
3234 18:02:03.621987 Set Vref, RX VrefLevel [Byte0]: 51
3235 18:02:03.622063 [Byte1]: 51
3236 18:02:03.622140
3237 18:02:03.622225 Set Vref, RX VrefLevel [Byte0]: 52
3238 18:02:03.622307 [Byte1]: 52
3239 18:02:03.622384
3240 18:02:03.622460 Set Vref, RX VrefLevel [Byte0]: 53
3241 18:02:03.622537 [Byte1]: 53
3242 18:02:03.622613
3243 18:02:03.622690 Set Vref, RX VrefLevel [Byte0]: 54
3244 18:02:03.622767 [Byte1]: 54
3245 18:02:03.622843
3246 18:02:03.622919 Set Vref, RX VrefLevel [Byte0]: 55
3247 18:02:03.622995 [Byte1]: 55
3248 18:02:03.623072
3249 18:02:03.623149 Set Vref, RX VrefLevel [Byte0]: 56
3250 18:02:03.623226 [Byte1]: 56
3251 18:02:03.623303
3252 18:02:03.623379 Set Vref, RX VrefLevel [Byte0]: 57
3253 18:02:03.623455 [Byte1]: 57
3254 18:02:03.623532
3255 18:02:03.623606 Set Vref, RX VrefLevel [Byte0]: 58
3256 18:02:03.623682 [Byte1]: 58
3257 18:02:03.623759
3258 18:02:03.623836 Set Vref, RX VrefLevel [Byte0]: 59
3259 18:02:03.623913 [Byte1]: 59
3260 18:02:03.623990
3261 18:02:03.624081 Set Vref, RX VrefLevel [Byte0]: 60
3262 18:02:03.624176 [Byte1]: 60
3263 18:02:03.624255
3264 18:02:03.624331 Set Vref, RX VrefLevel [Byte0]: 61
3265 18:02:03.624408 [Byte1]: 61
3266 18:02:03.624502
3267 18:02:03.624591 Set Vref, RX VrefLevel [Byte0]: 62
3268 18:02:03.624669 [Byte1]: 62
3269 18:02:03.624746
3270 18:02:03.624822 Set Vref, RX VrefLevel [Byte0]: 63
3271 18:02:03.624901 [Byte1]: 63
3272 18:02:03.624978
3273 18:02:03.625054 Set Vref, RX VrefLevel [Byte0]: 64
3274 18:02:03.625132 [Byte1]: 64
3275 18:02:03.625209
3276 18:02:03.625285 Set Vref, RX VrefLevel [Byte0]: 65
3277 18:02:03.625363 [Byte1]: 65
3278 18:02:03.625439
3279 18:02:03.625516 Set Vref, RX VrefLevel [Byte0]: 66
3280 18:02:03.625592 [Byte1]: 66
3281 18:02:03.625669
3282 18:02:03.625745 Final RX Vref Byte 0 = 56 to rank0
3283 18:02:03.625822 Final RX Vref Byte 1 = 48 to rank0
3284 18:02:03.625898 Final RX Vref Byte 0 = 56 to rank1
3285 18:02:03.625975 Final RX Vref Byte 1 = 48 to rank1==
3286 18:02:03.626053 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 18:02:03.626131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3288 18:02:03.626216 ==
3289 18:02:03.626299 DQS Delay:
3290 18:02:03.626376 DQS0 = 0, DQS1 = 0
3291 18:02:03.626461 DQM Delay:
3292 18:02:03.626528 DQM0 = 114, DQM1 = 105
3293 18:02:03.626594 DQ Delay:
3294 18:02:03.626864 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =114
3295 18:02:03.626941 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3296 18:02:03.627011 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =96
3297 18:02:03.627080 DQ12 =112, DQ13 =114, DQ14 =116, DQ15 =114
3298 18:02:03.627147
3299 18:02:03.627215
3300 18:02:03.627284 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3301 18:02:03.627354 CH1 RK0: MR19=404, MR18=1414
3302 18:02:03.627422 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3303 18:02:03.627490
3304 18:02:03.627589 ----->DramcWriteLeveling(PI) begin...
3305 18:02:03.627679 ==
3306 18:02:03.627760 Dram Type= 6, Freq= 0, CH_1, rank 1
3307 18:02:03.627829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3308 18:02:03.627898 ==
3309 18:02:03.627966 Write leveling (Byte 0): 21 => 21
3310 18:02:03.628034 Write leveling (Byte 1): 22 => 22
3311 18:02:03.628102 DramcWriteLeveling(PI) end<-----
3312 18:02:03.628169
3313 18:02:03.628236 ==
3314 18:02:03.628303 Dram Type= 6, Freq= 0, CH_1, rank 1
3315 18:02:03.628372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3316 18:02:03.628439 ==
3317 18:02:03.628506 [Gating] SW mode calibration
3318 18:02:03.628573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3319 18:02:03.628642 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3320 18:02:03.628711 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3321 18:02:03.628780 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3322 18:02:03.628848 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3323 18:02:03.628916 0 11 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
3324 18:02:03.628984 0 11 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
3325 18:02:03.629051 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3326 18:02:03.629118 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3327 18:02:03.629186 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3328 18:02:03.629253 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3329 18:02:03.629321 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3330 18:02:03.629389 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3331 18:02:03.629455 0 12 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
3332 18:02:03.629523 0 12 16 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
3333 18:02:03.629589 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 18:02:03.629656 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3335 18:02:03.629723 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3336 18:02:03.629790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3337 18:02:03.629857 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3338 18:02:03.629925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3339 18:02:03.629993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3340 18:02:03.630060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3341 18:02:03.630128 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3342 18:02:03.630195 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3343 18:02:03.630274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3344 18:02:03.630343 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3345 18:02:03.630411 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3346 18:02:03.630478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3347 18:02:03.630545 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3348 18:02:03.630612 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3349 18:02:03.630717 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3350 18:02:03.630789 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 18:02:03.630858 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 18:02:03.630926 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 18:02:03.630994 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 18:02:03.631062 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 18:02:03.631131 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3356 18:02:03.631210 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3357 18:02:03.631296 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3358 18:02:03.631365 Total UI for P1: 0, mck2ui 16
3359 18:02:03.631434 best dqsien dly found for B0: ( 0, 15, 14)
3360 18:02:03.631510 Total UI for P1: 0, mck2ui 16
3361 18:02:03.631571 best dqsien dly found for B1: ( 0, 15, 16)
3362 18:02:03.631631 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3363 18:02:03.631691 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3364 18:02:03.631751
3365 18:02:03.631810 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3366 18:02:03.631869 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3367 18:02:03.631928 [Gating] SW calibration Done
3368 18:02:03.631987 ==
3369 18:02:03.632048 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 18:02:03.632108 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 18:02:03.632168 ==
3372 18:02:03.632228 RX Vref Scan: 0
3373 18:02:03.632287
3374 18:02:03.632346 RX Vref 0 -> 0, step: 1
3375 18:02:03.632406
3376 18:02:03.632464 RX Delay -40 -> 252, step: 8
3377 18:02:03.632524 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3378 18:02:03.632583 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3379 18:02:03.632643 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3380 18:02:03.632702 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3381 18:02:03.632761 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3382 18:02:03.632821 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3383 18:02:03.632880 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3384 18:02:03.632940 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3385 18:02:03.632999 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3386 18:02:03.633058 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
3387 18:02:03.633117 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3388 18:02:03.633176 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3389 18:02:03.633236 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3390 18:02:03.633295 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3391 18:02:03.633355 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3392 18:02:03.633414 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3393 18:02:03.633473 ==
3394 18:02:03.633533 Dram Type= 6, Freq= 0, CH_1, rank 1
3395 18:02:03.633790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3396 18:02:03.633861 ==
3397 18:02:03.633922 DQS Delay:
3398 18:02:03.633983 DQS0 = 0, DQS1 = 0
3399 18:02:03.634043 DQM Delay:
3400 18:02:03.634106 DQM0 = 114, DQM1 = 105
3401 18:02:03.634200 DQ Delay:
3402 18:02:03.634288 DQ0 =115, DQ1 =107, DQ2 =107, DQ3 =115
3403 18:02:03.634364 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =111
3404 18:02:03.634426 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =95
3405 18:02:03.634488 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3406 18:02:03.634548
3407 18:02:03.634607
3408 18:02:03.634665 ==
3409 18:02:03.634724 Dram Type= 6, Freq= 0, CH_1, rank 1
3410 18:02:03.634784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3411 18:02:03.634845 ==
3412 18:02:03.634905
3413 18:02:03.634965
3414 18:02:03.635024 TX Vref Scan disable
3415 18:02:03.635083 == TX Byte 0 ==
3416 18:02:03.635143 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3417 18:02:03.635204 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3418 18:02:03.635263 == TX Byte 1 ==
3419 18:02:03.635323 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3420 18:02:03.635383 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3421 18:02:03.635442 ==
3422 18:02:03.635502 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 18:02:03.635562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3424 18:02:03.635622 ==
3425 18:02:03.635682 TX Vref=22, minBit 9, minWin=25, winSum=423
3426 18:02:03.635743 TX Vref=24, minBit 8, minWin=26, winSum=429
3427 18:02:03.635803 TX Vref=26, minBit 9, minWin=25, winSum=428
3428 18:02:03.635863 TX Vref=28, minBit 3, minWin=26, winSum=429
3429 18:02:03.635924 TX Vref=30, minBit 8, minWin=26, winSum=432
3430 18:02:03.635984 TX Vref=32, minBit 0, minWin=26, winSum=432
3431 18:02:03.636045 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3432 18:02:03.636105
3433 18:02:03.636165 Final TX Range 1 Vref 30
3434 18:02:03.636224
3435 18:02:03.636283 ==
3436 18:02:03.636343 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 18:02:03.636402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3438 18:02:03.636473 ==
3439 18:02:03.636527
3440 18:02:03.636581
3441 18:02:03.636634 TX Vref Scan disable
3442 18:02:03.636704 == TX Byte 0 ==
3443 18:02:03.636761 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3444 18:02:03.636815 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3445 18:02:03.636870 == TX Byte 1 ==
3446 18:02:03.636923 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3447 18:02:03.636977 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3448 18:02:03.637031
3449 18:02:03.637084 [DATLAT]
3450 18:02:03.637146 Freq=1200, CH1 RK1
3451 18:02:03.637216
3452 18:02:03.637271 DATLAT Default: 0xc
3453 18:02:03.637326 0, 0xFFFF, sum = 0
3454 18:02:03.637381 1, 0xFFFF, sum = 0
3455 18:02:03.637435 2, 0xFFFF, sum = 0
3456 18:02:03.637489 3, 0xFFFF, sum = 0
3457 18:02:03.637544 4, 0xFFFF, sum = 0
3458 18:02:03.637599 5, 0xFFFF, sum = 0
3459 18:02:03.637656 6, 0xFFFF, sum = 0
3460 18:02:03.637710 7, 0xFFFF, sum = 0
3461 18:02:03.637796 8, 0xFFFF, sum = 0
3462 18:02:03.637855 9, 0xFFFF, sum = 0
3463 18:02:03.637911 10, 0xFFFF, sum = 0
3464 18:02:03.637967 11, 0x0, sum = 1
3465 18:02:03.638022 12, 0x0, sum = 2
3466 18:02:03.638076 13, 0x0, sum = 3
3467 18:02:03.638130 14, 0x0, sum = 4
3468 18:02:03.638185 best_step = 12
3469 18:02:03.638249
3470 18:02:03.638304 ==
3471 18:02:03.638358 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 18:02:03.638412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3473 18:02:03.638467 ==
3474 18:02:03.638520 RX Vref Scan: 0
3475 18:02:03.638574
3476 18:02:03.638628 RX Vref 0 -> 0, step: 1
3477 18:02:03.638683
3478 18:02:03.638756 RX Delay -21 -> 252, step: 4
3479 18:02:03.638810 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3480 18:02:03.638864 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3481 18:02:03.638919 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3482 18:02:03.638973 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3483 18:02:03.639026 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3484 18:02:03.639080 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3485 18:02:03.639135 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3486 18:02:03.639189 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3487 18:02:03.639242 iDelay=199, Bit 8, Center 84 (19 ~ 150) 132
3488 18:02:03.639296 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3489 18:02:03.639350 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3490 18:02:03.639404 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3491 18:02:03.639458 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3492 18:02:03.639511 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3493 18:02:03.639565 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3494 18:02:03.639619 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3495 18:02:03.639673 ==
3496 18:02:03.639726 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 18:02:03.639780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3498 18:02:03.639835 ==
3499 18:02:03.639888 DQS Delay:
3500 18:02:03.639942 DQS0 = 0, DQS1 = 0
3501 18:02:03.639995 DQM Delay:
3502 18:02:03.640049 DQM0 = 114, DQM1 = 103
3503 18:02:03.640102 DQ Delay:
3504 18:02:03.640155 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3505 18:02:03.640209 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3506 18:02:03.640262 DQ8 =84, DQ9 =90, DQ10 =106, DQ11 =96
3507 18:02:03.640315 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3508 18:02:03.640367
3509 18:02:03.640421
3510 18:02:03.640474 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3511 18:02:03.640529 CH1 RK1: MR19=404, MR18=C0C
3512 18:02:03.640582 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3513 18:02:03.640663 [RxdqsGatingPostProcess] freq 1200
3514 18:02:03.640753 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3515 18:02:03.640829 Pre-setting of DQS Precalculation
3516 18:02:03.640886 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3517 18:02:03.640941 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3518 18:02:03.640997 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3519 18:02:03.641051
3520 18:02:03.641135
3521 18:02:03.641194 [Calibration Summary] 2400 Mbps
3522 18:02:03.641250 CH 0, Rank 0
3523 18:02:03.641306 SW Impedance : PASS
3524 18:02:03.641361 DUTY Scan : NO K
3525 18:02:03.641427 ZQ Calibration : PASS
3526 18:02:03.641476 Jitter Meter : NO K
3527 18:02:03.641525 CBT Training : PASS
3528 18:02:03.641573 Write leveling : PASS
3529 18:02:03.641621 RX DQS gating : PASS
3530 18:02:03.641670 RX DQ/DQS(RDDQC) : PASS
3531 18:02:03.641719 TX DQ/DQS : PASS
3532 18:02:03.641769 RX DATLAT : PASS
3533 18:02:03.641818 RX DQ/DQS(Engine): PASS
3534 18:02:03.641866 TX OE : NO K
3535 18:02:03.641914 All Pass.
3536 18:02:03.641963
3537 18:02:03.642012 CH 0, Rank 1
3538 18:02:03.642060 SW Impedance : PASS
3539 18:02:03.642108 DUTY Scan : NO K
3540 18:02:03.642157 ZQ Calibration : PASS
3541 18:02:03.642206 Jitter Meter : NO K
3542 18:02:03.642453 CBT Training : PASS
3543 18:02:03.642510 Write leveling : PASS
3544 18:02:03.642560 RX DQS gating : PASS
3545 18:02:03.642610 RX DQ/DQS(RDDQC) : PASS
3546 18:02:03.642658 TX DQ/DQS : PASS
3547 18:02:03.642707 RX DATLAT : PASS
3548 18:02:03.642755 RX DQ/DQS(Engine): PASS
3549 18:02:03.642804 TX OE : NO K
3550 18:02:03.642853 All Pass.
3551 18:02:03.642903
3552 18:02:03.642952 CH 1, Rank 0
3553 18:02:03.643000 SW Impedance : PASS
3554 18:02:03.643049 DUTY Scan : NO K
3555 18:02:03.643098 ZQ Calibration : PASS
3556 18:02:03.643146 Jitter Meter : NO K
3557 18:02:03.643194 CBT Training : PASS
3558 18:02:03.643242 Write leveling : PASS
3559 18:02:03.643290 RX DQS gating : PASS
3560 18:02:03.643339 RX DQ/DQS(RDDQC) : PASS
3561 18:02:03.643388 TX DQ/DQS : PASS
3562 18:02:03.643437 RX DATLAT : PASS
3563 18:02:03.643486 RX DQ/DQS(Engine): PASS
3564 18:02:03.643534 TX OE : NO K
3565 18:02:03.643584 All Pass.
3566 18:02:03.643634
3567 18:02:03.643682 CH 1, Rank 1
3568 18:02:03.643730 SW Impedance : PASS
3569 18:02:03.643779 DUTY Scan : NO K
3570 18:02:03.643827 ZQ Calibration : PASS
3571 18:02:03.643876 Jitter Meter : NO K
3572 18:02:03.643924 CBT Training : PASS
3573 18:02:03.643972 Write leveling : PASS
3574 18:02:03.644020 RX DQS gating : PASS
3575 18:02:03.644068 RX DQ/DQS(RDDQC) : PASS
3576 18:02:03.644116 TX DQ/DQS : PASS
3577 18:02:03.644185 RX DATLAT : PASS
3578 18:02:03.644263 RX DQ/DQS(Engine): PASS
3579 18:02:03.644316 TX OE : NO K
3580 18:02:03.644366 All Pass.
3581 18:02:03.644415
3582 18:02:03.644464 DramC Write-DBI off
3583 18:02:03.644513 PER_BANK_REFRESH: Hybrid Mode
3584 18:02:03.644562 TX_TRACKING: ON
3585 18:02:03.644610 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3586 18:02:03.644660 [FAST_K] Save calibration result to emmc
3587 18:02:03.644710 dramc_set_vcore_voltage set vcore to 650000
3588 18:02:03.644759 Read voltage for 600, 5
3589 18:02:03.644807 Vio18 = 0
3590 18:02:03.644855 Vcore = 650000
3591 18:02:03.644904 Vdram = 0
3592 18:02:03.644952 Vddq = 0
3593 18:02:03.645001 Vmddr = 0
3594 18:02:03.645049 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3595 18:02:03.645098 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3596 18:02:03.645147 MEM_TYPE=3, freq_sel=19
3597 18:02:03.645195 sv_algorithm_assistance_LP4_1600
3598 18:02:03.645244 ============ PULL DRAM RESETB DOWN ============
3599 18:02:03.645294 ========== PULL DRAM RESETB DOWN end =========
3600 18:02:03.645343 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3601 18:02:03.645391 ===================================
3602 18:02:03.645440 LPDDR4 DRAM CONFIGURATION
3603 18:02:03.645489 ===================================
3604 18:02:03.645537 EX_ROW_EN[0] = 0x0
3605 18:02:03.645585 EX_ROW_EN[1] = 0x0
3606 18:02:03.645633 LP4Y_EN = 0x0
3607 18:02:03.645683 WORK_FSP = 0x0
3608 18:02:03.645733 WL = 0x2
3609 18:02:03.645781 RL = 0x2
3610 18:02:03.645829 BL = 0x2
3611 18:02:03.645878 RPST = 0x0
3612 18:02:03.645926 RD_PRE = 0x0
3613 18:02:03.645974 WR_PRE = 0x1
3614 18:02:03.646023 WR_PST = 0x0
3615 18:02:03.646071 DBI_WR = 0x0
3616 18:02:03.646120 DBI_RD = 0x0
3617 18:02:03.646168 OTF = 0x1
3618 18:02:03.646223 ===================================
3619 18:02:03.646274 ===================================
3620 18:02:03.646324 ANA top config
3621 18:02:03.646373 ===================================
3622 18:02:03.646423 DLL_ASYNC_EN = 0
3623 18:02:03.646484 ALL_SLAVE_EN = 1
3624 18:02:03.646531 NEW_RANK_MODE = 1
3625 18:02:03.646579 DLL_IDLE_MODE = 1
3626 18:02:03.646627 LP45_APHY_COMB_EN = 1
3627 18:02:03.646675 TX_ODT_DIS = 1
3628 18:02:03.646722 NEW_8X_MODE = 1
3629 18:02:03.646771 ===================================
3630 18:02:03.646819 ===================================
3631 18:02:03.646867 data_rate = 1200
3632 18:02:03.646914 CKR = 1
3633 18:02:03.646961 DQ_P2S_RATIO = 8
3634 18:02:03.647009 ===================================
3635 18:02:03.647057 CA_P2S_RATIO = 8
3636 18:02:03.647105 DQ_CA_OPEN = 0
3637 18:02:03.647152 DQ_SEMI_OPEN = 0
3638 18:02:03.647199 CA_SEMI_OPEN = 0
3639 18:02:03.647246 CA_FULL_RATE = 0
3640 18:02:03.647293 DQ_CKDIV4_EN = 1
3641 18:02:03.647351 CA_CKDIV4_EN = 1
3642 18:02:03.647409 CA_PREDIV_EN = 0
3643 18:02:03.647457 PH8_DLY = 0
3644 18:02:03.647505 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3645 18:02:03.647553 DQ_AAMCK_DIV = 4
3646 18:02:03.647601 CA_AAMCK_DIV = 4
3647 18:02:03.647648 CA_ADMCK_DIV = 4
3648 18:02:03.647696 DQ_TRACK_CA_EN = 0
3649 18:02:03.647744 CA_PICK = 600
3650 18:02:03.647820 CA_MCKIO = 600
3651 18:02:03.647872 MCKIO_SEMI = 0
3652 18:02:03.647920 PLL_FREQ = 2288
3653 18:02:03.647968 DQ_UI_PI_RATIO = 32
3654 18:02:03.648016 CA_UI_PI_RATIO = 0
3655 18:02:03.648064 ===================================
3656 18:02:03.648112 ===================================
3657 18:02:03.648160 memory_type:LPDDR4
3658 18:02:03.648207 GP_NUM : 10
3659 18:02:03.648254 SRAM_EN : 1
3660 18:02:03.648301 MD32_EN : 0
3661 18:02:03.648347 ===================================
3662 18:02:03.648395 [ANA_INIT] >>>>>>>>>>>>>>
3663 18:02:03.648442 <<<<<< [CONFIGURE PHASE]: ANA_TX
3664 18:02:03.648490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3665 18:02:03.648537 ===================================
3666 18:02:03.648585 data_rate = 1200,PCW = 0X5800
3667 18:02:03.648632 ===================================
3668 18:02:03.648679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3669 18:02:03.648727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3670 18:02:03.648775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3671 18:02:03.648824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3672 18:02:03.648871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3673 18:02:03.648919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3674 18:02:03.648967 [ANA_INIT] flow start
3675 18:02:03.649014 [ANA_INIT] PLL >>>>>>>>
3676 18:02:03.649062 [ANA_INIT] PLL <<<<<<<<
3677 18:02:03.649108 [ANA_INIT] MIDPI >>>>>>>>
3678 18:02:03.649156 [ANA_INIT] MIDPI <<<<<<<<
3679 18:02:03.649203 [ANA_INIT] DLL >>>>>>>>
3680 18:02:03.649250 [ANA_INIT] flow end
3681 18:02:03.649298 ============ LP4 DIFF to SE enter ============
3682 18:02:03.649534 ============ LP4 DIFF to SE exit ============
3683 18:02:03.649588 [ANA_INIT] <<<<<<<<<<<<<
3684 18:02:03.649638 [Flow] Enable top DCM control >>>>>
3685 18:02:03.649686 [Flow] Enable top DCM control <<<<<
3686 18:02:03.649734 Enable DLL master slave shuffle
3687 18:02:03.649783 ==============================================================
3688 18:02:03.649833 Gating Mode config
3689 18:02:03.649881 ==============================================================
3690 18:02:03.649929 Config description:
3691 18:02:03.649978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3692 18:02:03.650027 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3693 18:02:03.650076 SELPH_MODE 0: By rank 1: By Phase
3694 18:02:03.650124 ==============================================================
3695 18:02:03.650172 GAT_TRACK_EN = 1
3696 18:02:03.650229 RX_GATING_MODE = 2
3697 18:02:03.650320 RX_GATING_TRACK_MODE = 2
3698 18:02:03.650368 SELPH_MODE = 1
3699 18:02:03.650416 PICG_EARLY_EN = 1
3700 18:02:03.650463 VALID_LAT_VALUE = 1
3701 18:02:03.650510 ==============================================================
3702 18:02:03.650558 Enter into Gating configuration >>>>
3703 18:02:03.650606 Exit from Gating configuration <<<<
3704 18:02:03.650679 Enter into DVFS_PRE_config >>>>>
3705 18:02:03.650733 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3706 18:02:03.650783 Exit from DVFS_PRE_config <<<<<
3707 18:02:03.650855 Enter into PICG configuration >>>>
3708 18:02:03.650906 Exit from PICG configuration <<<<
3709 18:02:03.650954 [RX_INPUT] configuration >>>>>
3710 18:02:03.651002 [RX_INPUT] configuration <<<<<
3711 18:02:03.651050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3712 18:02:03.651099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3713 18:02:03.651147 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3714 18:02:03.651196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3715 18:02:03.651244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3716 18:02:03.651293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3717 18:02:03.651340 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3718 18:02:03.651388 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3719 18:02:03.651437 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3720 18:02:03.651486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3721 18:02:03.651534 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3722 18:02:03.651583 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 18:02:03.651631 ===================================
3724 18:02:03.651679 LPDDR4 DRAM CONFIGURATION
3725 18:02:03.651726 ===================================
3726 18:02:03.651774 EX_ROW_EN[0] = 0x0
3727 18:02:03.651822 EX_ROW_EN[1] = 0x0
3728 18:02:03.651869 LP4Y_EN = 0x0
3729 18:02:03.651916 WORK_FSP = 0x0
3730 18:02:03.651964 WL = 0x2
3731 18:02:03.652011 RL = 0x2
3732 18:02:03.652058 BL = 0x2
3733 18:02:03.652105 RPST = 0x0
3734 18:02:03.652153 RD_PRE = 0x0
3735 18:02:03.652200 WR_PRE = 0x1
3736 18:02:03.652247 WR_PST = 0x0
3737 18:02:03.652294 DBI_WR = 0x0
3738 18:02:03.652341 DBI_RD = 0x0
3739 18:02:03.652389 OTF = 0x1
3740 18:02:03.652437 ===================================
3741 18:02:03.652485 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3742 18:02:03.652534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3743 18:02:03.652582 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 18:02:03.652629 ===================================
3745 18:02:03.652676 LPDDR4 DRAM CONFIGURATION
3746 18:02:03.652723 ===================================
3747 18:02:03.652771 EX_ROW_EN[0] = 0x10
3748 18:02:03.652819 EX_ROW_EN[1] = 0x0
3749 18:02:03.652866 LP4Y_EN = 0x0
3750 18:02:03.652913 WORK_FSP = 0x0
3751 18:02:03.652960 WL = 0x2
3752 18:02:03.653007 RL = 0x2
3753 18:02:03.653055 BL = 0x2
3754 18:02:03.653102 RPST = 0x0
3755 18:02:03.653149 RD_PRE = 0x0
3756 18:02:03.653196 WR_PRE = 0x1
3757 18:02:03.653243 WR_PST = 0x0
3758 18:02:03.653290 DBI_WR = 0x0
3759 18:02:03.653338 DBI_RD = 0x0
3760 18:02:03.653385 OTF = 0x1
3761 18:02:03.653434 ===================================
3762 18:02:03.653482 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3763 18:02:03.653531 nWR fixed to 30
3764 18:02:03.653580 [ModeRegInit_LP4] CH0 RK0
3765 18:02:03.653626 [ModeRegInit_LP4] CH0 RK1
3766 18:02:03.653673 [ModeRegInit_LP4] CH1 RK0
3767 18:02:03.653720 [ModeRegInit_LP4] CH1 RK1
3768 18:02:03.653768 match AC timing 16
3769 18:02:03.653816 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3770 18:02:03.653864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3771 18:02:03.653912 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3772 18:02:03.653960 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3773 18:02:03.654008 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3774 18:02:03.654055 ==
3775 18:02:03.654103 Dram Type= 6, Freq= 0, CH_0, rank 0
3776 18:02:03.654151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3777 18:02:03.654199 ==
3778 18:02:03.654323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3779 18:02:03.654385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3780 18:02:03.654456 [CA 0] Center 35 (5~66) winsize 62
3781 18:02:03.654507 [CA 1] Center 35 (5~66) winsize 62
3782 18:02:03.654555 [CA 2] Center 34 (4~65) winsize 62
3783 18:02:03.654603 [CA 3] Center 34 (3~65) winsize 63
3784 18:02:03.654652 [CA 4] Center 33 (3~64) winsize 62
3785 18:02:03.654699 [CA 5] Center 33 (3~64) winsize 62
3786 18:02:03.654746
3787 18:02:03.654794 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3788 18:02:03.654841
3789 18:02:03.654890 [CATrainingPosCal] consider 1 rank data
3790 18:02:03.654937 u2DelayCellTimex100 = 270/100 ps
3791 18:02:03.655173 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3792 18:02:03.655228 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3793 18:02:03.655278 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3794 18:02:03.655327 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3795 18:02:03.655375 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3796 18:02:03.655424 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3797 18:02:03.655471
3798 18:02:03.655530 CA PerBit enable=1, Macro0, CA PI delay=33
3799 18:02:03.655582
3800 18:02:03.655631 [CBTSetCACLKResult] CA Dly = 33
3801 18:02:03.655680 CS Dly: 5 (0~36)
3802 18:02:03.655728 ==
3803 18:02:03.655776 Dram Type= 6, Freq= 0, CH_0, rank 1
3804 18:02:03.655824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3805 18:02:03.655873 ==
3806 18:02:03.655920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3807 18:02:03.655969 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3808 18:02:03.656017 [CA 0] Center 36 (6~66) winsize 61
3809 18:02:03.656065 [CA 1] Center 35 (5~66) winsize 62
3810 18:02:03.656113 [CA 2] Center 34 (4~65) winsize 62
3811 18:02:03.656160 [CA 3] Center 34 (4~65) winsize 62
3812 18:02:03.656207 [CA 4] Center 33 (3~64) winsize 62
3813 18:02:03.656255 [CA 5] Center 33 (3~64) winsize 62
3814 18:02:03.656302
3815 18:02:03.656349 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3816 18:02:03.656396
3817 18:02:03.656443 [CATrainingPosCal] consider 2 rank data
3818 18:02:03.656491 u2DelayCellTimex100 = 270/100 ps
3819 18:02:03.656539 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3820 18:02:03.656600 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3821 18:02:03.656650 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3822 18:02:03.656698 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3823 18:02:03.656746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3824 18:02:03.656795 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3825 18:02:03.656843
3826 18:02:03.656890 CA PerBit enable=1, Macro0, CA PI delay=33
3827 18:02:03.656938
3828 18:02:03.656986 [CBTSetCACLKResult] CA Dly = 33
3829 18:02:03.657034 CS Dly: 5 (0~36)
3830 18:02:03.657081
3831 18:02:03.657128 ----->DramcWriteLeveling(PI) begin...
3832 18:02:03.657177 ==
3833 18:02:03.657253 Dram Type= 6, Freq= 0, CH_0, rank 0
3834 18:02:03.657304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3835 18:02:03.657352 ==
3836 18:02:03.657401 Write leveling (Byte 0): 30 => 30
3837 18:02:03.657449 Write leveling (Byte 1): 30 => 30
3838 18:02:03.657498 DramcWriteLeveling(PI) end<-----
3839 18:02:03.657546
3840 18:02:03.657595 ==
3841 18:02:03.657642 Dram Type= 6, Freq= 0, CH_0, rank 0
3842 18:02:03.657690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3843 18:02:03.657738 ==
3844 18:02:03.657785 [Gating] SW mode calibration
3845 18:02:03.657833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3846 18:02:03.657882 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3847 18:02:03.657930 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3848 18:02:03.657979 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3849 18:02:03.658058 0 5 8 | B1->B0 | 3232 3030 | 0 1 | (0 1) (1 0)
3850 18:02:03.658135 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3851 18:02:03.658219 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3852 18:02:03.658308 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3853 18:02:03.658358 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3854 18:02:03.658406 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3855 18:02:03.658454 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3856 18:02:03.658502 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3857 18:02:03.658550 0 6 8 | B1->B0 | 2828 3232 | 0 1 | (0 0) (0 0)
3858 18:02:03.658598 0 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3859 18:02:03.658647 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3860 18:02:03.658695 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 18:02:03.658743 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3862 18:02:03.658791 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3863 18:02:03.658839 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3864 18:02:03.658887 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3865 18:02:03.658935 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3866 18:02:03.658983 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3867 18:02:03.659031 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3868 18:02:03.659079 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3869 18:02:03.659127 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3870 18:02:03.659175 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3871 18:02:03.659223 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3872 18:02:03.659271 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3873 18:02:03.659319 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3874 18:02:03.659367 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3875 18:02:03.659415 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 18:02:03.659462 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 18:02:03.659510 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 18:02:03.659558 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 18:02:03.659606 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 18:02:03.659655 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3881 18:02:03.659702 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3882 18:02:03.659750 Total UI for P1: 0, mck2ui 16
3883 18:02:03.659798 best dqsien dly found for B0: ( 0, 9, 4)
3884 18:02:03.659846 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3885 18:02:03.659893 Total UI for P1: 0, mck2ui 16
3886 18:02:03.659941 best dqsien dly found for B1: ( 0, 9, 8)
3887 18:02:03.659988 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
3888 18:02:03.660036 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3889 18:02:03.660084
3890 18:02:03.660131 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
3891 18:02:03.660180 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3892 18:02:03.660227 [Gating] SW calibration Done
3893 18:02:03.660275 ==
3894 18:02:03.660322 Dram Type= 6, Freq= 0, CH_0, rank 0
3895 18:02:03.660370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3896 18:02:03.660418 ==
3897 18:02:03.660465 RX Vref Scan: 0
3898 18:02:03.660512
3899 18:02:03.660559 RX Vref 0 -> 0, step: 1
3900 18:02:03.660606
3901 18:02:03.660844 RX Delay -230 -> 252, step: 16
3902 18:02:03.660902 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3903 18:02:03.660952 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3904 18:02:03.661001 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3905 18:02:03.661050 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3906 18:02:03.661098 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3907 18:02:03.661146 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3908 18:02:03.661194 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3909 18:02:03.661243 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3910 18:02:03.661290 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3911 18:02:03.661347 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3912 18:02:03.661408 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3913 18:02:03.661457 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3914 18:02:03.661505 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3915 18:02:03.661553 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3916 18:02:03.661600 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3917 18:02:03.661647 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3918 18:02:03.661694 ==
3919 18:02:03.661742 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 18:02:03.661790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3921 18:02:03.661838 ==
3922 18:02:03.661886 DQS Delay:
3923 18:02:03.661934 DQS0 = 0, DQS1 = 0
3924 18:02:03.661981 DQM Delay:
3925 18:02:03.662028 DQM0 = 38, DQM1 = 33
3926 18:02:03.662076 DQ Delay:
3927 18:02:03.662123 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3928 18:02:03.662170 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3929 18:02:03.662224 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3930 18:02:03.662314 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3931 18:02:03.662362
3932 18:02:03.662409
3933 18:02:03.662456 ==
3934 18:02:03.662504 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 18:02:03.662552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 18:02:03.662599 ==
3937 18:02:03.662646
3938 18:02:03.662693
3939 18:02:03.662740 TX Vref Scan disable
3940 18:02:03.662788 == TX Byte 0 ==
3941 18:02:03.662835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3942 18:02:03.662883 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3943 18:02:03.662932 == TX Byte 1 ==
3944 18:02:03.662980 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3945 18:02:03.663028 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3946 18:02:03.663075 ==
3947 18:02:03.663123 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 18:02:03.663170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3949 18:02:03.663217 ==
3950 18:02:03.663265
3951 18:02:03.663312
3952 18:02:03.663359 TX Vref Scan disable
3953 18:02:03.663407 == TX Byte 0 ==
3954 18:02:03.663455 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3955 18:02:03.663502 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3956 18:02:03.663550 == TX Byte 1 ==
3957 18:02:03.663597 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3958 18:02:03.663645 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3959 18:02:03.663692
3960 18:02:03.663739 [DATLAT]
3961 18:02:03.663787 Freq=600, CH0 RK0
3962 18:02:03.663851
3963 18:02:03.663937 DATLAT Default: 0x9
3964 18:02:03.663990 0, 0xFFFF, sum = 0
3965 18:02:03.664040 1, 0xFFFF, sum = 0
3966 18:02:03.664089 2, 0xFFFF, sum = 0
3967 18:02:03.664139 3, 0xFFFF, sum = 0
3968 18:02:03.664188 4, 0xFFFF, sum = 0
3969 18:02:03.664236 5, 0xFFFF, sum = 0
3970 18:02:03.664284 6, 0xFFFF, sum = 0
3971 18:02:03.664333 7, 0x0, sum = 1
3972 18:02:03.664380 8, 0x0, sum = 2
3973 18:02:03.664428 9, 0x0, sum = 3
3974 18:02:03.664477 10, 0x0, sum = 4
3975 18:02:03.664526 best_step = 8
3976 18:02:03.664574
3977 18:02:03.664622 ==
3978 18:02:03.664670 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 18:02:03.664719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3980 18:02:03.664767 ==
3981 18:02:03.664814 RX Vref Scan: 1
3982 18:02:03.664861
3983 18:02:03.664908 RX Vref 0 -> 0, step: 1
3984 18:02:03.664956
3985 18:02:03.665003 RX Delay -195 -> 252, step: 8
3986 18:02:03.665050
3987 18:02:03.665097 Set Vref, RX VrefLevel [Byte0]: 46
3988 18:02:03.665145 [Byte1]: 48
3989 18:02:03.665193
3990 18:02:03.665240 Final RX Vref Byte 0 = 46 to rank0
3991 18:02:03.665288 Final RX Vref Byte 1 = 48 to rank0
3992 18:02:03.665336 Final RX Vref Byte 0 = 46 to rank1
3993 18:02:03.665383 Final RX Vref Byte 1 = 48 to rank1==
3994 18:02:03.665431 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 18:02:03.665479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3996 18:02:03.665527 ==
3997 18:02:03.855189 DQS Delay:
3998 18:02:03.855632 DQS0 = 0, DQS1 = 0
3999 18:02:03.855988 DQM Delay:
4000 18:02:03.856279 DQM0 = 39, DQM1 = 29
4001 18:02:03.856548 DQ Delay:
4002 18:02:03.856810 DQ0 =32, DQ1 =40, DQ2 =36, DQ3 =36
4003 18:02:03.857132 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4004 18:02:03.857392 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4005 18:02:03.857647 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4006 18:02:03.857897
4007 18:02:03.858149
4008 18:02:03.858555 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4009 18:02:03.858838 CH0 RK0: MR19=808, MR18=5858
4010 18:02:03.859097 CH0_RK0: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4011 18:02:03.859350
4012 18:02:03.859601 ----->DramcWriteLeveling(PI) begin...
4013 18:02:03.859860 ==
4014 18:02:03.860114 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 18:02:03.860382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4016 18:02:03.860640 ==
4017 18:02:03.860889 Write leveling (Byte 0): 30 => 30
4018 18:02:03.861138 Write leveling (Byte 1): 30 => 30
4019 18:02:03.861386 DramcWriteLeveling(PI) end<-----
4020 18:02:03.861629
4021 18:02:03.861874 ==
4022 18:02:03.862121 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 18:02:03.862414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 18:02:03.862673 ==
4025 18:02:03.862924 [Gating] SW mode calibration
4026 18:02:03.863171 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4027 18:02:03.863433 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4028 18:02:03.863688 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 18:02:03.863943 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 18:02:03.864193 0 5 8 | B1->B0 | 3333 3131 | 1 0 | (1 0) (0 0)
4031 18:02:03.864460 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4032 18:02:03.864938 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 18:02:03.865224 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 18:02:03.865477 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 18:02:03.865727 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 18:02:03.865978 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 18:02:03.866260 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 18:02:03.866522 0 6 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4039 18:02:03.867107 0 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4040 18:02:03.867389 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 18:02:03.867650 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 18:02:03.867900 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 18:02:03.868148 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 18:02:03.868396 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 18:02:03.868646 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 18:02:03.868894 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4047 18:02:03.869141 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4048 18:02:03.869388 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 18:02:03.869635 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 18:02:03.869883 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 18:02:03.870125 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 18:02:03.870424 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 18:02:03.870676 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 18:02:03.870924 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 18:02:03.871174 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 18:02:03.871422 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 18:02:03.871667 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 18:02:03.871913 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 18:02:03.872159 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 18:02:03.872405 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 18:02:03.872653 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 18:02:03.872959 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4063 18:02:03.875626 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 18:02:03.878925 Total UI for P1: 0, mck2ui 16
4065 18:02:03.882487 best dqsien dly found for B0: ( 0, 9, 8)
4066 18:02:03.882767 Total UI for P1: 0, mck2ui 16
4067 18:02:03.889112 best dqsien dly found for B1: ( 0, 9, 8)
4068 18:02:03.892105 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4069 18:02:03.895618 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4070 18:02:03.895896
4071 18:02:03.899339 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4072 18:02:03.902167 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4073 18:02:03.905861 [Gating] SW calibration Done
4074 18:02:03.906169 ==
4075 18:02:03.908952 Dram Type= 6, Freq= 0, CH_0, rank 1
4076 18:02:03.912655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4077 18:02:03.912958 ==
4078 18:02:03.915782 RX Vref Scan: 0
4079 18:02:03.916061
4080 18:02:03.916278 RX Vref 0 -> 0, step: 1
4081 18:02:03.916485
4082 18:02:03.918923 RX Delay -230 -> 252, step: 16
4083 18:02:03.926024 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4084 18:02:03.928622 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4085 18:02:03.932066 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4086 18:02:03.935693 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4087 18:02:03.939204 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4088 18:02:03.945241 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4089 18:02:03.949081 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4090 18:02:03.952135 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4091 18:02:03.955434 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4092 18:02:03.961941 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4093 18:02:03.965278 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4094 18:02:03.968813 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4095 18:02:03.971979 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4096 18:02:03.978513 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4097 18:02:03.982049 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4098 18:02:03.984993 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4099 18:02:03.985383 ==
4100 18:02:03.988337 Dram Type= 6, Freq= 0, CH_0, rank 1
4101 18:02:03.991961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4102 18:02:03.992355 ==
4103 18:02:03.994917 DQS Delay:
4104 18:02:03.995308 DQS0 = 0, DQS1 = 0
4105 18:02:03.998525 DQM Delay:
4106 18:02:03.998917 DQM0 = 43, DQM1 = 33
4107 18:02:04.001841 DQ Delay:
4108 18:02:04.002254 DQ0 =33, DQ1 =49, DQ2 =41, DQ3 =41
4109 18:02:04.005186 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4110 18:02:04.008735 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4111 18:02:04.011550 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4112 18:02:04.011944
4113 18:02:04.014467
4114 18:02:04.014857 ==
4115 18:02:04.018260 Dram Type= 6, Freq= 0, CH_0, rank 1
4116 18:02:04.021482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4117 18:02:04.021969 ==
4118 18:02:04.022315
4119 18:02:04.022603
4120 18:02:04.024489 TX Vref Scan disable
4121 18:02:04.024879 == TX Byte 0 ==
4122 18:02:04.031351 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4123 18:02:04.034678 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4124 18:02:04.035088 == TX Byte 1 ==
4125 18:02:04.041459 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4126 18:02:04.044756 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4127 18:02:04.045150 ==
4128 18:02:04.047993 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 18:02:04.051249 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4130 18:02:04.051645 ==
4131 18:02:04.051950
4132 18:02:04.052228
4133 18:02:04.054495 TX Vref Scan disable
4134 18:02:04.057820 == TX Byte 0 ==
4135 18:02:04.061246 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 18:02:04.064319 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 18:02:04.067985 == TX Byte 1 ==
4138 18:02:04.070712 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4139 18:02:04.074240 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4140 18:02:04.077363
4141 18:02:04.077811 [DATLAT]
4142 18:02:04.078143 Freq=600, CH0 RK1
4143 18:02:04.078492
4144 18:02:04.080900 DATLAT Default: 0x8
4145 18:02:04.081307 0, 0xFFFF, sum = 0
4146 18:02:04.084101 1, 0xFFFF, sum = 0
4147 18:02:04.084611 2, 0xFFFF, sum = 0
4148 18:02:04.087744 3, 0xFFFF, sum = 0
4149 18:02:04.088243 4, 0xFFFF, sum = 0
4150 18:02:04.090685 5, 0xFFFF, sum = 0
4151 18:02:04.093951 6, 0xFFFF, sum = 0
4152 18:02:04.094451 7, 0x0, sum = 1
4153 18:02:04.094790 8, 0x0, sum = 2
4154 18:02:04.097446 9, 0x0, sum = 3
4155 18:02:04.097933 10, 0x0, sum = 4
4156 18:02:04.100662 best_step = 8
4157 18:02:04.101051
4158 18:02:04.101353 ==
4159 18:02:04.103917 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 18:02:04.107652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4161 18:02:04.108049 ==
4162 18:02:04.110708 RX Vref Scan: 0
4163 18:02:04.111097
4164 18:02:04.111399 RX Vref 0 -> 0, step: 1
4165 18:02:04.111685
4166 18:02:04.114304 RX Delay -195 -> 252, step: 8
4167 18:02:04.120968 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4168 18:02:04.124594 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4169 18:02:04.127684 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4170 18:02:04.131148 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4171 18:02:04.137831 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4172 18:02:04.140932 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4173 18:02:04.144080 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4174 18:02:04.147464 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4175 18:02:04.151186 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4176 18:02:04.157196 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4177 18:02:04.160574 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4178 18:02:04.163854 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4179 18:02:04.167494 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4180 18:02:04.173962 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4181 18:02:04.177503 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4182 18:02:04.180545 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4183 18:02:04.180632 ==
4184 18:02:04.184005 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 18:02:04.190538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 18:02:04.190624 ==
4187 18:02:04.190691 DQS Delay:
4188 18:02:04.190752 DQS0 = 0, DQS1 = 0
4189 18:02:04.193648 DQM Delay:
4190 18:02:04.193733 DQM0 = 40, DQM1 = 32
4191 18:02:04.197408 DQ Delay:
4192 18:02:04.200429 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4193 18:02:04.203578 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =48
4194 18:02:04.206696 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4195 18:02:04.209971 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4196 18:02:04.210071
4197 18:02:04.210149
4198 18:02:04.216862 [DQSOSCAuto] RK1, (LSB)MR18= 0x7070, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4199 18:02:04.219890 CH0 RK1: MR19=808, MR18=7070
4200 18:02:04.226584 CH0_RK1: MR19=0x808, MR18=0x7070, DQSOSC=388, MR23=63, INC=174, DEC=116
4201 18:02:04.230099 [RxdqsGatingPostProcess] freq 600
4202 18:02:04.233647 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4203 18:02:04.236763 Pre-setting of DQS Precalculation
4204 18:02:04.243606 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4205 18:02:04.243944 ==
4206 18:02:04.246975 Dram Type= 6, Freq= 0, CH_1, rank 0
4207 18:02:04.249953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4208 18:02:04.250327 ==
4209 18:02:04.256799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4210 18:02:04.263276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4211 18:02:04.266664 [CA 0] Center 35 (5~66) winsize 62
4212 18:02:04.269605 [CA 1] Center 35 (5~65) winsize 61
4213 18:02:04.273218 [CA 2] Center 33 (3~64) winsize 62
4214 18:02:04.276294 [CA 3] Center 33 (3~64) winsize 62
4215 18:02:04.279800 [CA 4] Center 33 (2~64) winsize 63
4216 18:02:04.282994 [CA 5] Center 33 (2~64) winsize 63
4217 18:02:04.283511
4218 18:02:04.286701 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4219 18:02:04.287093
4220 18:02:04.289720 [CATrainingPosCal] consider 1 rank data
4221 18:02:04.292858 u2DelayCellTimex100 = 270/100 ps
4222 18:02:04.296164 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4223 18:02:04.299951 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4224 18:02:04.302774 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4225 18:02:04.306278 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4226 18:02:04.309352 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4227 18:02:04.312885 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4228 18:02:04.313056
4229 18:02:04.319238 CA PerBit enable=1, Macro0, CA PI delay=33
4230 18:02:04.319381
4231 18:02:04.319492 [CBTSetCACLKResult] CA Dly = 33
4232 18:02:04.322099 CS Dly: 4 (0~35)
4233 18:02:04.322227 ==
4234 18:02:04.325668 Dram Type= 6, Freq= 0, CH_1, rank 1
4235 18:02:04.328791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4236 18:02:04.328898 ==
4237 18:02:04.335642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4238 18:02:04.342591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4239 18:02:04.345399 [CA 0] Center 35 (5~66) winsize 62
4240 18:02:04.348844 [CA 1] Center 34 (4~65) winsize 62
4241 18:02:04.351860 [CA 2] Center 33 (3~64) winsize 62
4242 18:02:04.355352 [CA 3] Center 33 (3~64) winsize 62
4243 18:02:04.358464 [CA 4] Center 32 (2~63) winsize 62
4244 18:02:04.362078 [CA 5] Center 32 (2~63) winsize 62
4245 18:02:04.362175
4246 18:02:04.364993 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4247 18:02:04.365200
4248 18:02:04.368433 [CATrainingPosCal] consider 2 rank data
4249 18:02:04.371847 u2DelayCellTimex100 = 270/100 ps
4250 18:02:04.374810 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4251 18:02:04.378329 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4252 18:02:04.381702 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4253 18:02:04.385206 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4254 18:02:04.388271 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4255 18:02:04.394934 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4256 18:02:04.395012
4257 18:02:04.398546 CA PerBit enable=1, Macro0, CA PI delay=32
4258 18:02:04.398622
4259 18:02:04.401720 [CBTSetCACLKResult] CA Dly = 32
4260 18:02:04.401797 CS Dly: 4 (0~36)
4261 18:02:04.401856
4262 18:02:04.404862 ----->DramcWriteLeveling(PI) begin...
4263 18:02:04.404940 ==
4264 18:02:04.408165 Dram Type= 6, Freq= 0, CH_1, rank 0
4265 18:02:04.414562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4266 18:02:04.414639 ==
4267 18:02:04.418397 Write leveling (Byte 0): 29 => 29
4268 18:02:04.421466 Write leveling (Byte 1): 30 => 30
4269 18:02:04.421542 DramcWriteLeveling(PI) end<-----
4270 18:02:04.421601
4271 18:02:04.424752 ==
4272 18:02:04.427799 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 18:02:04.431466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 18:02:04.431559 ==
4275 18:02:04.434451 [Gating] SW mode calibration
4276 18:02:04.441083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4277 18:02:04.444318 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4278 18:02:04.451079 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4279 18:02:04.454739 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4280 18:02:04.458109 0 5 8 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 0)
4281 18:02:04.464969 0 5 12 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
4282 18:02:04.467846 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 18:02:04.471193 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4284 18:02:04.477861 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4285 18:02:04.481485 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4286 18:02:04.485011 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4287 18:02:04.490892 0 6 4 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 1)
4288 18:02:04.494609 0 6 8 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
4289 18:02:04.497673 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 18:02:04.504436 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 18:02:04.507578 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 18:02:04.510890 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4293 18:02:04.517886 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 18:02:04.520981 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4295 18:02:04.524573 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4296 18:02:04.530743 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4297 18:02:04.533956 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 18:02:04.537764 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 18:02:04.543914 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 18:02:04.546947 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 18:02:04.550482 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 18:02:04.557137 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 18:02:04.560085 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 18:02:04.563811 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 18:02:04.570377 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 18:02:04.574074 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 18:02:04.577078 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 18:02:04.584048 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 18:02:04.587124 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 18:02:04.590256 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 18:02:04.596846 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 18:02:04.599844 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 18:02:04.603536 Total UI for P1: 0, mck2ui 16
4314 18:02:04.606388 best dqsien dly found for B0: ( 0, 9, 6)
4315 18:02:04.610227 Total UI for P1: 0, mck2ui 16
4316 18:02:04.613040 best dqsien dly found for B1: ( 0, 9, 6)
4317 18:02:04.616732 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4318 18:02:04.619846 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4319 18:02:04.620240
4320 18:02:04.622910 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4321 18:02:04.626520 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4322 18:02:04.629897 [Gating] SW calibration Done
4323 18:02:04.630463 ==
4324 18:02:04.633114 Dram Type= 6, Freq= 0, CH_1, rank 0
4325 18:02:04.636386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4326 18:02:04.636782 ==
4327 18:02:04.639895 RX Vref Scan: 0
4328 18:02:04.640287
4329 18:02:04.643286 RX Vref 0 -> 0, step: 1
4330 18:02:04.643723
4331 18:02:04.646190 RX Delay -230 -> 252, step: 16
4332 18:02:04.649331 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4333 18:02:04.652920 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4334 18:02:04.656317 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4335 18:02:04.662924 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4336 18:02:04.665673 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4337 18:02:04.669461 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4338 18:02:04.672289 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4339 18:02:04.675913 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4340 18:02:04.682588 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4341 18:02:04.685370 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4342 18:02:04.689133 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4343 18:02:04.692599 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4344 18:02:04.699170 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4345 18:02:04.702148 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4346 18:02:04.705800 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4347 18:02:04.708623 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4348 18:02:04.708937 ==
4349 18:02:04.712376 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 18:02:04.719404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 18:02:04.719927 ==
4352 18:02:04.720323 DQS Delay:
4353 18:02:04.722374 DQS0 = 0, DQS1 = 0
4354 18:02:04.722861 DQM Delay:
4355 18:02:04.726143 DQM0 = 39, DQM1 = 30
4356 18:02:04.726675 DQ Delay:
4357 18:02:04.728964 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4358 18:02:04.732087 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4359 18:02:04.735450 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4360 18:02:04.738619 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4361 18:02:04.739000
4362 18:02:04.739292
4363 18:02:04.739569 ==
4364 18:02:04.742085 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 18:02:04.745440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4366 18:02:04.745856 ==
4367 18:02:04.746191
4368 18:02:04.746526
4369 18:02:04.748766 TX Vref Scan disable
4370 18:02:04.752290 == TX Byte 0 ==
4371 18:02:04.755632 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4372 18:02:04.758669 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4373 18:02:04.761713 == TX Byte 1 ==
4374 18:02:04.765056 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4375 18:02:04.768327 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4376 18:02:04.768609 ==
4377 18:02:04.771909 Dram Type= 6, Freq= 0, CH_1, rank 0
4378 18:02:04.774989 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4379 18:02:04.778537 ==
4380 18:02:04.778938
4381 18:02:04.779286
4382 18:02:04.779626 TX Vref Scan disable
4383 18:02:04.782171 == TX Byte 0 ==
4384 18:02:04.785778 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4385 18:02:04.792458 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4386 18:02:04.792787 == TX Byte 1 ==
4387 18:02:04.795757 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4388 18:02:04.802597 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4389 18:02:04.802873
4390 18:02:04.803083 [DATLAT]
4391 18:02:04.803278 Freq=600, CH1 RK0
4392 18:02:04.803467
4393 18:02:04.805501 DATLAT Default: 0x9
4394 18:02:04.805773 0, 0xFFFF, sum = 0
4395 18:02:04.808978 1, 0xFFFF, sum = 0
4396 18:02:04.809264 2, 0xFFFF, sum = 0
4397 18:02:04.812020 3, 0xFFFF, sum = 0
4398 18:02:04.815638 4, 0xFFFF, sum = 0
4399 18:02:04.815807 5, 0xFFFF, sum = 0
4400 18:02:04.818450 6, 0xFFFF, sum = 0
4401 18:02:04.818589 7, 0x0, sum = 1
4402 18:02:04.818702 8, 0x0, sum = 2
4403 18:02:04.822102 9, 0x0, sum = 3
4404 18:02:04.822234 10, 0x0, sum = 4
4405 18:02:04.824966 best_step = 8
4406 18:02:04.825117
4407 18:02:04.825250 ==
4408 18:02:04.828631 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 18:02:04.831601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4410 18:02:04.831696 ==
4411 18:02:04.834843 RX Vref Scan: 1
4412 18:02:04.834936
4413 18:02:04.835037 RX Vref 0 -> 0, step: 1
4414 18:02:04.835110
4415 18:02:04.838286 RX Delay -195 -> 252, step: 8
4416 18:02:04.838385
4417 18:02:04.842277 Set Vref, RX VrefLevel [Byte0]: 56
4418 18:02:04.845252 [Byte1]: 48
4419 18:02:04.849235
4420 18:02:04.849453 Final RX Vref Byte 0 = 56 to rank0
4421 18:02:04.852761 Final RX Vref Byte 1 = 48 to rank0
4422 18:02:04.855820 Final RX Vref Byte 0 = 56 to rank1
4423 18:02:04.859526 Final RX Vref Byte 1 = 48 to rank1==
4424 18:02:04.862586 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 18:02:04.869169 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4426 18:02:04.869676 ==
4427 18:02:04.870123 DQS Delay:
4428 18:02:04.870491 DQS0 = 0, DQS1 = 0
4429 18:02:04.872369 DQM Delay:
4430 18:02:04.872748 DQM0 = 38, DQM1 = 30
4431 18:02:04.875987 DQ Delay:
4432 18:02:04.879073 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4433 18:02:04.882914 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4434 18:02:04.886022 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4435 18:02:04.889242 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4436 18:02:04.889645
4437 18:02:04.889941
4438 18:02:04.895545 [DQSOSCAuto] RK0, (LSB)MR18= 0x7676, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4439 18:02:04.899182 CH1 RK0: MR19=808, MR18=7676
4440 18:02:04.906306 CH1_RK0: MR19=0x808, MR18=0x7676, DQSOSC=387, MR23=63, INC=175, DEC=116
4441 18:02:04.906746
4442 18:02:04.909080 ----->DramcWriteLeveling(PI) begin...
4443 18:02:04.909471 ==
4444 18:02:04.912909 Dram Type= 6, Freq= 0, CH_1, rank 1
4445 18:02:04.915638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4446 18:02:04.916038 ==
4447 18:02:04.919535 Write leveling (Byte 0): 27 => 27
4448 18:02:04.922172 Write leveling (Byte 1): 28 => 28
4449 18:02:04.926041 DramcWriteLeveling(PI) end<-----
4450 18:02:04.926534
4451 18:02:04.926837 ==
4452 18:02:04.928795 Dram Type= 6, Freq= 0, CH_1, rank 1
4453 18:02:04.932545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4454 18:02:04.933100 ==
4455 18:02:04.935722 [Gating] SW mode calibration
4456 18:02:04.942204 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 18:02:04.948767 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4458 18:02:04.951833 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 18:02:04.958659 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4460 18:02:04.961864 0 5 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
4461 18:02:04.965667 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 18:02:04.971985 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 18:02:04.975257 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 18:02:04.978983 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 18:02:04.985093 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 18:02:04.988879 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 18:02:04.992071 0 6 4 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
4468 18:02:04.998607 0 6 8 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
4469 18:02:05.001925 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 18:02:05.005243 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 18:02:05.012283 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 18:02:05.014978 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 18:02:05.018784 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 18:02:05.025717 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 18:02:05.028404 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 18:02:05.031748 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 18:02:05.034824 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 18:02:05.041535 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 18:02:05.044965 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 18:02:05.048059 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 18:02:05.054715 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 18:02:05.058156 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 18:02:05.061263 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 18:02:05.068340 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 18:02:05.071296 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 18:02:05.074565 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 18:02:05.081216 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 18:02:05.085047 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 18:02:05.088541 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 18:02:05.094769 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 18:02:05.098004 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4492 18:02:05.101293 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4493 18:02:05.107657 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 18:02:05.110895 Total UI for P1: 0, mck2ui 16
4495 18:02:05.114319 best dqsien dly found for B0: ( 0, 9, 6)
4496 18:02:05.114732 Total UI for P1: 0, mck2ui 16
4497 18:02:05.121007 best dqsien dly found for B1: ( 0, 9, 8)
4498 18:02:05.124334 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4499 18:02:05.127423 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4500 18:02:05.127818
4501 18:02:05.130712 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4502 18:02:05.133877 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4503 18:02:05.137415 [Gating] SW calibration Done
4504 18:02:05.137806 ==
4505 18:02:05.140429 Dram Type= 6, Freq= 0, CH_1, rank 1
4506 18:02:05.144059 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4507 18:02:05.144457 ==
4508 18:02:05.147876 RX Vref Scan: 0
4509 18:02:05.148340
4510 18:02:05.148647 RX Vref 0 -> 0, step: 1
4511 18:02:05.148930
4512 18:02:05.150542 RX Delay -230 -> 252, step: 16
4513 18:02:05.157150 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4514 18:02:05.160826 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4515 18:02:05.163713 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 18:02:05.167321 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4517 18:02:05.170519 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 18:02:05.177062 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4519 18:02:05.180497 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4520 18:02:05.183630 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4521 18:02:05.186718 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4522 18:02:05.193351 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4523 18:02:05.196808 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 18:02:05.200489 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4525 18:02:05.203456 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 18:02:05.210041 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 18:02:05.213595 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4528 18:02:05.216543 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4529 18:02:05.216933 ==
4530 18:02:05.219845 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 18:02:05.223503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 18:02:05.226884 ==
4533 18:02:05.227272 DQS Delay:
4534 18:02:05.227577 DQS0 = 0, DQS1 = 0
4535 18:02:05.230311 DQM Delay:
4536 18:02:05.230705 DQM0 = 39, DQM1 = 33
4537 18:02:05.233314 DQ Delay:
4538 18:02:05.233716 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4539 18:02:05.236718 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4540 18:02:05.239999 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4541 18:02:05.243547 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4542 18:02:05.244031
4543 18:02:05.246326
4544 18:02:05.246716 ==
4545 18:02:05.249744 Dram Type= 6, Freq= 0, CH_1, rank 1
4546 18:02:05.253755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4547 18:02:05.254274 ==
4548 18:02:05.254613
4549 18:02:05.254897
4550 18:02:05.256433 TX Vref Scan disable
4551 18:02:05.256822 == TX Byte 0 ==
4552 18:02:05.263055 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4553 18:02:05.266696 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4554 18:02:05.267092 == TX Byte 1 ==
4555 18:02:05.273278 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4556 18:02:05.276275 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4557 18:02:05.276668 ==
4558 18:02:05.279934 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 18:02:05.283023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 18:02:05.283417 ==
4561 18:02:05.283718
4562 18:02:05.283995
4563 18:02:05.286487 TX Vref Scan disable
4564 18:02:05.289368 == TX Byte 0 ==
4565 18:02:05.292958 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4566 18:02:05.296259 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4567 18:02:05.299862 == TX Byte 1 ==
4568 18:02:05.303209 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4569 18:02:05.306285 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4570 18:02:05.306681
4571 18:02:05.309331 [DATLAT]
4572 18:02:05.309838 Freq=600, CH1 RK1
4573 18:02:05.310350
4574 18:02:05.312734 DATLAT Default: 0x8
4575 18:02:05.313129 0, 0xFFFF, sum = 0
4576 18:02:05.316004 1, 0xFFFF, sum = 0
4577 18:02:05.316476 2, 0xFFFF, sum = 0
4578 18:02:05.319479 3, 0xFFFF, sum = 0
4579 18:02:05.319884 4, 0xFFFF, sum = 0
4580 18:02:05.322589 5, 0xFFFF, sum = 0
4581 18:02:05.322997 6, 0xFFFF, sum = 0
4582 18:02:05.326202 7, 0x0, sum = 1
4583 18:02:05.326647 8, 0x0, sum = 2
4584 18:02:05.329490 9, 0x0, sum = 3
4585 18:02:05.329893 10, 0x0, sum = 4
4586 18:02:05.332599 best_step = 8
4587 18:02:05.332999
4588 18:02:05.333393 ==
4589 18:02:05.336143 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 18:02:05.339746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4591 18:02:05.340163 ==
4592 18:02:05.342727 RX Vref Scan: 0
4593 18:02:05.343121
4594 18:02:05.343511 RX Vref 0 -> 0, step: 1
4595 18:02:05.343881
4596 18:02:05.345735 RX Delay -195 -> 252, step: 8
4597 18:02:05.353193 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4598 18:02:05.356226 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4599 18:02:05.359253 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4600 18:02:05.362837 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4601 18:02:05.369124 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4602 18:02:05.372745 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4603 18:02:05.376348 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4604 18:02:05.379428 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4605 18:02:05.386280 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4606 18:02:05.389595 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4607 18:02:05.392774 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4608 18:02:05.395926 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4609 18:02:05.399129 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4610 18:02:05.405614 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4611 18:02:05.409196 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4612 18:02:05.412509 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4613 18:02:05.412973 ==
4614 18:02:05.415381 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 18:02:05.422549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4616 18:02:05.423030 ==
4617 18:02:05.423367 DQS Delay:
4618 18:02:05.425363 DQS0 = 0, DQS1 = 0
4619 18:02:05.425786 DQM Delay:
4620 18:02:05.426117 DQM0 = 37, DQM1 = 29
4621 18:02:05.428913 DQ Delay:
4622 18:02:05.432246 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4623 18:02:05.435622 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4624 18:02:05.438775 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4625 18:02:05.442339 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4626 18:02:05.442766
4627 18:02:05.443091
4628 18:02:05.448322 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4629 18:02:05.452468 CH1 RK1: MR19=808, MR18=5A5A
4630 18:02:05.458386 CH1_RK1: MR19=0x808, MR18=0x5A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4631 18:02:05.462319 [RxdqsGatingPostProcess] freq 600
4632 18:02:05.465323 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4633 18:02:05.468659 Pre-setting of DQS Precalculation
4634 18:02:05.475066 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4635 18:02:05.481671 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4636 18:02:05.488395 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4637 18:02:05.488788
4638 18:02:05.489088
4639 18:02:05.491973 [Calibration Summary] 1200 Mbps
4640 18:02:05.492360 CH 0, Rank 0
4641 18:02:05.494843 SW Impedance : PASS
4642 18:02:05.497810 DUTY Scan : NO K
4643 18:02:05.498200 ZQ Calibration : PASS
4644 18:02:05.501553 Jitter Meter : NO K
4645 18:02:05.504577 CBT Training : PASS
4646 18:02:05.504964 Write leveling : PASS
4647 18:02:05.508315 RX DQS gating : PASS
4648 18:02:05.511697 RX DQ/DQS(RDDQC) : PASS
4649 18:02:05.512087 TX DQ/DQS : PASS
4650 18:02:05.514911 RX DATLAT : PASS
4651 18:02:05.518266 RX DQ/DQS(Engine): PASS
4652 18:02:05.518744 TX OE : NO K
4653 18:02:05.521237 All Pass.
4654 18:02:05.521625
4655 18:02:05.521927 CH 0, Rank 1
4656 18:02:05.524619 SW Impedance : PASS
4657 18:02:05.525010 DUTY Scan : NO K
4658 18:02:05.527955 ZQ Calibration : PASS
4659 18:02:05.531603 Jitter Meter : NO K
4660 18:02:05.531993 CBT Training : PASS
4661 18:02:05.534707 Write leveling : PASS
4662 18:02:05.537600 RX DQS gating : PASS
4663 18:02:05.538046 RX DQ/DQS(RDDQC) : PASS
4664 18:02:05.540937 TX DQ/DQS : PASS
4665 18:02:05.541328 RX DATLAT : PASS
4666 18:02:05.544753 RX DQ/DQS(Engine): PASS
4667 18:02:05.548281 TX OE : NO K
4668 18:02:05.548754 All Pass.
4669 18:02:05.549057
4670 18:02:05.549334 CH 1, Rank 0
4671 18:02:05.551329 SW Impedance : PASS
4672 18:02:05.554351 DUTY Scan : NO K
4673 18:02:05.554743 ZQ Calibration : PASS
4674 18:02:05.558087 Jitter Meter : NO K
4675 18:02:05.561419 CBT Training : PASS
4676 18:02:05.561811 Write leveling : PASS
4677 18:02:05.564919 RX DQS gating : PASS
4678 18:02:05.567810 RX DQ/DQS(RDDQC) : PASS
4679 18:02:05.568251 TX DQ/DQS : PASS
4680 18:02:05.571258 RX DATLAT : PASS
4681 18:02:05.574549 RX DQ/DQS(Engine): PASS
4682 18:02:05.574940 TX OE : NO K
4683 18:02:05.577823 All Pass.
4684 18:02:05.578374
4685 18:02:05.578692 CH 1, Rank 1
4686 18:02:05.581159 SW Impedance : PASS
4687 18:02:05.581546 DUTY Scan : NO K
4688 18:02:05.584246 ZQ Calibration : PASS
4689 18:02:05.587691 Jitter Meter : NO K
4690 18:02:05.588083 CBT Training : PASS
4691 18:02:05.590540 Write leveling : PASS
4692 18:02:05.594181 RX DQS gating : PASS
4693 18:02:05.594597 RX DQ/DQS(RDDQC) : PASS
4694 18:02:05.597151 TX DQ/DQS : PASS
4695 18:02:05.600817 RX DATLAT : PASS
4696 18:02:05.601207 RX DQ/DQS(Engine): PASS
4697 18:02:05.603872 TX OE : NO K
4698 18:02:05.604263 All Pass.
4699 18:02:05.604565
4700 18:02:05.607615 DramC Write-DBI off
4701 18:02:05.610509 PER_BANK_REFRESH: Hybrid Mode
4702 18:02:05.610971 TX_TRACKING: ON
4703 18:02:05.620726 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4704 18:02:05.623934 [FAST_K] Save calibration result to emmc
4705 18:02:05.627500 dramc_set_vcore_voltage set vcore to 662500
4706 18:02:05.630707 Read voltage for 933, 3
4707 18:02:05.631295 Vio18 = 0
4708 18:02:05.631652 Vcore = 662500
4709 18:02:05.633684 Vdram = 0
4710 18:02:05.634074 Vddq = 0
4711 18:02:05.634500 Vmddr = 0
4712 18:02:05.640429 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4713 18:02:05.644206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4714 18:02:05.647063 MEM_TYPE=3, freq_sel=17
4715 18:02:05.649996 sv_algorithm_assistance_LP4_1600
4716 18:02:05.653566 ============ PULL DRAM RESETB DOWN ============
4717 18:02:05.656902 ========== PULL DRAM RESETB DOWN end =========
4718 18:02:05.663159 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4719 18:02:05.666713 ===================================
4720 18:02:05.670251 LPDDR4 DRAM CONFIGURATION
4721 18:02:05.670717 ===================================
4722 18:02:05.673563 EX_ROW_EN[0] = 0x0
4723 18:02:05.676815 EX_ROW_EN[1] = 0x0
4724 18:02:05.677201 LP4Y_EN = 0x0
4725 18:02:05.680185 WORK_FSP = 0x0
4726 18:02:05.680778 WL = 0x3
4727 18:02:05.683525 RL = 0x3
4728 18:02:05.684150 BL = 0x2
4729 18:02:05.686423 RPST = 0x0
4730 18:02:05.686807 RD_PRE = 0x0
4731 18:02:05.689890 WR_PRE = 0x1
4732 18:02:05.690502 WR_PST = 0x0
4733 18:02:05.693274 DBI_WR = 0x0
4734 18:02:05.693689 DBI_RD = 0x0
4735 18:02:05.696579 OTF = 0x1
4736 18:02:05.700124 ===================================
4737 18:02:05.703176 ===================================
4738 18:02:05.703565 ANA top config
4739 18:02:05.706073 ===================================
4740 18:02:05.709800 DLL_ASYNC_EN = 0
4741 18:02:05.712753 ALL_SLAVE_EN = 1
4742 18:02:05.716418 NEW_RANK_MODE = 1
4743 18:02:05.716810 DLL_IDLE_MODE = 1
4744 18:02:05.719426 LP45_APHY_COMB_EN = 1
4745 18:02:05.722813 TX_ODT_DIS = 1
4746 18:02:05.725915 NEW_8X_MODE = 1
4747 18:02:05.729684 ===================================
4748 18:02:05.732956 ===================================
4749 18:02:05.735809 data_rate = 1866
4750 18:02:05.739304 CKR = 1
4751 18:02:05.739693 DQ_P2S_RATIO = 8
4752 18:02:05.742665 ===================================
4753 18:02:05.745635 CA_P2S_RATIO = 8
4754 18:02:05.748929 DQ_CA_OPEN = 0
4755 18:02:05.752826 DQ_SEMI_OPEN = 0
4756 18:02:05.755690 CA_SEMI_OPEN = 0
4757 18:02:05.759280 CA_FULL_RATE = 0
4758 18:02:05.759696 DQ_CKDIV4_EN = 1
4759 18:02:05.762758 CA_CKDIV4_EN = 1
4760 18:02:05.765663 CA_PREDIV_EN = 0
4761 18:02:05.769187 PH8_DLY = 0
4762 18:02:05.772129 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4763 18:02:05.775887 DQ_AAMCK_DIV = 4
4764 18:02:05.776279 CA_AAMCK_DIV = 4
4765 18:02:05.778950 CA_ADMCK_DIV = 4
4766 18:02:05.782256 DQ_TRACK_CA_EN = 0
4767 18:02:05.785498 CA_PICK = 933
4768 18:02:05.789041 CA_MCKIO = 933
4769 18:02:05.792024 MCKIO_SEMI = 0
4770 18:02:05.795498 PLL_FREQ = 3732
4771 18:02:05.798750 DQ_UI_PI_RATIO = 32
4772 18:02:05.799183 CA_UI_PI_RATIO = 0
4773 18:02:05.801850 ===================================
4774 18:02:05.805167 ===================================
4775 18:02:05.808861 memory_type:LPDDR4
4776 18:02:05.811847 GP_NUM : 10
4777 18:02:05.812240 SRAM_EN : 1
4778 18:02:05.815446 MD32_EN : 0
4779 18:02:05.818283 ===================================
4780 18:02:05.821870 [ANA_INIT] >>>>>>>>>>>>>>
4781 18:02:05.825152 <<<<<< [CONFIGURE PHASE]: ANA_TX
4782 18:02:05.828396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4783 18:02:05.831995 ===================================
4784 18:02:05.832394 data_rate = 1866,PCW = 0X8f00
4785 18:02:05.834927 ===================================
4786 18:02:05.838361 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4787 18:02:05.845158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4788 18:02:05.851724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4789 18:02:05.854894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4790 18:02:05.858354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4791 18:02:05.861388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4792 18:02:05.865205 [ANA_INIT] flow start
4793 18:02:05.865779 [ANA_INIT] PLL >>>>>>>>
4794 18:02:05.868284 [ANA_INIT] PLL <<<<<<<<
4795 18:02:05.871633 [ANA_INIT] MIDPI >>>>>>>>
4796 18:02:05.875094 [ANA_INIT] MIDPI <<<<<<<<
4797 18:02:05.875486 [ANA_INIT] DLL >>>>>>>>
4798 18:02:05.878056 [ANA_INIT] flow end
4799 18:02:05.881521 ============ LP4 DIFF to SE enter ============
4800 18:02:05.884653 ============ LP4 DIFF to SE exit ============
4801 18:02:05.887672 [ANA_INIT] <<<<<<<<<<<<<
4802 18:02:05.891218 [Flow] Enable top DCM control >>>>>
4803 18:02:05.894608 [Flow] Enable top DCM control <<<<<
4804 18:02:05.897627 Enable DLL master slave shuffle
4805 18:02:05.904413 ==============================================================
4806 18:02:05.904811 Gating Mode config
4807 18:02:05.911009 ==============================================================
4808 18:02:05.911439 Config description:
4809 18:02:05.921552 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4810 18:02:05.927847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4811 18:02:05.933995 SELPH_MODE 0: By rank 1: By Phase
4812 18:02:05.937425 ==============================================================
4813 18:02:05.941180 GAT_TRACK_EN = 1
4814 18:02:05.944166 RX_GATING_MODE = 2
4815 18:02:05.947687 RX_GATING_TRACK_MODE = 2
4816 18:02:05.950561 SELPH_MODE = 1
4817 18:02:05.954421 PICG_EARLY_EN = 1
4818 18:02:05.957463 VALID_LAT_VALUE = 1
4819 18:02:05.963677 ==============================================================
4820 18:02:05.967423 Enter into Gating configuration >>>>
4821 18:02:05.970388 Exit from Gating configuration <<<<
4822 18:02:05.973776 Enter into DVFS_PRE_config >>>>>
4823 18:02:05.983888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4824 18:02:05.986655 Exit from DVFS_PRE_config <<<<<
4825 18:02:05.990399 Enter into PICG configuration >>>>
4826 18:02:05.993432 Exit from PICG configuration <<<<
4827 18:02:05.996928 [RX_INPUT] configuration >>>>>
4828 18:02:05.997359 [RX_INPUT] configuration <<<<<
4829 18:02:06.003473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4830 18:02:06.010453 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4831 18:02:06.013432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4832 18:02:06.020004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4833 18:02:06.026635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4834 18:02:06.033171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4835 18:02:06.036850 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4836 18:02:06.039942 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4837 18:02:06.046840 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4838 18:02:06.049767 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4839 18:02:06.053536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4840 18:02:06.059985 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4841 18:02:06.063084 ===================================
4842 18:02:06.063520 LPDDR4 DRAM CONFIGURATION
4843 18:02:06.066689 ===================================
4844 18:02:06.069601 EX_ROW_EN[0] = 0x0
4845 18:02:06.072944 EX_ROW_EN[1] = 0x0
4846 18:02:06.073359 LP4Y_EN = 0x0
4847 18:02:06.076473 WORK_FSP = 0x0
4848 18:02:06.076871 WL = 0x3
4849 18:02:06.079832 RL = 0x3
4850 18:02:06.080220 BL = 0x2
4851 18:02:06.082854 RPST = 0x0
4852 18:02:06.083238 RD_PRE = 0x0
4853 18:02:06.085902 WR_PRE = 0x1
4854 18:02:06.086474 WR_PST = 0x0
4855 18:02:06.089503 DBI_WR = 0x0
4856 18:02:06.089942 DBI_RD = 0x0
4857 18:02:06.092688 OTF = 0x1
4858 18:02:06.095766 ===================================
4859 18:02:06.099366 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4860 18:02:06.103092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4861 18:02:06.109193 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 18:02:06.112427 ===================================
4863 18:02:06.112707 LPDDR4 DRAM CONFIGURATION
4864 18:02:06.115727 ===================================
4865 18:02:06.118681 EX_ROW_EN[0] = 0x10
4866 18:02:06.122526 EX_ROW_EN[1] = 0x0
4867 18:02:06.122694 LP4Y_EN = 0x0
4868 18:02:06.125546 WORK_FSP = 0x0
4869 18:02:06.125712 WL = 0x3
4870 18:02:06.128809 RL = 0x3
4871 18:02:06.128976 BL = 0x2
4872 18:02:06.132042 RPST = 0x0
4873 18:02:06.132209 RD_PRE = 0x0
4874 18:02:06.135208 WR_PRE = 0x1
4875 18:02:06.135373 WR_PST = 0x0
4876 18:02:06.138814 DBI_WR = 0x0
4877 18:02:06.139201 DBI_RD = 0x0
4878 18:02:06.142197 OTF = 0x1
4879 18:02:06.145174 ===================================
4880 18:02:06.152249 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4881 18:02:06.155765 nWR fixed to 30
4882 18:02:06.156216 [ModeRegInit_LP4] CH0 RK0
4883 18:02:06.158808 [ModeRegInit_LP4] CH0 RK1
4884 18:02:06.162120 [ModeRegInit_LP4] CH1 RK0
4885 18:02:06.165348 [ModeRegInit_LP4] CH1 RK1
4886 18:02:06.165736 match AC timing 8
4887 18:02:06.172130 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4888 18:02:06.175561 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4889 18:02:06.178674 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4890 18:02:06.185340 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4891 18:02:06.188917 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4892 18:02:06.189415 ==
4893 18:02:06.191720 Dram Type= 6, Freq= 0, CH_0, rank 0
4894 18:02:06.195348 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4895 18:02:06.195740 ==
4896 18:02:06.201780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4897 18:02:06.208296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4898 18:02:06.211612 [CA 0] Center 38 (8~69) winsize 62
4899 18:02:06.215020 [CA 1] Center 38 (8~69) winsize 62
4900 18:02:06.217990 [CA 2] Center 36 (6~67) winsize 62
4901 18:02:06.221932 [CA 3] Center 36 (6~67) winsize 62
4902 18:02:06.224861 [CA 4] Center 35 (5~65) winsize 61
4903 18:02:06.228638 [CA 5] Center 34 (4~65) winsize 62
4904 18:02:06.229033
4905 18:02:06.231277 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4906 18:02:06.231790
4907 18:02:06.234724 [CATrainingPosCal] consider 1 rank data
4908 18:02:06.238609 u2DelayCellTimex100 = 270/100 ps
4909 18:02:06.241510 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4910 18:02:06.244719 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4911 18:02:06.248405 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4912 18:02:06.251483 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4913 18:02:06.255091 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4914 18:02:06.257752 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4915 18:02:06.261149
4916 18:02:06.264468 CA PerBit enable=1, Macro0, CA PI delay=34
4917 18:02:06.265049
4918 18:02:06.268230 [CBTSetCACLKResult] CA Dly = 34
4919 18:02:06.268736 CS Dly: 7 (0~38)
4920 18:02:06.269040 ==
4921 18:02:06.270975 Dram Type= 6, Freq= 0, CH_0, rank 1
4922 18:02:06.274587 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4923 18:02:06.277384 ==
4924 18:02:06.280975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4925 18:02:06.287777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4926 18:02:06.290767 [CA 0] Center 38 (8~69) winsize 62
4927 18:02:06.294170 [CA 1] Center 38 (7~69) winsize 63
4928 18:02:06.297771 [CA 2] Center 36 (5~67) winsize 63
4929 18:02:06.301124 [CA 3] Center 35 (5~66) winsize 62
4930 18:02:06.304370 [CA 4] Center 34 (4~65) winsize 62
4931 18:02:06.307557 [CA 5] Center 34 (4~65) winsize 62
4932 18:02:06.307946
4933 18:02:06.310578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4934 18:02:06.310970
4935 18:02:06.313657 [CATrainingPosCal] consider 2 rank data
4936 18:02:06.317154 u2DelayCellTimex100 = 270/100 ps
4937 18:02:06.320220 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4938 18:02:06.323829 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4939 18:02:06.327135 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4940 18:02:06.333993 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4941 18:02:06.337031 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4942 18:02:06.340785 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4943 18:02:06.341175
4944 18:02:06.343399 CA PerBit enable=1, Macro0, CA PI delay=34
4945 18:02:06.343790
4946 18:02:06.346890 [CBTSetCACLKResult] CA Dly = 34
4947 18:02:06.347349 CS Dly: 7 (0~39)
4948 18:02:06.347662
4949 18:02:06.350205 ----->DramcWriteLeveling(PI) begin...
4950 18:02:06.353869 ==
4951 18:02:06.354370 Dram Type= 6, Freq= 0, CH_0, rank 0
4952 18:02:06.359924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 18:02:06.360331 ==
4954 18:02:06.363800 Write leveling (Byte 0): 29 => 29
4955 18:02:06.366626 Write leveling (Byte 1): 27 => 27
4956 18:02:06.370319 DramcWriteLeveling(PI) end<-----
4957 18:02:06.370755
4958 18:02:06.371058 ==
4959 18:02:06.373373 Dram Type= 6, Freq= 0, CH_0, rank 0
4960 18:02:06.376762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4961 18:02:06.377278 ==
4962 18:02:06.380515 [Gating] SW mode calibration
4963 18:02:06.386310 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4964 18:02:06.393588 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4965 18:02:06.396475 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4966 18:02:06.400150 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4967 18:02:06.406852 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4968 18:02:06.409770 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4969 18:02:06.413331 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4970 18:02:06.419559 0 10 20 | B1->B0 | 3434 3030 | 0 0 | (0 0) (1 0)
4971 18:02:06.422903 0 10 24 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)
4972 18:02:06.426090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4973 18:02:06.432555 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4974 18:02:06.436189 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4975 18:02:06.439476 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4976 18:02:06.445921 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4977 18:02:06.449607 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4978 18:02:06.452736 0 11 20 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4979 18:02:06.459422 0 11 24 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
4980 18:02:06.462513 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4981 18:02:06.465811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4982 18:02:06.472596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 18:02:06.476148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4984 18:02:06.479738 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4985 18:02:06.482374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4986 18:02:06.489343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4987 18:02:06.492164 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4988 18:02:06.495521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4989 18:02:06.502652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4990 18:02:06.506029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4991 18:02:06.508893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4992 18:02:06.516163 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4993 18:02:06.518746 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4994 18:02:06.522122 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4995 18:02:06.529121 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4996 18:02:06.531893 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 18:02:06.535762 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 18:02:06.541945 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 18:02:06.545230 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 18:02:06.548460 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 18:02:06.555339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 18:02:06.558301 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5003 18:02:06.561516 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 18:02:06.564771 Total UI for P1: 0, mck2ui 16
5005 18:02:06.568384 best dqsien dly found for B0: ( 0, 14, 20)
5006 18:02:06.571584 Total UI for P1: 0, mck2ui 16
5007 18:02:06.574719 best dqsien dly found for B1: ( 0, 14, 20)
5008 18:02:06.578365 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5009 18:02:06.584495 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5010 18:02:06.584926
5011 18:02:06.588349 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5012 18:02:06.591649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5013 18:02:06.594669 [Gating] SW calibration Done
5014 18:02:06.595054 ==
5015 18:02:06.598027 Dram Type= 6, Freq= 0, CH_0, rank 0
5016 18:02:06.601739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5017 18:02:06.602127 ==
5018 18:02:06.604633 RX Vref Scan: 0
5019 18:02:06.605017
5020 18:02:06.605316 RX Vref 0 -> 0, step: 1
5021 18:02:06.605601
5022 18:02:06.607691 RX Delay -80 -> 252, step: 8
5023 18:02:06.611328 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5024 18:02:06.614172 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5025 18:02:06.621369 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5026 18:02:06.624434 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5027 18:02:06.627861 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5028 18:02:06.631345 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5029 18:02:06.634364 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5030 18:02:06.638295 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5031 18:02:06.644407 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5032 18:02:06.648124 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5033 18:02:06.651074 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5034 18:02:06.654029 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5035 18:02:06.657496 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5036 18:02:06.663963 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5037 18:02:06.667284 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5038 18:02:06.671013 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5039 18:02:06.671402 ==
5040 18:02:06.673998 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 18:02:06.677056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5042 18:02:06.677507 ==
5043 18:02:06.680849 DQS Delay:
5044 18:02:06.681237 DQS0 = 0, DQS1 = 0
5045 18:02:06.684084 DQM Delay:
5046 18:02:06.684438 DQM0 = 97, DQM1 = 85
5047 18:02:06.684727 DQ Delay:
5048 18:02:06.687024 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5049 18:02:06.690273 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5050 18:02:06.693742 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5051 18:02:06.697038 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5052 18:02:06.697430
5053 18:02:06.697730
5054 18:02:06.700747 ==
5055 18:02:06.701137 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 18:02:06.707186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 18:02:06.707582 ==
5058 18:02:06.707885
5059 18:02:06.708160
5060 18:02:06.710118 TX Vref Scan disable
5061 18:02:06.710535 == TX Byte 0 ==
5062 18:02:06.713819 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5063 18:02:06.720348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5064 18:02:06.720779 == TX Byte 1 ==
5065 18:02:06.723396 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5066 18:02:06.729938 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5067 18:02:06.730395 ==
5068 18:02:06.733424 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 18:02:06.736927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 18:02:06.737324 ==
5071 18:02:06.737625
5072 18:02:06.737904
5073 18:02:06.739993 TX Vref Scan disable
5074 18:02:06.743608 == TX Byte 0 ==
5075 18:02:06.746694 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5076 18:02:06.750030 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5077 18:02:06.753424 == TX Byte 1 ==
5078 18:02:06.756952 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5079 18:02:06.759908 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5080 18:02:06.760302
5081 18:02:06.763387 [DATLAT]
5082 18:02:06.763777 Freq=933, CH0 RK0
5083 18:02:06.764081
5084 18:02:06.766408 DATLAT Default: 0xd
5085 18:02:06.766799 0, 0xFFFF, sum = 0
5086 18:02:06.769826 1, 0xFFFF, sum = 0
5087 18:02:06.770257 2, 0xFFFF, sum = 0
5088 18:02:06.773161 3, 0xFFFF, sum = 0
5089 18:02:06.773555 4, 0xFFFF, sum = 0
5090 18:02:06.776678 5, 0xFFFF, sum = 0
5091 18:02:06.777193 6, 0xFFFF, sum = 0
5092 18:02:06.779614 7, 0xFFFF, sum = 0
5093 18:02:06.780004 8, 0xFFFF, sum = 0
5094 18:02:06.782792 9, 0xFFFF, sum = 0
5095 18:02:06.783200 10, 0x0, sum = 1
5096 18:02:06.786709 11, 0x0, sum = 2
5097 18:02:06.787102 12, 0x0, sum = 3
5098 18:02:06.789485 13, 0x0, sum = 4
5099 18:02:06.789894 best_step = 11
5100 18:02:06.790201
5101 18:02:06.790528 ==
5102 18:02:06.792871 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 18:02:06.799805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5104 18:02:06.800199 ==
5105 18:02:06.800500 RX Vref Scan: 1
5106 18:02:06.800781
5107 18:02:06.802825 RX Vref 0 -> 0, step: 1
5108 18:02:06.803214
5109 18:02:06.806479 RX Delay -69 -> 252, step: 4
5110 18:02:06.806864
5111 18:02:06.809932 Set Vref, RX VrefLevel [Byte0]: 46
5112 18:02:06.812919 [Byte1]: 48
5113 18:02:06.813304
5114 18:02:06.816080 Final RX Vref Byte 0 = 46 to rank0
5115 18:02:06.819652 Final RX Vref Byte 1 = 48 to rank0
5116 18:02:06.823059 Final RX Vref Byte 0 = 46 to rank1
5117 18:02:06.826033 Final RX Vref Byte 1 = 48 to rank1==
5118 18:02:06.829482 Dram Type= 6, Freq= 0, CH_0, rank 0
5119 18:02:06.832741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5120 18:02:06.833229 ==
5121 18:02:06.836210 DQS Delay:
5122 18:02:06.836739 DQS0 = 0, DQS1 = 0
5123 18:02:06.837058 DQM Delay:
5124 18:02:06.839655 DQM0 = 97, DQM1 = 87
5125 18:02:06.840041 DQ Delay:
5126 18:02:06.842751 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =96
5127 18:02:06.845779 DQ4 =98, DQ5 =90, DQ6 =104, DQ7 =104
5128 18:02:06.849399 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5129 18:02:06.852777 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =98
5130 18:02:06.853289
5131 18:02:06.853597
5132 18:02:06.862669 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5133 18:02:06.865538 CH0 RK0: MR19=505, MR18=1D1D
5134 18:02:06.872762 CH0_RK0: MR19=0x505, MR18=0x1D1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5135 18:02:06.873251
5136 18:02:06.875431 ----->DramcWriteLeveling(PI) begin...
5137 18:02:06.875823 ==
5138 18:02:06.878724 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 18:02:06.882081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5140 18:02:06.882527 ==
5141 18:02:06.885548 Write leveling (Byte 0): 29 => 29
5142 18:02:06.889405 Write leveling (Byte 1): 29 => 29
5143 18:02:06.892234 DramcWriteLeveling(PI) end<-----
5144 18:02:06.892621
5145 18:02:06.892986 ==
5146 18:02:06.895770 Dram Type= 6, Freq= 0, CH_0, rank 1
5147 18:02:06.898777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5148 18:02:06.899179 ==
5149 18:02:06.902093 [Gating] SW mode calibration
5150 18:02:06.908831 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5151 18:02:06.915420 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5152 18:02:06.918489 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 18:02:06.921914 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 18:02:06.928785 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 18:02:06.931669 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 18:02:06.935380 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5157 18:02:06.941914 0 10 20 | B1->B0 | 3232 2d2d | 0 0 | (0 0) (0 0)
5158 18:02:06.945369 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5159 18:02:06.948694 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 18:02:06.955035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 18:02:06.958929 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 18:02:06.961784 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 18:02:06.968460 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 18:02:06.971730 0 11 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5165 18:02:06.975103 0 11 20 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5166 18:02:06.981642 0 11 24 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
5167 18:02:06.985017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 18:02:06.988126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 18:02:06.994793 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 18:02:06.998288 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 18:02:07.001548 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 18:02:07.008055 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 18:02:07.011651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 18:02:07.015099 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 18:02:07.021300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 18:02:07.024947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 18:02:07.028223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 18:02:07.031174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 18:02:07.038168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 18:02:07.041238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 18:02:07.045177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 18:02:07.051331 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 18:02:07.054355 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 18:02:07.057956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 18:02:07.064565 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 18:02:07.068110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 18:02:07.071019 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 18:02:07.078106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 18:02:07.081100 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5190 18:02:07.084114 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 18:02:07.087705 Total UI for P1: 0, mck2ui 16
5192 18:02:07.091169 best dqsien dly found for B0: ( 0, 14, 20)
5193 18:02:07.094384 Total UI for P1: 0, mck2ui 16
5194 18:02:07.097356 best dqsien dly found for B1: ( 0, 14, 20)
5195 18:02:07.100994 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5196 18:02:07.107154 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5197 18:02:07.107546
5198 18:02:07.110641 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5199 18:02:07.113881 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5200 18:02:07.117644 [Gating] SW calibration Done
5201 18:02:07.118033 ==
5202 18:02:07.120615 Dram Type= 6, Freq= 0, CH_0, rank 1
5203 18:02:07.124147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5204 18:02:07.124543 ==
5205 18:02:07.127503 RX Vref Scan: 0
5206 18:02:07.127895
5207 18:02:07.128196 RX Vref 0 -> 0, step: 1
5208 18:02:07.128478
5209 18:02:07.130369 RX Delay -80 -> 252, step: 8
5210 18:02:07.133867 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5211 18:02:07.137323 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 18:02:07.143771 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5213 18:02:07.147178 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5214 18:02:07.150557 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5215 18:02:07.154024 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5216 18:02:07.157637 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5217 18:02:07.160437 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 18:02:07.166989 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 18:02:07.170821 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5220 18:02:07.173778 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 18:02:07.177186 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 18:02:07.180539 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5223 18:02:07.186889 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5224 18:02:07.190913 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 18:02:07.193503 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 18:02:07.193890 ==
5227 18:02:07.196928 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 18:02:07.200241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 18:02:07.200636 ==
5230 18:02:07.203454 DQS Delay:
5231 18:02:07.203903 DQS0 = 0, DQS1 = 0
5232 18:02:07.206988 DQM Delay:
5233 18:02:07.207378 DQM0 = 96, DQM1 = 85
5234 18:02:07.207680 DQ Delay:
5235 18:02:07.210114 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5236 18:02:07.213209 DQ4 =103, DQ5 =83, DQ6 =103, DQ7 =107
5237 18:02:07.216736 DQ8 =79, DQ9 =67, DQ10 =87, DQ11 =79
5238 18:02:07.219959 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5239 18:02:07.220374
5240 18:02:07.223193
5241 18:02:07.223579 ==
5242 18:02:07.226672 Dram Type= 6, Freq= 0, CH_0, rank 1
5243 18:02:07.229575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5244 18:02:07.229969 ==
5245 18:02:07.230312
5246 18:02:07.230601
5247 18:02:07.232827 TX Vref Scan disable
5248 18:02:07.233217 == TX Byte 0 ==
5249 18:02:07.240260 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5250 18:02:07.243038 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5251 18:02:07.243427 == TX Byte 1 ==
5252 18:02:07.249829 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5253 18:02:07.253236 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5254 18:02:07.253679 ==
5255 18:02:07.256488 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 18:02:07.260158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 18:02:07.260553 ==
5258 18:02:07.260853
5259 18:02:07.261128
5260 18:02:07.263044 TX Vref Scan disable
5261 18:02:07.266461 == TX Byte 0 ==
5262 18:02:07.269908 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5263 18:02:07.273090 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5264 18:02:07.276503 == TX Byte 1 ==
5265 18:02:07.279718 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5266 18:02:07.282841 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5267 18:02:07.283236
5268 18:02:07.286252 [DATLAT]
5269 18:02:07.286642 Freq=933, CH0 RK1
5270 18:02:07.286942
5271 18:02:07.289855 DATLAT Default: 0xb
5272 18:02:07.290281 0, 0xFFFF, sum = 0
5273 18:02:07.292776 1, 0xFFFF, sum = 0
5274 18:02:07.293279 2, 0xFFFF, sum = 0
5275 18:02:07.296023 3, 0xFFFF, sum = 0
5276 18:02:07.296419 4, 0xFFFF, sum = 0
5277 18:02:07.299921 5, 0xFFFF, sum = 0
5278 18:02:07.300406 6, 0xFFFF, sum = 0
5279 18:02:07.302722 7, 0xFFFF, sum = 0
5280 18:02:07.303223 8, 0xFFFF, sum = 0
5281 18:02:07.305996 9, 0xFFFF, sum = 0
5282 18:02:07.306577 10, 0x0, sum = 1
5283 18:02:07.309793 11, 0x0, sum = 2
5284 18:02:07.310324 12, 0x0, sum = 3
5285 18:02:07.312439 13, 0x0, sum = 4
5286 18:02:07.312936 best_step = 11
5287 18:02:07.313243
5288 18:02:07.313536 ==
5289 18:02:07.315791 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 18:02:07.322331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5291 18:02:07.322757 ==
5292 18:02:07.323071 RX Vref Scan: 0
5293 18:02:07.323357
5294 18:02:07.325866 RX Vref 0 -> 0, step: 1
5295 18:02:07.326384
5296 18:02:07.329298 RX Delay -77 -> 252, step: 4
5297 18:02:07.332534 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5298 18:02:07.338797 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5299 18:02:07.342516 iDelay=199, Bit 2, Center 98 (7 ~ 190) 184
5300 18:02:07.345783 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5301 18:02:07.349404 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5302 18:02:07.352556 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5303 18:02:07.355596 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5304 18:02:07.362009 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5305 18:02:07.365423 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5306 18:02:07.369172 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5307 18:02:07.372323 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5308 18:02:07.375453 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5309 18:02:07.381722 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5310 18:02:07.385409 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5311 18:02:07.388453 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5312 18:02:07.391929 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5313 18:02:07.392322 ==
5314 18:02:07.395632 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 18:02:07.398487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 18:02:07.401774 ==
5317 18:02:07.402164 DQS Delay:
5318 18:02:07.402532 DQS0 = 0, DQS1 = 0
5319 18:02:07.405044 DQM Delay:
5320 18:02:07.405433 DQM0 = 98, DQM1 = 86
5321 18:02:07.408105 DQ Delay:
5322 18:02:07.411818 DQ0 =94, DQ1 =100, DQ2 =98, DQ3 =92
5323 18:02:07.414801 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5324 18:02:07.418328 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5325 18:02:07.421464 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5326 18:02:07.421856
5327 18:02:07.422157
5328 18:02:07.428229 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5329 18:02:07.431526 CH0 RK1: MR19=505, MR18=2828
5330 18:02:07.438112 CH0_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5331 18:02:07.441362 [RxdqsGatingPostProcess] freq 933
5332 18:02:07.444375 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5333 18:02:07.448043 Pre-setting of DQS Precalculation
5334 18:02:07.454359 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5335 18:02:07.454829 ==
5336 18:02:07.457916 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 18:02:07.460996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 18:02:07.461392 ==
5339 18:02:07.468043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5340 18:02:07.474099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5341 18:02:07.477692 [CA 0] Center 37 (6~68) winsize 63
5342 18:02:07.480813 [CA 1] Center 37 (6~68) winsize 63
5343 18:02:07.484318 [CA 2] Center 34 (4~65) winsize 62
5344 18:02:07.487504 [CA 3] Center 34 (3~65) winsize 63
5345 18:02:07.490991 [CA 4] Center 33 (2~64) winsize 63
5346 18:02:07.491382 [CA 5] Center 33 (2~64) winsize 63
5347 18:02:07.494020
5348 18:02:07.497729 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5349 18:02:07.498117
5350 18:02:07.500846 [CATrainingPosCal] consider 1 rank data
5351 18:02:07.504259 u2DelayCellTimex100 = 270/100 ps
5352 18:02:07.507703 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5353 18:02:07.511012 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5354 18:02:07.514009 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5355 18:02:07.517560 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5356 18:02:07.521200 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5357 18:02:07.524024 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5358 18:02:07.524417
5359 18:02:07.527231 CA PerBit enable=1, Macro0, CA PI delay=33
5360 18:02:07.527621
5361 18:02:07.531143 [CBTSetCACLKResult] CA Dly = 33
5362 18:02:07.533924 CS Dly: 5 (0~36)
5363 18:02:07.534351 ==
5364 18:02:07.537663 Dram Type= 6, Freq= 0, CH_1, rank 1
5365 18:02:07.540643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5366 18:02:07.541032 ==
5367 18:02:07.547034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5368 18:02:07.553842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5369 18:02:07.557396 [CA 0] Center 37 (6~68) winsize 63
5370 18:02:07.560821 [CA 1] Center 37 (6~68) winsize 63
5371 18:02:07.563969 [CA 2] Center 34 (4~65) winsize 62
5372 18:02:07.567352 [CA 3] Center 34 (4~64) winsize 61
5373 18:02:07.570469 [CA 4] Center 33 (2~64) winsize 63
5374 18:02:07.573897 [CA 5] Center 32 (2~63) winsize 62
5375 18:02:07.574559
5376 18:02:07.577104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5377 18:02:07.577488
5378 18:02:07.580652 [CATrainingPosCal] consider 2 rank data
5379 18:02:07.583673 u2DelayCellTimex100 = 270/100 ps
5380 18:02:07.587167 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5381 18:02:07.590346 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5382 18:02:07.593631 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5383 18:02:07.597125 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5384 18:02:07.600190 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5385 18:02:07.603816 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5386 18:02:07.604199
5387 18:02:07.610489 CA PerBit enable=1, Macro0, CA PI delay=32
5388 18:02:07.610889
5389 18:02:07.611188 [CBTSetCACLKResult] CA Dly = 32
5390 18:02:07.613810 CS Dly: 5 (0~37)
5391 18:02:07.614192
5392 18:02:07.616945 ----->DramcWriteLeveling(PI) begin...
5393 18:02:07.617498 ==
5394 18:02:07.620722 Dram Type= 6, Freq= 0, CH_1, rank 0
5395 18:02:07.623675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5396 18:02:07.624090 ==
5397 18:02:07.626668 Write leveling (Byte 0): 27 => 27
5398 18:02:07.630326 Write leveling (Byte 1): 27 => 27
5399 18:02:07.633258 DramcWriteLeveling(PI) end<-----
5400 18:02:07.633641
5401 18:02:07.633936 ==
5402 18:02:07.636487 Dram Type= 6, Freq= 0, CH_1, rank 0
5403 18:02:07.643236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5404 18:02:07.643703 ==
5405 18:02:07.644033 [Gating] SW mode calibration
5406 18:02:07.653800 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5407 18:02:07.656773 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5408 18:02:07.659827 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 18:02:07.666331 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 18:02:07.670029 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 18:02:07.673516 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 18:02:07.680046 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5413 18:02:07.683237 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
5414 18:02:07.686171 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5415 18:02:07.693071 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 18:02:07.696480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 18:02:07.699478 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 18:02:07.706684 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 18:02:07.709539 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 18:02:07.712791 0 11 16 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
5421 18:02:07.719379 0 11 20 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5422 18:02:07.722803 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5423 18:02:07.726081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 18:02:07.733110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 18:02:07.735820 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 18:02:07.739239 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 18:02:07.746397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 18:02:07.749408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5429 18:02:07.752291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 18:02:07.758942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5431 18:02:07.762520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 18:02:07.765364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 18:02:07.772012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 18:02:07.775758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 18:02:07.779172 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 18:02:07.785223 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 18:02:07.788942 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 18:02:07.792202 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 18:02:07.798855 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 18:02:07.802056 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 18:02:07.805490 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 18:02:07.812220 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 18:02:07.815006 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 18:02:07.818734 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 18:02:07.825753 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5446 18:02:07.828476 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5447 18:02:07.832138 Total UI for P1: 0, mck2ui 16
5448 18:02:07.835344 best dqsien dly found for B0: ( 0, 14, 18)
5449 18:02:07.838349 Total UI for P1: 0, mck2ui 16
5450 18:02:07.841778 best dqsien dly found for B1: ( 0, 14, 20)
5451 18:02:07.845303 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5452 18:02:07.848253 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5453 18:02:07.848641
5454 18:02:07.851834 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5455 18:02:07.855055 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5456 18:02:07.858343 [Gating] SW calibration Done
5457 18:02:07.858741 ==
5458 18:02:07.861565 Dram Type= 6, Freq= 0, CH_1, rank 0
5459 18:02:07.867876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5460 18:02:07.868265 ==
5461 18:02:07.868589 RX Vref Scan: 0
5462 18:02:07.868876
5463 18:02:07.871651 RX Vref 0 -> 0, step: 1
5464 18:02:07.872117
5465 18:02:07.874859 RX Delay -80 -> 252, step: 8
5466 18:02:07.878160 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5467 18:02:07.881480 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5468 18:02:07.884740 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5469 18:02:07.887930 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 18:02:07.894745 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5471 18:02:07.898029 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5472 18:02:07.901125 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5473 18:02:07.904957 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5474 18:02:07.907868 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5475 18:02:07.914187 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5476 18:02:07.917561 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5477 18:02:07.920692 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5478 18:02:07.924647 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5479 18:02:07.927428 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5480 18:02:07.933954 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5481 18:02:07.937501 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5482 18:02:07.937909 ==
5483 18:02:07.940487 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 18:02:07.944234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5485 18:02:07.944660 ==
5486 18:02:07.945180 DQS Delay:
5487 18:02:07.947340 DQS0 = 0, DQS1 = 0
5488 18:02:07.947737 DQM Delay:
5489 18:02:07.950795 DQM0 = 95, DQM1 = 86
5490 18:02:07.951194 DQ Delay:
5491 18:02:07.953985 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5492 18:02:07.957591 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5493 18:02:07.960327 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5494 18:02:07.963781 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5495 18:02:07.964165
5496 18:02:07.964461
5497 18:02:07.964748 ==
5498 18:02:07.966874 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 18:02:07.973846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5500 18:02:07.974451 ==
5501 18:02:07.974891
5502 18:02:07.975306
5503 18:02:07.975713 TX Vref Scan disable
5504 18:02:07.977114 == TX Byte 0 ==
5505 18:02:07.980039 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5506 18:02:07.987173 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5507 18:02:07.987388 == TX Byte 1 ==
5508 18:02:07.990168 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5509 18:02:07.996693 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5510 18:02:07.996900 ==
5511 18:02:07.999724 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 18:02:08.003226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 18:02:08.003395 ==
5514 18:02:08.003527
5515 18:02:08.003647
5516 18:02:08.006625 TX Vref Scan disable
5517 18:02:08.006794 == TX Byte 0 ==
5518 18:02:08.013680 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5519 18:02:08.016888 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5520 18:02:08.017056 == TX Byte 1 ==
5521 18:02:08.023256 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5522 18:02:08.026424 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5523 18:02:08.026614
5524 18:02:08.026746 [DATLAT]
5525 18:02:08.029829 Freq=933, CH1 RK0
5526 18:02:08.029997
5527 18:02:08.030133 DATLAT Default: 0xd
5528 18:02:08.033222 0, 0xFFFF, sum = 0
5529 18:02:08.033393 1, 0xFFFF, sum = 0
5530 18:02:08.036471 2, 0xFFFF, sum = 0
5531 18:02:08.036642 3, 0xFFFF, sum = 0
5532 18:02:08.040096 4, 0xFFFF, sum = 0
5533 18:02:08.043081 5, 0xFFFF, sum = 0
5534 18:02:08.043633 6, 0xFFFF, sum = 0
5535 18:02:08.046627 7, 0xFFFF, sum = 0
5536 18:02:08.047146 8, 0xFFFF, sum = 0
5537 18:02:08.050090 9, 0xFFFF, sum = 0
5538 18:02:08.050503 10, 0x0, sum = 1
5539 18:02:08.053497 11, 0x0, sum = 2
5540 18:02:08.053933 12, 0x0, sum = 3
5541 18:02:08.054290 13, 0x0, sum = 4
5542 18:02:08.056374 best_step = 11
5543 18:02:08.056829
5544 18:02:08.057242 ==
5545 18:02:08.059581 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 18:02:08.063231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 18:02:08.063628 ==
5548 18:02:08.066371 RX Vref Scan: 1
5549 18:02:08.066762
5550 18:02:08.069840 RX Vref 0 -> 0, step: 1
5551 18:02:08.070283
5552 18:02:08.070616 RX Delay -69 -> 252, step: 4
5553 18:02:08.070908
5554 18:02:08.073168 Set Vref, RX VrefLevel [Byte0]: 56
5555 18:02:08.076366 [Byte1]: 48
5556 18:02:08.080911
5557 18:02:08.081298 Final RX Vref Byte 0 = 56 to rank0
5558 18:02:08.084532 Final RX Vref Byte 1 = 48 to rank0
5559 18:02:08.087646 Final RX Vref Byte 0 = 56 to rank1
5560 18:02:08.091230 Final RX Vref Byte 1 = 48 to rank1==
5561 18:02:08.094259 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 18:02:08.100836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5563 18:02:08.101229 ==
5564 18:02:08.101527 DQS Delay:
5565 18:02:08.104494 DQS0 = 0, DQS1 = 0
5566 18:02:08.104905 DQM Delay:
5567 18:02:08.105210 DQM0 = 94, DQM1 = 88
5568 18:02:08.107439 DQ Delay:
5569 18:02:08.110986 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5570 18:02:08.114277 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5571 18:02:08.117465 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5572 18:02:08.120825 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5573 18:02:08.121245
5574 18:02:08.121584
5575 18:02:08.127201 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5576 18:02:08.130146 CH1 RK0: MR19=505, MR18=3737
5577 18:02:08.136901 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5578 18:02:08.137071
5579 18:02:08.140619 ----->DramcWriteLeveling(PI) begin...
5580 18:02:08.140871 ==
5581 18:02:08.143775 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 18:02:08.147234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5583 18:02:08.147420 ==
5584 18:02:08.150235 Write leveling (Byte 0): 23 => 23
5585 18:02:08.153389 Write leveling (Byte 1): 23 => 23
5586 18:02:08.156887 DramcWriteLeveling(PI) end<-----
5587 18:02:08.157029
5588 18:02:08.157138 ==
5589 18:02:08.159951 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 18:02:08.163720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 18:02:08.163862 ==
5592 18:02:08.166909 [Gating] SW mode calibration
5593 18:02:08.173427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 18:02:08.180000 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5595 18:02:08.183606 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 18:02:08.190257 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 18:02:08.193388 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 18:02:08.197000 0 10 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5599 18:02:08.203632 0 10 16 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
5600 18:02:08.206562 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
5601 18:02:08.210168 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 18:02:08.216585 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 18:02:08.219636 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 18:02:08.223053 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 18:02:08.230018 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 18:02:08.233009 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5607 18:02:08.236441 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
5608 18:02:08.242841 0 11 20 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
5609 18:02:08.246242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 18:02:08.249760 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 18:02:08.256390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 18:02:08.259756 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 18:02:08.262585 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 18:02:08.269345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5615 18:02:08.272314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5616 18:02:08.275752 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5617 18:02:08.282739 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 18:02:08.286148 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 18:02:08.288997 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 18:02:08.295944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 18:02:08.299068 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 18:02:08.302776 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 18:02:08.308877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 18:02:08.312548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 18:02:08.315301 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 18:02:08.322309 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 18:02:08.325929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 18:02:08.329519 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 18:02:08.332297 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 18:02:08.338977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 18:02:08.342411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5632 18:02:08.345874 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5633 18:02:08.348811 Total UI for P1: 0, mck2ui 16
5634 18:02:08.352696 best dqsien dly found for B0: ( 0, 14, 16)
5635 18:02:08.359158 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 18:02:08.362148 Total UI for P1: 0, mck2ui 16
5637 18:02:08.365873 best dqsien dly found for B1: ( 0, 14, 18)
5638 18:02:08.368986 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5639 18:02:08.372571 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5640 18:02:08.373154
5641 18:02:08.375782 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5642 18:02:08.379231 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5643 18:02:08.382075 [Gating] SW calibration Done
5644 18:02:08.382586 ==
5645 18:02:08.385372 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 18:02:08.388693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5647 18:02:08.389127 ==
5648 18:02:08.392544 RX Vref Scan: 0
5649 18:02:08.393156
5650 18:02:08.395203 RX Vref 0 -> 0, step: 1
5651 18:02:08.395635
5652 18:02:08.396022 RX Delay -80 -> 252, step: 8
5653 18:02:08.401771 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5654 18:02:08.405698 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5655 18:02:08.409103 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5656 18:02:08.411625 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5657 18:02:08.415321 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5658 18:02:08.418763 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5659 18:02:08.425189 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5660 18:02:08.428253 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5661 18:02:08.431566 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5662 18:02:08.435224 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5663 18:02:08.438148 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5664 18:02:08.444672 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5665 18:02:08.448187 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5666 18:02:08.451850 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5667 18:02:08.454540 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5668 18:02:08.458033 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5669 18:02:08.458550 ==
5670 18:02:08.461644 Dram Type= 6, Freq= 0, CH_1, rank 1
5671 18:02:08.468147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5672 18:02:08.468538 ==
5673 18:02:08.468837 DQS Delay:
5674 18:02:08.471489 DQS0 = 0, DQS1 = 0
5675 18:02:08.472027 DQM Delay:
5676 18:02:08.472337 DQM0 = 94, DQM1 = 86
5677 18:02:08.474286 DQ Delay:
5678 18:02:08.477921 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5679 18:02:08.481485 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5680 18:02:08.484784 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5681 18:02:08.487699 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5682 18:02:08.488097
5683 18:02:08.488395
5684 18:02:08.488669 ==
5685 18:02:08.491116 Dram Type= 6, Freq= 0, CH_1, rank 1
5686 18:02:08.494595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5687 18:02:08.494985 ==
5688 18:02:08.495282
5689 18:02:08.495593
5690 18:02:08.498007 TX Vref Scan disable
5691 18:02:08.500932 == TX Byte 0 ==
5692 18:02:08.504772 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5693 18:02:08.507979 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5694 18:02:08.511092 == TX Byte 1 ==
5695 18:02:08.514005 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5696 18:02:08.517826 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5697 18:02:08.518247 ==
5698 18:02:08.521236 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 18:02:08.524240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 18:02:08.527210 ==
5701 18:02:08.527596
5702 18:02:08.527891
5703 18:02:08.528202 TX Vref Scan disable
5704 18:02:08.530720 == TX Byte 0 ==
5705 18:02:08.534303 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5706 18:02:08.541070 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5707 18:02:08.541550 == TX Byte 1 ==
5708 18:02:08.544618 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5709 18:02:08.550853 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5710 18:02:08.551240
5711 18:02:08.551559 [DATLAT]
5712 18:02:08.551861 Freq=933, CH1 RK1
5713 18:02:08.552135
5714 18:02:08.554343 DATLAT Default: 0xb
5715 18:02:08.554736 0, 0xFFFF, sum = 0
5716 18:02:08.557267 1, 0xFFFF, sum = 0
5717 18:02:08.560596 2, 0xFFFF, sum = 0
5718 18:02:08.560987 3, 0xFFFF, sum = 0
5719 18:02:08.564046 4, 0xFFFF, sum = 0
5720 18:02:08.564439 5, 0xFFFF, sum = 0
5721 18:02:08.567432 6, 0xFFFF, sum = 0
5722 18:02:08.567826 7, 0xFFFF, sum = 0
5723 18:02:08.570899 8, 0xFFFF, sum = 0
5724 18:02:08.571295 9, 0xFFFF, sum = 0
5725 18:02:08.574506 10, 0x0, sum = 1
5726 18:02:08.574945 11, 0x0, sum = 2
5727 18:02:08.577260 12, 0x0, sum = 3
5728 18:02:08.577651 13, 0x0, sum = 4
5729 18:02:08.577959 best_step = 11
5730 18:02:08.578258
5731 18:02:08.580685 ==
5732 18:02:08.584083 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 18:02:08.587401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5734 18:02:08.588026 ==
5735 18:02:08.588362 RX Vref Scan: 0
5736 18:02:08.588680
5737 18:02:08.590365 RX Vref 0 -> 0, step: 1
5738 18:02:08.590768
5739 18:02:08.594280 RX Delay -69 -> 252, step: 4
5740 18:02:08.600393 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5741 18:02:08.603883 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5742 18:02:08.607210 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5743 18:02:08.610168 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5744 18:02:08.613888 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5745 18:02:08.616863 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5746 18:02:08.623612 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5747 18:02:08.627194 iDelay=203, Bit 7, Center 96 (3 ~ 190) 188
5748 18:02:08.630429 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5749 18:02:08.633655 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5750 18:02:08.636674 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5751 18:02:08.644031 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5752 18:02:08.646499 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5753 18:02:08.650165 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5754 18:02:08.653724 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5755 18:02:08.656689 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5756 18:02:08.657196 ==
5757 18:02:08.659834 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 18:02:08.666484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5759 18:02:08.667052 ==
5760 18:02:08.667585 DQS Delay:
5761 18:02:08.669983 DQS0 = 0, DQS1 = 0
5762 18:02:08.670433 DQM Delay:
5763 18:02:08.670899 DQM0 = 96, DQM1 = 87
5764 18:02:08.673517 DQ Delay:
5765 18:02:08.676813 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5766 18:02:08.679561 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =96
5767 18:02:08.683058 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5768 18:02:08.686599 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =94
5769 18:02:08.687031
5770 18:02:08.687403
5771 18:02:08.693119 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5772 18:02:08.696558 CH1 RK1: MR19=505, MR18=2626
5773 18:02:08.702823 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5774 18:02:08.706295 [RxdqsGatingPostProcess] freq 933
5775 18:02:08.709580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5776 18:02:08.712673 Pre-setting of DQS Precalculation
5777 18:02:08.719795 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5778 18:02:08.725927 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5779 18:02:08.732851 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5780 18:02:08.733319
5781 18:02:08.733618
5782 18:02:08.736063 [Calibration Summary] 1866 Mbps
5783 18:02:08.736450 CH 0, Rank 0
5784 18:02:08.738990 SW Impedance : PASS
5785 18:02:08.742573 DUTY Scan : NO K
5786 18:02:08.743007 ZQ Calibration : PASS
5787 18:02:08.745991 Jitter Meter : NO K
5788 18:02:08.749554 CBT Training : PASS
5789 18:02:08.749938 Write leveling : PASS
5790 18:02:08.753036 RX DQS gating : PASS
5791 18:02:08.756153 RX DQ/DQS(RDDQC) : PASS
5792 18:02:08.756659 TX DQ/DQS : PASS
5793 18:02:08.759459 RX DATLAT : PASS
5794 18:02:08.762921 RX DQ/DQS(Engine): PASS
5795 18:02:08.763308 TX OE : NO K
5796 18:02:08.765930 All Pass.
5797 18:02:08.766444
5798 18:02:08.766749 CH 0, Rank 1
5799 18:02:08.769282 SW Impedance : PASS
5800 18:02:08.769672 DUTY Scan : NO K
5801 18:02:08.772635 ZQ Calibration : PASS
5802 18:02:08.775773 Jitter Meter : NO K
5803 18:02:08.776159 CBT Training : PASS
5804 18:02:08.779065 Write leveling : PASS
5805 18:02:08.782573 RX DQS gating : PASS
5806 18:02:08.782959 RX DQ/DQS(RDDQC) : PASS
5807 18:02:08.785461 TX DQ/DQS : PASS
5808 18:02:08.788630 RX DATLAT : PASS
5809 18:02:08.789017 RX DQ/DQS(Engine): PASS
5810 18:02:08.792203 TX OE : NO K
5811 18:02:08.792596 All Pass.
5812 18:02:08.792895
5813 18:02:08.795208 CH 1, Rank 0
5814 18:02:08.795597 SW Impedance : PASS
5815 18:02:08.798995 DUTY Scan : NO K
5816 18:02:08.802319 ZQ Calibration : PASS
5817 18:02:08.802712 Jitter Meter : NO K
5818 18:02:08.805682 CBT Training : PASS
5819 18:02:08.806073 Write leveling : PASS
5820 18:02:08.808920 RX DQS gating : PASS
5821 18:02:08.811904 RX DQ/DQS(RDDQC) : PASS
5822 18:02:08.812294 TX DQ/DQS : PASS
5823 18:02:08.815045 RX DATLAT : PASS
5824 18:02:08.818905 RX DQ/DQS(Engine): PASS
5825 18:02:08.819295 TX OE : NO K
5826 18:02:08.821652 All Pass.
5827 18:02:08.822052
5828 18:02:08.822389 CH 1, Rank 1
5829 18:02:08.825050 SW Impedance : PASS
5830 18:02:08.825421 DUTY Scan : NO K
5831 18:02:08.828183 ZQ Calibration : PASS
5832 18:02:08.831803 Jitter Meter : NO K
5833 18:02:08.832191 CBT Training : PASS
5834 18:02:08.835262 Write leveling : PASS
5835 18:02:08.838532 RX DQS gating : PASS
5836 18:02:08.838919 RX DQ/DQS(RDDQC) : PASS
5837 18:02:08.841552 TX DQ/DQS : PASS
5838 18:02:08.845218 RX DATLAT : PASS
5839 18:02:08.845603 RX DQ/DQS(Engine): PASS
5840 18:02:08.848474 TX OE : NO K
5841 18:02:08.848861 All Pass.
5842 18:02:08.849156
5843 18:02:08.851955 DramC Write-DBI off
5844 18:02:08.855070 PER_BANK_REFRESH: Hybrid Mode
5845 18:02:08.855498 TX_TRACKING: ON
5846 18:02:08.864729 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5847 18:02:08.868381 [FAST_K] Save calibration result to emmc
5848 18:02:08.871555 dramc_set_vcore_voltage set vcore to 650000
5849 18:02:08.875358 Read voltage for 400, 6
5850 18:02:08.875922 Vio18 = 0
5851 18:02:08.876348 Vcore = 650000
5852 18:02:08.878065 Vdram = 0
5853 18:02:08.878498 Vddq = 0
5854 18:02:08.878804 Vmddr = 0
5855 18:02:08.885116 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5856 18:02:08.888013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5857 18:02:08.891517 MEM_TYPE=3, freq_sel=20
5858 18:02:08.894898 sv_algorithm_assistance_LP4_800
5859 18:02:08.897952 ============ PULL DRAM RESETB DOWN ============
5860 18:02:08.900949 ========== PULL DRAM RESETB DOWN end =========
5861 18:02:08.908136 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5862 18:02:08.911240 ===================================
5863 18:02:08.911679 LPDDR4 DRAM CONFIGURATION
5864 18:02:08.914517 ===================================
5865 18:02:08.918044 EX_ROW_EN[0] = 0x0
5866 18:02:08.921106 EX_ROW_EN[1] = 0x0
5867 18:02:08.921498 LP4Y_EN = 0x0
5868 18:02:08.924608 WORK_FSP = 0x0
5869 18:02:08.925178 WL = 0x2
5870 18:02:08.927801 RL = 0x2
5871 18:02:08.928333 BL = 0x2
5872 18:02:08.931210 RPST = 0x0
5873 18:02:08.931685 RD_PRE = 0x0
5874 18:02:08.934474 WR_PRE = 0x1
5875 18:02:08.935075 WR_PST = 0x0
5876 18:02:08.937898 DBI_WR = 0x0
5877 18:02:08.938497 DBI_RD = 0x0
5878 18:02:08.940776 OTF = 0x1
5879 18:02:08.944378 ===================================
5880 18:02:08.947725 ===================================
5881 18:02:08.948255 ANA top config
5882 18:02:08.950857 ===================================
5883 18:02:08.954072 DLL_ASYNC_EN = 0
5884 18:02:08.957324 ALL_SLAVE_EN = 1
5885 18:02:08.960729 NEW_RANK_MODE = 1
5886 18:02:08.961148 DLL_IDLE_MODE = 1
5887 18:02:08.964432 LP45_APHY_COMB_EN = 1
5888 18:02:08.967312 TX_ODT_DIS = 1
5889 18:02:08.970778 NEW_8X_MODE = 1
5890 18:02:08.973737 ===================================
5891 18:02:08.977680 ===================================
5892 18:02:08.980667 data_rate = 800
5893 18:02:08.984257 CKR = 1
5894 18:02:08.984697 DQ_P2S_RATIO = 4
5895 18:02:08.987519 ===================================
5896 18:02:08.991002 CA_P2S_RATIO = 4
5897 18:02:08.994003 DQ_CA_OPEN = 0
5898 18:02:08.997632 DQ_SEMI_OPEN = 1
5899 18:02:09.000487 CA_SEMI_OPEN = 1
5900 18:02:09.000904 CA_FULL_RATE = 0
5901 18:02:09.004069 DQ_CKDIV4_EN = 0
5902 18:02:09.007514 CA_CKDIV4_EN = 1
5903 18:02:09.010751 CA_PREDIV_EN = 0
5904 18:02:09.013683 PH8_DLY = 0
5905 18:02:09.016991 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5906 18:02:09.017416 DQ_AAMCK_DIV = 0
5907 18:02:09.020328 CA_AAMCK_DIV = 0
5908 18:02:09.023481 CA_ADMCK_DIV = 4
5909 18:02:09.027086 DQ_TRACK_CA_EN = 0
5910 18:02:09.030165 CA_PICK = 800
5911 18:02:09.033461 CA_MCKIO = 400
5912 18:02:09.036522 MCKIO_SEMI = 400
5913 18:02:09.039891 PLL_FREQ = 3016
5914 18:02:09.040257 DQ_UI_PI_RATIO = 32
5915 18:02:09.043196 CA_UI_PI_RATIO = 32
5916 18:02:09.046415 ===================================
5917 18:02:09.049942 ===================================
5918 18:02:09.052810 memory_type:LPDDR4
5919 18:02:09.056371 GP_NUM : 10
5920 18:02:09.056537 SRAM_EN : 1
5921 18:02:09.059644 MD32_EN : 0
5922 18:02:09.062754 ===================================
5923 18:02:09.066114 [ANA_INIT] >>>>>>>>>>>>>>
5924 18:02:09.066245 <<<<<< [CONFIGURE PHASE]: ANA_TX
5925 18:02:09.072648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5926 18:02:09.075977 ===================================
5927 18:02:09.076098 data_rate = 800,PCW = 0X7400
5928 18:02:09.079713 ===================================
5929 18:02:09.082597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5930 18:02:09.089502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5931 18:02:09.099384 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5932 18:02:09.106402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5933 18:02:09.109562 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5934 18:02:09.113003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5935 18:02:09.115964 [ANA_INIT] flow start
5936 18:02:09.116295 [ANA_INIT] PLL >>>>>>>>
5937 18:02:09.119740 [ANA_INIT] PLL <<<<<<<<
5938 18:02:09.123138 [ANA_INIT] MIDPI >>>>>>>>
5939 18:02:09.123532 [ANA_INIT] MIDPI <<<<<<<<
5940 18:02:09.126470 [ANA_INIT] DLL >>>>>>>>
5941 18:02:09.129777 [ANA_INIT] flow end
5942 18:02:09.132740 ============ LP4 DIFF to SE enter ============
5943 18:02:09.136406 ============ LP4 DIFF to SE exit ============
5944 18:02:09.139411 [ANA_INIT] <<<<<<<<<<<<<
5945 18:02:09.142965 [Flow] Enable top DCM control >>>>>
5946 18:02:09.146080 [Flow] Enable top DCM control <<<<<
5947 18:02:09.149461 Enable DLL master slave shuffle
5948 18:02:09.153151 ==============================================================
5949 18:02:09.155847 Gating Mode config
5950 18:02:09.162670 ==============================================================
5951 18:02:09.163105 Config description:
5952 18:02:09.172675 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5953 18:02:09.179389 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5954 18:02:09.182599 SELPH_MODE 0: By rank 1: By Phase
5955 18:02:09.189110 ==============================================================
5956 18:02:09.192102 GAT_TRACK_EN = 0
5957 18:02:09.195792 RX_GATING_MODE = 2
5958 18:02:09.198652 RX_GATING_TRACK_MODE = 2
5959 18:02:09.202018 SELPH_MODE = 1
5960 18:02:09.205525 PICG_EARLY_EN = 1
5961 18:02:09.208891 VALID_LAT_VALUE = 1
5962 18:02:09.211939 ==============================================================
5963 18:02:09.215339 Enter into Gating configuration >>>>
5964 18:02:09.219048 Exit from Gating configuration <<<<
5965 18:02:09.222171 Enter into DVFS_PRE_config >>>>>
5966 18:02:09.235079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5967 18:02:09.238673 Exit from DVFS_PRE_config <<<<<
5968 18:02:09.239067 Enter into PICG configuration >>>>
5969 18:02:09.242247 Exit from PICG configuration <<<<
5970 18:02:09.245323 [RX_INPUT] configuration >>>>>
5971 18:02:09.248728 [RX_INPUT] configuration <<<<<
5972 18:02:09.255168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5973 18:02:09.258694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5974 18:02:09.265522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5975 18:02:09.272272 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5976 18:02:09.278671 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5977 18:02:09.285004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5978 18:02:09.288449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5979 18:02:09.291722 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5980 18:02:09.295015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5981 18:02:09.301316 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5982 18:02:09.304935 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5983 18:02:09.307863 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5984 18:02:09.311615 ===================================
5985 18:02:09.314713 LPDDR4 DRAM CONFIGURATION
5986 18:02:09.317904 ===================================
5987 18:02:09.321280 EX_ROW_EN[0] = 0x0
5988 18:02:09.321759 EX_ROW_EN[1] = 0x0
5989 18:02:09.324376 LP4Y_EN = 0x0
5990 18:02:09.324789 WORK_FSP = 0x0
5991 18:02:09.328040 WL = 0x2
5992 18:02:09.328463 RL = 0x2
5993 18:02:09.331098 BL = 0x2
5994 18:02:09.331487 RPST = 0x0
5995 18:02:09.334517 RD_PRE = 0x0
5996 18:02:09.335038 WR_PRE = 0x1
5997 18:02:09.337816 WR_PST = 0x0
5998 18:02:09.338254 DBI_WR = 0x0
5999 18:02:09.341125 DBI_RD = 0x0
6000 18:02:09.341515 OTF = 0x1
6001 18:02:09.344250 ===================================
6002 18:02:09.351263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6003 18:02:09.354291 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6004 18:02:09.357758 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 18:02:09.361314 ===================================
6006 18:02:09.364272 LPDDR4 DRAM CONFIGURATION
6007 18:02:09.367367 ===================================
6008 18:02:09.370785 EX_ROW_EN[0] = 0x10
6009 18:02:09.371177 EX_ROW_EN[1] = 0x0
6010 18:02:09.374537 LP4Y_EN = 0x0
6011 18:02:09.374971 WORK_FSP = 0x0
6012 18:02:09.377440 WL = 0x2
6013 18:02:09.377829 RL = 0x2
6014 18:02:09.381008 BL = 0x2
6015 18:02:09.381398 RPST = 0x0
6016 18:02:09.384314 RD_PRE = 0x0
6017 18:02:09.384777 WR_PRE = 0x1
6018 18:02:09.387324 WR_PST = 0x0
6019 18:02:09.387712 DBI_WR = 0x0
6020 18:02:09.390811 DBI_RD = 0x0
6021 18:02:09.391420 OTF = 0x1
6022 18:02:09.393929 ===================================
6023 18:02:09.400420 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6024 18:02:09.405578 nWR fixed to 30
6025 18:02:09.409068 [ModeRegInit_LP4] CH0 RK0
6026 18:02:09.409535 [ModeRegInit_LP4] CH0 RK1
6027 18:02:09.412089 [ModeRegInit_LP4] CH1 RK0
6028 18:02:09.415555 [ModeRegInit_LP4] CH1 RK1
6029 18:02:09.415946 match AC timing 18
6030 18:02:09.422182 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6031 18:02:09.425482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6032 18:02:09.428786 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6033 18:02:09.435489 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6034 18:02:09.438560 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6035 18:02:09.438992 ==
6036 18:02:09.442325 Dram Type= 6, Freq= 0, CH_0, rank 0
6037 18:02:09.445611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6038 18:02:09.446074 ==
6039 18:02:09.452692 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6040 18:02:09.458585 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6041 18:02:09.462281 [CA 0] Center 36 (8~64) winsize 57
6042 18:02:09.465253 [CA 1] Center 36 (8~64) winsize 57
6043 18:02:09.468565 [CA 2] Center 36 (8~64) winsize 57
6044 18:02:09.471969 [CA 3] Center 36 (8~64) winsize 57
6045 18:02:09.475244 [CA 4] Center 36 (8~64) winsize 57
6046 18:02:09.475675 [CA 5] Center 36 (8~64) winsize 57
6047 18:02:09.478169
6048 18:02:09.481448 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6049 18:02:09.482062
6050 18:02:09.485117 [CATrainingPosCal] consider 1 rank data
6051 18:02:09.488204 u2DelayCellTimex100 = 270/100 ps
6052 18:02:09.491701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6053 18:02:09.494620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6054 18:02:09.498615 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6055 18:02:09.501181 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6056 18:02:09.504818 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6057 18:02:09.508106 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 18:02:09.508613
6059 18:02:09.511338 CA PerBit enable=1, Macro0, CA PI delay=36
6060 18:02:09.511772
6061 18:02:09.514854 [CBTSetCACLKResult] CA Dly = 36
6062 18:02:09.518047 CS Dly: 1 (0~32)
6063 18:02:09.518553 ==
6064 18:02:09.521280 Dram Type= 6, Freq= 0, CH_0, rank 1
6065 18:02:09.524676 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6066 18:02:09.525110 ==
6067 18:02:09.531266 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6068 18:02:09.537855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6069 18:02:09.541150 [CA 0] Center 36 (8~64) winsize 57
6070 18:02:09.544466 [CA 1] Center 36 (8~64) winsize 57
6071 18:02:09.544902 [CA 2] Center 36 (8~64) winsize 57
6072 18:02:09.547859 [CA 3] Center 36 (8~64) winsize 57
6073 18:02:09.551087 [CA 4] Center 36 (8~64) winsize 57
6074 18:02:09.554330 [CA 5] Center 36 (8~64) winsize 57
6075 18:02:09.554745
6076 18:02:09.557614 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6077 18:02:09.561211
6078 18:02:09.564127 [CATrainingPosCal] consider 2 rank data
6079 18:02:09.564519 u2DelayCellTimex100 = 270/100 ps
6080 18:02:09.570706 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 18:02:09.574755 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 18:02:09.577459 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 18:02:09.581142 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 18:02:09.584374 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 18:02:09.587266 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 18:02:09.587968
6087 18:02:09.590586 CA PerBit enable=1, Macro0, CA PI delay=36
6088 18:02:09.591015
6089 18:02:09.594117 [CBTSetCACLKResult] CA Dly = 36
6090 18:02:09.597022 CS Dly: 1 (0~32)
6091 18:02:09.597449
6092 18:02:09.600686 ----->DramcWriteLeveling(PI) begin...
6093 18:02:09.601121 ==
6094 18:02:09.603683 Dram Type= 6, Freq= 0, CH_0, rank 0
6095 18:02:09.607409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 18:02:09.607937 ==
6097 18:02:09.610325 Write leveling (Byte 0): 32 => 0
6098 18:02:09.613932 Write leveling (Byte 1): 32 => 0
6099 18:02:09.617624 DramcWriteLeveling(PI) end<-----
6100 18:02:09.618129
6101 18:02:09.618527 ==
6102 18:02:09.620769 Dram Type= 6, Freq= 0, CH_0, rank 0
6103 18:02:09.624160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6104 18:02:09.624597 ==
6105 18:02:09.627711 [Gating] SW mode calibration
6106 18:02:09.634081 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6107 18:02:09.640240 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6108 18:02:09.643926 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6109 18:02:09.646991 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6110 18:02:09.653736 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6111 18:02:09.656888 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6112 18:02:09.659954 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6113 18:02:09.666621 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6114 18:02:09.670464 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6115 18:02:09.673494 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6116 18:02:09.680149 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6117 18:02:09.680582 Total UI for P1: 0, mck2ui 16
6118 18:02:09.686787 best dqsien dly found for B0: ( 0, 10, 16)
6119 18:02:09.687220 Total UI for P1: 0, mck2ui 16
6120 18:02:09.693893 best dqsien dly found for B1: ( 0, 10, 24)
6121 18:02:09.697020 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6122 18:02:09.699942 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6123 18:02:09.700462
6124 18:02:09.703349 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6125 18:02:09.706336 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6126 18:02:09.709864 [Gating] SW calibration Done
6127 18:02:09.710287 ==
6128 18:02:09.712853 Dram Type= 6, Freq= 0, CH_0, rank 0
6129 18:02:09.716405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6130 18:02:09.716794 ==
6131 18:02:09.719515 RX Vref Scan: 0
6132 18:02:09.719903
6133 18:02:09.720205 RX Vref 0 -> 0, step: 1
6134 18:02:09.723024
6135 18:02:09.723415 RX Delay -410 -> 252, step: 16
6136 18:02:09.729696 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6137 18:02:09.733185 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6138 18:02:09.736332 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6139 18:02:09.739279 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6140 18:02:09.746267 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6141 18:02:09.749105 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6142 18:02:09.752799 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6143 18:02:09.756214 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6144 18:02:09.762671 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6145 18:02:09.765623 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6146 18:02:09.768920 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6147 18:02:09.775473 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6148 18:02:09.778497 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6149 18:02:09.782290 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6150 18:02:09.785541 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6151 18:02:09.792099 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6152 18:02:09.792249 ==
6153 18:02:09.795377 Dram Type= 6, Freq= 0, CH_0, rank 0
6154 18:02:09.798803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6155 18:02:09.798946 ==
6156 18:02:09.799055 DQS Delay:
6157 18:02:09.801832 DQS0 = 51, DQS1 = 59
6158 18:02:09.801977 DQM Delay:
6159 18:02:09.805128 DQM0 = 12, DQM1 = 16
6160 18:02:09.805276 DQ Delay:
6161 18:02:09.808598 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6162 18:02:09.811612 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6163 18:02:09.815212 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6164 18:02:09.818263 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6165 18:02:09.818425
6166 18:02:09.818550
6167 18:02:09.818664 ==
6168 18:02:09.822065 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 18:02:09.825002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 18:02:09.825190 ==
6171 18:02:09.825335
6172 18:02:09.828682
6173 18:02:09.828904 TX Vref Scan disable
6174 18:02:09.831827 == TX Byte 0 ==
6175 18:02:09.834882 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6176 18:02:09.838602 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6177 18:02:09.841533 == TX Byte 1 ==
6178 18:02:09.845041 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6179 18:02:09.848455 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6180 18:02:09.848887 ==
6181 18:02:09.851484 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 18:02:09.858284 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 18:02:09.858729 ==
6184 18:02:09.859035
6185 18:02:09.859312
6186 18:02:09.859575 TX Vref Scan disable
6187 18:02:09.861713 == TX Byte 0 ==
6188 18:02:09.865147 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 18:02:09.868158 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 18:02:09.871760 == TX Byte 1 ==
6191 18:02:09.874721 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 18:02:09.878307 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 18:02:09.878695
6194 18:02:09.881308 [DATLAT]
6195 18:02:09.881695 Freq=400, CH0 RK0
6196 18:02:09.881993
6197 18:02:09.884584 DATLAT Default: 0xf
6198 18:02:09.885062 0, 0xFFFF, sum = 0
6199 18:02:09.888231 1, 0xFFFF, sum = 0
6200 18:02:09.888705 2, 0xFFFF, sum = 0
6201 18:02:09.891766 3, 0xFFFF, sum = 0
6202 18:02:09.892161 4, 0xFFFF, sum = 0
6203 18:02:09.894617 5, 0xFFFF, sum = 0
6204 18:02:09.895029 6, 0xFFFF, sum = 0
6205 18:02:09.897862 7, 0xFFFF, sum = 0
6206 18:02:09.898399 8, 0xFFFF, sum = 0
6207 18:02:09.901079 9, 0xFFFF, sum = 0
6208 18:02:09.904281 10, 0xFFFF, sum = 0
6209 18:02:09.904675 11, 0xFFFF, sum = 0
6210 18:02:09.907781 12, 0x0, sum = 1
6211 18:02:09.908257 13, 0x0, sum = 2
6212 18:02:09.911036 14, 0x0, sum = 3
6213 18:02:09.911428 15, 0x0, sum = 4
6214 18:02:09.911738 best_step = 13
6215 18:02:09.912015
6216 18:02:09.914325 ==
6217 18:02:09.917655 Dram Type= 6, Freq= 0, CH_0, rank 0
6218 18:02:09.920887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6219 18:02:09.921342 ==
6220 18:02:09.921655 RX Vref Scan: 1
6221 18:02:09.921941
6222 18:02:09.924239 RX Vref 0 -> 0, step: 1
6223 18:02:09.924659
6224 18:02:09.927772 RX Delay -359 -> 252, step: 8
6225 18:02:09.928194
6226 18:02:09.930649 Set Vref, RX VrefLevel [Byte0]: 46
6227 18:02:09.934465 [Byte1]: 48
6228 18:02:09.938514
6229 18:02:09.938955 Final RX Vref Byte 0 = 46 to rank0
6230 18:02:09.941253 Final RX Vref Byte 1 = 48 to rank0
6231 18:02:09.944823 Final RX Vref Byte 0 = 46 to rank1
6232 18:02:09.947873 Final RX Vref Byte 1 = 48 to rank1==
6233 18:02:09.951556 Dram Type= 6, Freq= 0, CH_0, rank 0
6234 18:02:09.957680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 18:02:09.958117 ==
6236 18:02:09.958475 DQS Delay:
6237 18:02:09.961294 DQS0 = 52, DQS1 = 68
6238 18:02:09.961683 DQM Delay:
6239 18:02:09.961984 DQM0 = 9, DQM1 = 16
6240 18:02:09.965010 DQ Delay:
6241 18:02:09.967709 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6242 18:02:09.968104 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6243 18:02:09.971183 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6244 18:02:09.974657 DQ12 =20, DQ13 =24, DQ14 =28, DQ15 =28
6245 18:02:09.975124
6246 18:02:09.975427
6247 18:02:09.984209 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6248 18:02:09.988195 CH0 RK0: MR19=C0C, MR18=A8A8
6249 18:02:09.994511 CH0_RK0: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6250 18:02:09.995022 ==
6251 18:02:09.997390 Dram Type= 6, Freq= 0, CH_0, rank 1
6252 18:02:10.001057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 18:02:10.001488 ==
6254 18:02:10.004025 [Gating] SW mode calibration
6255 18:02:10.010856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 18:02:10.017699 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6257 18:02:10.020626 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 18:02:10.024064 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 18:02:10.030998 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 18:02:10.034065 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6261 18:02:10.037230 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 18:02:10.043662 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 18:02:10.046942 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 18:02:10.050334 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6265 18:02:10.057149 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 18:02:10.057662 Total UI for P1: 0, mck2ui 16
6267 18:02:10.063850 best dqsien dly found for B0: ( 0, 10, 16)
6268 18:02:10.064341 Total UI for P1: 0, mck2ui 16
6269 18:02:10.066898 best dqsien dly found for B1: ( 0, 10, 24)
6270 18:02:10.073501 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6271 18:02:10.076965 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6272 18:02:10.077460
6273 18:02:10.080156 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6274 18:02:10.083522 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6275 18:02:10.086769 [Gating] SW calibration Done
6276 18:02:10.087202 ==
6277 18:02:10.090124 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 18:02:10.093232 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6279 18:02:10.093632 ==
6280 18:02:10.096793 RX Vref Scan: 0
6281 18:02:10.097188
6282 18:02:10.097491 RX Vref 0 -> 0, step: 1
6283 18:02:10.097771
6284 18:02:10.099863 RX Delay -410 -> 252, step: 16
6285 18:02:10.106493 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6286 18:02:10.110182 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6287 18:02:10.113239 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6288 18:02:10.116370 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6289 18:02:10.122928 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6290 18:02:10.126770 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6291 18:02:10.129645 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6292 18:02:10.132807 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6293 18:02:10.139460 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 18:02:10.143193 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6295 18:02:10.146588 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 18:02:10.149983 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6297 18:02:10.156551 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 18:02:10.159274 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6299 18:02:10.162957 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 18:02:10.166147 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 18:02:10.169319 ==
6302 18:02:10.172786 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 18:02:10.176157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6304 18:02:10.176554 ==
6305 18:02:10.176857 DQS Delay:
6306 18:02:10.179256 DQS0 = 43, DQS1 = 59
6307 18:02:10.179646 DQM Delay:
6308 18:02:10.182452 DQM0 = 6, DQM1 = 15
6309 18:02:10.182841 DQ Delay:
6310 18:02:10.185728 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6311 18:02:10.189324 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6312 18:02:10.192342 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6313 18:02:10.195993 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6314 18:02:10.196413
6315 18:02:10.196716
6316 18:02:10.196991 ==
6317 18:02:10.199660 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 18:02:10.202667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 18:02:10.203079 ==
6320 18:02:10.203463
6321 18:02:10.203749
6322 18:02:10.206097 TX Vref Scan disable
6323 18:02:10.206707 == TX Byte 0 ==
6324 18:02:10.212853 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6325 18:02:10.215864 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6326 18:02:10.216255 == TX Byte 1 ==
6327 18:02:10.219348 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6328 18:02:10.225888 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6329 18:02:10.226314 ==
6330 18:02:10.229410 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 18:02:10.232357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 18:02:10.232754 ==
6333 18:02:10.233056
6334 18:02:10.233330
6335 18:02:10.235827 TX Vref Scan disable
6336 18:02:10.236219 == TX Byte 0 ==
6337 18:02:10.242510 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6338 18:02:10.245917 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6339 18:02:10.246332 == TX Byte 1 ==
6340 18:02:10.252093 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6341 18:02:10.255445 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6342 18:02:10.255995
6343 18:02:10.256434 [DATLAT]
6344 18:02:10.259072 Freq=400, CH0 RK1
6345 18:02:10.259465
6346 18:02:10.259763 DATLAT Default: 0xd
6347 18:02:10.262073 0, 0xFFFF, sum = 0
6348 18:02:10.262518 1, 0xFFFF, sum = 0
6349 18:02:10.265540 2, 0xFFFF, sum = 0
6350 18:02:10.265935 3, 0xFFFF, sum = 0
6351 18:02:10.269083 4, 0xFFFF, sum = 0
6352 18:02:10.269478 5, 0xFFFF, sum = 0
6353 18:02:10.271978 6, 0xFFFF, sum = 0
6354 18:02:10.272379 7, 0xFFFF, sum = 0
6355 18:02:10.275914 8, 0xFFFF, sum = 0
6356 18:02:10.276312 9, 0xFFFF, sum = 0
6357 18:02:10.279225 10, 0xFFFF, sum = 0
6358 18:02:10.279620 11, 0xFFFF, sum = 0
6359 18:02:10.281966 12, 0x0, sum = 1
6360 18:02:10.282408 13, 0x0, sum = 2
6361 18:02:10.285412 14, 0x0, sum = 3
6362 18:02:10.285798 15, 0x0, sum = 4
6363 18:02:10.288582 best_step = 13
6364 18:02:10.288961
6365 18:02:10.289255 ==
6366 18:02:10.291966 Dram Type= 6, Freq= 0, CH_0, rank 1
6367 18:02:10.295514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6368 18:02:10.295933 ==
6369 18:02:10.298657 RX Vref Scan: 0
6370 18:02:10.299145
6371 18:02:10.299438 RX Vref 0 -> 0, step: 1
6372 18:02:10.299710
6373 18:02:10.302052 RX Delay -359 -> 252, step: 8
6374 18:02:10.310309 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6375 18:02:10.313221 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6376 18:02:10.316779 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6377 18:02:10.319834 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6378 18:02:10.326653 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6379 18:02:10.330395 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6380 18:02:10.333706 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6381 18:02:10.336728 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6382 18:02:10.343581 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6383 18:02:10.346631 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6384 18:02:10.350426 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6385 18:02:10.353361 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6386 18:02:10.360276 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6387 18:02:10.363118 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6388 18:02:10.367253 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6389 18:02:10.372862 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6390 18:02:10.373245 ==
6391 18:02:10.376240 Dram Type= 6, Freq= 0, CH_0, rank 1
6392 18:02:10.380088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6393 18:02:10.380474 ==
6394 18:02:10.380768 DQS Delay:
6395 18:02:10.382796 DQS0 = 52, DQS1 = 64
6396 18:02:10.383156 DQM Delay:
6397 18:02:10.386407 DQM0 = 9, DQM1 = 13
6398 18:02:10.386788 DQ Delay:
6399 18:02:10.389486 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6400 18:02:10.392793 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6401 18:02:10.396027 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6402 18:02:10.399791 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6403 18:02:10.400174
6404 18:02:10.400507
6405 18:02:10.406309 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6406 18:02:10.409386 CH0 RK1: MR19=C0C, MR18=C0C0
6407 18:02:10.415878 CH0_RK1: MR19=0xC0C, MR18=0xC0C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6408 18:02:10.419209 [RxdqsGatingPostProcess] freq 400
6409 18:02:10.425741 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6410 18:02:10.429230 Pre-setting of DQS Precalculation
6411 18:02:10.432786 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6412 18:02:10.433171 ==
6413 18:02:10.435774 Dram Type= 6, Freq= 0, CH_1, rank 0
6414 18:02:10.439470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6415 18:02:10.439859 ==
6416 18:02:10.445634 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6417 18:02:10.452252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6418 18:02:10.455880 [CA 0] Center 36 (8~64) winsize 57
6419 18:02:10.459014 [CA 1] Center 36 (8~64) winsize 57
6420 18:02:10.462665 [CA 2] Center 36 (8~64) winsize 57
6421 18:02:10.465893 [CA 3] Center 36 (8~64) winsize 57
6422 18:02:10.469155 [CA 4] Center 36 (8~64) winsize 57
6423 18:02:10.469539 [CA 5] Center 36 (8~64) winsize 57
6424 18:02:10.472179
6425 18:02:10.475577 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6426 18:02:10.476030
6427 18:02:10.479008 [CATrainingPosCal] consider 1 rank data
6428 18:02:10.482189 u2DelayCellTimex100 = 270/100 ps
6429 18:02:10.485092 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6430 18:02:10.488946 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6431 18:02:10.491968 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6432 18:02:10.495233 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6433 18:02:10.498626 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6434 18:02:10.501972 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 18:02:10.502478
6436 18:02:10.508771 CA PerBit enable=1, Macro0, CA PI delay=36
6437 18:02:10.509168
6438 18:02:10.509472 [CBTSetCACLKResult] CA Dly = 36
6439 18:02:10.511754 CS Dly: 1 (0~32)
6440 18:02:10.512144 ==
6441 18:02:10.515256 Dram Type= 6, Freq= 0, CH_1, rank 1
6442 18:02:10.518328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6443 18:02:10.518752 ==
6444 18:02:10.525057 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6445 18:02:10.531309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6446 18:02:10.535098 [CA 0] Center 36 (8~64) winsize 57
6447 18:02:10.538073 [CA 1] Center 36 (8~64) winsize 57
6448 18:02:10.541582 [CA 2] Center 36 (8~64) winsize 57
6449 18:02:10.544688 [CA 3] Center 36 (8~64) winsize 57
6450 18:02:10.545077 [CA 4] Center 36 (8~64) winsize 57
6451 18:02:10.548226 [CA 5] Center 36 (8~64) winsize 57
6452 18:02:10.548614
6453 18:02:10.555099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6454 18:02:10.555534
6455 18:02:10.558059 [CATrainingPosCal] consider 2 rank data
6456 18:02:10.561354 u2DelayCellTimex100 = 270/100 ps
6457 18:02:10.564729 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 18:02:10.567721 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 18:02:10.571153 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 18:02:10.574323 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 18:02:10.577996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 18:02:10.580860 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 18:02:10.581254
6464 18:02:10.584469 CA PerBit enable=1, Macro0, CA PI delay=36
6465 18:02:10.584859
6466 18:02:10.588007 [CBTSetCACLKResult] CA Dly = 36
6467 18:02:10.591337 CS Dly: 1 (0~32)
6468 18:02:10.591728
6469 18:02:10.594905 ----->DramcWriteLeveling(PI) begin...
6470 18:02:10.595309 ==
6471 18:02:10.597555 Dram Type= 6, Freq= 0, CH_1, rank 0
6472 18:02:10.601126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 18:02:10.601656 ==
6474 18:02:10.604024 Write leveling (Byte 0): 32 => 0
6475 18:02:10.607518 Write leveling (Byte 1): 32 => 0
6476 18:02:10.610932 DramcWriteLeveling(PI) end<-----
6477 18:02:10.611320
6478 18:02:10.611619 ==
6479 18:02:10.614168 Dram Type= 6, Freq= 0, CH_1, rank 0
6480 18:02:10.617376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6481 18:02:10.617886 ==
6482 18:02:10.620412 [Gating] SW mode calibration
6483 18:02:10.627078 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 18:02:10.633779 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6485 18:02:10.637317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 18:02:10.643825 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 18:02:10.647174 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 18:02:10.650365 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 18:02:10.656724 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 18:02:10.660648 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 18:02:10.663689 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 18:02:10.670351 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6493 18:02:10.673353 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 18:02:10.676979 Total UI for P1: 0, mck2ui 16
6495 18:02:10.680008 best dqsien dly found for B0: ( 0, 10, 16)
6496 18:02:10.683752 Total UI for P1: 0, mck2ui 16
6497 18:02:10.686627 best dqsien dly found for B1: ( 0, 10, 16)
6498 18:02:10.690354 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6499 18:02:10.693290 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6500 18:02:10.693726
6501 18:02:10.696893 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6502 18:02:10.700000 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6503 18:02:10.703567 [Gating] SW calibration Done
6504 18:02:10.703954 ==
6505 18:02:10.706421 Dram Type= 6, Freq= 0, CH_1, rank 0
6506 18:02:10.709690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6507 18:02:10.713634 ==
6508 18:02:10.714039 RX Vref Scan: 0
6509 18:02:10.714489
6510 18:02:10.716395 RX Vref 0 -> 0, step: 1
6511 18:02:10.716796
6512 18:02:10.719690 RX Delay -410 -> 252, step: 16
6513 18:02:10.723250 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6514 18:02:10.726188 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 18:02:10.729616 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 18:02:10.736063 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 18:02:10.739598 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 18:02:10.742718 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6519 18:02:10.746535 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6520 18:02:10.752654 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6521 18:02:10.755896 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 18:02:10.759222 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 18:02:10.762693 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 18:02:10.769583 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6525 18:02:10.772804 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6526 18:02:10.776025 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6527 18:02:10.782587 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6528 18:02:10.785869 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6529 18:02:10.786301 ==
6530 18:02:10.789202 Dram Type= 6, Freq= 0, CH_1, rank 0
6531 18:02:10.792302 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6532 18:02:10.792819 ==
6533 18:02:10.796041 DQS Delay:
6534 18:02:10.796424 DQS0 = 43, DQS1 = 59
6535 18:02:10.796724 DQM Delay:
6536 18:02:10.798899 DQM0 = 6, DQM1 = 15
6537 18:02:10.799283 DQ Delay:
6538 18:02:10.802142 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6539 18:02:10.805702 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6540 18:02:10.809107 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6541 18:02:10.812819 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6542 18:02:10.813277
6543 18:02:10.813578
6544 18:02:10.813865 ==
6545 18:02:10.815408 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 18:02:10.818852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 18:02:10.822607 ==
6548 18:02:10.823008
6549 18:02:10.823402
6550 18:02:10.823772 TX Vref Scan disable
6551 18:02:10.825651 == TX Byte 0 ==
6552 18:02:10.828904 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6553 18:02:10.832568 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6554 18:02:10.836065 == TX Byte 1 ==
6555 18:02:10.838847 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6556 18:02:10.842144 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6557 18:02:10.842577 ==
6558 18:02:10.845284 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 18:02:10.851883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 18:02:10.852274 ==
6561 18:02:10.852575
6562 18:02:10.852853
6563 18:02:10.853117 TX Vref Scan disable
6564 18:02:10.855786 == TX Byte 0 ==
6565 18:02:10.859014 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 18:02:10.862482 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 18:02:10.865561 == TX Byte 1 ==
6568 18:02:10.868753 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 18:02:10.874895 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 18:02:10.875322
6571 18:02:10.875631 [DATLAT]
6572 18:02:10.875913 Freq=400, CH1 RK0
6573 18:02:10.876180
6574 18:02:10.878271 DATLAT Default: 0xf
6575 18:02:10.878664 0, 0xFFFF, sum = 0
6576 18:02:10.881644 1, 0xFFFF, sum = 0
6577 18:02:10.885082 2, 0xFFFF, sum = 0
6578 18:02:10.885509 3, 0xFFFF, sum = 0
6579 18:02:10.888187 4, 0xFFFF, sum = 0
6580 18:02:10.888583 5, 0xFFFF, sum = 0
6581 18:02:10.891612 6, 0xFFFF, sum = 0
6582 18:02:10.892008 7, 0xFFFF, sum = 0
6583 18:02:10.894816 8, 0xFFFF, sum = 0
6584 18:02:10.895210 9, 0xFFFF, sum = 0
6585 18:02:10.898451 10, 0xFFFF, sum = 0
6586 18:02:10.899079 11, 0xFFFF, sum = 0
6587 18:02:10.901672 12, 0x0, sum = 1
6588 18:02:10.902066 13, 0x0, sum = 2
6589 18:02:10.904592 14, 0x0, sum = 3
6590 18:02:10.904985 15, 0x0, sum = 4
6591 18:02:10.908437 best_step = 13
6592 18:02:10.908912
6593 18:02:10.909226 ==
6594 18:02:10.911404 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 18:02:10.914836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6596 18:02:10.915232 ==
6597 18:02:10.915536 RX Vref Scan: 1
6598 18:02:10.918446
6599 18:02:10.918936 RX Vref 0 -> 0, step: 1
6600 18:02:10.919405
6601 18:02:10.921417 RX Delay -359 -> 252, step: 8
6602 18:02:10.921856
6603 18:02:10.924297 Set Vref, RX VrefLevel [Byte0]: 56
6604 18:02:10.927798 [Byte1]: 48
6605 18:02:10.932200
6606 18:02:10.932587 Final RX Vref Byte 0 = 56 to rank0
6607 18:02:10.935476 Final RX Vref Byte 1 = 48 to rank0
6608 18:02:10.938841 Final RX Vref Byte 0 = 56 to rank1
6609 18:02:10.941969 Final RX Vref Byte 1 = 48 to rank1==
6610 18:02:10.945357 Dram Type= 6, Freq= 0, CH_1, rank 0
6611 18:02:10.952009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 18:02:10.952553 ==
6613 18:02:10.952870 DQS Delay:
6614 18:02:10.955573 DQS0 = 48, DQS1 = 64
6615 18:02:10.956179 DQM Delay:
6616 18:02:10.956646 DQM0 = 7, DQM1 = 16
6617 18:02:10.958825 DQ Delay:
6618 18:02:10.962612 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6619 18:02:10.963221 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6620 18:02:10.965559 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6621 18:02:10.968727 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6622 18:02:10.969177
6623 18:02:10.969492
6624 18:02:10.978528 [DQSOSCAuto] RK0, (LSB)MR18= 0xdede, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6625 18:02:10.982100 CH1 RK0: MR19=C0C, MR18=DEDE
6626 18:02:10.988896 CH1_RK0: MR19=0xC0C, MR18=0xDEDE, DQSOSC=382, MR23=63, INC=404, DEC=269
6627 18:02:10.989311 ==
6628 18:02:10.992316 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 18:02:10.995166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 18:02:10.995554 ==
6631 18:02:10.998284 [Gating] SW mode calibration
6632 18:02:11.004823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6633 18:02:11.008383 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6634 18:02:11.014879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6635 18:02:11.018463 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6636 18:02:11.021521 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6637 18:02:11.028156 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6638 18:02:11.031537 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6639 18:02:11.035059 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6640 18:02:11.041639 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6641 18:02:11.044819 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6642 18:02:11.048021 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6643 18:02:11.051547 Total UI for P1: 0, mck2ui 16
6644 18:02:11.054290 best dqsien dly found for B0: ( 0, 10, 16)
6645 18:02:11.057839 Total UI for P1: 0, mck2ui 16
6646 18:02:11.061284 best dqsien dly found for B1: ( 0, 10, 16)
6647 18:02:11.064556 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6648 18:02:11.071171 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6649 18:02:11.071485
6650 18:02:11.074518 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6651 18:02:11.077946 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6652 18:02:11.080897 [Gating] SW calibration Done
6653 18:02:11.081186 ==
6654 18:02:11.084235 Dram Type= 6, Freq= 0, CH_1, rank 1
6655 18:02:11.087326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6656 18:02:11.087695 ==
6657 18:02:11.090790 RX Vref Scan: 0
6658 18:02:11.091075
6659 18:02:11.091305 RX Vref 0 -> 0, step: 1
6660 18:02:11.091530
6661 18:02:11.094323 RX Delay -410 -> 252, step: 16
6662 18:02:11.100754 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6663 18:02:11.103809 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6664 18:02:11.106880 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6665 18:02:11.110598 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6666 18:02:11.117141 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6667 18:02:11.120788 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6668 18:02:11.123833 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6669 18:02:11.126860 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6670 18:02:11.133819 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6671 18:02:11.137203 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6672 18:02:11.140773 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6673 18:02:11.143524 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6674 18:02:11.150740 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6675 18:02:11.153678 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6676 18:02:11.156789 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6677 18:02:11.160343 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6678 18:02:11.163191 ==
6679 18:02:11.167025 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 18:02:11.170330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6681 18:02:11.170699 ==
6682 18:02:11.170994 DQS Delay:
6683 18:02:11.173480 DQS0 = 43, DQS1 = 59
6684 18:02:11.173957 DQM Delay:
6685 18:02:11.176901 DQM0 = 10, DQM1 = 17
6686 18:02:11.177290 DQ Delay:
6687 18:02:11.180304 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6688 18:02:11.183274 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6689 18:02:11.186793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6690 18:02:11.190482 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6691 18:02:11.190866
6692 18:02:11.191165
6693 18:02:11.191438 ==
6694 18:02:11.193310 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 18:02:11.196619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 18:02:11.197012 ==
6697 18:02:11.197312
6698 18:02:11.197585
6699 18:02:11.200038 TX Vref Scan disable
6700 18:02:11.200608 == TX Byte 0 ==
6701 18:02:11.206408 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6702 18:02:11.210013 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6703 18:02:11.210452 == TX Byte 1 ==
6704 18:02:11.216275 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6705 18:02:11.219828 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6706 18:02:11.220328 ==
6707 18:02:11.223456 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 18:02:11.226506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 18:02:11.227029 ==
6710 18:02:11.227512
6711 18:02:11.227813
6712 18:02:11.230038 TX Vref Scan disable
6713 18:02:11.230593 == TX Byte 0 ==
6714 18:02:11.236546 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6715 18:02:11.239590 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6716 18:02:11.239978 == TX Byte 1 ==
6717 18:02:11.246348 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6718 18:02:11.249837 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6719 18:02:11.250373
6720 18:02:11.250731 [DATLAT]
6721 18:02:11.253029 Freq=400, CH1 RK1
6722 18:02:11.253635
6723 18:02:11.254098 DATLAT Default: 0xd
6724 18:02:11.256487 0, 0xFFFF, sum = 0
6725 18:02:11.257080 1, 0xFFFF, sum = 0
6726 18:02:11.259493 2, 0xFFFF, sum = 0
6727 18:02:11.260011 3, 0xFFFF, sum = 0
6728 18:02:11.262979 4, 0xFFFF, sum = 0
6729 18:02:11.263505 5, 0xFFFF, sum = 0
6730 18:02:11.266284 6, 0xFFFF, sum = 0
6731 18:02:11.266810 7, 0xFFFF, sum = 0
6732 18:02:11.269414 8, 0xFFFF, sum = 0
6733 18:02:11.269922 9, 0xFFFF, sum = 0
6734 18:02:11.273057 10, 0xFFFF, sum = 0
6735 18:02:11.276496 11, 0xFFFF, sum = 0
6736 18:02:11.277054 12, 0x0, sum = 1
6737 18:02:11.277546 13, 0x0, sum = 2
6738 18:02:11.279622 14, 0x0, sum = 3
6739 18:02:11.280213 15, 0x0, sum = 4
6740 18:02:11.283201 best_step = 13
6741 18:02:11.283582
6742 18:02:11.283879 ==
6743 18:02:11.286377 Dram Type= 6, Freq= 0, CH_1, rank 1
6744 18:02:11.289911 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6745 18:02:11.290406 ==
6746 18:02:11.292656 RX Vref Scan: 0
6747 18:02:11.293041
6748 18:02:11.293338 RX Vref 0 -> 0, step: 1
6749 18:02:11.293617
6750 18:02:11.296187 RX Delay -359 -> 252, step: 8
6751 18:02:11.304407 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6752 18:02:11.307792 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6753 18:02:11.311393 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6754 18:02:11.314408 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6755 18:02:11.321056 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6756 18:02:11.324352 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6757 18:02:11.327667 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6758 18:02:11.331166 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6759 18:02:11.337982 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6760 18:02:11.341009 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6761 18:02:11.343921 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6762 18:02:11.350780 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6763 18:02:11.353947 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6764 18:02:11.357275 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6765 18:02:11.360778 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6766 18:02:11.367393 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6767 18:02:11.367829 ==
6768 18:02:11.370432 Dram Type= 6, Freq= 0, CH_1, rank 1
6769 18:02:11.373781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6770 18:02:11.374309 ==
6771 18:02:11.374643 DQS Delay:
6772 18:02:11.377249 DQS0 = 48, DQS1 = 64
6773 18:02:11.377758 DQM Delay:
6774 18:02:11.380307 DQM0 = 9, DQM1 = 15
6775 18:02:11.380833 DQ Delay:
6776 18:02:11.383929 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6777 18:02:11.387004 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6778 18:02:11.390593 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6779 18:02:11.393593 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6780 18:02:11.394116
6781 18:02:11.394484
6782 18:02:11.400547 [DQSOSCAuto] RK1, (LSB)MR18= 0xa2a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6783 18:02:11.403739 CH1 RK1: MR19=C0C, MR18=A2A2
6784 18:02:11.409943 CH1_RK1: MR19=0xC0C, MR18=0xA2A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6785 18:02:11.413175 [RxdqsGatingPostProcess] freq 400
6786 18:02:11.420384 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6787 18:02:11.423598 Pre-setting of DQS Precalculation
6788 18:02:11.426879 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6789 18:02:11.433218 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6790 18:02:11.439918 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6791 18:02:11.440353
6792 18:02:11.443423
6793 18:02:11.443808 [Calibration Summary] 800 Mbps
6794 18:02:11.446263 CH 0, Rank 0
6795 18:02:11.446651 SW Impedance : PASS
6796 18:02:11.450023 DUTY Scan : NO K
6797 18:02:11.453364 ZQ Calibration : PASS
6798 18:02:11.453760 Jitter Meter : NO K
6799 18:02:11.456798 CBT Training : PASS
6800 18:02:11.459637 Write leveling : PASS
6801 18:02:11.460076 RX DQS gating : PASS
6802 18:02:11.463268 RX DQ/DQS(RDDQC) : PASS
6803 18:02:11.466253 TX DQ/DQS : PASS
6804 18:02:11.466654 RX DATLAT : PASS
6805 18:02:11.469733 RX DQ/DQS(Engine): PASS
6806 18:02:11.472856 TX OE : NO K
6807 18:02:11.473242 All Pass.
6808 18:02:11.473540
6809 18:02:11.473814 CH 0, Rank 1
6810 18:02:11.476660 SW Impedance : PASS
6811 18:02:11.480120 DUTY Scan : NO K
6812 18:02:11.480563 ZQ Calibration : PASS
6813 18:02:11.483152 Jitter Meter : NO K
6814 18:02:11.483539 CBT Training : PASS
6815 18:02:11.486534 Write leveling : NO K
6816 18:02:11.489995 RX DQS gating : PASS
6817 18:02:11.490462 RX DQ/DQS(RDDQC) : PASS
6818 18:02:11.493036 TX DQ/DQS : PASS
6819 18:02:11.496527 RX DATLAT : PASS
6820 18:02:11.496976 RX DQ/DQS(Engine): PASS
6821 18:02:11.499880 TX OE : NO K
6822 18:02:11.500413 All Pass.
6823 18:02:11.500974
6824 18:02:11.502464 CH 1, Rank 0
6825 18:02:11.502891 SW Impedance : PASS
6826 18:02:11.505674 DUTY Scan : NO K
6827 18:02:11.509393 ZQ Calibration : PASS
6828 18:02:11.509804 Jitter Meter : NO K
6829 18:02:11.512438 CBT Training : PASS
6830 18:02:11.515827 Write leveling : PASS
6831 18:02:11.516261 RX DQS gating : PASS
6832 18:02:11.518905 RX DQ/DQS(RDDQC) : PASS
6833 18:02:11.522318 TX DQ/DQS : PASS
6834 18:02:11.522709 RX DATLAT : PASS
6835 18:02:11.525724 RX DQ/DQS(Engine): PASS
6836 18:02:11.529286 TX OE : NO K
6837 18:02:11.529674 All Pass.
6838 18:02:11.529974
6839 18:02:11.530277 CH 1, Rank 1
6840 18:02:11.532328 SW Impedance : PASS
6841 18:02:11.535764 DUTY Scan : NO K
6842 18:02:11.536228 ZQ Calibration : PASS
6843 18:02:11.539158 Jitter Meter : NO K
6844 18:02:11.542359 CBT Training : PASS
6845 18:02:11.542751 Write leveling : NO K
6846 18:02:11.545382 RX DQS gating : PASS
6847 18:02:11.548830 RX DQ/DQS(RDDQC) : PASS
6848 18:02:11.549213 TX DQ/DQS : PASS
6849 18:02:11.552164 RX DATLAT : PASS
6850 18:02:11.555486 RX DQ/DQS(Engine): PASS
6851 18:02:11.555882 TX OE : NO K
6852 18:02:11.556260 All Pass.
6853 18:02:11.556544
6854 18:02:11.558709 DramC Write-DBI off
6855 18:02:11.561902 PER_BANK_REFRESH: Hybrid Mode
6856 18:02:11.562318 TX_TRACKING: ON
6857 18:02:11.571980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6858 18:02:11.575519 [FAST_K] Save calibration result to emmc
6859 18:02:11.578313 dramc_set_vcore_voltage set vcore to 725000
6860 18:02:11.582112 Read voltage for 1600, 0
6861 18:02:11.582569 Vio18 = 0
6862 18:02:11.585079 Vcore = 725000
6863 18:02:11.585463 Vdram = 0
6864 18:02:11.585762 Vddq = 0
6865 18:02:11.586089 Vmddr = 0
6866 18:02:11.591767 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6867 18:02:11.598458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6868 18:02:11.598847 MEM_TYPE=3, freq_sel=13
6869 18:02:11.601415 sv_algorithm_assistance_LP4_3733
6870 18:02:11.608288 ============ PULL DRAM RESETB DOWN ============
6871 18:02:11.611351 ========== PULL DRAM RESETB DOWN end =========
6872 18:02:11.614431 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6873 18:02:11.617927 ===================================
6874 18:02:11.621558 LPDDR4 DRAM CONFIGURATION
6875 18:02:11.624748 ===================================
6876 18:02:11.625133 EX_ROW_EN[0] = 0x0
6877 18:02:11.628245 EX_ROW_EN[1] = 0x0
6878 18:02:11.631281 LP4Y_EN = 0x0
6879 18:02:11.631667 WORK_FSP = 0x1
6880 18:02:11.634314 WL = 0x5
6881 18:02:11.634697 RL = 0x5
6882 18:02:11.638027 BL = 0x2
6883 18:02:11.638496 RPST = 0x0
6884 18:02:11.640829 RD_PRE = 0x0
6885 18:02:11.641215 WR_PRE = 0x1
6886 18:02:11.644613 WR_PST = 0x1
6887 18:02:11.645265 DBI_WR = 0x0
6888 18:02:11.647668 DBI_RD = 0x0
6889 18:02:11.648129 OTF = 0x1
6890 18:02:11.650970 ===================================
6891 18:02:11.654070 ===================================
6892 18:02:11.657587 ANA top config
6893 18:02:11.660664 ===================================
6894 18:02:11.664251 DLL_ASYNC_EN = 0
6895 18:02:11.664637 ALL_SLAVE_EN = 0
6896 18:02:11.667598 NEW_RANK_MODE = 1
6897 18:02:11.670920 DLL_IDLE_MODE = 1
6898 18:02:11.673987 LP45_APHY_COMB_EN = 1
6899 18:02:11.674429 TX_ODT_DIS = 0
6900 18:02:11.677260 NEW_8X_MODE = 1
6901 18:02:11.680762 ===================================
6902 18:02:11.683994 ===================================
6903 18:02:11.687034 data_rate = 3200
6904 18:02:11.690865 CKR = 1
6905 18:02:11.693832 DQ_P2S_RATIO = 8
6906 18:02:11.696952 ===================================
6907 18:02:11.700456 CA_P2S_RATIO = 8
6908 18:02:11.700899 DQ_CA_OPEN = 0
6909 18:02:11.703996 DQ_SEMI_OPEN = 0
6910 18:02:11.707113 CA_SEMI_OPEN = 0
6911 18:02:11.710069 CA_FULL_RATE = 0
6912 18:02:11.713462 DQ_CKDIV4_EN = 0
6913 18:02:11.717004 CA_CKDIV4_EN = 0
6914 18:02:11.719987 CA_PREDIV_EN = 0
6915 18:02:11.720377 PH8_DLY = 12
6916 18:02:11.723622 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6917 18:02:11.726754 DQ_AAMCK_DIV = 4
6918 18:02:11.729940 CA_AAMCK_DIV = 4
6919 18:02:11.733456 CA_ADMCK_DIV = 4
6920 18:02:11.736851 DQ_TRACK_CA_EN = 0
6921 18:02:11.737284 CA_PICK = 1600
6922 18:02:11.739739 CA_MCKIO = 1600
6923 18:02:11.743466 MCKIO_SEMI = 0
6924 18:02:11.746468 PLL_FREQ = 3068
6925 18:02:11.750022 DQ_UI_PI_RATIO = 32
6926 18:02:11.753363 CA_UI_PI_RATIO = 0
6927 18:02:11.756321 ===================================
6928 18:02:11.760051 ===================================
6929 18:02:11.762914 memory_type:LPDDR4
6930 18:02:11.763303 GP_NUM : 10
6931 18:02:11.766666 SRAM_EN : 1
6932 18:02:11.767118 MD32_EN : 0
6933 18:02:11.770025 ===================================
6934 18:02:11.773078 [ANA_INIT] >>>>>>>>>>>>>>
6935 18:02:11.776352 <<<<<< [CONFIGURE PHASE]: ANA_TX
6936 18:02:11.779952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6937 18:02:11.783281 ===================================
6938 18:02:11.786496 data_rate = 3200,PCW = 0X7600
6939 18:02:11.789952 ===================================
6940 18:02:11.793221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6941 18:02:11.799683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6942 18:02:11.802908 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6943 18:02:11.809054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6944 18:02:11.812702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6945 18:02:11.816036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6946 18:02:11.816424 [ANA_INIT] flow start
6947 18:02:11.819101 [ANA_INIT] PLL >>>>>>>>
6948 18:02:11.822703 [ANA_INIT] PLL <<<<<<<<
6949 18:02:11.823087 [ANA_INIT] MIDPI >>>>>>>>
6950 18:02:11.825670 [ANA_INIT] MIDPI <<<<<<<<
6951 18:02:11.829503 [ANA_INIT] DLL >>>>>>>>
6952 18:02:11.829978 [ANA_INIT] DLL <<<<<<<<
6953 18:02:11.832590 [ANA_INIT] flow end
6954 18:02:11.836371 ============ LP4 DIFF to SE enter ============
6955 18:02:11.842634 ============ LP4 DIFF to SE exit ============
6956 18:02:11.843258 [ANA_INIT] <<<<<<<<<<<<<
6957 18:02:11.845574 [Flow] Enable top DCM control >>>>>
6958 18:02:11.849061 [Flow] Enable top DCM control <<<<<
6959 18:02:11.852164 Enable DLL master slave shuffle
6960 18:02:11.859363 ==============================================================
6961 18:02:11.859840 Gating Mode config
6962 18:02:11.865951 ==============================================================
6963 18:02:11.868911 Config description:
6964 18:02:11.878875 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6965 18:02:11.885216 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6966 18:02:11.888650 SELPH_MODE 0: By rank 1: By Phase
6967 18:02:11.895101 ==============================================================
6968 18:02:11.898892 GAT_TRACK_EN = 1
6969 18:02:11.899285 RX_GATING_MODE = 2
6970 18:02:11.901665 RX_GATING_TRACK_MODE = 2
6971 18:02:11.905061 SELPH_MODE = 1
6972 18:02:11.908243 PICG_EARLY_EN = 1
6973 18:02:11.911758 VALID_LAT_VALUE = 1
6974 18:02:11.918278 ==============================================================
6975 18:02:11.921856 Enter into Gating configuration >>>>
6976 18:02:11.924790 Exit from Gating configuration <<<<
6977 18:02:11.928355 Enter into DVFS_PRE_config >>>>>
6978 18:02:11.938120 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6979 18:02:11.941626 Exit from DVFS_PRE_config <<<<<
6980 18:02:11.944724 Enter into PICG configuration >>>>
6981 18:02:11.947985 Exit from PICG configuration <<<<
6982 18:02:11.951189 [RX_INPUT] configuration >>>>>
6983 18:02:11.954821 [RX_INPUT] configuration <<<<<
6984 18:02:11.957782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6985 18:02:11.964710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6986 18:02:11.971199 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6987 18:02:11.977783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6988 18:02:11.981342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6989 18:02:11.987860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6990 18:02:11.990790 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6991 18:02:11.997711 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6992 18:02:12.000778 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6993 18:02:12.004212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6994 18:02:12.007766 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6995 18:02:12.014476 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6996 18:02:12.017616 ===================================
6997 18:02:12.020775 LPDDR4 DRAM CONFIGURATION
6998 18:02:12.024023 ===================================
6999 18:02:12.024412 EX_ROW_EN[0] = 0x0
7000 18:02:12.027636 EX_ROW_EN[1] = 0x0
7001 18:02:12.028024 LP4Y_EN = 0x0
7002 18:02:12.030487 WORK_FSP = 0x1
7003 18:02:12.030875 WL = 0x5
7004 18:02:12.034204 RL = 0x5
7005 18:02:12.034620 BL = 0x2
7006 18:02:12.037711 RPST = 0x0
7007 18:02:12.038095 RD_PRE = 0x0
7008 18:02:12.040617 WR_PRE = 0x1
7009 18:02:12.041002 WR_PST = 0x1
7010 18:02:12.043695 DBI_WR = 0x0
7011 18:02:12.044080 DBI_RD = 0x0
7012 18:02:12.047533 OTF = 0x1
7013 18:02:12.050855 ===================================
7014 18:02:12.053798 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7015 18:02:12.057434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7016 18:02:12.063895 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7017 18:02:12.066999 ===================================
7018 18:02:12.070104 LPDDR4 DRAM CONFIGURATION
7019 18:02:12.073539 ===================================
7020 18:02:12.073928 EX_ROW_EN[0] = 0x10
7021 18:02:12.076933 EX_ROW_EN[1] = 0x0
7022 18:02:12.077318 LP4Y_EN = 0x0
7023 18:02:12.080726 WORK_FSP = 0x1
7024 18:02:12.081166 WL = 0x5
7025 18:02:12.083655 RL = 0x5
7026 18:02:12.084041 BL = 0x2
7027 18:02:12.086801 RPST = 0x0
7028 18:02:12.087190 RD_PRE = 0x0
7029 18:02:12.090329 WR_PRE = 0x1
7030 18:02:12.090780 WR_PST = 0x1
7031 18:02:12.093342 DBI_WR = 0x0
7032 18:02:12.093790 DBI_RD = 0x0
7033 18:02:12.096716 OTF = 0x1
7034 18:02:12.100398 ===================================
7035 18:02:12.106493 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7036 18:02:12.106888 ==
7037 18:02:12.109854 Dram Type= 6, Freq= 0, CH_0, rank 0
7038 18:02:12.113089 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7039 18:02:12.113474 ==
7040 18:02:12.116526 [Duty_Offset_Calibration]
7041 18:02:12.116923 B0:0 B1:2 CA:1
7042 18:02:12.117219
7043 18:02:12.119996 [DutyScan_Calibration_Flow] k_type=0
7044 18:02:12.130825
7045 18:02:12.131207 ==CLK 0==
7046 18:02:12.134501 Final CLK duty delay cell = 0
7047 18:02:12.137847 [0] MAX Duty = 5156%(X100), DQS PI = 22
7048 18:02:12.141313 [0] MIN Duty = 4938%(X100), DQS PI = 52
7049 18:02:12.141695 [0] AVG Duty = 5047%(X100)
7050 18:02:12.144482
7051 18:02:12.147898 CH0 CLK Duty spec in!! Max-Min= 218%
7052 18:02:12.151349 [DutyScan_Calibration_Flow] ====Done====
7053 18:02:12.151733
7054 18:02:12.154425 [DutyScan_Calibration_Flow] k_type=1
7055 18:02:12.171416
7056 18:02:12.171863 ==DQS 0 ==
7057 18:02:12.174446 Final DQS duty delay cell = 0
7058 18:02:12.177592 [0] MAX Duty = 5125%(X100), DQS PI = 2
7059 18:02:12.181225 [0] MIN Duty = 5031%(X100), DQS PI = 8
7060 18:02:12.181672 [0] AVG Duty = 5078%(X100)
7061 18:02:12.184816
7062 18:02:12.185195 ==DQS 1 ==
7063 18:02:12.188077 Final DQS duty delay cell = 0
7064 18:02:12.190983 [0] MAX Duty = 5031%(X100), DQS PI = 46
7065 18:02:12.194800 [0] MIN Duty = 4844%(X100), DQS PI = 18
7066 18:02:12.195243 [0] AVG Duty = 4937%(X100)
7067 18:02:12.197644
7068 18:02:12.200998 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7069 18:02:12.201387
7070 18:02:12.204093 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7071 18:02:12.207894 [DutyScan_Calibration_Flow] ====Done====
7072 18:02:12.208381
7073 18:02:12.210801 [DutyScan_Calibration_Flow] k_type=3
7074 18:02:12.228074
7075 18:02:12.228487 ==DQM 0 ==
7076 18:02:12.231727 Final DQM duty delay cell = 0
7077 18:02:12.234525 [0] MAX Duty = 5187%(X100), DQS PI = 24
7078 18:02:12.237970 [0] MIN Duty = 4876%(X100), DQS PI = 56
7079 18:02:12.241264 [0] AVG Duty = 5031%(X100)
7080 18:02:12.241759
7081 18:02:12.242266 ==DQM 1 ==
7082 18:02:12.244723 Final DQM duty delay cell = 0
7083 18:02:12.248077 [0] MAX Duty = 5031%(X100), DQS PI = 50
7084 18:02:12.251553 [0] MIN Duty = 4782%(X100), DQS PI = 14
7085 18:02:12.254676 [0] AVG Duty = 4906%(X100)
7086 18:02:12.255060
7087 18:02:12.258276 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7088 18:02:12.258665
7089 18:02:12.261330 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7090 18:02:12.264816 [DutyScan_Calibration_Flow] ====Done====
7091 18:02:12.265259
7092 18:02:12.267839 [DutyScan_Calibration_Flow] k_type=2
7093 18:02:12.284845
7094 18:02:12.285308 ==DQ 0 ==
7095 18:02:12.287801 Final DQ duty delay cell = 0
7096 18:02:12.291418 [0] MAX Duty = 5218%(X100), DQS PI = 18
7097 18:02:12.294567 [0] MIN Duty = 4938%(X100), DQS PI = 56
7098 18:02:12.298072 [0] AVG Duty = 5078%(X100)
7099 18:02:12.298495
7100 18:02:12.298811 ==DQ 1 ==
7101 18:02:12.300666 Final DQ duty delay cell = -4
7102 18:02:12.304452 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7103 18:02:12.307963 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7104 18:02:12.310854 [-4] AVG Duty = 4969%(X100)
7105 18:02:12.311347
7106 18:02:12.314175 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7107 18:02:12.314618
7108 18:02:12.317845 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7109 18:02:12.320914 [DutyScan_Calibration_Flow] ====Done====
7110 18:02:12.321326 ==
7111 18:02:12.324269 Dram Type= 6, Freq= 0, CH_1, rank 0
7112 18:02:12.327438 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7113 18:02:12.327825 ==
7114 18:02:12.331160 [Duty_Offset_Calibration]
7115 18:02:12.331543 B0:0 B1:4 CA:-5
7116 18:02:12.331840
7117 18:02:12.334107 [DutyScan_Calibration_Flow] k_type=0
7118 18:02:12.344849
7119 18:02:12.345231 ==CLK 0==
7120 18:02:12.348399 Final CLK duty delay cell = 0
7121 18:02:12.351470 [0] MAX Duty = 5156%(X100), DQS PI = 18
7122 18:02:12.355063 [0] MIN Duty = 4906%(X100), DQS PI = 50
7123 18:02:12.355446 [0] AVG Duty = 5031%(X100)
7124 18:02:12.358283
7125 18:02:12.361631 CH1 CLK Duty spec in!! Max-Min= 250%
7126 18:02:12.365166 [DutyScan_Calibration_Flow] ====Done====
7127 18:02:12.365603
7128 18:02:12.368470 [DutyScan_Calibration_Flow] k_type=1
7129 18:02:12.384779
7130 18:02:12.385270 ==DQS 0 ==
7131 18:02:12.387536 Final DQS duty delay cell = 0
7132 18:02:12.391267 [0] MAX Duty = 5187%(X100), DQS PI = 20
7133 18:02:12.394201 [0] MIN Duty = 4907%(X100), DQS PI = 0
7134 18:02:12.397546 [0] AVG Duty = 5047%(X100)
7135 18:02:12.398200
7136 18:02:12.398621 ==DQS 1 ==
7137 18:02:12.400968 Final DQS duty delay cell = -4
7138 18:02:12.404125 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7139 18:02:12.407465 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7140 18:02:12.410269 [-4] AVG Duty = 4922%(X100)
7141 18:02:12.410653
7142 18:02:12.413921 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7143 18:02:12.414442
7144 18:02:12.417515 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7145 18:02:12.420370 [DutyScan_Calibration_Flow] ====Done====
7146 18:02:12.420809
7147 18:02:12.424284 [DutyScan_Calibration_Flow] k_type=3
7148 18:02:12.439911
7149 18:02:12.440304 ==DQM 0 ==
7150 18:02:12.443064 Final DQM duty delay cell = -4
7151 18:02:12.446714 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7152 18:02:12.449828 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7153 18:02:12.452943 [-4] AVG Duty = 4937%(X100)
7154 18:02:12.453346
7155 18:02:12.453681 ==DQM 1 ==
7156 18:02:12.456355 Final DQM duty delay cell = -4
7157 18:02:12.459308 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7158 18:02:12.462766 [-4] MIN Duty = 4876%(X100), DQS PI = 38
7159 18:02:12.465821 [-4] AVG Duty = 4969%(X100)
7160 18:02:12.466543
7161 18:02:12.469193 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7162 18:02:12.469877
7163 18:02:12.472671 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7164 18:02:12.475961 [DutyScan_Calibration_Flow] ====Done====
7165 18:02:12.476377
7166 18:02:12.479008 [DutyScan_Calibration_Flow] k_type=2
7167 18:02:12.497800
7168 18:02:12.498306 ==DQ 0 ==
7169 18:02:12.500751 Final DQ duty delay cell = 0
7170 18:02:12.504179 [0] MAX Duty = 5093%(X100), DQS PI = 18
7171 18:02:12.506999 [0] MIN Duty = 4938%(X100), DQS PI = 46
7172 18:02:12.507458 [0] AVG Duty = 5015%(X100)
7173 18:02:12.510340
7174 18:02:12.510779 ==DQ 1 ==
7175 18:02:12.513661 Final DQ duty delay cell = 0
7176 18:02:12.516787 [0] MAX Duty = 5031%(X100), DQS PI = 4
7177 18:02:12.520668 [0] MIN Duty = 4876%(X100), DQS PI = 28
7178 18:02:12.521289 [0] AVG Duty = 4953%(X100)
7179 18:02:12.523807
7180 18:02:12.526670 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7181 18:02:12.527058
7182 18:02:12.530286 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7183 18:02:12.533921 [DutyScan_Calibration_Flow] ====Done====
7184 18:02:12.536819 nWR fixed to 30
7185 18:02:12.537261 [ModeRegInit_LP4] CH0 RK0
7186 18:02:12.540512 [ModeRegInit_LP4] CH0 RK1
7187 18:02:12.543955 [ModeRegInit_LP4] CH1 RK0
7188 18:02:12.547109 [ModeRegInit_LP4] CH1 RK1
7189 18:02:12.547496 match AC timing 4
7190 18:02:12.550478 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7191 18:02:12.557189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7192 18:02:12.559948 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7193 18:02:12.566961 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7194 18:02:12.570184 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7195 18:02:12.570800 [MiockJmeterHQA]
7196 18:02:12.571142
7197 18:02:12.573226 [DramcMiockJmeter] u1RxGatingPI = 0
7198 18:02:12.576910 0 : 4366, 4140
7199 18:02:12.577343 4 : 4252, 4027
7200 18:02:12.580139 8 : 4253, 4026
7201 18:02:12.580569 12 : 4252, 4027
7202 18:02:12.580871 16 : 4255, 4029
7203 18:02:12.583185 20 : 4362, 4137
7204 18:02:12.583573 24 : 4252, 4027
7205 18:02:12.586550 28 : 4363, 4138
7206 18:02:12.587016 32 : 4253, 4026
7207 18:02:12.589881 36 : 4252, 4026
7208 18:02:12.590335 40 : 4252, 4027
7209 18:02:12.593684 44 : 4363, 4137
7210 18:02:12.594075 48 : 4363, 4138
7211 18:02:12.594435 52 : 4253, 4027
7212 18:02:12.596314 56 : 4253, 4027
7213 18:02:12.596836 60 : 4253, 4026
7214 18:02:12.600034 64 : 4252, 4027
7215 18:02:12.600428 68 : 4254, 4029
7216 18:02:12.603040 72 : 4361, 4137
7217 18:02:12.603457 76 : 4250, 4027
7218 18:02:12.606333 80 : 4250, 4026
7219 18:02:12.606903 84 : 4250, 4027
7220 18:02:12.607232 88 : 4252, 4030
7221 18:02:12.609409 92 : 4250, 4026
7222 18:02:12.609721 96 : 4361, 4137
7223 18:02:12.613093 100 : 4361, 1566
7224 18:02:12.613487 104 : 4249, 0
7225 18:02:12.616832 108 : 4250, 0
7226 18:02:12.617228 112 : 4250, 0
7227 18:02:12.617532 116 : 4361, 0
7228 18:02:12.619476 120 : 4250, 0
7229 18:02:12.619865 124 : 4250, 0
7230 18:02:12.622907 128 : 4250, 0
7231 18:02:12.623342 132 : 4250, 0
7232 18:02:12.623655 136 : 4252, 0
7233 18:02:12.626581 140 : 4250, 0
7234 18:02:12.626975 144 : 4360, 0
7235 18:02:12.627275 148 : 4249, 0
7236 18:02:12.629551 152 : 4250, 0
7237 18:02:12.629941 156 : 4249, 0
7238 18:02:12.633277 160 : 4250, 0
7239 18:02:12.633784 164 : 4361, 0
7240 18:02:12.634092 168 : 4360, 0
7241 18:02:12.635981 172 : 4250, 0
7242 18:02:12.636370 176 : 4250, 0
7243 18:02:12.639511 180 : 4360, 0
7244 18:02:12.639903 184 : 4250, 0
7245 18:02:12.640205 188 : 4250, 0
7246 18:02:12.642569 192 : 4250, 0
7247 18:02:12.642962 196 : 4250, 0
7248 18:02:12.646367 200 : 4252, 0
7249 18:02:12.646761 204 : 4250, 0
7250 18:02:12.647066 208 : 4250, 0
7251 18:02:12.649441 212 : 4252, 0
7252 18:02:12.649833 216 : 4250, 0
7253 18:02:12.652746 220 : 4361, 674
7254 18:02:12.653140 224 : 4250, 4006
7255 18:02:12.656637 228 : 4253, 4029
7256 18:02:12.657104 232 : 4252, 4029
7257 18:02:12.657407 236 : 4250, 4026
7258 18:02:12.659244 240 : 4361, 4137
7259 18:02:12.659634 244 : 4250, 4027
7260 18:02:12.662317 248 : 4360, 4138
7261 18:02:12.662759 252 : 4360, 4138
7262 18:02:12.665970 256 : 4250, 4027
7263 18:02:12.666461 260 : 4250, 4027
7264 18:02:12.668823 264 : 4363, 4140
7265 18:02:12.669211 268 : 4250, 4027
7266 18:02:12.672703 272 : 4250, 4027
7267 18:02:12.673122 276 : 4250, 4027
7268 18:02:12.675839 280 : 4250, 4027
7269 18:02:12.676228 284 : 4249, 4027
7270 18:02:12.678903 288 : 4250, 4026
7271 18:02:12.679295 292 : 4361, 4137
7272 18:02:12.682161 296 : 4253, 4029
7273 18:02:12.682653 300 : 4250, 4027
7274 18:02:12.682959 304 : 4360, 4137
7275 18:02:12.685770 308 : 4250, 4027
7276 18:02:12.686258 312 : 4250, 4027
7277 18:02:12.689090 316 : 4363, 4139
7278 18:02:12.689496 320 : 4250, 4027
7279 18:02:12.692154 324 : 4250, 4026
7280 18:02:12.692566 328 : 4250, 4027
7281 18:02:12.695541 332 : 4250, 4027
7282 18:02:12.695946 336 : 4250, 3675
7283 18:02:12.698908 340 : 4250, 1543
7284 18:02:12.699561
7285 18:02:12.699982 MIOCK jitter meter ch=0
7286 18:02:12.700277
7287 18:02:12.702590 1T = (340-100) = 240 dly cells
7288 18:02:12.708657 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7289 18:02:12.709049 ==
7290 18:02:12.712417 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 18:02:12.715688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7292 18:02:12.716169 ==
7293 18:02:12.721838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7294 18:02:12.725339 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7295 18:02:12.732297 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7296 18:02:12.735270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7297 18:02:12.744806 [CA 0] Center 42 (12~73) winsize 62
7298 18:02:12.747707 [CA 1] Center 42 (12~73) winsize 62
7299 18:02:12.751424 [CA 2] Center 39 (9~69) winsize 61
7300 18:02:12.754427 [CA 3] Center 38 (9~68) winsize 60
7301 18:02:12.757922 [CA 4] Center 36 (6~67) winsize 62
7302 18:02:12.761181 [CA 5] Center 36 (6~66) winsize 61
7303 18:02:12.761639
7304 18:02:12.764886 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7305 18:02:12.765376
7306 18:02:12.767745 [CATrainingPosCal] consider 1 rank data
7307 18:02:12.771361 u2DelayCellTimex100 = 271/100 ps
7308 18:02:12.774496 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7309 18:02:12.781285 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7310 18:02:12.784526 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7311 18:02:12.787634 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7312 18:02:12.791054 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
7313 18:02:12.794540 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7314 18:02:12.794927
7315 18:02:12.797440 CA PerBit enable=1, Macro0, CA PI delay=36
7316 18:02:12.797830
7317 18:02:12.800969 [CBTSetCACLKResult] CA Dly = 36
7318 18:02:12.804408 CS Dly: 10 (0~41)
7319 18:02:12.807367 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7320 18:02:12.810817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7321 18:02:12.811203 ==
7322 18:02:12.814329 Dram Type= 6, Freq= 0, CH_0, rank 1
7323 18:02:12.817194 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7324 18:02:12.820649 ==
7325 18:02:12.823992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7326 18:02:12.827454 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7327 18:02:12.834307 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7328 18:02:12.840774 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7329 18:02:12.847139 [CA 0] Center 42 (12~73) winsize 62
7330 18:02:12.850721 [CA 1] Center 41 (11~72) winsize 62
7331 18:02:12.853871 [CA 2] Center 38 (9~68) winsize 60
7332 18:02:12.857701 [CA 3] Center 37 (7~67) winsize 61
7333 18:02:12.860610 [CA 4] Center 35 (5~65) winsize 61
7334 18:02:12.863942 [CA 5] Center 35 (5~66) winsize 62
7335 18:02:12.864439
7336 18:02:12.867028 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7337 18:02:12.867419
7338 18:02:12.870515 [CATrainingPosCal] consider 2 rank data
7339 18:02:12.873641 u2DelayCellTimex100 = 271/100 ps
7340 18:02:12.880267 CA0 delay=42 (12~73),Diff = 7 PI (25 cell)
7341 18:02:12.883458 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7342 18:02:12.886810 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7343 18:02:12.890202 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7344 18:02:12.893586 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7345 18:02:12.896728 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
7346 18:02:12.897117
7347 18:02:12.900146 CA PerBit enable=1, Macro0, CA PI delay=35
7348 18:02:12.900533
7349 18:02:12.903255 [CBTSetCACLKResult] CA Dly = 35
7350 18:02:12.906401 CS Dly: 11 (0~43)
7351 18:02:12.910099 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7352 18:02:12.913515 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7353 18:02:12.913906
7354 18:02:12.916567 ----->DramcWriteLeveling(PI) begin...
7355 18:02:12.916957 ==
7356 18:02:12.920117 Dram Type= 6, Freq= 0, CH_0, rank 0
7357 18:02:12.926483 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7358 18:02:12.926872 ==
7359 18:02:12.929689 Write leveling (Byte 0): 31 => 31
7360 18:02:12.932850 Write leveling (Byte 1): 27 => 27
7361 18:02:12.933359 DramcWriteLeveling(PI) end<-----
7362 18:02:12.936389
7363 18:02:12.936851 ==
7364 18:02:12.940003 Dram Type= 6, Freq= 0, CH_0, rank 0
7365 18:02:12.942694 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7366 18:02:12.943153 ==
7367 18:02:12.946059 [Gating] SW mode calibration
7368 18:02:12.953047 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7369 18:02:12.956080 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7370 18:02:12.962788 0 12 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7371 18:02:12.965577 0 12 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7372 18:02:12.969212 0 12 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7373 18:02:12.975593 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7374 18:02:12.979255 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7375 18:02:12.982287 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7376 18:02:12.988748 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7377 18:02:12.992817 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7378 18:02:12.995944 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7379 18:02:13.002553 0 13 4 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
7380 18:02:13.006104 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7381 18:02:13.008870 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7382 18:02:13.015666 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7383 18:02:13.018906 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7384 18:02:13.022609 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7385 18:02:13.028607 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7386 18:02:13.032390 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7387 18:02:13.035330 0 14 4 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
7388 18:02:13.041890 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7389 18:02:13.045321 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 18:02:13.048749 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7391 18:02:13.055084 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7392 18:02:13.058236 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7393 18:02:13.062276 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7394 18:02:13.068622 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7395 18:02:13.071771 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7396 18:02:13.075279 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7397 18:02:13.081718 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7398 18:02:13.085324 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7399 18:02:13.088846 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7400 18:02:13.095253 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7401 18:02:13.098190 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7402 18:02:13.101562 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7403 18:02:13.107933 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7404 18:02:13.111661 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7405 18:02:13.115001 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 18:02:13.121688 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 18:02:13.125141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 18:02:13.127839 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 18:02:13.134520 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 18:02:13.138205 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7411 18:02:13.141390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7412 18:02:13.147647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7413 18:02:13.148111 Total UI for P1: 0, mck2ui 16
7414 18:02:13.154816 best dqsien dly found for B0: ( 1, 1, 2)
7415 18:02:13.157918 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7416 18:02:13.161286 Total UI for P1: 0, mck2ui 16
7417 18:02:13.164978 best dqsien dly found for B1: ( 1, 1, 4)
7418 18:02:13.167928 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7419 18:02:13.171293 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7420 18:02:13.171693
7421 18:02:13.174107 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7422 18:02:13.177582 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7423 18:02:13.181016 [Gating] SW calibration Done
7424 18:02:13.181506 ==
7425 18:02:13.184487 Dram Type= 6, Freq= 0, CH_0, rank 0
7426 18:02:13.187756 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7427 18:02:13.188147 ==
7428 18:02:13.190751 RX Vref Scan: 0
7429 18:02:13.191140
7430 18:02:13.194478 RX Vref 0 -> 0, step: 1
7431 18:02:13.194941
7432 18:02:13.195242 RX Delay 0 -> 252, step: 8
7433 18:02:13.201122 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
7434 18:02:13.203838 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7435 18:02:13.207102 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7436 18:02:13.210719 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7437 18:02:13.213713 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7438 18:02:13.220232 iDelay=200, Bit 5, Center 119 (56 ~ 183) 128
7439 18:02:13.223966 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7440 18:02:13.227391 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7441 18:02:13.230258 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7442 18:02:13.233815 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7443 18:02:13.240479 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7444 18:02:13.243641 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7445 18:02:13.247202 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7446 18:02:13.250738 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7447 18:02:13.257407 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7448 18:02:13.260360 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7449 18:02:13.260762 ==
7450 18:02:13.263527 Dram Type= 6, Freq= 0, CH_0, rank 0
7451 18:02:13.267079 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7452 18:02:13.267481 ==
7453 18:02:13.269930 DQS Delay:
7454 18:02:13.270379 DQS0 = 0, DQS1 = 0
7455 18:02:13.270778 DQM Delay:
7456 18:02:13.273357 DQM0 = 129, DQM1 = 123
7457 18:02:13.273759 DQ Delay:
7458 18:02:13.276853 DQ0 =123, DQ1 =131, DQ2 =123, DQ3 =127
7459 18:02:13.280557 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7460 18:02:13.283246 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
7461 18:02:13.290319 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7462 18:02:13.290722
7463 18:02:13.291117
7464 18:02:13.291489 ==
7465 18:02:13.293216 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 18:02:13.297051 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7467 18:02:13.297489 ==
7468 18:02:13.297992
7469 18:02:13.298438
7470 18:02:13.300218 TX Vref Scan disable
7471 18:02:13.300620 == TX Byte 0 ==
7472 18:02:13.306792 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7473 18:02:13.309600 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7474 18:02:13.310180 == TX Byte 1 ==
7475 18:02:13.316778 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7476 18:02:13.319809 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7477 18:02:13.320210 ==
7478 18:02:13.323371 Dram Type= 6, Freq= 0, CH_0, rank 0
7479 18:02:13.326524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7480 18:02:13.326926 ==
7481 18:02:13.341904
7482 18:02:13.345011 TX Vref early break, caculate TX vref
7483 18:02:13.348361 TX Vref=16, minBit 8, minWin=22, winSum=372
7484 18:02:13.351256 TX Vref=18, minBit 8, minWin=22, winSum=379
7485 18:02:13.354916 TX Vref=20, minBit 8, minWin=22, winSum=388
7486 18:02:13.358578 TX Vref=22, minBit 8, minWin=23, winSum=401
7487 18:02:13.361171 TX Vref=24, minBit 8, minWin=24, winSum=408
7488 18:02:13.368343 TX Vref=26, minBit 8, minWin=24, winSum=411
7489 18:02:13.371337 TX Vref=28, minBit 1, minWin=25, winSum=414
7490 18:02:13.374537 TX Vref=30, minBit 8, minWin=24, winSum=408
7491 18:02:13.378451 TX Vref=32, minBit 6, minWin=24, winSum=399
7492 18:02:13.381143 TX Vref=34, minBit 1, minWin=24, winSum=398
7493 18:02:13.384902 TX Vref=36, minBit 8, minWin=22, winSum=384
7494 18:02:13.391657 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7495 18:02:13.392189
7496 18:02:13.394649 Final TX Range 0 Vref 28
7497 18:02:13.395178
7498 18:02:13.395617 ==
7499 18:02:13.398119 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 18:02:13.401131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7501 18:02:13.401574 ==
7502 18:02:13.402011
7503 18:02:13.404822
7504 18:02:13.405356 TX Vref Scan disable
7505 18:02:13.411150 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7506 18:02:13.411774 == TX Byte 0 ==
7507 18:02:13.414935 u2DelayCellOfst[0]=10 cells (3 PI)
7508 18:02:13.417881 u2DelayCellOfst[1]=14 cells (4 PI)
7509 18:02:13.421330 u2DelayCellOfst[2]=10 cells (3 PI)
7510 18:02:13.424371 u2DelayCellOfst[3]=10 cells (3 PI)
7511 18:02:13.427920 u2DelayCellOfst[4]=3 cells (1 PI)
7512 18:02:13.430892 u2DelayCellOfst[5]=0 cells (0 PI)
7513 18:02:13.434374 u2DelayCellOfst[6]=14 cells (4 PI)
7514 18:02:13.437894 u2DelayCellOfst[7]=14 cells (4 PI)
7515 18:02:13.441035 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7516 18:02:13.444499 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7517 18:02:13.447317 == TX Byte 1 ==
7518 18:02:13.450905 u2DelayCellOfst[8]=3 cells (1 PI)
7519 18:02:13.453934 u2DelayCellOfst[9]=0 cells (0 PI)
7520 18:02:13.457808 u2DelayCellOfst[10]=10 cells (3 PI)
7521 18:02:13.461144 u2DelayCellOfst[11]=7 cells (2 PI)
7522 18:02:13.461658 u2DelayCellOfst[12]=14 cells (4 PI)
7523 18:02:13.464095 u2DelayCellOfst[13]=18 cells (5 PI)
7524 18:02:13.467809 u2DelayCellOfst[14]=21 cells (6 PI)
7525 18:02:13.470687 u2DelayCellOfst[15]=18 cells (5 PI)
7526 18:02:13.477227 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7527 18:02:13.480834 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7528 18:02:13.481246 DramC Write-DBI on
7529 18:02:13.484045 ==
7530 18:02:13.487176 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 18:02:13.490322 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7532 18:02:13.490725 ==
7533 18:02:13.491120
7534 18:02:13.491486
7535 18:02:13.493767 TX Vref Scan disable
7536 18:02:13.494161 == TX Byte 0 ==
7537 18:02:13.500630 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7538 18:02:13.501031 == TX Byte 1 ==
7539 18:02:13.503511 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7540 18:02:13.507018 DramC Write-DBI off
7541 18:02:13.507416
7542 18:02:13.507804 [DATLAT]
7543 18:02:13.510662 Freq=1600, CH0 RK0
7544 18:02:13.511263
7545 18:02:13.511671 DATLAT Default: 0xf
7546 18:02:13.513848 0, 0xFFFF, sum = 0
7547 18:02:13.514278 1, 0xFFFF, sum = 0
7548 18:02:13.516921 2, 0xFFFF, sum = 0
7549 18:02:13.517323 3, 0xFFFF, sum = 0
7550 18:02:13.520631 4, 0xFFFF, sum = 0
7551 18:02:13.521035 5, 0xFFFF, sum = 0
7552 18:02:13.523674 6, 0xFFFF, sum = 0
7553 18:02:13.524075 7, 0xFFFF, sum = 0
7554 18:02:13.526668 8, 0xFFFF, sum = 0
7555 18:02:13.530451 9, 0xFFFF, sum = 0
7556 18:02:13.530979 10, 0xFFFF, sum = 0
7557 18:02:13.533535 11, 0xFFFF, sum = 0
7558 18:02:13.534063 12, 0x8BFF, sum = 0
7559 18:02:13.537046 13, 0x0, sum = 1
7560 18:02:13.537572 14, 0x0, sum = 2
7561 18:02:13.540030 15, 0x0, sum = 3
7562 18:02:13.540420 16, 0x0, sum = 4
7563 18:02:13.540744 best_step = 14
7564 18:02:13.543181
7565 18:02:13.543563 ==
7566 18:02:13.546637 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 18:02:13.549982 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7568 18:02:13.550429 ==
7569 18:02:13.550901 RX Vref Scan: 1
7570 18:02:13.551361
7571 18:02:13.553494 Set Vref Range= 24 -> 127
7572 18:02:13.554022
7573 18:02:13.556860 RX Vref 24 -> 127, step: 1
7574 18:02:13.557325
7575 18:02:13.559703 RX Delay 11 -> 252, step: 4
7576 18:02:13.560089
7577 18:02:13.563355 Set Vref, RX VrefLevel [Byte0]: 24
7578 18:02:13.566755 [Byte1]: 24
7579 18:02:13.567143
7580 18:02:13.570047 Set Vref, RX VrefLevel [Byte0]: 25
7581 18:02:13.573605 [Byte1]: 25
7582 18:02:13.574042
7583 18:02:13.576656 Set Vref, RX VrefLevel [Byte0]: 26
7584 18:02:13.579438 [Byte1]: 26
7585 18:02:13.583694
7586 18:02:13.584156 Set Vref, RX VrefLevel [Byte0]: 27
7587 18:02:13.587496 [Byte1]: 27
7588 18:02:13.591337
7589 18:02:13.591727 Set Vref, RX VrefLevel [Byte0]: 28
7590 18:02:13.594347 [Byte1]: 28
7591 18:02:13.598744
7592 18:02:13.599133 Set Vref, RX VrefLevel [Byte0]: 29
7593 18:02:13.601824 [Byte1]: 29
7594 18:02:13.606468
7595 18:02:13.606901 Set Vref, RX VrefLevel [Byte0]: 30
7596 18:02:13.609411 [Byte1]: 30
7597 18:02:13.614156
7598 18:02:13.614588 Set Vref, RX VrefLevel [Byte0]: 31
7599 18:02:13.617303 [Byte1]: 31
7600 18:02:13.621535
7601 18:02:13.621920 Set Vref, RX VrefLevel [Byte0]: 32
7602 18:02:13.624871 [Byte1]: 32
7603 18:02:13.629282
7604 18:02:13.629746 Set Vref, RX VrefLevel [Byte0]: 33
7605 18:02:13.632182 [Byte1]: 33
7606 18:02:13.636872
7607 18:02:13.637258 Set Vref, RX VrefLevel [Byte0]: 34
7608 18:02:13.640295 [Byte1]: 34
7609 18:02:13.645158
7610 18:02:13.645627 Set Vref, RX VrefLevel [Byte0]: 35
7611 18:02:13.648103 [Byte1]: 35
7612 18:02:13.651992
7613 18:02:13.652382 Set Vref, RX VrefLevel [Byte0]: 36
7614 18:02:13.655396 [Byte1]: 36
7615 18:02:13.659926
7616 18:02:13.660363 Set Vref, RX VrefLevel [Byte0]: 37
7617 18:02:13.662808 [Byte1]: 37
7618 18:02:13.667014
7619 18:02:13.667402 Set Vref, RX VrefLevel [Byte0]: 38
7620 18:02:13.670423 [Byte1]: 38
7621 18:02:13.674909
7622 18:02:13.675296 Set Vref, RX VrefLevel [Byte0]: 39
7623 18:02:13.677928 [Byte1]: 39
7624 18:02:13.682869
7625 18:02:13.683257 Set Vref, RX VrefLevel [Byte0]: 40
7626 18:02:13.685794 [Byte1]: 40
7627 18:02:13.689985
7628 18:02:13.690410 Set Vref, RX VrefLevel [Byte0]: 41
7629 18:02:13.694254 [Byte1]: 41
7630 18:02:13.697617
7631 18:02:13.698068 Set Vref, RX VrefLevel [Byte0]: 42
7632 18:02:13.701270 [Byte1]: 42
7633 18:02:13.705510
7634 18:02:13.705901 Set Vref, RX VrefLevel [Byte0]: 43
7635 18:02:13.708573 [Byte1]: 43
7636 18:02:13.713171
7637 18:02:13.713573 Set Vref, RX VrefLevel [Byte0]: 44
7638 18:02:13.716190 [Byte1]: 44
7639 18:02:13.720266
7640 18:02:13.720874 Set Vref, RX VrefLevel [Byte0]: 45
7641 18:02:13.723927 [Byte1]: 45
7642 18:02:13.727984
7643 18:02:13.728578 Set Vref, RX VrefLevel [Byte0]: 46
7644 18:02:13.731251 [Byte1]: 46
7645 18:02:13.735472
7646 18:02:13.735888 Set Vref, RX VrefLevel [Byte0]: 47
7647 18:02:13.738891 [Byte1]: 47
7648 18:02:13.743342
7649 18:02:13.743706 Set Vref, RX VrefLevel [Byte0]: 48
7650 18:02:13.746712 [Byte1]: 48
7651 18:02:13.751064
7652 18:02:13.751431 Set Vref, RX VrefLevel [Byte0]: 49
7653 18:02:13.754009 [Byte1]: 49
7654 18:02:13.758299
7655 18:02:13.758635 Set Vref, RX VrefLevel [Byte0]: 50
7656 18:02:13.762164 [Byte1]: 50
7657 18:02:13.766180
7658 18:02:13.766485 Set Vref, RX VrefLevel [Byte0]: 51
7659 18:02:13.769315 [Byte1]: 51
7660 18:02:13.774038
7661 18:02:13.774331 Set Vref, RX VrefLevel [Byte0]: 52
7662 18:02:13.776906 [Byte1]: 52
7663 18:02:13.781518
7664 18:02:13.781867 Set Vref, RX VrefLevel [Byte0]: 53
7665 18:02:13.784755 [Byte1]: 53
7666 18:02:13.788738
7667 18:02:13.789067 Set Vref, RX VrefLevel [Byte0]: 54
7668 18:02:13.792206 [Byte1]: 54
7669 18:02:13.796436
7670 18:02:13.796711 Set Vref, RX VrefLevel [Byte0]: 55
7671 18:02:13.799661 [Byte1]: 55
7672 18:02:13.804210
7673 18:02:13.804487 Set Vref, RX VrefLevel [Byte0]: 56
7674 18:02:13.807459 [Byte1]: 56
7675 18:02:13.812023
7676 18:02:13.812589 Set Vref, RX VrefLevel [Byte0]: 57
7677 18:02:13.815419 [Byte1]: 57
7678 18:02:13.819413
7679 18:02:13.819800 Set Vref, RX VrefLevel [Byte0]: 58
7680 18:02:13.822738 [Byte1]: 58
7681 18:02:13.826859
7682 18:02:13.827250 Set Vref, RX VrefLevel [Byte0]: 59
7683 18:02:13.830396 [Byte1]: 59
7684 18:02:13.834839
7685 18:02:13.835230 Set Vref, RX VrefLevel [Byte0]: 60
7686 18:02:13.837874 [Byte1]: 60
7687 18:02:13.842379
7688 18:02:13.842782 Set Vref, RX VrefLevel [Byte0]: 61
7689 18:02:13.846022 [Byte1]: 61
7690 18:02:13.850005
7691 18:02:13.850440 Set Vref, RX VrefLevel [Byte0]: 62
7692 18:02:13.852957 [Byte1]: 62
7693 18:02:13.857800
7694 18:02:13.858195 Set Vref, RX VrefLevel [Byte0]: 63
7695 18:02:13.860817 [Byte1]: 63
7696 18:02:13.865446
7697 18:02:13.865840 Set Vref, RX VrefLevel [Byte0]: 64
7698 18:02:13.868441 [Byte1]: 64
7699 18:02:13.872638
7700 18:02:13.873049 Set Vref, RX VrefLevel [Byte0]: 65
7701 18:02:13.876144 [Byte1]: 65
7702 18:02:13.880723
7703 18:02:13.881116 Set Vref, RX VrefLevel [Byte0]: 66
7704 18:02:13.883693 [Byte1]: 66
7705 18:02:13.887875
7706 18:02:13.888269 Set Vref, RX VrefLevel [Byte0]: 67
7707 18:02:13.891267 [Byte1]: 67
7708 18:02:13.895856
7709 18:02:13.896445 Set Vref, RX VrefLevel [Byte0]: 68
7710 18:02:13.898983 [Byte1]: 68
7711 18:02:13.903343
7712 18:02:13.903740 Set Vref, RX VrefLevel [Byte0]: 69
7713 18:02:13.906800 [Byte1]: 69
7714 18:02:13.911024
7715 18:02:13.911418 Set Vref, RX VrefLevel [Byte0]: 70
7716 18:02:13.913998 [Byte1]: 70
7717 18:02:13.918370
7718 18:02:13.918754 Set Vref, RX VrefLevel [Byte0]: 71
7719 18:02:13.921848 [Byte1]: 71
7720 18:02:13.925921
7721 18:02:13.926346 Set Vref, RX VrefLevel [Byte0]: 72
7722 18:02:13.929406 [Byte1]: 72
7723 18:02:13.933712
7724 18:02:13.934110 Final RX Vref Byte 0 = 54 to rank0
7725 18:02:13.936950 Final RX Vref Byte 1 = 58 to rank0
7726 18:02:13.940469 Final RX Vref Byte 0 = 54 to rank1
7727 18:02:13.943795 Final RX Vref Byte 1 = 58 to rank1==
7728 18:02:13.946739 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 18:02:13.953496 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7730 18:02:13.954020 ==
7731 18:02:13.954452 DQS Delay:
7732 18:02:13.956875 DQS0 = 0, DQS1 = 0
7733 18:02:13.957394 DQM Delay:
7734 18:02:13.957738 DQM0 = 126, DQM1 = 120
7735 18:02:13.959761 DQ Delay:
7736 18:02:13.963328 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7737 18:02:13.966531 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7738 18:02:13.970024 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7739 18:02:13.973578 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7740 18:02:13.973996
7741 18:02:13.974457
7742 18:02:13.974752
7743 18:02:13.976647 [DramC_TX_OE_Calibration] TA2
7744 18:02:13.980156 Original DQ_B0 (3 6) =30, OEN = 27
7745 18:02:13.983184 Original DQ_B1 (3 6) =30, OEN = 27
7746 18:02:13.986900 24, 0x0, End_B0=24 End_B1=24
7747 18:02:13.987286 25, 0x0, End_B0=25 End_B1=25
7748 18:02:13.990022 26, 0x0, End_B0=26 End_B1=26
7749 18:02:13.993134 27, 0x0, End_B0=27 End_B1=27
7750 18:02:13.996383 28, 0x0, End_B0=28 End_B1=28
7751 18:02:14.000347 29, 0x0, End_B0=29 End_B1=29
7752 18:02:14.000829 30, 0x0, End_B0=30 End_B1=30
7753 18:02:14.003365 31, 0x4141, End_B0=30 End_B1=30
7754 18:02:14.006377 Byte0 end_step=30 best_step=27
7755 18:02:14.009912 Byte1 end_step=30 best_step=27
7756 18:02:14.012905 Byte0 TX OE(2T, 0.5T) = (3, 3)
7757 18:02:14.016465 Byte1 TX OE(2T, 0.5T) = (3, 3)
7758 18:02:14.016850
7759 18:02:14.017149
7760 18:02:14.022996 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7761 18:02:14.026330 CH0 RK0: MR19=303, MR18=1B1B
7762 18:02:14.033142 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7763 18:02:14.033530
7764 18:02:14.036069 ----->DramcWriteLeveling(PI) begin...
7765 18:02:14.036462 ==
7766 18:02:14.039479 Dram Type= 6, Freq= 0, CH_0, rank 1
7767 18:02:14.043081 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7768 18:02:14.043552 ==
7769 18:02:14.046755 Write leveling (Byte 0): 29 => 29
7770 18:02:14.049699 Write leveling (Byte 1): 25 => 25
7771 18:02:14.052685 DramcWriteLeveling(PI) end<-----
7772 18:02:14.053071
7773 18:02:14.053371 ==
7774 18:02:14.056271 Dram Type= 6, Freq= 0, CH_0, rank 1
7775 18:02:14.059557 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7776 18:02:14.060060 ==
7777 18:02:14.062941 [Gating] SW mode calibration
7778 18:02:14.069448 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7779 18:02:14.075864 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7780 18:02:14.079417 0 12 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7781 18:02:14.086278 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7782 18:02:14.089114 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7783 18:02:14.092617 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7784 18:02:14.098922 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 18:02:14.102315 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 18:02:14.105604 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7787 18:02:14.112692 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7788 18:02:14.115409 0 13 0 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
7789 18:02:14.119176 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7790 18:02:14.125637 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7791 18:02:14.128755 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7792 18:02:14.132250 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7793 18:02:14.138733 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 18:02:14.142421 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 18:02:14.145470 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7796 18:02:14.152289 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
7797 18:02:14.155676 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7798 18:02:14.158850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7799 18:02:14.161806 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7800 18:02:14.168992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 18:02:14.172268 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 18:02:14.175220 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 18:02:14.182200 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7804 18:02:14.185716 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7805 18:02:14.188495 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7806 18:02:14.194996 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7807 18:02:14.198734 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7808 18:02:14.201622 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7809 18:02:14.208558 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 18:02:14.211835 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 18:02:14.214799 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 18:02:14.221534 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 18:02:14.225139 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 18:02:14.228092 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 18:02:14.234810 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 18:02:14.238399 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 18:02:14.241439 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 18:02:14.247967 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 18:02:14.251493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7820 18:02:14.254846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7821 18:02:14.261391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7822 18:02:14.261806 Total UI for P1: 0, mck2ui 16
7823 18:02:14.267932 best dqsien dly found for B0: ( 1, 0, 30)
7824 18:02:14.271397 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7825 18:02:14.274979 Total UI for P1: 0, mck2ui 16
7826 18:02:14.277910 best dqsien dly found for B1: ( 1, 1, 2)
7827 18:02:14.281467 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7828 18:02:14.284871 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7829 18:02:14.285258
7830 18:02:14.287782 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7831 18:02:14.291323 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7832 18:02:14.294397 [Gating] SW calibration Done
7833 18:02:14.294788 ==
7834 18:02:14.297933 Dram Type= 6, Freq= 0, CH_0, rank 1
7835 18:02:14.300976 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7836 18:02:14.304174 ==
7837 18:02:14.304561 RX Vref Scan: 0
7838 18:02:14.304861
7839 18:02:14.307599 RX Vref 0 -> 0, step: 1
7840 18:02:14.307993
7841 18:02:14.311070 RX Delay 0 -> 252, step: 8
7842 18:02:14.314139 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7843 18:02:14.317788 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7844 18:02:14.320705 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7845 18:02:14.323914 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7846 18:02:14.331324 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7847 18:02:14.333753 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7848 18:02:14.337451 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7849 18:02:14.340700 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7850 18:02:14.343992 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7851 18:02:14.350707 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7852 18:02:14.354547 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7853 18:02:14.356987 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7854 18:02:14.360681 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7855 18:02:14.364334 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7856 18:02:14.370160 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7857 18:02:14.373702 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7858 18:02:14.374141 ==
7859 18:02:14.377165 Dram Type= 6, Freq= 0, CH_0, rank 1
7860 18:02:14.380315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7861 18:02:14.380836 ==
7862 18:02:14.383670 DQS Delay:
7863 18:02:14.384180 DQS0 = 0, DQS1 = 0
7864 18:02:14.384480 DQM Delay:
7865 18:02:14.386835 DQM0 = 130, DQM1 = 123
7866 18:02:14.387217 DQ Delay:
7867 18:02:14.390146 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7868 18:02:14.393727 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7869 18:02:14.400033 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7870 18:02:14.403473 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7871 18:02:14.403860
7872 18:02:14.404157
7873 18:02:14.404432 ==
7874 18:02:14.406400 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 18:02:14.410119 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 18:02:14.410658 ==
7877 18:02:14.410973
7878 18:02:14.411251
7879 18:02:14.413391 TX Vref Scan disable
7880 18:02:14.416429 == TX Byte 0 ==
7881 18:02:14.419978 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7882 18:02:14.423083 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7883 18:02:14.426874 == TX Byte 1 ==
7884 18:02:14.429616 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7885 18:02:14.433265 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7886 18:02:14.433673 ==
7887 18:02:14.436443 Dram Type= 6, Freq= 0, CH_0, rank 1
7888 18:02:14.439919 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7889 18:02:14.443149 ==
7890 18:02:14.454588
7891 18:02:14.457484 TX Vref early break, caculate TX vref
7892 18:02:14.461151 TX Vref=16, minBit 8, minWin=22, winSum=373
7893 18:02:14.464579 TX Vref=18, minBit 10, minWin=22, winSum=379
7894 18:02:14.468123 TX Vref=20, minBit 1, minWin=23, winSum=387
7895 18:02:14.471110 TX Vref=22, minBit 9, minWin=23, winSum=395
7896 18:02:14.474502 TX Vref=24, minBit 8, minWin=24, winSum=405
7897 18:02:14.480780 TX Vref=26, minBit 8, minWin=24, winSum=408
7898 18:02:14.483783 TX Vref=28, minBit 8, minWin=24, winSum=415
7899 18:02:14.487475 TX Vref=30, minBit 1, minWin=25, winSum=412
7900 18:02:14.490880 TX Vref=32, minBit 7, minWin=24, winSum=402
7901 18:02:14.494399 TX Vref=34, minBit 1, minWin=23, winSum=393
7902 18:02:14.500780 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 30
7903 18:02:14.501278
7904 18:02:14.503870 Final TX Range 0 Vref 30
7905 18:02:14.504303
7906 18:02:14.504632 ==
7907 18:02:14.507207 Dram Type= 6, Freq= 0, CH_0, rank 1
7908 18:02:14.510722 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7909 18:02:14.511149 ==
7910 18:02:14.511482
7911 18:02:14.511782
7912 18:02:14.513736 TX Vref Scan disable
7913 18:02:14.520665 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7914 18:02:14.521050 == TX Byte 0 ==
7915 18:02:14.524169 u2DelayCellOfst[0]=10 cells (3 PI)
7916 18:02:14.527212 u2DelayCellOfst[1]=18 cells (5 PI)
7917 18:02:14.530330 u2DelayCellOfst[2]=14 cells (4 PI)
7918 18:02:14.533877 u2DelayCellOfst[3]=14 cells (4 PI)
7919 18:02:14.536868 u2DelayCellOfst[4]=10 cells (3 PI)
7920 18:02:14.540611 u2DelayCellOfst[5]=0 cells (0 PI)
7921 18:02:14.543917 u2DelayCellOfst[6]=21 cells (6 PI)
7922 18:02:14.547625 u2DelayCellOfst[7]=18 cells (5 PI)
7923 18:02:14.550308 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7924 18:02:14.553744 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7925 18:02:14.557020 == TX Byte 1 ==
7926 18:02:14.560131 u2DelayCellOfst[8]=3 cells (1 PI)
7927 18:02:14.563930 u2DelayCellOfst[9]=0 cells (0 PI)
7928 18:02:14.564425 u2DelayCellOfst[10]=14 cells (4 PI)
7929 18:02:14.567149 u2DelayCellOfst[11]=3 cells (1 PI)
7930 18:02:14.570182 u2DelayCellOfst[12]=14 cells (4 PI)
7931 18:02:14.573647 u2DelayCellOfst[13]=18 cells (5 PI)
7932 18:02:14.577028 u2DelayCellOfst[14]=18 cells (5 PI)
7933 18:02:14.580185 u2DelayCellOfst[15]=18 cells (5 PI)
7934 18:02:14.586591 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7935 18:02:14.590235 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7936 18:02:14.590629 DramC Write-DBI on
7937 18:02:14.590926 ==
7938 18:02:14.593319 Dram Type= 6, Freq= 0, CH_0, rank 1
7939 18:02:14.599720 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7940 18:02:14.599998 ==
7941 18:02:14.600209
7942 18:02:14.600411
7943 18:02:14.600550 TX Vref Scan disable
7944 18:02:14.603995 == TX Byte 0 ==
7945 18:02:14.607081 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7946 18:02:14.610615 == TX Byte 1 ==
7947 18:02:14.613905 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7948 18:02:14.617320 DramC Write-DBI off
7949 18:02:14.617524
7950 18:02:14.617682 [DATLAT]
7951 18:02:14.617827 Freq=1600, CH0 RK1
7952 18:02:14.617970
7953 18:02:14.621047 DATLAT Default: 0xe
7954 18:02:14.621347 0, 0xFFFF, sum = 0
7955 18:02:14.623936 1, 0xFFFF, sum = 0
7956 18:02:14.627440 2, 0xFFFF, sum = 0
7957 18:02:14.627724 3, 0xFFFF, sum = 0
7958 18:02:14.630317 4, 0xFFFF, sum = 0
7959 18:02:14.630565 5, 0xFFFF, sum = 0
7960 18:02:14.633633 6, 0xFFFF, sum = 0
7961 18:02:14.633876 7, 0xFFFF, sum = 0
7962 18:02:14.637208 8, 0xFFFF, sum = 0
7963 18:02:14.637462 9, 0xFFFF, sum = 0
7964 18:02:14.640500 10, 0xFFFF, sum = 0
7965 18:02:14.640912 11, 0xFFFF, sum = 0
7966 18:02:14.644161 12, 0x8FFF, sum = 0
7967 18:02:14.644587 13, 0x0, sum = 1
7968 18:02:14.647463 14, 0x0, sum = 2
7969 18:02:14.647861 15, 0x0, sum = 3
7970 18:02:14.650502 16, 0x0, sum = 4
7971 18:02:14.650859 best_step = 14
7972 18:02:14.651109
7973 18:02:14.651338 ==
7974 18:02:14.653962 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 18:02:14.657162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7976 18:02:14.660544 ==
7977 18:02:14.660872 RX Vref Scan: 0
7978 18:02:14.661127
7979 18:02:14.663923 RX Vref 0 -> 0, step: 1
7980 18:02:14.664351
7981 18:02:14.664611 RX Delay 11 -> 252, step: 4
7982 18:02:14.670920 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7983 18:02:14.674570 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
7984 18:02:14.677898 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7985 18:02:14.681474 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7986 18:02:14.684392 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7987 18:02:14.690825 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7988 18:02:14.694297 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7989 18:02:14.697925 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7990 18:02:14.700991 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7991 18:02:14.703991 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7992 18:02:14.710767 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7993 18:02:14.714160 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7994 18:02:14.717102 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7995 18:02:14.720738 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7996 18:02:14.727587 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7997 18:02:14.730664 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7998 18:02:14.730958 ==
7999 18:02:14.733809 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 18:02:14.737684 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8001 18:02:14.738076 ==
8002 18:02:14.740492 DQS Delay:
8003 18:02:14.740868 DQS0 = 0, DQS1 = 0
8004 18:02:14.741098 DQM Delay:
8005 18:02:14.744203 DQM0 = 127, DQM1 = 120
8006 18:02:14.744589 DQ Delay:
8007 18:02:14.747101 DQ0 =122, DQ1 =128, DQ2 =126, DQ3 =122
8008 18:02:14.750596 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8009 18:02:14.756898 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8010 18:02:14.760379 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8011 18:02:14.760842
8012 18:02:14.761151
8013 18:02:14.761424
8014 18:02:14.763504 [DramC_TX_OE_Calibration] TA2
8015 18:02:14.766942 Original DQ_B0 (3 6) =30, OEN = 27
8016 18:02:14.770280 Original DQ_B1 (3 6) =30, OEN = 27
8017 18:02:14.770674 24, 0x0, End_B0=24 End_B1=24
8018 18:02:14.773805 25, 0x0, End_B0=25 End_B1=25
8019 18:02:14.776806 26, 0x0, End_B0=26 End_B1=26
8020 18:02:14.779887 27, 0x0, End_B0=27 End_B1=27
8021 18:02:14.780376 28, 0x0, End_B0=28 End_B1=28
8022 18:02:14.783186 29, 0x0, End_B0=29 End_B1=29
8023 18:02:14.787183 30, 0x0, End_B0=30 End_B1=30
8024 18:02:14.789874 31, 0x4141, End_B0=30 End_B1=30
8025 18:02:14.793346 Byte0 end_step=30 best_step=27
8026 18:02:14.796323 Byte1 end_step=30 best_step=27
8027 18:02:14.796752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8028 18:02:14.800259 Byte1 TX OE(2T, 0.5T) = (3, 3)
8029 18:02:14.800790
8030 18:02:14.801123
8031 18:02:14.809640 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8032 18:02:14.813261 CH0 RK1: MR19=303, MR18=1F1F
8033 18:02:14.816307 CH0_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8034 18:02:14.819843 [RxdqsGatingPostProcess] freq 1600
8035 18:02:14.826626 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8036 18:02:14.829591 Pre-setting of DQS Precalculation
8037 18:02:14.832668 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8038 18:02:14.836049 ==
8039 18:02:14.839785 Dram Type= 6, Freq= 0, CH_1, rank 0
8040 18:02:14.843248 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8041 18:02:14.843634 ==
8042 18:02:14.845903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8043 18:02:14.852631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8044 18:02:14.856090 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8045 18:02:14.862533 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8046 18:02:14.870517 [CA 0] Center 41 (11~71) winsize 61
8047 18:02:14.873784 [CA 1] Center 41 (11~72) winsize 62
8048 18:02:14.876904 [CA 2] Center 37 (7~67) winsize 61
8049 18:02:14.879968 [CA 3] Center 36 (7~66) winsize 60
8050 18:02:14.883850 [CA 4] Center 34 (4~64) winsize 61
8051 18:02:14.886332 [CA 5] Center 34 (4~64) winsize 61
8052 18:02:14.886762
8053 18:02:14.890192 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8054 18:02:14.890742
8055 18:02:14.896510 [CATrainingPosCal] consider 1 rank data
8056 18:02:14.897162 u2DelayCellTimex100 = 271/100 ps
8057 18:02:14.902907 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8058 18:02:14.906887 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8059 18:02:14.909820 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8060 18:02:14.913132 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8061 18:02:14.916141 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8062 18:02:14.919926 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8063 18:02:14.920427
8064 18:02:14.922805 CA PerBit enable=1, Macro0, CA PI delay=34
8065 18:02:14.923228
8066 18:02:14.926381 [CBTSetCACLKResult] CA Dly = 34
8067 18:02:14.929335 CS Dly: 8 (0~39)
8068 18:02:14.933185 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8069 18:02:14.935886 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8070 18:02:14.936309 ==
8071 18:02:14.939363 Dram Type= 6, Freq= 0, CH_1, rank 1
8072 18:02:14.945858 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8073 18:02:14.946311 ==
8074 18:02:14.949548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8075 18:02:14.956010 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8076 18:02:14.959417 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8077 18:02:14.966030 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8078 18:02:14.972591 [CA 0] Center 41 (11~71) winsize 61
8079 18:02:14.976058 [CA 1] Center 40 (10~71) winsize 62
8080 18:02:14.979210 [CA 2] Center 36 (7~66) winsize 60
8081 18:02:14.982586 [CA 3] Center 35 (6~65) winsize 60
8082 18:02:14.985744 [CA 4] Center 34 (4~64) winsize 61
8083 18:02:14.989455 [CA 5] Center 34 (4~64) winsize 61
8084 18:02:14.989975
8085 18:02:14.992401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8086 18:02:14.992901
8087 18:02:14.995805 [CATrainingPosCal] consider 2 rank data
8088 18:02:14.998844 u2DelayCellTimex100 = 271/100 ps
8089 18:02:15.005905 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8090 18:02:15.008996 CA1 delay=41 (11~71),Diff = 7 PI (25 cell)
8091 18:02:15.011905 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8092 18:02:15.015505 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8093 18:02:15.018703 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8094 18:02:15.022273 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8095 18:02:15.022670
8096 18:02:15.025130 CA PerBit enable=1, Macro0, CA PI delay=34
8097 18:02:15.025520
8098 18:02:15.028909 [CBTSetCACLKResult] CA Dly = 34
8099 18:02:15.031813 CS Dly: 9 (0~41)
8100 18:02:15.035719 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8101 18:02:15.038633 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8102 18:02:15.039024
8103 18:02:15.042258 ----->DramcWriteLeveling(PI) begin...
8104 18:02:15.042657 ==
8105 18:02:15.045486 Dram Type= 6, Freq= 0, CH_1, rank 0
8106 18:02:15.051779 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8107 18:02:15.052174 ==
8108 18:02:15.055609 Write leveling (Byte 0): 22 => 22
8109 18:02:15.056016 Write leveling (Byte 1): 21 => 21
8110 18:02:15.058621 DramcWriteLeveling(PI) end<-----
8111 18:02:15.059097
8112 18:02:15.061794 ==
8113 18:02:15.062404 Dram Type= 6, Freq= 0, CH_1, rank 0
8114 18:02:15.068293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8115 18:02:15.068686 ==
8116 18:02:15.071609 [Gating] SW mode calibration
8117 18:02:15.078123 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8118 18:02:15.081369 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8119 18:02:15.087964 0 12 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8120 18:02:15.091725 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 18:02:15.094491 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 18:02:15.101345 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 18:02:15.104612 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 18:02:15.107714 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 18:02:15.114375 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 18:02:15.117731 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8127 18:02:15.121280 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8128 18:02:15.127856 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8129 18:02:15.131006 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 18:02:15.133990 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 18:02:15.141035 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 18:02:15.144054 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 18:02:15.147695 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 18:02:15.154252 0 13 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8135 18:02:15.157601 0 14 0 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8136 18:02:15.160724 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 18:02:15.167629 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 18:02:15.170575 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 18:02:15.174375 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 18:02:15.180640 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 18:02:15.184068 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 18:02:15.187243 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 18:02:15.193827 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 18:02:15.197187 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8145 18:02:15.200694 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 18:02:15.207210 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 18:02:15.210535 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 18:02:15.213960 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 18:02:15.220086 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 18:02:15.223916 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 18:02:15.227177 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 18:02:15.233789 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 18:02:15.236895 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 18:02:15.240536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 18:02:15.246578 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 18:02:15.250180 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 18:02:15.253412 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8158 18:02:15.259832 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 18:02:15.263550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8160 18:02:15.266566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8161 18:02:15.270080 Total UI for P1: 0, mck2ui 16
8162 18:02:15.273181 best dqsien dly found for B0: ( 1, 0, 28)
8163 18:02:15.280089 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8164 18:02:15.280601 Total UI for P1: 0, mck2ui 16
8165 18:02:15.283119 best dqsien dly found for B1: ( 1, 1, 2)
8166 18:02:15.289818 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8167 18:02:15.293185 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8168 18:02:15.293575
8169 18:02:15.296319 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8170 18:02:15.299588 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8171 18:02:15.302739 [Gating] SW calibration Done
8172 18:02:15.303132 ==
8173 18:02:15.306420 Dram Type= 6, Freq= 0, CH_1, rank 0
8174 18:02:15.310143 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8175 18:02:15.310700 ==
8176 18:02:15.312888 RX Vref Scan: 0
8177 18:02:15.313319
8178 18:02:15.313653 RX Vref 0 -> 0, step: 1
8179 18:02:15.313963
8180 18:02:15.316196 RX Delay 0 -> 252, step: 8
8181 18:02:15.319716 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8182 18:02:15.323283 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8183 18:02:15.329772 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8184 18:02:15.333050 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8185 18:02:15.336264 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8186 18:02:15.339286 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8187 18:02:15.342874 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8188 18:02:15.349576 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8189 18:02:15.352396 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8190 18:02:15.355947 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8191 18:02:15.359609 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8192 18:02:15.362956 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8193 18:02:15.369359 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8194 18:02:15.372695 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8195 18:02:15.375920 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8196 18:02:15.379306 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8197 18:02:15.382259 ==
8198 18:02:15.382681 Dram Type= 6, Freq= 0, CH_1, rank 0
8199 18:02:15.389241 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8200 18:02:15.389791 ==
8201 18:02:15.390293 DQS Delay:
8202 18:02:15.392559 DQS0 = 0, DQS1 = 0
8203 18:02:15.392980 DQM Delay:
8204 18:02:15.396056 DQM0 = 130, DQM1 = 125
8205 18:02:15.396607 DQ Delay:
8206 18:02:15.399187 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8207 18:02:15.402609 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8208 18:02:15.405699 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8209 18:02:15.409064 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8210 18:02:15.409579
8211 18:02:15.409913
8212 18:02:15.410242 ==
8213 18:02:15.412041 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 18:02:15.418688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 18:02:15.419192 ==
8216 18:02:15.419530
8217 18:02:15.419835
8218 18:02:15.420133 TX Vref Scan disable
8219 18:02:15.422438 == TX Byte 0 ==
8220 18:02:15.425823 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8221 18:02:15.432176 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8222 18:02:15.432611 == TX Byte 1 ==
8223 18:02:15.435349 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8224 18:02:15.442057 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8225 18:02:15.442591 ==
8226 18:02:15.445307 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 18:02:15.448567 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8228 18:02:15.449001 ==
8229 18:02:15.462208
8230 18:02:15.465479 TX Vref early break, caculate TX vref
8231 18:02:15.468576 TX Vref=16, minBit 0, minWin=21, winSum=366
8232 18:02:15.472139 TX Vref=18, minBit 3, minWin=21, winSum=373
8233 18:02:15.474800 TX Vref=20, minBit 0, minWin=22, winSum=386
8234 18:02:15.478607 TX Vref=22, minBit 3, minWin=23, winSum=396
8235 18:02:15.481826 TX Vref=24, minBit 3, minWin=23, winSum=402
8236 18:02:15.488442 TX Vref=26, minBit 1, minWin=24, winSum=411
8237 18:02:15.491970 TX Vref=28, minBit 3, minWin=23, winSum=410
8238 18:02:15.494942 TX Vref=30, minBit 3, minWin=23, winSum=406
8239 18:02:15.498140 TX Vref=32, minBit 3, minWin=23, winSum=397
8240 18:02:15.501623 TX Vref=34, minBit 1, minWin=23, winSum=392
8241 18:02:15.504578 TX Vref=36, minBit 1, minWin=22, winSum=378
8242 18:02:15.511244 [TxChooseVref] Worse bit 1, Min win 24, Win sum 411, Final Vref 26
8243 18:02:15.511740
8244 18:02:15.514502 Final TX Range 0 Vref 26
8245 18:02:15.514933
8246 18:02:15.515266 ==
8247 18:02:15.518588 Dram Type= 6, Freq= 0, CH_1, rank 0
8248 18:02:15.521376 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8249 18:02:15.521834 ==
8250 18:02:15.522170
8251 18:02:15.522534
8252 18:02:15.524521 TX Vref Scan disable
8253 18:02:15.531238 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8254 18:02:15.531673 == TX Byte 0 ==
8255 18:02:15.534670 u2DelayCellOfst[0]=14 cells (4 PI)
8256 18:02:15.537852 u2DelayCellOfst[1]=7 cells (2 PI)
8257 18:02:15.541274 u2DelayCellOfst[2]=0 cells (0 PI)
8258 18:02:15.545000 u2DelayCellOfst[3]=3 cells (1 PI)
8259 18:02:15.548325 u2DelayCellOfst[4]=7 cells (2 PI)
8260 18:02:15.551579 u2DelayCellOfst[5]=14 cells (4 PI)
8261 18:02:15.554292 u2DelayCellOfst[6]=14 cells (4 PI)
8262 18:02:15.557962 u2DelayCellOfst[7]=3 cells (1 PI)
8263 18:02:15.561372 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8264 18:02:15.564703 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8265 18:02:15.568208 == TX Byte 1 ==
8266 18:02:15.568708 u2DelayCellOfst[8]=0 cells (0 PI)
8267 18:02:15.571512 u2DelayCellOfst[9]=3 cells (1 PI)
8268 18:02:15.574657 u2DelayCellOfst[10]=7 cells (2 PI)
8269 18:02:15.577993 u2DelayCellOfst[11]=3 cells (1 PI)
8270 18:02:15.581282 u2DelayCellOfst[12]=14 cells (4 PI)
8271 18:02:15.584955 u2DelayCellOfst[13]=18 cells (5 PI)
8272 18:02:15.587692 u2DelayCellOfst[14]=18 cells (5 PI)
8273 18:02:15.591137 u2DelayCellOfst[15]=14 cells (4 PI)
8274 18:02:15.594568 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8275 18:02:15.600761 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8276 18:02:15.601259 DramC Write-DBI on
8277 18:02:15.601594 ==
8278 18:02:15.604166 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 18:02:15.610668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8280 18:02:15.611113 ==
8281 18:02:15.611442
8282 18:02:15.611743
8283 18:02:15.612036 TX Vref Scan disable
8284 18:02:15.614960 == TX Byte 0 ==
8285 18:02:15.617890 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8286 18:02:15.621330 == TX Byte 1 ==
8287 18:02:15.624375 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8288 18:02:15.627844 DramC Write-DBI off
8289 18:02:15.628276
8290 18:02:15.628664 [DATLAT]
8291 18:02:15.628976 Freq=1600, CH1 RK0
8292 18:02:15.629273
8293 18:02:15.630992 DATLAT Default: 0xf
8294 18:02:15.631419 0, 0xFFFF, sum = 0
8295 18:02:15.634390 1, 0xFFFF, sum = 0
8296 18:02:15.634956 2, 0xFFFF, sum = 0
8297 18:02:15.637696 3, 0xFFFF, sum = 0
8298 18:02:15.641407 4, 0xFFFF, sum = 0
8299 18:02:15.641801 5, 0xFFFF, sum = 0
8300 18:02:15.644427 6, 0xFFFF, sum = 0
8301 18:02:15.644922 7, 0xFFFF, sum = 0
8302 18:02:15.647948 8, 0xFFFF, sum = 0
8303 18:02:15.648399 9, 0xFFFF, sum = 0
8304 18:02:15.651145 10, 0xFFFF, sum = 0
8305 18:02:15.651540 11, 0xFFFF, sum = 0
8306 18:02:15.654449 12, 0xFFF, sum = 0
8307 18:02:15.654848 13, 0x0, sum = 1
8308 18:02:15.657690 14, 0x0, sum = 2
8309 18:02:15.658082 15, 0x0, sum = 3
8310 18:02:15.660896 16, 0x0, sum = 4
8311 18:02:15.661295 best_step = 14
8312 18:02:15.661594
8313 18:02:15.661869 ==
8314 18:02:15.664678 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 18:02:15.667702 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8316 18:02:15.670958 ==
8317 18:02:15.671346 RX Vref Scan: 1
8318 18:02:15.671649
8319 18:02:15.674138 Set Vref Range= 24 -> 127
8320 18:02:15.674557
8321 18:02:15.677695 RX Vref 24 -> 127, step: 1
8322 18:02:15.678083
8323 18:02:15.678419 RX Delay 3 -> 252, step: 4
8324 18:02:15.678704
8325 18:02:15.680705 Set Vref, RX VrefLevel [Byte0]: 24
8326 18:02:15.684665 [Byte1]: 24
8327 18:02:15.688350
8328 18:02:15.688814 Set Vref, RX VrefLevel [Byte0]: 25
8329 18:02:15.690921 [Byte1]: 25
8330 18:02:15.695115
8331 18:02:15.695503 Set Vref, RX VrefLevel [Byte0]: 26
8332 18:02:15.699143 [Byte1]: 26
8333 18:02:15.703141
8334 18:02:15.703604 Set Vref, RX VrefLevel [Byte0]: 27
8335 18:02:15.706111 [Byte1]: 27
8336 18:02:15.710800
8337 18:02:15.711199 Set Vref, RX VrefLevel [Byte0]: 28
8338 18:02:15.713884 [Byte1]: 28
8339 18:02:15.718601
8340 18:02:15.719064 Set Vref, RX VrefLevel [Byte0]: 29
8341 18:02:15.721440 [Byte1]: 29
8342 18:02:15.725673
8343 18:02:15.726099 Set Vref, RX VrefLevel [Byte0]: 30
8344 18:02:15.729258 [Byte1]: 30
8345 18:02:15.733307
8346 18:02:15.733735 Set Vref, RX VrefLevel [Byte0]: 31
8347 18:02:15.737490 [Byte1]: 31
8348 18:02:15.741556
8349 18:02:15.741990 Set Vref, RX VrefLevel [Byte0]: 32
8350 18:02:15.744971 [Byte1]: 32
8351 18:02:15.749221
8352 18:02:15.749651 Set Vref, RX VrefLevel [Byte0]: 33
8353 18:02:15.752066 [Byte1]: 33
8354 18:02:15.756824
8355 18:02:15.757396 Set Vref, RX VrefLevel [Byte0]: 34
8356 18:02:15.760122 [Byte1]: 34
8357 18:02:15.764635
8358 18:02:15.765140 Set Vref, RX VrefLevel [Byte0]: 35
8359 18:02:15.767991 [Byte1]: 35
8360 18:02:15.771760
8361 18:02:15.772188 Set Vref, RX VrefLevel [Byte0]: 36
8362 18:02:15.775320 [Byte1]: 36
8363 18:02:15.779484
8364 18:02:15.779908 Set Vref, RX VrefLevel [Byte0]: 37
8365 18:02:15.782647 [Byte1]: 37
8366 18:02:15.787202
8367 18:02:15.787585 Set Vref, RX VrefLevel [Byte0]: 38
8368 18:02:15.790167 [Byte1]: 38
8369 18:02:15.795100
8370 18:02:15.795547 Set Vref, RX VrefLevel [Byte0]: 39
8371 18:02:15.798090 [Byte1]: 39
8372 18:02:15.803168
8373 18:02:15.803628 Set Vref, RX VrefLevel [Byte0]: 40
8374 18:02:15.805770 [Byte1]: 40
8375 18:02:15.809999
8376 18:02:15.810414 Set Vref, RX VrefLevel [Byte0]: 41
8377 18:02:15.813424 [Byte1]: 41
8378 18:02:15.818336
8379 18:02:15.818799 Set Vref, RX VrefLevel [Byte0]: 42
8380 18:02:15.821457 [Byte1]: 42
8381 18:02:15.825452
8382 18:02:15.826025 Set Vref, RX VrefLevel [Byte0]: 43
8383 18:02:15.829006 [Byte1]: 43
8384 18:02:15.833138
8385 18:02:15.833520 Set Vref, RX VrefLevel [Byte0]: 44
8386 18:02:15.836629 [Byte1]: 44
8387 18:02:15.840762
8388 18:02:15.841145 Set Vref, RX VrefLevel [Byte0]: 45
8389 18:02:15.844206 [Byte1]: 45
8390 18:02:15.848777
8391 18:02:15.849250 Set Vref, RX VrefLevel [Byte0]: 46
8392 18:02:15.851518 [Byte1]: 46
8393 18:02:15.856385
8394 18:02:15.856897 Set Vref, RX VrefLevel [Byte0]: 47
8395 18:02:15.859670 [Byte1]: 47
8396 18:02:15.863801
8397 18:02:15.864304 Set Vref, RX VrefLevel [Byte0]: 48
8398 18:02:15.866896 [Byte1]: 48
8399 18:02:15.871663
8400 18:02:15.872184 Set Vref, RX VrefLevel [Byte0]: 49
8401 18:02:15.874466 [Byte1]: 49
8402 18:02:15.878931
8403 18:02:15.879354 Set Vref, RX VrefLevel [Byte0]: 50
8404 18:02:15.882033 [Byte1]: 50
8405 18:02:15.886535
8406 18:02:15.886919 Set Vref, RX VrefLevel [Byte0]: 51
8407 18:02:15.890085 [Byte1]: 51
8408 18:02:15.894628
8409 18:02:15.895124 Set Vref, RX VrefLevel [Byte0]: 52
8410 18:02:15.898143 [Byte1]: 52
8411 18:02:15.902154
8412 18:02:15.902633 Set Vref, RX VrefLevel [Byte0]: 53
8413 18:02:15.905273 [Byte1]: 53
8414 18:02:15.909908
8415 18:02:15.910522 Set Vref, RX VrefLevel [Byte0]: 54
8416 18:02:15.913003 [Byte1]: 54
8417 18:02:15.917167
8418 18:02:15.917666 Set Vref, RX VrefLevel [Byte0]: 55
8419 18:02:15.920502 [Byte1]: 55
8420 18:02:15.925199
8421 18:02:15.925623 Set Vref, RX VrefLevel [Byte0]: 56
8422 18:02:15.928549 [Byte1]: 56
8423 18:02:15.932814
8424 18:02:15.933327 Set Vref, RX VrefLevel [Byte0]: 57
8425 18:02:15.936082 [Byte1]: 57
8426 18:02:15.940013
8427 18:02:15.940438 Set Vref, RX VrefLevel [Byte0]: 58
8428 18:02:15.944053 [Byte1]: 58
8429 18:02:15.948141
8430 18:02:15.948818 Set Vref, RX VrefLevel [Byte0]: 59
8431 18:02:15.951445 [Byte1]: 59
8432 18:02:15.955807
8433 18:02:15.956306 Set Vref, RX VrefLevel [Byte0]: 60
8434 18:02:15.958937 [Byte1]: 60
8435 18:02:15.963553
8436 18:02:15.964056 Set Vref, RX VrefLevel [Byte0]: 61
8437 18:02:15.966627 [Byte1]: 61
8438 18:02:15.971130
8439 18:02:15.971632 Set Vref, RX VrefLevel [Byte0]: 62
8440 18:02:15.974700 [Byte1]: 62
8441 18:02:15.978867
8442 18:02:15.979293 Set Vref, RX VrefLevel [Byte0]: 63
8443 18:02:15.981821 [Byte1]: 63
8444 18:02:15.986647
8445 18:02:15.987156 Set Vref, RX VrefLevel [Byte0]: 64
8446 18:02:15.989803 [Byte1]: 64
8447 18:02:15.993745
8448 18:02:15.994170 Set Vref, RX VrefLevel [Byte0]: 65
8449 18:02:15.996985 [Byte1]: 65
8450 18:02:16.001834
8451 18:02:16.002368 Set Vref, RX VrefLevel [Byte0]: 66
8452 18:02:16.005029 [Byte1]: 66
8453 18:02:16.009368
8454 18:02:16.009796 Set Vref, RX VrefLevel [Byte0]: 67
8455 18:02:16.012557 [Byte1]: 67
8456 18:02:16.016981
8457 18:02:16.017482 Set Vref, RX VrefLevel [Byte0]: 68
8458 18:02:16.020513 [Byte1]: 68
8459 18:02:16.024778
8460 18:02:16.025215 Set Vref, RX VrefLevel [Byte0]: 69
8461 18:02:16.028144 [Byte1]: 69
8462 18:02:16.032512
8463 18:02:16.032939 Set Vref, RX VrefLevel [Byte0]: 70
8464 18:02:16.035557 [Byte1]: 70
8465 18:02:16.039616
8466 18:02:16.040195 Set Vref, RX VrefLevel [Byte0]: 71
8467 18:02:16.042957 [Byte1]: 71
8468 18:02:16.047331
8469 18:02:16.047793 Set Vref, RX VrefLevel [Byte0]: 72
8470 18:02:16.050868 [Byte1]: 72
8471 18:02:16.055298
8472 18:02:16.055684 Set Vref, RX VrefLevel [Byte0]: 73
8473 18:02:16.058315 [Byte1]: 73
8474 18:02:16.063111
8475 18:02:16.063577 Final RX Vref Byte 0 = 60 to rank0
8476 18:02:16.065855 Final RX Vref Byte 1 = 54 to rank0
8477 18:02:16.069433 Final RX Vref Byte 0 = 60 to rank1
8478 18:02:16.072797 Final RX Vref Byte 1 = 54 to rank1==
8479 18:02:16.076406 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 18:02:16.082926 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8481 18:02:16.083399 ==
8482 18:02:16.083706 DQS Delay:
8483 18:02:16.083984 DQS0 = 0, DQS1 = 0
8484 18:02:16.086550 DQM Delay:
8485 18:02:16.087013 DQM0 = 128, DQM1 = 124
8486 18:02:16.089487 DQ Delay:
8487 18:02:16.092468 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8488 18:02:16.095926 DQ4 =130, DQ5 =138, DQ6 =136, DQ7 =124
8489 18:02:16.098854 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8490 18:02:16.102697 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8491 18:02:16.103087
8492 18:02:16.103386
8493 18:02:16.103664
8494 18:02:16.105855 [DramC_TX_OE_Calibration] TA2
8495 18:02:16.109115 Original DQ_B0 (3 6) =30, OEN = 27
8496 18:02:16.112124 Original DQ_B1 (3 6) =30, OEN = 27
8497 18:02:16.115747 24, 0x0, End_B0=24 End_B1=24
8498 18:02:16.116221 25, 0x0, End_B0=25 End_B1=25
8499 18:02:16.118794 26, 0x0, End_B0=26 End_B1=26
8500 18:02:16.122442 27, 0x0, End_B0=27 End_B1=27
8501 18:02:16.125772 28, 0x0, End_B0=28 End_B1=28
8502 18:02:16.129286 29, 0x0, End_B0=29 End_B1=29
8503 18:02:16.129757 30, 0x0, End_B0=30 End_B1=30
8504 18:02:16.132706 31, 0x4141, End_B0=30 End_B1=30
8505 18:02:16.135643 Byte0 end_step=30 best_step=27
8506 18:02:16.139179 Byte1 end_step=30 best_step=27
8507 18:02:16.142250 Byte0 TX OE(2T, 0.5T) = (3, 3)
8508 18:02:16.145553 Byte1 TX OE(2T, 0.5T) = (3, 3)
8509 18:02:16.145927
8510 18:02:16.146251
8511 18:02:16.152437 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8512 18:02:16.155379 CH1 RK0: MR19=303, MR18=2B2B
8513 18:02:16.162557 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8514 18:02:16.163028
8515 18:02:16.165459 ----->DramcWriteLeveling(PI) begin...
8516 18:02:16.165929 ==
8517 18:02:16.169010 Dram Type= 6, Freq= 0, CH_1, rank 1
8518 18:02:16.171813 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8519 18:02:16.172306 ==
8520 18:02:16.174979 Write leveling (Byte 0): 24 => 24
8521 18:02:16.178651 Write leveling (Byte 1): 20 => 20
8522 18:02:16.181563 DramcWriteLeveling(PI) end<-----
8523 18:02:16.181950
8524 18:02:16.182278 ==
8525 18:02:16.185058 Dram Type= 6, Freq= 0, CH_1, rank 1
8526 18:02:16.188403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8527 18:02:16.191785 ==
8528 18:02:16.192254 [Gating] SW mode calibration
8529 18:02:16.198538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8530 18:02:16.204432 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8531 18:02:16.208125 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8532 18:02:16.214850 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8533 18:02:16.218198 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8534 18:02:16.221842 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8535 18:02:16.228087 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8536 18:02:16.231609 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8537 18:02:16.234539 0 12 24 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8538 18:02:16.240964 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
8539 18:02:16.244388 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8540 18:02:16.247941 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8541 18:02:16.254360 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8542 18:02:16.257995 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8543 18:02:16.260807 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8544 18:02:16.267765 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8545 18:02:16.270778 0 13 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8546 18:02:16.274432 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8547 18:02:16.280733 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8548 18:02:16.284258 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8549 18:02:16.287805 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8550 18:02:16.294358 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8551 18:02:16.297331 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8552 18:02:16.300786 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8553 18:02:16.307088 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8554 18:02:16.310478 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8555 18:02:16.314060 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8556 18:02:16.320403 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8557 18:02:16.323666 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8558 18:02:16.326776 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 18:02:16.333479 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 18:02:16.337037 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 18:02:16.340135 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 18:02:16.346865 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 18:02:16.349967 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 18:02:16.353243 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 18:02:16.359848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 18:02:16.363289 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 18:02:16.366826 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 18:02:16.373194 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 18:02:16.376703 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8570 18:02:16.379680 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8571 18:02:16.383357 Total UI for P1: 0, mck2ui 16
8572 18:02:16.386550 best dqsien dly found for B0: ( 1, 0, 24)
8573 18:02:16.390037 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8574 18:02:16.396251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 18:02:16.399766 Total UI for P1: 0, mck2ui 16
8576 18:02:16.402780 best dqsien dly found for B1: ( 1, 1, 0)
8577 18:02:16.406252 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8578 18:02:16.409811 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8579 18:02:16.410200
8580 18:02:16.412731 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8581 18:02:16.416161 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8582 18:02:16.419521 [Gating] SW calibration Done
8583 18:02:16.419913 ==
8584 18:02:16.422539 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 18:02:16.426085 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 18:02:16.426539 ==
8587 18:02:16.429074 RX Vref Scan: 0
8588 18:02:16.429518
8589 18:02:16.432655 RX Vref 0 -> 0, step: 1
8590 18:02:16.433047
8591 18:02:16.433351 RX Delay 0 -> 252, step: 8
8592 18:02:16.439475 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8593 18:02:16.442260 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8594 18:02:16.445822 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8595 18:02:16.448932 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8596 18:02:16.452648 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8597 18:02:16.459347 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8598 18:02:16.462108 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8599 18:02:16.465821 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8600 18:02:16.468843 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8601 18:02:16.472245 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8602 18:02:16.478911 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8603 18:02:16.482394 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8604 18:02:16.485828 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8605 18:02:16.488753 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8606 18:02:16.495207 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8607 18:02:16.498802 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8608 18:02:16.499203 ==
8609 18:02:16.501871 Dram Type= 6, Freq= 0, CH_1, rank 1
8610 18:02:16.505527 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8611 18:02:16.505886 ==
8612 18:02:16.506299 DQS Delay:
8613 18:02:16.508361 DQS0 = 0, DQS1 = 0
8614 18:02:16.508706 DQM Delay:
8615 18:02:16.511908 DQM0 = 131, DQM1 = 125
8616 18:02:16.512251 DQ Delay:
8617 18:02:16.514927 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8618 18:02:16.518586 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8619 18:02:16.521937 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8620 18:02:16.528305 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8621 18:02:16.528712
8622 18:02:16.529010
8623 18:02:16.529283 ==
8624 18:02:16.531925 Dram Type= 6, Freq= 0, CH_1, rank 1
8625 18:02:16.534917 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8626 18:02:16.535305 ==
8627 18:02:16.535604
8628 18:02:16.535881
8629 18:02:16.538475 TX Vref Scan disable
8630 18:02:16.539005 == TX Byte 0 ==
8631 18:02:16.544908 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8632 18:02:16.548119 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8633 18:02:16.548510 == TX Byte 1 ==
8634 18:02:16.555085 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8635 18:02:16.557962 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8636 18:02:16.558373 ==
8637 18:02:16.561753 Dram Type= 6, Freq= 0, CH_1, rank 1
8638 18:02:16.564959 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8639 18:02:16.565313 ==
8640 18:02:16.578194
8641 18:02:16.581371 TX Vref early break, caculate TX vref
8642 18:02:16.584886 TX Vref=16, minBit 0, minWin=22, winSum=384
8643 18:02:16.588089 TX Vref=18, minBit 0, minWin=23, winSum=392
8644 18:02:16.591438 TX Vref=20, minBit 0, minWin=22, winSum=395
8645 18:02:16.594936 TX Vref=22, minBit 0, minWin=24, winSum=405
8646 18:02:16.598544 TX Vref=24, minBit 0, minWin=23, winSum=417
8647 18:02:16.605132 TX Vref=26, minBit 5, minWin=24, winSum=423
8648 18:02:16.608223 TX Vref=28, minBit 0, minWin=24, winSum=423
8649 18:02:16.611764 TX Vref=30, minBit 0, minWin=23, winSum=415
8650 18:02:16.614510 TX Vref=32, minBit 0, minWin=23, winSum=405
8651 18:02:16.618154 TX Vref=34, minBit 0, minWin=23, winSum=399
8652 18:02:16.624560 [TxChooseVref] Worse bit 5, Min win 24, Win sum 423, Final Vref 26
8653 18:02:16.624629
8654 18:02:16.628113 Final TX Range 0 Vref 26
8655 18:02:16.628196
8656 18:02:16.628270 ==
8657 18:02:16.631487 Dram Type= 6, Freq= 0, CH_1, rank 1
8658 18:02:16.634403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8659 18:02:16.634475 ==
8660 18:02:16.634546
8661 18:02:16.634617
8662 18:02:16.637914 TX Vref Scan disable
8663 18:02:16.644489 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8664 18:02:16.644558 == TX Byte 0 ==
8665 18:02:16.647981 u2DelayCellOfst[0]=14 cells (4 PI)
8666 18:02:16.651213 u2DelayCellOfst[1]=7 cells (2 PI)
8667 18:02:16.654363 u2DelayCellOfst[2]=0 cells (0 PI)
8668 18:02:16.657573 u2DelayCellOfst[3]=7 cells (2 PI)
8669 18:02:16.661092 u2DelayCellOfst[4]=7 cells (2 PI)
8670 18:02:16.664270 u2DelayCellOfst[5]=18 cells (5 PI)
8671 18:02:16.667584 u2DelayCellOfst[6]=14 cells (4 PI)
8672 18:02:16.671153 u2DelayCellOfst[7]=3 cells (1 PI)
8673 18:02:16.674138 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8674 18:02:16.677693 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8675 18:02:16.677781 == TX Byte 1 ==
8676 18:02:16.681318 u2DelayCellOfst[8]=0 cells (0 PI)
8677 18:02:16.684329 u2DelayCellOfst[9]=3 cells (1 PI)
8678 18:02:16.687870 u2DelayCellOfst[10]=10 cells (3 PI)
8679 18:02:16.690999 u2DelayCellOfst[11]=3 cells (1 PI)
8680 18:02:16.694136 u2DelayCellOfst[12]=14 cells (4 PI)
8681 18:02:16.697571 u2DelayCellOfst[13]=18 cells (5 PI)
8682 18:02:16.700820 u2DelayCellOfst[14]=18 cells (5 PI)
8683 18:02:16.704440 u2DelayCellOfst[15]=14 cells (4 PI)
8684 18:02:16.707407 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8685 18:02:16.714194 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8686 18:02:16.714315 DramC Write-DBI on
8687 18:02:16.714388 ==
8688 18:02:16.717407 Dram Type= 6, Freq= 0, CH_1, rank 1
8689 18:02:16.723837 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8690 18:02:16.723909 ==
8691 18:02:16.723981
8692 18:02:16.724053
8693 18:02:16.724119 TX Vref Scan disable
8694 18:02:16.727499 == TX Byte 0 ==
8695 18:02:16.731287 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8696 18:02:16.733973 == TX Byte 1 ==
8697 18:02:16.737428 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8698 18:02:16.741064 DramC Write-DBI off
8699 18:02:16.741133
8700 18:02:16.741204 [DATLAT]
8701 18:02:16.741276 Freq=1600, CH1 RK1
8702 18:02:16.741342
8703 18:02:16.743982 DATLAT Default: 0xe
8704 18:02:16.747682 0, 0xFFFF, sum = 0
8705 18:02:16.747748 1, 0xFFFF, sum = 0
8706 18:02:16.750581 2, 0xFFFF, sum = 0
8707 18:02:16.750644 3, 0xFFFF, sum = 0
8708 18:02:16.754268 4, 0xFFFF, sum = 0
8709 18:02:16.754334 5, 0xFFFF, sum = 0
8710 18:02:16.757112 6, 0xFFFF, sum = 0
8711 18:02:16.757175 7, 0xFFFF, sum = 0
8712 18:02:16.760790 8, 0xFFFF, sum = 0
8713 18:02:16.760854 9, 0xFFFF, sum = 0
8714 18:02:16.764167 10, 0xFFFF, sum = 0
8715 18:02:16.764233 11, 0xFFFF, sum = 0
8716 18:02:16.767581 12, 0x8F7F, sum = 0
8717 18:02:16.767652 13, 0x0, sum = 1
8718 18:02:16.770482 14, 0x0, sum = 2
8719 18:02:16.770546 15, 0x0, sum = 3
8720 18:02:16.773892 16, 0x0, sum = 4
8721 18:02:16.773955 best_step = 14
8722 18:02:16.774023
8723 18:02:16.774110 ==
8724 18:02:16.776940 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 18:02:16.780626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8726 18:02:16.783508 ==
8727 18:02:16.783572 RX Vref Scan: 0
8728 18:02:16.783644
8729 18:02:16.787264 RX Vref 0 -> 0, step: 1
8730 18:02:16.787326
8731 18:02:16.790310 RX Delay 3 -> 252, step: 4
8732 18:02:16.793899 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8733 18:02:16.796935 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8734 18:02:16.800238 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8735 18:02:16.806889 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8736 18:02:16.809997 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8737 18:02:16.813593 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8738 18:02:16.816974 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8739 18:02:16.820294 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8740 18:02:16.826463 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8741 18:02:16.829816 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8742 18:02:16.833152 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8743 18:02:16.836668 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8744 18:02:16.839693 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8745 18:02:16.846159 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8746 18:02:16.849768 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8747 18:02:16.853355 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8748 18:02:16.853431 ==
8749 18:02:16.856305 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 18:02:16.859976 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8751 18:02:16.862748 ==
8752 18:02:16.862824 DQS Delay:
8753 18:02:16.862882 DQS0 = 0, DQS1 = 0
8754 18:02:16.866290 DQM Delay:
8755 18:02:16.866365 DQM0 = 126, DQM1 = 123
8756 18:02:16.869807 DQ Delay:
8757 18:02:16.873268 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =122
8758 18:02:16.876259 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8759 18:02:16.879536 DQ8 =106, DQ9 =110, DQ10 =126, DQ11 =116
8760 18:02:16.883104 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8761 18:02:16.883180
8762 18:02:16.883239
8763 18:02:16.883292
8764 18:02:16.886245 [DramC_TX_OE_Calibration] TA2
8765 18:02:16.889684 Original DQ_B0 (3 6) =30, OEN = 27
8766 18:02:16.892723 Original DQ_B1 (3 6) =30, OEN = 27
8767 18:02:16.896431 24, 0x0, End_B0=24 End_B1=24
8768 18:02:16.896500 25, 0x0, End_B0=25 End_B1=25
8769 18:02:16.899529 26, 0x0, End_B0=26 End_B1=26
8770 18:02:16.902793 27, 0x0, End_B0=27 End_B1=27
8771 18:02:16.906354 28, 0x0, End_B0=28 End_B1=28
8772 18:02:16.906422 29, 0x0, End_B0=29 End_B1=29
8773 18:02:16.909243 30, 0x0, End_B0=30 End_B1=30
8774 18:02:16.912316 31, 0x5151, End_B0=30 End_B1=30
8775 18:02:16.915856 Byte0 end_step=30 best_step=27
8776 18:02:16.919523 Byte1 end_step=30 best_step=27
8777 18:02:16.922507 Byte0 TX OE(2T, 0.5T) = (3, 3)
8778 18:02:16.922573 Byte1 TX OE(2T, 0.5T) = (3, 3)
8779 18:02:16.926124
8780 18:02:16.926227
8781 18:02:16.932072 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8782 18:02:16.935749 CH1 RK1: MR19=303, MR18=1E1E
8783 18:02:16.942373 CH1_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
8784 18:02:16.945912 [RxdqsGatingPostProcess] freq 1600
8785 18:02:16.949052 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8786 18:02:16.952467 Pre-setting of DQS Precalculation
8787 18:02:16.959239 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8788 18:02:16.965800 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8789 18:02:16.972667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8790 18:02:16.972736
8791 18:02:16.972808
8792 18:02:16.975674 [Calibration Summary] 3200 Mbps
8793 18:02:16.975739 CH 0, Rank 0
8794 18:02:16.979142 SW Impedance : PASS
8795 18:02:16.982431 DUTY Scan : NO K
8796 18:02:16.982497 ZQ Calibration : PASS
8797 18:02:16.985572 Jitter Meter : NO K
8798 18:02:16.988571 CBT Training : PASS
8799 18:02:16.988638 Write leveling : PASS
8800 18:02:16.992336 RX DQS gating : PASS
8801 18:02:16.995684 RX DQ/DQS(RDDQC) : PASS
8802 18:02:16.995759 TX DQ/DQS : PASS
8803 18:02:16.998658 RX DATLAT : PASS
8804 18:02:17.002188 RX DQ/DQS(Engine): PASS
8805 18:02:17.002269 TX OE : PASS
8806 18:02:17.002327 All Pass.
8807 18:02:17.005281
8808 18:02:17.005356 CH 0, Rank 1
8809 18:02:17.008865 SW Impedance : PASS
8810 18:02:17.008940 DUTY Scan : NO K
8811 18:02:17.012274 ZQ Calibration : PASS
8812 18:02:17.012349 Jitter Meter : NO K
8813 18:02:17.015197 CBT Training : PASS
8814 18:02:17.018702 Write leveling : PASS
8815 18:02:17.018781 RX DQS gating : PASS
8816 18:02:17.022376 RX DQ/DQS(RDDQC) : PASS
8817 18:02:17.025372 TX DQ/DQS : PASS
8818 18:02:17.025451 RX DATLAT : PASS
8819 18:02:17.028984 RX DQ/DQS(Engine): PASS
8820 18:02:17.032104 TX OE : PASS
8821 18:02:17.032179 All Pass.
8822 18:02:17.032237
8823 18:02:17.032291 CH 1, Rank 0
8824 18:02:17.035022 SW Impedance : PASS
8825 18:02:17.038719 DUTY Scan : NO K
8826 18:02:17.038795 ZQ Calibration : PASS
8827 18:02:17.041541 Jitter Meter : NO K
8828 18:02:17.044899 CBT Training : PASS
8829 18:02:17.044975 Write leveling : PASS
8830 18:02:17.048269 RX DQS gating : PASS
8831 18:02:17.051879 RX DQ/DQS(RDDQC) : PASS
8832 18:02:17.051955 TX DQ/DQS : PASS
8833 18:02:17.054863 RX DATLAT : PASS
8834 18:02:17.058410 RX DQ/DQS(Engine): PASS
8835 18:02:17.058486 TX OE : PASS
8836 18:02:17.061761 All Pass.
8837 18:02:17.061835
8838 18:02:17.061893 CH 1, Rank 1
8839 18:02:17.065209 SW Impedance : PASS
8840 18:02:17.065285 DUTY Scan : NO K
8841 18:02:17.067886 ZQ Calibration : PASS
8842 18:02:17.071306 Jitter Meter : NO K
8843 18:02:17.071381 CBT Training : PASS
8844 18:02:17.075055 Write leveling : PASS
8845 18:02:17.075131 RX DQS gating : PASS
8846 18:02:17.078053 RX DQ/DQS(RDDQC) : PASS
8847 18:02:17.081192 TX DQ/DQS : PASS
8848 18:02:17.081268 RX DATLAT : PASS
8849 18:02:17.084944 RX DQ/DQS(Engine): PASS
8850 18:02:17.087881 TX OE : PASS
8851 18:02:17.087956 All Pass.
8852 18:02:17.088015
8853 18:02:17.091399 DramC Write-DBI on
8854 18:02:17.091477 PER_BANK_REFRESH: Hybrid Mode
8855 18:02:17.094591 TX_TRACKING: ON
8856 18:02:17.104175 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8857 18:02:17.111267 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8858 18:02:17.117681 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8859 18:02:17.120731 [FAST_K] Save calibration result to emmc
8860 18:02:17.124272 sync common calibartion params.
8861 18:02:17.127922 sync cbt_mode0:0, 1:0
8862 18:02:17.127998 dram_init: ddr_geometry: 0
8863 18:02:17.130951 dram_init: ddr_geometry: 0
8864 18:02:17.134536 dram_init: ddr_geometry: 0
8865 18:02:17.137628 0:dram_rank_size:80000000
8866 18:02:17.137705 1:dram_rank_size:80000000
8867 18:02:17.144343 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8868 18:02:17.147350 DFS_SHUFFLE_HW_MODE: ON
8869 18:02:17.150499 dramc_set_vcore_voltage set vcore to 725000
8870 18:02:17.153948 Read voltage for 1600, 0
8871 18:02:17.154023 Vio18 = 0
8872 18:02:17.154081 Vcore = 725000
8873 18:02:17.157713 Vdram = 0
8874 18:02:17.157789 Vddq = 0
8875 18:02:17.157847 Vmddr = 0
8876 18:02:17.160643 switch to 3200 Mbps bootup
8877 18:02:17.160717 [DramcRunTimeConfig]
8878 18:02:17.163712 PHYPLL
8879 18:02:17.163787 DPM_CONTROL_AFTERK: ON
8880 18:02:17.167261 PER_BANK_REFRESH: ON
8881 18:02:17.170391 REFRESH_OVERHEAD_REDUCTION: ON
8882 18:02:17.170466 CMD_PICG_NEW_MODE: OFF
8883 18:02:17.173947 XRTWTW_NEW_MODE: ON
8884 18:02:17.174022 XRTRTR_NEW_MODE: ON
8885 18:02:17.176812 TX_TRACKING: ON
8886 18:02:17.176888 RDSEL_TRACKING: OFF
8887 18:02:17.180222 DQS Precalculation for DVFS: ON
8888 18:02:17.183814 RX_TRACKING: OFF
8889 18:02:17.183886 HW_GATING DBG: ON
8890 18:02:17.187102 ZQCS_ENABLE_LP4: ON
8891 18:02:17.187168 RX_PICG_NEW_MODE: ON
8892 18:02:17.190313 TX_PICG_NEW_MODE: ON
8893 18:02:17.190377 ENABLE_RX_DCM_DPHY: ON
8894 18:02:17.193786 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8895 18:02:17.197158 DUMMY_READ_FOR_TRACKING: OFF
8896 18:02:17.200593 !!! SPM_CONTROL_AFTERK: OFF
8897 18:02:17.203542 !!! SPM could not control APHY
8898 18:02:17.203618 IMPEDANCE_TRACKING: ON
8899 18:02:17.206663 TEMP_SENSOR: ON
8900 18:02:17.206740 HW_SAVE_FOR_SR: OFF
8901 18:02:17.210369 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8902 18:02:17.213196 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8903 18:02:17.216898 Read ODT Tracking: ON
8904 18:02:17.219857 Refresh Rate DeBounce: ON
8905 18:02:17.219933 DFS_NO_QUEUE_FLUSH: ON
8906 18:02:17.223627 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8907 18:02:17.226558 ENABLE_DFS_RUNTIME_MRW: OFF
8908 18:02:17.230285 DDR_RESERVE_NEW_MODE: ON
8909 18:02:17.230360 MR_CBT_SWITCH_FREQ: ON
8910 18:02:17.233305 =========================
8911 18:02:17.251978 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8912 18:02:17.255317 dram_init: ddr_geometry: 0
8913 18:02:17.273332 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8914 18:02:17.276956 dram_init: dram init end (result: 0)
8915 18:02:17.283364 DRAM-K: Full calibration passed in 23390 msecs
8916 18:02:17.286491 MRC: failed to locate region type 0.
8917 18:02:17.286562 DRAM rank0 size:0x80000000,
8918 18:02:17.290123 DRAM rank1 size=0x80000000
8919 18:02:17.299842 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8920 18:02:17.306963 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8921 18:02:17.312893 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8922 18:02:17.319452 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8923 18:02:17.323233 DRAM rank0 size:0x80000000,
8924 18:02:17.326583 DRAM rank1 size=0x80000000
8925 18:02:17.326689 CBMEM:
8926 18:02:17.329616 IMD: root @ 0xfffff000 254 entries.
8927 18:02:17.332842 IMD: root @ 0xffffec00 62 entries.
8928 18:02:17.336257 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8929 18:02:17.339491 WARNING: RO_VPD is uninitialized or empty.
8930 18:02:17.346347 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8931 18:02:17.352886 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8932 18:02:17.366105 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8933 18:02:17.377347 BS: romstage times (exec / console): total (unknown) / 22934 ms
8934 18:02:17.377427
8935 18:02:17.377502
8936 18:02:17.387430 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8937 18:02:17.390499 ARM64: Exception handlers installed.
8938 18:02:17.394085 ARM64: Testing exception
8939 18:02:17.397087 ARM64: Done test exception
8940 18:02:17.397155 Enumerating buses...
8941 18:02:17.400745 Show all devs... Before device enumeration.
8942 18:02:17.403764 Root Device: enabled 1
8943 18:02:17.407234 CPU_CLUSTER: 0: enabled 1
8944 18:02:17.407301 CPU: 00: enabled 1
8945 18:02:17.410147 Compare with tree...
8946 18:02:17.410217 Root Device: enabled 1
8947 18:02:17.413281 CPU_CLUSTER: 0: enabled 1
8948 18:02:17.416928 CPU: 00: enabled 1
8949 18:02:17.416995 Root Device scanning...
8950 18:02:17.420526 scan_static_bus for Root Device
8951 18:02:17.423532 CPU_CLUSTER: 0 enabled
8952 18:02:17.426706 scan_static_bus for Root Device done
8953 18:02:17.429980 scan_bus: bus Root Device finished in 8 msecs
8954 18:02:17.430052 done
8955 18:02:17.436498 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8956 18:02:17.440091 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8957 18:02:17.446377 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8958 18:02:17.450177 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8959 18:02:17.453429 Allocating resources...
8960 18:02:17.456461 Reading resources...
8961 18:02:17.460160 Root Device read_resources bus 0 link: 0
8962 18:02:17.460236 DRAM rank0 size:0x80000000,
8963 18:02:17.463374 DRAM rank1 size=0x80000000
8964 18:02:17.466899 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8965 18:02:17.469604 CPU: 00 missing read_resources
8966 18:02:17.476354 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8967 18:02:17.479784 Root Device read_resources bus 0 link: 0 done
8968 18:02:17.479883 Done reading resources.
8969 18:02:17.486369 Show resources in subtree (Root Device)...After reading.
8970 18:02:17.489935 Root Device child on link 0 CPU_CLUSTER: 0
8971 18:02:17.493434 CPU_CLUSTER: 0 child on link 0 CPU: 00
8972 18:02:17.502947 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8973 18:02:17.503028 CPU: 00
8974 18:02:17.505931 Root Device assign_resources, bus 0 link: 0
8975 18:02:17.509322 CPU_CLUSTER: 0 missing set_resources
8976 18:02:17.516188 Root Device assign_resources, bus 0 link: 0 done
8977 18:02:17.516288 Done setting resources.
8978 18:02:17.522794 Show resources in subtree (Root Device)...After assigning values.
8979 18:02:17.525849 Root Device child on link 0 CPU_CLUSTER: 0
8980 18:02:17.529350 CPU_CLUSTER: 0 child on link 0 CPU: 00
8981 18:02:17.539536 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8982 18:02:17.539614 CPU: 00
8983 18:02:17.542719 Done allocating resources.
8984 18:02:17.549105 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8985 18:02:17.549182 Enabling resources...
8986 18:02:17.549239 done.
8987 18:02:17.555885 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8988 18:02:17.555964 Initializing devices...
8989 18:02:17.558860 Root Device init
8990 18:02:17.558974 init hardware done!
8991 18:02:17.562162 0x00000018: ctrlr->caps
8992 18:02:17.565781 52.000 MHz: ctrlr->f_max
8993 18:02:17.565862 0.400 MHz: ctrlr->f_min
8994 18:02:17.569304 0x40ff8080: ctrlr->voltages
8995 18:02:17.572196 sclk: 390625
8996 18:02:17.572271 Bus Width = 1
8997 18:02:17.572330 sclk: 390625
8998 18:02:17.575960 Bus Width = 1
8999 18:02:17.576036 Early init status = 3
9000 18:02:17.582346 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9001 18:02:17.585403 in-header: 03 fc 00 00 01 00 00 00
9002 18:02:17.588602 in-data: 00
9003 18:02:17.591952 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9004 18:02:17.596626 in-header: 03 fd 00 00 00 00 00 00
9005 18:02:17.599704 in-data:
9006 18:02:17.603462 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9007 18:02:17.607008 in-header: 03 fc 00 00 01 00 00 00
9008 18:02:17.609968 in-data: 00
9009 18:02:17.613716 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9010 18:02:17.618496 in-header: 03 fd 00 00 00 00 00 00
9011 18:02:17.622078 in-data:
9012 18:02:17.625098 [SSUSB] Setting up USB HOST controller...
9013 18:02:17.628155 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9014 18:02:17.631794 [SSUSB] phy power-on done.
9015 18:02:17.634808 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9016 18:02:17.641423 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9017 18:02:17.645032 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9018 18:02:17.651644 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9019 18:02:17.658100 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9020 18:02:17.665062 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9021 18:02:17.671230 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9022 18:02:17.678192 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9023 18:02:17.681261 SPM: binary array size = 0x9dc
9024 18:02:17.684853 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9025 18:02:17.691505 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9026 18:02:17.697712 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9027 18:02:17.704705 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9028 18:02:17.707601 configure_display: Starting display init
9029 18:02:17.742098 anx7625_power_on_init: Init interface.
9030 18:02:17.744993 anx7625_disable_pd_protocol: Disabled PD feature.
9031 18:02:17.748594 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9032 18:02:17.776120 anx7625_start_dp_work: Secure OCM version=00
9033 18:02:17.779177 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9034 18:02:17.794348 sp_tx_get_edid_block: EDID Block = 1
9035 18:02:17.897815 Extracted contents:
9036 18:02:17.900485 header: 00 ff ff ff ff ff ff 00
9037 18:02:17.903532 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9038 18:02:17.906818 version: 01 04
9039 18:02:17.909788 basic params: 95 1f 11 78 0a
9040 18:02:17.913274 chroma info: 76 90 94 55 54 90 27 21 50 54
9041 18:02:17.916723 established: 00 00 00
9042 18:02:17.923374 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9043 18:02:17.926298 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9044 18:02:17.933362 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9045 18:02:17.939788 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9046 18:02:17.946161 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9047 18:02:17.949796 extensions: 00
9048 18:02:17.949867 checksum: fb
9049 18:02:17.949942
9050 18:02:17.953071 Manufacturer: IVO Model 57d Serial Number 0
9051 18:02:17.956125 Made week 0 of 2020
9052 18:02:17.956195 EDID version: 1.4
9053 18:02:17.959704 Digital display
9054 18:02:17.963171 6 bits per primary color channel
9055 18:02:17.963240 DisplayPort interface
9056 18:02:17.966176 Maximum image size: 31 cm x 17 cm
9057 18:02:17.969656 Gamma: 220%
9058 18:02:17.969723 Check DPMS levels
9059 18:02:17.972747 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9060 18:02:17.979657 First detailed timing is preferred timing
9061 18:02:17.979725 Established timings supported:
9062 18:02:17.983358 Standard timings supported:
9063 18:02:17.985922 Detailed timings
9064 18:02:17.989788 Hex of detail: 383680a07038204018303c0035ae10000019
9065 18:02:17.992546 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9066 18:02:17.999509 0780 0798 07c8 0820 hborder 0
9067 18:02:18.002763 0438 043b 0447 0458 vborder 0
9068 18:02:18.006194 -hsync -vsync
9069 18:02:18.006272 Did detailed timing
9070 18:02:18.012744 Hex of detail: 000000000000000000000000000000000000
9071 18:02:18.015627 Manufacturer-specified data, tag 0
9072 18:02:18.019195 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9073 18:02:18.022248 ASCII string: InfoVision
9074 18:02:18.025851 Hex of detail: 000000fe00523134304e574635205248200a
9075 18:02:18.029505 ASCII string: R140NWF5 RH
9076 18:02:18.029581 Checksum
9077 18:02:18.032356 Checksum: 0xfb (valid)
9078 18:02:18.035859 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9079 18:02:18.038957 DSI data_rate: 832800000 bps
9080 18:02:18.045509 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9081 18:02:18.049040 anx7625_parse_edid: pixelclock(138800).
9082 18:02:18.052286 hactive(1920), hsync(48), hfp(24), hbp(88)
9083 18:02:18.055572 vactive(1080), vsync(12), vfp(3), vbp(17)
9084 18:02:18.058951 anx7625_dsi_config: config dsi.
9085 18:02:18.065558 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9086 18:02:18.078667 anx7625_dsi_config: success to config DSI
9087 18:02:18.082317 anx7625_dp_start: MIPI phy setup OK.
9088 18:02:18.085178 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9089 18:02:18.088803 mtk_ddp_mode_set invalid vrefresh 60
9090 18:02:18.092197 main_disp_path_setup
9091 18:02:18.092263 ovl_layer_smi_id_en
9092 18:02:18.095189 ovl_layer_smi_id_en
9093 18:02:18.095256 ccorr_config
9094 18:02:18.095335 aal_config
9095 18:02:18.098679 gamma_config
9096 18:02:18.098743 postmask_config
9097 18:02:18.101797 dither_config
9098 18:02:18.105389 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9099 18:02:18.111947 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9100 18:02:18.115381 Root Device init finished in 552 msecs
9101 18:02:18.118593 CPU_CLUSTER: 0 init
9102 18:02:18.125055 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9103 18:02:18.128616 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9104 18:02:18.131564 APU_MBOX 0x190000b0 = 0x10001
9105 18:02:18.134990 APU_MBOX 0x190001b0 = 0x10001
9106 18:02:18.138543 APU_MBOX 0x190005b0 = 0x10001
9107 18:02:18.141542 APU_MBOX 0x190006b0 = 0x10001
9108 18:02:18.145075 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9109 18:02:18.157749 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9110 18:02:18.170322 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9111 18:02:18.176770 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9112 18:02:18.188727 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9113 18:02:18.197798 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9114 18:02:18.200724 CPU_CLUSTER: 0 init finished in 81 msecs
9115 18:02:18.204519 Devices initialized
9116 18:02:18.207540 Show all devs... After init.
9117 18:02:18.207615 Root Device: enabled 1
9118 18:02:18.211290 CPU_CLUSTER: 0: enabled 1
9119 18:02:18.214117 CPU: 00: enabled 1
9120 18:02:18.217733 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9121 18:02:18.220764 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9122 18:02:18.224344 ELOG: NV offset 0x57f000 size 0x1000
9123 18:02:18.231029 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9124 18:02:18.237240 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9125 18:02:18.240509 ELOG: Event(17) added with size 13 at 2024-06-11 18:02:18 UTC
9126 18:02:18.244161 out: cmd=0x121: 03 db 21 01 00 00 00 00
9127 18:02:18.248002 in-header: 03 4c 00 00 2c 00 00 00
9128 18:02:18.261192 in-data: f7 6c 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9129 18:02:18.267567 ELOG: Event(A1) added with size 10 at 2024-06-11 18:02:18 UTC
9130 18:02:18.274402 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9131 18:02:18.280943 ELOG: Event(A0) added with size 9 at 2024-06-11 18:02:18 UTC
9132 18:02:18.283810 elog_add_boot_reason: Logged dev mode boot
9133 18:02:18.287217 BS: BS_POST_DEVICE entry times (exec / console): 1 / 64 ms
9134 18:02:18.290829 Finalize devices...
9135 18:02:18.290898 Devices finalized
9136 18:02:18.297113 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9137 18:02:18.300537 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9138 18:02:18.303965 in-header: 03 07 00 00 08 00 00 00
9139 18:02:18.306974 in-data: aa e4 47 04 13 02 00 00
9140 18:02:18.310496 Chrome EC: UHEPI supported
9141 18:02:18.317058 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9142 18:02:18.320121 in-header: 03 a9 00 00 08 00 00 00
9143 18:02:18.323692 in-data: 84 60 60 08 00 00 00 00
9144 18:02:18.326669 ELOG: Event(91) added with size 10 at 2024-06-11 18:02:18 UTC
9145 18:02:18.333257 Chrome EC: clear events_b mask to 0x0000000020004000
9146 18:02:18.340577 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9147 18:02:18.344240 in-header: 03 fd 00 00 00 00 00 00
9148 18:02:18.344310 in-data:
9149 18:02:18.350907 BS: BS_WRITE_TABLES entry times (exec / console): 1 / 46 ms
9150 18:02:18.354025 Writing coreboot table at 0xffe64000
9151 18:02:18.357120 0. 000000000010a000-0000000000113fff: RAMSTAGE
9152 18:02:18.360532 1. 0000000040000000-00000000400fffff: RAM
9153 18:02:18.363584 2. 0000000040100000-000000004032afff: RAMSTAGE
9154 18:02:18.367165 3. 000000004032b000-00000000545fffff: RAM
9155 18:02:18.373761 4. 0000000054600000-000000005465ffff: BL31
9156 18:02:18.377377 5. 0000000054660000-00000000ffe63fff: RAM
9157 18:02:18.380669 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9158 18:02:18.383946 7. 0000000100000000-000000013fffffff: RAM
9159 18:02:18.387328 Passing 5 GPIOs to payload:
9160 18:02:18.393503 NAME | PORT | POLARITY | VALUE
9161 18:02:18.396982 EC in RW | 0x000000aa | low | undefined
9162 18:02:18.400584 EC interrupt | 0x00000005 | low | undefined
9163 18:02:18.406853 TPM interrupt | 0x000000ab | high | undefined
9164 18:02:18.410358 SD card detect | 0x00000011 | high | undefined
9165 18:02:18.417000 speaker enable | 0x00000093 | high | undefined
9166 18:02:18.420022 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9167 18:02:18.423684 in-header: 03 f8 00 00 02 00 00 00
9168 18:02:18.423751 in-data: 03 00
9169 18:02:18.426623 ADC[4]: Raw value=669327 ID=5
9170 18:02:18.430138 ADC[3]: Raw value=212549 ID=1
9171 18:02:18.430234 RAM Code: 0x51
9172 18:02:18.433740 ADC[6]: Raw value=74410 ID=0
9173 18:02:18.436767 ADC[5]: Raw value=211444 ID=1
9174 18:02:18.436837 SKU Code: 0x1
9175 18:02:18.443583 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 42ca
9176 18:02:18.446941 coreboot table: 964 bytes.
9177 18:02:18.449827 IMD ROOT 0. 0xfffff000 0x00001000
9178 18:02:18.453565 IMD SMALL 1. 0xffffe000 0x00001000
9179 18:02:18.456456 RO MCACHE 2. 0xffffc000 0x00001104
9180 18:02:18.460255 CONSOLE 3. 0xfff7c000 0x00080000
9181 18:02:18.463210 FMAP 4. 0xfff7b000 0x00000452
9182 18:02:18.466651 TIME STAMP 5. 0xfff7a000 0x00000910
9183 18:02:18.469783 VBOOT WORK 6. 0xfff66000 0x00014000
9184 18:02:18.473224 RAMOOPS 7. 0xffe66000 0x00100000
9185 18:02:18.476649 COREBOOT 8. 0xffe64000 0x00002000
9186 18:02:18.476721 IMD small region:
9187 18:02:18.479594 IMD ROOT 0. 0xffffec00 0x00000400
9188 18:02:18.483329 VPD 1. 0xffffeb80 0x0000006c
9189 18:02:18.486323 MMC STATUS 2. 0xffffeb60 0x00000004
9190 18:02:18.492824 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9191 18:02:18.499582 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9192 18:02:18.539198 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9193 18:02:18.542867 Checking segment from ROM address 0x40100000
9194 18:02:18.546463 Checking segment from ROM address 0x4010001c
9195 18:02:18.553333 Loading segment from ROM address 0x40100000
9196 18:02:18.553410 code (compression=0)
9197 18:02:18.562993 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9198 18:02:18.569323 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9199 18:02:18.569399 it's not compressed!
9200 18:02:18.575849 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9201 18:02:18.579106 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9202 18:02:18.599972 Loading segment from ROM address 0x4010001c
9203 18:02:18.600047 Entry Point 0x80000000
9204 18:02:18.602949 Loaded segments
9205 18:02:18.606152 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9206 18:02:18.613150 Jumping to boot code at 0x80000000(0xffe64000)
9207 18:02:18.619744 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9208 18:02:18.626329 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9209 18:02:18.634467 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9210 18:02:18.637352 Checking segment from ROM address 0x40100000
9211 18:02:18.640946 Checking segment from ROM address 0x4010001c
9212 18:02:18.647570 Loading segment from ROM address 0x40100000
9213 18:02:18.647641 code (compression=1)
9214 18:02:18.654133 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9215 18:02:18.664197 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9216 18:02:18.664273 using LZMA
9217 18:02:18.672663 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9218 18:02:18.679295 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9219 18:02:18.682167 Loading segment from ROM address 0x4010001c
9220 18:02:18.685923 Entry Point 0x54601000
9221 18:02:18.686022 Loaded segments
9222 18:02:18.688916 NOTICE: MT8192 bl31_setup
9223 18:02:18.695944 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9224 18:02:18.699385 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9225 18:02:18.702954 WARNING: region 0:
9226 18:02:18.705971 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9227 18:02:18.706069 WARNING: region 1:
9228 18:02:18.712922 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9229 18:02:18.716294 WARNING: region 2:
9230 18:02:18.719324 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9231 18:02:18.722892 WARNING: region 3:
9232 18:02:18.726382 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9233 18:02:18.729312 WARNING: region 4:
9234 18:02:18.735858 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9235 18:02:18.735962 WARNING: region 5:
9236 18:02:18.739321 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9237 18:02:18.742620 WARNING: region 6:
9238 18:02:18.746118 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9239 18:02:18.749212 WARNING: region 7:
9240 18:02:18.752653 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9241 18:02:18.759245 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9242 18:02:18.762918 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9243 18:02:18.765940 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9244 18:02:18.772756 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9245 18:02:18.775731 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9246 18:02:18.779287 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9247 18:02:18.785657 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9248 18:02:18.789219 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9249 18:02:18.795852 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9250 18:02:18.798850 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9251 18:02:18.802170 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9252 18:02:18.809416 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9253 18:02:18.812449 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9254 18:02:18.815952 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9255 18:02:18.822362 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9256 18:02:18.825895 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9257 18:02:18.832251 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9258 18:02:18.835382 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9259 18:02:18.838862 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9260 18:02:18.845331 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9261 18:02:18.848956 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9262 18:02:18.855254 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9263 18:02:18.858244 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9264 18:02:18.861729 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9265 18:02:18.868230 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9266 18:02:18.871710 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9267 18:02:18.878674 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9268 18:02:18.881529 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9269 18:02:18.888136 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9270 18:02:18.891634 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9271 18:02:18.894741 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9272 18:02:18.901691 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9273 18:02:18.904712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9274 18:02:18.908158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9275 18:02:18.911634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9276 18:02:18.918181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9277 18:02:18.921377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9278 18:02:18.924858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9279 18:02:18.927864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9280 18:02:18.934483 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9281 18:02:18.937929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9282 18:02:18.940969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9283 18:02:18.944433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9284 18:02:18.951010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9285 18:02:18.954551 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9286 18:02:18.957501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9287 18:02:18.964387 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9288 18:02:18.967495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9289 18:02:18.970925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9290 18:02:18.977778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9291 18:02:18.980527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9292 18:02:18.987197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9293 18:02:18.990868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9294 18:02:18.997439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9295 18:02:19.000221 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9296 18:02:19.003807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9297 18:02:19.010405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9298 18:02:19.013940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9299 18:02:19.020539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9300 18:02:19.023491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9301 18:02:19.030479 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9302 18:02:19.033466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9303 18:02:19.040500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9304 18:02:19.043448 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9305 18:02:19.047005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9306 18:02:19.053620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9307 18:02:19.056407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9308 18:02:19.063231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9309 18:02:19.066633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9310 18:02:19.073139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9311 18:02:19.076733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9312 18:02:19.080124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9313 18:02:19.086529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9314 18:02:19.089868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9315 18:02:19.096227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9316 18:02:19.099620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9317 18:02:19.106315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9318 18:02:19.109928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9319 18:02:19.116450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9320 18:02:19.119526 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9321 18:02:19.125805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9322 18:02:19.129422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9323 18:02:19.132327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9324 18:02:19.139457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9325 18:02:19.142831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9326 18:02:19.149481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9327 18:02:19.152511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9328 18:02:19.159125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9329 18:02:19.162687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9330 18:02:19.165521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9331 18:02:19.172143 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9332 18:02:19.175564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9333 18:02:19.182547 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9334 18:02:19.185439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9335 18:02:19.192209 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9336 18:02:19.195877 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9337 18:02:19.198780 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9338 18:02:19.205381 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9339 18:02:19.208720 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9340 18:02:19.212219 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9341 18:02:19.215369 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9342 18:02:19.221803 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9343 18:02:19.225403 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9344 18:02:19.232026 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9345 18:02:19.235494 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9346 18:02:19.238451 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9347 18:02:19.245479 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9348 18:02:19.248521 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9349 18:02:19.255091 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9350 18:02:19.258735 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9351 18:02:19.261798 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9352 18:02:19.268375 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9353 18:02:19.271973 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9354 18:02:19.278253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9355 18:02:19.281551 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9356 18:02:19.288018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9357 18:02:19.291202 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9358 18:02:19.294659 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9359 18:02:19.298061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9360 18:02:19.304604 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9361 18:02:19.308100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9362 18:02:19.311548 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9363 18:02:19.314633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9364 18:02:19.321699 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9365 18:02:19.324905 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9366 18:02:19.327910 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9367 18:02:19.334479 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9368 18:02:19.338120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9369 18:02:19.344475 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9370 18:02:19.347861 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9371 18:02:19.351498 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9372 18:02:19.358170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9373 18:02:19.361129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9374 18:02:19.367647 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9375 18:02:19.371299 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9376 18:02:19.374231 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9377 18:02:19.381371 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9378 18:02:19.384327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9379 18:02:19.390987 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9380 18:02:19.394333 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9381 18:02:19.397561 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9382 18:02:19.404254 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9383 18:02:19.407676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9384 18:02:19.414332 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9385 18:02:19.417593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9386 18:02:19.421000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9387 18:02:19.427594 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9388 18:02:19.431128 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9389 18:02:19.434575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9390 18:02:19.440724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9391 18:02:19.444257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9392 18:02:19.450768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9393 18:02:19.454127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9394 18:02:19.457757 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9395 18:02:19.464362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9396 18:02:19.467337 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9397 18:02:19.474022 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9398 18:02:19.477683 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9399 18:02:19.480687 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9400 18:02:19.487299 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9401 18:02:19.490493 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9402 18:02:19.497547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9403 18:02:19.500715 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9404 18:02:19.503882 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9405 18:02:19.510289 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9406 18:02:19.513494 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9407 18:02:19.520740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9408 18:02:19.523999 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9409 18:02:19.527119 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9410 18:02:19.533663 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9411 18:02:19.536799 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9412 18:02:19.543829 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9413 18:02:19.547084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9414 18:02:19.550378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9415 18:02:19.556699 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9416 18:02:19.560331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9417 18:02:19.563696 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9418 18:02:19.570410 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9419 18:02:19.573324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9420 18:02:19.579962 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9421 18:02:19.583600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9422 18:02:19.586649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9423 18:02:19.593203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9424 18:02:19.596743 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9425 18:02:19.603242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9426 18:02:19.606273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9427 18:02:19.610237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9428 18:02:19.616722 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9429 18:02:19.619944 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9430 18:02:19.626322 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9431 18:02:19.629947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9432 18:02:19.633035 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9433 18:02:19.639969 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9434 18:02:19.642879 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9435 18:02:19.649956 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9436 18:02:19.653170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9437 18:02:19.659677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9438 18:02:19.663327 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9439 18:02:19.665949 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9440 18:02:19.672843 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9441 18:02:19.676442 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9442 18:02:19.683053 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9443 18:02:19.686172 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9444 18:02:19.692734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9445 18:02:19.696263 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9446 18:02:19.699336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9447 18:02:19.705993 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9448 18:02:19.709609 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9449 18:02:19.715851 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9450 18:02:19.719198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9451 18:02:19.722516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9452 18:02:19.729101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9453 18:02:19.732434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9454 18:02:19.739153 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9455 18:02:19.742172 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9456 18:02:19.748753 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9457 18:02:19.752227 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9458 18:02:19.755665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9459 18:02:19.762327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9460 18:02:19.765779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9461 18:02:19.772329 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9462 18:02:19.776096 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9463 18:02:19.778897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9464 18:02:19.785735 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9465 18:02:19.788636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9466 18:02:19.795321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9467 18:02:19.798987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9468 18:02:19.805213 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9469 18:02:19.808732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9470 18:02:19.812329 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9471 18:02:19.815325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9472 18:02:19.822182 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9473 18:02:19.825314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9474 18:02:19.828902 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9475 18:02:19.832161 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9476 18:02:19.838721 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9477 18:02:19.842147 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9478 18:02:19.848671 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9479 18:02:19.851704 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9480 18:02:19.855299 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9481 18:02:19.861771 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9482 18:02:19.864866 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9483 18:02:19.871874 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9484 18:02:19.874834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9485 18:02:19.878428 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9486 18:02:19.884779 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9487 18:02:19.888034 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9488 18:02:19.891663 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9489 18:02:19.897799 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9490 18:02:19.901243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9491 18:02:19.904863 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9492 18:02:19.911395 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9493 18:02:19.914460 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9494 18:02:19.918104 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9495 18:02:19.924415 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9496 18:02:19.928045 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9497 18:02:19.934486 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9498 18:02:19.937671 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9499 18:02:19.941100 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9500 18:02:19.947670 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9501 18:02:19.951223 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9502 18:02:19.957653 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9503 18:02:19.961360 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9504 18:02:19.964299 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9505 18:02:19.970850 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9506 18:02:19.974370 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9507 18:02:19.977548 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9508 18:02:19.984313 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9509 18:02:19.987700 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9510 18:02:19.991102 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9511 18:02:19.994842 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9512 18:02:20.001000 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9513 18:02:20.004814 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9514 18:02:20.007700 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9515 18:02:20.011048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9516 18:02:20.018073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9517 18:02:20.021019 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9518 18:02:20.024918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9519 18:02:20.027658 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9520 18:02:20.034308 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9521 18:02:20.037729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9522 18:02:20.041139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9523 18:02:20.047901 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9524 18:02:20.051477 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9525 18:02:20.054638 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9526 18:02:20.061347 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9527 18:02:20.064401 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9528 18:02:20.071079 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9529 18:02:20.074751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9530 18:02:20.077549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9531 18:02:20.084203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9532 18:02:20.087693 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9533 18:02:20.094512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9534 18:02:20.097535 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9535 18:02:20.104176 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9536 18:02:20.107735 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9537 18:02:20.110932 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9538 18:02:20.117433 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9539 18:02:20.120727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9540 18:02:20.127736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9541 18:02:20.131112 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9542 18:02:20.134301 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9543 18:02:20.140871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9544 18:02:20.144696 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9545 18:02:20.150833 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9546 18:02:20.154102 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9547 18:02:20.157345 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9548 18:02:20.163950 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9549 18:02:20.167079 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9550 18:02:20.174659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9551 18:02:20.177588 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9552 18:02:20.184010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9553 18:02:20.187062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9554 18:02:20.190951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9555 18:02:20.197412 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9556 18:02:20.200806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9557 18:02:20.206902 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9558 18:02:20.210453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9559 18:02:20.214046 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9560 18:02:20.220747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9561 18:02:20.223562 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9562 18:02:20.230443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9563 18:02:20.233651 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9564 18:02:20.237163 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9565 18:02:20.243922 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9566 18:02:20.247145 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9567 18:02:20.253810 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9568 18:02:20.257141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9569 18:02:20.263529 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9570 18:02:20.267114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9571 18:02:20.270121 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9572 18:02:20.276654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9573 18:02:20.280358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9574 18:02:20.286844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9575 18:02:20.290033 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9576 18:02:20.293640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9577 18:02:20.300188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9578 18:02:20.303186 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9579 18:02:20.309534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9580 18:02:20.313037 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9581 18:02:20.316251 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9582 18:02:20.322906 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9583 18:02:20.326514 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9584 18:02:20.332924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9585 18:02:20.336016 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9586 18:02:20.339654 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9587 18:02:20.346407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9588 18:02:20.349282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9589 18:02:20.356113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9590 18:02:20.359444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9591 18:02:20.366106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9592 18:02:20.369523 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9593 18:02:20.372281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9594 18:02:20.378948 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9595 18:02:20.382373 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9596 18:02:20.388980 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9597 18:02:20.392782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9598 18:02:20.399228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9599 18:02:20.402270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9600 18:02:20.408961 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9601 18:02:20.412290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9602 18:02:20.415236 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9603 18:02:20.422045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9604 18:02:20.425752 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9605 18:02:20.431851 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9606 18:02:20.435311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9607 18:02:20.442444 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9608 18:02:20.445473 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9609 18:02:20.449026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9610 18:02:20.454914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9611 18:02:20.458835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9612 18:02:20.465072 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9613 18:02:20.468095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9614 18:02:20.475267 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9615 18:02:20.478780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9616 18:02:20.485200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9617 18:02:20.488469 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9618 18:02:20.491821 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9619 18:02:20.498603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9620 18:02:20.501489 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9621 18:02:20.508299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9622 18:02:20.511583 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9623 18:02:20.518378 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9624 18:02:20.521168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9625 18:02:20.524900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9626 18:02:20.531460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9627 18:02:20.534433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9628 18:02:20.541168 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9629 18:02:20.544303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9630 18:02:20.551057 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9631 18:02:20.554607 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9632 18:02:20.561322 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9633 18:02:20.564335 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9634 18:02:20.567796 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9635 18:02:20.574576 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9636 18:02:20.577732 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9637 18:02:20.584096 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9638 18:02:20.587772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9639 18:02:20.594245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9640 18:02:20.597726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9641 18:02:20.604143 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9642 18:02:20.607197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9643 18:02:20.610953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9644 18:02:20.617560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9645 18:02:20.620699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9646 18:02:20.627521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9647 18:02:20.630439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9648 18:02:20.636967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9649 18:02:20.640686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9650 18:02:20.643556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9651 18:02:20.650398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9652 18:02:20.653775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9653 18:02:20.660385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9654 18:02:20.663638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9655 18:02:20.670753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9656 18:02:20.673665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9657 18:02:20.680555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9658 18:02:20.683045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9659 18:02:20.689853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9660 18:02:20.693620 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9661 18:02:20.699954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9662 18:02:20.702971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9663 18:02:20.709977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9664 18:02:20.712939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9665 18:02:20.719735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9666 18:02:20.723124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9667 18:02:20.729802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9668 18:02:20.732688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9669 18:02:20.739527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9670 18:02:20.742862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9671 18:02:20.749840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9672 18:02:20.753146 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9673 18:02:20.760246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9674 18:02:20.762831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9675 18:02:20.769702 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9676 18:02:20.770209 INFO: [APUAPC] vio 0
9677 18:02:20.776717 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9678 18:02:20.779980 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9679 18:02:20.782943 INFO: [APUAPC] D0_APC_0: 0x400510
9680 18:02:20.786315 INFO: [APUAPC] D0_APC_1: 0x0
9681 18:02:20.789851 INFO: [APUAPC] D0_APC_2: 0x1540
9682 18:02:20.793016 INFO: [APUAPC] D0_APC_3: 0x0
9683 18:02:20.796482 INFO: [APUAPC] D1_APC_0: 0xffffffff
9684 18:02:20.799870 INFO: [APUAPC] D1_APC_1: 0xffffffff
9685 18:02:20.803177 INFO: [APUAPC] D1_APC_2: 0x3fffff
9686 18:02:20.806476 INFO: [APUAPC] D1_APC_3: 0x0
9687 18:02:20.809479 INFO: [APUAPC] D2_APC_0: 0xffffffff
9688 18:02:20.813123 INFO: [APUAPC] D2_APC_1: 0xffffffff
9689 18:02:20.816352 INFO: [APUAPC] D2_APC_2: 0x3fffff
9690 18:02:20.819634 INFO: [APUAPC] D2_APC_3: 0x0
9691 18:02:20.822614 INFO: [APUAPC] D3_APC_0: 0xffffffff
9692 18:02:20.826061 INFO: [APUAPC] D3_APC_1: 0xffffffff
9693 18:02:20.829721 INFO: [APUAPC] D3_APC_2: 0x3fffff
9694 18:02:20.833084 INFO: [APUAPC] D3_APC_3: 0x0
9695 18:02:20.836100 INFO: [APUAPC] D4_APC_0: 0xffffffff
9696 18:02:20.840044 INFO: [APUAPC] D4_APC_1: 0xffffffff
9697 18:02:20.842811 INFO: [APUAPC] D4_APC_2: 0x3fffff
9698 18:02:20.843242 INFO: [APUAPC] D4_APC_3: 0x0
9699 18:02:20.849623 INFO: [APUAPC] D5_APC_0: 0xffffffff
9700 18:02:20.852792 INFO: [APUAPC] D5_APC_1: 0xffffffff
9701 18:02:20.856097 INFO: [APUAPC] D5_APC_2: 0x3fffff
9702 18:02:20.856605 INFO: [APUAPC] D5_APC_3: 0x0
9703 18:02:20.859090 INFO: [APUAPC] D6_APC_0: 0xffffffff
9704 18:02:20.865749 INFO: [APUAPC] D6_APC_1: 0xffffffff
9705 18:02:20.869763 INFO: [APUAPC] D6_APC_2: 0x3fffff
9706 18:02:20.870326 INFO: [APUAPC] D6_APC_3: 0x0
9707 18:02:20.872688 INFO: [APUAPC] D7_APC_0: 0xffffffff
9708 18:02:20.876353 INFO: [APUAPC] D7_APC_1: 0xffffffff
9709 18:02:20.879167 INFO: [APUAPC] D7_APC_2: 0x3fffff
9710 18:02:20.883108 INFO: [APUAPC] D7_APC_3: 0x0
9711 18:02:20.885868 INFO: [APUAPC] D8_APC_0: 0xffffffff
9712 18:02:20.889285 INFO: [APUAPC] D8_APC_1: 0xffffffff
9713 18:02:20.893016 INFO: [APUAPC] D8_APC_2: 0x3fffff
9714 18:02:20.895940 INFO: [APUAPC] D8_APC_3: 0x0
9715 18:02:20.899242 INFO: [APUAPC] D9_APC_0: 0xffffffff
9716 18:02:20.902298 INFO: [APUAPC] D9_APC_1: 0xffffffff
9717 18:02:20.906073 INFO: [APUAPC] D9_APC_2: 0x3fffff
9718 18:02:20.909145 INFO: [APUAPC] D9_APC_3: 0x0
9719 18:02:20.912370 INFO: [APUAPC] D10_APC_0: 0xffffffff
9720 18:02:20.915623 INFO: [APUAPC] D10_APC_1: 0xffffffff
9721 18:02:20.919101 INFO: [APUAPC] D10_APC_2: 0x3fffff
9722 18:02:20.922543 INFO: [APUAPC] D10_APC_3: 0x0
9723 18:02:20.925693 INFO: [APUAPC] D11_APC_0: 0xffffffff
9724 18:02:20.928818 INFO: [APUAPC] D11_APC_1: 0xffffffff
9725 18:02:20.932322 INFO: [APUAPC] D11_APC_2: 0x3fffff
9726 18:02:20.935529 INFO: [APUAPC] D11_APC_3: 0x0
9727 18:02:20.938776 INFO: [APUAPC] D12_APC_0: 0xffffffff
9728 18:02:20.942383 INFO: [APUAPC] D12_APC_1: 0xffffffff
9729 18:02:20.945576 INFO: [APUAPC] D12_APC_2: 0x3fffff
9730 18:02:20.948583 INFO: [APUAPC] D12_APC_3: 0x0
9731 18:02:20.952224 INFO: [APUAPC] D13_APC_0: 0xffffffff
9732 18:02:20.955703 INFO: [APUAPC] D13_APC_1: 0xffffffff
9733 18:02:20.958603 INFO: [APUAPC] D13_APC_2: 0x3fffff
9734 18:02:20.962268 INFO: [APUAPC] D13_APC_3: 0x0
9735 18:02:20.965189 INFO: [APUAPC] D14_APC_0: 0xffffffff
9736 18:02:20.969066 INFO: [APUAPC] D14_APC_1: 0xffffffff
9737 18:02:20.971751 INFO: [APUAPC] D14_APC_2: 0x3fffff
9738 18:02:20.975401 INFO: [APUAPC] D14_APC_3: 0x0
9739 18:02:20.978286 INFO: [APUAPC] D15_APC_0: 0xffffffff
9740 18:02:20.981833 INFO: [APUAPC] D15_APC_1: 0xffffffff
9741 18:02:20.985444 INFO: [APUAPC] D15_APC_2: 0x3fffff
9742 18:02:20.988531 INFO: [APUAPC] D15_APC_3: 0x0
9743 18:02:20.992272 INFO: [APUAPC] APC_CON: 0x4
9744 18:02:20.995235 INFO: [NOCDAPC] D0_APC_0: 0x0
9745 18:02:20.998181 INFO: [NOCDAPC] D0_APC_1: 0x0
9746 18:02:21.001696 INFO: [NOCDAPC] D1_APC_0: 0x0
9747 18:02:21.005420 INFO: [NOCDAPC] D1_APC_1: 0xfff
9748 18:02:21.008209 INFO: [NOCDAPC] D2_APC_0: 0x0
9749 18:02:21.012847 INFO: [NOCDAPC] D2_APC_1: 0xfff
9750 18:02:21.013249 INFO: [NOCDAPC] D3_APC_0: 0x0
9751 18:02:21.015152 INFO: [NOCDAPC] D3_APC_1: 0xfff
9752 18:02:21.018379 INFO: [NOCDAPC] D4_APC_0: 0x0
9753 18:02:21.021708 INFO: [NOCDAPC] D4_APC_1: 0xfff
9754 18:02:21.024986 INFO: [NOCDAPC] D5_APC_0: 0x0
9755 18:02:21.028215 INFO: [NOCDAPC] D5_APC_1: 0xfff
9756 18:02:21.031430 INFO: [NOCDAPC] D6_APC_0: 0x0
9757 18:02:21.035113 INFO: [NOCDAPC] D6_APC_1: 0xfff
9758 18:02:21.038213 INFO: [NOCDAPC] D7_APC_0: 0x0
9759 18:02:21.041523 INFO: [NOCDAPC] D7_APC_1: 0xfff
9760 18:02:21.044778 INFO: [NOCDAPC] D8_APC_0: 0x0
9761 18:02:21.045169 INFO: [NOCDAPC] D8_APC_1: 0xfff
9762 18:02:21.048384 INFO: [NOCDAPC] D9_APC_0: 0x0
9763 18:02:21.051235 INFO: [NOCDAPC] D9_APC_1: 0xfff
9764 18:02:21.055277 INFO: [NOCDAPC] D10_APC_0: 0x0
9765 18:02:21.058283 INFO: [NOCDAPC] D10_APC_1: 0xfff
9766 18:02:21.061801 INFO: [NOCDAPC] D11_APC_0: 0x0
9767 18:02:21.064730 INFO: [NOCDAPC] D11_APC_1: 0xfff
9768 18:02:21.068268 INFO: [NOCDAPC] D12_APC_0: 0x0
9769 18:02:21.071364 INFO: [NOCDAPC] D12_APC_1: 0xfff
9770 18:02:21.075008 INFO: [NOCDAPC] D13_APC_0: 0x0
9771 18:02:21.077982 INFO: [NOCDAPC] D13_APC_1: 0xfff
9772 18:02:21.081102 INFO: [NOCDAPC] D14_APC_0: 0x0
9773 18:02:21.084676 INFO: [NOCDAPC] D14_APC_1: 0xfff
9774 18:02:21.088179 INFO: [NOCDAPC] D15_APC_0: 0x0
9775 18:02:21.088844 INFO: [NOCDAPC] D15_APC_1: 0xfff
9776 18:02:21.091439 INFO: [NOCDAPC] APC_CON: 0x4
9777 18:02:21.094885 INFO: [APUAPC] set_apusys_apc done
9778 18:02:21.097907 INFO: [DEVAPC] devapc_init done
9779 18:02:21.104578 INFO: GICv3 without legacy support detected.
9780 18:02:21.107882 INFO: ARM GICv3 driver initialized in EL3
9781 18:02:21.111359 INFO: Maximum SPI INTID supported: 639
9782 18:02:21.114644 INFO: BL31: Initializing runtime services
9783 18:02:21.121074 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9784 18:02:21.124721 INFO: SPM: enable CPC mode
9785 18:02:21.127670 INFO: mcdi ready for mcusys-off-idle and system suspend
9786 18:02:21.134666 INFO: BL31: Preparing for EL3 exit to normal world
9787 18:02:21.137902 INFO: Entry point address = 0x80000000
9788 18:02:21.138426 INFO: SPSR = 0x8
9789 18:02:21.144293
9790 18:02:21.144672
9791 18:02:21.144968
9792 18:02:21.147504 Starting depthcharge on Spherion...
9793 18:02:21.148110
9794 18:02:21.148497 Wipe memory regions:
9795 18:02:21.148800
9796 18:02:21.151389 end: 2.2.3 depthcharge-start (duration 00:00:18) [common]
9797 18:02:21.151884 start: 2.2.4 bootloader-commands (timeout 00:04:28) [common]
9798 18:02:21.152261 Setting prompt string to ['asurada:']
9799 18:02:21.152629 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:28)
9800 18:02:21.153234 [0x00000040000000, 0x00000054600000)
9801 18:02:21.273277
9802 18:02:21.273721 [0x00000054660000, 0x00000080000000)
9803 18:02:21.534196
9804 18:02:21.534742 [0x000000821a7280, 0x000000ffe64000)
9805 18:02:22.278794
9806 18:02:22.279302 [0x00000100000000, 0x00000140000000)
9807 18:02:22.659935
9808 18:02:22.663268 Initializing XHCI USB controller at 0x11200000.
9809 18:02:23.702556
9810 18:02:23.705818 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9811 18:02:23.706351
9812 18:02:23.706773
9813 18:02:23.707536 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9815 18:02:23.808671 asurada: tftpboot 192.168.201.1 14291331/tftp-deploy-q2673t4g/kernel/image.itb 14291331/tftp-deploy-q2673t4g/kernel/cmdline
9816 18:02:23.809480 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9817 18:02:23.809999 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:25)
9818 18:02:23.814128 tftpboot 192.168.201.1 14291331/tftp-deploy-q2673t4g/kernel/image.itp-deploy-q2673t4g/kernel/cmdline
9819 18:02:23.814591
9820 18:02:23.814920 Waiting for link
9821 18:02:23.972514
9822 18:02:23.973003 R8152: Initializing
9823 18:02:23.973342
9824 18:02:23.975938 Version 9 (ocp_data = 6010)
9825 18:02:23.976451
9826 18:02:23.978827 R8152: Done initializing
9827 18:02:23.979251
9828 18:02:23.979574 Adding net device
9829 18:02:25.864218
9830 18:02:25.864663 done.
9831 18:02:25.864964
9832 18:02:25.865240 MAC: 00:e0:4c:68:03:bd
9833 18:02:25.865533
9834 18:02:25.867067 Sending DHCP discover... done.
9835 18:02:25.867447
9836 18:02:29.051688 Waiting for reply... done.
9837 18:02:29.052251
9838 18:02:29.052595 Sending DHCP request... done.
9839 18:02:29.054460
9840 18:02:29.054901 Waiting for reply... done.
9841 18:02:29.058208
9842 18:02:29.058688 My ip is 192.168.201.16
9843 18:02:29.059023
9844 18:02:29.061304 The DHCP server ip is 192.168.201.1
9845 18:02:29.061736
9846 18:02:29.064950 TFTP server IP predefined by user: 192.168.201.1
9847 18:02:29.065459
9848 18:02:29.071703 Bootfile predefined by user: 14291331/tftp-deploy-q2673t4g/kernel/image.itb
9849 18:02:29.072169
9850 18:02:29.074435 Sending tftp read request... done.
9851 18:02:29.074827
9852 18:02:29.084507 Waiting for the transfer...
9853 18:02:29.084941
9854 18:02:29.370846 00000000 ################################################################
9855 18:02:29.370970
9856 18:02:29.632915 00080000 ################################################################
9857 18:02:29.633046
9858 18:02:29.904603 00100000 ################################################################
9859 18:02:29.904732
9860 18:02:30.166377 00180000 ################################################################
9861 18:02:30.166493
9862 18:02:30.458239 00200000 ################################################################
9863 18:02:30.458376
9864 18:02:30.740839 00280000 ################################################################
9865 18:02:30.740967
9866 18:02:31.023600 00300000 ################################################################
9867 18:02:31.023720
9868 18:02:31.310461 00380000 ################################################################
9869 18:02:31.310594
9870 18:02:31.590902 00400000 ################################################################
9871 18:02:31.591029
9872 18:02:31.873573 00480000 ################################################################
9873 18:02:31.873699
9874 18:02:32.133075 00500000 ################################################################
9875 18:02:32.133201
9876 18:02:32.383852 00580000 ################################################################
9877 18:02:32.383999
9878 18:02:32.642662 00600000 ################################################################
9879 18:02:32.642791
9880 18:02:32.893034 00680000 ################################################################
9881 18:02:32.893148
9882 18:02:33.156734 00700000 ################################################################
9883 18:02:33.156891
9884 18:02:33.447908 00780000 ################################################################
9885 18:02:33.448042
9886 18:02:33.698479 00800000 ################################################################
9887 18:02:33.698583
9888 18:02:33.950251 00880000 ################################################################
9889 18:02:33.950371
9890 18:02:34.242283 00900000 ################################################################
9891 18:02:34.242405
9892 18:02:34.513228 00980000 ################################################################
9893 18:02:34.513351
9894 18:02:34.802707 00a00000 ################################################################
9895 18:02:34.802821
9896 18:02:35.091173 00a80000 ################################################################
9897 18:02:35.091299
9898 18:02:35.382258 00b00000 ################################################################
9899 18:02:35.382389
9900 18:02:35.650472 00b80000 ################################################################
9901 18:02:35.650599
9902 18:02:35.937522 00c00000 ################################################################
9903 18:02:35.937644
9904 18:02:36.204228 00c80000 ################################################################
9905 18:02:36.204345
9906 18:02:36.459520 00d00000 ################################################################
9907 18:02:36.459651
9908 18:02:36.717699 00d80000 ################################################################
9909 18:02:36.717822
9910 18:02:36.991261 00e00000 ################################################################
9911 18:02:36.991384
9912 18:02:37.250017 00e80000 ################################################################
9913 18:02:37.250142
9914 18:02:37.503477 00f00000 ################################################################
9915 18:02:37.503604
9916 18:02:37.794905 00f80000 ################################################################
9917 18:02:37.795027
9918 18:02:38.062189 01000000 ################################################################
9919 18:02:38.062326
9920 18:02:38.355384 01080000 ################################################################
9921 18:02:38.355510
9922 18:02:38.642126 01100000 ################################################################
9923 18:02:38.642252
9924 18:02:38.922033 01180000 ################################################################
9925 18:02:38.922141
9926 18:02:39.203352 01200000 ################################################################
9927 18:02:39.203483
9928 18:02:39.485986 01280000 ################################################################
9929 18:02:39.486112
9930 18:02:39.778558 01300000 ################################################################
9931 18:02:39.778687
9932 18:02:40.040496 01380000 ################################################################
9933 18:02:40.040623
9934 18:02:40.290081 01400000 ################################################################
9935 18:02:40.290238
9936 18:02:40.549809 01480000 ################################################################
9937 18:02:40.549932
9938 18:02:40.824225 01500000 ################################################################
9939 18:02:40.824361
9940 18:02:41.177296 01580000 ################################################################
9941 18:02:41.177753
9942 18:02:41.575694 01600000 ################################################################
9943 18:02:41.576175
9944 18:02:41.980857 01680000 ################################################################
9945 18:02:41.981306
9946 18:02:42.374107 01700000 ################################################################
9947 18:02:42.374869
9948 18:02:42.661911 01780000 ################################################################
9949 18:02:42.662057
9950 18:02:42.937337 01800000 ################################################################
9951 18:02:42.937488
9952 18:02:43.204987 01880000 ################################################################
9953 18:02:43.205113
9954 18:02:43.485861 01900000 ################################################################
9955 18:02:43.485986
9956 18:02:43.762720 01980000 ################################################################
9957 18:02:43.762846
9958 18:02:44.050375 01a00000 ################################################################
9959 18:02:44.050504
9960 18:02:44.305268 01a80000 ################################################################
9961 18:02:44.305402
9962 18:02:44.555783 01b00000 ################################################################
9963 18:02:44.555909
9964 18:02:44.805558 01b80000 ################################################################
9965 18:02:44.805687
9966 18:02:45.056081 01c00000 ################################################################
9967 18:02:45.056209
9968 18:02:45.316602 01c80000 ################################################################
9969 18:02:45.316729
9970 18:02:45.581346 01d00000 ################################################################
9971 18:02:45.581502
9972 18:02:45.852601 01d80000 ################################################################
9973 18:02:45.852729
9974 18:02:46.081690 01e00000 ####################################################### done.
9975 18:02:46.081822
9976 18:02:46.084859 The bootfile was 31907190 bytes long.
9977 18:02:46.084952
9978 18:02:46.088437 Sending tftp read request... done.
9979 18:02:46.088514
9980 18:02:46.088572 Waiting for the transfer...
9981 18:02:46.088625
9982 18:02:46.091522 00000000 # done.
9983 18:02:46.091599
9984 18:02:46.098231 Command line loaded dynamically from TFTP file: 14291331/tftp-deploy-q2673t4g/kernel/cmdline
9985 18:02:46.098346
9986 18:02:46.121780 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
9987 18:02:46.122002
9988 18:02:46.122111 Loading FIT.
9989 18:02:46.122205
9990 18:02:46.124495 Image ramdisk-1 has 18732804 bytes.
9991 18:02:46.124640
9992 18:02:46.127993 Image fdt-1 has 47258 bytes.
9993 18:02:46.128151
9994 18:02:46.131412 Image kernel-1 has 13125101 bytes.
9995 18:02:46.131570
9996 18:02:46.141337 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9997 18:02:46.141636
9998 18:02:46.158661 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9999 18:02:46.159183
10000 18:02:46.165199 Choosing best match conf-1 for compat google,spherion-rev3.
10001 18:02:46.165706
10002 18:02:46.172652 Connected to device vid:did:rid of 1ae0:0028:00
10003 18:02:46.179433
10004 18:02:46.183002 tpm_get_response: command 0x17b, return code 0x0
10005 18:02:46.183512
10006 18:02:46.185921 ec_init: CrosEC protocol v3 supported (256, 248)
10007 18:02:46.190205
10008 18:02:46.193419 tpm_cleanup: add release locality here.
10009 18:02:46.193936
10010 18:02:46.197061 Shutting down all USB controllers.
10011 18:02:46.197505
10012 18:02:46.197936 Removing current net device
10013 18:02:46.198468
10014 18:02:46.203996 Exiting depthcharge with code 4 at timestamp: 53259118
10015 18:02:46.204608
10016 18:02:46.206760 LZMA decompressing kernel-1 to 0x821a6718
10017 18:02:46.207244
10018 18:02:46.210366 LZMA decompressing kernel-1 to 0x40000000
10019 18:02:47.826437
10020 18:02:47.826590 jumping to kernel
10021 18:02:47.827059 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10022 18:02:47.827148 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10023 18:02:47.827224 Setting prompt string to ['Linux version [0-9]']
10024 18:02:47.827286 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 18:02:47.827347 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10026 18:02:47.876998
10027 18:02:47.880360 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10028 18:02:47.884308 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10029 18:02:47.884750 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10030 18:02:47.885044 Setting prompt string to []
10031 18:02:47.885361 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10032 18:02:47.885699 Using line separator: #'\n'#
10033 18:02:47.885998 No login prompt set.
10034 18:02:47.886407 Parsing kernel messages
10035 18:02:47.886698 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10036 18:02:47.887174 [login-action] Waiting for messages, (timeout 00:04:01)
10037 18:02:47.887496 Waiting using forced prompt support (timeout 00:02:01)
10038 18:02:47.903964 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10039 18:02:47.906924 [ 0.000000] random: crng init done
10040 18:02:47.913594 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10041 18:02:47.916544 [ 0.000000] efi: UEFI not found.
10042 18:02:47.923163 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10043 18:02:47.933190 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10044 18:02:47.940256 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10045 18:02:47.950017 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10046 18:02:47.956488 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10047 18:02:47.962757 [ 0.000000] printk: bootconsole [mtk8250] enabled
10048 18:02:47.969556 [ 0.000000] NUMA: No NUMA configuration found
10049 18:02:47.976263 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10050 18:02:47.982813 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10051 18:02:47.983330 [ 0.000000] Zone ranges:
10052 18:02:47.989244 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10053 18:02:47.993051 [ 0.000000] DMA32 empty
10054 18:02:47.999468 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10055 18:02:48.002734 [ 0.000000] Movable zone start for each node
10056 18:02:48.006012 [ 0.000000] Early memory node ranges
10057 18:02:48.012846 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10058 18:02:48.018873 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10059 18:02:48.025672 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10060 18:02:48.031950 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10061 18:02:48.039084 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10062 18:02:48.045049 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10063 18:02:48.075787 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10064 18:02:48.082361 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10065 18:02:48.088660 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10066 18:02:48.091944 [ 0.000000] psci: probing for conduit method from DT.
10067 18:02:48.098784 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10068 18:02:48.101944 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10069 18:02:48.109041 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10070 18:02:48.111920 [ 0.000000] psci: SMC Calling Convention v1.2
10071 18:02:48.118778 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10072 18:02:48.121696 [ 0.000000] Detected VIPT I-cache on CPU0
10073 18:02:48.128100 [ 0.000000] CPU features: detected: GIC system register CPU interface
10074 18:02:48.134755 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10075 18:02:48.141918 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10076 18:02:48.148545 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10077 18:02:48.158450 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10078 18:02:48.164945 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10079 18:02:48.167985 [ 0.000000] alternatives: applying boot alternatives
10080 18:02:48.174805 [ 0.000000] Fallback order for Node 0: 0
10081 18:02:48.181186 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10082 18:02:48.184792 [ 0.000000] Policy zone: Normal
10083 18:02:48.207545 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10084 18:02:48.217349 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10085 18:02:48.227086 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10086 18:02:48.233788 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10087 18:02:48.240592 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10088 18:02:48.247787 <6>[ 0.000000] software IO TLB: area num 8.
10089 18:02:48.302874 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10090 18:02:48.383690 <6>[ 0.000000] Memory: 3831356K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 327108K reserved, 32768K cma-reserved)
10091 18:02:48.390089 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10092 18:02:48.396893 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10093 18:02:48.399862 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10094 18:02:48.406428 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10095 18:02:48.413133 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10096 18:02:48.416758 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10097 18:02:48.426202 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10098 18:02:48.433071 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10099 18:02:48.439402 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10100 18:02:48.446401 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10101 18:02:48.449614 <6>[ 0.000000] GICv3: 608 SPIs implemented
10102 18:02:48.452977 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10103 18:02:48.459681 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10104 18:02:48.462601 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10105 18:02:48.469399 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10106 18:02:48.482147 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10107 18:02:48.495155 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10108 18:02:48.501650 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10109 18:02:48.509466 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10110 18:02:48.522786 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10111 18:02:48.529339 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10112 18:02:48.536507 <6>[ 0.009176] Console: colour dummy device 80x25
10113 18:02:48.546178 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10114 18:02:48.552663 <6>[ 0.024373] pid_max: default: 32768 minimum: 301
10115 18:02:48.556230 <6>[ 0.029275] LSM: Security Framework initializing
10116 18:02:48.563055 <6>[ 0.034217] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10117 18:02:48.572579 <6>[ 0.041825] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10118 18:02:48.579185 <6>[ 0.051057] cblist_init_generic: Setting adjustable number of callback queues.
10119 18:02:48.585982 <6>[ 0.058501] cblist_init_generic: Setting shift to 3 and lim to 1.
10120 18:02:48.596168 <6>[ 0.064879] cblist_init_generic: Setting adjustable number of callback queues.
10121 18:02:48.602373 <6>[ 0.072306] cblist_init_generic: Setting shift to 3 and lim to 1.
10122 18:02:48.605768 <6>[ 0.078705] rcu: Hierarchical SRCU implementation.
10123 18:02:48.612315 <6>[ 0.083720] rcu: Max phase no-delay instances is 1000.
10124 18:02:48.618606 <6>[ 0.090754] EFI services will not be available.
10125 18:02:48.622191 <6>[ 0.095706] smp: Bringing up secondary CPUs ...
10126 18:02:48.630421 <6>[ 0.100781] Detected VIPT I-cache on CPU1
10127 18:02:48.636973 <6>[ 0.100850] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10128 18:02:48.643392 <6>[ 0.100880] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10129 18:02:48.647008 <6>[ 0.101218] Detected VIPT I-cache on CPU2
10130 18:02:48.653719 <6>[ 0.101270] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10131 18:02:48.660195 <6>[ 0.101288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10132 18:02:48.666486 <6>[ 0.101548] Detected VIPT I-cache on CPU3
10133 18:02:48.673280 <6>[ 0.101595] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10134 18:02:48.680001 <6>[ 0.101608] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10135 18:02:48.683482 <6>[ 0.101910] CPU features: detected: Spectre-v4
10136 18:02:48.690002 <6>[ 0.101915] CPU features: detected: Spectre-BHB
10137 18:02:48.692914 <6>[ 0.101920] Detected PIPT I-cache on CPU4
10138 18:02:48.699589 <6>[ 0.101981] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10139 18:02:48.706404 <6>[ 0.101998] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10140 18:02:48.712992 <6>[ 0.102288] Detected PIPT I-cache on CPU5
10141 18:02:48.719139 <6>[ 0.102351] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10142 18:02:48.726099 <6>[ 0.102367] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10143 18:02:48.729370 <6>[ 0.102649] Detected PIPT I-cache on CPU6
10144 18:02:48.736278 <6>[ 0.102710] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10145 18:02:48.742497 <6>[ 0.102727] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10146 18:02:48.749019 <6>[ 0.103026] Detected PIPT I-cache on CPU7
10147 18:02:48.755362 <6>[ 0.103092] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10148 18:02:48.762576 <6>[ 0.103108] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10149 18:02:48.765723 <6>[ 0.103155] smp: Brought up 1 node, 8 CPUs
10150 18:02:48.772205 <6>[ 0.244519] SMP: Total of 8 processors activated.
10151 18:02:48.775676 <6>[ 0.249470] CPU features: detected: 32-bit EL0 Support
10152 18:02:48.785661 <6>[ 0.254867] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10153 18:02:48.791736 <6>[ 0.263667] CPU features: detected: Common not Private translations
10154 18:02:48.798506 <6>[ 0.270143] CPU features: detected: CRC32 instructions
10155 18:02:48.805474 <6>[ 0.275527] CPU features: detected: RCpc load-acquire (LDAPR)
10156 18:02:48.808301 <6>[ 0.281524] CPU features: detected: LSE atomic instructions
10157 18:02:48.815189 <6>[ 0.287342] CPU features: detected: Privileged Access Never
10158 18:02:48.821765 <6>[ 0.293121] CPU features: detected: RAS Extension Support
10159 18:02:48.828132 <6>[ 0.298765] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10160 18:02:48.831670 <6>[ 0.305983] CPU: All CPU(s) started at EL2
10161 18:02:48.838630 <6>[ 0.310300] alternatives: applying system-wide alternatives
10162 18:02:48.847364 <6>[ 0.320248] devtmpfs: initialized
10163 18:02:48.862137 <6>[ 0.328539] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10164 18:02:48.869233 <6>[ 0.338498] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10165 18:02:48.875267 <6>[ 0.346525] pinctrl core: initialized pinctrl subsystem
10166 18:02:48.878631 <6>[ 0.353217] DMI not present or invalid.
10167 18:02:48.884967 <6>[ 0.357624] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10168 18:02:48.895064 <6>[ 0.364475] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10169 18:02:48.901529 <6>[ 0.371922] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10170 18:02:48.911747 <6>[ 0.380014] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10171 18:02:48.914897 <6>[ 0.388169] audit: initializing netlink subsys (disabled)
10172 18:02:48.924583 <5>[ 0.393866] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10173 18:02:48.931573 <6>[ 0.394581] thermal_sys: Registered thermal governor 'step_wise'
10174 18:02:48.937868 <6>[ 0.401830] thermal_sys: Registered thermal governor 'power_allocator'
10175 18:02:48.940964 <6>[ 0.408083] cpuidle: using governor menu
10176 18:02:48.947387 <6>[ 0.419042] NET: Registered PF_QIPCRTR protocol family
10177 18:02:48.954016 <6>[ 0.424526] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10178 18:02:48.960608 <6>[ 0.431627] ASID allocator initialised with 32768 entries
10179 18:02:48.964093 <6>[ 0.438195] Serial: AMBA PL011 UART driver
10180 18:02:48.974053 <4>[ 0.447071] Trying to register duplicate clock ID: 134
10181 18:02:49.034466 <6>[ 0.510236] KASLR enabled
10182 18:02:49.048381 <6>[ 0.517945] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10183 18:02:49.054925 <6>[ 0.524958] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10184 18:02:49.062003 <6>[ 0.531448] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10185 18:02:49.068216 <6>[ 0.538453] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10186 18:02:49.074679 <6>[ 0.544940] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10187 18:02:49.081629 <6>[ 0.551944] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10188 18:02:49.087740 <6>[ 0.558431] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10189 18:02:49.094139 <6>[ 0.565436] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10190 18:02:49.097892 <6>[ 0.572882] ACPI: Interpreter disabled.
10191 18:02:49.106571 <6>[ 0.579342] iommu: Default domain type: Translated
10192 18:02:49.113116 <6>[ 0.584456] iommu: DMA domain TLB invalidation policy: strict mode
10193 18:02:49.116366 <5>[ 0.591118] SCSI subsystem initialized
10194 18:02:49.123071 <6>[ 0.595370] usbcore: registered new interface driver usbfs
10195 18:02:49.129264 <6>[ 0.601101] usbcore: registered new interface driver hub
10196 18:02:49.132844 <6>[ 0.606650] usbcore: registered new device driver usb
10197 18:02:49.139540 <6>[ 0.612766] pps_core: LinuxPPS API ver. 1 registered
10198 18:02:49.149800 <6>[ 0.617960] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10199 18:02:49.152641 <6>[ 0.627302] PTP clock support registered
10200 18:02:49.156126 <6>[ 0.631545] EDAC MC: Ver: 3.0.0
10201 18:02:49.163545 <6>[ 0.636694] FPGA manager framework
10202 18:02:49.170311 <6>[ 0.640373] Advanced Linux Sound Architecture Driver Initialized.
10203 18:02:49.173762 <6>[ 0.647151] vgaarb: loaded
10204 18:02:49.180310 <6>[ 0.650303] clocksource: Switched to clocksource arch_sys_counter
10205 18:02:49.183343 <5>[ 0.656745] VFS: Disk quotas dquot_6.6.0
10206 18:02:49.190299 <6>[ 0.660930] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10207 18:02:49.193494 <6>[ 0.668123] pnp: PnP ACPI: disabled
10208 18:02:49.202243 <6>[ 0.674860] NET: Registered PF_INET protocol family
10209 18:02:49.208593 <6>[ 0.680248] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10210 18:02:49.220714 <6>[ 0.690277] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10211 18:02:49.230303 <6>[ 0.699064] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10212 18:02:49.236948 <6>[ 0.707030] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10213 18:02:49.243920 <6>[ 0.715433] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10214 18:02:49.254745 <6>[ 0.724085] TCP: Hash tables configured (established 32768 bind 32768)
10215 18:02:49.261614 <6>[ 0.730941] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10216 18:02:49.267535 <6>[ 0.737961] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10217 18:02:49.274546 <6>[ 0.745485] NET: Registered PF_UNIX/PF_LOCAL protocol family
10218 18:02:49.281032 <6>[ 0.751635] RPC: Registered named UNIX socket transport module.
10219 18:02:49.284018 <6>[ 0.757790] RPC: Registered udp transport module.
10220 18:02:49.290582 <6>[ 0.762725] RPC: Registered tcp transport module.
10221 18:02:49.297288 <6>[ 0.767655] RPC: Registered tcp NFSv4.1 backchannel transport module.
10222 18:02:49.300303 <6>[ 0.774322] PCI: CLS 0 bytes, default 64
10223 18:02:49.303866 <6>[ 0.778655] Unpacking initramfs...
10224 18:02:49.328579 <6>[ 0.798390] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10225 18:02:49.338678 <6>[ 0.807037] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10226 18:02:49.341697 <6>[ 0.815862] kvm [1]: IPA Size Limit: 40 bits
10227 18:02:49.348497 <6>[ 0.820391] kvm [1]: GICv3: no GICV resource entry
10228 18:02:49.351648 <6>[ 0.825415] kvm [1]: disabling GICv2 emulation
10229 18:02:49.358452 <6>[ 0.830111] kvm [1]: GIC system register CPU interface enabled
10230 18:02:49.361846 <6>[ 0.836270] kvm [1]: vgic interrupt IRQ18
10231 18:02:49.368802 <6>[ 0.840621] kvm [1]: VHE mode initialized successfully
10232 18:02:49.374691 <5>[ 0.847030] Initialise system trusted keyrings
10233 18:02:49.381215 <6>[ 0.851860] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10234 18:02:49.388989 <6>[ 0.861938] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10235 18:02:49.395574 <5>[ 0.868352] NFS: Registering the id_resolver key type
10236 18:02:49.398567 <5>[ 0.873647] Key type id_resolver registered
10237 18:02:49.405174 <5>[ 0.878062] Key type id_legacy registered
10238 18:02:49.411899 <6>[ 0.882343] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10239 18:02:49.418395 <6>[ 0.889264] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10240 18:02:49.425026 <6>[ 0.896959] 9p: Installing v9fs 9p2000 file system support
10241 18:02:49.460482 <5>[ 0.933386] Key type asymmetric registered
10242 18:02:49.463617 <5>[ 0.937717] Asymmetric key parser 'x509' registered
10243 18:02:49.473399 <6>[ 0.942869] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10244 18:02:49.476828 <6>[ 0.950490] io scheduler mq-deadline registered
10245 18:02:49.480431 <6>[ 0.955252] io scheduler kyber registered
10246 18:02:49.499353 <6>[ 0.972244] EINJ: ACPI disabled.
10247 18:02:49.532733 <4>[ 0.998586] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10248 18:02:49.541867 <4>[ 1.009217] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10249 18:02:49.556719 <6>[ 1.029971] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10250 18:02:49.564618 <6>[ 1.037848] printk: console [ttyS0] disabled
10251 18:02:49.592995 <6>[ 1.062473] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10252 18:02:49.599775 <6>[ 1.071949] printk: console [ttyS0] enabled
10253 18:02:49.602628 <6>[ 1.071949] printk: console [ttyS0] enabled
10254 18:02:49.609455 <6>[ 1.080843] printk: bootconsole [mtk8250] disabled
10255 18:02:49.612937 <6>[ 1.080843] printk: bootconsole [mtk8250] disabled
10256 18:02:49.619356 <6>[ 1.091877] SuperH (H)SCI(F) driver initialized
10257 18:02:49.622263 <6>[ 1.097147] msm_serial: driver initialized
10258 18:02:49.636780 <6>[ 1.106082] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10259 18:02:49.646365 <6>[ 1.114632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10260 18:02:49.652729 <6>[ 1.123175] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10261 18:02:49.662765 <6>[ 1.131803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10262 18:02:49.673038 <6>[ 1.140511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10263 18:02:49.679347 <6>[ 1.149224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10264 18:02:49.688994 <6>[ 1.157764] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10265 18:02:49.696149 <6>[ 1.166568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10266 18:02:49.706286 <6>[ 1.175113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10267 18:02:49.717582 <6>[ 1.190598] loop: module loaded
10268 18:02:49.724276 <6>[ 1.196440] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10269 18:02:49.746366 <4>[ 1.219545] mtk-pmic-keys: Failed to locate of_node [id: -1]
10270 18:02:49.753094 <6>[ 1.226344] megasas: 07.719.03.00-rc1
10271 18:02:49.763368 <6>[ 1.236158] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10272 18:02:49.772933 <6>[ 1.245687] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10273 18:02:49.789638 <6>[ 1.262436] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10274 18:02:49.845852 <6>[ 1.312189] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10275 18:02:50.093283 <6>[ 1.566239] Freeing initrd memory: 18288K
10276 18:02:50.105239 <6>[ 1.577885] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10277 18:02:50.116387 <6>[ 1.588836] tun: Universal TUN/TAP device driver, 1.6
10278 18:02:50.119162 <6>[ 1.594903] thunder_xcv, ver 1.0
10279 18:02:50.122750 <6>[ 1.598405] thunder_bgx, ver 1.0
10280 18:02:50.125696 <6>[ 1.601898] nicpf, ver 1.0
10281 18:02:50.136240 <6>[ 1.605934] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10282 18:02:50.139596 <6>[ 1.613410] hns3: Copyright (c) 2017 Huawei Corporation.
10283 18:02:50.145820 <6>[ 1.618999] hclge is initializing
10284 18:02:50.149427 <6>[ 1.622575] e1000: Intel(R) PRO/1000 Network Driver
10285 18:02:50.155985 <6>[ 1.627704] e1000: Copyright (c) 1999-2006 Intel Corporation.
10286 18:02:50.159696 <6>[ 1.633716] e1000e: Intel(R) PRO/1000 Network Driver
10287 18:02:50.166506 <6>[ 1.638931] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10288 18:02:50.172796 <6>[ 1.645116] igb: Intel(R) Gigabit Ethernet Network Driver
10289 18:02:50.179429 <6>[ 1.650766] igb: Copyright (c) 2007-2014 Intel Corporation.
10290 18:02:50.185940 <6>[ 1.656602] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10291 18:02:50.192449 <6>[ 1.663120] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10292 18:02:50.195940 <6>[ 1.669581] sky2: driver version 1.30
10293 18:02:50.202422 <6>[ 1.674520] usbcore: registered new device driver r8152-cfgselector
10294 18:02:50.209505 <6>[ 1.681056] usbcore: registered new interface driver r8152
10295 18:02:50.215800 <6>[ 1.686872] VFIO - User Level meta-driver version: 0.3
10296 18:02:50.222655 <6>[ 1.695154] usbcore: registered new interface driver usb-storage
10297 18:02:50.228910 <6>[ 1.701597] usbcore: registered new device driver onboard-usb-hub
10298 18:02:50.237845 <6>[ 1.710773] mt6397-rtc mt6359-rtc: registered as rtc0
10299 18:02:50.248131 <6>[ 1.716241] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:02:50 UTC (1718128970)
10300 18:02:50.250829 <6>[ 1.725811] i2c_dev: i2c /dev entries driver
10301 18:02:50.264681 <4>[ 1.737938] cpu cpu0: supply cpu not found, using dummy regulator
10302 18:02:50.271531 <4>[ 1.744365] cpu cpu1: supply cpu not found, using dummy regulator
10303 18:02:50.278012 <4>[ 1.750784] cpu cpu2: supply cpu not found, using dummy regulator
10304 18:02:50.284584 <4>[ 1.757184] cpu cpu3: supply cpu not found, using dummy regulator
10305 18:02:50.291831 <4>[ 1.763578] cpu cpu4: supply cpu not found, using dummy regulator
10306 18:02:50.298522 <4>[ 1.769978] cpu cpu5: supply cpu not found, using dummy regulator
10307 18:02:50.304692 <4>[ 1.776373] cpu cpu6: supply cpu not found, using dummy regulator
10308 18:02:50.311577 <4>[ 1.782784] cpu cpu7: supply cpu not found, using dummy regulator
10309 18:02:50.330303 <6>[ 1.803407] cpu cpu0: EM: created perf domain
10310 18:02:50.333858 <6>[ 1.808285] cpu cpu4: EM: created perf domain
10311 18:02:50.340672 <6>[ 1.813848] sdhci: Secure Digital Host Controller Interface driver
10312 18:02:50.347426 <6>[ 1.820278] sdhci: Copyright(c) Pierre Ossman
10313 18:02:50.354203 <6>[ 1.825182] Synopsys Designware Multimedia Card Interface Driver
10314 18:02:50.360587 <6>[ 1.831791] sdhci-pltfm: SDHCI platform and OF driver helper
10315 18:02:50.364260 <6>[ 1.831959] mmc0: CQHCI version 5.10
10316 18:02:50.371107 <6>[ 1.841808] ledtrig-cpu: registered to indicate activity on CPUs
10317 18:02:50.377153 <6>[ 1.848832] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10318 18:02:50.383628 <6>[ 1.855861] usbcore: registered new interface driver usbhid
10319 18:02:50.387596 <6>[ 1.861682] usbhid: USB HID core driver
10320 18:02:50.393997 <6>[ 1.865874] spi_master spi0: will run message pump with realtime priority
10321 18:02:50.436915 <6>[ 1.903228] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10322 18:02:50.455676 <6>[ 1.918844] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10323 18:02:50.458928 <6>[ 1.932404] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15014
10324 18:02:50.466436 <6>[ 1.939322] cros-ec-spi spi0.0: Chrome EC device registered
10325 18:02:50.473287 <6>[ 1.945347] mmc0: Command Queue Engine enabled
10326 18:02:50.479835 <6>[ 1.950104] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10327 18:02:50.483460 <6>[ 1.957908] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10328 18:02:50.494461 <6>[ 1.967327] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10329 18:02:50.502444 <6>[ 1.975097] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10330 18:02:50.512196 <6>[ 1.978920] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10331 18:02:50.515485 <6>[ 1.981048] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10332 18:02:50.522144 <6>[ 1.990696] NET: Registered PF_PACKET protocol family
10333 18:02:50.528369 <6>[ 1.995542] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10334 18:02:50.531673 <6>[ 2.000234] 9pnet: Installing 9P2000 support
10335 18:02:50.538508 <5>[ 2.011245] Key type dns_resolver registered
10336 18:02:50.541620 <6>[ 2.016253] registered taskstats version 1
10337 18:02:50.548780 <5>[ 2.020629] Loading compiled-in X.509 certificates
10338 18:02:50.575240 <4>[ 2.041390] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10339 18:02:50.584809 <4>[ 2.052138] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10340 18:02:50.602718 <6>[ 2.075673] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10341 18:02:50.609321 <6>[ 2.082595] xhci-mtk 11200000.usb: xHCI Host Controller
10342 18:02:50.615761 <6>[ 2.088091] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10343 18:02:50.626267 <6>[ 2.095922] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10344 18:02:50.632537 <6>[ 2.105339] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10345 18:02:50.639063 <6>[ 2.111402] xhci-mtk 11200000.usb: xHCI Host Controller
10346 18:02:50.645884 <6>[ 2.116880] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10347 18:02:50.652550 <6>[ 2.124531] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10348 18:02:50.659513 <6>[ 2.132145] hub 1-0:1.0: USB hub found
10349 18:02:50.662540 <6>[ 2.136161] hub 1-0:1.0: 1 port detected
10350 18:02:50.669044 <6>[ 2.140425] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10351 18:02:50.675664 <6>[ 2.148922] hub 2-0:1.0: USB hub found
10352 18:02:50.678989 <6>[ 2.152928] hub 2-0:1.0: 1 port detected
10353 18:02:50.686626 <6>[ 2.159788] mtk-msdc 11f70000.mmc: Got CD GPIO
10354 18:02:50.703821 <6>[ 2.173388] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10355 18:02:50.713968 <6>[ 2.182050] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10356 18:02:50.720310 <6>[ 2.190412] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10357 18:02:50.730298 <6>[ 2.198750] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10358 18:02:50.736476 <6>[ 2.207093] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10359 18:02:50.746586 <6>[ 2.215430] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10360 18:02:50.753093 <6>[ 2.223768] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10361 18:02:50.763084 <6>[ 2.232106] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10362 18:02:50.770032 <6>[ 2.240443] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10363 18:02:50.779529 <6>[ 2.248781] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10364 18:02:50.786278 <6>[ 2.257119] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10365 18:02:50.796127 <6>[ 2.265456] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10366 18:02:50.802950 <6>[ 2.273793] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10367 18:02:50.812912 <6>[ 2.282130] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10368 18:02:50.819850 <6>[ 2.290467] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10369 18:02:50.826436 <6>[ 2.299294] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10370 18:02:50.833387 <6>[ 2.306577] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10371 18:02:50.840069 <6>[ 2.313377] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10372 18:02:50.850367 <6>[ 2.320129] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10373 18:02:50.856922 <6>[ 2.327079] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10374 18:02:50.863498 <6>[ 2.333934] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10375 18:02:50.873331 <6>[ 2.343065] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10376 18:02:50.883423 <6>[ 2.352183] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10377 18:02:50.893365 <6>[ 2.361476] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10378 18:02:50.903065 <6>[ 2.370942] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10379 18:02:50.909734 <6>[ 2.380408] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10380 18:02:50.920373 <6>[ 2.389528] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10381 18:02:50.929912 <6>[ 2.398994] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10382 18:02:50.939718 <6>[ 2.408113] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10383 18:02:50.949391 <6>[ 2.417406] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10384 18:02:50.959464 <6>[ 2.427565] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10385 18:02:50.969070 <6>[ 2.439182] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10386 18:02:50.976867 <6>[ 2.450205] Trying to probe devices needed for running init ...
10387 18:02:50.987378 <3>[ 2.457395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10388 18:02:51.069046 <6>[ 2.538804] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10389 18:02:51.096753 <6>[ 2.569507] hub 2-1:1.0: USB hub found
10390 18:02:51.099854 <6>[ 2.573951] hub 2-1:1.0: 3 ports detected
10391 18:02:51.108719 <6>[ 2.581903] hub 2-1:1.0: USB hub found
10392 18:02:51.112141 <6>[ 2.586254] hub 2-1:1.0: 3 ports detected
10393 18:02:51.220550 <6>[ 2.690574] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10394 18:02:51.374791 <6>[ 2.848362] hub 1-1:1.0: USB hub found
10395 18:02:51.378297 <6>[ 2.852887] hub 1-1:1.0: 4 ports detected
10396 18:02:51.390710 <6>[ 2.864077] hub 1-1:1.0: USB hub found
10397 18:02:51.394077 <6>[ 2.868522] hub 1-1:1.0: 4 ports detected
10398 18:02:51.460584 <6>[ 2.930689] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10399 18:02:51.569203 <6>[ 3.038987] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10400 18:02:51.601464 <4>[ 3.070831] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10401 18:02:51.611063 <4>[ 3.079926] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10402 18:02:51.649668 <6>[ 3.123257] r8152 2-1.3:1.0 eth0: v1.12.13
10403 18:02:51.724303 <6>[ 3.194585] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10404 18:02:51.856610 <6>[ 3.329730] hub 1-1.4:1.0: USB hub found
10405 18:02:51.859756 <6>[ 3.334345] hub 1-1.4:1.0: 2 ports detected
10406 18:02:51.871987 <6>[ 3.344911] hub 1-1.4:1.0: USB hub found
10407 18:02:51.874667 <6>[ 3.349529] hub 1-1.4:1.0: 2 ports detected
10408 18:02:52.172726 <6>[ 3.642612] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10409 18:02:52.368719 <6>[ 3.838659] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10410 18:02:53.543245 <6>[ 5.016829] r8152 2-1.3:1.0 eth0: carrier on
10411 18:02:56.468369 <5>[ 5.046428] Sending DHCP requests .., OK
10412 18:02:56.475488 <6>[ 7.946784] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10413 18:02:56.478469 <6>[ 7.955092] IP-Config: Complete:
10414 18:02:56.491487 <6>[ 7.958623] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10415 18:02:56.498840 <6>[ 7.969363] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10416 18:02:56.508805 <6>[ 7.977983] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10417 18:02:56.511797 <6>[ 7.977992] nameserver0=192.168.201.1
10418 18:02:56.514590 <6>[ 7.990174] clk: Disabling unused clocks
10419 18:02:56.518730 <6>[ 7.995680] ALSA device list:
10420 18:02:56.525275 <6>[ 7.998959] No soundcards found.
10421 18:02:56.532866 <6>[ 8.006547] Freeing unused kernel memory: 8512K
10422 18:02:56.536165 <6>[ 8.011456] Run /init as init process
10423 18:02:56.545887 Loading, please wait...
10424 18:02:56.574331 Starting systemd-udevd version 252.22-1~deb12u1
10425 18:02:56.767369 <6>[ 8.237951] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10426 18:02:56.784459 <6>[ 8.255053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10427 18:02:56.791267 <6>[ 8.263125] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10428 18:02:56.801813 <4>[ 8.272473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10429 18:02:56.812281 <6>[ 8.282456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10430 18:02:56.818879 <6>[ 8.290561] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10431 18:02:56.828394 <6>[ 8.292439] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10432 18:02:56.835449 <6>[ 8.299756] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10433 18:02:56.841828 <6>[ 8.300525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10434 18:02:56.851439 <6>[ 8.300536] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10435 18:02:56.858267 <6>[ 8.300540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10436 18:02:56.868098 <6>[ 8.300549] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10437 18:02:56.875341 <6>[ 8.306115] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10438 18:02:56.881698 <6>[ 8.314062] mc: Linux media interface: v0.10
10439 18:02:56.884598 <6>[ 8.320583] remoteproc remoteproc0: scp is available
10440 18:02:56.891063 <6>[ 8.320628] remoteproc remoteproc0: powering up scp
10441 18:02:56.901476 <6>[ 8.320631] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10442 18:02:56.904538 <6>[ 8.320650] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10443 18:02:56.914654 <6>[ 8.321450] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10444 18:02:56.921237 <4>[ 8.348733] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10445 18:02:56.931359 <3>[ 8.359685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10446 18:02:56.938879 <4>[ 8.360331] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10447 18:02:56.944836 <3>[ 8.365404] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10448 18:02:56.951818 <6>[ 8.367627] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10449 18:02:56.962100 <4>[ 8.391159] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10450 18:02:56.965374 <4>[ 8.391159] Fallback method does not support PEC.
10451 18:02:56.975887 <3>[ 8.393161] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10452 18:02:56.982057 <3>[ 8.415616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10453 18:02:56.992154 <3>[ 8.415965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10454 18:02:56.998668 <3>[ 8.444811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10455 18:02:57.008775 <3>[ 8.445492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10456 18:02:57.015226 <6>[ 8.447612] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10457 18:02:57.025381 <6>[ 8.447660] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10458 18:02:57.031676 <6>[ 8.447666] remoteproc remoteproc0: remote processor scp is now up
10459 18:02:57.041668 <6>[ 8.452156] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10460 18:02:57.047953 <6>[ 8.452474] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10461 18:02:57.054772 <6>[ 8.475656] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10462 18:02:57.064916 <3>[ 8.478905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 18:02:57.071333 <3>[ 8.478912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 18:02:57.081575 <3>[ 8.478915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10465 18:02:57.091357 <6>[ 8.483651] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10466 18:02:57.094664 <6>[ 8.487042] pci_bus 0000:00: root bus resource [bus 00-ff]
10467 18:02:57.104737 <3>[ 8.494085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10468 18:02:57.110764 <6>[ 8.502559] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10469 18:02:57.121053 <6>[ 8.502562] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10470 18:02:57.127654 <6>[ 8.502941] videodev: Linux video capture interface: v2.00
10471 18:02:57.134087 <3>[ 8.509042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 18:02:57.143976 <6>[ 8.511013] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10473 18:02:57.150479 <6>[ 8.515472] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10474 18:02:57.157541 <6>[ 8.519116] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10475 18:02:57.163554 <3>[ 8.528110] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 18:02:57.173812 <6>[ 8.534982] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10477 18:02:57.177119 <6>[ 8.535878] Bluetooth: Core ver 2.22
10478 18:02:57.183488 <6>[ 8.535987] NET: Registered PF_BLUETOOTH protocol family
10479 18:02:57.190117 <6>[ 8.535991] Bluetooth: HCI device and connection manager initialized
10480 18:02:57.193663 <6>[ 8.536012] Bluetooth: HCI socket layer initialized
10481 18:02:57.200369 <6>[ 8.536018] Bluetooth: L2CAP socket layer initialized
10482 18:02:57.203382 <6>[ 8.536032] Bluetooth: SCO socket layer initialized
10483 18:02:57.213391 <3>[ 8.543052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10484 18:02:57.216550 <6>[ 8.551186] pci 0000:00:00.0: supports D1 D2
10485 18:02:57.223363 <3>[ 8.559242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 18:02:57.232941 <6>[ 8.568491] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10487 18:02:57.239817 <6>[ 8.569798] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10488 18:02:57.249328 <3>[ 8.574235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10489 18:02:57.256231 <3>[ 8.574241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 18:02:57.262333 <6>[ 8.582425] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10491 18:02:57.269665 <6>[ 8.584008] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10492 18:02:57.282525 <6>[ 8.585065] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10493 18:02:57.289251 <6>[ 8.585161] usbcore: registered new interface driver uvcvideo
10494 18:02:57.295989 <3>[ 8.589442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10495 18:02:57.302807 <6>[ 8.599366] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10496 18:02:57.312114 <3>[ 8.605074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10497 18:02:57.315684 <6>[ 8.605736] usbcore: registered new interface driver btusb
10498 18:02:57.329076 <4>[ 8.606930] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10499 18:02:57.332262 <3>[ 8.606948] Bluetooth: hci0: Failed to load firmware file (-2)
10500 18:02:57.338619 <3>[ 8.606954] Bluetooth: hci0: Failed to set up firmware (-2)
10501 18:02:57.348453 <4>[ 8.606961] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10502 18:02:57.358568 <6>[ 8.613162] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10503 18:02:57.364910 <3>[ 8.621418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10504 18:02:57.371472 <6>[ 8.621894] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10505 18:02:57.378621 <6>[ 8.629669] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10506 18:02:57.385037 <6>[ 8.858397] pci 0000:01:00.0: supports D1 D2
10507 18:02:57.391026 <6>[ 8.862919] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10508 18:02:57.411995 <6>[ 8.882523] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10509 18:02:57.418471 <6>[ 8.889426] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10510 18:02:57.425283 <6>[ 8.897506] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10511 18:02:57.435451 <6>[ 8.905503] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10512 18:02:57.441977 <6>[ 8.913503] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10513 18:02:57.451765 <6>[ 8.921503] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10514 18:02:57.455038 <6>[ 8.929503] pci 0000:00:00.0: PCI bridge to [bus 01]
10515 18:02:57.464994 <6>[ 8.934719] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10516 18:02:57.471178 <6>[ 8.942827] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10517 18:02:57.477866 <6>[ 8.949627] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10518 18:02:57.484563 <6>[ 8.956289] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10519 18:02:57.498171 <5>[ 8.968943] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10520 18:02:57.519560 <5>[ 8.990057] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10521 18:02:57.526190 <5>[ 8.997574] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10522 18:02:57.535724 <4>[ 9.006061] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10523 18:02:57.542326 <6>[ 9.015016] cfg80211: failed to load regulatory.db
10524 18:02:57.593552 <6>[ 9.063907] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10525 18:02:57.599646 <6>[ 9.071409] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10526 18:02:57.624432 <6>[ 9.098219] mt7921e 0000:01:00.0: ASIC revision: 79610010
10527 18:02:57.728457 <6>[ 9.198752] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10528 18:02:57.731481 <6>[ 9.198752]
10529 18:02:57.735111 Begin: Loading essential drivers ... done.
10530 18:02:57.737928 Begin: Running /scripts/init-premount ... done.
10531 18:02:57.744553 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10532 18:02:57.755110 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10533 18:02:57.757790 Device /sys/class/net/eth0 found
10534 18:02:57.758249 done.
10535 18:02:57.764431 Begin: Waiting up to 180 secs for any network device to become available ... done.
10536 18:02:57.812516 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10537 18:02:57.819199 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10538 18:02:57.825683 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10539 18:02:57.832506 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10540 18:02:57.839475 host : mt8192-asurada-spherion-r0-cbg-4
10541 18:02:57.845789 domain : lava-rack
10542 18:02:57.848663 rootserver: 192.168.201.1 rootpath:
10543 18:02:57.849092 filename :
10544 18:02:57.869897 done.
10545 18:02:57.878567 Begin: Running /scripts/nfs-bottom ... done.
10546 18:02:57.892078 Begin: Running /scripts/init-bottom ... done.
10547 18:02:57.997514 <6>[ 9.468349] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10548 18:02:59.226624 <6>[ 10.701125] NET: Registered PF_INET6 protocol family
10549 18:02:59.234315 <6>[ 10.708795] Segment Routing with IPv6
10550 18:02:59.237493 <6>[ 10.712802] In-situ OAM (IOAM) with IPv6
10551 18:02:59.405655 <30>[ 10.853575] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10552 18:02:59.412633 <30>[ 10.886712] systemd[1]: Detected architecture arm64.
10553 18:02:59.421375
10554 18:02:59.424898 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10555 18:02:59.425290
10556 18:02:59.449985 <30>[ 10.924392] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10557 18:03:00.536945 <30>[ 12.007997] systemd[1]: Queued start job for default target graphical.target.
10558 18:03:00.576320 <30>[ 12.047662] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10559 18:03:00.583114 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10560 18:03:00.605589 <30>[ 12.076473] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10561 18:03:00.615588 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10562 18:03:00.634077 <30>[ 12.104441] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10563 18:03:00.643402 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10564 18:03:00.660639 <30>[ 12.131598] systemd[1]: Created slice user.slice - User and Session Slice.
10565 18:03:00.667148 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10566 18:03:00.687674 <30>[ 12.154939] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10567 18:03:00.697079 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10568 18:03:00.715299 <30>[ 12.182871] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10569 18:03:00.721911 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10570 18:03:00.749625 <30>[ 12.210794] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10571 18:03:00.759807 <30>[ 12.230601] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10572 18:03:00.766548 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10573 18:03:00.784012 <30>[ 12.255003] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10574 18:03:00.794290 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10575 18:03:00.812424 <30>[ 12.283068] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10576 18:03:00.821825 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10577 18:03:00.836902 <30>[ 12.311057] systemd[1]: Reached target paths.target - Path Units.
10578 18:03:00.846825 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10579 18:03:00.864152 <30>[ 12.335024] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10580 18:03:00.870847 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10581 18:03:00.884091 <30>[ 12.358588] systemd[1]: Reached target slices.target - Slice Units.
10582 18:03:00.894158 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10583 18:03:00.908687 <30>[ 12.382653] systemd[1]: Reached target swap.target - Swaps.
10584 18:03:00.914851 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10585 18:03:00.935992 <30>[ 12.407029] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10586 18:03:00.945833 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10587 18:03:00.964729 <30>[ 12.435612] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10588 18:03:00.974546 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10589 18:03:00.994272 <30>[ 12.465469] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10590 18:03:01.004374 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10591 18:03:01.021300 <30>[ 12.492033] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10592 18:03:01.031022 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10593 18:03:01.048557 <30>[ 12.519254] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10594 18:03:01.055011 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10595 18:03:01.073030 <30>[ 12.544110] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10596 18:03:01.083360 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10597 18:03:01.102642 <30>[ 12.573618] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10598 18:03:01.112298 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10599 18:03:01.128086 <30>[ 12.599062] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10600 18:03:01.138289 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10601 18:03:01.179526 <30>[ 12.650677] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10602 18:03:01.185929 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10603 18:03:01.207740 <30>[ 12.679283] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10604 18:03:01.214268 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10605 18:03:01.242155 <30>[ 12.713161] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10606 18:03:01.248784 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10607 18:03:01.274641 <30>[ 12.739246] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10608 18:03:01.289797 <30>[ 12.760824] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10609 18:03:01.299988 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10610 18:03:01.319690 <30>[ 12.790747] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10611 18:03:01.329619 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10612 18:03:01.353400 <30>[ 12.824469] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10613 18:03:01.359824 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10614 18:03:01.385192 <30>[ 12.856252] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10615 18:03:01.395331 Starting [0;1;39mmodpr<6>[ 12.866598] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10616 18:03:01.401463 obe@drm.service[0m - Load Kernel Module drm...
10617 18:03:01.425245 <30>[ 12.896423] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10618 18:03:01.435626 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10619 18:03:01.457179 <30>[ 12.928095] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10620 18:03:01.464032 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10621 18:03:01.500355 <6>[ 12.974742] fuse: init (API version 7.37)
10622 18:03:01.524196 <30>[ 12.995510] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10623 18:03:01.530612 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10624 18:03:01.561416 <30>[ 13.032526] systemd[1]: Starting systemd-journald.service - Journal Service...
10625 18:03:01.567830 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10626 18:03:01.601438 <30>[ 13.072544] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10627 18:03:01.608087 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10628 18:03:01.637226 <30>[ 13.105279] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10629 18:03:01.644282 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10630 18:03:01.669233 <30>[ 13.140562] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10631 18:03:01.679608 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10632 18:03:01.717666 <3>[ 13.188854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 18:03:01.748036 <3>[ 13.218997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 18:03:01.757786 <30>[ 13.219303] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10635 18:03:01.764456 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10636 18:03:01.787398 <30>[ 13.258482] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10637 18:03:01.795255 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10638 18:03:01.804861 <3>[ 13.275059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 18:03:01.815889 <30>[ 13.287463] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10640 18:03:01.822606 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10641 18:03:01.832613 <3>[ 13.303023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 18:03:01.843458 <30>[ 13.314929] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10643 18:03:01.850673 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10644 18:03:01.860605 <3>[ 13.330989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10645 18:03:01.870578 <30>[ 13.341456] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10646 18:03:01.877877 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10647 18:03:01.887912 <3>[ 13.358585] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 18:03:01.897700 <30>[ 13.368953] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10649 18:03:01.905178 <30>[ 13.376729] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10650 18:03:01.915240 [[0;32m OK [<3>[ 13.386281] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 18:03:01.921868 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10652 18:03:01.942112 <3>[ 13.413294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 18:03:01.952394 <30>[ 13.423505] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10654 18:03:01.959437 <30>[ 13.431155] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10655 18:03:01.973304 [[0;32m OK [0m] Finished [0<3>[ 13.442107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 18:03:01.976797 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10657 18:03:01.993937 <30>[ 13.467681] systemd[1]: modprobe@drm.service: Deactivated successfully.
10658 18:03:02.003856 <3>[ 13.472844] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 18:03:02.010810 <30>[ 13.475346] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10660 18:03:02.020445 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10661 18:03:02.033535 <3>[ 13.504450] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 18:03:02.044524 <30>[ 13.515531] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10663 18:03:02.054916 <30>[ 13.523889] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10664 18:03:02.064990 [[0;32m OK [0m] Finished [0<3>[ 13.534690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 18:03:02.071996 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10666 18:03:02.086068 <30>[ 13.560084] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10667 18:03:02.097330 <30>[ 13.568356] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10668 18:03:02.107627 [[0;32m OK [0m] Finished [0<3>[ 13.579002] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 18:03:02.113781 ;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10670 18:03:02.137554 <30>[ 13.607921] systemd[1]: modprobe@loop.service: Deactivated successfully.
10671 18:03:02.144030 <30>[ 13.615819] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10672 18:03:02.158057 [[0;32m OK [0m] Finished [0<3>[ 13.626088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10673 18:03:02.160975 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10674 18:03:02.171500 <3>[ 13.640774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 18:03:02.184130 <4>[ 13.649628] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10676 18:03:02.193910 <3>[ 13.665276] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10677 18:03:02.200773 <30>[ 13.666959] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10678 18:03:02.217929 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<3>[ 13.687059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 18:03:02.218139 nel Modules.
10680 18:03:02.240577 <30>[ 13.707777] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10681 18:03:02.247141 <3>[ 13.716492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10682 18:03:02.257062 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10683 18:03:02.276910 <30>[ 13.748168] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10684 18:03:02.287014 <3>[ 13.748658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10685 18:03:02.296575 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10686 18:03:02.313274 <30>[ 13.783259] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10687 18:03:02.319476 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10688 18:03:02.340762 <30>[ 13.811320] systemd[1]: Reached target network-pre.target - Preparation for Network.
10689 18:03:02.346749 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10690 18:03:02.391672 <30>[ 13.862771] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10691 18:03:02.398162 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10692 18:03:02.423872 <30>[ 13.895321] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10693 18:03:02.430959 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10694 18:03:02.454649 <30>[ 13.922726] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10695 18:03:02.471569 <30>[ 13.936358] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10696 18:03:02.486510 <30>[ 13.957361] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10697 18:03:02.492533 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10698 18:03:02.517620 <30>[ 13.985600] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10699 18:03:02.556113 <30>[ 14.027370] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10700 18:03:02.562649 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10701 18:03:02.591189 <30>[ 14.062360] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10702 18:03:02.597764 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10703 18:03:02.622142 <30>[ 14.093200] systemd[1]: Started systemd-journald.service - Journal Service.
10704 18:03:02.628723 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10705 18:03:02.652549 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10706 18:03:02.672584 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10707 18:03:02.693025 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10708 18:03:02.712903 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10709 18:03:02.732484 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10710 18:03:02.783609 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10711 18:03:02.806073 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10712 18:03:02.837179 <46>[ 14.308441] systemd-journald[306]: Received client request to flush runtime journal.
10713 18:03:03.933222 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10714 18:03:03.955221 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10715 18:03:03.975275 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10716 18:03:04.244172 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10717 18:03:04.264986 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10718 18:03:04.291872 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10719 18:03:04.429429 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10720 18:03:04.477212 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10721 18:03:04.563022 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10722 18:03:04.830865 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10723 18:03:04.891406 Starting [0;1;39msystemd-backlight…ess of leds:white<6>[ 16.363261] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10724 18:03:04.891859 :kbd_backlight...
10725 18:03:04.929488 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10726 18:03:05.011922 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10727 18:03:05.032690 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10728 18:03:05.071434 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10729 18:03:05.092331 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10730 18:03:05.124870 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10731 18:03:05.146942 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10732 18:03:05.244022 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10733 18:03:05.269626 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10734 18:03:05.291726 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10735 18:03:05.338058 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10736 18:03:05.384500 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10737 18:03:05.403946 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10738 18:03:05.428223 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10739 18:03:05.451637 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10740 18:03:05.476832 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10741 18:03:05.498266 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10742 18:03:05.515778 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10743 18:03:05.534629 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10744 18:03:05.554975 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10745 18:03:05.571197 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10746 18:03:05.589619 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10747 18:03:05.607152 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10748 18:03:05.623467 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10749 18:03:05.672787 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10750 18:03:05.718007 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10751 18:03:05.813767 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10752 18:03:05.845073 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10753 18:03:05.932048 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10754 18:03:05.997888 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10755 18:03:06.058541 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10756 18:03:06.076037 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10757 18:03:06.093076 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10758 18:03:06.129417 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10759 18:03:06.159634 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10760 18:03:06.180631 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10761 18:03:06.200009 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10762 18:03:06.256772 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10763 18:03:06.313084 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10764 18:03:06.391292
10765 18:03:06.395024 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10766 18:03:06.395517
10767 18:03:06.398011 debian-bookworm-arm64 login: root (automatic login)
10768 18:03:06.398537
10769 18:03:06.681092 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
10770 18:03:06.681225
10771 18:03:06.687367 The programs included with the Debian GNU/Linux system are free software;
10772 18:03:06.693779 the exact distribution terms for each program are described in the
10773 18:03:06.696815 individual files in /usr/share/doc/*/copyright.
10774 18:03:06.696939
10775 18:03:06.703523 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10776 18:03:06.706956 permitted by applicable law.
10777 18:03:07.738674 Matched prompt #10: / #
10779 18:03:07.739710 Setting prompt string to ['/ #']
10780 18:03:07.740118 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10782 18:03:07.740999 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10783 18:03:07.741421 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
10784 18:03:07.741781 Setting prompt string to ['/ #']
10785 18:03:07.742089 Forcing a shell prompt, looking for ['/ #']
10787 18:03:07.792897 / #
10788 18:03:07.793588 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10789 18:03:07.794005 Waiting using forced prompt support (timeout 00:02:30)
10790 18:03:07.799380
10791 18:03:07.800251 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10792 18:03:07.800740 start: 2.2.7 export-device-env (timeout 00:03:41) [common]
10794 18:03:07.902008 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr'
10795 18:03:07.909396 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291331/extract-nfsrootfs-4j7w23qr'
10797 18:03:08.011002 / # export NFS_SERVER_IP='192.168.201.1'
10798 18:03:08.017132 export NFS_SERVER_IP='192.168.201.1'
10799 18:03:08.017957 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10800 18:03:08.018507 end: 2.2 depthcharge-retry (duration 00:01:19) [common]
10801 18:03:08.018998 end: 2 depthcharge-action (duration 00:01:19) [common]
10802 18:03:08.019455 start: 3 lava-test-retry (timeout 00:07:23) [common]
10803 18:03:08.019918 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
10804 18:03:08.020291 Using namespace: common
10806 18:03:08.121366 / # #
10807 18:03:08.122027 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10808 18:03:08.128095 #
10809 18:03:08.128910 Using /lava-14291331
10811 18:03:08.230159 / # export SHELL=/bin/bash
10812 18:03:08.236989 export SHELL=/bin/bash
10814 18:03:08.338501 / # . /lava-14291331/environment
10815 18:03:08.345006 . /lava-14291331/environment
10817 18:03:08.451914 / # /lava-14291331/bin/lava-test-runner /lava-14291331/0
10818 18:03:08.452572 Test shell timeout: 10s (minimum of the action and connection timeout)
10819 18:03:08.458445 /lava-14291331/bin/lava-test-runner /lava-14291331/0
10820 18:03:08.688844 + export TESTRUN_ID=0_timesync-off
10821 18:03:08.691850 + TESTRUN_ID=0_timesync-off
10822 18:03:08.695450 + cd /lava-14291331/0/tests/0_timesync-off
10823 18:03:08.698519 ++ cat uuid
10824 18:03:08.701954 + UUID=14291331_1.6.2.3.1
10825 18:03:08.702528 + set +x
10826 18:03:08.708206 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291331_1.6.2.3.1>
10827 18:03:08.708874 Received signal: <STARTRUN> 0_timesync-off 14291331_1.6.2.3.1
10828 18:03:08.709213 Starting test lava.0_timesync-off (14291331_1.6.2.3.1)
10829 18:03:08.709588 Skipping test definition patterns.
10830 18:03:08.711882 + systemctl stop systemd-timesyncd
10831 18:03:08.793473 + set +x
10832 18:03:08.796370 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291331_1.6.2.3.1>
10833 18:03:08.797006 Received signal: <ENDRUN> 0_timesync-off 14291331_1.6.2.3.1
10834 18:03:08.797391 Ending use of test pattern.
10835 18:03:08.797681 Ending test lava.0_timesync-off (14291331_1.6.2.3.1), duration 0.09
10837 18:03:08.861426 + export TESTRUN_ID=1_kselftest-rtc
10838 18:03:08.864179 + TESTRUN_ID=1_kselftest-rtc
10839 18:03:08.867627 + cd /lava-14291331/0/tests/1_kselftest-rtc
10840 18:03:08.871295 ++ cat uuid
10841 18:03:08.871388 + UUID=14291331_1.6.2.3.5
10842 18:03:08.874398 + set +x
10843 18:03:08.877791 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14291331_1.6.2.3.5>
10844 18:03:08.878040 Received signal: <STARTRUN> 1_kselftest-rtc 14291331_1.6.2.3.5
10845 18:03:08.878131 Starting test lava.1_kselftest-rtc (14291331_1.6.2.3.5)
10846 18:03:08.878260 Skipping test definition patterns.
10847 18:03:08.880869 + cd ./automated/linux/kselftest/
10848 18:03:08.907293 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10849 18:03:08.946818 INFO: install_deps skipped
10850 18:03:09.446427 --2024-06-11 18:03:09-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10851 18:03:09.456039 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10852 18:03:09.590364 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10853 18:03:09.723275 HTTP request sent, awaiting response... 200 OK
10854 18:03:09.726604 Length: 1647744 (1.6M) [application/octet-stream]
10855 18:03:09.729818 Saving to: 'kselftest_armhf.tar.gz'
10856 18:03:09.730286
10857 18:03:09.730642
10858 18:03:09.989017 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10859 18:03:10.254671 kselftest_armhf.tar 2%[ ] 44.98K 170KB/s
10860 18:03:10.601550 kselftest_armhf.tar 13%[=> ] 214.67K 404KB/s
10861 18:03:10.921839 kselftest_armhf.tar 51%[=========> ] 822.71K 938KB/s
10862 18:03:10.927842 kselftest_armhf.tar 94%[=================> ] 1.49M 1.24MB/s
10863 18:03:10.934762 kselftest_armhf.tar 100%[===================>] 1.57M 1.31MB/s in 1.2s
10864 18:03:10.935191
10865 18:03:11.073289 2024-06-11 18:03:11 (1.31 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
10866 18:03:11.073433
10867 18:03:15.140591 skiplist:
10868 18:03:15.144231 ========================================
10869 18:03:15.147130 ========================================
10870 18:03:15.185472 rtc:rtctest
10871 18:03:15.204459 ============== Tests to run ===============
10872 18:03:15.204536 rtc:rtctest
10873 18:03:15.208225 ===========End Tests to run ===============
10874 18:03:15.211725 shardfile-rtc pass
10875 18:03:15.316368 <12>[ 26.792609] kselftest: Running tests in rtc
10876 18:03:15.325044 TAP version 13
10877 18:03:15.339288 1..1
10878 18:03:15.370880 # selftests: rtc: rtctest
10879 18:03:15.913126 # TAP version 13
10880 18:03:15.913315 # 1..8
10881 18:03:15.916083 # # Starting 8 tests from 2 test cases.
10882 18:03:15.918959 # # RUN rtc.date_read ...
10883 18:03:15.926204 # # rtctest.c:49:date_read:Current RTC date/time is 11/06/2024 18:03:15.
10884 18:03:15.929417 # # OK rtc.date_read
10885 18:03:15.932119 # ok 1 rtc.date_read
10886 18:03:15.935560 # # RUN rtc.date_read_loop ...
10887 18:03:15.945744 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
10888 18:03:28.533655 <6>[ 40.014457] vpu: disabling
10889 18:03:28.537000 <6>[ 40.017562] vproc2: disabling
10890 18:03:28.540075 <6>[ 40.020882] vproc1: disabling
10891 18:03:28.543569 <6>[ 40.024574] vaud18: disabling
10892 18:03:28.550885 <6>[ 40.028439] vsram_others: disabling
10893 18:03:28.554131 <6>[ 40.032412] va09: disabling
10894 18:03:28.557600 <6>[ 40.035578] vsram_md: disabling
10895 18:03:28.560541 <6>[ 40.039142] Vgpu: disabling
10896 18:03:45.971335 # # rtctest.c:115:date_read_loop:Performed 2630 RTC time reads.
10897 18:03:45.974380 # # OK rtc.date_read_loop
10898 18:03:45.978120 # ok 2 rtc.date_read_loop
10899 18:03:45.981037 # # RUN rtc.uie_read ...
10900 18:03:48.953632 # # OK rtc.uie_read
10901 18:03:48.956443 # ok 3 rtc.uie_read
10902 18:03:48.960017 # # RUN rtc.uie_select ...
10903 18:03:51.953558 # # OK rtc.uie_select
10904 18:03:51.956529 # ok 4 rtc.uie_select
10905 18:03:51.960000 # # RUN rtc.alarm_alm_set ...
10906 18:03:51.966599 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 18:03:55.
10907 18:03:51.969914 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
10908 18:03:51.976306 # # alarm_alm_set: Test terminated by assertion
10909 18:03:51.979562 # # FAIL rtc.alarm_alm_set
10910 18:03:51.983201 # not ok 5 rtc.alarm_alm_set
10911 18:03:51.986374 # # RUN rtc.alarm_wkalm_set ...
10912 18:03:51.992980 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 11/06/2024 18:03:55.
10913 18:03:54.956030 # # OK rtc.alarm_wkalm_set
10914 18:03:54.956534 # ok 6 rtc.alarm_wkalm_set
10915 18:03:54.962304 # # RUN rtc.alarm_alm_set_minute ...
10916 18:03:54.966012 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 18:04:00.
10917 18:03:54.971882 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
10918 18:03:54.978487 # # alarm_alm_set_minute: Test terminated by assertion
10919 18:03:54.982308 # # FAIL rtc.alarm_alm_set_minute
10920 18:03:54.985059 # not ok 7 rtc.alarm_alm_set_minute
10921 18:03:54.988787 # # RUN rtc.alarm_wkalm_set_minute ...
10922 18:03:54.995079 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 11/06/2024 18:04:00.
10923 18:03:59.955064 # # OK rtc.alarm_wkalm_set_minute
10924 18:03:59.958823 # ok 8 rtc.alarm_wkalm_set_minute
10925 18:03:59.959247 # # FAILED: 6 / 8 tests passed.
10926 18:03:59.965069 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
10927 18:03:59.968674 not ok 1 selftests: rtc: rtctest # exit=1
10928 18:04:01.442833 rtc_rtctest_rtc_date_read pass
10929 18:04:01.445263 rtc_rtctest_rtc_date_read_loop pass
10930 18:04:01.449247 rtc_rtctest_rtc_uie_read pass
10931 18:04:01.452052 rtc_rtctest_rtc_uie_select pass
10932 18:04:01.455812 rtc_rtctest_rtc_alarm_alm_set fail
10933 18:04:01.459096 rtc_rtctest_rtc_alarm_wkalm_set pass
10934 18:04:01.461768 rtc_rtctest_rtc_alarm_alm_set_minute fail
10935 18:04:01.465418 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
10936 18:04:01.468655 rtc_rtctest fail
10937 18:04:01.518309 + ../../utils/send-to-lava.sh ./output/result.txt
10938 18:04:01.581521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
10939 18:04:01.581784 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
10941 18:04:01.633636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
10942 18:04:01.634254 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
10944 18:04:01.682423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
10945 18:04:01.682689 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
10947 18:04:01.722473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
10948 18:04:01.723101 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
10950 18:04:01.770534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
10951 18:04:01.771166 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
10953 18:04:01.815502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
10954 18:04:01.815754 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
10956 18:04:01.861438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
10957 18:04:01.861683 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
10959 18:04:01.913764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
10960 18:04:01.914614 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
10962 18:04:01.962494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
10963 18:04:01.963246 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
10965 18:04:02.006487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
10966 18:04:02.006900 + set +x
10967 18:04:02.007440 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
10969 18:04:02.013404 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14291331_1.6.2.3.5>
10970 18:04:02.014179 Received signal: <ENDRUN> 1_kselftest-rtc 14291331_1.6.2.3.5
10971 18:04:02.014587 Ending use of test pattern.
10972 18:04:02.014871 Ending test lava.1_kselftest-rtc (14291331_1.6.2.3.5), duration 53.14
10974 18:04:02.015831 ok: lava_test_shell seems to have completed
10975 18:04:02.016454 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
10976 18:04:02.016881 end: 3.1 lava-test-shell (duration 00:00:54) [common]
10977 18:04:02.017329 end: 3 lava-test-retry (duration 00:00:54) [common]
10978 18:04:02.017876 start: 4 finalize (timeout 00:06:29) [common]
10979 18:04:02.018341 start: 4.1 power-off (timeout 00:00:30) [common]
10980 18:04:02.019015 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10981 18:04:02.275858 >> Command sent successfully.
10982 18:04:02.290554 Returned 0 in 0 seconds
10983 18:04:02.391865 end: 4.1 power-off (duration 00:00:00) [common]
10985 18:04:02.393287 start: 4.2 read-feedback (timeout 00:06:29) [common]
10987 18:04:02.395390 Listened to connection for namespace 'common' for up to 1s
10988 18:04:03.394646 Finalising connection for namespace 'common'
10989 18:04:03.395234 Disconnecting from shell: Finalise
10990 18:04:03.395601 / #
10991 18:04:03.496469 end: 4.2 read-feedback (duration 00:00:01) [common]
10992 18:04:03.497105 end: 4 finalize (duration 00:00:01) [common]
10993 18:04:03.497717 Cleaning after the job
10994 18:04:03.498280 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/ramdisk
10995 18:04:03.508444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/kernel
10996 18:04:03.542305 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/dtb
10997 18:04:03.542662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/nfsrootfs
10998 18:04:03.609189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291331/tftp-deploy-q2673t4g/modules
10999 18:04:03.614561 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291331
11000 18:04:04.129691 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291331
11001 18:04:04.129859 Job finished correctly