Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:08:02.820714 lava-dispatcher, installed at version: 2024.03
2 18:08:02.820922 start: 0 validate
3 18:08:02.821053 Start time: 2024-06-11 18:08:02.821040+00:00 (UTC)
4 18:08:02.821169 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:08:02.821298 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:08:03.089227 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:08:03.089399 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:08:03.354838 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:08:03.355010 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:08:03.620422 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:08:03.620665 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:08:03.885548 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:08:03.885725 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:08:04.152289 validate duration: 1.33
16 18:08:04.152598 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:08:04.152697 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:08:04.152789 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:08:04.152912 Not decompressing ramdisk as can be used compressed.
20 18:08:04.153023 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:08:04.153118 saving as /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/ramdisk/initrd.cpio.gz
22 18:08:04.153217 total size: 5628169 (5 MB)
23 18:08:04.154297 progress 0 % (0 MB)
24 18:08:04.155888 progress 5 % (0 MB)
25 18:08:04.157584 progress 10 % (0 MB)
26 18:08:04.158991 progress 15 % (0 MB)
27 18:08:04.160563 progress 20 % (1 MB)
28 18:08:04.162078 progress 25 % (1 MB)
29 18:08:04.163640 progress 30 % (1 MB)
30 18:08:04.165220 progress 35 % (1 MB)
31 18:08:04.166693 progress 40 % (2 MB)
32 18:08:04.168233 progress 45 % (2 MB)
33 18:08:04.169625 progress 50 % (2 MB)
34 18:08:04.171254 progress 55 % (2 MB)
35 18:08:04.172843 progress 60 % (3 MB)
36 18:08:04.174350 progress 65 % (3 MB)
37 18:08:04.175925 progress 70 % (3 MB)
38 18:08:04.177381 progress 75 % (4 MB)
39 18:08:04.179012 progress 80 % (4 MB)
40 18:08:04.180391 progress 85 % (4 MB)
41 18:08:04.181976 progress 90 % (4 MB)
42 18:08:04.183628 progress 95 % (5 MB)
43 18:08:04.185221 progress 100 % (5 MB)
44 18:08:04.185439 5 MB downloaded in 0.03 s (166.58 MB/s)
45 18:08:04.185595 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:08:04.185846 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:08:04.185955 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:08:04.186080 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:08:04.186262 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:08:04.186367 saving as /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/kernel/Image
52 18:08:04.186434 total size: 54813184 (52 MB)
53 18:08:04.186503 No compression specified
54 18:08:04.187594 progress 0 % (0 MB)
55 18:08:04.202127 progress 5 % (2 MB)
56 18:08:04.216810 progress 10 % (5 MB)
57 18:08:04.231043 progress 15 % (7 MB)
58 18:08:04.245570 progress 20 % (10 MB)
59 18:08:04.260074 progress 25 % (13 MB)
60 18:08:04.274766 progress 30 % (15 MB)
61 18:08:04.289734 progress 35 % (18 MB)
62 18:08:04.304527 progress 40 % (20 MB)
63 18:08:04.319418 progress 45 % (23 MB)
64 18:08:04.334098 progress 50 % (26 MB)
65 18:08:04.348590 progress 55 % (28 MB)
66 18:08:04.362804 progress 60 % (31 MB)
67 18:08:04.377183 progress 65 % (34 MB)
68 18:08:04.391319 progress 70 % (36 MB)
69 18:08:04.405607 progress 75 % (39 MB)
70 18:08:04.419816 progress 80 % (41 MB)
71 18:08:04.433881 progress 85 % (44 MB)
72 18:08:04.448056 progress 90 % (47 MB)
73 18:08:04.461890 progress 95 % (49 MB)
74 18:08:04.475392 progress 100 % (52 MB)
75 18:08:04.475616 52 MB downloaded in 0.29 s (180.77 MB/s)
76 18:08:04.475765 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:08:04.476000 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:08:04.476099 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:08:04.476191 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:08:04.476328 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:08:04.476398 saving as /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/dtb/mt8192-asurada-spherion-r0.dtb
83 18:08:04.476457 total size: 47258 (0 MB)
84 18:08:04.476520 No compression specified
85 18:08:04.477611 progress 69 % (0 MB)
86 18:08:04.477886 progress 100 % (0 MB)
87 18:08:04.478045 0 MB downloaded in 0.00 s (28.44 MB/s)
88 18:08:04.478165 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:08:04.478394 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:08:04.478493 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:08:04.478616 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:08:04.478768 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:08:04.478851 saving as /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/nfsrootfs/full.rootfs.tar
95 18:08:04.478912 total size: 120894716 (115 MB)
96 18:08:04.478974 Using unxz to decompress xz
97 18:08:04.482610 progress 0 % (0 MB)
98 18:08:04.832184 progress 5 % (5 MB)
99 18:08:05.188070 progress 10 % (11 MB)
100 18:08:05.538904 progress 15 % (17 MB)
101 18:08:05.867200 progress 20 % (23 MB)
102 18:08:06.163424 progress 25 % (28 MB)
103 18:08:06.523865 progress 30 % (34 MB)
104 18:08:06.887612 progress 35 % (40 MB)
105 18:08:07.058563 progress 40 % (46 MB)
106 18:08:07.240077 progress 45 % (51 MB)
107 18:08:07.575069 progress 50 % (57 MB)
108 18:08:07.975997 progress 55 % (63 MB)
109 18:08:08.346139 progress 60 % (69 MB)
110 18:08:08.698598 progress 65 % (74 MB)
111 18:08:09.056370 progress 70 % (80 MB)
112 18:08:09.421360 progress 75 % (86 MB)
113 18:08:09.774465 progress 80 % (92 MB)
114 18:08:10.128060 progress 85 % (98 MB)
115 18:08:10.496930 progress 90 % (103 MB)
116 18:08:10.843366 progress 95 % (109 MB)
117 18:08:11.211333 progress 100 % (115 MB)
118 18:08:11.216859 115 MB downloaded in 6.74 s (17.11 MB/s)
119 18:08:11.217112 end: 1.4.1 http-download (duration 00:00:07) [common]
121 18:08:11.217381 end: 1.4 download-retry (duration 00:00:07) [common]
122 18:08:11.217474 start: 1.5 download-retry (timeout 00:09:53) [common]
123 18:08:11.217562 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 18:08:11.217715 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:08:11.217789 saving as /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/modules/modules.tar
126 18:08:11.217852 total size: 8618176 (8 MB)
127 18:08:11.217918 Using unxz to decompress xz
128 18:08:11.221421 progress 0 % (0 MB)
129 18:08:11.240988 progress 5 % (0 MB)
130 18:08:11.268741 progress 10 % (0 MB)
131 18:08:11.299066 progress 15 % (1 MB)
132 18:08:11.323514 progress 20 % (1 MB)
133 18:08:11.347340 progress 25 % (2 MB)
134 18:08:11.371407 progress 30 % (2 MB)
135 18:08:11.398035 progress 35 % (2 MB)
136 18:08:11.423454 progress 40 % (3 MB)
137 18:08:11.447035 progress 45 % (3 MB)
138 18:08:11.471813 progress 50 % (4 MB)
139 18:08:11.498208 progress 55 % (4 MB)
140 18:08:11.523044 progress 60 % (4 MB)
141 18:08:11.548213 progress 65 % (5 MB)
142 18:08:11.576460 progress 70 % (5 MB)
143 18:08:11.600687 progress 75 % (6 MB)
144 18:08:11.627144 progress 80 % (6 MB)
145 18:08:11.652172 progress 85 % (7 MB)
146 18:08:11.678311 progress 90 % (7 MB)
147 18:08:11.704471 progress 95 % (7 MB)
148 18:08:11.732011 progress 100 % (8 MB)
149 18:08:11.736500 8 MB downloaded in 0.52 s (15.85 MB/s)
150 18:08:11.736825 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:08:11.737111 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:08:11.737217 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 18:08:11.737345 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 18:08:15.103674 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e
156 18:08:15.103859 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 18:08:15.103962 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 18:08:15.104192 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf
159 18:08:15.104320 makedir: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin
160 18:08:15.104417 makedir: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/tests
161 18:08:15.104511 makedir: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/results
162 18:08:15.104647 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-add-keys
163 18:08:15.104784 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-add-sources
164 18:08:15.104906 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-background-process-start
165 18:08:15.105026 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-background-process-stop
166 18:08:15.105143 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-common-functions
167 18:08:15.105265 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-echo-ipv4
168 18:08:15.105380 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-install-packages
169 18:08:15.105495 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-installed-packages
170 18:08:15.105608 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-os-build
171 18:08:15.105723 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-probe-channel
172 18:08:15.105837 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-probe-ip
173 18:08:15.105950 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-target-ip
174 18:08:15.106064 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-target-mac
175 18:08:15.106178 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-target-storage
176 18:08:15.106294 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-case
177 18:08:15.106455 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-event
178 18:08:15.106583 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-feedback
179 18:08:15.106696 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-raise
180 18:08:15.106809 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-reference
181 18:08:15.106922 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-runner
182 18:08:15.107041 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-set
183 18:08:15.107157 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-test-shell
184 18:08:15.107273 Updating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-add-keys (debian)
185 18:08:15.107414 Updating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-add-sources (debian)
186 18:08:15.107555 Updating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-install-packages (debian)
187 18:08:15.107684 Updating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-installed-packages (debian)
188 18:08:15.107811 Updating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/bin/lava-os-build (debian)
189 18:08:15.107931 Creating /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/environment
190 18:08:15.108025 LAVA metadata
191 18:08:15.108089 - LAVA_JOB_ID=14291472
192 18:08:15.108149 - LAVA_DISPATCHER_IP=192.168.201.1
193 18:08:15.108246 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 18:08:15.108309 skipped lava-vland-overlay
195 18:08:15.108380 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 18:08:15.108456 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 18:08:15.108514 skipped lava-multinode-overlay
198 18:08:15.108620 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 18:08:15.108698 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 18:08:15.108768 Loading test definitions
201 18:08:15.108853 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 18:08:15.108923 Using /lava-14291472 at stage 0
203 18:08:15.109183 uuid=14291472_1.6.2.3.1 testdef=None
204 18:08:15.109268 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 18:08:15.109349 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 18:08:15.109811 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 18:08:15.110028 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 18:08:15.110557 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 18:08:15.110785 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 18:08:15.111299 runner path: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/0/tests/0_timesync-off test_uuid 14291472_1.6.2.3.1
213 18:08:15.111449 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 18:08:15.111666 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 18:08:15.111735 Using /lava-14291472 at stage 0
217 18:08:15.111830 Fetching tests from https://github.com/kernelci/test-definitions.git
218 18:08:15.111913 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/0/tests/1_kselftest-tpm2'
219 18:08:17.093534 Running '/usr/bin/git checkout kernelci.org
220 18:08:17.170115 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 18:08:17.170824 uuid=14291472_1.6.2.3.5 testdef=None
222 18:08:17.170984 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 18:08:17.171232 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 18:08:17.171962 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 18:08:17.172193 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 18:08:17.173198 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 18:08:17.173437 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 18:08:17.174349 runner path: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/0/tests/1_kselftest-tpm2 test_uuid 14291472_1.6.2.3.5
232 18:08:17.174442 BOARD='mt8192-asurada-spherion-r0'
233 18:08:17.174508 BRANCH='cip'
234 18:08:17.174568 SKIPFILE='/dev/null'
235 18:08:17.174628 SKIP_INSTALL='True'
236 18:08:17.174687 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 18:08:17.174745 TST_CASENAME=''
238 18:08:17.174801 TST_CMDFILES='tpm2'
239 18:08:17.174939 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 18:08:17.175143 Creating lava-test-runner.conf files
242 18:08:17.175207 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291472/lava-overlay-h6sbibpf/lava-14291472/0 for stage 0
243 18:08:17.175298 - 0_timesync-off
244 18:08:17.175368 - 1_kselftest-tpm2
245 18:08:17.175488 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 18:08:17.175632 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 18:08:24.918886 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 18:08:24.919087 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 18:08:24.919219 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 18:08:24.919358 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 18:08:24.919484 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 18:08:25.080374 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 18:08:25.080776 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 18:08:25.080895 extracting modules file /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e
255 18:08:25.283379 extracting modules file /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291472/extract-overlay-ramdisk-o7_uz9bh/ramdisk
256 18:08:25.500676 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 18:08:25.500869 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 18:08:25.500971 [common] Applying overlay to NFS
259 18:08:25.501045 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291472/compress-overlay-6scnabc7/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e
260 18:08:26.441156 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 18:08:26.441319 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 18:08:26.441427 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 18:08:26.441522 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 18:08:26.441607 Building ramdisk /var/lib/lava/dispatcher/tmp/14291472/extract-overlay-ramdisk-o7_uz9bh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291472/extract-overlay-ramdisk-o7_uz9bh/ramdisk
265 18:08:26.748954 >> 130400 blocks
266 18:08:28.800958 rename /var/lib/lava/dispatcher/tmp/14291472/extract-overlay-ramdisk-o7_uz9bh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/ramdisk/ramdisk.cpio.gz
267 18:08:28.801397 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 18:08:28.801552 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 18:08:28.801699 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 18:08:28.801853 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/kernel/Image']
271 18:08:42.455446 Returned 0 in 13 seconds
272 18:08:42.556019 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/kernel/image.itb
273 18:08:42.977360 output: FIT description: Kernel Image image with one or more FDT blobs
274 18:08:42.977693 output: Created: Tue Jun 11 19:08:42 2024
275 18:08:42.977769 output: Image 0 (kernel-1)
276 18:08:42.977837 output: Description:
277 18:08:42.977901 output: Created: Tue Jun 11 19:08:42 2024
278 18:08:42.977963 output: Type: Kernel Image
279 18:08:42.978023 output: Compression: lzma compressed
280 18:08:42.978082 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
281 18:08:42.978137 output: Architecture: AArch64
282 18:08:42.978194 output: OS: Linux
283 18:08:42.978250 output: Load Address: 0x00000000
284 18:08:42.978307 output: Entry Point: 0x00000000
285 18:08:42.978365 output: Hash algo: crc32
286 18:08:42.978422 output: Hash value: 7a9e9d3e
287 18:08:42.978479 output: Image 1 (fdt-1)
288 18:08:42.978534 output: Description: mt8192-asurada-spherion-r0
289 18:08:42.978587 output: Created: Tue Jun 11 19:08:42 2024
290 18:08:42.978643 output: Type: Flat Device Tree
291 18:08:42.978696 output: Compression: uncompressed
292 18:08:42.978754 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 18:08:42.978807 output: Architecture: AArch64
294 18:08:42.978881 output: Hash algo: crc32
295 18:08:42.978940 output: Hash value: 0f8e4d2e
296 18:08:42.978993 output: Image 2 (ramdisk-1)
297 18:08:42.979047 output: Description: unavailable
298 18:08:42.979100 output: Created: Tue Jun 11 19:08:42 2024
299 18:08:42.979154 output: Type: RAMDisk Image
300 18:08:42.979207 output: Compression: Unknown Compression
301 18:08:42.979260 output: Data Size: 18740413 Bytes = 18301.18 KiB = 17.87 MiB
302 18:08:42.979314 output: Architecture: AArch64
303 18:08:42.979368 output: OS: Linux
304 18:08:42.979420 output: Load Address: unavailable
305 18:08:42.979473 output: Entry Point: unavailable
306 18:08:42.979525 output: Hash algo: crc32
307 18:08:42.979578 output: Hash value: 6c32b867
308 18:08:42.979631 output: Default Configuration: 'conf-1'
309 18:08:42.979685 output: Configuration 0 (conf-1)
310 18:08:42.979737 output: Description: mt8192-asurada-spherion-r0
311 18:08:42.979790 output: Kernel: kernel-1
312 18:08:42.979862 output: Init Ramdisk: ramdisk-1
313 18:08:42.979950 output: FDT: fdt-1
314 18:08:42.980017 output: Loadables: kernel-1
315 18:08:42.980070 output:
316 18:08:42.980262 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 18:08:42.980359 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 18:08:42.980463 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 18:08:42.980578 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 18:08:42.980674 No LXC device requested
321 18:08:42.980751 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 18:08:42.980840 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 18:08:42.980919 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 18:08:42.980987 Checking files for TFTP limit of 4294967296 bytes.
325 18:08:42.981462 end: 1 tftp-deploy (duration 00:00:39) [common]
326 18:08:42.981571 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 18:08:42.981660 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 18:08:42.981787 substitutions:
329 18:08:42.981856 - {DTB}: 14291472/tftp-deploy-rq3g_akw/dtb/mt8192-asurada-spherion-r0.dtb
330 18:08:42.981922 - {INITRD}: 14291472/tftp-deploy-rq3g_akw/ramdisk/ramdisk.cpio.gz
331 18:08:42.981984 - {KERNEL}: 14291472/tftp-deploy-rq3g_akw/kernel/Image
332 18:08:42.982068 - {LAVA_MAC}: None
333 18:08:42.982129 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e
334 18:08:42.982188 - {NFS_SERVER_IP}: 192.168.201.1
335 18:08:42.982245 - {PRESEED_CONFIG}: None
336 18:08:42.982303 - {PRESEED_LOCAL}: None
337 18:08:42.982359 - {RAMDISK}: 14291472/tftp-deploy-rq3g_akw/ramdisk/ramdisk.cpio.gz
338 18:08:42.982416 - {ROOT_PART}: None
339 18:08:42.982471 - {ROOT}: None
340 18:08:42.982526 - {SERVER_IP}: 192.168.201.1
341 18:08:42.982580 - {TEE}: None
342 18:08:42.982635 Parsed boot commands:
343 18:08:42.982689 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 18:08:42.982865 Parsed boot commands: tftpboot 192.168.201.1 14291472/tftp-deploy-rq3g_akw/kernel/image.itb 14291472/tftp-deploy-rq3g_akw/kernel/cmdline
345 18:08:42.982956 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 18:08:42.983043 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 18:08:42.983136 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 18:08:42.983223 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 18:08:42.983295 Not connected, no need to disconnect.
350 18:08:42.983368 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 18:08:42.983451 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 18:08:42.983519 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 18:08:42.986694 Setting prompt string to ['lava-test: # ']
354 18:08:42.987034 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 18:08:42.987144 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 18:08:42.987243 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 18:08:42.987337 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 18:08:42.987538 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 18:08:56.601889 Returned 0 in 13 seconds
360 18:08:56.702553 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 18:08:56.702887 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 18:08:56.703009 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 18:08:56.703110 Setting prompt string to 'Starting depthcharge on Spherion...'
365 18:08:56.703191 Changing prompt to 'Starting depthcharge on Spherion...'
366 18:08:56.703282 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 18:08:56.703839 [Enter `^Ec?' for help]
368 18:08:56.703956
369 18:08:56.704064
370 18:08:56.704165 F0: 102B 0000
371 18:08:56.704265
372 18:08:56.704361 F3: 1001 0000 [0200]
373 18:08:56.704476
374 18:08:56.704596 F3: 1001 0000
375 18:08:56.704674
376 18:08:56.704768 F7: 102D 0000
377 18:08:56.704862
378 18:08:56.704956 F1: 0000 0000
379 18:08:56.705049
380 18:08:56.705141 V0: 0000 0000 [0001]
381 18:08:56.705233
382 18:08:56.705325 00: 0007 8000
383 18:08:56.705420
384 18:08:56.705511 01: 0000 0000
385 18:08:56.705606
386 18:08:56.705697 BP: 0C00 0209 [0000]
387 18:08:56.705789
388 18:08:56.705880 G0: 1182 0000
389 18:08:56.705971
390 18:08:56.706062 EC: 0000 0021 [4000]
391 18:08:56.706154
392 18:08:56.706245 S7: 0000 0000 [0000]
393 18:08:56.706336
394 18:08:56.706427 CC: 0000 0000 [0001]
395 18:08:56.706518
396 18:08:56.706609 T0: 0000 0040 [010F]
397 18:08:56.706701
398 18:08:56.706791 Jump to BL
399 18:08:56.706883
400 18:08:56.706973
401 18:08:56.707064
402 18:08:56.707155 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 18:08:56.707251 ARM64: Exception handlers installed.
404 18:08:56.707344 ARM64: Testing exception
405 18:08:56.707436 ARM64: Done test exception
406 18:08:56.707526 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 18:08:56.707618 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 18:08:56.707711 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 18:08:56.707803 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 18:08:56.707895 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 18:08:56.707987 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 18:08:56.708079 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 18:08:56.708172 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 18:08:56.708264 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 18:08:56.708355 WDT: Last reset was cold boot
416 18:08:56.708446 SPI1(PAD0) initialized at 2873684 Hz
417 18:08:56.708537 SPI5(PAD0) initialized at 992727 Hz
418 18:08:56.708664 VBOOT: Loading verstage.
419 18:08:56.708755 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 18:08:56.708847 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 18:08:56.708939 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 18:08:56.709031 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 18:08:56.709124 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 18:08:56.709217 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 18:08:56.709309 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 18:08:56.709401
427 18:08:56.709491
428 18:08:56.709582 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 18:08:56.709674 ARM64: Exception handlers installed.
430 18:08:56.709765 ARM64: Testing exception
431 18:08:56.709856 ARM64: Done test exception
432 18:08:56.709947 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 18:08:56.710039 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 18:08:56.710131 Probing TPM: . done!
435 18:08:56.710222 TPM ready after 0 ms
436 18:08:56.710313 Connected to device vid:did:rid of 1ae0:0028:00
437 18:08:56.710404 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 18:08:56.710496 Initialized TPM device CR50 revision 0
439 18:08:56.710588 tlcl_send_startup: Startup return code is 0
440 18:08:56.710679 TPM: setup succeeded
441 18:08:56.710771 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 18:08:56.710862 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 18:08:56.710954 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 18:08:56.711045 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 18:08:56.711137 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 18:08:56.711229 in-header: 03 07 00 00 08 00 00 00
447 18:08:56.711320 in-data: aa e4 47 04 13 02 00 00
448 18:08:56.711410 Chrome EC: UHEPI supported
449 18:08:56.711501 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 18:08:56.711593 in-header: 03 a9 00 00 08 00 00 00
451 18:08:56.711684 in-data: 84 60 60 08 00 00 00 00
452 18:08:56.711775 Phase 1
453 18:08:56.711865 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 18:08:56.711957 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 18:08:56.712049 VB2:vb2_check_recovery() Recovery was requested manually
456 18:08:56.712141 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 18:08:56.712233 Recovery requested (1009000e)
458 18:08:56.712324 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 18:08:56.712415 tlcl_extend: response is 0
460 18:08:56.712506 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 18:08:56.712605 tlcl_extend: response is 0
462 18:08:56.712698 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 18:08:56.712790 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 18:08:56.712882 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 18:08:56.712974
466 18:08:56.713065
467 18:08:56.713156 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 18:08:56.713248 ARM64: Exception handlers installed.
469 18:08:56.713340 ARM64: Testing exception
470 18:08:56.713431 ARM64: Done test exception
471 18:08:56.713522 pmic_efuse_setting: Set efuses in 11 msecs
472 18:08:56.713613 pmwrap_interface_init: Select PMIF_VLD_RDY
473 18:08:56.713704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 18:08:56.713795 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 18:08:56.714080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 18:08:56.714173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 18:08:56.714268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 18:08:56.714361 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 18:08:56.714455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 18:08:56.714547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 18:08:56.714639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 18:08:56.714731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 18:08:56.714822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 18:08:56.714914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 18:08:56.715005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 18:08:56.715096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 18:08:56.715187 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 18:08:56.715279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 18:08:56.715371 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 18:08:56.715462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 18:08:56.715554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 18:08:56.715645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 18:08:56.715736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 18:08:56.715827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 18:08:56.715918 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 18:08:56.716009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 18:08:56.716100 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 18:08:56.716191 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 18:08:56.716283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 18:08:56.716374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 18:08:56.716465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 18:08:56.716593 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 18:08:56.716686 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 18:08:56.716778 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 18:08:56.716870 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 18:08:56.716961 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 18:08:56.717053 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 18:08:56.717144 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 18:08:56.717235 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 18:08:56.717326 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 18:08:56.717417 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 18:08:56.717508 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 18:08:56.717599 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 18:08:56.717691 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 18:08:56.717782 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 18:08:56.717872 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 18:08:56.717963 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 18:08:56.718054 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 18:08:56.718145 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 18:08:56.718237 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 18:08:56.718328 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 18:08:56.718418 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 18:08:56.718510 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 18:08:56.718601 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 18:08:56.718693 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 18:08:56.718784 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 18:08:56.718875 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 18:08:56.718967 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 18:08:56.719059 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 18:08:56.719151 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 18:08:56.719242 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 18:08:56.719333 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
533 18:08:56.719424 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 18:08:56.719516 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 18:08:56.719607 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 18:08:56.719698 [RTC]rtc_get_frequency_meter,154: input=15, output=772
537 18:08:56.719789 [RTC]rtc_get_frequency_meter,154: input=23, output=957
538 18:08:56.719879 [RTC]rtc_get_frequency_meter,154: input=19, output=864
539 18:08:56.719970 [RTC]rtc_get_frequency_meter,154: input=17, output=817
540 18:08:56.720061 [RTC]rtc_get_frequency_meter,154: input=16, output=795
541 18:08:56.720151 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 18:08:56.720241 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 18:08:56.720332 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 18:08:56.720422 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 18:08:56.720703 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 18:08:56.720796 ADC[4]: Raw value=902139 ID=7
547 18:08:56.720891 ADC[3]: Raw value=213179 ID=1
548 18:08:56.720983 RAM Code: 0x71
549 18:08:56.721075 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 18:08:56.721168 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 18:08:56.721261 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 18:08:56.721354 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 18:08:56.721447 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 18:08:56.721540 in-header: 03 07 00 00 08 00 00 00
555 18:08:56.721631 in-data: aa e4 47 04 13 02 00 00
556 18:08:56.721723 Chrome EC: UHEPI supported
557 18:08:56.721814 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 18:08:56.721906 in-header: 03 a9 00 00 08 00 00 00
559 18:08:56.721998 in-data: 84 60 60 08 00 00 00 00
560 18:08:56.722089 MRC: failed to locate region type 0.
561 18:08:56.722181 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 18:08:56.722273 DRAM-K: Running full calibration
563 18:08:56.722364 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 18:08:56.722456 header.status = 0x0
565 18:08:56.722547 header.version = 0x6 (expected: 0x6)
566 18:08:56.722638 header.size = 0xd00 (expected: 0xd00)
567 18:08:56.722728 header.flags = 0x0
568 18:08:56.722820 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 18:08:56.722912 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
570 18:08:56.723004 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 18:08:56.723095 dram_init: ddr_geometry: 2
572 18:08:56.723186 [EMI] MDL number = 2
573 18:08:56.723277 [EMI] Get MDL freq = 0
574 18:08:56.723367 dram_init: ddr_type: 0
575 18:08:56.723457 is_discrete_lpddr4: 1
576 18:08:56.723548 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 18:08:56.723638
578 18:08:56.723729
579 18:08:56.723819 [Bian_co] ETT version 0.0.0.1
580 18:08:56.723910 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 18:08:56.724001
582 18:08:56.724091 dramc_set_vcore_voltage set vcore to 650000
583 18:08:56.724183 Read voltage for 800, 4
584 18:08:56.724273 Vio18 = 0
585 18:08:56.724364 Vcore = 650000
586 18:08:56.724454 Vdram = 0
587 18:08:56.724548 Vddq = 0
588 18:08:56.724673 Vmddr = 0
589 18:08:56.724764 dram_init: config_dvfs: 1
590 18:08:56.724856 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 18:08:56.724948 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 18:08:56.725041 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 18:08:56.725133 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 18:08:56.725228 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 18:08:56.725319 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 18:08:56.725411 MEM_TYPE=3, freq_sel=18
597 18:08:56.725502 sv_algorithm_assistance_LP4_1600
598 18:08:56.725593 ============ PULL DRAM RESETB DOWN ============
599 18:08:56.725687 ========== PULL DRAM RESETB DOWN end =========
600 18:08:56.725779 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 18:08:56.725871 ===================================
602 18:08:56.725962 LPDDR4 DRAM CONFIGURATION
603 18:08:56.726053 ===================================
604 18:08:56.726144 EX_ROW_EN[0] = 0x0
605 18:08:56.726235 EX_ROW_EN[1] = 0x0
606 18:08:56.726325 LP4Y_EN = 0x0
607 18:08:56.726417 WORK_FSP = 0x0
608 18:08:56.726507 WL = 0x2
609 18:08:56.726598 RL = 0x2
610 18:08:56.726688 BL = 0x2
611 18:08:56.726779 RPST = 0x0
612 18:08:56.726877 RD_PRE = 0x0
613 18:08:56.726971 WR_PRE = 0x1
614 18:08:56.727062 WR_PST = 0x0
615 18:08:56.727153 DBI_WR = 0x0
616 18:08:56.727244 DBI_RD = 0x0
617 18:08:56.727334 OTF = 0x1
618 18:08:56.727426 ===================================
619 18:08:56.727519 ===================================
620 18:08:56.727611 ANA top config
621 18:08:56.727702 ===================================
622 18:08:56.727793 DLL_ASYNC_EN = 0
623 18:08:56.727884 ALL_SLAVE_EN = 1
624 18:08:56.727975 NEW_RANK_MODE = 1
625 18:08:56.728067 DLL_IDLE_MODE = 1
626 18:08:56.728158 LP45_APHY_COMB_EN = 1
627 18:08:56.728249 TX_ODT_DIS = 1
628 18:08:56.728340 NEW_8X_MODE = 1
629 18:08:56.728431 ===================================
630 18:08:56.728523 ===================================
631 18:08:56.728622 data_rate = 1600
632 18:08:56.728714 CKR = 1
633 18:08:56.728806 DQ_P2S_RATIO = 8
634 18:08:56.728897 ===================================
635 18:08:56.728989 CA_P2S_RATIO = 8
636 18:08:56.729080 DQ_CA_OPEN = 0
637 18:08:56.729171 DQ_SEMI_OPEN = 0
638 18:08:56.729262 CA_SEMI_OPEN = 0
639 18:08:56.729353 CA_FULL_RATE = 0
640 18:08:56.729443 DQ_CKDIV4_EN = 1
641 18:08:56.729534 CA_CKDIV4_EN = 1
642 18:08:56.729624 CA_PREDIV_EN = 0
643 18:08:56.729715 PH8_DLY = 0
644 18:08:56.729806 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 18:08:56.729896 DQ_AAMCK_DIV = 4
646 18:08:56.729987 CA_AAMCK_DIV = 4
647 18:08:56.730077 CA_ADMCK_DIV = 4
648 18:08:56.730167 DQ_TRACK_CA_EN = 0
649 18:08:56.730258 CA_PICK = 800
650 18:08:56.730348 CA_MCKIO = 800
651 18:08:56.730439 MCKIO_SEMI = 0
652 18:08:56.730529 PLL_FREQ = 3068
653 18:08:56.730629 DQ_UI_PI_RATIO = 32
654 18:08:56.730721 CA_UI_PI_RATIO = 0
655 18:08:56.730813 ===================================
656 18:08:56.730905 ===================================
657 18:08:56.730996 memory_type:LPDDR4
658 18:08:56.731087 GP_NUM : 10
659 18:08:56.731178 SRAM_EN : 1
660 18:08:56.731269 MD32_EN : 0
661 18:08:56.731360 ===================================
662 18:08:56.731452 [ANA_INIT] >>>>>>>>>>>>>>
663 18:08:56.731543 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 18:08:56.731668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 18:08:56.731760 ===================================
666 18:08:56.732058 data_rate = 1600,PCW = 0X7600
667 18:08:56.732152 ===================================
668 18:08:56.732248 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 18:08:56.732342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 18:08:56.732436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 18:08:56.732529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 18:08:56.732662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 18:08:56.732756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 18:08:56.732848 [ANA_INIT] flow start
675 18:08:56.732940 [ANA_INIT] PLL >>>>>>>>
676 18:08:56.733032 [ANA_INIT] PLL <<<<<<<<
677 18:08:56.733124 [ANA_INIT] MIDPI >>>>>>>>
678 18:08:56.733216 [ANA_INIT] MIDPI <<<<<<<<
679 18:08:56.733307 [ANA_INIT] DLL >>>>>>>>
680 18:08:56.733398 [ANA_INIT] flow end
681 18:08:56.733489 ============ LP4 DIFF to SE enter ============
682 18:08:56.733580 ============ LP4 DIFF to SE exit ============
683 18:08:56.733672 [ANA_INIT] <<<<<<<<<<<<<
684 18:08:56.733764 [Flow] Enable top DCM control >>>>>
685 18:08:56.733855 [Flow] Enable top DCM control <<<<<
686 18:08:56.733946 Enable DLL master slave shuffle
687 18:08:56.734038 ==============================================================
688 18:08:56.734129 Gating Mode config
689 18:08:56.734221 ==============================================================
690 18:08:56.734312 Config description:
691 18:08:56.734404 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 18:08:56.734496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 18:08:56.734587 SELPH_MODE 0: By rank 1: By Phase
694 18:08:56.734679 ==============================================================
695 18:08:56.734771 GAT_TRACK_EN = 1
696 18:08:56.734863 RX_GATING_MODE = 2
697 18:08:56.734953 RX_GATING_TRACK_MODE = 2
698 18:08:56.735044 SELPH_MODE = 1
699 18:08:56.735135 PICG_EARLY_EN = 1
700 18:08:56.735226 VALID_LAT_VALUE = 1
701 18:08:56.735317 ==============================================================
702 18:08:56.735408 Enter into Gating configuration >>>>
703 18:08:56.735500 Exit from Gating configuration <<<<
704 18:08:56.735591 Enter into DVFS_PRE_config >>>>>
705 18:08:56.735683 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 18:08:56.735779 Exit from DVFS_PRE_config <<<<<
707 18:08:56.735870 Enter into PICG configuration >>>>
708 18:08:56.735961 Exit from PICG configuration <<<<
709 18:08:56.736053 [RX_INPUT] configuration >>>>>
710 18:08:56.736144 [RX_INPUT] configuration <<<<<
711 18:08:56.736235 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 18:08:56.736326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 18:08:56.736418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 18:08:56.736525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 18:08:56.736637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 18:08:56.736729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 18:08:56.736820 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 18:08:56.736911 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 18:08:56.737003 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 18:08:56.737094 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 18:08:56.737186 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 18:08:56.737277 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 18:08:56.737369 ===================================
724 18:08:56.737460 LPDDR4 DRAM CONFIGURATION
725 18:08:56.737551 ===================================
726 18:08:56.737642 EX_ROW_EN[0] = 0x0
727 18:08:56.737733 EX_ROW_EN[1] = 0x0
728 18:08:56.737823 LP4Y_EN = 0x0
729 18:08:56.737915 WORK_FSP = 0x0
730 18:08:56.738006 WL = 0x2
731 18:08:56.738097 RL = 0x2
732 18:08:56.738187 BL = 0x2
733 18:08:56.738278 RPST = 0x0
734 18:08:56.738369 RD_PRE = 0x0
735 18:08:56.738459 WR_PRE = 0x1
736 18:08:56.738550 WR_PST = 0x0
737 18:08:56.738641 DBI_WR = 0x0
738 18:08:56.738731 DBI_RD = 0x0
739 18:08:56.738822 OTF = 0x1
740 18:08:56.738913 ===================================
741 18:08:56.739004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 18:08:56.739095 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 18:08:56.739186 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 18:08:56.739276 ===================================
745 18:08:56.739367 LPDDR4 DRAM CONFIGURATION
746 18:08:56.739458 ===================================
747 18:08:56.739548 EX_ROW_EN[0] = 0x10
748 18:08:56.739638 EX_ROW_EN[1] = 0x0
749 18:08:56.739728 LP4Y_EN = 0x0
750 18:08:56.739818 WORK_FSP = 0x0
751 18:08:56.739908 WL = 0x2
752 18:08:56.739999 RL = 0x2
753 18:08:56.740089 BL = 0x2
754 18:08:56.740179 RPST = 0x0
755 18:08:56.740269 RD_PRE = 0x0
756 18:08:56.740360 WR_PRE = 0x1
757 18:08:56.740450 WR_PST = 0x0
758 18:08:56.740586 DBI_WR = 0x0
759 18:08:56.740678 DBI_RD = 0x0
760 18:08:56.740768 OTF = 0x1
761 18:08:56.740859 ===================================
762 18:08:56.740951 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 18:08:56.741042 nWR fixed to 40
764 18:08:56.741133 [ModeRegInit_LP4] CH0 RK0
765 18:08:56.741235 [ModeRegInit_LP4] CH0 RK1
766 18:08:56.741327 [ModeRegInit_LP4] CH1 RK0
767 18:08:56.741419 [ModeRegInit_LP4] CH1 RK1
768 18:08:56.741510 match AC timing 13
769 18:08:56.741601 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 18:08:56.741693 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 18:08:56.741785 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 18:08:56.741876 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 18:08:56.742166 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 18:08:56.742261 [EMI DOE] emi_dcm 0
775 18:08:56.742357 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 18:08:56.742451 ==
777 18:08:56.742544 Dram Type= 6, Freq= 0, CH_0, rank 0
778 18:08:56.742637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 18:08:56.742730 ==
780 18:08:56.742822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 18:08:56.742914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 18:08:56.743006 [CA 0] Center 38 (7~69) winsize 63
783 18:08:56.743098 [CA 1] Center 38 (7~69) winsize 63
784 18:08:56.743199 [CA 2] Center 35 (5~66) winsize 62
785 18:08:56.743296 [CA 3] Center 35 (5~66) winsize 62
786 18:08:56.743384 [CA 4] Center 34 (4~65) winsize 62
787 18:08:56.743470 [CA 5] Center 33 (3~64) winsize 62
788 18:08:56.743554
789 18:08:56.743638 [CmdBusTrainingLP45] Vref(ca) range 1: 34
790 18:08:56.743721
791 18:08:56.743805 [CATrainingPosCal] consider 1 rank data
792 18:08:56.743888 u2DelayCellTimex100 = 270/100 ps
793 18:08:56.743972 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 18:08:56.744056 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 18:08:56.744139 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 18:08:56.744222 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 18:08:56.744305 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
798 18:08:56.744389 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 18:08:56.744471
800 18:08:56.744561 CA PerBit enable=1, Macro0, CA PI delay=33
801 18:08:56.744645
802 18:08:56.744728 [CBTSetCACLKResult] CA Dly = 33
803 18:08:56.744811 CS Dly: 6 (0~37)
804 18:08:56.744893 ==
805 18:08:56.744976 Dram Type= 6, Freq= 0, CH_0, rank 1
806 18:08:56.745060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 18:08:56.745142 ==
808 18:08:56.745226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 18:08:56.745311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 18:08:56.745395 [CA 0] Center 38 (7~69) winsize 63
811 18:08:56.745478 [CA 1] Center 38 (8~69) winsize 62
812 18:08:56.745561 [CA 2] Center 36 (6~67) winsize 62
813 18:08:56.745644 [CA 3] Center 35 (5~66) winsize 62
814 18:08:56.745726 [CA 4] Center 35 (4~66) winsize 63
815 18:08:56.745809 [CA 5] Center 34 (4~65) winsize 62
816 18:08:56.745890
817 18:08:56.745973 [CmdBusTrainingLP45] Vref(ca) range 1: 32
818 18:08:56.746055
819 18:08:56.746138 [CATrainingPosCal] consider 2 rank data
820 18:08:56.746220 u2DelayCellTimex100 = 270/100 ps
821 18:08:56.746303 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 18:08:56.746386 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 18:08:56.746470 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 18:08:56.746553 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 18:08:56.746636 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
826 18:08:56.746719 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 18:08:56.746801
828 18:08:56.746884 CA PerBit enable=1, Macro0, CA PI delay=34
829 18:08:56.746966
830 18:08:56.747048 [CBTSetCACLKResult] CA Dly = 34
831 18:08:56.747134 CS Dly: 6 (0~38)
832 18:08:56.747235
833 18:08:56.747325 ----->DramcWriteLeveling(PI) begin...
834 18:08:56.747410 ==
835 18:08:56.747494 Dram Type= 6, Freq= 0, CH_0, rank 0
836 18:08:56.747578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 18:08:56.747661 ==
838 18:08:56.747744 Write leveling (Byte 0): 32 => 32
839 18:08:56.747827 Write leveling (Byte 1): 31 => 31
840 18:08:56.747911 DramcWriteLeveling(PI) end<-----
841 18:08:56.747993
842 18:08:56.748075 ==
843 18:08:56.748158 Dram Type= 6, Freq= 0, CH_0, rank 0
844 18:08:56.748241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 18:08:56.748324 ==
846 18:08:56.748407 [Gating] SW mode calibration
847 18:08:56.748491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 18:08:56.748609 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 18:08:56.748666 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 18:08:56.748720 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 18:08:56.748774 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
852 18:08:56.748827 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 18:08:56.748881 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 18:08:56.748934 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 18:08:56.748988 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 18:08:56.749040 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 18:08:56.749094 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 18:08:56.749147 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:08:56.749200 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:08:56.749253 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:08:56.749306 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:08:56.749359 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:08:56.749413 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 18:08:56.749466 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 18:08:56.749519 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
866 18:08:56.749572 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
867 18:08:56.749625 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 18:08:56.749678 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 18:08:56.749731 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 18:08:56.749784 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 18:08:56.749836 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 18:08:56.749889 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 18:08:56.749942 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 18:08:56.749995 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
875 18:08:56.750048 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
876 18:08:56.750101 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
877 18:08:56.750153 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 18:08:56.750206 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 18:08:56.750263 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 18:08:56.750323 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 18:08:56.750570 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 18:08:56.750630 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
883 18:08:56.750684 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
884 18:08:56.750782 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
885 18:08:56.750837 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 18:08:56.750891 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 18:08:56.750945 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 18:08:56.751013 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 18:08:56.751066 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 18:08:56.751119 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
891 18:08:56.751172 0 11 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
892 18:08:56.751224 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
893 18:08:56.751277 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 18:08:56.751330 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 18:08:56.751383 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 18:08:56.751436 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 18:08:56.751489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 18:08:56.751542 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 18:08:56.751595 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
900 18:08:56.751648 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 18:08:56.751700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 18:08:56.751753 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 18:08:56.751806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 18:08:56.751858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 18:08:56.751911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 18:08:56.751964 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 18:08:56.752016 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 18:08:56.752069 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 18:08:56.752122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 18:08:56.752192 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 18:08:56.752311 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 18:08:56.752410 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 18:08:56.752531 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
914 18:08:56.752638 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 18:08:56.752722 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 18:08:56.752778 Total UI for P1: 0, mck2ui 16
917 18:08:56.752834 best dqsien dly found for B0: ( 0, 14, 2)
918 18:08:56.752890 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 18:08:56.752946 Total UI for P1: 0, mck2ui 16
920 18:08:56.753056 best dqsien dly found for B1: ( 0, 14, 8)
921 18:08:56.753113 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
922 18:08:56.753182 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
923 18:08:56.753236
924 18:08:56.753306 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
925 18:08:56.753373 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
926 18:08:56.753427 [Gating] SW calibration Done
927 18:08:56.753480 ==
928 18:08:56.753533 Dram Type= 6, Freq= 0, CH_0, rank 0
929 18:08:56.753586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 18:08:56.753640 ==
931 18:08:56.753693 RX Vref Scan: 0
932 18:08:56.753807
933 18:08:56.753868 RX Vref 0 -> 0, step: 1
934 18:08:56.753936
935 18:08:56.753990 RX Delay -130 -> 252, step: 16
936 18:08:56.754043 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
937 18:08:56.754097 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 18:08:56.754150 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 18:08:56.754203 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 18:08:56.754257 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
941 18:08:56.754310 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 18:08:56.754363 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 18:08:56.754416 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 18:08:56.754499 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 18:08:56.754568 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
946 18:08:56.754622 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 18:08:56.754676 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 18:08:56.754730 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
949 18:08:56.754784 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
950 18:08:56.754850 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 18:08:56.754903 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
952 18:08:56.754956 ==
953 18:08:56.755009 Dram Type= 6, Freq= 0, CH_0, rank 0
954 18:08:56.755063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 18:08:56.755116 ==
956 18:08:56.755169 DQS Delay:
957 18:08:56.755221 DQS0 = 0, DQS1 = 0
958 18:08:56.755274 DQM Delay:
959 18:08:56.755326 DQM0 = 90, DQM1 = 80
960 18:08:56.755379 DQ Delay:
961 18:08:56.755431 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
962 18:08:56.755484 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
963 18:08:56.755537 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
964 18:08:56.755590 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
965 18:08:56.755643
966 18:08:56.755695
967 18:08:56.755747 ==
968 18:08:56.755800 Dram Type= 6, Freq= 0, CH_0, rank 0
969 18:08:56.755852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 18:08:56.755921 ==
971 18:08:56.755989
972 18:08:56.756042
973 18:08:56.756094 TX Vref Scan disable
974 18:08:56.756146 == TX Byte 0 ==
975 18:08:56.756199 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
976 18:08:56.756253 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
977 18:08:56.756306 == TX Byte 1 ==
978 18:08:56.756358 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 18:08:56.756412 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 18:08:56.756465 ==
981 18:08:56.756518 Dram Type= 6, Freq= 0, CH_0, rank 0
982 18:08:56.756612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 18:08:56.756667 ==
984 18:08:56.756720 TX Vref=22, minBit 6, minWin=27, winSum=440
985 18:08:56.756774 TX Vref=24, minBit 6, minWin=27, winSum=441
986 18:08:56.756827 TX Vref=26, minBit 8, minWin=27, winSum=446
987 18:08:56.756880 TX Vref=28, minBit 8, minWin=27, winSum=454
988 18:08:56.756933 TX Vref=30, minBit 1, minWin=28, winSum=457
989 18:08:56.757183 TX Vref=32, minBit 5, minWin=28, winSum=456
990 18:08:56.757246 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
991 18:08:56.757300
992 18:08:56.757353 Final TX Range 1 Vref 30
993 18:08:56.757407
994 18:08:56.757459 ==
995 18:08:56.757512 Dram Type= 6, Freq= 0, CH_0, rank 0
996 18:08:56.757565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 18:08:56.757618 ==
998 18:08:56.757671
999 18:08:56.757723
1000 18:08:56.757776 TX Vref Scan disable
1001 18:08:56.757828 == TX Byte 0 ==
1002 18:08:56.757881 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1003 18:08:56.757934 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1004 18:08:56.757987 == TX Byte 1 ==
1005 18:08:56.758040 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 18:08:56.758093 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 18:08:56.758146
1008 18:08:56.758198 [DATLAT]
1009 18:08:56.758251 Freq=800, CH0 RK0
1010 18:08:56.758304
1011 18:08:56.758357 DATLAT Default: 0xa
1012 18:08:56.758411 0, 0xFFFF, sum = 0
1013 18:08:56.758465 1, 0xFFFF, sum = 0
1014 18:08:56.758520 2, 0xFFFF, sum = 0
1015 18:08:56.758573 3, 0xFFFF, sum = 0
1016 18:08:56.758626 4, 0xFFFF, sum = 0
1017 18:08:56.758679 5, 0xFFFF, sum = 0
1018 18:08:56.758732 6, 0xFFFF, sum = 0
1019 18:08:56.758785 7, 0xFFFF, sum = 0
1020 18:08:56.758839 8, 0xFFFF, sum = 0
1021 18:08:56.758923 9, 0x0, sum = 1
1022 18:08:56.758976 10, 0x0, sum = 2
1023 18:08:56.759029 11, 0x0, sum = 3
1024 18:08:56.759083 12, 0x0, sum = 4
1025 18:08:56.759142 best_step = 10
1026 18:08:56.759200
1027 18:08:56.759253 ==
1028 18:08:56.759306 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 18:08:56.759359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 18:08:56.759412 ==
1031 18:08:56.759464 RX Vref Scan: 1
1032 18:08:56.759517
1033 18:08:56.759569 Set Vref Range= 32 -> 127
1034 18:08:56.759622
1035 18:08:56.759673 RX Vref 32 -> 127, step: 1
1036 18:08:56.759725
1037 18:08:56.759777 RX Delay -95 -> 252, step: 8
1038 18:08:56.759830
1039 18:08:56.759882 Set Vref, RX VrefLevel [Byte0]: 32
1040 18:08:56.759934 [Byte1]: 32
1041 18:08:56.759986
1042 18:08:56.760038 Set Vref, RX VrefLevel [Byte0]: 33
1043 18:08:56.760091 [Byte1]: 33
1044 18:08:56.760143
1045 18:08:56.760194 Set Vref, RX VrefLevel [Byte0]: 34
1046 18:08:56.760246 [Byte1]: 34
1047 18:08:56.760297
1048 18:08:56.760349 Set Vref, RX VrefLevel [Byte0]: 35
1049 18:08:56.760401 [Byte1]: 35
1050 18:08:56.760453
1051 18:08:56.760504 Set Vref, RX VrefLevel [Byte0]: 36
1052 18:08:56.760584 [Byte1]: 36
1053 18:08:56.760652
1054 18:08:56.760704 Set Vref, RX VrefLevel [Byte0]: 37
1055 18:08:56.760756 [Byte1]: 37
1056 18:08:56.760809
1057 18:08:56.760860 Set Vref, RX VrefLevel [Byte0]: 38
1058 18:08:56.760913 [Byte1]: 38
1059 18:08:56.760965
1060 18:08:56.761017 Set Vref, RX VrefLevel [Byte0]: 39
1061 18:08:56.761069 [Byte1]: 39
1062 18:08:56.761121
1063 18:08:56.761173 Set Vref, RX VrefLevel [Byte0]: 40
1064 18:08:56.761225 [Byte1]: 40
1065 18:08:56.761277
1066 18:08:56.761328 Set Vref, RX VrefLevel [Byte0]: 41
1067 18:08:56.761380 [Byte1]: 41
1068 18:08:56.761432
1069 18:08:56.761484 Set Vref, RX VrefLevel [Byte0]: 42
1070 18:08:56.761536 [Byte1]: 42
1071 18:08:56.761588
1072 18:08:56.761640 Set Vref, RX VrefLevel [Byte0]: 43
1073 18:08:56.761692 [Byte1]: 43
1074 18:08:56.761745
1075 18:08:56.761796 Set Vref, RX VrefLevel [Byte0]: 44
1076 18:08:56.761848 [Byte1]: 44
1077 18:08:56.761900
1078 18:08:56.761951 Set Vref, RX VrefLevel [Byte0]: 45
1079 18:08:56.762003 [Byte1]: 45
1080 18:08:56.762055
1081 18:08:56.762107 Set Vref, RX VrefLevel [Byte0]: 46
1082 18:08:56.762159 [Byte1]: 46
1083 18:08:56.762211
1084 18:08:56.762263 Set Vref, RX VrefLevel [Byte0]: 47
1085 18:08:56.762319 [Byte1]: 47
1086 18:08:56.762371
1087 18:08:56.762422 Set Vref, RX VrefLevel [Byte0]: 48
1088 18:08:56.762474 [Byte1]: 48
1089 18:08:56.762526
1090 18:08:56.762577 Set Vref, RX VrefLevel [Byte0]: 49
1091 18:08:56.762629 [Byte1]: 49
1092 18:08:56.762681
1093 18:08:56.762732 Set Vref, RX VrefLevel [Byte0]: 50
1094 18:08:56.762784 [Byte1]: 50
1095 18:08:56.762836
1096 18:08:56.762891 Set Vref, RX VrefLevel [Byte0]: 51
1097 18:08:56.762943 [Byte1]: 51
1098 18:08:56.762995
1099 18:08:56.763046 Set Vref, RX VrefLevel [Byte0]: 52
1100 18:08:56.763098 [Byte1]: 52
1101 18:08:56.763151
1102 18:08:56.763202 Set Vref, RX VrefLevel [Byte0]: 53
1103 18:08:56.763254 [Byte1]: 53
1104 18:08:56.763305
1105 18:08:56.763357 Set Vref, RX VrefLevel [Byte0]: 54
1106 18:08:56.763409 [Byte1]: 54
1107 18:08:56.763461
1108 18:08:56.763512 Set Vref, RX VrefLevel [Byte0]: 55
1109 18:08:56.763564 [Byte1]: 55
1110 18:08:56.763616
1111 18:08:56.763668 Set Vref, RX VrefLevel [Byte0]: 56
1112 18:08:56.763720 [Byte1]: 56
1113 18:08:56.763772
1114 18:08:56.763823 Set Vref, RX VrefLevel [Byte0]: 57
1115 18:08:56.763875 [Byte1]: 57
1116 18:08:56.763927
1117 18:08:56.763977 Set Vref, RX VrefLevel [Byte0]: 58
1118 18:08:56.764029 [Byte1]: 58
1119 18:08:56.764081
1120 18:08:56.764132 Set Vref, RX VrefLevel [Byte0]: 59
1121 18:08:56.764184 [Byte1]: 59
1122 18:08:56.764235
1123 18:08:56.764287 Set Vref, RX VrefLevel [Byte0]: 60
1124 18:08:56.764338 [Byte1]: 60
1125 18:08:56.764390
1126 18:08:56.764441 Set Vref, RX VrefLevel [Byte0]: 61
1127 18:08:56.764493 [Byte1]: 61
1128 18:08:56.764544
1129 18:08:56.764636 Set Vref, RX VrefLevel [Byte0]: 62
1130 18:08:56.764687 [Byte1]: 62
1131 18:08:56.764739
1132 18:08:56.764791 Set Vref, RX VrefLevel [Byte0]: 63
1133 18:08:56.764843 [Byte1]: 63
1134 18:08:56.764895
1135 18:08:56.764946 Set Vref, RX VrefLevel [Byte0]: 64
1136 18:08:56.764998 [Byte1]: 64
1137 18:08:56.765051
1138 18:08:56.765102 Set Vref, RX VrefLevel [Byte0]: 65
1139 18:08:56.765154 [Byte1]: 65
1140 18:08:56.765205
1141 18:08:56.765257 Set Vref, RX VrefLevel [Byte0]: 66
1142 18:08:56.765308 [Byte1]: 66
1143 18:08:56.765360
1144 18:08:56.765412 Set Vref, RX VrefLevel [Byte0]: 67
1145 18:08:56.765464 [Byte1]: 67
1146 18:08:56.765516
1147 18:08:56.765566 Set Vref, RX VrefLevel [Byte0]: 68
1148 18:08:56.765618 [Byte1]: 68
1149 18:08:56.765670
1150 18:08:56.765722 Set Vref, RX VrefLevel [Byte0]: 69
1151 18:08:56.765774 [Byte1]: 69
1152 18:08:56.765825
1153 18:08:56.765877 Set Vref, RX VrefLevel [Byte0]: 70
1154 18:08:56.765929 [Byte1]: 70
1155 18:08:56.765981
1156 18:08:56.766032 Set Vref, RX VrefLevel [Byte0]: 71
1157 18:08:56.766084 [Byte1]: 71
1158 18:08:56.766136
1159 18:08:56.766187 Set Vref, RX VrefLevel [Byte0]: 72
1160 18:08:56.766429 [Byte1]: 72
1161 18:08:56.766489
1162 18:08:56.766542 Set Vref, RX VrefLevel [Byte0]: 73
1163 18:08:56.766595 [Byte1]: 73
1164 18:08:56.766649
1165 18:08:56.766748 Set Vref, RX VrefLevel [Byte0]: 74
1166 18:08:56.766815 [Byte1]: 74
1167 18:08:56.766867
1168 18:08:56.766919 Set Vref, RX VrefLevel [Byte0]: 75
1169 18:08:56.766987 [Byte1]: 75
1170 18:08:56.767054
1171 18:08:56.767124 Set Vref, RX VrefLevel [Byte0]: 76
1172 18:08:56.767191 [Byte1]: 76
1173 18:08:56.767243
1174 18:08:56.767296 Set Vref, RX VrefLevel [Byte0]: 77
1175 18:08:56.767348 [Byte1]: 77
1176 18:08:56.767415
1177 18:08:56.767481 Set Vref, RX VrefLevel [Byte0]: 78
1178 18:08:56.767579 [Byte1]: 78
1179 18:08:56.767659
1180 18:08:56.767713 Set Vref, RX VrefLevel [Byte0]: 79
1181 18:08:56.767766 [Byte1]: 79
1182 18:08:56.767819
1183 18:08:56.767886 Final RX Vref Byte 0 = 63 to rank0
1184 18:08:56.767967 Final RX Vref Byte 1 = 63 to rank0
1185 18:08:56.768019 Final RX Vref Byte 0 = 63 to rank1
1186 18:08:56.768072 Final RX Vref Byte 1 = 63 to rank1==
1187 18:08:56.768124 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 18:08:56.768191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 18:08:56.768257 ==
1190 18:08:56.768310 DQS Delay:
1191 18:08:56.768362 DQS0 = 0, DQS1 = 0
1192 18:08:56.768416 DQM Delay:
1193 18:08:56.768484 DQM0 = 93, DQM1 = 82
1194 18:08:56.768589 DQ Delay:
1195 18:08:56.768644 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1196 18:08:56.768698 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1197 18:08:56.768750 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1198 18:08:56.768802 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1199 18:08:56.768854
1200 18:08:56.768905
1201 18:08:56.768957 [DQSOSCAuto] RK0, (LSB)MR18= 0x3631, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
1202 18:08:56.769011 CH0 RK0: MR19=606, MR18=3631
1203 18:08:56.769094 CH0_RK0: MR19=0x606, MR18=0x3631, DQSOSC=396, MR23=63, INC=94, DEC=62
1204 18:08:56.769147
1205 18:08:56.769198 ----->DramcWriteLeveling(PI) begin...
1206 18:08:56.769252 ==
1207 18:08:56.769305 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 18:08:56.769374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 18:08:56.769441 ==
1210 18:08:56.769492 Write leveling (Byte 0): 34 => 34
1211 18:08:56.769545 Write leveling (Byte 1): 29 => 29
1212 18:08:56.769597 DramcWriteLeveling(PI) end<-----
1213 18:08:56.769649
1214 18:08:56.769729 ==
1215 18:08:56.769782 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 18:08:56.769834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 18:08:56.769886 ==
1218 18:08:56.769938 [Gating] SW mode calibration
1219 18:08:56.769991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 18:08:56.770047 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 18:08:56.770100 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 18:08:56.770153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 18:08:56.770206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 18:08:56.770258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 18:08:56.770339 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 18:08:56.770391 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:08:56.770443 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:08:56.770496 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 18:08:56.770548 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:08:56.770600 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 18:08:56.770653 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 18:08:56.770705 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 18:08:56.770757 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 18:08:56.770809 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 18:08:56.770861 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 18:08:56.770913 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 18:08:56.770992 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 18:08:56.771045 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 18:08:56.771097 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1240 18:08:56.771149 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 18:08:56.771201 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 18:08:56.771269 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 18:08:56.771335 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 18:08:56.771387 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 18:08:56.771439 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 18:08:56.771491 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 18:08:56.771543 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1248 18:08:56.771623 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 18:08:56.771675 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 18:08:56.771727 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 18:08:56.771779 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 18:08:56.771831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 18:08:56.771900 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 18:08:56.771967 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
1255 18:08:56.772018 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1256 18:08:56.772070 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 18:08:56.772123 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 18:08:56.772175 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 18:08:56.772258 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 18:08:56.772310 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 18:08:56.772363 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 18:08:56.772415 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
1263 18:08:56.772467 0 11 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
1264 18:08:56.772520 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 18:08:56.772613 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 18:08:56.772667 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 18:08:56.772920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 18:08:56.772978 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 18:08:56.773031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 18:08:56.773084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1271 18:08:56.773167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1272 18:08:56.773248 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 18:08:56.773301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 18:08:56.773353 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 18:08:56.773405 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 18:08:56.773458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 18:08:56.773540 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 18:08:56.773592 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 18:08:56.773644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 18:08:56.773696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 18:08:56.773748 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 18:08:56.773800 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 18:08:56.773881 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 18:08:56.773933 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 18:08:56.773984 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 18:08:56.774036 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 18:08:56.774088 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1288 18:08:56.774156 Total UI for P1: 0, mck2ui 16
1289 18:08:56.774223 best dqsien dly found for B0: ( 0, 14, 6)
1290 18:08:56.774275 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 18:08:56.774327 Total UI for P1: 0, mck2ui 16
1292 18:08:56.774380 best dqsien dly found for B1: ( 0, 14, 8)
1293 18:08:56.774432 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1294 18:08:56.774512 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1295 18:08:56.774564
1296 18:08:56.774615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1297 18:08:56.774668 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 18:08:56.774720 [Gating] SW calibration Done
1299 18:08:56.774772 ==
1300 18:08:56.774851 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 18:08:56.774904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 18:08:56.774957 ==
1303 18:08:56.775009 RX Vref Scan: 0
1304 18:08:56.775061
1305 18:08:56.775128 RX Vref 0 -> 0, step: 1
1306 18:08:56.775222
1307 18:08:56.775274 RX Delay -130 -> 252, step: 16
1308 18:08:56.775326 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1309 18:08:56.775378 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1310 18:08:56.775460 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1311 18:08:56.775512 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1312 18:08:56.775564 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1313 18:08:56.775615 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1314 18:08:56.775667 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1315 18:08:56.775748 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1316 18:08:56.775799 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1317 18:08:56.775851 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1318 18:08:56.775903 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1319 18:08:56.775955 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1320 18:08:56.776023 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1321 18:08:56.776089 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1322 18:08:56.776141 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1323 18:08:56.776194 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1324 18:08:56.776246 ==
1325 18:08:56.776314 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 18:08:56.776381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 18:08:56.776433 ==
1328 18:08:56.776486 DQS Delay:
1329 18:08:56.776537 DQS0 = 0, DQS1 = 0
1330 18:08:56.776629 DQM Delay:
1331 18:08:56.776682 DQM0 = 87, DQM1 = 79
1332 18:08:56.776734 DQ Delay:
1333 18:08:56.776786 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1334 18:08:56.776838 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1335 18:08:56.776890 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =77
1336 18:08:56.776942 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1337 18:08:56.776994
1338 18:08:56.777045
1339 18:08:56.777097 ==
1340 18:08:56.777149 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 18:08:56.777201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 18:08:56.777253 ==
1343 18:08:56.777305
1344 18:08:56.777357
1345 18:08:56.777408 TX Vref Scan disable
1346 18:08:56.777460 == TX Byte 0 ==
1347 18:08:56.777512 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1348 18:08:56.777565 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1349 18:08:56.777617 == TX Byte 1 ==
1350 18:08:56.777669 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1351 18:08:56.777721 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1352 18:08:56.777773 ==
1353 18:08:56.777825 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 18:08:56.777878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 18:08:56.777930 ==
1356 18:08:56.777982 TX Vref=22, minBit 1, minWin=27, winSum=446
1357 18:08:56.778034 TX Vref=24, minBit 8, minWin=27, winSum=450
1358 18:08:56.778087 TX Vref=26, minBit 10, minWin=27, winSum=453
1359 18:08:56.778139 TX Vref=28, minBit 8, minWin=27, winSum=454
1360 18:08:56.778191 TX Vref=30, minBit 14, minWin=27, winSum=456
1361 18:08:56.778243 TX Vref=32, minBit 8, minWin=28, winSum=459
1362 18:08:56.778294 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 32
1363 18:08:56.778344
1364 18:08:56.778394 Final TX Range 1 Vref 32
1365 18:08:56.778445
1366 18:08:56.778495 ==
1367 18:08:56.778544 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 18:08:56.778594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 18:08:56.778645 ==
1370 18:08:56.778695
1371 18:08:56.778745
1372 18:08:56.778794 TX Vref Scan disable
1373 18:08:56.778845 == TX Byte 0 ==
1374 18:08:56.778896 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1375 18:08:56.778946 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1376 18:08:56.778996 == TX Byte 1 ==
1377 18:08:56.779046 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1378 18:08:56.779097 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1379 18:08:56.779148
1380 18:08:56.779198 [DATLAT]
1381 18:08:56.779248 Freq=800, CH0 RK1
1382 18:08:56.779298
1383 18:08:56.779349 DATLAT Default: 0xa
1384 18:08:56.779399 0, 0xFFFF, sum = 0
1385 18:08:56.779451 1, 0xFFFF, sum = 0
1386 18:08:56.779503 2, 0xFFFF, sum = 0
1387 18:08:56.779554 3, 0xFFFF, sum = 0
1388 18:08:56.779605 4, 0xFFFF, sum = 0
1389 18:08:56.779657 5, 0xFFFF, sum = 0
1390 18:08:56.779708 6, 0xFFFF, sum = 0
1391 18:08:56.779759 7, 0xFFFF, sum = 0
1392 18:08:56.779810 8, 0xFFFF, sum = 0
1393 18:08:56.779861 9, 0x0, sum = 1
1394 18:08:56.780109 10, 0x0, sum = 2
1395 18:08:56.780170 11, 0x0, sum = 3
1396 18:08:56.780242 12, 0x0, sum = 4
1397 18:08:56.780365 best_step = 10
1398 18:08:56.780448
1399 18:08:56.780529 ==
1400 18:08:56.780598 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 18:08:56.780652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 18:08:56.780704 ==
1403 18:08:56.780756 RX Vref Scan: 0
1404 18:08:56.780807
1405 18:08:56.780860 RX Vref 0 -> 0, step: 1
1406 18:08:56.780912
1407 18:08:56.780962 RX Delay -95 -> 252, step: 8
1408 18:08:56.781014 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1409 18:08:56.781066 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 18:08:56.781118 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1411 18:08:56.781170 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1412 18:08:56.781221 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1413 18:08:56.781301 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1414 18:08:56.781364 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 18:08:56.781415 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 18:08:56.781464 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1417 18:08:56.781515 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1418 18:08:56.781565 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1419 18:08:56.781616 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1420 18:08:56.781665 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1421 18:08:56.781716 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1422 18:08:56.781766 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 18:08:56.781817 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1424 18:08:56.781866 ==
1425 18:08:56.781917 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 18:08:56.781968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 18:08:56.782018 ==
1428 18:08:56.782068 DQS Delay:
1429 18:08:56.782118 DQS0 = 0, DQS1 = 0
1430 18:08:56.782168 DQM Delay:
1431 18:08:56.782218 DQM0 = 90, DQM1 = 80
1432 18:08:56.782269 DQ Delay:
1433 18:08:56.782319 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1434 18:08:56.782369 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1435 18:08:56.782419 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1436 18:08:56.782470 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1437 18:08:56.782520
1438 18:08:56.782569
1439 18:08:56.782619 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1440 18:08:56.782670 CH0 RK1: MR19=606, MR18=3E18
1441 18:08:56.782721 CH0_RK1: MR19=0x606, MR18=0x3E18, DQSOSC=394, MR23=63, INC=95, DEC=63
1442 18:08:56.782772 [RxdqsGatingPostProcess] freq 800
1443 18:08:56.782822 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 18:08:56.782873 Pre-setting of DQS Precalculation
1445 18:08:56.782924 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 18:08:56.782974 ==
1447 18:08:56.783025 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 18:08:56.783075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 18:08:56.783126 ==
1450 18:08:56.783176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 18:08:56.783227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 18:08:56.783278 [CA 0] Center 36 (6~67) winsize 62
1453 18:08:56.783329 [CA 1] Center 36 (6~67) winsize 62
1454 18:08:56.783381 [CA 2] Center 34 (4~65) winsize 62
1455 18:08:56.783450 [CA 3] Center 34 (3~65) winsize 63
1456 18:08:56.783522 [CA 4] Center 34 (4~65) winsize 62
1457 18:08:56.783578 [CA 5] Center 34 (3~65) winsize 63
1458 18:08:56.783629
1459 18:08:56.783682 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1460 18:08:56.783734
1461 18:08:56.783784 [CATrainingPosCal] consider 1 rank data
1462 18:08:56.783837 u2DelayCellTimex100 = 270/100 ps
1463 18:08:56.783888 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 18:08:56.783939 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 18:08:56.783990 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 18:08:56.784042 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1467 18:08:56.784092 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1468 18:08:56.784143 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1469 18:08:56.784193
1470 18:08:56.784243 CA PerBit enable=1, Macro0, CA PI delay=34
1471 18:08:56.784293
1472 18:08:56.784343 [CBTSetCACLKResult] CA Dly = 34
1473 18:08:56.784393 CS Dly: 5 (0~36)
1474 18:08:56.784444 ==
1475 18:08:56.784494 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 18:08:56.784544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 18:08:56.784638 ==
1478 18:08:56.784689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 18:08:56.784739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 18:08:56.784790 [CA 0] Center 36 (6~67) winsize 62
1481 18:08:56.784840 [CA 1] Center 37 (6~68) winsize 63
1482 18:08:56.784892 [CA 2] Center 35 (5~66) winsize 62
1483 18:08:56.784942 [CA 3] Center 34 (4~65) winsize 62
1484 18:08:56.784992 [CA 4] Center 34 (4~65) winsize 62
1485 18:08:56.785043 [CA 5] Center 34 (4~65) winsize 62
1486 18:08:56.785093
1487 18:08:56.785143 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1488 18:08:56.785193
1489 18:08:56.785243 [CATrainingPosCal] consider 2 rank data
1490 18:08:56.785293 u2DelayCellTimex100 = 270/100 ps
1491 18:08:56.785344 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 18:08:56.785395 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 18:08:56.785445 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1494 18:08:56.785496 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 18:08:56.785546 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 18:08:56.785596 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 18:08:56.785646
1498 18:08:56.785696 CA PerBit enable=1, Macro0, CA PI delay=34
1499 18:08:56.785746
1500 18:08:56.785796 [CBTSetCACLKResult] CA Dly = 34
1501 18:08:56.785846 CS Dly: 6 (0~38)
1502 18:08:56.785896
1503 18:08:56.785946 ----->DramcWriteLeveling(PI) begin...
1504 18:08:56.785998 ==
1505 18:08:56.786048 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 18:08:56.786099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 18:08:56.786149 ==
1508 18:08:56.786200 Write leveling (Byte 0): 27 => 27
1509 18:08:56.786251 Write leveling (Byte 1): 29 => 29
1510 18:08:56.786301 DramcWriteLeveling(PI) end<-----
1511 18:08:56.786351
1512 18:08:56.786401 ==
1513 18:08:56.786451 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 18:08:56.786502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 18:08:56.786553 ==
1516 18:08:56.786603 [Gating] SW mode calibration
1517 18:08:56.786653 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 18:08:56.786704 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 18:08:56.786754 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1520 18:08:56.787015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1521 18:08:56.787074 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 18:08:56.787127 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 18:08:56.787179 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 18:08:56.787230 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 18:08:56.787281 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 18:08:56.787332 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:08:56.787383 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:08:56.787433 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 18:08:56.787484 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 18:08:56.787534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 18:08:56.787585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 18:08:56.787635 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 18:08:56.787686 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 18:08:56.787736 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 18:08:56.787787 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1536 18:08:56.787837 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 18:08:56.787887 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1538 18:08:56.787938 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 18:08:56.787989 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 18:08:56.788039 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 18:08:56.788090 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 18:08:56.788140 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 18:08:56.788190 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 18:08:56.788241 0 9 4 | B1->B0 | 2727 2929 | 1 1 | (1 1) (1 1)
1545 18:08:56.788291 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 18:08:56.788342 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 18:08:56.788392 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 18:08:56.788442 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 18:08:56.788493 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 18:08:56.788543 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 18:08:56.788637 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1552 18:08:56.788688 0 10 4 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 0)
1553 18:08:56.788738 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 18:08:56.788789 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 18:08:56.788840 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 18:08:56.788891 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 18:08:56.788941 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 18:08:56.788992 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 18:08:56.789042 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1560 18:08:56.789092 0 11 4 | B1->B0 | 3535 3f3f | 0 0 | (1 1) (0 0)
1561 18:08:56.789142 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 18:08:56.789193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 18:08:56.789243 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 18:08:56.789294 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 18:08:56.789345 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 18:08:56.789395 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 18:08:56.789445 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1568 18:08:56.789495 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 18:08:56.789545 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1570 18:08:56.789596 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 18:08:56.789646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 18:08:56.789696 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 18:08:56.789746 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 18:08:56.789797 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 18:08:56.789862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 18:08:56.789917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 18:08:56.789967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 18:08:56.790018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 18:08:56.790069 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 18:08:56.790120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 18:08:56.790170 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 18:08:56.790220 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 18:08:56.790271 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 18:08:56.790321 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 18:08:56.790372 Total UI for P1: 0, mck2ui 16
1586 18:08:56.790422 best dqsien dly found for B0: ( 0, 14, 2)
1587 18:08:56.790473 Total UI for P1: 0, mck2ui 16
1588 18:08:56.790523 best dqsien dly found for B1: ( 0, 14, 2)
1589 18:08:56.790574 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1590 18:08:56.790625 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1591 18:08:56.790675
1592 18:08:56.790724 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1593 18:08:56.790775 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 18:08:56.790825 [Gating] SW calibration Done
1595 18:08:56.790876 ==
1596 18:08:56.790927 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 18:08:56.790977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 18:08:56.791028 ==
1599 18:08:56.791078 RX Vref Scan: 0
1600 18:08:56.791129
1601 18:08:56.791178 RX Vref 0 -> 0, step: 1
1602 18:08:56.791229
1603 18:08:56.791279 RX Delay -130 -> 252, step: 16
1604 18:08:56.791330 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1605 18:08:56.791380 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1606 18:08:56.791431 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1607 18:08:56.791482 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1608 18:08:56.791532 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1609 18:08:56.791774 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1610 18:08:56.791833 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1611 18:08:56.791884 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1612 18:08:56.791935 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1613 18:08:56.791986 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1614 18:08:56.792037 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1615 18:08:56.792088 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1616 18:08:56.792138 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1617 18:08:56.792189 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1618 18:08:56.792244 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1619 18:08:56.792294 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1620 18:08:56.792345 ==
1621 18:08:56.792395 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 18:08:56.792446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 18:08:56.792496 ==
1624 18:08:56.792572 DQS Delay:
1625 18:08:56.792668 DQS0 = 0, DQS1 = 0
1626 18:08:56.792747 DQM Delay:
1627 18:08:56.792827 DQM0 = 86, DQM1 = 80
1628 18:08:56.792907 DQ Delay:
1629 18:08:56.792986 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1630 18:08:56.793061 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1631 18:08:56.793113 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1632 18:08:56.793165 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1633 18:08:56.793216
1634 18:08:56.793266
1635 18:08:56.793316 ==
1636 18:08:56.793366 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 18:08:56.793416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 18:08:56.793467 ==
1639 18:08:56.793518
1640 18:08:56.793567
1641 18:08:56.793617 TX Vref Scan disable
1642 18:08:56.793687 == TX Byte 0 ==
1643 18:08:56.793740 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1644 18:08:56.793791 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1645 18:08:56.793842 == TX Byte 1 ==
1646 18:08:56.793892 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1647 18:08:56.793943 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1648 18:08:56.793994 ==
1649 18:08:56.794044 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 18:08:56.794095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 18:08:56.794146 ==
1652 18:08:56.794197 TX Vref=22, minBit 10, minWin=27, winSum=449
1653 18:08:56.794247 TX Vref=24, minBit 8, minWin=27, winSum=452
1654 18:08:56.794299 TX Vref=26, minBit 15, minWin=27, winSum=457
1655 18:08:56.794349 TX Vref=28, minBit 8, minWin=28, winSum=459
1656 18:08:56.794405 TX Vref=30, minBit 15, minWin=27, winSum=458
1657 18:08:56.794456 TX Vref=32, minBit 8, minWin=28, winSum=460
1658 18:08:56.794506 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1659 18:08:56.794557
1660 18:08:56.794607 Final TX Range 1 Vref 32
1661 18:08:56.794658
1662 18:08:56.794708 ==
1663 18:08:56.794758 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 18:08:56.794808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 18:08:56.794859 ==
1666 18:08:56.794909
1667 18:08:56.794959
1668 18:08:56.795009 TX Vref Scan disable
1669 18:08:56.795059 == TX Byte 0 ==
1670 18:08:56.795110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1671 18:08:56.795161 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1672 18:08:56.795211 == TX Byte 1 ==
1673 18:08:56.795262 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1674 18:08:56.795312 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1675 18:08:56.795365
1676 18:08:56.795414 [DATLAT]
1677 18:08:56.795465 Freq=800, CH1 RK0
1678 18:08:56.795516
1679 18:08:56.795578 DATLAT Default: 0xa
1680 18:08:56.795629 0, 0xFFFF, sum = 0
1681 18:08:56.795680 1, 0xFFFF, sum = 0
1682 18:08:56.795740 2, 0xFFFF, sum = 0
1683 18:08:56.795795 3, 0xFFFF, sum = 0
1684 18:08:56.795846 4, 0xFFFF, sum = 0
1685 18:08:56.795896 5, 0xFFFF, sum = 0
1686 18:08:56.795960 6, 0xFFFF, sum = 0
1687 18:08:56.796011 7, 0xFFFF, sum = 0
1688 18:08:56.796062 8, 0xFFFF, sum = 0
1689 18:08:56.796122 9, 0x0, sum = 1
1690 18:08:56.796174 10, 0x0, sum = 2
1691 18:08:56.796226 11, 0x0, sum = 3
1692 18:08:56.796277 12, 0x0, sum = 4
1693 18:08:56.796349 best_step = 10
1694 18:08:56.796432
1695 18:08:56.796554 ==
1696 18:08:56.796623 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 18:08:56.796679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 18:08:56.796730 ==
1699 18:08:56.796781 RX Vref Scan: 1
1700 18:08:56.796832
1701 18:08:56.796884 Set Vref Range= 32 -> 127
1702 18:08:56.796934
1703 18:08:56.796985 RX Vref 32 -> 127, step: 1
1704 18:08:56.797035
1705 18:08:56.797085 RX Delay -95 -> 252, step: 8
1706 18:08:56.797136
1707 18:08:56.797186 Set Vref, RX VrefLevel [Byte0]: 32
1708 18:08:56.797237 [Byte1]: 32
1709 18:08:56.797288
1710 18:08:56.797338 Set Vref, RX VrefLevel [Byte0]: 33
1711 18:08:56.797388 [Byte1]: 33
1712 18:08:56.797438
1713 18:08:56.797488 Set Vref, RX VrefLevel [Byte0]: 34
1714 18:08:56.797538 [Byte1]: 34
1715 18:08:56.797589
1716 18:08:56.797639 Set Vref, RX VrefLevel [Byte0]: 35
1717 18:08:56.797690 [Byte1]: 35
1718 18:08:56.797740
1719 18:08:56.797790 Set Vref, RX VrefLevel [Byte0]: 36
1720 18:08:56.797840 [Byte1]: 36
1721 18:08:56.797890
1722 18:08:56.797940 Set Vref, RX VrefLevel [Byte0]: 37
1723 18:08:56.797990 [Byte1]: 37
1724 18:08:56.798041
1725 18:08:56.798091 Set Vref, RX VrefLevel [Byte0]: 38
1726 18:08:56.798141 [Byte1]: 38
1727 18:08:56.798191
1728 18:08:56.798241 Set Vref, RX VrefLevel [Byte0]: 39
1729 18:08:56.798291 [Byte1]: 39
1730 18:08:56.798350
1731 18:08:56.798402 Set Vref, RX VrefLevel [Byte0]: 40
1732 18:08:56.798461 [Byte1]: 40
1733 18:08:56.798552
1734 18:08:56.798602 Set Vref, RX VrefLevel [Byte0]: 41
1735 18:08:56.798652 [Byte1]: 41
1736 18:08:56.798703
1737 18:08:56.798753 Set Vref, RX VrefLevel [Byte0]: 42
1738 18:08:56.798804 [Byte1]: 42
1739 18:08:56.798854
1740 18:08:56.798904 Set Vref, RX VrefLevel [Byte0]: 43
1741 18:08:56.798955 [Byte1]: 43
1742 18:08:56.799005
1743 18:08:56.799056 Set Vref, RX VrefLevel [Byte0]: 44
1744 18:08:56.799105 [Byte1]: 44
1745 18:08:56.799155
1746 18:08:56.799205 Set Vref, RX VrefLevel [Byte0]: 45
1747 18:08:56.799255 [Byte1]: 45
1748 18:08:56.799305
1749 18:08:56.799371 Set Vref, RX VrefLevel [Byte0]: 46
1750 18:08:56.799424 [Byte1]: 46
1751 18:08:56.799474
1752 18:08:56.799524 Set Vref, RX VrefLevel [Byte0]: 47
1753 18:08:56.799575 [Byte1]: 47
1754 18:08:56.799625
1755 18:08:56.799691 Set Vref, RX VrefLevel [Byte0]: 48
1756 18:08:56.799754 [Byte1]: 48
1757 18:08:56.799805
1758 18:08:56.799856 Set Vref, RX VrefLevel [Byte0]: 49
1759 18:08:56.799906 [Byte1]: 49
1760 18:08:56.799957
1761 18:08:56.800006 Set Vref, RX VrefLevel [Byte0]: 50
1762 18:08:56.800077 [Byte1]: 50
1763 18:08:56.800130
1764 18:08:56.800180 Set Vref, RX VrefLevel [Byte0]: 51
1765 18:08:56.800231 [Byte1]: 51
1766 18:08:56.800281
1767 18:08:56.800332 Set Vref, RX VrefLevel [Byte0]: 52
1768 18:08:56.800382 [Byte1]: 52
1769 18:08:56.800432
1770 18:08:56.800677 Set Vref, RX VrefLevel [Byte0]: 53
1771 18:08:56.800734 [Byte1]: 53
1772 18:08:56.800786
1773 18:08:56.800837 Set Vref, RX VrefLevel [Byte0]: 54
1774 18:08:56.800888 [Byte1]: 54
1775 18:08:56.800939
1776 18:08:56.800990 Set Vref, RX VrefLevel [Byte0]: 55
1777 18:08:56.801040 [Byte1]: 55
1778 18:08:56.801090
1779 18:08:56.801141 Set Vref, RX VrefLevel [Byte0]: 56
1780 18:08:56.801191 [Byte1]: 56
1781 18:08:56.801242
1782 18:08:56.801291 Set Vref, RX VrefLevel [Byte0]: 57
1783 18:08:56.801342 [Byte1]: 57
1784 18:08:56.801392
1785 18:08:56.801442 Set Vref, RX VrefLevel [Byte0]: 58
1786 18:08:56.801493 [Byte1]: 58
1787 18:08:56.801543
1788 18:08:56.801592 Set Vref, RX VrefLevel [Byte0]: 59
1789 18:08:56.801643 [Byte1]: 59
1790 18:08:56.801693
1791 18:08:56.801742 Set Vref, RX VrefLevel [Byte0]: 60
1792 18:08:56.801792 [Byte1]: 60
1793 18:08:56.801842
1794 18:08:56.801892 Set Vref, RX VrefLevel [Byte0]: 61
1795 18:08:56.801942 [Byte1]: 61
1796 18:08:56.801992
1797 18:08:56.802042 Set Vref, RX VrefLevel [Byte0]: 62
1798 18:08:56.802092 [Byte1]: 62
1799 18:08:56.802143
1800 18:08:56.802193 Set Vref, RX VrefLevel [Byte0]: 63
1801 18:08:56.802243 [Byte1]: 63
1802 18:08:56.802293
1803 18:08:56.802343 Set Vref, RX VrefLevel [Byte0]: 64
1804 18:08:56.802393 [Byte1]: 64
1805 18:08:56.802443
1806 18:08:56.802492 Set Vref, RX VrefLevel [Byte0]: 65
1807 18:08:56.802542 [Byte1]: 65
1808 18:08:56.802592
1809 18:08:56.802642 Set Vref, RX VrefLevel [Byte0]: 66
1810 18:08:56.802692 [Byte1]: 66
1811 18:08:56.802742
1812 18:08:56.802791 Set Vref, RX VrefLevel [Byte0]: 67
1813 18:08:56.802841 [Byte1]: 67
1814 18:08:56.802891
1815 18:08:56.802941 Set Vref, RX VrefLevel [Byte0]: 68
1816 18:08:56.802991 [Byte1]: 68
1817 18:08:56.803041
1818 18:08:56.803090 Set Vref, RX VrefLevel [Byte0]: 69
1819 18:08:56.803140 [Byte1]: 69
1820 18:08:56.803224
1821 18:08:56.803287 Set Vref, RX VrefLevel [Byte0]: 70
1822 18:08:56.803339 [Byte1]: 70
1823 18:08:56.803390
1824 18:08:56.803440 Set Vref, RX VrefLevel [Byte0]: 71
1825 18:08:56.803490 [Byte1]: 71
1826 18:08:56.803540
1827 18:08:56.803590 Set Vref, RX VrefLevel [Byte0]: 72
1828 18:08:56.803640 [Byte1]: 72
1829 18:08:56.803690
1830 18:08:56.803740 Set Vref, RX VrefLevel [Byte0]: 73
1831 18:08:56.803790 [Byte1]: 73
1832 18:08:56.803840
1833 18:08:56.803890 Set Vref, RX VrefLevel [Byte0]: 74
1834 18:08:56.803941 [Byte1]: 74
1835 18:08:56.803990
1836 18:08:56.804040 Set Vref, RX VrefLevel [Byte0]: 75
1837 18:08:56.804090 [Byte1]: 75
1838 18:08:56.804141
1839 18:08:56.804191 Set Vref, RX VrefLevel [Byte0]: 76
1840 18:08:56.804241 [Byte1]: 76
1841 18:08:56.804292
1842 18:08:56.804342 Final RX Vref Byte 0 = 53 to rank0
1843 18:08:56.804394 Final RX Vref Byte 1 = 62 to rank0
1844 18:08:56.804444 Final RX Vref Byte 0 = 53 to rank1
1845 18:08:56.804511 Final RX Vref Byte 1 = 62 to rank1==
1846 18:08:56.804588 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 18:08:56.804640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 18:08:56.804692 ==
1849 18:08:56.804742 DQS Delay:
1850 18:08:56.804792 DQS0 = 0, DQS1 = 0
1851 18:08:56.804843 DQM Delay:
1852 18:08:56.804892 DQM0 = 91, DQM1 = 82
1853 18:08:56.804942 DQ Delay:
1854 18:08:56.804992 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1855 18:08:56.805043 DQ4 =92, DQ5 =96, DQ6 =100, DQ7 =88
1856 18:08:56.805093 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1857 18:08:56.805143 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1858 18:08:56.805193
1859 18:08:56.805243
1860 18:08:56.805293 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1861 18:08:56.805344 CH1 RK0: MR19=606, MR18=2F4C
1862 18:08:56.805395 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1863 18:08:56.805446
1864 18:08:56.805496 ----->DramcWriteLeveling(PI) begin...
1865 18:08:56.805548 ==
1866 18:08:56.805598 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 18:08:56.805649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 18:08:56.805700 ==
1869 18:08:56.805750 Write leveling (Byte 0): 30 => 30
1870 18:08:56.805801 Write leveling (Byte 1): 28 => 28
1871 18:08:56.805851 DramcWriteLeveling(PI) end<-----
1872 18:08:56.805900
1873 18:08:56.805951 ==
1874 18:08:56.806001 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 18:08:56.806051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 18:08:56.806101 ==
1877 18:08:56.806151 [Gating] SW mode calibration
1878 18:08:56.806201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 18:08:56.806252 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 18:08:56.806303 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1881 18:08:56.806355 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1882 18:08:56.806405 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 18:08:56.806456 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 18:08:56.806507 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 18:08:56.806557 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 18:08:56.806607 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 18:08:56.806658 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 18:08:56.806708 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 18:08:56.806758 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 18:08:56.806809 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 18:08:56.806860 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 18:08:56.806910 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 18:08:56.806961 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 18:08:56.807032 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 18:08:56.807085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:08:56.807136 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 18:08:56.807186 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1898 18:08:56.807237 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 18:08:56.807287 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 18:08:56.807337 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 18:08:56.807576 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 18:08:56.807646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 18:08:56.807700 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 18:08:56.807751 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 18:08:56.807802 0 9 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1906 18:08:56.807862 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 18:08:56.807913 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 18:08:56.807963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 18:08:56.808025 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 18:08:56.808077 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 18:08:56.808128 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 18:08:56.808187 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1913 18:08:56.808240 0 10 4 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 0)
1914 18:08:56.808291 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 18:08:56.808342 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 18:08:56.808396 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 18:08:56.808447 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 18:08:56.808514 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 18:08:56.808598 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 18:08:56.808651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 18:08:56.808701 0 11 4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (1 1)
1922 18:08:56.808754 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1923 18:08:56.808804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 18:08:56.808854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 18:08:56.808904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 18:08:56.808958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 18:08:56.809008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 18:08:56.809057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 18:08:56.809109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1930 18:08:56.809160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 18:08:56.809210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 18:08:56.809260 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 18:08:56.809311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 18:08:56.809361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 18:08:56.809411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 18:08:56.809461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 18:08:56.809511 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 18:08:56.809561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 18:08:56.809612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 18:08:56.809662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 18:08:56.809713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 18:08:56.809763 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 18:08:56.809814 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 18:08:56.809864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 18:08:56.809927 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 18:08:56.809982 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 18:08:56.810034 Total UI for P1: 0, mck2ui 16
1948 18:08:56.810086 best dqsien dly found for B0: ( 0, 14, 4)
1949 18:08:56.810136 Total UI for P1: 0, mck2ui 16
1950 18:08:56.810188 best dqsien dly found for B1: ( 0, 14, 4)
1951 18:08:56.810238 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1952 18:08:56.810289 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 18:08:56.810339
1954 18:08:56.810389 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 18:08:56.810440 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 18:08:56.810490 [Gating] SW calibration Done
1957 18:08:56.810540 ==
1958 18:08:56.810591 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 18:08:56.810641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 18:08:56.810691 ==
1961 18:08:56.810741 RX Vref Scan: 0
1962 18:08:56.810791
1963 18:08:56.810841 RX Vref 0 -> 0, step: 1
1964 18:08:56.810892
1965 18:08:56.810942 RX Delay -130 -> 252, step: 16
1966 18:08:56.810993 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1967 18:08:56.811043 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1968 18:08:56.811093 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1969 18:08:56.811143 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1970 18:08:56.811193 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1971 18:08:56.811243 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1972 18:08:56.811294 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1973 18:08:56.811344 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1974 18:08:56.811395 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1975 18:08:56.811445 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1976 18:08:56.811495 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1977 18:08:56.811546 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1978 18:08:56.811596 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1979 18:08:56.811647 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1980 18:08:56.811697 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1981 18:08:56.811747 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1982 18:08:56.811797 ==
1983 18:08:56.811846 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 18:08:56.811897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 18:08:57.078747 ==
1986 18:08:57.078910 DQS Delay:
1987 18:08:57.078976 DQS0 = 0, DQS1 = 0
1988 18:08:57.079035 DQM Delay:
1989 18:08:57.079092 DQM0 = 90, DQM1 = 84
1990 18:08:57.079147 DQ Delay:
1991 18:08:57.079200 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1992 18:08:57.079253 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1993 18:08:57.079305 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1994 18:08:57.079357 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1995 18:08:57.079409
1996 18:08:57.079460
1997 18:08:57.079511 ==
1998 18:08:57.079562 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 18:08:57.079614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 18:08:57.079666 ==
2001 18:08:57.079717
2002 18:08:57.079767
2003 18:08:57.079817 TX Vref Scan disable
2004 18:08:57.079868 == TX Byte 0 ==
2005 18:08:57.079918 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2006 18:08:57.080211 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2007 18:08:57.080326 == TX Byte 1 ==
2008 18:08:57.080408 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2009 18:08:57.080461 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2010 18:08:57.080533 ==
2011 18:08:57.080623 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 18:08:57.080707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 18:08:57.080819 ==
2014 18:08:57.080889 TX Vref=22, minBit 5, minWin=27, winSum=446
2015 18:08:57.080971 TX Vref=24, minBit 13, minWin=27, winSum=450
2016 18:08:57.081024 TX Vref=26, minBit 0, minWin=28, winSum=458
2017 18:08:57.081077 TX Vref=28, minBit 6, minWin=28, winSum=459
2018 18:08:57.081129 TX Vref=30, minBit 8, minWin=28, winSum=459
2019 18:08:57.081182 TX Vref=32, minBit 8, minWin=28, winSum=461
2020 18:08:57.081240 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 32
2021 18:08:57.081306
2022 18:08:57.081377 Final TX Range 1 Vref 32
2023 18:08:57.081432
2024 18:08:57.081486 ==
2025 18:08:57.081538 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 18:08:57.081618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 18:08:57.081717 ==
2028 18:08:57.081772
2029 18:08:57.081822
2030 18:08:57.081873 TX Vref Scan disable
2031 18:08:57.081924 == TX Byte 0 ==
2032 18:08:57.081975 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2033 18:08:57.082043 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2034 18:08:57.082097 == TX Byte 1 ==
2035 18:08:57.082147 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2036 18:08:57.082213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2037 18:08:57.082265
2038 18:08:57.082346 [DATLAT]
2039 18:08:57.082396 Freq=800, CH1 RK1
2040 18:08:57.082448
2041 18:08:57.082509 DATLAT Default: 0xa
2042 18:08:57.082561 0, 0xFFFF, sum = 0
2043 18:08:57.082615 1, 0xFFFF, sum = 0
2044 18:08:57.082667 2, 0xFFFF, sum = 0
2045 18:08:57.082718 3, 0xFFFF, sum = 0
2046 18:08:57.082769 4, 0xFFFF, sum = 0
2047 18:08:57.082821 5, 0xFFFF, sum = 0
2048 18:08:57.082895 6, 0xFFFF, sum = 0
2049 18:08:57.082960 7, 0xFFFF, sum = 0
2050 18:08:57.083033 8, 0xFFFF, sum = 0
2051 18:08:57.083086 9, 0x0, sum = 1
2052 18:08:57.083169 10, 0x0, sum = 2
2053 18:08:57.083221 11, 0x0, sum = 3
2054 18:08:57.083272 12, 0x0, sum = 4
2055 18:08:57.083323 best_step = 10
2056 18:08:57.083374
2057 18:08:57.083424 ==
2058 18:08:57.083483 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 18:08:57.083546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 18:08:57.083598 ==
2061 18:08:57.083649 RX Vref Scan: 0
2062 18:08:57.083700
2063 18:08:57.083749 RX Vref 0 -> 0, step: 1
2064 18:08:57.083800
2065 18:08:57.083850 RX Delay -95 -> 252, step: 8
2066 18:08:57.083901 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2067 18:08:57.083952 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2068 18:08:57.084003 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2069 18:08:57.084053 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2070 18:08:57.084103 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2071 18:08:57.084153 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2072 18:08:57.084206 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2073 18:08:57.084259 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2074 18:08:57.084310 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2075 18:08:57.084361 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2076 18:08:57.084414 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2077 18:08:57.084481 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2078 18:08:57.084532 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2079 18:08:57.084613 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2080 18:08:57.084664 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2081 18:08:57.084720 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2082 18:08:57.084775 ==
2083 18:08:57.084828 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 18:08:57.084880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 18:08:57.084952 ==
2086 18:08:57.085008 DQS Delay:
2087 18:08:57.085064 DQS0 = 0, DQS1 = 0
2088 18:08:57.085117 DQM Delay:
2089 18:08:57.085168 DQM0 = 91, DQM1 = 83
2090 18:08:57.085221 DQ Delay:
2091 18:08:57.085273 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2092 18:08:57.085326 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2093 18:08:57.085378 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2094 18:08:57.085430 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2095 18:08:57.085482
2096 18:08:57.085534
2097 18:08:57.085585 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2098 18:08:57.085638 CH1 RK1: MR19=606, MR18=3A0F
2099 18:08:57.085691 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2100 18:08:57.085744 [RxdqsGatingPostProcess] freq 800
2101 18:08:57.085796 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 18:08:57.085848 Pre-setting of DQS Precalculation
2103 18:08:57.085903 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 18:08:57.085956 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 18:08:57.086010 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 18:08:57.086063
2107 18:08:57.086115
2108 18:08:57.086168 [Calibration Summary] 1600 Mbps
2109 18:08:57.086220 CH 0, Rank 0
2110 18:08:57.086272 SW Impedance : PASS
2111 18:08:57.086324 DUTY Scan : NO K
2112 18:08:57.086376 ZQ Calibration : PASS
2113 18:08:57.086443 Jitter Meter : NO K
2114 18:08:57.086503 CBT Training : PASS
2115 18:08:57.086558 Write leveling : PASS
2116 18:08:57.086631 RX DQS gating : PASS
2117 18:08:57.086687 RX DQ/DQS(RDDQC) : PASS
2118 18:08:57.086740 TX DQ/DQS : PASS
2119 18:08:57.086792 RX DATLAT : PASS
2120 18:08:57.086845 RX DQ/DQS(Engine): PASS
2121 18:08:57.086897 TX OE : NO K
2122 18:08:57.086949 All Pass.
2123 18:08:57.087007
2124 18:08:57.087072 CH 0, Rank 1
2125 18:08:57.087127 SW Impedance : PASS
2126 18:08:57.087179 DUTY Scan : NO K
2127 18:08:57.087231 ZQ Calibration : PASS
2128 18:08:57.087283 Jitter Meter : NO K
2129 18:08:57.087364 CBT Training : PASS
2130 18:08:57.087416 Write leveling : PASS
2131 18:08:57.087468 RX DQS gating : PASS
2132 18:08:57.087520 RX DQ/DQS(RDDQC) : PASS
2133 18:08:57.087572 TX DQ/DQS : PASS
2134 18:08:57.087624 RX DATLAT : PASS
2135 18:08:57.087676 RX DQ/DQS(Engine): PASS
2136 18:08:57.087727 TX OE : NO K
2137 18:08:57.087780 All Pass.
2138 18:08:57.087845
2139 18:08:57.087912 CH 1, Rank 0
2140 18:08:57.087964 SW Impedance : PASS
2141 18:08:57.088016 DUTY Scan : NO K
2142 18:08:57.088068 ZQ Calibration : PASS
2143 18:08:57.088148 Jitter Meter : NO K
2144 18:08:57.088244 CBT Training : PASS
2145 18:08:57.088318 Write leveling : PASS
2146 18:08:57.088409 RX DQS gating : PASS
2147 18:08:57.088502 RX DQ/DQS(RDDQC) : PASS
2148 18:08:57.088603 TX DQ/DQS : PASS
2149 18:08:57.088676 RX DATLAT : PASS
2150 18:08:57.088775 RX DQ/DQS(Engine): PASS
2151 18:08:57.088864 TX OE : NO K
2152 18:08:57.089161 All Pass.
2153 18:08:57.089252
2154 18:08:57.089372 CH 1, Rank 1
2155 18:08:57.089463 SW Impedance : PASS
2156 18:08:57.089583 DUTY Scan : NO K
2157 18:08:57.089674 ZQ Calibration : PASS
2158 18:08:57.089768 Jitter Meter : NO K
2159 18:08:57.089886 CBT Training : PASS
2160 18:08:57.089976 Write leveling : PASS
2161 18:08:57.090066 RX DQS gating : PASS
2162 18:08:57.090158 RX DQ/DQS(RDDQC) : PASS
2163 18:08:57.090249 TX DQ/DQS : PASS
2164 18:08:57.090355 RX DATLAT : PASS
2165 18:08:57.090460 RX DQ/DQS(Engine): PASS
2166 18:08:57.090554 TX OE : NO K
2167 18:08:57.090680 All Pass.
2168 18:08:57.090770
2169 18:08:57.090860 DramC Write-DBI off
2170 18:08:57.090949 PER_BANK_REFRESH: Hybrid Mode
2171 18:08:57.091038 TX_TRACKING: ON
2172 18:08:57.091128 [GetDramInforAfterCalByMRR] Vendor 6.
2173 18:08:57.091218 [GetDramInforAfterCalByMRR] Revision 606.
2174 18:08:57.091326 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 18:08:57.091473 MR0 0x3b3b
2176 18:08:57.091596 MR8 0x5151
2177 18:08:57.091717 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 18:08:57.091800
2179 18:08:57.091881 MR0 0x3b3b
2180 18:08:57.092037 MR8 0x5151
2181 18:08:57.092120 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 18:08:57.092201
2183 18:08:57.092319 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 18:08:57.092419 [FAST_K] Save calibration result to emmc
2185 18:08:57.092502 [FAST_K] Save calibration result to emmc
2186 18:08:57.092609 dram_init: config_dvfs: 1
2187 18:08:57.092700 dramc_set_vcore_voltage set vcore to 662500
2188 18:08:57.092790 Read voltage for 1200, 2
2189 18:08:57.092880 Vio18 = 0
2190 18:08:57.092970 Vcore = 662500
2191 18:08:57.093059 Vdram = 0
2192 18:08:57.093148 Vddq = 0
2193 18:08:57.093237 Vmddr = 0
2194 18:08:57.093326 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 18:08:57.093418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 18:08:57.093507 MEM_TYPE=3, freq_sel=15
2197 18:08:57.093590 sv_algorithm_assistance_LP4_1600
2198 18:08:57.093675 ============ PULL DRAM RESETB DOWN ============
2199 18:08:57.093759 ========== PULL DRAM RESETB DOWN end =========
2200 18:08:57.093844 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 18:08:57.093931 ===================================
2202 18:08:57.094015 LPDDR4 DRAM CONFIGURATION
2203 18:08:57.094100 ===================================
2204 18:08:57.094182 EX_ROW_EN[0] = 0x0
2205 18:08:57.094264 EX_ROW_EN[1] = 0x0
2206 18:08:57.094345 LP4Y_EN = 0x0
2207 18:08:57.094426 WORK_FSP = 0x0
2208 18:08:57.094506 WL = 0x4
2209 18:08:57.094587 RL = 0x4
2210 18:08:57.094686 BL = 0x2
2211 18:08:57.094788 RPST = 0x0
2212 18:08:57.094884 RD_PRE = 0x0
2213 18:08:57.094966 WR_PRE = 0x1
2214 18:08:57.095076 WR_PST = 0x0
2215 18:08:57.095163 DBI_WR = 0x0
2216 18:08:57.095257 DBI_RD = 0x0
2217 18:08:57.095339 OTF = 0x1
2218 18:08:57.095421 ===================================
2219 18:08:57.095503 ===================================
2220 18:08:57.095612 ANA top config
2221 18:08:57.095694 ===================================
2222 18:08:57.095775 DLL_ASYNC_EN = 0
2223 18:08:57.095857 ALL_SLAVE_EN = 0
2224 18:08:57.095938 NEW_RANK_MODE = 1
2225 18:08:57.096021 DLL_IDLE_MODE = 1
2226 18:08:57.096102 LP45_APHY_COMB_EN = 1
2227 18:08:57.096183 TX_ODT_DIS = 1
2228 18:08:57.096265 NEW_8X_MODE = 1
2229 18:08:57.096348 ===================================
2230 18:08:57.096430 ===================================
2231 18:08:57.096511 data_rate = 2400
2232 18:08:57.096629 CKR = 1
2233 18:08:57.096711 DQ_P2S_RATIO = 8
2234 18:08:57.096793 ===================================
2235 18:08:57.096875 CA_P2S_RATIO = 8
2236 18:08:57.096956 DQ_CA_OPEN = 0
2237 18:08:57.097051 DQ_SEMI_OPEN = 0
2238 18:08:57.097207 CA_SEMI_OPEN = 0
2239 18:08:57.097342 CA_FULL_RATE = 0
2240 18:08:57.097455 DQ_CKDIV4_EN = 0
2241 18:08:57.097568 CA_CKDIV4_EN = 0
2242 18:08:57.097665 CA_PREDIV_EN = 0
2243 18:08:57.097746 PH8_DLY = 17
2244 18:08:57.097870 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 18:08:57.097963 DQ_AAMCK_DIV = 4
2246 18:08:57.098045 CA_AAMCK_DIV = 4
2247 18:08:57.098126 CA_ADMCK_DIV = 4
2248 18:08:57.098207 DQ_TRACK_CA_EN = 0
2249 18:08:57.098288 CA_PICK = 1200
2250 18:08:57.098369 CA_MCKIO = 1200
2251 18:08:57.098451 MCKIO_SEMI = 0
2252 18:08:57.098540 PLL_FREQ = 2366
2253 18:08:57.098600 DQ_UI_PI_RATIO = 32
2254 18:08:57.098653 CA_UI_PI_RATIO = 0
2255 18:08:57.098706 ===================================
2256 18:08:57.098759 ===================================
2257 18:08:57.098815 memory_type:LPDDR4
2258 18:08:57.098869 GP_NUM : 10
2259 18:08:57.098922 SRAM_EN : 1
2260 18:08:57.098977 MD32_EN : 0
2261 18:08:57.099029 ===================================
2262 18:08:57.099082 [ANA_INIT] >>>>>>>>>>>>>>
2263 18:08:57.099134 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 18:08:57.099204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 18:08:57.099270 ===================================
2266 18:08:57.099323 data_rate = 2400,PCW = 0X5b00
2267 18:08:57.099376 ===================================
2268 18:08:57.099431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 18:08:57.099485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 18:08:57.099540 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 18:08:57.099594 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 18:08:57.099650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 18:08:57.099703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 18:08:57.099770 [ANA_INIT] flow start
2275 18:08:57.099826 [ANA_INIT] PLL >>>>>>>>
2276 18:08:57.099878 [ANA_INIT] PLL <<<<<<<<
2277 18:08:57.099930 [ANA_INIT] MIDPI >>>>>>>>
2278 18:08:57.099982 [ANA_INIT] MIDPI <<<<<<<<
2279 18:08:57.100035 [ANA_INIT] DLL >>>>>>>>
2280 18:08:57.100087 [ANA_INIT] DLL <<<<<<<<
2281 18:08:57.100139 [ANA_INIT] flow end
2282 18:08:57.100191 ============ LP4 DIFF to SE enter ============
2283 18:08:57.100245 ============ LP4 DIFF to SE exit ============
2284 18:08:57.100297 [ANA_INIT] <<<<<<<<<<<<<
2285 18:08:57.100349 [Flow] Enable top DCM control >>>>>
2286 18:08:57.100401 [Flow] Enable top DCM control <<<<<
2287 18:08:57.100653 Enable DLL master slave shuffle
2288 18:08:57.100714 ==============================================================
2289 18:08:57.100768 Gating Mode config
2290 18:08:57.100821 ==============================================================
2291 18:08:57.100875 Config description:
2292 18:08:57.100928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 18:08:57.100983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 18:08:57.101037 SELPH_MODE 0: By rank 1: By Phase
2295 18:08:57.101091 ==============================================================
2296 18:08:57.101144 GAT_TRACK_EN = 1
2297 18:08:57.101197 RX_GATING_MODE = 2
2298 18:08:57.101249 RX_GATING_TRACK_MODE = 2
2299 18:08:57.101302 SELPH_MODE = 1
2300 18:08:57.101399 PICG_EARLY_EN = 1
2301 18:08:57.101465 VALID_LAT_VALUE = 1
2302 18:08:57.101517 ==============================================================
2303 18:08:57.101570 Enter into Gating configuration >>>>
2304 18:08:57.101626 Exit from Gating configuration <<<<
2305 18:08:57.101694 Enter into DVFS_PRE_config >>>>>
2306 18:08:57.101748 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 18:08:57.101802 Exit from DVFS_PRE_config <<<<<
2308 18:08:57.101855 Enter into PICG configuration >>>>
2309 18:08:57.101953 Exit from PICG configuration <<<<
2310 18:08:57.102037 [RX_INPUT] configuration >>>>>
2311 18:08:57.102090 [RX_INPUT] configuration <<<<<
2312 18:08:57.102144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 18:08:57.102210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 18:08:57.102263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 18:08:57.102316 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 18:08:57.102369 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 18:08:57.102421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 18:08:57.102474 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 18:08:57.102526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 18:08:57.102579 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 18:08:57.102650 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 18:08:57.102715 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 18:08:57.102781 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 18:08:57.102835 ===================================
2325 18:08:57.102888 LPDDR4 DRAM CONFIGURATION
2326 18:08:57.102957 ===================================
2327 18:08:57.103054 EX_ROW_EN[0] = 0x0
2328 18:08:57.103121 EX_ROW_EN[1] = 0x0
2329 18:08:57.103174 LP4Y_EN = 0x0
2330 18:08:57.103235 WORK_FSP = 0x0
2331 18:08:57.103302 WL = 0x4
2332 18:08:57.103368 RL = 0x4
2333 18:08:57.103420 BL = 0x2
2334 18:08:57.103473 RPST = 0x0
2335 18:08:57.103525 RD_PRE = 0x0
2336 18:08:57.103577 WR_PRE = 0x1
2337 18:08:57.103629 WR_PST = 0x0
2338 18:08:57.103680 DBI_WR = 0x0
2339 18:08:57.103732 DBI_RD = 0x0
2340 18:08:57.103784 OTF = 0x1
2341 18:08:57.103836 ===================================
2342 18:08:57.103889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 18:08:57.103942 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 18:08:57.103994 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 18:08:57.104046 ===================================
2346 18:08:57.104098 LPDDR4 DRAM CONFIGURATION
2347 18:08:57.104150 ===================================
2348 18:08:57.104202 EX_ROW_EN[0] = 0x10
2349 18:08:57.104254 EX_ROW_EN[1] = 0x0
2350 18:08:57.104306 LP4Y_EN = 0x0
2351 18:08:57.104358 WORK_FSP = 0x0
2352 18:08:57.104410 WL = 0x4
2353 18:08:57.104462 RL = 0x4
2354 18:08:57.104514 BL = 0x2
2355 18:08:57.104590 RPST = 0x0
2356 18:08:57.104656 RD_PRE = 0x0
2357 18:08:57.104708 WR_PRE = 0x1
2358 18:08:57.104760 WR_PST = 0x0
2359 18:08:57.104812 DBI_WR = 0x0
2360 18:08:57.104864 DBI_RD = 0x0
2361 18:08:57.104928 OTF = 0x1
2362 18:08:57.104983 ===================================
2363 18:08:57.105035 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 18:08:57.105087 ==
2365 18:08:57.105141 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 18:08:57.105193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 18:08:57.105244 ==
2368 18:08:57.105298 [Duty_Offset_Calibration]
2369 18:08:57.105364 B0:2 B1:0 CA:1
2370 18:08:57.105418
2371 18:08:57.105469 [DutyScan_Calibration_Flow] k_type=0
2372 18:08:57.105535
2373 18:08:57.105611 ==CLK 0==
2374 18:08:57.105705 Final CLK duty delay cell = -4
2375 18:08:57.105760 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2376 18:08:57.105812 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2377 18:08:57.105864 [-4] AVG Duty = 4953%(X100)
2378 18:08:57.105930
2379 18:08:57.105980 CH0 CLK Duty spec in!! Max-Min= 156%
2380 18:08:57.106036 [DutyScan_Calibration_Flow] ====Done====
2381 18:08:57.106099
2382 18:08:57.106151 [DutyScan_Calibration_Flow] k_type=1
2383 18:08:57.106202
2384 18:08:57.106252 ==DQS 0 ==
2385 18:08:57.106303 Final DQS duty delay cell = 0
2386 18:08:57.106354 [0] MAX Duty = 5187%(X100), DQS PI = 30
2387 18:08:57.106404 [0] MIN Duty = 4938%(X100), DQS PI = 0
2388 18:08:57.106455 [0] AVG Duty = 5062%(X100)
2389 18:08:57.106505
2390 18:08:57.106555 ==DQS 1 ==
2391 18:08:57.106605 Final DQS duty delay cell = -4
2392 18:08:57.106656 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2393 18:08:57.106707 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2394 18:08:57.106758 [-4] AVG Duty = 5031%(X100)
2395 18:08:57.106809
2396 18:08:57.106888 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2397 18:08:57.106939
2398 18:08:57.106989 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2399 18:08:57.107039 [DutyScan_Calibration_Flow] ====Done====
2400 18:08:57.107089
2401 18:08:57.107140 [DutyScan_Calibration_Flow] k_type=3
2402 18:08:57.107190
2403 18:08:57.107242 ==DQM 0 ==
2404 18:08:57.107293 Final DQM duty delay cell = 0
2405 18:08:57.107344 [0] MAX Duty = 5062%(X100), DQS PI = 24
2406 18:08:57.107395 [0] MIN Duty = 4813%(X100), DQS PI = 0
2407 18:08:57.107445 [0] AVG Duty = 4937%(X100)
2408 18:08:57.107496
2409 18:08:57.107547 ==DQM 1 ==
2410 18:08:57.107597 Final DQM duty delay cell = 0
2411 18:08:57.107844 [0] MAX Duty = 5187%(X100), DQS PI = 48
2412 18:08:57.107947 [0] MIN Duty = 5000%(X100), DQS PI = 12
2413 18:08:57.108002 [0] AVG Duty = 5093%(X100)
2414 18:08:57.108055
2415 18:08:57.108107 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2416 18:08:57.108160
2417 18:08:57.108267 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2418 18:08:57.108352 [DutyScan_Calibration_Flow] ====Done====
2419 18:08:57.108440
2420 18:08:57.108535 [DutyScan_Calibration_Flow] k_type=2
2421 18:08:57.108651
2422 18:08:57.108702 ==DQ 0 ==
2423 18:08:57.108754 Final DQ duty delay cell = -4
2424 18:08:57.108806 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2425 18:08:57.108858 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2426 18:08:57.108908 [-4] AVG Duty = 4968%(X100)
2427 18:08:57.108959
2428 18:08:57.109010 ==DQ 1 ==
2429 18:08:57.109061 Final DQ duty delay cell = 4
2430 18:08:57.109112 [4] MAX Duty = 5093%(X100), DQS PI = 6
2431 18:08:57.109163 [4] MIN Duty = 5031%(X100), DQS PI = 0
2432 18:08:57.109214 [4] AVG Duty = 5062%(X100)
2433 18:08:57.109265
2434 18:08:57.109315 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2435 18:08:57.109365
2436 18:08:57.109415 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2437 18:08:57.109465 [DutyScan_Calibration_Flow] ====Done====
2438 18:08:57.109515 ==
2439 18:08:57.109566 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 18:08:57.109616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 18:08:57.109666 ==
2442 18:08:57.109717 [Duty_Offset_Calibration]
2443 18:08:57.109767 B0:0 B1:-1 CA:2
2444 18:08:57.109818
2445 18:08:57.109868 [DutyScan_Calibration_Flow] k_type=0
2446 18:08:57.109919
2447 18:08:57.109970 ==CLK 0==
2448 18:08:57.110020 Final CLK duty delay cell = 0
2449 18:08:57.110071 [0] MAX Duty = 5156%(X100), DQS PI = 16
2450 18:08:57.110122 [0] MIN Duty = 4938%(X100), DQS PI = 44
2451 18:08:57.110173 [0] AVG Duty = 5047%(X100)
2452 18:08:57.110223
2453 18:08:57.110273 CH1 CLK Duty spec in!! Max-Min= 218%
2454 18:08:57.110324 [DutyScan_Calibration_Flow] ====Done====
2455 18:08:57.110374
2456 18:08:57.110424 [DutyScan_Calibration_Flow] k_type=1
2457 18:08:57.110474
2458 18:08:57.110526 ==DQS 0 ==
2459 18:08:57.110584 Final DQS duty delay cell = 0
2460 18:08:57.110637 [0] MAX Duty = 5062%(X100), DQS PI = 22
2461 18:08:57.110689 [0] MIN Duty = 4969%(X100), DQS PI = 0
2462 18:08:57.110739 [0] AVG Duty = 5015%(X100)
2463 18:08:57.110790
2464 18:08:57.110841 ==DQS 1 ==
2465 18:08:57.110902 Final DQS duty delay cell = 0
2466 18:08:57.110953 [0] MAX Duty = 5156%(X100), DQS PI = 0
2467 18:08:57.111003 [0] MIN Duty = 4844%(X100), DQS PI = 36
2468 18:08:57.111056 [0] AVG Duty = 5000%(X100)
2469 18:08:57.111107
2470 18:08:57.111156 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2471 18:08:57.111207
2472 18:08:57.111260 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2473 18:08:57.111311 [DutyScan_Calibration_Flow] ====Done====
2474 18:08:57.111382
2475 18:08:57.111436 [DutyScan_Calibration_Flow] k_type=3
2476 18:08:57.111487
2477 18:08:57.111538 ==DQM 0 ==
2478 18:08:57.111589 Final DQM duty delay cell = 4
2479 18:08:57.111640 [4] MAX Duty = 5062%(X100), DQS PI = 6
2480 18:08:57.111691 [4] MIN Duty = 4907%(X100), DQS PI = 46
2481 18:08:57.111742 [4] AVG Duty = 4984%(X100)
2482 18:08:57.111792
2483 18:08:57.111842 ==DQM 1 ==
2484 18:08:57.111893 Final DQM duty delay cell = 0
2485 18:08:57.111944 [0] MAX Duty = 5249%(X100), DQS PI = 60
2486 18:08:57.111995 [0] MIN Duty = 4875%(X100), DQS PI = 36
2487 18:08:57.112045 [0] AVG Duty = 5062%(X100)
2488 18:08:57.112096
2489 18:08:57.112147 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2490 18:08:57.112197
2491 18:08:57.112247 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2492 18:08:57.112298 [DutyScan_Calibration_Flow] ====Done====
2493 18:08:57.112349
2494 18:08:57.112399 [DutyScan_Calibration_Flow] k_type=2
2495 18:08:57.112449
2496 18:08:57.112499 ==DQ 0 ==
2497 18:08:57.112556 Final DQ duty delay cell = 0
2498 18:08:57.112648 [0] MAX Duty = 5062%(X100), DQS PI = 22
2499 18:08:57.112700 [0] MIN Duty = 4938%(X100), DQS PI = 0
2500 18:08:57.112750 [0] AVG Duty = 5000%(X100)
2501 18:08:57.112801
2502 18:08:57.112851 ==DQ 1 ==
2503 18:08:57.112902 Final DQ duty delay cell = 0
2504 18:08:57.112953 [0] MAX Duty = 5031%(X100), DQS PI = 0
2505 18:08:57.113004 [0] MIN Duty = 4813%(X100), DQS PI = 34
2506 18:08:57.113055 [0] AVG Duty = 4922%(X100)
2507 18:08:57.113105
2508 18:08:57.113154 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2509 18:08:57.113205
2510 18:08:57.113254 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2511 18:08:57.113304 [DutyScan_Calibration_Flow] ====Done====
2512 18:08:57.113354 nWR fixed to 30
2513 18:08:57.113406 [ModeRegInit_LP4] CH0 RK0
2514 18:08:57.113456 [ModeRegInit_LP4] CH0 RK1
2515 18:08:57.113507 [ModeRegInit_LP4] CH1 RK0
2516 18:08:57.113557 [ModeRegInit_LP4] CH1 RK1
2517 18:08:57.113607 match AC timing 7
2518 18:08:57.113656 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 18:08:57.113707 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 18:08:57.113758 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 18:08:57.113809 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 18:08:57.113859 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 18:08:57.113910 ==
2524 18:08:57.113960 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 18:08:57.114011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 18:08:57.114062 ==
2527 18:08:57.114112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 18:08:57.114163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2529 18:08:57.114214 [CA 0] Center 38 (8~69) winsize 62
2530 18:08:57.114265 [CA 1] Center 38 (8~69) winsize 62
2531 18:08:57.114315 [CA 2] Center 35 (5~66) winsize 62
2532 18:08:57.114365 [CA 3] Center 35 (4~66) winsize 63
2533 18:08:57.114416 [CA 4] Center 34 (4~65) winsize 62
2534 18:08:57.114466 [CA 5] Center 33 (3~64) winsize 62
2535 18:08:57.114516
2536 18:08:57.114566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2537 18:08:57.114617
2538 18:08:57.114667 [CATrainingPosCal] consider 1 rank data
2539 18:08:57.114717 u2DelayCellTimex100 = 270/100 ps
2540 18:08:57.114768 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2541 18:08:57.114819 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2542 18:08:57.114870 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2543 18:08:57.114920 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2544 18:08:57.114971 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2545 18:08:57.115040 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2546 18:08:57.115095
2547 18:08:57.115146 CA PerBit enable=1, Macro0, CA PI delay=33
2548 18:08:57.115197
2549 18:08:57.115248 [CBTSetCACLKResult] CA Dly = 33
2550 18:08:57.115298 CS Dly: 6 (0~37)
2551 18:08:57.115349 ==
2552 18:08:57.115399 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 18:08:57.115450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 18:08:57.115501 ==
2555 18:08:57.115552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 18:08:57.115603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2557 18:08:57.115854 [CA 0] Center 39 (8~70) winsize 63
2558 18:08:57.115912 [CA 1] Center 38 (8~69) winsize 62
2559 18:08:57.115964 [CA 2] Center 35 (5~66) winsize 62
2560 18:08:57.116015 [CA 3] Center 35 (5~66) winsize 62
2561 18:08:57.116066 [CA 4] Center 34 (4~65) winsize 62
2562 18:08:57.116117 [CA 5] Center 34 (4~64) winsize 61
2563 18:08:57.116168
2564 18:08:57.116218 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2565 18:08:57.116269
2566 18:08:57.116319 [CATrainingPosCal] consider 2 rank data
2567 18:08:57.116370 u2DelayCellTimex100 = 270/100 ps
2568 18:08:57.116422 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2569 18:08:57.116473 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2570 18:08:57.116524 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2571 18:08:57.116612 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2572 18:08:57.116663 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2573 18:08:57.116713 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2574 18:08:57.116764
2575 18:08:57.116814 CA PerBit enable=1, Macro0, CA PI delay=34
2576 18:08:57.116864
2577 18:08:57.116914 [CBTSetCACLKResult] CA Dly = 34
2578 18:08:57.116965 CS Dly: 7 (0~39)
2579 18:08:57.117015
2580 18:08:57.117065 ----->DramcWriteLeveling(PI) begin...
2581 18:08:57.117117 ==
2582 18:08:57.117168 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 18:08:57.117219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 18:08:57.117270 ==
2585 18:08:57.117321 Write leveling (Byte 0): 33 => 33
2586 18:08:57.117372 Write leveling (Byte 1): 30 => 30
2587 18:08:57.117423 DramcWriteLeveling(PI) end<-----
2588 18:08:57.117473
2589 18:08:57.117523 ==
2590 18:08:57.117573 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 18:08:57.117624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 18:08:57.117675 ==
2593 18:08:57.117726 [Gating] SW mode calibration
2594 18:08:57.117777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 18:08:57.117828 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 18:08:57.117879 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2597 18:08:57.117930 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2598 18:08:57.117981 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 18:08:57.118031 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 18:08:57.118082 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 18:08:57.118132 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 18:08:57.118183 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2603 18:08:57.118244 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2604 18:08:57.118303 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2605 18:08:57.118355 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 18:08:57.118407 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 18:08:57.118457 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 18:08:57.118508 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 18:08:57.118559 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 18:08:57.118609 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2611 18:08:57.118660 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2612 18:08:57.118710 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
2613 18:08:57.118761 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 18:08:57.118812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 18:08:57.118862 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 18:08:57.118913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 18:08:57.118963 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 18:08:57.119014 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 18:08:57.119064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 18:08:57.119115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2621 18:08:57.119166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 18:08:57.119217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 18:08:57.119267 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 18:08:57.119317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 18:08:57.119368 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 18:08:57.119419 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 18:08:57.119469 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 18:08:57.119519 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 18:08:57.119570 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 18:08:57.119621 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 18:08:57.119672 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 18:08:57.119722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 18:08:57.119773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 18:08:57.119823 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 18:08:57.119874 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 18:08:57.119924 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2637 18:08:57.119975 Total UI for P1: 0, mck2ui 16
2638 18:08:57.120026 best dqsien dly found for B0: ( 1, 3, 28)
2639 18:08:57.120077 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 18:08:57.120127 Total UI for P1: 0, mck2ui 16
2641 18:08:57.120179 best dqsien dly found for B1: ( 1, 4, 0)
2642 18:08:57.120230 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2643 18:08:57.120281 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2644 18:08:57.120331
2645 18:08:57.120382 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2646 18:08:57.120432 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2647 18:08:57.120483 [Gating] SW calibration Done
2648 18:08:57.120533 ==
2649 18:08:57.120623 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 18:08:57.120674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 18:08:57.120725 ==
2652 18:08:57.120776 RX Vref Scan: 0
2653 18:08:57.120826
2654 18:08:57.120876 RX Vref 0 -> 0, step: 1
2655 18:08:57.120926
2656 18:08:57.120976 RX Delay -40 -> 252, step: 8
2657 18:08:57.121026 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2658 18:08:57.121077 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2659 18:08:57.121128 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2660 18:08:57.121178 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2661 18:08:57.121229 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2662 18:08:57.121471 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2663 18:08:57.121532 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2664 18:08:57.121584 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2665 18:08:57.121636 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2666 18:08:57.121687 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2667 18:08:57.121738 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2668 18:08:57.121789 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2669 18:08:57.121840 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2670 18:08:57.121890 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2671 18:08:57.121941 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2672 18:08:57.121992 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2673 18:08:57.122043 ==
2674 18:08:57.122094 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 18:08:57.122145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 18:08:57.122196 ==
2677 18:08:57.122246 DQS Delay:
2678 18:08:57.122297 DQS0 = 0, DQS1 = 0
2679 18:08:57.122349 DQM Delay:
2680 18:08:57.122399 DQM0 = 122, DQM1 = 110
2681 18:08:57.122450 DQ Delay:
2682 18:08:57.122502 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2683 18:08:57.122592 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2684 18:08:57.122642 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2685 18:08:57.122697 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2686 18:08:57.122748
2687 18:08:57.122798
2688 18:08:57.122851 ==
2689 18:08:57.122903 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 18:08:57.122954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 18:08:57.123005 ==
2692 18:08:57.123058
2693 18:08:57.123108
2694 18:08:57.123158 TX Vref Scan disable
2695 18:08:57.123209 == TX Byte 0 ==
2696 18:08:57.123262 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2697 18:08:57.123314 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2698 18:08:57.123364 == TX Byte 1 ==
2699 18:08:57.123416 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2700 18:08:57.123467 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2701 18:08:57.123518 ==
2702 18:08:57.123569 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 18:08:57.123623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 18:08:57.123675 ==
2705 18:08:57.123725 TX Vref=22, minBit 4, minWin=23, winSum=408
2706 18:08:57.123778 TX Vref=24, minBit 7, minWin=24, winSum=414
2707 18:08:57.123829 TX Vref=26, minBit 0, minWin=25, winSum=418
2708 18:08:57.123880 TX Vref=28, minBit 2, minWin=25, winSum=425
2709 18:08:57.123931 TX Vref=30, minBit 7, minWin=25, winSum=430
2710 18:08:57.123982 TX Vref=32, minBit 7, minWin=25, winSum=425
2711 18:08:57.124033 [TxChooseVref] Worse bit 7, Min win 25, Win sum 430, Final Vref 30
2712 18:08:57.124084
2713 18:08:57.124134 Final TX Range 1 Vref 30
2714 18:08:57.124185
2715 18:08:57.124235 ==
2716 18:08:57.124284 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 18:08:57.124335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 18:08:57.124386 ==
2719 18:08:57.124436
2720 18:08:57.124485
2721 18:08:57.124536 TX Vref Scan disable
2722 18:08:57.124630 == TX Byte 0 ==
2723 18:08:57.124694 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2724 18:08:57.124746 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2725 18:08:57.124797 == TX Byte 1 ==
2726 18:08:57.124847 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2727 18:08:57.124898 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2728 18:08:57.124949
2729 18:08:57.124999 [DATLAT]
2730 18:08:57.125049 Freq=1200, CH0 RK0
2731 18:08:57.125101
2732 18:08:57.125151 DATLAT Default: 0xd
2733 18:08:57.125202 0, 0xFFFF, sum = 0
2734 18:08:57.125254 1, 0xFFFF, sum = 0
2735 18:08:57.125306 2, 0xFFFF, sum = 0
2736 18:08:57.125358 3, 0xFFFF, sum = 0
2737 18:08:57.125409 4, 0xFFFF, sum = 0
2738 18:08:57.125461 5, 0xFFFF, sum = 0
2739 18:08:57.125512 6, 0xFFFF, sum = 0
2740 18:08:57.125564 7, 0xFFFF, sum = 0
2741 18:08:57.125615 8, 0xFFFF, sum = 0
2742 18:08:57.125666 9, 0xFFFF, sum = 0
2743 18:08:57.125717 10, 0xFFFF, sum = 0
2744 18:08:57.125768 11, 0xFFFF, sum = 0
2745 18:08:57.125819 12, 0x0, sum = 1
2746 18:08:57.125871 13, 0x0, sum = 2
2747 18:08:57.125921 14, 0x0, sum = 3
2748 18:08:57.125972 15, 0x0, sum = 4
2749 18:08:57.126023 best_step = 13
2750 18:08:57.126073
2751 18:08:57.126123 ==
2752 18:08:57.126173 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 18:08:57.126223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 18:08:57.126274 ==
2755 18:08:57.126324 RX Vref Scan: 1
2756 18:08:57.126375
2757 18:08:57.126425 Set Vref Range= 32 -> 127
2758 18:08:57.126476
2759 18:08:57.126525 RX Vref 32 -> 127, step: 1
2760 18:08:57.126576
2761 18:08:57.126625 RX Delay -13 -> 252, step: 4
2762 18:08:57.126676
2763 18:08:57.126726 Set Vref, RX VrefLevel [Byte0]: 32
2764 18:08:57.126776 [Byte1]: 32
2765 18:08:57.126827
2766 18:08:57.126877 Set Vref, RX VrefLevel [Byte0]: 33
2767 18:08:57.126928 [Byte1]: 33
2768 18:08:57.126978
2769 18:08:57.127029 Set Vref, RX VrefLevel [Byte0]: 34
2770 18:08:57.127079 [Byte1]: 34
2771 18:08:57.127130
2772 18:08:57.127180 Set Vref, RX VrefLevel [Byte0]: 35
2773 18:08:57.127230 [Byte1]: 35
2774 18:08:57.127280
2775 18:08:57.127330 Set Vref, RX VrefLevel [Byte0]: 36
2776 18:08:57.127381 [Byte1]: 36
2777 18:08:57.127431
2778 18:08:57.127481 Set Vref, RX VrefLevel [Byte0]: 37
2779 18:08:57.127532 [Byte1]: 37
2780 18:08:57.127583
2781 18:08:57.127633 Set Vref, RX VrefLevel [Byte0]: 38
2782 18:08:57.127683 [Byte1]: 38
2783 18:08:57.127734
2784 18:08:57.127784 Set Vref, RX VrefLevel [Byte0]: 39
2785 18:08:57.127835 [Byte1]: 39
2786 18:08:57.127885
2787 18:08:57.127936 Set Vref, RX VrefLevel [Byte0]: 40
2788 18:08:57.127986 [Byte1]: 40
2789 18:08:57.128037
2790 18:08:57.128087 Set Vref, RX VrefLevel [Byte0]: 41
2791 18:08:57.128138 [Byte1]: 41
2792 18:08:57.128188
2793 18:08:57.128238 Set Vref, RX VrefLevel [Byte0]: 42
2794 18:08:57.128289 [Byte1]: 42
2795 18:08:57.128339
2796 18:08:57.128404 Set Vref, RX VrefLevel [Byte0]: 43
2797 18:08:57.128487 [Byte1]: 43
2798 18:08:57.128604
2799 18:08:57.128659 Set Vref, RX VrefLevel [Byte0]: 44
2800 18:08:57.128710 [Byte1]: 44
2801 18:08:57.128762
2802 18:08:57.128812 Set Vref, RX VrefLevel [Byte0]: 45
2803 18:08:57.128864 [Byte1]: 45
2804 18:08:57.128915
2805 18:08:57.128966 Set Vref, RX VrefLevel [Byte0]: 46
2806 18:08:57.129016 [Byte1]: 46
2807 18:08:57.129066
2808 18:08:57.129116 Set Vref, RX VrefLevel [Byte0]: 47
2809 18:08:57.129167 [Byte1]: 47
2810 18:08:57.129218
2811 18:08:57.129268 Set Vref, RX VrefLevel [Byte0]: 48
2812 18:08:57.129319 [Byte1]: 48
2813 18:08:57.129370
2814 18:08:57.129420 Set Vref, RX VrefLevel [Byte0]: 49
2815 18:08:57.129471 [Byte1]: 49
2816 18:08:57.129521
2817 18:08:57.129572 Set Vref, RX VrefLevel [Byte0]: 50
2818 18:08:57.129622 [Byte1]: 50
2819 18:08:57.129672
2820 18:08:57.129722 Set Vref, RX VrefLevel [Byte0]: 51
2821 18:08:57.129965 [Byte1]: 51
2822 18:08:57.130022
2823 18:08:57.130074 Set Vref, RX VrefLevel [Byte0]: 52
2824 18:08:57.130126 [Byte1]: 52
2825 18:08:57.130177
2826 18:08:57.130228 Set Vref, RX VrefLevel [Byte0]: 53
2827 18:08:57.130279 [Byte1]: 53
2828 18:08:57.130330
2829 18:08:57.130380 Set Vref, RX VrefLevel [Byte0]: 54
2830 18:08:57.130431 [Byte1]: 54
2831 18:08:57.130482
2832 18:08:57.130533 Set Vref, RX VrefLevel [Byte0]: 55
2833 18:08:57.130584 [Byte1]: 55
2834 18:08:57.130635
2835 18:08:57.130685 Set Vref, RX VrefLevel [Byte0]: 56
2836 18:08:57.130735 [Byte1]: 56
2837 18:08:57.130786
2838 18:08:57.130837 Set Vref, RX VrefLevel [Byte0]: 57
2839 18:08:57.130887 [Byte1]: 57
2840 18:08:57.130938
2841 18:08:57.130988 Set Vref, RX VrefLevel [Byte0]: 58
2842 18:08:57.131039 [Byte1]: 58
2843 18:08:57.131090
2844 18:08:57.131140 Set Vref, RX VrefLevel [Byte0]: 59
2845 18:08:57.131191 [Byte1]: 59
2846 18:08:57.131242
2847 18:08:57.131292 Set Vref, RX VrefLevel [Byte0]: 60
2848 18:08:57.131342 [Byte1]: 60
2849 18:08:57.131393
2850 18:08:57.131464 Set Vref, RX VrefLevel [Byte0]: 61
2851 18:08:57.131518 [Byte1]: 61
2852 18:08:57.131569
2853 18:08:57.131620 Set Vref, RX VrefLevel [Byte0]: 62
2854 18:08:57.131671 [Byte1]: 62
2855 18:08:57.131722
2856 18:08:57.131772 Set Vref, RX VrefLevel [Byte0]: 63
2857 18:08:57.131823 [Byte1]: 63
2858 18:08:57.131874
2859 18:08:57.131924 Set Vref, RX VrefLevel [Byte0]: 64
2860 18:08:57.131975 [Byte1]: 64
2861 18:08:57.132025
2862 18:08:57.132075 Set Vref, RX VrefLevel [Byte0]: 65
2863 18:08:57.132126 [Byte1]: 65
2864 18:08:57.132177
2865 18:08:57.132228 Set Vref, RX VrefLevel [Byte0]: 66
2866 18:08:57.132278 [Byte1]: 66
2867 18:08:57.132329
2868 18:08:57.132379 Set Vref, RX VrefLevel [Byte0]: 67
2869 18:08:57.132429 [Byte1]: 67
2870 18:08:57.132480
2871 18:08:57.132530 Set Vref, RX VrefLevel [Byte0]: 68
2872 18:08:57.132627 [Byte1]: 68
2873 18:08:57.132678
2874 18:08:57.132728 Set Vref, RX VrefLevel [Byte0]: 69
2875 18:08:57.132779 [Byte1]: 69
2876 18:08:57.132829
2877 18:08:57.132879 Set Vref, RX VrefLevel [Byte0]: 70
2878 18:08:57.132930 [Byte1]: 70
2879 18:08:57.132980
2880 18:08:57.133031 Final RX Vref Byte 0 = 59 to rank0
2881 18:08:57.133082 Final RX Vref Byte 1 = 48 to rank0
2882 18:08:57.133133 Final RX Vref Byte 0 = 59 to rank1
2883 18:08:57.133184 Final RX Vref Byte 1 = 48 to rank1==
2884 18:08:57.133235 Dram Type= 6, Freq= 0, CH_0, rank 0
2885 18:08:57.133286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 18:08:57.133338 ==
2887 18:08:57.133388 DQS Delay:
2888 18:08:57.133439 DQS0 = 0, DQS1 = 0
2889 18:08:57.133489 DQM Delay:
2890 18:08:57.133540 DQM0 = 122, DQM1 = 109
2891 18:08:57.133590 DQ Delay:
2892 18:08:57.133640 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2893 18:08:57.133692 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2894 18:08:57.133743 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =104
2895 18:08:57.133793 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2896 18:08:57.133844
2897 18:08:57.133894
2898 18:08:57.133944 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2899 18:08:57.133996 CH0 RK0: MR19=404, MR18=804
2900 18:08:57.134047 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2901 18:08:57.134097
2902 18:08:57.134148 ----->DramcWriteLeveling(PI) begin...
2903 18:08:57.134199 ==
2904 18:08:57.134250 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 18:08:57.134300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 18:08:57.134352 ==
2907 18:08:57.134402 Write leveling (Byte 0): 35 => 35
2908 18:08:57.134453 Write leveling (Byte 1): 29 => 29
2909 18:08:57.134503 DramcWriteLeveling(PI) end<-----
2910 18:08:57.134554
2911 18:08:57.134603 ==
2912 18:08:57.134654 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 18:08:57.134705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 18:08:57.134756 ==
2915 18:08:57.134806 [Gating] SW mode calibration
2916 18:08:57.134875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2917 18:08:57.134929 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2918 18:08:57.134981 0 15 0 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
2919 18:08:57.135032 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 18:08:57.135084 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 18:08:57.135134 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 18:08:57.135185 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 18:08:57.135236 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 18:08:57.135287 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 18:08:57.135338 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (1 0) (0 1)
2926 18:08:57.135388 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 18:08:57.135439 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 18:08:57.135490 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 18:08:57.135541 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 18:08:57.135592 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 18:08:57.135643 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 18:08:57.135693 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2933 18:08:57.135744 1 0 28 | B1->B0 | 3534 4040 | 1 1 | (0 0) (0 0)
2934 18:08:57.135794 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 18:08:57.135845 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 18:08:57.135895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 18:08:57.135945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 18:08:57.135995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 18:08:57.136045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 18:08:57.136096 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 18:08:57.136146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 18:08:57.136196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 18:08:57.136247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 18:08:57.136297 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 18:08:57.136347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 18:08:57.136647 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 18:08:57.136706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 18:08:57.136783 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 18:08:57.136849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 18:08:57.136927 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 18:08:57.136978 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 18:08:57.137029 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 18:08:57.137080 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 18:08:57.137130 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 18:08:57.137181 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 18:08:57.137232 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 18:08:57.137282 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2958 18:08:57.137333 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2959 18:08:57.137383 Total UI for P1: 0, mck2ui 16
2960 18:08:57.137434 best dqsien dly found for B0: ( 1, 3, 28)
2961 18:08:57.137485 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 18:08:57.137536 Total UI for P1: 0, mck2ui 16
2963 18:08:57.137586 best dqsien dly found for B1: ( 1, 4, 0)
2964 18:08:57.137638 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2965 18:08:57.137689 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2966 18:08:57.137740
2967 18:08:57.137790 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2968 18:08:57.137840 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2969 18:08:57.137891 [Gating] SW calibration Done
2970 18:08:57.137941 ==
2971 18:08:57.138013 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 18:08:57.138066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 18:08:57.138118 ==
2974 18:08:57.138168 RX Vref Scan: 0
2975 18:08:57.138219
2976 18:08:57.138269 RX Vref 0 -> 0, step: 1
2977 18:08:57.138319
2978 18:08:57.138369 RX Delay -40 -> 252, step: 8
2979 18:08:57.138419 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2980 18:08:57.138470 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2981 18:08:57.138521 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2982 18:08:57.138572 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2983 18:08:57.138622 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2984 18:08:57.138673 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2985 18:08:57.138723 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2986 18:08:57.138774 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2987 18:08:57.138824 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2988 18:08:57.138875 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2989 18:08:57.138925 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2990 18:08:57.138976 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2991 18:08:57.139026 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2992 18:08:57.139076 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2993 18:08:57.139127 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2994 18:08:57.139177 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2995 18:08:57.139227 ==
2996 18:08:57.139278 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 18:08:57.139329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 18:08:57.139380 ==
2999 18:08:57.139431 DQS Delay:
3000 18:08:57.139481 DQS0 = 0, DQS1 = 0
3001 18:08:57.139532 DQM Delay:
3002 18:08:57.139582 DQM0 = 120, DQM1 = 108
3003 18:08:57.429089 DQ Delay:
3004 18:08:57.429225 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3005 18:08:57.429291 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3006 18:08:57.429350 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3007 18:08:57.429406 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3008 18:08:57.429460
3009 18:08:57.429514
3010 18:08:57.429567 ==
3011 18:08:57.429620 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 18:08:57.429673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 18:08:57.429727 ==
3014 18:08:57.429779
3015 18:08:57.429848
3016 18:08:57.429904 TX Vref Scan disable
3017 18:08:57.429957 == TX Byte 0 ==
3018 18:08:57.430010 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3019 18:08:57.430062 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3020 18:08:57.430114 == TX Byte 1 ==
3021 18:08:57.430166 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3022 18:08:57.430217 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3023 18:08:57.430268 ==
3024 18:08:57.430319 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 18:08:57.430371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 18:08:57.430422 ==
3027 18:08:57.430473 TX Vref=22, minBit 1, minWin=24, winSum=411
3028 18:08:57.430525 TX Vref=24, minBit 0, minWin=24, winSum=415
3029 18:08:57.430576 TX Vref=26, minBit 2, minWin=25, winSum=423
3030 18:08:57.430627 TX Vref=28, minBit 0, minWin=25, winSum=423
3031 18:08:57.430679 TX Vref=30, minBit 1, minWin=25, winSum=426
3032 18:08:57.430729 TX Vref=32, minBit 1, minWin=25, winSum=420
3033 18:08:57.430781 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 30
3034 18:08:57.430833
3035 18:08:57.430884 Final TX Range 1 Vref 30
3036 18:08:57.430934
3037 18:08:57.430984 ==
3038 18:08:57.431035 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 18:08:57.431086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 18:08:57.431138 ==
3041 18:08:57.431188
3042 18:08:57.431239
3043 18:08:57.431289 TX Vref Scan disable
3044 18:08:57.431340 == TX Byte 0 ==
3045 18:08:57.431390 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3046 18:08:57.431441 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3047 18:08:57.431492 == TX Byte 1 ==
3048 18:08:57.431543 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3049 18:08:57.431593 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3050 18:08:57.431644
3051 18:08:57.431694 [DATLAT]
3052 18:08:57.431744 Freq=1200, CH0 RK1
3053 18:08:57.431795
3054 18:08:57.431845 DATLAT Default: 0xd
3055 18:08:57.431896 0, 0xFFFF, sum = 0
3056 18:08:57.431948 1, 0xFFFF, sum = 0
3057 18:08:57.432001 2, 0xFFFF, sum = 0
3058 18:08:57.432052 3, 0xFFFF, sum = 0
3059 18:08:57.432104 4, 0xFFFF, sum = 0
3060 18:08:57.432156 5, 0xFFFF, sum = 0
3061 18:08:57.432208 6, 0xFFFF, sum = 0
3062 18:08:57.432259 7, 0xFFFF, sum = 0
3063 18:08:57.432310 8, 0xFFFF, sum = 0
3064 18:08:57.432362 9, 0xFFFF, sum = 0
3065 18:08:57.432413 10, 0xFFFF, sum = 0
3066 18:08:57.432464 11, 0xFFFF, sum = 0
3067 18:08:57.432516 12, 0x0, sum = 1
3068 18:08:57.432582 13, 0x0, sum = 2
3069 18:08:57.432635 14, 0x0, sum = 3
3070 18:08:57.432687 15, 0x0, sum = 4
3071 18:08:57.432739 best_step = 13
3072 18:08:57.432790
3073 18:08:57.432840 ==
3074 18:08:57.432891 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 18:08:57.432942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 18:08:57.433015 ==
3077 18:08:57.433068 RX Vref Scan: 0
3078 18:08:57.433120
3079 18:08:57.433172 RX Vref 0 -> 0, step: 1
3080 18:08:57.433223
3081 18:08:57.433274 RX Delay -21 -> 252, step: 4
3082 18:08:57.433362 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3083 18:08:57.433650 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3084 18:08:57.433709 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3085 18:08:57.433761 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3086 18:08:57.433813 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3087 18:08:57.433864 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3088 18:08:57.433943 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3089 18:08:57.433993 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3090 18:08:57.434044 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3091 18:08:57.434095 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3092 18:08:57.434146 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3093 18:08:57.434197 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3094 18:08:57.434248 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3095 18:08:57.434299 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3096 18:08:57.434349 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3097 18:08:57.434400 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3098 18:08:57.434451 ==
3099 18:08:57.434502 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 18:08:57.434553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 18:08:57.434604 ==
3102 18:08:57.434654 DQS Delay:
3103 18:08:57.434705 DQS0 = 0, DQS1 = 0
3104 18:08:57.434756 DQM Delay:
3105 18:08:57.434806 DQM0 = 118, DQM1 = 107
3106 18:08:57.434857 DQ Delay:
3107 18:08:57.434907 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3108 18:08:57.434957 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =124
3109 18:08:57.435010 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =106
3110 18:08:57.435061 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3111 18:08:57.435113
3112 18:08:57.435192
3113 18:08:57.435307 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3114 18:08:57.435417 CH0 RK1: MR19=403, MR18=DF5
3115 18:08:57.435513 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3116 18:08:57.435609 [RxdqsGatingPostProcess] freq 1200
3117 18:08:57.435704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3118 18:08:57.435799 best DQS0 dly(2T, 0.5T) = (0, 11)
3119 18:08:57.435894 best DQS1 dly(2T, 0.5T) = (0, 12)
3120 18:08:57.435989 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3121 18:08:57.436146 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3122 18:08:57.436302 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 18:08:57.436396 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 18:08:57.436492 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 18:08:57.436623 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 18:08:57.436731 Pre-setting of DQS Precalculation
3127 18:08:57.436829 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3128 18:08:57.436924 ==
3129 18:08:57.437020 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 18:08:57.437116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 18:08:57.437210 ==
3132 18:08:57.437307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 18:08:57.437431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3134 18:08:57.437527 [CA 0] Center 37 (7~68) winsize 62
3135 18:08:57.437622 [CA 1] Center 37 (7~68) winsize 62
3136 18:08:57.437716 [CA 2] Center 35 (5~65) winsize 61
3137 18:08:57.437810 [CA 3] Center 34 (4~65) winsize 62
3138 18:08:57.437905 [CA 4] Center 34 (4~65) winsize 62
3139 18:08:57.437999 [CA 5] Center 33 (3~64) winsize 62
3140 18:08:57.438092
3141 18:08:57.438186 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3142 18:08:57.438281
3143 18:08:57.438374 [CATrainingPosCal] consider 1 rank data
3144 18:08:57.438468 u2DelayCellTimex100 = 270/100 ps
3145 18:08:57.438562 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3146 18:08:57.438658 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 18:08:57.438752 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3148 18:08:57.438846 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3149 18:08:57.438941 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3150 18:08:57.439035 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3151 18:08:57.439128
3152 18:08:57.439222 CA PerBit enable=1, Macro0, CA PI delay=33
3153 18:08:57.439317
3154 18:08:57.439410 [CBTSetCACLKResult] CA Dly = 33
3155 18:08:57.439505 CS Dly: 5 (0~36)
3156 18:08:57.439598 ==
3157 18:08:57.439694 Dram Type= 6, Freq= 0, CH_1, rank 1
3158 18:08:57.439788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 18:08:57.439882 ==
3160 18:08:57.439983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3161 18:08:57.440068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3162 18:08:57.440150 [CA 0] Center 38 (8~68) winsize 61
3163 18:08:57.440232 [CA 1] Center 38 (7~69) winsize 63
3164 18:08:57.440313 [CA 2] Center 35 (5~66) winsize 62
3165 18:08:57.440395 [CA 3] Center 35 (5~65) winsize 61
3166 18:08:57.440476 [CA 4] Center 35 (5~65) winsize 61
3167 18:08:57.440581 [CA 5] Center 34 (4~64) winsize 61
3168 18:08:57.440677
3169 18:08:57.440759 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3170 18:08:57.440840
3171 18:08:57.440921 [CATrainingPosCal] consider 2 rank data
3172 18:08:57.441002 u2DelayCellTimex100 = 270/100 ps
3173 18:08:57.441084 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3174 18:08:57.441166 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3175 18:08:57.441247 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3176 18:08:57.441329 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3177 18:08:57.441411 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3178 18:08:57.441492 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3179 18:08:57.441573
3180 18:08:57.441654 CA PerBit enable=1, Macro0, CA PI delay=34
3181 18:08:57.441738
3182 18:08:57.441820 [CBTSetCACLKResult] CA Dly = 34
3183 18:08:57.441902 CS Dly: 6 (0~39)
3184 18:08:57.441983
3185 18:08:57.442064 ----->DramcWriteLeveling(PI) begin...
3186 18:08:57.442147 ==
3187 18:08:57.442228 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 18:08:57.442311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 18:08:57.442392 ==
3190 18:08:57.442474 Write leveling (Byte 0): 24 => 24
3191 18:08:57.442555 Write leveling (Byte 1): 27 => 27
3192 18:08:57.442637 DramcWriteLeveling(PI) end<-----
3193 18:08:57.442717
3194 18:08:57.442798 ==
3195 18:08:57.442879 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 18:08:57.442962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 18:08:57.443018 ==
3198 18:08:57.443071 [Gating] SW mode calibration
3199 18:08:57.443125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3200 18:08:57.443179 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3201 18:08:57.443232 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 18:08:57.443501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 18:08:57.443561 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 18:08:57.443616 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 18:08:57.443670 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 18:08:57.443723 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 18:08:57.443775 0 15 24 | B1->B0 | 3030 2929 | 0 0 | (0 0) (1 0)
3208 18:08:57.443828 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3209 18:08:57.443881 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 18:08:57.443934 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 18:08:57.443986 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 18:08:57.444039 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 18:08:57.444092 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 18:08:57.444144 1 0 20 | B1->B0 | 2424 2626 | 1 0 | (0 0) (0 0)
3215 18:08:57.444197 1 0 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3216 18:08:57.444249 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 18:08:57.444302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 18:08:57.444354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 18:08:57.444406 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 18:08:57.444458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 18:08:57.444510 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 18:08:57.444591 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 18:08:57.444662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3224 18:08:57.444715 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3225 18:08:57.444768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 18:08:57.444824 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 18:08:57.444876 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 18:08:57.444928 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 18:08:57.444981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 18:08:57.445033 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 18:08:57.445086 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 18:08:57.445138 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 18:08:57.445190 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 18:08:57.445243 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 18:08:57.445295 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 18:08:57.445347 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 18:08:57.445399 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 18:08:57.445451 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 18:08:57.445504 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 18:08:57.445556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 18:08:57.445608 Total UI for P1: 0, mck2ui 16
3242 18:08:57.445661 best dqsien dly found for B0: ( 1, 3, 24)
3243 18:08:57.445714 Total UI for P1: 0, mck2ui 16
3244 18:08:57.445767 best dqsien dly found for B1: ( 1, 3, 24)
3245 18:08:57.445819 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3246 18:08:57.445871 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3247 18:08:57.445923
3248 18:08:57.445975 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3249 18:08:57.446028 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3250 18:08:57.446081 [Gating] SW calibration Done
3251 18:08:57.446133 ==
3252 18:08:57.446185 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 18:08:57.446237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 18:08:57.446290 ==
3255 18:08:57.446342 RX Vref Scan: 0
3256 18:08:57.446395
3257 18:08:57.446446 RX Vref 0 -> 0, step: 1
3258 18:08:57.446499
3259 18:08:57.446576 RX Delay -40 -> 252, step: 8
3260 18:08:57.446630 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3261 18:08:57.446683 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3262 18:08:57.446737 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3263 18:08:57.446790 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3264 18:08:57.446842 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3265 18:08:57.446894 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3266 18:08:57.446947 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3267 18:08:57.447000 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3268 18:08:57.447052 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3269 18:08:57.447104 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3270 18:08:57.447155 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3271 18:08:57.447207 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3272 18:08:57.447258 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3273 18:08:57.447311 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3274 18:08:57.447361 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3275 18:08:57.447413 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3276 18:08:57.447464 ==
3277 18:08:57.447516 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 18:08:57.447569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 18:08:57.447622 ==
3280 18:08:57.447674 DQS Delay:
3281 18:08:57.447726 DQS0 = 0, DQS1 = 0
3282 18:08:57.447778 DQM Delay:
3283 18:08:57.447830 DQM0 = 119, DQM1 = 113
3284 18:08:57.447883 DQ Delay:
3285 18:08:57.447936 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3286 18:08:57.447988 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3287 18:08:57.448055 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3288 18:08:57.448122 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3289 18:08:57.448174
3290 18:08:57.448254
3291 18:08:57.448359 ==
3292 18:08:57.448457 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 18:08:57.448540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 18:08:57.448656 ==
3295 18:08:57.448724
3296 18:08:57.448776
3297 18:08:57.448828 TX Vref Scan disable
3298 18:08:57.448882 == TX Byte 0 ==
3299 18:08:57.448950 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3300 18:08:57.449017 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3301 18:08:57.449087 == TX Byte 1 ==
3302 18:08:57.449152 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3303 18:08:57.449205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3304 18:08:57.449273 ==
3305 18:08:57.449340 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 18:08:57.449391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 18:08:57.449444 ==
3308 18:08:57.449496 TX Vref=22, minBit 1, minWin=24, winSum=403
3309 18:08:57.449566 TX Vref=24, minBit 11, minWin=24, winSum=409
3310 18:08:57.449852 TX Vref=26, minBit 8, minWin=25, winSum=418
3311 18:08:57.449929 TX Vref=28, minBit 10, minWin=25, winSum=420
3312 18:08:57.449984 TX Vref=30, minBit 10, minWin=25, winSum=425
3313 18:08:57.450038 TX Vref=32, minBit 10, minWin=25, winSum=419
3314 18:08:57.450091 [TxChooseVref] Worse bit 10, Min win 25, Win sum 425, Final Vref 30
3315 18:08:57.450174
3316 18:08:57.450226 Final TX Range 1 Vref 30
3317 18:08:57.450279
3318 18:08:57.450330 ==
3319 18:08:57.450383 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 18:08:57.450452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 18:08:57.450518 ==
3322 18:08:57.450586
3323 18:08:57.450640
3324 18:08:57.450723 TX Vref Scan disable
3325 18:08:57.450791 == TX Byte 0 ==
3326 18:08:57.450843 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3327 18:08:57.450896 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3328 18:08:57.450949 == TX Byte 1 ==
3329 18:08:57.451017 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3330 18:08:57.451101 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3331 18:08:57.451184
3332 18:08:57.451237 [DATLAT]
3333 18:08:57.451320 Freq=1200, CH1 RK0
3334 18:08:57.451387
3335 18:08:57.451439 DATLAT Default: 0xd
3336 18:08:57.451491 0, 0xFFFF, sum = 0
3337 18:08:57.451544 1, 0xFFFF, sum = 0
3338 18:08:57.451614 2, 0xFFFF, sum = 0
3339 18:08:57.451681 3, 0xFFFF, sum = 0
3340 18:08:57.451734 4, 0xFFFF, sum = 0
3341 18:08:57.451787 5, 0xFFFF, sum = 0
3342 18:08:57.451839 6, 0xFFFF, sum = 0
3343 18:08:57.451919 7, 0xFFFF, sum = 0
3344 18:08:57.451972 8, 0xFFFF, sum = 0
3345 18:08:57.452026 9, 0xFFFF, sum = 0
3346 18:08:57.452079 10, 0xFFFF, sum = 0
3347 18:08:57.452146 11, 0xFFFF, sum = 0
3348 18:08:57.452200 12, 0x0, sum = 1
3349 18:08:57.452253 13, 0x0, sum = 2
3350 18:08:57.452320 14, 0x0, sum = 3
3351 18:08:57.452386 15, 0x0, sum = 4
3352 18:08:57.452440 best_step = 13
3353 18:08:57.452492
3354 18:08:57.452554 ==
3355 18:08:57.452627 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 18:08:57.452694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 18:08:57.452761 ==
3358 18:08:57.452819 RX Vref Scan: 1
3359 18:08:57.452886
3360 18:08:57.452954 Set Vref Range= 32 -> 127
3361 18:08:57.453021
3362 18:08:57.453071 RX Vref 32 -> 127, step: 1
3363 18:08:57.453123
3364 18:08:57.453174 RX Delay -13 -> 252, step: 4
3365 18:08:57.453239
3366 18:08:57.453304 Set Vref, RX VrefLevel [Byte0]: 32
3367 18:08:57.453354 [Byte1]: 32
3368 18:08:57.453405
3369 18:08:57.453455 Set Vref, RX VrefLevel [Byte0]: 33
3370 18:08:57.453520 [Byte1]: 33
3371 18:08:57.453585
3372 18:08:57.453635 Set Vref, RX VrefLevel [Byte0]: 34
3373 18:08:57.453686 [Byte1]: 34
3374 18:08:57.453737
3375 18:08:57.453787 Set Vref, RX VrefLevel [Byte0]: 35
3376 18:08:57.453837 [Byte1]: 35
3377 18:08:57.453888
3378 18:08:57.453938 Set Vref, RX VrefLevel [Byte0]: 36
3379 18:08:57.453989 [Byte1]: 36
3380 18:08:57.454040
3381 18:08:57.454090 Set Vref, RX VrefLevel [Byte0]: 37
3382 18:08:57.454141 [Byte1]: 37
3383 18:08:57.454192
3384 18:08:57.454241 Set Vref, RX VrefLevel [Byte0]: 38
3385 18:08:57.454292 [Byte1]: 38
3386 18:08:57.454342
3387 18:08:57.454392 Set Vref, RX VrefLevel [Byte0]: 39
3388 18:08:57.454443 [Byte1]: 39
3389 18:08:57.454493
3390 18:08:57.454543 Set Vref, RX VrefLevel [Byte0]: 40
3391 18:08:57.454593 [Byte1]: 40
3392 18:08:57.454644
3393 18:08:57.454694 Set Vref, RX VrefLevel [Byte0]: 41
3394 18:08:57.454744 [Byte1]: 41
3395 18:08:57.454795
3396 18:08:57.454845 Set Vref, RX VrefLevel [Byte0]: 42
3397 18:08:57.454895 [Byte1]: 42
3398 18:08:57.454945
3399 18:08:57.454995 Set Vref, RX VrefLevel [Byte0]: 43
3400 18:08:57.455045 [Byte1]: 43
3401 18:08:57.455095
3402 18:08:57.455145 Set Vref, RX VrefLevel [Byte0]: 44
3403 18:08:57.455196 [Byte1]: 44
3404 18:08:57.455248
3405 18:08:57.455298 Set Vref, RX VrefLevel [Byte0]: 45
3406 18:08:57.455348 [Byte1]: 45
3407 18:08:57.455398
3408 18:08:57.455448 Set Vref, RX VrefLevel [Byte0]: 46
3409 18:08:57.455499 [Byte1]: 46
3410 18:08:57.455549
3411 18:08:57.455599 Set Vref, RX VrefLevel [Byte0]: 47
3412 18:08:57.455650 [Byte1]: 47
3413 18:08:57.455700
3414 18:08:57.455750 Set Vref, RX VrefLevel [Byte0]: 48
3415 18:08:57.455821 [Byte1]: 48
3416 18:08:57.455886
3417 18:08:57.455936 Set Vref, RX VrefLevel [Byte0]: 49
3418 18:08:57.455986 [Byte1]: 49
3419 18:08:57.456036
3420 18:08:57.456086 Set Vref, RX VrefLevel [Byte0]: 50
3421 18:08:57.456137 [Byte1]: 50
3422 18:08:57.456187
3423 18:08:57.456237 Set Vref, RX VrefLevel [Byte0]: 51
3424 18:08:57.456287 [Byte1]: 51
3425 18:08:57.456337
3426 18:08:57.456388 Set Vref, RX VrefLevel [Byte0]: 52
3427 18:08:57.456438 [Byte1]: 52
3428 18:08:57.456488
3429 18:08:57.456538 Set Vref, RX VrefLevel [Byte0]: 53
3430 18:08:57.456703 [Byte1]: 53
3431 18:08:57.456784
3432 18:08:57.456869 Set Vref, RX VrefLevel [Byte0]: 54
3433 18:08:57.456925 [Byte1]: 54
3434 18:08:57.456976
3435 18:08:57.457028 Set Vref, RX VrefLevel [Byte0]: 55
3436 18:08:57.457078 [Byte1]: 55
3437 18:08:57.457129
3438 18:08:57.457179 Set Vref, RX VrefLevel [Byte0]: 56
3439 18:08:57.457230 [Byte1]: 56
3440 18:08:57.457281
3441 18:08:57.457331 Set Vref, RX VrefLevel [Byte0]: 57
3442 18:08:57.457382 [Byte1]: 57
3443 18:08:57.457432
3444 18:08:57.457482 Set Vref, RX VrefLevel [Byte0]: 58
3445 18:08:57.457533 [Byte1]: 58
3446 18:08:57.457584
3447 18:08:57.457634 Set Vref, RX VrefLevel [Byte0]: 59
3448 18:08:57.457685 [Byte1]: 59
3449 18:08:57.457735
3450 18:08:57.457785 Set Vref, RX VrefLevel [Byte0]: 60
3451 18:08:57.457836 [Byte1]: 60
3452 18:08:57.457886
3453 18:08:57.457941 Set Vref, RX VrefLevel [Byte0]: 61
3454 18:08:57.457992 [Byte1]: 61
3455 18:08:57.458042
3456 18:08:57.458100 Set Vref, RX VrefLevel [Byte0]: 62
3457 18:08:57.458152 [Byte1]: 62
3458 18:08:57.458203
3459 18:08:57.458255 Set Vref, RX VrefLevel [Byte0]: 63
3460 18:08:57.458313 [Byte1]: 63
3461 18:08:57.458365
3462 18:08:57.458415 Set Vref, RX VrefLevel [Byte0]: 64
3463 18:08:57.458466 [Byte1]: 64
3464 18:08:57.458519
3465 18:08:57.458569 Set Vref, RX VrefLevel [Byte0]: 65
3466 18:08:57.458620 [Byte1]: 65
3467 18:08:57.458673
3468 18:08:57.458724 Set Vref, RX VrefLevel [Byte0]: 66
3469 18:08:57.458774 [Byte1]: 66
3470 18:08:57.458825
3471 18:08:57.458876 Set Vref, RX VrefLevel [Byte0]: 67
3472 18:08:57.458927 [Byte1]: 67
3473 18:08:57.458978
3474 18:08:57.459028 Final RX Vref Byte 0 = 54 to rank0
3475 18:08:57.459081 Final RX Vref Byte 1 = 49 to rank0
3476 18:08:57.459132 Final RX Vref Byte 0 = 54 to rank1
3477 18:08:57.459377 Final RX Vref Byte 1 = 49 to rank1==
3478 18:08:57.459438 Dram Type= 6, Freq= 0, CH_1, rank 0
3479 18:08:57.459490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 18:08:57.459542 ==
3481 18:08:57.459593 DQS Delay:
3482 18:08:57.459644 DQS0 = 0, DQS1 = 0
3483 18:08:57.459695 DQM Delay:
3484 18:08:57.459771 DQM0 = 119, DQM1 = 111
3485 18:08:57.459824 DQ Delay:
3486 18:08:57.459876 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3487 18:08:57.459927 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3488 18:08:57.459979 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3489 18:08:57.460031 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3490 18:08:57.460082
3491 18:08:57.460131
3492 18:08:57.460182 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3493 18:08:57.460234 CH1 RK0: MR19=404, MR18=114
3494 18:08:57.460285 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3495 18:08:57.460336
3496 18:08:57.460386 ----->DramcWriteLeveling(PI) begin...
3497 18:08:57.460439 ==
3498 18:08:57.460490 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 18:08:57.460541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 18:08:57.460636 ==
3501 18:08:57.460687 Write leveling (Byte 0): 26 => 26
3502 18:08:57.460738 Write leveling (Byte 1): 30 => 30
3503 18:08:57.460790 DramcWriteLeveling(PI) end<-----
3504 18:08:57.460840
3505 18:08:57.460890 ==
3506 18:08:57.460941 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 18:08:57.460992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 18:08:57.461043 ==
3509 18:08:57.461093 [Gating] SW mode calibration
3510 18:08:57.461145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3511 18:08:57.461196 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3512 18:08:57.461247 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 18:08:57.461299 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 18:08:57.461350 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 18:08:57.461401 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 18:08:57.461452 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 18:08:57.461503 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 18:08:57.461553 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 1)
3519 18:08:57.461604 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
3520 18:08:57.461655 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 18:08:57.461705 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 18:08:57.461756 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 18:08:57.461808 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 18:08:57.461858 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 18:08:57.461910 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 18:08:57.461960 1 0 24 | B1->B0 | 3f3f 2d2d | 0 0 | (0 0) (0 0)
3527 18:08:57.462011 1 0 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
3528 18:08:57.462062 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 18:08:57.462112 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 18:08:57.462162 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 18:08:57.462213 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 18:08:57.462264 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 18:08:57.462315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 18:08:57.462365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3535 18:08:57.462416 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3536 18:08:57.462466 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 18:08:57.462517 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 18:08:57.462567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 18:08:57.462618 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 18:08:57.462668 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 18:08:57.462718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 18:08:57.462769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 18:08:57.462819 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 18:08:57.462870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 18:08:57.462921 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 18:08:57.462971 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 18:08:57.463021 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 18:08:57.463072 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 18:08:57.463123 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 18:08:57.463173 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3551 18:08:57.463224 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3552 18:08:57.463275 Total UI for P1: 0, mck2ui 16
3553 18:08:57.463326 best dqsien dly found for B0: ( 1, 3, 24)
3554 18:08:57.463381 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 18:08:57.463481 Total UI for P1: 0, mck2ui 16
3556 18:08:57.463534 best dqsien dly found for B1: ( 1, 3, 26)
3557 18:08:57.463586 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3558 18:08:57.463637 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3559 18:08:57.463689
3560 18:08:57.463740 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3561 18:08:57.463792 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3562 18:08:57.463843 [Gating] SW calibration Done
3563 18:08:57.463894 ==
3564 18:08:57.463944 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 18:08:57.463995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 18:08:57.464046 ==
3567 18:08:57.464097 RX Vref Scan: 0
3568 18:08:57.464147
3569 18:08:57.464197 RX Vref 0 -> 0, step: 1
3570 18:08:57.464248
3571 18:08:57.464298 RX Delay -40 -> 252, step: 8
3572 18:08:57.464349 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3573 18:08:57.464400 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3574 18:08:57.464451 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3575 18:08:57.464502 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3576 18:08:57.464580 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3577 18:08:57.464647 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3578 18:08:57.464698 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3579 18:08:57.464749 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3580 18:08:57.464800 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3581 18:08:57.465042 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3582 18:08:57.465101 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3583 18:08:57.465153 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3584 18:08:57.465204 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3585 18:08:57.465255 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3586 18:08:57.465306 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3587 18:08:57.465357 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3588 18:08:57.465408 ==
3589 18:08:57.465459 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 18:08:57.465510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 18:08:57.465561 ==
3592 18:08:57.465612 DQS Delay:
3593 18:08:57.465663 DQS0 = 0, DQS1 = 0
3594 18:08:57.465714 DQM Delay:
3595 18:08:57.465765 DQM0 = 120, DQM1 = 112
3596 18:08:57.465815 DQ Delay:
3597 18:08:57.465866 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3598 18:08:57.465917 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3599 18:08:57.465969 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3600 18:08:57.466020 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3601 18:08:57.466071
3602 18:08:57.466121
3603 18:08:57.466171 ==
3604 18:08:57.466222 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 18:08:57.466273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 18:08:57.466324 ==
3607 18:08:57.466374
3608 18:08:57.466424
3609 18:08:57.466474 TX Vref Scan disable
3610 18:08:57.466524 == TX Byte 0 ==
3611 18:08:57.466579 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3612 18:08:57.466650 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3613 18:08:57.466703 == TX Byte 1 ==
3614 18:08:57.466754 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3615 18:08:57.466806 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3616 18:08:57.466857 ==
3617 18:08:57.466907 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 18:08:57.466958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 18:08:57.467010 ==
3620 18:08:57.467061 TX Vref=22, minBit 9, minWin=24, winSum=420
3621 18:08:57.467113 TX Vref=24, minBit 1, minWin=25, winSum=422
3622 18:08:57.467164 TX Vref=26, minBit 1, minWin=26, winSum=425
3623 18:08:57.467215 TX Vref=28, minBit 9, minWin=26, winSum=433
3624 18:08:57.467266 TX Vref=30, minBit 1, minWin=26, winSum=432
3625 18:08:57.467318 TX Vref=32, minBit 9, minWin=25, winSum=429
3626 18:08:57.467369 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3627 18:08:57.467420
3628 18:08:57.467470 Final TX Range 1 Vref 28
3629 18:08:57.467521
3630 18:08:57.467571 ==
3631 18:08:57.467622 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 18:08:57.467673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 18:08:57.467724 ==
3634 18:08:57.467775
3635 18:08:57.467824
3636 18:08:57.467875 TX Vref Scan disable
3637 18:08:57.467925 == TX Byte 0 ==
3638 18:08:57.467976 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3639 18:08:57.468027 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3640 18:08:57.468079 == TX Byte 1 ==
3641 18:08:57.468129 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3642 18:08:57.468180 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3643 18:08:57.468231
3644 18:08:57.468281 [DATLAT]
3645 18:08:57.468331 Freq=1200, CH1 RK1
3646 18:08:57.468382
3647 18:08:57.468448 DATLAT Default: 0xd
3648 18:08:57.468499 0, 0xFFFF, sum = 0
3649 18:08:57.468563 1, 0xFFFF, sum = 0
3650 18:08:57.468629 2, 0xFFFF, sum = 0
3651 18:08:57.468681 3, 0xFFFF, sum = 0
3652 18:08:57.468732 4, 0xFFFF, sum = 0
3653 18:08:57.468784 5, 0xFFFF, sum = 0
3654 18:08:57.468835 6, 0xFFFF, sum = 0
3655 18:08:57.468886 7, 0xFFFF, sum = 0
3656 18:08:57.468938 8, 0xFFFF, sum = 0
3657 18:08:57.468990 9, 0xFFFF, sum = 0
3658 18:08:57.469041 10, 0xFFFF, sum = 0
3659 18:08:57.469093 11, 0xFFFF, sum = 0
3660 18:08:57.469145 12, 0x0, sum = 1
3661 18:08:57.469196 13, 0x0, sum = 2
3662 18:08:57.469248 14, 0x0, sum = 3
3663 18:08:57.469298 15, 0x0, sum = 4
3664 18:08:57.469349 best_step = 13
3665 18:08:57.469399
3666 18:08:57.469463 ==
3667 18:08:57.469515 Dram Type= 6, Freq= 0, CH_1, rank 1
3668 18:08:57.469567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3669 18:08:57.469618 ==
3670 18:08:57.469669 RX Vref Scan: 0
3671 18:08:57.469720
3672 18:08:57.469796 RX Vref 0 -> 0, step: 1
3673 18:08:57.469852
3674 18:08:57.469904 RX Delay -13 -> 252, step: 4
3675 18:08:57.469956 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3676 18:08:57.470007 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3677 18:08:57.470062 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3678 18:08:57.470113 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3679 18:08:57.470164 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3680 18:08:57.470217 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3681 18:08:57.470268 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3682 18:08:57.470319 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3683 18:08:57.470372 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3684 18:08:57.470426 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3685 18:08:57.470477 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3686 18:08:57.470528 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3687 18:08:57.470579 iDelay=195, Bit 12, Center 120 (55 ~ 186) 132
3688 18:08:57.470632 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3689 18:08:57.470683 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3690 18:08:57.470734 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3691 18:08:57.470787 ==
3692 18:08:57.470838 Dram Type= 6, Freq= 0, CH_1, rank 1
3693 18:08:57.470889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3694 18:08:57.470940 ==
3695 18:08:57.470993 DQS Delay:
3696 18:08:57.471043 DQS0 = 0, DQS1 = 0
3697 18:08:57.471094 DQM Delay:
3698 18:08:57.471144 DQM0 = 119, DQM1 = 112
3699 18:08:57.471195 DQ Delay:
3700 18:08:57.471245 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3701 18:08:57.471296 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3702 18:08:57.471347 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3703 18:08:57.471398 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =120
3704 18:08:57.471449
3705 18:08:57.471499
3706 18:08:57.471549 [DQSOSCAuto] RK1, (LSB)MR18= 0x8ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 406 ps
3707 18:08:57.471601 CH1 RK1: MR19=403, MR18=8EC
3708 18:08:57.471651 CH1_RK1: MR19=0x403, MR18=0x8EC, DQSOSC=406, MR23=63, INC=39, DEC=26
3709 18:08:57.471703 [RxdqsGatingPostProcess] freq 1200
3710 18:08:57.471754 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3711 18:08:57.471805 best DQS0 dly(2T, 0.5T) = (0, 11)
3712 18:08:57.471856 best DQS1 dly(2T, 0.5T) = (0, 11)
3713 18:08:57.471907 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3714 18:08:57.471957 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3715 18:08:57.472008 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 18:08:57.472058 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 18:08:57.472109 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 18:08:57.472160 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 18:08:57.472210 Pre-setting of DQS Precalculation
3720 18:08:57.472455 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3721 18:08:57.472513 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3722 18:08:57.472587 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3723 18:08:57.472654
3724 18:08:57.472705
3725 18:08:57.472756 [Calibration Summary] 2400 Mbps
3726 18:08:57.472821 CH 0, Rank 0
3727 18:08:57.472881 SW Impedance : PASS
3728 18:08:57.472933 DUTY Scan : NO K
3729 18:08:57.472985 ZQ Calibration : PASS
3730 18:08:57.473036 Jitter Meter : NO K
3731 18:08:57.473087 CBT Training : PASS
3732 18:08:57.473137 Write leveling : PASS
3733 18:08:57.473189 RX DQS gating : PASS
3734 18:08:57.473239 RX DQ/DQS(RDDQC) : PASS
3735 18:08:57.473290 TX DQ/DQS : PASS
3736 18:08:57.473342 RX DATLAT : PASS
3737 18:08:57.473393 RX DQ/DQS(Engine): PASS
3738 18:08:57.473444 TX OE : NO K
3739 18:08:57.473495 All Pass.
3740 18:08:57.473545
3741 18:08:57.473595 CH 0, Rank 1
3742 18:08:57.473646 SW Impedance : PASS
3743 18:08:57.473696 DUTY Scan : NO K
3744 18:08:57.473747 ZQ Calibration : PASS
3745 18:08:57.473797 Jitter Meter : NO K
3746 18:08:57.473848 CBT Training : PASS
3747 18:08:57.473899 Write leveling : PASS
3748 18:08:57.473949 RX DQS gating : PASS
3749 18:08:57.474001 RX DQ/DQS(RDDQC) : PASS
3750 18:08:57.474051 TX DQ/DQS : PASS
3751 18:08:57.474102 RX DATLAT : PASS
3752 18:08:57.474153 RX DQ/DQS(Engine): PASS
3753 18:08:57.474203 TX OE : NO K
3754 18:08:57.474255 All Pass.
3755 18:08:57.474305
3756 18:08:57.474355 CH 1, Rank 0
3757 18:08:57.474406 SW Impedance : PASS
3758 18:08:57.474457 DUTY Scan : NO K
3759 18:08:57.474508 ZQ Calibration : PASS
3760 18:08:57.474558 Jitter Meter : NO K
3761 18:08:57.474608 CBT Training : PASS
3762 18:08:57.474659 Write leveling : PASS
3763 18:08:57.474709 RX DQS gating : PASS
3764 18:08:57.474761 RX DQ/DQS(RDDQC) : PASS
3765 18:08:57.474811 TX DQ/DQS : PASS
3766 18:08:57.474862 RX DATLAT : PASS
3767 18:08:57.474913 RX DQ/DQS(Engine): PASS
3768 18:08:57.474963 TX OE : NO K
3769 18:08:57.475014 All Pass.
3770 18:08:57.475065
3771 18:08:57.475115 CH 1, Rank 1
3772 18:08:57.475166 SW Impedance : PASS
3773 18:08:57.475216 DUTY Scan : NO K
3774 18:08:57.475267 ZQ Calibration : PASS
3775 18:08:57.475317 Jitter Meter : NO K
3776 18:08:57.475368 CBT Training : PASS
3777 18:08:57.475419 Write leveling : PASS
3778 18:08:57.475469 RX DQS gating : PASS
3779 18:08:57.475520 RX DQ/DQS(RDDQC) : PASS
3780 18:08:57.475571 TX DQ/DQS : PASS
3781 18:08:57.475621 RX DATLAT : PASS
3782 18:08:57.475672 RX DQ/DQS(Engine): PASS
3783 18:08:57.475722 TX OE : NO K
3784 18:08:57.475773 All Pass.
3785 18:08:57.475823
3786 18:08:57.475873 DramC Write-DBI off
3787 18:08:57.475923 PER_BANK_REFRESH: Hybrid Mode
3788 18:08:57.475974 TX_TRACKING: ON
3789 18:08:57.476042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3790 18:08:57.476107 [FAST_K] Save calibration result to emmc
3791 18:08:57.476158 dramc_set_vcore_voltage set vcore to 650000
3792 18:08:57.476208 Read voltage for 600, 5
3793 18:08:57.476259 Vio18 = 0
3794 18:08:57.476310 Vcore = 650000
3795 18:08:57.476365 Vdram = 0
3796 18:08:57.476435 Vddq = 0
3797 18:08:57.476487 Vmddr = 0
3798 18:08:57.476537 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3799 18:08:57.476629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3800 18:08:57.476681 MEM_TYPE=3, freq_sel=19
3801 18:08:57.476732 sv_algorithm_assistance_LP4_1600
3802 18:08:57.476783 ============ PULL DRAM RESETB DOWN ============
3803 18:08:57.476835 ========== PULL DRAM RESETB DOWN end =========
3804 18:08:57.476885 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3805 18:08:57.476937 ===================================
3806 18:08:57.476989 LPDDR4 DRAM CONFIGURATION
3807 18:08:57.477039 ===================================
3808 18:08:57.477090 EX_ROW_EN[0] = 0x0
3809 18:08:57.477141 EX_ROW_EN[1] = 0x0
3810 18:08:57.477192 LP4Y_EN = 0x0
3811 18:08:57.477242 WORK_FSP = 0x0
3812 18:08:57.477293 WL = 0x2
3813 18:08:57.477343 RL = 0x2
3814 18:08:57.477393 BL = 0x2
3815 18:08:57.477475 RPST = 0x0
3816 18:08:57.477526 RD_PRE = 0x0
3817 18:08:57.477576 WR_PRE = 0x1
3818 18:08:57.477627 WR_PST = 0x0
3819 18:08:57.477677 DBI_WR = 0x0
3820 18:08:57.477728 DBI_RD = 0x0
3821 18:08:57.477778 OTF = 0x1
3822 18:08:57.477829 ===================================
3823 18:08:57.477880 ===================================
3824 18:08:57.477931 ANA top config
3825 18:08:57.477981 ===================================
3826 18:08:57.478032 DLL_ASYNC_EN = 0
3827 18:08:57.478083 ALL_SLAVE_EN = 1
3828 18:08:57.478133 NEW_RANK_MODE = 1
3829 18:08:57.478185 DLL_IDLE_MODE = 1
3830 18:08:57.478235 LP45_APHY_COMB_EN = 1
3831 18:08:57.478285 TX_ODT_DIS = 1
3832 18:08:57.478336 NEW_8X_MODE = 1
3833 18:08:57.478387 ===================================
3834 18:08:57.478437 ===================================
3835 18:08:57.478488 data_rate = 1200
3836 18:08:57.478539 CKR = 1
3837 18:08:57.478590 DQ_P2S_RATIO = 8
3838 18:08:57.478641 ===================================
3839 18:08:57.478691 CA_P2S_RATIO = 8
3840 18:08:57.478742 DQ_CA_OPEN = 0
3841 18:08:57.478793 DQ_SEMI_OPEN = 0
3842 18:08:57.478843 CA_SEMI_OPEN = 0
3843 18:08:57.478893 CA_FULL_RATE = 0
3844 18:08:57.478944 DQ_CKDIV4_EN = 1
3845 18:08:57.478994 CA_CKDIV4_EN = 1
3846 18:08:57.479045 CA_PREDIV_EN = 0
3847 18:08:57.479112 PH8_DLY = 0
3848 18:08:57.479190 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3849 18:08:57.479317 DQ_AAMCK_DIV = 4
3850 18:08:57.479372 CA_AAMCK_DIV = 4
3851 18:08:57.479447 CA_ADMCK_DIV = 4
3852 18:08:57.479512 DQ_TRACK_CA_EN = 0
3853 18:08:57.479595 CA_PICK = 600
3854 18:08:57.479650 CA_MCKIO = 600
3855 18:08:57.479702 MCKIO_SEMI = 0
3856 18:08:57.479753 PLL_FREQ = 2288
3857 18:08:57.479804 DQ_UI_PI_RATIO = 32
3858 18:08:57.479855 CA_UI_PI_RATIO = 0
3859 18:08:57.479906 ===================================
3860 18:08:57.479957 ===================================
3861 18:08:57.480008 memory_type:LPDDR4
3862 18:08:57.480059 GP_NUM : 10
3863 18:08:57.480110 SRAM_EN : 1
3864 18:08:57.480161 MD32_EN : 0
3865 18:08:57.480212 ===================================
3866 18:08:57.480263 [ANA_INIT] >>>>>>>>>>>>>>
3867 18:08:57.480314 <<<<<< [CONFIGURE PHASE]: ANA_TX
3868 18:08:57.480585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3869 18:08:57.480700 ===================================
3870 18:08:57.480794 data_rate = 1200,PCW = 0X5800
3871 18:08:57.480888 ===================================
3872 18:08:57.480981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3873 18:08:57.481077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3874 18:08:57.481171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3875 18:08:57.481264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3876 18:08:57.481358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3877 18:08:57.481451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3878 18:08:57.481544 [ANA_INIT] flow start
3879 18:08:57.481637 [ANA_INIT] PLL >>>>>>>>
3880 18:08:57.481729 [ANA_INIT] PLL <<<<<<<<
3881 18:08:57.481822 [ANA_INIT] MIDPI >>>>>>>>
3882 18:08:57.481914 [ANA_INIT] MIDPI <<<<<<<<
3883 18:08:57.482007 [ANA_INIT] DLL >>>>>>>>
3884 18:08:57.482098 [ANA_INIT] flow end
3885 18:08:57.482192 ============ LP4 DIFF to SE enter ============
3886 18:08:57.482285 ============ LP4 DIFF to SE exit ============
3887 18:08:57.482375 [ANA_INIT] <<<<<<<<<<<<<
3888 18:08:57.482464 [Flow] Enable top DCM control >>>>>
3889 18:08:57.482556 [Flow] Enable top DCM control <<<<<
3890 18:08:57.482646 Enable DLL master slave shuffle
3891 18:08:57.482736 ==============================================================
3892 18:08:57.482825 Gating Mode config
3893 18:08:57.482914 ==============================================================
3894 18:08:57.482970 Config description:
3895 18:08:57.483022 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3896 18:08:57.483075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3897 18:08:57.483128 SELPH_MODE 0: By rank 1: By Phase
3898 18:08:57.483180 ==============================================================
3899 18:08:57.483231 GAT_TRACK_EN = 1
3900 18:08:57.483282 RX_GATING_MODE = 2
3901 18:08:57.483333 RX_GATING_TRACK_MODE = 2
3902 18:08:57.483384 SELPH_MODE = 1
3903 18:08:57.483435 PICG_EARLY_EN = 1
3904 18:08:57.483486 VALID_LAT_VALUE = 1
3905 18:08:57.483536 ==============================================================
3906 18:08:57.483588 Enter into Gating configuration >>>>
3907 18:08:57.483639 Exit from Gating configuration <<<<
3908 18:08:57.483690 Enter into DVFS_PRE_config >>>>>
3909 18:08:57.483741 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3910 18:08:57.483793 Exit from DVFS_PRE_config <<<<<
3911 18:08:57.483844 Enter into PICG configuration >>>>
3912 18:08:57.483895 Exit from PICG configuration <<<<
3913 18:08:57.483946 [RX_INPUT] configuration >>>>>
3914 18:08:57.483997 [RX_INPUT] configuration <<<<<
3915 18:08:57.484047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3916 18:08:57.484098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3917 18:08:57.484149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3918 18:08:57.484200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3919 18:08:57.484252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3920 18:08:57.484303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3921 18:08:57.484354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3922 18:08:57.484405 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3923 18:08:57.484456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3924 18:08:57.484507 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3925 18:08:57.484598 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3926 18:08:57.484666 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 18:08:57.484718 ===================================
3928 18:08:57.484769 LPDDR4 DRAM CONFIGURATION
3929 18:08:57.484819 ===================================
3930 18:08:57.484879 EX_ROW_EN[0] = 0x0
3931 18:08:57.484937 EX_ROW_EN[1] = 0x0
3932 18:08:57.484988 LP4Y_EN = 0x0
3933 18:08:57.485039 WORK_FSP = 0x0
3934 18:08:57.485090 WL = 0x2
3935 18:08:57.485140 RL = 0x2
3936 18:08:57.485191 BL = 0x2
3937 18:08:57.485241 RPST = 0x0
3938 18:08:57.485292 RD_PRE = 0x0
3939 18:08:57.485342 WR_PRE = 0x1
3940 18:08:57.485393 WR_PST = 0x0
3941 18:08:57.485443 DBI_WR = 0x0
3942 18:08:57.485494 DBI_RD = 0x0
3943 18:08:57.485545 OTF = 0x1
3944 18:08:57.485596 ===================================
3945 18:08:57.485647 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3946 18:08:57.485698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3947 18:08:57.485749 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3948 18:08:57.485799 ===================================
3949 18:08:57.485850 LPDDR4 DRAM CONFIGURATION
3950 18:08:57.485901 ===================================
3951 18:08:57.485952 EX_ROW_EN[0] = 0x10
3952 18:08:57.486016 EX_ROW_EN[1] = 0x0
3953 18:08:57.486265 LP4Y_EN = 0x0
3954 18:08:57.486327 WORK_FSP = 0x0
3955 18:08:57.489459 WL = 0x2
3956 18:08:57.489538 RL = 0x2
3957 18:08:57.493214 BL = 0x2
3958 18:08:57.493294 RPST = 0x0
3959 18:08:57.496357 RD_PRE = 0x0
3960 18:08:57.496435 WR_PRE = 0x1
3961 18:08:57.499594 WR_PST = 0x0
3962 18:08:57.499672 DBI_WR = 0x0
3963 18:08:57.502820 DBI_RD = 0x0
3964 18:08:57.502899 OTF = 0x1
3965 18:08:57.506028 ===================================
3966 18:08:57.512968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3967 18:08:57.517295 nWR fixed to 30
3968 18:08:57.520505 [ModeRegInit_LP4] CH0 RK0
3969 18:08:57.520632 [ModeRegInit_LP4] CH0 RK1
3970 18:08:57.523733 [ModeRegInit_LP4] CH1 RK0
3971 18:08:57.526810 [ModeRegInit_LP4] CH1 RK1
3972 18:08:57.526889 match AC timing 17
3973 18:08:57.533825 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3974 18:08:57.536983 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3975 18:08:57.540458 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3976 18:08:57.546907 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3977 18:08:57.550044 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3978 18:08:57.550123 ==
3979 18:08:57.553839 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 18:08:57.556939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 18:08:57.557030 ==
3982 18:08:57.563679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 18:08:57.570429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3984 18:08:57.573668 [CA 0] Center 36 (6~67) winsize 62
3985 18:08:57.576698 [CA 1] Center 36 (6~67) winsize 62
3986 18:08:57.580349 [CA 2] Center 34 (4~65) winsize 62
3987 18:08:57.583495 [CA 3] Center 34 (3~65) winsize 63
3988 18:08:57.586721 [CA 4] Center 33 (3~64) winsize 62
3989 18:08:57.590015 [CA 5] Center 33 (3~64) winsize 62
3990 18:08:57.590094
3991 18:08:57.593386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3992 18:08:57.593466
3993 18:08:57.596437 [CATrainingPosCal] consider 1 rank data
3994 18:08:57.600187 u2DelayCellTimex100 = 270/100 ps
3995 18:08:57.603478 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 18:08:57.606705 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3997 18:08:57.690891 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 18:08:57.691015 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3999 18:08:57.691081 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 18:08:57.691141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 18:08:57.691199
4002 18:08:57.691255 CA PerBit enable=1, Macro0, CA PI delay=33
4003 18:08:57.691310
4004 18:08:57.691363 [CBTSetCACLKResult] CA Dly = 33
4005 18:08:57.691417 CS Dly: 5 (0~36)
4006 18:08:57.691471 ==
4007 18:08:57.691526 Dram Type= 6, Freq= 0, CH_0, rank 1
4008 18:08:57.691579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 18:08:57.691655 ==
4010 18:08:57.691730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4011 18:08:57.691785 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4012 18:08:57.691839 [CA 0] Center 36 (6~67) winsize 62
4013 18:08:57.691892 [CA 1] Center 36 (6~67) winsize 62
4014 18:08:57.691945 [CA 2] Center 35 (5~66) winsize 62
4015 18:08:57.691997 [CA 3] Center 35 (4~66) winsize 63
4016 18:08:57.692050 [CA 4] Center 34 (3~65) winsize 63
4017 18:08:57.692102 [CA 5] Center 34 (3~65) winsize 63
4018 18:08:57.692153
4019 18:08:57.692205 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4020 18:08:57.692258
4021 18:08:57.692309 [CATrainingPosCal] consider 2 rank data
4022 18:08:57.692374 u2DelayCellTimex100 = 270/100 ps
4023 18:08:57.692458 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4024 18:08:57.692540 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4025 18:08:57.692645 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4026 18:08:57.695916 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4027 18:08:57.699224 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4028 18:08:57.702561 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4029 18:08:57.702712
4030 18:08:57.705847 CA PerBit enable=1, Macro0, CA PI delay=33
4031 18:08:57.705929
4032 18:08:57.709152 [CBTSetCACLKResult] CA Dly = 33
4033 18:08:57.709254 CS Dly: 5 (0~37)
4034 18:08:57.709334
4035 18:08:57.712370 ----->DramcWriteLeveling(PI) begin...
4036 18:08:57.712453 ==
4037 18:08:57.716059 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 18:08:57.722542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 18:08:57.722625 ==
4040 18:08:57.725756 Write leveling (Byte 0): 35 => 35
4041 18:08:57.729430 Write leveling (Byte 1): 31 => 31
4042 18:08:57.729512 DramcWriteLeveling(PI) end<-----
4043 18:08:57.732728
4044 18:08:57.732809 ==
4045 18:08:57.735726 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 18:08:57.738938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 18:08:57.739021 ==
4048 18:08:57.742575 [Gating] SW mode calibration
4049 18:08:57.748828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4050 18:08:57.752753 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4051 18:08:57.759258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 18:08:57.762334 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4053 18:08:57.765916 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 18:08:57.772154 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4055 18:08:57.775808 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
4056 18:08:57.779172 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 18:08:57.785448 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 18:08:57.789125 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 18:08:57.792278 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 18:08:57.798843 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 18:08:57.801934 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4062 18:08:57.805649 0 10 12 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
4063 18:08:57.812187 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
4064 18:08:57.815522 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 18:08:57.818867 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 18:08:57.825396 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 18:08:57.828695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 18:08:57.831814 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 18:08:57.838837 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 18:08:57.842072 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4071 18:08:57.845197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 18:08:57.851931 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 18:08:57.855152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 18:08:57.858500 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 18:08:57.864985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 18:08:57.868674 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 18:08:57.871967 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 18:08:57.878528 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 18:08:57.881688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 18:08:57.884895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 18:08:57.891931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 18:08:57.895007 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 18:08:57.898209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 18:08:57.904665 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 18:08:57.908308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 18:08:57.911643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4087 18:08:57.914862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4088 18:08:57.918097 Total UI for P1: 0, mck2ui 16
4089 18:08:57.921412 best dqsien dly found for B0: ( 0, 13, 12)
4090 18:08:57.928035 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 18:08:57.931702 Total UI for P1: 0, mck2ui 16
4092 18:08:57.934936 best dqsien dly found for B1: ( 0, 13, 16)
4093 18:08:57.938251 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4094 18:08:57.941416 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4095 18:08:57.941498
4096 18:08:57.944480 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4097 18:08:57.948242 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4098 18:08:57.951467 [Gating] SW calibration Done
4099 18:08:57.951549 ==
4100 18:08:57.954677 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 18:08:57.957877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 18:08:57.957960 ==
4103 18:08:57.961053 RX Vref Scan: 0
4104 18:08:57.961134
4105 18:08:57.964211 RX Vref 0 -> 0, step: 1
4106 18:08:57.964292
4107 18:08:57.964357 RX Delay -230 -> 252, step: 16
4108 18:08:57.971080 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4109 18:08:57.974292 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4110 18:08:57.977886 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4111 18:08:57.981185 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4112 18:08:57.987589 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4113 18:08:57.991392 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4114 18:08:57.994570 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4115 18:08:57.997830 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4116 18:08:58.001002 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4117 18:08:58.008060 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4118 18:08:58.011407 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4119 18:08:58.014627 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4120 18:08:58.017732 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4121 18:08:58.024157 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4122 18:08:58.027359 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4123 18:08:58.031125 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4124 18:08:58.031208 ==
4125 18:08:58.034366 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 18:08:58.037581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 18:08:58.040751 ==
4128 18:08:58.040834 DQS Delay:
4129 18:08:58.040899 DQS0 = 0, DQS1 = 0
4130 18:08:58.044069 DQM Delay:
4131 18:08:58.044153 DQM0 = 52, DQM1 = 39
4132 18:08:58.047326 DQ Delay:
4133 18:08:58.047409 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4134 18:08:58.050947 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4135 18:08:58.054980 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4136 18:08:58.057666 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4137 18:08:58.057749
4138 18:08:58.060679
4139 18:08:58.060761 ==
4140 18:08:58.063986 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 18:08:58.067280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 18:08:58.067364 ==
4143 18:08:58.067429
4144 18:08:58.067488
4145 18:08:58.070577 TX Vref Scan disable
4146 18:08:58.070660 == TX Byte 0 ==
4147 18:08:58.077354 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4148 18:08:58.081043 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4149 18:08:58.081126 == TX Byte 1 ==
4150 18:08:58.087328 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4151 18:08:58.091164 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4152 18:08:58.091248 ==
4153 18:08:58.093829 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 18:08:58.097567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 18:08:58.097650 ==
4156 18:08:58.097715
4157 18:08:58.097774
4158 18:08:58.100799 TX Vref Scan disable
4159 18:08:58.103927 == TX Byte 0 ==
4160 18:08:58.107209 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4161 18:08:58.110413 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4162 18:08:58.113790 == TX Byte 1 ==
4163 18:08:58.117627 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4164 18:08:58.120320 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4165 18:08:58.124084
4166 18:08:58.124170 [DATLAT]
4167 18:08:58.124237 Freq=600, CH0 RK0
4168 18:08:58.124299
4169 18:08:58.127315 DATLAT Default: 0x9
4170 18:08:58.127396 0, 0xFFFF, sum = 0
4171 18:08:58.130649 1, 0xFFFF, sum = 0
4172 18:08:58.130733 2, 0xFFFF, sum = 0
4173 18:08:58.133771 3, 0xFFFF, sum = 0
4174 18:08:58.133855 4, 0xFFFF, sum = 0
4175 18:08:58.136980 5, 0xFFFF, sum = 0
4176 18:08:58.137065 6, 0xFFFF, sum = 0
4177 18:08:58.140277 7, 0xFFFF, sum = 0
4178 18:08:58.140389 8, 0x0, sum = 1
4179 18:08:58.144029 9, 0x0, sum = 2
4180 18:08:58.144112 10, 0x0, sum = 3
4181 18:08:58.147298 11, 0x0, sum = 4
4182 18:08:58.147381 best_step = 9
4183 18:08:58.147447
4184 18:08:58.147506 ==
4185 18:08:58.150521 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 18:08:58.157280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 18:08:58.157367 ==
4188 18:08:58.157432 RX Vref Scan: 1
4189 18:08:58.157492
4190 18:08:58.160454 RX Vref 0 -> 0, step: 1
4191 18:08:58.160569
4192 18:08:58.163617 RX Delay -163 -> 252, step: 8
4193 18:08:58.163700
4194 18:08:58.166839 Set Vref, RX VrefLevel [Byte0]: 59
4195 18:08:58.170096 [Byte1]: 48
4196 18:08:58.170177
4197 18:08:58.173923 Final RX Vref Byte 0 = 59 to rank0
4198 18:08:58.177099 Final RX Vref Byte 1 = 48 to rank0
4199 18:08:58.179988 Final RX Vref Byte 0 = 59 to rank1
4200 18:08:58.183805 Final RX Vref Byte 1 = 48 to rank1==
4201 18:08:58.186814 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 18:08:58.190009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 18:08:58.190092 ==
4204 18:08:58.193733 DQS Delay:
4205 18:08:58.193814 DQS0 = 0, DQS1 = 0
4206 18:08:58.193890 DQM Delay:
4207 18:08:58.197011 DQM0 = 48, DQM1 = 38
4208 18:08:58.197093 DQ Delay:
4209 18:08:58.200247 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4210 18:08:58.203425 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4211 18:08:58.206656 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4212 18:08:58.210210 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =44
4213 18:08:58.210310
4214 18:08:58.210400
4215 18:08:58.220363 [DQSOSCAuto] RK0, (LSB)MR18= 0x5851, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4216 18:08:58.220486 CH0 RK0: MR19=808, MR18=5851
4217 18:08:58.226937 CH0_RK0: MR19=0x808, MR18=0x5851, DQSOSC=393, MR23=63, INC=169, DEC=113
4218 18:08:58.227020
4219 18:08:58.230177 ----->DramcWriteLeveling(PI) begin...
4220 18:08:58.233462 ==
4221 18:08:58.236656 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 18:08:58.239872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 18:08:58.239979 ==
4224 18:08:58.243742 Write leveling (Byte 0): 35 => 35
4225 18:08:58.246910 Write leveling (Byte 1): 31 => 31
4226 18:08:58.250075 DramcWriteLeveling(PI) end<-----
4227 18:08:58.250177
4228 18:08:58.250267 ==
4229 18:08:58.253384 Dram Type= 6, Freq= 0, CH_0, rank 1
4230 18:08:58.256640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4231 18:08:58.256713 ==
4232 18:08:58.259873 [Gating] SW mode calibration
4233 18:08:58.266773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 18:08:58.270032 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4235 18:08:58.276433 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 18:08:58.280123 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4237 18:08:58.283258 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4238 18:08:58.289942 0 9 12 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
4239 18:08:58.292979 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
4240 18:08:58.296582 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 18:08:58.303005 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 18:08:58.306275 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 18:08:58.309524 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 18:08:58.316376 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 18:08:58.319616 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 18:08:58.322842 0 10 12 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
4247 18:08:58.329626 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4248 18:08:58.332833 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 18:08:58.336181 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 18:08:58.343101 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 18:08:58.346479 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 18:08:58.349748 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 18:08:58.356215 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 18:08:58.359420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4255 18:08:58.362613 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 18:08:58.369444 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 18:08:58.372819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 18:08:58.376346 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 18:08:58.382847 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 18:08:58.386004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 18:08:58.389276 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 18:08:58.396093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 18:08:58.399315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 18:08:58.402570 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 18:08:58.409190 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 18:08:58.412397 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 18:08:58.416185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 18:08:58.422412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 18:08:58.425747 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 18:08:58.429006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4271 18:08:58.435613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 18:08:58.435697 Total UI for P1: 0, mck2ui 16
4273 18:08:58.439336 best dqsien dly found for B0: ( 0, 13, 14)
4274 18:08:58.442602 Total UI for P1: 0, mck2ui 16
4275 18:08:58.445811 best dqsien dly found for B1: ( 0, 13, 12)
4276 18:08:58.449019 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4277 18:08:58.455589 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4278 18:08:58.455672
4279 18:08:58.459017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 18:08:58.462215 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4281 18:08:58.466058 [Gating] SW calibration Done
4282 18:08:58.466141 ==
4283 18:08:58.469118 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 18:08:58.472403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 18:08:58.472516 ==
4286 18:08:58.475433 RX Vref Scan: 0
4287 18:08:58.475515
4288 18:08:58.475580 RX Vref 0 -> 0, step: 1
4289 18:08:58.475641
4290 18:08:58.478705 RX Delay -230 -> 252, step: 16
4291 18:08:58.481996 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4292 18:08:58.488968 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4293 18:08:58.492046 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4294 18:08:58.495651 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4295 18:08:58.498785 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4296 18:08:58.502459 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4297 18:08:58.508632 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4298 18:08:58.511934 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4299 18:08:58.515698 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4300 18:08:58.518991 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4301 18:08:58.525191 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4302 18:08:58.528379 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4303 18:08:58.532088 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4304 18:08:58.535465 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4305 18:08:58.541991 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4306 18:08:58.545226 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4307 18:08:58.545309 ==
4308 18:08:58.548542 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 18:08:58.551785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 18:08:58.551869 ==
4311 18:08:58.555125 DQS Delay:
4312 18:08:58.555207 DQS0 = 0, DQS1 = 0
4313 18:08:58.555273 DQM Delay:
4314 18:08:58.558410 DQM0 = 47, DQM1 = 42
4315 18:08:58.558493 DQ Delay:
4316 18:08:58.561535 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4317 18:08:58.564855 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4318 18:08:58.568238 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4319 18:08:58.571905 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4320 18:08:58.571988
4321 18:08:58.572053
4322 18:08:58.572113 ==
4323 18:08:58.575085 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 18:08:58.581278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 18:08:58.581360 ==
4326 18:08:58.581425
4327 18:08:58.581484
4328 18:08:58.581541 TX Vref Scan disable
4329 18:08:58.585653 == TX Byte 0 ==
4330 18:08:58.588954 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4331 18:08:58.595398 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4332 18:08:58.595479 == TX Byte 1 ==
4333 18:08:58.598565 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4334 18:08:58.605140 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4335 18:08:58.605221 ==
4336 18:08:58.608716 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 18:08:58.611962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 18:08:58.612044 ==
4339 18:08:58.612108
4340 18:08:58.612167
4341 18:08:58.615204 TX Vref Scan disable
4342 18:08:58.618413 == TX Byte 0 ==
4343 18:08:58.621947 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4344 18:08:58.625009 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4345 18:08:58.628536 == TX Byte 1 ==
4346 18:08:58.631848 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4347 18:08:58.635094 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4348 18:08:58.635206
4349 18:08:58.635272 [DATLAT]
4350 18:08:58.638561 Freq=600, CH0 RK1
4351 18:08:58.638647
4352 18:08:58.641869 DATLAT Default: 0x9
4353 18:08:58.641981 0, 0xFFFF, sum = 0
4354 18:08:58.645177 1, 0xFFFF, sum = 0
4355 18:08:58.645259 2, 0xFFFF, sum = 0
4356 18:08:58.648459 3, 0xFFFF, sum = 0
4357 18:08:58.648605 4, 0xFFFF, sum = 0
4358 18:08:58.651807 5, 0xFFFF, sum = 0
4359 18:08:58.651889 6, 0xFFFF, sum = 0
4360 18:08:58.654929 7, 0xFFFF, sum = 0
4361 18:08:58.655034 8, 0x0, sum = 1
4362 18:08:58.658632 9, 0x0, sum = 2
4363 18:08:58.658712 10, 0x0, sum = 3
4364 18:08:58.658776 11, 0x0, sum = 4
4365 18:08:58.662128 best_step = 9
4366 18:08:58.662207
4367 18:08:58.662269 ==
4368 18:08:58.665259 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 18:08:58.668429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 18:08:58.668627 ==
4371 18:08:58.671591 RX Vref Scan: 0
4372 18:08:58.671723
4373 18:08:58.671802 RX Vref 0 -> 0, step: 1
4374 18:08:58.674906
4375 18:08:58.675044 RX Delay -179 -> 252, step: 8
4376 18:08:58.683018 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4377 18:08:58.685980 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4378 18:08:58.689274 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4379 18:08:58.692477 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4380 18:08:58.695793 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4381 18:08:58.702670 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4382 18:08:58.705702 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4383 18:08:58.709362 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4384 18:08:58.712526 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4385 18:08:58.718931 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4386 18:08:58.722718 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4387 18:08:58.726076 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4388 18:08:58.729028 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4389 18:08:58.735886 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4390 18:08:58.739146 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4391 18:08:58.742489 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4392 18:08:58.742944 ==
4393 18:08:58.745701 Dram Type= 6, Freq= 0, CH_0, rank 1
4394 18:08:58.748917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 18:08:58.749603 ==
4396 18:08:58.752680 DQS Delay:
4397 18:08:58.753225 DQS0 = 0, DQS1 = 0
4398 18:08:58.755951 DQM Delay:
4399 18:08:58.756398 DQM0 = 48, DQM1 = 40
4400 18:08:58.756812 DQ Delay:
4401 18:08:58.759212 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4402 18:08:58.762357 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4403 18:08:58.765633 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4404 18:08:58.768975 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =44
4405 18:08:58.769429
4406 18:08:58.769784
4407 18:08:58.779253 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4408 18:08:58.782450 CH0 RK1: MR19=808, MR18=6532
4409 18:08:58.785819 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4410 18:08:58.789131 [RxdqsGatingPostProcess] freq 600
4411 18:08:58.795587 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4412 18:08:58.798892 Pre-setting of DQS Precalculation
4413 18:08:58.802148 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4414 18:08:58.802562 ==
4415 18:08:58.805867 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 18:08:58.812537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 18:08:58.813024 ==
4418 18:08:58.815660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 18:08:58.822431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4420 18:08:58.825726 [CA 0] Center 35 (5~66) winsize 62
4421 18:08:58.828896 [CA 1] Center 35 (5~66) winsize 62
4422 18:08:58.832462 [CA 2] Center 34 (4~65) winsize 62
4423 18:08:58.835634 [CA 3] Center 34 (4~65) winsize 62
4424 18:08:58.838867 [CA 4] Center 34 (3~65) winsize 63
4425 18:08:58.842055 [CA 5] Center 34 (3~65) winsize 63
4426 18:08:58.842511
4427 18:08:58.845295 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4428 18:08:58.845750
4429 18:08:58.849043 [CATrainingPosCal] consider 1 rank data
4430 18:08:58.852216 u2DelayCellTimex100 = 270/100 ps
4431 18:08:58.855485 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4432 18:08:58.859032 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4433 18:08:58.865262 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4434 18:08:58.868443 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4435 18:08:58.871805 CA4 delay=34 (3~65),Diff = 0 PI (0 cell)
4436 18:08:58.875613 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4437 18:08:58.876027
4438 18:08:58.878836 CA PerBit enable=1, Macro0, CA PI delay=34
4439 18:08:58.879248
4440 18:08:58.882076 [CBTSetCACLKResult] CA Dly = 34
4441 18:08:58.882491 CS Dly: 4 (0~35)
4442 18:08:58.885260 ==
4443 18:08:58.885674 Dram Type= 6, Freq= 0, CH_1, rank 1
4444 18:08:58.892060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 18:08:58.892476 ==
4446 18:08:58.895148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4447 18:08:58.901906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4448 18:08:58.905570 [CA 0] Center 35 (5~66) winsize 62
4449 18:08:58.908882 [CA 1] Center 35 (5~66) winsize 62
4450 18:08:58.912155 [CA 2] Center 34 (4~65) winsize 62
4451 18:08:58.915270 [CA 3] Center 34 (4~65) winsize 62
4452 18:08:58.918843 [CA 4] Center 34 (4~65) winsize 62
4453 18:08:58.921887 [CA 5] Center 33 (3~64) winsize 62
4454 18:08:58.922309
4455 18:08:58.925566 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4456 18:08:58.926028
4457 18:08:58.928874 [CATrainingPosCal] consider 2 rank data
4458 18:08:58.932050 u2DelayCellTimex100 = 270/100 ps
4459 18:08:58.935614 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4460 18:08:58.942311 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4461 18:08:58.945417 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 18:08:58.948622 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 18:08:58.952306 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 18:08:58.955380 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4465 18:08:58.955839
4466 18:08:58.958620 CA PerBit enable=1, Macro0, CA PI delay=33
4467 18:08:58.959078
4468 18:08:58.961911 [CBTSetCACLKResult] CA Dly = 33
4469 18:08:58.962369 CS Dly: 5 (0~37)
4470 18:08:58.962732
4471 18:08:58.968399 ----->DramcWriteLeveling(PI) begin...
4472 18:08:58.968901 ==
4473 18:08:58.972046 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 18:08:58.975302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 18:08:58.975762 ==
4476 18:08:58.978559 Write leveling (Byte 0): 28 => 28
4477 18:08:58.981696 Write leveling (Byte 1): 29 => 29
4478 18:08:58.984948 DramcWriteLeveling(PI) end<-----
4479 18:08:58.985405
4480 18:08:58.985760 ==
4481 18:08:58.988342 Dram Type= 6, Freq= 0, CH_1, rank 0
4482 18:08:58.991619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 18:08:58.992081 ==
4484 18:08:58.995213 [Gating] SW mode calibration
4485 18:08:59.001632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4486 18:08:59.008081 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4487 18:08:59.011938 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 18:08:59.015191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 18:08:59.021316 0 9 8 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
4490 18:08:59.025028 0 9 12 | B1->B0 | 2b2b 2c2c | 0 0 | (0 0) (1 1)
4491 18:08:59.028110 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 18:08:59.034652 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 18:08:59.037850 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 18:08:59.041513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 18:08:59.048445 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 18:08:59.051659 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 18:08:59.054812 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4498 18:08:59.058043 0 10 12 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (1 1)
4499 18:08:59.064617 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 18:08:59.067932 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 18:08:59.071174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 18:08:59.077764 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 18:08:59.081013 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 18:08:59.084267 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 18:08:59.091299 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 18:08:59.094564 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4507 18:08:59.097746 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 18:08:59.104181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 18:08:59.107885 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 18:08:59.111073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 18:08:59.117435 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 18:08:59.121330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 18:08:59.124367 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 18:08:59.131047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 18:08:59.134263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 18:08:59.137475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 18:08:59.144102 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 18:08:59.147706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 18:08:59.150997 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 18:08:59.157834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 18:08:59.160978 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 18:08:59.164196 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4523 18:08:59.167949 Total UI for P1: 0, mck2ui 16
4524 18:08:59.171056 best dqsien dly found for B0: ( 0, 13, 10)
4525 18:08:59.177543 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 18:08:59.178042 Total UI for P1: 0, mck2ui 16
4527 18:08:59.180802 best dqsien dly found for B1: ( 0, 13, 12)
4528 18:08:59.187452 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4529 18:08:59.190543 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4530 18:08:59.190961
4531 18:08:59.193906 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4532 18:08:59.197210 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4533 18:08:59.200826 [Gating] SW calibration Done
4534 18:08:59.201240 ==
4535 18:08:59.203990 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 18:08:59.207293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 18:08:59.207711 ==
4538 18:08:59.210644 RX Vref Scan: 0
4539 18:08:59.211056
4540 18:08:59.211385 RX Vref 0 -> 0, step: 1
4541 18:08:59.211690
4542 18:08:59.213794 RX Delay -230 -> 252, step: 16
4543 18:08:59.217546 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4544 18:08:59.224036 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4545 18:08:59.227026 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4546 18:08:59.230669 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4547 18:08:59.233763 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4548 18:08:59.240523 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4549 18:08:59.243843 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4550 18:08:59.247144 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4551 18:08:59.250404 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4552 18:08:59.254112 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4553 18:08:59.260516 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4554 18:08:59.263632 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4555 18:08:59.266841 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4556 18:08:59.270231 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4557 18:08:59.277054 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4558 18:08:59.280303 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4559 18:08:59.280812 ==
4560 18:08:59.283488 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 18:08:59.286741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 18:08:59.287206 ==
4563 18:08:59.290040 DQS Delay:
4564 18:08:59.290502 DQS0 = 0, DQS1 = 0
4565 18:08:59.293773 DQM Delay:
4566 18:08:59.294230 DQM0 = 50, DQM1 = 45
4567 18:08:59.294594 DQ Delay:
4568 18:08:59.297215 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4569 18:08:59.300404 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4570 18:08:59.303757 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4571 18:08:59.306920 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4572 18:08:59.307382
4573 18:08:59.307744
4574 18:08:59.308065 ==
4575 18:08:59.310123 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 18:08:59.317131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 18:08:59.317607 ==
4578 18:08:59.317970
4579 18:08:59.318304
4580 18:08:59.318628 TX Vref Scan disable
4581 18:08:59.320851 == TX Byte 0 ==
4582 18:08:59.324450 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 18:08:59.330649 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 18:08:59.331239 == TX Byte 1 ==
4585 18:08:59.334364 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4586 18:08:59.340779 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4587 18:08:59.341376 ==
4588 18:08:59.344090 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 18:08:59.347272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 18:08:59.347737 ==
4591 18:08:59.348099
4592 18:08:59.348433
4593 18:08:59.350535 TX Vref Scan disable
4594 18:08:59.350989 == TX Byte 0 ==
4595 18:08:59.357434 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4596 18:08:59.360529 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4597 18:08:59.361061 == TX Byte 1 ==
4598 18:08:59.367366 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4599 18:08:59.370568 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4600 18:08:59.371034
4601 18:08:59.371402 [DATLAT]
4602 18:08:59.373699 Freq=600, CH1 RK0
4603 18:08:59.374166
4604 18:08:59.374533 DATLAT Default: 0x9
4605 18:08:59.377442 0, 0xFFFF, sum = 0
4606 18:08:59.377910 1, 0xFFFF, sum = 0
4607 18:08:59.380491 2, 0xFFFF, sum = 0
4608 18:08:59.383931 3, 0xFFFF, sum = 0
4609 18:08:59.384402 4, 0xFFFF, sum = 0
4610 18:08:59.387196 5, 0xFFFF, sum = 0
4611 18:08:59.387732 6, 0xFFFF, sum = 0
4612 18:08:59.390526 7, 0xFFFF, sum = 0
4613 18:08:59.390999 8, 0x0, sum = 1
4614 18:08:59.393863 9, 0x0, sum = 2
4615 18:08:59.394332 10, 0x0, sum = 3
4616 18:08:59.394703 11, 0x0, sum = 4
4617 18:08:59.397052 best_step = 9
4618 18:08:59.397517
4619 18:08:59.397884 ==
4620 18:08:59.400437 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 18:08:59.403755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 18:08:59.404271 ==
4623 18:08:59.407031 RX Vref Scan: 1
4624 18:08:59.407452
4625 18:08:59.407804 RX Vref 0 -> 0, step: 1
4626 18:08:59.410545
4627 18:08:59.411135 RX Delay -163 -> 252, step: 8
4628 18:08:59.411510
4629 18:08:59.413872 Set Vref, RX VrefLevel [Byte0]: 54
4630 18:08:59.417015 [Byte1]: 49
4631 18:08:59.420982
4632 18:08:59.421528 Final RX Vref Byte 0 = 54 to rank0
4633 18:08:59.424687 Final RX Vref Byte 1 = 49 to rank0
4634 18:08:59.427973 Final RX Vref Byte 0 = 54 to rank1
4635 18:08:59.431320 Final RX Vref Byte 1 = 49 to rank1==
4636 18:08:59.434356 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 18:08:59.440752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 18:08:59.441216 ==
4639 18:08:59.441580 DQS Delay:
4640 18:08:59.441920 DQS0 = 0, DQS1 = 0
4641 18:08:59.444373 DQM Delay:
4642 18:08:59.444867 DQM0 = 47, DQM1 = 40
4643 18:08:59.447602 DQ Delay:
4644 18:08:59.451086 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4645 18:08:59.451549 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4646 18:08:59.454440 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =32
4647 18:08:59.460967 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4648 18:08:59.461424
4649 18:08:59.461782
4650 18:08:59.467931 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4651 18:08:59.470949 CH1 RK0: MR19=808, MR18=4A71
4652 18:08:59.477649 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4653 18:08:59.478110
4654 18:08:59.480882 ----->DramcWriteLeveling(PI) begin...
4655 18:08:59.481361 ==
4656 18:08:59.484727 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 18:08:59.487878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 18:08:59.488336 ==
4659 18:08:59.491231 Write leveling (Byte 0): 28 => 28
4660 18:08:59.494816 Write leveling (Byte 1): 31 => 31
4661 18:08:59.497742 DramcWriteLeveling(PI) end<-----
4662 18:08:59.498241
4663 18:08:59.498612 ==
4664 18:08:59.500946 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 18:08:59.504274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 18:08:59.504784 ==
4667 18:08:59.507468 [Gating] SW mode calibration
4668 18:08:59.514607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4669 18:08:59.520669 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4670 18:08:59.524248 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 18:08:59.528198 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 18:08:59.534815 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 18:08:59.538009 0 9 12 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 1)
4674 18:08:59.541259 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
4675 18:08:59.547735 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 18:08:59.550796 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 18:08:59.553956 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 18:08:59.561263 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 18:08:59.564208 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 18:08:59.567184 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4681 18:08:59.573893 0 10 12 | B1->B0 | 3f3f 3030 | 0 0 | (0 0) (0 0)
4682 18:08:59.577291 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 18:08:59.580727 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 18:08:59.587816 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 18:08:59.590848 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 18:08:59.593929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 18:08:59.600756 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 18:08:59.603837 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 18:08:59.607072 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4690 18:08:59.613764 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 18:08:59.617008 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 18:08:59.620232 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 18:08:59.627081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 18:08:59.630405 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 18:08:59.633625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 18:08:59.640172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 18:08:59.644078 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 18:08:59.647315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 18:08:59.650475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 18:08:59.656975 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 18:08:59.660165 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 18:08:59.663841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 18:08:59.670188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 18:08:59.673472 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 18:08:59.677061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4706 18:08:59.683297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 18:08:59.686940 Total UI for P1: 0, mck2ui 16
4708 18:08:59.690240 best dqsien dly found for B0: ( 0, 13, 12)
4709 18:08:59.693470 Total UI for P1: 0, mck2ui 16
4710 18:08:59.696708 best dqsien dly found for B1: ( 0, 13, 12)
4711 18:08:59.700093 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4712 18:08:59.703387 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4713 18:08:59.703834
4714 18:08:59.706795 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 18:08:59.709904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4716 18:08:59.713736 [Gating] SW calibration Done
4717 18:08:59.714155 ==
4718 18:08:59.716865 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 18:08:59.720148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 18:08:59.720594 ==
4721 18:08:59.723435 RX Vref Scan: 0
4722 18:08:59.723860
4723 18:08:59.724190 RX Vref 0 -> 0, step: 1
4724 18:08:59.726686
4725 18:08:59.727121 RX Delay -230 -> 252, step: 16
4726 18:08:59.733442 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4727 18:08:59.736777 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4728 18:08:59.739516 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4729 18:08:59.743426 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4730 18:08:59.749733 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4731 18:08:59.752916 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4732 18:08:59.756307 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4733 18:08:59.759404 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4734 18:08:59.763169 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4735 18:08:59.769464 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4736 18:08:59.772592 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4737 18:08:59.776365 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4738 18:08:59.779395 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4739 18:08:59.786251 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4740 18:08:59.789326 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4741 18:08:59.792849 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4742 18:08:59.793271 ==
4743 18:08:59.795965 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 18:08:59.799318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 18:08:59.799738 ==
4746 18:08:59.802561 DQS Delay:
4747 18:08:59.802978 DQS0 = 0, DQS1 = 0
4748 18:08:59.805863 DQM Delay:
4749 18:08:59.806281 DQM0 = 53, DQM1 = 47
4750 18:08:59.806613 DQ Delay:
4751 18:08:59.809784 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4752 18:08:59.812908 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4753 18:08:59.816164 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4754 18:08:59.819502 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =65
4755 18:08:59.819925
4756 18:08:59.820375
4757 18:08:59.822592 ==
4758 18:08:59.826009 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 18:08:59.829396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 18:08:59.829816 ==
4761 18:08:59.830145
4762 18:08:59.830450
4763 18:08:59.832670 TX Vref Scan disable
4764 18:08:59.833089 == TX Byte 0 ==
4765 18:08:59.839157 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4766 18:08:59.842229 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4767 18:08:59.842651 == TX Byte 1 ==
4768 18:08:59.849603 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 18:08:59.852195 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 18:08:59.852657 ==
4771 18:08:59.856063 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 18:08:59.858918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 18:08:59.859384 ==
4774 18:08:59.859749
4775 18:08:59.860089
4776 18:08:59.862015 TX Vref Scan disable
4777 18:08:59.865646 == TX Byte 0 ==
4778 18:08:59.868944 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4779 18:08:59.872074 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4780 18:08:59.875593 == TX Byte 1 ==
4781 18:08:59.879200 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4782 18:08:59.882186 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4783 18:08:59.885234
4784 18:08:59.885733 [DATLAT]
4785 18:08:59.886208 Freq=600, CH1 RK1
4786 18:08:59.886655
4787 18:08:59.888466 DATLAT Default: 0x9
4788 18:08:59.888990 0, 0xFFFF, sum = 0
4789 18:08:59.891657 1, 0xFFFF, sum = 0
4790 18:08:59.892140 2, 0xFFFF, sum = 0
4791 18:08:59.895663 3, 0xFFFF, sum = 0
4792 18:08:59.898437 4, 0xFFFF, sum = 0
4793 18:08:59.898927 5, 0xFFFF, sum = 0
4794 18:08:59.901671 6, 0xFFFF, sum = 0
4795 18:08:59.902159 7, 0xFFFF, sum = 0
4796 18:08:59.905228 8, 0x0, sum = 1
4797 18:08:59.905806 9, 0x0, sum = 2
4798 18:08:59.906304 10, 0x0, sum = 3
4799 18:08:59.908764 11, 0x0, sum = 4
4800 18:08:59.909250 best_step = 9
4801 18:08:59.909732
4802 18:08:59.910184 ==
4803 18:08:59.911839 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 18:08:59.918493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 18:08:59.919055 ==
4806 18:08:59.919539 RX Vref Scan: 0
4807 18:08:59.919988
4808 18:08:59.921667 RX Vref 0 -> 0, step: 1
4809 18:08:59.922147
4810 18:08:59.925004 RX Delay -163 -> 252, step: 8
4811 18:08:59.928202 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4812 18:08:59.934826 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4813 18:08:59.937973 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4814 18:08:59.941266 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4815 18:08:59.944612 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4816 18:08:59.947822 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4817 18:08:59.954407 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4818 18:08:59.957790 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4819 18:08:59.961390 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4820 18:08:59.964338 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4821 18:08:59.971417 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4822 18:08:59.974779 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4823 18:08:59.977910 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4824 18:08:59.981278 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4825 18:08:59.984404 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4826 18:08:59.991236 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4827 18:08:59.991815 ==
4828 18:08:59.994700 Dram Type= 6, Freq= 0, CH_1, rank 1
4829 18:08:59.997620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4830 18:08:59.998097 ==
4831 18:08:59.998706 DQS Delay:
4832 18:09:00.001158 DQS0 = 0, DQS1 = 0
4833 18:09:00.001630 DQM Delay:
4834 18:09:00.004427 DQM0 = 47, DQM1 = 42
4835 18:09:00.005022 DQ Delay:
4836 18:09:00.007651 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4837 18:09:00.010873 DQ4 =48, DQ5 =60, DQ6 =52, DQ7 =44
4838 18:09:00.014498 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4839 18:09:00.017168 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4840 18:09:00.017788
4841 18:09:00.018344
4842 18:09:00.027522 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4843 18:09:00.028274 CH1 RK1: MR19=808, MR18=5B22
4844 18:09:00.033801 CH1_RK1: MR19=0x808, MR18=0x5B22, DQSOSC=392, MR23=63, INC=170, DEC=113
4845 18:09:00.037643 [RxdqsGatingPostProcess] freq 600
4846 18:09:00.044042 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4847 18:09:00.047337 Pre-setting of DQS Precalculation
4848 18:09:00.050510 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4849 18:09:00.057082 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4850 18:09:00.067413 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4851 18:09:00.067998
4852 18:09:00.068374
4853 18:09:00.068757 [Calibration Summary] 1200 Mbps
4854 18:09:00.070057 CH 0, Rank 0
4855 18:09:00.070514 SW Impedance : PASS
4856 18:09:00.073764 DUTY Scan : NO K
4857 18:09:00.076992 ZQ Calibration : PASS
4858 18:09:00.077450 Jitter Meter : NO K
4859 18:09:00.080254 CBT Training : PASS
4860 18:09:00.083737 Write leveling : PASS
4861 18:09:00.084313 RX DQS gating : PASS
4862 18:09:00.086866 RX DQ/DQS(RDDQC) : PASS
4863 18:09:00.089958 TX DQ/DQS : PASS
4864 18:09:00.090426 RX DATLAT : PASS
4865 18:09:00.093513 RX DQ/DQS(Engine): PASS
4866 18:09:00.096772 TX OE : NO K
4867 18:09:00.097407 All Pass.
4868 18:09:00.097791
4869 18:09:00.098139 CH 0, Rank 1
4870 18:09:00.100212 SW Impedance : PASS
4871 18:09:00.103206 DUTY Scan : NO K
4872 18:09:00.103673 ZQ Calibration : PASS
4873 18:09:00.106952 Jitter Meter : NO K
4874 18:09:00.110065 CBT Training : PASS
4875 18:09:00.110529 Write leveling : PASS
4876 18:09:00.113392 RX DQS gating : PASS
4877 18:09:00.116709 RX DQ/DQS(RDDQC) : PASS
4878 18:09:00.117181 TX DQ/DQS : PASS
4879 18:09:00.120350 RX DATLAT : PASS
4880 18:09:00.123708 RX DQ/DQS(Engine): PASS
4881 18:09:00.124265 TX OE : NO K
4882 18:09:00.124694 All Pass.
4883 18:09:00.126729
4884 18:09:00.127194 CH 1, Rank 0
4885 18:09:00.130050 SW Impedance : PASS
4886 18:09:00.130514 DUTY Scan : NO K
4887 18:09:00.133328 ZQ Calibration : PASS
4888 18:09:00.136709 Jitter Meter : NO K
4889 18:09:00.137269 CBT Training : PASS
4890 18:09:00.139784 Write leveling : PASS
4891 18:09:00.140251 RX DQS gating : PASS
4892 18:09:00.143200 RX DQ/DQS(RDDQC) : PASS
4893 18:09:00.146385 TX DQ/DQS : PASS
4894 18:09:00.146852 RX DATLAT : PASS
4895 18:09:00.149840 RX DQ/DQS(Engine): PASS
4896 18:09:00.153131 TX OE : NO K
4897 18:09:00.153556 All Pass.
4898 18:09:00.153896
4899 18:09:00.154235 CH 1, Rank 1
4900 18:09:00.156489 SW Impedance : PASS
4901 18:09:00.159638 DUTY Scan : NO K
4902 18:09:00.160053 ZQ Calibration : PASS
4903 18:09:00.163048 Jitter Meter : NO K
4904 18:09:00.166240 CBT Training : PASS
4905 18:09:00.166653 Write leveling : PASS
4906 18:09:00.169467 RX DQS gating : PASS
4907 18:09:00.172513 RX DQ/DQS(RDDQC) : PASS
4908 18:09:00.172956 TX DQ/DQS : PASS
4909 18:09:00.176262 RX DATLAT : PASS
4910 18:09:00.179750 RX DQ/DQS(Engine): PASS
4911 18:09:00.180169 TX OE : NO K
4912 18:09:00.180595 All Pass.
4913 18:09:00.182768
4914 18:09:00.183181 DramC Write-DBI off
4915 18:09:00.186173 PER_BANK_REFRESH: Hybrid Mode
4916 18:09:00.186588 TX_TRACKING: ON
4917 18:09:00.196484 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4918 18:09:00.199581 [FAST_K] Save calibration result to emmc
4919 18:09:00.202827 dramc_set_vcore_voltage set vcore to 662500
4920 18:09:00.205876 Read voltage for 933, 3
4921 18:09:00.206365 Vio18 = 0
4922 18:09:00.209406 Vcore = 662500
4923 18:09:00.209882 Vdram = 0
4924 18:09:00.210223 Vddq = 0
4925 18:09:00.210540 Vmddr = 0
4926 18:09:00.215835 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4927 18:09:00.222802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4928 18:09:00.223228 MEM_TYPE=3, freq_sel=17
4929 18:09:00.226107 sv_algorithm_assistance_LP4_1600
4930 18:09:00.229353 ============ PULL DRAM RESETB DOWN ============
4931 18:09:00.235943 ========== PULL DRAM RESETB DOWN end =========
4932 18:09:00.239202 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4933 18:09:00.242297 ===================================
4934 18:09:00.245677 LPDDR4 DRAM CONFIGURATION
4935 18:09:00.249305 ===================================
4936 18:09:00.249733 EX_ROW_EN[0] = 0x0
4937 18:09:00.252345 EX_ROW_EN[1] = 0x0
4938 18:09:00.252833 LP4Y_EN = 0x0
4939 18:09:00.255751 WORK_FSP = 0x0
4940 18:09:00.256165 WL = 0x3
4941 18:09:00.259348 RL = 0x3
4942 18:09:00.262503 BL = 0x2
4943 18:09:00.262917 RPST = 0x0
4944 18:09:00.266072 RD_PRE = 0x0
4945 18:09:00.266603 WR_PRE = 0x1
4946 18:09:00.269091 WR_PST = 0x0
4947 18:09:00.269521 DBI_WR = 0x0
4948 18:09:00.272366 DBI_RD = 0x0
4949 18:09:00.272845 OTF = 0x1
4950 18:09:00.275459 ===================================
4951 18:09:00.279175 ===================================
4952 18:09:00.282035 ANA top config
4953 18:09:00.285673 ===================================
4954 18:09:00.286088 DLL_ASYNC_EN = 0
4955 18:09:00.288736 ALL_SLAVE_EN = 1
4956 18:09:00.292370 NEW_RANK_MODE = 1
4957 18:09:00.295521 DLL_IDLE_MODE = 1
4958 18:09:00.295933 LP45_APHY_COMB_EN = 1
4959 18:09:00.298836 TX_ODT_DIS = 1
4960 18:09:00.301882 NEW_8X_MODE = 1
4961 18:09:00.305630 ===================================
4962 18:09:00.308937 ===================================
4963 18:09:00.312167 data_rate = 1866
4964 18:09:00.315531 CKR = 1
4965 18:09:00.319013 DQ_P2S_RATIO = 8
4966 18:09:00.322563 ===================================
4967 18:09:00.323222 CA_P2S_RATIO = 8
4968 18:09:00.325718 DQ_CA_OPEN = 0
4969 18:09:00.328943 DQ_SEMI_OPEN = 0
4970 18:09:00.332258 CA_SEMI_OPEN = 0
4971 18:09:00.335949 CA_FULL_RATE = 0
4972 18:09:00.336624 DQ_CKDIV4_EN = 1
4973 18:09:00.338940 CA_CKDIV4_EN = 1
4974 18:09:00.342221 CA_PREDIV_EN = 0
4975 18:09:00.345454 PH8_DLY = 0
4976 18:09:00.348697 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4977 18:09:00.352224 DQ_AAMCK_DIV = 4
4978 18:09:00.352785 CA_AAMCK_DIV = 4
4979 18:09:00.355599 CA_ADMCK_DIV = 4
4980 18:09:00.358738 DQ_TRACK_CA_EN = 0
4981 18:09:00.361897 CA_PICK = 933
4982 18:09:00.365140 CA_MCKIO = 933
4983 18:09:00.368864 MCKIO_SEMI = 0
4984 18:09:00.371830 PLL_FREQ = 3732
4985 18:09:00.372284 DQ_UI_PI_RATIO = 32
4986 18:09:00.374937 CA_UI_PI_RATIO = 0
4987 18:09:00.378728 ===================================
4988 18:09:00.381963 ===================================
4989 18:09:00.384983 memory_type:LPDDR4
4990 18:09:00.388704 GP_NUM : 10
4991 18:09:00.389135 SRAM_EN : 1
4992 18:09:00.391770 MD32_EN : 0
4993 18:09:00.394976 ===================================
4994 18:09:00.398642 [ANA_INIT] >>>>>>>>>>>>>>
4995 18:09:00.399078 <<<<<< [CONFIGURE PHASE]: ANA_TX
4996 18:09:00.405056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4997 18:09:00.405477 ===================================
4998 18:09:00.408682 data_rate = 1866,PCW = 0X8f00
4999 18:09:00.412207 ===================================
5000 18:09:00.415339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5001 18:09:00.422050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 18:09:00.428254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5003 18:09:00.431487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5004 18:09:00.435293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5005 18:09:00.438379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5006 18:09:00.441813 [ANA_INIT] flow start
5007 18:09:00.442275 [ANA_INIT] PLL >>>>>>>>
5008 18:09:00.445185 [ANA_INIT] PLL <<<<<<<<
5009 18:09:00.448369 [ANA_INIT] MIDPI >>>>>>>>
5010 18:09:00.448868 [ANA_INIT] MIDPI <<<<<<<<
5011 18:09:00.452078 [ANA_INIT] DLL >>>>>>>>
5012 18:09:00.454870 [ANA_INIT] flow end
5013 18:09:00.458681 ============ LP4 DIFF to SE enter ============
5014 18:09:00.462210 ============ LP4 DIFF to SE exit ============
5015 18:09:00.465295 [ANA_INIT] <<<<<<<<<<<<<
5016 18:09:00.468452 [Flow] Enable top DCM control >>>>>
5017 18:09:00.471813 [Flow] Enable top DCM control <<<<<
5018 18:09:00.474918 Enable DLL master slave shuffle
5019 18:09:00.478194 ==============================================================
5020 18:09:00.481859 Gating Mode config
5021 18:09:00.488060 ==============================================================
5022 18:09:00.488660 Config description:
5023 18:09:00.498546 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5024 18:09:00.504777 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5025 18:09:00.511549 SELPH_MODE 0: By rank 1: By Phase
5026 18:09:00.515236 ==============================================================
5027 18:09:00.518669 GAT_TRACK_EN = 1
5028 18:09:00.521901 RX_GATING_MODE = 2
5029 18:09:00.525101 RX_GATING_TRACK_MODE = 2
5030 18:09:00.528228 SELPH_MODE = 1
5031 18:09:00.531952 PICG_EARLY_EN = 1
5032 18:09:00.535190 VALID_LAT_VALUE = 1
5033 18:09:00.538438 ==============================================================
5034 18:09:00.541568 Enter into Gating configuration >>>>
5035 18:09:00.544971 Exit from Gating configuration <<<<
5036 18:09:00.548047 Enter into DVFS_PRE_config >>>>>
5037 18:09:00.561696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5038 18:09:00.562272 Exit from DVFS_PRE_config <<<<<
5039 18:09:00.564952 Enter into PICG configuration >>>>
5040 18:09:00.568221 Exit from PICG configuration <<<<
5041 18:09:00.571608 [RX_INPUT] configuration >>>>>
5042 18:09:00.574743 [RX_INPUT] configuration <<<<<
5043 18:09:00.581519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5044 18:09:00.584850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5045 18:09:00.591373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 18:09:00.598007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 18:09:00.604870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 18:09:00.611451 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 18:09:00.614824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5050 18:09:00.617924 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5051 18:09:00.621549 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5052 18:09:00.628081 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5053 18:09:00.631233 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5054 18:09:00.634311 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 18:09:00.638081 ===================================
5056 18:09:00.641292 LPDDR4 DRAM CONFIGURATION
5057 18:09:00.644509 ===================================
5058 18:09:00.644946 EX_ROW_EN[0] = 0x0
5059 18:09:00.647739 EX_ROW_EN[1] = 0x0
5060 18:09:00.651356 LP4Y_EN = 0x0
5061 18:09:00.651903 WORK_FSP = 0x0
5062 18:09:00.654535 WL = 0x3
5063 18:09:00.655071 RL = 0x3
5064 18:09:00.657687 BL = 0x2
5065 18:09:00.658101 RPST = 0x0
5066 18:09:00.661430 RD_PRE = 0x0
5067 18:09:00.661845 WR_PRE = 0x1
5068 18:09:00.664228 WR_PST = 0x0
5069 18:09:00.664678 DBI_WR = 0x0
5070 18:09:00.668052 DBI_RD = 0x0
5071 18:09:00.668467 OTF = 0x1
5072 18:09:00.671295 ===================================
5073 18:09:00.674489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5074 18:09:00.680729 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5075 18:09:00.684443 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5076 18:09:00.687749 ===================================
5077 18:09:00.690985 LPDDR4 DRAM CONFIGURATION
5078 18:09:00.694281 ===================================
5079 18:09:00.694701 EX_ROW_EN[0] = 0x10
5080 18:09:00.697224 EX_ROW_EN[1] = 0x0
5081 18:09:00.700815 LP4Y_EN = 0x0
5082 18:09:00.701234 WORK_FSP = 0x0
5083 18:09:00.704215 WL = 0x3
5084 18:09:00.704683 RL = 0x3
5085 18:09:00.707364 BL = 0x2
5086 18:09:00.707778 RPST = 0x0
5087 18:09:00.710613 RD_PRE = 0x0
5088 18:09:00.711032 WR_PRE = 0x1
5089 18:09:00.714340 WR_PST = 0x0
5090 18:09:00.714756 DBI_WR = 0x0
5091 18:09:00.717630 DBI_RD = 0x0
5092 18:09:00.718235 OTF = 0x1
5093 18:09:00.720688 ===================================
5094 18:09:00.727713 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5095 18:09:00.731421 nWR fixed to 30
5096 18:09:00.734610 [ModeRegInit_LP4] CH0 RK0
5097 18:09:00.735035 [ModeRegInit_LP4] CH0 RK1
5098 18:09:00.738321 [ModeRegInit_LP4] CH1 RK0
5099 18:09:00.741412 [ModeRegInit_LP4] CH1 RK1
5100 18:09:00.741841 match AC timing 9
5101 18:09:00.748236 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5102 18:09:00.751516 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5103 18:09:00.754714 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5104 18:09:00.761427 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5105 18:09:00.764653 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5106 18:09:00.765130 ==
5107 18:09:00.767892 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 18:09:00.771735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 18:09:00.772158 ==
5110 18:09:00.778298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 18:09:00.784919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5112 18:09:00.788225 [CA 0] Center 38 (7~69) winsize 63
5113 18:09:00.791494 [CA 1] Center 38 (8~69) winsize 62
5114 18:09:00.794706 [CA 2] Center 35 (5~66) winsize 62
5115 18:09:00.798001 [CA 3] Center 35 (5~66) winsize 62
5116 18:09:00.801122 [CA 4] Center 35 (5~65) winsize 61
5117 18:09:00.804801 [CA 5] Center 33 (3~64) winsize 62
5118 18:09:00.805416
5119 18:09:00.807757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5120 18:09:00.808143
5121 18:09:00.811508 [CATrainingPosCal] consider 1 rank data
5122 18:09:00.814758 u2DelayCellTimex100 = 270/100 ps
5123 18:09:00.817942 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5124 18:09:00.821110 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5125 18:09:00.824344 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5126 18:09:00.827465 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5127 18:09:00.831295 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5128 18:09:00.837646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5129 18:09:00.838094
5130 18:09:00.841293 CA PerBit enable=1, Macro0, CA PI delay=33
5131 18:09:00.841710
5132 18:09:00.844422 [CBTSetCACLKResult] CA Dly = 33
5133 18:09:00.844900 CS Dly: 7 (0~38)
5134 18:09:00.845253 ==
5135 18:09:00.847710 Dram Type= 6, Freq= 0, CH_0, rank 1
5136 18:09:00.850983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 18:09:00.851403 ==
5138 18:09:00.858098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5139 18:09:00.864434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5140 18:09:00.867766 [CA 0] Center 38 (8~69) winsize 62
5141 18:09:00.870869 [CA 1] Center 38 (8~69) winsize 62
5142 18:09:00.874280 [CA 2] Center 36 (6~66) winsize 61
5143 18:09:00.877795 [CA 3] Center 35 (5~66) winsize 62
5144 18:09:00.880948 [CA 4] Center 34 (4~65) winsize 62
5145 18:09:00.884263 [CA 5] Center 34 (4~65) winsize 62
5146 18:09:00.884719
5147 18:09:00.887729 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5148 18:09:00.888144
5149 18:09:00.890856 [CATrainingPosCal] consider 2 rank data
5150 18:09:00.894291 u2DelayCellTimex100 = 270/100 ps
5151 18:09:00.897296 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5152 18:09:00.900982 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5153 18:09:00.904291 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5154 18:09:00.907333 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5155 18:09:00.914045 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5156 18:09:00.917628 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5157 18:09:00.918355
5158 18:09:00.920689 CA PerBit enable=1, Macro0, CA PI delay=34
5159 18:09:00.921365
5160 18:09:00.924192 [CBTSetCACLKResult] CA Dly = 34
5161 18:09:00.924681 CS Dly: 7 (0~39)
5162 18:09:00.925113
5163 18:09:00.927531 ----->DramcWriteLeveling(PI) begin...
5164 18:09:00.927947 ==
5165 18:09:00.930666 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 18:09:00.937157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 18:09:00.937400 ==
5168 18:09:00.940827 Write leveling (Byte 0): 35 => 35
5169 18:09:00.941121 Write leveling (Byte 1): 27 => 27
5170 18:09:00.943926 DramcWriteLeveling(PI) end<-----
5171 18:09:00.944108
5172 18:09:00.944252 ==
5173 18:09:00.947204 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 18:09:00.953934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 18:09:00.954200 ==
5176 18:09:00.957019 [Gating] SW mode calibration
5177 18:09:00.963705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5178 18:09:00.967100 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5179 18:09:00.973474 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5180 18:09:00.976775 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 18:09:00.980347 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 18:09:00.987050 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 18:09:00.990685 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 18:09:00.993786 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 18:09:01.000349 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5186 18:09:01.003589 0 14 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
5187 18:09:01.006768 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5188 18:09:01.013544 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 18:09:01.016926 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 18:09:01.020137 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 18:09:01.026692 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 18:09:01.030320 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 18:09:01.033475 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5194 18:09:01.039885 0 15 28 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
5195 18:09:01.043613 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5196 18:09:01.046882 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 18:09:01.053120 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 18:09:01.056952 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 18:09:01.059752 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 18:09:01.066684 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 18:09:01.069794 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 18:09:01.073081 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5203 18:09:01.079715 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5204 18:09:01.082989 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 18:09:01.086615 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 18:09:01.089898 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 18:09:01.096380 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 18:09:01.099967 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 18:09:01.106422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 18:09:01.109860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 18:09:01.113024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 18:09:01.116204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 18:09:01.122930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 18:09:01.126037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 18:09:01.129228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 18:09:01.136092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 18:09:01.139237 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5218 18:09:01.142943 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5219 18:09:01.146247 Total UI for P1: 0, mck2ui 16
5220 18:09:01.149401 best dqsien dly found for B0: ( 1, 2, 24)
5221 18:09:01.156175 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 18:09:01.159764 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 18:09:01.162964 Total UI for P1: 0, mck2ui 16
5224 18:09:01.166151 best dqsien dly found for B1: ( 1, 3, 0)
5225 18:09:01.169404 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5226 18:09:01.172631 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5227 18:09:01.173065
5228 18:09:01.175818 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5229 18:09:01.179156 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5230 18:09:01.182972 [Gating] SW calibration Done
5231 18:09:01.183478 ==
5232 18:09:01.186213 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 18:09:01.189411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 18:09:01.193038 ==
5235 18:09:01.193544 RX Vref Scan: 0
5236 18:09:01.193977
5237 18:09:01.195985 RX Vref 0 -> 0, step: 1
5238 18:09:01.196416
5239 18:09:01.199414 RX Delay -80 -> 252, step: 8
5240 18:09:01.202702 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5241 18:09:01.206124 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5242 18:09:01.209397 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5243 18:09:01.212645 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5244 18:09:01.215954 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5245 18:09:01.222779 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5246 18:09:01.225699 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5247 18:09:01.228985 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5248 18:09:01.232348 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5249 18:09:01.235798 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5250 18:09:01.242523 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5251 18:09:01.245693 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5252 18:09:01.249216 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5253 18:09:01.252505 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5254 18:09:01.255626 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5255 18:09:01.258718 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5256 18:09:01.259278 ==
5257 18:09:01.262356 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 18:09:01.269340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 18:09:01.269943 ==
5260 18:09:01.270429 DQS Delay:
5261 18:09:01.272531 DQS0 = 0, DQS1 = 0
5262 18:09:01.273161 DQM Delay:
5263 18:09:01.273736 DQM0 = 105, DQM1 = 90
5264 18:09:01.275702 DQ Delay:
5265 18:09:01.279033 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5266 18:09:01.282091 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5267 18:09:01.285458 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5268 18:09:01.289272 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5269 18:09:01.289743
5270 18:09:01.290372
5271 18:09:01.291041 ==
5272 18:09:01.291983 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 18:09:01.295711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 18:09:01.296335 ==
5275 18:09:01.296942
5276 18:09:01.297321
5277 18:09:01.298849 TX Vref Scan disable
5278 18:09:01.302173 == TX Byte 0 ==
5279 18:09:01.305780 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5280 18:09:01.308895 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5281 18:09:01.312089 == TX Byte 1 ==
5282 18:09:01.315332 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5283 18:09:01.319205 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5284 18:09:01.319624 ==
5285 18:09:01.322012 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 18:09:01.325674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 18:09:01.328853 ==
5288 18:09:01.329268
5289 18:09:01.329592
5290 18:09:01.329891 TX Vref Scan disable
5291 18:09:01.332504 == TX Byte 0 ==
5292 18:09:01.335716 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5293 18:09:01.342577 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5294 18:09:01.343004 == TX Byte 1 ==
5295 18:09:01.346256 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5296 18:09:01.352738 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5297 18:09:01.353222
5298 18:09:01.353560 [DATLAT]
5299 18:09:01.353874 Freq=933, CH0 RK0
5300 18:09:01.354177
5301 18:09:01.355842 DATLAT Default: 0xd
5302 18:09:01.356261 0, 0xFFFF, sum = 0
5303 18:09:01.359048 1, 0xFFFF, sum = 0
5304 18:09:01.359635 2, 0xFFFF, sum = 0
5305 18:09:01.362550 3, 0xFFFF, sum = 0
5306 18:09:01.365901 4, 0xFFFF, sum = 0
5307 18:09:01.366330 5, 0xFFFF, sum = 0
5308 18:09:01.368985 6, 0xFFFF, sum = 0
5309 18:09:01.369575 7, 0xFFFF, sum = 0
5310 18:09:01.372001 8, 0xFFFF, sum = 0
5311 18:09:01.372423 9, 0xFFFF, sum = 0
5312 18:09:01.375551 10, 0x0, sum = 1
5313 18:09:01.375970 11, 0x0, sum = 2
5314 18:09:01.378868 12, 0x0, sum = 3
5315 18:09:01.379287 13, 0x0, sum = 4
5316 18:09:01.379620 best_step = 11
5317 18:09:01.379920
5318 18:09:01.383120 ==
5319 18:09:01.385548 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 18:09:01.389486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 18:09:01.389903 ==
5322 18:09:01.390233 RX Vref Scan: 1
5323 18:09:01.390564
5324 18:09:01.392659 RX Vref 0 -> 0, step: 1
5325 18:09:01.393075
5326 18:09:01.395629 RX Delay -53 -> 252, step: 4
5327 18:09:01.396044
5328 18:09:01.398913 Set Vref, RX VrefLevel [Byte0]: 59
5329 18:09:01.402193 [Byte1]: 48
5330 18:09:01.402609
5331 18:09:01.406067 Final RX Vref Byte 0 = 59 to rank0
5332 18:09:01.409280 Final RX Vref Byte 1 = 48 to rank0
5333 18:09:01.412403 Final RX Vref Byte 0 = 59 to rank1
5334 18:09:01.415970 Final RX Vref Byte 1 = 48 to rank1==
5335 18:09:01.419049 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 18:09:01.422553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 18:09:01.423076 ==
5338 18:09:01.425648 DQS Delay:
5339 18:09:01.426074 DQS0 = 0, DQS1 = 0
5340 18:09:01.428852 DQM Delay:
5341 18:09:01.429374 DQM0 = 108, DQM1 = 91
5342 18:09:01.429821 DQ Delay:
5343 18:09:01.435743 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5344 18:09:01.438980 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =114
5345 18:09:01.442472 DQ8 =82, DQ9 =76, DQ10 =92, DQ11 =90
5346 18:09:01.445338 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5347 18:09:01.445766
5348 18:09:01.446100
5349 18:09:01.452320 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
5350 18:09:01.455579 CH0 RK0: MR19=505, MR18=1F1B
5351 18:09:01.461903 CH0_RK0: MR19=0x505, MR18=0x1F1B, DQSOSC=412, MR23=63, INC=63, DEC=42
5352 18:09:01.462412
5353 18:09:01.465587 ----->DramcWriteLeveling(PI) begin...
5354 18:09:01.466016 ==
5355 18:09:01.468664 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 18:09:01.472291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 18:09:01.472763 ==
5358 18:09:01.475380 Write leveling (Byte 0): 34 => 34
5359 18:09:01.478728 Write leveling (Byte 1): 29 => 29
5360 18:09:01.481893 DramcWriteLeveling(PI) end<-----
5361 18:09:01.482505
5362 18:09:01.483065 ==
5363 18:09:01.485307 Dram Type= 6, Freq= 0, CH_0, rank 1
5364 18:09:01.488598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5365 18:09:01.489016 ==
5366 18:09:01.492003 [Gating] SW mode calibration
5367 18:09:01.498575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5368 18:09:01.505185 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5369 18:09:01.508305 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 18:09:01.515433 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 18:09:01.518501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 18:09:01.521716 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 18:09:01.528275 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 18:09:01.532093 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 18:09:01.534874 0 14 24 | B1->B0 | 3232 3131 | 1 0 | (1 1) (0 1)
5376 18:09:01.541523 0 14 28 | B1->B0 | 2828 2727 | 0 0 | (1 0) (0 0)
5377 18:09:01.544779 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5378 18:09:01.548438 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 18:09:01.554747 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 18:09:01.558528 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 18:09:01.561602 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 18:09:01.568283 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 18:09:01.571515 0 15 24 | B1->B0 | 2c2c 3333 | 0 0 | (0 0) (1 1)
5384 18:09:01.574543 0 15 28 | B1->B0 | 3737 4141 | 0 1 | (0 0) (0 0)
5385 18:09:01.581513 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 18:09:01.584809 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 18:09:01.588088 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 18:09:01.591365 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 18:09:01.597909 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 18:09:01.601203 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 18:09:01.604498 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5392 18:09:01.611028 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5393 18:09:01.614579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 18:09:01.617744 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 18:09:01.624613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 18:09:01.627886 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 18:09:01.631071 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 18:09:01.637608 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 18:09:01.641085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 18:09:01.644291 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 18:09:01.650970 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 18:09:01.654558 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 18:09:01.657733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 18:09:01.664401 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 18:09:01.667588 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 18:09:01.671035 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 18:09:01.677966 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5408 18:09:01.681270 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5409 18:09:01.684444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 18:09:01.687749 Total UI for P1: 0, mck2ui 16
5411 18:09:01.690990 best dqsien dly found for B0: ( 1, 2, 26)
5412 18:09:01.694366 Total UI for P1: 0, mck2ui 16
5413 18:09:01.697588 best dqsien dly found for B1: ( 1, 2, 28)
5414 18:09:01.700850 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5415 18:09:01.704115 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5416 18:09:01.704710
5417 18:09:01.707530 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5418 18:09:01.714259 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5419 18:09:01.714673 [Gating] SW calibration Done
5420 18:09:01.714999 ==
5421 18:09:01.717513 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 18:09:01.724218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 18:09:01.724765 ==
5424 18:09:01.725103 RX Vref Scan: 0
5425 18:09:01.725412
5426 18:09:01.727516 RX Vref 0 -> 0, step: 1
5427 18:09:01.727946
5428 18:09:01.730819 RX Delay -80 -> 252, step: 8
5429 18:09:01.734213 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5430 18:09:01.737422 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5431 18:09:01.740943 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5432 18:09:01.744011 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5433 18:09:01.750868 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5434 18:09:01.753946 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5435 18:09:01.757469 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5436 18:09:01.760406 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5437 18:09:01.764174 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5438 18:09:01.770481 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5439 18:09:01.774139 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5440 18:09:01.777287 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5441 18:09:01.780522 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5442 18:09:01.784204 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5443 18:09:01.787410 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5444 18:09:01.793936 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5445 18:09:01.794399 ==
5446 18:09:01.797172 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 18:09:01.800499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 18:09:01.800949 ==
5449 18:09:01.801277 DQS Delay:
5450 18:09:01.803790 DQS0 = 0, DQS1 = 0
5451 18:09:01.804202 DQM Delay:
5452 18:09:01.806981 DQM0 = 103, DQM1 = 90
5453 18:09:01.807396 DQ Delay:
5454 18:09:01.810427 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5455 18:09:01.814182 DQ4 =103, DQ5 =95, DQ6 =115, DQ7 =111
5456 18:09:01.817624 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5457 18:09:01.820901 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5458 18:09:01.821443
5459 18:09:01.821916
5460 18:09:01.822399 ==
5461 18:09:01.823981 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 18:09:01.827191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 18:09:01.827569 ==
5464 18:09:01.830877
5465 18:09:01.831422
5466 18:09:01.831763 TX Vref Scan disable
5467 18:09:01.833773 == TX Byte 0 ==
5468 18:09:01.836930 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5469 18:09:01.840233 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5470 18:09:01.843619 == TX Byte 1 ==
5471 18:09:01.846880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5472 18:09:01.850339 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5473 18:09:01.850899 ==
5474 18:09:01.854007 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 18:09:01.860299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 18:09:01.860772 ==
5477 18:09:01.861104
5478 18:09:01.861582
5479 18:09:01.862073 TX Vref Scan disable
5480 18:09:01.864858 == TX Byte 0 ==
5481 18:09:01.868183 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5482 18:09:01.871239 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5483 18:09:01.874830 == TX Byte 1 ==
5484 18:09:01.878019 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5485 18:09:01.881178 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5486 18:09:01.884574
5487 18:09:01.885000 [DATLAT]
5488 18:09:01.885416 Freq=933, CH0 RK1
5489 18:09:01.885813
5490 18:09:01.887737 DATLAT Default: 0xb
5491 18:09:01.888159 0, 0xFFFF, sum = 0
5492 18:09:01.891386 1, 0xFFFF, sum = 0
5493 18:09:01.891945 2, 0xFFFF, sum = 0
5494 18:09:01.894385 3, 0xFFFF, sum = 0
5495 18:09:01.894816 4, 0xFFFF, sum = 0
5496 18:09:01.897738 5, 0xFFFF, sum = 0
5497 18:09:01.901064 6, 0xFFFF, sum = 0
5498 18:09:01.901523 7, 0xFFFF, sum = 0
5499 18:09:01.904231 8, 0xFFFF, sum = 0
5500 18:09:01.904735 9, 0xFFFF, sum = 0
5501 18:09:01.907588 10, 0x0, sum = 1
5502 18:09:01.908012 11, 0x0, sum = 2
5503 18:09:01.911031 12, 0x0, sum = 3
5504 18:09:01.911456 13, 0x0, sum = 4
5505 18:09:01.911794 best_step = 11
5506 18:09:01.912104
5507 18:09:01.914610 ==
5508 18:09:01.915024 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 18:09:01.921360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 18:09:01.921852 ==
5511 18:09:01.922181 RX Vref Scan: 0
5512 18:09:01.922485
5513 18:09:01.924630 RX Vref 0 -> 0, step: 1
5514 18:09:01.925047
5515 18:09:01.927819 RX Delay -53 -> 252, step: 4
5516 18:09:01.931058 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5517 18:09:01.938074 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5518 18:09:01.941172 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5519 18:09:01.944199 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5520 18:09:01.947974 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5521 18:09:01.951285 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5522 18:09:01.957518 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5523 18:09:01.961092 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5524 18:09:01.964135 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5525 18:09:01.967635 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5526 18:09:01.970930 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5527 18:09:01.974564 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5528 18:09:01.981047 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5529 18:09:01.984383 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5530 18:09:01.987489 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5531 18:09:01.991159 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5532 18:09:01.991615 ==
5533 18:09:01.994290 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 18:09:02.001155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 18:09:02.001588 ==
5536 18:09:02.001917 DQS Delay:
5537 18:09:02.002224 DQS0 = 0, DQS1 = 0
5538 18:09:02.004511 DQM Delay:
5539 18:09:02.005038 DQM0 = 104, DQM1 = 92
5540 18:09:02.007774 DQ Delay:
5541 18:09:02.011374 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5542 18:09:02.014535 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5543 18:09:02.017744 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =92
5544 18:09:02.020812 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5545 18:09:02.021216
5546 18:09:02.021545
5547 18:09:02.027395 [DQSOSCAuto] RK1, (LSB)MR18= 0x2605, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5548 18:09:02.031018 CH0 RK1: MR19=505, MR18=2605
5549 18:09:02.037563 CH0_RK1: MR19=0x505, MR18=0x2605, DQSOSC=409, MR23=63, INC=64, DEC=43
5550 18:09:02.040745 [RxdqsGatingPostProcess] freq 933
5551 18:09:02.044534 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 18:09:02.047624 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 18:09:02.050989 best DQS1 dly(2T, 0.5T) = (0, 11)
5554 18:09:02.054082 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 18:09:02.057350 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5556 18:09:02.061210 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 18:09:02.064303 best DQS1 dly(2T, 0.5T) = (0, 10)
5558 18:09:02.067258 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 18:09:02.070996 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5560 18:09:02.074422 Pre-setting of DQS Precalculation
5561 18:09:02.077516 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 18:09:02.080734 ==
5563 18:09:02.081160 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 18:09:02.087567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 18:09:02.087995 ==
5566 18:09:02.090725 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 18:09:02.097150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5568 18:09:02.100885 [CA 0] Center 37 (7~68) winsize 62
5569 18:09:02.104591 [CA 1] Center 37 (7~68) winsize 62
5570 18:09:02.107859 [CA 2] Center 36 (6~66) winsize 61
5571 18:09:02.111140 [CA 3] Center 35 (5~65) winsize 61
5572 18:09:02.114392 [CA 4] Center 35 (5~66) winsize 62
5573 18:09:02.117607 [CA 5] Center 34 (4~65) winsize 62
5574 18:09:02.118031
5575 18:09:02.120723 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5576 18:09:02.121148
5577 18:09:02.124487 [CATrainingPosCal] consider 1 rank data
5578 18:09:02.127746 u2DelayCellTimex100 = 270/100 ps
5579 18:09:02.131146 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5580 18:09:02.134439 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5581 18:09:02.140925 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5582 18:09:02.143988 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5583 18:09:02.147323 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5584 18:09:02.150605 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5585 18:09:02.151038
5586 18:09:02.154595 CA PerBit enable=1, Macro0, CA PI delay=34
5587 18:09:02.155086
5588 18:09:02.157706 [CBTSetCACLKResult] CA Dly = 34
5589 18:09:02.158187 CS Dly: 7 (0~38)
5590 18:09:02.161010 ==
5591 18:09:02.164312 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 18:09:02.167504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 18:09:02.168019 ==
5594 18:09:02.170681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 18:09:02.177493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 18:09:02.181377 [CA 0] Center 38 (7~69) winsize 63
5597 18:09:02.184448 [CA 1] Center 38 (8~69) winsize 62
5598 18:09:02.187787 [CA 2] Center 36 (5~67) winsize 63
5599 18:09:02.190932 [CA 3] Center 35 (5~65) winsize 61
5600 18:09:02.194445 [CA 4] Center 35 (5~65) winsize 61
5601 18:09:02.197767 [CA 5] Center 35 (5~65) winsize 61
5602 18:09:02.198230
5603 18:09:02.201012 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 18:09:02.201492
5605 18:09:02.204429 [CATrainingPosCal] consider 2 rank data
5606 18:09:02.208149 u2DelayCellTimex100 = 270/100 ps
5607 18:09:02.210899 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5608 18:09:02.214689 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5609 18:09:02.220911 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5610 18:09:02.224103 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5611 18:09:02.227966 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5612 18:09:02.231109 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5613 18:09:02.231670
5614 18:09:02.234235 CA PerBit enable=1, Macro0, CA PI delay=35
5615 18:09:02.234787
5616 18:09:02.237899 [CBTSetCACLKResult] CA Dly = 35
5617 18:09:02.238324 CS Dly: 7 (0~39)
5618 18:09:02.238661
5619 18:09:02.241195 ----->DramcWriteLeveling(PI) begin...
5620 18:09:02.244377 ==
5621 18:09:02.244927 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 18:09:02.250926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 18:09:02.251423 ==
5624 18:09:02.254229 Write leveling (Byte 0): 27 => 27
5625 18:09:02.257617 Write leveling (Byte 1): 28 => 28
5626 18:09:02.260753 DramcWriteLeveling(PI) end<-----
5627 18:09:02.261174
5628 18:09:02.261502 ==
5629 18:09:02.264347 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 18:09:02.267529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 18:09:02.267952 ==
5632 18:09:02.270975 [Gating] SW mode calibration
5633 18:09:02.277743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 18:09:02.284060 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 18:09:02.287412 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 18:09:02.291060 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 18:09:02.294236 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 18:09:02.300623 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 18:09:02.303844 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 18:09:02.307353 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5641 18:09:02.313915 0 14 24 | B1->B0 | 3232 3333 | 1 0 | (1 1) (0 1)
5642 18:09:02.317225 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5643 18:09:02.320336 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 18:09:02.326907 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 18:09:02.330174 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 18:09:02.333598 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 18:09:02.340291 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 18:09:02.343334 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 18:09:02.346654 0 15 24 | B1->B0 | 2929 2929 | 0 0 | (1 1) (0 0)
5650 18:09:02.353529 0 15 28 | B1->B0 | 4040 4444 | 0 0 | (0 0) (0 0)
5651 18:09:02.356791 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 18:09:02.360077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 18:09:02.366417 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 18:09:02.370228 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 18:09:02.373462 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 18:09:02.379723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 18:09:02.383165 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5658 18:09:02.386644 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5659 18:09:02.393172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 18:09:02.396245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 18:09:02.399443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 18:09:02.406281 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 18:09:02.409956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 18:09:02.413169 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 18:09:02.420093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 18:09:02.423269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 18:09:02.426413 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 18:09:02.433276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 18:09:02.436288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 18:09:02.439483 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 18:09:02.446419 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 18:09:02.449687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 18:09:02.453134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5674 18:09:02.456449 Total UI for P1: 0, mck2ui 16
5675 18:09:02.459744 best dqsien dly found for B0: ( 1, 2, 22)
5676 18:09:02.466294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5677 18:09:02.469797 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 18:09:02.473067 Total UI for P1: 0, mck2ui 16
5679 18:09:02.476443 best dqsien dly found for B1: ( 1, 2, 26)
5680 18:09:02.479602 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5681 18:09:02.482756 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5682 18:09:02.483195
5683 18:09:02.485904 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5684 18:09:02.489669 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5685 18:09:02.492719 [Gating] SW calibration Done
5686 18:09:02.493142 ==
5687 18:09:02.496145 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 18:09:02.499434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 18:09:02.499857 ==
5690 18:09:02.502351 RX Vref Scan: 0
5691 18:09:02.503006
5692 18:09:02.506048 RX Vref 0 -> 0, step: 1
5693 18:09:02.506672
5694 18:09:02.507151 RX Delay -80 -> 252, step: 8
5695 18:09:02.512658 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5696 18:09:02.516492 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5697 18:09:02.519527 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5698 18:09:02.522953 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5699 18:09:02.526163 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5700 18:09:02.529356 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5701 18:09:02.535993 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5702 18:09:02.539536 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5703 18:09:02.542556 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5704 18:09:02.546388 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5705 18:09:02.549154 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5706 18:09:02.552963 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5707 18:09:02.559478 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5708 18:09:02.562745 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5709 18:09:02.565998 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5710 18:09:02.569138 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5711 18:09:02.569623 ==
5712 18:09:02.572455 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 18:09:02.579127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 18:09:02.579552 ==
5715 18:09:02.579882 DQS Delay:
5716 18:09:02.580188 DQS0 = 0, DQS1 = 0
5717 18:09:02.582537 DQM Delay:
5718 18:09:02.582984 DQM0 = 102, DQM1 = 95
5719 18:09:02.585651 DQ Delay:
5720 18:09:02.589564 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5721 18:09:02.592657 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5722 18:09:02.595615 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5723 18:09:02.598880 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5724 18:09:02.599499
5725 18:09:02.599985
5726 18:09:02.600497 ==
5727 18:09:02.602375 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 18:09:02.605635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 18:09:02.606184 ==
5730 18:09:02.606531
5731 18:09:02.606844
5732 18:09:02.609247 TX Vref Scan disable
5733 18:09:02.612370 == TX Byte 0 ==
5734 18:09:02.615478 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5735 18:09:02.619195 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5736 18:09:02.622529 == TX Byte 1 ==
5737 18:09:02.625430 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5738 18:09:02.629361 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5739 18:09:02.629871 ==
5740 18:09:02.632530 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 18:09:02.635418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 18:09:02.636067 ==
5743 18:09:02.638708
5744 18:09:02.639128
5745 18:09:02.639456 TX Vref Scan disable
5746 18:09:02.642152 == TX Byte 0 ==
5747 18:09:02.645452 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5748 18:09:02.651966 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5749 18:09:02.652485 == TX Byte 1 ==
5750 18:09:02.655338 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5751 18:09:02.662332 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5752 18:09:02.662752
5753 18:09:02.663081 [DATLAT]
5754 18:09:02.663386 Freq=933, CH1 RK0
5755 18:09:02.663682
5756 18:09:02.665598 DATLAT Default: 0xd
5757 18:09:02.666014 0, 0xFFFF, sum = 0
5758 18:09:02.668668 1, 0xFFFF, sum = 0
5759 18:09:02.669311 2, 0xFFFF, sum = 0
5760 18:09:02.672238 3, 0xFFFF, sum = 0
5761 18:09:02.672710 4, 0xFFFF, sum = 0
5762 18:09:02.675465 5, 0xFFFF, sum = 0
5763 18:09:02.678675 6, 0xFFFF, sum = 0
5764 18:09:02.679094 7, 0xFFFF, sum = 0
5765 18:09:02.682032 8, 0xFFFF, sum = 0
5766 18:09:02.682452 9, 0xFFFF, sum = 0
5767 18:09:02.685167 10, 0x0, sum = 1
5768 18:09:02.685587 11, 0x0, sum = 2
5769 18:09:02.688978 12, 0x0, sum = 3
5770 18:09:02.689395 13, 0x0, sum = 4
5771 18:09:02.689726 best_step = 11
5772 18:09:02.690230
5773 18:09:02.692046 ==
5774 18:09:02.695382 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 18:09:02.698658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 18:09:02.699078 ==
5777 18:09:02.699460 RX Vref Scan: 1
5778 18:09:02.699933
5779 18:09:02.702303 RX Vref 0 -> 0, step: 1
5780 18:09:02.702737
5781 18:09:02.705279 RX Delay -53 -> 252, step: 4
5782 18:09:02.705695
5783 18:09:02.708328 Set Vref, RX VrefLevel [Byte0]: 54
5784 18:09:02.711828 [Byte1]: 49
5785 18:09:02.712279
5786 18:09:02.715323 Final RX Vref Byte 0 = 54 to rank0
5787 18:09:02.718482 Final RX Vref Byte 1 = 49 to rank0
5788 18:09:02.722238 Final RX Vref Byte 0 = 54 to rank1
5789 18:09:02.725315 Final RX Vref Byte 1 = 49 to rank1==
5790 18:09:02.728486 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 18:09:02.731583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 18:09:02.732009 ==
5793 18:09:02.735461 DQS Delay:
5794 18:09:02.735878 DQS0 = 0, DQS1 = 0
5795 18:09:02.738684 DQM Delay:
5796 18:09:02.739165 DQM0 = 104, DQM1 = 97
5797 18:09:02.741879 DQ Delay:
5798 18:09:02.745006 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5799 18:09:02.748399 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5800 18:09:02.751549 DQ8 =86, DQ9 =86, DQ10 =102, DQ11 =90
5801 18:09:02.755282 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =102
5802 18:09:02.755794
5803 18:09:02.756123
5804 18:09:02.762094 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5805 18:09:02.765530 CH1 RK0: MR19=505, MR18=162E
5806 18:09:02.771781 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5807 18:09:02.772269
5808 18:09:02.775240 ----->DramcWriteLeveling(PI) begin...
5809 18:09:02.775797 ==
5810 18:09:02.778492 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 18:09:02.782079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 18:09:02.782503 ==
5813 18:09:02.785229 Write leveling (Byte 0): 27 => 27
5814 18:09:02.788357 Write leveling (Byte 1): 29 => 29
5815 18:09:02.791609 DramcWriteLeveling(PI) end<-----
5816 18:09:02.792059
5817 18:09:02.792444 ==
5818 18:09:02.795118 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 18:09:02.798353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 18:09:02.801529 ==
5821 18:09:02.801946 [Gating] SW mode calibration
5822 18:09:02.808281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 18:09:02.814825 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 18:09:02.818230 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 18:09:02.824471 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 18:09:02.828134 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 18:09:02.831422 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 18:09:02.838250 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 18:09:02.841471 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 18:09:02.844807 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (1 0)
5831 18:09:02.851514 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5832 18:09:02.854856 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 18:09:02.857965 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 18:09:02.864812 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 18:09:02.868118 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 18:09:02.871393 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 18:09:02.877517 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 18:09:02.880899 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5839 18:09:02.884682 0 15 28 | B1->B0 | 3e3e 3b3b | 1 0 | (0 0) (1 1)
5840 18:09:02.891231 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 18:09:02.894499 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 18:09:02.897553 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 18:09:02.901042 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 18:09:02.907993 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 18:09:02.910992 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 18:09:02.914651 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 18:09:02.920934 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5848 18:09:02.924504 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 18:09:02.927757 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 18:09:02.934510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 18:09:02.937888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 18:09:02.941042 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 18:09:02.948090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 18:09:02.951242 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 18:09:02.954406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 18:09:02.961090 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 18:09:02.964307 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 18:09:02.967548 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 18:09:02.974575 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 18:09:02.977684 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 18:09:02.980853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 18:09:02.987611 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5863 18:09:02.990937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5864 18:09:02.994484 Total UI for P1: 0, mck2ui 16
5865 18:09:02.997898 best dqsien dly found for B1: ( 1, 2, 24)
5866 18:09:03.000748 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 18:09:03.004852 Total UI for P1: 0, mck2ui 16
5868 18:09:03.007412 best dqsien dly found for B0: ( 1, 2, 28)
5869 18:09:03.011222 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5870 18:09:03.014144 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5871 18:09:03.014573
5872 18:09:03.017263 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5873 18:09:03.024215 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5874 18:09:03.024707 [Gating] SW calibration Done
5875 18:09:03.025049 ==
5876 18:09:03.027454 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 18:09:03.034261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 18:09:03.034703 ==
5879 18:09:03.035049 RX Vref Scan: 0
5880 18:09:03.035358
5881 18:09:03.037265 RX Vref 0 -> 0, step: 1
5882 18:09:03.037755
5883 18:09:03.040581 RX Delay -80 -> 252, step: 8
5884 18:09:03.044092 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5885 18:09:03.047230 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5886 18:09:03.050553 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5887 18:09:03.057066 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5888 18:09:03.060632 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5889 18:09:03.063914 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5890 18:09:03.067046 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5891 18:09:03.070363 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5892 18:09:03.073588 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5893 18:09:03.080538 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5894 18:09:03.083795 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5895 18:09:03.086978 iDelay=200, Bit 11, Center 95 (8 ~ 183) 176
5896 18:09:03.090196 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5897 18:09:03.093289 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5898 18:09:03.096696 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5899 18:09:03.103681 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5900 18:09:03.104105 ==
5901 18:09:03.107073 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 18:09:03.110206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 18:09:03.110649 ==
5904 18:09:03.110992 DQS Delay:
5905 18:09:03.113580 DQS0 = 0, DQS1 = 0
5906 18:09:03.114018 DQM Delay:
5907 18:09:03.116649 DQM0 = 101, DQM1 = 96
5908 18:09:03.117089 DQ Delay:
5909 18:09:03.120522 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5910 18:09:03.123431 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5911 18:09:03.127107 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =95
5912 18:09:03.130335 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5913 18:09:03.130753
5914 18:09:03.131081
5915 18:09:03.131385 ==
5916 18:09:03.133475 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 18:09:03.140320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 18:09:03.140812 ==
5919 18:09:03.141140
5920 18:09:03.141458
5921 18:09:03.141808 TX Vref Scan disable
5922 18:09:03.143476 == TX Byte 0 ==
5923 18:09:03.146654 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5924 18:09:03.150204 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5925 18:09:03.153644 == TX Byte 1 ==
5926 18:09:03.156959 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5927 18:09:03.163202 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5928 18:09:03.163621 ==
5929 18:09:03.167082 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 18:09:03.169763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 18:09:03.170205 ==
5932 18:09:03.170539
5933 18:09:03.170845
5934 18:09:03.173126 TX Vref Scan disable
5935 18:09:03.173544 == TX Byte 0 ==
5936 18:09:03.179688 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 18:09:03.182973 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 18:09:03.183393 == TX Byte 1 ==
5939 18:09:03.189842 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5940 18:09:03.193456 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5941 18:09:03.193975
5942 18:09:03.194441 [DATLAT]
5943 18:09:03.196648 Freq=933, CH1 RK1
5944 18:09:03.197002
5945 18:09:03.197306 DATLAT Default: 0xb
5946 18:09:03.200090 0, 0xFFFF, sum = 0
5947 18:09:03.200517 1, 0xFFFF, sum = 0
5948 18:09:03.203308 2, 0xFFFF, sum = 0
5949 18:09:03.203754 3, 0xFFFF, sum = 0
5950 18:09:03.206319 4, 0xFFFF, sum = 0
5951 18:09:03.206747 5, 0xFFFF, sum = 0
5952 18:09:03.210079 6, 0xFFFF, sum = 0
5953 18:09:03.213280 7, 0xFFFF, sum = 0
5954 18:09:03.213708 8, 0xFFFF, sum = 0
5955 18:09:03.216680 9, 0xFFFF, sum = 0
5956 18:09:03.217125 10, 0x0, sum = 1
5957 18:09:03.217465 11, 0x0, sum = 2
5958 18:09:03.219707 12, 0x0, sum = 3
5959 18:09:03.220179 13, 0x0, sum = 4
5960 18:09:03.223088 best_step = 11
5961 18:09:03.223581
5962 18:09:03.223998 ==
5963 18:09:03.226412 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 18:09:03.229835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 18:09:03.230262 ==
5966 18:09:03.233264 RX Vref Scan: 0
5967 18:09:03.233684
5968 18:09:03.234016 RX Vref 0 -> 0, step: 1
5969 18:09:03.234325
5970 18:09:03.236372 RX Delay -53 -> 252, step: 4
5971 18:09:03.243841 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5972 18:09:03.247286 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5973 18:09:03.250430 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5974 18:09:03.253520 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5975 18:09:03.257030 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5976 18:09:03.263546 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5977 18:09:03.267051 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5978 18:09:03.270406 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5979 18:09:03.273680 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5980 18:09:03.276976 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5981 18:09:03.280376 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5982 18:09:03.287208 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5983 18:09:03.290255 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5984 18:09:03.293484 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5985 18:09:03.296652 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5986 18:09:03.303640 iDelay=199, Bit 15, Center 104 (19 ~ 190) 172
5987 18:09:03.304068 ==
5988 18:09:03.306886 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 18:09:03.310137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 18:09:03.310952 ==
5991 18:09:03.311442 DQS Delay:
5992 18:09:03.313022 DQS0 = 0, DQS1 = 0
5993 18:09:03.313517 DQM Delay:
5994 18:09:03.316780 DQM0 = 104, DQM1 = 96
5995 18:09:03.317212 DQ Delay:
5996 18:09:03.319974 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5997 18:09:03.323253 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5998 18:09:03.326310 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =92
5999 18:09:03.330181 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =104
6000 18:09:03.330605
6001 18:09:03.330993
6002 18:09:03.339728 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
6003 18:09:03.340205 CH1 RK1: MR19=505, MR18=2300
6004 18:09:03.346267 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
6005 18:09:03.349862 [RxdqsGatingPostProcess] freq 933
6006 18:09:03.356003 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 18:09:03.359618 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 18:09:03.363153 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 18:09:03.366211 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 18:09:03.369466 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 18:09:03.372759 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 18:09:03.376677 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 18:09:03.379338 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 18:09:03.382788 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 18:09:03.383338 Pre-setting of DQS Precalculation
6016 18:09:03.389658 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 18:09:03.396199 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 18:09:03.402902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 18:09:03.403339
6020 18:09:03.403669
6021 18:09:03.406057 [Calibration Summary] 1866 Mbps
6022 18:09:03.409356 CH 0, Rank 0
6023 18:09:03.409778 SW Impedance : PASS
6024 18:09:03.412901 DUTY Scan : NO K
6025 18:09:03.415944 ZQ Calibration : PASS
6026 18:09:03.416458 Jitter Meter : NO K
6027 18:09:03.419818 CBT Training : PASS
6028 18:09:03.420246 Write leveling : PASS
6029 18:09:03.422956 RX DQS gating : PASS
6030 18:09:03.426285 RX DQ/DQS(RDDQC) : PASS
6031 18:09:03.426722 TX DQ/DQS : PASS
6032 18:09:03.429319 RX DATLAT : PASS
6033 18:09:03.432530 RX DQ/DQS(Engine): PASS
6034 18:09:03.433163 TX OE : NO K
6035 18:09:03.435891 All Pass.
6036 18:09:03.436482
6037 18:09:03.436901 CH 0, Rank 1
6038 18:09:03.439370 SW Impedance : PASS
6039 18:09:03.439916 DUTY Scan : NO K
6040 18:09:03.442876 ZQ Calibration : PASS
6041 18:09:03.446211 Jitter Meter : NO K
6042 18:09:03.446761 CBT Training : PASS
6043 18:09:03.449393 Write leveling : PASS
6044 18:09:03.452488 RX DQS gating : PASS
6045 18:09:03.452952 RX DQ/DQS(RDDQC) : PASS
6046 18:09:03.455664 TX DQ/DQS : PASS
6047 18:09:03.459272 RX DATLAT : PASS
6048 18:09:03.459692 RX DQ/DQS(Engine): PASS
6049 18:09:03.462493 TX OE : NO K
6050 18:09:03.462915 All Pass.
6051 18:09:03.463248
6052 18:09:03.465486 CH 1, Rank 0
6053 18:09:03.466004 SW Impedance : PASS
6054 18:09:03.469235 DUTY Scan : NO K
6055 18:09:03.472576 ZQ Calibration : PASS
6056 18:09:03.473031 Jitter Meter : NO K
6057 18:09:03.475874 CBT Training : PASS
6058 18:09:03.479025 Write leveling : PASS
6059 18:09:03.479442 RX DQS gating : PASS
6060 18:09:03.482326 RX DQ/DQS(RDDQC) : PASS
6061 18:09:03.482740 TX DQ/DQS : PASS
6062 18:09:03.485775 RX DATLAT : PASS
6063 18:09:03.488932 RX DQ/DQS(Engine): PASS
6064 18:09:03.489527 TX OE : NO K
6065 18:09:03.492109 All Pass.
6066 18:09:03.492519
6067 18:09:03.492875 CH 1, Rank 1
6068 18:09:03.495430 SW Impedance : PASS
6069 18:09:03.495844 DUTY Scan : NO K
6070 18:09:03.498731 ZQ Calibration : PASS
6071 18:09:03.502422 Jitter Meter : NO K
6072 18:09:03.502860 CBT Training : PASS
6073 18:09:03.505400 Write leveling : PASS
6074 18:09:03.508734 RX DQS gating : PASS
6075 18:09:03.509149 RX DQ/DQS(RDDQC) : PASS
6076 18:09:03.512473 TX DQ/DQS : PASS
6077 18:09:03.515720 RX DATLAT : PASS
6078 18:09:03.516189 RX DQ/DQS(Engine): PASS
6079 18:09:03.518688 TX OE : NO K
6080 18:09:03.519253 All Pass.
6081 18:09:03.519599
6082 18:09:03.521670 DramC Write-DBI off
6083 18:09:03.525547 PER_BANK_REFRESH: Hybrid Mode
6084 18:09:03.526103 TX_TRACKING: ON
6085 18:09:03.535390 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 18:09:03.538774 [FAST_K] Save calibration result to emmc
6087 18:09:03.541852 dramc_set_vcore_voltage set vcore to 650000
6088 18:09:03.545353 Read voltage for 400, 6
6089 18:09:03.545883 Vio18 = 0
6090 18:09:03.546230 Vcore = 650000
6091 18:09:03.548612 Vdram = 0
6092 18:09:03.549042 Vddq = 0
6093 18:09:03.549480 Vmddr = 0
6094 18:09:03.555261 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 18:09:03.558524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 18:09:03.561824 MEM_TYPE=3, freq_sel=20
6097 18:09:03.565492 sv_algorithm_assistance_LP4_800
6098 18:09:03.568819 ============ PULL DRAM RESETB DOWN ============
6099 18:09:03.572014 ========== PULL DRAM RESETB DOWN end =========
6100 18:09:03.578612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 18:09:03.582038 ===================================
6102 18:09:03.582626 LPDDR4 DRAM CONFIGURATION
6103 18:09:03.584958 ===================================
6104 18:09:03.588601 EX_ROW_EN[0] = 0x0
6105 18:09:03.591901 EX_ROW_EN[1] = 0x0
6106 18:09:03.592360 LP4Y_EN = 0x0
6107 18:09:03.595132 WORK_FSP = 0x0
6108 18:09:03.595661 WL = 0x2
6109 18:09:03.598569 RL = 0x2
6110 18:09:03.599005 BL = 0x2
6111 18:09:03.601865 RPST = 0x0
6112 18:09:03.602277 RD_PRE = 0x0
6113 18:09:03.605105 WR_PRE = 0x1
6114 18:09:03.605520 WR_PST = 0x0
6115 18:09:03.608370 DBI_WR = 0x0
6116 18:09:03.608824 DBI_RD = 0x0
6117 18:09:03.611739 OTF = 0x1
6118 18:09:03.614909 ===================================
6119 18:09:03.618095 ===================================
6120 18:09:03.618512 ANA top config
6121 18:09:03.621443 ===================================
6122 18:09:03.625062 DLL_ASYNC_EN = 0
6123 18:09:03.628193 ALL_SLAVE_EN = 1
6124 18:09:03.631724 NEW_RANK_MODE = 1
6125 18:09:03.632263 DLL_IDLE_MODE = 1
6126 18:09:03.634693 LP45_APHY_COMB_EN = 1
6127 18:09:03.638061 TX_ODT_DIS = 1
6128 18:09:03.641386 NEW_8X_MODE = 1
6129 18:09:03.645153 ===================================
6130 18:09:03.648022 ===================================
6131 18:09:03.651788 data_rate = 800
6132 18:09:03.652216 CKR = 1
6133 18:09:03.655151 DQ_P2S_RATIO = 4
6134 18:09:03.658218 ===================================
6135 18:09:03.661339 CA_P2S_RATIO = 4
6136 18:09:03.664656 DQ_CA_OPEN = 0
6137 18:09:03.667864 DQ_SEMI_OPEN = 1
6138 18:09:03.671488 CA_SEMI_OPEN = 1
6139 18:09:03.672026 CA_FULL_RATE = 0
6140 18:09:03.674632 DQ_CKDIV4_EN = 0
6141 18:09:03.677943 CA_CKDIV4_EN = 1
6142 18:09:03.681401 CA_PREDIV_EN = 0
6143 18:09:03.684732 PH8_DLY = 0
6144 18:09:03.688027 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 18:09:03.688446 DQ_AAMCK_DIV = 0
6146 18:09:03.691319 CA_AAMCK_DIV = 0
6147 18:09:03.694512 CA_ADMCK_DIV = 4
6148 18:09:03.697792 DQ_TRACK_CA_EN = 0
6149 18:09:03.700977 CA_PICK = 800
6150 18:09:03.704207 CA_MCKIO = 400
6151 18:09:03.707920 MCKIO_SEMI = 400
6152 18:09:03.708435 PLL_FREQ = 3016
6153 18:09:03.711255 DQ_UI_PI_RATIO = 32
6154 18:09:03.714577 CA_UI_PI_RATIO = 32
6155 18:09:03.717813 ===================================
6156 18:09:03.721227 ===================================
6157 18:09:03.724529 memory_type:LPDDR4
6158 18:09:03.724981 GP_NUM : 10
6159 18:09:03.727751 SRAM_EN : 1
6160 18:09:03.730954 MD32_EN : 0
6161 18:09:03.734152 ===================================
6162 18:09:03.734570 [ANA_INIT] >>>>>>>>>>>>>>
6163 18:09:03.737840 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 18:09:03.740664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 18:09:03.744686 ===================================
6166 18:09:03.747824 data_rate = 800,PCW = 0X7400
6167 18:09:03.750928 ===================================
6168 18:09:03.754061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 18:09:03.761039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 18:09:03.770913 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 18:09:03.777323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 18:09:03.780609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 18:09:03.784355 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 18:09:03.784825 [ANA_INIT] flow start
6175 18:09:03.787057 [ANA_INIT] PLL >>>>>>>>
6176 18:09:03.790438 [ANA_INIT] PLL <<<<<<<<
6177 18:09:03.790875 [ANA_INIT] MIDPI >>>>>>>>
6178 18:09:03.794271 [ANA_INIT] MIDPI <<<<<<<<
6179 18:09:03.797699 [ANA_INIT] DLL >>>>>>>>
6180 18:09:03.798116 [ANA_INIT] flow end
6181 18:09:03.803960 ============ LP4 DIFF to SE enter ============
6182 18:09:03.807402 ============ LP4 DIFF to SE exit ============
6183 18:09:03.810687 [ANA_INIT] <<<<<<<<<<<<<
6184 18:09:03.814001 [Flow] Enable top DCM control >>>>>
6185 18:09:03.817236 [Flow] Enable top DCM control <<<<<
6186 18:09:03.817656 Enable DLL master slave shuffle
6187 18:09:03.823834 ==============================================================
6188 18:09:03.826981 Gating Mode config
6189 18:09:03.830229 ==============================================================
6190 18:09:03.834182 Config description:
6191 18:09:03.843783 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 18:09:03.850781 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 18:09:03.854002 SELPH_MODE 0: By rank 1: By Phase
6194 18:09:03.860067 ==============================================================
6195 18:09:03.863660 GAT_TRACK_EN = 0
6196 18:09:03.867022 RX_GATING_MODE = 2
6197 18:09:03.870310 RX_GATING_TRACK_MODE = 2
6198 18:09:03.873341 SELPH_MODE = 1
6199 18:09:03.873785 PICG_EARLY_EN = 1
6200 18:09:03.877099 VALID_LAT_VALUE = 1
6201 18:09:03.883729 ==============================================================
6202 18:09:03.886929 Enter into Gating configuration >>>>
6203 18:09:03.890401 Exit from Gating configuration <<<<
6204 18:09:03.893968 Enter into DVFS_PRE_config >>>>>
6205 18:09:03.903238 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 18:09:03.906604 Exit from DVFS_PRE_config <<<<<
6207 18:09:03.909983 Enter into PICG configuration >>>>
6208 18:09:03.913038 Exit from PICG configuration <<<<
6209 18:09:03.916403 [RX_INPUT] configuration >>>>>
6210 18:09:03.919633 [RX_INPUT] configuration <<<<<
6211 18:09:03.923337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 18:09:03.930229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 18:09:03.936739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 18:09:03.943453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 18:09:03.949638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 18:09:03.952938 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 18:09:03.959908 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 18:09:03.962913 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 18:09:03.966447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 18:09:03.969534 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 18:09:03.976425 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 18:09:03.979720 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 18:09:03.983003 ===================================
6224 18:09:03.986142 LPDDR4 DRAM CONFIGURATION
6225 18:09:03.990061 ===================================
6226 18:09:03.990503 EX_ROW_EN[0] = 0x0
6227 18:09:03.993238 EX_ROW_EN[1] = 0x0
6228 18:09:03.993655 LP4Y_EN = 0x0
6229 18:09:03.996521 WORK_FSP = 0x0
6230 18:09:03.996963 WL = 0x2
6231 18:09:03.999797 RL = 0x2
6232 18:09:04.000210 BL = 0x2
6233 18:09:04.003088 RPST = 0x0
6234 18:09:04.003638 RD_PRE = 0x0
6235 18:09:04.006388 WR_PRE = 0x1
6236 18:09:04.006960 WR_PST = 0x0
6237 18:09:04.009686 DBI_WR = 0x0
6238 18:09:04.013072 DBI_RD = 0x0
6239 18:09:04.013492 OTF = 0x1
6240 18:09:04.016391 ===================================
6241 18:09:04.019878 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 18:09:04.023005 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 18:09:04.029570 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 18:09:04.032864 ===================================
6245 18:09:04.036196 LPDDR4 DRAM CONFIGURATION
6246 18:09:04.039412 ===================================
6247 18:09:04.039830 EX_ROW_EN[0] = 0x10
6248 18:09:04.042691 EX_ROW_EN[1] = 0x0
6249 18:09:04.043298 LP4Y_EN = 0x0
6250 18:09:04.046450 WORK_FSP = 0x0
6251 18:09:04.046918 WL = 0x2
6252 18:09:04.049511 RL = 0x2
6253 18:09:04.049868 BL = 0x2
6254 18:09:04.052537 RPST = 0x0
6255 18:09:04.052663 RD_PRE = 0x0
6256 18:09:04.055848 WR_PRE = 0x1
6257 18:09:04.055930 WR_PST = 0x0
6258 18:09:04.059632 DBI_WR = 0x0
6259 18:09:04.059810 DBI_RD = 0x0
6260 18:09:04.062996 OTF = 0x1
6261 18:09:04.065779 ===================================
6262 18:09:04.072312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 18:09:04.075918 nWR fixed to 30
6264 18:09:04.079262 [ModeRegInit_LP4] CH0 RK0
6265 18:09:04.079389 [ModeRegInit_LP4] CH0 RK1
6266 18:09:04.082561 [ModeRegInit_LP4] CH1 RK0
6267 18:09:04.085932 [ModeRegInit_LP4] CH1 RK1
6268 18:09:04.086035 match AC timing 19
6269 18:09:04.092676 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 18:09:04.096054 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 18:09:04.099202 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 18:09:04.105773 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 18:09:04.109436 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 18:09:04.109878 ==
6275 18:09:04.112695 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 18:09:04.116081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 18:09:04.116729 ==
6278 18:09:04.121965 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 18:09:04.129270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 18:09:04.132955 [CA 0] Center 36 (8~64) winsize 57
6281 18:09:04.136284 [CA 1] Center 36 (8~64) winsize 57
6282 18:09:04.139456 [CA 2] Center 36 (8~64) winsize 57
6283 18:09:04.142449 [CA 3] Center 36 (8~64) winsize 57
6284 18:09:04.142879 [CA 4] Center 36 (8~64) winsize 57
6285 18:09:04.145799 [CA 5] Center 36 (8~64) winsize 57
6286 18:09:04.146223
6287 18:09:04.152211 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 18:09:04.152964
6289 18:09:04.155267 [CATrainingPosCal] consider 1 rank data
6290 18:09:04.158768 u2DelayCellTimex100 = 270/100 ps
6291 18:09:04.161966 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 18:09:04.165281 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 18:09:04.168601 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 18:09:04.172089 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 18:09:04.175222 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 18:09:04.178321 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 18:09:04.178771
6298 18:09:04.181755 CA PerBit enable=1, Macro0, CA PI delay=36
6299 18:09:04.182211
6300 18:09:04.184948 [CBTSetCACLKResult] CA Dly = 36
6301 18:09:04.188542 CS Dly: 1 (0~32)
6302 18:09:04.188996 ==
6303 18:09:04.191754 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 18:09:04.194896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 18:09:04.195316 ==
6306 18:09:04.201717 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 18:09:04.207900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6308 18:09:04.211441 [CA 0] Center 36 (8~64) winsize 57
6309 18:09:04.214656 [CA 1] Center 36 (8~64) winsize 57
6310 18:09:04.215080 [CA 2] Center 36 (8~64) winsize 57
6311 18:09:04.217912 [CA 3] Center 36 (8~64) winsize 57
6312 18:09:04.221224 [CA 4] Center 36 (8~64) winsize 57
6313 18:09:04.224907 [CA 5] Center 36 (8~64) winsize 57
6314 18:09:04.225333
6315 18:09:04.228134 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6316 18:09:04.231238
6317 18:09:04.235200 [CATrainingPosCal] consider 2 rank data
6318 18:09:04.235764 u2DelayCellTimex100 = 270/100 ps
6319 18:09:04.241134 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 18:09:04.245104 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 18:09:04.247905 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 18:09:04.251013 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 18:09:04.254377 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 18:09:04.258182 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 18:09:04.258605
6326 18:09:04.261500 CA PerBit enable=1, Macro0, CA PI delay=36
6327 18:09:04.261923
6328 18:09:04.264749 [CBTSetCACLKResult] CA Dly = 36
6329 18:09:04.268081 CS Dly: 1 (0~32)
6330 18:09:04.268637
6331 18:09:04.271058 ----->DramcWriteLeveling(PI) begin...
6332 18:09:04.271705 ==
6333 18:09:04.274259 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 18:09:04.277635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 18:09:04.278068 ==
6336 18:09:04.281266 Write leveling (Byte 0): 40 => 8
6337 18:09:04.284577 Write leveling (Byte 1): 32 => 0
6338 18:09:04.287524 DramcWriteLeveling(PI) end<-----
6339 18:09:04.287949
6340 18:09:04.288392 ==
6341 18:09:04.291184 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 18:09:04.294457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 18:09:04.294884 ==
6344 18:09:04.297742 [Gating] SW mode calibration
6345 18:09:04.304601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 18:09:04.310997 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 18:09:04.314361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 18:09:04.317295 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 18:09:04.324424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 18:09:04.327582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 18:09:04.330774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 18:09:04.337545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 18:09:04.340832 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 18:09:04.344051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 18:09:04.350614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 18:09:04.351103 Total UI for P1: 0, mck2ui 16
6357 18:09:04.357317 best dqsien dly found for B0: ( 0, 14, 24)
6358 18:09:04.357770 Total UI for P1: 0, mck2ui 16
6359 18:09:04.363761 best dqsien dly found for B1: ( 0, 14, 24)
6360 18:09:04.367084 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 18:09:04.370495 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 18:09:04.371030
6363 18:09:04.373722 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 18:09:04.377316 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 18:09:04.380146 [Gating] SW calibration Done
6366 18:09:04.380745 ==
6367 18:09:04.383488 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 18:09:04.386944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 18:09:04.387305 ==
6370 18:09:04.390153 RX Vref Scan: 0
6371 18:09:04.390377
6372 18:09:04.390548 RX Vref 0 -> 0, step: 1
6373 18:09:04.390706
6374 18:09:04.393229 RX Delay -410 -> 252, step: 16
6375 18:09:04.400061 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6376 18:09:04.403146 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6377 18:09:04.406484 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6378 18:09:04.410162 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6379 18:09:04.416393 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6380 18:09:04.419590 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6381 18:09:04.422955 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6382 18:09:04.426193 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6383 18:09:04.433080 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6384 18:09:04.436234 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6385 18:09:04.439544 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6386 18:09:04.442766 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6387 18:09:04.449404 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6388 18:09:04.452879 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6389 18:09:04.456025 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6390 18:09:04.462592 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6391 18:09:04.462769 ==
6392 18:09:04.466365 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 18:09:04.469783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 18:09:04.469959 ==
6395 18:09:04.470096 DQS Delay:
6396 18:09:04.472956 DQS0 = 27, DQS1 = 43
6397 18:09:04.473161 DQM Delay:
6398 18:09:04.476070 DQM0 = 12, DQM1 = 12
6399 18:09:04.476288 DQ Delay:
6400 18:09:04.479485 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6401 18:09:04.482731 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6402 18:09:04.486015 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6403 18:09:04.489803 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6404 18:09:04.490118
6405 18:09:04.490359
6406 18:09:04.490586 ==
6407 18:09:04.493093 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 18:09:04.496166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 18:09:04.496518 ==
6410 18:09:04.496815
6411 18:09:04.497052
6412 18:09:04.499286 TX Vref Scan disable
6413 18:09:04.499759 == TX Byte 0 ==
6414 18:09:04.506059 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 18:09:04.509654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 18:09:04.510084 == TX Byte 1 ==
6417 18:09:04.516132 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 18:09:04.519430 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 18:09:04.519733 ==
6420 18:09:04.522584 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 18:09:04.526072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 18:09:04.526449 ==
6423 18:09:04.526731
6424 18:09:04.526962
6425 18:09:04.529407 TX Vref Scan disable
6426 18:09:04.532759 == TX Byte 0 ==
6427 18:09:04.536127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 18:09:04.539171 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 18:09:04.542580 == TX Byte 1 ==
6430 18:09:04.545849 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6431 18:09:04.548924 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6432 18:09:04.549390
6433 18:09:04.549829 [DATLAT]
6434 18:09:04.552271 Freq=400, CH0 RK0
6435 18:09:04.552712
6436 18:09:04.555755 DATLAT Default: 0xf
6437 18:09:04.556069 0, 0xFFFF, sum = 0
6438 18:09:04.558879 1, 0xFFFF, sum = 0
6439 18:09:04.559198 2, 0xFFFF, sum = 0
6440 18:09:04.562321 3, 0xFFFF, sum = 0
6441 18:09:04.562705 4, 0xFFFF, sum = 0
6442 18:09:04.565420 5, 0xFFFF, sum = 0
6443 18:09:04.565726 6, 0xFFFF, sum = 0
6444 18:09:04.569240 7, 0xFFFF, sum = 0
6445 18:09:04.569585 8, 0xFFFF, sum = 0
6446 18:09:04.572303 9, 0xFFFF, sum = 0
6447 18:09:04.572754 10, 0xFFFF, sum = 0
6448 18:09:04.575465 11, 0xFFFF, sum = 0
6449 18:09:04.575790 12, 0xFFFF, sum = 0
6450 18:09:04.578977 13, 0x0, sum = 1
6451 18:09:04.579301 14, 0x0, sum = 2
6452 18:09:04.582220 15, 0x0, sum = 3
6453 18:09:04.582664 16, 0x0, sum = 4
6454 18:09:04.585410 best_step = 14
6455 18:09:04.585862
6456 18:09:04.586270 ==
6457 18:09:04.588691 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 18:09:04.592260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 18:09:04.592754 ==
6460 18:09:04.595424 RX Vref Scan: 1
6461 18:09:04.595864
6462 18:09:04.596187 RX Vref 0 -> 0, step: 1
6463 18:09:04.596435
6464 18:09:04.598542 RX Delay -327 -> 252, step: 8
6465 18:09:04.598896
6466 18:09:04.602406 Set Vref, RX VrefLevel [Byte0]: 59
6467 18:09:04.605459 [Byte1]: 48
6468 18:09:04.609812
6469 18:09:04.610131 Final RX Vref Byte 0 = 59 to rank0
6470 18:09:04.613107 Final RX Vref Byte 1 = 48 to rank0
6471 18:09:04.616453 Final RX Vref Byte 0 = 59 to rank1
6472 18:09:04.619587 Final RX Vref Byte 1 = 48 to rank1==
6473 18:09:04.623061 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 18:09:04.629635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 18:09:04.630214 ==
6476 18:09:04.630646 DQS Delay:
6477 18:09:04.632844 DQS0 = 28, DQS1 = 48
6478 18:09:04.633293 DQM Delay:
6479 18:09:04.633728 DQM0 = 12, DQM1 = 15
6480 18:09:04.636022 DQ Delay:
6481 18:09:04.639465 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6482 18:09:04.639791 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6483 18:09:04.642837 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6484 18:09:04.646081 DQ12 =24, DQ13 =16, DQ14 =28, DQ15 =24
6485 18:09:04.646407
6486 18:09:04.649821
6487 18:09:04.656160 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
6488 18:09:04.659308 CH0 RK0: MR19=C0C, MR18=B0A7
6489 18:09:04.666323 CH0_RK0: MR19=0xC0C, MR18=0xB0A7, DQSOSC=387, MR23=63, INC=394, DEC=262
6490 18:09:04.666650 ==
6491 18:09:04.669582 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 18:09:04.672917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 18:09:04.673242 ==
6494 18:09:04.675999 [Gating] SW mode calibration
6495 18:09:04.682542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 18:09:04.689595 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 18:09:04.693029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 18:09:04.696135 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 18:09:04.702524 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 18:09:04.706138 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 18:09:04.709458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 18:09:04.712812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 18:09:04.719622 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 18:09:04.722924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 18:09:04.726273 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 18:09:04.729379 Total UI for P1: 0, mck2ui 16
6507 18:09:04.732657 best dqsien dly found for B0: ( 0, 14, 24)
6508 18:09:04.736463 Total UI for P1: 0, mck2ui 16
6509 18:09:04.739686 best dqsien dly found for B1: ( 0, 14, 24)
6510 18:09:04.743418 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 18:09:04.746322 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 18:09:04.746752
6513 18:09:04.752777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 18:09:04.756053 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 18:09:04.759802 [Gating] SW calibration Done
6516 18:09:04.760285 ==
6517 18:09:04.762630 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 18:09:04.766027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 18:09:04.766443 ==
6520 18:09:04.766772 RX Vref Scan: 0
6521 18:09:04.767075
6522 18:09:04.769305 RX Vref 0 -> 0, step: 1
6523 18:09:04.769719
6524 18:09:04.772637 RX Delay -410 -> 252, step: 16
6525 18:09:04.776186 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6526 18:09:04.783148 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6527 18:09:04.785953 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6528 18:09:04.789208 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6529 18:09:04.793092 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6530 18:09:04.799474 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6531 18:09:04.802700 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6532 18:09:04.805821 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6533 18:09:04.809473 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6534 18:09:04.815889 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6535 18:09:04.819542 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6536 18:09:04.823007 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6537 18:09:04.825814 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6538 18:09:04.832974 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6539 18:09:04.835582 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6540 18:09:04.839353 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6541 18:09:04.839773 ==
6542 18:09:04.842750 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 18:09:04.846340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 18:09:04.849301 ==
6545 18:09:04.849724 DQS Delay:
6546 18:09:04.850058 DQS0 = 27, DQS1 = 43
6547 18:09:04.852711 DQM Delay:
6548 18:09:04.853274 DQM0 = 9, DQM1 = 16
6549 18:09:04.855634 DQ Delay:
6550 18:09:04.856052 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6551 18:09:04.859073 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6552 18:09:04.862682 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6553 18:09:04.865965 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6554 18:09:04.866436
6555 18:09:04.866796
6556 18:09:04.867218 ==
6557 18:09:04.868986 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 18:09:04.875833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 18:09:04.876302 ==
6560 18:09:04.876713
6561 18:09:04.877068
6562 18:09:04.878535 TX Vref Scan disable
6563 18:09:04.878978 == TX Byte 0 ==
6564 18:09:04.882259 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 18:09:04.888694 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 18:09:04.889161 == TX Byte 1 ==
6567 18:09:04.892302 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6568 18:09:04.895487 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6569 18:09:04.898774 ==
6570 18:09:04.902310 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 18:09:04.905436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 18:09:04.905853 ==
6573 18:09:04.906246
6574 18:09:04.906632
6575 18:09:04.909010 TX Vref Scan disable
6576 18:09:04.909506 == TX Byte 0 ==
6577 18:09:04.912074 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6578 18:09:04.918786 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6579 18:09:04.919201 == TX Byte 1 ==
6580 18:09:04.922047 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6581 18:09:04.928445 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6582 18:09:04.928906
6583 18:09:04.929236 [DATLAT]
6584 18:09:04.929537 Freq=400, CH0 RK1
6585 18:09:04.929827
6586 18:09:04.932402 DATLAT Default: 0xe
6587 18:09:04.932968 0, 0xFFFF, sum = 0
6588 18:09:04.935204 1, 0xFFFF, sum = 0
6589 18:09:04.938399 2, 0xFFFF, sum = 0
6590 18:09:04.938826 3, 0xFFFF, sum = 0
6591 18:09:04.941979 4, 0xFFFF, sum = 0
6592 18:09:04.942508 5, 0xFFFF, sum = 0
6593 18:09:04.945257 6, 0xFFFF, sum = 0
6594 18:09:04.945680 7, 0xFFFF, sum = 0
6595 18:09:04.948641 8, 0xFFFF, sum = 0
6596 18:09:04.949061 9, 0xFFFF, sum = 0
6597 18:09:04.951820 10, 0xFFFF, sum = 0
6598 18:09:04.952270 11, 0xFFFF, sum = 0
6599 18:09:04.955126 12, 0xFFFF, sum = 0
6600 18:09:04.955572 13, 0x0, sum = 1
6601 18:09:04.958546 14, 0x0, sum = 2
6602 18:09:04.958963 15, 0x0, sum = 3
6603 18:09:04.962068 16, 0x0, sum = 4
6604 18:09:04.962549 best_step = 14
6605 18:09:04.962877
6606 18:09:04.963179 ==
6607 18:09:04.965752 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 18:09:04.969252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 18:09:04.969810 ==
6610 18:09:04.972625 RX Vref Scan: 0
6611 18:09:04.973170
6612 18:09:04.975780 RX Vref 0 -> 0, step: 1
6613 18:09:04.976302
6614 18:09:04.976685 RX Delay -327 -> 252, step: 8
6615 18:09:04.983989 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6616 18:09:04.987224 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6617 18:09:04.990552 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6618 18:09:04.993698 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6619 18:09:05.001105 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6620 18:09:05.004384 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6621 18:09:05.007073 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6622 18:09:05.010278 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6623 18:09:05.016839 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6624 18:09:05.020669 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6625 18:09:05.023734 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6626 18:09:05.030332 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6627 18:09:05.033537 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6628 18:09:05.036807 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6629 18:09:05.040042 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6630 18:09:05.046794 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6631 18:09:05.047215 ==
6632 18:09:05.050374 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 18:09:05.053878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 18:09:05.054299 ==
6635 18:09:05.054632 DQS Delay:
6636 18:09:05.057031 DQS0 = 28, DQS1 = 40
6637 18:09:05.057451 DQM Delay:
6638 18:09:05.060351 DQM0 = 10, DQM1 = 12
6639 18:09:05.060924 DQ Delay:
6640 18:09:05.063411 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6641 18:09:05.066817 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6642 18:09:05.070034 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6643 18:09:05.073534 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6644 18:09:05.073950
6645 18:09:05.074277
6646 18:09:05.079891 [DQSOSCAuto] RK1, (LSB)MR18= 0xb365, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 387 ps
6647 18:09:05.083303 CH0 RK1: MR19=C0C, MR18=B365
6648 18:09:05.089758 CH0_RK1: MR19=0xC0C, MR18=0xB365, DQSOSC=387, MR23=63, INC=394, DEC=262
6649 18:09:05.093116 [RxdqsGatingPostProcess] freq 400
6650 18:09:05.099461 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 18:09:05.102707 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 18:09:05.106102 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 18:09:05.109344 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 18:09:05.112397 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 18:09:05.112878 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 18:09:05.116095 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 18:09:05.119210 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 18:09:05.122862 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 18:09:05.125945 Pre-setting of DQS Precalculation
6660 18:09:05.132243 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 18:09:05.132742 ==
6662 18:09:05.135410 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 18:09:05.138989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 18:09:05.139292 ==
6665 18:09:05.145501 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 18:09:05.152378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6667 18:09:05.155769 [CA 0] Center 36 (8~64) winsize 57
6668 18:09:05.156183 [CA 1] Center 36 (8~64) winsize 57
6669 18:09:05.159022 [CA 2] Center 36 (8~64) winsize 57
6670 18:09:05.162320 [CA 3] Center 36 (8~64) winsize 57
6671 18:09:05.166194 [CA 4] Center 36 (8~64) winsize 57
6672 18:09:05.169310 [CA 5] Center 36 (8~64) winsize 57
6673 18:09:05.169890
6674 18:09:05.172447 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6675 18:09:05.172943
6676 18:09:05.179041 [CATrainingPosCal] consider 1 rank data
6677 18:09:05.179663 u2DelayCellTimex100 = 270/100 ps
6678 18:09:05.185675 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 18:09:05.188971 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 18:09:05.192159 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 18:09:05.195627 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 18:09:05.198872 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 18:09:05.202058 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 18:09:05.202480
6685 18:09:05.205699 CA PerBit enable=1, Macro0, CA PI delay=36
6686 18:09:05.206123
6687 18:09:05.208932 [CBTSetCACLKResult] CA Dly = 36
6688 18:09:05.212054 CS Dly: 1 (0~32)
6689 18:09:05.212492 ==
6690 18:09:05.215340 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 18:09:05.218839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 18:09:05.219264 ==
6693 18:09:05.225551 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 18:09:05.228843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6695 18:09:05.231789 [CA 0] Center 36 (8~64) winsize 57
6696 18:09:05.235226 [CA 1] Center 36 (8~64) winsize 57
6697 18:09:05.238494 [CA 2] Center 36 (8~64) winsize 57
6698 18:09:05.242233 [CA 3] Center 36 (8~64) winsize 57
6699 18:09:05.245296 [CA 4] Center 36 (8~64) winsize 57
6700 18:09:05.248441 [CA 5] Center 36 (8~64) winsize 57
6701 18:09:05.248911
6702 18:09:05.252042 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6703 18:09:05.252466
6704 18:09:05.255257 [CATrainingPosCal] consider 2 rank data
6705 18:09:05.258844 u2DelayCellTimex100 = 270/100 ps
6706 18:09:05.262503 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 18:09:05.265486 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 18:09:05.268664 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 18:09:05.272385 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 18:09:05.278875 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 18:09:05.281853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 18:09:05.282272
6713 18:09:05.285189 CA PerBit enable=1, Macro0, CA PI delay=36
6714 18:09:05.285623
6715 18:09:05.288366 [CBTSetCACLKResult] CA Dly = 36
6716 18:09:05.288825 CS Dly: 1 (0~32)
6717 18:09:05.289159
6718 18:09:05.291485 ----->DramcWriteLeveling(PI) begin...
6719 18:09:05.291906 ==
6720 18:09:05.294701 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 18:09:05.301811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 18:09:05.302242 ==
6723 18:09:05.305043 Write leveling (Byte 0): 40 => 8
6724 18:09:05.308213 Write leveling (Byte 1): 32 => 0
6725 18:09:05.308675 DramcWriteLeveling(PI) end<-----
6726 18:09:05.309098
6727 18:09:05.311483 ==
6728 18:09:05.315329 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 18:09:05.318466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 18:09:05.318887 ==
6731 18:09:05.321714 [Gating] SW mode calibration
6732 18:09:05.328606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 18:09:05.331584 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 18:09:05.338395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 18:09:05.341747 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 18:09:05.345043 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 18:09:05.351482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 18:09:05.354910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 18:09:05.358484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 18:09:05.365184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 18:09:05.368400 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 18:09:05.371585 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 18:09:05.374970 Total UI for P1: 0, mck2ui 16
6744 18:09:05.378130 best dqsien dly found for B0: ( 0, 14, 24)
6745 18:09:05.381329 Total UI for P1: 0, mck2ui 16
6746 18:09:05.384795 best dqsien dly found for B1: ( 0, 14, 24)
6747 18:09:05.388040 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 18:09:05.391494 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 18:09:05.391910
6750 18:09:05.394712 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 18:09:05.401356 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 18:09:05.401807 [Gating] SW calibration Done
6753 18:09:05.404935 ==
6754 18:09:05.405493 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 18:09:05.411484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 18:09:05.412011 ==
6757 18:09:05.412352 RX Vref Scan: 0
6758 18:09:05.412708
6759 18:09:05.414901 RX Vref 0 -> 0, step: 1
6760 18:09:05.415315
6761 18:09:05.417863 RX Delay -410 -> 252, step: 16
6762 18:09:05.421226 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6763 18:09:05.425141 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6764 18:09:05.431012 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6765 18:09:05.434587 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6766 18:09:05.437751 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6767 18:09:05.441456 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6768 18:09:05.448014 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6769 18:09:05.451279 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6770 18:09:05.454366 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6771 18:09:05.457806 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6772 18:09:05.464837 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6773 18:09:05.468048 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6774 18:09:05.471171 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6775 18:09:05.474453 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6776 18:09:05.481448 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6777 18:09:05.484805 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6778 18:09:05.485263 ==
6779 18:09:05.487863 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 18:09:05.491263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 18:09:05.491687 ==
6782 18:09:05.494288 DQS Delay:
6783 18:09:05.494819 DQS0 = 27, DQS1 = 43
6784 18:09:05.497659 DQM Delay:
6785 18:09:05.498142 DQM0 = 11, DQM1 = 17
6786 18:09:05.498510 DQ Delay:
6787 18:09:05.500931 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6788 18:09:05.504419 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =0
6789 18:09:05.507452 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6790 18:09:05.510823 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6791 18:09:05.511348
6792 18:09:05.511804
6793 18:09:05.512305 ==
6794 18:09:05.514150 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 18:09:05.521141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 18:09:05.521558 ==
6797 18:09:05.521886
6798 18:09:05.522189
6799 18:09:05.522477 TX Vref Scan disable
6800 18:09:05.524250 == TX Byte 0 ==
6801 18:09:05.527589 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 18:09:05.530891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 18:09:05.534208 == TX Byte 1 ==
6804 18:09:05.537297 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6805 18:09:05.540714 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6806 18:09:05.541141 ==
6807 18:09:05.544227 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 18:09:05.550752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 18:09:05.551253 ==
6810 18:09:05.551600
6811 18:09:05.551912
6812 18:09:05.552235 TX Vref Scan disable
6813 18:09:05.553947 == TX Byte 0 ==
6814 18:09:05.557701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 18:09:05.560744 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 18:09:05.563986 == TX Byte 1 ==
6817 18:09:05.567248 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6818 18:09:05.570872 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6819 18:09:05.574160
6820 18:09:05.574533 [DATLAT]
6821 18:09:05.574876 Freq=400, CH1 RK0
6822 18:09:05.575184
6823 18:09:05.577337 DATLAT Default: 0xf
6824 18:09:05.577705 0, 0xFFFF, sum = 0
6825 18:09:05.580617 1, 0xFFFF, sum = 0
6826 18:09:05.581116 2, 0xFFFF, sum = 0
6827 18:09:05.583775 3, 0xFFFF, sum = 0
6828 18:09:05.584178 4, 0xFFFF, sum = 0
6829 18:09:05.587065 5, 0xFFFF, sum = 0
6830 18:09:05.590955 6, 0xFFFF, sum = 0
6831 18:09:05.591379 7, 0xFFFF, sum = 0
6832 18:09:05.594176 8, 0xFFFF, sum = 0
6833 18:09:05.594601 9, 0xFFFF, sum = 0
6834 18:09:05.597465 10, 0xFFFF, sum = 0
6835 18:09:05.598094 11, 0xFFFF, sum = 0
6836 18:09:05.600683 12, 0xFFFF, sum = 0
6837 18:09:05.601111 13, 0x0, sum = 1
6838 18:09:05.604094 14, 0x0, sum = 2
6839 18:09:05.604617 15, 0x0, sum = 3
6840 18:09:05.607189 16, 0x0, sum = 4
6841 18:09:05.607630 best_step = 14
6842 18:09:05.607963
6843 18:09:05.608269 ==
6844 18:09:05.610283 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 18:09:05.613506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 18:09:05.613860 ==
6847 18:09:05.617084 RX Vref Scan: 1
6848 18:09:05.617169
6849 18:09:05.620343 RX Vref 0 -> 0, step: 1
6850 18:09:05.620426
6851 18:09:05.620492 RX Delay -327 -> 252, step: 8
6852 18:09:05.623565
6853 18:09:05.623648 Set Vref, RX VrefLevel [Byte0]: 54
6854 18:09:05.626764 [Byte1]: 49
6855 18:09:05.632126
6856 18:09:05.632210 Final RX Vref Byte 0 = 54 to rank0
6857 18:09:05.635891 Final RX Vref Byte 1 = 49 to rank0
6858 18:09:05.638715 Final RX Vref Byte 0 = 54 to rank1
6859 18:09:05.642357 Final RX Vref Byte 1 = 49 to rank1==
6860 18:09:05.645424 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 18:09:05.652380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 18:09:05.652464 ==
6863 18:09:05.652531 DQS Delay:
6864 18:09:05.655225 DQS0 = 28, DQS1 = 40
6865 18:09:05.655310 DQM Delay:
6866 18:09:05.655377 DQM0 = 8, DQM1 = 12
6867 18:09:05.658919 DQ Delay:
6868 18:09:05.662052 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6869 18:09:05.662136 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6870 18:09:05.665290 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6871 18:09:05.668554 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6872 18:09:05.668640
6873 18:09:05.668705
6874 18:09:05.678516 [DQSOSCAuto] RK0, (LSB)MR18= 0x94ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6875 18:09:05.681816 CH1 RK0: MR19=C0C, MR18=94CE
6876 18:09:05.688300 CH1_RK0: MR19=0xC0C, MR18=0x94CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6877 18:09:05.688383 ==
6878 18:09:05.692139 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 18:09:05.695405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 18:09:05.695488 ==
6881 18:09:05.698740 [Gating] SW mode calibration
6882 18:09:05.705255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 18:09:05.711672 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 18:09:05.714883 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 18:09:05.718142 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 18:09:05.721912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 18:09:05.728238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 18:09:05.731562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 18:09:05.735138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 18:09:05.741518 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 18:09:05.744753 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 18:09:05.748273 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 18:09:05.751680 Total UI for P1: 0, mck2ui 16
6894 18:09:05.755050 best dqsien dly found for B0: ( 0, 14, 24)
6895 18:09:05.758161 Total UI for P1: 0, mck2ui 16
6896 18:09:05.761688 best dqsien dly found for B1: ( 0, 14, 24)
6897 18:09:05.764957 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 18:09:05.771766 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 18:09:05.771846
6900 18:09:05.774871 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 18:09:05.778015 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 18:09:05.781751 [Gating] SW calibration Done
6903 18:09:05.781851 ==
6904 18:09:05.784866 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 18:09:05.788085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 18:09:05.788192 ==
6907 18:09:05.791357 RX Vref Scan: 0
6908 18:09:05.791433
6909 18:09:05.791525 RX Vref 0 -> 0, step: 1
6910 18:09:05.791585
6911 18:09:05.794743 RX Delay -410 -> 252, step: 16
6912 18:09:05.797976 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6913 18:09:05.804474 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6914 18:09:05.807802 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6915 18:09:05.811504 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6916 18:09:05.814706 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6917 18:09:05.821286 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6918 18:09:05.824488 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6919 18:09:05.827868 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6920 18:09:05.831148 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6921 18:09:05.837969 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6922 18:09:05.841278 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6923 18:09:05.844701 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6924 18:09:05.847802 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6925 18:09:05.854659 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6926 18:09:05.858152 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6927 18:09:05.861315 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6928 18:09:05.861463 ==
6929 18:09:05.864471 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 18:09:05.871021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 18:09:05.871106 ==
6932 18:09:05.871172 DQS Delay:
6933 18:09:05.874628 DQS0 = 35, DQS1 = 35
6934 18:09:05.874711 DQM Delay:
6935 18:09:05.874777 DQM0 = 17, DQM1 = 13
6936 18:09:05.877937 DQ Delay:
6937 18:09:05.881051 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6938 18:09:05.884715 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6939 18:09:05.884806 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6940 18:09:05.887864 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6941 18:09:05.891155
6942 18:09:05.891238
6943 18:09:05.891302 ==
6944 18:09:05.894304 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 18:09:05.897569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 18:09:05.897652 ==
6947 18:09:05.897717
6948 18:09:05.897778
6949 18:09:05.900830 TX Vref Scan disable
6950 18:09:05.900913 == TX Byte 0 ==
6951 18:09:05.904711 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 18:09:05.911187 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 18:09:05.911271 == TX Byte 1 ==
6954 18:09:05.914526 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6955 18:09:05.920931 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6956 18:09:05.921014 ==
6957 18:09:05.924091 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 18:09:05.927825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 18:09:05.927908 ==
6960 18:09:05.927973
6961 18:09:05.928033
6962 18:09:05.931103 TX Vref Scan disable
6963 18:09:05.931185 == TX Byte 0 ==
6964 18:09:05.934396 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6965 18:09:05.940716 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6966 18:09:05.940799 == TX Byte 1 ==
6967 18:09:05.944266 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6968 18:09:05.950859 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6969 18:09:05.950942
6970 18:09:05.951007 [DATLAT]
6971 18:09:05.951067 Freq=400, CH1 RK1
6972 18:09:05.951124
6973 18:09:05.953950 DATLAT Default: 0xe
6974 18:09:05.957699 0, 0xFFFF, sum = 0
6975 18:09:05.957790 1, 0xFFFF, sum = 0
6976 18:09:05.960702 2, 0xFFFF, sum = 0
6977 18:09:05.960815 3, 0xFFFF, sum = 0
6978 18:09:05.963727 4, 0xFFFF, sum = 0
6979 18:09:05.963811 5, 0xFFFF, sum = 0
6980 18:09:05.967386 6, 0xFFFF, sum = 0
6981 18:09:05.967480 7, 0xFFFF, sum = 0
6982 18:09:05.970537 8, 0xFFFF, sum = 0
6983 18:09:05.970621 9, 0xFFFF, sum = 0
6984 18:09:05.973686 10, 0xFFFF, sum = 0
6985 18:09:05.973771 11, 0xFFFF, sum = 0
6986 18:09:05.977388 12, 0xFFFF, sum = 0
6987 18:09:05.977473 13, 0x0, sum = 1
6988 18:09:05.980440 14, 0x0, sum = 2
6989 18:09:05.980523 15, 0x0, sum = 3
6990 18:09:05.983529 16, 0x0, sum = 4
6991 18:09:05.983612 best_step = 14
6992 18:09:05.983676
6993 18:09:05.983736 ==
6994 18:09:05.987089 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 18:09:05.993723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 18:09:05.993806 ==
6997 18:09:05.993872 RX Vref Scan: 0
6998 18:09:05.993932
6999 18:09:05.996938 RX Vref 0 -> 0, step: 1
7000 18:09:05.997019
7001 18:09:06.000150 RX Delay -311 -> 252, step: 8
7002 18:09:06.007180 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7003 18:09:06.010405 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7004 18:09:06.013650 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7005 18:09:06.016954 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
7006 18:09:06.023950 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7007 18:09:06.027303 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7008 18:09:06.030028 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7009 18:09:06.033809 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7010 18:09:06.040302 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7011 18:09:06.043637 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7012 18:09:06.046707 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7013 18:09:06.050453 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
7014 18:09:06.056884 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7015 18:09:06.059924 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7016 18:09:06.063172 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7017 18:09:06.066789 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7018 18:09:06.069773 ==
7019 18:09:06.069854 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 18:09:06.076690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 18:09:06.076771 ==
7022 18:09:06.076860 DQS Delay:
7023 18:09:06.079882 DQS0 = 32, DQS1 = 36
7024 18:09:06.079998 DQM Delay:
7025 18:09:06.083240 DQM0 = 13, DQM1 = 10
7026 18:09:06.083344 DQ Delay:
7027 18:09:06.086328 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
7028 18:09:06.090052 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
7029 18:09:06.093141 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7030 18:09:06.096491 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7031 18:09:06.096617
7032 18:09:06.096684
7033 18:09:06.103052 [DQSOSCAuto] RK1, (LSB)MR18= 0xac54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7034 18:09:06.106759 CH1 RK1: MR19=C0C, MR18=AC54
7035 18:09:06.113211 CH1_RK1: MR19=0xC0C, MR18=0xAC54, DQSOSC=388, MR23=63, INC=392, DEC=261
7036 18:09:06.116354 [RxdqsGatingPostProcess] freq 400
7037 18:09:06.119630 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 18:09:06.122876 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 18:09:06.126116 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 18:09:06.129902 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 18:09:06.133109 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 18:09:06.136255 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 18:09:06.139534 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 18:09:06.142724 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 18:09:06.146058 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 18:09:06.149746 Pre-setting of DQS Precalculation
7047 18:09:06.152928 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 18:09:06.162717 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 18:09:06.169211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 18:09:06.169295
7051 18:09:06.169359
7052 18:09:06.172909 [Calibration Summary] 800 Mbps
7053 18:09:06.172991 CH 0, Rank 0
7054 18:09:06.175949 SW Impedance : PASS
7055 18:09:06.176033 DUTY Scan : NO K
7056 18:09:06.179498 ZQ Calibration : PASS
7057 18:09:06.182594 Jitter Meter : NO K
7058 18:09:06.182680 CBT Training : PASS
7059 18:09:06.186185 Write leveling : PASS
7060 18:09:06.189188 RX DQS gating : PASS
7061 18:09:06.189268 RX DQ/DQS(RDDQC) : PASS
7062 18:09:06.193007 TX DQ/DQS : PASS
7063 18:09:06.196153 RX DATLAT : PASS
7064 18:09:06.196228 RX DQ/DQS(Engine): PASS
7065 18:09:06.199294 TX OE : NO K
7066 18:09:06.199371 All Pass.
7067 18:09:06.199437
7068 18:09:06.202675 CH 0, Rank 1
7069 18:09:06.202755 SW Impedance : PASS
7070 18:09:06.205994 DUTY Scan : NO K
7071 18:09:06.206061 ZQ Calibration : PASS
7072 18:09:06.209335 Jitter Meter : NO K
7073 18:09:06.212603 CBT Training : PASS
7074 18:09:06.212672 Write leveling : NO K
7075 18:09:06.216412 RX DQS gating : PASS
7076 18:09:06.219122 RX DQ/DQS(RDDQC) : PASS
7077 18:09:06.219189 TX DQ/DQS : PASS
7078 18:09:06.222866 RX DATLAT : PASS
7079 18:09:06.226197 RX DQ/DQS(Engine): PASS
7080 18:09:06.226278 TX OE : NO K
7081 18:09:06.229516 All Pass.
7082 18:09:06.229592
7083 18:09:06.229653 CH 1, Rank 0
7084 18:09:06.232858 SW Impedance : PASS
7085 18:09:06.232963 DUTY Scan : NO K
7086 18:09:06.235616 ZQ Calibration : PASS
7087 18:09:06.239263 Jitter Meter : NO K
7088 18:09:06.239334 CBT Training : PASS
7089 18:09:06.242690 Write leveling : PASS
7090 18:09:06.246087 RX DQS gating : PASS
7091 18:09:06.246168 RX DQ/DQS(RDDQC) : PASS
7092 18:09:06.249343 TX DQ/DQS : PASS
7093 18:09:06.252601 RX DATLAT : PASS
7094 18:09:06.252688 RX DQ/DQS(Engine): PASS
7095 18:09:06.255790 TX OE : NO K
7096 18:09:06.255882 All Pass.
7097 18:09:06.255955
7098 18:09:06.259549 CH 1, Rank 1
7099 18:09:06.259730 SW Impedance : PASS
7100 18:09:06.262617 DUTY Scan : NO K
7101 18:09:06.262771 ZQ Calibration : PASS
7102 18:09:06.266103 Jitter Meter : NO K
7103 18:09:06.269661 CBT Training : PASS
7104 18:09:06.269853 Write leveling : NO K
7105 18:09:06.272356 RX DQS gating : PASS
7106 18:09:06.276060 RX DQ/DQS(RDDQC) : PASS
7107 18:09:06.276243 TX DQ/DQS : PASS
7108 18:09:06.279389 RX DATLAT : PASS
7109 18:09:06.282527 RX DQ/DQS(Engine): PASS
7110 18:09:06.282679 TX OE : NO K
7111 18:09:06.285756 All Pass.
7112 18:09:06.285926
7113 18:09:06.286061 DramC Write-DBI off
7114 18:09:06.288980 PER_BANK_REFRESH: Hybrid Mode
7115 18:09:06.289201 TX_TRACKING: ON
7116 18:09:06.298796 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 18:09:06.302376 [FAST_K] Save calibration result to emmc
7118 18:09:06.305719 dramc_set_vcore_voltage set vcore to 725000
7119 18:09:06.308874 Read voltage for 1600, 0
7120 18:09:06.308963 Vio18 = 0
7121 18:09:06.312542 Vcore = 725000
7122 18:09:06.312665 Vdram = 0
7123 18:09:06.312729 Vddq = 0
7124 18:09:06.315939 Vmddr = 0
7125 18:09:06.319021 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 18:09:06.325733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 18:09:06.325827 MEM_TYPE=3, freq_sel=13
7128 18:09:06.329232 sv_algorithm_assistance_LP4_3733
7129 18:09:06.335740 ============ PULL DRAM RESETB DOWN ============
7130 18:09:06.338967 ========== PULL DRAM RESETB DOWN end =========
7131 18:09:06.342363 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 18:09:06.345903 ===================================
7133 18:09:06.349118 LPDDR4 DRAM CONFIGURATION
7134 18:09:06.352674 ===================================
7135 18:09:06.352865 EX_ROW_EN[0] = 0x0
7136 18:09:06.355609 EX_ROW_EN[1] = 0x0
7137 18:09:06.358785 LP4Y_EN = 0x0
7138 18:09:06.358911 WORK_FSP = 0x1
7139 18:09:06.362524 WL = 0x5
7140 18:09:06.362743 RL = 0x5
7141 18:09:06.365550 BL = 0x2
7142 18:09:06.365728 RPST = 0x0
7143 18:09:06.368783 RD_PRE = 0x0
7144 18:09:06.368939 WR_PRE = 0x1
7145 18:09:06.372121 WR_PST = 0x1
7146 18:09:06.372300 DBI_WR = 0x0
7147 18:09:06.375467 DBI_RD = 0x0
7148 18:09:06.375677 OTF = 0x1
7149 18:09:06.378711 ===================================
7150 18:09:06.382093 ===================================
7151 18:09:06.385229 ANA top config
7152 18:09:06.388735 ===================================
7153 18:09:06.389096 DLL_ASYNC_EN = 0
7154 18:09:06.392347 ALL_SLAVE_EN = 0
7155 18:09:06.395637 NEW_RANK_MODE = 1
7156 18:09:06.398867 DLL_IDLE_MODE = 1
7157 18:09:06.402214 LP45_APHY_COMB_EN = 1
7158 18:09:06.402779 TX_ODT_DIS = 0
7159 18:09:06.405864 NEW_8X_MODE = 1
7160 18:09:06.408683 ===================================
7161 18:09:06.411832 ===================================
7162 18:09:06.415532 data_rate = 3200
7163 18:09:06.418972 CKR = 1
7164 18:09:06.421942 DQ_P2S_RATIO = 8
7165 18:09:06.425305 ===================================
7166 18:09:06.428884 CA_P2S_RATIO = 8
7167 18:09:06.429305 DQ_CA_OPEN = 0
7168 18:09:06.432196 DQ_SEMI_OPEN = 0
7169 18:09:06.435341 CA_SEMI_OPEN = 0
7170 18:09:06.438522 CA_FULL_RATE = 0
7171 18:09:06.441749 DQ_CKDIV4_EN = 0
7172 18:09:06.442156 CA_CKDIV4_EN = 0
7173 18:09:06.445017 CA_PREDIV_EN = 0
7174 18:09:06.448504 PH8_DLY = 12
7175 18:09:06.452347 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 18:09:06.455507 DQ_AAMCK_DIV = 4
7177 18:09:06.458744 CA_AAMCK_DIV = 4
7178 18:09:06.459172 CA_ADMCK_DIV = 4
7179 18:09:06.461921 DQ_TRACK_CA_EN = 0
7180 18:09:06.464997 CA_PICK = 1600
7181 18:09:06.468925 CA_MCKIO = 1600
7182 18:09:06.472112 MCKIO_SEMI = 0
7183 18:09:06.475276 PLL_FREQ = 3068
7184 18:09:06.478691 DQ_UI_PI_RATIO = 32
7185 18:09:06.481579 CA_UI_PI_RATIO = 0
7186 18:09:06.485256 ===================================
7187 18:09:06.488389 ===================================
7188 18:09:06.488680 memory_type:LPDDR4
7189 18:09:06.492011 GP_NUM : 10
7190 18:09:06.492192 SRAM_EN : 1
7191 18:09:06.494930 MD32_EN : 0
7192 18:09:06.498837 ===================================
7193 18:09:06.501865 [ANA_INIT] >>>>>>>>>>>>>>
7194 18:09:06.504906 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 18:09:06.508474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 18:09:06.511832 ===================================
7197 18:09:06.511941 data_rate = 3200,PCW = 0X7600
7198 18:09:06.514955 ===================================
7199 18:09:06.521421 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 18:09:06.524669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 18:09:06.531127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 18:09:06.534451 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 18:09:06.537833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 18:09:06.541026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 18:09:06.544305 [ANA_INIT] flow start
7206 18:09:06.547634 [ANA_INIT] PLL >>>>>>>>
7207 18:09:06.547717 [ANA_INIT] PLL <<<<<<<<
7208 18:09:06.551338 [ANA_INIT] MIDPI >>>>>>>>
7209 18:09:06.554554 [ANA_INIT] MIDPI <<<<<<<<
7210 18:09:06.554636 [ANA_INIT] DLL >>>>>>>>
7211 18:09:06.557806 [ANA_INIT] DLL <<<<<<<<
7212 18:09:06.560986 [ANA_INIT] flow end
7213 18:09:06.564206 ============ LP4 DIFF to SE enter ============
7214 18:09:06.567472 ============ LP4 DIFF to SE exit ============
7215 18:09:06.571177 [ANA_INIT] <<<<<<<<<<<<<
7216 18:09:06.574522 [Flow] Enable top DCM control >>>>>
7217 18:09:06.577760 [Flow] Enable top DCM control <<<<<
7218 18:09:06.580948 Enable DLL master slave shuffle
7219 18:09:06.584599 ==============================================================
7220 18:09:06.587492 Gating Mode config
7221 18:09:06.594526 ==============================================================
7222 18:09:06.594643 Config description:
7223 18:09:06.604261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 18:09:06.611010 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 18:09:06.614268 SELPH_MODE 0: By rank 1: By Phase
7226 18:09:06.620911 ==============================================================
7227 18:09:06.624678 GAT_TRACK_EN = 1
7228 18:09:06.627936 RX_GATING_MODE = 2
7229 18:09:06.631103 RX_GATING_TRACK_MODE = 2
7230 18:09:06.634403 SELPH_MODE = 1
7231 18:09:06.637746 PICG_EARLY_EN = 1
7232 18:09:06.641483 VALID_LAT_VALUE = 1
7233 18:09:06.644840 ==============================================================
7234 18:09:06.647989 Enter into Gating configuration >>>>
7235 18:09:06.651352 Exit from Gating configuration <<<<
7236 18:09:06.654594 Enter into DVFS_PRE_config >>>>>
7237 18:09:06.664236 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 18:09:06.667965 Exit from DVFS_PRE_config <<<<<
7239 18:09:06.671230 Enter into PICG configuration >>>>
7240 18:09:06.674480 Exit from PICG configuration <<<<
7241 18:09:06.677815 [RX_INPUT] configuration >>>>>
7242 18:09:06.680831 [RX_INPUT] configuration <<<<<
7243 18:09:06.687621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 18:09:06.691227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 18:09:06.697801 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 18:09:06.704294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 18:09:06.710579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 18:09:06.717548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 18:09:06.720972 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 18:09:06.724479 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 18:09:06.727712 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 18:09:06.734399 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 18:09:06.737475 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 18:09:06.740753 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 18:09:06.743974 ===================================
7256 18:09:06.748009 LPDDR4 DRAM CONFIGURATION
7257 18:09:06.751334 ===================================
7258 18:09:06.751536 EX_ROW_EN[0] = 0x0
7259 18:09:06.754556 EX_ROW_EN[1] = 0x0
7260 18:09:06.757780 LP4Y_EN = 0x0
7261 18:09:06.757973 WORK_FSP = 0x1
7262 18:09:06.761033 WL = 0x5
7263 18:09:06.761204 RL = 0x5
7264 18:09:06.764361 BL = 0x2
7265 18:09:06.764543 RPST = 0x0
7266 18:09:06.767998 RD_PRE = 0x0
7267 18:09:06.768254 WR_PRE = 0x1
7268 18:09:06.771362 WR_PST = 0x1
7269 18:09:06.771621 DBI_WR = 0x0
7270 18:09:06.774495 DBI_RD = 0x0
7271 18:09:06.774780 OTF = 0x1
7272 18:09:06.777841 ===================================
7273 18:09:06.780891 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 18:09:06.787617 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 18:09:06.790862 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 18:09:06.794495 ===================================
7277 18:09:06.797849 LPDDR4 DRAM CONFIGURATION
7278 18:09:06.800581 ===================================
7279 18:09:06.801010 EX_ROW_EN[0] = 0x10
7280 18:09:06.804327 EX_ROW_EN[1] = 0x0
7281 18:09:06.804716 LP4Y_EN = 0x0
7282 18:09:06.807583 WORK_FSP = 0x1
7283 18:09:06.808114 WL = 0x5
7284 18:09:06.811361 RL = 0x5
7285 18:09:06.814501 BL = 0x2
7286 18:09:06.815057 RPST = 0x0
7287 18:09:06.817847 RD_PRE = 0x0
7288 18:09:06.818406 WR_PRE = 0x1
7289 18:09:06.820760 WR_PST = 0x1
7290 18:09:06.821279 DBI_WR = 0x0
7291 18:09:06.824074 DBI_RD = 0x0
7292 18:09:06.824733 OTF = 0x1
7293 18:09:06.827234 ===================================
7294 18:09:06.834108 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 18:09:06.834685 ==
7296 18:09:06.837298 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 18:09:06.840575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 18:09:06.841001 ==
7299 18:09:06.843752 [Duty_Offset_Calibration]
7300 18:09:06.847620 B0:2 B1:0 CA:1
7301 18:09:06.848144
7302 18:09:06.850631 [DutyScan_Calibration_Flow] k_type=0
7303 18:09:06.858261
7304 18:09:06.858760 ==CLK 0==
7305 18:09:06.861521 Final CLK duty delay cell = -4
7306 18:09:06.864825 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7307 18:09:06.868155 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7308 18:09:06.871591 [-4] AVG Duty = 4922%(X100)
7309 18:09:06.872105
7310 18:09:06.875063 CH0 CLK Duty spec in!! Max-Min= 218%
7311 18:09:06.878440 [DutyScan_Calibration_Flow] ====Done====
7312 18:09:06.878862
7313 18:09:06.881666 [DutyScan_Calibration_Flow] k_type=1
7314 18:09:06.897286
7315 18:09:06.897924 ==DQS 0 ==
7316 18:09:06.900896 Final DQS duty delay cell = 0
7317 18:09:06.904394 [0] MAX Duty = 5218%(X100), DQS PI = 32
7318 18:09:06.907477 [0] MIN Duty = 4938%(X100), DQS PI = 62
7319 18:09:06.910616 [0] AVG Duty = 5078%(X100)
7320 18:09:06.911259
7321 18:09:06.911771 ==DQS 1 ==
7322 18:09:06.914336 Final DQS duty delay cell = -4
7323 18:09:06.917622 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7324 18:09:06.920927 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7325 18:09:06.924156 [-4] AVG Duty = 4969%(X100)
7326 18:09:06.924689
7327 18:09:06.927965 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7328 18:09:06.928385
7329 18:09:06.931191 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7330 18:09:06.934132 [DutyScan_Calibration_Flow] ====Done====
7331 18:09:06.934646
7332 18:09:06.937643 [DutyScan_Calibration_Flow] k_type=3
7333 18:09:06.954936
7334 18:09:06.955387 ==DQM 0 ==
7335 18:09:06.958578 Final DQM duty delay cell = 0
7336 18:09:06.961591 [0] MAX Duty = 5062%(X100), DQS PI = 12
7337 18:09:06.964919 [0] MIN Duty = 4813%(X100), DQS PI = 50
7338 18:09:06.968142 [0] AVG Duty = 4937%(X100)
7339 18:09:06.968225
7340 18:09:06.968289 ==DQM 1 ==
7341 18:09:06.971523 Final DQM duty delay cell = 0
7342 18:09:06.974269 [0] MAX Duty = 5249%(X100), DQS PI = 28
7343 18:09:06.978064 [0] MIN Duty = 5000%(X100), DQS PI = 20
7344 18:09:06.981485 [0] AVG Duty = 5124%(X100)
7345 18:09:06.981567
7346 18:09:06.984156 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7347 18:09:06.984239
7348 18:09:06.987677 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7349 18:09:06.990887 [DutyScan_Calibration_Flow] ====Done====
7350 18:09:06.990989
7351 18:09:06.994005 [DutyScan_Calibration_Flow] k_type=2
7352 18:09:07.011738
7353 18:09:07.011844 ==DQ 0 ==
7354 18:09:07.015351 Final DQ duty delay cell = 0
7355 18:09:07.018696 [0] MAX Duty = 5124%(X100), DQS PI = 34
7356 18:09:07.021664 [0] MIN Duty = 5000%(X100), DQS PI = 0
7357 18:09:07.021738 [0] AVG Duty = 5062%(X100)
7358 18:09:07.021816
7359 18:09:07.025442 ==DQ 1 ==
7360 18:09:07.028525 Final DQ duty delay cell = 0
7361 18:09:07.031601 [0] MAX Duty = 4969%(X100), DQS PI = 50
7362 18:09:07.035375 [0] MIN Duty = 4875%(X100), DQS PI = 0
7363 18:09:07.035482 [0] AVG Duty = 4922%(X100)
7364 18:09:07.035573
7365 18:09:07.038275 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7366 18:09:07.041946
7367 18:09:07.042047 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7368 18:09:07.048284 [DutyScan_Calibration_Flow] ====Done====
7369 18:09:07.048387 ==
7370 18:09:07.051680 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 18:09:07.054852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 18:09:07.054950 ==
7373 18:09:07.058145 [Duty_Offset_Calibration]
7374 18:09:07.058212 B0:0 B1:-1 CA:2
7375 18:09:07.058270
7376 18:09:07.061373 [DutyScan_Calibration_Flow] k_type=0
7377 18:09:07.071893
7378 18:09:07.071961 ==CLK 0==
7379 18:09:07.075181 Final CLK duty delay cell = 0
7380 18:09:07.078460 [0] MAX Duty = 5156%(X100), DQS PI = 10
7381 18:09:07.081794 [0] MIN Duty = 4938%(X100), DQS PI = 46
7382 18:09:07.081863 [0] AVG Duty = 5047%(X100)
7383 18:09:07.085524
7384 18:09:07.088862 CH1 CLK Duty spec in!! Max-Min= 218%
7385 18:09:07.091968 [DutyScan_Calibration_Flow] ====Done====
7386 18:09:07.092048
7387 18:09:07.095010 [DutyScan_Calibration_Flow] k_type=1
7388 18:09:07.111577
7389 18:09:07.111677 ==DQS 0 ==
7390 18:09:07.115027 Final DQS duty delay cell = 0
7391 18:09:07.118049 [0] MAX Duty = 5124%(X100), DQS PI = 26
7392 18:09:07.121808 [0] MIN Duty = 4969%(X100), DQS PI = 0
7393 18:09:07.124902 [0] AVG Duty = 5046%(X100)
7394 18:09:07.124972
7395 18:09:07.125032 ==DQS 1 ==
7396 18:09:07.128088 Final DQS duty delay cell = 0
7397 18:09:07.131439 [0] MAX Duty = 5187%(X100), DQS PI = 0
7398 18:09:07.134707 [0] MIN Duty = 4844%(X100), DQS PI = 32
7399 18:09:07.137911 [0] AVG Duty = 5015%(X100)
7400 18:09:07.137982
7401 18:09:07.141648 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7402 18:09:07.141742
7403 18:09:07.144840 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7404 18:09:07.148104 [DutyScan_Calibration_Flow] ====Done====
7405 18:09:07.148201
7406 18:09:07.151352 [DutyScan_Calibration_Flow] k_type=3
7407 18:09:07.169317
7408 18:09:07.169418 ==DQM 0 ==
7409 18:09:07.172601 Final DQM duty delay cell = 4
7410 18:09:07.175866 [4] MAX Duty = 5125%(X100), DQS PI = 22
7411 18:09:07.179189 [4] MIN Duty = 4969%(X100), DQS PI = 34
7412 18:09:07.182420 [4] AVG Duty = 5047%(X100)
7413 18:09:07.182519
7414 18:09:07.182610 ==DQM 1 ==
7415 18:09:07.185649 Final DQM duty delay cell = 0
7416 18:09:07.188897 [0] MAX Duty = 5281%(X100), DQS PI = 58
7417 18:09:07.192498 [0] MIN Duty = 4876%(X100), DQS PI = 34
7418 18:09:07.195675 [0] AVG Duty = 5078%(X100)
7419 18:09:07.195757
7420 18:09:07.198906 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7421 18:09:07.198988
7422 18:09:07.202150 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7423 18:09:07.205550 [DutyScan_Calibration_Flow] ====Done====
7424 18:09:07.205631
7425 18:09:07.208813 [DutyScan_Calibration_Flow] k_type=2
7426 18:09:07.226177
7427 18:09:07.226298 ==DQ 0 ==
7428 18:09:07.229658 Final DQ duty delay cell = 0
7429 18:09:07.232963 [0] MAX Duty = 5062%(X100), DQS PI = 20
7430 18:09:07.236222 [0] MIN Duty = 4969%(X100), DQS PI = 0
7431 18:09:07.236304 [0] AVG Duty = 5015%(X100)
7432 18:09:07.239367
7433 18:09:07.239448 ==DQ 1 ==
7434 18:09:07.242798 Final DQ duty delay cell = 0
7435 18:09:07.246081 [0] MAX Duty = 5031%(X100), DQS PI = 0
7436 18:09:07.249326 [0] MIN Duty = 4813%(X100), DQS PI = 32
7437 18:09:07.249420 [0] AVG Duty = 4922%(X100)
7438 18:09:07.249493
7439 18:09:07.252977 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7440 18:09:07.256248
7441 18:09:07.259692 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7442 18:09:07.262924 [DutyScan_Calibration_Flow] ====Done====
7443 18:09:07.266192 nWR fixed to 30
7444 18:09:07.266386 [ModeRegInit_LP4] CH0 RK0
7445 18:09:07.269364 [ModeRegInit_LP4] CH0 RK1
7446 18:09:07.272731 [ModeRegInit_LP4] CH1 RK0
7447 18:09:07.272881 [ModeRegInit_LP4] CH1 RK1
7448 18:09:07.276159 match AC timing 5
7449 18:09:07.279670 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 18:09:07.282859 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 18:09:07.289734 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 18:09:07.293397 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 18:09:07.299899 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 18:09:07.300347 [MiockJmeterHQA]
7455 18:09:07.300796
7456 18:09:07.302935 [DramcMiockJmeter] u1RxGatingPI = 0
7457 18:09:07.306077 0 : 4255, 4029
7458 18:09:07.306495 4 : 4252, 4026
7459 18:09:07.306829 8 : 4252, 4027
7460 18:09:07.309943 12 : 4252, 4026
7461 18:09:07.310385 16 : 4252, 4027
7462 18:09:07.313077 20 : 4253, 4026
7463 18:09:07.313495 24 : 4253, 4027
7464 18:09:07.316177 28 : 4363, 4137
7465 18:09:07.316627 32 : 4253, 4027
7466 18:09:07.319341 36 : 4253, 4026
7467 18:09:07.319761 40 : 4252, 4027
7468 18:09:07.320091 44 : 4255, 4030
7469 18:09:07.323103 48 : 4254, 4029
7470 18:09:07.323523 52 : 4365, 4140
7471 18:09:07.325868 56 : 4361, 4137
7472 18:09:07.326284 60 : 4363, 4140
7473 18:09:07.329659 64 : 4253, 4029
7474 18:09:07.330076 68 : 4252, 4029
7475 18:09:07.330407 72 : 4252, 4029
7476 18:09:07.332705 76 : 4249, 4027
7477 18:09:07.333258 80 : 4361, 4137
7478 18:09:07.335774 84 : 4250, 4027
7479 18:09:07.336190 88 : 4250, 3719
7480 18:09:07.339619 92 : 4252, 0
7481 18:09:07.340039 96 : 4250, 0
7482 18:09:07.340376 100 : 4363, 0
7483 18:09:07.343027 104 : 4252, 0
7484 18:09:07.343561 108 : 4253, 0
7485 18:09:07.345931 112 : 4255, 0
7486 18:09:07.346351 116 : 4252, 0
7487 18:09:07.346684 120 : 4250, 0
7488 18:09:07.349983 124 : 4250, 0
7489 18:09:07.350508 128 : 4252, 0
7490 18:09:07.350849 132 : 4360, 0
7491 18:09:07.352788 136 : 4250, 0
7492 18:09:07.353207 140 : 4363, 0
7493 18:09:07.356020 144 : 4255, 0
7494 18:09:07.356441 148 : 4250, 0
7495 18:09:07.356837 152 : 4250, 0
7496 18:09:07.359305 156 : 4255, 0
7497 18:09:07.359765 160 : 4255, 0
7498 18:09:07.362444 164 : 4250, 0
7499 18:09:07.362868 168 : 4252, 0
7500 18:09:07.363254 172 : 4250, 0
7501 18:09:07.365835 176 : 4250, 0
7502 18:09:07.366256 180 : 4252, 0
7503 18:09:07.369294 184 : 4360, 0
7504 18:09:07.369817 188 : 4250, 0
7505 18:09:07.370152 192 : 4363, 0
7506 18:09:07.372577 196 : 4255, 0
7507 18:09:07.373007 200 : 4250, 8
7508 18:09:07.375947 204 : 4250, 2456
7509 18:09:07.376463 208 : 4363, 4140
7510 18:09:07.379152 212 : 4361, 4137
7511 18:09:07.379621 216 : 4250, 4027
7512 18:09:07.380083 220 : 4361, 4137
7513 18:09:07.382373 224 : 4250, 4026
7514 18:09:07.382813 228 : 4250, 4026
7515 18:09:07.385888 232 : 4252, 4029
7516 18:09:07.386332 236 : 4363, 4140
7517 18:09:07.389212 240 : 4250, 4026
7518 18:09:07.389636 244 : 4250, 4026
7519 18:09:07.392289 248 : 4360, 4138
7520 18:09:07.392688 252 : 4250, 4027
7521 18:09:07.396166 256 : 4252, 4029
7522 18:09:07.396513 260 : 4361, 4137
7523 18:09:07.398919 264 : 4363, 4137
7524 18:09:07.399342 268 : 4250, 4027
7525 18:09:07.402645 272 : 4254, 4030
7526 18:09:07.403183 276 : 4250, 4027
7527 18:09:07.403524 280 : 4250, 4026
7528 18:09:07.406405 284 : 4252, 4029
7529 18:09:07.406925 288 : 4363, 4138
7530 18:09:07.409112 292 : 4250, 4026
7531 18:09:07.409530 296 : 4250, 4026
7532 18:09:07.412335 300 : 4360, 4138
7533 18:09:07.412802 304 : 4250, 4027
7534 18:09:07.416054 308 : 4252, 4029
7535 18:09:07.416473 312 : 4361, 4088
7536 18:09:07.419286 316 : 4363, 2216
7537 18:09:07.419726 320 : 4250, 1
7538 18:09:07.420062
7539 18:09:07.422793 MIOCK jitter meter ch=0
7540 18:09:07.423311
7541 18:09:07.426174 1T = (320-92) = 228 dly cells
7542 18:09:07.429190 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7543 18:09:07.429619 ==
7544 18:09:07.432899 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 18:09:07.439160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 18:09:07.439669 ==
7547 18:09:07.442399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 18:09:07.448724 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 18:09:07.452401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 18:09:07.458908 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 18:09:07.466686 [CA 0] Center 43 (13~73) winsize 61
7552 18:09:07.469913 [CA 1] Center 43 (13~73) winsize 61
7553 18:09:07.473286 [CA 2] Center 38 (8~68) winsize 61
7554 18:09:07.476666 [CA 3] Center 37 (8~67) winsize 60
7555 18:09:07.479797 [CA 4] Center 36 (6~66) winsize 61
7556 18:09:07.483039 [CA 5] Center 35 (5~65) winsize 61
7557 18:09:07.483454
7558 18:09:07.486346 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 18:09:07.486811
7560 18:09:07.489582 [CATrainingPosCal] consider 1 rank data
7561 18:09:07.493414 u2DelayCellTimex100 = 285/100 ps
7562 18:09:07.496079 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7563 18:09:07.503280 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7564 18:09:07.506694 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7565 18:09:07.509742 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7566 18:09:07.512775 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7567 18:09:07.516354 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7568 18:09:07.516837
7569 18:09:07.519692 CA PerBit enable=1, Macro0, CA PI delay=35
7570 18:09:07.520133
7571 18:09:07.523003 [CBTSetCACLKResult] CA Dly = 35
7572 18:09:07.526615 CS Dly: 9 (0~40)
7573 18:09:07.529519 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 18:09:07.533105 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 18:09:07.533574 ==
7576 18:09:07.536164 Dram Type= 6, Freq= 0, CH_0, rank 1
7577 18:09:07.539182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 18:09:07.542829 ==
7579 18:09:07.546026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7580 18:09:07.549403 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7581 18:09:07.556259 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7582 18:09:07.559366 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7583 18:09:07.573488 [CA 0] Center 43 (13~74) winsize 62
7584 18:09:07.574017 [CA 1] Center 43 (13~73) winsize 61
7585 18:09:07.576960 [CA 2] Center 38 (9~68) winsize 60
7586 18:09:07.579994 [CA 3] Center 38 (9~68) winsize 60
7587 18:09:07.583072 [CA 4] Center 36 (7~66) winsize 60
7588 18:09:07.586705 [CA 5] Center 36 (6~66) winsize 61
7589 18:09:07.587130
7590 18:09:07.589894 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7591 18:09:07.590317
7592 18:09:07.593055 [CATrainingPosCal] consider 2 rank data
7593 18:09:07.596274 u2DelayCellTimex100 = 285/100 ps
7594 18:09:07.600085 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7595 18:09:07.606220 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7596 18:09:07.609384 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7597 18:09:07.613183 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7598 18:09:07.616270 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7599 18:09:07.619719 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7600 18:09:07.620143
7601 18:09:07.622931 CA PerBit enable=1, Macro0, CA PI delay=35
7602 18:09:07.623351
7603 18:09:07.626423 [CBTSetCACLKResult] CA Dly = 35
7604 18:09:07.629819 CS Dly: 10 (0~43)
7605 18:09:07.633032 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7606 18:09:07.636262 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7607 18:09:07.636738
7608 18:09:07.639900 ----->DramcWriteLeveling(PI) begin...
7609 18:09:07.640332 ==
7610 18:09:07.643036 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 18:09:07.649979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 18:09:07.650505 ==
7613 18:09:07.653042 Write leveling (Byte 0): 36 => 36
7614 18:09:07.653470 Write leveling (Byte 1): 30 => 30
7615 18:09:07.656109 DramcWriteLeveling(PI) end<-----
7616 18:09:07.656533
7617 18:09:07.659316 ==
7618 18:09:07.659740 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 18:09:07.666235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 18:09:07.666815 ==
7621 18:09:07.669483 [Gating] SW mode calibration
7622 18:09:07.676015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7623 18:09:07.679211 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7624 18:09:07.685837 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 18:09:07.689017 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 18:09:07.692297 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7627 18:09:07.699110 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7628 18:09:07.702345 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7629 18:09:07.705578 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7630 18:09:07.712330 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 18:09:07.716128 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 18:09:07.719211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 18:09:07.725456 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 18:09:07.729070 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7635 18:09:07.732261 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7636 18:09:07.735399 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7637 18:09:07.742268 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7638 18:09:07.745818 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 18:09:07.748894 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 18:09:07.755695 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 18:09:07.758762 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 18:09:07.761925 1 6 8 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
7643 18:09:07.768761 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7644 18:09:07.772380 1 6 16 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7645 18:09:07.775739 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 18:09:07.782000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 18:09:07.785209 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 18:09:07.788875 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 18:09:07.795644 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 18:09:07.798848 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 18:09:07.801746 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7652 18:09:07.808502 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7653 18:09:07.811932 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 18:09:07.815103 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 18:09:07.821894 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 18:09:07.825035 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 18:09:07.828238 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 18:09:07.834557 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 18:09:07.838499 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 18:09:07.841637 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 18:09:07.847863 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 18:09:07.851516 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 18:09:07.855056 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 18:09:07.861742 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 18:09:07.864923 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 18:09:07.868296 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7667 18:09:07.874986 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7668 18:09:07.878119 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7669 18:09:07.881298 Total UI for P1: 0, mck2ui 16
7670 18:09:07.884804 best dqsien dly found for B0: ( 1, 9, 10)
7671 18:09:07.887984 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7672 18:09:07.894937 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 18:09:07.895381 Total UI for P1: 0, mck2ui 16
7674 18:09:07.901459 best dqsien dly found for B1: ( 1, 9, 20)
7675 18:09:07.904729 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7676 18:09:07.908016 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7677 18:09:07.908455
7678 18:09:07.911144 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7679 18:09:07.914475 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7680 18:09:07.917486 [Gating] SW calibration Done
7681 18:09:07.917799 ==
7682 18:09:07.920634 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 18:09:07.924297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 18:09:07.924643 ==
7685 18:09:07.927396 RX Vref Scan: 0
7686 18:09:07.927632
7687 18:09:07.927779 RX Vref 0 -> 0, step: 1
7688 18:09:07.930579
7689 18:09:07.930772 RX Delay 0 -> 252, step: 8
7690 18:09:07.937553 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7691 18:09:07.940621 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7692 18:09:07.943961 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7693 18:09:07.947144 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7694 18:09:07.950464 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7695 18:09:07.953608 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7696 18:09:07.960557 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7697 18:09:07.964170 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7698 18:09:07.967231 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7699 18:09:07.970312 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7700 18:09:07.973929 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7701 18:09:07.980055 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7702 18:09:07.983274 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7703 18:09:07.986633 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7704 18:09:07.990245 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7705 18:09:07.996870 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7706 18:09:07.996986 ==
7707 18:09:07.999983 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 18:09:08.003422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 18:09:08.003550 ==
7710 18:09:08.003650 DQS Delay:
7711 18:09:08.006851 DQS0 = 0, DQS1 = 0
7712 18:09:08.007074 DQM Delay:
7713 18:09:08.010003 DQM0 = 138, DQM1 = 127
7714 18:09:08.010162 DQ Delay:
7715 18:09:08.013174 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7716 18:09:08.016754 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7717 18:09:08.019922 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7718 18:09:08.023279 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7719 18:09:08.023578
7720 18:09:08.023758
7721 18:09:08.026453 ==
7722 18:09:08.029787 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 18:09:08.032895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 18:09:08.033155 ==
7725 18:09:08.033359
7726 18:09:08.033545
7727 18:09:08.036609 TX Vref Scan disable
7728 18:09:08.036933 == TX Byte 0 ==
7729 18:09:08.039794 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7730 18:09:08.046814 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 18:09:08.047352 == TX Byte 1 ==
7732 18:09:08.053062 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7733 18:09:08.056593 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7734 18:09:08.057010 ==
7735 18:09:08.059569 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 18:09:08.062796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 18:09:08.063217 ==
7738 18:09:08.076532
7739 18:09:08.079951 TX Vref early break, caculate TX vref
7740 18:09:08.083456 TX Vref=16, minBit 12, minWin=22, winSum=376
7741 18:09:08.086656 TX Vref=18, minBit 6, minWin=23, winSum=388
7742 18:09:08.090207 TX Vref=20, minBit 12, minWin=23, winSum=397
7743 18:09:08.093528 TX Vref=22, minBit 7, minWin=24, winSum=406
7744 18:09:08.096599 TX Vref=24, minBit 4, minWin=25, winSum=414
7745 18:09:08.103310 TX Vref=26, minBit 7, minWin=25, winSum=424
7746 18:09:08.106415 TX Vref=28, minBit 2, minWin=25, winSum=433
7747 18:09:08.109725 TX Vref=30, minBit 0, minWin=25, winSum=420
7748 18:09:08.113383 TX Vref=32, minBit 0, minWin=25, winSum=416
7749 18:09:08.116533 TX Vref=34, minBit 7, minWin=24, winSum=410
7750 18:09:08.123355 [TxChooseVref] Worse bit 2, Min win 25, Win sum 433, Final Vref 28
7751 18:09:08.123797
7752 18:09:08.126528 Final TX Range 0 Vref 28
7753 18:09:08.127067
7754 18:09:08.127487 ==
7755 18:09:08.129735 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 18:09:08.132899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 18:09:08.133339 ==
7758 18:09:08.133669
7759 18:09:08.133995
7760 18:09:08.136180 TX Vref Scan disable
7761 18:09:08.143107 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7762 18:09:08.143523 == TX Byte 0 ==
7763 18:09:08.146462 u2DelayCellOfst[0]=13 cells (4 PI)
7764 18:09:08.149920 u2DelayCellOfst[1]=17 cells (5 PI)
7765 18:09:08.153245 u2DelayCellOfst[2]=10 cells (3 PI)
7766 18:09:08.156324 u2DelayCellOfst[3]=13 cells (4 PI)
7767 18:09:08.159424 u2DelayCellOfst[4]=6 cells (2 PI)
7768 18:09:08.163212 u2DelayCellOfst[5]=0 cells (0 PI)
7769 18:09:08.166434 u2DelayCellOfst[6]=17 cells (5 PI)
7770 18:09:08.169539 u2DelayCellOfst[7]=13 cells (4 PI)
7771 18:09:08.172917 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7772 18:09:08.175913 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7773 18:09:08.179175 == TX Byte 1 ==
7774 18:09:08.183164 u2DelayCellOfst[8]=0 cells (0 PI)
7775 18:09:08.183588 u2DelayCellOfst[9]=0 cells (0 PI)
7776 18:09:08.186336 u2DelayCellOfst[10]=6 cells (2 PI)
7777 18:09:08.189530 u2DelayCellOfst[11]=3 cells (1 PI)
7778 18:09:08.193080 u2DelayCellOfst[12]=13 cells (4 PI)
7779 18:09:08.196287 u2DelayCellOfst[13]=10 cells (3 PI)
7780 18:09:08.199718 u2DelayCellOfst[14]=13 cells (4 PI)
7781 18:09:08.202855 u2DelayCellOfst[15]=10 cells (3 PI)
7782 18:09:08.206550 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7783 18:09:08.213032 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7784 18:09:08.213452 DramC Write-DBI on
7785 18:09:08.213781 ==
7786 18:09:08.216399 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 18:09:08.219617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 18:09:08.222753 ==
7789 18:09:08.223166
7790 18:09:08.223515
7791 18:09:08.223954 TX Vref Scan disable
7792 18:09:08.226254 == TX Byte 0 ==
7793 18:09:08.229649 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7794 18:09:08.232949 == TX Byte 1 ==
7795 18:09:08.236639 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7796 18:09:08.239873 DramC Write-DBI off
7797 18:09:08.240287
7798 18:09:08.240645 [DATLAT]
7799 18:09:08.240949 Freq=1600, CH0 RK0
7800 18:09:08.241238
7801 18:09:08.242974 DATLAT Default: 0xf
7802 18:09:08.243386 0, 0xFFFF, sum = 0
7803 18:09:08.246177 1, 0xFFFF, sum = 0
7804 18:09:08.249425 2, 0xFFFF, sum = 0
7805 18:09:08.249843 3, 0xFFFF, sum = 0
7806 18:09:08.253143 4, 0xFFFF, sum = 0
7807 18:09:08.253668 5, 0xFFFF, sum = 0
7808 18:09:08.256731 6, 0xFFFF, sum = 0
7809 18:09:08.257255 7, 0xFFFF, sum = 0
7810 18:09:08.259589 8, 0xFFFF, sum = 0
7811 18:09:08.260013 9, 0xFFFF, sum = 0
7812 18:09:08.262897 10, 0xFFFF, sum = 0
7813 18:09:08.263316 11, 0xFFFF, sum = 0
7814 18:09:08.266414 12, 0xFFFF, sum = 0
7815 18:09:08.266986 13, 0xFFFF, sum = 0
7816 18:09:08.269984 14, 0x0, sum = 1
7817 18:09:08.270556 15, 0x0, sum = 2
7818 18:09:08.272653 16, 0x0, sum = 3
7819 18:09:08.273106 17, 0x0, sum = 4
7820 18:09:08.276528 best_step = 15
7821 18:09:08.277175
7822 18:09:08.277663 ==
7823 18:09:08.279448 Dram Type= 6, Freq= 0, CH_0, rank 0
7824 18:09:08.282996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7825 18:09:08.283483 ==
7826 18:09:08.286018 RX Vref Scan: 1
7827 18:09:08.286508
7828 18:09:08.286879 Set Vref Range= 24 -> 127
7829 18:09:08.287191
7830 18:09:08.289242 RX Vref 24 -> 127, step: 1
7831 18:09:08.289733
7832 18:09:08.292739 RX Delay 19 -> 252, step: 4
7833 18:09:08.293156
7834 18:09:08.295809 Set Vref, RX VrefLevel [Byte0]: 24
7835 18:09:08.299082 [Byte1]: 24
7836 18:09:08.299499
7837 18:09:08.302905 Set Vref, RX VrefLevel [Byte0]: 25
7838 18:09:08.306093 [Byte1]: 25
7839 18:09:08.306511
7840 18:09:08.309178 Set Vref, RX VrefLevel [Byte0]: 26
7841 18:09:08.312387 [Byte1]: 26
7842 18:09:08.316896
7843 18:09:08.317419 Set Vref, RX VrefLevel [Byte0]: 27
7844 18:09:08.319741 [Byte1]: 27
7845 18:09:08.324490
7846 18:09:08.325130 Set Vref, RX VrefLevel [Byte0]: 28
7847 18:09:08.327860 [Byte1]: 28
7848 18:09:08.331862
7849 18:09:08.332432 Set Vref, RX VrefLevel [Byte0]: 29
7850 18:09:08.334943 [Byte1]: 29
7851 18:09:08.339958
7852 18:09:08.340606 Set Vref, RX VrefLevel [Byte0]: 30
7853 18:09:08.342839 [Byte1]: 30
7854 18:09:08.347402
7855 18:09:08.347937 Set Vref, RX VrefLevel [Byte0]: 31
7856 18:09:08.350646 [Byte1]: 31
7857 18:09:08.354809
7858 18:09:08.355335 Set Vref, RX VrefLevel [Byte0]: 32
7859 18:09:08.357848 [Byte1]: 32
7860 18:09:08.361970
7861 18:09:08.362393 Set Vref, RX VrefLevel [Byte0]: 33
7862 18:09:08.365661 [Byte1]: 33
7863 18:09:08.369406
7864 18:09:08.369827 Set Vref, RX VrefLevel [Byte0]: 34
7865 18:09:08.373192 [Byte1]: 34
7866 18:09:08.376948
7867 18:09:08.377441 Set Vref, RX VrefLevel [Byte0]: 35
7868 18:09:08.380590 [Byte1]: 35
7869 18:09:08.384731
7870 18:09:08.385315 Set Vref, RX VrefLevel [Byte0]: 36
7871 18:09:08.388227 [Byte1]: 36
7872 18:09:08.392527
7873 18:09:08.392977 Set Vref, RX VrefLevel [Byte0]: 37
7874 18:09:08.395695 [Byte1]: 37
7875 18:09:08.399906
7876 18:09:08.400315 Set Vref, RX VrefLevel [Byte0]: 38
7877 18:09:08.402992 [Byte1]: 38
7878 18:09:08.407297
7879 18:09:08.407884 Set Vref, RX VrefLevel [Byte0]: 39
7880 18:09:08.410932 [Byte1]: 39
7881 18:09:08.415069
7882 18:09:08.415700 Set Vref, RX VrefLevel [Byte0]: 40
7883 18:09:08.418197 [Byte1]: 40
7884 18:09:08.422805
7885 18:09:08.423226 Set Vref, RX VrefLevel [Byte0]: 41
7886 18:09:08.426442 [Byte1]: 41
7887 18:09:08.430681
7888 18:09:08.431203 Set Vref, RX VrefLevel [Byte0]: 42
7889 18:09:08.433600 [Byte1]: 42
7890 18:09:08.437667
7891 18:09:08.438221 Set Vref, RX VrefLevel [Byte0]: 43
7892 18:09:08.440912 [Byte1]: 43
7893 18:09:08.445652
7894 18:09:08.446070 Set Vref, RX VrefLevel [Byte0]: 44
7895 18:09:08.448862 [Byte1]: 44
7896 18:09:08.453005
7897 18:09:08.453431 Set Vref, RX VrefLevel [Byte0]: 45
7898 18:09:08.456315 [Byte1]: 45
7899 18:09:08.460529
7900 18:09:08.461201 Set Vref, RX VrefLevel [Byte0]: 46
7901 18:09:08.464213 [Byte1]: 46
7902 18:09:08.468205
7903 18:09:08.468775 Set Vref, RX VrefLevel [Byte0]: 47
7904 18:09:08.471342 [Byte1]: 47
7905 18:09:08.475449
7906 18:09:08.475985 Set Vref, RX VrefLevel [Byte0]: 48
7907 18:09:08.479169 [Byte1]: 48
7908 18:09:08.483066
7909 18:09:08.483477 Set Vref, RX VrefLevel [Byte0]: 49
7910 18:09:08.486530 [Byte1]: 49
7911 18:09:08.490571
7912 18:09:08.490991 Set Vref, RX VrefLevel [Byte0]: 50
7913 18:09:08.494740 [Byte1]: 50
7914 18:09:08.498797
7915 18:09:08.499223 Set Vref, RX VrefLevel [Byte0]: 51
7916 18:09:08.501691 [Byte1]: 51
7917 18:09:08.506307
7918 18:09:08.506852 Set Vref, RX VrefLevel [Byte0]: 52
7919 18:09:08.509263 [Byte1]: 52
7920 18:09:08.513596
7921 18:09:08.514016 Set Vref, RX VrefLevel [Byte0]: 53
7922 18:09:08.517034 [Byte1]: 53
7923 18:09:08.521115
7924 18:09:08.521537 Set Vref, RX VrefLevel [Byte0]: 54
7925 18:09:08.524462 [Byte1]: 54
7926 18:09:08.528482
7927 18:09:08.529097 Set Vref, RX VrefLevel [Byte0]: 55
7928 18:09:08.532220 [Byte1]: 55
7929 18:09:08.536413
7930 18:09:08.536899 Set Vref, RX VrefLevel [Byte0]: 56
7931 18:09:08.539687 [Byte1]: 56
7932 18:09:08.543789
7933 18:09:08.544230 Set Vref, RX VrefLevel [Byte0]: 57
7934 18:09:08.547045 [Byte1]: 57
7935 18:09:08.551333
7936 18:09:08.551745 Set Vref, RX VrefLevel [Byte0]: 58
7937 18:09:08.554498 [Byte1]: 58
7938 18:09:08.559428
7939 18:09:08.559938 Set Vref, RX VrefLevel [Byte0]: 59
7940 18:09:08.562568 [Byte1]: 59
7941 18:09:08.566604
7942 18:09:08.567163 Set Vref, RX VrefLevel [Byte0]: 60
7943 18:09:08.569881 [Byte1]: 60
7944 18:09:08.573742
7945 18:09:08.574259 Set Vref, RX VrefLevel [Byte0]: 61
7946 18:09:08.577569 [Byte1]: 61
7947 18:09:08.582075
7948 18:09:08.582527 Set Vref, RX VrefLevel [Byte0]: 62
7949 18:09:08.585021 [Byte1]: 62
7950 18:09:08.589073
7951 18:09:08.589519 Set Vref, RX VrefLevel [Byte0]: 63
7952 18:09:08.592604 [Byte1]: 63
7953 18:09:08.596828
7954 18:09:08.597245 Set Vref, RX VrefLevel [Byte0]: 64
7955 18:09:08.600468 [Byte1]: 64
7956 18:09:08.604695
7957 18:09:08.605364 Set Vref, RX VrefLevel [Byte0]: 65
7958 18:09:08.607447 [Byte1]: 65
7959 18:09:08.611778
7960 18:09:08.612186 Set Vref, RX VrefLevel [Byte0]: 66
7961 18:09:08.615196 [Byte1]: 66
7962 18:09:08.619732
7963 18:09:08.620322 Set Vref, RX VrefLevel [Byte0]: 67
7964 18:09:08.622908 [Byte1]: 67
7965 18:09:08.627220
7966 18:09:08.627799 Set Vref, RX VrefLevel [Byte0]: 68
7967 18:09:08.630379 [Byte1]: 68
7968 18:09:08.634658
7969 18:09:08.635120 Set Vref, RX VrefLevel [Byte0]: 69
7970 18:09:08.637728 [Byte1]: 69
7971 18:09:08.642143
7972 18:09:08.642561 Set Vref, RX VrefLevel [Byte0]: 70
7973 18:09:08.645392 [Byte1]: 70
7974 18:09:08.649969
7975 18:09:08.650407 Set Vref, RX VrefLevel [Byte0]: 71
7976 18:09:08.653243 [Byte1]: 71
7977 18:09:08.657322
7978 18:09:08.657843 Set Vref, RX VrefLevel [Byte0]: 72
7979 18:09:08.660485 [Byte1]: 72
7980 18:09:08.664747
7981 18:09:08.665169 Set Vref, RX VrefLevel [Byte0]: 73
7982 18:09:08.668015 [Byte1]: 73
7983 18:09:08.672632
7984 18:09:08.673042 Set Vref, RX VrefLevel [Byte0]: 74
7985 18:09:08.675917 [Byte1]: 74
7986 18:09:08.680252
7987 18:09:08.680709 Set Vref, RX VrefLevel [Byte0]: 75
7988 18:09:08.683489 [Byte1]: 75
7989 18:09:08.687564
7990 18:09:08.687977 Set Vref, RX VrefLevel [Byte0]: 76
7991 18:09:08.691130 [Byte1]: 76
7992 18:09:08.695597
7993 18:09:08.696114 Set Vref, RX VrefLevel [Byte0]: 77
7994 18:09:08.698793 [Byte1]: 77
7995 18:09:08.702860
7996 18:09:08.703313 Set Vref, RX VrefLevel [Byte0]: 78
7997 18:09:08.706036 [Byte1]: 78
7998 18:09:08.710422
7999 18:09:08.710839 Final RX Vref Byte 0 = 62 to rank0
8000 18:09:08.714421 Final RX Vref Byte 1 = 63 to rank0
8001 18:09:08.717285 Final RX Vref Byte 0 = 62 to rank1
8002 18:09:08.720621 Final RX Vref Byte 1 = 63 to rank1==
8003 18:09:08.723661 Dram Type= 6, Freq= 0, CH_0, rank 0
8004 18:09:08.730155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8005 18:09:08.730575 ==
8006 18:09:08.730908 DQS Delay:
8007 18:09:08.733429 DQS0 = 0, DQS1 = 0
8008 18:09:08.733886 DQM Delay:
8009 18:09:08.734215 DQM0 = 136, DQM1 = 124
8010 18:09:08.737208 DQ Delay:
8011 18:09:08.740377 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8012 18:09:08.743460 DQ4 =138, DQ5 =126, DQ6 =146, DQ7 =142
8013 18:09:08.746622 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8014 18:09:08.750506 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
8015 18:09:08.751017
8016 18:09:08.751345
8017 18:09:08.751647
8018 18:09:08.753511 [DramC_TX_OE_Calibration] TA2
8019 18:09:08.756891 Original DQ_B0 (3 6) =30, OEN = 27
8020 18:09:08.760209 Original DQ_B1 (3 6) =30, OEN = 27
8021 18:09:08.763516 24, 0x0, End_B0=24 End_B1=24
8022 18:09:08.763945 25, 0x0, End_B0=25 End_B1=25
8023 18:09:08.766770 26, 0x0, End_B0=26 End_B1=26
8024 18:09:08.770094 27, 0x0, End_B0=27 End_B1=27
8025 18:09:08.773334 28, 0x0, End_B0=28 End_B1=28
8026 18:09:08.776596 29, 0x0, End_B0=29 End_B1=29
8027 18:09:08.777056 30, 0x0, End_B0=30 End_B1=30
8028 18:09:08.780223 31, 0x4545, End_B0=30 End_B1=30
8029 18:09:08.783468 Byte0 end_step=30 best_step=27
8030 18:09:08.786409 Byte1 end_step=30 best_step=27
8031 18:09:08.790081 Byte0 TX OE(2T, 0.5T) = (3, 3)
8032 18:09:08.793127 Byte1 TX OE(2T, 0.5T) = (3, 3)
8033 18:09:08.793559
8034 18:09:08.794011
8035 18:09:08.799953 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8036 18:09:08.803150 CH0 RK0: MR19=303, MR18=1E1C
8037 18:09:08.809923 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8038 18:09:08.810510
8039 18:09:08.813052 ----->DramcWriteLeveling(PI) begin...
8040 18:09:08.813509 ==
8041 18:09:08.816607 Dram Type= 6, Freq= 0, CH_0, rank 1
8042 18:09:08.819842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 18:09:08.820306 ==
8044 18:09:08.823474 Write leveling (Byte 0): 36 => 36
8045 18:09:08.826889 Write leveling (Byte 1): 32 => 32
8046 18:09:08.830099 DramcWriteLeveling(PI) end<-----
8047 18:09:08.830589
8048 18:09:08.830926 ==
8049 18:09:08.833267 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 18:09:08.836778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 18:09:08.837312 ==
8052 18:09:08.839735 [Gating] SW mode calibration
8053 18:09:08.846431 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8054 18:09:08.853241 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8055 18:09:08.856343 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 18:09:08.859537 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 18:09:08.866621 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 18:09:08.869634 1 4 12 | B1->B0 | 2525 3232 | 0 1 | (0 0) (0 0)
8059 18:09:08.872796 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 18:09:08.879742 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 18:09:08.883011 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 18:09:08.885944 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 18:09:08.893034 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 18:09:08.895812 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 18:09:08.899473 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8066 18:09:08.906421 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
8067 18:09:08.909532 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8068 18:09:08.912685 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 18:09:08.919218 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 18:09:08.922669 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 18:09:08.925857 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 18:09:08.932605 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 18:09:08.936088 1 6 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8074 18:09:08.939087 1 6 12 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
8075 18:09:08.945535 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 18:09:08.949023 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 18:09:08.952381 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 18:09:08.959120 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 18:09:08.962227 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 18:09:08.965520 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 18:09:08.972205 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 18:09:08.976051 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 18:09:08.979098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 18:09:08.985870 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 18:09:08.989316 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 18:09:08.992276 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 18:09:08.999160 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 18:09:09.002367 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 18:09:09.005781 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 18:09:09.009340 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 18:09:09.015773 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 18:09:09.019146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 18:09:09.022408 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 18:09:09.029035 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 18:09:09.032044 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 18:09:09.035613 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 18:09:09.042307 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 18:09:09.045558 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8099 18:09:09.048828 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8100 18:09:09.055722 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 18:09:09.058738 Total UI for P1: 0, mck2ui 16
8102 18:09:09.061985 best dqsien dly found for B0: ( 1, 9, 14)
8103 18:09:09.062583 Total UI for P1: 0, mck2ui 16
8104 18:09:09.068880 best dqsien dly found for B1: ( 1, 9, 14)
8105 18:09:09.071983 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8106 18:09:09.075184 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8107 18:09:09.075767
8108 18:09:09.078908 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8109 18:09:09.082573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8110 18:09:09.085467 [Gating] SW calibration Done
8111 18:09:09.085943 ==
8112 18:09:09.088701 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 18:09:09.091971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 18:09:09.092464 ==
8115 18:09:09.095493 RX Vref Scan: 0
8116 18:09:09.095918
8117 18:09:09.096250 RX Vref 0 -> 0, step: 1
8118 18:09:09.098660
8119 18:09:09.099078 RX Delay 0 -> 252, step: 8
8120 18:09:09.102348 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8121 18:09:09.108679 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8122 18:09:09.112155 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8123 18:09:09.115302 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8124 18:09:09.118578 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8125 18:09:09.122266 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8126 18:09:09.128717 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8127 18:09:09.132115 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8128 18:09:09.135446 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8129 18:09:09.138440 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8130 18:09:09.141908 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8131 18:09:09.148267 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8132 18:09:09.151924 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8133 18:09:09.155013 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8134 18:09:09.158362 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8135 18:09:09.165131 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8136 18:09:09.165553 ==
8137 18:09:09.168289 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 18:09:09.171508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 18:09:09.171929 ==
8140 18:09:09.172258 DQS Delay:
8141 18:09:09.174692 DQS0 = 0, DQS1 = 0
8142 18:09:09.175166 DQM Delay:
8143 18:09:09.178171 DQM0 = 135, DQM1 = 125
8144 18:09:09.178780 DQ Delay:
8145 18:09:09.181401 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8146 18:09:09.185083 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8147 18:09:09.188130 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8148 18:09:09.191244 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8149 18:09:09.191628
8150 18:09:09.191940
8151 18:09:09.194531 ==
8152 18:09:09.198306 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 18:09:09.201370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 18:09:09.201796 ==
8155 18:09:09.202128
8156 18:09:09.202439
8157 18:09:09.204404 TX Vref Scan disable
8158 18:09:09.204877 == TX Byte 0 ==
8159 18:09:09.208024 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8160 18:09:09.214221 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8161 18:09:09.214657 == TX Byte 1 ==
8162 18:09:09.221285 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8163 18:09:09.224335 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8164 18:09:09.224877 ==
8165 18:09:09.227736 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 18:09:09.231143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 18:09:09.231598 ==
8168 18:09:09.245903
8169 18:09:09.249407 TX Vref early break, caculate TX vref
8170 18:09:09.252390 TX Vref=16, minBit 1, minWin=23, winSum=388
8171 18:09:09.256122 TX Vref=18, minBit 0, minWin=24, winSum=394
8172 18:09:09.259206 TX Vref=20, minBit 0, minWin=24, winSum=403
8173 18:09:09.262374 TX Vref=22, minBit 1, minWin=25, winSum=415
8174 18:09:09.265648 TX Vref=24, minBit 2, minWin=25, winSum=419
8175 18:09:09.272438 TX Vref=26, minBit 0, minWin=26, winSum=427
8176 18:09:09.275767 TX Vref=28, minBit 0, minWin=26, winSum=428
8177 18:09:09.279370 TX Vref=30, minBit 0, minWin=25, winSum=423
8178 18:09:09.282391 TX Vref=32, minBit 0, minWin=25, winSum=412
8179 18:09:09.285987 TX Vref=34, minBit 0, minWin=24, winSum=407
8180 18:09:09.289062 TX Vref=36, minBit 7, minWin=24, winSum=399
8181 18:09:09.296096 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8182 18:09:09.296530
8183 18:09:09.299092 Final TX Range 0 Vref 28
8184 18:09:09.299591
8185 18:09:09.299976 ==
8186 18:09:09.302138 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 18:09:09.305940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 18:09:09.306427 ==
8189 18:09:09.306769
8190 18:09:09.307271
8191 18:09:09.309203 TX Vref Scan disable
8192 18:09:09.315477 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8193 18:09:09.315943 == TX Byte 0 ==
8194 18:09:09.319271 u2DelayCellOfst[0]=13 cells (4 PI)
8195 18:09:09.322164 u2DelayCellOfst[1]=17 cells (5 PI)
8196 18:09:09.325584 u2DelayCellOfst[2]=10 cells (3 PI)
8197 18:09:09.328840 u2DelayCellOfst[3]=10 cells (3 PI)
8198 18:09:09.332365 u2DelayCellOfst[4]=6 cells (2 PI)
8199 18:09:09.335446 u2DelayCellOfst[5]=0 cells (0 PI)
8200 18:09:09.338611 u2DelayCellOfst[6]=17 cells (5 PI)
8201 18:09:09.342326 u2DelayCellOfst[7]=17 cells (5 PI)
8202 18:09:09.345292 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8203 18:09:09.349096 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8204 18:09:09.352251 == TX Byte 1 ==
8205 18:09:09.355380 u2DelayCellOfst[8]=0 cells (0 PI)
8206 18:09:09.358590 u2DelayCellOfst[9]=0 cells (0 PI)
8207 18:09:09.359005 u2DelayCellOfst[10]=10 cells (3 PI)
8208 18:09:09.362415 u2DelayCellOfst[11]=3 cells (1 PI)
8209 18:09:09.365469 u2DelayCellOfst[12]=13 cells (4 PI)
8210 18:09:09.368458 u2DelayCellOfst[13]=13 cells (4 PI)
8211 18:09:09.372356 u2DelayCellOfst[14]=17 cells (5 PI)
8212 18:09:09.375353 u2DelayCellOfst[15]=13 cells (4 PI)
8213 18:09:09.382139 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8214 18:09:09.385341 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8215 18:09:09.385915 DramC Write-DBI on
8216 18:09:09.386253 ==
8217 18:09:09.388525 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 18:09:09.395392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 18:09:09.395844 ==
8220 18:09:09.396371
8221 18:09:09.396972
8222 18:09:09.397556 TX Vref Scan disable
8223 18:09:09.399129 == TX Byte 0 ==
8224 18:09:09.402574 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8225 18:09:09.406209 == TX Byte 1 ==
8226 18:09:09.409423 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
8227 18:09:09.412514 DramC Write-DBI off
8228 18:09:09.412963
8229 18:09:09.413293 [DATLAT]
8230 18:09:09.413597 Freq=1600, CH0 RK1
8231 18:09:09.413892
8232 18:09:09.416127 DATLAT Default: 0xf
8233 18:09:09.419157 0, 0xFFFF, sum = 0
8234 18:09:09.419581 1, 0xFFFF, sum = 0
8235 18:09:09.422252 2, 0xFFFF, sum = 0
8236 18:09:09.422720 3, 0xFFFF, sum = 0
8237 18:09:09.425663 4, 0xFFFF, sum = 0
8238 18:09:09.426098 5, 0xFFFF, sum = 0
8239 18:09:09.429078 6, 0xFFFF, sum = 0
8240 18:09:09.429600 7, 0xFFFF, sum = 0
8241 18:09:09.432161 8, 0xFFFF, sum = 0
8242 18:09:09.432613 9, 0xFFFF, sum = 0
8243 18:09:09.435898 10, 0xFFFF, sum = 0
8244 18:09:09.436345 11, 0xFFFF, sum = 0
8245 18:09:09.438833 12, 0xFFFF, sum = 0
8246 18:09:09.439389 13, 0xFFFF, sum = 0
8247 18:09:09.442112 14, 0x0, sum = 1
8248 18:09:09.442639 15, 0x0, sum = 2
8249 18:09:09.445618 16, 0x0, sum = 3
8250 18:09:09.446061 17, 0x0, sum = 4
8251 18:09:09.448802 best_step = 15
8252 18:09:09.449217
8253 18:09:09.449544 ==
8254 18:09:09.452519 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 18:09:09.455661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 18:09:09.456083 ==
8257 18:09:09.459242 RX Vref Scan: 0
8258 18:09:09.459660
8259 18:09:09.459987 RX Vref 0 -> 0, step: 1
8260 18:09:09.460291
8261 18:09:09.462053 RX Delay 11 -> 252, step: 4
8262 18:09:09.468955 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8263 18:09:09.472179 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8264 18:09:09.475746 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8265 18:09:09.478443 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8266 18:09:09.481960 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8267 18:09:09.484980 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8268 18:09:09.492106 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8269 18:09:09.495242 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8270 18:09:09.498401 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8271 18:09:09.501731 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8272 18:09:09.504958 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8273 18:09:09.511769 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8274 18:09:09.515218 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8275 18:09:09.518734 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8276 18:09:09.521805 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8277 18:09:09.528652 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8278 18:09:09.529355 ==
8279 18:09:09.532019 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 18:09:09.535101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 18:09:09.535530 ==
8282 18:09:09.535863 DQS Delay:
8283 18:09:09.538326 DQS0 = 0, DQS1 = 0
8284 18:09:09.538794 DQM Delay:
8285 18:09:09.541677 DQM0 = 132, DQM1 = 123
8286 18:09:09.542283 DQ Delay:
8287 18:09:09.544932 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =130
8288 18:09:09.548671 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8289 18:09:09.551735 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8290 18:09:09.555328 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8291 18:09:09.555973
8292 18:09:09.556483
8293 18:09:09.557004
8294 18:09:09.558526 [DramC_TX_OE_Calibration] TA2
8295 18:09:09.561634 Original DQ_B0 (3 6) =30, OEN = 27
8296 18:09:09.565284 Original DQ_B1 (3 6) =30, OEN = 27
8297 18:09:09.568540 24, 0x0, End_B0=24 End_B1=24
8298 18:09:09.571608 25, 0x0, End_B0=25 End_B1=25
8299 18:09:09.572074 26, 0x0, End_B0=26 End_B1=26
8300 18:09:09.575204 27, 0x0, End_B0=27 End_B1=27
8301 18:09:09.578492 28, 0x0, End_B0=28 End_B1=28
8302 18:09:09.581587 29, 0x0, End_B0=29 End_B1=29
8303 18:09:09.585138 30, 0x0, End_B0=30 End_B1=30
8304 18:09:09.585680 31, 0x4141, End_B0=30 End_B1=30
8305 18:09:09.588542 Byte0 end_step=30 best_step=27
8306 18:09:09.591636 Byte1 end_step=30 best_step=27
8307 18:09:09.594841 Byte0 TX OE(2T, 0.5T) = (3, 3)
8308 18:09:09.598444 Byte1 TX OE(2T, 0.5T) = (3, 3)
8309 18:09:09.599072
8310 18:09:09.599517
8311 18:09:09.605163 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8312 18:09:09.608184 CH0 RK1: MR19=303, MR18=1D0B
8313 18:09:09.615240 CH0_RK1: MR19=0x303, MR18=0x1D0B, DQSOSC=395, MR23=63, INC=23, DEC=15
8314 18:09:09.618353 [RxdqsGatingPostProcess] freq 1600
8315 18:09:09.625312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8316 18:09:09.625747 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 18:09:09.628220 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 18:09:09.631285 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 18:09:09.634929 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 18:09:09.638506 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 18:09:09.641718 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 18:09:09.644500 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 18:09:09.648164 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 18:09:09.651272 Pre-setting of DQS Precalculation
8325 18:09:09.655091 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8326 18:09:09.655507 ==
8327 18:09:09.658006 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 18:09:09.664969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 18:09:09.665463 ==
8330 18:09:09.667957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 18:09:09.674251 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 18:09:09.678195 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 18:09:09.684270 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 18:09:09.692193 [CA 0] Center 42 (13~72) winsize 60
8335 18:09:09.695439 [CA 1] Center 42 (12~73) winsize 62
8336 18:09:09.698968 [CA 2] Center 39 (10~68) winsize 59
8337 18:09:09.702134 [CA 3] Center 37 (8~67) winsize 60
8338 18:09:09.705330 [CA 4] Center 37 (8~67) winsize 60
8339 18:09:09.708519 [CA 5] Center 37 (8~67) winsize 60
8340 18:09:09.709167
8341 18:09:09.712053 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8342 18:09:09.712686
8343 18:09:09.715170 [CATrainingPosCal] consider 1 rank data
8344 18:09:09.718783 u2DelayCellTimex100 = 285/100 ps
8345 18:09:09.725675 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8346 18:09:09.728622 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8347 18:09:09.732228 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8348 18:09:09.735348 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8349 18:09:09.738801 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8350 18:09:09.742001 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8351 18:09:09.742918
8352 18:09:09.744979 CA PerBit enable=1, Macro0, CA PI delay=37
8353 18:09:09.745500
8354 18:09:09.748492 [CBTSetCACLKResult] CA Dly = 37
8355 18:09:09.751679 CS Dly: 9 (0~40)
8356 18:09:09.755271 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 18:09:09.758323 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 18:09:09.758753 ==
8359 18:09:09.761866 Dram Type= 6, Freq= 0, CH_1, rank 1
8360 18:09:09.768067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 18:09:09.768759 ==
8362 18:09:09.771784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 18:09:09.774780 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 18:09:09.781693 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 18:09:09.787928 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 18:09:09.795460 [CA 0] Center 42 (13~72) winsize 60
8367 18:09:09.799125 [CA 1] Center 42 (13~72) winsize 60
8368 18:09:09.802201 [CA 2] Center 38 (9~68) winsize 60
8369 18:09:09.805399 [CA 3] Center 37 (8~67) winsize 60
8370 18:09:09.808404 [CA 4] Center 39 (10~68) winsize 59
8371 18:09:09.812263 [CA 5] Center 38 (8~68) winsize 61
8372 18:09:09.812678
8373 18:09:09.815417 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8374 18:09:09.815710
8375 18:09:09.819107 [CATrainingPosCal] consider 2 rank data
8376 18:09:09.822204 u2DelayCellTimex100 = 285/100 ps
8377 18:09:09.825437 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8378 18:09:09.832307 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8379 18:09:09.835213 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8380 18:09:09.838586 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8381 18:09:09.842210 CA4 delay=38 (10~67),Diff = 1 PI (3 cell)
8382 18:09:09.845155 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8383 18:09:09.845451
8384 18:09:09.848890 CA PerBit enable=1, Macro0, CA PI delay=37
8385 18:09:09.849184
8386 18:09:09.852614 [CBTSetCACLKResult] CA Dly = 37
8387 18:09:09.855236 CS Dly: 10 (0~42)
8388 18:09:09.858581 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 18:09:09.861720 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 18:09:09.862034
8391 18:09:09.865213 ----->DramcWriteLeveling(PI) begin...
8392 18:09:09.865458 ==
8393 18:09:09.868667 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 18:09:09.875107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 18:09:09.875611 ==
8396 18:09:09.878652 Write leveling (Byte 0): 24 => 24
8397 18:09:09.879060 Write leveling (Byte 1): 29 => 29
8398 18:09:09.881886 DramcWriteLeveling(PI) end<-----
8399 18:09:09.882444
8400 18:09:09.882778 ==
8401 18:09:09.885408 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 18:09:09.892278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 18:09:09.892803 ==
8404 18:09:09.895064 [Gating] SW mode calibration
8405 18:09:09.901920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8406 18:09:09.905020 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8407 18:09:09.911842 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 18:09:09.914886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 18:09:09.918588 1 4 8 | B1->B0 | 2525 3131 | 0 1 | (0 0) (1 1)
8410 18:09:09.924992 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8411 18:09:09.928629 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 18:09:09.931765 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 18:09:09.938774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 18:09:09.941597 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 18:09:09.944850 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 18:09:09.948575 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8417 18:09:09.955234 1 5 8 | B1->B0 | 3131 2727 | 1 0 | (1 0) (0 0)
8418 18:09:09.958260 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8419 18:09:09.962036 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 18:09:09.968376 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 18:09:09.971747 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 18:09:09.975053 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 18:09:09.981340 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 18:09:09.985080 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8425 18:09:09.988620 1 6 8 | B1->B0 | 2f2f 4444 | 1 0 | (0 0) (0 0)
8426 18:09:09.994871 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 18:09:09.998233 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 18:09:10.001969 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 18:09:10.008200 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 18:09:10.011605 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 18:09:10.014758 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 18:09:10.021579 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 18:09:10.024933 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8434 18:09:10.027960 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8435 18:09:10.035043 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8436 18:09:10.038302 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 18:09:10.041394 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 18:09:10.048165 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 18:09:10.051429 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 18:09:10.054886 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 18:09:10.061549 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 18:09:10.064881 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 18:09:10.068072 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 18:09:10.071136 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 18:09:10.077963 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 18:09:10.081157 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 18:09:10.084889 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 18:09:10.091083 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 18:09:10.094811 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8450 18:09:10.098004 Total UI for P1: 0, mck2ui 16
8451 18:09:10.101132 best dqsien dly found for B0: ( 1, 9, 6)
8452 18:09:10.104953 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8453 18:09:10.111163 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 18:09:10.114678 Total UI for P1: 0, mck2ui 16
8455 18:09:10.117771 best dqsien dly found for B1: ( 1, 9, 10)
8456 18:09:10.121011 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8457 18:09:10.124257 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8458 18:09:10.124705
8459 18:09:10.128193 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8460 18:09:10.131159 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8461 18:09:10.134470 [Gating] SW calibration Done
8462 18:09:10.135140 ==
8463 18:09:10.137512 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 18:09:10.140662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 18:09:10.141082 ==
8466 18:09:10.144401 RX Vref Scan: 0
8467 18:09:10.145079
8468 18:09:10.147452 RX Vref 0 -> 0, step: 1
8469 18:09:10.147966
8470 18:09:10.148380 RX Delay 0 -> 252, step: 8
8471 18:09:10.154122 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8472 18:09:10.157322 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8473 18:09:10.160758 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8474 18:09:10.163932 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8475 18:09:10.167520 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8476 18:09:10.171314 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8477 18:09:10.177471 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8478 18:09:10.180996 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8479 18:09:10.184108 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8480 18:09:10.187662 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8481 18:09:10.190854 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8482 18:09:10.197522 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8483 18:09:10.200786 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8484 18:09:10.204368 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8485 18:09:10.207435 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8486 18:09:10.210715 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8487 18:09:10.213926 ==
8488 18:09:10.214361 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 18:09:10.220683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 18:09:10.221135 ==
8491 18:09:10.221471 DQS Delay:
8492 18:09:10.223814 DQS0 = 0, DQS1 = 0
8493 18:09:10.224250 DQM Delay:
8494 18:09:10.227559 DQM0 = 139, DQM1 = 130
8495 18:09:10.227981 DQ Delay:
8496 18:09:10.230694 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8497 18:09:10.233902 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8498 18:09:10.237095 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8499 18:09:10.240862 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8500 18:09:10.241356
8501 18:09:10.241693
8502 18:09:10.241997 ==
8503 18:09:10.243932 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 18:09:10.250465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 18:09:10.250882 ==
8506 18:09:10.251215
8507 18:09:10.251632
8508 18:09:10.251941 TX Vref Scan disable
8509 18:09:10.253910 == TX Byte 0 ==
8510 18:09:10.257053 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 18:09:10.263991 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8512 18:09:10.264731 == TX Byte 1 ==
8513 18:09:10.266957 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8514 18:09:10.273618 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8515 18:09:10.274039 ==
8516 18:09:10.277027 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 18:09:10.280201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 18:09:10.280647 ==
8519 18:09:10.294328
8520 18:09:10.297533 TX Vref early break, caculate TX vref
8521 18:09:10.300445 TX Vref=16, minBit 8, minWin=22, winSum=370
8522 18:09:10.303944 TX Vref=18, minBit 15, minWin=21, winSum=381
8523 18:09:10.307262 TX Vref=20, minBit 10, minWin=23, winSum=387
8524 18:09:10.311169 TX Vref=22, minBit 9, minWin=24, winSum=402
8525 18:09:10.313989 TX Vref=24, minBit 15, minWin=24, winSum=407
8526 18:09:10.320661 TX Vref=26, minBit 10, minWin=25, winSum=421
8527 18:09:10.324178 TX Vref=28, minBit 9, minWin=25, winSum=420
8528 18:09:10.327142 TX Vref=30, minBit 10, minWin=25, winSum=420
8529 18:09:10.330474 TX Vref=32, minBit 9, minWin=24, winSum=406
8530 18:09:10.333646 TX Vref=34, minBit 10, minWin=23, winSum=399
8531 18:09:10.340426 TX Vref=36, minBit 10, minWin=23, winSum=389
8532 18:09:10.343765 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 26
8533 18:09:10.344180
8534 18:09:10.347080 Final TX Range 0 Vref 26
8535 18:09:10.347595
8536 18:09:10.347922 ==
8537 18:09:10.350567 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 18:09:10.353765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 18:09:10.357187 ==
8540 18:09:10.357615
8541 18:09:10.357964
8542 18:09:10.358295 TX Vref Scan disable
8543 18:09:10.364070 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8544 18:09:10.364727 == TX Byte 0 ==
8545 18:09:10.367604 u2DelayCellOfst[0]=20 cells (6 PI)
8546 18:09:10.370893 u2DelayCellOfst[1]=13 cells (4 PI)
8547 18:09:10.373963 u2DelayCellOfst[2]=0 cells (0 PI)
8548 18:09:10.377430 u2DelayCellOfst[3]=10 cells (3 PI)
8549 18:09:10.380659 u2DelayCellOfst[4]=10 cells (3 PI)
8550 18:09:10.383861 u2DelayCellOfst[5]=20 cells (6 PI)
8551 18:09:10.387007 u2DelayCellOfst[6]=20 cells (6 PI)
8552 18:09:10.390421 u2DelayCellOfst[7]=6 cells (2 PI)
8553 18:09:10.393647 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8554 18:09:10.397142 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8555 18:09:10.400664 == TX Byte 1 ==
8556 18:09:10.403700 u2DelayCellOfst[8]=0 cells (0 PI)
8557 18:09:10.407276 u2DelayCellOfst[9]=3 cells (1 PI)
8558 18:09:10.410596 u2DelayCellOfst[10]=13 cells (4 PI)
8559 18:09:10.414087 u2DelayCellOfst[11]=6 cells (2 PI)
8560 18:09:10.414502 u2DelayCellOfst[12]=17 cells (5 PI)
8561 18:09:10.417253 u2DelayCellOfst[13]=17 cells (5 PI)
8562 18:09:10.420349 u2DelayCellOfst[14]=17 cells (5 PI)
8563 18:09:10.423708 u2DelayCellOfst[15]=17 cells (5 PI)
8564 18:09:10.430681 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8565 18:09:10.433787 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8566 18:09:10.434221 DramC Write-DBI on
8567 18:09:10.436814 ==
8568 18:09:10.437244 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 18:09:10.443720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 18:09:10.444138 ==
8571 18:09:10.444465
8572 18:09:10.444803
8573 18:09:10.446939 TX Vref Scan disable
8574 18:09:10.447590 == TX Byte 0 ==
8575 18:09:10.453791 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8576 18:09:10.454207 == TX Byte 1 ==
8577 18:09:10.457046 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8578 18:09:10.460090 DramC Write-DBI off
8579 18:09:10.460524
8580 18:09:10.461059 [DATLAT]
8581 18:09:10.463342 Freq=1600, CH1 RK0
8582 18:09:10.463761
8583 18:09:10.464088 DATLAT Default: 0xf
8584 18:09:10.467082 0, 0xFFFF, sum = 0
8585 18:09:10.467505 1, 0xFFFF, sum = 0
8586 18:09:10.470256 2, 0xFFFF, sum = 0
8587 18:09:10.470815 3, 0xFFFF, sum = 0
8588 18:09:10.473528 4, 0xFFFF, sum = 0
8589 18:09:10.474036 5, 0xFFFF, sum = 0
8590 18:09:10.476586 6, 0xFFFF, sum = 0
8591 18:09:10.477015 7, 0xFFFF, sum = 0
8592 18:09:10.480163 8, 0xFFFF, sum = 0
8593 18:09:10.480656 9, 0xFFFF, sum = 0
8594 18:09:10.483304 10, 0xFFFF, sum = 0
8595 18:09:10.486958 11, 0xFFFF, sum = 0
8596 18:09:10.487466 12, 0xFFFF, sum = 0
8597 18:09:10.489943 13, 0xFFFF, sum = 0
8598 18:09:10.490369 14, 0x0, sum = 1
8599 18:09:10.493034 15, 0x0, sum = 2
8600 18:09:10.493455 16, 0x0, sum = 3
8601 18:09:10.496751 17, 0x0, sum = 4
8602 18:09:10.497187 best_step = 15
8603 18:09:10.497512
8604 18:09:10.497814 ==
8605 18:09:10.499917 Dram Type= 6, Freq= 0, CH_1, rank 0
8606 18:09:10.503326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8607 18:09:10.503745 ==
8608 18:09:10.506429 RX Vref Scan: 1
8609 18:09:10.506840
8610 18:09:10.509643 Set Vref Range= 24 -> 127
8611 18:09:10.510199
8612 18:09:10.510668 RX Vref 24 -> 127, step: 1
8613 18:09:10.511114
8614 18:09:10.513325 RX Delay 19 -> 252, step: 4
8615 18:09:10.513737
8616 18:09:10.516459 Set Vref, RX VrefLevel [Byte0]: 24
8617 18:09:10.519606 [Byte1]: 24
8618 18:09:10.523199
8619 18:09:10.523633 Set Vref, RX VrefLevel [Byte0]: 25
8620 18:09:10.526530 [Byte1]: 25
8621 18:09:10.530978
8622 18:09:10.531630 Set Vref, RX VrefLevel [Byte0]: 26
8623 18:09:10.534083 [Byte1]: 26
8624 18:09:10.538182
8625 18:09:10.538594 Set Vref, RX VrefLevel [Byte0]: 27
8626 18:09:10.541623 [Byte1]: 27
8627 18:09:10.545849
8628 18:09:10.546368 Set Vref, RX VrefLevel [Byte0]: 28
8629 18:09:10.549102 [Byte1]: 28
8630 18:09:10.553226
8631 18:09:10.553872 Set Vref, RX VrefLevel [Byte0]: 29
8632 18:09:10.556940 [Byte1]: 29
8633 18:09:10.560674
8634 18:09:10.561108 Set Vref, RX VrefLevel [Byte0]: 30
8635 18:09:10.564396 [Byte1]: 30
8636 18:09:10.568633
8637 18:09:10.569015 Set Vref, RX VrefLevel [Byte0]: 31
8638 18:09:10.572176 [Byte1]: 31
8639 18:09:10.576384
8640 18:09:10.577130 Set Vref, RX VrefLevel [Byte0]: 32
8641 18:09:10.579218 [Byte1]: 32
8642 18:09:10.584006
8643 18:09:10.584422 Set Vref, RX VrefLevel [Byte0]: 33
8644 18:09:10.587220 [Byte1]: 33
8645 18:09:10.591354
8646 18:09:10.591763 Set Vref, RX VrefLevel [Byte0]: 34
8647 18:09:10.594664 [Byte1]: 34
8648 18:09:10.598951
8649 18:09:10.599395 Set Vref, RX VrefLevel [Byte0]: 35
8650 18:09:10.602035 [Byte1]: 35
8651 18:09:10.606848
8652 18:09:10.607260 Set Vref, RX VrefLevel [Byte0]: 36
8653 18:09:10.609991 [Byte1]: 36
8654 18:09:10.614177
8655 18:09:10.614701 Set Vref, RX VrefLevel [Byte0]: 37
8656 18:09:10.620869 [Byte1]: 37
8657 18:09:10.621390
8658 18:09:10.623806 Set Vref, RX VrefLevel [Byte0]: 38
8659 18:09:10.626920 [Byte1]: 38
8660 18:09:10.627344
8661 18:09:10.630641 Set Vref, RX VrefLevel [Byte0]: 39
8662 18:09:10.633851 [Byte1]: 39
8663 18:09:10.634261
8664 18:09:10.637164 Set Vref, RX VrefLevel [Byte0]: 40
8665 18:09:10.640332 [Byte1]: 40
8666 18:09:10.644399
8667 18:09:10.644970 Set Vref, RX VrefLevel [Byte0]: 41
8668 18:09:10.647705 [Byte1]: 41
8669 18:09:10.652055
8670 18:09:10.652466 Set Vref, RX VrefLevel [Byte0]: 42
8671 18:09:10.655131 [Byte1]: 42
8672 18:09:10.659492
8673 18:09:10.660208 Set Vref, RX VrefLevel [Byte0]: 43
8674 18:09:10.662422 [Byte1]: 43
8675 18:09:10.666948
8676 18:09:10.667375 Set Vref, RX VrefLevel [Byte0]: 44
8677 18:09:10.670557 [Byte1]: 44
8678 18:09:10.674605
8679 18:09:10.675179 Set Vref, RX VrefLevel [Byte0]: 45
8680 18:09:10.677754 [Byte1]: 45
8681 18:09:10.682315
8682 18:09:10.682723 Set Vref, RX VrefLevel [Byte0]: 46
8683 18:09:10.685324 [Byte1]: 46
8684 18:09:10.689547
8685 18:09:10.690048 Set Vref, RX VrefLevel [Byte0]: 47
8686 18:09:10.693109 [Byte1]: 47
8687 18:09:10.697310
8688 18:09:10.697720 Set Vref, RX VrefLevel [Byte0]: 48
8689 18:09:10.700440 [Byte1]: 48
8690 18:09:10.705211
8691 18:09:10.705874 Set Vref, RX VrefLevel [Byte0]: 49
8692 18:09:10.708218 [Byte1]: 49
8693 18:09:10.712324
8694 18:09:10.712799 Set Vref, RX VrefLevel [Byte0]: 50
8695 18:09:10.715938 [Byte1]: 50
8696 18:09:10.719897
8697 18:09:10.720326 Set Vref, RX VrefLevel [Byte0]: 51
8698 18:09:10.723394 [Byte1]: 51
8699 18:09:10.727551
8700 18:09:10.727964 Set Vref, RX VrefLevel [Byte0]: 52
8701 18:09:10.730757 [Byte1]: 52
8702 18:09:10.735291
8703 18:09:10.735796 Set Vref, RX VrefLevel [Byte0]: 53
8704 18:09:10.738461 [Byte1]: 53
8705 18:09:10.743395
8706 18:09:10.744211 Set Vref, RX VrefLevel [Byte0]: 54
8707 18:09:10.746322 [Byte1]: 54
8708 18:09:10.750606
8709 18:09:10.751021 Set Vref, RX VrefLevel [Byte0]: 55
8710 18:09:10.754138 [Byte1]: 55
8711 18:09:10.757879
8712 18:09:10.758518 Set Vref, RX VrefLevel [Byte0]: 56
8713 18:09:10.761106 [Byte1]: 56
8714 18:09:10.765518
8715 18:09:10.765992 Set Vref, RX VrefLevel [Byte0]: 57
8716 18:09:10.768588 [Byte1]: 57
8717 18:09:10.772877
8718 18:09:10.773271 Set Vref, RX VrefLevel [Byte0]: 58
8719 18:09:10.776101 [Byte1]: 58
8720 18:09:10.780679
8721 18:09:10.781317 Set Vref, RX VrefLevel [Byte0]: 59
8722 18:09:10.783930 [Byte1]: 59
8723 18:09:10.788121
8724 18:09:10.788845 Set Vref, RX VrefLevel [Byte0]: 60
8725 18:09:10.791707 [Byte1]: 60
8726 18:09:10.795910
8727 18:09:10.796782 Set Vref, RX VrefLevel [Byte0]: 61
8728 18:09:10.799399 [Byte1]: 61
8729 18:09:10.802989
8730 18:09:10.803626 Set Vref, RX VrefLevel [Byte0]: 62
8731 18:09:10.806868 [Byte1]: 62
8732 18:09:10.810696
8733 18:09:10.811168 Set Vref, RX VrefLevel [Byte0]: 63
8734 18:09:10.814424 [Byte1]: 63
8735 18:09:10.818505
8736 18:09:10.819092 Set Vref, RX VrefLevel [Byte0]: 64
8737 18:09:10.821592 [Byte1]: 64
8738 18:09:10.825820
8739 18:09:10.826267 Set Vref, RX VrefLevel [Byte0]: 65
8740 18:09:10.829166 [Byte1]: 65
8741 18:09:10.833745
8742 18:09:10.834186 Set Vref, RX VrefLevel [Byte0]: 66
8743 18:09:10.837093 [Byte1]: 66
8744 18:09:10.841347
8745 18:09:10.841829 Set Vref, RX VrefLevel [Byte0]: 67
8746 18:09:10.844412 [Byte1]: 67
8747 18:09:10.848977
8748 18:09:10.849693 Set Vref, RX VrefLevel [Byte0]: 68
8749 18:09:10.852171 [Byte1]: 68
8750 18:09:10.855887
8751 18:09:10.856249 Set Vref, RX VrefLevel [Byte0]: 69
8752 18:09:10.859752 [Byte1]: 69
8753 18:09:10.864171
8754 18:09:10.864626 Set Vref, RX VrefLevel [Byte0]: 70
8755 18:09:10.867364 [Byte1]: 70
8756 18:09:10.871958
8757 18:09:10.872711 Set Vref, RX VrefLevel [Byte0]: 71
8758 18:09:10.874892 [Byte1]: 71
8759 18:09:10.879002
8760 18:09:10.879422 Set Vref, RX VrefLevel [Byte0]: 72
8761 18:09:10.882425 [Byte1]: 72
8762 18:09:10.886451
8763 18:09:10.886876 Set Vref, RX VrefLevel [Byte0]: 73
8764 18:09:10.889711 [Byte1]: 73
8765 18:09:10.894245
8766 18:09:10.894909 Set Vref, RX VrefLevel [Byte0]: 74
8767 18:09:10.897317 [Byte1]: 74
8768 18:09:10.901894
8769 18:09:10.902558 Set Vref, RX VrefLevel [Byte0]: 75
8770 18:09:10.905064 [Byte1]: 75
8771 18:09:10.909214
8772 18:09:10.909627 Set Vref, RX VrefLevel [Byte0]: 76
8773 18:09:10.912708 [Byte1]: 76
8774 18:09:10.917187
8775 18:09:10.917595 Final RX Vref Byte 0 = 61 to rank0
8776 18:09:10.920412 Final RX Vref Byte 1 = 61 to rank0
8777 18:09:10.923610 Final RX Vref Byte 0 = 61 to rank1
8778 18:09:10.927334 Final RX Vref Byte 1 = 61 to rank1==
8779 18:09:10.930507 Dram Type= 6, Freq= 0, CH_1, rank 0
8780 18:09:10.936992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 18:09:10.937406 ==
8782 18:09:10.937763 DQS Delay:
8783 18:09:10.938072 DQS0 = 0, DQS1 = 0
8784 18:09:10.940603 DQM Delay:
8785 18:09:10.941030 DQM0 = 135, DQM1 = 129
8786 18:09:10.943830 DQ Delay:
8787 18:09:10.947491 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =134
8788 18:09:10.950633 DQ4 =132, DQ5 =146, DQ6 =148, DQ7 =132
8789 18:09:10.953421 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8790 18:09:10.957219 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8791 18:09:10.957638
8792 18:09:10.957965
8793 18:09:10.958269
8794 18:09:10.960402 [DramC_TX_OE_Calibration] TA2
8795 18:09:10.963479 Original DQ_B0 (3 6) =30, OEN = 27
8796 18:09:10.966712 Original DQ_B1 (3 6) =30, OEN = 27
8797 18:09:10.969918 24, 0x0, End_B0=24 End_B1=24
8798 18:09:10.970383 25, 0x0, End_B0=25 End_B1=25
8799 18:09:10.973991 26, 0x0, End_B0=26 End_B1=26
8800 18:09:10.976974 27, 0x0, End_B0=27 End_B1=27
8801 18:09:10.980039 28, 0x0, End_B0=28 End_B1=28
8802 18:09:10.983389 29, 0x0, End_B0=29 End_B1=29
8803 18:09:10.983908 30, 0x0, End_B0=30 End_B1=30
8804 18:09:10.987071 31, 0x4141, End_B0=30 End_B1=30
8805 18:09:10.989787 Byte0 end_step=30 best_step=27
8806 18:09:10.993281 Byte1 end_step=30 best_step=27
8807 18:09:10.996440 Byte0 TX OE(2T, 0.5T) = (3, 3)
8808 18:09:10.999911 Byte1 TX OE(2T, 0.5T) = (3, 3)
8809 18:09:11.000460
8810 18:09:11.000975
8811 18:09:11.006551 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8812 18:09:11.009798 CH1 RK0: MR19=303, MR18=1725
8813 18:09:11.016254 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8814 18:09:11.016717
8815 18:09:11.019775 ----->DramcWriteLeveling(PI) begin...
8816 18:09:11.020196 ==
8817 18:09:11.023274 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 18:09:11.026347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 18:09:11.026776 ==
8820 18:09:11.029503 Write leveling (Byte 0): 24 => 24
8821 18:09:11.033286 Write leveling (Byte 1): 30 => 30
8822 18:09:11.036208 DramcWriteLeveling(PI) end<-----
8823 18:09:11.036617
8824 18:09:11.036946 ==
8825 18:09:11.039425 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 18:09:11.043020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 18:09:11.043441 ==
8828 18:09:11.046749 [Gating] SW mode calibration
8829 18:09:11.053151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8830 18:09:11.059996 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8831 18:09:11.063024 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 18:09:11.066687 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 18:09:11.073185 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
8834 18:09:11.076282 1 4 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8835 18:09:11.079829 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 18:09:11.086783 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 18:09:11.089921 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 18:09:11.093037 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 18:09:11.099725 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 18:09:11.103060 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 18:09:11.105975 1 5 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 1) (1 0)
8842 18:09:11.112938 1 5 12 | B1->B0 | 2323 2e2e | 0 1 | (1 0) (1 0)
8843 18:09:11.116037 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 18:09:11.119982 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 18:09:11.126302 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 18:09:11.129549 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 18:09:11.133043 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 18:09:11.139588 1 6 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8849 18:09:11.142553 1 6 8 | B1->B0 | 4444 2323 | 1 0 | (0 0) (0 0)
8850 18:09:11.146377 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8851 18:09:11.152309 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 18:09:11.155828 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 18:09:11.158940 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 18:09:11.165987 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 18:09:11.169169 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 18:09:11.172320 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 18:09:11.179144 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8858 18:09:11.182477 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 18:09:11.186591 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 18:09:11.192692 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 18:09:11.196144 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 18:09:11.199042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 18:09:11.202783 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 18:09:11.209172 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 18:09:11.212158 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 18:09:11.215709 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 18:09:11.222435 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 18:09:11.226009 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 18:09:11.228982 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 18:09:11.235607 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 18:09:11.238745 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 18:09:11.242970 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8873 18:09:11.248808 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8874 18:09:11.252189 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 18:09:11.255387 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 18:09:11.258633 Total UI for P1: 0, mck2ui 16
8877 18:09:11.262410 best dqsien dly found for B0: ( 1, 9, 8)
8878 18:09:11.265518 Total UI for P1: 0, mck2ui 16
8879 18:09:11.268827 best dqsien dly found for B1: ( 1, 9, 10)
8880 18:09:11.271983 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8881 18:09:11.276108 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8882 18:09:11.276717
8883 18:09:11.282386 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8884 18:09:11.285445 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8885 18:09:11.288699 [Gating] SW calibration Done
8886 18:09:11.289258 ==
8887 18:09:11.291788 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 18:09:11.295305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 18:09:11.295727 ==
8890 18:09:11.296060 RX Vref Scan: 0
8891 18:09:11.296366
8892 18:09:11.298631 RX Vref 0 -> 0, step: 1
8893 18:09:11.299049
8894 18:09:11.302274 RX Delay 0 -> 252, step: 8
8895 18:09:11.305292 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8896 18:09:11.308544 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8897 18:09:11.312096 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8898 18:09:11.318346 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8899 18:09:11.322048 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8900 18:09:11.325051 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8901 18:09:11.329000 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8902 18:09:11.332197 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8903 18:09:11.338574 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8904 18:09:11.342143 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8905 18:09:11.345050 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8906 18:09:11.348648 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8907 18:09:11.351867 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8908 18:09:11.358738 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8909 18:09:11.361907 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8910 18:09:11.365196 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8911 18:09:11.365724 ==
8912 18:09:11.368984 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 18:09:11.371651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 18:09:11.374872 ==
8915 18:09:11.375295 DQS Delay:
8916 18:09:11.375629 DQS0 = 0, DQS1 = 0
8917 18:09:11.378162 DQM Delay:
8918 18:09:11.378584 DQM0 = 139, DQM1 = 132
8919 18:09:11.381464 DQ Delay:
8920 18:09:11.385171 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8921 18:09:11.388293 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =139
8922 18:09:11.391689 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8923 18:09:11.394876 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8924 18:09:11.395296
8925 18:09:11.395625
8926 18:09:11.395929 ==
8927 18:09:11.398137 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 18:09:11.401387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 18:09:11.401812 ==
8930 18:09:11.402147
8931 18:09:11.402455
8932 18:09:11.405086 TX Vref Scan disable
8933 18:09:11.408355 == TX Byte 0 ==
8934 18:09:11.411485 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8935 18:09:11.415510 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8936 18:09:11.418163 == TX Byte 1 ==
8937 18:09:11.421776 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8938 18:09:11.424483 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8939 18:09:11.424590 ==
8940 18:09:11.427913 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 18:09:11.434353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 18:09:11.434534 ==
8943 18:09:11.446507
8944 18:09:11.449703 TX Vref early break, caculate TX vref
8945 18:09:11.453302 TX Vref=16, minBit 9, minWin=22, winSum=380
8946 18:09:11.456885 TX Vref=18, minBit 13, minWin=22, winSum=393
8947 18:09:11.460165 TX Vref=20, minBit 9, minWin=23, winSum=400
8948 18:09:11.462763 TX Vref=22, minBit 9, minWin=24, winSum=408
8949 18:09:11.466249 TX Vref=24, minBit 9, minWin=24, winSum=416
8950 18:09:11.473256 TX Vref=26, minBit 11, minWin=25, winSum=422
8951 18:09:11.476757 TX Vref=28, minBit 15, minWin=24, winSum=423
8952 18:09:11.479671 TX Vref=30, minBit 15, minWin=24, winSum=420
8953 18:09:11.482885 TX Vref=32, minBit 9, minWin=24, winSum=410
8954 18:09:11.486237 TX Vref=34, minBit 9, minWin=24, winSum=397
8955 18:09:11.493094 [TxChooseVref] Worse bit 11, Min win 25, Win sum 422, Final Vref 26
8956 18:09:11.493607
8957 18:09:11.496604 Final TX Range 0 Vref 26
8958 18:09:11.497134
8959 18:09:11.497470 ==
8960 18:09:11.500103 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 18:09:11.503046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 18:09:11.503486 ==
8963 18:09:11.503839
8964 18:09:11.504178
8965 18:09:11.506302 TX Vref Scan disable
8966 18:09:11.513141 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8967 18:09:11.513596 == TX Byte 0 ==
8968 18:09:11.516185 u2DelayCellOfst[0]=17 cells (5 PI)
8969 18:09:11.519994 u2DelayCellOfst[1]=13 cells (4 PI)
8970 18:09:11.523093 u2DelayCellOfst[2]=0 cells (0 PI)
8971 18:09:11.526072 u2DelayCellOfst[3]=6 cells (2 PI)
8972 18:09:11.529796 u2DelayCellOfst[4]=10 cells (3 PI)
8973 18:09:11.532702 u2DelayCellOfst[5]=20 cells (6 PI)
8974 18:09:11.536208 u2DelayCellOfst[6]=20 cells (6 PI)
8975 18:09:11.539490 u2DelayCellOfst[7]=6 cells (2 PI)
8976 18:09:11.542674 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8977 18:09:11.546289 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8978 18:09:11.549446 == TX Byte 1 ==
8979 18:09:11.552900 u2DelayCellOfst[8]=0 cells (0 PI)
8980 18:09:11.553321 u2DelayCellOfst[9]=6 cells (2 PI)
8981 18:09:11.556326 u2DelayCellOfst[10]=10 cells (3 PI)
8982 18:09:11.559517 u2DelayCellOfst[11]=3 cells (1 PI)
8983 18:09:11.562868 u2DelayCellOfst[12]=13 cells (4 PI)
8984 18:09:11.565843 u2DelayCellOfst[13]=17 cells (5 PI)
8985 18:09:11.569525 u2DelayCellOfst[14]=17 cells (5 PI)
8986 18:09:11.572898 u2DelayCellOfst[15]=17 cells (5 PI)
8987 18:09:11.576196 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8988 18:09:11.583012 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8989 18:09:11.583530 DramC Write-DBI on
8990 18:09:11.583866 ==
8991 18:09:11.586036 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 18:09:11.589854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 18:09:11.592758 ==
8994 18:09:11.593178
8995 18:09:11.593506
8996 18:09:11.593808 TX Vref Scan disable
8997 18:09:11.596437 == TX Byte 0 ==
8998 18:09:11.599984 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8999 18:09:11.603159 == TX Byte 1 ==
9000 18:09:11.606206 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9001 18:09:11.610210 DramC Write-DBI off
9002 18:09:11.610740
9003 18:09:11.611079 [DATLAT]
9004 18:09:11.611390 Freq=1600, CH1 RK1
9005 18:09:11.611695
9006 18:09:11.613007 DATLAT Default: 0xf
9007 18:09:11.613425 0, 0xFFFF, sum = 0
9008 18:09:11.616068 1, 0xFFFF, sum = 0
9009 18:09:11.619693 2, 0xFFFF, sum = 0
9010 18:09:11.620352 3, 0xFFFF, sum = 0
9011 18:09:11.622899 4, 0xFFFF, sum = 0
9012 18:09:11.623346 5, 0xFFFF, sum = 0
9013 18:09:11.626253 6, 0xFFFF, sum = 0
9014 18:09:11.626705 7, 0xFFFF, sum = 0
9015 18:09:11.629654 8, 0xFFFF, sum = 0
9016 18:09:11.630082 9, 0xFFFF, sum = 0
9017 18:09:11.632645 10, 0xFFFF, sum = 0
9018 18:09:11.633072 11, 0xFFFF, sum = 0
9019 18:09:11.636648 12, 0xFFFF, sum = 0
9020 18:09:11.637179 13, 0xFFFF, sum = 0
9021 18:09:11.639294 14, 0x0, sum = 1
9022 18:09:11.639815 15, 0x0, sum = 2
9023 18:09:11.643250 16, 0x0, sum = 3
9024 18:09:11.643774 17, 0x0, sum = 4
9025 18:09:11.645999 best_step = 15
9026 18:09:11.646413
9027 18:09:11.646766 ==
9028 18:09:11.649761 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 18:09:11.652741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 18:09:11.653162 ==
9031 18:09:11.656284 RX Vref Scan: 0
9032 18:09:11.656737
9033 18:09:11.657072 RX Vref 0 -> 0, step: 1
9034 18:09:11.657383
9035 18:09:11.659248 RX Delay 19 -> 252, step: 4
9036 18:09:11.663022 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
9037 18:09:11.669053 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
9038 18:09:11.672925 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9039 18:09:11.676270 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9040 18:09:11.679154 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9041 18:09:11.682926 iDelay=195, Bit 5, Center 146 (103 ~ 190) 88
9042 18:09:11.686456 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
9043 18:09:11.693190 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9044 18:09:11.696050 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9045 18:09:11.699233 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9046 18:09:11.702820 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9047 18:09:11.705705 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9048 18:09:11.712423 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9049 18:09:11.716373 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9050 18:09:11.719541 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9051 18:09:11.722581 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9052 18:09:11.722995 ==
9053 18:09:11.726311 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 18:09:11.733028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 18:09:11.733600 ==
9056 18:09:11.733951 DQS Delay:
9057 18:09:11.735982 DQS0 = 0, DQS1 = 0
9058 18:09:11.736404 DQM Delay:
9059 18:09:11.739126 DQM0 = 135, DQM1 = 129
9060 18:09:11.739587 DQ Delay:
9061 18:09:11.742762 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
9062 18:09:11.745621 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
9063 18:09:11.749293 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9064 18:09:11.751981 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
9065 18:09:11.752063
9066 18:09:11.752129
9067 18:09:11.752196
9068 18:09:11.755599 [DramC_TX_OE_Calibration] TA2
9069 18:09:11.758570 Original DQ_B0 (3 6) =30, OEN = 27
9070 18:09:11.762158 Original DQ_B1 (3 6) =30, OEN = 27
9071 18:09:11.765416 24, 0x0, End_B0=24 End_B1=24
9072 18:09:11.765492 25, 0x0, End_B0=25 End_B1=25
9073 18:09:11.769133 26, 0x0, End_B0=26 End_B1=26
9074 18:09:11.772361 27, 0x0, End_B0=27 End_B1=27
9075 18:09:11.775544 28, 0x0, End_B0=28 End_B1=28
9076 18:09:11.778827 29, 0x0, End_B0=29 End_B1=29
9077 18:09:11.778924 30, 0x0, End_B0=30 End_B1=30
9078 18:09:11.782091 31, 0x4141, End_B0=30 End_B1=30
9079 18:09:11.785969 Byte0 end_step=30 best_step=27
9080 18:09:11.788597 Byte1 end_step=30 best_step=27
9081 18:09:11.792604 Byte0 TX OE(2T, 0.5T) = (3, 3)
9082 18:09:11.795459 Byte1 TX OE(2T, 0.5T) = (3, 3)
9083 18:09:11.795679
9084 18:09:11.795820
9085 18:09:11.801964 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9086 18:09:11.805674 CH1 RK1: MR19=303, MR18=1B06
9087 18:09:11.811831 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9088 18:09:11.815593 [RxdqsGatingPostProcess] freq 1600
9089 18:09:11.818703 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9090 18:09:11.821853 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 18:09:11.824966 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 18:09:11.828519 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 18:09:11.831789 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 18:09:11.834844 best DQS0 dly(2T, 0.5T) = (1, 1)
9095 18:09:11.838560 best DQS1 dly(2T, 0.5T) = (1, 1)
9096 18:09:11.841535 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9097 18:09:11.845117 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9098 18:09:11.848195 Pre-setting of DQS Precalculation
9099 18:09:11.851627 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9100 18:09:11.858599 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9101 18:09:11.868345 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9102 18:09:11.868513
9103 18:09:11.868656
9104 18:09:11.871521 [Calibration Summary] 3200 Mbps
9105 18:09:11.871675 CH 0, Rank 0
9106 18:09:11.875166 SW Impedance : PASS
9107 18:09:11.875342 DUTY Scan : NO K
9108 18:09:11.878409 ZQ Calibration : PASS
9109 18:09:11.881551 Jitter Meter : NO K
9110 18:09:11.881761 CBT Training : PASS
9111 18:09:11.884934 Write leveling : PASS
9112 18:09:11.885178 RX DQS gating : PASS
9113 18:09:11.888514 RX DQ/DQS(RDDQC) : PASS
9114 18:09:11.891706 TX DQ/DQS : PASS
9115 18:09:11.892024 RX DATLAT : PASS
9116 18:09:11.895010 RX DQ/DQS(Engine): PASS
9117 18:09:11.898174 TX OE : PASS
9118 18:09:11.898590 All Pass.
9119 18:09:11.898920
9120 18:09:11.899221 CH 0, Rank 1
9121 18:09:11.902145 SW Impedance : PASS
9122 18:09:11.905376 DUTY Scan : NO K
9123 18:09:11.905795 ZQ Calibration : PASS
9124 18:09:11.908434 Jitter Meter : NO K
9125 18:09:11.911588 CBT Training : PASS
9126 18:09:11.911958 Write leveling : PASS
9127 18:09:11.914660 RX DQS gating : PASS
9128 18:09:11.918148 RX DQ/DQS(RDDQC) : PASS
9129 18:09:11.918560 TX DQ/DQS : PASS
9130 18:09:11.921590 RX DATLAT : PASS
9131 18:09:11.924683 RX DQ/DQS(Engine): PASS
9132 18:09:11.925111 TX OE : PASS
9133 18:09:11.927984 All Pass.
9134 18:09:11.928402
9135 18:09:11.928794 CH 1, Rank 0
9136 18:09:11.931791 SW Impedance : PASS
9137 18:09:11.932214 DUTY Scan : NO K
9138 18:09:11.934648 ZQ Calibration : PASS
9139 18:09:11.938175 Jitter Meter : NO K
9140 18:09:11.938600 CBT Training : PASS
9141 18:09:11.941681 Write leveling : PASS
9142 18:09:11.942167 RX DQS gating : PASS
9143 18:09:11.944756 RX DQ/DQS(RDDQC) : PASS
9144 18:09:11.948022 TX DQ/DQS : PASS
9145 18:09:11.948678 RX DATLAT : PASS
9146 18:09:11.951451 RX DQ/DQS(Engine): PASS
9147 18:09:11.954601 TX OE : PASS
9148 18:09:11.955123 All Pass.
9149 18:09:11.955633
9150 18:09:11.956067 CH 1, Rank 1
9151 18:09:11.958217 SW Impedance : PASS
9152 18:09:11.961396 DUTY Scan : NO K
9153 18:09:11.961813 ZQ Calibration : PASS
9154 18:09:11.964447 Jitter Meter : NO K
9155 18:09:11.967957 CBT Training : PASS
9156 18:09:11.968374 Write leveling : PASS
9157 18:09:11.971629 RX DQS gating : PASS
9158 18:09:11.974586 RX DQ/DQS(RDDQC) : PASS
9159 18:09:11.975003 TX DQ/DQS : PASS
9160 18:09:11.978029 RX DATLAT : PASS
9161 18:09:11.981180 RX DQ/DQS(Engine): PASS
9162 18:09:11.981597 TX OE : PASS
9163 18:09:11.984382 All Pass.
9164 18:09:11.984871
9165 18:09:11.985252 DramC Write-DBI on
9166 18:09:11.987838 PER_BANK_REFRESH: Hybrid Mode
9167 18:09:11.988256 TX_TRACKING: ON
9168 18:09:11.997579 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9169 18:09:12.004237 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9170 18:09:12.014144 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9171 18:09:12.017531 [FAST_K] Save calibration result to emmc
9172 18:09:12.021470 sync common calibartion params.
9173 18:09:12.021924 sync cbt_mode0:1, 1:1
9174 18:09:12.024585 dram_init: ddr_geometry: 2
9175 18:09:12.027781 dram_init: ddr_geometry: 2
9176 18:09:12.028196 dram_init: ddr_geometry: 2
9177 18:09:12.031417 0:dram_rank_size:100000000
9178 18:09:12.034317 1:dram_rank_size:100000000
9179 18:09:12.040989 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9180 18:09:12.041419 DFS_SHUFFLE_HW_MODE: ON
9181 18:09:12.044136 dramc_set_vcore_voltage set vcore to 725000
9182 18:09:12.047468 Read voltage for 1600, 0
9183 18:09:12.047882 Vio18 = 0
9184 18:09:12.051006 Vcore = 725000
9185 18:09:12.051421 Vdram = 0
9186 18:09:12.051748 Vddq = 0
9187 18:09:12.054227 Vmddr = 0
9188 18:09:12.054726 switch to 3200 Mbps bootup
9189 18:09:12.057576 [DramcRunTimeConfig]
9190 18:09:12.057990 PHYPLL
9191 18:09:12.060669 DPM_CONTROL_AFTERK: ON
9192 18:09:12.061084 PER_BANK_REFRESH: ON
9193 18:09:12.064401 REFRESH_OVERHEAD_REDUCTION: ON
9194 18:09:12.067333 CMD_PICG_NEW_MODE: OFF
9195 18:09:12.067815 XRTWTW_NEW_MODE: ON
9196 18:09:12.070583 XRTRTR_NEW_MODE: ON
9197 18:09:12.071006 TX_TRACKING: ON
9198 18:09:12.074220 RDSEL_TRACKING: OFF
9199 18:09:12.077255 DQS Precalculation for DVFS: ON
9200 18:09:12.077709 RX_TRACKING: OFF
9201 18:09:12.081009 HW_GATING DBG: ON
9202 18:09:12.081597 ZQCS_ENABLE_LP4: ON
9203 18:09:12.083774 RX_PICG_NEW_MODE: ON
9204 18:09:12.084375 TX_PICG_NEW_MODE: ON
9205 18:09:12.087558 ENABLE_RX_DCM_DPHY: ON
9206 18:09:12.090723 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9207 18:09:12.093903 DUMMY_READ_FOR_TRACKING: OFF
9208 18:09:12.094364 !!! SPM_CONTROL_AFTERK: OFF
9209 18:09:12.097455 !!! SPM could not control APHY
9210 18:09:12.100513 IMPEDANCE_TRACKING: ON
9211 18:09:12.100981 TEMP_SENSOR: ON
9212 18:09:12.104218 HW_SAVE_FOR_SR: OFF
9213 18:09:12.107296 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9214 18:09:12.110620 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9215 18:09:12.111190 Read ODT Tracking: ON
9216 18:09:12.113686 Refresh Rate DeBounce: ON
9217 18:09:12.117265 DFS_NO_QUEUE_FLUSH: ON
9218 18:09:12.120519 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9219 18:09:12.120947 ENABLE_DFS_RUNTIME_MRW: OFF
9220 18:09:12.123647 DDR_RESERVE_NEW_MODE: ON
9221 18:09:12.126934 MR_CBT_SWITCH_FREQ: ON
9222 18:09:12.127399 =========================
9223 18:09:12.147314 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9224 18:09:12.151012 dram_init: ddr_geometry: 2
9225 18:09:12.168982 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9226 18:09:12.172462 dram_init: dram init end (result: 0)
9227 18:09:12.179212 DRAM-K: Full calibration passed in 24534 msecs
9228 18:09:12.182313 MRC: failed to locate region type 0.
9229 18:09:12.182741 DRAM rank0 size:0x100000000,
9230 18:09:12.186295 DRAM rank1 size=0x100000000
9231 18:09:12.195795 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9232 18:09:12.202815 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9233 18:09:12.209062 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9234 18:09:12.215459 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9235 18:09:12.218789 DRAM rank0 size:0x100000000,
9236 18:09:12.222389 DRAM rank1 size=0x100000000
9237 18:09:12.222816 CBMEM:
9238 18:09:12.225607 IMD: root @ 0xfffff000 254 entries.
9239 18:09:12.228873 IMD: root @ 0xffffec00 62 entries.
9240 18:09:12.232330 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9241 18:09:12.235439 WARNING: RO_VPD is uninitialized or empty.
9242 18:09:12.242458 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9243 18:09:12.249058 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9244 18:09:12.261662 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9245 18:09:12.273183 BS: romstage times (exec / console): total (unknown) / 24027 ms
9246 18:09:12.273606
9247 18:09:12.273947
9248 18:09:12.283353 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9249 18:09:12.286426 ARM64: Exception handlers installed.
9250 18:09:12.290054 ARM64: Testing exception
9251 18:09:12.293072 ARM64: Done test exception
9252 18:09:12.293486 Enumerating buses...
9253 18:09:12.296254 Show all devs... Before device enumeration.
9254 18:09:12.299952 Root Device: enabled 1
9255 18:09:12.303152 CPU_CLUSTER: 0: enabled 1
9256 18:09:12.303570 CPU: 00: enabled 1
9257 18:09:12.306249 Compare with tree...
9258 18:09:12.306663 Root Device: enabled 1
9259 18:09:12.309498 CPU_CLUSTER: 0: enabled 1
9260 18:09:12.312838 CPU: 00: enabled 1
9261 18:09:12.313253 Root Device scanning...
9262 18:09:12.316329 scan_static_bus for Root Device
9263 18:09:12.319565 CPU_CLUSTER: 0 enabled
9264 18:09:12.322725 scan_static_bus for Root Device done
9265 18:09:12.326244 scan_bus: bus Root Device finished in 8 msecs
9266 18:09:12.326808 done
9267 18:09:12.333163 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9268 18:09:12.336525 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9269 18:09:12.343181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9270 18:09:12.346350 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9271 18:09:12.349885 Allocating resources...
9272 18:09:12.353025 Reading resources...
9273 18:09:12.356362 Root Device read_resources bus 0 link: 0
9274 18:09:12.356930 DRAM rank0 size:0x100000000,
9275 18:09:12.359571 DRAM rank1 size=0x100000000
9276 18:09:12.362798 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9277 18:09:12.366008 CPU: 00 missing read_resources
9278 18:09:12.372434 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9279 18:09:12.376180 Root Device read_resources bus 0 link: 0 done
9280 18:09:12.376733 Done reading resources.
9281 18:09:12.382655 Show resources in subtree (Root Device)...After reading.
9282 18:09:12.385920 Root Device child on link 0 CPU_CLUSTER: 0
9283 18:09:12.389068 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 18:09:12.398915 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 18:09:12.399388 CPU: 00
9286 18:09:12.402176 Root Device assign_resources, bus 0 link: 0
9287 18:09:12.405994 CPU_CLUSTER: 0 missing set_resources
9288 18:09:12.412267 Root Device assign_resources, bus 0 link: 0 done
9289 18:09:12.412792 Done setting resources.
9290 18:09:12.418987 Show resources in subtree (Root Device)...After assigning values.
9291 18:09:12.422220 Root Device child on link 0 CPU_CLUSTER: 0
9292 18:09:12.425990 CPU_CLUSTER: 0 child on link 0 CPU: 00
9293 18:09:12.435508 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9294 18:09:12.435932 CPU: 00
9295 18:09:12.439206 Done allocating resources.
9296 18:09:12.442414 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9297 18:09:12.445632 Enabling resources...
9298 18:09:12.446048 done.
9299 18:09:12.452225 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9300 18:09:12.452703 Initializing devices...
9301 18:09:12.456133 Root Device init
9302 18:09:12.456822 init hardware done!
9303 18:09:12.459106 0x00000018: ctrlr->caps
9304 18:09:12.462315 52.000 MHz: ctrlr->f_max
9305 18:09:12.462845 0.400 MHz: ctrlr->f_min
9306 18:09:12.466220 0x40ff8080: ctrlr->voltages
9307 18:09:12.466747 sclk: 390625
9308 18:09:12.469036 Bus Width = 1
9309 18:09:12.469454 sclk: 390625
9310 18:09:12.472253 Bus Width = 1
9311 18:09:12.472711 Early init status = 3
9312 18:09:12.478742 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9313 18:09:12.482252 in-header: 03 fc 00 00 01 00 00 00
9314 18:09:12.485212 in-data: 00
9315 18:09:12.488636 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9316 18:09:12.494350 in-header: 03 fd 00 00 00 00 00 00
9317 18:09:12.497774 in-data:
9318 18:09:12.500965 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9319 18:09:12.505353 in-header: 03 fc 00 00 01 00 00 00
9320 18:09:12.508453 in-data: 00
9321 18:09:12.511820 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9322 18:09:12.518044 in-header: 03 fd 00 00 00 00 00 00
9323 18:09:12.521163 in-data:
9324 18:09:12.524351 [SSUSB] Setting up USB HOST controller...
9325 18:09:12.527653 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9326 18:09:12.531217 [SSUSB] phy power-on done.
9327 18:09:12.534361 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9328 18:09:12.540989 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9329 18:09:12.544263 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9330 18:09:12.550558 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9331 18:09:12.557318 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9332 18:09:12.563988 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9333 18:09:12.571151 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9334 18:09:12.577349 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9335 18:09:12.580717 SPM: binary array size = 0x9dc
9336 18:09:12.584104 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9337 18:09:12.590784 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9338 18:09:12.597123 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9339 18:09:12.600820 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9340 18:09:12.607349 configure_display: Starting display init
9341 18:09:12.640566 anx7625_power_on_init: Init interface.
9342 18:09:12.643859 anx7625_disable_pd_protocol: Disabled PD feature.
9343 18:09:12.647093 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9344 18:09:12.675044 anx7625_start_dp_work: Secure OCM version=00
9345 18:09:12.678335 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9346 18:09:12.693339 sp_tx_get_edid_block: EDID Block = 1
9347 18:09:12.796086 Extracted contents:
9348 18:09:12.799489 header: 00 ff ff ff ff ff ff 00
9349 18:09:12.802468 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9350 18:09:12.805949 version: 01 04
9351 18:09:12.809185 basic params: 95 1f 11 78 0a
9352 18:09:12.812798 chroma info: 76 90 94 55 54 90 27 21 50 54
9353 18:09:12.815631 established: 00 00 00
9354 18:09:12.822227 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9355 18:09:12.825884 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9356 18:09:12.832544 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 18:09:12.839199 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9358 18:09:12.845991 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9359 18:09:12.848989 extensions: 00
9360 18:09:12.849409 checksum: fb
9361 18:09:12.849738
9362 18:09:12.852409 Manufacturer: IVO Model 57d Serial Number 0
9363 18:09:12.855515 Made week 0 of 2020
9364 18:09:12.855924 EDID version: 1.4
9365 18:09:12.858671 Digital display
9366 18:09:12.861809 6 bits per primary color channel
9367 18:09:12.862228 DisplayPort interface
9368 18:09:12.865419 Maximum image size: 31 cm x 17 cm
9369 18:09:12.868647 Gamma: 220%
9370 18:09:12.869061 Check DPMS levels
9371 18:09:12.871885 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9372 18:09:12.875378 First detailed timing is preferred timing
9373 18:09:12.878510 Established timings supported:
9374 18:09:12.882336 Standard timings supported:
9375 18:09:12.885480 Detailed timings
9376 18:09:12.888597 Hex of detail: 383680a07038204018303c0035ae10000019
9377 18:09:12.891908 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9378 18:09:12.898944 0780 0798 07c8 0820 hborder 0
9379 18:09:12.901920 0438 043b 0447 0458 vborder 0
9380 18:09:12.905443 -hsync -vsync
9381 18:09:12.905732 Did detailed timing
9382 18:09:12.911791 Hex of detail: 000000000000000000000000000000000000
9383 18:09:12.912247 Manufacturer-specified data, tag 0
9384 18:09:12.918576 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9385 18:09:12.921751 ASCII string: InfoVision
9386 18:09:12.925267 Hex of detail: 000000fe00523134304e574635205248200a
9387 18:09:12.928597 ASCII string: R140NWF5 RH
9388 18:09:12.929027 Checksum
9389 18:09:12.931795 Checksum: 0xfb (valid)
9390 18:09:12.934871 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9391 18:09:12.938258 DSI data_rate: 832800000 bps
9392 18:09:12.945244 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9393 18:09:12.948402 anx7625_parse_edid: pixelclock(138800).
9394 18:09:12.951603 hactive(1920), hsync(48), hfp(24), hbp(88)
9395 18:09:12.954958 vactive(1080), vsync(12), vfp(3), vbp(17)
9396 18:09:12.958237 anx7625_dsi_config: config dsi.
9397 18:09:12.964613 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9398 18:09:12.978240 anx7625_dsi_config: success to config DSI
9399 18:09:12.981245 anx7625_dp_start: MIPI phy setup OK.
9400 18:09:12.984781 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9401 18:09:12.988091 mtk_ddp_mode_set invalid vrefresh 60
9402 18:09:12.991140 main_disp_path_setup
9403 18:09:12.991566 ovl_layer_smi_id_en
9404 18:09:12.994768 ovl_layer_smi_id_en
9405 18:09:12.995172 ccorr_config
9406 18:09:12.995489 aal_config
9407 18:09:12.997942 gamma_config
9408 18:09:12.998496 postmask_config
9409 18:09:13.001208 dither_config
9410 18:09:13.004673 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9411 18:09:13.011157 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9412 18:09:13.014413 Root Device init finished in 555 msecs
9413 18:09:13.014817 CPU_CLUSTER: 0 init
9414 18:09:13.024285 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9415 18:09:13.027971 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9416 18:09:13.031166 APU_MBOX 0x190000b0 = 0x10001
9417 18:09:13.034230 APU_MBOX 0x190001b0 = 0x10001
9418 18:09:13.037940 APU_MBOX 0x190005b0 = 0x10001
9419 18:09:13.041042 APU_MBOX 0x190006b0 = 0x10001
9420 18:09:13.044057 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9421 18:09:13.056961 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9422 18:09:13.069753 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9423 18:09:13.076185 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9424 18:09:13.087583 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9425 18:09:13.096706 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9426 18:09:13.100019 CPU_CLUSTER: 0 init finished in 81 msecs
9427 18:09:13.103760 Devices initialized
9428 18:09:13.106860 Show all devs... After init.
9429 18:09:13.107263 Root Device: enabled 1
9430 18:09:13.109912 CPU_CLUSTER: 0: enabled 1
9431 18:09:13.113298 CPU: 00: enabled 1
9432 18:09:13.117067 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9433 18:09:13.119976 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9434 18:09:13.123302 ELOG: NV offset 0x57f000 size 0x1000
9435 18:09:13.130326 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9436 18:09:13.136709 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9437 18:09:13.140241 ELOG: Event(17) added with size 13 at 2024-06-11 18:07:47 UTC
9438 18:09:13.143408 out: cmd=0x121: 03 db 21 01 00 00 00 00
9439 18:09:13.147079 in-header: 03 28 00 00 2c 00 00 00
9440 18:09:13.160408 in-data: 16 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9441 18:09:13.166917 ELOG: Event(A1) added with size 10 at 2024-06-11 18:07:47 UTC
9442 18:09:13.173753 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9443 18:09:13.180067 ELOG: Event(A0) added with size 9 at 2024-06-11 18:07:47 UTC
9444 18:09:13.183267 elog_add_boot_reason: Logged dev mode boot
9445 18:09:13.186974 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9446 18:09:13.190084 Finalize devices...
9447 18:09:13.190500 Devices finalized
9448 18:09:13.196671 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 18:09:13.199937 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9450 18:09:13.203168 in-header: 03 07 00 00 08 00 00 00
9451 18:09:13.206708 in-data: aa e4 47 04 13 02 00 00
9452 18:09:13.210087 Chrome EC: UHEPI supported
9453 18:09:13.216791 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9454 18:09:13.219884 in-header: 03 a9 00 00 08 00 00 00
9455 18:09:13.222917 in-data: 84 60 60 08 00 00 00 00
9456 18:09:13.229703 ELOG: Event(91) added with size 10 at 2024-06-11 18:07:47 UTC
9457 18:09:13.233287 Chrome EC: clear events_b mask to 0x0000000020004000
9458 18:09:13.239899 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9459 18:09:13.243571 in-header: 03 fd 00 00 00 00 00 00
9460 18:09:13.247400 in-data:
9461 18:09:13.250533 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9462 18:09:13.254017 Writing coreboot table at 0xffe64000
9463 18:09:13.257138 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 18:09:13.263346 1. 0000000040000000-00000000400fffff: RAM
9465 18:09:13.267098 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 18:09:13.270435 3. 000000004032b000-00000000545fffff: RAM
9467 18:09:13.273638 4. 0000000054600000-000000005465ffff: BL31
9468 18:09:13.277266 5. 0000000054660000-00000000ffe63fff: RAM
9469 18:09:13.283991 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 18:09:13.287006 7. 0000000100000000-000000023fffffff: RAM
9471 18:09:13.290308 Passing 5 GPIOs to payload:
9472 18:09:13.293586 NAME | PORT | POLARITY | VALUE
9473 18:09:13.296845 EC in RW | 0x000000aa | low | undefined
9474 18:09:13.303977 EC interrupt | 0x00000005 | low | undefined
9475 18:09:13.306964 TPM interrupt | 0x000000ab | high | undefined
9476 18:09:13.313853 SD card detect | 0x00000011 | high | undefined
9477 18:09:13.316951 speaker enable | 0x00000093 | high | undefined
9478 18:09:13.320192 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 18:09:13.323662 in-header: 03 f9 00 00 02 00 00 00
9480 18:09:13.326814 in-data: 02 00
9481 18:09:13.330265 ADC[4]: Raw value=899926 ID=7
9482 18:09:13.330685 ADC[3]: Raw value=213179 ID=1
9483 18:09:13.333788 RAM Code: 0x71
9484 18:09:13.336849 ADC[6]: Raw value=74502 ID=0
9485 18:09:13.337307 ADC[5]: Raw value=211703 ID=1
9486 18:09:13.340406 SKU Code: 0x1
9487 18:09:13.343442 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 659e
9488 18:09:13.347091 coreboot table: 964 bytes.
9489 18:09:13.350275 IMD ROOT 0. 0xfffff000 0x00001000
9490 18:09:13.353455 IMD SMALL 1. 0xffffe000 0x00001000
9491 18:09:13.356665 RO MCACHE 2. 0xffffc000 0x00001104
9492 18:09:13.360286 CONSOLE 3. 0xfff7c000 0x00080000
9493 18:09:13.363686 FMAP 4. 0xfff7b000 0x00000452
9494 18:09:13.366907 TIME STAMP 5. 0xfff7a000 0x00000910
9495 18:09:13.369980 VBOOT WORK 6. 0xfff66000 0x00014000
9496 18:09:13.373321 RAMOOPS 7. 0xffe66000 0x00100000
9497 18:09:13.376452 COREBOOT 8. 0xffe64000 0x00002000
9498 18:09:13.380290 IMD small region:
9499 18:09:13.383124 IMD ROOT 0. 0xffffec00 0x00000400
9500 18:09:13.386901 VPD 1. 0xffffeb80 0x0000006c
9501 18:09:13.390058 MMC STATUS 2. 0xffffeb60 0x00000004
9502 18:09:13.393333 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9503 18:09:13.400207 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9504 18:09:13.440363 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9505 18:09:13.443557 Checking segment from ROM address 0x40100000
9506 18:09:13.447276 Checking segment from ROM address 0x4010001c
9507 18:09:13.454054 Loading segment from ROM address 0x40100000
9508 18:09:13.454470 code (compression=0)
9509 18:09:13.464102 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9510 18:09:13.470448 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9511 18:09:13.470863 it's not compressed!
9512 18:09:13.477235 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9513 18:09:13.480123 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9514 18:09:13.500978 Loading segment from ROM address 0x4010001c
9515 18:09:13.501395 Entry Point 0x80000000
9516 18:09:13.504053 Loaded segments
9517 18:09:13.507766 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9518 18:09:13.514007 Jumping to boot code at 0x80000000(0xffe64000)
9519 18:09:13.521193 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9520 18:09:13.527270 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9521 18:09:13.535369 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9522 18:09:13.538833 Checking segment from ROM address 0x40100000
9523 18:09:13.542243 Checking segment from ROM address 0x4010001c
9524 18:09:13.549246 Loading segment from ROM address 0x40100000
9525 18:09:13.549806 code (compression=1)
9526 18:09:13.556036 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9527 18:09:13.565129 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9528 18:09:13.565654 using LZMA
9529 18:09:13.573929 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9530 18:09:13.580346 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9531 18:09:13.583873 Loading segment from ROM address 0x4010001c
9532 18:09:13.584351 Entry Point 0x54601000
9533 18:09:13.587149 Loaded segments
9534 18:09:13.590360 NOTICE: MT8192 bl31_setup
9535 18:09:13.597530 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9536 18:09:13.600750 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9537 18:09:13.604689 WARNING: region 0:
9538 18:09:13.607594 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 18:09:13.608092 WARNING: region 1:
9540 18:09:13.614049 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9541 18:09:13.617534 WARNING: region 2:
9542 18:09:13.620836 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9543 18:09:13.624237 WARNING: region 3:
9544 18:09:13.627284 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 18:09:13.630942 WARNING: region 4:
9546 18:09:13.637159 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9547 18:09:13.637714 WARNING: region 5:
9548 18:09:13.640795 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 18:09:13.643770 WARNING: region 6:
9550 18:09:13.646979 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 18:09:13.650439 WARNING: region 7:
9552 18:09:13.654001 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 18:09:13.660178 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9554 18:09:13.663805 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9555 18:09:13.667122 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9556 18:09:13.674081 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9557 18:09:13.677012 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9558 18:09:13.680207 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9559 18:09:13.687471 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9560 18:09:13.690420 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9561 18:09:13.697114 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9562 18:09:13.700367 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9563 18:09:13.703612 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9564 18:09:13.710177 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9565 18:09:13.713791 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9566 18:09:13.716986 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9567 18:09:13.723390 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9568 18:09:13.726999 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9569 18:09:13.733509 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9570 18:09:13.736825 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9571 18:09:13.739944 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9572 18:09:13.746873 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9573 18:09:13.749950 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9574 18:09:13.756661 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9575 18:09:13.760783 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9576 18:09:13.763679 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9577 18:09:13.769973 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9578 18:09:13.773768 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9579 18:09:13.780601 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9580 18:09:13.783450 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9581 18:09:13.786627 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9582 18:09:13.793388 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9583 18:09:13.796737 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9584 18:09:13.803254 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9585 18:09:13.806879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9586 18:09:13.810193 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9587 18:09:13.813373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9588 18:09:13.820027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9589 18:09:13.822942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9590 18:09:13.826625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9591 18:09:13.829746 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9592 18:09:13.836924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9593 18:09:13.839916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9594 18:09:13.843453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9595 18:09:13.846516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9596 18:09:13.853161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9597 18:09:13.856259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9598 18:09:13.859969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9599 18:09:13.863149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9600 18:09:13.869802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9601 18:09:13.872881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9602 18:09:13.876657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9603 18:09:13.883041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9604 18:09:13.886405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9605 18:09:13.892703 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9606 18:09:13.896027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9607 18:09:13.902816 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9608 18:09:13.905931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9609 18:09:13.912856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9610 18:09:13.916076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9611 18:09:13.919066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9612 18:09:13.926179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9613 18:09:13.929345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9614 18:09:13.936097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9615 18:09:13.939269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9616 18:09:13.945784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9617 18:09:13.949023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9618 18:09:13.955540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9619 18:09:13.958928 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9620 18:09:13.962247 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9621 18:09:13.969121 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9622 18:09:13.972287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9623 18:09:13.978529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9624 18:09:13.981868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9625 18:09:13.988450 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9626 18:09:13.992250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9627 18:09:13.995346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9628 18:09:14.001803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9629 18:09:14.005452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9630 18:09:14.011701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9631 18:09:14.015048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9632 18:09:14.021819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9633 18:09:14.024989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9634 18:09:14.031842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9635 18:09:14.035047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9636 18:09:14.041710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9637 18:09:14.044976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9638 18:09:14.048174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9639 18:09:14.055084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9640 18:09:14.058051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9641 18:09:14.064638 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9642 18:09:14.068178 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9643 18:09:14.074912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9644 18:09:14.078264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9645 18:09:14.081361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9646 18:09:14.088226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9647 18:09:14.091533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9648 18:09:14.098122 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9649 18:09:14.101401 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9650 18:09:14.104763 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9651 18:09:14.111482 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9652 18:09:14.114832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9653 18:09:14.117943 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9654 18:09:14.124543 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9655 18:09:14.127852 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9656 18:09:14.131127 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9657 18:09:14.137852 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9658 18:09:14.141113 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9659 18:09:14.144743 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9660 18:09:14.150948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9661 18:09:14.154659 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9662 18:09:14.161277 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9663 18:09:14.164104 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9664 18:09:14.167643 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9665 18:09:14.174326 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9666 18:09:14.177963 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9667 18:09:14.184168 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9668 18:09:14.188000 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9669 18:09:14.190968 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9670 18:09:14.197688 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9671 18:09:14.200687 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9672 18:09:14.204420 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9673 18:09:14.207442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9674 18:09:14.214319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9675 18:09:14.217569 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9676 18:09:14.220894 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9677 18:09:14.227979 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9678 18:09:14.231060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9679 18:09:14.234172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9680 18:09:14.241122 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9681 18:09:14.244304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9682 18:09:14.250743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9683 18:09:14.254569 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9684 18:09:14.257458 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9685 18:09:14.263927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9686 18:09:14.267466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9687 18:09:14.273858 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9688 18:09:14.277470 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9689 18:09:14.280694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9690 18:09:14.287395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9691 18:09:14.290954 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9692 18:09:14.294085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9693 18:09:14.300399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9694 18:09:14.304155 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9695 18:09:14.310867 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9696 18:09:14.314170 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9697 18:09:14.317289 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9698 18:09:14.323647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9699 18:09:14.326987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9700 18:09:14.334120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9701 18:09:14.337256 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9702 18:09:14.340484 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9703 18:09:14.347529 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9704 18:09:14.350452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9705 18:09:14.357411 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9706 18:09:14.360632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9707 18:09:14.364108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9708 18:09:14.370167 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9709 18:09:14.373545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9710 18:09:14.379962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9711 18:09:14.383591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9712 18:09:14.386701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9713 18:09:14.393429 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9714 18:09:14.396970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9715 18:09:14.400222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9716 18:09:14.406617 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9717 18:09:14.410021 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9718 18:09:14.416970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9719 18:09:14.420003 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9720 18:09:14.423214 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9721 18:09:14.429978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9722 18:09:14.433276 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9723 18:09:14.439960 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9724 18:09:14.443210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9725 18:09:14.446416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9726 18:09:14.453360 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9727 18:09:14.456426 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9728 18:09:14.463112 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9729 18:09:14.466323 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9730 18:09:14.469739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9731 18:09:14.476431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9732 18:09:14.479503 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9733 18:09:14.483047 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9734 18:09:14.490048 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9735 18:09:14.493220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9736 18:09:14.499761 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9737 18:09:14.503241 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9738 18:09:14.506392 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9739 18:09:14.513223 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9740 18:09:14.516081 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9741 18:09:14.523110 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9742 18:09:14.526201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9743 18:09:14.533186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9744 18:09:14.536333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9745 18:09:14.539481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9746 18:09:14.546263 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9747 18:09:14.550093 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9748 18:09:14.553269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9749 18:09:14.559557 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9750 18:09:14.563246 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9751 18:09:14.569929 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9752 18:09:14.573107 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9753 18:09:14.579961 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9754 18:09:14.583001 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9755 18:09:14.586648 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9756 18:09:14.593134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9757 18:09:14.596284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9758 18:09:14.602949 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9759 18:09:14.606571 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9760 18:09:14.609555 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9761 18:09:14.616538 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9762 18:09:14.619513 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9763 18:09:14.626545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9764 18:09:14.629560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9765 18:09:14.636351 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9766 18:09:14.639363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9767 18:09:14.643127 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9768 18:09:14.649656 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9769 18:09:14.652968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9770 18:09:14.659437 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9771 18:09:14.663111 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9772 18:09:14.666291 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9773 18:09:14.672622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9774 18:09:14.676383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9775 18:09:14.682715 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9776 18:09:14.685982 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9777 18:09:14.692670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9778 18:09:14.696394 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9779 18:09:14.699391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9780 18:09:14.706232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9781 18:09:14.709356 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9782 18:09:14.712641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9783 18:09:14.719482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9784 18:09:14.722663 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9785 18:09:14.725796 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9786 18:09:14.729202 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9787 18:09:14.736079 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9788 18:09:14.739086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9789 18:09:14.742153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9790 18:09:14.749069 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9791 18:09:14.752877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9792 18:09:14.756076 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9793 18:09:14.762461 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9794 18:09:14.766160 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9795 18:09:14.772606 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9796 18:09:14.775650 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9797 18:09:14.778930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9798 18:09:14.786279 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9799 18:09:14.788802 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9800 18:09:14.795330 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9801 18:09:14.799187 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9802 18:09:14.802423 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9803 18:09:14.809179 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9804 18:09:14.812146 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9805 18:09:14.815702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9806 18:09:14.821894 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9807 18:09:14.825359 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9808 18:09:14.828908 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9809 18:09:14.835711 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9810 18:09:14.839086 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9811 18:09:14.842229 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9812 18:09:14.848734 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9813 18:09:14.852472 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9814 18:09:14.859131 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9815 18:09:14.862336 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9816 18:09:14.865518 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9817 18:09:14.872310 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9818 18:09:14.875432 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9819 18:09:14.879352 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9820 18:09:14.885620 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9821 18:09:14.889024 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9822 18:09:14.892458 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9823 18:09:14.895453 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9824 18:09:14.901986 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9825 18:09:14.905524 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9826 18:09:14.908676 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9827 18:09:14.912661 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9828 18:09:14.919390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9829 18:09:14.922018 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9830 18:09:14.925402 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9831 18:09:14.928648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9832 18:09:14.935863 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9833 18:09:14.939083 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9834 18:09:14.942576 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9835 18:09:14.948779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9836 18:09:14.952153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9837 18:09:14.955389 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9838 18:09:14.962497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9839 18:09:14.965281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9840 18:09:14.972130 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9841 18:09:14.975097 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9842 18:09:14.978351 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9843 18:09:14.985446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9844 18:09:14.988725 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9845 18:09:14.995358 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9846 18:09:14.998288 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9847 18:09:15.004661 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9848 18:09:15.008183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9849 18:09:15.011646 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9850 18:09:15.018219 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9851 18:09:15.021370 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9852 18:09:15.027989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9853 18:09:15.031639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9854 18:09:15.034797 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9855 18:09:15.041805 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9856 18:09:15.044885 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9857 18:09:15.051626 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9858 18:09:15.054787 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9859 18:09:15.058426 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9860 18:09:15.065132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9861 18:09:15.068813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9862 18:09:15.075214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9863 18:09:15.079015 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9864 18:09:15.082224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9865 18:09:15.088483 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9866 18:09:15.091485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9867 18:09:15.098594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9868 18:09:15.101937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9869 18:09:15.105032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9870 18:09:15.111495 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9871 18:09:15.115415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9872 18:09:15.121384 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9873 18:09:15.124745 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9874 18:09:15.128594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9875 18:09:15.135166 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9876 18:09:15.138450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9877 18:09:15.144887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9878 18:09:15.147624 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9879 18:09:15.154331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9880 18:09:15.157469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9881 18:09:15.161182 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9882 18:09:15.167860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9883 18:09:15.170922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9884 18:09:15.178067 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9885 18:09:15.181245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9886 18:09:15.184527 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9887 18:09:15.191462 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9888 18:09:15.195268 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9889 18:09:15.201380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9890 18:09:15.204815 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9891 18:09:15.208001 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9892 18:09:15.214537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9893 18:09:15.218216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9894 18:09:15.224141 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9895 18:09:15.227990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9896 18:09:15.234860 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9897 18:09:15.237710 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9898 18:09:15.241189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9899 18:09:15.248241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9900 18:09:15.251404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9901 18:09:15.254551 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9902 18:09:15.261487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9903 18:09:15.264840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9904 18:09:15.271253 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9905 18:09:15.274465 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9906 18:09:15.277655 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9907 18:09:15.284714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9908 18:09:15.287811 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9909 18:09:15.294551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9910 18:09:15.297601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9911 18:09:15.304598 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9912 18:09:15.307653 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9913 18:09:15.314692 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9914 18:09:15.317818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9915 18:09:15.321103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9916 18:09:15.327357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9917 18:09:15.330650 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9918 18:09:15.337387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9919 18:09:15.340434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9920 18:09:15.347589 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9921 18:09:15.350688 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9922 18:09:15.354025 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9923 18:09:15.360662 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9924 18:09:15.364256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9925 18:09:15.370187 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9926 18:09:15.373560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9927 18:09:15.380637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9928 18:09:15.383545 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9929 18:09:15.390578 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9930 18:09:15.393829 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9931 18:09:15.396954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9932 18:09:15.404072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9933 18:09:15.407241 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9934 18:09:15.414174 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9935 18:09:15.417285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9936 18:09:15.423460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9937 18:09:15.427046 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9938 18:09:15.430176 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9939 18:09:15.436655 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9940 18:09:15.440072 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9941 18:09:15.447166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9942 18:09:15.450038 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9943 18:09:15.457284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9944 18:09:15.460412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9945 18:09:15.466773 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9946 18:09:15.470216 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9947 18:09:15.473471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9948 18:09:15.480005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9949 18:09:15.483198 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9950 18:09:15.489661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9951 18:09:15.493459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9952 18:09:15.500081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9953 18:09:15.503173 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9954 18:09:15.506654 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9955 18:09:15.513261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9956 18:09:15.516743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9957 18:09:15.523187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9958 18:09:15.526059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9959 18:09:15.532928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9960 18:09:15.536429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9961 18:09:15.542691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9962 18:09:15.546144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9963 18:09:15.553075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9964 18:09:15.556359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9965 18:09:15.559861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9966 18:09:15.565911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9967 18:09:15.569662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9968 18:09:15.576144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9969 18:09:15.579713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9970 18:09:15.586191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9971 18:09:15.589504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9972 18:09:15.596194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9973 18:09:15.599577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9974 18:09:15.606221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9975 18:09:15.609429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9976 18:09:15.616192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9977 18:09:15.619049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9978 18:09:15.626076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9979 18:09:15.629404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9980 18:09:15.636151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9981 18:09:15.639228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9982 18:09:15.646489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9983 18:09:15.648929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9984 18:09:15.656049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9985 18:09:15.659035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9986 18:09:15.665815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9987 18:09:15.669064 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9988 18:09:15.672661 INFO: [APUAPC] vio 0
9989 18:09:15.675750 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9990 18:09:15.683008 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9991 18:09:15.686233 INFO: [APUAPC] D0_APC_0: 0x400510
9992 18:09:15.686759 INFO: [APUAPC] D0_APC_1: 0x0
9993 18:09:15.689175 INFO: [APUAPC] D0_APC_2: 0x1540
9994 18:09:15.692224 INFO: [APUAPC] D0_APC_3: 0x0
9995 18:09:15.696052 INFO: [APUAPC] D1_APC_0: 0xffffffff
9996 18:09:15.699223 INFO: [APUAPC] D1_APC_1: 0xffffffff
9997 18:09:15.702224 INFO: [APUAPC] D1_APC_2: 0x3fffff
9998 18:09:15.706013 INFO: [APUAPC] D1_APC_3: 0x0
9999 18:09:15.709102 INFO: [APUAPC] D2_APC_0: 0xffffffff
10000 18:09:15.712299 INFO: [APUAPC] D2_APC_1: 0xffffffff
10001 18:09:15.716005 INFO: [APUAPC] D2_APC_2: 0x3fffff
10002 18:09:15.719349 INFO: [APUAPC] D2_APC_3: 0x0
10003 18:09:15.722327 INFO: [APUAPC] D3_APC_0: 0xffffffff
10004 18:09:15.725891 INFO: [APUAPC] D3_APC_1: 0xffffffff
10005 18:09:15.729011 INFO: [APUAPC] D3_APC_2: 0x3fffff
10006 18:09:15.732231 INFO: [APUAPC] D3_APC_3: 0x0
10007 18:09:15.735396 INFO: [APUAPC] D4_APC_0: 0xffffffff
10008 18:09:15.739068 INFO: [APUAPC] D4_APC_1: 0xffffffff
10009 18:09:15.742481 INFO: [APUAPC] D4_APC_2: 0x3fffff
10010 18:09:15.745557 INFO: [APUAPC] D4_APC_3: 0x0
10011 18:09:15.749084 INFO: [APUAPC] D5_APC_0: 0xffffffff
10012 18:09:15.752187 INFO: [APUAPC] D5_APC_1: 0xffffffff
10013 18:09:15.755514 INFO: [APUAPC] D5_APC_2: 0x3fffff
10014 18:09:15.759009 INFO: [APUAPC] D5_APC_3: 0x0
10015 18:09:15.762468 INFO: [APUAPC] D6_APC_0: 0xffffffff
10016 18:09:15.765742 INFO: [APUAPC] D6_APC_1: 0xffffffff
10017 18:09:15.768936 INFO: [APUAPC] D6_APC_2: 0x3fffff
10018 18:09:15.772084 INFO: [APUAPC] D6_APC_3: 0x0
10019 18:09:15.775214 INFO: [APUAPC] D7_APC_0: 0xffffffff
10020 18:09:15.779380 INFO: [APUAPC] D7_APC_1: 0xffffffff
10021 18:09:15.782179 INFO: [APUAPC] D7_APC_2: 0x3fffff
10022 18:09:15.785085 INFO: [APUAPC] D7_APC_3: 0x0
10023 18:09:15.788661 INFO: [APUAPC] D8_APC_0: 0xffffffff
10024 18:09:15.792104 INFO: [APUAPC] D8_APC_1: 0xffffffff
10025 18:09:15.795256 INFO: [APUAPC] D8_APC_2: 0x3fffff
10026 18:09:15.798439 INFO: [APUAPC] D8_APC_3: 0x0
10027 18:09:15.802238 INFO: [APUAPC] D9_APC_0: 0xffffffff
10028 18:09:15.805420 INFO: [APUAPC] D9_APC_1: 0xffffffff
10029 18:09:15.808740 INFO: [APUAPC] D9_APC_2: 0x3fffff
10030 18:09:15.811907 INFO: [APUAPC] D9_APC_3: 0x0
10031 18:09:15.815141 INFO: [APUAPC] D10_APC_0: 0xffffffff
10032 18:09:15.818298 INFO: [APUAPC] D10_APC_1: 0xffffffff
10033 18:09:15.822130 INFO: [APUAPC] D10_APC_2: 0x3fffff
10034 18:09:15.825138 INFO: [APUAPC] D10_APC_3: 0x0
10035 18:09:15.828178 INFO: [APUAPC] D11_APC_0: 0xffffffff
10036 18:09:15.831579 INFO: [APUAPC] D11_APC_1: 0xffffffff
10037 18:09:15.834958 INFO: [APUAPC] D11_APC_2: 0x3fffff
10038 18:09:15.838530 INFO: [APUAPC] D11_APC_3: 0x0
10039 18:09:15.841809 INFO: [APUAPC] D12_APC_0: 0xffffffff
10040 18:09:15.845170 INFO: [APUAPC] D12_APC_1: 0xffffffff
10041 18:09:15.848049 INFO: [APUAPC] D12_APC_2: 0x3fffff
10042 18:09:15.851690 INFO: [APUAPC] D12_APC_3: 0x0
10043 18:09:15.855083 INFO: [APUAPC] D13_APC_0: 0xffffffff
10044 18:09:15.858367 INFO: [APUAPC] D13_APC_1: 0xffffffff
10045 18:09:15.861510 INFO: [APUAPC] D13_APC_2: 0x3fffff
10046 18:09:15.864837 INFO: [APUAPC] D13_APC_3: 0x0
10047 18:09:15.868505 INFO: [APUAPC] D14_APC_0: 0xffffffff
10048 18:09:15.871677 INFO: [APUAPC] D14_APC_1: 0xffffffff
10049 18:09:15.874923 INFO: [APUAPC] D14_APC_2: 0x3fffff
10050 18:09:15.878697 INFO: [APUAPC] D14_APC_3: 0x0
10051 18:09:15.881759 INFO: [APUAPC] D15_APC_0: 0xffffffff
10052 18:09:15.885026 INFO: [APUAPC] D15_APC_1: 0xffffffff
10053 18:09:15.888104 INFO: [APUAPC] D15_APC_2: 0x3fffff
10054 18:09:15.891396 INFO: [APUAPC] D15_APC_3: 0x0
10055 18:09:15.891817 INFO: [APUAPC] APC_CON: 0x4
10056 18:09:15.895229 INFO: [NOCDAPC] D0_APC_0: 0x0
10057 18:09:15.898633 INFO: [NOCDAPC] D0_APC_1: 0x0
10058 18:09:15.901649 INFO: [NOCDAPC] D1_APC_0: 0x0
10059 18:09:15.904848 INFO: [NOCDAPC] D1_APC_1: 0xfff
10060 18:09:15.908096 INFO: [NOCDAPC] D2_APC_0: 0x0
10061 18:09:15.911938 INFO: [NOCDAPC] D2_APC_1: 0xfff
10062 18:09:15.915088 INFO: [NOCDAPC] D3_APC_0: 0x0
10063 18:09:15.918260 INFO: [NOCDAPC] D3_APC_1: 0xfff
10064 18:09:15.921378 INFO: [NOCDAPC] D4_APC_0: 0x0
10065 18:09:15.921801 INFO: [NOCDAPC] D4_APC_1: 0xfff
10066 18:09:15.924670 INFO: [NOCDAPC] D5_APC_0: 0x0
10067 18:09:15.927812 INFO: [NOCDAPC] D5_APC_1: 0xfff
10068 18:09:15.931545 INFO: [NOCDAPC] D6_APC_0: 0x0
10069 18:09:15.934741 INFO: [NOCDAPC] D6_APC_1: 0xfff
10070 18:09:15.938454 INFO: [NOCDAPC] D7_APC_0: 0x0
10071 18:09:15.941702 INFO: [NOCDAPC] D7_APC_1: 0xfff
10072 18:09:15.944971 INFO: [NOCDAPC] D8_APC_0: 0x0
10073 18:09:15.947963 INFO: [NOCDAPC] D8_APC_1: 0xfff
10074 18:09:15.951735 INFO: [NOCDAPC] D9_APC_0: 0x0
10075 18:09:15.954618 INFO: [NOCDAPC] D9_APC_1: 0xfff
10076 18:09:15.955040 INFO: [NOCDAPC] D10_APC_0: 0x0
10077 18:09:15.958228 INFO: [NOCDAPC] D10_APC_1: 0xfff
10078 18:09:15.961545 INFO: [NOCDAPC] D11_APC_0: 0x0
10079 18:09:15.964897 INFO: [NOCDAPC] D11_APC_1: 0xfff
10080 18:09:15.968116 INFO: [NOCDAPC] D12_APC_0: 0x0
10081 18:09:15.971089 INFO: [NOCDAPC] D12_APC_1: 0xfff
10082 18:09:15.974779 INFO: [NOCDAPC] D13_APC_0: 0x0
10083 18:09:15.977696 INFO: [NOCDAPC] D13_APC_1: 0xfff
10084 18:09:15.981616 INFO: [NOCDAPC] D14_APC_0: 0x0
10085 18:09:15.984788 INFO: [NOCDAPC] D14_APC_1: 0xfff
10086 18:09:15.987961 INFO: [NOCDAPC] D15_APC_0: 0x0
10087 18:09:15.991230 INFO: [NOCDAPC] D15_APC_1: 0xfff
10088 18:09:15.994328 INFO: [NOCDAPC] APC_CON: 0x4
10089 18:09:15.997944 INFO: [APUAPC] set_apusys_apc done
10090 18:09:16.001202 INFO: [DEVAPC] devapc_init done
10091 18:09:16.004534 INFO: GICv3 without legacy support detected.
10092 18:09:16.007659 INFO: ARM GICv3 driver initialized in EL3
10093 18:09:16.010950 INFO: Maximum SPI INTID supported: 639
10094 18:09:16.014676 INFO: BL31: Initializing runtime services
10095 18:09:16.021157 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10096 18:09:16.024411 INFO: SPM: enable CPC mode
10097 18:09:16.031199 INFO: mcdi ready for mcusys-off-idle and system suspend
10098 18:09:16.034420 INFO: BL31: Preparing for EL3 exit to normal world
10099 18:09:16.037685 INFO: Entry point address = 0x80000000
10100 18:09:16.040690 INFO: SPSR = 0x8
10101 18:09:16.045843
10102 18:09:16.046398
10103 18:09:16.046894
10104 18:09:16.048754 Starting depthcharge on Spherion...
10105 18:09:16.049171
10106 18:09:16.049537 Wipe memory regions:
10107 18:09:16.049862
10108 18:09:16.052339 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10109 18:09:16.052951 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10110 18:09:16.053496 Setting prompt string to ['asurada:']
10111 18:09:16.053917 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10112 18:09:16.055011 [0x00000040000000, 0x00000054600000)
10113 18:09:16.174117
10114 18:09:16.174608 [0x00000054660000, 0x00000080000000)
10115 18:09:16.435396
10116 18:09:16.435954 [0x000000821a7280, 0x000000ffe64000)
10117 18:09:17.179609
10118 18:09:17.180206 [0x00000100000000, 0x00000240000000)
10119 18:09:19.069518
10120 18:09:19.072472 Initializing XHCI USB controller at 0x11200000.
10121 18:09:20.111882
10122 18:09:20.115011 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10123 18:09:20.115436
10124 18:09:20.115765
10125 18:09:20.116616 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10127 18:09:20.217462 asurada: tftpboot 192.168.201.1 14291472/tftp-deploy-rq3g_akw/kernel/image.itb 14291472/tftp-deploy-rq3g_akw/kernel/cmdline
10128 18:09:20.217655 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10129 18:09:20.217739 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10130 18:09:20.222351 tftpboot 192.168.201.1 14291472/tftp-deploy-rq3g_akw/kernel/image.itp-deploy-rq3g_akw/kernel/cmdline
10131 18:09:20.222449
10132 18:09:20.222524 Waiting for link
10133 18:09:20.380568
10134 18:09:20.380734 R8152: Initializing
10135 18:09:20.380803
10136 18:09:20.384068 Version 9 (ocp_data = 6010)
10137 18:09:20.384151
10138 18:09:20.387350 R8152: Done initializing
10139 18:09:20.387432
10140 18:09:20.387497 Adding net device
10141 18:09:22.259802
10142 18:09:22.260320 done.
10143 18:09:22.260913
10144 18:09:22.261322 MAC: 00:e0:4c:72:2d:d6
10145 18:09:22.261637
10146 18:09:22.263746 Sending DHCP discover... done.
10147 18:09:22.264274
10148 18:09:22.266532 Waiting for reply... done.
10149 18:09:22.266982
10150 18:09:22.269705 Sending DHCP request... done.
10151 18:09:22.270127
10152 18:09:22.273385 Waiting for reply... done.
10153 18:09:22.273806
10154 18:09:22.274223 My ip is 192.168.201.21
10155 18:09:22.274537
10156 18:09:22.276514 The DHCP server ip is 192.168.201.1
10157 18:09:22.276965
10158 18:09:22.283497 TFTP server IP predefined by user: 192.168.201.1
10159 18:09:22.284028
10160 18:09:22.289871 Bootfile predefined by user: 14291472/tftp-deploy-rq3g_akw/kernel/image.itb
10161 18:09:22.290397
10162 18:09:22.292981 Sending tftp read request... done.
10163 18:09:22.293405
10164 18:09:22.297366 Waiting for the transfer...
10165 18:09:22.297786
10166 18:09:22.706436 00000000 ################################################################
10167 18:09:22.706973
10168 18:09:23.073777 00080000 ################################################################
10169 18:09:23.073908
10170 18:09:23.407750 00100000 ################################################################
10171 18:09:23.407889
10172 18:09:23.696008 00180000 ################################################################
10173 18:09:23.696153
10174 18:09:23.980267 00200000 ################################################################
10175 18:09:23.980461
10176 18:09:24.262872 00280000 ################################################################
10177 18:09:24.263033
10178 18:09:24.515806 00300000 ################################################################
10179 18:09:24.515954
10180 18:09:24.773736 00380000 ################################################################
10181 18:09:24.773881
10182 18:09:25.050620 00400000 ################################################################
10183 18:09:25.050764
10184 18:09:25.335137 00480000 ################################################################
10185 18:09:25.335276
10186 18:09:25.600116 00500000 ################################################################
10187 18:09:25.600258
10188 18:09:25.899941 00580000 ################################################################
10189 18:09:25.900086
10190 18:09:26.286586 00600000 ################################################################
10191 18:09:26.287115
10192 18:09:26.696523 00680000 ################################################################
10193 18:09:26.697120
10194 18:09:27.009926 00700000 ################################################################
10195 18:09:27.010066
10196 18:09:27.299702 00780000 ################################################################
10197 18:09:27.299871
10198 18:09:27.571847 00800000 ################################################################
10199 18:09:27.571995
10200 18:09:27.842628 00880000 ################################################################
10201 18:09:27.842774
10202 18:09:28.127253 00900000 ################################################################
10203 18:09:28.127386
10204 18:09:28.403852 00980000 ################################################################
10205 18:09:28.403997
10206 18:09:28.671637 00a00000 ################################################################
10207 18:09:28.671844
10208 18:09:28.953316 00a80000 ################################################################
10209 18:09:28.953458
10210 18:09:29.221455 00b00000 ################################################################
10211 18:09:29.221597
10212 18:09:29.512488 00b80000 ################################################################
10213 18:09:29.512657
10214 18:09:29.785603 00c00000 ################################################################
10215 18:09:29.785750
10216 18:09:30.062845 00c80000 ################################################################
10217 18:09:30.062981
10218 18:09:30.356921 00d00000 ################################################################
10219 18:09:30.357064
10220 18:09:30.653592 00d80000 ################################################################
10221 18:09:30.653743
10222 18:09:30.925538 00e00000 ################################################################
10223 18:09:30.925688
10224 18:09:31.224558 00e80000 ################################################################
10225 18:09:31.224697
10226 18:09:31.517524 00f00000 ################################################################
10227 18:09:31.517700
10228 18:09:31.797446 00f80000 ################################################################
10229 18:09:31.797579
10230 18:09:32.060656 01000000 ################################################################
10231 18:09:32.060798
10232 18:09:32.320199 01080000 ################################################################
10233 18:09:32.320355
10234 18:09:32.579549 01100000 ################################################################
10235 18:09:32.579717
10236 18:09:32.862335 01180000 ################################################################
10237 18:09:32.862483
10238 18:09:33.153576 01200000 ################################################################
10239 18:09:33.153719
10240 18:09:33.454895 01280000 ################################################################
10241 18:09:33.455054
10242 18:09:33.733970 01300000 ################################################################
10243 18:09:33.734118
10244 18:09:34.008182 01380000 ################################################################
10245 18:09:34.008322
10246 18:09:34.306468 01400000 ################################################################
10247 18:09:34.306603
10248 18:09:34.594237 01480000 ################################################################
10249 18:09:34.594411
10250 18:09:34.873975 01500000 ################################################################
10251 18:09:34.874112
10252 18:09:35.152053 01580000 ################################################################
10253 18:09:35.152202
10254 18:09:35.523727 01600000 ################################################################
10255 18:09:35.524653
10256 18:09:35.734680 01680000 ################################################################
10257 18:09:35.734824
10258 18:09:36.011858 01700000 ################################################################
10259 18:09:36.012002
10260 18:09:36.276183 01780000 ################################################################
10261 18:09:36.276317
10262 18:09:36.545927 01800000 ################################################################
10263 18:09:36.546078
10264 18:09:36.810458 01880000 ################################################################
10265 18:09:36.810619
10266 18:09:37.082344 01900000 ################################################################
10267 18:09:37.082479
10268 18:09:37.333493 01980000 ################################################################
10269 18:09:37.333620
10270 18:09:37.612186 01a00000 ################################################################
10271 18:09:37.612318
10272 18:09:37.891986 01a80000 ################################################################
10273 18:09:37.892124
10274 18:09:38.144150 01b00000 ################################################################
10275 18:09:38.144313
10276 18:09:38.391648 01b80000 ################################################################
10277 18:09:38.391785
10278 18:09:38.638292 01c00000 ################################################################
10279 18:09:38.638434
10280 18:09:38.885355 01c80000 ################################################################
10281 18:09:38.885496
10282 18:09:39.133129 01d00000 ################################################################
10283 18:09:39.133270
10284 18:09:39.382802 01d80000 ################################################################
10285 18:09:39.382961
10286 18:09:39.608028 01e00000 ######################################################## done.
10287 18:09:39.608189
10288 18:09:39.611127 The bootfile was 31914810 bytes long.
10289 18:09:39.611216
10290 18:09:39.614626 Sending tftp read request... done.
10291 18:09:39.614784
10292 18:09:39.614910 Waiting for the transfer...
10293 18:09:39.615029
10294 18:09:39.617924 00000000 # done.
10295 18:09:39.618048
10296 18:09:39.624484 Command line loaded dynamically from TFTP file: 14291472/tftp-deploy-rq3g_akw/kernel/cmdline
10297 18:09:39.624720
10298 18:09:39.648155 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10299 18:09:39.648301
10300 18:09:39.648368 Loading FIT.
10301 18:09:39.648428
10302 18:09:39.651353 Image ramdisk-1 has 18740413 bytes.
10303 18:09:39.651435
10304 18:09:39.654581 Image fdt-1 has 47258 bytes.
10305 18:09:39.654662
10306 18:09:39.658139 Image kernel-1 has 13125101 bytes.
10307 18:09:39.658220
10308 18:09:39.668012 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10309 18:09:39.668094
10310 18:09:39.684577 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10311 18:09:39.684677
10312 18:09:39.687696 Choosing best match conf-1 for compat google,spherion-rev2.
10313 18:09:39.691319
10314 18:09:39.694626 Connected to device vid:did:rid of 1ae0:0028:00
10315 18:09:39.704939
10316 18:09:39.708375 tpm_get_response: command 0x17b, return code 0x0
10317 18:09:39.708454
10318 18:09:39.711758 ec_init: CrosEC protocol v3 supported (256, 248)
10319 18:09:39.716659
10320 18:09:39.720000 tpm_cleanup: add release locality here.
10321 18:09:39.720083
10322 18:09:39.720148 Shutting down all USB controllers.
10323 18:09:39.723674
10324 18:09:39.723756 Removing current net device
10325 18:09:39.723827
10326 18:09:39.730190 Exiting depthcharge with code 4 at timestamp: 53027183
10327 18:09:39.730272
10328 18:09:39.733367 LZMA decompressing kernel-1 to 0x821a6718
10329 18:09:39.733450
10330 18:09:39.736962 LZMA decompressing kernel-1 to 0x40000000
10331 18:09:41.354512
10332 18:09:41.354657 jumping to kernel
10333 18:09:41.355119 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10334 18:09:41.355218 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10335 18:09:41.355298 Setting prompt string to ['Linux version [0-9]']
10336 18:09:41.355367 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10337 18:09:41.355434 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10338 18:09:41.435787
10339 18:09:41.439467 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10340 18:09:41.442794 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10341 18:09:41.442907 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10342 18:09:41.443008 Setting prompt string to []
10343 18:09:41.443098 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10344 18:09:41.443231 Using line separator: #'\n'#
10345 18:09:41.443318 No login prompt set.
10346 18:09:41.443394 Parsing kernel messages
10347 18:09:41.443462 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10348 18:09:41.443616 [login-action] Waiting for messages, (timeout 00:04:02)
10349 18:09:41.443680 Waiting using forced prompt support (timeout 00:02:01)
10350 18:09:41.462815 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10351 18:09:41.466335 [ 0.000000] random: crng init done
10352 18:09:41.469672 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10353 18:09:41.472721 [ 0.000000] efi: UEFI not found.
10354 18:09:41.483008 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10355 18:09:41.489326 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10356 18:09:41.499401 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10357 18:09:41.509432 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10358 18:09:41.516085 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10359 18:09:41.519562 [ 0.000000] printk: bootconsole [mtk8250] enabled
10360 18:09:41.528148 [ 0.000000] NUMA: No NUMA configuration found
10361 18:09:41.534379 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10362 18:09:41.541122 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10363 18:09:41.541208 [ 0.000000] Zone ranges:
10364 18:09:41.547892 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10365 18:09:41.551533 [ 0.000000] DMA32 empty
10366 18:09:41.558175 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10367 18:09:41.561232 [ 0.000000] Movable zone start for each node
10368 18:09:41.564915 [ 0.000000] Early memory node ranges
10369 18:09:41.571474 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10370 18:09:41.577605 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10371 18:09:41.584359 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10372 18:09:41.591201 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10373 18:09:41.597663 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10374 18:09:41.604492 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10375 18:09:41.660963 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10376 18:09:41.667572 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10377 18:09:41.674028 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10378 18:09:41.677504 [ 0.000000] psci: probing for conduit method from DT.
10379 18:09:41.684073 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10380 18:09:41.687372 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10381 18:09:41.693771 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10382 18:09:41.697150 [ 0.000000] psci: SMC Calling Convention v1.2
10383 18:09:41.704155 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10384 18:09:41.707373 [ 0.000000] Detected VIPT I-cache on CPU0
10385 18:09:41.713897 [ 0.000000] CPU features: detected: GIC system register CPU interface
10386 18:09:41.720467 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10387 18:09:41.727489 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10388 18:09:41.733912 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10389 18:09:41.740629 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10390 18:09:41.747290 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10391 18:09:41.754046 [ 0.000000] alternatives: applying boot alternatives
10392 18:09:41.757497 [ 0.000000] Fallback order for Node 0: 0
10393 18:09:41.764149 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10394 18:09:41.767700 [ 0.000000] Policy zone: Normal
10395 18:09:41.790705 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10396 18:09:41.801083 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10397 18:09:41.813737 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10398 18:09:41.824072 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10399 18:09:41.830704 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10400 18:09:41.834290 <6>[ 0.000000] software IO TLB: area num 8.
10401 18:09:41.890141 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10402 18:09:42.039790 <6>[ 0.000000] Memory: 7945760K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407008K reserved, 32768K cma-reserved)
10403 18:09:42.046473 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10404 18:09:42.053407 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10405 18:09:42.056806 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10406 18:09:42.063129 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10407 18:09:42.069744 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10408 18:09:42.073487 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10409 18:09:42.083155 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10410 18:09:42.090011 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10411 18:09:42.093061 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10412 18:09:42.101010 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10413 18:09:42.104173 <6>[ 0.000000] GICv3: 608 SPIs implemented
10414 18:09:42.110813 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10415 18:09:42.113961 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10416 18:09:42.117375 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10417 18:09:42.127410 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10418 18:09:42.137349 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10419 18:09:42.150533 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10420 18:09:42.157298 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10421 18:09:42.166480 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10422 18:09:42.179554 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10423 18:09:42.186335 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10424 18:09:42.193023 <6>[ 0.009181] Console: colour dummy device 80x25
10425 18:09:42.202923 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10426 18:09:42.206533 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10427 18:09:42.213243 <6>[ 0.029221] LSM: Security Framework initializing
10428 18:09:42.219928 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10429 18:09:42.230017 <6>[ 0.041972] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 18:09:42.236778 <6>[ 0.051243] cblist_init_generic: Setting adjustable number of callback queues.
10431 18:09:42.243036 <6>[ 0.058732] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 18:09:42.250030 <6>[ 0.065071] cblist_init_generic: Setting adjustable number of callback queues.
10433 18:09:42.256906 <6>[ 0.072498] cblist_init_generic: Setting shift to 3 and lim to 1.
10434 18:09:42.263335 <6>[ 0.078938] rcu: Hierarchical SRCU implementation.
10435 18:09:42.266554 <6>[ 0.083953] rcu: Max phase no-delay instances is 1000.
10436 18:09:42.274705 <6>[ 0.090989] EFI services will not be available.
10437 18:09:42.277850 <6>[ 0.095943] smp: Bringing up secondary CPUs ...
10438 18:09:42.287164 <6>[ 0.100956] Detected VIPT I-cache on CPU1
10439 18:09:42.293435 <6>[ 0.101018] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10440 18:09:42.300203 <6>[ 0.101043] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10441 18:09:42.303742 <6>[ 0.101377] Detected VIPT I-cache on CPU2
10442 18:09:42.310554 <6>[ 0.101430] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10443 18:09:42.316882 <6>[ 0.101450] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10444 18:09:42.323769 <6>[ 0.101708] Detected VIPT I-cache on CPU3
10445 18:09:42.330521 <6>[ 0.101756] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10446 18:09:42.337212 <6>[ 0.101770] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10447 18:09:42.340274 <6>[ 0.102075] CPU features: detected: Spectre-v4
10448 18:09:42.347447 <6>[ 0.102081] CPU features: detected: Spectre-BHB
10449 18:09:42.350381 <6>[ 0.102085] Detected PIPT I-cache on CPU4
10450 18:09:42.357337 <6>[ 0.102144] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10451 18:09:42.363953 <6>[ 0.102161] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10452 18:09:42.367460 <6>[ 0.102457] Detected PIPT I-cache on CPU5
10453 18:09:42.377477 <6>[ 0.102520] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10454 18:09:42.384248 <6>[ 0.102536] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10455 18:09:42.387185 <6>[ 0.102817] Detected PIPT I-cache on CPU6
10456 18:09:42.393933 <6>[ 0.102881] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10457 18:09:42.400729 <6>[ 0.102897] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10458 18:09:42.404366 <6>[ 0.103197] Detected PIPT I-cache on CPU7
10459 18:09:42.411038 <6>[ 0.103262] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10460 18:09:42.417347 <6>[ 0.103278] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10461 18:09:42.424081 <6>[ 0.103325] smp: Brought up 1 node, 8 CPUs
10462 18:09:42.427697 <6>[ 0.244681] SMP: Total of 8 processors activated.
10463 18:09:42.434075 <6>[ 0.249602] CPU features: detected: 32-bit EL0 Support
10464 18:09:42.440711 <6>[ 0.254965] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10465 18:09:42.447367 <6>[ 0.263766] CPU features: detected: Common not Private translations
10466 18:09:42.454032 <6>[ 0.270281] CPU features: detected: CRC32 instructions
10467 18:09:42.460791 <6>[ 0.275666] CPU features: detected: RCpc load-acquire (LDAPR)
10468 18:09:42.467806 <6>[ 0.281626] CPU features: detected: LSE atomic instructions
10469 18:09:42.470863 <6>[ 0.287407] CPU features: detected: Privileged Access Never
10470 18:09:42.477715 <6>[ 0.293187] CPU features: detected: RAS Extension Support
10471 18:09:42.484466 <6>[ 0.298796] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10472 18:09:42.487537 <6>[ 0.306061] CPU: All CPU(s) started at EL2
10473 18:09:42.494108 <6>[ 0.310377] alternatives: applying system-wide alternatives
10474 18:09:42.504813 <6>[ 0.321194] devtmpfs: initialized
10475 18:09:42.517075 <6>[ 0.330140] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10476 18:09:42.526930 <6>[ 0.340100] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10477 18:09:42.533596 <6>[ 0.348118] pinctrl core: initialized pinctrl subsystem
10478 18:09:42.537014 <6>[ 0.354808] DMI not present or invalid.
10479 18:09:42.543421 <6>[ 0.359223] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10480 18:09:42.553662 <6>[ 0.366080] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10481 18:09:42.560394 <6>[ 0.373670] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10482 18:09:42.570439 <6>[ 0.381892] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10483 18:09:42.573845 <6>[ 0.390135] audit: initializing netlink subsys (disabled)
10484 18:09:42.583326 <5>[ 0.395829] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10485 18:09:42.587072 <6>[ 0.396554] thermal_sys: Registered thermal governor 'step_wise'
10486 18:09:42.596937 <6>[ 0.403796] thermal_sys: Registered thermal governor 'power_allocator'
10487 18:09:42.600522 <6>[ 0.410051] cpuidle: using governor menu
10488 18:09:42.603520 <6>[ 0.421012] NET: Registered PF_QIPCRTR protocol family
10489 18:09:42.613477 <6>[ 0.426500] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10490 18:09:42.616951 <6>[ 0.433602] ASID allocator initialised with 32768 entries
10491 18:09:42.623675 <6>[ 0.440194] Serial: AMBA PL011 UART driver
10492 18:09:42.632572 <4>[ 0.449082] Trying to register duplicate clock ID: 134
10493 18:09:42.692612 <6>[ 0.512321] KASLR enabled
10494 18:09:42.706958 <6>[ 0.519963] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10495 18:09:42.713666 <6>[ 0.526976] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10496 18:09:42.719759 <6>[ 0.533462] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10497 18:09:42.726525 <6>[ 0.540466] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10498 18:09:42.733374 <6>[ 0.546953] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10499 18:09:42.740027 <6>[ 0.553957] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10500 18:09:42.746561 <6>[ 0.560444] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10501 18:09:42.753308 <6>[ 0.567446] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10502 18:09:42.756857 <6>[ 0.574911] ACPI: Interpreter disabled.
10503 18:09:42.764734 <6>[ 0.581348] iommu: Default domain type: Translated
10504 18:09:42.771511 <6>[ 0.586494] iommu: DMA domain TLB invalidation policy: strict mode
10505 18:09:42.774972 <5>[ 0.593154] SCSI subsystem initialized
10506 18:09:42.781542 <6>[ 0.597403] usbcore: registered new interface driver usbfs
10507 18:09:42.788034 <6>[ 0.603135] usbcore: registered new interface driver hub
10508 18:09:42.791538 <6>[ 0.608688] usbcore: registered new device driver usb
10509 18:09:42.798302 <6>[ 0.614811] pps_core: LinuxPPS API ver. 1 registered
10510 18:09:42.808092 <6>[ 0.620005] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10511 18:09:42.811702 <6>[ 0.629351] PTP clock support registered
10512 18:09:42.814775 <6>[ 0.633594] EDAC MC: Ver: 3.0.0
10513 18:09:42.822544 <6>[ 0.638743] FPGA manager framework
10514 18:09:42.828727 <6>[ 0.642419] Advanced Linux Sound Architecture Driver Initialized.
10515 18:09:42.831842 <6>[ 0.649203] vgaarb: loaded
10516 18:09:42.838459 <6>[ 0.652358] clocksource: Switched to clocksource arch_sys_counter
10517 18:09:42.842052 <5>[ 0.658803] VFS: Disk quotas dquot_6.6.0
10518 18:09:42.848698 <6>[ 0.662990] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10519 18:09:42.851571 <6>[ 0.670183] pnp: PnP ACPI: disabled
10520 18:09:42.860210 <6>[ 0.676931] NET: Registered PF_INET protocol family
10521 18:09:42.870079 <6>[ 0.682524] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10522 18:09:42.881533 <6>[ 0.694860] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10523 18:09:42.891384 <6>[ 0.703676] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10524 18:09:42.898496 <6>[ 0.711646] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10525 18:09:42.905058 <6>[ 0.720351] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10526 18:09:42.916770 <6>[ 0.730099] TCP: Hash tables configured (established 65536 bind 65536)
10527 18:09:42.923676 <6>[ 0.736967] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10528 18:09:42.930224 <6>[ 0.744166] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10529 18:09:42.936673 <6>[ 0.751874] NET: Registered PF_UNIX/PF_LOCAL protocol family
10530 18:09:42.943279 <6>[ 0.758020] RPC: Registered named UNIX socket transport module.
10531 18:09:42.946776 <6>[ 0.764175] RPC: Registered udp transport module.
10532 18:09:42.953107 <6>[ 0.769110] RPC: Registered tcp transport module.
10533 18:09:42.959604 <6>[ 0.774043] RPC: Registered tcp NFSv4.1 backchannel transport module.
10534 18:09:42.963182 <6>[ 0.780708] PCI: CLS 0 bytes, default 64
10535 18:09:42.966314 <6>[ 0.785067] Unpacking initramfs...
10536 18:09:42.976449 <6>[ 0.788784] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10537 18:09:42.983082 <6>[ 0.797413] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10538 18:09:42.989976 <6>[ 0.806222] kvm [1]: IPA Size Limit: 40 bits
10539 18:09:42.992907 <6>[ 0.810753] kvm [1]: GICv3: no GICV resource entry
10540 18:09:42.999696 <6>[ 0.815775] kvm [1]: disabling GICv2 emulation
10541 18:09:43.006385 <6>[ 0.820461] kvm [1]: GIC system register CPU interface enabled
10542 18:09:43.009575 <6>[ 0.826627] kvm [1]: vgic interrupt IRQ18
10543 18:09:43.015883 <6>[ 0.832409] kvm [1]: VHE mode initialized successfully
10544 18:09:43.022504 <5>[ 0.838693] Initialise system trusted keyrings
10545 18:09:43.029209 <6>[ 0.843491] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10546 18:09:43.036929 <6>[ 0.853519] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10547 18:09:43.043703 <5>[ 0.859889] NFS: Registering the id_resolver key type
10548 18:09:43.046793 <5>[ 0.865187] Key type id_resolver registered
10549 18:09:43.053524 <5>[ 0.869601] Key type id_legacy registered
10550 18:09:43.059908 <6>[ 0.873877] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10551 18:09:43.066998 <6>[ 0.880797] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10552 18:09:43.073333 <6>[ 0.888486] 9p: Installing v9fs 9p2000 file system support
10553 18:09:43.109347 <5>[ 0.926097] Key type asymmetric registered
10554 18:09:43.112832 <5>[ 0.930429] Asymmetric key parser 'x509' registered
10555 18:09:43.122673 <6>[ 0.935563] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10556 18:09:43.126246 <6>[ 0.943179] io scheduler mq-deadline registered
10557 18:09:43.129438 <6>[ 0.947941] io scheduler kyber registered
10558 18:09:43.148524 <6>[ 0.964983] EINJ: ACPI disabled.
10559 18:09:43.181596 <4>[ 0.991425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 18:09:43.191455 <4>[ 1.002045] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 18:09:43.206310 <6>[ 1.022845] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10562 18:09:43.214330 <6>[ 1.030789] printk: console [ttyS0] disabled
10563 18:09:43.242024 <6>[ 1.055425] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10564 18:09:43.248663 <6>[ 1.064906] printk: console [ttyS0] enabled
10565 18:09:43.252225 <6>[ 1.064906] printk: console [ttyS0] enabled
10566 18:09:43.258974 <6>[ 1.073800] printk: bootconsole [mtk8250] disabled
10567 18:09:43.262068 <6>[ 1.073800] printk: bootconsole [mtk8250] disabled
10568 18:09:43.268739 <6>[ 1.084827] SuperH (H)SCI(F) driver initialized
10569 18:09:43.272110 <6>[ 1.090080] msm_serial: driver initialized
10570 18:09:43.285562 <6>[ 1.098967] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10571 18:09:43.295532 <6>[ 1.107513] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10572 18:09:43.302207 <6>[ 1.116055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10573 18:09:43.312195 <6>[ 1.124683] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10574 18:09:43.322629 <6>[ 1.133389] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10575 18:09:43.328778 <6>[ 1.142109] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10576 18:09:43.338724 <6>[ 1.150650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10577 18:09:43.345321 <6>[ 1.159447] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10578 18:09:43.355582 <6>[ 1.167989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10579 18:09:43.367303 <6>[ 1.183758] loop: module loaded
10580 18:09:43.373577 <6>[ 1.189762] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10581 18:09:43.396414 <4>[ 1.213114] mtk-pmic-keys: Failed to locate of_node [id: -1]
10582 18:09:43.403406 <6>[ 1.219867] megasas: 07.719.03.00-rc1
10583 18:09:43.413125 <6>[ 1.229510] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10584 18:09:43.419588 <6>[ 1.235760] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10585 18:09:43.435329 <6>[ 1.251673] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10586 18:09:43.490995 <6>[ 1.300916] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10587 18:09:43.755181 <6>[ 1.571580] Freeing initrd memory: 18296K
10588 18:09:43.766917 <6>[ 1.583400] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10589 18:09:43.777653 <6>[ 1.594231] tun: Universal TUN/TAP device driver, 1.6
10590 18:09:43.781200 <6>[ 1.600294] thunder_xcv, ver 1.0
10591 18:09:43.784416 <6>[ 1.603797] thunder_bgx, ver 1.0
10592 18:09:43.787604 <6>[ 1.607297] nicpf, ver 1.0
10593 18:09:43.798168 <6>[ 1.611329] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10594 18:09:43.801700 <6>[ 1.618805] hns3: Copyright (c) 2017 Huawei Corporation.
10595 18:09:43.804728 <6>[ 1.624392] hclge is initializing
10596 18:09:43.811419 <6>[ 1.627968] e1000: Intel(R) PRO/1000 Network Driver
10597 18:09:43.817959 <6>[ 1.633098] e1000: Copyright (c) 1999-2006 Intel Corporation.
10598 18:09:43.821596 <6>[ 1.639114] e1000e: Intel(R) PRO/1000 Network Driver
10599 18:09:43.828022 <6>[ 1.644329] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10600 18:09:43.834507 <6>[ 1.650514] igb: Intel(R) Gigabit Ethernet Network Driver
10601 18:09:43.841145 <6>[ 1.656164] igb: Copyright (c) 2007-2014 Intel Corporation.
10602 18:09:43.847669 <6>[ 1.662001] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10603 18:09:43.854404 <6>[ 1.668519] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10604 18:09:43.858019 <6>[ 1.674981] sky2: driver version 1.30
10605 18:09:43.864537 <6>[ 1.679911] usbcore: registered new device driver r8152-cfgselector
10606 18:09:43.871198 <6>[ 1.686447] usbcore: registered new interface driver r8152
10607 18:09:43.874596 <6>[ 1.692264] VFIO - User Level meta-driver version: 0.3
10608 18:09:43.883963 <6>[ 1.700494] usbcore: registered new interface driver usb-storage
10609 18:09:43.890737 <6>[ 1.706935] usbcore: registered new device driver onboard-usb-hub
10610 18:09:43.899512 <6>[ 1.716084] mt6397-rtc mt6359-rtc: registered as rtc0
10611 18:09:43.909389 <6>[ 1.721552] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:08:17 UTC (1718129297)
10612 18:09:43.912663 <6>[ 1.731116] i2c_dev: i2c /dev entries driver
10613 18:09:43.926650 <4>[ 1.743102] cpu cpu0: supply cpu not found, using dummy regulator
10614 18:09:43.933088 <4>[ 1.749543] cpu cpu1: supply cpu not found, using dummy regulator
10615 18:09:43.939602 <4>[ 1.755948] cpu cpu2: supply cpu not found, using dummy regulator
10616 18:09:43.946570 <4>[ 1.762347] cpu cpu3: supply cpu not found, using dummy regulator
10617 18:09:43.953457 <4>[ 1.768746] cpu cpu4: supply cpu not found, using dummy regulator
10618 18:09:43.960083 <4>[ 1.775146] cpu cpu5: supply cpu not found, using dummy regulator
10619 18:09:43.966388 <4>[ 1.781562] cpu cpu6: supply cpu not found, using dummy regulator
10620 18:09:43.973001 <4>[ 1.787959] cpu cpu7: supply cpu not found, using dummy regulator
10621 18:09:43.992901 <6>[ 1.809597] cpu cpu0: EM: created perf domain
10622 18:09:43.996421 <6>[ 1.814509] cpu cpu4: EM: created perf domain
10623 18:09:44.003436 <6>[ 1.820075] sdhci: Secure Digital Host Controller Interface driver
10624 18:09:44.010156 <6>[ 1.826506] sdhci: Copyright(c) Pierre Ossman
10625 18:09:44.016702 <6>[ 1.831467] Synopsys Designware Multimedia Card Interface Driver
10626 18:09:44.023248 <6>[ 1.838104] sdhci-pltfm: SDHCI platform and OF driver helper
10627 18:09:44.026781 <6>[ 1.838150] mmc0: CQHCI version 5.10
10628 18:09:44.033161 <6>[ 1.848314] ledtrig-cpu: registered to indicate activity on CPUs
10629 18:09:44.040199 <6>[ 1.855294] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10630 18:09:44.046651 <6>[ 1.862344] usbcore: registered new interface driver usbhid
10631 18:09:44.049719 <6>[ 1.868165] usbhid: USB HID core driver
10632 18:09:44.056320 <6>[ 1.872369] spi_master spi0: will run message pump with realtime priority
10633 18:09:44.107443 <6>[ 1.917145] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10634 18:09:44.127479 <6>[ 1.933594] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10635 18:09:44.130576 <6>[ 1.944544] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10636 18:09:44.138123 <6>[ 1.949832] cros-ec-spi spi0.0: Chrome EC device registered
10637 18:09:44.141173 <6>[ 1.959001] mmc0: Command Queue Engine enabled
10638 18:09:44.147814 <6>[ 1.963728] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 18:09:44.154400 <6>[ 1.971081] mmcblk0: mmc0:0001 DA4128 116 GiB
10640 18:09:44.164526 <6>[ 1.973107] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10641 18:09:44.170770 <6>[ 1.979869] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 18:09:44.174451 <6>[ 1.986149] NET: Registered PF_PACKET protocol family
10643 18:09:44.181227 <6>[ 1.992266] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10644 18:09:44.184162 <6>[ 1.996411] 9pnet: Installing 9P2000 support
10645 18:09:44.190874 <6>[ 2.002243] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10646 18:09:44.193960 <5>[ 2.006094] Key type dns_resolver registered
10647 18:09:44.200694 <6>[ 2.011855] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10648 18:09:44.203754 <6>[ 2.016254] registered taskstats version 1
10649 18:09:44.210568 <5>[ 2.026689] Loading compiled-in X.509 certificates
10650 18:09:44.243495 <4>[ 2.053454] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10651 18:09:44.253484 <4>[ 2.064174] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 18:09:44.268313 <6>[ 2.084965] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10653 18:09:44.275003 <6>[ 2.091847] xhci-mtk 11200000.usb: xHCI Host Controller
10654 18:09:44.281650 <6>[ 2.097388] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10655 18:09:44.292112 <6>[ 2.105264] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10656 18:09:44.298408 <6>[ 2.114704] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10657 18:09:44.305091 <6>[ 2.120885] xhci-mtk 11200000.usb: xHCI Host Controller
10658 18:09:44.312064 <6>[ 2.126375] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10659 18:09:44.318965 <6>[ 2.134036] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10660 18:09:44.325651 <6>[ 2.141849] hub 1-0:1.0: USB hub found
10661 18:09:44.328662 <6>[ 2.145881] hub 1-0:1.0: 1 port detected
10662 18:09:44.335541 <6>[ 2.150171] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10663 18:09:44.342062 <6>[ 2.158885] hub 2-0:1.0: USB hub found
10664 18:09:44.345562 <6>[ 2.162914] hub 2-0:1.0: 1 port detected
10665 18:09:44.353505 <6>[ 2.170114] mtk-msdc 11f70000.mmc: Got CD GPIO
10666 18:09:44.372076 <6>[ 2.185660] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 18:09:44.382395 <6>[ 2.194066] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 18:09:44.389058 <6>[ 2.202405] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 18:09:44.398659 <6>[ 2.210743] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 18:09:44.405456 <6>[ 2.219082] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 18:09:44.415569 <6>[ 2.227420] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 18:09:44.421944 <6>[ 2.235757] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 18:09:44.432040 <6>[ 2.244096] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 18:09:44.438764 <6>[ 2.252438] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 18:09:44.448426 <6>[ 2.260778] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 18:09:44.455536 <6>[ 2.269126] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 18:09:44.465421 <6>[ 2.277464] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 18:09:44.472007 <6>[ 2.285802] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 18:09:44.481826 <6>[ 2.294140] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 18:09:44.488517 <6>[ 2.302477] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 18:09:44.494915 <6>[ 2.311213] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 18:09:44.501501 <6>[ 2.318443] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 18:09:44.508280 <6>[ 2.325221] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 18:09:44.518402 <6>[ 2.331988] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 18:09:44.525177 <6>[ 2.338968] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 18:09:44.531719 <6>[ 2.345822] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 18:09:44.542068 <6>[ 2.354956] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 18:09:44.551647 <6>[ 2.364076] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 18:09:44.561771 <6>[ 2.373372] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 18:09:44.571636 <6>[ 2.382839] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 18:09:44.578273 <6>[ 2.392306] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 18:09:44.588396 <6>[ 2.401425] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 18:09:44.598274 <6>[ 2.410891] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 18:09:44.608022 <6>[ 2.420010] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 18:09:44.618021 <6>[ 2.429309] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 18:09:44.627937 <6>[ 2.439469] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 18:09:44.637744 <6>[ 2.451075] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 18:09:44.645634 <6>[ 2.462214] Trying to probe devices needed for running init ...
10699 18:09:44.655816 <3>[ 2.469523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10700 18:09:44.735714 <6>[ 2.548864] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10701 18:09:44.762908 <6>[ 2.579689] hub 2-1:1.0: USB hub found
10702 18:09:44.766424 <6>[ 2.584131] hub 2-1:1.0: 3 ports detected
10703 18:09:44.775497 <6>[ 2.592285] hub 2-1:1.0: USB hub found
10704 18:09:44.778936 <6>[ 2.596745] hub 2-1:1.0: 3 ports detected
10705 18:09:44.887016 <6>[ 2.700650] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10706 18:09:45.042117 <6>[ 2.858835] hub 1-1:1.0: USB hub found
10707 18:09:45.045220 <6>[ 2.863328] hub 1-1:1.0: 4 ports detected
10708 18:09:45.058521 <6>[ 2.875021] hub 1-1:1.0: USB hub found
10709 18:09:45.061501 <6>[ 2.879381] hub 1-1:1.0: 4 ports detected
10710 18:09:45.119623 <6>[ 2.932795] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10711 18:09:45.227538 <6>[ 3.041046] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10712 18:09:45.259493 <4>[ 3.073155] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10713 18:09:45.269731 <4>[ 3.082300] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10714 18:09:45.308491 <6>[ 3.125520] r8152 2-1.3:1.0 eth0: v1.12.13
10715 18:09:45.382774 <6>[ 3.196652] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10716 18:09:45.516530 <6>[ 3.333232] hub 1-1.4:1.0: USB hub found
10717 18:09:45.520001 <6>[ 3.337982] hub 1-1.4:1.0: 2 ports detected
10718 18:09:45.533029 <6>[ 3.349819] hub 1-1.4:1.0: USB hub found
10719 18:09:45.536104 <6>[ 3.354566] hub 1-1.4:1.0: 2 ports detected
10720 18:09:45.835611 <6>[ 3.648671] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10721 18:09:46.031978 <6>[ 3.844691] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10722 18:09:46.969432 <6>[ 4.786150] r8152 2-1.3:1.0 eth0: carrier on
10723 18:09:49.423867 <5>[ 4.812471] Sending DHCP requests .., OK
10724 18:09:49.430483 <6>[ 7.244812] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10725 18:09:49.433679 <6>[ 7.253135] IP-Config: Complete:
10726 18:09:49.446883 <6>[ 7.256631] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10727 18:09:49.453358 <6>[ 7.267341] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10728 18:09:49.460149 <6>[ 7.275957] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10729 18:09:49.466912 <6>[ 7.275967] nameserver0=192.168.201.1
10730 18:09:49.470283 <6>[ 7.288135] clk: Disabling unused clocks
10731 18:09:49.473338 <6>[ 7.293681] ALSA device list:
10732 18:09:49.479822 <6>[ 7.296955] No soundcards found.
10733 18:09:49.487822 <6>[ 7.304689] Freeing unused kernel memory: 8512K
10734 18:09:49.491026 <6>[ 7.309623] Run /init as init process
10735 18:09:49.500775 Loading, please wait...
10736 18:09:49.528798 Starting systemd-udevd version 252.22-1~deb12u1
10737 18:09:49.824265 <6>[ 7.637783] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10738 18:09:49.834426 <6>[ 7.645826] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10739 18:09:49.840992 <6>[ 7.654620] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10740 18:09:49.875127 <4>[ 7.688210] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10741 18:09:49.881163 <6>[ 7.692713] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10742 18:09:49.895594 <4>[ 7.709283] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10743 18:09:49.909379 <6>[ 7.722629] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10744 18:09:49.912484 <6>[ 7.730067] mc: Linux media interface: v0.10
10745 18:09:49.922727 <6>[ 7.731052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10746 18:09:49.929110 <3>[ 7.744273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 18:09:49.939181 <4>[ 7.744380] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10748 18:09:49.948998 <3>[ 7.753342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 18:09:49.955780 <6>[ 7.762467] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10750 18:09:49.962116 <6>[ 7.762749] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10751 18:09:49.972453 <6>[ 7.762755] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10752 18:09:49.979101 <6>[ 7.763041] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10753 18:09:49.988636 <6>[ 7.763060] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10754 18:09:49.995440 <6>[ 7.763066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10755 18:09:50.005474 <6>[ 7.763072] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10756 18:09:50.012051 <3>[ 7.770339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 18:09:50.018377 <6>[ 7.770855] videodev: Linux video capture interface: v2.00
10758 18:09:50.024995 <6>[ 7.783286] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10759 18:09:50.031632 <3>[ 7.785799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 18:09:50.041677 <3>[ 7.785808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 18:09:50.048461 <3>[ 7.785813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 18:09:50.055108 <6>[ 7.793938] pci_bus 0000:00: root bus resource [bus 00-ff]
10763 18:09:50.065065 <3>[ 7.801666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 18:09:50.071410 <3>[ 7.801678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 18:09:50.077837 <3>[ 7.801751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 18:09:50.087712 <6>[ 7.809734] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10767 18:09:50.094380 <4>[ 7.813994] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10768 18:09:50.101137 <4>[ 7.813994] Fallback method does not support PEC.
10769 18:09:50.107717 <3>[ 7.817403] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 18:09:50.117310 <6>[ 7.826501] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10771 18:09:50.127036 <6>[ 7.832686] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10772 18:09:50.133849 <3>[ 7.834573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10773 18:09:50.147377 <6>[ 7.835205] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10774 18:09:50.154037 <6>[ 7.835472] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10775 18:09:50.160847 <6>[ 7.840341] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10776 18:09:50.170896 <3>[ 7.847168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 18:09:50.177253 <3>[ 7.847209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 18:09:50.183998 <6>[ 7.848523] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10779 18:09:50.190622 <6>[ 7.850816] remoteproc remoteproc0: scp is available
10780 18:09:50.193754 <6>[ 7.850875] remoteproc remoteproc0: powering up scp
10781 18:09:50.204095 <6>[ 7.850879] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10782 18:09:50.210550 <6>[ 7.850891] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10783 18:09:50.217123 <6>[ 7.855307] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10784 18:09:50.223812 <3>[ 7.863341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 18:09:50.230849 <6>[ 7.871539] pci 0000:00:00.0: supports D1 D2
10786 18:09:50.236956 <3>[ 7.877163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 18:09:50.243831 <6>[ 7.885244] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 18:09:50.247047 <6>[ 7.886068] Bluetooth: Core ver 2.22
10789 18:09:50.253562 <6>[ 7.886294] NET: Registered PF_BLUETOOTH protocol family
10790 18:09:50.260152 <6>[ 7.886297] Bluetooth: HCI device and connection manager initialized
10791 18:09:50.266771 <6>[ 7.886318] Bluetooth: HCI socket layer initialized
10792 18:09:50.270130 <6>[ 7.886323] Bluetooth: L2CAP socket layer initialized
10793 18:09:50.276629 <6>[ 7.886334] Bluetooth: SCO socket layer initialized
10794 18:09:50.283240 <3>[ 7.893323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 18:09:50.290161 <6>[ 7.902659] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10796 18:09:50.299786 <6>[ 7.902668] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10797 18:09:50.306037 <6>[ 7.902773] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10798 18:09:50.312753 <6>[ 7.902799] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10799 18:09:50.319363 <6>[ 7.902817] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10800 18:09:50.329235 <6>[ 7.902831] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10801 18:09:50.332849 <6>[ 7.902940] pci 0000:01:00.0: supports D1 D2
10802 18:09:50.339285 <6>[ 7.902942] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10803 18:09:50.345940 <3>[ 7.908526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 18:09:50.355798 <3>[ 7.908577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 18:09:50.362864 <6>[ 7.912418] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10806 18:09:50.369440 <6>[ 7.912446] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10807 18:09:50.379562 <6>[ 7.912449] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10808 18:09:50.385948 <6>[ 7.912457] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10809 18:09:50.395726 <6>[ 7.912470] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10810 18:09:50.402619 <6>[ 7.912482] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10811 18:09:50.408698 <6>[ 7.912494] pci 0000:00:00.0: PCI bridge to [bus 01]
10812 18:09:50.415353 <6>[ 7.912499] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10813 18:09:50.422095 <6>[ 7.912630] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10814 18:09:50.428725 <6>[ 7.913093] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10815 18:09:50.432117 <6>[ 7.913550] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10816 18:09:50.445042 <6>[ 7.924124] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10817 18:09:50.455106 <5>[ 7.932989] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10818 18:09:50.458414 <6>[ 7.940592] usbcore: registered new interface driver uvcvideo
10819 18:09:50.465056 <6>[ 7.941776] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10820 18:09:50.471988 <6>[ 7.958903] usbcore: registered new interface driver btusb
10821 18:09:50.481713 <4>[ 7.959521] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10822 18:09:50.488413 <3>[ 7.959533] Bluetooth: hci0: Failed to load firmware file (-2)
10823 18:09:50.494956 <3>[ 7.959537] Bluetooth: hci0: Failed to set up firmware (-2)
10824 18:09:50.505069 <4>[ 7.959541] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10825 18:09:50.511304 <5>[ 7.963544] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10826 18:09:50.521364 <5>[ 7.964065] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10827 18:09:50.527948 <4>[ 7.964137] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10828 18:09:50.534574 <6>[ 7.964146] cfg80211: failed to load regulatory.db
10829 18:09:50.541202 <6>[ 7.976577] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10830 18:09:50.550929 <6>[ 7.976589] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10831 18:09:50.557517 <6>[ 7.984175] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10832 18:09:50.563952 <6>[ 7.991260] remoteproc remoteproc0: remote processor scp is now up
10833 18:09:50.573983 <6>[ 8.001803] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10834 18:09:50.580682 <6>[ 8.078542] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10835 18:09:50.587423 <6>[ 8.402236] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10836 18:09:50.611499 <6>[ 8.428468] mt7921e 0000:01:00.0: ASIC revision: 79610010
10837 18:09:50.714707 <6>[ 8.528168] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10838 18:09:50.717758 <6>[ 8.528168]
10839 18:09:50.826111 Begin: Loading essential drivers ... done.
10840 18:09:50.829172 Begin: Running /scripts/init-premount ... done.
10841 18:09:50.836317 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10842 18:09:50.845721 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10843 18:09:50.849190 Device /sys/class/net/eth0 found
10844 18:09:50.849720 done.
10845 18:09:50.855919 Begin: Waiting up to 180 secs for any network device to become available ... done.
10846 18:09:50.927887 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10847 18:09:50.934246 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10848 18:09:50.940608 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10849 18:09:50.947128 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10850 18:09:50.953820 host : mt8192-asurada-spherion-r0-cbg-1
10851 18:09:50.960535 domain : lava-rack
10852 18:09:50.963692 rootserver: 192.168.201.1 rootpath:
10853 18:09:50.964114 filename :
10854 18:09:50.982539 <6>[ 8.796345] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10855 18:09:51.095330 done.
10856 18:09:51.103024 Begin: Running /scripts/nfs-bottom ... done.
10857 18:09:51.120258 Begin: Running /scripts/init-bottom ... done.
10858 18:09:52.463428 <6>[ 10.280739] NET: Registered PF_INET6 protocol family
10859 18:09:52.470981 <6>[ 10.287949] Segment Routing with IPv6
10860 18:09:52.473936 <6>[ 10.291936] In-situ OAM (IOAM) with IPv6
10861 18:09:52.640097 <30>[ 10.430743] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10862 18:09:52.646808 <30>[ 10.463817] systemd[1]: Detected architecture arm64.
10863 18:09:52.653686
10864 18:09:52.657158 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10865 18:09:52.657584
10866 18:09:52.680396 <30>[ 10.497830] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10867 18:09:53.663951 <30>[ 11.478077] systemd[1]: Queued start job for default target graphical.target.
10868 18:09:53.712008 <30>[ 11.525881] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10869 18:09:53.718767 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10870 18:09:53.740601 <30>[ 11.554437] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10871 18:09:53.750853 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10872 18:09:53.768125 <30>[ 11.582381] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10873 18:09:53.778166 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10874 18:09:53.796210 <30>[ 11.610037] systemd[1]: Created slice user.slice - User and Session Slice.
10875 18:09:53.802297 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10876 18:09:53.826206 <30>[ 11.636937] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10877 18:09:53.832818 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10878 18:09:53.854752 <30>[ 11.664888] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10879 18:09:53.861003 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10880 18:09:53.889378 <30>[ 11.693285] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10881 18:09:53.899306 <30>[ 11.713198] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10882 18:09:53.906027 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10883 18:09:53.922766 <30>[ 11.736652] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10884 18:09:53.929373 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10885 18:09:53.946786 <30>[ 11.760708] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10886 18:09:53.956998 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10887 18:09:53.971997 <30>[ 11.788760] systemd[1]: Reached target paths.target - Path Units.
10888 18:09:53.981265 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10889 18:09:53.998895 <30>[ 11.813092] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10890 18:09:54.006164 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10891 18:09:54.019496 <30>[ 11.836644] systemd[1]: Reached target slices.target - Slice Units.
10892 18:09:54.029493 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10893 18:09:54.044182 <30>[ 11.861156] systemd[1]: Reached target swap.target - Swaps.
10894 18:09:54.050408 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10895 18:09:54.071476 <30>[ 11.885155] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10896 18:09:54.081232 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10897 18:09:54.099624 <30>[ 11.913654] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10898 18:09:54.109490 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10899 18:09:54.128584 <30>[ 11.942745] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10900 18:09:54.138497 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10901 18:09:54.156847 <30>[ 11.970914] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10902 18:09:54.167406 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10903 18:09:54.183470 <30>[ 11.997286] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10904 18:09:54.189987 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10905 18:09:54.208525 <30>[ 12.022314] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10906 18:09:54.218119 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10907 18:09:54.237706 <30>[ 12.051463] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10908 18:09:54.247683 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10909 18:09:54.263609 <30>[ 12.077126] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10910 18:09:54.273110 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10911 18:09:54.322782 <30>[ 12.137105] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10912 18:09:54.329412 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10913 18:09:54.348793 <30>[ 12.163146] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10914 18:09:54.355566 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10915 18:09:54.378542 <30>[ 12.192585] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10916 18:09:54.384913 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10917 18:09:54.409848 <30>[ 12.217094] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10918 18:09:54.467656 <30>[ 12.281443] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10919 18:09:54.477292 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10920 18:09:54.499578 <30>[ 12.313560] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10921 18:09:54.506025 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10922 18:09:54.551611 <30>[ 12.365389] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10923 18:09:54.558014 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10924 18:09:54.582354 <30>[ 12.396678] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10925 18:09:54.589350 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10926 18:09:54.610745 <30>[ 12.424634] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10927 18:09:54.623745 Startin<6>[ 12.435470] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10928 18:09:54.627398 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10929 18:09:54.650141 <30>[ 12.464278] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10930 18:09:54.656757 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10931 18:09:54.682615 <30>[ 12.496695] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10932 18:09:54.689345 Starting [0;1;39mmodpr<6>[ 12.507476] fuse: init (API version 7.37)
10933 18:09:54.696063 obe@loop.ser…e[0m - Load Kernel Module loop...
10934 18:09:54.739162 <30>[ 12.553413] systemd[1]: Starting systemd-journald.service - Journal Service...
10935 18:09:54.745711 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10936 18:09:54.778797 <30>[ 12.592764] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10937 18:09:54.785182 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10938 18:09:54.814063 <30>[ 12.624947] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10939 18:09:54.820676 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10940 18:09:54.871324 <30>[ 12.685484] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10941 18:09:54.881061 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10942 18:09:54.908253 <30>[ 12.722118] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10943 18:09:54.914755 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10944 18:09:54.946561 <30>[ 12.760934] systemd[1]: Started systemd-journald.service - Journal Service.
10945 18:09:54.953230 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10946 18:09:54.978808 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10947 18:09:54.995429 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10948 18:09:55.010820 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10949 18:09:55.031642 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10950 18:09:55.056822 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10951 18:09:55.076982 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10952 18:09:55.096010 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10953 18:09:55.116187 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10954 18:09:55.137198 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10955 18:09:55.157043 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10956 18:09:55.176444 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10957 18:09:55.196192 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10958 18:09:55.216668 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10959 18:09:55.237926 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10960 18:09:55.295909 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10961 18:09:55.321502 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10962 18:09:55.347005 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10963 18:09:55.365651 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10964 18:09:55.406362 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ke<46>[ 13.218989] systemd-journald[311]: Received client request to flush runtime journal.
10965 18:09:55.406812 rnel Variables...
10966 18:09:55.431932 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10967 18:09:55.732843 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10968 18:09:55.751569 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10969 18:09:55.770981 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10970 18:09:55.791620 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10971 18:09:56.180258 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10972 18:09:56.529849 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10973 18:09:56.590833 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10974 18:09:56.814601 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10975 18:09:56.917445 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10976 18:09:56.935635 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10977 18:09:56.954576 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10978 18:09:57.002950 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10979 18:09:57.025016 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10980 18:09:57.304224 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10981 18:09:57.364428 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10982 18:09:57.423948 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10983 18:09:57.452024 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10984 18:09:57.627931 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10985 18:09:57.642686 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10986 18:09:57.740806 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10987 18:09:57.755674 <6>[ 15.573315] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10988 18:09:57.808591 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10989 18:09:57.905198 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10990 18:09:57.931396 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10991 18:09:57.982316 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10992 18:09:57.998961 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10993 18:09:58.030081 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10994 18:09:58.049050 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10995 18:09:58.070435 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10996 18:09:58.086318 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10997 18:09:58.102644 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10998 18:09:58.126801 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10999 18:09:58.145852 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11000 18:09:58.162639 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11001 18:09:58.182196 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11002 18:09:58.202300 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11003 18:09:58.221970 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11004 18:09:58.241090 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11005 18:09:58.257945 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11006 18:09:58.274706 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11007 18:09:58.294259 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11008 18:09:58.332291 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11009 18:09:58.415288 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11010 18:09:58.486921 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11011 18:09:58.512462 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11012 18:09:58.544464 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11013 18:09:58.565648 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11014 18:09:58.616488 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11015 18:09:58.658486 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11016 18:09:58.681854 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11017 18:09:58.698497 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11018 18:09:58.727428 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11019 18:09:58.753429 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11020 18:09:58.885235 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11021 18:09:58.908746 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11022 18:09:58.927059 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11023 18:09:58.976271 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11024 18:09:59.030582 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11025 18:09:59.115292
11026 18:09:59.118719 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11027 18:09:59.119143
11028 18:09:59.121763 debian-bookworm-arm64 login: root (automatic login)
11029 18:09:59.122178
11030 18:09:59.424619 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11031 18:09:59.425107
11032 18:09:59.430502 The programs included with the Debian GNU/Linux system are free software;
11033 18:09:59.437078 the exact distribution terms for each program are described in the
11034 18:09:59.440588 individual files in /usr/share/doc/*/copyright.
11035 18:09:59.440662
11036 18:09:59.446986 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11037 18:09:59.450324 permitted by applicable law.
11038 18:10:00.411014 Matched prompt #10: / #
11040 18:10:00.411304 Setting prompt string to ['/ #']
11041 18:10:00.411402 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11043 18:10:00.411601 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11044 18:10:00.411695 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
11045 18:10:00.411769 Setting prompt string to ['/ #']
11046 18:10:00.411831 Forcing a shell prompt, looking for ['/ #']
11048 18:10:00.462057 / #
11049 18:10:00.462388 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11050 18:10:00.462597 Waiting using forced prompt support (timeout 00:02:30)
11051 18:10:00.467588
11052 18:10:00.468375 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11053 18:10:00.468860 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
11055 18:10:00.569955 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e'
11056 18:10:00.576715 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291472/extract-nfsrootfs-v_8s5z7e'
11058 18:10:00.678501 / # export NFS_SERVER_IP='192.168.201.1'
11059 18:10:00.685286 export NFS_SERVER_IP='192.168.201.1'
11060 18:10:00.686219 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11061 18:10:00.686763 end: 2.2 depthcharge-retry (duration 00:01:18) [common]
11062 18:10:00.687246 end: 2 depthcharge-action (duration 00:01:18) [common]
11063 18:10:00.687726 start: 3 lava-test-retry (timeout 00:08:03) [common]
11064 18:10:00.688201 start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11065 18:10:00.688647 Using namespace: common
11067 18:10:00.789936 / # #
11068 18:10:00.790658 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11069 18:10:00.796522 #
11070 18:10:00.797460 Using /lava-14291472
11072 18:10:00.898932 / # export SHELL=/bin/bash
11073 18:10:00.905570 export SHELL=/bin/bash
11075 18:10:01.007246 / # . /lava-14291472/environment
11076 18:10:01.013266 . /lava-14291472/environment
11078 18:10:01.121668 / # /lava-14291472/bin/lava-test-runner /lava-14291472/0
11079 18:10:01.121843 Test shell timeout: 10s (minimum of the action and connection timeout)
11080 18:10:01.127444 /lava-14291472/bin/lava-test-runner /lava-14291472/0
11081 18:10:01.373688 + export TESTRUN_ID=0_timesync-off
11082 18:10:01.376500 + TESTRUN_ID=0_timesync-off
11083 18:10:01.380428 + cd /lava-14291472/0/tests/0_timesync-off
11084 18:10:01.383420 ++ cat uuid
11085 18:10:01.387048 + UUID=14291472_1.6.2.3.1
11086 18:10:01.387471 + set +x
11087 18:10:01.390078 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14291472_1.6.2.3.1>
11088 18:10:01.390780 Received signal: <STARTRUN> 0_timesync-off 14291472_1.6.2.3.1
11089 18:10:01.391160 Starting test lava.0_timesync-off (14291472_1.6.2.3.1)
11090 18:10:01.391568 Skipping test definition patterns.
11091 18:10:01.393321 + systemctl stop systemd-timesyncd
11092 18:10:01.468672 + set +x
11093 18:10:01.471737 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14291472_1.6.2.3.1>
11094 18:10:01.472436 Received signal: <ENDRUN> 0_timesync-off 14291472_1.6.2.3.1
11095 18:10:01.472895 Ending use of test pattern.
11096 18:10:01.473212 Ending test lava.0_timesync-off (14291472_1.6.2.3.1), duration 0.08
11098 18:10:01.536006 + export TESTRUN_ID=1_kselftest-tpm2
11099 18:10:01.539731 + TESTRUN_ID=1_kselftest-tpm2
11100 18:10:01.546083 + cd /lava-14291472/0/tests/1_kselftest-tpm2
11101 18:10:01.546207 ++ cat uuid
11102 18:10:01.550070 + UUID=14291472_1.6.2.3.5
11103 18:10:01.550206 + set +x
11104 18:10:01.556291 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14291472_1.6.2.3.5>
11105 18:10:01.556592 Received signal: <STARTRUN> 1_kselftest-tpm2 14291472_1.6.2.3.5
11106 18:10:01.556721 Starting test lava.1_kselftest-tpm2 (14291472_1.6.2.3.5)
11107 18:10:01.556866 Skipping test definition patterns.
11108 18:10:01.559640 + cd ./automated/linux/kselftest/
11109 18:10:01.586433 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11110 18:10:01.629672 INFO: install_deps skipped
11111 18:10:02.140667 --2024-06-11 18:08:36-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11112 18:10:02.150955 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11113 18:10:02.283542 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11114 18:10:02.417085 HTTP request sent, awaiting response... 200 OK
11115 18:10:02.420241 Length: 1647744 (1.6M) [application/octet-stream]
11116 18:10:02.423147 Saving to: 'kselftest_armhf.tar.gz'
11117 18:10:02.423640
11118 18:10:02.424100
11119 18:10:02.682214 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11120 18:10:02.948189 kselftest_armhf.tar 2%[ ] 47.81K 181KB/s
11121 18:10:03.259794 kselftest_armhf.tar 13%[=> ] 218.91K 412KB/s
11122 18:10:03.396624 kselftest_armhf.tar 50%[=========> ] 808.57K 959KB/s
11123 18:10:03.403275 kselftest_armhf.tar 100%[===================>] 1.57M 1.60MB/s in 1.0s
11124 18:10:03.403610
11125 18:10:03.547462 2024-06-11 18:08:37 (1.60 MB/s) - 'kselftest_armhf.tar.gz' saved [1647744/1647744]
11126 18:10:03.547595
11127 18:10:07.827098 skiplist:
11128 18:10:07.830510 ========================================
11129 18:10:07.833530 ========================================
11130 18:10:07.877735 tpm2:test_smoke.sh
11131 18:10:07.881332 tpm2:test_space.sh
11132 18:10:07.896573 ============== Tests to run ===============
11133 18:10:07.896734 tpm2:test_smoke.sh
11134 18:10:07.899956 tpm2:test_space.sh
11135 18:10:07.903134 ===========End Tests to run ===============
11136 18:10:07.903261 shardfile-tpm2 pass
11137 18:10:08.006927 <12>[ 25.826401] kselftest: Running tests in tpm2
11138 18:10:08.016120 TAP version 13
11139 18:10:08.030488 1..2
11140 18:10:08.059916 # selftests: tpm2: test_smoke.sh
11141 18:10:09.837523 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11142 18:10:09.843788 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11143 18:10:09.850545 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11144 18:10:09.853967 # Traceback (most recent call last):
11145 18:10:09.863867 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11146 18:10:09.863952 # if self.tpm:
11147 18:10:09.867158 # ^^^^^^^^
11148 18:10:09.870654 # AttributeError: 'Client' object has no attribute 'tpm'
11149 18:10:09.877066 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11150 18:10:09.883960 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11151 18:10:09.887489 # Traceback (most recent call last):
11152 18:10:09.897007 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11153 18:10:09.897231 # if self.tpm:
11154 18:10:09.900673 # ^^^^^^^^
11155 18:10:09.903710 # AttributeError: 'Client' object has no attribute 'tpm'
11156 18:10:09.910671 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11157 18:10:09.917640 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11158 18:10:09.920717 # Traceback (most recent call last):
11159 18:10:09.930670 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11160 18:10:09.934270 # if self.tpm:
11161 18:10:09.934803 # ^^^^^^^^
11162 18:10:09.940692 # AttributeError: 'Client' object has no attribute 'tpm'
11163 18:10:09.947447 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11164 18:10:09.954367 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11165 18:10:09.957449 # Traceback (most recent call last):
11166 18:10:09.967249 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11167 18:10:09.967853 # if self.tpm:
11168 18:10:09.970436 # ^^^^^^^^
11169 18:10:09.974053 # AttributeError: 'Client' object has no attribute 'tpm'
11170 18:10:09.980497 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11171 18:10:09.987248 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11172 18:10:09.990266 # Traceback (most recent call last):
11173 18:10:10.000148 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11174 18:10:10.003417 # if self.tpm:
11175 18:10:10.003548 # ^^^^^^^^
11176 18:10:10.010187 # AttributeError: 'Client' object has no attribute 'tpm'
11177 18:10:10.016879 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11178 18:10:10.020305 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11179 18:10:10.023274 # Traceback (most recent call last):
11180 18:10:10.033098 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11181 18:10:10.036529 # if self.tpm:
11182 18:10:10.036689 # ^^^^^^^^
11183 18:10:10.043291 # AttributeError: 'Client' object has no attribute 'tpm'
11184 18:10:10.050190 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11185 18:10:10.056424 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11186 18:10:10.060149 # Traceback (most recent call last):
11187 18:10:10.070140 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11188 18:10:10.073400 # if self.tpm:
11189 18:10:10.073498 # ^^^^^^^^
11190 18:10:10.079927 # AttributeError: 'Client' object has no attribute 'tpm'
11191 18:10:10.086333 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11192 18:10:10.093191 # Exception ignored in: <function Client.__del__ at 0xffff8725ccc0>
11193 18:10:10.096480 # Traceback (most recent call last):
11194 18:10:10.106650 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11195 18:10:10.106780 # if self.tpm:
11196 18:10:10.109770 # ^^^^^^^^
11197 18:10:10.113504 # AttributeError: 'Client' object has no attribute 'tpm'
11198 18:10:10.116447 #
11199 18:10:10.119926 # ======================================================================
11200 18:10:10.130715 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11201 18:10:10.134288 # ----------------------------------------------------------------------
11202 18:10:10.137271 # Traceback (most recent call last):
11203 18:10:10.147380 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11204 18:10:10.153936 # self.root_key = self.client.create_root_key()
11205 18:10:10.157689 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11206 18:10:10.167590 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11207 18:10:10.174646 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11208 18:10:10.177665 # ^^^^^^^^^^^^^^^^^^
11209 18:10:10.187746 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11210 18:10:10.190950 # raise ProtocolError(cc, rc)
11211 18:10:10.197357 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11212 18:10:10.197516 #
11213 18:10:10.204188 # ======================================================================
11214 18:10:10.210502 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11215 18:10:10.217169 # ----------------------------------------------------------------------
11216 18:10:10.220886 # Traceback (most recent call last):
11217 18:10:10.230638 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11218 18:10:10.233601 # self.client = tpm2.Client()
11219 18:10:10.237231 # ^^^^^^^^^^^^^
11220 18:10:10.247422 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11221 18:10:10.250505 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11222 18:10:10.257196 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11223 18:10:10.260853 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11224 18:10:10.263911 #
11225 18:10:10.270386 # ======================================================================
11226 18:10:10.273796 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11227 18:10:10.280312 # ----------------------------------------------------------------------
11228 18:10:10.283935 # Traceback (most recent call last):
11229 18:10:10.293954 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11230 18:10:10.297307 # self.client = tpm2.Client()
11231 18:10:10.300464 # ^^^^^^^^^^^^^
11232 18:10:10.310560 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11233 18:10:10.317457 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11234 18:10:10.320638 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11235 18:10:10.327626 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11236 18:10:10.327944 #
11237 18:10:10.334416 # ======================================================================
11238 18:10:10.341096 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11239 18:10:10.347934 # ----------------------------------------------------------------------
11240 18:10:10.350892 # Traceback (most recent call last):
11241 18:10:10.361095 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11242 18:10:10.361643 # self.client = tpm2.Client()
11243 18:10:10.364089 # ^^^^^^^^^^^^^
11244 18:10:10.374069 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11245 18:10:10.380681 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11246 18:10:10.384334 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11247 18:10:10.390710 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11248 18:10:10.391295 #
11249 18:10:10.398592 # ======================================================================
11250 18:10:10.405500 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11251 18:10:10.412270 # ----------------------------------------------------------------------
11252 18:10:10.416111 # Traceback (most recent call last):
11253 18:10:10.425153 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11254 18:10:10.428410 # self.client = tpm2.Client()
11255 18:10:10.431577 # ^^^^^^^^^^^^^
11256 18:10:10.439616 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11257 18:10:10.447354 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11258 18:10:10.453831 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11259 18:10:10.457221 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11260 18:10:10.457641 #
11261 18:10:10.463872 # ======================================================================
11262 18:10:10.467311 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11263 18:10:10.474350 # ----------------------------------------------------------------------
11264 18:10:10.477716 # Traceback (most recent call last):
11265 18:10:10.487769 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11266 18:10:10.490897 # self.client = tpm2.Client()
11267 18:10:10.494164 # ^^^^^^^^^^^^^
11268 18:10:10.503950 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11269 18:10:10.510347 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11270 18:10:10.513985 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11271 18:10:10.520205 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11272 18:10:10.520673 #
11273 18:10:10.526982 # ======================================================================
11274 18:10:10.534119 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11275 18:10:10.537215 # ----------------------------------------------------------------------
11276 18:10:10.540773 # Traceback (most recent call last):
11277 18:10:10.550720 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11278 18:10:10.554006 # self.client = tpm2.Client()
11279 18:10:10.557190 # ^^^^^^^^^^^^^
11280 18:10:10.567249 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11281 18:10:10.573950 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11282 18:10:10.577804 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11283 18:10:10.584003 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11284 18:10:10.584512 #
11285 18:10:10.591042 # ======================================================================
11286 18:10:10.598007 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11287 18:10:10.604354 # ----------------------------------------------------------------------
11288 18:10:10.607940 # Traceback (most recent call last):
11289 18:10:10.617955 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11290 18:10:10.621004 # self.client = tpm2.Client()
11291 18:10:10.624265 # ^^^^^^^^^^^^^
11292 18:10:10.634224 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11293 18:10:10.637496 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11294 18:10:10.643826 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11295 18:10:10.647279 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11296 18:10:10.647700 #
11297 18:10:10.654245 # ======================================================================
11298 18:10:10.664378 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11299 18:10:10.670990 # ----------------------------------------------------------------------
11300 18:10:10.674472 # Traceback (most recent call last):
11301 18:10:10.684411 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11302 18:10:10.687640 # self.client = tpm2.Client()
11303 18:10:10.688072 # ^^^^^^^^^^^^^
11304 18:10:10.697303 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11305 18:10:10.704054 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11306 18:10:10.707056 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11307 18:10:10.713808 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11308 18:10:10.714359 #
11309 18:10:10.720705 # ----------------------------------------------------------------------
11310 18:10:10.723797 # Ran 9 tests in 0.051s
11311 18:10:10.724475 #
11312 18:10:10.725130 # FAILED (errors=9)
11313 18:10:10.730526 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11314 18:10:10.737227 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11315 18:10:10.737644 #
11316 18:10:10.744100 # ----------------------------------------------------------------------
11317 18:10:10.747450 # Ran 2 tests in 0.025s
11318 18:10:10.747870 #
11319 18:10:10.748200 # OK
11320 18:10:10.750241 ok 1 selftests: tpm2: test_smoke.sh
11321 18:10:10.753790 # selftests: tpm2: test_space.sh
11322 18:10:10.760837 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11323 18:10:10.767184 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11324 18:10:10.770475 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11325 18:10:10.777389 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11326 18:10:10.780224 #
11327 18:10:10.783845 # ======================================================================
11328 18:10:10.790385 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11329 18:10:10.796837 # ----------------------------------------------------------------------
11330 18:10:10.800578 # Traceback (most recent call last):
11331 18:10:10.813790 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11332 18:10:10.816789 # root1 = space1.create_root_key()
11333 18:10:10.820606 # ^^^^^^^^^^^^^^^^^^^^^^^^
11334 18:10:10.830397 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11335 18:10:10.833975 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11336 18:10:10.840830 # ^^^^^^^^^^^^^^^^^^
11337 18:10:10.850666 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11338 18:10:10.853697 # raise ProtocolError(cc, rc)
11339 18:10:10.857101 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11340 18:10:10.861120 #
11341 18:10:10.867110 # ======================================================================
11342 18:10:10.870791 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11343 18:10:10.876832 # ----------------------------------------------------------------------
11344 18:10:10.880448 # Traceback (most recent call last):
11345 18:10:10.893676 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11346 18:10:10.894111 # space1.create_root_key()
11347 18:10:10.906725 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11348 18:10:10.910341 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11349 18:10:10.916656 # ^^^^^^^^^^^^^^^^^^
11350 18:10:10.926903 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11351 18:10:10.927329 # raise ProtocolError(cc, rc)
11352 18:10:10.933574 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11353 18:10:10.933992 #
11354 18:10:10.940624 # ======================================================================
11355 18:10:10.946702 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11356 18:10:10.953494 # ----------------------------------------------------------------------
11357 18:10:10.957146 # Traceback (most recent call last):
11358 18:10:10.966791 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11359 18:10:10.970563 # root1 = space1.create_root_key()
11360 18:10:10.973453 # ^^^^^^^^^^^^^^^^^^^^^^^^
11361 18:10:10.983680 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11362 18:10:10.990317 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11363 18:10:10.997124 # ^^^^^^^^^^^^^^^^^^
11364 18:10:11.003804 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11365 18:10:11.007209 # raise ProtocolError(cc, rc)
11366 18:10:11.013900 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11367 18:10:11.014491 #
11368 18:10:11.020276 # ======================================================================
11369 18:10:11.026773 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11370 18:10:11.033421 # ----------------------------------------------------------------------
11371 18:10:11.036936 # Traceback (most recent call last):
11372 18:10:11.049762 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11373 18:10:11.053464 # root1 = space1.create_root_key()
11374 18:10:11.056511 # ^^^^^^^^^^^^^^^^^^^^^^^^
11375 18:10:11.066627 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11376 18:10:11.069936 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11377 18:10:11.076663 # ^^^^^^^^^^^^^^^^^^
11378 18:10:11.086306 # File "/lava-14291472/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11379 18:10:11.090019 # raise ProtocolError(cc, rc)
11380 18:10:11.096529 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11381 18:10:11.096664 #
11382 18:10:11.103226 # ----------------------------------------------------------------------
11383 18:10:11.103314 # Ran 4 tests in 0.067s
11384 18:10:11.103382 #
11385 18:10:11.106430 # FAILED (errors=4)
11386 18:10:11.109536 not ok 2 selftests: tpm2: test_space.sh # exit=1
11387 18:10:11.379715 tpm2_test_smoke_sh pass
11388 18:10:11.382682 tpm2_test_space_sh fail
11389 18:10:11.450891 + ../../utils/send-to-lava.sh ./output/result.txt
11390 18:10:11.521756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11391 18:10:11.522097 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11393 18:10:11.570433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11394 18:10:11.570762 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11396 18:10:11.617778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11397 18:10:11.618287 + set +x
11398 18:10:11.618894 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11400 18:10:11.624645 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14291472_1.6.2.3.5>
11401 18:10:11.625311 Received signal: <ENDRUN> 1_kselftest-tpm2 14291472_1.6.2.3.5
11402 18:10:11.625675 Ending use of test pattern.
11403 18:10:11.625984 Ending test lava.1_kselftest-tpm2 (14291472_1.6.2.3.5), duration 10.07
11405 18:10:11.628057 <LAVA_TEST_RUNNER EXIT>
11406 18:10:11.628715 ok: lava_test_shell seems to have completed
11407 18:10:11.629243 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11408 18:10:11.629651 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11409 18:10:11.630068 end: 3 lava-test-retry (duration 00:00:11) [common]
11410 18:10:11.630487 start: 4 finalize (timeout 00:07:53) [common]
11411 18:10:11.630921 start: 4.1 power-off (timeout 00:00:30) [common]
11412 18:10:11.631645 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11413 18:10:11.880469 >> Command sent successfully.
11414 18:10:11.893381 Returned 0 in 0 seconds
11415 18:10:11.994532 end: 4.1 power-off (duration 00:00:00) [common]
11417 18:10:11.996099 start: 4.2 read-feedback (timeout 00:07:52) [common]
11418 18:10:11.997278 Listened to connection for namespace 'common' for up to 1s
11419 18:10:12.998036 Finalising connection for namespace 'common'
11420 18:10:12.998651 Disconnecting from shell: Finalise
11421 18:10:12.999004 / #
11422 18:10:13.099919 end: 4.2 read-feedback (duration 00:00:01) [common]
11423 18:10:13.100628 end: 4 finalize (duration 00:00:01) [common]
11424 18:10:13.101229 Cleaning after the job
11425 18:10:13.101721 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/ramdisk
11426 18:10:13.111172 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/kernel
11427 18:10:13.144184 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/dtb
11428 18:10:13.144506 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/nfsrootfs
11429 18:10:13.212047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291472/tftp-deploy-rq3g_akw/modules
11430 18:10:13.217677 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291472
11431 18:10:13.738691 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291472
11432 18:10:13.738873 Job finished correctly