Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 34
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 25
1 18:08:37.183344 lava-dispatcher, installed at version: 2024.03
2 18:08:37.183547 start: 0 validate
3 18:08:37.183677 Start time: 2024-06-11 18:08:37.183670+00:00 (UTC)
4 18:08:37.183793 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:08:37.183914 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:08:37.454542 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:08:37.455258 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:08:37.726346 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:08:37.727065 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:08:37.999968 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:08:38.000635 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:08:38.531671 Using caching service: 'http://localhost/cache/?uri=%s'
13 18:08:38.532448 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 18:08:38.810356 validate duration: 1.63
16 18:08:38.811744 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:08:38.812339 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:08:38.812893 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:08:38.813501 Not decompressing ramdisk as can be used compressed.
20 18:08:38.813974 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 18:08:38.814424 saving as /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/ramdisk/initrd.cpio.gz
22 18:08:38.814821 total size: 5628151 (5 MB)
23 18:08:38.820035 progress 0 % (0 MB)
24 18:08:38.829427 progress 5 % (0 MB)
25 18:08:38.836490 progress 10 % (0 MB)
26 18:08:38.840607 progress 15 % (0 MB)
27 18:08:38.846382 progress 20 % (1 MB)
28 18:08:38.849131 progress 25 % (1 MB)
29 18:08:38.852039 progress 30 % (1 MB)
30 18:08:38.854574 progress 35 % (1 MB)
31 18:08:38.856770 progress 40 % (2 MB)
32 18:08:38.858965 progress 45 % (2 MB)
33 18:08:38.860926 progress 50 % (2 MB)
34 18:08:38.862957 progress 55 % (2 MB)
35 18:08:38.864908 progress 60 % (3 MB)
36 18:08:38.866648 progress 65 % (3 MB)
37 18:08:38.868411 progress 70 % (3 MB)
38 18:08:38.869974 progress 75 % (4 MB)
39 18:08:38.871711 progress 80 % (4 MB)
40 18:08:38.873126 progress 85 % (4 MB)
41 18:08:38.874743 progress 90 % (4 MB)
42 18:08:38.876348 progress 95 % (5 MB)
43 18:08:38.877762 progress 100 % (5 MB)
44 18:08:38.877969 5 MB downloaded in 0.06 s (84.97 MB/s)
45 18:08:38.878122 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:08:38.878461 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:08:38.878548 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:08:38.878632 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:08:38.878758 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 18:08:38.878828 saving as /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/kernel/Image
52 18:08:38.878887 total size: 54813184 (52 MB)
53 18:08:38.878946 No compression specified
54 18:08:38.880109 progress 0 % (0 MB)
55 18:08:38.894047 progress 5 % (2 MB)
56 18:08:38.907986 progress 10 % (5 MB)
57 18:08:38.921577 progress 15 % (7 MB)
58 18:08:38.935675 progress 20 % (10 MB)
59 18:08:38.949630 progress 25 % (13 MB)
60 18:08:38.963422 progress 30 % (15 MB)
61 18:08:38.977515 progress 35 % (18 MB)
62 18:08:38.991542 progress 40 % (20 MB)
63 18:08:39.005281 progress 45 % (23 MB)
64 18:08:39.019383 progress 50 % (26 MB)
65 18:08:39.033292 progress 55 % (28 MB)
66 18:08:39.047158 progress 60 % (31 MB)
67 18:08:39.061084 progress 65 % (34 MB)
68 18:08:39.074672 progress 70 % (36 MB)
69 18:08:39.088394 progress 75 % (39 MB)
70 18:08:39.102089 progress 80 % (41 MB)
71 18:08:39.115727 progress 85 % (44 MB)
72 18:08:39.129771 progress 90 % (47 MB)
73 18:08:39.143690 progress 95 % (49 MB)
74 18:08:39.157160 progress 100 % (52 MB)
75 18:08:39.157387 52 MB downloaded in 0.28 s (187.70 MB/s)
76 18:08:39.157536 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:08:39.157768 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:08:39.157852 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:08:39.157933 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:08:39.158066 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 18:08:39.158133 saving as /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/dtb/mt8192-asurada-spherion-r0.dtb
83 18:08:39.158220 total size: 47258 (0 MB)
84 18:08:39.158292 No compression specified
85 18:08:39.159417 progress 69 % (0 MB)
86 18:08:39.159682 progress 100 % (0 MB)
87 18:08:39.159834 0 MB downloaded in 0.00 s (27.97 MB/s)
88 18:08:39.159953 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:08:39.160165 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:08:39.160247 start: 1.4 download-retry (timeout 00:10:00) [common]
92 18:08:39.160326 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 18:08:39.160432 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 18:08:39.160496 saving as /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/nfsrootfs/full.rootfs.tar
95 18:08:39.160554 total size: 69067788 (65 MB)
96 18:08:39.160613 Using unxz to decompress xz
97 18:08:39.164591 progress 0 % (0 MB)
98 18:08:39.355472 progress 5 % (3 MB)
99 18:08:39.556172 progress 10 % (6 MB)
100 18:08:39.757886 progress 15 % (9 MB)
101 18:08:39.921113 progress 20 % (13 MB)
102 18:08:40.098237 progress 25 % (16 MB)
103 18:08:40.298402 progress 30 % (19 MB)
104 18:08:40.416416 progress 35 % (23 MB)
105 18:08:40.512922 progress 40 % (26 MB)
106 18:08:40.711898 progress 45 % (29 MB)
107 18:08:40.920330 progress 50 % (32 MB)
108 18:08:41.125788 progress 55 % (36 MB)
109 18:08:41.344056 progress 60 % (39 MB)
110 18:08:41.530382 progress 65 % (42 MB)
111 18:08:41.723264 progress 70 % (46 MB)
112 18:08:41.914072 progress 75 % (49 MB)
113 18:08:42.126171 progress 80 % (52 MB)
114 18:08:42.302696 progress 85 % (56 MB)
115 18:08:42.493961 progress 90 % (59 MB)
116 18:08:42.694911 progress 95 % (62 MB)
117 18:08:42.894622 progress 100 % (65 MB)
118 18:08:42.900655 65 MB downloaded in 3.74 s (17.61 MB/s)
119 18:08:42.900908 end: 1.4.1 http-download (duration 00:00:04) [common]
121 18:08:42.901174 end: 1.4 download-retry (duration 00:00:04) [common]
122 18:08:42.901262 start: 1.5 download-retry (timeout 00:09:56) [common]
123 18:08:42.901348 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 18:08:42.901493 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 18:08:42.901565 saving as /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/modules/modules.tar
126 18:08:42.901624 total size: 8618176 (8 MB)
127 18:08:42.901686 Using unxz to decompress xz
128 18:08:42.905906 progress 0 % (0 MB)
129 18:08:42.924553 progress 5 % (0 MB)
130 18:08:42.951644 progress 10 % (0 MB)
131 18:08:42.981239 progress 15 % (1 MB)
132 18:08:43.005213 progress 20 % (1 MB)
133 18:08:43.028472 progress 25 % (2 MB)
134 18:08:43.052084 progress 30 % (2 MB)
135 18:08:43.078120 progress 35 % (2 MB)
136 18:08:43.102594 progress 40 % (3 MB)
137 18:08:43.125126 progress 45 % (3 MB)
138 18:08:43.149104 progress 50 % (4 MB)
139 18:08:43.173966 progress 55 % (4 MB)
140 18:08:43.198033 progress 60 % (4 MB)
141 18:08:43.221953 progress 65 % (5 MB)
142 18:08:43.248715 progress 70 % (5 MB)
143 18:08:43.272422 progress 75 % (6 MB)
144 18:08:43.297997 progress 80 % (6 MB)
145 18:08:43.322128 progress 85 % (7 MB)
146 18:08:43.347460 progress 90 % (7 MB)
147 18:08:43.372669 progress 95 % (7 MB)
148 18:08:43.399301 progress 100 % (8 MB)
149 18:08:43.403572 8 MB downloaded in 0.50 s (16.37 MB/s)
150 18:08:43.403816 end: 1.5.1 http-download (duration 00:00:01) [common]
152 18:08:43.404084 end: 1.5 download-retry (duration 00:00:01) [common]
153 18:08:43.404178 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 18:08:43.404273 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 18:08:44.944331 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7
156 18:08:44.944530 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 18:08:44.944626 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 18:08:44.944788 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf
159 18:08:44.944913 makedir: /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin
160 18:08:44.945015 makedir: /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/tests
161 18:08:44.945110 makedir: /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/results
162 18:08:44.945207 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-add-keys
163 18:08:44.945343 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-add-sources
164 18:08:44.945470 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-background-process-start
165 18:08:44.945595 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-background-process-stop
166 18:08:44.945718 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-common-functions
167 18:08:44.945840 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-echo-ipv4
168 18:08:44.945963 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-install-packages
169 18:08:44.946085 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-installed-packages
170 18:08:44.946244 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-os-build
171 18:08:44.946366 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-probe-channel
172 18:08:44.946488 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-probe-ip
173 18:08:44.946609 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-target-ip
174 18:08:44.946729 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-target-mac
175 18:08:44.946847 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-target-storage
176 18:08:44.946971 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-case
177 18:08:44.947091 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-event
178 18:08:44.947212 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-feedback
179 18:08:44.947333 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-raise
180 18:08:44.947453 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-reference
181 18:08:44.947573 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-runner
182 18:08:44.947694 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-set
183 18:08:44.947814 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-test-shell
184 18:08:44.947937 Updating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-install-packages (oe)
185 18:08:44.948086 Updating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/bin/lava-installed-packages (oe)
186 18:08:44.948204 Creating /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/environment
187 18:08:44.948300 LAVA metadata
188 18:08:44.948365 - LAVA_JOB_ID=14291485
189 18:08:44.948425 - LAVA_DISPATCHER_IP=192.168.201.1
190 18:08:44.948520 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 18:08:44.948584 skipped lava-vland-overlay
192 18:08:44.948657 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 18:08:44.948734 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 18:08:44.948792 skipped lava-multinode-overlay
195 18:08:44.948861 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 18:08:44.948934 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 18:08:44.949004 Loading test definitions
198 18:08:44.949089 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 18:08:44.949158 Using /lava-14291485 at stage 0
200 18:08:44.949451 uuid=14291485_1.6.2.3.1 testdef=None
201 18:08:44.949537 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 18:08:44.949622 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 18:08:44.950103 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 18:08:44.950426 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 18:08:44.951017 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 18:08:44.951236 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 18:08:44.951807 runner path: /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/0/tests/0_lc-compliance test_uuid 14291485_1.6.2.3.1
210 18:08:44.951959 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 18:08:44.952156 Creating lava-test-runner.conf files
213 18:08:44.952217 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291485/lava-overlay-tvbttgsf/lava-14291485/0 for stage 0
214 18:08:44.952303 - 0_lc-compliance
215 18:08:44.952397 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 18:08:44.952481 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 18:08:44.958308 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 18:08:44.958407 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 18:08:44.958488 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 18:08:44.958569 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 18:08:44.958651 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 18:08:45.123861 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 18:08:45.124310 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 18:08:45.124425 extracting modules file /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7
225 18:08:45.336073 extracting modules file /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291485/extract-overlay-ramdisk-26zv0gtg/ramdisk
226 18:08:45.555220 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 18:08:45.555390 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 18:08:45.555489 [common] Applying overlay to NFS
229 18:08:45.555556 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291485/compress-overlay-llok6kdu/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7
230 18:08:45.562025 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 18:08:45.562132 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 18:08:45.562311 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 18:08:45.562401 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 18:08:45.562481 Building ramdisk /var/lib/lava/dispatcher/tmp/14291485/extract-overlay-ramdisk-26zv0gtg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291485/extract-overlay-ramdisk-26zv0gtg/ramdisk
235 18:08:45.901777 >> 130400 blocks
236 18:08:47.932114 rename /var/lib/lava/dispatcher/tmp/14291485/extract-overlay-ramdisk-26zv0gtg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/ramdisk/ramdisk.cpio.gz
237 18:08:47.932544 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 18:08:47.932675 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 18:08:47.932777 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 18:08:47.932880 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/kernel/Image']
241 18:09:01.006200 Returned 0 in 13 seconds
242 18:09:01.106846 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/kernel/image.itb
243 18:09:01.482404 output: FIT description: Kernel Image image with one or more FDT blobs
244 18:09:01.482766 output: Created: Tue Jun 11 19:09:01 2024
245 18:09:01.482842 output: Image 0 (kernel-1)
246 18:09:01.482907 output: Description:
247 18:09:01.482968 output: Created: Tue Jun 11 19:09:01 2024
248 18:09:01.483029 output: Type: Kernel Image
249 18:09:01.483087 output: Compression: lzma compressed
250 18:09:01.483150 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
251 18:09:01.483208 output: Architecture: AArch64
252 18:09:01.483307 output: OS: Linux
253 18:09:01.483394 output: Load Address: 0x00000000
254 18:09:01.483482 output: Entry Point: 0x00000000
255 18:09:01.483571 output: Hash algo: crc32
256 18:09:01.483627 output: Hash value: 7a9e9d3e
257 18:09:01.483682 output: Image 1 (fdt-1)
258 18:09:01.483736 output: Description: mt8192-asurada-spherion-r0
259 18:09:01.483790 output: Created: Tue Jun 11 19:09:01 2024
260 18:09:01.483844 output: Type: Flat Device Tree
261 18:09:01.483906 output: Compression: uncompressed
262 18:09:01.483961 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 18:09:01.484013 output: Architecture: AArch64
264 18:09:01.484065 output: Hash algo: crc32
265 18:09:01.484117 output: Hash value: 0f8e4d2e
266 18:09:01.484169 output: Image 2 (ramdisk-1)
267 18:09:01.484220 output: Description: unavailable
268 18:09:01.484273 output: Created: Tue Jun 11 19:09:01 2024
269 18:09:01.484325 output: Type: RAMDisk Image
270 18:09:01.484377 output: Compression: Unknown Compression
271 18:09:01.484429 output: Data Size: 18742477 Bytes = 18303.20 KiB = 17.87 MiB
272 18:09:01.484481 output: Architecture: AArch64
273 18:09:01.484532 output: OS: Linux
274 18:09:01.484583 output: Load Address: unavailable
275 18:09:01.484635 output: Entry Point: unavailable
276 18:09:01.484692 output: Hash algo: crc32
277 18:09:01.484745 output: Hash value: da9004d1
278 18:09:01.484796 output: Default Configuration: 'conf-1'
279 18:09:01.484848 output: Configuration 0 (conf-1)
280 18:09:01.484900 output: Description: mt8192-asurada-spherion-r0
281 18:09:01.484951 output: Kernel: kernel-1
282 18:09:01.485003 output: Init Ramdisk: ramdisk-1
283 18:09:01.485054 output: FDT: fdt-1
284 18:09:01.485111 output: Loadables: kernel-1
285 18:09:01.485164 output:
286 18:09:01.485395 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 18:09:01.485491 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 18:09:01.485612 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 18:09:01.485745 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 18:09:01.485846 No LXC device requested
291 18:09:01.485925 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 18:09:01.486014 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 18:09:01.486121 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 18:09:01.486241 Checking files for TFTP limit of 4294967296 bytes.
295 18:09:01.486737 end: 1 tftp-deploy (duration 00:00:23) [common]
296 18:09:01.486842 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 18:09:01.486962 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 18:09:01.487100 substitutions:
299 18:09:01.487165 - {DTB}: 14291485/tftp-deploy-kh0bjebm/dtb/mt8192-asurada-spherion-r0.dtb
300 18:09:01.487234 - {INITRD}: 14291485/tftp-deploy-kh0bjebm/ramdisk/ramdisk.cpio.gz
301 18:09:01.487291 - {KERNEL}: 14291485/tftp-deploy-kh0bjebm/kernel/Image
302 18:09:01.487347 - {LAVA_MAC}: None
303 18:09:01.487436 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7
304 18:09:01.487518 - {NFS_SERVER_IP}: 192.168.201.1
305 18:09:01.487596 - {PRESEED_CONFIG}: None
306 18:09:01.487657 - {PRESEED_LOCAL}: None
307 18:09:01.487712 - {RAMDISK}: 14291485/tftp-deploy-kh0bjebm/ramdisk/ramdisk.cpio.gz
308 18:09:01.487765 - {ROOT_PART}: None
309 18:09:01.487825 - {ROOT}: None
310 18:09:01.487879 - {SERVER_IP}: 192.168.201.1
311 18:09:01.487932 - {TEE}: None
312 18:09:01.487985 Parsed boot commands:
313 18:09:01.488037 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 18:09:01.488223 Parsed boot commands: tftpboot 192.168.201.1 14291485/tftp-deploy-kh0bjebm/kernel/image.itb 14291485/tftp-deploy-kh0bjebm/kernel/cmdline
315 18:09:01.488313 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 18:09:01.488397 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 18:09:01.488485 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 18:09:01.488565 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 18:09:01.488639 Not connected, no need to disconnect.
320 18:09:01.488716 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 18:09:01.488795 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 18:09:01.488864 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 18:09:01.492869 Setting prompt string to ['lava-test: # ']
324 18:09:01.493380 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 18:09:01.493485 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 18:09:01.493632 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 18:09:01.493785 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 18:09:01.493972 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
329 18:09:15.177360 Returned 0 in 13 seconds
330 18:09:15.278099 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 18:09:15.278475 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 18:09:15.278596 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 18:09:15.278719 Setting prompt string to 'Starting depthcharge on Spherion...'
335 18:09:15.278797 Changing prompt to 'Starting depthcharge on Spherion...'
336 18:09:15.278884 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 18:09:15.279317 [Enter `^Ec?' for help]
338 18:09:15.279400
339 18:09:15.279484
340 18:09:15.279565 F0: 102B 0000
341 18:09:15.279646
342 18:09:15.279747 F3: 1001 0000 [0200]
343 18:09:15.279844
344 18:09:15.279941 F3: 1001 0000
345 18:09:15.280037
346 18:09:15.280134 F7: 102D 0000
347 18:09:15.280229
348 18:09:15.280323 F1: 0000 0000
349 18:09:15.280416
350 18:09:15.280509 V0: 0000 0000 [0001]
351 18:09:15.280603
352 18:09:15.280695 00: 0007 8000
353 18:09:15.280793
354 18:09:15.280886 01: 0000 0000
355 18:09:15.280981
356 18:09:15.281073 BP: 0C00 0209 [0000]
357 18:09:15.281165
358 18:09:15.281256 G0: 1182 0000
359 18:09:15.281349
360 18:09:15.281448 EC: 0000 0021 [4000]
361 18:09:15.281537
362 18:09:15.281621 S7: 0000 0000 [0000]
363 18:09:15.281703
364 18:09:15.281786 CC: 0000 0000 [0001]
365 18:09:15.281868
366 18:09:15.281950 T0: 0000 0040 [010F]
367 18:09:15.282033
368 18:09:15.282114 Jump to BL
369 18:09:15.282204
370 18:09:15.282286
371 18:09:15.282368
372 18:09:15.282451 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 18:09:15.282540 ARM64: Exception handlers installed.
374 18:09:15.282623 ARM64: Testing exception
375 18:09:15.282705 ARM64: Done test exception
376 18:09:15.282788 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 18:09:15.282911 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 18:09:15.283002 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 18:09:15.283094 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 18:09:15.283186 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 18:09:15.283277 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 18:09:15.283368 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 18:09:15.283461 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 18:09:15.283554 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 18:09:15.283645 WDT: Last reset was cold boot
386 18:09:15.283737 SPI1(PAD0) initialized at 2873684 Hz
387 18:09:15.283828 SPI5(PAD0) initialized at 992727 Hz
388 18:09:15.283919 VBOOT: Loading verstage.
389 18:09:15.284010 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 18:09:15.284101 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 18:09:15.284193 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 18:09:15.284285 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 18:09:15.284377 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 18:09:15.284469 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 18:09:15.284561 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 18:09:15.284653
397 18:09:15.284743
398 18:09:15.284834 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 18:09:15.284926 ARM64: Exception handlers installed.
400 18:09:15.285017 ARM64: Testing exception
401 18:09:15.285109 ARM64: Done test exception
402 18:09:15.285199 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 18:09:15.285291 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 18:09:15.285383 Probing TPM: . done!
405 18:09:15.285474 TPM ready after 0 ms
406 18:09:15.285565 Connected to device vid:did:rid of 1ae0:0028:00
407 18:09:15.285656 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
408 18:09:15.285749 Initialized TPM device CR50 revision 0
409 18:09:15.285840 tlcl_send_startup: Startup return code is 0
410 18:09:15.285931 TPM: setup succeeded
411 18:09:15.286022 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 18:09:15.286130 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 18:09:15.286243 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 18:09:15.286336 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 18:09:15.286427 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 18:09:15.286518 in-header: 03 07 00 00 08 00 00 00
417 18:09:15.286609 in-data: aa e4 47 04 13 02 00 00
418 18:09:15.286701 Chrome EC: UHEPI supported
419 18:09:15.286791 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 18:09:15.286882 in-header: 03 a9 00 00 08 00 00 00
421 18:09:15.286973 in-data: 84 60 60 08 00 00 00 00
422 18:09:15.287063 Phase 1
423 18:09:15.287153 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 18:09:15.287245 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 18:09:15.287337 VB2:vb2_check_recovery() Recovery was requested manually
426 18:09:15.287429 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 18:09:15.287520 Recovery requested (1009000e)
428 18:09:15.287612 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 18:09:15.287704 tlcl_extend: response is 0
430 18:09:15.287796 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 18:09:15.287888 tlcl_extend: response is 0
432 18:09:15.287980 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 18:09:15.288072 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 18:09:15.288165 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 18:09:15.288256
436 18:09:15.288349
437 18:09:15.288442 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 18:09:15.288534 ARM64: Exception handlers installed.
439 18:09:15.288626 ARM64: Testing exception
440 18:09:15.288718 ARM64: Done test exception
441 18:09:15.288809 pmic_efuse_setting: Set efuses in 11 msecs
442 18:09:15.288901 pmwrap_interface_init: Select PMIF_VLD_RDY
443 18:09:15.288993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 18:09:15.289085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 18:09:15.289387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 18:09:15.289532 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 18:09:15.289665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 18:09:15.289796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 18:09:15.289926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 18:09:15.290056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 18:09:15.290214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 18:09:15.290360 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 18:09:15.290485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 18:09:15.290585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 18:09:15.290671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 18:09:15.290755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 18:09:15.290839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 18:09:15.290922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 18:09:15.291005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 18:09:15.291088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 18:09:15.291170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 18:09:15.291253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 18:09:15.291336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 18:09:15.291418 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 18:09:15.291501 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 18:09:15.291583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 18:09:15.291665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 18:09:15.291747 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 18:09:15.291830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 18:09:15.291912 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 18:09:15.291994 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 18:09:15.292076 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 18:09:15.292159 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 18:09:15.292242 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 18:09:15.292324 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 18:09:15.292406 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 18:09:15.292488 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 18:09:15.292571 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 18:09:15.292653 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 18:09:15.292735 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 18:09:15.292817 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 18:09:15.292912 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 18:09:15.292996 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 18:09:15.293078 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 18:09:15.293160 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 18:09:15.293242 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 18:09:15.293324 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 18:09:15.293406 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 18:09:15.293488 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 18:09:15.293570 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 18:09:15.293653 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 18:09:15.293735 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 18:09:15.293817 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 18:09:15.293900 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
495 18:09:15.293984 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 18:09:15.294067 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 18:09:15.294173 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 18:09:15.294272 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 18:09:15.294355 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 18:09:15.294437 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 18:09:15.294520 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 18:09:15.294591 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6c, sec=0x8
503 18:09:15.294646 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
504 18:09:15.294699 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
505 18:09:15.294752 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 18:09:15.294805 [RTC]rtc_get_frequency_meter,154: input=15, output=834
507 18:09:15.294862 [RTC]rtc_get_frequency_meter,154: input=7, output=708
508 18:09:15.294936 [RTC]rtc_get_frequency_meter,154: input=11, output=772
509 18:09:15.295028 [RTC]rtc_get_frequency_meter,154: input=13, output=802
510 18:09:15.295119 [RTC]rtc_get_frequency_meter,154: input=12, output=786
511 18:09:15.295210 [RTC]rtc_get_frequency_meter,154: input=12, output=786
512 18:09:15.295301 [RTC]rtc_get_frequency_meter,154: input=13, output=803
513 18:09:15.295393 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
514 18:09:15.295483 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
515 18:09:15.295799 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 18:09:15.295897 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 18:09:15.295993 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 18:09:15.296087 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 18:09:15.296180 ADC[4]: Raw value=904509 ID=7
520 18:09:15.296273 ADC[3]: Raw value=213652 ID=1
521 18:09:15.296366 RAM Code: 0x71
522 18:09:15.296458 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 18:09:15.296577 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 18:09:15.296686 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 18:09:15.296799 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 18:09:15.296895 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 18:09:15.296990 in-header: 03 07 00 00 08 00 00 00
528 18:09:15.297084 in-data: aa e4 47 04 13 02 00 00
529 18:09:15.297178 Chrome EC: UHEPI supported
530 18:09:15.297271 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 18:09:15.297365 in-header: 03 a9 00 00 08 00 00 00
532 18:09:15.297458 in-data: 84 60 60 08 00 00 00 00
533 18:09:15.297551 MRC: failed to locate region type 0.
534 18:09:15.297643 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 18:09:15.297735 DRAM-K: Running full calibration
536 18:09:15.297827 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 18:09:15.297919 header.status = 0x0
538 18:09:15.298011 header.version = 0x6 (expected: 0x6)
539 18:09:15.298102 header.size = 0xd00 (expected: 0xd00)
540 18:09:15.298228 header.flags = 0x0
541 18:09:15.298334 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 18:09:15.298426 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 18:09:15.298519 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 18:09:15.298611 dram_init: ddr_geometry: 2
545 18:09:15.298702 [EMI] MDL number = 2
546 18:09:15.298793 [EMI] Get MDL freq = 0
547 18:09:15.298926 dram_init: ddr_type: 0
548 18:09:15.299020 is_discrete_lpddr4: 1
549 18:09:15.299112 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 18:09:15.299203
551 18:09:15.299295
552 18:09:15.299385 [Bian_co] ETT version 0.0.0.1
553 18:09:15.299477 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 18:09:15.299569
555 18:09:15.299659 dramc_set_vcore_voltage set vcore to 650000
556 18:09:15.299750 Read voltage for 800, 4
557 18:09:15.299841 Vio18 = 0
558 18:09:15.299932 Vcore = 650000
559 18:09:15.300022 Vdram = 0
560 18:09:15.300112 Vddq = 0
561 18:09:15.300205 Vmddr = 0
562 18:09:15.300295 dram_init: config_dvfs: 1
563 18:09:15.300386 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 18:09:15.300478 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 18:09:15.300569 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
566 18:09:15.300660 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
567 18:09:15.300752 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
568 18:09:15.300843 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
569 18:09:15.300934 MEM_TYPE=3, freq_sel=18
570 18:09:15.301025 sv_algorithm_assistance_LP4_1600
571 18:09:15.301116 ============ PULL DRAM RESETB DOWN ============
572 18:09:15.301211 ========== PULL DRAM RESETB DOWN end =========
573 18:09:15.301303 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 18:09:15.301394 ===================================
575 18:09:15.301485 LPDDR4 DRAM CONFIGURATION
576 18:09:15.301577 ===================================
577 18:09:15.301668 EX_ROW_EN[0] = 0x0
578 18:09:15.301759 EX_ROW_EN[1] = 0x0
579 18:09:15.301849 LP4Y_EN = 0x0
580 18:09:15.301940 WORK_FSP = 0x0
581 18:09:15.302031 WL = 0x2
582 18:09:15.302122 RL = 0x2
583 18:09:15.302252 BL = 0x2
584 18:09:15.302344 RPST = 0x0
585 18:09:15.302435 RD_PRE = 0x0
586 18:09:15.302525 WR_PRE = 0x1
587 18:09:15.302616 WR_PST = 0x0
588 18:09:15.302706 DBI_WR = 0x0
589 18:09:15.302796 DBI_RD = 0x0
590 18:09:15.302887 OTF = 0x1
591 18:09:15.302980 ===================================
592 18:09:15.303071 ===================================
593 18:09:15.303163 ANA top config
594 18:09:15.303253 ===================================
595 18:09:15.303345 DLL_ASYNC_EN = 0
596 18:09:15.303435 ALL_SLAVE_EN = 1
597 18:09:15.303526 NEW_RANK_MODE = 1
598 18:09:15.303618 DLL_IDLE_MODE = 1
599 18:09:15.303708 LP45_APHY_COMB_EN = 1
600 18:09:15.303798 TX_ODT_DIS = 1
601 18:09:15.303890 NEW_8X_MODE = 1
602 18:09:15.303981 ===================================
603 18:09:15.304072 ===================================
604 18:09:15.304163 data_rate = 1600
605 18:09:15.304254 CKR = 1
606 18:09:15.304344 DQ_P2S_RATIO = 8
607 18:09:15.304434 ===================================
608 18:09:15.304525 CA_P2S_RATIO = 8
609 18:09:15.304616 DQ_CA_OPEN = 0
610 18:09:15.304706 DQ_SEMI_OPEN = 0
611 18:09:15.304799 CA_SEMI_OPEN = 0
612 18:09:15.304890 CA_FULL_RATE = 0
613 18:09:15.304981 DQ_CKDIV4_EN = 1
614 18:09:15.305071 CA_CKDIV4_EN = 1
615 18:09:15.305162 CA_PREDIV_EN = 0
616 18:09:15.305252 PH8_DLY = 0
617 18:09:15.305343 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 18:09:15.305433 DQ_AAMCK_DIV = 4
619 18:09:15.305524 CA_AAMCK_DIV = 4
620 18:09:15.305614 CA_ADMCK_DIV = 4
621 18:09:15.305704 DQ_TRACK_CA_EN = 0
622 18:09:15.305795 CA_PICK = 800
623 18:09:15.305887 CA_MCKIO = 800
624 18:09:15.305977 MCKIO_SEMI = 0
625 18:09:15.306068 PLL_FREQ = 3068
626 18:09:15.306159 DQ_UI_PI_RATIO = 32
627 18:09:15.306289 CA_UI_PI_RATIO = 0
628 18:09:15.306380 ===================================
629 18:09:15.306471 ===================================
630 18:09:15.306563 memory_type:LPDDR4
631 18:09:15.306654 GP_NUM : 10
632 18:09:15.306745 SRAM_EN : 1
633 18:09:15.306835 MD32_EN : 0
634 18:09:15.306926 ===================================
635 18:09:15.307244 [ANA_INIT] >>>>>>>>>>>>>>
636 18:09:15.307384 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 18:09:15.307554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 18:09:15.307686 ===================================
639 18:09:15.307863 data_rate = 1600,PCW = 0X7600
640 18:09:15.308007 ===================================
641 18:09:15.308136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 18:09:15.308266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 18:09:15.308396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 18:09:15.308493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 18:09:15.308579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 18:09:15.308671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 18:09:15.308764 [ANA_INIT] flow start
648 18:09:15.308857 [ANA_INIT] PLL >>>>>>>>
649 18:09:15.308948 [ANA_INIT] PLL <<<<<<<<
650 18:09:15.309040 [ANA_INIT] MIDPI >>>>>>>>
651 18:09:15.309131 [ANA_INIT] MIDPI <<<<<<<<
652 18:09:15.309222 [ANA_INIT] DLL >>>>>>>>
653 18:09:15.309313 [ANA_INIT] flow end
654 18:09:15.309404 ============ LP4 DIFF to SE enter ============
655 18:09:15.309496 ============ LP4 DIFF to SE exit ============
656 18:09:15.309587 [ANA_INIT] <<<<<<<<<<<<<
657 18:09:15.309678 [Flow] Enable top DCM control >>>>>
658 18:09:15.309769 [Flow] Enable top DCM control <<<<<
659 18:09:15.309860 Enable DLL master slave shuffle
660 18:09:15.309951 ==============================================================
661 18:09:15.310042 Gating Mode config
662 18:09:15.310134 ==============================================================
663 18:09:15.310274 Config description:
664 18:09:15.310367 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 18:09:15.310460 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 18:09:15.310553 SELPH_MODE 0: By rank 1: By Phase
667 18:09:15.310645 ==============================================================
668 18:09:15.310737 GAT_TRACK_EN = 1
669 18:09:15.310829 RX_GATING_MODE = 2
670 18:09:15.310920 RX_GATING_TRACK_MODE = 2
671 18:09:15.311011 SELPH_MODE = 1
672 18:09:15.311102 PICG_EARLY_EN = 1
673 18:09:15.311193 VALID_LAT_VALUE = 1
674 18:09:15.311283 ==============================================================
675 18:09:15.311376 Enter into Gating configuration >>>>
676 18:09:15.311467 Exit from Gating configuration <<<<
677 18:09:15.311558 Enter into DVFS_PRE_config >>>>>
678 18:09:15.311649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 18:09:15.311744 Exit from DVFS_PRE_config <<<<<
680 18:09:15.311835 Enter into PICG configuration >>>>
681 18:09:15.311926 Exit from PICG configuration <<<<
682 18:09:15.312017 [RX_INPUT] configuration >>>>>
683 18:09:15.312107 [RX_INPUT] configuration <<<<<
684 18:09:15.312198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 18:09:15.312289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 18:09:15.312379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 18:09:15.312471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 18:09:15.312562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 18:09:15.312653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 18:09:15.312743 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 18:09:15.312834 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 18:09:15.312924 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 18:09:15.313016 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 18:09:15.313107 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 18:09:15.313233 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 18:09:15.313327 ===================================
697 18:09:15.313419 LPDDR4 DRAM CONFIGURATION
698 18:09:15.313510 ===================================
699 18:09:15.313601 EX_ROW_EN[0] = 0x0
700 18:09:15.313691 EX_ROW_EN[1] = 0x0
701 18:09:15.313782 LP4Y_EN = 0x0
702 18:09:15.313873 WORK_FSP = 0x0
703 18:09:15.313964 WL = 0x2
704 18:09:15.314054 RL = 0x2
705 18:09:15.314145 BL = 0x2
706 18:09:15.314271 RPST = 0x0
707 18:09:15.314363 RD_PRE = 0x0
708 18:09:15.314454 WR_PRE = 0x1
709 18:09:15.314545 WR_PST = 0x0
710 18:09:15.314635 DBI_WR = 0x0
711 18:09:15.314726 DBI_RD = 0x0
712 18:09:15.314816 OTF = 0x1
713 18:09:15.314908 ===================================
714 18:09:15.314999 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 18:09:15.315090 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 18:09:15.315181 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 18:09:15.315272 ===================================
718 18:09:15.315363 LPDDR4 DRAM CONFIGURATION
719 18:09:15.315454 ===================================
720 18:09:15.315545 EX_ROW_EN[0] = 0x10
721 18:09:15.315635 EX_ROW_EN[1] = 0x0
722 18:09:15.315725 LP4Y_EN = 0x0
723 18:09:15.315816 WORK_FSP = 0x0
724 18:09:15.315906 WL = 0x2
725 18:09:15.315996 RL = 0x2
726 18:09:15.316086 BL = 0x2
727 18:09:15.316176 RPST = 0x0
728 18:09:15.316266 RD_PRE = 0x0
729 18:09:15.316356 WR_PRE = 0x1
730 18:09:15.316445 WR_PST = 0x0
731 18:09:15.316535 DBI_WR = 0x0
732 18:09:15.316624 DBI_RD = 0x0
733 18:09:15.316714 OTF = 0x1
734 18:09:15.316805 ===================================
735 18:09:15.316896 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 18:09:15.316987 nWR fixed to 40
737 18:09:15.317079 [ModeRegInit_LP4] CH0 RK0
738 18:09:15.317169 [ModeRegInit_LP4] CH0 RK1
739 18:09:15.317260 [ModeRegInit_LP4] CH1 RK0
740 18:09:15.317349 [ModeRegInit_LP4] CH1 RK1
741 18:09:15.317439 match AC timing 13
742 18:09:15.317529 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 18:09:15.317833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 18:09:15.317928 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 18:09:15.318024 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 18:09:15.318118 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 18:09:15.318258 [EMI DOE] emi_dcm 0
748 18:09:15.318351 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 18:09:15.318444 ==
750 18:09:15.318537 Dram Type= 6, Freq= 0, CH_0, rank 0
751 18:09:15.318629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 18:09:15.318722 ==
753 18:09:15.318814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 18:09:15.318907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 18:09:15.318999 [CA 0] Center 37 (7~68) winsize 62
756 18:09:15.319091 [CA 1] Center 37 (7~68) winsize 62
757 18:09:15.319182 [CA 2] Center 34 (4~65) winsize 62
758 18:09:15.319275 [CA 3] Center 34 (4~65) winsize 62
759 18:09:15.319366 [CA 4] Center 33 (3~64) winsize 62
760 18:09:15.319458 [CA 5] Center 33 (3~64) winsize 62
761 18:09:15.319549
762 18:09:15.319640 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 18:09:15.319732
764 18:09:15.319823 [CATrainingPosCal] consider 1 rank data
765 18:09:15.319914 u2DelayCellTimex100 = 270/100 ps
766 18:09:15.320005 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 18:09:15.320098 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
768 18:09:15.320189 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
769 18:09:15.320281 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 18:09:15.320372 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 18:09:15.320463 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 18:09:15.320554
773 18:09:15.320644 CA PerBit enable=1, Macro0, CA PI delay=33
774 18:09:15.320736
775 18:09:15.320826 [CBTSetCACLKResult] CA Dly = 33
776 18:09:15.320917 CS Dly: 6 (0~37)
777 18:09:15.321008 ==
778 18:09:15.321099 Dram Type= 6, Freq= 0, CH_0, rank 1
779 18:09:15.321190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 18:09:15.321282 ==
781 18:09:15.321373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 18:09:15.321465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 18:09:15.321557 [CA 0] Center 37 (6~68) winsize 63
784 18:09:15.321649 [CA 1] Center 37 (7~68) winsize 62
785 18:09:15.321740 [CA 2] Center 34 (4~65) winsize 62
786 18:09:15.321830 [CA 3] Center 34 (4~65) winsize 62
787 18:09:15.321921 [CA 4] Center 33 (3~64) winsize 62
788 18:09:15.322011 [CA 5] Center 33 (3~64) winsize 62
789 18:09:15.322102
790 18:09:15.322236 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 18:09:15.322324
792 18:09:15.322408 [CATrainingPosCal] consider 2 rank data
793 18:09:15.322492 u2DelayCellTimex100 = 270/100 ps
794 18:09:15.322575 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 18:09:15.322657 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
796 18:09:15.322740 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
797 18:09:15.322822 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 18:09:15.322904 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 18:09:15.322986 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 18:09:15.323068
801 18:09:15.323150 CA PerBit enable=1, Macro0, CA PI delay=33
802 18:09:15.323231
803 18:09:15.323313 [CBTSetCACLKResult] CA Dly = 33
804 18:09:15.323395 CS Dly: 6 (0~38)
805 18:09:15.323476
806 18:09:15.323558 ----->DramcWriteLeveling(PI) begin...
807 18:09:15.323645 ==
808 18:09:15.323727 Dram Type= 6, Freq= 0, CH_0, rank 0
809 18:09:15.323810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 18:09:15.323892 ==
811 18:09:15.323975 Write leveling (Byte 0): 34 => 34
812 18:09:15.324057 Write leveling (Byte 1): 28 => 28
813 18:09:15.324139 DramcWriteLeveling(PI) end<-----
814 18:09:15.324221
815 18:09:15.324302 ==
816 18:09:15.324384 Dram Type= 6, Freq= 0, CH_0, rank 0
817 18:09:15.324466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 18:09:15.324548 ==
819 18:09:15.324630 [Gating] SW mode calibration
820 18:09:15.324713 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 18:09:15.324796 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 18:09:15.324879 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 18:09:15.324963 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 18:09:15.325045 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 18:09:15.325128 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 18:09:15.325210 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 18:09:15.325293 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 18:09:15.325375 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 18:09:15.325457 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 18:09:15.325539 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 18:09:15.325622 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 18:09:15.325704 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 18:09:15.325787 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 18:09:15.325869 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 18:09:15.325951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 18:09:15.326034 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 18:09:15.326116 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 18:09:15.326245 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 18:09:15.326328 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
840 18:09:15.326411 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
841 18:09:15.326493 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
842 18:09:15.326575 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 18:09:15.326658 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 18:09:15.326740 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 18:09:15.326823 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 18:09:15.326905 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 18:09:15.326987 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 18:09:15.327070 0 9 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
849 18:09:15.327152 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 18:09:15.327234 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 18:09:15.327527 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 18:09:15.327662 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 18:09:15.327792 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 18:09:15.327920 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 18:09:15.328048 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
856 18:09:15.328175 0 10 8 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 1)
857 18:09:15.328303 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
858 18:09:15.328428 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 18:09:15.328552 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 18:09:15.328661 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 18:09:15.328745 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 18:09:15.328829 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 18:09:15.328912 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
864 18:09:15.328995 0 11 8 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
865 18:09:15.329077 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
866 18:09:15.329160 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 18:09:15.329242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 18:09:15.329325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 18:09:15.329407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 18:09:15.329489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 18:09:15.329571 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
872 18:09:15.329654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 18:09:15.329736 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 18:09:15.329818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 18:09:15.329900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 18:09:15.329983 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 18:09:15.330065 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 18:09:15.330147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 18:09:15.330274 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 18:09:15.330357 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 18:09:15.330439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 18:09:15.330522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 18:09:15.330604 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 18:09:15.330687 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 18:09:15.330769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 18:09:15.330851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 18:09:15.330936 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 18:09:15.330992 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 18:09:15.331045 Total UI for P1: 0, mck2ui 16
890 18:09:15.331100 best dqsien dly found for B0: ( 0, 14, 6)
891 18:09:15.331153 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 18:09:15.331205 Total UI for P1: 0, mck2ui 16
893 18:09:15.331259 best dqsien dly found for B1: ( 0, 14, 8)
894 18:09:15.331312 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
895 18:09:15.331364 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
896 18:09:15.331416
897 18:09:15.331468 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
898 18:09:15.331521 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 18:09:15.331573 [Gating] SW calibration Done
900 18:09:15.331625 ==
901 18:09:15.331677 Dram Type= 6, Freq= 0, CH_0, rank 0
902 18:09:15.331730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 18:09:15.331783 ==
904 18:09:15.331835 RX Vref Scan: 0
905 18:09:15.331887
906 18:09:15.331938 RX Vref 0 -> 0, step: 1
907 18:09:15.331991
908 18:09:15.332042 RX Delay -130 -> 252, step: 16
909 18:09:15.332094 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
910 18:09:15.332146 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
911 18:09:15.332198 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
912 18:09:15.332250 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
913 18:09:15.332302 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
914 18:09:15.332354 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
915 18:09:15.332406 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
916 18:09:15.332458 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
917 18:09:15.332509 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
918 18:09:15.332561 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
919 18:09:15.332613 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
920 18:09:15.332665 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
921 18:09:15.332717 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
922 18:09:15.332768 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
923 18:09:15.332821 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
924 18:09:15.332873 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
925 18:09:15.332924 ==
926 18:09:15.332976 Dram Type= 6, Freq= 0, CH_0, rank 0
927 18:09:15.333029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 18:09:15.333081 ==
929 18:09:15.333133 DQS Delay:
930 18:09:15.333185 DQS0 = 0, DQS1 = 0
931 18:09:15.333237 DQM Delay:
932 18:09:15.333288 DQM0 = 85, DQM1 = 71
933 18:09:15.333340 DQ Delay:
934 18:09:15.333392 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
935 18:09:15.333444 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
936 18:09:15.333496 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
937 18:09:15.333547 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
938 18:09:15.333599
939 18:09:15.333655
940 18:09:15.333707 ==
941 18:09:15.333758 Dram Type= 6, Freq= 0, CH_0, rank 0
942 18:09:15.333811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
943 18:09:15.333863 ==
944 18:09:15.333916
945 18:09:15.333966
946 18:09:15.334017 TX Vref Scan disable
947 18:09:15.334069 == TX Byte 0 ==
948 18:09:15.334120 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
949 18:09:15.334209 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
950 18:09:15.334276 == TX Byte 1 ==
951 18:09:15.334328 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
952 18:09:15.334381 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
953 18:09:15.334433 ==
954 18:09:15.334485 Dram Type= 6, Freq= 0, CH_0, rank 0
955 18:09:15.334537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 18:09:15.334590 ==
957 18:09:15.334641 TX Vref=22, minBit 3, minWin=27, winSum=437
958 18:09:15.334694 TX Vref=24, minBit 3, minWin=27, winSum=444
959 18:09:15.334953 TX Vref=26, minBit 8, minWin=27, winSum=447
960 18:09:15.335016 TX Vref=28, minBit 8, minWin=27, winSum=450
961 18:09:15.335070 TX Vref=30, minBit 10, minWin=27, winSum=451
962 18:09:15.335123 TX Vref=32, minBit 7, minWin=27, winSum=442
963 18:09:15.335176 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 30
964 18:09:15.335229
965 18:09:15.335281 Final TX Range 1 Vref 30
966 18:09:15.335332
967 18:09:15.335384 ==
968 18:09:15.335435 Dram Type= 6, Freq= 0, CH_0, rank 0
969 18:09:15.335487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 18:09:15.335539 ==
971 18:09:15.335591
972 18:09:15.335642
973 18:09:15.335694 TX Vref Scan disable
974 18:09:15.335764 == TX Byte 0 ==
975 18:09:15.335830 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
976 18:09:15.335882 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
977 18:09:15.335934 == TX Byte 1 ==
978 18:09:15.335985 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
979 18:09:15.336037 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
980 18:09:15.336089
981 18:09:15.336141 [DATLAT]
982 18:09:15.336192 Freq=800, CH0 RK0
983 18:09:15.336244
984 18:09:15.336295 DATLAT Default: 0xa
985 18:09:15.336362 0, 0xFFFF, sum = 0
986 18:09:15.336416 1, 0xFFFF, sum = 0
987 18:09:15.336469 2, 0xFFFF, sum = 0
988 18:09:15.336522 3, 0xFFFF, sum = 0
989 18:09:15.336575 4, 0xFFFF, sum = 0
990 18:09:15.336628 5, 0xFFFF, sum = 0
991 18:09:15.336681 6, 0xFFFF, sum = 0
992 18:09:15.336733 7, 0xFFFF, sum = 0
993 18:09:15.336786 8, 0xFFFF, sum = 0
994 18:09:15.336839 9, 0x0, sum = 1
995 18:09:15.336891 10, 0x0, sum = 2
996 18:09:15.336944 11, 0x0, sum = 3
997 18:09:15.336997 12, 0x0, sum = 4
998 18:09:15.337049 best_step = 10
999 18:09:15.337100
1000 18:09:15.337152 ==
1001 18:09:15.337203 Dram Type= 6, Freq= 0, CH_0, rank 0
1002 18:09:15.337256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1003 18:09:15.337308 ==
1004 18:09:15.337360 RX Vref Scan: 1
1005 18:09:15.337412
1006 18:09:15.337463 Set Vref Range= 32 -> 127
1007 18:09:15.337515
1008 18:09:15.337566 RX Vref 32 -> 127, step: 1
1009 18:09:15.337617
1010 18:09:15.337669 RX Delay -111 -> 252, step: 8
1011 18:09:15.337721
1012 18:09:15.337773 Set Vref, RX VrefLevel [Byte0]: 32
1013 18:09:15.337825 [Byte1]: 32
1014 18:09:15.337878
1015 18:09:15.337929 Set Vref, RX VrefLevel [Byte0]: 33
1016 18:09:15.337981 [Byte1]: 33
1017 18:09:15.338034
1018 18:09:15.338090 Set Vref, RX VrefLevel [Byte0]: 34
1019 18:09:15.338142 [Byte1]: 34
1020 18:09:15.338239
1021 18:09:15.338291 Set Vref, RX VrefLevel [Byte0]: 35
1022 18:09:15.338344 [Byte1]: 35
1023 18:09:15.338397
1024 18:09:15.338449 Set Vref, RX VrefLevel [Byte0]: 36
1025 18:09:15.338508 [Byte1]: 36
1026 18:09:15.338563
1027 18:09:15.338615 Set Vref, RX VrefLevel [Byte0]: 37
1028 18:09:15.338668 [Byte1]: 37
1029 18:09:15.338718
1030 18:09:15.338769 Set Vref, RX VrefLevel [Byte0]: 38
1031 18:09:15.338820 [Byte1]: 38
1032 18:09:15.338871
1033 18:09:15.338953 Set Vref, RX VrefLevel [Byte0]: 39
1034 18:09:15.339004 [Byte1]: 39
1035 18:09:15.339055
1036 18:09:15.339106 Set Vref, RX VrefLevel [Byte0]: 40
1037 18:09:15.339157 [Byte1]: 40
1038 18:09:15.339208
1039 18:09:15.339259 Set Vref, RX VrefLevel [Byte0]: 41
1040 18:09:15.339310 [Byte1]: 41
1041 18:09:15.339361
1042 18:09:15.339411 Set Vref, RX VrefLevel [Byte0]: 42
1043 18:09:15.339462 [Byte1]: 42
1044 18:09:15.339513
1045 18:09:15.339563 Set Vref, RX VrefLevel [Byte0]: 43
1046 18:09:15.339614 [Byte1]: 43
1047 18:09:15.339664
1048 18:09:15.339715 Set Vref, RX VrefLevel [Byte0]: 44
1049 18:09:15.339766 [Byte1]: 44
1050 18:09:15.339817
1051 18:09:15.339867 Set Vref, RX VrefLevel [Byte0]: 45
1052 18:09:15.339918 [Byte1]: 45
1053 18:09:15.339969
1054 18:09:15.340020 Set Vref, RX VrefLevel [Byte0]: 46
1055 18:09:15.340070 [Byte1]: 46
1056 18:09:15.340121
1057 18:09:15.340171 Set Vref, RX VrefLevel [Byte0]: 47
1058 18:09:15.340222 [Byte1]: 47
1059 18:09:15.340273
1060 18:09:15.340322 Set Vref, RX VrefLevel [Byte0]: 48
1061 18:09:15.340373 [Byte1]: 48
1062 18:09:15.340424
1063 18:09:15.340475 Set Vref, RX VrefLevel [Byte0]: 49
1064 18:09:15.340526 [Byte1]: 49
1065 18:09:15.340576
1066 18:09:15.340627 Set Vref, RX VrefLevel [Byte0]: 50
1067 18:09:15.340678 [Byte1]: 50
1068 18:09:15.340729
1069 18:09:15.340780 Set Vref, RX VrefLevel [Byte0]: 51
1070 18:09:15.340830 [Byte1]: 51
1071 18:09:15.340881
1072 18:09:15.340932 Set Vref, RX VrefLevel [Byte0]: 52
1073 18:09:15.340982 [Byte1]: 52
1074 18:09:15.341033
1075 18:09:15.341084 Set Vref, RX VrefLevel [Byte0]: 53
1076 18:09:15.341134 [Byte1]: 53
1077 18:09:15.341185
1078 18:09:15.341234 Set Vref, RX VrefLevel [Byte0]: 54
1079 18:09:15.341285 [Byte1]: 54
1080 18:09:15.341336
1081 18:09:15.341386 Set Vref, RX VrefLevel [Byte0]: 55
1082 18:09:15.341437 [Byte1]: 55
1083 18:09:15.341488
1084 18:09:15.341539 Set Vref, RX VrefLevel [Byte0]: 56
1085 18:09:15.341590 [Byte1]: 56
1086 18:09:15.341641
1087 18:09:15.341691 Set Vref, RX VrefLevel [Byte0]: 57
1088 18:09:15.341742 [Byte1]: 57
1089 18:09:15.341793
1090 18:09:15.341843 Set Vref, RX VrefLevel [Byte0]: 58
1091 18:09:15.341893 [Byte1]: 58
1092 18:09:15.341944
1093 18:09:15.341994 Set Vref, RX VrefLevel [Byte0]: 59
1094 18:09:15.342045 [Byte1]: 59
1095 18:09:15.342095
1096 18:09:15.342146 Set Vref, RX VrefLevel [Byte0]: 60
1097 18:09:15.342242 [Byte1]: 60
1098 18:09:15.342294
1099 18:09:15.342345 Set Vref, RX VrefLevel [Byte0]: 61
1100 18:09:15.342396 [Byte1]: 61
1101 18:09:15.342447
1102 18:09:15.342497 Set Vref, RX VrefLevel [Byte0]: 62
1103 18:09:15.342548 [Byte1]: 62
1104 18:09:15.342599
1105 18:09:15.342649 Set Vref, RX VrefLevel [Byte0]: 63
1106 18:09:15.342700 [Byte1]: 63
1107 18:09:15.342751
1108 18:09:15.342802 Set Vref, RX VrefLevel [Byte0]: 64
1109 18:09:15.342853 [Byte1]: 64
1110 18:09:15.342903
1111 18:09:15.342954 Set Vref, RX VrefLevel [Byte0]: 65
1112 18:09:15.343005 [Byte1]: 65
1113 18:09:15.343055
1114 18:09:15.343106 Set Vref, RX VrefLevel [Byte0]: 66
1115 18:09:15.343156 [Byte1]: 66
1116 18:09:15.343207
1117 18:09:15.343257 Set Vref, RX VrefLevel [Byte0]: 67
1118 18:09:15.343323 [Byte1]: 67
1119 18:09:15.343376
1120 18:09:15.343426 Set Vref, RX VrefLevel [Byte0]: 68
1121 18:09:15.343478 [Byte1]: 68
1122 18:09:15.343528
1123 18:09:15.343579 Set Vref, RX VrefLevel [Byte0]: 69
1124 18:09:15.343630 [Byte1]: 69
1125 18:09:15.343681
1126 18:09:15.343732 Set Vref, RX VrefLevel [Byte0]: 70
1127 18:09:15.343991 [Byte1]: 70
1128 18:09:15.344124
1129 18:09:15.344250 Set Vref, RX VrefLevel [Byte0]: 71
1130 18:09:15.344377 [Byte1]: 71
1131 18:09:15.344503
1132 18:09:15.344628 Set Vref, RX VrefLevel [Byte0]: 72
1133 18:09:15.344754 [Byte1]: 72
1134 18:09:15.344879
1135 18:09:15.345003 Set Vref, RX VrefLevel [Byte0]: 73
1136 18:09:15.345099 [Byte1]: 73
1137 18:09:15.345155
1138 18:09:15.345208 Set Vref, RX VrefLevel [Byte0]: 74
1139 18:09:15.345260 [Byte1]: 74
1140 18:09:15.345312
1141 18:09:15.345363 Set Vref, RX VrefLevel [Byte0]: 75
1142 18:09:15.345414 [Byte1]: 75
1143 18:09:15.345464
1144 18:09:15.345515 Set Vref, RX VrefLevel [Byte0]: 76
1145 18:09:15.345567 [Byte1]: 76
1146 18:09:15.345618
1147 18:09:15.345669 Set Vref, RX VrefLevel [Byte0]: 77
1148 18:09:15.345720 [Byte1]: 77
1149 18:09:15.345771
1150 18:09:15.345838 Set Vref, RX VrefLevel [Byte0]: 78
1151 18:09:15.345902 [Byte1]: 78
1152 18:09:15.345953
1153 18:09:15.346004 Set Vref, RX VrefLevel [Byte0]: 79
1154 18:09:15.346055 [Byte1]: 79
1155 18:09:15.346106
1156 18:09:15.346157 Set Vref, RX VrefLevel [Byte0]: 80
1157 18:09:15.346246 [Byte1]: 80
1158 18:09:15.346297
1159 18:09:15.346348 Set Vref, RX VrefLevel [Byte0]: 81
1160 18:09:15.346398 [Byte1]: 81
1161 18:09:15.346449
1162 18:09:15.346514 Set Vref, RX VrefLevel [Byte0]: 82
1163 18:09:15.346579 [Byte1]: 82
1164 18:09:15.346630
1165 18:09:15.346681 Set Vref, RX VrefLevel [Byte0]: 83
1166 18:09:15.346732 [Byte1]: 83
1167 18:09:15.346782
1168 18:09:15.346833 Final RX Vref Byte 0 = 68 to rank0
1169 18:09:15.346884 Final RX Vref Byte 1 = 51 to rank0
1170 18:09:15.346935 Final RX Vref Byte 0 = 68 to rank1
1171 18:09:15.346986 Final RX Vref Byte 1 = 51 to rank1==
1172 18:09:15.347036 Dram Type= 6, Freq= 0, CH_0, rank 0
1173 18:09:15.347088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 18:09:15.347140 ==
1175 18:09:15.347191 DQS Delay:
1176 18:09:15.347242 DQS0 = 0, DQS1 = 0
1177 18:09:15.347294 DQM Delay:
1178 18:09:15.347344 DQM0 = 88, DQM1 = 76
1179 18:09:15.347395 DQ Delay:
1180 18:09:15.347446 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1181 18:09:15.347497 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1182 18:09:15.347548 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1183 18:09:15.347599 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1184 18:09:15.347650
1185 18:09:15.347700
1186 18:09:15.347751 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1187 18:09:15.347803 CH0 RK0: MR19=606, MR18=4325
1188 18:09:15.347854 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1189 18:09:15.347906
1190 18:09:15.347956 ----->DramcWriteLeveling(PI) begin...
1191 18:09:15.348008 ==
1192 18:09:15.348059 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 18:09:15.348110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 18:09:15.348162 ==
1195 18:09:15.348212 Write leveling (Byte 0): 31 => 31
1196 18:09:15.348264 Write leveling (Byte 1): 30 => 30
1197 18:09:15.348315 DramcWriteLeveling(PI) end<-----
1198 18:09:15.348365
1199 18:09:15.348416 ==
1200 18:09:15.348466 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 18:09:15.348517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 18:09:15.348569 ==
1203 18:09:15.348619 [Gating] SW mode calibration
1204 18:09:15.348670 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1205 18:09:15.348722 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1206 18:09:15.348773 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 18:09:15.348825 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 18:09:15.348876 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 18:09:15.348927 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 18:09:15.348978 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 18:09:15.349029 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 18:09:15.349080 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 18:09:15.349130 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 18:09:15.349182 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 18:09:15.349233 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 18:09:15.349284 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 18:09:15.349336 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 18:09:15.349387 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 18:09:15.349438 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 18:09:15.349489 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 18:09:15.349540 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 18:09:15.349591 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 18:09:15.349642 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 18:09:15.349693 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1225 18:09:15.349744 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 18:09:15.349795 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 18:09:15.349846 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 18:09:15.349897 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 18:09:15.349948 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 18:09:15.349999 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 18:09:15.350050 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 18:09:15.350101 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1233 18:09:15.350152 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1234 18:09:15.350237 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 18:09:15.350288 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 18:09:15.350339 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 18:09:15.350390 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 18:09:15.350442 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 18:09:15.350493 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1240 18:09:15.350545 0 10 8 | B1->B0 | 3131 2525 | 1 0 | (1 1) (1 0)
1241 18:09:15.350596 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1242 18:09:15.350647 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 18:09:15.350899 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 18:09:15.350959 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 18:09:15.351012 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 18:09:15.351065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 18:09:15.351116 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 18:09:15.351168 0 11 8 | B1->B0 | 2d2d 3a3a | 0 1 | (0 0) (1 1)
1249 18:09:15.351219 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1250 18:09:15.351271 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 18:09:15.351322 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 18:09:15.351373 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 18:09:15.351424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 18:09:15.351475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 18:09:15.351526 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 18:09:15.351577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 18:09:15.351628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 18:09:15.351679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 18:09:15.351731 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 18:09:15.351782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 18:09:15.351833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 18:09:15.351885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 18:09:15.351936 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 18:09:15.351991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 18:09:15.352066 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 18:09:15.352139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 18:09:15.352210 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 18:09:15.352281 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 18:09:15.352351 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 18:09:15.352441 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 18:09:15.352531 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 18:09:15.352620 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1273 18:09:15.352710 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 18:09:15.352799 Total UI for P1: 0, mck2ui 16
1275 18:09:15.352889 best dqsien dly found for B0: ( 0, 14, 8)
1276 18:09:15.352979 Total UI for P1: 0, mck2ui 16
1277 18:09:15.353069 best dqsien dly found for B1: ( 0, 14, 8)
1278 18:09:15.353158 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1279 18:09:15.353248 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1280 18:09:15.353337
1281 18:09:15.353426 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 18:09:15.353515 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1283 18:09:15.353604 [Gating] SW calibration Done
1284 18:09:15.353693 ==
1285 18:09:15.353782 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 18:09:15.353872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 18:09:15.353962 ==
1288 18:09:15.354051 RX Vref Scan: 0
1289 18:09:15.354140
1290 18:09:15.354276 RX Vref 0 -> 0, step: 1
1291 18:09:15.354366
1292 18:09:15.354455 RX Delay -130 -> 252, step: 16
1293 18:09:15.354545 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1294 18:09:15.354634 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1295 18:09:15.354724 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1296 18:09:15.354814 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1297 18:09:15.354904 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1298 18:09:15.354993 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1299 18:09:15.355083 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1300 18:09:15.355171 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1301 18:09:15.355261 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1302 18:09:15.355351 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1303 18:09:15.355440 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1304 18:09:15.355529 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1305 18:09:15.355619 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1306 18:09:15.355708 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1307 18:09:15.355797 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1308 18:09:15.355886 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1309 18:09:15.355975 ==
1310 18:09:15.356065 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 18:09:15.356155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 18:09:15.356245 ==
1313 18:09:15.356334 DQS Delay:
1314 18:09:15.356423 DQS0 = 0, DQS1 = 0
1315 18:09:15.356513 DQM Delay:
1316 18:09:15.356602 DQM0 = 83, DQM1 = 78
1317 18:09:15.356692 DQ Delay:
1318 18:09:15.356781 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1319 18:09:15.356870 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1320 18:09:15.356960 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1321 18:09:15.357050 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1322 18:09:15.357139
1323 18:09:15.357228
1324 18:09:15.357317 ==
1325 18:09:15.357406 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 18:09:15.357496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 18:09:15.357586 ==
1328 18:09:15.357675
1329 18:09:15.357764
1330 18:09:15.357853 TX Vref Scan disable
1331 18:09:15.357945 == TX Byte 0 ==
1332 18:09:15.358034 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1333 18:09:15.358122 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1334 18:09:15.358252 == TX Byte 1 ==
1335 18:09:15.358345 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1336 18:09:15.358433 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1337 18:09:15.358518 ==
1338 18:09:15.358602 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 18:09:15.358686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 18:09:15.358769 ==
1341 18:09:15.358851 TX Vref=22, minBit 9, minWin=27, winSum=447
1342 18:09:15.358934 TX Vref=24, minBit 3, minWin=27, winSum=448
1343 18:09:15.359016 TX Vref=26, minBit 8, minWin=27, winSum=448
1344 18:09:15.359098 TX Vref=28, minBit 8, minWin=27, winSum=447
1345 18:09:15.359179 TX Vref=30, minBit 9, minWin=27, winSum=449
1346 18:09:15.359260 TX Vref=32, minBit 8, minWin=27, winSum=445
1347 18:09:15.359345 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1348 18:09:15.359428
1349 18:09:15.359508 Final TX Range 1 Vref 30
1350 18:09:15.359589
1351 18:09:15.359669 ==
1352 18:09:15.359750 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 18:09:15.359831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 18:09:15.359912 ==
1355 18:09:15.359992
1356 18:09:15.360071
1357 18:09:15.360153 TX Vref Scan disable
1358 18:09:15.360235 == TX Byte 0 ==
1359 18:09:15.360531 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1360 18:09:15.360625 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1361 18:09:15.360711 == TX Byte 1 ==
1362 18:09:15.360794 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1363 18:09:15.360876 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1364 18:09:15.360958
1365 18:09:15.361040 [DATLAT]
1366 18:09:15.361120 Freq=800, CH0 RK1
1367 18:09:15.361202
1368 18:09:15.361283 DATLAT Default: 0xa
1369 18:09:15.361366 0, 0xFFFF, sum = 0
1370 18:09:15.361449 1, 0xFFFF, sum = 0
1371 18:09:15.361532 2, 0xFFFF, sum = 0
1372 18:09:15.361615 3, 0xFFFF, sum = 0
1373 18:09:15.361697 4, 0xFFFF, sum = 0
1374 18:09:15.361779 5, 0xFFFF, sum = 0
1375 18:09:15.361861 6, 0xFFFF, sum = 0
1376 18:09:15.361942 7, 0xFFFF, sum = 0
1377 18:09:15.362027 8, 0xFFFF, sum = 0
1378 18:09:15.362110 9, 0x0, sum = 1
1379 18:09:15.362234 10, 0x0, sum = 2
1380 18:09:15.362317 11, 0x0, sum = 3
1381 18:09:15.362398 12, 0x0, sum = 4
1382 18:09:15.362479 best_step = 10
1383 18:09:15.362561
1384 18:09:15.362640 ==
1385 18:09:15.362720 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 18:09:15.362801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 18:09:15.362882 ==
1388 18:09:15.362962 RX Vref Scan: 0
1389 18:09:15.363042
1390 18:09:15.363121 RX Vref 0 -> 0, step: 1
1391 18:09:15.363200
1392 18:09:15.363279 RX Delay -95 -> 252, step: 8
1393 18:09:15.363359 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1394 18:09:15.363440 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1395 18:09:15.363521 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1396 18:09:15.363601 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1397 18:09:15.363681 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1398 18:09:15.363760 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1399 18:09:15.363841 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1400 18:09:15.363921 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1401 18:09:15.364027 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1402 18:09:15.364122 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1403 18:09:15.364202 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1404 18:09:15.364282 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1405 18:09:15.364363 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1406 18:09:15.364443 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1407 18:09:15.364523 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1408 18:09:15.364602 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1409 18:09:15.364681 ==
1410 18:09:15.364757 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 18:09:15.364832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 18:09:15.364908 ==
1413 18:09:15.364982 DQS Delay:
1414 18:09:15.365060 DQS0 = 0, DQS1 = 0
1415 18:09:15.365140 DQM Delay:
1416 18:09:15.365222 DQM0 = 85, DQM1 = 76
1417 18:09:15.365302 DQ Delay:
1418 18:09:15.365386 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =76
1419 18:09:15.365469 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1420 18:09:15.365550 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1421 18:09:15.365631 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1422 18:09:15.365712
1423 18:09:15.365791
1424 18:09:15.365870 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
1425 18:09:15.365950 CH0 RK1: MR19=606, MR18=3D05
1426 18:09:15.366030 CH0_RK1: MR19=0x606, MR18=0x3D05, DQSOSC=394, MR23=63, INC=95, DEC=63
1427 18:09:15.366116 [RxdqsGatingPostProcess] freq 800
1428 18:09:15.366248 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 18:09:15.366339 Pre-setting of DQS Precalculation
1430 18:09:15.366433 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1431 18:09:15.366526 ==
1432 18:09:15.366617 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 18:09:15.366714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 18:09:15.366813 ==
1435 18:09:15.366900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 18:09:15.366984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 18:09:15.367066 [CA 0] Center 36 (6~67) winsize 62
1438 18:09:15.367148 [CA 1] Center 36 (6~67) winsize 62
1439 18:09:15.367230 [CA 2] Center 34 (4~65) winsize 62
1440 18:09:15.367311 [CA 3] Center 34 (4~65) winsize 62
1441 18:09:15.367391 [CA 4] Center 34 (4~65) winsize 62
1442 18:09:15.367471 [CA 5] Center 34 (4~65) winsize 62
1443 18:09:15.367551
1444 18:09:15.367631 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1445 18:09:15.367712
1446 18:09:15.367792 [CATrainingPosCal] consider 1 rank data
1447 18:09:15.367872 u2DelayCellTimex100 = 270/100 ps
1448 18:09:15.367952 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 18:09:15.368098 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 18:09:15.368178 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1451 18:09:15.368260 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 18:09:15.368340 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 18:09:15.368420 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 18:09:15.368500
1455 18:09:15.368580 CA PerBit enable=1, Macro0, CA PI delay=34
1456 18:09:15.368659
1457 18:09:15.368738 [CBTSetCACLKResult] CA Dly = 34
1458 18:09:15.368818 CS Dly: 4 (0~35)
1459 18:09:15.368897 ==
1460 18:09:15.368977 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 18:09:15.369057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 18:09:15.369137 ==
1463 18:09:15.369218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 18:09:15.369299 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 18:09:15.369380 [CA 0] Center 36 (6~67) winsize 62
1466 18:09:15.369459 [CA 1] Center 37 (6~68) winsize 63
1467 18:09:15.369539 [CA 2] Center 34 (4~65) winsize 62
1468 18:09:15.369619 [CA 3] Center 34 (3~65) winsize 63
1469 18:09:15.369699 [CA 4] Center 34 (4~65) winsize 62
1470 18:09:15.369779 [CA 5] Center 34 (3~65) winsize 63
1471 18:09:15.369858
1472 18:09:15.369938 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1473 18:09:15.370018
1474 18:09:15.370097 [CATrainingPosCal] consider 2 rank data
1475 18:09:15.370205 u2DelayCellTimex100 = 270/100 ps
1476 18:09:15.370301 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 18:09:15.370381 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 18:09:15.370462 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 18:09:15.370542 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 18:09:15.370622 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 18:09:15.370702 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 18:09:15.370781
1483 18:09:15.370861 CA PerBit enable=1, Macro0, CA PI delay=34
1484 18:09:15.370940
1485 18:09:15.371020 [CBTSetCACLKResult] CA Dly = 34
1486 18:09:15.371099 CS Dly: 5 (0~38)
1487 18:09:15.371179
1488 18:09:15.371258 ----->DramcWriteLeveling(PI) begin...
1489 18:09:15.371339 ==
1490 18:09:15.371419 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 18:09:15.371710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 18:09:15.371798 ==
1493 18:09:15.371879 Write leveling (Byte 0): 24 => 24
1494 18:09:15.371960 Write leveling (Byte 1): 28 => 28
1495 18:09:15.372043 DramcWriteLeveling(PI) end<-----
1496 18:09:15.372123
1497 18:09:15.372202 ==
1498 18:09:15.372282 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 18:09:15.372363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 18:09:15.372443 ==
1501 18:09:15.372523 [Gating] SW mode calibration
1502 18:09:15.372604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 18:09:15.372686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 18:09:15.372767 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 18:09:15.372848 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1506 18:09:15.372928 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1507 18:09:15.373009 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 18:09:15.373089 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 18:09:15.373169 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 18:09:15.373249 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 18:09:15.373329 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 18:09:15.373410 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 18:09:15.373490 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 18:09:15.373570 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 18:09:15.373650 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 18:09:15.373730 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 18:09:15.373811 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 18:09:15.373891 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 18:09:15.373971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 18:09:15.374091 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1521 18:09:15.374195 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1522 18:09:15.374286 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 18:09:15.374367 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 18:09:15.374448 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 18:09:15.374531 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 18:09:15.374596 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 18:09:15.374649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 18:09:15.374701 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 18:09:15.374752 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 18:09:15.374804 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (1 1)
1531 18:09:15.374855 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 18:09:15.374906 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 18:09:15.374962 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 18:09:15.375034 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 18:09:15.375088 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 18:09:15.375139 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1537 18:09:15.375197 0 10 4 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 0)
1538 18:09:15.375270 0 10 8 | B1->B0 | 2828 2525 | 0 1 | (0 0) (1 0)
1539 18:09:15.375324 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 18:09:15.375376 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 18:09:15.375426 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 18:09:15.375478 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 18:09:15.375529 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 18:09:15.375580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 18:09:15.375631 0 11 4 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
1546 18:09:15.375681 0 11 8 | B1->B0 | 3939 3d3d | 1 0 | (0 0) (0 0)
1547 18:09:15.375732 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 18:09:15.375783 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 18:09:15.375834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 18:09:15.375884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 18:09:15.375935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 18:09:15.375991 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 18:09:15.376107 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1554 18:09:15.376302 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1555 18:09:15.376382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 18:09:15.376436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 18:09:15.376489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 18:09:15.376571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 18:09:15.376623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 18:09:15.376674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 18:09:15.376725 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 18:09:15.376813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 18:09:15.376896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 18:09:15.376977 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 18:09:15.377058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 18:09:15.377138 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 18:09:15.377218 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 18:09:15.377299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1569 18:09:15.377379 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1570 18:09:15.377459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 18:09:15.377539 Total UI for P1: 0, mck2ui 16
1572 18:09:15.377620 best dqsien dly found for B0: ( 0, 14, 2)
1573 18:09:15.377701 Total UI for P1: 0, mck2ui 16
1574 18:09:15.377781 best dqsien dly found for B1: ( 0, 14, 6)
1575 18:09:15.377862 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1576 18:09:15.377947 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1577 18:09:15.378028
1578 18:09:15.378109 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1579 18:09:15.378443 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1580 18:09:15.378505 [Gating] SW calibration Done
1581 18:09:15.378559 ==
1582 18:09:15.378611 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 18:09:15.378663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 18:09:15.378715 ==
1585 18:09:15.378767 RX Vref Scan: 0
1586 18:09:15.378819
1587 18:09:15.378887 RX Vref 0 -> 0, step: 1
1588 18:09:15.378952
1589 18:09:15.379003 RX Delay -130 -> 252, step: 16
1590 18:09:15.379054 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1591 18:09:15.379105 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1592 18:09:15.379156 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1593 18:09:15.379212 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1594 18:09:15.379287 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1595 18:09:15.379340 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1596 18:09:15.379392 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1597 18:09:15.379444 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1598 18:09:15.379495 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1599 18:09:15.379546 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1600 18:09:15.379597 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1601 18:09:15.379648 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1602 18:09:15.379699 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1603 18:09:15.379749 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1604 18:09:15.379800 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1605 18:09:15.379851 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1606 18:09:15.379902 ==
1607 18:09:15.379953 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 18:09:15.380005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 18:09:15.380056 ==
1610 18:09:15.380107 DQS Delay:
1611 18:09:15.380158 DQS0 = 0, DQS1 = 0
1612 18:09:15.380220 DQM Delay:
1613 18:09:15.380274 DQM0 = 88, DQM1 = 78
1614 18:09:15.380325 DQ Delay:
1615 18:09:15.380376 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1616 18:09:15.380427 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1617 18:09:15.380479 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1618 18:09:15.380530 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1619 18:09:15.380581
1620 18:09:15.380632
1621 18:09:15.380682 ==
1622 18:09:15.380732 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 18:09:15.380784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 18:09:15.380835 ==
1625 18:09:15.380886
1626 18:09:15.380958
1627 18:09:15.381022 TX Vref Scan disable
1628 18:09:15.381073 == TX Byte 0 ==
1629 18:09:15.381124 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1630 18:09:15.381199 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1631 18:09:15.381280 == TX Byte 1 ==
1632 18:09:15.381361 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1633 18:09:15.381442 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1634 18:09:15.381521 ==
1635 18:09:15.381600 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 18:09:15.381655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 18:09:15.381707 ==
1638 18:09:15.381759 TX Vref=22, minBit 13, minWin=26, winSum=437
1639 18:09:15.381810 TX Vref=24, minBit 0, minWin=27, winSum=443
1640 18:09:15.381861 TX Vref=26, minBit 6, minWin=27, winSum=446
1641 18:09:15.381913 TX Vref=28, minBit 1, minWin=27, winSum=444
1642 18:09:15.381964 TX Vref=30, minBit 0, minWin=27, winSum=442
1643 18:09:15.382014 TX Vref=32, minBit 0, minWin=27, winSum=439
1644 18:09:15.382065 [TxChooseVref] Worse bit 6, Min win 27, Win sum 446, Final Vref 26
1645 18:09:15.382117
1646 18:09:15.382199 Final TX Range 1 Vref 26
1647 18:09:15.382266
1648 18:09:15.382317 ==
1649 18:09:15.382368 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 18:09:15.382418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 18:09:15.382470 ==
1652 18:09:15.382520
1653 18:09:15.382570
1654 18:09:15.382621 TX Vref Scan disable
1655 18:09:15.382672 == TX Byte 0 ==
1656 18:09:15.382723 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1657 18:09:15.382774 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1658 18:09:15.382825 == TX Byte 1 ==
1659 18:09:15.382876 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1660 18:09:15.382927 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1661 18:09:15.382977
1662 18:09:15.383028 [DATLAT]
1663 18:09:15.383079 Freq=800, CH1 RK0
1664 18:09:15.383129
1665 18:09:15.383179 DATLAT Default: 0xa
1666 18:09:15.383230 0, 0xFFFF, sum = 0
1667 18:09:15.383282 1, 0xFFFF, sum = 0
1668 18:09:15.383335 2, 0xFFFF, sum = 0
1669 18:09:15.383386 3, 0xFFFF, sum = 0
1670 18:09:15.383437 4, 0xFFFF, sum = 0
1671 18:09:15.383489 5, 0xFFFF, sum = 0
1672 18:09:15.383540 6, 0xFFFF, sum = 0
1673 18:09:15.383591 7, 0xFFFF, sum = 0
1674 18:09:15.383643 8, 0xFFFF, sum = 0
1675 18:09:15.383694 9, 0x0, sum = 1
1676 18:09:15.383745 10, 0x0, sum = 2
1677 18:09:15.383797 11, 0x0, sum = 3
1678 18:09:15.383849 12, 0x0, sum = 4
1679 18:09:15.383901 best_step = 10
1680 18:09:15.383951
1681 18:09:15.384002 ==
1682 18:09:15.384052 Dram Type= 6, Freq= 0, CH_1, rank 0
1683 18:09:15.384103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1684 18:09:15.384154 ==
1685 18:09:15.384204 RX Vref Scan: 1
1686 18:09:15.384255
1687 18:09:15.384306 Set Vref Range= 32 -> 127
1688 18:09:15.384357
1689 18:09:15.384407 RX Vref 32 -> 127, step: 1
1690 18:09:15.384458
1691 18:09:15.384508 RX Delay -95 -> 252, step: 8
1692 18:09:15.384559
1693 18:09:15.384609 Set Vref, RX VrefLevel [Byte0]: 32
1694 18:09:15.384660 [Byte1]: 32
1695 18:09:15.384710
1696 18:09:15.384760 Set Vref, RX VrefLevel [Byte0]: 33
1697 18:09:15.384812 [Byte1]: 33
1698 18:09:15.384862
1699 18:09:15.384912 Set Vref, RX VrefLevel [Byte0]: 34
1700 18:09:15.384963 [Byte1]: 34
1701 18:09:15.385013
1702 18:09:15.385063 Set Vref, RX VrefLevel [Byte0]: 35
1703 18:09:15.385114 [Byte1]: 35
1704 18:09:15.385164
1705 18:09:15.385215 Set Vref, RX VrefLevel [Byte0]: 36
1706 18:09:15.385265 [Byte1]: 36
1707 18:09:15.385316
1708 18:09:15.385366 Set Vref, RX VrefLevel [Byte0]: 37
1709 18:09:15.385417 [Byte1]: 37
1710 18:09:15.385468
1711 18:09:15.385518 Set Vref, RX VrefLevel [Byte0]: 38
1712 18:09:15.385569 [Byte1]: 38
1713 18:09:15.385619
1714 18:09:15.385684 Set Vref, RX VrefLevel [Byte0]: 39
1715 18:09:15.385739 [Byte1]: 39
1716 18:09:15.385790
1717 18:09:15.385841 Set Vref, RX VrefLevel [Byte0]: 40
1718 18:09:15.385892 [Byte1]: 40
1719 18:09:15.385942
1720 18:09:15.385992 Set Vref, RX VrefLevel [Byte0]: 41
1721 18:09:15.386043 [Byte1]: 41
1722 18:09:15.386094
1723 18:09:15.386144 Set Vref, RX VrefLevel [Byte0]: 42
1724 18:09:15.386244 [Byte1]: 42
1725 18:09:15.386296
1726 18:09:15.386346 Set Vref, RX VrefLevel [Byte0]: 43
1727 18:09:15.386397 [Byte1]: 43
1728 18:09:15.386448
1729 18:09:15.386498 Set Vref, RX VrefLevel [Byte0]: 44
1730 18:09:15.386548 [Byte1]: 44
1731 18:09:15.386599
1732 18:09:15.386650 Set Vref, RX VrefLevel [Byte0]: 45
1733 18:09:15.386700 [Byte1]: 45
1734 18:09:15.386751
1735 18:09:15.387009 Set Vref, RX VrefLevel [Byte0]: 46
1736 18:09:15.387109 [Byte1]: 46
1737 18:09:15.387161
1738 18:09:15.387213 Set Vref, RX VrefLevel [Byte0]: 47
1739 18:09:15.387265 [Byte1]: 47
1740 18:09:15.387316
1741 18:09:15.387366 Set Vref, RX VrefLevel [Byte0]: 48
1742 18:09:15.387417 [Byte1]: 48
1743 18:09:15.387468
1744 18:09:15.387519 Set Vref, RX VrefLevel [Byte0]: 49
1745 18:09:15.387569 [Byte1]: 49
1746 18:09:15.387619
1747 18:09:15.387670 Set Vref, RX VrefLevel [Byte0]: 50
1748 18:09:15.387721 [Byte1]: 50
1749 18:09:15.387772
1750 18:09:15.387822 Set Vref, RX VrefLevel [Byte0]: 51
1751 18:09:15.387873 [Byte1]: 51
1752 18:09:15.387923
1753 18:09:15.387974 Set Vref, RX VrefLevel [Byte0]: 52
1754 18:09:15.388025 [Byte1]: 52
1755 18:09:15.388075
1756 18:09:15.388125 Set Vref, RX VrefLevel [Byte0]: 53
1757 18:09:15.388175 [Byte1]: 53
1758 18:09:15.388226
1759 18:09:15.388276 Set Vref, RX VrefLevel [Byte0]: 54
1760 18:09:15.388326 [Byte1]: 54
1761 18:09:15.388376
1762 18:09:15.388426 Set Vref, RX VrefLevel [Byte0]: 55
1763 18:09:15.388476 [Byte1]: 55
1764 18:09:15.388527
1765 18:09:15.388578 Set Vref, RX VrefLevel [Byte0]: 56
1766 18:09:15.388628 [Byte1]: 56
1767 18:09:15.388679
1768 18:09:15.388729 Set Vref, RX VrefLevel [Byte0]: 57
1769 18:09:15.388779 [Byte1]: 57
1770 18:09:15.388829
1771 18:09:15.388879 Set Vref, RX VrefLevel [Byte0]: 58
1772 18:09:15.388930 [Byte1]: 58
1773 18:09:15.388980
1774 18:09:15.389030 Set Vref, RX VrefLevel [Byte0]: 59
1775 18:09:15.389081 [Byte1]: 59
1776 18:09:15.389131
1777 18:09:15.389181 Set Vref, RX VrefLevel [Byte0]: 60
1778 18:09:15.389232 [Byte1]: 60
1779 18:09:15.389282
1780 18:09:15.389333 Set Vref, RX VrefLevel [Byte0]: 61
1781 18:09:15.389383 [Byte1]: 61
1782 18:09:15.389434
1783 18:09:15.389484 Set Vref, RX VrefLevel [Byte0]: 62
1784 18:09:15.389534 [Byte1]: 62
1785 18:09:15.389584
1786 18:09:15.389634 Set Vref, RX VrefLevel [Byte0]: 63
1787 18:09:15.389685 [Byte1]: 63
1788 18:09:15.389735
1789 18:09:15.389786 Set Vref, RX VrefLevel [Byte0]: 64
1790 18:09:15.389836 [Byte1]: 64
1791 18:09:15.389887
1792 18:09:15.389937 Set Vref, RX VrefLevel [Byte0]: 65
1793 18:09:15.389988 [Byte1]: 65
1794 18:09:15.390038
1795 18:09:15.390088 Set Vref, RX VrefLevel [Byte0]: 66
1796 18:09:15.390138 [Byte1]: 66
1797 18:09:15.390229
1798 18:09:15.390294 Set Vref, RX VrefLevel [Byte0]: 67
1799 18:09:15.390345 [Byte1]: 67
1800 18:09:15.390395
1801 18:09:15.390446 Set Vref, RX VrefLevel [Byte0]: 68
1802 18:09:15.390496 [Byte1]: 68
1803 18:09:15.390547
1804 18:09:15.390597 Set Vref, RX VrefLevel [Byte0]: 69
1805 18:09:15.390648 [Byte1]: 69
1806 18:09:15.390699
1807 18:09:15.390750 Set Vref, RX VrefLevel [Byte0]: 70
1808 18:09:15.390800 [Byte1]: 70
1809 18:09:15.390851
1810 18:09:15.390901 Set Vref, RX VrefLevel [Byte0]: 71
1811 18:09:15.390951 [Byte1]: 71
1812 18:09:15.391002
1813 18:09:15.391052 Set Vref, RX VrefLevel [Byte0]: 72
1814 18:09:15.391102 [Byte1]: 72
1815 18:09:15.391153
1816 18:09:15.391203 Set Vref, RX VrefLevel [Byte0]: 73
1817 18:09:15.391253 [Byte1]: 73
1818 18:09:15.391303
1819 18:09:15.391354 Set Vref, RX VrefLevel [Byte0]: 74
1820 18:09:15.391404 [Byte1]: 74
1821 18:09:15.391453
1822 18:09:15.391504 Final RX Vref Byte 0 = 55 to rank0
1823 18:09:15.391555 Final RX Vref Byte 1 = 63 to rank0
1824 18:09:15.391605 Final RX Vref Byte 0 = 55 to rank1
1825 18:09:15.391655 Final RX Vref Byte 1 = 63 to rank1==
1826 18:09:15.391706 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 18:09:15.391757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 18:09:15.391808 ==
1829 18:09:15.391859 DQS Delay:
1830 18:09:15.391909 DQS0 = 0, DQS1 = 0
1831 18:09:15.391960 DQM Delay:
1832 18:09:15.392010 DQM0 = 86, DQM1 = 79
1833 18:09:15.392061 DQ Delay:
1834 18:09:15.392111 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1835 18:09:15.392162 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1836 18:09:15.392212 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1837 18:09:15.392262 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1838 18:09:15.392313
1839 18:09:15.392362
1840 18:09:15.392412 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1841 18:09:15.392464 CH1 RK0: MR19=606, MR18=2B17
1842 18:09:15.392514 CH1_RK0: MR19=0x606, MR18=0x2B17, DQSOSC=398, MR23=63, INC=93, DEC=62
1843 18:09:15.392565
1844 18:09:15.392615 ----->DramcWriteLeveling(PI) begin...
1845 18:09:15.392667 ==
1846 18:09:15.392718 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 18:09:15.392770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 18:09:15.392822 ==
1849 18:09:15.392873 Write leveling (Byte 0): 30 => 30
1850 18:09:15.392923 Write leveling (Byte 1): 31 => 31
1851 18:09:15.392974 DramcWriteLeveling(PI) end<-----
1852 18:09:15.393023
1853 18:09:15.393074 ==
1854 18:09:15.393125 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 18:09:15.393176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 18:09:15.393227 ==
1857 18:09:15.393277 [Gating] SW mode calibration
1858 18:09:15.393328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 18:09:15.393380 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 18:09:15.393431 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 18:09:15.393481 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1862 18:09:15.393533 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 18:09:15.393583 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 18:09:15.393634 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 18:09:15.393684 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 18:09:15.393735 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 18:09:15.393785 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 18:09:15.393836 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 18:09:15.393886 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 18:09:15.393937 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 18:09:15.393987 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 18:09:15.394037 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 18:09:15.394088 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 18:09:15.394340 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 18:09:15.394399 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 18:09:15.394452 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 18:09:15.394503 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1878 18:09:15.394555 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 18:09:15.394606 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 18:09:15.394657 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 18:09:15.394707 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 18:09:15.394759 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 18:09:15.394810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 18:09:15.394861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 18:09:15.394912 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 18:09:15.394962 0 9 8 | B1->B0 | 3030 2929 | 1 0 | (1 1) (0 0)
1887 18:09:15.395012 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 18:09:15.395063 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 18:09:15.395114 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 18:09:15.395164 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 18:09:15.395215 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 18:09:15.395265 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 18:09:15.395316 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1894 18:09:15.395367 0 10 8 | B1->B0 | 2626 2d2d | 1 1 | (1 0) (1 0)
1895 18:09:15.395417 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 18:09:15.395468 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 18:09:15.395518 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 18:09:15.395569 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 18:09:15.395619 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 18:09:15.395670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 18:09:15.395721 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1902 18:09:15.395771 0 11 8 | B1->B0 | 4040 3b3b | 0 1 | (0 0) (0 0)
1903 18:09:15.395822 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1904 18:09:15.395873 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 18:09:15.395923 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 18:09:15.395974 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 18:09:15.396025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 18:09:15.396076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 18:09:15.396126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1910 18:09:15.396176 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1911 18:09:15.396226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 18:09:15.396277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 18:09:15.396327 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 18:09:15.396378 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 18:09:15.396429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 18:09:15.396479 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 18:09:15.396530 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 18:09:15.396581 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 18:09:15.396632 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 18:09:15.396682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 18:09:15.396740 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 18:09:15.396854 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 18:09:15.396950 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 18:09:15.397004 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 18:09:15.397055 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1926 18:09:15.397106 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 18:09:15.397158 Total UI for P1: 0, mck2ui 16
1928 18:09:15.397209 best dqsien dly found for B0: ( 0, 14, 6)
1929 18:09:15.397261 Total UI for P1: 0, mck2ui 16
1930 18:09:15.397312 best dqsien dly found for B1: ( 0, 14, 4)
1931 18:09:15.397363 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1932 18:09:15.397414 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1933 18:09:15.397465
1934 18:09:15.397517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1935 18:09:15.397568 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1936 18:09:15.397619 [Gating] SW calibration Done
1937 18:09:15.397670 ==
1938 18:09:15.397721 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 18:09:15.397772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 18:09:15.397824 ==
1941 18:09:15.397874 RX Vref Scan: 0
1942 18:09:15.397925
1943 18:09:15.397976 RX Vref 0 -> 0, step: 1
1944 18:09:15.398026
1945 18:09:15.398077 RX Delay -130 -> 252, step: 16
1946 18:09:15.398128 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1947 18:09:15.398219 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1948 18:09:15.398272 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1949 18:09:15.398322 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1950 18:09:15.398373 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1951 18:09:15.398424 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1952 18:09:15.535608 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1953 18:09:15.535803 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1954 18:09:15.535922 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1955 18:09:15.536024 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1956 18:09:15.536123 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1957 18:09:15.536221 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1958 18:09:15.536318 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1959 18:09:15.536414 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1960 18:09:15.536510 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1961 18:09:15.536606 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1962 18:09:15.536703 ==
1963 18:09:15.536798 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 18:09:15.536894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 18:09:15.536990 ==
1966 18:09:15.537084 DQS Delay:
1967 18:09:15.537179 DQS0 = 0, DQS1 = 0
1968 18:09:15.537273 DQM Delay:
1969 18:09:15.537595 DQM0 = 86, DQM1 = 78
1970 18:09:15.537701 DQ Delay:
1971 18:09:15.537799 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1972 18:09:15.537895 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1973 18:09:15.537990 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1974 18:09:15.538084 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1975 18:09:15.538206
1976 18:09:15.538315
1977 18:09:15.538408 ==
1978 18:09:15.538502 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 18:09:15.538595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 18:09:15.538690 ==
1981 18:09:15.538783
1982 18:09:15.538874
1983 18:09:15.538967 TX Vref Scan disable
1984 18:09:15.539060 == TX Byte 0 ==
1985 18:09:15.539153 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1986 18:09:15.539247 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1987 18:09:15.539341 == TX Byte 1 ==
1988 18:09:15.539433 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1989 18:09:15.539526 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1990 18:09:15.539618 ==
1991 18:09:15.539711 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 18:09:15.539804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 18:09:15.539898 ==
1994 18:09:15.539992 TX Vref=22, minBit 8, minWin=26, winSum=447
1995 18:09:15.540086 TX Vref=24, minBit 13, minWin=27, winSum=450
1996 18:09:15.540179 TX Vref=26, minBit 13, minWin=27, winSum=450
1997 18:09:15.540273 TX Vref=28, minBit 8, minWin=27, winSum=452
1998 18:09:15.540367 TX Vref=30, minBit 8, minWin=27, winSum=452
1999 18:09:15.540460 TX Vref=32, minBit 8, minWin=27, winSum=451
2000 18:09:15.540553 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 28
2001 18:09:15.540646
2002 18:09:15.540738 Final TX Range 1 Vref 28
2003 18:09:15.540830
2004 18:09:15.540922 ==
2005 18:09:15.541015 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 18:09:15.541107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 18:09:15.541201 ==
2008 18:09:15.541293
2009 18:09:15.541385
2010 18:09:15.541475 TX Vref Scan disable
2011 18:09:15.541568 == TX Byte 0 ==
2012 18:09:15.541660 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2013 18:09:15.541752 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2014 18:09:15.541845 == TX Byte 1 ==
2015 18:09:15.541936 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2016 18:09:15.542032 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2017 18:09:15.542124
2018 18:09:15.542271 [DATLAT]
2019 18:09:15.542364 Freq=800, CH1 RK1
2020 18:09:15.542458
2021 18:09:15.542549 DATLAT Default: 0xa
2022 18:09:15.542641 0, 0xFFFF, sum = 0
2023 18:09:15.542736 1, 0xFFFF, sum = 0
2024 18:09:15.542854 2, 0xFFFF, sum = 0
2025 18:09:15.542962 3, 0xFFFF, sum = 0
2026 18:09:15.543055 4, 0xFFFF, sum = 0
2027 18:09:15.543149 5, 0xFFFF, sum = 0
2028 18:09:15.543242 6, 0xFFFF, sum = 0
2029 18:09:15.543336 7, 0xFFFF, sum = 0
2030 18:09:15.543429 8, 0xFFFF, sum = 0
2031 18:09:15.543524 9, 0x0, sum = 1
2032 18:09:15.543619 10, 0x0, sum = 2
2033 18:09:15.543713 11, 0x0, sum = 3
2034 18:09:15.543807 12, 0x0, sum = 4
2035 18:09:15.543901 best_step = 10
2036 18:09:15.543993
2037 18:09:15.544085 ==
2038 18:09:15.544176 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 18:09:15.544268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 18:09:15.544361 ==
2041 18:09:15.544452 RX Vref Scan: 0
2042 18:09:15.544544
2043 18:09:15.544635 RX Vref 0 -> 0, step: 1
2044 18:09:15.544728
2045 18:09:15.544819 RX Delay -95 -> 252, step: 8
2046 18:09:15.544911 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
2047 18:09:15.545005 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2048 18:09:15.545097 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2049 18:09:15.545188 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2050 18:09:15.545280 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2051 18:09:15.545371 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2052 18:09:15.545462 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2053 18:09:15.545554 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2054 18:09:15.545647 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2055 18:09:15.545738 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2056 18:09:15.545830 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2057 18:09:15.545921 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2058 18:09:15.546013 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2059 18:09:15.546104 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2060 18:09:15.546232 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2061 18:09:15.546323 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2062 18:09:15.546415 ==
2063 18:09:15.546506 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 18:09:15.546599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 18:09:15.546691 ==
2066 18:09:15.546782 DQS Delay:
2067 18:09:15.546873 DQS0 = 0, DQS1 = 0
2068 18:09:15.546964 DQM Delay:
2069 18:09:15.547046 DQM0 = 87, DQM1 = 78
2070 18:09:15.547119 DQ Delay:
2071 18:09:15.547191 DQ0 =88, DQ1 =80, DQ2 =80, DQ3 =84
2072 18:09:15.547263 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2073 18:09:15.547334 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2074 18:09:15.547424 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2075 18:09:15.547515
2076 18:09:15.547605
2077 18:09:15.547695 [DQSOSCAuto] RK1, (LSB)MR18= 0x110b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2078 18:09:15.547786 CH1 RK1: MR19=606, MR18=110B
2079 18:09:15.547877 CH1_RK1: MR19=0x606, MR18=0x110B, DQSOSC=405, MR23=63, INC=90, DEC=60
2080 18:09:15.547967 [RxdqsGatingPostProcess] freq 800
2081 18:09:15.548057 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 18:09:15.548146 Pre-setting of DQS Precalculation
2083 18:09:15.548236 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 18:09:15.548326 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 18:09:15.548416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 18:09:15.548506
2087 18:09:15.548595
2088 18:09:15.548684 [Calibration Summary] 1600 Mbps
2089 18:09:15.548774 CH 0, Rank 0
2090 18:09:15.548863 SW Impedance : PASS
2091 18:09:15.548952 DUTY Scan : NO K
2092 18:09:15.549041 ZQ Calibration : PASS
2093 18:09:15.549130 Jitter Meter : NO K
2094 18:09:15.549219 CBT Training : PASS
2095 18:09:15.549307 Write leveling : PASS
2096 18:09:15.549396 RX DQS gating : PASS
2097 18:09:15.549485 RX DQ/DQS(RDDQC) : PASS
2098 18:09:15.549573 TX DQ/DQS : PASS
2099 18:09:15.549663 RX DATLAT : PASS
2100 18:09:15.549751 RX DQ/DQS(Engine): PASS
2101 18:09:15.549840 TX OE : NO K
2102 18:09:15.549930 All Pass.
2103 18:09:15.550019
2104 18:09:15.550108 CH 0, Rank 1
2105 18:09:15.550242 SW Impedance : PASS
2106 18:09:15.550332 DUTY Scan : NO K
2107 18:09:15.550422 ZQ Calibration : PASS
2108 18:09:15.550512 Jitter Meter : NO K
2109 18:09:15.550601 CBT Training : PASS
2110 18:09:15.550690 Write leveling : PASS
2111 18:09:15.550778 RX DQS gating : PASS
2112 18:09:15.550867 RX DQ/DQS(RDDQC) : PASS
2113 18:09:15.550956 TX DQ/DQS : PASS
2114 18:09:15.551045 RX DATLAT : PASS
2115 18:09:15.551351 RX DQ/DQS(Engine): PASS
2116 18:09:15.551443 TX OE : NO K
2117 18:09:15.551537 All Pass.
2118 18:09:15.551629
2119 18:09:15.551719 CH 1, Rank 0
2120 18:09:15.551809 SW Impedance : PASS
2121 18:09:15.551899 DUTY Scan : NO K
2122 18:09:15.551989 ZQ Calibration : PASS
2123 18:09:15.552078 Jitter Meter : NO K
2124 18:09:15.552176 CBT Training : PASS
2125 18:09:15.552270 Write leveling : PASS
2126 18:09:15.552361 RX DQS gating : PASS
2127 18:09:15.552451 RX DQ/DQS(RDDQC) : PASS
2128 18:09:15.552546 TX DQ/DQS : PASS
2129 18:09:15.552637 RX DATLAT : PASS
2130 18:09:15.552727 RX DQ/DQS(Engine): PASS
2131 18:09:15.552816 TX OE : NO K
2132 18:09:15.552905 All Pass.
2133 18:09:15.552996
2134 18:09:15.553091 CH 1, Rank 1
2135 18:09:15.553183 SW Impedance : PASS
2136 18:09:15.553272 DUTY Scan : NO K
2137 18:09:15.553362 ZQ Calibration : PASS
2138 18:09:15.553452 Jitter Meter : NO K
2139 18:09:15.553541 CBT Training : PASS
2140 18:09:15.553630 Write leveling : PASS
2141 18:09:15.553719 RX DQS gating : PASS
2142 18:09:15.553808 RX DQ/DQS(RDDQC) : PASS
2143 18:09:15.553897 TX DQ/DQS : PASS
2144 18:09:15.553986 RX DATLAT : PASS
2145 18:09:15.554075 RX DQ/DQS(Engine): PASS
2146 18:09:15.554178 TX OE : NO K
2147 18:09:15.554307 All Pass.
2148 18:09:15.554397
2149 18:09:15.554487 DramC Write-DBI off
2150 18:09:15.554577 PER_BANK_REFRESH: Hybrid Mode
2151 18:09:15.554667 TX_TRACKING: ON
2152 18:09:15.554757 [GetDramInforAfterCalByMRR] Vendor 6.
2153 18:09:15.554846 [GetDramInforAfterCalByMRR] Revision 606.
2154 18:09:15.554935 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 18:09:15.555024 MR0 0x3b3b
2156 18:09:15.555113 MR8 0x5151
2157 18:09:15.555202 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 18:09:15.555291
2159 18:09:15.555381 MR0 0x3b3b
2160 18:09:15.555469 MR8 0x5151
2161 18:09:15.555558 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 18:09:15.555648
2163 18:09:15.555736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 18:09:15.555827 [FAST_K] Save calibration result to emmc
2165 18:09:15.555916 [FAST_K] Save calibration result to emmc
2166 18:09:15.556005 dram_init: config_dvfs: 1
2167 18:09:15.556094 dramc_set_vcore_voltage set vcore to 662500
2168 18:09:15.556183 Read voltage for 1200, 2
2169 18:09:15.556272 Vio18 = 0
2170 18:09:15.556360 Vcore = 662500
2171 18:09:15.556449 Vdram = 0
2172 18:09:15.556538 Vddq = 0
2173 18:09:15.556626 Vmddr = 0
2174 18:09:15.556714 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 18:09:15.556804 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 18:09:15.556893 MEM_TYPE=3, freq_sel=15
2177 18:09:15.556982 sv_algorithm_assistance_LP4_1600
2178 18:09:15.557070 ============ PULL DRAM RESETB DOWN ============
2179 18:09:15.557160 ========== PULL DRAM RESETB DOWN end =========
2180 18:09:15.557249 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 18:09:15.557338 ===================================
2182 18:09:15.557427 LPDDR4 DRAM CONFIGURATION
2183 18:09:15.557516 ===================================
2184 18:09:15.557605 EX_ROW_EN[0] = 0x0
2185 18:09:15.557694 EX_ROW_EN[1] = 0x0
2186 18:09:15.557782 LP4Y_EN = 0x0
2187 18:09:15.557871 WORK_FSP = 0x0
2188 18:09:15.557960 WL = 0x4
2189 18:09:15.558048 RL = 0x4
2190 18:09:15.558137 BL = 0x2
2191 18:09:15.558269 RPST = 0x0
2192 18:09:15.558358 RD_PRE = 0x0
2193 18:09:15.558447 WR_PRE = 0x1
2194 18:09:15.558535 WR_PST = 0x0
2195 18:09:15.558624 DBI_WR = 0x0
2196 18:09:15.558713 DBI_RD = 0x0
2197 18:09:15.558801 OTF = 0x1
2198 18:09:15.558890 ===================================
2199 18:09:15.558980 ===================================
2200 18:09:15.559071 ANA top config
2201 18:09:15.559160 ===================================
2202 18:09:15.559249 DLL_ASYNC_EN = 0
2203 18:09:15.559338 ALL_SLAVE_EN = 0
2204 18:09:15.559426 NEW_RANK_MODE = 1
2205 18:09:15.559523 DLL_IDLE_MODE = 1
2206 18:09:15.559614 LP45_APHY_COMB_EN = 1
2207 18:09:15.559703 TX_ODT_DIS = 1
2208 18:09:15.559792 NEW_8X_MODE = 1
2209 18:09:15.559883 ===================================
2210 18:09:15.559972 ===================================
2211 18:09:15.560062 data_rate = 2400
2212 18:09:15.560159 CKR = 1
2213 18:09:15.560250 DQ_P2S_RATIO = 8
2214 18:09:15.560340 ===================================
2215 18:09:15.560438 CA_P2S_RATIO = 8
2216 18:09:15.560529 DQ_CA_OPEN = 0
2217 18:09:15.560618 DQ_SEMI_OPEN = 0
2218 18:09:15.560708 CA_SEMI_OPEN = 0
2219 18:09:15.560797 CA_FULL_RATE = 0
2220 18:09:15.560885 DQ_CKDIV4_EN = 0
2221 18:09:15.560981 CA_CKDIV4_EN = 0
2222 18:09:15.561072 CA_PREDIV_EN = 0
2223 18:09:15.561162 PH8_DLY = 17
2224 18:09:15.561251 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 18:09:15.561340 DQ_AAMCK_DIV = 4
2226 18:09:15.561428 CA_AAMCK_DIV = 4
2227 18:09:15.561517 CA_ADMCK_DIV = 4
2228 18:09:15.561606 DQ_TRACK_CA_EN = 0
2229 18:09:15.561695 CA_PICK = 1200
2230 18:09:15.561784 CA_MCKIO = 1200
2231 18:09:15.561873 MCKIO_SEMI = 0
2232 18:09:15.561961 PLL_FREQ = 2366
2233 18:09:15.562049 DQ_UI_PI_RATIO = 32
2234 18:09:15.562137 CA_UI_PI_RATIO = 0
2235 18:09:15.562271 ===================================
2236 18:09:15.562361 ===================================
2237 18:09:15.562477 memory_type:LPDDR4
2238 18:09:15.562566 GP_NUM : 10
2239 18:09:15.562656 SRAM_EN : 1
2240 18:09:15.562745 MD32_EN : 0
2241 18:09:15.562834 ===================================
2242 18:09:15.562931 [ANA_INIT] >>>>>>>>>>>>>>
2243 18:09:15.563021 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 18:09:15.563156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 18:09:15.563247 ===================================
2246 18:09:15.563337 data_rate = 2400,PCW = 0X5b00
2247 18:09:15.563427 ===================================
2248 18:09:15.563519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 18:09:15.563610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 18:09:15.563703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 18:09:15.563794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 18:09:15.563884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 18:09:15.563973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 18:09:15.564063 [ANA_INIT] flow start
2255 18:09:15.564152 [ANA_INIT] PLL >>>>>>>>
2256 18:09:15.564461 [ANA_INIT] PLL <<<<<<<<
2257 18:09:15.564597 [ANA_INIT] MIDPI >>>>>>>>
2258 18:09:15.564729 [ANA_INIT] MIDPI <<<<<<<<
2259 18:09:15.564856 [ANA_INIT] DLL >>>>>>>>
2260 18:09:15.564982 [ANA_INIT] DLL <<<<<<<<
2261 18:09:15.565107 [ANA_INIT] flow end
2262 18:09:15.565232 ============ LP4 DIFF to SE enter ============
2263 18:09:15.565360 ============ LP4 DIFF to SE exit ============
2264 18:09:15.565487 [ANA_INIT] <<<<<<<<<<<<<
2265 18:09:15.565607 [Flow] Enable top DCM control >>>>>
2266 18:09:15.565690 [Flow] Enable top DCM control <<<<<
2267 18:09:15.565772 Enable DLL master slave shuffle
2268 18:09:15.565853 ==============================================================
2269 18:09:15.565934 Gating Mode config
2270 18:09:15.566015 ==============================================================
2271 18:09:15.566095 Config description:
2272 18:09:15.566220 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 18:09:15.566305 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 18:09:15.566387 SELPH_MODE 0: By rank 1: By Phase
2275 18:09:15.566469 ==============================================================
2276 18:09:15.566550 GAT_TRACK_EN = 1
2277 18:09:15.566630 RX_GATING_MODE = 2
2278 18:09:15.566710 RX_GATING_TRACK_MODE = 2
2279 18:09:15.566790 SELPH_MODE = 1
2280 18:09:15.566870 PICG_EARLY_EN = 1
2281 18:09:15.566951 VALID_LAT_VALUE = 1
2282 18:09:15.567062 ==============================================================
2283 18:09:15.567143 Enter into Gating configuration >>>>
2284 18:09:15.567223 Exit from Gating configuration <<<<
2285 18:09:15.567304 Enter into DVFS_PRE_config >>>>>
2286 18:09:15.567386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 18:09:15.567468 Exit from DVFS_PRE_config <<<<<
2288 18:09:15.567548 Enter into PICG configuration >>>>
2289 18:09:15.567628 Exit from PICG configuration <<<<
2290 18:09:15.567708 [RX_INPUT] configuration >>>>>
2291 18:09:15.567788 [RX_INPUT] configuration <<<<<
2292 18:09:15.567869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 18:09:15.567950 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 18:09:15.568031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 18:09:15.568112 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 18:09:15.568193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 18:09:15.568304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 18:09:15.568385 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 18:09:15.568465 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 18:09:15.568545 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 18:09:15.568626 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 18:09:15.568706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 18:09:15.568787 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 18:09:15.568868 ===================================
2305 18:09:15.568948 LPDDR4 DRAM CONFIGURATION
2306 18:09:15.569027 ===================================
2307 18:09:15.569107 EX_ROW_EN[0] = 0x0
2308 18:09:15.569187 EX_ROW_EN[1] = 0x0
2309 18:09:15.569266 LP4Y_EN = 0x0
2310 18:09:15.569345 WORK_FSP = 0x0
2311 18:09:15.569425 WL = 0x4
2312 18:09:15.569505 RL = 0x4
2313 18:09:15.569584 BL = 0x2
2314 18:09:15.569663 RPST = 0x0
2315 18:09:15.569743 RD_PRE = 0x0
2316 18:09:15.569822 WR_PRE = 0x1
2317 18:09:15.569902 WR_PST = 0x0
2318 18:09:15.569981 DBI_WR = 0x0
2319 18:09:15.570060 DBI_RD = 0x0
2320 18:09:15.570139 OTF = 0x1
2321 18:09:15.570245 ===================================
2322 18:09:15.570299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 18:09:15.570350 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 18:09:15.570402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 18:09:15.570454 ===================================
2326 18:09:15.570509 LPDDR4 DRAM CONFIGURATION
2327 18:09:15.570564 ===================================
2328 18:09:15.570615 EX_ROW_EN[0] = 0x10
2329 18:09:15.570672 EX_ROW_EN[1] = 0x0
2330 18:09:15.570724 LP4Y_EN = 0x0
2331 18:09:15.570775 WORK_FSP = 0x0
2332 18:09:15.570824 WL = 0x4
2333 18:09:15.570875 RL = 0x4
2334 18:09:15.570925 BL = 0x2
2335 18:09:15.570976 RPST = 0x0
2336 18:09:15.571030 RD_PRE = 0x0
2337 18:09:15.571084 WR_PRE = 0x1
2338 18:09:15.571138 WR_PST = 0x0
2339 18:09:15.571193 DBI_WR = 0x0
2340 18:09:15.571244 DBI_RD = 0x0
2341 18:09:15.571294 OTF = 0x1
2342 18:09:15.571345 ===================================
2343 18:09:15.571396 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 18:09:15.571448 ==
2345 18:09:15.571499 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 18:09:15.571550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 18:09:15.571602 ==
2348 18:09:15.571653 [Duty_Offset_Calibration]
2349 18:09:15.571704 B0:1 B1:-1 CA:0
2350 18:09:15.571754
2351 18:09:15.571805 [DutyScan_Calibration_Flow] k_type=0
2352 18:09:15.571855
2353 18:09:15.571906 ==CLK 0==
2354 18:09:15.571956 Final CLK duty delay cell = 0
2355 18:09:15.572007 [0] MAX Duty = 5094%(X100), DQS PI = 16
2356 18:09:15.572058 [0] MIN Duty = 4875%(X100), DQS PI = 8
2357 18:09:15.572109 [0] AVG Duty = 4984%(X100)
2358 18:09:15.572159
2359 18:09:15.572209 CH0 CLK Duty spec in!! Max-Min= 219%
2360 18:09:15.572260 [DutyScan_Calibration_Flow] ====Done====
2361 18:09:15.572310
2362 18:09:15.572360 [DutyScan_Calibration_Flow] k_type=1
2363 18:09:15.572410
2364 18:09:15.572460 ==DQS 0 ==
2365 18:09:15.572510 Final DQS duty delay cell = -4
2366 18:09:15.572561 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2367 18:09:15.572611 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2368 18:09:15.572662 [-4] AVG Duty = 4968%(X100)
2369 18:09:15.572713
2370 18:09:15.572763 ==DQS 1 ==
2371 18:09:15.572814 Final DQS duty delay cell = 0
2372 18:09:15.572864 [0] MAX Duty = 5124%(X100), DQS PI = 8
2373 18:09:15.572915 [0] MIN Duty = 5000%(X100), DQS PI = 20
2374 18:09:15.572967 [0] AVG Duty = 5062%(X100)
2375 18:09:15.573018
2376 18:09:15.573277 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2377 18:09:15.573337
2378 18:09:15.573390 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2379 18:09:15.573441 [DutyScan_Calibration_Flow] ====Done====
2380 18:09:15.573492
2381 18:09:15.573543 [DutyScan_Calibration_Flow] k_type=3
2382 18:09:15.573594
2383 18:09:15.573643 ==DQM 0 ==
2384 18:09:15.573694 Final DQM duty delay cell = 0
2385 18:09:15.573745 [0] MAX Duty = 5062%(X100), DQS PI = 18
2386 18:09:15.573796 [0] MIN Duty = 4875%(X100), DQS PI = 8
2387 18:09:15.573847 [0] AVG Duty = 4968%(X100)
2388 18:09:15.573897
2389 18:09:15.573948 ==DQM 1 ==
2390 18:09:15.573999 Final DQM duty delay cell = 4
2391 18:09:15.574049 [4] MAX Duty = 5187%(X100), DQS PI = 14
2392 18:09:15.574100 [4] MIN Duty = 5000%(X100), DQS PI = 22
2393 18:09:15.574150 [4] AVG Duty = 5093%(X100)
2394 18:09:15.574249
2395 18:09:15.574300 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2396 18:09:15.574351
2397 18:09:15.574401 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2398 18:09:15.574452 [DutyScan_Calibration_Flow] ====Done====
2399 18:09:15.574503
2400 18:09:15.574553 [DutyScan_Calibration_Flow] k_type=2
2401 18:09:15.574604
2402 18:09:15.574655 ==DQ 0 ==
2403 18:09:15.574705 Final DQ duty delay cell = -4
2404 18:09:15.574756 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2405 18:09:15.574806 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2406 18:09:15.574856 [-4] AVG Duty = 4953%(X100)
2407 18:09:15.574907
2408 18:09:15.574957 ==DQ 1 ==
2409 18:09:15.575007 Final DQ duty delay cell = 0
2410 18:09:15.575058 [0] MAX Duty = 5093%(X100), DQS PI = 0
2411 18:09:15.575108 [0] MIN Duty = 4969%(X100), DQS PI = 40
2412 18:09:15.575159 [0] AVG Duty = 5031%(X100)
2413 18:09:15.575209
2414 18:09:15.575259 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2415 18:09:15.575309
2416 18:09:15.575359 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2417 18:09:15.575411 [DutyScan_Calibration_Flow] ====Done====
2418 18:09:15.575462 ==
2419 18:09:15.575513 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 18:09:15.575563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 18:09:15.575615 ==
2422 18:09:15.575665 [Duty_Offset_Calibration]
2423 18:09:15.575715 B0:-1 B1:1 CA:2
2424 18:09:15.575765
2425 18:09:15.575815 [DutyScan_Calibration_Flow] k_type=0
2426 18:09:15.575866
2427 18:09:15.575916 ==CLK 0==
2428 18:09:15.575966 Final CLK duty delay cell = 0
2429 18:09:15.576017 [0] MAX Duty = 5156%(X100), DQS PI = 22
2430 18:09:15.576068 [0] MIN Duty = 5000%(X100), DQS PI = 0
2431 18:09:15.576118 [0] AVG Duty = 5078%(X100)
2432 18:09:15.576168
2433 18:09:15.576217 CH1 CLK Duty spec in!! Max-Min= 156%
2434 18:09:15.576268 [DutyScan_Calibration_Flow] ====Done====
2435 18:09:15.576319
2436 18:09:15.576369 [DutyScan_Calibration_Flow] k_type=1
2437 18:09:15.576419
2438 18:09:15.576470 ==DQS 0 ==
2439 18:09:15.576520 Final DQS duty delay cell = 0
2440 18:09:15.576571 [0] MAX Duty = 5125%(X100), DQS PI = 50
2441 18:09:15.576622 [0] MIN Duty = 4875%(X100), DQS PI = 6
2442 18:09:15.576672 [0] AVG Duty = 5000%(X100)
2443 18:09:15.576722
2444 18:09:15.576772 ==DQS 1 ==
2445 18:09:15.576823 Final DQS duty delay cell = 0
2446 18:09:15.576874 [0] MAX Duty = 5094%(X100), DQS PI = 12
2447 18:09:15.576924 [0] MIN Duty = 4969%(X100), DQS PI = 58
2448 18:09:15.576975 [0] AVG Duty = 5031%(X100)
2449 18:09:15.577025
2450 18:09:15.577075 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2451 18:09:15.577125
2452 18:09:15.577174 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2453 18:09:15.577225 [DutyScan_Calibration_Flow] ====Done====
2454 18:09:15.577275
2455 18:09:15.577324 [DutyScan_Calibration_Flow] k_type=3
2456 18:09:15.577374
2457 18:09:15.577424 ==DQM 0 ==
2458 18:09:15.577475 Final DQM duty delay cell = -4
2459 18:09:15.577525 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2460 18:09:15.577577 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2461 18:09:15.577627 [-4] AVG Duty = 4937%(X100)
2462 18:09:15.577678
2463 18:09:15.577728 ==DQM 1 ==
2464 18:09:15.577778 Final DQM duty delay cell = 0
2465 18:09:15.577829 [0] MAX Duty = 5156%(X100), DQS PI = 6
2466 18:09:15.577879 [0] MIN Duty = 4969%(X100), DQS PI = 28
2467 18:09:15.577939 [0] AVG Duty = 5062%(X100)
2468 18:09:15.578020
2469 18:09:15.578100 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2470 18:09:15.578214
2471 18:09:15.578270 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2472 18:09:15.578322 [DutyScan_Calibration_Flow] ====Done====
2473 18:09:15.578373
2474 18:09:15.578428 [DutyScan_Calibration_Flow] k_type=2
2475 18:09:15.578483
2476 18:09:15.578537 ==DQ 0 ==
2477 18:09:15.578593 Final DQ duty delay cell = 0
2478 18:09:15.578676 [0] MAX Duty = 5156%(X100), DQS PI = 28
2479 18:09:15.578759 [0] MIN Duty = 4876%(X100), DQS PI = 6
2480 18:09:15.578840 [0] AVG Duty = 5016%(X100)
2481 18:09:15.578921
2482 18:09:15.579000 ==DQ 1 ==
2483 18:09:15.579080 Final DQ duty delay cell = 0
2484 18:09:15.579160 [0] MAX Duty = 5124%(X100), DQS PI = 10
2485 18:09:15.579240 [0] MIN Duty = 4969%(X100), DQS PI = 0
2486 18:09:15.579320 [0] AVG Duty = 5046%(X100)
2487 18:09:15.579398
2488 18:09:15.579478 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2489 18:09:15.579557
2490 18:09:15.579637 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2491 18:09:15.579717 [DutyScan_Calibration_Flow] ====Done====
2492 18:09:15.579796 nWR fixed to 30
2493 18:09:15.579877 [ModeRegInit_LP4] CH0 RK0
2494 18:09:15.579957 [ModeRegInit_LP4] CH0 RK1
2495 18:09:15.580036 [ModeRegInit_LP4] CH1 RK0
2496 18:09:15.580115 [ModeRegInit_LP4] CH1 RK1
2497 18:09:15.580194 match AC timing 7
2498 18:09:15.580275 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 18:09:15.580355 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 18:09:15.580441 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 18:09:15.580526 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 18:09:15.580607 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 18:09:15.580686 ==
2504 18:09:15.580766 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 18:09:15.580846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 18:09:15.580926 ==
2507 18:09:15.581006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 18:09:15.581087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2509 18:09:15.581167 [CA 0] Center 39 (9~70) winsize 62
2510 18:09:15.581247 [CA 1] Center 39 (9~69) winsize 61
2511 18:09:15.581327 [CA 2] Center 35 (5~66) winsize 62
2512 18:09:15.581407 [CA 3] Center 35 (5~66) winsize 62
2513 18:09:15.581486 [CA 4] Center 33 (4~63) winsize 60
2514 18:09:15.581582 [CA 5] Center 33 (3~63) winsize 61
2515 18:09:15.581676
2516 18:09:15.581755 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2517 18:09:15.581839
2518 18:09:15.581925 [CATrainingPosCal] consider 1 rank data
2519 18:09:15.582005 u2DelayCellTimex100 = 270/100 ps
2520 18:09:15.582085 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2521 18:09:15.582187 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2522 18:09:15.582256 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2523 18:09:15.582308 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2524 18:09:15.582359 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2525 18:09:15.582623 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2526 18:09:15.582752
2527 18:09:15.582877 CA PerBit enable=1, Macro0, CA PI delay=33
2528 18:09:15.583001
2529 18:09:15.583126 [CBTSetCACLKResult] CA Dly = 33
2530 18:09:15.583252 CS Dly: 8 (0~39)
2531 18:09:15.583376 ==
2532 18:09:15.583500 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 18:09:15.583625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 18:09:15.583713 ==
2535 18:09:15.583768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 18:09:15.583820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 18:09:15.583873 [CA 0] Center 39 (9~70) winsize 62
2538 18:09:15.583925 [CA 1] Center 39 (9~70) winsize 62
2539 18:09:15.583977 [CA 2] Center 35 (5~66) winsize 62
2540 18:09:15.584029 [CA 3] Center 34 (4~65) winsize 62
2541 18:09:15.584080 [CA 4] Center 33 (3~64) winsize 62
2542 18:09:15.584130 [CA 5] Center 33 (3~63) winsize 61
2543 18:09:15.584181
2544 18:09:15.584232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 18:09:15.584283
2546 18:09:15.584333 [CATrainingPosCal] consider 2 rank data
2547 18:09:15.584384 u2DelayCellTimex100 = 270/100 ps
2548 18:09:15.584435 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2549 18:09:15.584486 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2550 18:09:15.584536 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 18:09:15.584587 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2552 18:09:15.584638 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2553 18:09:15.584688 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 18:09:15.584738
2555 18:09:15.584788 CA PerBit enable=1, Macro0, CA PI delay=33
2556 18:09:15.584839
2557 18:09:15.584889 [CBTSetCACLKResult] CA Dly = 33
2558 18:09:15.584939 CS Dly: 9 (0~41)
2559 18:09:15.584989
2560 18:09:15.585039 ----->DramcWriteLeveling(PI) begin...
2561 18:09:15.585091 ==
2562 18:09:15.585141 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 18:09:15.585192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 18:09:15.585243 ==
2565 18:09:15.585293 Write leveling (Byte 0): 35 => 35
2566 18:09:15.585344 Write leveling (Byte 1): 30 => 30
2567 18:09:15.585395 DramcWriteLeveling(PI) end<-----
2568 18:09:15.585445
2569 18:09:15.585496 ==
2570 18:09:15.585546 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 18:09:15.585597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 18:09:15.585648 ==
2573 18:09:15.585699 [Gating] SW mode calibration
2574 18:09:15.585749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 18:09:15.585801 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 18:09:15.585852 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2577 18:09:15.585903 0 15 4 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
2578 18:09:15.585953 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
2579 18:09:15.586005 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 18:09:15.586055 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 18:09:15.586106 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 18:09:15.586156 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 18:09:15.586256 0 15 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
2584 18:09:15.586307 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2585 18:09:15.586358 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 18:09:15.586409 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 18:09:15.586460 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 18:09:15.586510 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 18:09:15.586561 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 18:09:15.586612 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 18:09:15.586662 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2592 18:09:15.586713 1 1 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2593 18:09:15.586763 1 1 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2594 18:09:15.586814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 18:09:15.586865 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 18:09:15.586916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 18:09:15.586966 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 18:09:15.587017 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 18:09:15.587071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2600 18:09:15.587122 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2601 18:09:15.587172 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 18:09:15.587222 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 18:09:15.587342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 18:09:15.587431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 18:09:15.587481 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 18:09:15.587532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 18:09:15.587583 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 18:09:15.587634 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 18:09:15.587685 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 18:09:15.587739 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 18:09:15.587795 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 18:09:15.587851 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 18:09:15.587903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 18:09:15.587954 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2615 18:09:15.588004 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 18:09:15.588055 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 18:09:15.588106 Total UI for P1: 0, mck2ui 16
2618 18:09:15.588158 best dqsien dly found for B0: ( 1, 3, 26)
2619 18:09:15.588209 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 18:09:15.588260 Total UI for P1: 0, mck2ui 16
2621 18:09:15.588311 best dqsien dly found for B1: ( 1, 4, 0)
2622 18:09:15.588362 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2623 18:09:15.588413 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 18:09:15.588463
2625 18:09:15.588513 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2626 18:09:15.588564 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 18:09:15.588614 [Gating] SW calibration Done
2628 18:09:15.588666 ==
2629 18:09:15.588716 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 18:09:15.588991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 18:09:15.589052 ==
2632 18:09:15.589104 RX Vref Scan: 0
2633 18:09:15.589155
2634 18:09:15.589206 RX Vref 0 -> 0, step: 1
2635 18:09:15.589257
2636 18:09:15.589307 RX Delay -40 -> 252, step: 8
2637 18:09:15.589358 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2638 18:09:15.589410 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2639 18:09:15.589461 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2640 18:09:15.589512 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2641 18:09:15.589563 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2642 18:09:15.589614 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2643 18:09:15.589677 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2644 18:09:15.589746 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2645 18:09:15.589810 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2646 18:09:15.589861 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2647 18:09:15.589912 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2648 18:09:15.589963 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2649 18:09:15.590014 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2650 18:09:15.590066 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2651 18:09:15.590117 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2652 18:09:15.590208 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 18:09:15.590282 ==
2654 18:09:15.590334 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 18:09:15.590385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 18:09:15.590499 ==
2657 18:09:15.590562 DQS Delay:
2658 18:09:15.590614 DQS0 = 0, DQS1 = 0
2659 18:09:15.590665 DQM Delay:
2660 18:09:15.590716 DQM0 = 119, DQM1 = 105
2661 18:09:15.590779 DQ Delay:
2662 18:09:15.590846 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2663 18:09:15.590911 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2664 18:09:15.590962 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2665 18:09:15.591013 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2666 18:09:15.591063
2667 18:09:15.591114
2668 18:09:15.591163 ==
2669 18:09:15.591214 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 18:09:15.591265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 18:09:15.591316 ==
2672 18:09:15.591374
2673 18:09:15.591427
2674 18:09:15.591477 TX Vref Scan disable
2675 18:09:15.591528 == TX Byte 0 ==
2676 18:09:15.591578 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2677 18:09:15.591629 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2678 18:09:15.591680 == TX Byte 1 ==
2679 18:09:15.591731 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2680 18:09:15.591812 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2681 18:09:15.591863 ==
2682 18:09:15.591913 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 18:09:15.591964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 18:09:15.592026 ==
2685 18:09:15.592078 TX Vref=22, minBit 0, minWin=25, winSum=419
2686 18:09:15.592130 TX Vref=24, minBit 5, minWin=25, winSum=424
2687 18:09:15.592182 TX Vref=26, minBit 4, minWin=25, winSum=429
2688 18:09:15.592276 TX Vref=28, minBit 12, minWin=26, winSum=433
2689 18:09:15.592367 TX Vref=30, minBit 4, minWin=26, winSum=433
2690 18:09:15.592418 TX Vref=32, minBit 4, minWin=26, winSum=432
2691 18:09:15.592507 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 28
2692 18:09:15.592559
2693 18:09:15.592609 Final TX Range 1 Vref 28
2694 18:09:15.592659
2695 18:09:15.592710 ==
2696 18:09:15.592760 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 18:09:15.592810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 18:09:15.592861 ==
2699 18:09:15.592919
2700 18:09:15.592971
2701 18:09:15.593022 TX Vref Scan disable
2702 18:09:15.593073 == TX Byte 0 ==
2703 18:09:15.593123 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2704 18:09:15.593174 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2705 18:09:15.593224 == TX Byte 1 ==
2706 18:09:15.593275 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2707 18:09:15.593326 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2708 18:09:15.593376
2709 18:09:15.593427 [DATLAT]
2710 18:09:15.593477 Freq=1200, CH0 RK0
2711 18:09:15.593527
2712 18:09:15.593577 DATLAT Default: 0xd
2713 18:09:15.593628 0, 0xFFFF, sum = 0
2714 18:09:15.593680 1, 0xFFFF, sum = 0
2715 18:09:15.593732 2, 0xFFFF, sum = 0
2716 18:09:15.593782 3, 0xFFFF, sum = 0
2717 18:09:15.593834 4, 0xFFFF, sum = 0
2718 18:09:15.593885 5, 0xFFFF, sum = 0
2719 18:09:15.593937 6, 0xFFFF, sum = 0
2720 18:09:15.593988 7, 0xFFFF, sum = 0
2721 18:09:15.594039 8, 0xFFFF, sum = 0
2722 18:09:15.594091 9, 0xFFFF, sum = 0
2723 18:09:15.594142 10, 0xFFFF, sum = 0
2724 18:09:15.594225 11, 0xFFFF, sum = 0
2725 18:09:15.594291 12, 0x0, sum = 1
2726 18:09:15.594342 13, 0x0, sum = 2
2727 18:09:15.594393 14, 0x0, sum = 3
2728 18:09:15.594445 15, 0x0, sum = 4
2729 18:09:15.594496 best_step = 13
2730 18:09:15.594582
2731 18:09:15.594631 ==
2732 18:09:15.594682 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 18:09:15.594732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 18:09:15.594784 ==
2735 18:09:15.594835 RX Vref Scan: 1
2736 18:09:15.594885
2737 18:09:15.594935 Set Vref Range= 32 -> 127
2738 18:09:15.594986
2739 18:09:15.595036 RX Vref 32 -> 127, step: 1
2740 18:09:15.595086
2741 18:09:15.595136 RX Delay -21 -> 252, step: 4
2742 18:09:15.595186
2743 18:09:15.595236 Set Vref, RX VrefLevel [Byte0]: 32
2744 18:09:15.595287 [Byte1]: 32
2745 18:09:15.595338
2746 18:09:15.595388 Set Vref, RX VrefLevel [Byte0]: 33
2747 18:09:15.595439 [Byte1]: 33
2748 18:09:15.595489
2749 18:09:15.595539 Set Vref, RX VrefLevel [Byte0]: 34
2750 18:09:15.595589 [Byte1]: 34
2751 18:09:15.595644
2752 18:09:15.595698 Set Vref, RX VrefLevel [Byte0]: 35
2753 18:09:15.595748 [Byte1]: 35
2754 18:09:15.595799
2755 18:09:15.595849 Set Vref, RX VrefLevel [Byte0]: 36
2756 18:09:15.595903 [Byte1]: 36
2757 18:09:15.595954
2758 18:09:15.596004 Set Vref, RX VrefLevel [Byte0]: 37
2759 18:09:15.596055 [Byte1]: 37
2760 18:09:15.596105
2761 18:09:15.596155 Set Vref, RX VrefLevel [Byte0]: 38
2762 18:09:15.596208 [Byte1]: 38
2763 18:09:15.596262
2764 18:09:15.596317 Set Vref, RX VrefLevel [Byte0]: 39
2765 18:09:15.596373 [Byte1]: 39
2766 18:09:15.596424
2767 18:09:15.596474 Set Vref, RX VrefLevel [Byte0]: 40
2768 18:09:15.596551 [Byte1]: 40
2769 18:09:15.596641
2770 18:09:15.596726 Set Vref, RX VrefLevel [Byte0]: 41
2771 18:09:15.596814 [Byte1]: 41
2772 18:09:15.596895
2773 18:09:15.596975 Set Vref, RX VrefLevel [Byte0]: 42
2774 18:09:15.597055 [Byte1]: 42
2775 18:09:15.597137
2776 18:09:15.597230 Set Vref, RX VrefLevel [Byte0]: 43
2777 18:09:15.597353 [Byte1]: 43
2778 18:09:15.597451
2779 18:09:15.597532 Set Vref, RX VrefLevel [Byte0]: 44
2780 18:09:15.597613 [Byte1]: 44
2781 18:09:15.597692
2782 18:09:15.597772 Set Vref, RX VrefLevel [Byte0]: 45
2783 18:09:15.597852 [Byte1]: 45
2784 18:09:15.597931
2785 18:09:15.598011 Set Vref, RX VrefLevel [Byte0]: 46
2786 18:09:15.598307 [Byte1]: 46
2787 18:09:15.598438
2788 18:09:15.598594 Set Vref, RX VrefLevel [Byte0]: 47
2789 18:09:15.598722 [Byte1]: 47
2790 18:09:15.598847
2791 18:09:15.598973 Set Vref, RX VrefLevel [Byte0]: 48
2792 18:09:15.599098 [Byte1]: 48
2793 18:09:15.599222
2794 18:09:15.599346 Set Vref, RX VrefLevel [Byte0]: 49
2795 18:09:15.599423 [Byte1]: 49
2796 18:09:15.599476
2797 18:09:15.599527 Set Vref, RX VrefLevel [Byte0]: 50
2798 18:09:15.599579 [Byte1]: 50
2799 18:09:15.599630
2800 18:09:15.599681 Set Vref, RX VrefLevel [Byte0]: 51
2801 18:09:15.599732 [Byte1]: 51
2802 18:09:15.599783
2803 18:09:15.599833 Set Vref, RX VrefLevel [Byte0]: 52
2804 18:09:15.599885 [Byte1]: 52
2805 18:09:15.599935
2806 18:09:15.599986 Set Vref, RX VrefLevel [Byte0]: 53
2807 18:09:15.600037 [Byte1]: 53
2808 18:09:15.600088
2809 18:09:15.600138 Set Vref, RX VrefLevel [Byte0]: 54
2810 18:09:15.600188 [Byte1]: 54
2811 18:09:15.600239
2812 18:09:15.600290 Set Vref, RX VrefLevel [Byte0]: 55
2813 18:09:15.600340 [Byte1]: 55
2814 18:09:15.600391
2815 18:09:15.600441 Set Vref, RX VrefLevel [Byte0]: 56
2816 18:09:15.600508 [Byte1]: 56
2817 18:09:15.600572
2818 18:09:15.600622 Set Vref, RX VrefLevel [Byte0]: 57
2819 18:09:15.600672 [Byte1]: 57
2820 18:09:15.600724
2821 18:09:15.600774 Set Vref, RX VrefLevel [Byte0]: 58
2822 18:09:15.600824 [Byte1]: 58
2823 18:09:15.600874
2824 18:09:15.600925 Set Vref, RX VrefLevel [Byte0]: 59
2825 18:09:15.600976 [Byte1]: 59
2826 18:09:15.601026
2827 18:09:15.601076 Set Vref, RX VrefLevel [Byte0]: 60
2828 18:09:15.601126 [Byte1]: 60
2829 18:09:15.601177
2830 18:09:15.601228 Set Vref, RX VrefLevel [Byte0]: 61
2831 18:09:15.601278 [Byte1]: 61
2832 18:09:15.601329
2833 18:09:15.601379 Set Vref, RX VrefLevel [Byte0]: 62
2834 18:09:15.601430 [Byte1]: 62
2835 18:09:15.601480
2836 18:09:15.601531 Set Vref, RX VrefLevel [Byte0]: 63
2837 18:09:15.601582 [Byte1]: 63
2838 18:09:15.601632
2839 18:09:15.601682 Set Vref, RX VrefLevel [Byte0]: 64
2840 18:09:15.601733 [Byte1]: 64
2841 18:09:15.601783
2842 18:09:15.601833 Set Vref, RX VrefLevel [Byte0]: 65
2843 18:09:15.601883 [Byte1]: 65
2844 18:09:15.601934
2845 18:09:15.601984 Set Vref, RX VrefLevel [Byte0]: 66
2846 18:09:15.602034 [Byte1]: 66
2847 18:09:15.602084
2848 18:09:15.602135 Set Vref, RX VrefLevel [Byte0]: 67
2849 18:09:15.602228 [Byte1]: 67
2850 18:09:15.602279
2851 18:09:15.602330 Set Vref, RX VrefLevel [Byte0]: 68
2852 18:09:15.602380 [Byte1]: 68
2853 18:09:15.602430
2854 18:09:15.602480 Set Vref, RX VrefLevel [Byte0]: 69
2855 18:09:15.602530 [Byte1]: 69
2856 18:09:15.602580
2857 18:09:15.602631 Set Vref, RX VrefLevel [Byte0]: 70
2858 18:09:15.602681 [Byte1]: 70
2859 18:09:15.602731
2860 18:09:15.602781 Set Vref, RX VrefLevel [Byte0]: 71
2861 18:09:15.602832 [Byte1]: 71
2862 18:09:15.602882
2863 18:09:15.602933 Set Vref, RX VrefLevel [Byte0]: 72
2864 18:09:15.602984 [Byte1]: 72
2865 18:09:15.603034
2866 18:09:15.603085 Set Vref, RX VrefLevel [Byte0]: 73
2867 18:09:15.603135 [Byte1]: 73
2868 18:09:15.603186
2869 18:09:15.603236 Set Vref, RX VrefLevel [Byte0]: 74
2870 18:09:15.603286 [Byte1]: 74
2871 18:09:15.603336
2872 18:09:15.603387 Set Vref, RX VrefLevel [Byte0]: 75
2873 18:09:15.603437 [Byte1]: 75
2874 18:09:15.603488
2875 18:09:15.603538 Set Vref, RX VrefLevel [Byte0]: 76
2876 18:09:15.603588 [Byte1]: 76
2877 18:09:15.603639
2878 18:09:15.603690 Set Vref, RX VrefLevel [Byte0]: 77
2879 18:09:15.603740 [Byte1]: 77
2880 18:09:15.603790
2881 18:09:15.603841 Set Vref, RX VrefLevel [Byte0]: 78
2882 18:09:15.603891 [Byte1]: 78
2883 18:09:15.603941
2884 18:09:15.603991 Final RX Vref Byte 0 = 55 to rank0
2885 18:09:15.604042 Final RX Vref Byte 1 = 56 to rank0
2886 18:09:15.604093 Final RX Vref Byte 0 = 55 to rank1
2887 18:09:15.604144 Final RX Vref Byte 1 = 56 to rank1==
2888 18:09:15.604195 Dram Type= 6, Freq= 0, CH_0, rank 0
2889 18:09:15.604245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 18:09:15.604297 ==
2891 18:09:15.604348 DQS Delay:
2892 18:09:15.604398 DQS0 = 0, DQS1 = 0
2893 18:09:15.604448 DQM Delay:
2894 18:09:15.604498 DQM0 = 118, DQM1 = 107
2895 18:09:15.604549 DQ Delay:
2896 18:09:15.604604 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =114
2897 18:09:15.604674 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2898 18:09:15.604727 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2899 18:09:15.604791 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
2900 18:09:15.604848
2901 18:09:15.604901
2902 18:09:15.604953 [DQSOSCAuto] RK0, (LSB)MR18= 0xcf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2903 18:09:15.605006 CH0 RK0: MR19=403, MR18=CF8
2904 18:09:15.605058 CH0_RK0: MR19=0x403, MR18=0xCF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2905 18:09:15.605110
2906 18:09:15.605190 ----->DramcWriteLeveling(PI) begin...
2907 18:09:15.605259 ==
2908 18:09:15.605343 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 18:09:15.605424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 18:09:15.605504 ==
2911 18:09:15.605584 Write leveling (Byte 0): 31 => 31
2912 18:09:15.605665 Write leveling (Byte 1): 31 => 31
2913 18:09:15.605744 DramcWriteLeveling(PI) end<-----
2914 18:09:15.605823
2915 18:09:15.605902 ==
2916 18:09:15.605983 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 18:09:15.606063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 18:09:15.606143 ==
2919 18:09:15.606269 [Gating] SW mode calibration
2920 18:09:15.606350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2921 18:09:15.606432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2922 18:09:15.606537 0 15 0 | B1->B0 | 2322 3333 | 1 0 | (0 0) (0 0)
2923 18:09:15.606631 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2924 18:09:15.606712 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 18:09:15.606793 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 18:09:15.606873 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 18:09:15.606953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 18:09:15.607034 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 18:09:15.607114 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2930 18:09:15.607194 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2931 18:09:15.607490 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2932 18:09:15.607553 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 18:09:15.607623 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 18:09:15.607704 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 18:09:15.607785 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 18:09:15.607866 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 18:09:15.607932 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2938 18:09:15.607987 1 1 0 | B1->B0 | 3434 4444 | 1 0 | (0 0) (0 0)
2939 18:09:15.608042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 18:09:15.608125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 18:09:15.608207 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 18:09:15.608287 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 18:09:15.608367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 18:09:15.608448 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 18:09:15.608528 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2946 18:09:15.608609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2947 18:09:15.608689 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 18:09:15.608769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 18:09:15.608850 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 18:09:15.608930 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 18:09:15.609010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 18:09:15.609090 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 18:09:15.609171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 18:09:15.609251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 18:09:15.609331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 18:09:15.609411 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 18:09:15.609491 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 18:09:15.609572 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 18:09:15.609652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 18:09:15.609732 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 18:09:15.609812 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2962 18:09:15.609892 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2963 18:09:15.609972 Total UI for P1: 0, mck2ui 16
2964 18:09:15.610052 best dqsien dly found for B0: ( 1, 3, 28)
2965 18:09:15.610133 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 18:09:15.610263 Total UI for P1: 0, mck2ui 16
2967 18:09:15.610344 best dqsien dly found for B1: ( 1, 3, 30)
2968 18:09:15.610424 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2969 18:09:15.610505 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2970 18:09:15.610631
2971 18:09:15.610725 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2972 18:09:15.610805 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2973 18:09:15.610885 [Gating] SW calibration Done
2974 18:09:15.610964 ==
2975 18:09:15.753012 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 18:09:15.753154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 18:09:15.753220 ==
2978 18:09:15.753280 RX Vref Scan: 0
2979 18:09:15.753336
2980 18:09:15.753391 RX Vref 0 -> 0, step: 1
2981 18:09:15.753444
2982 18:09:15.753497 RX Delay -40 -> 252, step: 8
2983 18:09:15.753550 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2984 18:09:15.753603 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2985 18:09:15.753655 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2986 18:09:15.753707 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2987 18:09:15.753758 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2988 18:09:15.753808 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2989 18:09:15.753859 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2990 18:09:15.753911 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2991 18:09:15.753962 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2992 18:09:15.754013 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2993 18:09:15.754063 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2994 18:09:15.754115 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2995 18:09:15.754192 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2996 18:09:15.754257 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2997 18:09:15.754308 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2998 18:09:15.754359 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2999 18:09:15.754410 ==
3000 18:09:15.754461 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 18:09:15.754512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 18:09:15.754564 ==
3003 18:09:15.754615 DQS Delay:
3004 18:09:15.754666 DQS0 = 0, DQS1 = 0
3005 18:09:15.754716 DQM Delay:
3006 18:09:15.754766 DQM0 = 118, DQM1 = 108
3007 18:09:15.754818 DQ Delay:
3008 18:09:15.754869 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3009 18:09:15.754920 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
3010 18:09:15.754971 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3011 18:09:15.755022 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3012 18:09:15.755073
3013 18:09:15.755123
3014 18:09:15.755173 ==
3015 18:09:15.755224 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 18:09:15.755275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 18:09:15.755326 ==
3018 18:09:15.755377
3019 18:09:15.755428
3020 18:09:15.755478 TX Vref Scan disable
3021 18:09:15.755547 == TX Byte 0 ==
3022 18:09:15.755629 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 18:09:15.755757 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 18:09:15.755831 == TX Byte 1 ==
3025 18:09:15.755905 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3026 18:09:15.755958 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3027 18:09:15.756010 ==
3028 18:09:15.756062 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 18:09:15.756113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 18:09:15.756165 ==
3031 18:09:15.756216 TX Vref=22, minBit 5, minWin=25, winSum=425
3032 18:09:15.756302 TX Vref=24, minBit 1, minWin=25, winSum=425
3033 18:09:15.756360 TX Vref=26, minBit 1, minWin=26, winSum=427
3034 18:09:15.756413 TX Vref=28, minBit 1, minWin=26, winSum=429
3035 18:09:15.756464 TX Vref=30, minBit 10, minWin=26, winSum=431
3036 18:09:15.756515 TX Vref=32, minBit 10, minWin=26, winSum=426
3037 18:09:15.756567 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
3038 18:09:15.756619
3039 18:09:15.756670 Final TX Range 1 Vref 30
3040 18:09:15.756722
3041 18:09:15.756772 ==
3042 18:09:15.757038 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 18:09:15.757167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 18:09:15.757300 ==
3045 18:09:15.757429
3046 18:09:15.757552
3047 18:09:15.757677 TX Vref Scan disable
3048 18:09:15.757802 == TX Byte 0 ==
3049 18:09:15.757928 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3050 18:09:15.758052 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3051 18:09:15.758197 == TX Byte 1 ==
3052 18:09:15.758280 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3053 18:09:15.758335 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3054 18:09:15.758388
3055 18:09:15.758441 [DATLAT]
3056 18:09:15.758492 Freq=1200, CH0 RK1
3057 18:09:15.758543
3058 18:09:15.758594 DATLAT Default: 0xd
3059 18:09:15.758645 0, 0xFFFF, sum = 0
3060 18:09:15.758697 1, 0xFFFF, sum = 0
3061 18:09:15.758749 2, 0xFFFF, sum = 0
3062 18:09:15.758801 3, 0xFFFF, sum = 0
3063 18:09:15.758854 4, 0xFFFF, sum = 0
3064 18:09:15.758905 5, 0xFFFF, sum = 0
3065 18:09:15.758957 6, 0xFFFF, sum = 0
3066 18:09:15.759009 7, 0xFFFF, sum = 0
3067 18:09:15.759061 8, 0xFFFF, sum = 0
3068 18:09:15.759112 9, 0xFFFF, sum = 0
3069 18:09:15.759164 10, 0xFFFF, sum = 0
3070 18:09:15.759216 11, 0xFFFF, sum = 0
3071 18:09:15.759268 12, 0x0, sum = 1
3072 18:09:15.759319 13, 0x0, sum = 2
3073 18:09:15.759370 14, 0x0, sum = 3
3074 18:09:15.759421 15, 0x0, sum = 4
3075 18:09:15.759473 best_step = 13
3076 18:09:15.759523
3077 18:09:15.759574 ==
3078 18:09:15.759626 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 18:09:15.759677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 18:09:15.759728 ==
3081 18:09:15.759779 RX Vref Scan: 0
3082 18:09:15.759830
3083 18:09:15.759881 RX Vref 0 -> 0, step: 1
3084 18:09:15.759932
3085 18:09:15.759982 RX Delay -21 -> 252, step: 4
3086 18:09:15.760033 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3087 18:09:15.760084 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3088 18:09:15.760135 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3089 18:09:15.760186 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3090 18:09:15.760238 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3091 18:09:15.760289 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3092 18:09:15.760339 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3093 18:09:15.760390 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3094 18:09:15.760441 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3095 18:09:15.760493 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3096 18:09:15.760544 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3097 18:09:15.760595 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3098 18:09:15.760647 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3099 18:09:15.760698 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3100 18:09:15.760749 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3101 18:09:15.760800 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3102 18:09:15.760851 ==
3103 18:09:15.760902 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 18:09:15.760952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 18:09:15.761004 ==
3106 18:09:15.761054 DQS Delay:
3107 18:09:15.761131 DQS0 = 0, DQS1 = 0
3108 18:09:15.761195 DQM Delay:
3109 18:09:15.761246 DQM0 = 116, DQM1 = 108
3110 18:09:15.761297 DQ Delay:
3111 18:09:15.761347 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3112 18:09:15.761399 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3113 18:09:15.761450 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
3114 18:09:15.761501 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3115 18:09:15.761552
3116 18:09:15.761602
3117 18:09:15.761653 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 406 ps
3118 18:09:15.761705 CH0 RK1: MR19=403, MR18=8E3
3119 18:09:15.761756 CH0_RK1: MR19=0x403, MR18=0x8E3, DQSOSC=406, MR23=63, INC=39, DEC=26
3120 18:09:15.761808 [RxdqsGatingPostProcess] freq 1200
3121 18:09:15.761859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 18:09:15.761911 best DQS0 dly(2T, 0.5T) = (0, 11)
3123 18:09:15.761962 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 18:09:15.762013 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3125 18:09:15.762065 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 18:09:15.762116 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 18:09:15.762171 best DQS1 dly(2T, 0.5T) = (0, 11)
3128 18:09:15.762255 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 18:09:15.762306 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3130 18:09:15.762357 Pre-setting of DQS Precalculation
3131 18:09:15.762408 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 18:09:15.762459 ==
3133 18:09:15.762510 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 18:09:15.762562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 18:09:15.762613 ==
3136 18:09:15.762686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 18:09:15.762769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3138 18:09:15.762822 [CA 0] Center 37 (7~67) winsize 61
3139 18:09:15.762873 [CA 1] Center 38 (8~68) winsize 61
3140 18:09:15.762924 [CA 2] Center 34 (4~64) winsize 61
3141 18:09:15.762975 [CA 3] Center 33 (3~64) winsize 62
3142 18:09:15.763027 [CA 4] Center 34 (4~64) winsize 61
3143 18:09:15.763078 [CA 5] Center 33 (3~64) winsize 62
3144 18:09:15.763128
3145 18:09:15.763179 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 18:09:15.763230
3147 18:09:15.763281 [CATrainingPosCal] consider 1 rank data
3148 18:09:15.763332 u2DelayCellTimex100 = 270/100 ps
3149 18:09:15.763383 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 18:09:15.763434 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 18:09:15.763485 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 18:09:15.763536 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 18:09:15.763587 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 18:09:15.763638 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3155 18:09:15.763689
3156 18:09:15.763794 CA PerBit enable=1, Macro0, CA PI delay=33
3157 18:09:15.763873
3158 18:09:15.763926 [CBTSetCACLKResult] CA Dly = 33
3159 18:09:15.763978 CS Dly: 5 (0~36)
3160 18:09:15.764029 ==
3161 18:09:15.764081 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 18:09:15.764132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 18:09:15.764184 ==
3164 18:09:15.764236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 18:09:15.764287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3166 18:09:15.764339 [CA 0] Center 37 (7~68) winsize 62
3167 18:09:15.764391 [CA 1] Center 38 (8~68) winsize 61
3168 18:09:15.764442 [CA 2] Center 34 (4~65) winsize 62
3169 18:09:15.764492 [CA 3] Center 33 (3~64) winsize 62
3170 18:09:15.764543 [CA 4] Center 34 (4~65) winsize 62
3171 18:09:15.764594 [CA 5] Center 33 (3~64) winsize 62
3172 18:09:15.764649
3173 18:09:15.764729 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3174 18:09:15.764806
3175 18:09:15.765070 [CATrainingPosCal] consider 2 rank data
3176 18:09:15.765130 u2DelayCellTimex100 = 270/100 ps
3177 18:09:15.765183 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3178 18:09:15.765236 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3179 18:09:15.765288 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3180 18:09:15.765340 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3181 18:09:15.765391 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 18:09:15.765443 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3183 18:09:15.765494
3184 18:09:15.765546 CA PerBit enable=1, Macro0, CA PI delay=33
3185 18:09:15.765598
3186 18:09:15.765649 [CBTSetCACLKResult] CA Dly = 33
3187 18:09:15.765701 CS Dly: 7 (0~40)
3188 18:09:15.765752
3189 18:09:15.765803 ----->DramcWriteLeveling(PI) begin...
3190 18:09:15.765855 ==
3191 18:09:15.765906 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 18:09:15.765957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 18:09:15.766008 ==
3194 18:09:15.766060 Write leveling (Byte 0): 24 => 24
3195 18:09:15.766111 Write leveling (Byte 1): 27 => 27
3196 18:09:15.766172 DramcWriteLeveling(PI) end<-----
3197 18:09:15.766260
3198 18:09:15.766311 ==
3199 18:09:15.766362 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 18:09:15.766414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 18:09:15.766465 ==
3202 18:09:15.766516 [Gating] SW mode calibration
3203 18:09:15.766568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 18:09:15.766622 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 18:09:15.766675 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
3206 18:09:15.766726 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 18:09:15.766778 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 18:09:15.766830 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 18:09:15.766881 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 18:09:15.766932 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 18:09:15.766983 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
3212 18:09:15.767034 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3213 18:09:15.767085 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 18:09:15.767136 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 18:09:15.767187 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 18:09:15.767238 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 18:09:15.767289 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 18:09:15.767339 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 18:09:15.767391 1 0 24 | B1->B0 | 2525 3636 | 0 0 | (1 1) (0 0)
3220 18:09:15.767441 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3221 18:09:15.767492 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 18:09:15.767543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 18:09:15.767594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 18:09:15.767645 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 18:09:15.767696 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 18:09:15.767746 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 18:09:15.767797 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 18:09:15.767848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3229 18:09:15.767899 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3230 18:09:15.767950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 18:09:15.768001 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 18:09:15.768051 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 18:09:15.768102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 18:09:15.768153 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 18:09:15.768204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 18:09:15.768255 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 18:09:15.768306 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 18:09:15.768357 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 18:09:15.768408 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 18:09:15.768459 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 18:09:15.768510 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 18:09:15.768561 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 18:09:15.768612 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3244 18:09:15.768663 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3245 18:09:15.768714 Total UI for P1: 0, mck2ui 16
3246 18:09:15.768765 best dqsien dly found for B0: ( 1, 3, 24)
3247 18:09:15.768817 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 18:09:15.768868 Total UI for P1: 0, mck2ui 16
3249 18:09:15.768919 best dqsien dly found for B1: ( 1, 3, 26)
3250 18:09:15.768970 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3251 18:09:15.769021 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3252 18:09:15.769072
3253 18:09:15.769123 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3254 18:09:15.769175 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3255 18:09:15.769227 [Gating] SW calibration Done
3256 18:09:15.769277 ==
3257 18:09:15.769328 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 18:09:15.769380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 18:09:15.769432 ==
3260 18:09:15.769482 RX Vref Scan: 0
3261 18:09:15.769533
3262 18:09:15.769583 RX Vref 0 -> 0, step: 1
3263 18:09:15.769635
3264 18:09:15.769686 RX Delay -40 -> 252, step: 8
3265 18:09:15.769736 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3266 18:09:15.769788 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3267 18:09:15.769839 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3268 18:09:15.769890 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3269 18:09:15.769941 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3270 18:09:15.769992 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3271 18:09:15.770043 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3272 18:09:15.770093 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3273 18:09:15.770144 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3274 18:09:15.770238 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3275 18:09:15.770290 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3276 18:09:15.770342 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3277 18:09:15.770599 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3278 18:09:15.770692 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3279 18:09:15.770748 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3280 18:09:15.770800 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3281 18:09:15.770853 ==
3282 18:09:15.770905 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 18:09:15.770957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 18:09:15.771010 ==
3285 18:09:15.771061 DQS Delay:
3286 18:09:15.771113 DQS0 = 0, DQS1 = 0
3287 18:09:15.771165 DQM Delay:
3288 18:09:15.771216 DQM0 = 118, DQM1 = 109
3289 18:09:15.771268 DQ Delay:
3290 18:09:15.771319 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3291 18:09:15.771370 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3292 18:09:15.771422 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3293 18:09:15.771473 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3294 18:09:15.771524
3295 18:09:15.771575
3296 18:09:15.771626 ==
3297 18:09:15.771677 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 18:09:15.771729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 18:09:15.771782 ==
3300 18:09:15.771833
3301 18:09:15.771884
3302 18:09:15.771934 TX Vref Scan disable
3303 18:09:15.771985 == TX Byte 0 ==
3304 18:09:15.772036 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3305 18:09:15.772087 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3306 18:09:15.772138 == TX Byte 1 ==
3307 18:09:15.772189 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3308 18:09:15.772241 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3309 18:09:15.772292 ==
3310 18:09:15.772343 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 18:09:15.772394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 18:09:15.772446 ==
3313 18:09:15.772497 TX Vref=22, minBit 9, minWin=25, winSum=420
3314 18:09:15.772549 TX Vref=24, minBit 9, minWin=25, winSum=422
3315 18:09:15.772601 TX Vref=26, minBit 8, minWin=25, winSum=429
3316 18:09:15.772673 TX Vref=28, minBit 10, minWin=26, winSum=435
3317 18:09:15.772728 TX Vref=30, minBit 7, minWin=26, winSum=433
3318 18:09:15.772780 TX Vref=32, minBit 11, minWin=25, winSum=427
3319 18:09:15.772849 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
3320 18:09:15.772915
3321 18:09:15.772966 Final TX Range 1 Vref 28
3322 18:09:15.773018
3323 18:09:15.773068 ==
3324 18:09:15.773119 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 18:09:15.773171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 18:09:15.773222 ==
3327 18:09:15.773274
3328 18:09:15.773324
3329 18:09:15.773375 TX Vref Scan disable
3330 18:09:15.773426 == TX Byte 0 ==
3331 18:09:15.773477 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3332 18:09:15.773528 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3333 18:09:15.773579 == TX Byte 1 ==
3334 18:09:15.773630 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3335 18:09:15.773682 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3336 18:09:15.773732
3337 18:09:15.773782 [DATLAT]
3338 18:09:15.773833 Freq=1200, CH1 RK0
3339 18:09:15.773884
3340 18:09:15.773935 DATLAT Default: 0xd
3341 18:09:15.773985 0, 0xFFFF, sum = 0
3342 18:09:15.774037 1, 0xFFFF, sum = 0
3343 18:09:15.774089 2, 0xFFFF, sum = 0
3344 18:09:15.774140 3, 0xFFFF, sum = 0
3345 18:09:15.774224 4, 0xFFFF, sum = 0
3346 18:09:15.774290 5, 0xFFFF, sum = 0
3347 18:09:15.774342 6, 0xFFFF, sum = 0
3348 18:09:15.774394 7, 0xFFFF, sum = 0
3349 18:09:15.774445 8, 0xFFFF, sum = 0
3350 18:09:15.774497 9, 0xFFFF, sum = 0
3351 18:09:15.774549 10, 0xFFFF, sum = 0
3352 18:09:15.774601 11, 0xFFFF, sum = 0
3353 18:09:15.774652 12, 0x0, sum = 1
3354 18:09:15.774704 13, 0x0, sum = 2
3355 18:09:15.774755 14, 0x0, sum = 3
3356 18:09:15.774806 15, 0x0, sum = 4
3357 18:09:15.774857 best_step = 13
3358 18:09:15.774907
3359 18:09:15.774958 ==
3360 18:09:15.775008 Dram Type= 6, Freq= 0, CH_1, rank 0
3361 18:09:15.775059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3362 18:09:15.775110 ==
3363 18:09:15.775161 RX Vref Scan: 1
3364 18:09:15.775212
3365 18:09:15.775262 Set Vref Range= 32 -> 127
3366 18:09:15.775313
3367 18:09:15.775363 RX Vref 32 -> 127, step: 1
3368 18:09:15.775414
3369 18:09:15.775465 RX Delay -21 -> 252, step: 4
3370 18:09:15.775516
3371 18:09:15.775566 Set Vref, RX VrefLevel [Byte0]: 32
3372 18:09:15.775617 [Byte1]: 32
3373 18:09:15.775667
3374 18:09:15.775718 Set Vref, RX VrefLevel [Byte0]: 33
3375 18:09:15.775769 [Byte1]: 33
3376 18:09:15.775841
3377 18:09:15.775895 Set Vref, RX VrefLevel [Byte0]: 34
3378 18:09:15.775946 [Byte1]: 34
3379 18:09:15.775997
3380 18:09:15.776047 Set Vref, RX VrefLevel [Byte0]: 35
3381 18:09:15.776098 [Byte1]: 35
3382 18:09:15.776149
3383 18:09:15.776199 Set Vref, RX VrefLevel [Byte0]: 36
3384 18:09:15.776251 [Byte1]: 36
3385 18:09:15.776302
3386 18:09:15.776353 Set Vref, RX VrefLevel [Byte0]: 37
3387 18:09:15.776403 [Byte1]: 37
3388 18:09:15.776454
3389 18:09:15.776504 Set Vref, RX VrefLevel [Byte0]: 38
3390 18:09:15.776555 [Byte1]: 38
3391 18:09:15.776605
3392 18:09:15.776656 Set Vref, RX VrefLevel [Byte0]: 39
3393 18:09:15.776707 [Byte1]: 39
3394 18:09:15.776757
3395 18:09:15.776808 Set Vref, RX VrefLevel [Byte0]: 40
3396 18:09:15.776858 [Byte1]: 40
3397 18:09:15.776909
3398 18:09:15.776959 Set Vref, RX VrefLevel [Byte0]: 41
3399 18:09:15.777009 [Byte1]: 41
3400 18:09:15.777059
3401 18:09:15.777109 Set Vref, RX VrefLevel [Byte0]: 42
3402 18:09:15.777159 [Byte1]: 42
3403 18:09:15.777210
3404 18:09:15.777261 Set Vref, RX VrefLevel [Byte0]: 43
3405 18:09:15.777312 [Byte1]: 43
3406 18:09:15.777362
3407 18:09:15.777412 Set Vref, RX VrefLevel [Byte0]: 44
3408 18:09:15.777463 [Byte1]: 44
3409 18:09:15.777513
3410 18:09:15.777563 Set Vref, RX VrefLevel [Byte0]: 45
3411 18:09:15.777614 [Byte1]: 45
3412 18:09:15.777665
3413 18:09:15.777715 Set Vref, RX VrefLevel [Byte0]: 46
3414 18:09:15.777766 [Byte1]: 46
3415 18:09:15.777816
3416 18:09:15.777866 Set Vref, RX VrefLevel [Byte0]: 47
3417 18:09:15.777917 [Byte1]: 47
3418 18:09:15.777969
3419 18:09:15.778020 Set Vref, RX VrefLevel [Byte0]: 48
3420 18:09:15.778070 [Byte1]: 48
3421 18:09:15.778120
3422 18:09:15.778199 Set Vref, RX VrefLevel [Byte0]: 49
3423 18:09:15.778266 [Byte1]: 49
3424 18:09:15.778316
3425 18:09:15.778367 Set Vref, RX VrefLevel [Byte0]: 50
3426 18:09:15.778418 [Byte1]: 50
3427 18:09:15.778468
3428 18:09:15.778518 Set Vref, RX VrefLevel [Byte0]: 51
3429 18:09:15.778570 [Byte1]: 51
3430 18:09:15.778620
3431 18:09:15.778670 Set Vref, RX VrefLevel [Byte0]: 52
3432 18:09:15.778721 [Byte1]: 52
3433 18:09:15.778772
3434 18:09:15.778822 Set Vref, RX VrefLevel [Byte0]: 53
3435 18:09:15.778873 [Byte1]: 53
3436 18:09:15.778923
3437 18:09:15.778980 Set Vref, RX VrefLevel [Byte0]: 54
3438 18:09:15.779042 [Byte1]: 54
3439 18:09:15.779093
3440 18:09:15.779144 Set Vref, RX VrefLevel [Byte0]: 55
3441 18:09:15.779194 [Byte1]: 55
3442 18:09:15.779244
3443 18:09:15.779502 Set Vref, RX VrefLevel [Byte0]: 56
3444 18:09:15.779559 [Byte1]: 56
3445 18:09:15.779611
3446 18:09:15.779662 Set Vref, RX VrefLevel [Byte0]: 57
3447 18:09:15.779712 [Byte1]: 57
3448 18:09:15.779762
3449 18:09:15.779813 Set Vref, RX VrefLevel [Byte0]: 58
3450 18:09:15.779863 [Byte1]: 58
3451 18:09:15.779914
3452 18:09:15.779964 Set Vref, RX VrefLevel [Byte0]: 59
3453 18:09:15.780014 [Byte1]: 59
3454 18:09:15.780065
3455 18:09:15.780115 Set Vref, RX VrefLevel [Byte0]: 60
3456 18:09:15.780165 [Byte1]: 60
3457 18:09:15.780215
3458 18:09:15.780266 Set Vref, RX VrefLevel [Byte0]: 61
3459 18:09:15.780316 [Byte1]: 61
3460 18:09:15.780367
3461 18:09:15.780418 Set Vref, RX VrefLevel [Byte0]: 62
3462 18:09:15.780469 [Byte1]: 62
3463 18:09:15.780519
3464 18:09:15.780569 Set Vref, RX VrefLevel [Byte0]: 63
3465 18:09:15.780619 [Byte1]: 63
3466 18:09:15.780669
3467 18:09:15.780734 Set Vref, RX VrefLevel [Byte0]: 64
3468 18:09:15.780786 [Byte1]: 64
3469 18:09:15.780836
3470 18:09:15.780886 Set Vref, RX VrefLevel [Byte0]: 65
3471 18:09:15.780937 [Byte1]: 65
3472 18:09:15.780987
3473 18:09:15.781037 Set Vref, RX VrefLevel [Byte0]: 66
3474 18:09:15.781088 [Byte1]: 66
3475 18:09:15.781138
3476 18:09:15.781189 Set Vref, RX VrefLevel [Byte0]: 67
3477 18:09:15.781239 [Byte1]: 67
3478 18:09:15.781290
3479 18:09:15.781340 Final RX Vref Byte 0 = 48 to rank0
3480 18:09:15.781391 Final RX Vref Byte 1 = 54 to rank0
3481 18:09:15.781442 Final RX Vref Byte 0 = 48 to rank1
3482 18:09:15.781493 Final RX Vref Byte 1 = 54 to rank1==
3483 18:09:15.781544 Dram Type= 6, Freq= 0, CH_1, rank 0
3484 18:09:15.781595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 18:09:15.781646 ==
3486 18:09:15.781697 DQS Delay:
3487 18:09:15.781747 DQS0 = 0, DQS1 = 0
3488 18:09:15.781798 DQM Delay:
3489 18:09:15.781848 DQM0 = 116, DQM1 = 110
3490 18:09:15.781899 DQ Delay:
3491 18:09:15.781949 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3492 18:09:15.782000 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3493 18:09:15.782051 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3494 18:09:15.782108 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3495 18:09:15.782230
3496 18:09:15.782283
3497 18:09:15.782335 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3498 18:09:15.782388 CH1 RK0: MR19=403, MR18=3F6
3499 18:09:15.782439 CH1_RK0: MR19=0x403, MR18=0x3F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3500 18:09:15.782491
3501 18:09:15.782551 ----->DramcWriteLeveling(PI) begin...
3502 18:09:15.782613 ==
3503 18:09:15.782665 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 18:09:15.782716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 18:09:15.782768 ==
3506 18:09:15.782819 Write leveling (Byte 0): 25 => 25
3507 18:09:15.782870 Write leveling (Byte 1): 28 => 28
3508 18:09:15.782920 DramcWriteLeveling(PI) end<-----
3509 18:09:15.782971
3510 18:09:15.783022 ==
3511 18:09:15.783072 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 18:09:15.783122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 18:09:15.783174 ==
3514 18:09:15.783224 [Gating] SW mode calibration
3515 18:09:15.783275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3516 18:09:15.783327 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3517 18:09:15.783378 0 15 0 | B1->B0 | 3434 3332 | 1 1 | (1 1) (1 1)
3518 18:09:15.783429 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 18:09:15.783480 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 18:09:15.783532 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 18:09:15.783583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 18:09:15.783633 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 18:09:15.783685 0 15 24 | B1->B0 | 3333 3434 | 0 0 | (1 0) (0 1)
3524 18:09:15.783735 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (0 0)
3525 18:09:15.783785 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 18:09:15.783836 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 18:09:15.783887 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 18:09:15.783938 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 18:09:15.783989 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 18:09:15.784040 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 18:09:15.784091 1 0 24 | B1->B0 | 3939 2525 | 0 0 | (0 0) (1 1)
3532 18:09:15.784142 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3533 18:09:15.784192 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 18:09:15.784242 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 18:09:15.784293 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 18:09:15.784343 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 18:09:15.784394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 18:09:15.784445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 18:09:15.784496 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3540 18:09:15.784546 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3541 18:09:15.784597 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 18:09:15.784647 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 18:09:15.784698 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 18:09:15.784748 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 18:09:15.784799 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 18:09:15.784849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 18:09:15.784899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 18:09:15.784950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 18:09:15.785000 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 18:09:15.785051 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 18:09:15.785100 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 18:09:15.785151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 18:09:15.785201 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 18:09:15.785252 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 18:09:15.785302 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3556 18:09:15.785555 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3557 18:09:15.785613 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 18:09:15.785666 Total UI for P1: 0, mck2ui 16
3559 18:09:15.785718 best dqsien dly found for B0: ( 1, 3, 28)
3560 18:09:15.785770 Total UI for P1: 0, mck2ui 16
3561 18:09:15.785821 best dqsien dly found for B1: ( 1, 3, 26)
3562 18:09:15.785872 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3563 18:09:15.785923 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3564 18:09:15.785974
3565 18:09:15.786025 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3566 18:09:15.786077 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 18:09:15.786193 [Gating] SW calibration Done
3568 18:09:15.786263 ==
3569 18:09:15.786315 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 18:09:15.786367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 18:09:15.786418 ==
3572 18:09:15.786469 RX Vref Scan: 0
3573 18:09:15.786521
3574 18:09:15.786572 RX Vref 0 -> 0, step: 1
3575 18:09:15.786623
3576 18:09:15.786673 RX Delay -40 -> 252, step: 8
3577 18:09:15.786724 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3578 18:09:15.786775 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3579 18:09:15.786826 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3580 18:09:15.786877 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3581 18:09:15.786928 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3582 18:09:15.786978 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3583 18:09:15.787028 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3584 18:09:15.787078 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3585 18:09:15.787129 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3586 18:09:15.787180 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3587 18:09:15.787231 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3588 18:09:15.787281 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3589 18:09:15.787332 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3590 18:09:15.787383 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3591 18:09:15.787433 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3592 18:09:15.787483 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3593 18:09:15.787534 ==
3594 18:09:15.787585 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 18:09:15.787636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 18:09:15.787687 ==
3597 18:09:15.787738 DQS Delay:
3598 18:09:15.787789 DQS0 = 0, DQS1 = 0
3599 18:09:15.787840 DQM Delay:
3600 18:09:15.787891 DQM0 = 116, DQM1 = 110
3601 18:09:15.787942 DQ Delay:
3602 18:09:15.787992 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3603 18:09:15.788043 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3604 18:09:15.788094 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3605 18:09:15.788145 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3606 18:09:15.788195
3607 18:09:15.788246
3608 18:09:15.788295 ==
3609 18:09:15.788346 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 18:09:15.788396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 18:09:15.788447 ==
3612 18:09:15.788497
3613 18:09:15.788548
3614 18:09:15.788598 TX Vref Scan disable
3615 18:09:15.788649 == TX Byte 0 ==
3616 18:09:15.788700 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3617 18:09:15.788751 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3618 18:09:15.788801 == TX Byte 1 ==
3619 18:09:15.788851 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3620 18:09:15.788902 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3621 18:09:15.788952 ==
3622 18:09:15.789003 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 18:09:15.789054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 18:09:15.789105 ==
3625 18:09:15.789155 TX Vref=22, minBit 1, minWin=26, winSum=426
3626 18:09:15.789220 TX Vref=24, minBit 3, minWin=26, winSum=430
3627 18:09:15.789275 TX Vref=26, minBit 8, minWin=26, winSum=430
3628 18:09:15.789326 TX Vref=28, minBit 9, minWin=26, winSum=435
3629 18:09:15.789377 TX Vref=30, minBit 9, minWin=26, winSum=438
3630 18:09:15.789428 TX Vref=32, minBit 7, minWin=26, winSum=431
3631 18:09:15.789479 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3632 18:09:15.789530
3633 18:09:15.789581 Final TX Range 1 Vref 30
3634 18:09:15.789632
3635 18:09:15.789682 ==
3636 18:09:15.789733 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 18:09:15.789784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 18:09:15.789836 ==
3639 18:09:15.789887
3640 18:09:15.789937
3641 18:09:15.789987 TX Vref Scan disable
3642 18:09:15.790038 == TX Byte 0 ==
3643 18:09:15.790088 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3644 18:09:15.790139 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3645 18:09:15.790243 == TX Byte 1 ==
3646 18:09:15.790296 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3647 18:09:15.790347 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3648 18:09:15.790398
3649 18:09:15.790449 [DATLAT]
3650 18:09:15.790500 Freq=1200, CH1 RK1
3651 18:09:15.790551
3652 18:09:15.790602 DATLAT Default: 0xd
3653 18:09:15.790652 0, 0xFFFF, sum = 0
3654 18:09:15.790704 1, 0xFFFF, sum = 0
3655 18:09:15.790757 2, 0xFFFF, sum = 0
3656 18:09:15.790809 3, 0xFFFF, sum = 0
3657 18:09:15.790860 4, 0xFFFF, sum = 0
3658 18:09:15.790911 5, 0xFFFF, sum = 0
3659 18:09:15.790963 6, 0xFFFF, sum = 0
3660 18:09:15.791015 7, 0xFFFF, sum = 0
3661 18:09:15.791065 8, 0xFFFF, sum = 0
3662 18:09:15.791117 9, 0xFFFF, sum = 0
3663 18:09:15.791168 10, 0xFFFF, sum = 0
3664 18:09:15.791220 11, 0xFFFF, sum = 0
3665 18:09:15.791271 12, 0x0, sum = 1
3666 18:09:15.791322 13, 0x0, sum = 2
3667 18:09:15.791373 14, 0x0, sum = 3
3668 18:09:15.791424 15, 0x0, sum = 4
3669 18:09:15.791475 best_step = 13
3670 18:09:15.791525
3671 18:09:15.791575 ==
3672 18:09:15.791625 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 18:09:15.791676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 18:09:15.791727 ==
3675 18:09:15.791778 RX Vref Scan: 0
3676 18:09:15.791829
3677 18:09:15.791878 RX Vref 0 -> 0, step: 1
3678 18:09:15.791929
3679 18:09:15.791979 RX Delay -21 -> 252, step: 4
3680 18:09:15.792030 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3681 18:09:15.792081 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3682 18:09:15.792131 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3683 18:09:15.792207 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3684 18:09:15.792313 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3685 18:09:15.792388 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3686 18:09:15.792476 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3687 18:09:15.792528 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3688 18:09:15.792580 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3689 18:09:15.792631 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3690 18:09:15.792681 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3691 18:09:15.792732 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3692 18:09:15.792783 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3693 18:09:15.792833 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3694 18:09:15.793090 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3695 18:09:15.793152 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3696 18:09:15.793205 ==
3697 18:09:15.793257 Dram Type= 6, Freq= 0, CH_1, rank 1
3698 18:09:15.793309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3699 18:09:15.793361 ==
3700 18:09:15.793412 DQS Delay:
3701 18:09:15.793463 DQS0 = 0, DQS1 = 0
3702 18:09:15.793514 DQM Delay:
3703 18:09:15.793565 DQM0 = 116, DQM1 = 110
3704 18:09:15.793616 DQ Delay:
3705 18:09:15.793666 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3706 18:09:15.793717 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3707 18:09:15.793768 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3708 18:09:15.793819 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3709 18:09:15.793869
3710 18:09:15.793920
3711 18:09:15.793970 [DQSOSCAuto] RK1, (LSB)MR18= 0xefea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 417 ps
3712 18:09:15.794023 CH1 RK1: MR19=303, MR18=EFEA
3713 18:09:15.794074 CH1_RK1: MR19=0x303, MR18=0xEFEA, DQSOSC=417, MR23=63, INC=37, DEC=25
3714 18:09:15.794125 [RxdqsGatingPostProcess] freq 1200
3715 18:09:15.794209 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3716 18:09:15.794276 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 18:09:15.794327 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 18:09:15.794378 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 18:09:15.794428 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 18:09:15.794478 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 18:09:15.794529 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 18:09:15.794578 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 18:09:15.794628 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 18:09:15.794678 Pre-setting of DQS Precalculation
3725 18:09:15.794729 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3726 18:09:15.794780 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3727 18:09:15.794831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3728 18:09:15.794882
3729 18:09:15.794932
3730 18:09:15.794982 [Calibration Summary] 2400 Mbps
3731 18:09:15.795033 CH 0, Rank 0
3732 18:09:15.795083 SW Impedance : PASS
3733 18:09:15.795134 DUTY Scan : NO K
3734 18:09:15.795185 ZQ Calibration : PASS
3735 18:09:15.795236 Jitter Meter : NO K
3736 18:09:15.795287 CBT Training : PASS
3737 18:09:15.795337 Write leveling : PASS
3738 18:09:15.795387 RX DQS gating : PASS
3739 18:09:15.795438 RX DQ/DQS(RDDQC) : PASS
3740 18:09:15.795488 TX DQ/DQS : PASS
3741 18:09:15.795608 RX DATLAT : PASS
3742 18:09:15.795711 RX DQ/DQS(Engine): PASS
3743 18:09:15.795766 TX OE : NO K
3744 18:09:15.795818 All Pass.
3745 18:09:15.795870
3746 18:09:15.795920 CH 0, Rank 1
3747 18:09:15.795971 SW Impedance : PASS
3748 18:09:15.796022 DUTY Scan : NO K
3749 18:09:15.796073 ZQ Calibration : PASS
3750 18:09:15.796123 Jitter Meter : NO K
3751 18:09:15.796174 CBT Training : PASS
3752 18:09:15.796224 Write leveling : PASS
3753 18:09:15.796275 RX DQS gating : PASS
3754 18:09:15.796326 RX DQ/DQS(RDDQC) : PASS
3755 18:09:15.796377 TX DQ/DQS : PASS
3756 18:09:15.796427 RX DATLAT : PASS
3757 18:09:15.796478 RX DQ/DQS(Engine): PASS
3758 18:09:15.796528 TX OE : NO K
3759 18:09:15.796579 All Pass.
3760 18:09:15.796629
3761 18:09:15.796680 CH 1, Rank 0
3762 18:09:15.796730 SW Impedance : PASS
3763 18:09:15.796781 DUTY Scan : NO K
3764 18:09:15.796831 ZQ Calibration : PASS
3765 18:09:15.796882 Jitter Meter : NO K
3766 18:09:15.796933 CBT Training : PASS
3767 18:09:15.796983 Write leveling : PASS
3768 18:09:15.797034 RX DQS gating : PASS
3769 18:09:15.797084 RX DQ/DQS(RDDQC) : PASS
3770 18:09:15.797134 TX DQ/DQS : PASS
3771 18:09:15.797185 RX DATLAT : PASS
3772 18:09:15.797238 RX DQ/DQS(Engine): PASS
3773 18:09:15.797289 TX OE : NO K
3774 18:09:15.797340 All Pass.
3775 18:09:15.797391
3776 18:09:15.797441 CH 1, Rank 1
3777 18:09:15.797491 SW Impedance : PASS
3778 18:09:15.797542 DUTY Scan : NO K
3779 18:09:15.797599 ZQ Calibration : PASS
3780 18:09:15.797693 Jitter Meter : NO K
3781 18:09:15.797786 CBT Training : PASS
3782 18:09:15.797840 Write leveling : PASS
3783 18:09:15.797905 RX DQS gating : PASS
3784 18:09:15.797955 RX DQ/DQS(RDDQC) : PASS
3785 18:09:15.798006 TX DQ/DQS : PASS
3786 18:09:15.798056 RX DATLAT : PASS
3787 18:09:15.798107 RX DQ/DQS(Engine): PASS
3788 18:09:15.798157 TX OE : NO K
3789 18:09:15.798250 All Pass.
3790 18:09:15.798301
3791 18:09:15.798351 DramC Write-DBI off
3792 18:09:15.798403 PER_BANK_REFRESH: Hybrid Mode
3793 18:09:15.798454 TX_TRACKING: ON
3794 18:09:15.798504 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3795 18:09:15.798556 [FAST_K] Save calibration result to emmc
3796 18:09:15.798607 dramc_set_vcore_voltage set vcore to 650000
3797 18:09:15.798657 Read voltage for 600, 5
3798 18:09:15.798708 Vio18 = 0
3799 18:09:15.798759 Vcore = 650000
3800 18:09:15.798809 Vdram = 0
3801 18:09:15.798860 Vddq = 0
3802 18:09:15.798910 Vmddr = 0
3803 18:09:15.798961 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3804 18:09:15.799012 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3805 18:09:15.799064 MEM_TYPE=3, freq_sel=19
3806 18:09:15.799115 sv_algorithm_assistance_LP4_1600
3807 18:09:15.799172 ============ PULL DRAM RESETB DOWN ============
3808 18:09:15.799244 ========== PULL DRAM RESETB DOWN end =========
3809 18:09:15.799299 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3810 18:09:15.799358 ===================================
3811 18:09:15.799409 LPDDR4 DRAM CONFIGURATION
3812 18:09:15.799460 ===================================
3813 18:09:15.799510 EX_ROW_EN[0] = 0x0
3814 18:09:15.799561 EX_ROW_EN[1] = 0x0
3815 18:09:15.799611 LP4Y_EN = 0x0
3816 18:09:15.799662 WORK_FSP = 0x0
3817 18:09:15.799712 WL = 0x2
3818 18:09:15.799762 RL = 0x2
3819 18:09:15.799813 BL = 0x2
3820 18:09:15.799864 RPST = 0x0
3821 18:09:15.799914 RD_PRE = 0x0
3822 18:09:15.799965 WR_PRE = 0x1
3823 18:09:15.800015 WR_PST = 0x0
3824 18:09:15.800066 DBI_WR = 0x0
3825 18:09:15.800116 DBI_RD = 0x0
3826 18:09:15.800166 OTF = 0x1
3827 18:09:15.800217 ===================================
3828 18:09:15.800268 ===================================
3829 18:09:15.800319 ANA top config
3830 18:09:15.800369 ===================================
3831 18:09:15.800419 DLL_ASYNC_EN = 0
3832 18:09:15.800470 ALL_SLAVE_EN = 1
3833 18:09:15.800520 NEW_RANK_MODE = 1
3834 18:09:15.800571 DLL_IDLE_MODE = 1
3835 18:09:15.800622 LP45_APHY_COMB_EN = 1
3836 18:09:15.800672 TX_ODT_DIS = 1
3837 18:09:15.800723 NEW_8X_MODE = 1
3838 18:09:15.800774 ===================================
3839 18:09:15.800825 ===================================
3840 18:09:15.801080 data_rate = 1200
3841 18:09:15.801137 CKR = 1
3842 18:09:15.801189 DQ_P2S_RATIO = 8
3843 18:09:15.801240 ===================================
3844 18:09:15.801292 CA_P2S_RATIO = 8
3845 18:09:15.801342 DQ_CA_OPEN = 0
3846 18:09:15.801393 DQ_SEMI_OPEN = 0
3847 18:09:15.802436 CA_SEMI_OPEN = 0
3848 18:09:15.806317 CA_FULL_RATE = 0
3849 18:09:15.809135 DQ_CKDIV4_EN = 1
3850 18:09:15.809216 CA_CKDIV4_EN = 1
3851 18:09:15.812658 CA_PREDIV_EN = 0
3852 18:09:15.815498 PH8_DLY = 0
3853 18:09:15.818743 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3854 18:09:15.822150 DQ_AAMCK_DIV = 4
3855 18:09:15.825238 CA_AAMCK_DIV = 4
3856 18:09:15.828926 CA_ADMCK_DIV = 4
3857 18:09:15.829011 DQ_TRACK_CA_EN = 0
3858 18:09:15.832058 CA_PICK = 600
3859 18:09:15.835405 CA_MCKIO = 600
3860 18:09:15.838940 MCKIO_SEMI = 0
3861 18:09:15.841951 PLL_FREQ = 2288
3862 18:09:15.845121 DQ_UI_PI_RATIO = 32
3863 18:09:15.848418 CA_UI_PI_RATIO = 0
3864 18:09:15.852394 ===================================
3865 18:09:15.855150 ===================================
3866 18:09:15.855235 memory_type:LPDDR4
3867 18:09:15.858388 GP_NUM : 10
3868 18:09:15.862001 SRAM_EN : 1
3869 18:09:15.862084 MD32_EN : 0
3870 18:09:15.865018 ===================================
3871 18:09:15.868197 [ANA_INIT] >>>>>>>>>>>>>>
3872 18:09:15.871669 <<<<<< [CONFIGURE PHASE]: ANA_TX
3873 18:09:15.875284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3874 18:09:15.878273 ===================================
3875 18:09:15.881446 data_rate = 1200,PCW = 0X5800
3876 18:09:15.884795 ===================================
3877 18:09:15.888318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3878 18:09:15.891226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 18:09:15.897872 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 18:09:15.901147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3881 18:09:15.904735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3882 18:09:15.911087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3883 18:09:15.911196 [ANA_INIT] flow start
3884 18:09:15.914555 [ANA_INIT] PLL >>>>>>>>
3885 18:09:15.917372 [ANA_INIT] PLL <<<<<<<<
3886 18:09:15.917456 [ANA_INIT] MIDPI >>>>>>>>
3887 18:09:15.921110 [ANA_INIT] MIDPI <<<<<<<<
3888 18:09:15.924219 [ANA_INIT] DLL >>>>>>>>
3889 18:09:15.924305 [ANA_INIT] flow end
3890 18:09:15.927294 ============ LP4 DIFF to SE enter ============
3891 18:09:15.934001 ============ LP4 DIFF to SE exit ============
3892 18:09:15.934125 [ANA_INIT] <<<<<<<<<<<<<
3893 18:09:15.937481 [Flow] Enable top DCM control >>>>>
3894 18:09:15.940595 [Flow] Enable top DCM control <<<<<
3895 18:09:15.943695 Enable DLL master slave shuffle
3896 18:09:15.950685 ==============================================================
3897 18:09:15.953897 Gating Mode config
3898 18:09:15.957291 ==============================================================
3899 18:09:15.960732 Config description:
3900 18:09:15.970474 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3901 18:09:15.977246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3902 18:09:15.979944 SELPH_MODE 0: By rank 1: By Phase
3903 18:09:15.986971 ==============================================================
3904 18:09:15.989959 GAT_TRACK_EN = 1
3905 18:09:15.993808 RX_GATING_MODE = 2
3906 18:09:15.996465 RX_GATING_TRACK_MODE = 2
3907 18:09:15.999828 SELPH_MODE = 1
3908 18:09:15.999955 PICG_EARLY_EN = 1
3909 18:09:16.003317 VALID_LAT_VALUE = 1
3910 18:09:16.009456 ==============================================================
3911 18:09:16.012650 Enter into Gating configuration >>>>
3912 18:09:16.016150 Exit from Gating configuration <<<<
3913 18:09:16.019365 Enter into DVFS_PRE_config >>>>>
3914 18:09:16.029640 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3915 18:09:16.032865 Exit from DVFS_PRE_config <<<<<
3916 18:09:16.036100 Enter into PICG configuration >>>>
3917 18:09:16.039157 Exit from PICG configuration <<<<
3918 18:09:16.042669 [RX_INPUT] configuration >>>>>
3919 18:09:16.045770 [RX_INPUT] configuration <<<<<
3920 18:09:16.052897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3921 18:09:16.056083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3922 18:09:16.062137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 18:09:16.069654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 18:09:16.075811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 18:09:16.082329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 18:09:16.085513 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3927 18:09:16.089046 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3928 18:09:16.091960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3929 18:09:16.098682 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3930 18:09:16.102295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3931 18:09:16.105009 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 18:09:16.108680 ===================================
3933 18:09:16.111663 LPDDR4 DRAM CONFIGURATION
3934 18:09:16.115588 ===================================
3935 18:09:16.118437 EX_ROW_EN[0] = 0x0
3936 18:09:16.118523 EX_ROW_EN[1] = 0x0
3937 18:09:16.121875 LP4Y_EN = 0x0
3938 18:09:16.121983 WORK_FSP = 0x0
3939 18:09:16.125015 WL = 0x2
3940 18:09:16.125096 RL = 0x2
3941 18:09:16.128228 BL = 0x2
3942 18:09:16.128309 RPST = 0x0
3943 18:09:16.131966 RD_PRE = 0x0
3944 18:09:16.132051 WR_PRE = 0x1
3945 18:09:16.134844 WR_PST = 0x0
3946 18:09:16.134925 DBI_WR = 0x0
3947 18:09:16.138010 DBI_RD = 0x0
3948 18:09:16.138116 OTF = 0x1
3949 18:09:16.141418 ===================================
3950 18:09:16.148014 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3951 18:09:16.151233 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3952 18:09:16.154575 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 18:09:16.157886 ===================================
3954 18:09:16.161664 LPDDR4 DRAM CONFIGURATION
3955 18:09:16.164670 ===================================
3956 18:09:16.168034 EX_ROW_EN[0] = 0x10
3957 18:09:16.168117 EX_ROW_EN[1] = 0x0
3958 18:09:16.171189 LP4Y_EN = 0x0
3959 18:09:16.171271 WORK_FSP = 0x0
3960 18:09:16.174345 WL = 0x2
3961 18:09:16.174427 RL = 0x2
3962 18:09:16.177634 BL = 0x2
3963 18:09:16.177715 RPST = 0x0
3964 18:09:16.180913 RD_PRE = 0x0
3965 18:09:16.181020 WR_PRE = 0x1
3966 18:09:16.184464 WR_PST = 0x0
3967 18:09:16.184545 DBI_WR = 0x0
3968 18:09:16.187759 DBI_RD = 0x0
3969 18:09:16.187840 OTF = 0x1
3970 18:09:16.190964 ===================================
3971 18:09:16.197539 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3972 18:09:16.202588 nWR fixed to 30
3973 18:09:16.206094 [ModeRegInit_LP4] CH0 RK0
3974 18:09:16.206229 [ModeRegInit_LP4] CH0 RK1
3975 18:09:16.208879 [ModeRegInit_LP4] CH1 RK0
3976 18:09:16.212149 [ModeRegInit_LP4] CH1 RK1
3977 18:09:16.212231 match AC timing 17
3978 18:09:16.218870 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3979 18:09:16.222365 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3980 18:09:16.225541 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3981 18:09:16.232074 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3982 18:09:16.235136 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3983 18:09:16.235256 ==
3984 18:09:16.238939 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 18:09:16.242358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 18:09:16.242470 ==
3987 18:09:16.248418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 18:09:16.255124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3989 18:09:16.258325 [CA 0] Center 36 (6~66) winsize 61
3990 18:09:16.261691 [CA 1] Center 36 (6~66) winsize 61
3991 18:09:16.265079 [CA 2] Center 34 (4~65) winsize 62
3992 18:09:16.268052 [CA 3] Center 34 (4~65) winsize 62
3993 18:09:16.271340 [CA 4] Center 34 (4~64) winsize 61
3994 18:09:16.274567 [CA 5] Center 33 (3~64) winsize 62
3995 18:09:16.274683
3996 18:09:16.277840 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3997 18:09:16.277949
3998 18:09:16.281201 [CATrainingPosCal] consider 1 rank data
3999 18:09:16.284482 u2DelayCellTimex100 = 270/100 ps
4000 18:09:16.288157 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4001 18:09:16.291771 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 18:09:16.294488 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 18:09:16.301023 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 18:09:16.304460 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 18:09:16.307425 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 18:09:16.307545
4007 18:09:16.310828 CA PerBit enable=1, Macro0, CA PI delay=33
4008 18:09:16.310939
4009 18:09:16.314041 [CBTSetCACLKResult] CA Dly = 33
4010 18:09:16.314151 CS Dly: 5 (0~36)
4011 18:09:16.314287 ==
4012 18:09:16.317427 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 18:09:16.323789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 18:09:16.323919 ==
4015 18:09:16.327506 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4016 18:09:16.334438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4017 18:09:16.337865 [CA 0] Center 36 (6~66) winsize 61
4018 18:09:16.341137 [CA 1] Center 36 (6~66) winsize 61
4019 18:09:16.344106 [CA 2] Center 33 (3~64) winsize 62
4020 18:09:16.347435 [CA 3] Center 33 (3~64) winsize 62
4021 18:09:16.350882 [CA 4] Center 33 (3~64) winsize 62
4022 18:09:16.354192 [CA 5] Center 33 (2~64) winsize 63
4023 18:09:16.354320
4024 18:09:16.357479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4025 18:09:16.357589
4026 18:09:16.360917 [CATrainingPosCal] consider 2 rank data
4027 18:09:16.364484 u2DelayCellTimex100 = 270/100 ps
4028 18:09:16.367193 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 18:09:16.373993 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 18:09:16.377610 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4031 18:09:16.381091 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4032 18:09:16.383466 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4033 18:09:16.387235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 18:09:16.387346
4035 18:09:16.390429 CA PerBit enable=1, Macro0, CA PI delay=33
4036 18:09:16.390537
4037 18:09:16.393859 [CBTSetCACLKResult] CA Dly = 33
4038 18:09:16.396648 CS Dly: 5 (0~37)
4039 18:09:16.396757
4040 18:09:16.400133 ----->DramcWriteLeveling(PI) begin...
4041 18:09:16.400248 ==
4042 18:09:16.403848 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 18:09:16.406589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 18:09:16.406699 ==
4045 18:09:16.410093 Write leveling (Byte 0): 35 => 35
4046 18:09:16.413072 Write leveling (Byte 1): 30 => 30
4047 18:09:16.416539 DramcWriteLeveling(PI) end<-----
4048 18:09:16.416653
4049 18:09:16.416747 ==
4050 18:09:16.419711 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 18:09:16.423079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 18:09:16.423193 ==
4053 18:09:16.426837 [Gating] SW mode calibration
4054 18:09:16.433182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4055 18:09:16.439551 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4056 18:09:16.442935 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 18:09:16.449590 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 18:09:16.452608 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 18:09:16.455995 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4060 18:09:16.462451 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
4061 18:09:16.465658 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 18:09:16.468917 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 18:09:16.475544 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 18:09:16.478728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 18:09:16.482529 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 18:09:16.488855 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 18:09:16.492043 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 18:09:16.495342 0 10 16 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
4069 18:09:16.502106 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 18:09:16.505352 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 18:09:16.508349 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 18:09:16.514929 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 18:09:16.518432 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 18:09:16.521687 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 18:09:16.528615 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 18:09:16.531381 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4077 18:09:16.535093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 18:09:16.541340 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 18:09:16.544638 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 18:09:16.547953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 18:09:16.555001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 18:09:16.557727 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 18:09:16.561226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 18:09:16.567818 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 18:09:16.570841 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 18:09:16.574451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 18:09:16.580864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 18:09:16.584011 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 18:09:16.587666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 18:09:16.594186 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 18:09:16.597995 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 18:09:16.601209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4093 18:09:16.607506 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 18:09:16.607646 Total UI for P1: 0, mck2ui 16
4095 18:09:16.614077 best dqsien dly found for B0: ( 0, 13, 16)
4096 18:09:16.614250 Total UI for P1: 0, mck2ui 16
4097 18:09:16.620432 best dqsien dly found for B1: ( 0, 13, 16)
4098 18:09:16.623650 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4099 18:09:16.626985 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4100 18:09:16.627101
4101 18:09:16.630710 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4102 18:09:16.633969 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4103 18:09:16.637351 [Gating] SW calibration Done
4104 18:09:16.637469 ==
4105 18:09:16.640355 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 18:09:16.643643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 18:09:16.643759 ==
4108 18:09:16.647018 RX Vref Scan: 0
4109 18:09:16.647129
4110 18:09:16.647224 RX Vref 0 -> 0, step: 1
4111 18:09:16.647314
4112 18:09:16.650349 RX Delay -230 -> 252, step: 16
4113 18:09:16.656937 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4114 18:09:16.660221 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4115 18:09:16.663464 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4116 18:09:16.666783 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4117 18:09:16.673362 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4118 18:09:16.676608 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4119 18:09:16.680270 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4120 18:09:16.683327 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4121 18:09:16.686483 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4122 18:09:16.693163 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4123 18:09:16.696246 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4124 18:09:16.699868 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4125 18:09:16.703071 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4126 18:09:16.709972 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4127 18:09:16.713152 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4128 18:09:16.716568 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4129 18:09:16.716665 ==
4130 18:09:16.719733 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 18:09:16.726072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 18:09:16.726209 ==
4133 18:09:16.726298 DQS Delay:
4134 18:09:16.726376 DQS0 = 0, DQS1 = 0
4135 18:09:16.729011 DQM Delay:
4136 18:09:16.729094 DQM0 = 44, DQM1 = 31
4137 18:09:16.732641 DQ Delay:
4138 18:09:16.735904 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4139 18:09:16.739384 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4140 18:09:16.742381 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4141 18:09:16.746099 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4142 18:09:16.746249
4143 18:09:16.746334
4144 18:09:16.746426 ==
4145 18:09:16.749267 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 18:09:16.752074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 18:09:16.752188 ==
4148 18:09:16.752288
4149 18:09:16.752385
4150 18:09:16.755891 TX Vref Scan disable
4151 18:09:16.758703 == TX Byte 0 ==
4152 18:09:16.762089 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4153 18:09:16.765466 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4154 18:09:16.768749 == TX Byte 1 ==
4155 18:09:16.771946 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4156 18:09:16.775056 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4157 18:09:16.775150 ==
4158 18:09:16.778576 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 18:09:16.781857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 18:09:16.784847 ==
4161 18:09:16.784943
4162 18:09:16.785029
4163 18:09:16.785126 TX Vref Scan disable
4164 18:09:16.789037 == TX Byte 0 ==
4165 18:09:16.792346 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4166 18:09:16.799557 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4167 18:09:16.799720 == TX Byte 1 ==
4168 18:09:16.802192 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4169 18:09:16.808805 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4170 18:09:16.808951
4171 18:09:16.809048 [DATLAT]
4172 18:09:16.809138 Freq=600, CH0 RK0
4173 18:09:16.809227
4174 18:09:16.812148 DATLAT Default: 0x9
4175 18:09:16.815287 0, 0xFFFF, sum = 0
4176 18:09:16.815375 1, 0xFFFF, sum = 0
4177 18:09:16.818598 2, 0xFFFF, sum = 0
4178 18:09:16.818683 3, 0xFFFF, sum = 0
4179 18:09:16.822203 4, 0xFFFF, sum = 0
4180 18:09:16.822302 5, 0xFFFF, sum = 0
4181 18:09:16.825487 6, 0xFFFF, sum = 0
4182 18:09:16.825573 7, 0xFFFF, sum = 0
4183 18:09:16.828754 8, 0x0, sum = 1
4184 18:09:16.828838 9, 0x0, sum = 2
4185 18:09:16.832251 10, 0x0, sum = 3
4186 18:09:16.832337 11, 0x0, sum = 4
4187 18:09:16.832403 best_step = 9
4188 18:09:16.832464
4189 18:09:16.835298 ==
4190 18:09:16.838326 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 18:09:16.841820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 18:09:16.841930 ==
4193 18:09:16.842021 RX Vref Scan: 1
4194 18:09:16.842108
4195 18:09:16.845063 RX Vref 0 -> 0, step: 1
4196 18:09:16.845143
4197 18:09:16.848224 RX Delay -195 -> 252, step: 8
4198 18:09:16.848306
4199 18:09:16.851673 Set Vref, RX VrefLevel [Byte0]: 55
4200 18:09:16.855107 [Byte1]: 56
4201 18:09:16.855227
4202 18:09:16.858012 Final RX Vref Byte 0 = 55 to rank0
4203 18:09:16.861276 Final RX Vref Byte 1 = 56 to rank0
4204 18:09:16.864943 Final RX Vref Byte 0 = 55 to rank1
4205 18:09:16.867984 Final RX Vref Byte 1 = 56 to rank1==
4206 18:09:16.871577 Dram Type= 6, Freq= 0, CH_0, rank 0
4207 18:09:16.877624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 18:09:16.877733 ==
4209 18:09:16.877798 DQS Delay:
4210 18:09:16.877856 DQS0 = 0, DQS1 = 0
4211 18:09:16.881173 DQM Delay:
4212 18:09:16.881256 DQM0 = 45, DQM1 = 32
4213 18:09:16.884208 DQ Delay:
4214 18:09:16.887528 DQ0 =44, DQ1 =48, DQ2 =40, DQ3 =44
4215 18:09:16.890995 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4216 18:09:16.894406 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4217 18:09:16.897525 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4218 18:09:16.897615
4219 18:09:16.897680
4220 18:09:16.904060 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f37, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4221 18:09:16.907285 CH0 RK0: MR19=808, MR18=5F37
4222 18:09:16.914678 CH0_RK0: MR19=0x808, MR18=0x5F37, DQSOSC=391, MR23=63, INC=171, DEC=114
4223 18:09:16.914793
4224 18:09:16.917800 ----->DramcWriteLeveling(PI) begin...
4225 18:09:16.917884 ==
4226 18:09:16.920905 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 18:09:16.924223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 18:09:16.924310 ==
4229 18:09:16.927540 Write leveling (Byte 0): 33 => 33
4230 18:09:16.930684 Write leveling (Byte 1): 30 => 30
4231 18:09:16.933713 DramcWriteLeveling(PI) end<-----
4232 18:09:16.933797
4233 18:09:16.933861 ==
4234 18:09:16.937435 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 18:09:16.941027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 18:09:16.943927 ==
4237 18:09:16.944016 [Gating] SW mode calibration
4238 18:09:16.953716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4239 18:09:16.957022 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4240 18:09:16.960168 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 18:09:16.967171 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 18:09:16.970386 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 18:09:16.973524 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4244 18:09:16.980420 0 9 16 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (0 0)
4245 18:09:16.983095 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 18:09:16.986574 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 18:09:16.993603 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 18:09:16.996966 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 18:09:17.000383 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 18:09:17.006587 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 18:09:17.009842 0 10 12 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4252 18:09:17.013416 0 10 16 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
4253 18:09:17.019685 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 18:09:17.023051 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 18:09:17.026581 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 18:09:17.033273 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 18:09:17.036603 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 18:09:17.039536 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 18:09:17.046122 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4260 18:09:17.049241 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4261 18:09:17.052504 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 18:09:17.059320 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 18:09:17.062553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 18:09:17.065801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 18:09:17.072375 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 18:09:17.075988 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 18:09:17.079060 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 18:09:17.085802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 18:09:17.088789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 18:09:17.092266 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 18:09:17.099032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 18:09:17.102155 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 18:09:17.105685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 18:09:17.112180 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 18:09:17.115630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4276 18:09:17.118954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4277 18:09:17.125135 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 18:09:17.125266 Total UI for P1: 0, mck2ui 16
4279 18:09:17.132172 best dqsien dly found for B0: ( 0, 13, 14)
4280 18:09:17.132314 Total UI for P1: 0, mck2ui 16
4281 18:09:17.138408 best dqsien dly found for B1: ( 0, 13, 14)
4282 18:09:17.141467 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4283 18:09:17.145232 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4284 18:09:17.145351
4285 18:09:17.148319 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4286 18:09:17.151774 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 18:09:17.154857 [Gating] SW calibration Done
4288 18:09:17.154966 ==
4289 18:09:17.158117 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 18:09:17.161262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 18:09:17.161373 ==
4292 18:09:17.165019 RX Vref Scan: 0
4293 18:09:17.165127
4294 18:09:17.167819 RX Vref 0 -> 0, step: 1
4295 18:09:17.167927
4296 18:09:17.168019 RX Delay -230 -> 252, step: 16
4297 18:09:17.174466 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4298 18:09:17.178293 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4299 18:09:17.181159 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4300 18:09:17.184508 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4301 18:09:17.191008 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4302 18:09:17.194561 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4303 18:09:17.197391 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4304 18:09:17.200634 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4305 18:09:17.207305 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4306 18:09:17.210574 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4307 18:09:17.214042 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4308 18:09:17.217925 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4309 18:09:17.223952 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4310 18:09:17.227215 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4311 18:09:17.230295 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4312 18:09:17.233876 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4313 18:09:17.233985 ==
4314 18:09:17.237114 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 18:09:17.243892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 18:09:17.244030 ==
4317 18:09:17.244127 DQS Delay:
4318 18:09:17.246997 DQS0 = 0, DQS1 = 0
4319 18:09:17.247103 DQM Delay:
4320 18:09:17.247196 DQM0 = 42, DQM1 = 35
4321 18:09:17.250123 DQ Delay:
4322 18:09:17.253685 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4323 18:09:17.257155 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4324 18:09:17.260558 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4325 18:09:17.263701 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4326 18:09:17.263813
4327 18:09:17.263906
4328 18:09:17.263995 ==
4329 18:09:17.266774 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 18:09:17.270033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 18:09:17.270137 ==
4332 18:09:17.270268
4333 18:09:17.270355
4334 18:09:17.273137 TX Vref Scan disable
4335 18:09:17.276540 == TX Byte 0 ==
4336 18:09:17.279885 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4337 18:09:17.283327 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4338 18:09:17.286457 == TX Byte 1 ==
4339 18:09:17.289796 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4340 18:09:17.293070 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4341 18:09:17.293172 ==
4342 18:09:17.296361 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 18:09:17.302829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 18:09:17.302938 ==
4345 18:09:17.303029
4346 18:09:17.303116
4347 18:09:17.303202 TX Vref Scan disable
4348 18:09:17.306983 == TX Byte 0 ==
4349 18:09:17.310583 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4350 18:09:17.317223 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4351 18:09:17.317330 == TX Byte 1 ==
4352 18:09:17.320356 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4353 18:09:17.326868 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4354 18:09:17.326970
4355 18:09:17.327058 [DATLAT]
4356 18:09:17.327141 Freq=600, CH0 RK1
4357 18:09:17.327224
4358 18:09:17.330676 DATLAT Default: 0x9
4359 18:09:17.330774 0, 0xFFFF, sum = 0
4360 18:09:17.333423 1, 0xFFFF, sum = 0
4361 18:09:17.337068 2, 0xFFFF, sum = 0
4362 18:09:17.337175 3, 0xFFFF, sum = 0
4363 18:09:17.340166 4, 0xFFFF, sum = 0
4364 18:09:17.340272 5, 0xFFFF, sum = 0
4365 18:09:17.343213 6, 0xFFFF, sum = 0
4366 18:09:17.343318 7, 0xFFFF, sum = 0
4367 18:09:17.346629 8, 0x0, sum = 1
4368 18:09:17.346735 9, 0x0, sum = 2
4369 18:09:17.349873 10, 0x0, sum = 3
4370 18:09:17.349977 11, 0x0, sum = 4
4371 18:09:17.350070 best_step = 9
4372 18:09:17.350158
4373 18:09:17.353083 ==
4374 18:09:17.356705 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 18:09:17.360025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 18:09:17.360128 ==
4377 18:09:17.360217 RX Vref Scan: 0
4378 18:09:17.360302
4379 18:09:17.362959 RX Vref 0 -> 0, step: 1
4380 18:09:17.363062
4381 18:09:17.366765 RX Delay -195 -> 252, step: 8
4382 18:09:17.372879 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4383 18:09:17.376082 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4384 18:09:17.379813 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4385 18:09:17.382843 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4386 18:09:17.389312 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4387 18:09:17.392585 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4388 18:09:17.395917 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4389 18:09:17.399355 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4390 18:09:17.402524 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4391 18:09:17.409416 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4392 18:09:17.412519 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4393 18:09:17.415622 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4394 18:09:17.418977 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4395 18:09:17.425499 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4396 18:09:17.429122 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4397 18:09:17.432275 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4398 18:09:17.432382 ==
4399 18:09:17.435398 Dram Type= 6, Freq= 0, CH_0, rank 1
4400 18:09:17.441909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 18:09:17.442015 ==
4402 18:09:17.442102 DQS Delay:
4403 18:09:17.442223 DQS0 = 0, DQS1 = 0
4404 18:09:17.445550 DQM Delay:
4405 18:09:17.445644 DQM0 = 41, DQM1 = 36
4406 18:09:17.448696 DQ Delay:
4407 18:09:17.451813 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4408 18:09:17.454939 DQ4 =44, DQ5 =36, DQ6 =48, DQ7 =48
4409 18:09:17.458254 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4410 18:09:17.461933 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4411 18:09:17.462027
4412 18:09:17.462111
4413 18:09:17.468516 [DQSOSCAuto] RK1, (LSB)MR18= 0x570a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
4414 18:09:17.471361 CH0 RK1: MR19=808, MR18=570A
4415 18:09:17.478314 CH0_RK1: MR19=0x808, MR18=0x570A, DQSOSC=393, MR23=63, INC=169, DEC=113
4416 18:09:17.481184 [RxdqsGatingPostProcess] freq 600
4417 18:09:17.487687 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4418 18:09:17.487771 Pre-setting of DQS Precalculation
4419 18:09:17.494496 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4420 18:09:17.494581 ==
4421 18:09:17.497910 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 18:09:17.501094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 18:09:17.501216 ==
4424 18:09:17.507709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 18:09:17.514336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4426 18:09:17.518251 [CA 0] Center 35 (5~66) winsize 62
4427 18:09:17.520937 [CA 1] Center 35 (5~66) winsize 62
4428 18:09:17.524123 [CA 2] Center 34 (4~65) winsize 62
4429 18:09:17.527371 [CA 3] Center 34 (3~65) winsize 63
4430 18:09:17.530718 [CA 4] Center 34 (4~65) winsize 62
4431 18:09:17.533901 [CA 5] Center 33 (3~64) winsize 62
4432 18:09:17.534003
4433 18:09:17.537373 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4434 18:09:17.537478
4435 18:09:17.540774 [CATrainingPosCal] consider 1 rank data
4436 18:09:17.544023 u2DelayCellTimex100 = 270/100 ps
4437 18:09:17.547099 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 18:09:17.550277 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 18:09:17.553893 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 18:09:17.557433 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4441 18:09:17.560539 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 18:09:17.566715 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 18:09:17.566815
4444 18:09:17.570351 CA PerBit enable=1, Macro0, CA PI delay=33
4445 18:09:17.570453
4446 18:09:17.573467 [CBTSetCACLKResult] CA Dly = 33
4447 18:09:17.573567 CS Dly: 4 (0~35)
4448 18:09:17.573653 ==
4449 18:09:17.576557 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 18:09:17.583049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 18:09:17.583153 ==
4452 18:09:17.586769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4453 18:09:17.593103 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4454 18:09:17.596881 [CA 0] Center 35 (5~66) winsize 62
4455 18:09:17.600002 [CA 1] Center 36 (6~66) winsize 61
4456 18:09:17.603373 [CA 2] Center 34 (4~65) winsize 62
4457 18:09:17.606343 [CA 3] Center 34 (3~65) winsize 63
4458 18:09:17.610092 [CA 4] Center 34 (3~65) winsize 63
4459 18:09:17.612996 [CA 5] Center 34 (3~65) winsize 63
4460 18:09:17.613098
4461 18:09:17.616146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4462 18:09:17.616233
4463 18:09:17.619619 [CATrainingPosCal] consider 2 rank data
4464 18:09:17.622940 u2DelayCellTimex100 = 270/100 ps
4465 18:09:17.626142 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 18:09:17.629251 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4467 18:09:17.636147 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 18:09:17.639779 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4469 18:09:17.642543 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 18:09:17.645937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 18:09:17.646039
4472 18:09:17.649132 CA PerBit enable=1, Macro0, CA PI delay=33
4473 18:09:17.649232
4474 18:09:17.652355 [CBTSetCACLKResult] CA Dly = 33
4475 18:09:17.652456 CS Dly: 5 (0~37)
4476 18:09:17.655873
4477 18:09:17.659044 ----->DramcWriteLeveling(PI) begin...
4478 18:09:17.659153 ==
4479 18:09:17.662703 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 18:09:17.665740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 18:09:17.665845 ==
4482 18:09:17.669031 Write leveling (Byte 0): 28 => 28
4483 18:09:17.672401 Write leveling (Byte 1): 28 => 28
4484 18:09:17.675386 DramcWriteLeveling(PI) end<-----
4485 18:09:17.675492
4486 18:09:17.675586 ==
4487 18:09:17.679628 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 18:09:17.682090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 18:09:17.682232 ==
4490 18:09:17.685296 [Gating] SW mode calibration
4491 18:09:17.691911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4492 18:09:17.698559 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4493 18:09:17.701696 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 18:09:17.705304 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 18:09:17.711714 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 18:09:17.714876 0 9 12 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
4497 18:09:17.718323 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 18:09:17.724552 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 18:09:17.728125 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 18:09:17.731361 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 18:09:17.737740 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 18:09:17.741306 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 18:09:17.744337 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 18:09:17.751285 0 10 12 | B1->B0 | 2727 3838 | 0 0 | (0 0) (1 1)
4505 18:09:17.754350 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 18:09:17.757483 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 18:09:17.763891 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 18:09:17.767557 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 18:09:17.770770 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 18:09:17.777299 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 18:09:17.780779 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 18:09:17.787212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4513 18:09:17.790145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4514 18:09:17.793570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 18:09:17.800259 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 18:09:17.803802 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 18:09:17.807000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 18:09:17.810350 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 18:09:17.816923 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 18:09:17.820089 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 18:09:17.826523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 18:09:17.829779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 18:09:17.833279 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 18:09:17.836742 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 18:09:17.843223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 18:09:17.846584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 18:09:17.850129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 18:09:17.856473 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4529 18:09:17.859714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 18:09:17.863213 Total UI for P1: 0, mck2ui 16
4531 18:09:17.866452 best dqsien dly found for B0: ( 0, 13, 12)
4532 18:09:17.869629 Total UI for P1: 0, mck2ui 16
4533 18:09:17.873211 best dqsien dly found for B1: ( 0, 13, 12)
4534 18:09:17.876485 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4535 18:09:17.879692 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4536 18:09:17.879794
4537 18:09:17.882817 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4538 18:09:17.889280 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4539 18:09:17.889386 [Gating] SW calibration Done
4540 18:09:17.889452 ==
4541 18:09:17.892903 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 18:09:17.899397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 18:09:17.899497 ==
4544 18:09:17.899566 RX Vref Scan: 0
4545 18:09:17.899627
4546 18:09:17.902510 RX Vref 0 -> 0, step: 1
4547 18:09:17.902603
4548 18:09:17.906046 RX Delay -230 -> 252, step: 16
4549 18:09:17.909135 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4550 18:09:17.912596 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4551 18:09:17.919336 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4552 18:09:17.922733 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4553 18:09:17.925823 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4554 18:09:17.928608 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4555 18:09:17.935245 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4556 18:09:17.938592 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4557 18:09:17.942233 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4558 18:09:17.945171 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4559 18:09:17.951760 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4560 18:09:17.955117 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4561 18:09:17.958552 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4562 18:09:17.961658 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4563 18:09:17.968146 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4564 18:09:17.971978 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4565 18:09:17.972104 ==
4566 18:09:17.975082 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 18:09:17.978210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 18:09:17.978332 ==
4569 18:09:17.981351 DQS Delay:
4570 18:09:17.981467 DQS0 = 0, DQS1 = 0
4571 18:09:17.981562 DQM Delay:
4572 18:09:17.984722 DQM0 = 46, DQM1 = 37
4573 18:09:17.984831 DQ Delay:
4574 18:09:17.988074 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4575 18:09:17.991254 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4576 18:09:17.994200 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4577 18:09:17.997833 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4578 18:09:17.997944
4579 18:09:17.998039
4580 18:09:17.998128 ==
4581 18:09:18.001118 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 18:09:18.007576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 18:09:18.007709 ==
4584 18:09:18.007776
4585 18:09:18.007835
4586 18:09:18.007890 TX Vref Scan disable
4587 18:09:18.011570 == TX Byte 0 ==
4588 18:09:18.014585 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 18:09:18.021337 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 18:09:18.021477 == TX Byte 1 ==
4591 18:09:18.024558 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4592 18:09:18.031247 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4593 18:09:18.031382 ==
4594 18:09:18.034408 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 18:09:18.038017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 18:09:18.038129 ==
4597 18:09:18.038264
4598 18:09:18.038354
4599 18:09:18.041102 TX Vref Scan disable
4600 18:09:18.044115 == TX Byte 0 ==
4601 18:09:18.047629 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4602 18:09:18.050468 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4603 18:09:18.054097 == TX Byte 1 ==
4604 18:09:18.057437 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4605 18:09:18.060446 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4606 18:09:18.060561
4607 18:09:18.063530 [DATLAT]
4608 18:09:18.063640 Freq=600, CH1 RK0
4609 18:09:18.063735
4610 18:09:18.067147 DATLAT Default: 0x9
4611 18:09:18.067256 0, 0xFFFF, sum = 0
4612 18:09:18.070091 1, 0xFFFF, sum = 0
4613 18:09:18.070235 2, 0xFFFF, sum = 0
4614 18:09:18.073650 3, 0xFFFF, sum = 0
4615 18:09:18.073761 4, 0xFFFF, sum = 0
4616 18:09:18.076811 5, 0xFFFF, sum = 0
4617 18:09:18.076900 6, 0xFFFF, sum = 0
4618 18:09:18.080465 7, 0xFFFF, sum = 0
4619 18:09:18.080547 8, 0x0, sum = 1
4620 18:09:18.083338 9, 0x0, sum = 2
4621 18:09:18.083419 10, 0x0, sum = 3
4622 18:09:18.086531 11, 0x0, sum = 4
4623 18:09:18.086613 best_step = 9
4624 18:09:18.086675
4625 18:09:18.086733 ==
4626 18:09:18.089926 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 18:09:18.093644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 18:09:18.097012 ==
4629 18:09:18.097092 RX Vref Scan: 1
4630 18:09:18.097154
4631 18:09:18.099689 RX Vref 0 -> 0, step: 1
4632 18:09:18.099769
4633 18:09:18.103244 RX Delay -195 -> 252, step: 8
4634 18:09:18.103326
4635 18:09:18.107003 Set Vref, RX VrefLevel [Byte0]: 48
4636 18:09:18.109960 [Byte1]: 54
4637 18:09:18.110040
4638 18:09:18.112774 Final RX Vref Byte 0 = 48 to rank0
4639 18:09:18.116555 Final RX Vref Byte 1 = 54 to rank0
4640 18:09:18.119425 Final RX Vref Byte 0 = 48 to rank1
4641 18:09:18.123060 Final RX Vref Byte 1 = 54 to rank1==
4642 18:09:18.126065 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 18:09:18.129271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 18:09:18.129352 ==
4645 18:09:18.132974 DQS Delay:
4646 18:09:18.133054 DQS0 = 0, DQS1 = 0
4647 18:09:18.135914 DQM Delay:
4648 18:09:18.135996 DQM0 = 48, DQM1 = 37
4649 18:09:18.136058 DQ Delay:
4650 18:09:18.139318 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4651 18:09:18.142443 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4652 18:09:18.145633 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4653 18:09:18.148949 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4654 18:09:18.149028
4655 18:09:18.149090
4656 18:09:18.159451 [DQSOSCAuto] RK0, (LSB)MR18= 0x482d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4657 18:09:18.162358 CH1 RK0: MR19=808, MR18=482D
4658 18:09:18.168626 CH1_RK0: MR19=0x808, MR18=0x482D, DQSOSC=396, MR23=63, INC=167, DEC=111
4659 18:09:18.168713
4660 18:09:18.172368 ----->DramcWriteLeveling(PI) begin...
4661 18:09:18.172450 ==
4662 18:09:18.175493 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 18:09:18.178671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 18:09:18.178752 ==
4665 18:09:18.182346 Write leveling (Byte 0): 30 => 30
4666 18:09:18.185621 Write leveling (Byte 1): 32 => 32
4667 18:09:18.188542 DramcWriteLeveling(PI) end<-----
4668 18:09:18.188623
4669 18:09:18.188685 ==
4670 18:09:18.191808 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 18:09:18.195231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 18:09:18.195312 ==
4673 18:09:18.198680 [Gating] SW mode calibration
4674 18:09:18.205303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 18:09:18.211763 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 18:09:18.215102 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 18:09:18.218108 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 18:09:18.225237 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 18:09:18.228042 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 1) (1 0)
4680 18:09:18.231543 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4681 18:09:18.238171 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 18:09:18.241551 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 18:09:18.244760 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 18:09:18.251168 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 18:09:18.254642 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 18:09:18.260812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 18:09:18.264228 0 10 12 | B1->B0 | 3030 2525 | 0 0 | (0 0) (0 0)
4688 18:09:18.267356 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4689 18:09:18.273964 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 18:09:18.277343 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 18:09:18.280611 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 18:09:18.287591 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 18:09:18.290705 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 18:09:18.293916 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 18:09:18.300588 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4696 18:09:18.303889 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 18:09:18.306904 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 18:09:18.313891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 18:09:18.316620 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 18:09:18.319942 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 18:09:18.326980 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 18:09:18.330203 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 18:09:18.333313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 18:09:18.339807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 18:09:18.343673 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 18:09:18.346276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 18:09:18.352963 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 18:09:18.357096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 18:09:18.359565 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 18:09:18.365832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 18:09:18.369397 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4712 18:09:18.372849 Total UI for P1: 0, mck2ui 16
4713 18:09:18.375817 best dqsien dly found for B1: ( 0, 13, 10)
4714 18:09:18.379103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 18:09:18.382747 Total UI for P1: 0, mck2ui 16
4716 18:09:18.385816 best dqsien dly found for B0: ( 0, 13, 14)
4717 18:09:18.389357 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4718 18:09:18.392552 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4719 18:09:18.392634
4720 18:09:18.399213 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4721 18:09:18.402093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4722 18:09:18.405622 [Gating] SW calibration Done
4723 18:09:18.405732 ==
4724 18:09:18.408915 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 18:09:18.412093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 18:09:18.412173 ==
4727 18:09:18.412236 RX Vref Scan: 0
4728 18:09:18.412294
4729 18:09:18.415360 RX Vref 0 -> 0, step: 1
4730 18:09:18.415468
4731 18:09:18.418501 RX Delay -230 -> 252, step: 16
4732 18:09:18.422058 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4733 18:09:18.428978 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4734 18:09:18.431724 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4735 18:09:18.434990 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4736 18:09:18.438676 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4737 18:09:18.442088 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4738 18:09:18.448358 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4739 18:09:18.451622 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4740 18:09:18.455297 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4741 18:09:18.458142 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4742 18:09:18.464913 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4743 18:09:18.468229 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4744 18:09:18.471769 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4745 18:09:18.475079 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4746 18:09:18.481614 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4747 18:09:18.485265 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4748 18:09:18.485373 ==
4749 18:09:18.487975 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 18:09:18.491135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 18:09:18.491243 ==
4752 18:09:18.494550 DQS Delay:
4753 18:09:18.494655 DQS0 = 0, DQS1 = 0
4754 18:09:18.494746 DQM Delay:
4755 18:09:18.497784 DQM0 = 40, DQM1 = 39
4756 18:09:18.497889 DQ Delay:
4757 18:09:18.501398 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4758 18:09:18.504413 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4759 18:09:18.507867 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =33
4760 18:09:18.511478 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4761 18:09:18.511587
4762 18:09:18.511680
4763 18:09:18.511769 ==
4764 18:09:18.515191 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 18:09:18.521253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 18:09:18.521363 ==
4767 18:09:18.521457
4768 18:09:18.521547
4769 18:09:18.521636 TX Vref Scan disable
4770 18:09:18.524940 == TX Byte 0 ==
4771 18:09:18.528050 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4772 18:09:18.534782 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4773 18:09:18.534889 == TX Byte 1 ==
4774 18:09:18.538127 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4775 18:09:18.544857 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4776 18:09:18.544964 ==
4777 18:09:18.547495 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 18:09:18.551136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 18:09:18.551241 ==
4780 18:09:18.551333
4781 18:09:18.551420
4782 18:09:18.554383 TX Vref Scan disable
4783 18:09:18.557609 == TX Byte 0 ==
4784 18:09:18.561408 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4785 18:09:18.564057 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4786 18:09:18.567496 == TX Byte 1 ==
4787 18:09:18.570692 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4788 18:09:18.574062 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4789 18:09:18.574189
4790 18:09:18.577543 [DATLAT]
4791 18:09:18.577645 Freq=600, CH1 RK1
4792 18:09:18.577738
4793 18:09:18.580747 DATLAT Default: 0x9
4794 18:09:18.580853 0, 0xFFFF, sum = 0
4795 18:09:18.583868 1, 0xFFFF, sum = 0
4796 18:09:18.583977 2, 0xFFFF, sum = 0
4797 18:09:18.587343 3, 0xFFFF, sum = 0
4798 18:09:18.587450 4, 0xFFFF, sum = 0
4799 18:09:18.590695 5, 0xFFFF, sum = 0
4800 18:09:18.590803 6, 0xFFFF, sum = 0
4801 18:09:18.593895 7, 0xFFFF, sum = 0
4802 18:09:18.594000 8, 0x0, sum = 1
4803 18:09:18.597411 9, 0x0, sum = 2
4804 18:09:18.597517 10, 0x0, sum = 3
4805 18:09:18.600491 11, 0x0, sum = 4
4806 18:09:18.600597 best_step = 9
4807 18:09:18.600689
4808 18:09:18.600777 ==
4809 18:09:18.603711 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 18:09:18.607066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 18:09:18.610442 ==
4812 18:09:18.610548 RX Vref Scan: 0
4813 18:09:18.610640
4814 18:09:18.613391 RX Vref 0 -> 0, step: 1
4815 18:09:18.613499
4816 18:09:18.616866 RX Delay -195 -> 252, step: 8
4817 18:09:18.620311 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4818 18:09:18.623485 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4819 18:09:18.630112 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4820 18:09:18.633512 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4821 18:09:18.636929 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4822 18:09:18.640086 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4823 18:09:18.646290 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4824 18:09:18.649978 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4825 18:09:18.653178 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4826 18:09:18.656299 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4827 18:09:18.663117 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4828 18:09:18.666211 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4829 18:09:18.669701 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4830 18:09:18.673029 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4831 18:09:18.679614 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4832 18:09:18.682891 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4833 18:09:18.682998 ==
4834 18:09:18.685918 Dram Type= 6, Freq= 0, CH_1, rank 1
4835 18:09:18.689101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4836 18:09:18.689207 ==
4837 18:09:18.692585 DQS Delay:
4838 18:09:18.692689 DQS0 = 0, DQS1 = 0
4839 18:09:18.692780 DQM Delay:
4840 18:09:18.695796 DQM0 = 46, DQM1 = 37
4841 18:09:18.695899 DQ Delay:
4842 18:09:18.699525 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4843 18:09:18.702376 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4844 18:09:18.705945 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4845 18:09:18.708833 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4846 18:09:18.708914
4847 18:09:18.708976
4848 18:09:18.718927 [DQSOSCAuto] RK1, (LSB)MR18= 0x261c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4849 18:09:18.722384 CH1 RK1: MR19=808, MR18=261C
4850 18:09:18.725759 CH1_RK1: MR19=0x808, MR18=0x261C, DQSOSC=402, MR23=63, INC=162, DEC=108
4851 18:09:18.729404 [RxdqsGatingPostProcess] freq 600
4852 18:09:18.735534 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4853 18:09:18.739286 Pre-setting of DQS Precalculation
4854 18:09:18.741833 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4855 18:09:18.752157 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4856 18:09:18.758651 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4857 18:09:18.758732
4858 18:09:18.758795
4859 18:09:18.761765 [Calibration Summary] 1200 Mbps
4860 18:09:18.761836 CH 0, Rank 0
4861 18:09:18.765133 SW Impedance : PASS
4862 18:09:18.765207 DUTY Scan : NO K
4863 18:09:18.768711 ZQ Calibration : PASS
4864 18:09:18.771771 Jitter Meter : NO K
4865 18:09:18.771839 CBT Training : PASS
4866 18:09:18.774931 Write leveling : PASS
4867 18:09:18.778296 RX DQS gating : PASS
4868 18:09:18.778365 RX DQ/DQS(RDDQC) : PASS
4869 18:09:18.781486 TX DQ/DQS : PASS
4870 18:09:18.784719 RX DATLAT : PASS
4871 18:09:18.784787 RX DQ/DQS(Engine): PASS
4872 18:09:18.788184 TX OE : NO K
4873 18:09:18.788250 All Pass.
4874 18:09:18.788309
4875 18:09:18.791563 CH 0, Rank 1
4876 18:09:18.791666 SW Impedance : PASS
4877 18:09:18.794720 DUTY Scan : NO K
4878 18:09:18.797839 ZQ Calibration : PASS
4879 18:09:18.797918 Jitter Meter : NO K
4880 18:09:18.801179 CBT Training : PASS
4881 18:09:18.804292 Write leveling : PASS
4882 18:09:18.804373 RX DQS gating : PASS
4883 18:09:18.807935 RX DQ/DQS(RDDQC) : PASS
4884 18:09:18.811112 TX DQ/DQS : PASS
4885 18:09:18.811193 RX DATLAT : PASS
4886 18:09:18.814123 RX DQ/DQS(Engine): PASS
4887 18:09:18.817555 TX OE : NO K
4888 18:09:18.817633 All Pass.
4889 18:09:18.817695
4890 18:09:18.817753 CH 1, Rank 0
4891 18:09:18.820787 SW Impedance : PASS
4892 18:09:18.824117 DUTY Scan : NO K
4893 18:09:18.824195 ZQ Calibration : PASS
4894 18:09:18.827395 Jitter Meter : NO K
4895 18:09:18.830750 CBT Training : PASS
4896 18:09:18.830846 Write leveling : PASS
4897 18:09:18.833942 RX DQS gating : PASS
4898 18:09:18.834022 RX DQ/DQS(RDDQC) : PASS
4899 18:09:18.837430 TX DQ/DQS : PASS
4900 18:09:18.840843 RX DATLAT : PASS
4901 18:09:18.840925 RX DQ/DQS(Engine): PASS
4902 18:09:18.843810 TX OE : NO K
4903 18:09:18.843886 All Pass.
4904 18:09:18.843948
4905 18:09:18.847085 CH 1, Rank 1
4906 18:09:18.847153 SW Impedance : PASS
4907 18:09:18.850696 DUTY Scan : NO K
4908 18:09:18.853677 ZQ Calibration : PASS
4909 18:09:18.853751 Jitter Meter : NO K
4910 18:09:18.856889 CBT Training : PASS
4911 18:09:18.860831 Write leveling : PASS
4912 18:09:18.860910 RX DQS gating : PASS
4913 18:09:18.863542 RX DQ/DQS(RDDQC) : PASS
4914 18:09:18.866931 TX DQ/DQS : PASS
4915 18:09:18.867017 RX DATLAT : PASS
4916 18:09:18.870529 RX DQ/DQS(Engine): PASS
4917 18:09:18.874308 TX OE : NO K
4918 18:09:18.874375 All Pass.
4919 18:09:18.874434
4920 18:09:18.876982 DramC Write-DBI off
4921 18:09:18.877060 PER_BANK_REFRESH: Hybrid Mode
4922 18:09:18.880448 TX_TRACKING: ON
4923 18:09:18.886908 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4924 18:09:18.893636 [FAST_K] Save calibration result to emmc
4925 18:09:18.896403 dramc_set_vcore_voltage set vcore to 662500
4926 18:09:18.896482 Read voltage for 933, 3
4927 18:09:18.900198 Vio18 = 0
4928 18:09:18.900288 Vcore = 662500
4929 18:09:18.900357 Vdram = 0
4930 18:09:18.903524 Vddq = 0
4931 18:09:18.903662 Vmddr = 0
4932 18:09:18.906721 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4933 18:09:18.912968 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4934 18:09:18.916127 MEM_TYPE=3, freq_sel=17
4935 18:09:18.919523 sv_algorithm_assistance_LP4_1600
4936 18:09:18.922829 ============ PULL DRAM RESETB DOWN ============
4937 18:09:18.926393 ========== PULL DRAM RESETB DOWN end =========
4938 18:09:18.932356 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4939 18:09:18.936214 ===================================
4940 18:09:18.936296 LPDDR4 DRAM CONFIGURATION
4941 18:09:18.939180 ===================================
4942 18:09:18.942437 EX_ROW_EN[0] = 0x0
4943 18:09:18.946107 EX_ROW_EN[1] = 0x0
4944 18:09:18.946229 LP4Y_EN = 0x0
4945 18:09:18.948987 WORK_FSP = 0x0
4946 18:09:18.949135 WL = 0x3
4947 18:09:18.952608 RL = 0x3
4948 18:09:18.952698 BL = 0x2
4949 18:09:18.955443 RPST = 0x0
4950 18:09:18.955523 RD_PRE = 0x0
4951 18:09:18.959104 WR_PRE = 0x1
4952 18:09:18.959183 WR_PST = 0x0
4953 18:09:18.962486 DBI_WR = 0x0
4954 18:09:18.962565 DBI_RD = 0x0
4955 18:09:18.965648 OTF = 0x1
4956 18:09:18.968739 ===================================
4957 18:09:18.972100 ===================================
4958 18:09:18.972180 ANA top config
4959 18:09:18.975529 ===================================
4960 18:09:18.978586 DLL_ASYNC_EN = 0
4961 18:09:18.981824 ALL_SLAVE_EN = 1
4962 18:09:18.985119 NEW_RANK_MODE = 1
4963 18:09:18.985211 DLL_IDLE_MODE = 1
4964 18:09:18.988607 LP45_APHY_COMB_EN = 1
4965 18:09:18.991960 TX_ODT_DIS = 1
4966 18:09:18.995224 NEW_8X_MODE = 1
4967 18:09:18.998215 ===================================
4968 18:09:19.001523 ===================================
4969 18:09:19.005037 data_rate = 1866
4970 18:09:19.008813 CKR = 1
4971 18:09:19.008897 DQ_P2S_RATIO = 8
4972 18:09:19.011397 ===================================
4973 18:09:19.014966 CA_P2S_RATIO = 8
4974 18:09:19.018442 DQ_CA_OPEN = 0
4975 18:09:19.021198 DQ_SEMI_OPEN = 0
4976 18:09:19.024678 CA_SEMI_OPEN = 0
4977 18:09:19.027688 CA_FULL_RATE = 0
4978 18:09:19.027773 DQ_CKDIV4_EN = 1
4979 18:09:19.031442 CA_CKDIV4_EN = 1
4980 18:09:19.034271 CA_PREDIV_EN = 0
4981 18:09:19.037985 PH8_DLY = 0
4982 18:09:19.041065 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4983 18:09:19.044530 DQ_AAMCK_DIV = 4
4984 18:09:19.044612 CA_AAMCK_DIV = 4
4985 18:09:19.047679 CA_ADMCK_DIV = 4
4986 18:09:19.050742 DQ_TRACK_CA_EN = 0
4987 18:09:19.054392 CA_PICK = 933
4988 18:09:19.057488 CA_MCKIO = 933
4989 18:09:19.060992 MCKIO_SEMI = 0
4990 18:09:19.063931 PLL_FREQ = 3732
4991 18:09:19.067623 DQ_UI_PI_RATIO = 32
4992 18:09:19.067707 CA_UI_PI_RATIO = 0
4993 18:09:19.070655 ===================================
4994 18:09:19.074287 ===================================
4995 18:09:19.077145 memory_type:LPDDR4
4996 18:09:19.080569 GP_NUM : 10
4997 18:09:19.080650 SRAM_EN : 1
4998 18:09:19.083624 MD32_EN : 0
4999 18:09:19.086905 ===================================
5000 18:09:19.090718 [ANA_INIT] >>>>>>>>>>>>>>
5001 18:09:19.093750 <<<<<< [CONFIGURE PHASE]: ANA_TX
5002 18:09:19.097213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5003 18:09:19.100158 ===================================
5004 18:09:19.100239 data_rate = 1866,PCW = 0X8f00
5005 18:09:19.103800 ===================================
5006 18:09:19.106855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5007 18:09:19.113741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 18:09:19.120163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 18:09:19.123217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5010 18:09:19.126942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5011 18:09:19.129747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5012 18:09:19.133594 [ANA_INIT] flow start
5013 18:09:19.136628 [ANA_INIT] PLL >>>>>>>>
5014 18:09:19.136711 [ANA_INIT] PLL <<<<<<<<
5015 18:09:19.139889 [ANA_INIT] MIDPI >>>>>>>>
5016 18:09:19.143069 [ANA_INIT] MIDPI <<<<<<<<
5017 18:09:19.143150 [ANA_INIT] DLL >>>>>>>>
5018 18:09:19.146618 [ANA_INIT] flow end
5019 18:09:19.149746 ============ LP4 DIFF to SE enter ============
5020 18:09:19.152839 ============ LP4 DIFF to SE exit ============
5021 18:09:19.156219 [ANA_INIT] <<<<<<<<<<<<<
5022 18:09:19.159705 [Flow] Enable top DCM control >>>>>
5023 18:09:19.162902 [Flow] Enable top DCM control <<<<<
5024 18:09:19.166396 Enable DLL master slave shuffle
5025 18:09:19.172653 ==============================================================
5026 18:09:19.172739 Gating Mode config
5027 18:09:19.179249 ==============================================================
5028 18:09:19.182653 Config description:
5029 18:09:19.189434 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5030 18:09:19.196189 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5031 18:09:19.202409 SELPH_MODE 0: By rank 1: By Phase
5032 18:09:19.209025 ==============================================================
5033 18:09:19.212716 GAT_TRACK_EN = 1
5034 18:09:19.212805 RX_GATING_MODE = 2
5035 18:09:19.215790 RX_GATING_TRACK_MODE = 2
5036 18:09:19.219053 SELPH_MODE = 1
5037 18:09:19.222054 PICG_EARLY_EN = 1
5038 18:09:19.225436 VALID_LAT_VALUE = 1
5039 18:09:19.232286 ==============================================================
5040 18:09:19.235217 Enter into Gating configuration >>>>
5041 18:09:19.238683 Exit from Gating configuration <<<<
5042 18:09:19.241915 Enter into DVFS_PRE_config >>>>>
5043 18:09:19.251970 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5044 18:09:19.254931 Exit from DVFS_PRE_config <<<<<
5045 18:09:19.258654 Enter into PICG configuration >>>>
5046 18:09:19.261949 Exit from PICG configuration <<<<
5047 18:09:19.265169 [RX_INPUT] configuration >>>>>
5048 18:09:19.268008 [RX_INPUT] configuration <<<<<
5049 18:09:19.271725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5050 18:09:19.278194 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5051 18:09:19.285053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 18:09:19.291314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 18:09:19.298047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 18:09:19.301069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 18:09:19.307702 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5056 18:09:19.311351 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5057 18:09:19.314601 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5058 18:09:19.317599 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5059 18:09:19.324482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5060 18:09:19.327789 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 18:09:19.331233 ===================================
5062 18:09:19.334044 LPDDR4 DRAM CONFIGURATION
5063 18:09:19.337688 ===================================
5064 18:09:19.337769 EX_ROW_EN[0] = 0x0
5065 18:09:19.340688 EX_ROW_EN[1] = 0x0
5066 18:09:19.340769 LP4Y_EN = 0x0
5067 18:09:19.344039 WORK_FSP = 0x0
5068 18:09:19.344122 WL = 0x3
5069 18:09:19.347212 RL = 0x3
5070 18:09:19.347293 BL = 0x2
5071 18:09:19.350729 RPST = 0x0
5072 18:09:19.350811 RD_PRE = 0x0
5073 18:09:19.353981 WR_PRE = 0x1
5074 18:09:19.357174 WR_PST = 0x0
5075 18:09:19.357255 DBI_WR = 0x0
5076 18:09:19.360731 DBI_RD = 0x0
5077 18:09:19.360813 OTF = 0x1
5078 18:09:19.364155 ===================================
5079 18:09:19.367212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5080 18:09:19.373860 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5081 18:09:19.376753 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 18:09:19.380226 ===================================
5083 18:09:19.383840 LPDDR4 DRAM CONFIGURATION
5084 18:09:19.386938 ===================================
5085 18:09:19.387021 EX_ROW_EN[0] = 0x10
5086 18:09:19.390192 EX_ROW_EN[1] = 0x0
5087 18:09:19.390287 LP4Y_EN = 0x0
5088 18:09:19.393650 WORK_FSP = 0x0
5089 18:09:19.393731 WL = 0x3
5090 18:09:19.397070 RL = 0x3
5091 18:09:19.397150 BL = 0x2
5092 18:09:19.400335 RPST = 0x0
5093 18:09:19.403949 RD_PRE = 0x0
5094 18:09:19.404030 WR_PRE = 0x1
5095 18:09:19.406646 WR_PST = 0x0
5096 18:09:19.406728 DBI_WR = 0x0
5097 18:09:19.410077 DBI_RD = 0x0
5098 18:09:19.410182 OTF = 0x1
5099 18:09:19.413785 ===================================
5100 18:09:19.419985 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5101 18:09:19.423566 nWR fixed to 30
5102 18:09:19.426960 [ModeRegInit_LP4] CH0 RK0
5103 18:09:19.427041 [ModeRegInit_LP4] CH0 RK1
5104 18:09:19.430300 [ModeRegInit_LP4] CH1 RK0
5105 18:09:19.433836 [ModeRegInit_LP4] CH1 RK1
5106 18:09:19.433916 match AC timing 9
5107 18:09:19.440248 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5108 18:09:19.443642 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5109 18:09:19.446848 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5110 18:09:19.453235 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5111 18:09:19.456596 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5112 18:09:19.456677 ==
5113 18:09:19.460488 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 18:09:19.463334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 18:09:19.463415 ==
5116 18:09:19.469993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 18:09:19.476704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5118 18:09:19.479925 [CA 0] Center 37 (7~68) winsize 62
5119 18:09:19.483291 [CA 1] Center 37 (7~68) winsize 62
5120 18:09:19.486414 [CA 2] Center 34 (4~65) winsize 62
5121 18:09:19.489625 [CA 3] Center 35 (5~65) winsize 61
5122 18:09:19.492819 [CA 4] Center 33 (3~64) winsize 62
5123 18:09:19.496038 [CA 5] Center 33 (3~63) winsize 61
5124 18:09:19.496119
5125 18:09:19.499268 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5126 18:09:19.499348
5127 18:09:19.502541 [CATrainingPosCal] consider 1 rank data
5128 18:09:19.506380 u2DelayCellTimex100 = 270/100 ps
5129 18:09:19.509553 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5130 18:09:19.512980 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5131 18:09:19.515742 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 18:09:19.522730 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5133 18:09:19.525969 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5134 18:09:19.529115 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5135 18:09:19.529195
5136 18:09:19.532781 CA PerBit enable=1, Macro0, CA PI delay=33
5137 18:09:19.532861
5138 18:09:19.536148 [CBTSetCACLKResult] CA Dly = 33
5139 18:09:19.536229 CS Dly: 7 (0~38)
5140 18:09:19.536291 ==
5141 18:09:19.539177 Dram Type= 6, Freq= 0, CH_0, rank 1
5142 18:09:19.545651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 18:09:19.545733 ==
5144 18:09:19.548784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 18:09:19.555923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5146 18:09:19.559086 [CA 0] Center 37 (7~68) winsize 62
5147 18:09:19.562361 [CA 1] Center 37 (7~68) winsize 62
5148 18:09:19.565586 [CA 2] Center 34 (4~65) winsize 62
5149 18:09:19.569043 [CA 3] Center 34 (4~65) winsize 62
5150 18:09:19.571731 [CA 4] Center 33 (3~64) winsize 62
5151 18:09:19.575150 [CA 5] Center 32 (2~63) winsize 62
5152 18:09:19.575232
5153 18:09:19.578559 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5154 18:09:19.578640
5155 18:09:19.581714 [CATrainingPosCal] consider 2 rank data
5156 18:09:19.585072 u2DelayCellTimex100 = 270/100 ps
5157 18:09:19.588458 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 18:09:19.595107 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5159 18:09:19.598765 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 18:09:19.601596 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5161 18:09:19.604847 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 18:09:19.608100 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5163 18:09:19.608180
5164 18:09:19.611854 CA PerBit enable=1, Macro0, CA PI delay=33
5165 18:09:19.611933
5166 18:09:19.614785 [CBTSetCACLKResult] CA Dly = 33
5167 18:09:19.618500 CS Dly: 7 (0~39)
5168 18:09:19.618589
5169 18:09:19.621683 ----->DramcWriteLeveling(PI) begin...
5170 18:09:19.621763 ==
5171 18:09:19.624913 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 18:09:19.628053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 18:09:19.628133 ==
5174 18:09:19.631212 Write leveling (Byte 0): 30 => 30
5175 18:09:19.634500 Write leveling (Byte 1): 29 => 29
5176 18:09:19.637703 DramcWriteLeveling(PI) end<-----
5177 18:09:19.637782
5178 18:09:19.637844 ==
5179 18:09:19.641130 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 18:09:19.644619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 18:09:19.644785 ==
5182 18:09:19.647842 [Gating] SW mode calibration
5183 18:09:19.654602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5184 18:09:19.661249 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5185 18:09:19.664779 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5186 18:09:19.667748 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 18:09:19.674524 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 18:09:19.677640 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 18:09:19.684192 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 18:09:19.687523 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 18:09:19.691198 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 18:09:19.697588 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5193 18:09:19.700762 0 15 0 | B1->B0 | 3030 2828 | 0 0 | (1 0) (0 0)
5194 18:09:19.703952 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5195 18:09:19.710241 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 18:09:19.713737 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 18:09:19.716832 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 18:09:19.723639 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 18:09:19.727101 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 18:09:19.730478 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5201 18:09:19.736695 1 0 0 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
5202 18:09:19.740319 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5203 18:09:19.743321 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 18:09:19.750021 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 18:09:19.753273 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 18:09:19.756375 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 18:09:19.763287 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 18:09:19.766693 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5209 18:09:19.769616 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5210 18:09:19.776324 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 18:09:19.779429 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 18:09:19.782658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 18:09:19.789609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 18:09:19.793092 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 18:09:19.796107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 18:09:19.802560 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 18:09:19.805707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 18:09:19.809436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 18:09:19.815563 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 18:09:19.819223 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 18:09:19.822221 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 18:09:19.828940 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 18:09:19.832069 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 18:09:19.835489 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 18:09:19.842055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 18:09:19.842138 Total UI for P1: 0, mck2ui 16
5227 18:09:19.849021 best dqsien dly found for B0: ( 1, 2, 26)
5228 18:09:19.851972 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5229 18:09:19.855432 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 18:09:19.858762 Total UI for P1: 0, mck2ui 16
5231 18:09:19.862016 best dqsien dly found for B1: ( 1, 3, 2)
5232 18:09:19.865103 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5233 18:09:19.868253 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5234 18:09:19.868345
5235 18:09:19.871914 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5236 18:09:19.878072 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5237 18:09:19.878154 [Gating] SW calibration Done
5238 18:09:19.882033 ==
5239 18:09:19.882114 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 18:09:19.888086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 18:09:19.888168 ==
5242 18:09:19.888233 RX Vref Scan: 0
5243 18:09:19.888293
5244 18:09:19.891471 RX Vref 0 -> 0, step: 1
5245 18:09:19.891553
5246 18:09:19.894944 RX Delay -80 -> 252, step: 8
5247 18:09:19.898182 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5248 18:09:19.901514 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5249 18:09:19.904456 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5250 18:09:19.911520 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5251 18:09:19.914301 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5252 18:09:19.917650 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5253 18:09:19.920934 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5254 18:09:19.924129 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5255 18:09:19.930686 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5256 18:09:19.933956 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5257 18:09:19.937500 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5258 18:09:19.940813 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5259 18:09:19.943913 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5260 18:09:19.950729 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5261 18:09:19.953938 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5262 18:09:19.957627 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5263 18:09:19.957730 ==
5264 18:09:19.960661 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 18:09:19.963898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 18:09:19.964005 ==
5267 18:09:19.967450 DQS Delay:
5268 18:09:19.967567 DQS0 = 0, DQS1 = 0
5269 18:09:19.967659 DQM Delay:
5270 18:09:19.970807 DQM0 = 97, DQM1 = 85
5271 18:09:19.970924 DQ Delay:
5272 18:09:19.974122 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5273 18:09:19.977541 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5274 18:09:19.980252 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5275 18:09:19.983632 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5276 18:09:19.983937
5277 18:09:19.984137
5278 18:09:19.984329 ==
5279 18:09:19.986852 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 18:09:19.993941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 18:09:19.994205 ==
5282 18:09:19.994369
5283 18:09:19.994515
5284 18:09:19.997490 TX Vref Scan disable
5285 18:09:19.997685 == TX Byte 0 ==
5286 18:09:20.000351 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5287 18:09:20.007063 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5288 18:09:20.007283 == TX Byte 1 ==
5289 18:09:20.009959 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5290 18:09:20.016759 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5291 18:09:20.016922 ==
5292 18:09:20.020328 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 18:09:20.023657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 18:09:20.023783 ==
5295 18:09:20.023878
5296 18:09:20.023975
5297 18:09:20.026772 TX Vref Scan disable
5298 18:09:20.030087 == TX Byte 0 ==
5299 18:09:20.033031 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5300 18:09:20.036771 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5301 18:09:20.039636 == TX Byte 1 ==
5302 18:09:20.042830 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5303 18:09:20.046705 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5304 18:09:20.046819
5305 18:09:20.049422 [DATLAT]
5306 18:09:20.049501 Freq=933, CH0 RK0
5307 18:09:20.049562
5308 18:09:20.052834 DATLAT Default: 0xd
5309 18:09:20.052913 0, 0xFFFF, sum = 0
5310 18:09:20.056504 1, 0xFFFF, sum = 0
5311 18:09:20.056594 2, 0xFFFF, sum = 0
5312 18:09:20.059643 3, 0xFFFF, sum = 0
5313 18:09:20.059751 4, 0xFFFF, sum = 0
5314 18:09:20.062639 5, 0xFFFF, sum = 0
5315 18:09:20.062728 6, 0xFFFF, sum = 0
5316 18:09:20.066140 7, 0xFFFF, sum = 0
5317 18:09:20.066264 8, 0xFFFF, sum = 0
5318 18:09:20.069380 9, 0xFFFF, sum = 0
5319 18:09:20.069479 10, 0x0, sum = 1
5320 18:09:20.072730 11, 0x0, sum = 2
5321 18:09:20.072853 12, 0x0, sum = 3
5322 18:09:20.076091 13, 0x0, sum = 4
5323 18:09:20.076200 best_step = 11
5324 18:09:20.076289
5325 18:09:20.076375 ==
5326 18:09:20.079430 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 18:09:20.085908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 18:09:20.085985 ==
5329 18:09:20.086047 RX Vref Scan: 1
5330 18:09:20.086105
5331 18:09:20.089234 RX Vref 0 -> 0, step: 1
5332 18:09:20.089305
5333 18:09:20.092574 RX Delay -61 -> 252, step: 4
5334 18:09:20.092650
5335 18:09:20.095891 Set Vref, RX VrefLevel [Byte0]: 55
5336 18:09:20.099061 [Byte1]: 56
5337 18:09:20.099149
5338 18:09:20.102192 Final RX Vref Byte 0 = 55 to rank0
5339 18:09:20.105653 Final RX Vref Byte 1 = 56 to rank0
5340 18:09:20.108916 Final RX Vref Byte 0 = 55 to rank1
5341 18:09:20.112623 Final RX Vref Byte 1 = 56 to rank1==
5342 18:09:20.115983 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 18:09:20.118754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 18:09:20.118856 ==
5345 18:09:20.122215 DQS Delay:
5346 18:09:20.122297 DQS0 = 0, DQS1 = 0
5347 18:09:20.125764 DQM Delay:
5348 18:09:20.125838 DQM0 = 97, DQM1 = 86
5349 18:09:20.125927 DQ Delay:
5350 18:09:20.128875 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5351 18:09:20.132237 DQ4 =98, DQ5 =90, DQ6 =106, DQ7 =106
5352 18:09:20.135580 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5353 18:09:20.138950 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =94
5354 18:09:20.139030
5355 18:09:20.139090
5356 18:09:20.148535 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5357 18:09:20.152079 CH0 RK0: MR19=505, MR18=270E
5358 18:09:20.158749 CH0_RK0: MR19=0x505, MR18=0x270E, DQSOSC=409, MR23=63, INC=64, DEC=43
5359 18:09:20.158903
5360 18:09:20.162049 ----->DramcWriteLeveling(PI) begin...
5361 18:09:20.162155 ==
5362 18:09:20.165218 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 18:09:20.168433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 18:09:20.168512 ==
5365 18:09:20.171924 Write leveling (Byte 0): 32 => 32
5366 18:09:20.174962 Write leveling (Byte 1): 31 => 31
5367 18:09:20.178401 DramcWriteLeveling(PI) end<-----
5368 18:09:20.178559
5369 18:09:20.178637 ==
5370 18:09:20.181587 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 18:09:20.184780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 18:09:20.184866 ==
5373 18:09:20.188053 [Gating] SW mode calibration
5374 18:09:20.194696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5375 18:09:20.201167 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5376 18:09:20.204651 0 14 0 | B1->B0 | 2929 3030 | 1 1 | (1 1) (1 1)
5377 18:09:20.208499 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 18:09:20.214550 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 18:09:20.217858 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 18:09:20.221042 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 18:09:20.227892 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 18:09:20.231488 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 18:09:20.234435 0 14 28 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0)
5384 18:09:20.241321 0 15 0 | B1->B0 | 2e2e 2424 | 1 1 | (1 1) (1 0)
5385 18:09:20.244740 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 18:09:20.247500 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 18:09:20.254177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 18:09:20.257447 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 18:09:20.261055 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 18:09:20.267570 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 18:09:20.270817 0 15 28 | B1->B0 | 2727 3332 | 0 1 | (0 0) (1 1)
5392 18:09:20.277648 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
5393 18:09:20.280510 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 18:09:20.284010 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 18:09:20.290396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 18:09:20.293623 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 18:09:20.297011 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 18:09:20.300489 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 18:09:20.307341 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 18:09:20.310606 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5401 18:09:20.313887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 18:09:20.320166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 18:09:20.323532 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 18:09:20.326881 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 18:09:20.333225 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 18:09:20.337175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 18:09:20.339563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 18:09:20.346513 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 18:09:20.349735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 18:09:20.353312 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 18:09:20.359461 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 18:09:20.363176 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 18:09:20.366131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 18:09:20.373056 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 18:09:20.375937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 18:09:20.379158 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5417 18:09:20.382702 Total UI for P1: 0, mck2ui 16
5418 18:09:20.386088 best dqsien dly found for B0: ( 1, 2, 30)
5419 18:09:20.392403 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 18:09:20.395928 Total UI for P1: 0, mck2ui 16
5421 18:09:20.399007 best dqsien dly found for B1: ( 1, 3, 0)
5422 18:09:20.402558 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5423 18:09:20.405910 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5424 18:09:20.406057
5425 18:09:20.409512 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5426 18:09:20.412389 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5427 18:09:20.415597 [Gating] SW calibration Done
5428 18:09:20.415751 ==
5429 18:09:20.418685 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 18:09:20.422231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 18:09:20.422371 ==
5432 18:09:20.425478 RX Vref Scan: 0
5433 18:09:20.425614
5434 18:09:20.428988 RX Vref 0 -> 0, step: 1
5435 18:09:20.429107
5436 18:09:20.429201 RX Delay -80 -> 252, step: 8
5437 18:09:20.435307 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5438 18:09:20.438313 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5439 18:09:20.441935 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5440 18:09:20.445419 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5441 18:09:20.448572 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5442 18:09:20.451650 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5443 18:09:20.458505 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5444 18:09:20.461579 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5445 18:09:20.464773 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5446 18:09:20.468536 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5447 18:09:20.471549 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5448 18:09:20.478580 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5449 18:09:20.481295 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5450 18:09:20.484674 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5451 18:09:20.487983 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5452 18:09:20.491337 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5453 18:09:20.494477 ==
5454 18:09:20.494561 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 18:09:20.501323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 18:09:20.501422 ==
5457 18:09:20.501529 DQS Delay:
5458 18:09:20.505066 DQS0 = 0, DQS1 = 0
5459 18:09:20.505151 DQM Delay:
5460 18:09:20.507631 DQM0 = 96, DQM1 = 88
5461 18:09:20.507771 DQ Delay:
5462 18:09:20.510981 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5463 18:09:20.514284 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5464 18:09:20.517673 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5465 18:09:20.521057 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5466 18:09:20.521153
5467 18:09:20.521219
5468 18:09:20.521280 ==
5469 18:09:20.524049 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 18:09:20.527629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 18:09:20.527757 ==
5472 18:09:20.527850
5473 18:09:20.527936
5474 18:09:20.530557 TX Vref Scan disable
5475 18:09:20.534501 == TX Byte 0 ==
5476 18:09:20.537198 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5477 18:09:20.540823 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5478 18:09:20.544412 == TX Byte 1 ==
5479 18:09:20.547167 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5480 18:09:20.550897 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5481 18:09:20.551055 ==
5482 18:09:20.554074 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 18:09:20.560424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 18:09:20.560586 ==
5485 18:09:20.560726
5486 18:09:20.560818
5487 18:09:20.560961 TX Vref Scan disable
5488 18:09:20.564677 == TX Byte 0 ==
5489 18:09:20.567994 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5490 18:09:20.574822 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5491 18:09:20.575200 == TX Byte 1 ==
5492 18:09:20.577932 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5493 18:09:20.584560 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5494 18:09:20.584912
5495 18:09:20.585187 [DATLAT]
5496 18:09:20.585444 Freq=933, CH0 RK1
5497 18:09:20.585694
5498 18:09:20.587610 DATLAT Default: 0xb
5499 18:09:20.590960 0, 0xFFFF, sum = 0
5500 18:09:20.591317 1, 0xFFFF, sum = 0
5501 18:09:20.594577 2, 0xFFFF, sum = 0
5502 18:09:20.594933 3, 0xFFFF, sum = 0
5503 18:09:20.597861 4, 0xFFFF, sum = 0
5504 18:09:20.598405 5, 0xFFFF, sum = 0
5505 18:09:20.600838 6, 0xFFFF, sum = 0
5506 18:09:20.601221 7, 0xFFFF, sum = 0
5507 18:09:20.604748 8, 0xFFFF, sum = 0
5508 18:09:20.605132 9, 0xFFFF, sum = 0
5509 18:09:20.607630 10, 0x0, sum = 1
5510 18:09:20.608156 11, 0x0, sum = 2
5511 18:09:20.611419 12, 0x0, sum = 3
5512 18:09:20.611804 13, 0x0, sum = 4
5513 18:09:20.614078 best_step = 11
5514 18:09:20.614491
5515 18:09:20.614792 ==
5516 18:09:20.617553 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 18:09:20.621065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 18:09:20.621484 ==
5519 18:09:20.621791 RX Vref Scan: 0
5520 18:09:20.624134
5521 18:09:20.624541 RX Vref 0 -> 0, step: 1
5522 18:09:20.624852
5523 18:09:20.627448 RX Delay -61 -> 252, step: 4
5524 18:09:20.634263 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5525 18:09:20.637843 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5526 18:09:20.640776 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5527 18:09:20.644196 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5528 18:09:20.647715 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5529 18:09:20.650574 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5530 18:09:20.657187 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5531 18:09:20.660416 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5532 18:09:20.663988 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5533 18:09:20.666827 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5534 18:09:20.670982 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5535 18:09:20.676701 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5536 18:09:20.680248 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5537 18:09:20.683671 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5538 18:09:20.686867 iDelay=199, Bit 14, Center 94 (-1 ~ 190) 192
5539 18:09:20.690116 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5540 18:09:20.693686 ==
5541 18:09:20.696655 Dram Type= 6, Freq= 0, CH_0, rank 1
5542 18:09:20.699937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 18:09:20.700424 ==
5544 18:09:20.700728 DQS Delay:
5545 18:09:20.703178 DQS0 = 0, DQS1 = 0
5546 18:09:20.703557 DQM Delay:
5547 18:09:20.706385 DQM0 = 95, DQM1 = 87
5548 18:09:20.706947 DQ Delay:
5549 18:09:20.709510 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =92
5550 18:09:20.713207 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5551 18:09:20.716399 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5552 18:09:20.719673 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5553 18:09:20.720064
5554 18:09:20.720476
5555 18:09:20.726250 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5556 18:09:20.729606 CH0 RK1: MR19=504, MR18=26F7
5557 18:09:20.736051 CH0_RK1: MR19=0x504, MR18=0x26F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5558 18:09:20.739242 [RxdqsGatingPostProcess] freq 933
5559 18:09:20.746311 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5560 18:09:20.749195 best DQS0 dly(2T, 0.5T) = (0, 10)
5561 18:09:20.752794 best DQS1 dly(2T, 0.5T) = (0, 11)
5562 18:09:20.756083 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5563 18:09:20.756546 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5564 18:09:20.759389 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 18:09:20.762396 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 18:09:20.766152 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 18:09:20.769226 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 18:09:20.772578 Pre-setting of DQS Precalculation
5569 18:09:20.779547 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5570 18:09:20.779928 ==
5571 18:09:20.782800 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 18:09:20.785839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 18:09:20.786408 ==
5574 18:09:20.792422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 18:09:20.799390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5576 18:09:20.802203 [CA 0] Center 36 (6~67) winsize 62
5577 18:09:20.805543 [CA 1] Center 37 (7~68) winsize 62
5578 18:09:20.808691 [CA 2] Center 34 (4~64) winsize 61
5579 18:09:20.811887 [CA 3] Center 33 (3~64) winsize 62
5580 18:09:20.815349 [CA 4] Center 34 (4~64) winsize 61
5581 18:09:20.818529 [CA 5] Center 33 (3~64) winsize 62
5582 18:09:20.818909
5583 18:09:20.821647 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5584 18:09:20.822025
5585 18:09:20.825158 [CATrainingPosCal] consider 1 rank data
5586 18:09:20.828351 u2DelayCellTimex100 = 270/100 ps
5587 18:09:20.831586 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 18:09:20.834725 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5589 18:09:20.838388 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5590 18:09:20.841743 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 18:09:20.845129 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 18:09:20.848522 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 18:09:20.848900
5594 18:09:20.855054 CA PerBit enable=1, Macro0, CA PI delay=33
5595 18:09:20.855574
5596 18:09:20.855884 [CBTSetCACLKResult] CA Dly = 33
5597 18:09:20.858023 CS Dly: 6 (0~37)
5598 18:09:20.858422 ==
5599 18:09:20.861442 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 18:09:20.865003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 18:09:20.865384 ==
5602 18:09:20.871668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 18:09:20.878157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5604 18:09:20.881307 [CA 0] Center 36 (6~67) winsize 62
5605 18:09:20.884814 [CA 1] Center 37 (7~67) winsize 61
5606 18:09:20.888094 [CA 2] Center 34 (3~65) winsize 63
5607 18:09:20.890977 [CA 3] Center 33 (3~64) winsize 62
5608 18:09:20.894102 [CA 4] Center 34 (3~65) winsize 63
5609 18:09:20.898056 [CA 5] Center 33 (3~64) winsize 62
5610 18:09:20.898517
5611 18:09:20.901012 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5612 18:09:20.901384
5613 18:09:20.904543 [CATrainingPosCal] consider 2 rank data
5614 18:09:20.907905 u2DelayCellTimex100 = 270/100 ps
5615 18:09:20.910813 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5616 18:09:20.914272 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5617 18:09:20.917346 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 18:09:20.920757 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 18:09:20.927115 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 18:09:20.930568 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5621 18:09:20.930978
5622 18:09:20.933754 CA PerBit enable=1, Macro0, CA PI delay=33
5623 18:09:20.934199
5624 18:09:20.937439 [CBTSetCACLKResult] CA Dly = 33
5625 18:09:20.937892 CS Dly: 7 (0~39)
5626 18:09:20.938273
5627 18:09:20.940697 ----->DramcWriteLeveling(PI) begin...
5628 18:09:20.941334 ==
5629 18:09:20.943750 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 18:09:20.950620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 18:09:20.951038 ==
5632 18:09:20.953554 Write leveling (Byte 0): 27 => 27
5633 18:09:20.957071 Write leveling (Byte 1): 28 => 28
5634 18:09:20.957571 DramcWriteLeveling(PI) end<-----
5635 18:09:20.960260
5636 18:09:20.960732 ==
5637 18:09:20.963740 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 18:09:20.966915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 18:09:20.967402 ==
5640 18:09:20.970214 [Gating] SW mode calibration
5641 18:09:20.977085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5642 18:09:20.980160 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5643 18:09:20.986954 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5644 18:09:20.989689 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 18:09:20.992991 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 18:09:20.999907 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 18:09:21.002955 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 18:09:21.006502 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 18:09:21.012777 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5650 18:09:21.015968 0 14 28 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 0)
5651 18:09:21.019629 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5652 18:09:21.026004 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 18:09:21.029474 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 18:09:21.032529 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 18:09:21.039402 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 18:09:21.043088 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 18:09:21.046125 0 15 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
5658 18:09:21.052372 0 15 28 | B1->B0 | 3333 3838 | 0 0 | (0 0) (0 0)
5659 18:09:21.055694 1 0 0 | B1->B0 | 403f 4646 | 1 0 | (1 1) (0 0)
5660 18:09:21.059045 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 18:09:21.065617 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 18:09:21.068650 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 18:09:21.075520 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 18:09:21.078991 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5665 18:09:21.081945 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5666 18:09:21.088929 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 18:09:21.092314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 18:09:21.095190 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 18:09:21.098457 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 18:09:21.105497 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 18:09:21.108592 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 18:09:21.115067 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 18:09:21.118464 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 18:09:21.121344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 18:09:21.128678 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 18:09:21.131263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 18:09:21.134460 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 18:09:21.141138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 18:09:21.144770 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 18:09:21.147783 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 18:09:21.154574 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 18:09:21.158254 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5683 18:09:21.161312 Total UI for P1: 0, mck2ui 16
5684 18:09:21.164800 best dqsien dly found for B0: ( 1, 2, 26)
5685 18:09:21.167602 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 18:09:21.170876 Total UI for P1: 0, mck2ui 16
5687 18:09:21.174637 best dqsien dly found for B1: ( 1, 2, 28)
5688 18:09:21.177473 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5689 18:09:21.180831 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5690 18:09:21.181243
5691 18:09:21.184213 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5692 18:09:21.190825 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5693 18:09:21.191272 [Gating] SW calibration Done
5694 18:09:21.191601 ==
5695 18:09:21.194292 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 18:09:21.200538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 18:09:21.200953 ==
5698 18:09:21.201280 RX Vref Scan: 0
5699 18:09:21.201582
5700 18:09:21.203726 RX Vref 0 -> 0, step: 1
5701 18:09:21.204136
5702 18:09:21.207286 RX Delay -80 -> 252, step: 8
5703 18:09:21.210447 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5704 18:09:21.213670 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5705 18:09:21.217184 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5706 18:09:21.223823 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5707 18:09:21.227311 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5708 18:09:21.230320 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5709 18:09:21.233718 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5710 18:09:21.236655 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5711 18:09:21.239928 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5712 18:09:21.246888 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5713 18:09:21.249981 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5714 18:09:21.253522 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5715 18:09:21.256902 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5716 18:09:21.260057 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5717 18:09:21.266395 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5718 18:09:21.269842 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5719 18:09:21.270301 ==
5720 18:09:21.273236 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 18:09:21.276183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 18:09:21.276598 ==
5723 18:09:21.279886 DQS Delay:
5724 18:09:21.280296 DQS0 = 0, DQS1 = 0
5725 18:09:21.280624 DQM Delay:
5726 18:09:21.283194 DQM0 = 101, DQM1 = 91
5727 18:09:21.283591 DQ Delay:
5728 18:09:21.286566 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5729 18:09:21.289916 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5730 18:09:21.292840 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5731 18:09:21.296190 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5732 18:09:21.296617
5733 18:09:21.296993
5734 18:09:21.297479 ==
5735 18:09:21.299582 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 18:09:21.305999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 18:09:21.306495 ==
5738 18:09:21.306830
5739 18:09:21.307246
5740 18:09:21.307552 TX Vref Scan disable
5741 18:09:21.309742 == TX Byte 0 ==
5742 18:09:21.313261 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5743 18:09:21.319478 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5744 18:09:21.319830 == TX Byte 1 ==
5745 18:09:21.322788 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5746 18:09:21.329183 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5747 18:09:21.329404 ==
5748 18:09:21.333179 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 18:09:21.335819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 18:09:21.335989 ==
5751 18:09:21.336128
5752 18:09:21.336240
5753 18:09:21.339382 TX Vref Scan disable
5754 18:09:21.339527 == TX Byte 0 ==
5755 18:09:21.346048 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5756 18:09:21.349247 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5757 18:09:21.352300 == TX Byte 1 ==
5758 18:09:21.355852 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5759 18:09:21.358973 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5760 18:09:21.359056
5761 18:09:21.359121 [DATLAT]
5762 18:09:21.362490 Freq=933, CH1 RK0
5763 18:09:21.362572
5764 18:09:21.362636 DATLAT Default: 0xd
5765 18:09:21.365720 0, 0xFFFF, sum = 0
5766 18:09:21.369056 1, 0xFFFF, sum = 0
5767 18:09:21.369141 2, 0xFFFF, sum = 0
5768 18:09:21.372578 3, 0xFFFF, sum = 0
5769 18:09:21.372661 4, 0xFFFF, sum = 0
5770 18:09:21.375548 5, 0xFFFF, sum = 0
5771 18:09:21.375631 6, 0xFFFF, sum = 0
5772 18:09:21.378509 7, 0xFFFF, sum = 0
5773 18:09:21.378592 8, 0xFFFF, sum = 0
5774 18:09:21.381923 9, 0xFFFF, sum = 0
5775 18:09:21.382006 10, 0x0, sum = 1
5776 18:09:21.385356 11, 0x0, sum = 2
5777 18:09:21.385445 12, 0x0, sum = 3
5778 18:09:21.388774 13, 0x0, sum = 4
5779 18:09:21.388870 best_step = 11
5780 18:09:21.388945
5781 18:09:21.389014 ==
5782 18:09:21.391997 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 18:09:21.395525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 18:09:21.395629 ==
5785 18:09:21.398627 RX Vref Scan: 1
5786 18:09:21.398738
5787 18:09:21.402070 RX Vref 0 -> 0, step: 1
5788 18:09:21.402221
5789 18:09:21.402311 RX Delay -61 -> 252, step: 4
5790 18:09:21.405198
5791 18:09:21.405304 Set Vref, RX VrefLevel [Byte0]: 48
5792 18:09:21.408162 [Byte1]: 54
5793 18:09:21.413532
5794 18:09:21.413687 Final RX Vref Byte 0 = 48 to rank0
5795 18:09:21.416655 Final RX Vref Byte 1 = 54 to rank0
5796 18:09:21.420262 Final RX Vref Byte 0 = 48 to rank1
5797 18:09:21.423720 Final RX Vref Byte 1 = 54 to rank1==
5798 18:09:21.426835 Dram Type= 6, Freq= 0, CH_1, rank 0
5799 18:09:21.433807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 18:09:21.434236 ==
5801 18:09:21.434512 DQS Delay:
5802 18:09:21.436831 DQS0 = 0, DQS1 = 0
5803 18:09:21.437096 DQM Delay:
5804 18:09:21.437323 DQM0 = 100, DQM1 = 92
5805 18:09:21.440274 DQ Delay:
5806 18:09:21.443338 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5807 18:09:21.446845 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5808 18:09:21.450086 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =80
5809 18:09:21.452846 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5810 18:09:21.453226
5811 18:09:21.453534
5812 18:09:21.459834 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5813 18:09:21.463505 CH1 RK0: MR19=505, MR18=1C0C
5814 18:09:21.469384 CH1_RK0: MR19=0x505, MR18=0x1C0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5815 18:09:21.469781
5816 18:09:21.472825 ----->DramcWriteLeveling(PI) begin...
5817 18:09:21.473204 ==
5818 18:09:21.476218 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 18:09:21.482127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 18:09:21.482571 ==
5821 18:09:21.485653 Write leveling (Byte 0): 25 => 25
5822 18:09:21.485936 Write leveling (Byte 1): 30 => 30
5823 18:09:21.488960 DramcWriteLeveling(PI) end<-----
5824 18:09:21.489370
5825 18:09:21.492458 ==
5826 18:09:21.495948 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 18:09:21.498805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 18:09:21.498975 ==
5829 18:09:21.501766 [Gating] SW mode calibration
5830 18:09:21.508831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5831 18:09:21.512044 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5832 18:09:21.518432 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5833 18:09:21.521484 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 18:09:21.525253 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 18:09:21.531390 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 18:09:21.535134 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 18:09:21.538442 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 18:09:21.544332 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
5839 18:09:21.547943 0 14 28 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
5840 18:09:21.551218 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5841 18:09:21.557714 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 18:09:21.561140 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 18:09:21.564246 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 18:09:21.570945 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 18:09:21.574169 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 18:09:21.577614 0 15 24 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
5847 18:09:21.583921 0 15 28 | B1->B0 | 3b3b 3535 | 0 0 | (0 0) (0 0)
5848 18:09:21.587448 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 18:09:21.593967 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 18:09:21.597450 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 18:09:21.600454 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 18:09:21.607221 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 18:09:21.610561 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 18:09:21.614106 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5855 18:09:21.620887 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5856 18:09:21.623577 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 18:09:21.627042 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 18:09:21.633812 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 18:09:21.636641 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 18:09:21.640169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 18:09:21.647006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 18:09:21.650134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 18:09:21.653246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 18:09:21.659720 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 18:09:21.663035 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 18:09:21.666599 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 18:09:21.673508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 18:09:21.676222 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 18:09:21.679328 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 18:09:21.686452 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5871 18:09:21.689566 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5872 18:09:21.692655 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 18:09:21.696443 Total UI for P1: 0, mck2ui 16
5874 18:09:21.699307 best dqsien dly found for B0: ( 1, 2, 26)
5875 18:09:21.702586 Total UI for P1: 0, mck2ui 16
5876 18:09:21.706274 best dqsien dly found for B1: ( 1, 2, 26)
5877 18:09:21.709367 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5878 18:09:21.712460 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5879 18:09:21.712962
5880 18:09:21.715943 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5881 18:09:21.722706 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5882 18:09:21.723112 [Gating] SW calibration Done
5883 18:09:21.725962 ==
5884 18:09:21.729422 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 18:09:21.732496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 18:09:21.732903 ==
5887 18:09:21.733222 RX Vref Scan: 0
5888 18:09:21.733519
5889 18:09:21.736262 RX Vref 0 -> 0, step: 1
5890 18:09:21.736666
5891 18:09:21.739251 RX Delay -80 -> 252, step: 8
5892 18:09:21.742151 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5893 18:09:21.745779 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5894 18:09:21.749054 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5895 18:09:21.755485 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5896 18:09:21.758608 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5897 18:09:21.761936 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5898 18:09:21.765333 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5899 18:09:21.768739 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5900 18:09:21.775220 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5901 18:09:21.778426 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5902 18:09:21.781679 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5903 18:09:21.784869 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5904 18:09:21.788508 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5905 18:09:21.794882 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5906 18:09:21.798316 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5907 18:09:21.801199 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5908 18:09:21.801778 ==
5909 18:09:21.804649 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 18:09:21.807834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 18:09:21.808293 ==
5912 18:09:21.811065 DQS Delay:
5913 18:09:21.811476 DQS0 = 0, DQS1 = 0
5914 18:09:21.812004 DQM Delay:
5915 18:09:21.814494 DQM0 = 99, DQM1 = 90
5916 18:09:21.814993 DQ Delay:
5917 18:09:21.817783 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =95
5918 18:09:21.821198 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5919 18:09:21.824726 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5920 18:09:21.828122 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5921 18:09:21.828526
5922 18:09:21.828840
5923 18:09:21.831066 ==
5924 18:09:21.834642 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 18:09:21.837407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 18:09:21.837872 ==
5927 18:09:21.838377
5928 18:09:21.838684
5929 18:09:21.840771 TX Vref Scan disable
5930 18:09:21.841180 == TX Byte 0 ==
5931 18:09:21.847348 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5932 18:09:21.850571 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5933 18:09:21.851059 == TX Byte 1 ==
5934 18:09:21.857410 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5935 18:09:21.860816 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5936 18:09:21.861226 ==
5937 18:09:21.863618 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 18:09:21.867116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 18:09:21.867536 ==
5940 18:09:21.868008
5941 18:09:21.868469
5942 18:09:21.870338 TX Vref Scan disable
5943 18:09:21.874126 == TX Byte 0 ==
5944 18:09:21.876650 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5945 18:09:21.880329 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5946 18:09:21.883397 == TX Byte 1 ==
5947 18:09:21.886664 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5948 18:09:21.889872 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5949 18:09:21.890590
5950 18:09:21.893552 [DATLAT]
5951 18:09:21.894210 Freq=933, CH1 RK1
5952 18:09:21.894746
5953 18:09:21.896816 DATLAT Default: 0xb
5954 18:09:21.897353 0, 0xFFFF, sum = 0
5955 18:09:21.899636 1, 0xFFFF, sum = 0
5956 18:09:21.899998 2, 0xFFFF, sum = 0
5957 18:09:21.903294 3, 0xFFFF, sum = 0
5958 18:09:21.903713 4, 0xFFFF, sum = 0
5959 18:09:21.906289 5, 0xFFFF, sum = 0
5960 18:09:21.909805 6, 0xFFFF, sum = 0
5961 18:09:21.910429 7, 0xFFFF, sum = 0
5962 18:09:21.913002 8, 0xFFFF, sum = 0
5963 18:09:21.913443 9, 0xFFFF, sum = 0
5964 18:09:21.916309 10, 0x0, sum = 1
5965 18:09:21.916633 11, 0x0, sum = 2
5966 18:09:21.916872 12, 0x0, sum = 3
5967 18:09:21.919368 13, 0x0, sum = 4
5968 18:09:21.919642 best_step = 11
5969 18:09:21.919892
5970 18:09:21.923025 ==
5971 18:09:21.923349 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 18:09:21.929515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 18:09:21.929738 ==
5974 18:09:21.929919 RX Vref Scan: 0
5975 18:09:21.930080
5976 18:09:21.932718 RX Vref 0 -> 0, step: 1
5977 18:09:21.932928
5978 18:09:21.936383 RX Delay -61 -> 252, step: 4
5979 18:09:21.939783 iDelay=203, Bit 0, Center 104 (15 ~ 194) 180
5980 18:09:21.945980 iDelay=203, Bit 1, Center 94 (7 ~ 182) 176
5981 18:09:21.949652 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
5982 18:09:21.952530 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5983 18:09:21.956058 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5984 18:09:21.959283 iDelay=203, Bit 5, Center 110 (23 ~ 198) 176
5985 18:09:21.962830 iDelay=203, Bit 6, Center 112 (23 ~ 202) 180
5986 18:09:21.969496 iDelay=203, Bit 7, Center 98 (7 ~ 190) 184
5987 18:09:21.972277 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5988 18:09:21.975918 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5989 18:09:21.978911 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5990 18:09:21.982242 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5991 18:09:21.989479 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5992 18:09:21.992705 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5993 18:09:21.995630 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5994 18:09:21.999378 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5995 18:09:21.999781 ==
5996 18:09:22.002236 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 18:09:22.008911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 18:09:22.009340 ==
5999 18:09:22.009775 DQS Delay:
6000 18:09:22.012140 DQS0 = 0, DQS1 = 0
6001 18:09:22.012565 DQM Delay:
6002 18:09:22.012992 DQM0 = 100, DQM1 = 93
6003 18:09:22.015346 DQ Delay:
6004 18:09:22.018544 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6005 18:09:22.022052 DQ4 =98, DQ5 =110, DQ6 =112, DQ7 =98
6006 18:09:22.025500 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =84
6007 18:09:22.029083 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
6008 18:09:22.029641
6009 18:09:22.030154
6010 18:09:22.035221 [DQSOSCAuto] RK1, (LSB)MR18= 0x801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6011 18:09:22.038433 CH1 RK1: MR19=505, MR18=801
6012 18:09:22.045463 CH1_RK1: MR19=0x505, MR18=0x801, DQSOSC=419, MR23=63, INC=61, DEC=41
6013 18:09:22.048565 [RxdqsGatingPostProcess] freq 933
6014 18:09:22.055048 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6015 18:09:22.058418 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 18:09:22.058930 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 18:09:22.061482 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 18:09:22.065124 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 18:09:22.068166 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 18:09:22.071337 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 18:09:22.074712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 18:09:22.078012 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 18:09:22.081469 Pre-setting of DQS Precalculation
6024 18:09:22.087724 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6025 18:09:22.094579 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6026 18:09:22.101655 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6027 18:09:22.102261
6028 18:09:22.102776
6029 18:09:22.104407 [Calibration Summary] 1866 Mbps
6030 18:09:22.104920 CH 0, Rank 0
6031 18:09:22.107434 SW Impedance : PASS
6032 18:09:22.111176 DUTY Scan : NO K
6033 18:09:22.111772 ZQ Calibration : PASS
6034 18:09:22.114053 Jitter Meter : NO K
6035 18:09:22.117203 CBT Training : PASS
6036 18:09:22.117774 Write leveling : PASS
6037 18:09:22.120610 RX DQS gating : PASS
6038 18:09:22.124142 RX DQ/DQS(RDDQC) : PASS
6039 18:09:22.124707 TX DQ/DQS : PASS
6040 18:09:22.127091 RX DATLAT : PASS
6041 18:09:22.130673 RX DQ/DQS(Engine): PASS
6042 18:09:22.130945 TX OE : NO K
6043 18:09:22.133933 All Pass.
6044 18:09:22.134149
6045 18:09:22.134350 CH 0, Rank 1
6046 18:09:22.136713 SW Impedance : PASS
6047 18:09:22.136932 DUTY Scan : NO K
6048 18:09:22.140250 ZQ Calibration : PASS
6049 18:09:22.143634 Jitter Meter : NO K
6050 18:09:22.143852 CBT Training : PASS
6051 18:09:22.146840 Write leveling : PASS
6052 18:09:22.150116 RX DQS gating : PASS
6053 18:09:22.150380 RX DQ/DQS(RDDQC) : PASS
6054 18:09:22.153345 TX DQ/DQS : PASS
6055 18:09:22.156847 RX DATLAT : PASS
6056 18:09:22.157146 RX DQ/DQS(Engine): PASS
6057 18:09:22.159864 TX OE : NO K
6058 18:09:22.160151 All Pass.
6059 18:09:22.160406
6060 18:09:22.163366 CH 1, Rank 0
6061 18:09:22.163582 SW Impedance : PASS
6062 18:09:22.166793 DUTY Scan : NO K
6063 18:09:22.167048 ZQ Calibration : PASS
6064 18:09:22.169609 Jitter Meter : NO K
6065 18:09:22.173107 CBT Training : PASS
6066 18:09:22.173341 Write leveling : PASS
6067 18:09:22.176518 RX DQS gating : PASS
6068 18:09:22.180027 RX DQ/DQS(RDDQC) : PASS
6069 18:09:22.180258 TX DQ/DQS : PASS
6070 18:09:22.183241 RX DATLAT : PASS
6071 18:09:22.186586 RX DQ/DQS(Engine): PASS
6072 18:09:22.186817 TX OE : NO K
6073 18:09:22.189481 All Pass.
6074 18:09:22.189710
6075 18:09:22.189884 CH 1, Rank 1
6076 18:09:22.193107 SW Impedance : PASS
6077 18:09:22.193340 DUTY Scan : NO K
6078 18:09:22.196631 ZQ Calibration : PASS
6079 18:09:22.199525 Jitter Meter : NO K
6080 18:09:22.199815 CBT Training : PASS
6081 18:09:22.203142 Write leveling : PASS
6082 18:09:22.206247 RX DQS gating : PASS
6083 18:09:22.206529 RX DQ/DQS(RDDQC) : PASS
6084 18:09:22.209793 TX DQ/DQS : PASS
6085 18:09:22.213372 RX DATLAT : PASS
6086 18:09:22.213723 RX DQ/DQS(Engine): PASS
6087 18:09:22.216478 TX OE : NO K
6088 18:09:22.216834 All Pass.
6089 18:09:22.217149
6090 18:09:22.219416 DramC Write-DBI off
6091 18:09:22.223057 PER_BANK_REFRESH: Hybrid Mode
6092 18:09:22.223326 TX_TRACKING: ON
6093 18:09:22.232481 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6094 18:09:22.236051 [FAST_K] Save calibration result to emmc
6095 18:09:22.239311 dramc_set_vcore_voltage set vcore to 650000
6096 18:09:22.242695 Read voltage for 400, 6
6097 18:09:22.242983 Vio18 = 0
6098 18:09:22.243200 Vcore = 650000
6099 18:09:22.245969 Vdram = 0
6100 18:09:22.246276 Vddq = 0
6101 18:09:22.246510 Vmddr = 0
6102 18:09:22.252622 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6103 18:09:22.255611 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6104 18:09:22.258820 MEM_TYPE=3, freq_sel=20
6105 18:09:22.262449 sv_algorithm_assistance_LP4_800
6106 18:09:22.265570 ============ PULL DRAM RESETB DOWN ============
6107 18:09:22.268862 ========== PULL DRAM RESETB DOWN end =========
6108 18:09:22.275736 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6109 18:09:22.278625 ===================================
6110 18:09:22.282072 LPDDR4 DRAM CONFIGURATION
6111 18:09:22.285168 ===================================
6112 18:09:22.285449 EX_ROW_EN[0] = 0x0
6113 18:09:22.288405 EX_ROW_EN[1] = 0x0
6114 18:09:22.288672 LP4Y_EN = 0x0
6115 18:09:22.292035 WORK_FSP = 0x0
6116 18:09:22.292312 WL = 0x2
6117 18:09:22.294959 RL = 0x2
6118 18:09:22.295226 BL = 0x2
6119 18:09:22.298751 RPST = 0x0
6120 18:09:22.299019 RD_PRE = 0x0
6121 18:09:22.301785 WR_PRE = 0x1
6122 18:09:22.304716 WR_PST = 0x0
6123 18:09:22.305075 DBI_WR = 0x0
6124 18:09:22.308422 DBI_RD = 0x0
6125 18:09:22.308694 OTF = 0x1
6126 18:09:22.311261 ===================================
6127 18:09:22.314870 ===================================
6128 18:09:22.315158 ANA top config
6129 18:09:22.318132 ===================================
6130 18:09:22.321251 DLL_ASYNC_EN = 0
6131 18:09:22.324588 ALL_SLAVE_EN = 1
6132 18:09:22.328047 NEW_RANK_MODE = 1
6133 18:09:22.331204 DLL_IDLE_MODE = 1
6134 18:09:22.331488 LP45_APHY_COMB_EN = 1
6135 18:09:22.334570 TX_ODT_DIS = 1
6136 18:09:22.337856 NEW_8X_MODE = 1
6137 18:09:22.341217 ===================================
6138 18:09:22.344389 ===================================
6139 18:09:22.347664 data_rate = 800
6140 18:09:22.351091 CKR = 1
6141 18:09:22.354631 DQ_P2S_RATIO = 4
6142 18:09:22.357872 ===================================
6143 18:09:22.358295 CA_P2S_RATIO = 4
6144 18:09:22.360737 DQ_CA_OPEN = 0
6145 18:09:22.364621 DQ_SEMI_OPEN = 1
6146 18:09:22.367674 CA_SEMI_OPEN = 1
6147 18:09:22.370837 CA_FULL_RATE = 0
6148 18:09:22.374115 DQ_CKDIV4_EN = 0
6149 18:09:22.374603 CA_CKDIV4_EN = 1
6150 18:09:22.377537 CA_PREDIV_EN = 0
6151 18:09:22.380732 PH8_DLY = 0
6152 18:09:22.384370 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6153 18:09:22.387534 DQ_AAMCK_DIV = 0
6154 18:09:22.390503 CA_AAMCK_DIV = 0
6155 18:09:22.394053 CA_ADMCK_DIV = 4
6156 18:09:22.394644 DQ_TRACK_CA_EN = 0
6157 18:09:22.397382 CA_PICK = 800
6158 18:09:22.400495 CA_MCKIO = 400
6159 18:09:22.403832 MCKIO_SEMI = 400
6160 18:09:22.406788 PLL_FREQ = 3016
6161 18:09:22.410392 DQ_UI_PI_RATIO = 32
6162 18:09:22.413359 CA_UI_PI_RATIO = 32
6163 18:09:22.416872 ===================================
6164 18:09:22.419870 ===================================
6165 18:09:22.420281 memory_type:LPDDR4
6166 18:09:22.423328 GP_NUM : 10
6167 18:09:22.426431 SRAM_EN : 1
6168 18:09:22.426839 MD32_EN : 0
6169 18:09:22.430558 ===================================
6170 18:09:22.433205 [ANA_INIT] >>>>>>>>>>>>>>
6171 18:09:22.436495 <<<<<< [CONFIGURE PHASE]: ANA_TX
6172 18:09:22.439905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6173 18:09:22.443211 ===================================
6174 18:09:22.446557 data_rate = 800,PCW = 0X7400
6175 18:09:22.450318 ===================================
6176 18:09:22.453053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6177 18:09:22.456798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 18:09:22.470207 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 18:09:22.473369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6180 18:09:22.476066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6181 18:09:22.479709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6182 18:09:22.483163 [ANA_INIT] flow start
6183 18:09:22.486269 [ANA_INIT] PLL >>>>>>>>
6184 18:09:22.486681 [ANA_INIT] PLL <<<<<<<<
6185 18:09:22.489651 [ANA_INIT] MIDPI >>>>>>>>
6186 18:09:22.492897 [ANA_INIT] MIDPI <<<<<<<<
6187 18:09:22.493411 [ANA_INIT] DLL >>>>>>>>
6188 18:09:22.495968 [ANA_INIT] flow end
6189 18:09:22.499723 ============ LP4 DIFF to SE enter ============
6190 18:09:22.505763 ============ LP4 DIFF to SE exit ============
6191 18:09:22.506198 [ANA_INIT] <<<<<<<<<<<<<
6192 18:09:22.509400 [Flow] Enable top DCM control >>>>>
6193 18:09:22.512778 [Flow] Enable top DCM control <<<<<
6194 18:09:22.516215 Enable DLL master slave shuffle
6195 18:09:22.521933 ==============================================================
6196 18:09:22.522494 Gating Mode config
6197 18:09:22.528921 ==============================================================
6198 18:09:22.531972 Config description:
6199 18:09:22.542298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6200 18:09:22.548767 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6201 18:09:22.552001 SELPH_MODE 0: By rank 1: By Phase
6202 18:09:22.558986 ==============================================================
6203 18:09:22.562105 GAT_TRACK_EN = 0
6204 18:09:22.562673 RX_GATING_MODE = 2
6205 18:09:22.565466 RX_GATING_TRACK_MODE = 2
6206 18:09:22.568866 SELPH_MODE = 1
6207 18:09:22.571878 PICG_EARLY_EN = 1
6208 18:09:22.575377 VALID_LAT_VALUE = 1
6209 18:09:22.582152 ==============================================================
6210 18:09:22.585086 Enter into Gating configuration >>>>
6211 18:09:22.588808 Exit from Gating configuration <<<<
6212 18:09:22.591700 Enter into DVFS_PRE_config >>>>>
6213 18:09:22.601502 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6214 18:09:22.605043 Exit from DVFS_PRE_config <<<<<
6215 18:09:22.608394 Enter into PICG configuration >>>>
6216 18:09:22.611794 Exit from PICG configuration <<<<
6217 18:09:22.614907 [RX_INPUT] configuration >>>>>
6218 18:09:22.618319 [RX_INPUT] configuration <<<<<
6219 18:09:22.621578 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6220 18:09:22.628421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6221 18:09:22.634797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 18:09:22.641065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 18:09:22.644717 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 18:09:22.651561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 18:09:22.655011 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6226 18:09:22.661093 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6227 18:09:22.664651 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6228 18:09:22.668268 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6229 18:09:22.671297 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6230 18:09:22.677558 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 18:09:22.681093 ===================================
6232 18:09:22.684147 LPDDR4 DRAM CONFIGURATION
6233 18:09:22.687540 ===================================
6234 18:09:22.687953 EX_ROW_EN[0] = 0x0
6235 18:09:22.690843 EX_ROW_EN[1] = 0x0
6236 18:09:22.691255 LP4Y_EN = 0x0
6237 18:09:22.694315 WORK_FSP = 0x0
6238 18:09:22.694725 WL = 0x2
6239 18:09:22.697211 RL = 0x2
6240 18:09:22.697621 BL = 0x2
6241 18:09:22.700801 RPST = 0x0
6242 18:09:22.701211 RD_PRE = 0x0
6243 18:09:22.704053 WR_PRE = 0x1
6244 18:09:22.704462 WR_PST = 0x0
6245 18:09:22.707233 DBI_WR = 0x0
6246 18:09:22.707642 DBI_RD = 0x0
6247 18:09:22.710440 OTF = 0x1
6248 18:09:22.713699 ===================================
6249 18:09:22.717158 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6250 18:09:22.720568 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6251 18:09:22.727908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 18:09:22.730363 ===================================
6253 18:09:22.734270 LPDDR4 DRAM CONFIGURATION
6254 18:09:22.736976 ===================================
6255 18:09:22.737385 EX_ROW_EN[0] = 0x10
6256 18:09:22.740663 EX_ROW_EN[1] = 0x0
6257 18:09:22.741183 LP4Y_EN = 0x0
6258 18:09:22.743837 WORK_FSP = 0x0
6259 18:09:22.744239 WL = 0x2
6260 18:09:22.747264 RL = 0x2
6261 18:09:22.747674 BL = 0x2
6262 18:09:22.750295 RPST = 0x0
6263 18:09:22.750704 RD_PRE = 0x0
6264 18:09:22.753670 WR_PRE = 0x1
6265 18:09:22.754076 WR_PST = 0x0
6266 18:09:22.757109 DBI_WR = 0x0
6267 18:09:22.757514 DBI_RD = 0x0
6268 18:09:22.760331 OTF = 0x1
6269 18:09:22.763952 ===================================
6270 18:09:22.770404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6271 18:09:22.773959 nWR fixed to 30
6272 18:09:22.776907 [ModeRegInit_LP4] CH0 RK0
6273 18:09:22.777330 [ModeRegInit_LP4] CH0 RK1
6274 18:09:22.780629 [ModeRegInit_LP4] CH1 RK0
6275 18:09:22.783794 [ModeRegInit_LP4] CH1 RK1
6276 18:09:22.784323 match AC timing 19
6277 18:09:22.790003 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6278 18:09:22.793163 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6279 18:09:22.796848 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6280 18:09:22.803263 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6281 18:09:22.806668 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6282 18:09:22.807079 ==
6283 18:09:22.810212 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 18:09:22.813284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 18:09:22.813711 ==
6286 18:09:22.819848 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 18:09:22.826359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6288 18:09:22.830125 [CA 0] Center 36 (8~64) winsize 57
6289 18:09:22.833365 [CA 1] Center 36 (8~64) winsize 57
6290 18:09:22.836140 [CA 2] Center 36 (8~64) winsize 57
6291 18:09:22.839723 [CA 3] Center 36 (8~64) winsize 57
6292 18:09:22.842852 [CA 4] Center 36 (8~64) winsize 57
6293 18:09:22.846272 [CA 5] Center 36 (8~64) winsize 57
6294 18:09:22.846675
6295 18:09:22.849628 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6296 18:09:22.850030
6297 18:09:22.852691 [CATrainingPosCal] consider 1 rank data
6298 18:09:22.856341 u2DelayCellTimex100 = 270/100 ps
6299 18:09:22.859271 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 18:09:22.862916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 18:09:22.865982 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 18:09:22.869830 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 18:09:22.873131 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 18:09:22.876370 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 18:09:22.876951
6306 18:09:22.878951 CA PerBit enable=1, Macro0, CA PI delay=36
6307 18:09:22.882743
6308 18:09:22.883253 [CBTSetCACLKResult] CA Dly = 36
6309 18:09:22.886045 CS Dly: 1 (0~32)
6310 18:09:22.886592 ==
6311 18:09:22.889387 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 18:09:22.892603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 18:09:22.893053 ==
6314 18:09:22.898804 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 18:09:22.905690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6316 18:09:22.909139 [CA 0] Center 36 (8~64) winsize 57
6317 18:09:22.912252 [CA 1] Center 36 (8~64) winsize 57
6318 18:09:22.915673 [CA 2] Center 36 (8~64) winsize 57
6319 18:09:22.916102 [CA 3] Center 36 (8~64) winsize 57
6320 18:09:22.918848 [CA 4] Center 36 (8~64) winsize 57
6321 18:09:22.922039 [CA 5] Center 36 (8~64) winsize 57
6322 18:09:22.922508
6323 18:09:22.928543 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6324 18:09:22.929050
6325 18:09:22.932231 [CATrainingPosCal] consider 2 rank data
6326 18:09:22.936219 u2DelayCellTimex100 = 270/100 ps
6327 18:09:22.938295 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 18:09:22.941933 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 18:09:22.945052 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 18:09:22.949019 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 18:09:22.952010 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 18:09:22.954589 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 18:09:22.954998
6334 18:09:22.958596 CA PerBit enable=1, Macro0, CA PI delay=36
6335 18:09:22.959005
6336 18:09:22.961573 [CBTSetCACLKResult] CA Dly = 36
6337 18:09:22.965024 CS Dly: 1 (0~32)
6338 18:09:22.965429
6339 18:09:22.968296 ----->DramcWriteLeveling(PI) begin...
6340 18:09:22.968713 ==
6341 18:09:22.971192 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 18:09:22.975090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 18:09:22.975503 ==
6344 18:09:22.978108 Write leveling (Byte 0): 40 => 8
6345 18:09:22.981414 Write leveling (Byte 1): 32 => 0
6346 18:09:22.984402 DramcWriteLeveling(PI) end<-----
6347 18:09:22.984813
6348 18:09:22.985135 ==
6349 18:09:22.987817 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 18:09:22.991126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 18:09:22.991538 ==
6352 18:09:22.994553 [Gating] SW mode calibration
6353 18:09:23.001467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6354 18:09:23.007256 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6355 18:09:23.011436 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 18:09:23.017354 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 18:09:23.020460 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 18:09:23.024200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 18:09:23.030448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 18:09:23.033936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 18:09:23.037321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 18:09:23.044009 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 18:09:23.047048 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 18:09:23.050855 Total UI for P1: 0, mck2ui 16
6365 18:09:23.053963 best dqsien dly found for B0: ( 0, 14, 24)
6366 18:09:23.057209 Total UI for P1: 0, mck2ui 16
6367 18:09:23.060750 best dqsien dly found for B1: ( 0, 14, 24)
6368 18:09:23.063793 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6369 18:09:23.067199 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6370 18:09:23.067700
6371 18:09:23.070616 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 18:09:23.073764 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 18:09:23.076998 [Gating] SW calibration Done
6374 18:09:23.077406 ==
6375 18:09:23.080497 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 18:09:23.087102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 18:09:23.087594 ==
6378 18:09:23.087959 RX Vref Scan: 0
6379 18:09:23.088286
6380 18:09:23.090787 RX Vref 0 -> 0, step: 1
6381 18:09:23.091287
6382 18:09:23.093469 RX Delay -410 -> 252, step: 16
6383 18:09:23.096871 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6384 18:09:23.100670 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6385 18:09:23.106573 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6386 18:09:23.109718 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6387 18:09:23.113373 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6388 18:09:23.116358 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6389 18:09:23.123490 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6390 18:09:23.126472 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6391 18:09:23.129423 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6392 18:09:23.132914 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6393 18:09:23.140155 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6394 18:09:23.142831 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6395 18:09:23.146114 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6396 18:09:23.149734 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6397 18:09:23.155877 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6398 18:09:23.159593 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6399 18:09:23.160005 ==
6400 18:09:23.163042 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 18:09:23.166085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 18:09:23.166628 ==
6403 18:09:23.169694 DQS Delay:
6404 18:09:23.170228 DQS0 = 43, DQS1 = 59
6405 18:09:23.172942 DQM Delay:
6406 18:09:23.173440 DQM0 = 10, DQM1 = 11
6407 18:09:23.173770 DQ Delay:
6408 18:09:23.175609 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6409 18:09:23.179086 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6410 18:09:23.182325 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6411 18:09:23.185575 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6412 18:09:23.185987
6413 18:09:23.186369
6414 18:09:23.186677 ==
6415 18:09:23.188806 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 18:09:23.195598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 18:09:23.196116 ==
6418 18:09:23.196448
6419 18:09:23.196751
6420 18:09:23.197043 TX Vref Scan disable
6421 18:09:23.198769 == TX Byte 0 ==
6422 18:09:23.202268 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6423 18:09:23.205503 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6424 18:09:23.208804 == TX Byte 1 ==
6425 18:09:23.212189 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6426 18:09:23.215549 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6427 18:09:23.218523 ==
6428 18:09:23.218950 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 18:09:23.225176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 18:09:23.225706 ==
6431 18:09:23.226045
6432 18:09:23.226417
6433 18:09:23.228601 TX Vref Scan disable
6434 18:09:23.229123 == TX Byte 0 ==
6435 18:09:23.231844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 18:09:23.238884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 18:09:23.239393 == TX Byte 1 ==
6438 18:09:23.242227 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 18:09:23.248237 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 18:09:23.248746
6441 18:09:23.249071 [DATLAT]
6442 18:09:23.249368 Freq=400, CH0 RK0
6443 18:09:23.249661
6444 18:09:23.251348 DATLAT Default: 0xf
6445 18:09:23.255097 0, 0xFFFF, sum = 0
6446 18:09:23.255517 1, 0xFFFF, sum = 0
6447 18:09:23.258448 2, 0xFFFF, sum = 0
6448 18:09:23.258954 3, 0xFFFF, sum = 0
6449 18:09:23.261861 4, 0xFFFF, sum = 0
6450 18:09:23.262412 5, 0xFFFF, sum = 0
6451 18:09:23.265003 6, 0xFFFF, sum = 0
6452 18:09:23.265513 7, 0xFFFF, sum = 0
6453 18:09:23.268705 8, 0xFFFF, sum = 0
6454 18:09:23.269227 9, 0xFFFF, sum = 0
6455 18:09:23.271747 10, 0xFFFF, sum = 0
6456 18:09:23.272159 11, 0xFFFF, sum = 0
6457 18:09:23.274920 12, 0xFFFF, sum = 0
6458 18:09:23.275326 13, 0x0, sum = 1
6459 18:09:23.277864 14, 0x0, sum = 2
6460 18:09:23.278235 15, 0x0, sum = 3
6461 18:09:23.281733 16, 0x0, sum = 4
6462 18:09:23.282297 best_step = 14
6463 18:09:23.282627
6464 18:09:23.282923 ==
6465 18:09:23.284351 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 18:09:23.291498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 18:09:23.292035 ==
6468 18:09:23.292371 RX Vref Scan: 1
6469 18:09:23.292673
6470 18:09:23.294707 RX Vref 0 -> 0, step: 1
6471 18:09:23.295109
6472 18:09:23.297807 RX Delay -359 -> 252, step: 8
6473 18:09:23.298395
6474 18:09:23.301151 Set Vref, RX VrefLevel [Byte0]: 55
6475 18:09:23.304057 [Byte1]: 56
6476 18:09:23.307670
6477 18:09:23.308146 Final RX Vref Byte 0 = 55 to rank0
6478 18:09:23.310883 Final RX Vref Byte 1 = 56 to rank0
6479 18:09:23.314237 Final RX Vref Byte 0 = 55 to rank1
6480 18:09:23.317504 Final RX Vref Byte 1 = 56 to rank1==
6481 18:09:23.320675 Dram Type= 6, Freq= 0, CH_0, rank 0
6482 18:09:23.327177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 18:09:23.327631 ==
6484 18:09:23.328041 DQS Delay:
6485 18:09:23.330483 DQS0 = 48, DQS1 = 60
6486 18:09:23.330890 DQM Delay:
6487 18:09:23.331214 DQM0 = 11, DQM1 = 10
6488 18:09:23.333905 DQ Delay:
6489 18:09:23.337164 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6490 18:09:23.340177 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6491 18:09:23.343613 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6492 18:09:23.346917 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6493 18:09:23.347399
6494 18:09:23.347724
6495 18:09:23.353981 [DQSOSCAuto] RK0, (LSB)MR18= 0xb478, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6496 18:09:23.357543 CH0 RK0: MR19=C0C, MR18=B478
6497 18:09:23.363586 CH0_RK0: MR19=0xC0C, MR18=0xB478, DQSOSC=387, MR23=63, INC=394, DEC=262
6498 18:09:23.364013 ==
6499 18:09:23.366443 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 18:09:23.369981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 18:09:23.370478 ==
6502 18:09:23.373584 [Gating] SW mode calibration
6503 18:09:23.379719 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6504 18:09:23.386147 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6505 18:09:23.389791 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 18:09:23.392993 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 18:09:23.399553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 18:09:23.402977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 18:09:23.406209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 18:09:23.413042 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 18:09:23.415991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 18:09:23.419434 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 18:09:23.425942 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 18:09:23.429275 Total UI for P1: 0, mck2ui 16
6515 18:09:23.432760 best dqsien dly found for B0: ( 0, 14, 24)
6516 18:09:23.436580 Total UI for P1: 0, mck2ui 16
6517 18:09:23.439052 best dqsien dly found for B1: ( 0, 14, 24)
6518 18:09:23.442419 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6519 18:09:23.445702 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6520 18:09:23.446257
6521 18:09:23.449051 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 18:09:23.452559 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 18:09:23.455644 [Gating] SW calibration Done
6524 18:09:23.456054 ==
6525 18:09:23.458640 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 18:09:23.461996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 18:09:23.465677 ==
6528 18:09:23.466082 RX Vref Scan: 0
6529 18:09:23.466490
6530 18:09:23.468968 RX Vref 0 -> 0, step: 1
6531 18:09:23.469372
6532 18:09:23.471559 RX Delay -410 -> 252, step: 16
6533 18:09:23.475365 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6534 18:09:23.478528 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6535 18:09:23.481901 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6536 18:09:23.488163 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6537 18:09:23.491459 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6538 18:09:23.495022 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6539 18:09:23.498460 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6540 18:09:23.505146 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6541 18:09:23.507925 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6542 18:09:23.511587 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6543 18:09:23.518079 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6544 18:09:23.520784 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6545 18:09:23.524252 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6546 18:09:23.527794 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6547 18:09:23.534048 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6548 18:09:23.537692 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6549 18:09:23.538139 ==
6550 18:09:23.540793 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 18:09:23.544163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 18:09:23.544777 ==
6553 18:09:23.547393 DQS Delay:
6554 18:09:23.547982 DQS0 = 43, DQS1 = 59
6555 18:09:23.551002 DQM Delay:
6556 18:09:23.551733 DQM0 = 9, DQM1 = 15
6557 18:09:23.552349 DQ Delay:
6558 18:09:23.554258 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6559 18:09:23.557276 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6560 18:09:23.560642 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6561 18:09:23.563503 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6562 18:09:23.563911
6563 18:09:23.564232
6564 18:09:23.564563 ==
6565 18:09:23.567341 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 18:09:23.573835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 18:09:23.574272 ==
6568 18:09:23.574599
6569 18:09:23.574892
6570 18:09:23.575229 TX Vref Scan disable
6571 18:09:23.577076 == TX Byte 0 ==
6572 18:09:23.580667 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6573 18:09:23.583671 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6574 18:09:23.587187 == TX Byte 1 ==
6575 18:09:23.590051 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6576 18:09:23.593486 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6577 18:09:23.593890 ==
6578 18:09:23.596986 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 18:09:23.603693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 18:09:23.604102 ==
6581 18:09:23.604516
6582 18:09:23.604827
6583 18:09:23.605115 TX Vref Scan disable
6584 18:09:23.606605 == TX Byte 0 ==
6585 18:09:23.610096 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6586 18:09:23.613054 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6587 18:09:23.616322 == TX Byte 1 ==
6588 18:09:23.619931 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6589 18:09:23.623517 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6590 18:09:23.623924
6591 18:09:23.626683 [DATLAT]
6592 18:09:23.627087 Freq=400, CH0 RK1
6593 18:09:23.627407
6594 18:09:23.630089 DATLAT Default: 0xe
6595 18:09:23.630539 0, 0xFFFF, sum = 0
6596 18:09:23.633150 1, 0xFFFF, sum = 0
6597 18:09:23.633562 2, 0xFFFF, sum = 0
6598 18:09:23.636692 3, 0xFFFF, sum = 0
6599 18:09:23.637105 4, 0xFFFF, sum = 0
6600 18:09:23.639873 5, 0xFFFF, sum = 0
6601 18:09:23.640286 6, 0xFFFF, sum = 0
6602 18:09:23.642901 7, 0xFFFF, sum = 0
6603 18:09:23.646567 8, 0xFFFF, sum = 0
6604 18:09:23.646979 9, 0xFFFF, sum = 0
6605 18:09:23.649676 10, 0xFFFF, sum = 0
6606 18:09:23.650089 11, 0xFFFF, sum = 0
6607 18:09:23.652916 12, 0xFFFF, sum = 0
6608 18:09:23.653329 13, 0x0, sum = 1
6609 18:09:23.656387 14, 0x0, sum = 2
6610 18:09:23.656817 15, 0x0, sum = 3
6611 18:09:23.659595 16, 0x0, sum = 4
6612 18:09:23.660026 best_step = 14
6613 18:09:23.660353
6614 18:09:23.660682 ==
6615 18:09:23.662654 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 18:09:23.666326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 18:09:23.666860 ==
6618 18:09:23.669594 RX Vref Scan: 0
6619 18:09:23.670003
6620 18:09:23.672493 RX Vref 0 -> 0, step: 1
6621 18:09:23.672603
6622 18:09:23.672677 RX Delay -359 -> 252, step: 8
6623 18:09:23.681338 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6624 18:09:23.684582 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6625 18:09:23.687655 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6626 18:09:23.694395 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6627 18:09:23.698113 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6628 18:09:23.700887 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6629 18:09:23.704048 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6630 18:09:23.711075 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6631 18:09:23.713935 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6632 18:09:23.717666 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6633 18:09:23.720790 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6634 18:09:23.727637 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6635 18:09:23.730337 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6636 18:09:23.733950 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6637 18:09:23.740284 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6638 18:09:23.743730 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6639 18:09:23.743810 ==
6640 18:09:23.746913 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 18:09:23.750398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 18:09:23.750478 ==
6643 18:09:23.753805 DQS Delay:
6644 18:09:23.753884 DQS0 = 44, DQS1 = 60
6645 18:09:23.753946 DQM Delay:
6646 18:09:23.757134 DQM0 = 7, DQM1 = 14
6647 18:09:23.757214 DQ Delay:
6648 18:09:23.760116 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6649 18:09:23.763635 DQ4 =4, DQ5 =0, DQ6 =16, DQ7 =16
6650 18:09:23.766675 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6651 18:09:23.769949 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6652 18:09:23.770028
6653 18:09:23.770107
6654 18:09:23.779971 [DQSOSCAuto] RK1, (LSB)MR18= 0xae3c, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6655 18:09:23.780052 CH0 RK1: MR19=C0C, MR18=AE3C
6656 18:09:23.786456 CH0_RK1: MR19=0xC0C, MR18=0xAE3C, DQSOSC=388, MR23=63, INC=392, DEC=261
6657 18:09:23.789867 [RxdqsGatingPostProcess] freq 400
6658 18:09:23.796366 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6659 18:09:23.800025 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 18:09:23.802765 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 18:09:23.806036 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 18:09:23.809701 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 18:09:23.812990 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 18:09:23.813070 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 18:09:23.816605 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 18:09:23.819276 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 18:09:23.822787 Pre-setting of DQS Precalculation
6668 18:09:23.829514 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6669 18:09:23.829595 ==
6670 18:09:23.833170 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 18:09:23.835795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 18:09:23.835876 ==
6673 18:09:23.842445 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 18:09:23.849143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6675 18:09:23.852708 [CA 0] Center 36 (8~64) winsize 57
6676 18:09:23.855543 [CA 1] Center 36 (8~64) winsize 57
6677 18:09:23.858955 [CA 2] Center 36 (8~64) winsize 57
6678 18:09:23.862309 [CA 3] Center 36 (8~64) winsize 57
6679 18:09:23.862411 [CA 4] Center 36 (8~64) winsize 57
6680 18:09:23.865617 [CA 5] Center 36 (8~64) winsize 57
6681 18:09:23.865696
6682 18:09:23.871846 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6683 18:09:23.871927
6684 18:09:23.875772 [CATrainingPosCal] consider 1 rank data
6685 18:09:23.878595 u2DelayCellTimex100 = 270/100 ps
6686 18:09:23.881558 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 18:09:23.884958 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 18:09:23.888741 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 18:09:23.891801 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 18:09:23.895047 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 18:09:23.898771 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 18:09:23.898896
6693 18:09:23.901665 CA PerBit enable=1, Macro0, CA PI delay=36
6694 18:09:23.901745
6695 18:09:23.905162 [CBTSetCACLKResult] CA Dly = 36
6696 18:09:23.908568 CS Dly: 1 (0~32)
6697 18:09:23.908647 ==
6698 18:09:23.911445 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 18:09:23.915020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 18:09:23.915101 ==
6701 18:09:23.921443 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 18:09:23.928050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6703 18:09:23.931266 [CA 0] Center 36 (8~64) winsize 57
6704 18:09:23.934940 [CA 1] Center 36 (8~64) winsize 57
6705 18:09:23.937982 [CA 2] Center 36 (8~64) winsize 57
6706 18:09:23.938092 [CA 3] Center 36 (8~64) winsize 57
6707 18:09:23.941104 [CA 4] Center 36 (8~64) winsize 57
6708 18:09:23.944893 [CA 5] Center 36 (8~64) winsize 57
6709 18:09:23.944973
6710 18:09:23.951088 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6711 18:09:23.951168
6712 18:09:23.954484 [CATrainingPosCal] consider 2 rank data
6713 18:09:23.957819 u2DelayCellTimex100 = 270/100 ps
6714 18:09:23.961331 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 18:09:23.963999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 18:09:23.967437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 18:09:23.970855 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 18:09:23.974342 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 18:09:23.977486 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 18:09:23.977565
6721 18:09:23.980633 CA PerBit enable=1, Macro0, CA PI delay=36
6722 18:09:23.980713
6723 18:09:23.983692 [CBTSetCACLKResult] CA Dly = 36
6724 18:09:23.987384 CS Dly: 1 (0~32)
6725 18:09:23.987464
6726 18:09:23.990723 ----->DramcWriteLeveling(PI) begin...
6727 18:09:23.990805 ==
6728 18:09:23.993625 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 18:09:23.996838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 18:09:23.996925 ==
6731 18:09:24.000242 Write leveling (Byte 0): 40 => 8
6732 18:09:24.003509 Write leveling (Byte 1): 32 => 0
6733 18:09:24.006949 DramcWriteLeveling(PI) end<-----
6734 18:09:24.007096
6735 18:09:24.007163 ==
6736 18:09:24.010022 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 18:09:24.013582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 18:09:24.013663 ==
6739 18:09:24.016685 [Gating] SW mode calibration
6740 18:09:24.023449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6741 18:09:24.030255 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6742 18:09:24.033254 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 18:09:24.039889 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 18:09:24.043320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 18:09:24.046597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 18:09:24.052911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 18:09:24.056495 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 18:09:24.059539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 18:09:24.066535 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 18:09:24.069793 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 18:09:24.072839 Total UI for P1: 0, mck2ui 16
6752 18:09:24.075986 best dqsien dly found for B0: ( 0, 14, 24)
6753 18:09:24.079490 Total UI for P1: 0, mck2ui 16
6754 18:09:24.082826 best dqsien dly found for B1: ( 0, 14, 24)
6755 18:09:24.085756 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6756 18:09:24.089187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6757 18:09:24.089266
6758 18:09:24.092456 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 18:09:24.095975 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 18:09:24.099366 [Gating] SW calibration Done
6761 18:09:24.099445 ==
6762 18:09:24.102124 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 18:09:24.109229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 18:09:24.109310 ==
6765 18:09:24.109373 RX Vref Scan: 0
6766 18:09:24.109432
6767 18:09:24.112436 RX Vref 0 -> 0, step: 1
6768 18:09:24.112515
6769 18:09:24.115432 RX Delay -410 -> 252, step: 16
6770 18:09:24.118877 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6771 18:09:24.122351 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6772 18:09:24.128544 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6773 18:09:24.131995 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6774 18:09:24.135262 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6775 18:09:24.138878 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6776 18:09:24.145190 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6777 18:09:24.148685 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6778 18:09:24.152230 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6779 18:09:24.155258 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6780 18:09:24.161845 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6781 18:09:24.165317 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6782 18:09:24.168110 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6783 18:09:24.171596 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6784 18:09:24.177941 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6785 18:09:24.180986 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6786 18:09:24.181086 ==
6787 18:09:24.184551 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 18:09:24.187573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 18:09:24.190814 ==
6790 18:09:24.190894 DQS Delay:
6791 18:09:24.190957 DQS0 = 43, DQS1 = 51
6792 18:09:24.194094 DQM Delay:
6793 18:09:24.194183 DQM0 = 12, DQM1 = 14
6794 18:09:24.197416 DQ Delay:
6795 18:09:24.200744 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6796 18:09:24.200824 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6797 18:09:24.203785 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6798 18:09:24.207417 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6799 18:09:24.207497
6800 18:09:24.207560
6801 18:09:24.210277 ==
6802 18:09:24.213975 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 18:09:24.217224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 18:09:24.217304 ==
6805 18:09:24.217368
6806 18:09:24.217426
6807 18:09:24.220405 TX Vref Scan disable
6808 18:09:24.220484 == TX Byte 0 ==
6809 18:09:24.223865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 18:09:24.230272 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 18:09:24.230353 == TX Byte 1 ==
6812 18:09:24.233958 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6813 18:09:24.240251 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6814 18:09:24.240331 ==
6815 18:09:24.243444 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 18:09:24.246700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 18:09:24.246781 ==
6818 18:09:24.246843
6819 18:09:24.246902
6820 18:09:24.249867 TX Vref Scan disable
6821 18:09:24.249947 == TX Byte 0 ==
6822 18:09:24.256574 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 18:09:24.259940 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 18:09:24.260022 == TX Byte 1 ==
6825 18:09:24.266589 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6826 18:09:24.269504 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6827 18:09:24.269584
6828 18:09:24.269646 [DATLAT]
6829 18:09:24.273173 Freq=400, CH1 RK0
6830 18:09:24.273252
6831 18:09:24.273314 DATLAT Default: 0xf
6832 18:09:24.276083 0, 0xFFFF, sum = 0
6833 18:09:24.276164 1, 0xFFFF, sum = 0
6834 18:09:24.279344 2, 0xFFFF, sum = 0
6835 18:09:24.279424 3, 0xFFFF, sum = 0
6836 18:09:24.282717 4, 0xFFFF, sum = 0
6837 18:09:24.285863 5, 0xFFFF, sum = 0
6838 18:09:24.285940 6, 0xFFFF, sum = 0
6839 18:09:24.289497 7, 0xFFFF, sum = 0
6840 18:09:24.289592 8, 0xFFFF, sum = 0
6841 18:09:24.292604 9, 0xFFFF, sum = 0
6842 18:09:24.292673 10, 0xFFFF, sum = 0
6843 18:09:24.295584 11, 0xFFFF, sum = 0
6844 18:09:24.295664 12, 0xFFFF, sum = 0
6845 18:09:24.299035 13, 0x0, sum = 1
6846 18:09:24.299115 14, 0x0, sum = 2
6847 18:09:24.302141 15, 0x0, sum = 3
6848 18:09:24.302263 16, 0x0, sum = 4
6849 18:09:24.305461 best_step = 14
6850 18:09:24.305540
6851 18:09:24.305605 ==
6852 18:09:24.308953 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 18:09:24.312285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 18:09:24.312365 ==
6855 18:09:24.315613 RX Vref Scan: 1
6856 18:09:24.315693
6857 18:09:24.315756 RX Vref 0 -> 0, step: 1
6858 18:09:24.315814
6859 18:09:24.318854 RX Delay -343 -> 252, step: 8
6860 18:09:24.318934
6861 18:09:24.322429 Set Vref, RX VrefLevel [Byte0]: 48
6862 18:09:24.325278 [Byte1]: 54
6863 18:09:24.329892
6864 18:09:24.329970 Final RX Vref Byte 0 = 48 to rank0
6865 18:09:24.333344 Final RX Vref Byte 1 = 54 to rank0
6866 18:09:24.336565 Final RX Vref Byte 0 = 48 to rank1
6867 18:09:24.339752 Final RX Vref Byte 1 = 54 to rank1==
6868 18:09:24.342955 Dram Type= 6, Freq= 0, CH_1, rank 0
6869 18:09:24.349618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 18:09:24.349719 ==
6871 18:09:24.349782 DQS Delay:
6872 18:09:24.352824 DQS0 = 44, DQS1 = 56
6873 18:09:24.352904 DQM Delay:
6874 18:09:24.352967 DQM0 = 7, DQM1 = 11
6875 18:09:24.356020 DQ Delay:
6876 18:09:24.359354 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6877 18:09:24.362901 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6878 18:09:24.362980 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6879 18:09:24.365871 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6880 18:09:24.369685
6881 18:09:24.369764
6882 18:09:24.376176 [DQSOSCAuto] RK0, (LSB)MR18= 0x9167, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6883 18:09:24.379348 CH1 RK0: MR19=C0C, MR18=9167
6884 18:09:24.385891 CH1_RK0: MR19=0xC0C, MR18=0x9167, DQSOSC=391, MR23=63, INC=386, DEC=257
6885 18:09:24.385972 ==
6886 18:09:24.389417 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 18:09:24.392489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 18:09:24.392569 ==
6889 18:09:24.395356 [Gating] SW mode calibration
6890 18:09:24.402145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6891 18:09:24.408442 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6892 18:09:24.411891 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 18:09:24.415382 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 18:09:24.422057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 18:09:24.424768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 18:09:24.428391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 18:09:24.435128 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 18:09:24.438199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 18:09:24.441649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 18:09:24.448143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 18:09:24.451481 Total UI for P1: 0, mck2ui 16
6902 18:09:24.454658 best dqsien dly found for B0: ( 0, 14, 24)
6903 18:09:24.458127 Total UI for P1: 0, mck2ui 16
6904 18:09:24.461417 best dqsien dly found for B1: ( 0, 14, 24)
6905 18:09:24.464295 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6906 18:09:24.468039 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6907 18:09:24.468119
6908 18:09:24.470872 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 18:09:24.474387 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 18:09:24.477483 [Gating] SW calibration Done
6911 18:09:24.477562 ==
6912 18:09:24.480749 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 18:09:24.484180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 18:09:24.484261 ==
6915 18:09:24.487526 RX Vref Scan: 0
6916 18:09:24.487605
6917 18:09:24.490794 RX Vref 0 -> 0, step: 1
6918 18:09:24.490874
6919 18:09:24.494482 RX Delay -410 -> 252, step: 16
6920 18:09:24.497366 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6921 18:09:24.500760 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6922 18:09:24.503841 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6923 18:09:24.510567 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6924 18:09:24.514130 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6925 18:09:24.517302 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6926 18:09:24.520210 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6927 18:09:24.526817 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6928 18:09:24.530187 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6929 18:09:24.533319 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6930 18:09:24.536692 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6931 18:09:24.543350 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6932 18:09:24.546647 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6933 18:09:24.550108 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6934 18:09:24.556644 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6935 18:09:24.559881 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6936 18:09:24.559962 ==
6937 18:09:24.563185 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 18:09:24.566695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 18:09:24.566776 ==
6940 18:09:24.569628 DQS Delay:
6941 18:09:24.569707 DQS0 = 51, DQS1 = 51
6942 18:09:24.572907 DQM Delay:
6943 18:09:24.572986 DQM0 = 19, DQM1 = 14
6944 18:09:24.573050 DQ Delay:
6945 18:09:24.576295 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6946 18:09:24.579444 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6947 18:09:24.582861 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6948 18:09:24.586463 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6949 18:09:24.586543
6950 18:09:24.586607
6951 18:09:24.586664 ==
6952 18:09:24.589354 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 18:09:24.595833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 18:09:24.595914 ==
6955 18:09:24.595977
6956 18:09:24.596035
6957 18:09:24.596091 TX Vref Scan disable
6958 18:09:24.599113 == TX Byte 0 ==
6959 18:09:24.602913 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6960 18:09:24.605593 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6961 18:09:24.608915 == TX Byte 1 ==
6962 18:09:24.612555 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6963 18:09:24.615947 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6964 18:09:24.619292 ==
6965 18:09:24.619371 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 18:09:24.626098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 18:09:24.626219 ==
6968 18:09:24.626284
6969 18:09:24.626343
6970 18:09:24.626399 TX Vref Scan disable
6971 18:09:24.628996 == TX Byte 0 ==
6972 18:09:24.632343 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6973 18:09:24.635751 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6974 18:09:24.638994 == TX Byte 1 ==
6975 18:09:24.642632 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6976 18:09:24.645504 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6977 18:09:24.649009
6978 18:09:24.649089 [DATLAT]
6979 18:09:24.649152 Freq=400, CH1 RK1
6980 18:09:24.649211
6981 18:09:24.652104 DATLAT Default: 0xe
6982 18:09:24.652184 0, 0xFFFF, sum = 0
6983 18:09:24.655356 1, 0xFFFF, sum = 0
6984 18:09:24.655437 2, 0xFFFF, sum = 0
6985 18:09:24.658753 3, 0xFFFF, sum = 0
6986 18:09:24.662383 4, 0xFFFF, sum = 0
6987 18:09:24.662465 5, 0xFFFF, sum = 0
6988 18:09:24.665517 6, 0xFFFF, sum = 0
6989 18:09:24.665599 7, 0xFFFF, sum = 0
6990 18:09:24.668729 8, 0xFFFF, sum = 0
6991 18:09:24.668811 9, 0xFFFF, sum = 0
6992 18:09:24.671889 10, 0xFFFF, sum = 0
6993 18:09:24.671971 11, 0xFFFF, sum = 0
6994 18:09:24.675307 12, 0xFFFF, sum = 0
6995 18:09:24.675389 13, 0x0, sum = 1
6996 18:09:24.678679 14, 0x0, sum = 2
6997 18:09:24.678760 15, 0x0, sum = 3
6998 18:09:24.681752 16, 0x0, sum = 4
6999 18:09:24.681833 best_step = 14
7000 18:09:24.681896
7001 18:09:24.681954 ==
7002 18:09:24.685103 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 18:09:24.688454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 18:09:24.692164 ==
7005 18:09:24.692244 RX Vref Scan: 0
7006 18:09:24.692306
7007 18:09:24.694714 RX Vref 0 -> 0, step: 1
7008 18:09:24.694794
7009 18:09:24.698519 RX Delay -343 -> 252, step: 8
7010 18:09:24.704613 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7011 18:09:24.707776 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7012 18:09:24.711159 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7013 18:09:24.714732 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7014 18:09:24.721259 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7015 18:09:24.724559 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7016 18:09:24.727390 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7017 18:09:24.731072 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7018 18:09:24.737544 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7019 18:09:24.741065 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7020 18:09:24.744479 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7021 18:09:24.747864 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7022 18:09:24.754052 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7023 18:09:24.757665 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7024 18:09:24.761146 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7025 18:09:24.767641 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7026 18:09:24.767721 ==
7027 18:09:24.770634 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 18:09:24.774149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 18:09:24.774253 ==
7030 18:09:24.774316 DQS Delay:
7031 18:09:24.777219 DQS0 = 44, DQS1 = 56
7032 18:09:24.777298 DQM Delay:
7033 18:09:24.780586 DQM0 = 8, DQM1 = 11
7034 18:09:24.780665 DQ Delay:
7035 18:09:24.783541 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7036 18:09:24.787054 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
7037 18:09:24.790658 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7038 18:09:24.794064 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7039 18:09:24.794193
7040 18:09:24.794275
7041 18:09:24.800470 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b4b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7042 18:09:24.803754 CH1 RK1: MR19=C0C, MR18=5B4B
7043 18:09:24.810101 CH1_RK1: MR19=0xC0C, MR18=0x5B4B, DQSOSC=398, MR23=63, INC=372, DEC=248
7044 18:09:24.813423 [RxdqsGatingPostProcess] freq 400
7045 18:09:24.820040 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7046 18:09:24.820120 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 18:09:24.823775 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 18:09:24.826439 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 18:09:24.830073 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 18:09:24.833223 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 18:09:24.836574 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 18:09:24.840287 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 18:09:24.843591 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 18:09:24.846664 Pre-setting of DQS Precalculation
7055 18:09:24.853347 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7056 18:09:24.859761 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7057 18:09:24.866242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7058 18:09:24.866322
7059 18:09:24.866403
7060 18:09:24.869385 [Calibration Summary] 800 Mbps
7061 18:09:24.869465 CH 0, Rank 0
7062 18:09:24.872925 SW Impedance : PASS
7063 18:09:24.876107 DUTY Scan : NO K
7064 18:09:24.876187 ZQ Calibration : PASS
7065 18:09:24.879555 Jitter Meter : NO K
7066 18:09:24.883289 CBT Training : PASS
7067 18:09:24.883369 Write leveling : PASS
7068 18:09:24.886340 RX DQS gating : PASS
7069 18:09:24.889539 RX DQ/DQS(RDDQC) : PASS
7070 18:09:24.889617 TX DQ/DQS : PASS
7071 18:09:24.892557 RX DATLAT : PASS
7072 18:09:24.892636 RX DQ/DQS(Engine): PASS
7073 18:09:24.895901 TX OE : NO K
7074 18:09:24.895981 All Pass.
7075 18:09:24.896044
7076 18:09:24.899068 CH 0, Rank 1
7077 18:09:24.902585 SW Impedance : PASS
7078 18:09:24.902664 DUTY Scan : NO K
7079 18:09:24.906011 ZQ Calibration : PASS
7080 18:09:24.906091 Jitter Meter : NO K
7081 18:09:24.908768 CBT Training : PASS
7082 18:09:24.912523 Write leveling : NO K
7083 18:09:24.912603 RX DQS gating : PASS
7084 18:09:24.915627 RX DQ/DQS(RDDQC) : PASS
7085 18:09:24.919131 TX DQ/DQS : PASS
7086 18:09:24.919210 RX DATLAT : PASS
7087 18:09:24.922070 RX DQ/DQS(Engine): PASS
7088 18:09:24.925266 TX OE : NO K
7089 18:09:24.925346 All Pass.
7090 18:09:24.925408
7091 18:09:24.925466 CH 1, Rank 0
7092 18:09:24.928764 SW Impedance : PASS
7093 18:09:24.932158 DUTY Scan : NO K
7094 18:09:24.932237 ZQ Calibration : PASS
7095 18:09:24.935529 Jitter Meter : NO K
7096 18:09:24.938469 CBT Training : PASS
7097 18:09:24.938549 Write leveling : PASS
7098 18:09:24.941811 RX DQS gating : PASS
7099 18:09:24.945207 RX DQ/DQS(RDDQC) : PASS
7100 18:09:24.945286 TX DQ/DQS : PASS
7101 18:09:24.948387 RX DATLAT : PASS
7102 18:09:24.952078 RX DQ/DQS(Engine): PASS
7103 18:09:24.952156 TX OE : NO K
7104 18:09:24.955051 All Pass.
7105 18:09:24.955130
7106 18:09:24.955192 CH 1, Rank 1
7107 18:09:24.958269 SW Impedance : PASS
7108 18:09:24.958348 DUTY Scan : NO K
7109 18:09:24.961915 ZQ Calibration : PASS
7110 18:09:24.965072 Jitter Meter : NO K
7111 18:09:24.965151 CBT Training : PASS
7112 18:09:24.968148 Write leveling : NO K
7113 18:09:24.971352 RX DQS gating : PASS
7114 18:09:24.971431 RX DQ/DQS(RDDQC) : PASS
7115 18:09:24.974684 TX DQ/DQS : PASS
7116 18:09:24.978269 RX DATLAT : PASS
7117 18:09:24.978348 RX DQ/DQS(Engine): PASS
7118 18:09:24.981751 TX OE : NO K
7119 18:09:24.981830 All Pass.
7120 18:09:24.981892
7121 18:09:24.984727 DramC Write-DBI off
7122 18:09:24.988061 PER_BANK_REFRESH: Hybrid Mode
7123 18:09:24.988141 TX_TRACKING: ON
7124 18:09:24.998076 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7125 18:09:25.001096 [FAST_K] Save calibration result to emmc
7126 18:09:25.004791 dramc_set_vcore_voltage set vcore to 725000
7127 18:09:25.008254 Read voltage for 1600, 0
7128 18:09:25.008334 Vio18 = 0
7129 18:09:25.008396 Vcore = 725000
7130 18:09:25.011116 Vdram = 0
7131 18:09:25.011203 Vddq = 0
7132 18:09:25.011268 Vmddr = 0
7133 18:09:25.018108 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7134 18:09:25.021010 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7135 18:09:25.024732 MEM_TYPE=3, freq_sel=13
7136 18:09:25.028167 sv_algorithm_assistance_LP4_3733
7137 18:09:25.031097 ============ PULL DRAM RESETB DOWN ============
7138 18:09:25.034683 ========== PULL DRAM RESETB DOWN end =========
7139 18:09:25.041078 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7140 18:09:25.044312 ===================================
7141 18:09:25.044391 LPDDR4 DRAM CONFIGURATION
7142 18:09:25.047431 ===================================
7143 18:09:25.051536 EX_ROW_EN[0] = 0x0
7144 18:09:25.054490 EX_ROW_EN[1] = 0x0
7145 18:09:25.054569 LP4Y_EN = 0x0
7146 18:09:25.057576 WORK_FSP = 0x1
7147 18:09:25.057655 WL = 0x5
7148 18:09:25.060982 RL = 0x5
7149 18:09:25.061061 BL = 0x2
7150 18:09:25.064128 RPST = 0x0
7151 18:09:25.064208 RD_PRE = 0x0
7152 18:09:25.067735 WR_PRE = 0x1
7153 18:09:25.067816 WR_PST = 0x1
7154 18:09:25.070612 DBI_WR = 0x0
7155 18:09:25.070691 DBI_RD = 0x0
7156 18:09:25.073939 OTF = 0x1
7157 18:09:25.077232 ===================================
7158 18:09:25.080733 ===================================
7159 18:09:25.080813 ANA top config
7160 18:09:25.083721 ===================================
7161 18:09:25.087221 DLL_ASYNC_EN = 0
7162 18:09:25.090393 ALL_SLAVE_EN = 0
7163 18:09:25.093693 NEW_RANK_MODE = 1
7164 18:09:25.096716 DLL_IDLE_MODE = 1
7165 18:09:25.096796 LP45_APHY_COMB_EN = 1
7166 18:09:25.100135 TX_ODT_DIS = 0
7167 18:09:25.103382 NEW_8X_MODE = 1
7168 18:09:25.106948 ===================================
7169 18:09:25.110355 ===================================
7170 18:09:25.113647 data_rate = 3200
7171 18:09:25.116767 CKR = 1
7172 18:09:25.116847 DQ_P2S_RATIO = 8
7173 18:09:25.120005 ===================================
7174 18:09:25.123164 CA_P2S_RATIO = 8
7175 18:09:25.126801 DQ_CA_OPEN = 0
7176 18:09:25.129774 DQ_SEMI_OPEN = 0
7177 18:09:25.133115 CA_SEMI_OPEN = 0
7178 18:09:25.136502 CA_FULL_RATE = 0
7179 18:09:25.136581 DQ_CKDIV4_EN = 0
7180 18:09:25.139629 CA_CKDIV4_EN = 0
7181 18:09:25.143078 CA_PREDIV_EN = 0
7182 18:09:25.146576 PH8_DLY = 12
7183 18:09:25.149715 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7184 18:09:25.153181 DQ_AAMCK_DIV = 4
7185 18:09:25.156079 CA_AAMCK_DIV = 4
7186 18:09:25.156158 CA_ADMCK_DIV = 4
7187 18:09:25.159805 DQ_TRACK_CA_EN = 0
7188 18:09:25.162660 CA_PICK = 1600
7189 18:09:25.165983 CA_MCKIO = 1600
7190 18:09:25.169053 MCKIO_SEMI = 0
7191 18:09:25.172410 PLL_FREQ = 3068
7192 18:09:25.176095 DQ_UI_PI_RATIO = 32
7193 18:09:25.178894 CA_UI_PI_RATIO = 0
7194 18:09:25.182373 ===================================
7195 18:09:25.185570 ===================================
7196 18:09:25.185674 memory_type:LPDDR4
7197 18:09:25.188865 GP_NUM : 10
7198 18:09:25.188944 SRAM_EN : 1
7199 18:09:25.192273 MD32_EN : 0
7200 18:09:25.195773 ===================================
7201 18:09:25.199237 [ANA_INIT] >>>>>>>>>>>>>>
7202 18:09:25.202426 <<<<<< [CONFIGURE PHASE]: ANA_TX
7203 18:09:25.205732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7204 18:09:25.208582 ===================================
7205 18:09:25.212084 data_rate = 3200,PCW = 0X7600
7206 18:09:25.215635 ===================================
7207 18:09:25.218864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7208 18:09:25.221815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 18:09:25.228506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 18:09:25.231612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7211 18:09:25.235181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7212 18:09:25.238195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7213 18:09:25.241561 [ANA_INIT] flow start
7214 18:09:25.245147 [ANA_INIT] PLL >>>>>>>>
7215 18:09:25.245264 [ANA_INIT] PLL <<<<<<<<
7216 18:09:25.248405 [ANA_INIT] MIDPI >>>>>>>>
7217 18:09:25.251253 [ANA_INIT] MIDPI <<<<<<<<
7218 18:09:25.255203 [ANA_INIT] DLL >>>>>>>>
7219 18:09:25.255282 [ANA_INIT] DLL <<<<<<<<
7220 18:09:25.257874 [ANA_INIT] flow end
7221 18:09:25.261840 ============ LP4 DIFF to SE enter ============
7222 18:09:25.264425 ============ LP4 DIFF to SE exit ============
7223 18:09:25.267902 [ANA_INIT] <<<<<<<<<<<<<
7224 18:09:25.271403 [Flow] Enable top DCM control >>>>>
7225 18:09:25.274173 [Flow] Enable top DCM control <<<<<
7226 18:09:25.278102 Enable DLL master slave shuffle
7227 18:09:25.284145 ==============================================================
7228 18:09:25.284231 Gating Mode config
7229 18:09:25.291033 ==============================================================
7230 18:09:25.291114 Config description:
7231 18:09:25.300683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7232 18:09:25.307254 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7233 18:09:25.313923 SELPH_MODE 0: By rank 1: By Phase
7234 18:09:25.320439 ==============================================================
7235 18:09:25.320558 GAT_TRACK_EN = 1
7236 18:09:25.324161 RX_GATING_MODE = 2
7237 18:09:25.327282 RX_GATING_TRACK_MODE = 2
7238 18:09:25.330521 SELPH_MODE = 1
7239 18:09:25.333918 PICG_EARLY_EN = 1
7240 18:09:25.337493 VALID_LAT_VALUE = 1
7241 18:09:25.343788 ==============================================================
7242 18:09:25.346925 Enter into Gating configuration >>>>
7243 18:09:25.350613 Exit from Gating configuration <<<<
7244 18:09:25.353742 Enter into DVFS_PRE_config >>>>>
7245 18:09:25.363279 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7246 18:09:25.366667 Exit from DVFS_PRE_config <<<<<
7247 18:09:25.370149 Enter into PICG configuration >>>>
7248 18:09:25.373645 Exit from PICG configuration <<<<
7249 18:09:25.376620 [RX_INPUT] configuration >>>>>
7250 18:09:25.380067 [RX_INPUT] configuration <<<<<
7251 18:09:25.383158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7252 18:09:25.389747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7253 18:09:25.396522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 18:09:25.403086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 18:09:25.406468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 18:09:25.412866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 18:09:25.416140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7258 18:09:25.422654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7259 18:09:25.426447 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7260 18:09:25.429101 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7261 18:09:25.432322 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7262 18:09:25.439216 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 18:09:25.442069 ===================================
7264 18:09:25.445415 LPDDR4 DRAM CONFIGURATION
7265 18:09:25.448712 ===================================
7266 18:09:25.448791 EX_ROW_EN[0] = 0x0
7267 18:09:25.451897 EX_ROW_EN[1] = 0x0
7268 18:09:25.452005 LP4Y_EN = 0x0
7269 18:09:25.455786 WORK_FSP = 0x1
7270 18:09:25.455865 WL = 0x5
7271 18:09:25.458922 RL = 0x5
7272 18:09:25.459001 BL = 0x2
7273 18:09:25.462346 RPST = 0x0
7274 18:09:25.462425 RD_PRE = 0x0
7275 18:09:25.465853 WR_PRE = 0x1
7276 18:09:25.468488 WR_PST = 0x1
7277 18:09:25.468566 DBI_WR = 0x0
7278 18:09:25.471953 DBI_RD = 0x0
7279 18:09:25.472032 OTF = 0x1
7280 18:09:25.475164 ===================================
7281 18:09:25.478536 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7282 18:09:25.481994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7283 18:09:25.488623 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 18:09:25.492088 ===================================
7285 18:09:25.495465 LPDDR4 DRAM CONFIGURATION
7286 18:09:25.498742 ===================================
7287 18:09:25.498849 EX_ROW_EN[0] = 0x10
7288 18:09:25.501610 EX_ROW_EN[1] = 0x0
7289 18:09:25.501688 LP4Y_EN = 0x0
7290 18:09:25.505002 WORK_FSP = 0x1
7291 18:09:25.505081 WL = 0x5
7292 18:09:25.508521 RL = 0x5
7293 18:09:25.508601 BL = 0x2
7294 18:09:25.512040 RPST = 0x0
7295 18:09:25.512119 RD_PRE = 0x0
7296 18:09:25.514857 WR_PRE = 0x1
7297 18:09:25.514935 WR_PST = 0x1
7298 18:09:25.518449 DBI_WR = 0x0
7299 18:09:25.521403 DBI_RD = 0x0
7300 18:09:25.521483 OTF = 0x1
7301 18:09:25.524752 ===================================
7302 18:09:25.531978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7303 18:09:25.532060 ==
7304 18:09:25.535089 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 18:09:25.538021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7306 18:09:25.538140 ==
7307 18:09:25.541287 [Duty_Offset_Calibration]
7308 18:09:25.541366 B0:1 B1:-1 CA:0
7309 18:09:25.544761
7310 18:09:25.548093 [DutyScan_Calibration_Flow] k_type=0
7311 18:09:25.556313
7312 18:09:25.556391 ==CLK 0==
7313 18:09:25.559634 Final CLK duty delay cell = 0
7314 18:09:25.563067 [0] MAX Duty = 5093%(X100), DQS PI = 20
7315 18:09:25.566718 [0] MIN Duty = 4875%(X100), DQS PI = 10
7316 18:09:25.569460 [0] AVG Duty = 4984%(X100)
7317 18:09:25.569539
7318 18:09:25.572673 CH0 CLK Duty spec in!! Max-Min= 218%
7319 18:09:25.575870 [DutyScan_Calibration_Flow] ====Done====
7320 18:09:25.575950
7321 18:09:25.579433 [DutyScan_Calibration_Flow] k_type=1
7322 18:09:25.595654
7323 18:09:25.595733 ==DQS 0 ==
7324 18:09:25.598957 Final DQS duty delay cell = -4
7325 18:09:25.601877 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7326 18:09:25.605246 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7327 18:09:25.608704 [-4] AVG Duty = 4906%(X100)
7328 18:09:25.608783
7329 18:09:25.608845 ==DQS 1 ==
7330 18:09:25.612285 Final DQS duty delay cell = 0
7331 18:09:25.615250 [0] MAX Duty = 5156%(X100), DQS PI = 2
7332 18:09:25.618791 [0] MIN Duty = 5000%(X100), DQS PI = 20
7333 18:09:25.622002 [0] AVG Duty = 5078%(X100)
7334 18:09:25.622106
7335 18:09:25.625034 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7336 18:09:25.625113
7337 18:09:25.628492 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7338 18:09:25.631805 [DutyScan_Calibration_Flow] ====Done====
7339 18:09:25.631883
7340 18:09:25.634929 [DutyScan_Calibration_Flow] k_type=3
7341 18:09:25.652837
7342 18:09:25.652941 ==DQM 0 ==
7343 18:09:25.656016 Final DQM duty delay cell = 0
7344 18:09:25.659338 [0] MAX Duty = 5124%(X100), DQS PI = 24
7345 18:09:25.662934 [0] MIN Duty = 4907%(X100), DQS PI = 8
7346 18:09:25.666051 [0] AVG Duty = 5015%(X100)
7347 18:09:25.666130
7348 18:09:25.666231 ==DQM 1 ==
7349 18:09:25.669366 Final DQM duty delay cell = 0
7350 18:09:25.672682 [0] MAX Duty = 5031%(X100), DQS PI = 52
7351 18:09:25.675666 [0] MIN Duty = 4782%(X100), DQS PI = 22
7352 18:09:25.679166 [0] AVG Duty = 4906%(X100)
7353 18:09:25.679270
7354 18:09:25.682407 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7355 18:09:25.682489
7356 18:09:25.685636 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7357 18:09:25.689054 [DutyScan_Calibration_Flow] ====Done====
7358 18:09:25.689133
7359 18:09:25.692119 [DutyScan_Calibration_Flow] k_type=2
7360 18:09:25.709486
7361 18:09:25.709566 ==DQ 0 ==
7362 18:09:25.712753 Final DQ duty delay cell = -4
7363 18:09:25.715612 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7364 18:09:25.719055 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7365 18:09:25.722499 [-4] AVG Duty = 4953%(X100)
7366 18:09:25.722578
7367 18:09:25.722640 ==DQ 1 ==
7368 18:09:25.725726 Final DQ duty delay cell = 0
7369 18:09:25.729294 [0] MAX Duty = 5125%(X100), DQS PI = 46
7370 18:09:25.732851 [0] MIN Duty = 4969%(X100), DQS PI = 38
7371 18:09:25.735590 [0] AVG Duty = 5047%(X100)
7372 18:09:25.735669
7373 18:09:25.739210 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7374 18:09:25.739289
7375 18:09:25.742463 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7376 18:09:25.745500 [DutyScan_Calibration_Flow] ====Done====
7377 18:09:25.745578 ==
7378 18:09:25.749399 Dram Type= 6, Freq= 0, CH_1, rank 0
7379 18:09:25.751952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7380 18:09:25.752056 ==
7381 18:09:25.755836 [Duty_Offset_Calibration]
7382 18:09:25.755914 B0:-1 B1:1 CA:2
7383 18:09:25.755976
7384 18:09:25.758546 [DutyScan_Calibration_Flow] k_type=0
7385 18:09:25.769876
7386 18:09:25.769954 ==CLK 0==
7387 18:09:25.773098 Final CLK duty delay cell = 0
7388 18:09:25.776706 [0] MAX Duty = 5187%(X100), DQS PI = 22
7389 18:09:25.779852 [0] MIN Duty = 4969%(X100), DQS PI = 0
7390 18:09:25.779932 [0] AVG Duty = 5078%(X100)
7391 18:09:25.783250
7392 18:09:25.786371 CH1 CLK Duty spec in!! Max-Min= 218%
7393 18:09:25.789509 [DutyScan_Calibration_Flow] ====Done====
7394 18:09:25.789589
7395 18:09:25.792870 [DutyScan_Calibration_Flow] k_type=1
7396 18:09:25.809527
7397 18:09:25.809610 ==DQS 0 ==
7398 18:09:25.812863 Final DQS duty delay cell = 0
7399 18:09:25.816213 [0] MAX Duty = 5124%(X100), DQS PI = 18
7400 18:09:25.819242 [0] MIN Duty = 4907%(X100), DQS PI = 8
7401 18:09:25.822505 [0] AVG Duty = 5015%(X100)
7402 18:09:25.822602
7403 18:09:25.822699 ==DQS 1 ==
7404 18:09:25.826064 Final DQS duty delay cell = 0
7405 18:09:25.829345 [0] MAX Duty = 5093%(X100), DQS PI = 26
7406 18:09:25.832835 [0] MIN Duty = 4969%(X100), DQS PI = 54
7407 18:09:25.836335 [0] AVG Duty = 5031%(X100)
7408 18:09:25.836435
7409 18:09:25.839063 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7410 18:09:25.839159
7411 18:09:25.842307 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7412 18:09:25.845694 [DutyScan_Calibration_Flow] ====Done====
7413 18:09:25.845775
7414 18:09:25.849062 [DutyScan_Calibration_Flow] k_type=3
7415 18:09:25.866351
7416 18:09:25.866430 ==DQM 0 ==
7417 18:09:25.869617 Final DQM duty delay cell = 0
7418 18:09:25.873112 [0] MAX Duty = 5218%(X100), DQS PI = 34
7419 18:09:25.876118 [0] MIN Duty = 5031%(X100), DQS PI = 6
7420 18:09:25.879628 [0] AVG Duty = 5124%(X100)
7421 18:09:25.879707
7422 18:09:25.879769 ==DQM 1 ==
7423 18:09:25.883207 Final DQM duty delay cell = 0
7424 18:09:25.885954 [0] MAX Duty = 5125%(X100), DQS PI = 2
7425 18:09:25.889315 [0] MIN Duty = 4969%(X100), DQS PI = 28
7426 18:09:25.892605 [0] AVG Duty = 5047%(X100)
7427 18:09:25.892684
7428 18:09:25.895905 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7429 18:09:25.895984
7430 18:09:25.899221 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7431 18:09:25.902460 [DutyScan_Calibration_Flow] ====Done====
7432 18:09:25.902539
7433 18:09:25.906068 [DutyScan_Calibration_Flow] k_type=2
7434 18:09:25.923377
7435 18:09:25.923484 ==DQ 0 ==
7436 18:09:25.926581 Final DQ duty delay cell = 0
7437 18:09:25.929603 [0] MAX Duty = 5187%(X100), DQS PI = 32
7438 18:09:25.932907 [0] MIN Duty = 4906%(X100), DQS PI = 10
7439 18:09:25.936381 [0] AVG Duty = 5046%(X100)
7440 18:09:25.936461
7441 18:09:25.936523 ==DQ 1 ==
7442 18:09:25.939806 Final DQ duty delay cell = 0
7443 18:09:25.942857 [0] MAX Duty = 5156%(X100), DQS PI = 10
7444 18:09:25.946199 [0] MIN Duty = 4969%(X100), DQS PI = 56
7445 18:09:25.949758 [0] AVG Duty = 5062%(X100)
7446 18:09:25.949837
7447 18:09:25.952965 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7448 18:09:25.953045
7449 18:09:25.956258 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7450 18:09:25.959801 [DutyScan_Calibration_Flow] ====Done====
7451 18:09:25.962484 nWR fixed to 30
7452 18:09:25.965846 [ModeRegInit_LP4] CH0 RK0
7453 18:09:25.965926 [ModeRegInit_LP4] CH0 RK1
7454 18:09:25.969455 [ModeRegInit_LP4] CH1 RK0
7455 18:09:25.972692 [ModeRegInit_LP4] CH1 RK1
7456 18:09:25.972771 match AC timing 5
7457 18:09:25.979154 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7458 18:09:25.982237 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7459 18:09:25.985518 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7460 18:09:25.992302 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7461 18:09:25.995337 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7462 18:09:25.995416 [MiockJmeterHQA]
7463 18:09:25.999123
7464 18:09:25.999202 [DramcMiockJmeter] u1RxGatingPI = 0
7465 18:09:26.001786 0 : 4363, 4138
7466 18:09:26.001866 4 : 4363, 4138
7467 18:09:26.005420 8 : 4253, 4026
7468 18:09:26.005501 12 : 4252, 4027
7469 18:09:26.008605 16 : 4253, 4029
7470 18:09:26.008685 20 : 4252, 4027
7471 18:09:26.011937 24 : 4252, 4027
7472 18:09:26.012047 28 : 4363, 4140
7473 18:09:26.012139 32 : 4253, 4026
7474 18:09:26.015552 36 : 4252, 4030
7475 18:09:26.015632 40 : 4250, 4027
7476 18:09:26.018977 44 : 4363, 4137
7477 18:09:26.019057 48 : 4250, 4027
7478 18:09:26.021829 52 : 4360, 4138
7479 18:09:26.021928 56 : 4250, 4027
7480 18:09:26.022020 60 : 4250, 4027
7481 18:09:26.025392 64 : 4250, 4026
7482 18:09:26.025478 68 : 4252, 4029
7483 18:09:26.028814 72 : 4250, 4027
7484 18:09:26.028904 76 : 4250, 4027
7485 18:09:26.031534 80 : 4363, 4140
7486 18:09:26.031614 84 : 4250, 4026
7487 18:09:26.035257 88 : 4252, 4029
7488 18:09:26.035336 92 : 4250, 378
7489 18:09:26.035400 96 : 4250, 0
7490 18:09:26.038560 100 : 4361, 0
7491 18:09:26.038641 104 : 4249, 0
7492 18:09:26.042093 108 : 4250, 0
7493 18:09:26.042218 112 : 4250, 0
7494 18:09:26.042284 116 : 4249, 0
7495 18:09:26.044911 120 : 4363, 0
7496 18:09:26.044991 124 : 4250, 0
7497 18:09:26.048499 128 : 4250, 0
7498 18:09:26.048579 132 : 4250, 0
7499 18:09:26.048643 136 : 4252, 0
7500 18:09:26.051575 140 : 4250, 0
7501 18:09:26.051655 144 : 4250, 0
7502 18:09:26.054982 148 : 4252, 0
7503 18:09:26.055062 152 : 4361, 0
7504 18:09:26.055126 156 : 4250, 0
7505 18:09:26.058299 160 : 4250, 0
7506 18:09:26.058379 164 : 4250, 0
7507 18:09:26.058442 168 : 4360, 0
7508 18:09:26.061496 172 : 4360, 0
7509 18:09:26.061576 176 : 4250, 0
7510 18:09:26.064581 180 : 4250, 0
7511 18:09:26.064662 184 : 4250, 0
7512 18:09:26.064725 188 : 4252, 0
7513 18:09:26.067834 192 : 4250, 0
7514 18:09:26.067915 196 : 4250, 0
7515 18:09:26.071265 200 : 4252, 0
7516 18:09:26.071345 204 : 4361, 0
7517 18:09:26.071409 208 : 4250, 0
7518 18:09:26.074803 212 : 4250, 0
7519 18:09:26.074883 216 : 4250, 0
7520 18:09:26.077636 220 : 4360, 0
7521 18:09:26.077717 224 : 4360, 36
7522 18:09:26.077780 228 : 4361, 3327
7523 18:09:26.081103 232 : 4250, 4027
7524 18:09:26.081183 236 : 4362, 4140
7525 18:09:26.084279 240 : 4252, 4029
7526 18:09:26.084360 244 : 4250, 4026
7527 18:09:26.087587 248 : 4250, 4027
7528 18:09:26.087667 252 : 4252, 4029
7529 18:09:26.090888 256 : 4250, 4027
7530 18:09:26.090969 260 : 4250, 4026
7531 18:09:26.094124 264 : 4250, 4027
7532 18:09:26.094213 268 : 4252, 4030
7533 18:09:26.097612 272 : 4250, 4027
7534 18:09:26.097692 276 : 4361, 4137
7535 18:09:26.100839 280 : 4361, 4137
7536 18:09:26.100919 284 : 4250, 4026
7537 18:09:26.104219 288 : 4363, 4140
7538 18:09:26.104299 292 : 4361, 4137
7539 18:09:26.104363 296 : 4250, 4026
7540 18:09:26.107918 300 : 4250, 4027
7541 18:09:26.107998 304 : 4252, 4029
7542 18:09:26.110889 308 : 4250, 4026
7543 18:09:26.110970 312 : 4253, 4026
7544 18:09:26.114044 316 : 4250, 4027
7545 18:09:26.114125 320 : 4252, 4029
7546 18:09:26.117402 324 : 4250, 4027
7547 18:09:26.117483 328 : 4360, 4137
7548 18:09:26.120958 332 : 4363, 4137
7549 18:09:26.121039 336 : 4250, 3923
7550 18:09:26.124033 340 : 4363, 2088
7551 18:09:26.124113
7552 18:09:26.124175 MIOCK jitter meter ch=0
7553 18:09:26.124234
7554 18:09:26.127336 1T = (340-92) = 248 dly cells
7555 18:09:26.133661 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7556 18:09:26.133741 ==
7557 18:09:26.137475 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 18:09:26.140399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 18:09:26.140480 ==
7560 18:09:26.147053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 18:09:26.150444 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 18:09:26.156651 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 18:09:26.159965 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 18:09:26.170266 [CA 0] Center 43 (12~74) winsize 63
7565 18:09:26.173503 [CA 1] Center 42 (12~73) winsize 62
7566 18:09:26.176786 [CA 2] Center 38 (9~68) winsize 60
7567 18:09:26.180072 [CA 3] Center 38 (8~68) winsize 61
7568 18:09:26.183480 [CA 4] Center 36 (7~66) winsize 60
7569 18:09:26.187247 [CA 5] Center 35 (6~65) winsize 60
7570 18:09:26.187326
7571 18:09:26.190004 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 18:09:26.190108
7573 18:09:26.193395 [CATrainingPosCal] consider 1 rank data
7574 18:09:26.196797 u2DelayCellTimex100 = 262/100 ps
7575 18:09:26.203535 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7576 18:09:26.206929 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7577 18:09:26.210043 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7578 18:09:26.213003 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7579 18:09:26.216649 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7580 18:09:26.219804 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7581 18:09:26.219883
7582 18:09:26.222789 CA PerBit enable=1, Macro0, CA PI delay=35
7583 18:09:26.222869
7584 18:09:26.226366 [CBTSetCACLKResult] CA Dly = 35
7585 18:09:26.229747 CS Dly: 11 (0~42)
7586 18:09:26.233204 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 18:09:26.236272 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 18:09:26.236351 ==
7589 18:09:26.239457 Dram Type= 6, Freq= 0, CH_0, rank 1
7590 18:09:26.246206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 18:09:26.246301 ==
7592 18:09:26.249552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7593 18:09:26.256292 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7594 18:09:26.259789 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7595 18:09:26.265972 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7596 18:09:26.273996 [CA 0] Center 43 (13~74) winsize 62
7597 18:09:26.276992 [CA 1] Center 44 (14~74) winsize 61
7598 18:09:26.280630 [CA 2] Center 38 (9~68) winsize 60
7599 18:09:26.283805 [CA 3] Center 38 (9~68) winsize 60
7600 18:09:26.286925 [CA 4] Center 36 (7~66) winsize 60
7601 18:09:26.290110 [CA 5] Center 36 (7~66) winsize 60
7602 18:09:26.290225
7603 18:09:26.293632 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7604 18:09:26.293711
7605 18:09:26.296623 [CATrainingPosCal] consider 2 rank data
7606 18:09:26.300222 u2DelayCellTimex100 = 262/100 ps
7607 18:09:26.306548 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7608 18:09:26.310130 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7609 18:09:26.313204 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7610 18:09:26.316934 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7611 18:09:26.319814 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7612 18:09:26.323222 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7613 18:09:26.323301
7614 18:09:26.326225 CA PerBit enable=1, Macro0, CA PI delay=36
7615 18:09:26.326304
7616 18:09:26.330101 [CBTSetCACLKResult] CA Dly = 36
7617 18:09:26.333250 CS Dly: 11 (0~43)
7618 18:09:26.336038 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7619 18:09:26.339573 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7620 18:09:26.339652
7621 18:09:26.342732 ----->DramcWriteLeveling(PI) begin...
7622 18:09:26.345958 ==
7623 18:09:26.346037 Dram Type= 6, Freq= 0, CH_0, rank 0
7624 18:09:26.352438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7625 18:09:26.352531 ==
7626 18:09:26.355893 Write leveling (Byte 0): 37 => 37
7627 18:09:26.359081 Write leveling (Byte 1): 26 => 26
7628 18:09:26.362331 DramcWriteLeveling(PI) end<-----
7629 18:09:26.362410
7630 18:09:26.362472 ==
7631 18:09:26.365945 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 18:09:26.369190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 18:09:26.369270 ==
7634 18:09:26.372747 [Gating] SW mode calibration
7635 18:09:26.379070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7636 18:09:26.385563 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7637 18:09:26.388953 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 18:09:26.392344 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 18:09:26.399133 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 18:09:26.401860 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7641 18:09:26.405167 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7642 18:09:26.411936 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7643 18:09:26.415117 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
7644 18:09:26.418379 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 18:09:26.425200 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 18:09:26.428257 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 18:09:26.431536 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7648 18:09:26.439048 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7649 18:09:26.441645 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7650 18:09:26.445255 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7651 18:09:26.451515 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7652 18:09:26.454585 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 18:09:26.458129 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 18:09:26.465074 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 18:09:26.468774 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 18:09:26.471645 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7657 18:09:26.478322 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7658 18:09:26.481467 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7659 18:09:26.484407 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7660 18:09:26.488021 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 18:09:26.494450 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 18:09:26.497984 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 18:09:26.501449 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 18:09:26.507730 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 18:09:26.511097 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7666 18:09:26.514467 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7667 18:09:26.521133 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7668 18:09:26.524163 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 18:09:26.527295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 18:09:26.533924 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 18:09:26.537456 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 18:09:26.541074 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 18:09:26.547541 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 18:09:26.550728 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 18:09:26.553827 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 18:09:26.560667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 18:09:26.563831 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 18:09:26.567363 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 18:09:26.573876 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 18:09:26.576990 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7681 18:09:26.580146 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7682 18:09:26.583444 Total UI for P1: 0, mck2ui 16
7683 18:09:26.586864 best dqsien dly found for B0: ( 1, 9, 12)
7684 18:09:26.593763 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7685 18:09:26.596438 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7686 18:09:26.600080 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 18:09:26.603493 Total UI for P1: 0, mck2ui 16
7688 18:09:26.606966 best dqsien dly found for B1: ( 1, 9, 22)
7689 18:09:26.609679 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7690 18:09:26.616541 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7691 18:09:26.616620
7692 18:09:26.619537 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7693 18:09:26.622888 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7694 18:09:26.626575 [Gating] SW calibration Done
7695 18:09:26.626655 ==
7696 18:09:26.629807 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 18:09:26.633440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 18:09:26.633515 ==
7699 18:09:26.636550 RX Vref Scan: 0
7700 18:09:26.636629
7701 18:09:26.636692 RX Vref 0 -> 0, step: 1
7702 18:09:26.636750
7703 18:09:26.639870 RX Delay 0 -> 252, step: 8
7704 18:09:26.642764 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7705 18:09:26.649110 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7706 18:09:26.652827 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7707 18:09:26.655836 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7708 18:09:26.659025 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7709 18:09:26.662268 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7710 18:09:26.668857 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7711 18:09:26.672471 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7712 18:09:26.675966 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7713 18:09:26.678898 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7714 18:09:26.685032 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7715 18:09:26.688579 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7716 18:09:26.691848 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7717 18:09:26.695148 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7718 18:09:26.698165 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7719 18:09:26.704908 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7720 18:09:26.705017 ==
7721 18:09:26.708540 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 18:09:26.711533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 18:09:26.711613 ==
7724 18:09:26.711676 DQS Delay:
7725 18:09:26.714608 DQS0 = 0, DQS1 = 0
7726 18:09:26.714687 DQM Delay:
7727 18:09:26.718139 DQM0 = 134, DQM1 = 126
7728 18:09:26.718257 DQ Delay:
7729 18:09:26.721563 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7730 18:09:26.724847 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7731 18:09:26.728137 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7732 18:09:26.734668 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7733 18:09:26.734755
7734 18:09:26.734838
7735 18:09:26.734916 ==
7736 18:09:26.738102 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 18:09:26.741359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 18:09:26.741455 ==
7739 18:09:26.741550
7740 18:09:26.741640
7741 18:09:26.744877 TX Vref Scan disable
7742 18:09:26.744971 == TX Byte 0 ==
7743 18:09:26.750986 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7744 18:09:26.754201 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7745 18:09:26.754284 == TX Byte 1 ==
7746 18:09:26.760950 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7747 18:09:26.764262 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7748 18:09:26.764344 ==
7749 18:09:26.767592 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 18:09:26.771145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 18:09:26.771227 ==
7752 18:09:26.785677
7753 18:09:26.788960 TX Vref early break, caculate TX vref
7754 18:09:26.792512 TX Vref=16, minBit 6, minWin=22, winSum=366
7755 18:09:26.795777 TX Vref=18, minBit 2, minWin=23, winSum=379
7756 18:09:26.799308 TX Vref=20, minBit 6, minWin=23, winSum=388
7757 18:09:26.802187 TX Vref=22, minBit 3, minWin=24, winSum=403
7758 18:09:26.805284 TX Vref=24, minBit 1, minWin=25, winSum=407
7759 18:09:26.812205 TX Vref=26, minBit 6, minWin=25, winSum=415
7760 18:09:26.815903 TX Vref=28, minBit 4, minWin=25, winSum=417
7761 18:09:26.818940 TX Vref=30, minBit 4, minWin=24, winSum=408
7762 18:09:26.822461 TX Vref=32, minBit 0, minWin=24, winSum=399
7763 18:09:26.825731 TX Vref=34, minBit 5, minWin=23, winSum=390
7764 18:09:26.832567 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7765 18:09:26.832647
7766 18:09:26.835839 Final TX Range 0 Vref 28
7767 18:09:26.835920
7768 18:09:26.835983 ==
7769 18:09:26.838574 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 18:09:26.842289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 18:09:26.842369 ==
7772 18:09:26.842433
7773 18:09:26.842491
7774 18:09:26.845552 TX Vref Scan disable
7775 18:09:26.852027 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7776 18:09:26.852107 == TX Byte 0 ==
7777 18:09:26.855366 u2DelayCellOfst[0]=14 cells (4 PI)
7778 18:09:26.858577 u2DelayCellOfst[1]=14 cells (4 PI)
7779 18:09:26.861637 u2DelayCellOfst[2]=11 cells (3 PI)
7780 18:09:26.864945 u2DelayCellOfst[3]=14 cells (4 PI)
7781 18:09:26.868438 u2DelayCellOfst[4]=7 cells (2 PI)
7782 18:09:26.871754 u2DelayCellOfst[5]=0 cells (0 PI)
7783 18:09:26.874908 u2DelayCellOfst[6]=18 cells (5 PI)
7784 18:09:26.878153 u2DelayCellOfst[7]=18 cells (5 PI)
7785 18:09:26.881343 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7786 18:09:26.884690 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7787 18:09:26.888050 == TX Byte 1 ==
7788 18:09:26.891412 u2DelayCellOfst[8]=0 cells (0 PI)
7789 18:09:26.894569 u2DelayCellOfst[9]=3 cells (1 PI)
7790 18:09:26.894649 u2DelayCellOfst[10]=7 cells (2 PI)
7791 18:09:26.897668 u2DelayCellOfst[11]=3 cells (1 PI)
7792 18:09:26.901188 u2DelayCellOfst[12]=14 cells (4 PI)
7793 18:09:26.904774 u2DelayCellOfst[13]=14 cells (4 PI)
7794 18:09:26.907632 u2DelayCellOfst[14]=18 cells (5 PI)
7795 18:09:26.911052 u2DelayCellOfst[15]=14 cells (4 PI)
7796 18:09:26.917977 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7797 18:09:26.920833 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7798 18:09:26.920912 DramC Write-DBI on
7799 18:09:26.920975 ==
7800 18:09:26.924259 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 18:09:26.930709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 18:09:26.930789 ==
7803 18:09:26.930852
7804 18:09:26.930910
7805 18:09:26.934347 TX Vref Scan disable
7806 18:09:26.934426 == TX Byte 0 ==
7807 18:09:26.940615 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7808 18:09:26.940694 == TX Byte 1 ==
7809 18:09:26.943928 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7810 18:09:26.946914 DramC Write-DBI off
7811 18:09:26.946993
7812 18:09:26.947055 [DATLAT]
7813 18:09:26.950478 Freq=1600, CH0 RK0
7814 18:09:26.950558
7815 18:09:26.950620 DATLAT Default: 0xf
7816 18:09:26.953823 0, 0xFFFF, sum = 0
7817 18:09:26.953904 1, 0xFFFF, sum = 0
7818 18:09:26.957178 2, 0xFFFF, sum = 0
7819 18:09:26.957258 3, 0xFFFF, sum = 0
7820 18:09:26.960663 4, 0xFFFF, sum = 0
7821 18:09:26.960743 5, 0xFFFF, sum = 0
7822 18:09:26.964141 6, 0xFFFF, sum = 0
7823 18:09:26.966912 7, 0xFFFF, sum = 0
7824 18:09:26.966995 8, 0xFFFF, sum = 0
7825 18:09:26.970285 9, 0xFFFF, sum = 0
7826 18:09:26.970366 10, 0xFFFF, sum = 0
7827 18:09:26.973749 11, 0xFFFF, sum = 0
7828 18:09:26.973830 12, 0xFFFF, sum = 0
7829 18:09:26.977012 13, 0xFFFF, sum = 0
7830 18:09:26.977092 14, 0x0, sum = 1
7831 18:09:26.980166 15, 0x0, sum = 2
7832 18:09:26.980246 16, 0x0, sum = 3
7833 18:09:26.983570 17, 0x0, sum = 4
7834 18:09:26.983651 best_step = 15
7835 18:09:26.983714
7836 18:09:26.983772 ==
7837 18:09:26.987066 Dram Type= 6, Freq= 0, CH_0, rank 0
7838 18:09:26.990120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7839 18:09:26.993104 ==
7840 18:09:26.993183 RX Vref Scan: 1
7841 18:09:26.993245
7842 18:09:26.996525 Set Vref Range= 24 -> 127
7843 18:09:26.996605
7844 18:09:27.000386 RX Vref 24 -> 127, step: 1
7845 18:09:27.000465
7846 18:09:27.000528 RX Delay 11 -> 252, step: 4
7847 18:09:27.000586
7848 18:09:27.003517 Set Vref, RX VrefLevel [Byte0]: 24
7849 18:09:27.006706 [Byte1]: 24
7850 18:09:27.010373
7851 18:09:27.010452 Set Vref, RX VrefLevel [Byte0]: 25
7852 18:09:27.013555 [Byte1]: 25
7853 18:09:27.018134
7854 18:09:27.018251 Set Vref, RX VrefLevel [Byte0]: 26
7855 18:09:27.021422 [Byte1]: 26
7856 18:09:27.025489
7857 18:09:27.025559 Set Vref, RX VrefLevel [Byte0]: 27
7858 18:09:27.028867 [Byte1]: 27
7859 18:09:27.033219
7860 18:09:27.033298 Set Vref, RX VrefLevel [Byte0]: 28
7861 18:09:27.036524 [Byte1]: 28
7862 18:09:27.040951
7863 18:09:27.041030 Set Vref, RX VrefLevel [Byte0]: 29
7864 18:09:27.043993 [Byte1]: 29
7865 18:09:27.048733
7866 18:09:27.048812 Set Vref, RX VrefLevel [Byte0]: 30
7867 18:09:27.051700 [Byte1]: 30
7868 18:09:27.056536
7869 18:09:27.056615 Set Vref, RX VrefLevel [Byte0]: 31
7870 18:09:27.059152 [Byte1]: 31
7871 18:09:27.063928
7872 18:09:27.064006 Set Vref, RX VrefLevel [Byte0]: 32
7873 18:09:27.067279 [Byte1]: 32
7874 18:09:27.071186
7875 18:09:27.071265 Set Vref, RX VrefLevel [Byte0]: 33
7876 18:09:27.074816 [Byte1]: 33
7877 18:09:27.079234
7878 18:09:27.079316 Set Vref, RX VrefLevel [Byte0]: 34
7879 18:09:27.082514 [Byte1]: 34
7880 18:09:27.086845
7881 18:09:27.086923 Set Vref, RX VrefLevel [Byte0]: 35
7882 18:09:27.090116 [Byte1]: 35
7883 18:09:27.094266
7884 18:09:27.094344 Set Vref, RX VrefLevel [Byte0]: 36
7885 18:09:27.097853 [Byte1]: 36
7886 18:09:27.102114
7887 18:09:27.102258 Set Vref, RX VrefLevel [Byte0]: 37
7888 18:09:27.104914 [Byte1]: 37
7889 18:09:27.110013
7890 18:09:27.110091 Set Vref, RX VrefLevel [Byte0]: 38
7891 18:09:27.112985 [Byte1]: 38
7892 18:09:27.116942
7893 18:09:27.117021 Set Vref, RX VrefLevel [Byte0]: 39
7894 18:09:27.120338 [Byte1]: 39
7895 18:09:27.124746
7896 18:09:27.124824 Set Vref, RX VrefLevel [Byte0]: 40
7897 18:09:27.128180 [Byte1]: 40
7898 18:09:27.132047
7899 18:09:27.132125 Set Vref, RX VrefLevel [Byte0]: 41
7900 18:09:27.135485 [Byte1]: 41
7901 18:09:27.140380
7902 18:09:27.140474 Set Vref, RX VrefLevel [Byte0]: 42
7903 18:09:27.146897 [Byte1]: 42
7904 18:09:27.146976
7905 18:09:27.149379 Set Vref, RX VrefLevel [Byte0]: 43
7906 18:09:27.152857 [Byte1]: 43
7907 18:09:27.152936
7908 18:09:27.156344 Set Vref, RX VrefLevel [Byte0]: 44
7909 18:09:27.159266 [Byte1]: 44
7910 18:09:27.162810
7911 18:09:27.162889 Set Vref, RX VrefLevel [Byte0]: 45
7912 18:09:27.165971 [Byte1]: 45
7913 18:09:27.170311
7914 18:09:27.170389 Set Vref, RX VrefLevel [Byte0]: 46
7915 18:09:27.173581 [Byte1]: 46
7916 18:09:27.177900
7917 18:09:27.177979 Set Vref, RX VrefLevel [Byte0]: 47
7918 18:09:27.181385 [Byte1]: 47
7919 18:09:27.185761
7920 18:09:27.185839 Set Vref, RX VrefLevel [Byte0]: 48
7921 18:09:27.188666 [Byte1]: 48
7922 18:09:27.193218
7923 18:09:27.193297 Set Vref, RX VrefLevel [Byte0]: 49
7924 18:09:27.196865 [Byte1]: 49
7925 18:09:27.200923
7926 18:09:27.201002 Set Vref, RX VrefLevel [Byte0]: 50
7927 18:09:27.204047 [Byte1]: 50
7928 18:09:27.208425
7929 18:09:27.208504 Set Vref, RX VrefLevel [Byte0]: 51
7930 18:09:27.211867 [Byte1]: 51
7931 18:09:27.216271
7932 18:09:27.216350 Set Vref, RX VrefLevel [Byte0]: 52
7933 18:09:27.219101 [Byte1]: 52
7934 18:09:27.223765
7935 18:09:27.223843 Set Vref, RX VrefLevel [Byte0]: 53
7936 18:09:27.227027 [Byte1]: 53
7937 18:09:27.231478
7938 18:09:27.231557 Set Vref, RX VrefLevel [Byte0]: 54
7939 18:09:27.234603 [Byte1]: 54
7940 18:09:27.238974
7941 18:09:27.239053 Set Vref, RX VrefLevel [Byte0]: 55
7942 18:09:27.245309 [Byte1]: 55
7943 18:09:27.245388
7944 18:09:27.248501 Set Vref, RX VrefLevel [Byte0]: 56
7945 18:09:27.251885 [Byte1]: 56
7946 18:09:27.251965
7947 18:09:27.255505 Set Vref, RX VrefLevel [Byte0]: 57
7948 18:09:27.258777 [Byte1]: 57
7949 18:09:27.261582
7950 18:09:27.261661 Set Vref, RX VrefLevel [Byte0]: 58
7951 18:09:27.264973 [Byte1]: 58
7952 18:09:27.269182
7953 18:09:27.269260 Set Vref, RX VrefLevel [Byte0]: 59
7954 18:09:27.272337 [Byte1]: 59
7955 18:09:27.276664
7956 18:09:27.276742 Set Vref, RX VrefLevel [Byte0]: 60
7957 18:09:27.280095 [Byte1]: 60
7958 18:09:27.284942
7959 18:09:27.285021 Set Vref, RX VrefLevel [Byte0]: 61
7960 18:09:27.287649 [Byte1]: 61
7961 18:09:27.291946
7962 18:09:27.292025 Set Vref, RX VrefLevel [Byte0]: 62
7963 18:09:27.295177 [Byte1]: 62
7964 18:09:27.299741
7965 18:09:27.299820 Set Vref, RX VrefLevel [Byte0]: 63
7966 18:09:27.303156 [Byte1]: 63
7967 18:09:27.307522
7968 18:09:27.307601 Set Vref, RX VrefLevel [Byte0]: 64
7969 18:09:27.310730 [Byte1]: 64
7970 18:09:27.314719
7971 18:09:27.314798 Set Vref, RX VrefLevel [Byte0]: 65
7972 18:09:27.317935 [Byte1]: 65
7973 18:09:27.322934
7974 18:09:27.323012 Set Vref, RX VrefLevel [Byte0]: 66
7975 18:09:27.328653 [Byte1]: 66
7976 18:09:27.328732
7977 18:09:27.332070 Set Vref, RX VrefLevel [Byte0]: 67
7978 18:09:27.335388 [Byte1]: 67
7979 18:09:27.335468
7980 18:09:27.338750 Set Vref, RX VrefLevel [Byte0]: 68
7981 18:09:27.341824 [Byte1]: 68
7982 18:09:27.345533
7983 18:09:27.345612 Set Vref, RX VrefLevel [Byte0]: 69
7984 18:09:27.349018 [Byte1]: 69
7985 18:09:27.352916
7986 18:09:27.352995 Set Vref, RX VrefLevel [Byte0]: 70
7987 18:09:27.356450 [Byte1]: 70
7988 18:09:27.360912
7989 18:09:27.360991 Set Vref, RX VrefLevel [Byte0]: 71
7990 18:09:27.363948 [Byte1]: 71
7991 18:09:27.368292
7992 18:09:27.368371 Set Vref, RX VrefLevel [Byte0]: 72
7993 18:09:27.372144 [Byte1]: 72
7994 18:09:27.375862
7995 18:09:27.375941 Set Vref, RX VrefLevel [Byte0]: 73
7996 18:09:27.379235 [Byte1]: 73
7997 18:09:27.383535
7998 18:09:27.383613 Set Vref, RX VrefLevel [Byte0]: 74
7999 18:09:27.386981 [Byte1]: 74
8000 18:09:27.391248
8001 18:09:27.391327 Set Vref, RX VrefLevel [Byte0]: 75
8002 18:09:27.394555 [Byte1]: 75
8003 18:09:27.398858
8004 18:09:27.398936 Set Vref, RX VrefLevel [Byte0]: 76
8005 18:09:27.401904 [Byte1]: 76
8006 18:09:27.406246
8007 18:09:27.406325 Set Vref, RX VrefLevel [Byte0]: 77
8008 18:09:27.409507 [Byte1]: 77
8009 18:09:27.414044
8010 18:09:27.414144 Set Vref, RX VrefLevel [Byte0]: 78
8011 18:09:27.417442 [Byte1]: 78
8012 18:09:27.421719
8013 18:09:27.421801 Set Vref, RX VrefLevel [Byte0]: 79
8014 18:09:27.425402 [Byte1]: 79
8015 18:09:27.428890
8016 18:09:27.428976 Final RX Vref Byte 0 = 65 to rank0
8017 18:09:27.432274 Final RX Vref Byte 1 = 58 to rank0
8018 18:09:27.435937 Final RX Vref Byte 0 = 65 to rank1
8019 18:09:27.438784 Final RX Vref Byte 1 = 58 to rank1==
8020 18:09:27.442468 Dram Type= 6, Freq= 0, CH_0, rank 0
8021 18:09:27.448804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8022 18:09:27.448883 ==
8023 18:09:27.448946 DQS Delay:
8024 18:09:27.452096 DQS0 = 0, DQS1 = 0
8025 18:09:27.452176 DQM Delay:
8026 18:09:27.452239 DQM0 = 132, DQM1 = 123
8027 18:09:27.455450 DQ Delay:
8028 18:09:27.458769 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8029 18:09:27.462305 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8030 18:09:27.465627 DQ8 =116, DQ9 =112, DQ10 =122, DQ11 =118
8031 18:09:27.468544 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8032 18:09:27.468624
8033 18:09:27.468686
8034 18:09:27.468743
8035 18:09:27.471957 [DramC_TX_OE_Calibration] TA2
8036 18:09:27.475319 Original DQ_B0 (3 6) =30, OEN = 27
8037 18:09:27.478652 Original DQ_B1 (3 6) =30, OEN = 27
8038 18:09:27.482190 24, 0x0, End_B0=24 End_B1=24
8039 18:09:27.482284 25, 0x0, End_B0=25 End_B1=25
8040 18:09:27.485095 26, 0x0, End_B0=26 End_B1=26
8041 18:09:27.488527 27, 0x0, End_B0=27 End_B1=27
8042 18:09:27.491997 28, 0x0, End_B0=28 End_B1=28
8043 18:09:27.495277 29, 0x0, End_B0=29 End_B1=29
8044 18:09:27.495358 30, 0x0, End_B0=30 End_B1=30
8045 18:09:27.498114 31, 0x4141, End_B0=30 End_B1=30
8046 18:09:27.501576 Byte0 end_step=30 best_step=27
8047 18:09:27.505015 Byte1 end_step=30 best_step=27
8048 18:09:27.508128 Byte0 TX OE(2T, 0.5T) = (3, 3)
8049 18:09:27.511378 Byte1 TX OE(2T, 0.5T) = (3, 3)
8050 18:09:27.511457
8051 18:09:27.511519
8052 18:09:27.518299 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8053 18:09:27.521164 CH0 RK0: MR19=303, MR18=2011
8054 18:09:27.527892 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8055 18:09:27.527996
8056 18:09:27.531533 ----->DramcWriteLeveling(PI) begin...
8057 18:09:27.531617 ==
8058 18:09:27.534498 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 18:09:27.538321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 18:09:27.538402 ==
8061 18:09:27.541141 Write leveling (Byte 0): 35 => 35
8062 18:09:27.544579 Write leveling (Byte 1): 29 => 29
8063 18:09:27.547535 DramcWriteLeveling(PI) end<-----
8064 18:09:27.547615
8065 18:09:27.547678 ==
8066 18:09:27.550870 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 18:09:27.554350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 18:09:27.558120 ==
8069 18:09:27.558220 [Gating] SW mode calibration
8070 18:09:27.567847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8071 18:09:27.571185 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8072 18:09:27.574149 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 18:09:27.580818 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 18:09:27.583985 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 18:09:27.587224 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8076 18:09:27.593893 1 4 16 | B1->B0 | 2322 3332 | 1 1 | (0 0) (0 0)
8077 18:09:27.597307 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8078 18:09:27.600637 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 18:09:27.607344 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 18:09:27.610461 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 18:09:27.613785 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8082 18:09:27.620309 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8083 18:09:27.623457 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8084 18:09:27.626899 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8085 18:09:27.633750 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8086 18:09:27.636792 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8087 18:09:27.640256 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 18:09:27.646756 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 18:09:27.650067 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 18:09:27.653352 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 18:09:27.660019 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8092 18:09:27.663394 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8093 18:09:27.666534 1 6 20 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8094 18:09:27.673179 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 18:09:27.676642 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 18:09:27.679782 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 18:09:27.686346 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 18:09:27.689608 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 18:09:27.692588 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8100 18:09:27.699505 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 18:09:27.702881 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8102 18:09:27.705811 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 18:09:27.712704 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 18:09:27.715773 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 18:09:27.718958 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 18:09:27.725783 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 18:09:27.729251 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 18:09:27.735229 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 18:09:27.738832 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 18:09:27.742141 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 18:09:27.748915 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 18:09:27.751910 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 18:09:27.755345 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 18:09:27.762128 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 18:09:27.764944 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8116 18:09:27.768302 Total UI for P1: 0, mck2ui 16
8117 18:09:27.772014 best dqsien dly found for B0: ( 1, 9, 8)
8118 18:09:27.774958 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 18:09:27.778673 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 18:09:27.785111 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 18:09:27.788706 Total UI for P1: 0, mck2ui 16
8122 18:09:27.791605 best dqsien dly found for B1: ( 1, 9, 18)
8123 18:09:27.795067 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8124 18:09:27.798288 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8125 18:09:27.798367
8126 18:09:27.801232 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8127 18:09:27.804612 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8128 18:09:27.808049 [Gating] SW calibration Done
8129 18:09:27.808128 ==
8130 18:09:27.811408 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 18:09:27.814731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 18:09:27.814810 ==
8133 18:09:27.817613 RX Vref Scan: 0
8134 18:09:27.817692
8135 18:09:27.821235 RX Vref 0 -> 0, step: 1
8136 18:09:27.821321
8137 18:09:27.821385 RX Delay 0 -> 252, step: 8
8138 18:09:27.827742 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8139 18:09:27.830979 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8140 18:09:27.834067 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8141 18:09:27.837628 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8142 18:09:27.840707 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8143 18:09:27.847581 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8144 18:09:27.850465 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8145 18:09:27.853905 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8146 18:09:27.857190 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8147 18:09:27.864262 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8148 18:09:27.867528 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8149 18:09:27.870549 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8150 18:09:27.873791 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8151 18:09:27.876766 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8152 18:09:27.883666 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8153 18:09:27.886764 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8154 18:09:27.886843 ==
8155 18:09:27.890087 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 18:09:27.893646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 18:09:27.893726 ==
8158 18:09:27.896857 DQS Delay:
8159 18:09:27.896936 DQS0 = 0, DQS1 = 0
8160 18:09:27.896999 DQM Delay:
8161 18:09:27.900466 DQM0 = 133, DQM1 = 127
8162 18:09:27.900545 DQ Delay:
8163 18:09:27.903546 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8164 18:09:27.906813 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8165 18:09:27.913153 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8166 18:09:27.916427 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8167 18:09:27.916507
8168 18:09:27.916570
8169 18:09:27.916627 ==
8170 18:09:27.919695 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 18:09:27.923031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 18:09:27.923111 ==
8173 18:09:27.923174
8174 18:09:27.923233
8175 18:09:27.926909 TX Vref Scan disable
8176 18:09:27.929526 == TX Byte 0 ==
8177 18:09:27.933122 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8178 18:09:27.936051 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8179 18:09:27.939328 == TX Byte 1 ==
8180 18:09:27.942639 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8181 18:09:27.946127 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8182 18:09:27.946244 ==
8183 18:09:27.949565 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 18:09:27.956265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 18:09:27.956346 ==
8186 18:09:27.967903
8187 18:09:27.971399 TX Vref early break, caculate TX vref
8188 18:09:27.974567 TX Vref=16, minBit 0, minWin=22, winSum=378
8189 18:09:27.977883 TX Vref=18, minBit 1, minWin=23, winSum=387
8190 18:09:27.980893 TX Vref=20, minBit 0, minWin=24, winSum=397
8191 18:09:27.984381 TX Vref=22, minBit 1, minWin=23, winSum=404
8192 18:09:27.987849 TX Vref=24, minBit 1, minWin=24, winSum=413
8193 18:09:27.994319 TX Vref=26, minBit 0, minWin=24, winSum=412
8194 18:09:27.997630 TX Vref=28, minBit 1, minWin=24, winSum=414
8195 18:09:28.000795 TX Vref=30, minBit 1, minWin=24, winSum=405
8196 18:09:28.003944 TX Vref=32, minBit 0, minWin=24, winSum=399
8197 18:09:28.007664 TX Vref=34, minBit 5, minWin=23, winSum=390
8198 18:09:28.014014 [TxChooseVref] Worse bit 1, Min win 24, Win sum 414, Final Vref 28
8199 18:09:28.014094
8200 18:09:28.017345 Final TX Range 0 Vref 28
8201 18:09:28.017427
8202 18:09:28.017489 ==
8203 18:09:28.020799 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 18:09:28.023515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 18:09:28.023596 ==
8206 18:09:28.023659
8207 18:09:28.023717
8208 18:09:28.027394 TX Vref Scan disable
8209 18:09:28.033842 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8210 18:09:28.033952 == TX Byte 0 ==
8211 18:09:28.037411 u2DelayCellOfst[0]=14 cells (4 PI)
8212 18:09:28.040506 u2DelayCellOfst[1]=18 cells (5 PI)
8213 18:09:28.043480 u2DelayCellOfst[2]=14 cells (4 PI)
8214 18:09:28.047091 u2DelayCellOfst[3]=18 cells (5 PI)
8215 18:09:28.050564 u2DelayCellOfst[4]=11 cells (3 PI)
8216 18:09:28.054469 u2DelayCellOfst[5]=0 cells (0 PI)
8217 18:09:28.057534 u2DelayCellOfst[6]=22 cells (6 PI)
8218 18:09:28.060057 u2DelayCellOfst[7]=22 cells (6 PI)
8219 18:09:28.063651 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8220 18:09:28.067182 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8221 18:09:28.070624 == TX Byte 1 ==
8222 18:09:28.073746 u2DelayCellOfst[8]=0 cells (0 PI)
8223 18:09:28.076934 u2DelayCellOfst[9]=3 cells (1 PI)
8224 18:09:28.080182 u2DelayCellOfst[10]=11 cells (3 PI)
8225 18:09:28.080261 u2DelayCellOfst[11]=3 cells (1 PI)
8226 18:09:28.083079 u2DelayCellOfst[12]=14 cells (4 PI)
8227 18:09:28.086744 u2DelayCellOfst[13]=14 cells (4 PI)
8228 18:09:28.089650 u2DelayCellOfst[14]=18 cells (5 PI)
8229 18:09:28.093091 u2DelayCellOfst[15]=14 cells (4 PI)
8230 18:09:28.099888 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8231 18:09:28.102829 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8232 18:09:28.102938 DramC Write-DBI on
8233 18:09:28.106567 ==
8234 18:09:28.109597 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 18:09:28.113064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 18:09:28.113144 ==
8237 18:09:28.113207
8238 18:09:28.113264
8239 18:09:28.116174 TX Vref Scan disable
8240 18:09:28.116253 == TX Byte 0 ==
8241 18:09:28.122813 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8242 18:09:28.122892 == TX Byte 1 ==
8243 18:09:28.126146 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8244 18:09:28.129218 DramC Write-DBI off
8245 18:09:28.129297
8246 18:09:28.129360 [DATLAT]
8247 18:09:28.132612 Freq=1600, CH0 RK1
8248 18:09:28.132730
8249 18:09:28.132793 DATLAT Default: 0xf
8250 18:09:28.136169 0, 0xFFFF, sum = 0
8251 18:09:28.136250 1, 0xFFFF, sum = 0
8252 18:09:28.139553 2, 0xFFFF, sum = 0
8253 18:09:28.139641 3, 0xFFFF, sum = 0
8254 18:09:28.143074 4, 0xFFFF, sum = 0
8255 18:09:28.143155 5, 0xFFFF, sum = 0
8256 18:09:28.145901 6, 0xFFFF, sum = 0
8257 18:09:28.149431 7, 0xFFFF, sum = 0
8258 18:09:28.149511 8, 0xFFFF, sum = 0
8259 18:09:28.152748 9, 0xFFFF, sum = 0
8260 18:09:28.152828 10, 0xFFFF, sum = 0
8261 18:09:28.155684 11, 0xFFFF, sum = 0
8262 18:09:28.155764 12, 0xFFFF, sum = 0
8263 18:09:28.159797 13, 0xFFFF, sum = 0
8264 18:09:28.159878 14, 0x0, sum = 1
8265 18:09:28.162411 15, 0x0, sum = 2
8266 18:09:28.162516 16, 0x0, sum = 3
8267 18:09:28.165633 17, 0x0, sum = 4
8268 18:09:28.165714 best_step = 15
8269 18:09:28.165776
8270 18:09:28.165835 ==
8271 18:09:28.169068 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 18:09:28.172641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 18:09:28.176033 ==
8274 18:09:28.176112 RX Vref Scan: 0
8275 18:09:28.176176
8276 18:09:28.178997 RX Vref 0 -> 0, step: 1
8277 18:09:28.179076
8278 18:09:28.182486 RX Delay 11 -> 252, step: 4
8279 18:09:28.185610 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8280 18:09:28.189189 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8281 18:09:28.192180 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8282 18:09:28.199044 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8283 18:09:28.202102 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8284 18:09:28.205225 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8285 18:09:28.208521 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8286 18:09:28.212028 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8287 18:09:28.218478 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8288 18:09:28.221575 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8289 18:09:28.224879 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8290 18:09:28.228371 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8291 18:09:28.235094 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8292 18:09:28.237849 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8293 18:09:28.241714 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8294 18:09:28.244636 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8295 18:09:28.244718 ==
8296 18:09:28.247903 Dram Type= 6, Freq= 0, CH_0, rank 1
8297 18:09:28.254619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 18:09:28.254699 ==
8299 18:09:28.254762 DQS Delay:
8300 18:09:28.254821 DQS0 = 0, DQS1 = 0
8301 18:09:28.257892 DQM Delay:
8302 18:09:28.257971 DQM0 = 130, DQM1 = 125
8303 18:09:28.261480 DQ Delay:
8304 18:09:28.264725 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8305 18:09:28.268063 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8306 18:09:28.270981 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8307 18:09:28.274615 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8308 18:09:28.274695
8309 18:09:28.274757
8310 18:09:28.274815
8311 18:09:28.277997 [DramC_TX_OE_Calibration] TA2
8312 18:09:28.280912 Original DQ_B0 (3 6) =30, OEN = 27
8313 18:09:28.284591 Original DQ_B1 (3 6) =30, OEN = 27
8314 18:09:28.287298 24, 0x0, End_B0=24 End_B1=24
8315 18:09:28.287379 25, 0x0, End_B0=25 End_B1=25
8316 18:09:28.290757 26, 0x0, End_B0=26 End_B1=26
8317 18:09:28.294112 27, 0x0, End_B0=27 End_B1=27
8318 18:09:28.297463 28, 0x0, End_B0=28 End_B1=28
8319 18:09:28.301322 29, 0x0, End_B0=29 End_B1=29
8320 18:09:28.301402 30, 0x0, End_B0=30 End_B1=30
8321 18:09:28.304429 31, 0x5151, End_B0=30 End_B1=30
8322 18:09:28.307255 Byte0 end_step=30 best_step=27
8323 18:09:28.310842 Byte1 end_step=30 best_step=27
8324 18:09:28.314294 Byte0 TX OE(2T, 0.5T) = (3, 3)
8325 18:09:28.317121 Byte1 TX OE(2T, 0.5T) = (3, 3)
8326 18:09:28.317200
8327 18:09:28.317263
8328 18:09:28.323595 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8329 18:09:28.327224 CH0 RK1: MR19=303, MR18=1E02
8330 18:09:28.333726 CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15
8331 18:09:28.337236 [RxdqsGatingPostProcess] freq 1600
8332 18:09:28.340173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8333 18:09:28.343812 best DQS0 dly(2T, 0.5T) = (1, 1)
8334 18:09:28.347127 best DQS1 dly(2T, 0.5T) = (1, 1)
8335 18:09:28.349882 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8336 18:09:28.353661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8337 18:09:28.357014 best DQS0 dly(2T, 0.5T) = (1, 1)
8338 18:09:28.359919 best DQS1 dly(2T, 0.5T) = (1, 1)
8339 18:09:28.363430 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8340 18:09:28.366538 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8341 18:09:28.370382 Pre-setting of DQS Precalculation
8342 18:09:28.373099 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8343 18:09:28.373178 ==
8344 18:09:28.376593 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 18:09:28.383330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 18:09:28.383409 ==
8347 18:09:28.386307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 18:09:28.393180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 18:09:28.395986 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 18:09:28.402811 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 18:09:28.410778 [CA 0] Center 42 (13~71) winsize 59
8352 18:09:28.413727 [CA 1] Center 43 (14~72) winsize 59
8353 18:09:28.417219 [CA 2] Center 37 (9~66) winsize 58
8354 18:09:28.420751 [CA 3] Center 37 (8~67) winsize 60
8355 18:09:28.423630 [CA 4] Center 38 (8~68) winsize 61
8356 18:09:28.426991 [CA 5] Center 37 (8~67) winsize 60
8357 18:09:28.427069
8358 18:09:28.430186 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8359 18:09:28.430280
8360 18:09:28.437133 [CATrainingPosCal] consider 1 rank data
8361 18:09:28.437211 u2DelayCellTimex100 = 262/100 ps
8362 18:09:28.443349 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8363 18:09:28.446530 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8364 18:09:28.449904 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8365 18:09:28.453238 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8366 18:09:28.456865 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8367 18:09:28.459933 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8368 18:09:28.460013
8369 18:09:28.463946 CA PerBit enable=1, Macro0, CA PI delay=37
8370 18:09:28.464025
8371 18:09:28.466949 [CBTSetCACLKResult] CA Dly = 37
8372 18:09:28.470212 CS Dly: 9 (0~40)
8373 18:09:28.473811 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 18:09:28.476732 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 18:09:28.476815 ==
8376 18:09:28.479780 Dram Type= 6, Freq= 0, CH_1, rank 1
8377 18:09:28.486599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 18:09:28.486678 ==
8379 18:09:28.489632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8380 18:09:28.496493 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8381 18:09:28.500122 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8382 18:09:28.505992 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8383 18:09:28.513648 [CA 0] Center 42 (12~72) winsize 61
8384 18:09:28.516862 [CA 1] Center 42 (13~72) winsize 60
8385 18:09:28.520373 [CA 2] Center 37 (8~67) winsize 60
8386 18:09:28.523903 [CA 3] Center 37 (8~66) winsize 59
8387 18:09:28.526746 [CA 4] Center 37 (8~67) winsize 60
8388 18:09:28.529899 [CA 5] Center 37 (8~66) winsize 59
8389 18:09:28.530009
8390 18:09:28.533362 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8391 18:09:28.533443
8392 18:09:28.539791 [CATrainingPosCal] consider 2 rank data
8393 18:09:28.539870 u2DelayCellTimex100 = 262/100 ps
8394 18:09:28.546659 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8395 18:09:28.549875 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8396 18:09:28.553037 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8397 18:09:28.556411 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8398 18:09:28.559589 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8399 18:09:28.562905 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8400 18:09:28.562985
8401 18:09:28.566443 CA PerBit enable=1, Macro0, CA PI delay=37
8402 18:09:28.566522
8403 18:09:28.569682 [CBTSetCACLKResult] CA Dly = 37
8404 18:09:28.572981 CS Dly: 11 (0~44)
8405 18:09:28.576329 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8406 18:09:28.579696 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8407 18:09:28.579778
8408 18:09:28.582810 ----->DramcWriteLeveling(PI) begin...
8409 18:09:28.582938 ==
8410 18:09:28.586512 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 18:09:28.592787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 18:09:28.592936 ==
8413 18:09:28.596676 Write leveling (Byte 0): 23 => 23
8414 18:09:28.599703 Write leveling (Byte 1): 25 => 25
8415 18:09:28.599823 DramcWriteLeveling(PI) end<-----
8416 18:09:28.603036
8417 18:09:28.603217 ==
8418 18:09:28.606187 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 18:09:28.609148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 18:09:28.609239 ==
8421 18:09:28.612690 [Gating] SW mode calibration
8422 18:09:28.619244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8423 18:09:28.622420 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8424 18:09:28.629804 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 18:09:28.632779 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 18:09:28.635768 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8427 18:09:28.642758 1 4 12 | B1->B0 | 2a2a 3333 | 1 0 | (1 1) (0 0)
8428 18:09:28.645504 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 18:09:28.648983 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 18:09:28.655583 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 18:09:28.658784 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 18:09:28.665274 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 18:09:28.668708 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 18:09:28.672478 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8435 18:09:28.678309 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8436 18:09:28.681959 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 18:09:28.685083 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 18:09:28.688407 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 18:09:28.694991 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 18:09:28.698440 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 18:09:28.701657 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 18:09:28.708176 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 18:09:28.712036 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8444 18:09:28.715168 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 18:09:28.721777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 18:09:28.724570 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 18:09:28.727711 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 18:09:28.734185 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 18:09:28.737686 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 18:09:28.744253 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8451 18:09:28.747718 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8452 18:09:28.751519 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8453 18:09:28.754250 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 18:09:28.761249 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 18:09:28.764329 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 18:09:28.767431 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 18:09:28.774051 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 18:09:28.777506 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 18:09:28.781272 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 18:09:28.787615 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 18:09:28.791271 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 18:09:28.793804 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 18:09:28.800570 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 18:09:28.803669 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 18:09:28.807354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 18:09:28.813840 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8467 18:09:28.817223 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8468 18:09:28.820639 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 18:09:28.823621 Total UI for P1: 0, mck2ui 16
8470 18:09:28.826820 best dqsien dly found for B0: ( 1, 9, 10)
8471 18:09:28.830124 Total UI for P1: 0, mck2ui 16
8472 18:09:28.833817 best dqsien dly found for B1: ( 1, 9, 12)
8473 18:09:28.836788 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8474 18:09:28.840244 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8475 18:09:28.843685
8476 18:09:28.847254 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8477 18:09:28.850037 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8478 18:09:28.853234 [Gating] SW calibration Done
8479 18:09:28.853333 ==
8480 18:09:28.856595 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 18:09:28.860082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 18:09:28.860185 ==
8483 18:09:28.863172 RX Vref Scan: 0
8484 18:09:28.863332
8485 18:09:28.863437 RX Vref 0 -> 0, step: 1
8486 18:09:28.863526
8487 18:09:28.866632 RX Delay 0 -> 252, step: 8
8488 18:09:28.869881 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8489 18:09:28.876511 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8490 18:09:28.879671 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8491 18:09:28.883003 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8492 18:09:28.886080 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8493 18:09:28.889258 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8494 18:09:28.895884 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8495 18:09:28.899355 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8496 18:09:28.902839 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8497 18:09:28.905814 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8498 18:09:28.909307 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8499 18:09:28.915815 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8500 18:09:28.918911 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8501 18:09:28.922515 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8502 18:09:28.925563 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8503 18:09:28.932442 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8504 18:09:28.932553 ==
8505 18:09:28.935986 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 18:09:28.938892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 18:09:28.938993 ==
8508 18:09:28.939082 DQS Delay:
8509 18:09:28.942125 DQS0 = 0, DQS1 = 0
8510 18:09:28.942262 DQM Delay:
8511 18:09:28.945729 DQM0 = 137, DQM1 = 129
8512 18:09:28.945826 DQ Delay:
8513 18:09:28.949455 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8514 18:09:28.952221 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8515 18:09:28.955387 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8516 18:09:28.958530 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8517 18:09:28.958628
8518 18:09:28.958715
8519 18:09:28.962107 ==
8520 18:09:28.965502 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 18:09:28.968476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 18:09:28.968575 ==
8523 18:09:28.968664
8524 18:09:28.968748
8525 18:09:28.971733 TX Vref Scan disable
8526 18:09:28.971829 == TX Byte 0 ==
8527 18:09:28.975402 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8528 18:09:28.981490 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8529 18:09:28.981592 == TX Byte 1 ==
8530 18:09:28.988673 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8531 18:09:28.991881 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8532 18:09:28.991953 ==
8533 18:09:28.995159 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 18:09:28.998125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 18:09:28.998246 ==
8536 18:09:29.011584
8537 18:09:29.014481 TX Vref early break, caculate TX vref
8538 18:09:29.017851 TX Vref=16, minBit 0, minWin=22, winSum=375
8539 18:09:29.021274 TX Vref=18, minBit 0, minWin=22, winSum=385
8540 18:09:29.024849 TX Vref=20, minBit 0, minWin=23, winSum=392
8541 18:09:29.027926 TX Vref=22, minBit 0, minWin=24, winSum=404
8542 18:09:29.031345 TX Vref=24, minBit 0, minWin=24, winSum=409
8543 18:09:29.037804 TX Vref=26, minBit 0, minWin=24, winSum=415
8544 18:09:29.040901 TX Vref=28, minBit 0, minWin=24, winSum=419
8545 18:09:29.044608 TX Vref=30, minBit 0, minWin=24, winSum=413
8546 18:09:29.047970 TX Vref=32, minBit 0, minWin=24, winSum=406
8547 18:09:29.050851 TX Vref=34, minBit 0, minWin=23, winSum=395
8548 18:09:29.057817 [TxChooseVref] Worse bit 0, Min win 24, Win sum 419, Final Vref 28
8549 18:09:29.057917
8550 18:09:29.060819 Final TX Range 0 Vref 28
8551 18:09:29.060914
8552 18:09:29.061012 ==
8553 18:09:29.064196 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 18:09:29.067668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 18:09:29.067737 ==
8556 18:09:29.067799
8557 18:09:29.067856
8558 18:09:29.070975 TX Vref Scan disable
8559 18:09:29.077610 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8560 18:09:29.077709 == TX Byte 0 ==
8561 18:09:29.080530 u2DelayCellOfst[0]=14 cells (4 PI)
8562 18:09:29.084026 u2DelayCellOfst[1]=11 cells (3 PI)
8563 18:09:29.087665 u2DelayCellOfst[2]=0 cells (0 PI)
8564 18:09:29.091000 u2DelayCellOfst[3]=3 cells (1 PI)
8565 18:09:29.094107 u2DelayCellOfst[4]=7 cells (2 PI)
8566 18:09:29.097312 u2DelayCellOfst[5]=22 cells (6 PI)
8567 18:09:29.100768 u2DelayCellOfst[6]=18 cells (5 PI)
8568 18:09:29.104401 u2DelayCellOfst[7]=3 cells (1 PI)
8569 18:09:29.107700 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8570 18:09:29.110705 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8571 18:09:29.114118 == TX Byte 1 ==
8572 18:09:29.116896 u2DelayCellOfst[8]=0 cells (0 PI)
8573 18:09:29.116976 u2DelayCellOfst[9]=3 cells (1 PI)
8574 18:09:29.120206 u2DelayCellOfst[10]=11 cells (3 PI)
8575 18:09:29.124108 u2DelayCellOfst[11]=7 cells (2 PI)
8576 18:09:29.127392 u2DelayCellOfst[12]=18 cells (5 PI)
8577 18:09:29.130106 u2DelayCellOfst[13]=18 cells (5 PI)
8578 18:09:29.133789 u2DelayCellOfst[14]=18 cells (5 PI)
8579 18:09:29.136649 u2DelayCellOfst[15]=18 cells (5 PI)
8580 18:09:29.143374 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8581 18:09:29.146658 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8582 18:09:29.146737 DramC Write-DBI on
8583 18:09:29.146833 ==
8584 18:09:29.150071 Dram Type= 6, Freq= 0, CH_1, rank 0
8585 18:09:29.156590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8586 18:09:29.156697 ==
8587 18:09:29.156791
8588 18:09:29.156878
8589 18:09:29.156962 TX Vref Scan disable
8590 18:09:29.160401 == TX Byte 0 ==
8591 18:09:29.163846 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8592 18:09:29.167575 == TX Byte 1 ==
8593 18:09:29.170336 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8594 18:09:29.173902 DramC Write-DBI off
8595 18:09:29.173997
8596 18:09:29.174088 [DATLAT]
8597 18:09:29.174200 Freq=1600, CH1 RK0
8598 18:09:29.174274
8599 18:09:29.177469 DATLAT Default: 0xf
8600 18:09:29.180453 0, 0xFFFF, sum = 0
8601 18:09:29.180551 1, 0xFFFF, sum = 0
8602 18:09:29.183783 2, 0xFFFF, sum = 0
8603 18:09:29.183882 3, 0xFFFF, sum = 0
8604 18:09:29.186635 4, 0xFFFF, sum = 0
8605 18:09:29.186732 5, 0xFFFF, sum = 0
8606 18:09:29.190295 6, 0xFFFF, sum = 0
8607 18:09:29.190366 7, 0xFFFF, sum = 0
8608 18:09:29.193641 8, 0xFFFF, sum = 0
8609 18:09:29.193740 9, 0xFFFF, sum = 0
8610 18:09:29.196604 10, 0xFFFF, sum = 0
8611 18:09:29.196700 11, 0xFFFF, sum = 0
8612 18:09:29.200230 12, 0xFFFF, sum = 0
8613 18:09:29.200322 13, 0xFFFF, sum = 0
8614 18:09:29.203334 14, 0x0, sum = 1
8615 18:09:29.203401 15, 0x0, sum = 2
8616 18:09:29.206502 16, 0x0, sum = 3
8617 18:09:29.206571 17, 0x0, sum = 4
8618 18:09:29.209964 best_step = 15
8619 18:09:29.210056
8620 18:09:29.210153 ==
8621 18:09:29.213533 Dram Type= 6, Freq= 0, CH_1, rank 0
8622 18:09:29.216584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8623 18:09:29.216679 ==
8624 18:09:29.219734 RX Vref Scan: 1
8625 18:09:29.219831
8626 18:09:29.219927 Set Vref Range= 24 -> 127
8627 18:09:29.223368
8628 18:09:29.223464 RX Vref 24 -> 127, step: 1
8629 18:09:29.223549
8630 18:09:29.226368 RX Delay 11 -> 252, step: 4
8631 18:09:29.226436
8632 18:09:29.229821 Set Vref, RX VrefLevel [Byte0]: 24
8633 18:09:29.233105 [Byte1]: 24
8634 18:09:29.233205
8635 18:09:29.236343 Set Vref, RX VrefLevel [Byte0]: 25
8636 18:09:29.239655 [Byte1]: 25
8637 18:09:29.243642
8638 18:09:29.243741 Set Vref, RX VrefLevel [Byte0]: 26
8639 18:09:29.246510 [Byte1]: 26
8640 18:09:29.251023
8641 18:09:29.251118 Set Vref, RX VrefLevel [Byte0]: 27
8642 18:09:29.254328 [Byte1]: 27
8643 18:09:29.258725
8644 18:09:29.258824 Set Vref, RX VrefLevel [Byte0]: 28
8645 18:09:29.261658 [Byte1]: 28
8646 18:09:29.266411
8647 18:09:29.266508 Set Vref, RX VrefLevel [Byte0]: 29
8648 18:09:29.269524 [Byte1]: 29
8649 18:09:29.274005
8650 18:09:29.274108 Set Vref, RX VrefLevel [Byte0]: 30
8651 18:09:29.277211 [Byte1]: 30
8652 18:09:29.281827
8653 18:09:29.281927 Set Vref, RX VrefLevel [Byte0]: 31
8654 18:09:29.285047 [Byte1]: 31
8655 18:09:29.289189
8656 18:09:29.289287 Set Vref, RX VrefLevel [Byte0]: 32
8657 18:09:29.292135 [Byte1]: 32
8658 18:09:29.296914
8659 18:09:29.297018 Set Vref, RX VrefLevel [Byte0]: 33
8660 18:09:29.299956 [Byte1]: 33
8661 18:09:29.304245
8662 18:09:29.304345 Set Vref, RX VrefLevel [Byte0]: 34
8663 18:09:29.307561 [Byte1]: 34
8664 18:09:29.312066
8665 18:09:29.312164 Set Vref, RX VrefLevel [Byte0]: 35
8666 18:09:29.315341 [Byte1]: 35
8667 18:09:29.319538
8668 18:09:29.319637 Set Vref, RX VrefLevel [Byte0]: 36
8669 18:09:29.322862 [Byte1]: 36
8670 18:09:29.326977
8671 18:09:29.327076 Set Vref, RX VrefLevel [Byte0]: 37
8672 18:09:29.331099 [Byte1]: 37
8673 18:09:29.335002
8674 18:09:29.335103 Set Vref, RX VrefLevel [Byte0]: 38
8675 18:09:29.338076 [Byte1]: 38
8676 18:09:29.342405
8677 18:09:29.342476 Set Vref, RX VrefLevel [Byte0]: 39
8678 18:09:29.345617 [Byte1]: 39
8679 18:09:29.350230
8680 18:09:29.350326 Set Vref, RX VrefLevel [Byte0]: 40
8681 18:09:29.354005 [Byte1]: 40
8682 18:09:29.357570
8683 18:09:29.357640 Set Vref, RX VrefLevel [Byte0]: 41
8684 18:09:29.360728 [Byte1]: 41
8685 18:09:29.365370
8686 18:09:29.365467 Set Vref, RX VrefLevel [Byte0]: 42
8687 18:09:29.368816 [Byte1]: 42
8688 18:09:29.372957
8689 18:09:29.373060 Set Vref, RX VrefLevel [Byte0]: 43
8690 18:09:29.375922 [Byte1]: 43
8691 18:09:29.380453
8692 18:09:29.380551 Set Vref, RX VrefLevel [Byte0]: 44
8693 18:09:29.383876 [Byte1]: 44
8694 18:09:29.388325
8695 18:09:29.388422 Set Vref, RX VrefLevel [Byte0]: 45
8696 18:09:29.391780 [Byte1]: 45
8697 18:09:29.395767
8698 18:09:29.395841 Set Vref, RX VrefLevel [Byte0]: 46
8699 18:09:29.399281 [Byte1]: 46
8700 18:09:29.403323
8701 18:09:29.403424 Set Vref, RX VrefLevel [Byte0]: 47
8702 18:09:29.407020 [Byte1]: 47
8703 18:09:29.411053
8704 18:09:29.411149 Set Vref, RX VrefLevel [Byte0]: 48
8705 18:09:29.414284 [Byte1]: 48
8706 18:09:29.418717
8707 18:09:29.418788 Set Vref, RX VrefLevel [Byte0]: 49
8708 18:09:29.421591 [Byte1]: 49
8709 18:09:29.426192
8710 18:09:29.426287 Set Vref, RX VrefLevel [Byte0]: 50
8711 18:09:29.429127 [Byte1]: 50
8712 18:09:29.433852
8713 18:09:29.433953 Set Vref, RX VrefLevel [Byte0]: 51
8714 18:09:29.437012 [Byte1]: 51
8715 18:09:29.441331
8716 18:09:29.441403 Set Vref, RX VrefLevel [Byte0]: 52
8717 18:09:29.444484 [Byte1]: 52
8718 18:09:29.449183
8719 18:09:29.449265 Set Vref, RX VrefLevel [Byte0]: 53
8720 18:09:29.451966 [Byte1]: 53
8721 18:09:29.456580
8722 18:09:29.456678 Set Vref, RX VrefLevel [Byte0]: 54
8723 18:09:29.459584 [Byte1]: 54
8724 18:09:29.464202
8725 18:09:29.464299 Set Vref, RX VrefLevel [Byte0]: 55
8726 18:09:29.467459 [Byte1]: 55
8727 18:09:29.471602
8728 18:09:29.471673 Set Vref, RX VrefLevel [Byte0]: 56
8729 18:09:29.475212 [Byte1]: 56
8730 18:09:29.479534
8731 18:09:29.479634 Set Vref, RX VrefLevel [Byte0]: 57
8732 18:09:29.482572 [Byte1]: 57
8733 18:09:29.486862
8734 18:09:29.486960 Set Vref, RX VrefLevel [Byte0]: 58
8735 18:09:29.490419 [Byte1]: 58
8736 18:09:29.494685
8737 18:09:29.494764 Set Vref, RX VrefLevel [Byte0]: 59
8738 18:09:29.497963 [Byte1]: 59
8739 18:09:29.502538
8740 18:09:29.502616 Set Vref, RX VrefLevel [Byte0]: 60
8741 18:09:29.505590 [Byte1]: 60
8742 18:09:29.509662
8743 18:09:29.509741 Set Vref, RX VrefLevel [Byte0]: 61
8744 18:09:29.513197 [Byte1]: 61
8745 18:09:29.517557
8746 18:09:29.517636 Set Vref, RX VrefLevel [Byte0]: 62
8747 18:09:29.520819 [Byte1]: 62
8748 18:09:29.524808
8749 18:09:29.524910 Set Vref, RX VrefLevel [Byte0]: 63
8750 18:09:29.528461 [Byte1]: 63
8751 18:09:29.533339
8752 18:09:29.533419 Set Vref, RX VrefLevel [Byte0]: 64
8753 18:09:29.535889 [Byte1]: 64
8754 18:09:29.540329
8755 18:09:29.540408 Set Vref, RX VrefLevel [Byte0]: 65
8756 18:09:29.543560 [Byte1]: 65
8757 18:09:29.548221
8758 18:09:29.548300 Set Vref, RX VrefLevel [Byte0]: 66
8759 18:09:29.551681 [Byte1]: 66
8760 18:09:29.555662
8761 18:09:29.555741 Set Vref, RX VrefLevel [Byte0]: 67
8762 18:09:29.559051 [Byte1]: 67
8763 18:09:29.563215
8764 18:09:29.563320 Set Vref, RX VrefLevel [Byte0]: 68
8765 18:09:29.566706 [Byte1]: 68
8766 18:09:29.570586
8767 18:09:29.570665 Set Vref, RX VrefLevel [Byte0]: 69
8768 18:09:29.573763 [Byte1]: 69
8769 18:09:29.578156
8770 18:09:29.578244 Set Vref, RX VrefLevel [Byte0]: 70
8771 18:09:29.582095 [Byte1]: 70
8772 18:09:29.586029
8773 18:09:29.586108 Set Vref, RX VrefLevel [Byte0]: 71
8774 18:09:29.589462 [Byte1]: 71
8775 18:09:29.593357
8776 18:09:29.593435 Set Vref, RX VrefLevel [Byte0]: 72
8777 18:09:29.596682 [Byte1]: 72
8778 18:09:29.601039
8779 18:09:29.601118 Set Vref, RX VrefLevel [Byte0]: 73
8780 18:09:29.604382 [Byte1]: 73
8781 18:09:29.608706
8782 18:09:29.608785 Set Vref, RX VrefLevel [Byte0]: 74
8783 18:09:29.612446 [Byte1]: 74
8784 18:09:29.616189
8785 18:09:29.616268 Set Vref, RX VrefLevel [Byte0]: 75
8786 18:09:29.619477 [Byte1]: 75
8787 18:09:29.623735
8788 18:09:29.623834 Final RX Vref Byte 0 = 53 to rank0
8789 18:09:29.627865 Final RX Vref Byte 1 = 59 to rank0
8790 18:09:29.630499 Final RX Vref Byte 0 = 53 to rank1
8791 18:09:29.634008 Final RX Vref Byte 1 = 59 to rank1==
8792 18:09:29.637247 Dram Type= 6, Freq= 0, CH_1, rank 0
8793 18:09:29.643905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 18:09:29.643985 ==
8795 18:09:29.644049 DQS Delay:
8796 18:09:29.647381 DQS0 = 0, DQS1 = 0
8797 18:09:29.647460 DQM Delay:
8798 18:09:29.647523 DQM0 = 133, DQM1 = 127
8799 18:09:29.650343 DQ Delay:
8800 18:09:29.653474 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8801 18:09:29.657066 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8802 18:09:29.660248 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8803 18:09:29.663551 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8804 18:09:29.663654
8805 18:09:29.663744
8806 18:09:29.663830
8807 18:09:29.666958 [DramC_TX_OE_Calibration] TA2
8808 18:09:29.670094 Original DQ_B0 (3 6) =30, OEN = 27
8809 18:09:29.673602 Original DQ_B1 (3 6) =30, OEN = 27
8810 18:09:29.676452 24, 0x0, End_B0=24 End_B1=24
8811 18:09:29.679978 25, 0x0, End_B0=25 End_B1=25
8812 18:09:29.680059 26, 0x0, End_B0=26 End_B1=26
8813 18:09:29.683397 27, 0x0, End_B0=27 End_B1=27
8814 18:09:29.686509 28, 0x0, End_B0=28 End_B1=28
8815 18:09:29.689946 29, 0x0, End_B0=29 End_B1=29
8816 18:09:29.690026 30, 0x0, End_B0=30 End_B1=30
8817 18:09:29.693596 31, 0x4141, End_B0=30 End_B1=30
8818 18:09:29.696544 Byte0 end_step=30 best_step=27
8819 18:09:29.700165 Byte1 end_step=30 best_step=27
8820 18:09:29.703173 Byte0 TX OE(2T, 0.5T) = (3, 3)
8821 18:09:29.706296 Byte1 TX OE(2T, 0.5T) = (3, 3)
8822 18:09:29.706374
8823 18:09:29.706436
8824 18:09:29.712790 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8825 18:09:29.716837 CH1 RK0: MR19=303, MR18=170C
8826 18:09:29.723053 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8827 18:09:29.723134
8828 18:09:29.725988 ----->DramcWriteLeveling(PI) begin...
8829 18:09:29.726068 ==
8830 18:09:29.729349 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 18:09:29.732816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 18:09:29.732896 ==
8833 18:09:29.736141 Write leveling (Byte 0): 24 => 24
8834 18:09:29.739634 Write leveling (Byte 1): 28 => 28
8835 18:09:29.742788 DramcWriteLeveling(PI) end<-----
8836 18:09:29.742868
8837 18:09:29.742930 ==
8838 18:09:29.746140 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 18:09:29.749485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 18:09:29.752341 ==
8841 18:09:29.752420 [Gating] SW mode calibration
8842 18:09:29.762681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8843 18:09:29.765839 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8844 18:09:29.768943 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 18:09:29.775914 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 18:09:29.779477 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 18:09:29.782503 1 4 12 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8848 18:09:29.789040 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8849 18:09:29.792688 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 18:09:29.795501 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 18:09:29.802274 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 18:09:29.805398 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 18:09:29.808890 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 18:09:29.815596 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8855 18:09:29.818608 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8856 18:09:29.822047 1 5 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
8857 18:09:29.829001 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 18:09:29.831891 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 18:09:29.835079 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 18:09:29.841834 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 18:09:29.844636 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 18:09:29.848227 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8863 18:09:29.854632 1 6 12 | B1->B0 | 4545 2929 | 0 0 | (0 0) (1 1)
8864 18:09:29.858051 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 18:09:29.861601 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 18:09:29.868149 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 18:09:29.871498 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 18:09:29.874526 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 18:09:29.881013 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 18:09:29.884417 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8871 18:09:29.887905 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8872 18:09:29.894544 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8873 18:09:29.897586 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 18:09:29.901163 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 18:09:29.907323 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 18:09:29.911101 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 18:09:29.914333 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 18:09:29.920635 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 18:09:29.924129 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 18:09:29.927604 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 18:09:29.933873 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 18:09:29.937434 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 18:09:29.940239 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 18:09:29.946941 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 18:09:29.950348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 18:09:29.953701 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8887 18:09:29.960586 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8888 18:09:29.964011 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 18:09:29.966852 Total UI for P1: 0, mck2ui 16
8890 18:09:29.970280 best dqsien dly found for B0: ( 1, 9, 10)
8891 18:09:29.973543 Total UI for P1: 0, mck2ui 16
8892 18:09:29.976863 best dqsien dly found for B1: ( 1, 9, 10)
8893 18:09:29.980220 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8894 18:09:29.983304 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8895 18:09:29.983380
8896 18:09:29.986643 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8897 18:09:29.993348 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8898 18:09:29.993429 [Gating] SW calibration Done
8899 18:09:29.993493 ==
8900 18:09:29.996445 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 18:09:30.002861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 18:09:30.002940 ==
8903 18:09:30.003003 RX Vref Scan: 0
8904 18:09:30.003062
8905 18:09:30.006324 RX Vref 0 -> 0, step: 1
8906 18:09:30.006403
8907 18:09:30.009837 RX Delay 0 -> 252, step: 8
8908 18:09:30.013125 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8909 18:09:30.016317 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8910 18:09:30.019708 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8911 18:09:30.025969 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8912 18:09:30.029321 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8913 18:09:30.032732 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8914 18:09:30.035878 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8915 18:09:30.039396 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8916 18:09:30.045896 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8917 18:09:30.049413 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8918 18:09:30.052650 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8919 18:09:30.056129 iDelay=208, Bit 11, Center 115 (56 ~ 175) 120
8920 18:09:30.059685 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8921 18:09:30.065352 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8922 18:09:30.068682 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8923 18:09:30.072196 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8924 18:09:30.072288 ==
8925 18:09:30.075460 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 18:09:30.082262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 18:09:30.082344 ==
8928 18:09:30.082408 DQS Delay:
8929 18:09:30.082466 DQS0 = 0, DQS1 = 0
8930 18:09:30.085177 DQM Delay:
8931 18:09:30.085256 DQM0 = 136, DQM1 = 128
8932 18:09:30.088597 DQ Delay:
8933 18:09:30.091788 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8934 18:09:30.095338 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8935 18:09:30.098772 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =115
8936 18:09:30.101516 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8937 18:09:30.101596
8938 18:09:30.101659
8939 18:09:30.101747 ==
8940 18:09:30.104850 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 18:09:30.108469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 18:09:30.111986 ==
8943 18:09:30.112066
8944 18:09:30.112129
8945 18:09:30.112186 TX Vref Scan disable
8946 18:09:30.114877 == TX Byte 0 ==
8947 18:09:30.118571 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8948 18:09:30.121545 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8949 18:09:30.125055 == TX Byte 1 ==
8950 18:09:30.128205 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8951 18:09:30.134630 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8952 18:09:30.134709 ==
8953 18:09:30.138334 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 18:09:30.141451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 18:09:30.141536 ==
8956 18:09:30.153955
8957 18:09:30.156882 TX Vref early break, caculate TX vref
8958 18:09:30.160216 TX Vref=16, minBit 1, minWin=22, winSum=381
8959 18:09:30.163686 TX Vref=18, minBit 1, minWin=23, winSum=390
8960 18:09:30.166846 TX Vref=20, minBit 9, minWin=23, winSum=400
8961 18:09:30.170091 TX Vref=22, minBit 5, minWin=24, winSum=409
8962 18:09:30.174141 TX Vref=24, minBit 0, minWin=25, winSum=414
8963 18:09:30.180569 TX Vref=26, minBit 1, minWin=25, winSum=419
8964 18:09:30.183409 TX Vref=28, minBit 5, minWin=25, winSum=423
8965 18:09:30.186812 TX Vref=30, minBit 0, minWin=24, winSum=417
8966 18:09:30.190434 TX Vref=32, minBit 0, minWin=24, winSum=407
8967 18:09:30.193278 TX Vref=34, minBit 1, minWin=23, winSum=389
8968 18:09:30.199640 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 28
8969 18:09:30.199746
8970 18:09:30.203366 Final TX Range 0 Vref 28
8971 18:09:30.203448
8972 18:09:30.203519 ==
8973 18:09:30.206501 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 18:09:30.209730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 18:09:30.209829 ==
8976 18:09:30.209919
8977 18:09:30.210005
8978 18:09:30.213085 TX Vref Scan disable
8979 18:09:30.219534 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8980 18:09:30.219614 == TX Byte 0 ==
8981 18:09:30.222976 u2DelayCellOfst[0]=22 cells (6 PI)
8982 18:09:30.226768 u2DelayCellOfst[1]=14 cells (4 PI)
8983 18:09:30.229341 u2DelayCellOfst[2]=0 cells (0 PI)
8984 18:09:30.232757 u2DelayCellOfst[3]=7 cells (2 PI)
8985 18:09:30.235795 u2DelayCellOfst[4]=7 cells (2 PI)
8986 18:09:30.239299 u2DelayCellOfst[5]=22 cells (6 PI)
8987 18:09:30.242817 u2DelayCellOfst[6]=22 cells (6 PI)
8988 18:09:30.245867 u2DelayCellOfst[7]=7 cells (2 PI)
8989 18:09:30.249435 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8990 18:09:30.252618 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8991 18:09:30.256225 == TX Byte 1 ==
8992 18:09:30.259069 u2DelayCellOfst[8]=0 cells (0 PI)
8993 18:09:30.262490 u2DelayCellOfst[9]=7 cells (2 PI)
8994 18:09:30.265778 u2DelayCellOfst[10]=14 cells (4 PI)
8995 18:09:30.265857 u2DelayCellOfst[11]=7 cells (2 PI)
8996 18:09:30.269116 u2DelayCellOfst[12]=18 cells (5 PI)
8997 18:09:30.272329 u2DelayCellOfst[13]=18 cells (5 PI)
8998 18:09:30.275917 u2DelayCellOfst[14]=22 cells (6 PI)
8999 18:09:30.279273 u2DelayCellOfst[15]=18 cells (5 PI)
9000 18:09:30.285788 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9001 18:09:30.288780 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9002 18:09:30.288862 DramC Write-DBI on
9003 18:09:30.291987 ==
9004 18:09:30.292067 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 18:09:30.298657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 18:09:30.298738 ==
9007 18:09:30.298801
9008 18:09:30.298859
9009 18:09:30.302043 TX Vref Scan disable
9010 18:09:30.302125 == TX Byte 0 ==
9011 18:09:30.308503 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9012 18:09:30.308583 == TX Byte 1 ==
9013 18:09:30.311736 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9014 18:09:30.315300 DramC Write-DBI off
9015 18:09:30.315379
9016 18:09:30.315441 [DATLAT]
9017 18:09:30.318215 Freq=1600, CH1 RK1
9018 18:09:30.318294
9019 18:09:30.318356 DATLAT Default: 0xf
9020 18:09:30.321720 0, 0xFFFF, sum = 0
9021 18:09:30.321801 1, 0xFFFF, sum = 0
9022 18:09:30.325265 2, 0xFFFF, sum = 0
9023 18:09:30.325345 3, 0xFFFF, sum = 0
9024 18:09:30.328975 4, 0xFFFF, sum = 0
9025 18:09:30.329070 5, 0xFFFF, sum = 0
9026 18:09:30.331944 6, 0xFFFF, sum = 0
9027 18:09:30.332025 7, 0xFFFF, sum = 0
9028 18:09:30.335036 8, 0xFFFF, sum = 0
9029 18:09:30.338413 9, 0xFFFF, sum = 0
9030 18:09:30.338494 10, 0xFFFF, sum = 0
9031 18:09:30.341969 11, 0xFFFF, sum = 0
9032 18:09:30.342049 12, 0xFFFF, sum = 0
9033 18:09:30.344965 13, 0xFFFF, sum = 0
9034 18:09:30.345046 14, 0x0, sum = 1
9035 18:09:30.348324 15, 0x0, sum = 2
9036 18:09:30.348405 16, 0x0, sum = 3
9037 18:09:30.351509 17, 0x0, sum = 4
9038 18:09:30.351589 best_step = 15
9039 18:09:30.351652
9040 18:09:30.351719 ==
9041 18:09:30.354956 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 18:09:30.358287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 18:09:30.358367 ==
9044 18:09:30.361630 RX Vref Scan: 0
9045 18:09:30.361709
9046 18:09:30.364753 RX Vref 0 -> 0, step: 1
9047 18:09:30.364833
9048 18:09:30.364895 RX Delay 11 -> 252, step: 4
9049 18:09:30.372329 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9050 18:09:30.375356 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9051 18:09:30.378879 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9052 18:09:30.382089 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9053 18:09:30.388478 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9054 18:09:30.391963 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9055 18:09:30.395197 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9056 18:09:30.398329 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9057 18:09:30.401691 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9058 18:09:30.408234 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9059 18:09:30.411753 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9060 18:09:30.414719 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9061 18:09:30.418191 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9062 18:09:30.421119 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9063 18:09:30.427825 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9064 18:09:30.431291 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9065 18:09:30.431370 ==
9066 18:09:30.434316 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 18:09:30.437863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 18:09:30.437943 ==
9069 18:09:30.441084 DQS Delay:
9070 18:09:30.441164 DQS0 = 0, DQS1 = 0
9071 18:09:30.441227 DQM Delay:
9072 18:09:30.444400 DQM0 = 133, DQM1 = 126
9073 18:09:30.444479 DQ Delay:
9074 18:09:30.447779 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9075 18:09:30.450826 DQ4 =132, DQ5 =142, DQ6 =146, DQ7 =130
9076 18:09:30.458039 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9077 18:09:30.460969 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9078 18:09:30.461039
9079 18:09:30.461100
9080 18:09:30.461157
9081 18:09:30.464274 [DramC_TX_OE_Calibration] TA2
9082 18:09:30.467968 Original DQ_B0 (3 6) =30, OEN = 27
9083 18:09:30.470944 Original DQ_B1 (3 6) =30, OEN = 27
9084 18:09:30.471023 24, 0x0, End_B0=24 End_B1=24
9085 18:09:30.474378 25, 0x0, End_B0=25 End_B1=25
9086 18:09:30.477651 26, 0x0, End_B0=26 End_B1=26
9087 18:09:30.480873 27, 0x0, End_B0=27 End_B1=27
9088 18:09:30.480954 28, 0x0, End_B0=28 End_B1=28
9089 18:09:30.483960 29, 0x0, End_B0=29 End_B1=29
9090 18:09:30.487738 30, 0x0, End_B0=30 End_B1=30
9091 18:09:30.490709 31, 0x4545, End_B0=30 End_B1=30
9092 18:09:30.494131 Byte0 end_step=30 best_step=27
9093 18:09:30.497362 Byte1 end_step=30 best_step=27
9094 18:09:30.497441 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 18:09:30.501076 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 18:09:30.501155
9097 18:09:30.501218
9098 18:09:30.510735 [DQSOSCAuto] RK1, (LSB)MR18= 0xb09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 404 ps
9099 18:09:30.513678 CH1 RK1: MR19=303, MR18=B09
9100 18:09:30.517597 CH1_RK1: MR19=0x303, MR18=0xB09, DQSOSC=404, MR23=63, INC=22, DEC=15
9101 18:09:30.520326 [RxdqsGatingPostProcess] freq 1600
9102 18:09:30.527325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 18:09:30.530555 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 18:09:30.533865 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 18:09:30.536841 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 18:09:30.540225 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 18:09:30.543665 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 18:09:30.546566 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 18:09:30.550312 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 18:09:30.550411 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 18:09:30.553376 Pre-setting of DQS Precalculation
9112 18:09:30.559890 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 18:09:30.566867 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 18:09:30.573075 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 18:09:30.573174
9116 18:09:30.573264
9117 18:09:30.576472 [Calibration Summary] 3200 Mbps
9118 18:09:30.579823 CH 0, Rank 0
9119 18:09:30.579919 SW Impedance : PASS
9120 18:09:30.583250 DUTY Scan : NO K
9121 18:09:30.586079 ZQ Calibration : PASS
9122 18:09:30.586178 Jitter Meter : NO K
9123 18:09:30.589682 CBT Training : PASS
9124 18:09:30.592757 Write leveling : PASS
9125 18:09:30.592855 RX DQS gating : PASS
9126 18:09:30.596303 RX DQ/DQS(RDDQC) : PASS
9127 18:09:30.599453 TX DQ/DQS : PASS
9128 18:09:30.599554 RX DATLAT : PASS
9129 18:09:30.602345 RX DQ/DQS(Engine): PASS
9130 18:09:30.605881 TX OE : PASS
9131 18:09:30.605975 All Pass.
9132 18:09:30.606066
9133 18:09:30.606151 CH 0, Rank 1
9134 18:09:30.609067 SW Impedance : PASS
9135 18:09:30.612770 DUTY Scan : NO K
9136 18:09:30.612856 ZQ Calibration : PASS
9137 18:09:30.615507 Jitter Meter : NO K
9138 18:09:30.618769 CBT Training : PASS
9139 18:09:30.618867 Write leveling : PASS
9140 18:09:30.622357 RX DQS gating : PASS
9141 18:09:30.622454 RX DQ/DQS(RDDQC) : PASS
9142 18:09:30.625606 TX DQ/DQS : PASS
9143 18:09:30.629201 RX DATLAT : PASS
9144 18:09:30.629296 RX DQ/DQS(Engine): PASS
9145 18:09:30.632074 TX OE : PASS
9146 18:09:30.632170 All Pass.
9147 18:09:30.632256
9148 18:09:30.635394 CH 1, Rank 0
9149 18:09:30.635475 SW Impedance : PASS
9150 18:09:30.638776 DUTY Scan : NO K
9151 18:09:30.641805 ZQ Calibration : PASS
9152 18:09:30.641885 Jitter Meter : NO K
9153 18:09:30.645410 CBT Training : PASS
9154 18:09:30.648489 Write leveling : PASS
9155 18:09:30.648568 RX DQS gating : PASS
9156 18:09:30.651774 RX DQ/DQS(RDDQC) : PASS
9157 18:09:30.655312 TX DQ/DQS : PASS
9158 18:09:30.655392 RX DATLAT : PASS
9159 18:09:30.658834 RX DQ/DQS(Engine): PASS
9160 18:09:30.661706 TX OE : PASS
9161 18:09:30.661786 All Pass.
9162 18:09:30.661852
9163 18:09:30.661911 CH 1, Rank 1
9164 18:09:30.665169 SW Impedance : PASS
9165 18:09:30.668565 DUTY Scan : NO K
9166 18:09:30.668645 ZQ Calibration : PASS
9167 18:09:30.672121 Jitter Meter : NO K
9168 18:09:30.674826 CBT Training : PASS
9169 18:09:30.674909 Write leveling : PASS
9170 18:09:30.678364 RX DQS gating : PASS
9171 18:09:30.681741 RX DQ/DQS(RDDQC) : PASS
9172 18:09:30.681820 TX DQ/DQS : PASS
9173 18:09:30.684624 RX DATLAT : PASS
9174 18:09:30.688094 RX DQ/DQS(Engine): PASS
9175 18:09:30.688174 TX OE : PASS
9176 18:09:30.691474 All Pass.
9177 18:09:30.691554
9178 18:09:30.691617 DramC Write-DBI on
9179 18:09:30.694640 PER_BANK_REFRESH: Hybrid Mode
9180 18:09:30.694719 TX_TRACKING: ON
9181 18:09:30.704920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 18:09:30.714389 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 18:09:30.721112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 18:09:30.724838 [FAST_K] Save calibration result to emmc
9185 18:09:30.727475 sync common calibartion params.
9186 18:09:30.727555 sync cbt_mode0:1, 1:1
9187 18:09:30.730800 dram_init: ddr_geometry: 2
9188 18:09:30.734114 dram_init: ddr_geometry: 2
9189 18:09:30.734245 dram_init: ddr_geometry: 2
9190 18:09:30.737722 0:dram_rank_size:100000000
9191 18:09:30.740869 1:dram_rank_size:100000000
9192 18:09:30.747627 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 18:09:30.747708 DFS_SHUFFLE_HW_MODE: ON
9194 18:09:30.750695 dramc_set_vcore_voltage set vcore to 725000
9195 18:09:30.754455 Read voltage for 1600, 0
9196 18:09:30.754534 Vio18 = 0
9197 18:09:30.757082 Vcore = 725000
9198 18:09:30.757161 Vdram = 0
9199 18:09:30.757224 Vddq = 0
9200 18:09:30.760641 Vmddr = 0
9201 18:09:30.760721 switch to 3200 Mbps bootup
9202 18:09:30.763944 [DramcRunTimeConfig]
9203 18:09:30.764024 PHYPLL
9204 18:09:30.766926 DPM_CONTROL_AFTERK: ON
9205 18:09:30.767006 PER_BANK_REFRESH: ON
9206 18:09:30.770508 REFRESH_OVERHEAD_REDUCTION: ON
9207 18:09:30.773803 CMD_PICG_NEW_MODE: OFF
9208 18:09:30.773883 XRTWTW_NEW_MODE: ON
9209 18:09:30.777307 XRTRTR_NEW_MODE: ON
9210 18:09:30.777387 TX_TRACKING: ON
9211 18:09:30.780264 RDSEL_TRACKING: OFF
9212 18:09:30.783854 DQS Precalculation for DVFS: ON
9213 18:09:30.783934 RX_TRACKING: OFF
9214 18:09:30.787001 HW_GATING DBG: ON
9215 18:09:30.787081 ZQCS_ENABLE_LP4: ON
9216 18:09:30.790715 RX_PICG_NEW_MODE: ON
9217 18:09:30.790795 TX_PICG_NEW_MODE: ON
9218 18:09:30.793706 ENABLE_RX_DCM_DPHY: ON
9219 18:09:30.797192 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 18:09:30.800524 DUMMY_READ_FOR_TRACKING: OFF
9221 18:09:30.803458 !!! SPM_CONTROL_AFTERK: OFF
9222 18:09:30.803545 !!! SPM could not control APHY
9223 18:09:30.806839 IMPEDANCE_TRACKING: ON
9224 18:09:30.806918 TEMP_SENSOR: ON
9225 18:09:30.810214 HW_SAVE_FOR_SR: OFF
9226 18:09:30.813466 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 18:09:30.817010 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 18:09:30.819787 Read ODT Tracking: ON
9229 18:09:30.819867 Refresh Rate DeBounce: ON
9230 18:09:30.823436 DFS_NO_QUEUE_FLUSH: ON
9231 18:09:30.826602 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 18:09:30.829661 ENABLE_DFS_RUNTIME_MRW: OFF
9233 18:09:30.829740 DDR_RESERVE_NEW_MODE: ON
9234 18:09:30.833058 MR_CBT_SWITCH_FREQ: ON
9235 18:09:30.836528 =========================
9236 18:09:30.854739 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 18:09:30.857817 dram_init: ddr_geometry: 2
9238 18:09:30.876055 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 18:09:30.879086 dram_init: dram init end (result: 0)
9240 18:09:30.885622 DRAM-K: Full calibration passed in 24647 msecs
9241 18:09:30.889291 MRC: failed to locate region type 0.
9242 18:09:30.889398 DRAM rank0 size:0x100000000,
9243 18:09:30.892344 DRAM rank1 size=0x100000000
9244 18:09:30.902568 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 18:09:30.908913 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 18:09:30.915200 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 18:09:30.925484 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 18:09:30.925587 DRAM rank0 size:0x100000000,
9249 18:09:30.928376 DRAM rank1 size=0x100000000
9250 18:09:30.928472 CBMEM:
9251 18:09:30.932120 IMD: root @ 0xfffff000 254 entries.
9252 18:09:30.935307 IMD: root @ 0xffffec00 62 entries.
9253 18:09:30.938815 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 18:09:30.945120 WARNING: RO_VPD is uninitialized or empty.
9255 18:09:30.948304 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 18:09:30.956356 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 18:09:30.968850 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9258 18:09:30.980091 BS: romstage times (exec / console): total (unknown) / 24133 ms
9259 18:09:30.980192
9260 18:09:30.980285
9261 18:09:30.989934 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 18:09:30.993434 ARM64: Exception handlers installed.
9263 18:09:30.996893 ARM64: Testing exception
9264 18:09:31.000263 ARM64: Done test exception
9265 18:09:31.000362 Enumerating buses...
9266 18:09:31.003296 Show all devs... Before device enumeration.
9267 18:09:31.006471 Root Device: enabled 1
9268 18:09:31.009981 CPU_CLUSTER: 0: enabled 1
9269 18:09:31.010074 CPU: 00: enabled 1
9270 18:09:31.013015 Compare with tree...
9271 18:09:31.013109 Root Device: enabled 1
9272 18:09:31.016114 CPU_CLUSTER: 0: enabled 1
9273 18:09:31.019743 CPU: 00: enabled 1
9274 18:09:31.019845 Root Device scanning...
9275 18:09:31.023146 scan_static_bus for Root Device
9276 18:09:31.026126 CPU_CLUSTER: 0 enabled
9277 18:09:31.029761 scan_static_bus for Root Device done
9278 18:09:31.032932 scan_bus: bus Root Device finished in 8 msecs
9279 18:09:31.033040 done
9280 18:09:31.039210 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 18:09:31.042598 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 18:09:31.049095 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 18:09:31.056154 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 18:09:31.056259 Allocating resources...
9285 18:09:31.058968 Reading resources...
9286 18:09:31.062396 Root Device read_resources bus 0 link: 0
9287 18:09:31.065528 DRAM rank0 size:0x100000000,
9288 18:09:31.065622 DRAM rank1 size=0x100000000
9289 18:09:31.072608 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 18:09:31.072707 CPU: 00 missing read_resources
9291 18:09:31.078899 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 18:09:31.082278 Root Device read_resources bus 0 link: 0 done
9293 18:09:31.085691 Done reading resources.
9294 18:09:31.088662 Show resources in subtree (Root Device)...After reading.
9295 18:09:31.092315 Root Device child on link 0 CPU_CLUSTER: 0
9296 18:09:31.095774 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 18:09:31.105590 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 18:09:31.105693 CPU: 00
9299 18:09:31.112052 Root Device assign_resources, bus 0 link: 0
9300 18:09:31.115949 CPU_CLUSTER: 0 missing set_resources
9301 18:09:31.118737 Root Device assign_resources, bus 0 link: 0 done
9302 18:09:31.119273 Done setting resources.
9303 18:09:31.125369 Show resources in subtree (Root Device)...After assigning values.
9304 18:09:31.128792 Root Device child on link 0 CPU_CLUSTER: 0
9305 18:09:31.135359 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 18:09:31.141931 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 18:09:31.145378 CPU: 00
9308 18:09:31.145806 Done allocating resources.
9309 18:09:31.151578 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 18:09:31.152003 Enabling resources...
9311 18:09:31.155274 done.
9312 18:09:31.158446 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 18:09:31.162152 Initializing devices...
9314 18:09:31.162628 Root Device init
9315 18:09:31.164975 init hardware done!
9316 18:09:31.165421 0x00000018: ctrlr->caps
9317 18:09:31.168271 52.000 MHz: ctrlr->f_max
9318 18:09:31.171627 0.400 MHz: ctrlr->f_min
9319 18:09:31.175312 0x40ff8080: ctrlr->voltages
9320 18:09:31.175754 sclk: 390625
9321 18:09:31.176107 Bus Width = 1
9322 18:09:31.178119 sclk: 390625
9323 18:09:31.178583 Bus Width = 1
9324 18:09:31.181463 Early init status = 3
9325 18:09:31.185026 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 18:09:31.188121 in-header: 03 fc 00 00 01 00 00 00
9327 18:09:31.191440 in-data: 00
9328 18:09:31.194961 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 18:09:31.199489 in-header: 03 fd 00 00 00 00 00 00
9330 18:09:31.202780 in-data:
9331 18:09:31.206114 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 18:09:31.209560 in-header: 03 fc 00 00 01 00 00 00
9333 18:09:31.212495 in-data: 00
9334 18:09:31.215814 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 18:09:31.220382 in-header: 03 fd 00 00 00 00 00 00
9336 18:09:31.223939 in-data:
9337 18:09:31.227236 [SSUSB] Setting up USB HOST controller...
9338 18:09:31.230249 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 18:09:31.233690 [SSUSB] phy power-on done.
9340 18:09:31.236532 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 18:09:31.243537 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 18:09:31.246865 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 18:09:31.253229 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 18:09:31.259960 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 18:09:31.266336 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 18:09:31.273154 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 18:09:31.279665 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9348 18:09:31.282677 SPM: binary array size = 0x9dc
9349 18:09:31.285977 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 18:09:31.292752 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 18:09:31.299111 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 18:09:31.305937 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 18:09:31.308699 configure_display: Starting display init
9354 18:09:31.343580 anx7625_power_on_init: Init interface.
9355 18:09:31.346564 anx7625_disable_pd_protocol: Disabled PD feature.
9356 18:09:31.350110 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 18:09:31.377976 anx7625_start_dp_work: Secure OCM version=00
9358 18:09:31.380915 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 18:09:31.396131 sp_tx_get_edid_block: EDID Block = 1
9360 18:09:31.498412 Extracted contents:
9361 18:09:31.502077 header: 00 ff ff ff ff ff ff 00
9362 18:09:31.505280 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 18:09:31.508344 version: 01 04
9364 18:09:31.511805 basic params: 95 1f 11 78 0a
9365 18:09:31.515462 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 18:09:31.518509 established: 00 00 00
9367 18:09:31.524730 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 18:09:31.528275 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 18:09:31.534645 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 18:09:31.541728 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 18:09:31.548313 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 18:09:31.551498 extensions: 00
9373 18:09:31.551578 checksum: fb
9374 18:09:31.551642
9375 18:09:31.554733 Manufacturer: IVO Model 57d Serial Number 0
9376 18:09:31.557787 Made week 0 of 2020
9377 18:09:31.561787 EDID version: 1.4
9378 18:09:31.561867 Digital display
9379 18:09:31.564253 6 bits per primary color channel
9380 18:09:31.564334 DisplayPort interface
9381 18:09:31.567642 Maximum image size: 31 cm x 17 cm
9382 18:09:31.570985 Gamma: 220%
9383 18:09:31.571064 Check DPMS levels
9384 18:09:31.574440 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 18:09:31.580965 First detailed timing is preferred timing
9386 18:09:31.581046 Established timings supported:
9387 18:09:31.584571 Standard timings supported:
9388 18:09:31.587426 Detailed timings
9389 18:09:31.590707 Hex of detail: 383680a07038204018303c0035ae10000019
9390 18:09:31.597289 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 18:09:31.600621 0780 0798 07c8 0820 hborder 0
9392 18:09:31.604154 0438 043b 0447 0458 vborder 0
9393 18:09:31.607122 -hsync -vsync
9394 18:09:31.607202 Did detailed timing
9395 18:09:31.613523 Hex of detail: 000000000000000000000000000000000000
9396 18:09:31.617155 Manufacturer-specified data, tag 0
9397 18:09:31.620305 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 18:09:31.624044 ASCII string: InfoVision
9399 18:09:31.627294 Hex of detail: 000000fe00523134304e574635205248200a
9400 18:09:31.630539 ASCII string: R140NWF5 RH
9401 18:09:31.630619 Checksum
9402 18:09:31.633891 Checksum: 0xfb (valid)
9403 18:09:31.636767 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 18:09:31.640045 DSI data_rate: 832800000 bps
9405 18:09:31.646869 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 18:09:31.650344 anx7625_parse_edid: pixelclock(138800).
9407 18:09:31.653140 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 18:09:31.657081 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 18:09:31.659786 anx7625_dsi_config: config dsi.
9410 18:09:31.666638 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 18:09:31.680348 anx7625_dsi_config: success to config DSI
9412 18:09:31.683946 anx7625_dp_start: MIPI phy setup OK.
9413 18:09:31.686913 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 18:09:31.690510 mtk_ddp_mode_set invalid vrefresh 60
9415 18:09:31.693710 main_disp_path_setup
9416 18:09:31.693789 ovl_layer_smi_id_en
9417 18:09:31.696761 ovl_layer_smi_id_en
9418 18:09:31.696841 ccorr_config
9419 18:09:31.696905 aal_config
9420 18:09:31.700161 gamma_config
9421 18:09:31.700240 postmask_config
9422 18:09:31.703458 dither_config
9423 18:09:31.706851 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 18:09:31.713972 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 18:09:31.716479 Root Device init finished in 551 msecs
9426 18:09:31.719962 CPU_CLUSTER: 0 init
9427 18:09:31.726858 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 18:09:31.733243 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 18:09:31.733324 APU_MBOX 0x190000b0 = 0x10001
9430 18:09:31.736469 APU_MBOX 0x190001b0 = 0x10001
9431 18:09:31.739670 APU_MBOX 0x190005b0 = 0x10001
9432 18:09:31.743238 APU_MBOX 0x190006b0 = 0x10001
9433 18:09:31.749767 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 18:09:31.759368 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9435 18:09:31.772092 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 18:09:31.778311 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 18:09:31.790038 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9438 18:09:31.799569 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 18:09:31.802490 CPU_CLUSTER: 0 init finished in 81 msecs
9440 18:09:31.806116 Devices initialized
9441 18:09:31.809248 Show all devs... After init.
9442 18:09:31.809346 Root Device: enabled 1
9443 18:09:31.812493 CPU_CLUSTER: 0: enabled 1
9444 18:09:31.815876 CPU: 00: enabled 1
9445 18:09:31.819149 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9446 18:09:31.822082 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 18:09:31.825657 ELOG: NV offset 0x57f000 size 0x1000
9448 18:09:31.832285 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9449 18:09:31.838836 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 18:09:31.842345 ELOG: Event(17) added with size 13 at 2024-06-11 18:09:31 UTC
9451 18:09:31.848774 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 18:09:31.852388 in-header: 03 4f 00 00 2c 00 00 00
9453 18:09:31.865485 in-data: ef 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 18:09:31.868948 ELOG: Event(A1) added with size 10 at 2024-06-11 18:09:31 UTC
9455 18:09:31.875213 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9456 18:09:31.881999 ELOG: Event(A0) added with size 9 at 2024-06-11 18:09:31 UTC
9457 18:09:31.885383 elog_add_boot_reason: Logged dev mode boot
9458 18:09:31.891680 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9459 18:09:31.891761 Finalize devices...
9460 18:09:31.895245 Devices finalized
9461 18:09:31.898429 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 18:09:31.901831 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9463 18:09:31.905265 in-header: 03 07 00 00 08 00 00 00
9464 18:09:31.908147 in-data: aa e4 47 04 13 02 00 00
9465 18:09:31.911248 Chrome EC: UHEPI supported
9466 18:09:31.918124 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9467 18:09:31.921558 in-header: 03 a9 00 00 08 00 00 00
9468 18:09:31.924933 in-data: 84 60 60 08 00 00 00 00
9469 18:09:31.931553 ELOG: Event(91) added with size 10 at 2024-06-11 18:09:31 UTC
9470 18:09:31.934964 Chrome EC: clear events_b mask to 0x0000000020004000
9471 18:09:31.940996 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9472 18:09:31.946201 in-header: 03 fd 00 00 00 00 00 00
9473 18:09:31.949411 in-data:
9474 18:09:31.953073 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9475 18:09:31.955890 Writing coreboot table at 0xffe64000
9476 18:09:31.962917 0. 000000000010a000-0000000000113fff: RAMSTAGE
9477 18:09:31.966305 1. 0000000040000000-00000000400fffff: RAM
9478 18:09:31.969137 2. 0000000040100000-000000004032afff: RAMSTAGE
9479 18:09:31.972437 3. 000000004032b000-00000000545fffff: RAM
9480 18:09:31.975760 4. 0000000054600000-000000005465ffff: BL31
9481 18:09:31.979453 5. 0000000054660000-00000000ffe63fff: RAM
9482 18:09:31.985426 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9483 18:09:31.989021 7. 0000000100000000-000000023fffffff: RAM
9484 18:09:31.992161 Passing 5 GPIOs to payload:
9485 18:09:31.995894 NAME | PORT | POLARITY | VALUE
9486 18:09:32.002326 EC in RW | 0x000000aa | low | undefined
9487 18:09:32.005359 EC interrupt | 0x00000005 | low | undefined
9488 18:09:32.012081 TPM interrupt | 0x000000ab | high | undefined
9489 18:09:32.015164 SD card detect | 0x00000011 | high | undefined
9490 18:09:32.021777 speaker enable | 0x00000093 | high | undefined
9491 18:09:32.025287 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9492 18:09:32.028594 in-header: 03 f9 00 00 02 00 00 00
9493 18:09:32.028676 in-data: 02 00
9494 18:09:32.031882 ADC[4]: Raw value=903400 ID=7
9495 18:09:32.035186 ADC[3]: Raw value=213282 ID=1
9496 18:09:32.035266 RAM Code: 0x71
9497 18:09:32.038537 ADC[6]: Raw value=75036 ID=0
9498 18:09:32.041803 ADC[5]: Raw value=212543 ID=1
9499 18:09:32.041883 SKU Code: 0x1
9500 18:09:32.048335 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum cd5d
9501 18:09:32.051970 coreboot table: 964 bytes.
9502 18:09:32.055064 IMD ROOT 0. 0xfffff000 0x00001000
9503 18:09:32.058075 IMD SMALL 1. 0xffffe000 0x00001000
9504 18:09:32.061461 RO MCACHE 2. 0xffffc000 0x00001104
9505 18:09:32.064970 CONSOLE 3. 0xfff7c000 0x00080000
9506 18:09:32.067918 FMAP 4. 0xfff7b000 0x00000452
9507 18:09:32.071680 TIME STAMP 5. 0xfff7a000 0x00000910
9508 18:09:32.074580 VBOOT WORK 6. 0xfff66000 0x00014000
9509 18:09:32.077928 RAMOOPS 7. 0xffe66000 0x00100000
9510 18:09:32.081100 COREBOOT 8. 0xffe64000 0x00002000
9511 18:09:32.081174 IMD small region:
9512 18:09:32.084671 IMD ROOT 0. 0xffffec00 0x00000400
9513 18:09:32.088029 VPD 1. 0xffffeb80 0x0000006c
9514 18:09:32.090779 MMC STATUS 2. 0xffffeb60 0x00000004
9515 18:09:32.097446 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9516 18:09:32.104446 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9517 18:09:32.143189 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9518 18:09:32.146558 Checking segment from ROM address 0x40100000
9519 18:09:32.153020 Checking segment from ROM address 0x4010001c
9520 18:09:32.156691 Loading segment from ROM address 0x40100000
9521 18:09:32.156776 code (compression=0)
9522 18:09:32.166144 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9523 18:09:32.172984 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9524 18:09:32.176288 it's not compressed!
9525 18:09:32.179749 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9526 18:09:32.185996 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9527 18:09:32.203844 Loading segment from ROM address 0x4010001c
9528 18:09:32.203922 Entry Point 0x80000000
9529 18:09:32.207195 Loaded segments
9530 18:09:32.210070 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9531 18:09:32.216603 Jumping to boot code at 0x80000000(0xffe64000)
9532 18:09:32.223707 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9533 18:09:32.229956 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9534 18:09:32.237986 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9535 18:09:32.241551 Checking segment from ROM address 0x40100000
9536 18:09:32.244693 Checking segment from ROM address 0x4010001c
9537 18:09:32.251537 Loading segment from ROM address 0x40100000
9538 18:09:32.251612 code (compression=1)
9539 18:09:32.258082 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9540 18:09:32.267847 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9541 18:09:32.267920 using LZMA
9542 18:09:32.276742 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9543 18:09:32.282929 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9544 18:09:32.286444 Loading segment from ROM address 0x4010001c
9545 18:09:32.289663 Entry Point 0x54601000
9546 18:09:32.289732 Loaded segments
9547 18:09:32.292809 NOTICE: MT8192 bl31_setup
9548 18:09:32.300151 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9549 18:09:32.303091 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9550 18:09:32.307157 WARNING: region 0:
9551 18:09:32.310361 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 18:09:32.310429 WARNING: region 1:
9553 18:09:32.316490 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9554 18:09:32.319880 WARNING: region 2:
9555 18:09:32.323477 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9556 18:09:32.326256 WARNING: region 3:
9557 18:09:32.333106 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9558 18:09:32.333183 WARNING: region 4:
9559 18:09:32.339442 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 18:09:32.339523 WARNING: region 5:
9561 18:09:32.342773 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 18:09:32.346255 WARNING: region 6:
9563 18:09:32.349774 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 18:09:32.352486 WARNING: region 7:
9565 18:09:32.355975 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 18:09:32.362621 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9567 18:09:32.365800 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9568 18:09:32.372996 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9569 18:09:32.375719 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9570 18:09:32.379060 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9571 18:09:32.385409 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9572 18:09:32.389175 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9573 18:09:32.392204 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9574 18:09:32.398739 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9575 18:09:32.402367 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9576 18:09:32.408795 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9577 18:09:32.412324 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9578 18:09:32.415515 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9579 18:09:32.421921 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9580 18:09:32.425390 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9581 18:09:32.431871 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9582 18:09:32.435375 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9583 18:09:32.438537 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9584 18:09:32.445391 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9585 18:09:32.448283 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9586 18:09:32.455045 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9587 18:09:32.458361 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9588 18:09:32.461617 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9589 18:09:32.467883 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9590 18:09:32.471391 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9591 18:09:32.477862 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9592 18:09:32.481432 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9593 18:09:32.484428 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9594 18:09:32.491020 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9595 18:09:32.494558 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9596 18:09:32.500940 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9597 18:09:32.504492 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9598 18:09:32.507443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9599 18:09:32.514032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9600 18:09:32.517254 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9601 18:09:32.521189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9602 18:09:32.523907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9603 18:09:32.530932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9604 18:09:32.534109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9605 18:09:32.537080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9606 18:09:32.540510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9607 18:09:32.547289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9608 18:09:32.550329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9609 18:09:32.553701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9610 18:09:32.556900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9611 18:09:32.563431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9612 18:09:32.566998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9613 18:09:32.569879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9614 18:09:32.576923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9615 18:09:32.580383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9616 18:09:32.586359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9617 18:09:32.589708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9618 18:09:32.596186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9619 18:09:32.599499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9620 18:09:32.603210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9621 18:09:32.609413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9622 18:09:32.612764 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9623 18:09:32.619312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9624 18:09:32.622476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9625 18:09:32.629531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9626 18:09:32.632724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9627 18:09:32.638921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9628 18:09:32.642316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9629 18:09:32.649243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9630 18:09:32.652512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9631 18:09:32.656387 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9632 18:09:32.662139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9633 18:09:32.665744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9634 18:09:32.671868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9635 18:09:32.675710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9636 18:09:32.682517 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9637 18:09:32.685472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9638 18:09:32.688533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9639 18:09:32.695482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9640 18:09:32.698735 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9641 18:09:32.705326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9642 18:09:32.708621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9643 18:09:32.715527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9644 18:09:32.718414 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9645 18:09:32.724967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9646 18:09:32.728435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9647 18:09:32.731709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9648 18:09:32.738332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9649 18:09:32.741353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9650 18:09:32.748462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9651 18:09:32.751202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9652 18:09:32.758104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9653 18:09:32.761165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9654 18:09:32.768075 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9655 18:09:32.771688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9656 18:09:32.774473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9657 18:09:32.780990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9658 18:09:32.784470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9659 18:09:32.790852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9660 18:09:32.794215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9661 18:09:32.800842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9662 18:09:32.804270 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9663 18:09:32.807220 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9664 18:09:32.813942 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9665 18:09:32.817447 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9666 18:09:32.820243 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9667 18:09:32.826793 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9668 18:09:32.830291 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9669 18:09:32.833487 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9670 18:09:32.840442 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9671 18:09:32.843468 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9672 18:09:32.849794 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9673 18:09:32.853099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9674 18:09:32.859755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9675 18:09:32.863163 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9676 18:09:32.866822 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9677 18:09:32.873074 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9678 18:09:32.876038 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9679 18:09:32.883055 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9680 18:09:32.886367 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9681 18:09:32.889290 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9682 18:09:32.896042 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9683 18:09:32.899609 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9684 18:09:32.902609 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9685 18:09:32.909082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9686 18:09:32.912836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9687 18:09:32.916054 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9688 18:09:32.918821 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9689 18:09:32.925748 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9690 18:09:32.928884 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9691 18:09:32.932069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9692 18:09:32.938928 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9693 18:09:32.942089 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9694 18:09:32.948875 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9695 18:09:32.951913 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9696 18:09:32.955368 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9697 18:09:32.961795 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9698 18:09:32.964913 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9699 18:09:32.971592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9700 18:09:32.975161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9701 18:09:32.981885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9702 18:09:32.984761 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9703 18:09:32.988054 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9704 18:09:32.994929 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9705 18:09:32.998049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9706 18:09:33.001234 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9707 18:09:33.007818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9708 18:09:33.010888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9709 18:09:33.018000 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9710 18:09:33.020780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9711 18:09:33.024167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9712 18:09:33.031035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9713 18:09:33.034005 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9714 18:09:33.040664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9715 18:09:33.043848 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9716 18:09:33.050879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9717 18:09:33.053589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9718 18:09:33.057033 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9719 18:09:33.063574 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9720 18:09:33.067219 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9721 18:09:33.073622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9722 18:09:33.076461 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9723 18:09:33.080114 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9724 18:09:33.086556 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9725 18:09:33.089989 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9726 18:09:33.096681 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9727 18:09:33.099655 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9728 18:09:33.103143 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9729 18:09:33.109711 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9730 18:09:33.113172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9731 18:09:33.119350 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9732 18:09:33.122787 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9733 18:09:33.126285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9734 18:09:33.132722 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9735 18:09:33.136228 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9736 18:09:33.142528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9737 18:09:33.145963 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9738 18:09:33.149191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9739 18:09:33.155926 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9740 18:09:33.158834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9741 18:09:33.165254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9742 18:09:33.169270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9743 18:09:33.175560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9744 18:09:33.178671 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9745 18:09:33.182133 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9746 18:09:33.188491 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9747 18:09:33.191622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9748 18:09:33.195179 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9749 18:09:33.201663 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9750 18:09:33.204955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9751 18:09:33.211992 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9752 18:09:33.214676 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9753 18:09:33.221440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9754 18:09:33.224707 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9755 18:09:33.228031 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9756 18:09:33.234411 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9757 18:09:33.237739 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9758 18:09:33.244472 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9759 18:09:33.248060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9760 18:09:33.254404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9761 18:09:33.257715 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9762 18:09:33.260949 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9763 18:09:33.267924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9764 18:09:33.271027 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9765 18:09:33.277690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9766 18:09:33.280708 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9767 18:09:33.284063 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9768 18:09:33.290615 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9769 18:09:33.293664 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9770 18:09:33.300955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9771 18:09:33.303994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9772 18:09:33.310274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9773 18:09:33.313549 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9774 18:09:33.316966 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9775 18:09:33.323735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9776 18:09:33.327184 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9777 18:09:33.333645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9778 18:09:33.336641 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9779 18:09:33.343770 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9780 18:09:33.347081 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9781 18:09:33.350436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9782 18:09:33.356546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9783 18:09:33.360333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9784 18:09:33.367145 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9785 18:09:33.370327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9786 18:09:33.376340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9787 18:09:33.380140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9788 18:09:33.383044 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9789 18:09:33.390044 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9790 18:09:33.392844 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9791 18:09:33.399937 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9792 18:09:33.403149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9793 18:09:33.409770 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9794 18:09:33.412787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9795 18:09:33.416164 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9796 18:09:33.419175 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9797 18:09:33.426294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9798 18:09:33.429642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9799 18:09:33.432585 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9800 18:09:33.435792 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9801 18:09:33.442418 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9802 18:09:33.446081 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9803 18:09:33.452424 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9804 18:09:33.455535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9805 18:09:33.459424 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9806 18:09:33.482628 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9807 18:09:33.484307 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9808 18:09:33.484395 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9809 18:09:33.484481 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9810 18:09:33.484562 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9811 18:09:33.488847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9812 18:09:33.492305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9813 18:09:33.495425 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9814 18:09:33.501848 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9815 18:09:33.505218 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9816 18:09:33.508790 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9817 18:09:33.515351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9818 18:09:33.518220 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9819 18:09:33.525174 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9820 18:09:33.528307 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9821 18:09:33.531477 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9822 18:09:33.538743 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9823 18:09:33.542023 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9824 18:09:33.544668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9825 18:09:33.551567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9826 18:09:33.554745 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9827 18:09:33.561634 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9828 18:09:33.564639 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9829 18:09:33.567791 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9830 18:09:33.574872 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9831 18:09:33.577760 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9832 18:09:33.581102 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9833 18:09:33.587932 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9834 18:09:33.591389 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9835 18:09:33.594114 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9836 18:09:33.600681 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9837 18:09:33.604035 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9838 18:09:33.607596 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9839 18:09:33.610441 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9840 18:09:33.617146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9841 18:09:33.620755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9842 18:09:33.624039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9843 18:09:33.626879 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9844 18:09:33.633780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9845 18:09:33.637344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9846 18:09:33.640531 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9847 18:09:33.646670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9848 18:09:33.650268 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9849 18:09:33.653546 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9850 18:09:33.659807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9851 18:09:33.663350 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9852 18:09:33.669962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9853 18:09:33.672813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9854 18:09:33.679914 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9855 18:09:33.682992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9856 18:09:33.686273 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9857 18:09:33.692988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9858 18:09:33.695987 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9859 18:09:33.702814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9860 18:09:33.706397 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9861 18:09:33.709542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9862 18:09:33.715904 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9863 18:09:33.719305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9864 18:09:33.726146 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9865 18:09:33.729232 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9866 18:09:33.735823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9867 18:09:33.739045 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9868 18:09:33.742303 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9869 18:09:33.748905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9870 18:09:33.752307 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9871 18:09:33.758975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9872 18:09:33.762334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9873 18:09:33.765402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9874 18:09:33.772137 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9875 18:09:33.775801 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9876 18:09:33.782095 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9877 18:09:33.785358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9878 18:09:33.792284 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9879 18:09:33.795288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9880 18:09:33.798597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9881 18:09:33.805479 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9882 18:09:33.808669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9883 18:09:33.815000 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9884 18:09:33.818625 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9885 18:09:33.824766 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9886 18:09:33.827881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9887 18:09:33.831384 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9888 18:09:33.837883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9889 18:09:33.840916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9890 18:09:33.847814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9891 18:09:33.850931 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9892 18:09:33.857425 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9893 18:09:33.860969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9894 18:09:33.864181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9895 18:09:33.870593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9896 18:09:33.874104 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9897 18:09:33.880515 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9898 18:09:33.884002 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9899 18:09:33.887421 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9900 18:09:33.893997 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9901 18:09:33.896884 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9902 18:09:33.903501 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9903 18:09:33.906854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9904 18:09:33.910838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9905 18:09:33.917106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9906 18:09:33.920374 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9907 18:09:33.926874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9908 18:09:33.930302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9909 18:09:33.937042 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9910 18:09:33.939743 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9911 18:09:33.943331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9912 18:09:33.950008 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9913 18:09:33.953504 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9914 18:09:33.960147 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9915 18:09:33.963085 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9916 18:09:33.970200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9917 18:09:33.972841 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9918 18:09:33.976273 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9919 18:09:33.982867 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9920 18:09:33.986451 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9921 18:09:33.992568 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9922 18:09:33.996037 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9923 18:09:34.003120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9924 18:09:34.006283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9925 18:09:34.009477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9926 18:09:34.015917 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9927 18:09:34.019372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9928 18:09:34.026114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9929 18:09:34.029277 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9930 18:09:34.035739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9931 18:09:34.039115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9932 18:09:34.042328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9933 18:09:34.049103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9934 18:09:34.052061 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9935 18:09:34.058718 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9936 18:09:34.062261 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9937 18:09:34.068902 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9938 18:09:34.072058 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9939 18:09:34.078390 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9940 18:09:34.081909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9941 18:09:34.088415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9942 18:09:34.091840 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9943 18:09:34.094866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9944 18:09:34.101703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9945 18:09:34.105173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9946 18:09:34.111433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9947 18:09:34.114879 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9948 18:09:34.121460 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9949 18:09:34.125023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9950 18:09:34.131527 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9951 18:09:34.134685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9952 18:09:34.138257 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9953 18:09:34.144815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9954 18:09:34.147752 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9955 18:09:34.154569 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9956 18:09:34.157479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9957 18:09:34.164469 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9958 18:09:34.167447 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9959 18:09:34.170546 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9960 18:09:34.177158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9961 18:09:34.180859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9962 18:09:34.187554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9963 18:09:34.190487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9964 18:09:34.197388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9965 18:09:34.200501 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9966 18:09:34.206954 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9967 18:09:34.210597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9968 18:09:34.213919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9969 18:09:34.220617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9970 18:09:34.223832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9971 18:09:34.230607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9972 18:09:34.233343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9973 18:09:34.240404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9974 18:09:34.243306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9975 18:09:34.250154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9976 18:09:34.253020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9977 18:09:34.260262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9978 18:09:34.263428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9979 18:09:34.269845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9980 18:09:34.273715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9981 18:09:34.279637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9982 18:09:34.283529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9983 18:09:34.289420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9984 18:09:34.293348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9985 18:09:34.299302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9986 18:09:34.302719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9987 18:09:34.309783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9988 18:09:34.312572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9989 18:09:34.319213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9990 18:09:34.322648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9991 18:09:34.329225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9992 18:09:34.332477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9993 18:09:34.339123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9994 18:09:34.341993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9995 18:09:34.348512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9996 18:09:34.352042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9997 18:09:34.358794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9998 18:09:34.362025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9999 18:09:34.368393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10000 18:09:34.371710 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10001 18:09:34.374955 INFO: [APUAPC] vio 0
10002 18:09:34.378405 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10003 18:09:34.384826 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10004 18:09:34.388380 INFO: [APUAPC] D0_APC_0: 0x400510
10005 18:09:34.388461 INFO: [APUAPC] D0_APC_1: 0x0
10006 18:09:34.391472 INFO: [APUAPC] D0_APC_2: 0x1540
10007 18:09:34.395170 INFO: [APUAPC] D0_APC_3: 0x0
10008 18:09:34.398521 INFO: [APUAPC] D1_APC_0: 0xffffffff
10009 18:09:34.401924 INFO: [APUAPC] D1_APC_1: 0xffffffff
10010 18:09:34.404775 INFO: [APUAPC] D1_APC_2: 0x3fffff
10011 18:09:34.408625 INFO: [APUAPC] D1_APC_3: 0x0
10012 18:09:34.411572 INFO: [APUAPC] D2_APC_0: 0xffffffff
10013 18:09:34.414890 INFO: [APUAPC] D2_APC_1: 0xffffffff
10014 18:09:34.418456 INFO: [APUAPC] D2_APC_2: 0x3fffff
10015 18:09:34.421927 INFO: [APUAPC] D2_APC_3: 0x0
10016 18:09:34.425342 INFO: [APUAPC] D3_APC_0: 0xffffffff
10017 18:09:34.428595 INFO: [APUAPC] D3_APC_1: 0xffffffff
10018 18:09:34.431395 INFO: [APUAPC] D3_APC_2: 0x3fffff
10019 18:09:34.434952 INFO: [APUAPC] D3_APC_3: 0x0
10020 18:09:34.438432 INFO: [APUAPC] D4_APC_0: 0xffffffff
10021 18:09:34.441460 INFO: [APUAPC] D4_APC_1: 0xffffffff
10022 18:09:34.444896 INFO: [APUAPC] D4_APC_2: 0x3fffff
10023 18:09:34.448289 INFO: [APUAPC] D4_APC_3: 0x0
10024 18:09:34.451315 INFO: [APUAPC] D5_APC_0: 0xffffffff
10025 18:09:34.454473 INFO: [APUAPC] D5_APC_1: 0xffffffff
10026 18:09:34.458120 INFO: [APUAPC] D5_APC_2: 0x3fffff
10027 18:09:34.460999 INFO: [APUAPC] D5_APC_3: 0x0
10028 18:09:34.464333 INFO: [APUAPC] D6_APC_0: 0xffffffff
10029 18:09:34.467469 INFO: [APUAPC] D6_APC_1: 0xffffffff
10030 18:09:34.470858 INFO: [APUAPC] D6_APC_2: 0x3fffff
10031 18:09:34.474475 INFO: [APUAPC] D6_APC_3: 0x0
10032 18:09:34.477781 INFO: [APUAPC] D7_APC_0: 0xffffffff
10033 18:09:34.481090 INFO: [APUAPC] D7_APC_1: 0xffffffff
10034 18:09:34.484350 INFO: [APUAPC] D7_APC_2: 0x3fffff
10035 18:09:34.487586 INFO: [APUAPC] D7_APC_3: 0x0
10036 18:09:34.490805 INFO: [APUAPC] D8_APC_0: 0xffffffff
10037 18:09:34.493860 INFO: [APUAPC] D8_APC_1: 0xffffffff
10038 18:09:34.497538 INFO: [APUAPC] D8_APC_2: 0x3fffff
10039 18:09:34.500665 INFO: [APUAPC] D8_APC_3: 0x0
10040 18:09:34.503645 INFO: [APUAPC] D9_APC_0: 0xffffffff
10041 18:09:34.507216 INFO: [APUAPC] D9_APC_1: 0xffffffff
10042 18:09:34.510252 INFO: [APUAPC] D9_APC_2: 0x3fffff
10043 18:09:34.514044 INFO: [APUAPC] D9_APC_3: 0x0
10044 18:09:34.517073 INFO: [APUAPC] D10_APC_0: 0xffffffff
10045 18:09:34.520502 INFO: [APUAPC] D10_APC_1: 0xffffffff
10046 18:09:34.523779 INFO: [APUAPC] D10_APC_2: 0x3fffff
10047 18:09:34.526790 INFO: [APUAPC] D10_APC_3: 0x0
10048 18:09:34.530127 INFO: [APUAPC] D11_APC_0: 0xffffffff
10049 18:09:34.533985 INFO: [APUAPC] D11_APC_1: 0xffffffff
10050 18:09:34.537163 INFO: [APUAPC] D11_APC_2: 0x3fffff
10051 18:09:34.539954 INFO: [APUAPC] D11_APC_3: 0x0
10052 18:09:34.543341 INFO: [APUAPC] D12_APC_0: 0xffffffff
10053 18:09:34.546810 INFO: [APUAPC] D12_APC_1: 0xffffffff
10054 18:09:34.550029 INFO: [APUAPC] D12_APC_2: 0x3fffff
10055 18:09:34.553507 INFO: [APUAPC] D12_APC_3: 0x0
10056 18:09:34.556433 INFO: [APUAPC] D13_APC_0: 0xffffffff
10057 18:09:34.559777 INFO: [APUAPC] D13_APC_1: 0xffffffff
10058 18:09:34.563356 INFO: [APUAPC] D13_APC_2: 0x3fffff
10059 18:09:34.566588 INFO: [APUAPC] D13_APC_3: 0x0
10060 18:09:34.569992 INFO: [APUAPC] D14_APC_0: 0xffffffff
10061 18:09:34.573252 INFO: [APUAPC] D14_APC_1: 0xffffffff
10062 18:09:34.576705 INFO: [APUAPC] D14_APC_2: 0x3fffff
10063 18:09:34.579811 INFO: [APUAPC] D14_APC_3: 0x0
10064 18:09:34.583104 INFO: [APUAPC] D15_APC_0: 0xffffffff
10065 18:09:34.586435 INFO: [APUAPC] D15_APC_1: 0xffffffff
10066 18:09:34.589635 INFO: [APUAPC] D15_APC_2: 0x3fffff
10067 18:09:34.592977 INFO: [APUAPC] D15_APC_3: 0x0
10068 18:09:34.596209 INFO: [APUAPC] APC_CON: 0x4
10069 18:09:34.599212 INFO: [NOCDAPC] D0_APC_0: 0x0
10070 18:09:34.602561 INFO: [NOCDAPC] D0_APC_1: 0x0
10071 18:09:34.606008 INFO: [NOCDAPC] D1_APC_0: 0x0
10072 18:09:34.606106 INFO: [NOCDAPC] D1_APC_1: 0xfff
10073 18:09:34.609542 INFO: [NOCDAPC] D2_APC_0: 0x0
10074 18:09:34.612443 INFO: [NOCDAPC] D2_APC_1: 0xfff
10075 18:09:34.615980 INFO: [NOCDAPC] D3_APC_0: 0x0
10076 18:09:34.619425 INFO: [NOCDAPC] D3_APC_1: 0xfff
10077 18:09:34.622450 INFO: [NOCDAPC] D4_APC_0: 0x0
10078 18:09:34.625852 INFO: [NOCDAPC] D4_APC_1: 0xfff
10079 18:09:34.628835 INFO: [NOCDAPC] D5_APC_0: 0x0
10080 18:09:34.632359 INFO: [NOCDAPC] D5_APC_1: 0xfff
10081 18:09:34.635709 INFO: [NOCDAPC] D6_APC_0: 0x0
10082 18:09:34.639105 INFO: [NOCDAPC] D6_APC_1: 0xfff
10083 18:09:34.642262 INFO: [NOCDAPC] D7_APC_0: 0x0
10084 18:09:34.642336 INFO: [NOCDAPC] D7_APC_1: 0xfff
10085 18:09:34.645637 INFO: [NOCDAPC] D8_APC_0: 0x0
10086 18:09:34.648982 INFO: [NOCDAPC] D8_APC_1: 0xfff
10087 18:09:34.652007 INFO: [NOCDAPC] D9_APC_0: 0x0
10088 18:09:34.655620 INFO: [NOCDAPC] D9_APC_1: 0xfff
10089 18:09:34.658448 INFO: [NOCDAPC] D10_APC_0: 0x0
10090 18:09:34.661848 INFO: [NOCDAPC] D10_APC_1: 0xfff
10091 18:09:34.665454 INFO: [NOCDAPC] D11_APC_0: 0x0
10092 18:09:34.668776 INFO: [NOCDAPC] D11_APC_1: 0xfff
10093 18:09:34.671862 INFO: [NOCDAPC] D12_APC_0: 0x0
10094 18:09:34.675061 INFO: [NOCDAPC] D12_APC_1: 0xfff
10095 18:09:34.678228 INFO: [NOCDAPC] D13_APC_0: 0x0
10096 18:09:34.681602 INFO: [NOCDAPC] D13_APC_1: 0xfff
10097 18:09:34.685015 INFO: [NOCDAPC] D14_APC_0: 0x0
10098 18:09:34.688464 INFO: [NOCDAPC] D14_APC_1: 0xfff
10099 18:09:34.688563 INFO: [NOCDAPC] D15_APC_0: 0x0
10100 18:09:34.691765 INFO: [NOCDAPC] D15_APC_1: 0xfff
10101 18:09:34.695064 INFO: [NOCDAPC] APC_CON: 0x4
10102 18:09:34.698363 INFO: [APUAPC] set_apusys_apc done
10103 18:09:34.701839 INFO: [DEVAPC] devapc_init done
10104 18:09:34.708375 INFO: GICv3 without legacy support detected.
10105 18:09:34.711702 INFO: ARM GICv3 driver initialized in EL3
10106 18:09:34.714633 INFO: Maximum SPI INTID supported: 639
10107 18:09:34.718347 INFO: BL31: Initializing runtime services
10108 18:09:34.724921 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10109 18:09:34.728101 INFO: SPM: enable CPC mode
10110 18:09:34.731487 INFO: mcdi ready for mcusys-off-idle and system suspend
10111 18:09:34.737976 INFO: BL31: Preparing for EL3 exit to normal world
10112 18:09:34.741569 INFO: Entry point address = 0x80000000
10113 18:09:34.741642 INFO: SPSR = 0x8
10114 18:09:34.748206
10115 18:09:34.748298
10116 18:09:34.748383
10117 18:09:34.751528 Starting depthcharge on Spherion...
10118 18:09:34.751598
10119 18:09:34.751681 Wipe memory regions:
10120 18:09:34.751763
10121 18:09:34.752399 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10122 18:09:34.752524 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10123 18:09:34.752633 Setting prompt string to ['asurada:']
10124 18:09:34.752742 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10125 18:09:34.754484 [0x00000040000000, 0x00000054600000)
10126 18:09:34.876778
10127 18:09:34.876936 [0x00000054660000, 0x00000080000000)
10128 18:09:35.137262
10129 18:09:35.137428 [0x000000821a7280, 0x000000ffe64000)
10130 18:09:35.881343
10131 18:09:35.881508 [0x00000100000000, 0x00000240000000)
10132 18:09:37.770794
10133 18:09:37.773916 Initializing XHCI USB controller at 0x11200000.
10134 18:09:38.812234
10135 18:09:38.815311 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10136 18:09:38.815396
10137 18:09:38.815464
10138 18:09:38.815759 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10140 18:09:38.916108 asurada: tftpboot 192.168.201.1 14291485/tftp-deploy-kh0bjebm/kernel/image.itb 14291485/tftp-deploy-kh0bjebm/kernel/cmdline
10141 18:09:38.916238 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10142 18:09:38.916352 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10143 18:09:38.920141 tftpboot 192.168.201.1 14291485/tftp-deploy-kh0bjebm/kernel/image.itp-deploy-kh0bjebm/kernel/cmdline
10144 18:09:38.920222
10145 18:09:38.920284 Waiting for link
10146 18:09:39.078910
10147 18:09:39.079043 R8152: Initializing
10148 18:09:39.079109
10149 18:09:39.081711 Version 6 (ocp_data = 5c30)
10150 18:09:39.081790
10151 18:09:39.085235 R8152: Done initializing
10152 18:09:39.085344
10153 18:09:39.085439 Adding net device
10154 18:09:40.991287
10155 18:09:40.991484 done.
10156 18:09:40.991553
10157 18:09:40.991612 MAC: 00:e0:4c:68:02:81
10158 18:09:40.991669
10159 18:09:40.994729 Sending DHCP discover... done.
10160 18:09:40.994809
10161 18:09:44.947883 Waiting for reply... done.
10162 18:09:44.948103
10163 18:09:44.948223 Sending DHCP request... done.
10164 18:09:44.950530
10165 18:09:44.991268 Waiting for reply... done.
10166 18:09:44.991516
10167 18:09:44.991634 My ip is 192.168.201.14
10168 18:09:44.991738
10169 18:09:44.994178 The DHCP server ip is 192.168.201.1
10170 18:09:44.994332
10171 18:09:45.000734 TFTP server IP predefined by user: 192.168.201.1
10172 18:09:45.000878
10173 18:09:45.007807 Bootfile predefined by user: 14291485/tftp-deploy-kh0bjebm/kernel/image.itb
10174 18:09:45.007967
10175 18:09:45.010731 Sending tftp read request... done.
10176 18:09:45.010857
10177 18:09:45.014910 Waiting for the transfer...
10178 18:09:45.015047
10179 18:09:45.683544 00000000 ################################################################
10180 18:09:45.684045
10181 18:09:46.346936 00080000 ################################################################
10182 18:09:46.347443
10183 18:09:47.034706 00100000 ################################################################
10184 18:09:47.035272
10185 18:09:47.703909 00180000 ################################################################
10186 18:09:47.704528
10187 18:09:48.351570 00200000 ################################################################
10188 18:09:48.351851
10189 18:09:48.957155 00280000 ################################################################
10190 18:09:48.957299
10191 18:09:49.542220 00300000 ################################################################
10192 18:09:49.542378
10193 18:09:50.088967 00380000 ################################################################
10194 18:09:50.089104
10195 18:09:50.624783 00400000 ################################################################
10196 18:09:50.624925
10197 18:09:51.200318 00480000 ################################################################
10198 18:09:51.200462
10199 18:09:51.754190 00500000 ################################################################
10200 18:09:51.754336
10201 18:09:52.323897 00580000 ################################################################
10202 18:09:52.324032
10203 18:09:52.930769 00600000 ################################################################
10204 18:09:52.930939
10205 18:09:53.599456 00680000 ################################################################
10206 18:09:53.599933
10207 18:09:54.293633 00700000 ################################################################
10208 18:09:54.293807
10209 18:09:54.893029 00780000 ################################################################
10210 18:09:54.893680
10211 18:09:55.544523 00800000 ################################################################
10212 18:09:55.544675
10213 18:09:56.158778 00880000 ################################################################
10214 18:09:56.159286
10215 18:09:56.792348 00900000 ################################################################
10216 18:09:56.793006
10217 18:09:57.445151 00980000 ################################################################
10218 18:09:57.445281
10219 18:09:58.078673 00a00000 ################################################################
10220 18:09:58.079405
10221 18:09:58.660760 00a80000 ################################################################
10222 18:09:58.660912
10223 18:09:59.216536 00b00000 ################################################################
10224 18:09:59.216679
10225 18:09:59.770099 00b80000 ################################################################
10226 18:09:59.770253
10227 18:10:00.336929 00c00000 ################################################################
10228 18:10:00.337093
10229 18:10:00.926627 00c80000 ################################################################
10230 18:10:00.927251
10231 18:10:01.539929 00d00000 ################################################################
10232 18:10:01.540073
10233 18:10:02.168512 00d80000 ################################################################
10234 18:10:02.169003
10235 18:10:02.822019 00e00000 ################################################################
10236 18:10:02.822572
10237 18:10:03.437350 00e80000 ################################################################
10238 18:10:03.437507
10239 18:10:03.963236 00f00000 ################################################################
10240 18:10:03.963392
10241 18:10:04.589060 00f80000 ################################################################
10242 18:10:04.589201
10243 18:10:05.190038 01000000 ################################################################
10244 18:10:05.190320
10245 18:10:05.879384 01080000 ################################################################
10246 18:10:05.879907
10247 18:10:06.464207 01100000 ################################################################
10248 18:10:06.464373
10249 18:10:07.016309 01180000 ################################################################
10250 18:10:07.016480
10251 18:10:07.566718 01200000 ################################################################
10252 18:10:07.566862
10253 18:10:08.193567 01280000 ################################################################
10254 18:10:08.194066
10255 18:10:08.853302 01300000 ################################################################
10256 18:10:08.853654
10257 18:10:09.510401 01380000 ################################################################
10258 18:10:09.510594
10259 18:10:10.087421 01400000 ################################################################
10260 18:10:10.087574
10261 18:10:10.661590 01480000 ################################################################
10262 18:10:10.661741
10263 18:10:11.241104 01500000 ################################################################
10264 18:10:11.241251
10265 18:10:11.811957 01580000 ################################################################
10266 18:10:11.812108
10267 18:10:12.393753 01600000 ################################################################
10268 18:10:12.393909
10269 18:10:12.984125 01680000 ################################################################
10270 18:10:12.984278
10271 18:10:13.566741 01700000 ################################################################
10272 18:10:13.566895
10273 18:10:14.152015 01780000 ################################################################
10274 18:10:14.152165
10275 18:10:14.729893 01800000 ################################################################
10276 18:10:14.730044
10277 18:10:15.316907 01880000 ################################################################
10278 18:10:15.317056
10279 18:10:15.887322 01900000 ################################################################
10280 18:10:15.887473
10281 18:10:16.470651 01980000 ################################################################
10282 18:10:16.470811
10283 18:10:17.073109 01a00000 ################################################################
10284 18:10:17.073548
10285 18:10:17.735970 01a80000 ################################################################
10286 18:10:17.736114
10287 18:10:18.391872 01b00000 ################################################################
10288 18:10:18.392324
10289 18:10:19.036585 01b80000 ################################################################
10290 18:10:19.037195
10291 18:10:19.722754 01c00000 ################################################################
10292 18:10:19.723287
10293 18:10:20.441069 01c80000 ################################################################
10294 18:10:20.441591
10295 18:10:21.020102 01d00000 ################################################################
10296 18:10:21.020249
10297 18:10:21.553866 01d80000 ################################################################
10298 18:10:21.554003
10299 18:10:22.019977 01e00000 ######################################################### done.
10300 18:10:22.020116
10301 18:10:22.023244 The bootfile was 31916874 bytes long.
10302 18:10:22.023341
10303 18:10:22.026459 Sending tftp read request... done.
10304 18:10:22.026536
10305 18:10:22.030185 Waiting for the transfer...
10306 18:10:22.030278
10307 18:10:22.030340 00000000 # done.
10308 18:10:22.030400
10309 18:10:22.036622 Command line loaded dynamically from TFTP file: 14291485/tftp-deploy-kh0bjebm/kernel/cmdline
10310 18:10:22.039753
10311 18:10:22.059513 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10312 18:10:22.059603
10313 18:10:22.062685 Loading FIT.
10314 18:10:22.062760
10315 18:10:22.066080 Image ramdisk-1 has 18742477 bytes.
10316 18:10:22.066218
10317 18:10:22.066282 Image fdt-1 has 47258 bytes.
10318 18:10:22.066341
10319 18:10:22.069557 Image kernel-1 has 13125101 bytes.
10320 18:10:22.069633
10321 18:10:22.079024 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10322 18:10:22.079104
10323 18:10:22.095669 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10324 18:10:22.095755
10325 18:10:22.102021 Choosing best match conf-1 for compat google,spherion-rev2.
10326 18:10:22.106538
10327 18:10:22.110593 Connected to device vid:did:rid of 1ae0:0028:00
10328 18:10:22.117533
10329 18:10:22.120948 tpm_get_response: command 0x17b, return code 0x0
10330 18:10:22.121020
10331 18:10:22.124577 ec_init: CrosEC protocol v3 supported (256, 248)
10332 18:10:22.128361
10333 18:10:22.131845 tpm_cleanup: add release locality here.
10334 18:10:22.131918
10335 18:10:22.131979 Shutting down all USB controllers.
10336 18:10:22.134877
10337 18:10:22.134951 Removing current net device
10338 18:10:22.135031
10339 18:10:22.141812 Exiting depthcharge with code 4 at timestamp: 76856576
10340 18:10:22.141891
10341 18:10:22.144825 LZMA decompressing kernel-1 to 0x821a6718
10342 18:10:22.144900
10343 18:10:22.148131 LZMA decompressing kernel-1 to 0x40000000
10344 18:10:23.765736
10345 18:10:23.765905 jumping to kernel
10346 18:10:23.766428 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10347 18:10:23.766541 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10348 18:10:23.766630 Setting prompt string to ['Linux version [0-9]']
10349 18:10:23.766712 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10350 18:10:23.766793 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10351 18:10:23.847751
10352 18:10:23.851191 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10353 18:10:23.854765 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10354 18:10:23.854864 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10355 18:10:23.854943 Setting prompt string to []
10356 18:10:23.855041 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 18:10:23.855122 Using line separator: #'\n'#
10358 18:10:23.855191 No login prompt set.
10359 18:10:23.855272 Parsing kernel messages
10360 18:10:23.855341 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 18:10:23.855559 [login-action] Waiting for messages, (timeout 00:03:38)
10362 18:10:23.855674 Waiting using forced prompt support (timeout 00:01:49)
10363 18:10:23.874331 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10364 18:10:23.877538 [ 0.000000] random: crng init done
10365 18:10:23.884318 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10366 18:10:23.887740 [ 0.000000] efi: UEFI not found.
10367 18:10:23.893987 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10368 18:10:23.903543 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10369 18:10:23.914377 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10370 18:10:23.919951 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10371 18:10:23.926537 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10372 18:10:23.934002 [ 0.000000] printk: bootconsole [mtk8250] enabled
10373 18:10:23.940084 [ 0.000000] NUMA: No NUMA configuration found
10374 18:10:23.946436 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10375 18:10:23.952787 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10376 18:10:23.952864 [ 0.000000] Zone ranges:
10377 18:10:23.959713 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10378 18:10:23.962593 [ 0.000000] DMA32 empty
10379 18:10:23.969474 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10380 18:10:23.972748 [ 0.000000] Movable zone start for each node
10381 18:10:23.976124 [ 0.000000] Early memory node ranges
10382 18:10:23.982277 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10383 18:10:23.989352 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10384 18:10:23.995678 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10385 18:10:24.002190 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10386 18:10:24.008674 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10387 18:10:24.015092 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10388 18:10:24.072237 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10389 18:10:24.079001 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10390 18:10:24.085561 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10391 18:10:24.089037 [ 0.000000] psci: probing for conduit method from DT.
10392 18:10:24.095764 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10393 18:10:24.098492 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10394 18:10:24.105577 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10395 18:10:24.108420 [ 0.000000] psci: SMC Calling Convention v1.2
10396 18:10:24.115327 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10397 18:10:24.118983 [ 0.000000] Detected VIPT I-cache on CPU0
10398 18:10:24.125223 [ 0.000000] CPU features: detected: GIC system register CPU interface
10399 18:10:24.131860 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10400 18:10:24.138104 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10401 18:10:24.145147 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10402 18:10:24.154613 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10403 18:10:24.161255 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10404 18:10:24.164409 [ 0.000000] alternatives: applying boot alternatives
10405 18:10:24.171276 [ 0.000000] Fallback order for Node 0: 0
10406 18:10:24.177906 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10407 18:10:24.181410 [ 0.000000] Policy zone: Normal
10408 18:10:24.204654 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10409 18:10:24.213803 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10410 18:10:24.225676 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10411 18:10:24.235739 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10412 18:10:24.241924 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10413 18:10:24.245366 <6>[ 0.000000] software IO TLB: area num 8.
10414 18:10:24.301944 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10415 18:10:24.451528 <6>[ 0.000000] Memory: 7945756K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407012K reserved, 32768K cma-reserved)
10416 18:10:24.458259 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10417 18:10:24.464634 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10418 18:10:24.467990 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10419 18:10:24.474349 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10420 18:10:24.481123 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10421 18:10:24.484284 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10422 18:10:24.494351 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10423 18:10:24.501101 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10424 18:10:24.507302 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10425 18:10:24.514317 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10426 18:10:24.517665 <6>[ 0.000000] GICv3: 608 SPIs implemented
10427 18:10:24.520439 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10428 18:10:24.527337 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10429 18:10:24.530466 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10430 18:10:24.537388 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10431 18:10:24.550080 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10432 18:10:24.563368 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10433 18:10:24.569924 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10434 18:10:24.577928 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10435 18:10:24.591416 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10436 18:10:24.598123 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10437 18:10:24.604713 <6>[ 0.009179] Console: colour dummy device 80x25
10438 18:10:24.614347 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10439 18:10:24.621137 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10440 18:10:24.624334 <6>[ 0.029221] LSM: Security Framework initializing
10441 18:10:24.630912 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 18:10:24.640713 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 18:10:24.650729 <6>[ 0.051436] cblist_init_generic: Setting adjustable number of callback queues.
10444 18:10:24.657125 <6>[ 0.058882] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 18:10:24.663910 <6>[ 0.065220] cblist_init_generic: Setting adjustable number of callback queues.
10446 18:10:24.670319 <6>[ 0.072648] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 18:10:24.673416 <6>[ 0.079049] rcu: Hierarchical SRCU implementation.
10448 18:10:24.680097 <6>[ 0.084064] rcu: Max phase no-delay instances is 1000.
10449 18:10:24.686748 <6>[ 0.091099] EFI services will not be available.
10450 18:10:24.690094 <6>[ 0.096054] smp: Bringing up secondary CPUs ...
10451 18:10:24.698883 <6>[ 0.101102] Detected VIPT I-cache on CPU1
10452 18:10:24.705494 <6>[ 0.101174] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10453 18:10:24.712123 <6>[ 0.101206] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10454 18:10:24.715513 <6>[ 0.101544] Detected VIPT I-cache on CPU2
10455 18:10:24.725163 <6>[ 0.101598] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10456 18:10:24.731946 <6>[ 0.101616] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10457 18:10:24.734714 <6>[ 0.101872] Detected VIPT I-cache on CPU3
10458 18:10:24.741595 <6>[ 0.101918] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10459 18:10:24.747937 <6>[ 0.101932] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10460 18:10:24.754582 <6>[ 0.102234] CPU features: detected: Spectre-v4
10461 18:10:24.757818 <6>[ 0.102240] CPU features: detected: Spectre-BHB
10462 18:10:24.760966 <6>[ 0.102245] Detected PIPT I-cache on CPU4
10463 18:10:24.767733 <6>[ 0.102303] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10464 18:10:24.777826 <6>[ 0.102319] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10465 18:10:24.780750 <6>[ 0.102614] Detected PIPT I-cache on CPU5
10466 18:10:24.787877 <6>[ 0.102677] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10467 18:10:24.794131 <6>[ 0.102693] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10468 18:10:24.797322 <6>[ 0.102967] Detected PIPT I-cache on CPU6
10469 18:10:24.807354 <6>[ 0.103024] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10470 18:10:24.814117 <6>[ 0.103040] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10471 18:10:24.817698 <6>[ 0.103325] Detected PIPT I-cache on CPU7
10472 18:10:24.823665 <6>[ 0.103392] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10473 18:10:24.830317 <6>[ 0.103408] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10474 18:10:24.833585 <6>[ 0.103456] smp: Brought up 1 node, 8 CPUs
10475 18:10:24.840163 <6>[ 0.244555] SMP: Total of 8 processors activated.
10476 18:10:24.846620 <6>[ 0.249507] CPU features: detected: 32-bit EL0 Support
10477 18:10:24.853288 <6>[ 0.254870] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10478 18:10:24.860114 <6>[ 0.263725] CPU features: detected: Common not Private translations
10479 18:10:24.866429 <6>[ 0.270241] CPU features: detected: CRC32 instructions
10480 18:10:24.873081 <6>[ 0.275625] CPU features: detected: RCpc load-acquire (LDAPR)
10481 18:10:24.876669 <6>[ 0.281585] CPU features: detected: LSE atomic instructions
10482 18:10:24.882787 <6>[ 0.287367] CPU features: detected: Privileged Access Never
10483 18:10:24.889793 <6>[ 0.293147] CPU features: detected: RAS Extension Support
10484 18:10:24.896614 <6>[ 0.298755] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10485 18:10:24.900031 <6>[ 0.305976] CPU: All CPU(s) started at EL2
10486 18:10:24.906066 <6>[ 0.310319] alternatives: applying system-wide alternatives
10487 18:10:24.916500 <6>[ 0.321101] devtmpfs: initialized
10488 18:10:24.932051 <6>[ 0.330050] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10489 18:10:24.938467 <6>[ 0.340012] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10490 18:10:24.944833 <6>[ 0.348024] pinctrl core: initialized pinctrl subsystem
10491 18:10:24.948385 <6>[ 0.354662] DMI not present or invalid.
10492 18:10:24.955354 <6>[ 0.359077] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10493 18:10:24.965092 <6>[ 0.365931] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10494 18:10:24.971857 <6>[ 0.373520] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10495 18:10:24.981315 <6>[ 0.381737] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10496 18:10:24.984767 <6>[ 0.389981] audit: initializing netlink subsys (disabled)
10497 18:10:24.994743 <5>[ 0.395677] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10498 18:10:25.001323 <6>[ 0.396398] thermal_sys: Registered thermal governor 'step_wise'
10499 18:10:25.007471 <6>[ 0.403644] thermal_sys: Registered thermal governor 'power_allocator'
10500 18:10:25.010972 <6>[ 0.409901] cpuidle: using governor menu
10501 18:10:25.017752 <6>[ 0.420858] NET: Registered PF_QIPCRTR protocol family
10502 18:10:25.024307 <6>[ 0.426341] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10503 18:10:25.030427 <6>[ 0.433442] ASID allocator initialised with 32768 entries
10504 18:10:25.033977 <6>[ 0.440033] Serial: AMBA PL011 UART driver
10505 18:10:25.044244 <4>[ 0.448910] Trying to register duplicate clock ID: 134
10506 18:10:25.104292 <6>[ 0.512183] KASLR enabled
10507 18:10:25.118609 <6>[ 0.519879] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10508 18:10:25.124971 <6>[ 0.526891] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10509 18:10:25.131894 <6>[ 0.533384] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10510 18:10:25.138456 <6>[ 0.540388] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10511 18:10:25.144917 <6>[ 0.546875] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10512 18:10:25.151379 <6>[ 0.553881] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10513 18:10:25.157811 <6>[ 0.560369] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10514 18:10:25.164407 <6>[ 0.567372] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10515 18:10:25.167826 <6>[ 0.574838] ACPI: Interpreter disabled.
10516 18:10:25.176515 <6>[ 0.581269] iommu: Default domain type: Translated
10517 18:10:25.183353 <6>[ 0.586418] iommu: DMA domain TLB invalidation policy: strict mode
10518 18:10:25.186626 <5>[ 0.593077] SCSI subsystem initialized
10519 18:10:25.192982 <6>[ 0.597321] usbcore: registered new interface driver usbfs
10520 18:10:25.199333 <6>[ 0.603050] usbcore: registered new interface driver hub
10521 18:10:25.202934 <6>[ 0.608601] usbcore: registered new device driver usb
10522 18:10:25.210236 <6>[ 0.614723] pps_core: LinuxPPS API ver. 1 registered
10523 18:10:25.219695 <6>[ 0.619918] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10524 18:10:25.223141 <6>[ 0.629262] PTP clock support registered
10525 18:10:25.226727 <6>[ 0.633503] EDAC MC: Ver: 3.0.0
10526 18:10:25.233954 <6>[ 0.638704] FPGA manager framework
10527 18:10:25.240349 <6>[ 0.642383] Advanced Linux Sound Architecture Driver Initialized.
10528 18:10:25.244184 <6>[ 0.649159] vgaarb: loaded
10529 18:10:25.250521 <6>[ 0.652313] clocksource: Switched to clocksource arch_sys_counter
10530 18:10:25.253843 <5>[ 0.658755] VFS: Disk quotas dquot_6.6.0
10531 18:10:25.260335 <6>[ 0.662941] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10532 18:10:25.263647 <6>[ 0.670133] pnp: PnP ACPI: disabled
10533 18:10:25.272094 <6>[ 0.676858] NET: Registered PF_INET protocol family
10534 18:10:25.282010 <6>[ 0.682448] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10535 18:10:25.293570 <6>[ 0.694771] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10536 18:10:25.303362 <6>[ 0.703588] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10537 18:10:25.309870 <6>[ 0.711558] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10538 18:10:25.319345 <6>[ 0.720262] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10539 18:10:25.326208 <6>[ 0.730003] TCP: Hash tables configured (established 65536 bind 65536)
10540 18:10:25.332524 <6>[ 0.736867] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 18:10:25.342584 <6>[ 0.744063] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 18:10:25.348955 <6>[ 0.751772] NET: Registered PF_UNIX/PF_LOCAL protocol family
10543 18:10:25.356059 <6>[ 0.757930] RPC: Registered named UNIX socket transport module.
10544 18:10:25.358920 <6>[ 0.764084] RPC: Registered udp transport module.
10545 18:10:25.365941 <6>[ 0.769017] RPC: Registered tcp transport module.
10546 18:10:25.372182 <6>[ 0.773950] RPC: Registered tcp NFSv4.1 backchannel transport module.
10547 18:10:25.375658 <6>[ 0.780616] PCI: CLS 0 bytes, default 64
10548 18:10:25.378494 <6>[ 0.785034] Unpacking initramfs...
10549 18:10:25.388637 <6>[ 0.788754] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10550 18:10:25.395344 <6>[ 0.797414] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10551 18:10:25.401823 <6>[ 0.806252] kvm [1]: IPA Size Limit: 40 bits
10552 18:10:25.405076 <6>[ 0.810780] kvm [1]: GICv3: no GICV resource entry
10553 18:10:25.411607 <6>[ 0.815803] kvm [1]: disabling GICv2 emulation
10554 18:10:25.418517 <6>[ 0.820486] kvm [1]: GIC system register CPU interface enabled
10555 18:10:25.421436 <6>[ 0.826653] kvm [1]: vgic interrupt IRQ18
10556 18:10:25.428020 <6>[ 0.832361] kvm [1]: VHE mode initialized successfully
10557 18:10:25.434492 <5>[ 0.838739] Initialise system trusted keyrings
10558 18:10:25.441225 <6>[ 0.843559] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10559 18:10:25.449013 <6>[ 0.853566] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10560 18:10:25.455638 <5>[ 0.859934] NFS: Registering the id_resolver key type
10561 18:10:25.458848 <5>[ 0.865231] Key type id_resolver registered
10562 18:10:25.465735 <5>[ 0.869644] Key type id_legacy registered
10563 18:10:25.471631 <6>[ 0.873919] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10564 18:10:25.478303 <6>[ 0.880841] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10565 18:10:25.484908 <6>[ 0.888563] 9p: Installing v9fs 9p2000 file system support
10566 18:10:25.521476 <5>[ 0.926372] Key type asymmetric registered
10567 18:10:25.525061 <5>[ 0.930703] Asymmetric key parser 'x509' registered
10568 18:10:25.534501 <6>[ 0.935840] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10569 18:10:25.537939 <6>[ 0.943453] io scheduler mq-deadline registered
10570 18:10:25.541703 <6>[ 0.948214] io scheduler kyber registered
10571 18:10:25.560538 <6>[ 0.965245] EINJ: ACPI disabled.
10572 18:10:25.593908 <4>[ 0.991744] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 18:10:25.603275 <4>[ 1.002486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 18:10:25.618561 <6>[ 1.023403] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10575 18:10:25.626851 <6>[ 1.031358] printk: console [ttyS0] disabled
10576 18:10:25.654454 <6>[ 1.055993] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10577 18:10:25.661333 <6>[ 1.065465] printk: console [ttyS0] enabled
10578 18:10:25.664756 <6>[ 1.065465] printk: console [ttyS0] enabled
10579 18:10:25.670903 <6>[ 1.074359] printk: bootconsole [mtk8250] disabled
10580 18:10:25.674208 <6>[ 1.074359] printk: bootconsole [mtk8250] disabled
10581 18:10:25.680804 <6>[ 1.085404] SuperH (H)SCI(F) driver initialized
10582 18:10:25.684439 <6>[ 1.090675] msm_serial: driver initialized
10583 18:10:25.697817 <6>[ 1.099599] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10584 18:10:25.708347 <6>[ 1.108143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10585 18:10:25.714604 <6>[ 1.116685] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10586 18:10:25.724382 <6>[ 1.125317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10587 18:10:25.734565 <6>[ 1.134024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10588 18:10:25.741031 <6>[ 1.142738] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10589 18:10:25.751162 <6>[ 1.151278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10590 18:10:25.757622 <6>[ 1.160073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10591 18:10:25.767408 <6>[ 1.168615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10592 18:10:25.779638 <6>[ 1.184080] loop: module loaded
10593 18:10:25.785723 <6>[ 1.190115] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10594 18:10:25.808467 <4>[ 1.213288] mtk-pmic-keys: Failed to locate of_node [id: -1]
10595 18:10:25.815117 <6>[ 1.220056] megasas: 07.719.03.00-rc1
10596 18:10:25.824602 <6>[ 1.229716] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10597 18:10:25.834617 <6>[ 1.239698] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10598 18:10:25.851790 <6>[ 1.256281] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10599 18:10:25.911909 <6>[ 1.309994] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10600 18:10:26.174587 <6>[ 1.579133] Freeing initrd memory: 18296K
10601 18:10:26.193959 <6>[ 1.590773] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10602 18:10:26.196777 <6>[ 1.601776] tun: Universal TUN/TAP device driver, 1.6
10603 18:10:26.200207 <6>[ 1.607835] thunder_xcv, ver 1.0
10604 18:10:26.203605 <6>[ 1.611339] thunder_bgx, ver 1.0
10605 18:10:26.207270 <6>[ 1.614839] nicpf, ver 1.0
10606 18:10:26.217256 <6>[ 1.618877] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10607 18:10:26.220748 <6>[ 1.626354] hns3: Copyright (c) 2017 Huawei Corporation.
10608 18:10:26.227245 <6>[ 1.631944] hclge is initializing
10609 18:10:26.230787 <6>[ 1.635519] e1000: Intel(R) PRO/1000 Network Driver
10610 18:10:26.237058 <6>[ 1.640648] e1000: Copyright (c) 1999-2006 Intel Corporation.
10611 18:10:26.240455 <6>[ 1.646665] e1000e: Intel(R) PRO/1000 Network Driver
10612 18:10:26.247015 <6>[ 1.651881] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10613 18:10:26.253845 <6>[ 1.658068] igb: Intel(R) Gigabit Ethernet Network Driver
10614 18:10:26.260771 <6>[ 1.663719] igb: Copyright (c) 2007-2014 Intel Corporation.
10615 18:10:26.267467 <6>[ 1.669558] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10616 18:10:26.273982 <6>[ 1.676076] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10617 18:10:26.276989 <6>[ 1.682541] sky2: driver version 1.30
10618 18:10:26.283646 <6>[ 1.687477] usbcore: registered new device driver r8152-cfgselector
10619 18:10:26.290789 <6>[ 1.694020] usbcore: registered new interface driver r8152
10620 18:10:26.296571 <6>[ 1.699839] VFIO - User Level meta-driver version: 0.3
10621 18:10:26.303308 <6>[ 1.708080] usbcore: registered new interface driver usb-storage
10622 18:10:26.309700 <6>[ 1.714531] usbcore: registered new device driver onboard-usb-hub
10623 18:10:26.318619 <6>[ 1.723715] mt6397-rtc mt6359-rtc: registered as rtc0
10624 18:10:26.328611 <6>[ 1.729183] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:10:25 UTC (1718129425)
10625 18:10:26.331750 <6>[ 1.738756] i2c_dev: i2c /dev entries driver
10626 18:10:26.346072 <4>[ 1.750886] cpu cpu0: supply cpu not found, using dummy regulator
10627 18:10:26.352915 <4>[ 1.757313] cpu cpu1: supply cpu not found, using dummy regulator
10628 18:10:26.359086 <4>[ 1.763734] cpu cpu2: supply cpu not found, using dummy regulator
10629 18:10:26.365768 <4>[ 1.770137] cpu cpu3: supply cpu not found, using dummy regulator
10630 18:10:26.372563 <4>[ 1.776537] cpu cpu4: supply cpu not found, using dummy regulator
10631 18:10:26.378736 <4>[ 1.782936] cpu cpu5: supply cpu not found, using dummy regulator
10632 18:10:26.385715 <4>[ 1.789331] cpu cpu6: supply cpu not found, using dummy regulator
10633 18:10:26.392289 <4>[ 1.795732] cpu cpu7: supply cpu not found, using dummy regulator
10634 18:10:26.411673 <6>[ 1.816392] cpu cpu0: EM: created perf domain
10635 18:10:26.414734 <6>[ 1.821335] cpu cpu4: EM: created perf domain
10636 18:10:26.422376 <6>[ 1.826968] sdhci: Secure Digital Host Controller Interface driver
10637 18:10:26.428528 <6>[ 1.833399] sdhci: Copyright(c) Pierre Ossman
10638 18:10:26.435383 <6>[ 1.838368] Synopsys Designware Multimedia Card Interface Driver
10639 18:10:26.441594 <6>[ 1.845022] sdhci-pltfm: SDHCI platform and OF driver helper
10640 18:10:26.445366 <6>[ 1.845056] mmc0: CQHCI version 5.10
10641 18:10:26.451607 <6>[ 1.855254] ledtrig-cpu: registered to indicate activity on CPUs
10642 18:10:26.458660 <6>[ 1.862325] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10643 18:10:26.464796 <6>[ 1.869397] usbcore: registered new interface driver usbhid
10644 18:10:26.468626 <6>[ 1.875220] usbhid: USB HID core driver
10645 18:10:26.478244 <6>[ 1.879383] spi_master spi0: will run message pump with realtime priority
10646 18:10:26.519075 <6>[ 1.917422] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10647 18:10:26.537278 <6>[ 1.932510] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10648 18:10:26.540788 <6>[ 1.945381] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10649 18:10:26.548720 <6>[ 1.953329] cros-ec-spi spi0.0: Chrome EC device registered
10650 18:10:26.555124 <6>[ 1.959323] mmc0: Command Queue Engine enabled
10651 18:10:26.561953 <6>[ 1.964067] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10652 18:10:26.568353 <6>[ 1.971795] mmcblk0: mmc0:0001 DA4128 116 GiB
10653 18:10:26.575179 <6>[ 1.980326] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10654 18:10:26.582429 <6>[ 1.987530] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10655 18:10:26.592449 <6>[ 1.992289] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 18:10:26.595550 <6>[ 1.993438] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10657 18:10:26.602332 <6>[ 2.003364] NET: Registered PF_PACKET protocol family
10658 18:10:26.609002 <6>[ 2.007910] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10659 18:10:26.612638 <6>[ 2.012676] 9pnet: Installing 9P2000 support
10660 18:10:26.619554 <5>[ 2.023667] Key type dns_resolver registered
10661 18:10:26.622540 <6>[ 2.028675] registered taskstats version 1
10662 18:10:26.628901 <5>[ 2.033052] Loading compiled-in X.509 certificates
10663 18:10:26.657601 <4>[ 2.055663] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10664 18:10:26.667201 <4>[ 2.066408] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 18:10:26.683178 <6>[ 2.087591] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10666 18:10:26.690442 <6>[ 2.094422] xhci-mtk 11200000.usb: xHCI Host Controller
10667 18:10:26.696600 <6>[ 2.099916] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10668 18:10:26.706450 <6>[ 2.107758] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10669 18:10:26.713420 <6>[ 2.117189] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10670 18:10:26.720142 <6>[ 2.123274] xhci-mtk 11200000.usb: xHCI Host Controller
10671 18:10:26.726456 <6>[ 2.128751] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10672 18:10:26.733078 <6>[ 2.136398] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10673 18:10:26.739442 <6>[ 2.144033] hub 1-0:1.0: USB hub found
10674 18:10:26.743003 <6>[ 2.148071] hub 1-0:1.0: 1 port detected
10675 18:10:26.750145 <6>[ 2.152347] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10676 18:10:26.756250 <6>[ 2.160853] hub 2-0:1.0: USB hub found
10677 18:10:26.759737 <6>[ 2.164859] hub 2-0:1.0: 1 port detected
10678 18:10:26.767227 <6>[ 2.171756] mtk-msdc 11f70000.mmc: Got CD GPIO
10679 18:10:26.779695 <6>[ 2.181087] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10680 18:10:26.789893 <6>[ 2.189489] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10681 18:10:26.796367 <6>[ 2.197830] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10682 18:10:26.806090 <6>[ 2.206168] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10683 18:10:26.812988 <6>[ 2.214505] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10684 18:10:26.822915 <6>[ 2.222842] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10685 18:10:26.829154 <6>[ 2.231181] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10686 18:10:26.839581 <6>[ 2.239519] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10687 18:10:26.846208 <6>[ 2.247866] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10688 18:10:26.855973 <6>[ 2.256206] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10689 18:10:26.862575 <6>[ 2.264544] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10690 18:10:26.872303 <6>[ 2.272891] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10691 18:10:26.879045 <6>[ 2.281232] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10692 18:10:26.888869 <6>[ 2.289571] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10693 18:10:26.895179 <6>[ 2.297909] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10694 18:10:26.902357 <6>[ 2.306600] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10695 18:10:26.909192 <6>[ 2.313768] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10696 18:10:26.915955 <6>[ 2.320592] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10697 18:10:26.926536 <6>[ 2.327366] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10698 18:10:26.932711 <6>[ 2.334339] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10699 18:10:26.939432 <6>[ 2.341198] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10700 18:10:26.949069 <6>[ 2.350338] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10701 18:10:26.958864 <6>[ 2.359460] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10702 18:10:26.969085 <6>[ 2.368753] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10703 18:10:26.979094 <6>[ 2.378221] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10704 18:10:26.989327 <6>[ 2.387689] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10705 18:10:26.995329 <6>[ 2.396808] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10706 18:10:27.005379 <6>[ 2.406274] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10707 18:10:27.015380 <6>[ 2.415393] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10708 18:10:27.025697 <6>[ 2.424691] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10709 18:10:27.034998 <6>[ 2.434851] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10710 18:10:27.045629 <6>[ 2.446658] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10711 18:10:27.053646 <6>[ 2.457806] Trying to probe devices needed for running init ...
10712 18:10:27.063868 <3>[ 2.465176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10713 18:10:27.167598 <6>[ 2.568591] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 18:10:27.321985 <6>[ 2.726457] hub 1-1:1.0: USB hub found
10715 18:10:27.325028 <6>[ 2.730994] hub 1-1:1.0: 4 ports detected
10716 18:10:27.336180 <6>[ 2.740557] hub 1-1:1.0: USB hub found
10717 18:10:27.339100 <6>[ 2.744928] hub 1-1:1.0: 4 ports detected
10718 18:10:27.447794 <6>[ 2.848926] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10719 18:10:27.473963 <6>[ 2.878347] hub 2-1:1.0: USB hub found
10720 18:10:27.477303 <6>[ 2.882845] hub 2-1:1.0: 3 ports detected
10721 18:10:27.488104 <6>[ 2.892872] hub 2-1:1.0: USB hub found
10722 18:10:27.491565 <6>[ 2.897279] hub 2-1:1.0: 3 ports detected
10723 18:10:27.658926 <6>[ 3.060627] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10724 18:10:27.791674 <6>[ 3.196412] hub 1-1.4:1.0: USB hub found
10725 18:10:27.795075 <6>[ 3.201039] hub 1-1.4:1.0: 2 ports detected
10726 18:10:27.807441 <6>[ 3.211795] hub 1-1.4:1.0: USB hub found
10727 18:10:27.810706 <6>[ 3.216377] hub 1-1.4:1.0: 2 ports detected
10728 18:10:27.871343 <6>[ 3.272847] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10729 18:10:27.979453 <6>[ 3.381264] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10730 18:10:28.015913 <4>[ 3.417415] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10731 18:10:28.025473 <4>[ 3.426510] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10732 18:10:28.065850 <6>[ 3.470278] r8152 2-1.3:1.0 eth0: v1.12.13
10733 18:10:28.110763 <6>[ 3.512346] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10734 18:10:28.303437 <6>[ 3.704437] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10735 18:10:29.797130 <6>[ 5.202356] r8152 2-1.3:1.0 eth0: carrier on
10736 18:10:29.852003 <5>[ 5.228425] Sending DHCP requests ., OK
10737 18:10:29.858045 <6>[ 5.260799] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10738 18:10:29.861680 <6>[ 5.269098] IP-Config: Complete:
10739 18:10:29.874989 <6>[ 5.272596] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10740 18:10:29.881139 <6>[ 5.283319] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10741 18:10:29.890908 <6>[ 5.291938] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10742 18:10:29.894437 <6>[ 5.291948] nameserver0=192.168.201.1
10743 18:10:29.897588 <6>[ 5.304113] clk: Disabling unused clocks
10744 18:10:29.901466 <6>[ 5.309574] ALSA device list:
10745 18:10:29.907855 <6>[ 5.312876] No soundcards found.
10746 18:10:29.916098 <6>[ 5.320557] Freeing unused kernel memory: 8512K
10747 18:10:29.918855 <6>[ 5.325503] Run /init as init process
10748 18:10:29.929249 Loading, please wait...
10749 18:10:29.964356 Starting systemd-udevd version 252.22-1~deb12u1
10750 18:10:30.210822 <6>[ 5.612738] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10751 18:10:30.232606 <6>[ 5.634538] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10752 18:10:30.242348 <6>[ 5.643390] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10753 18:10:30.263889 <6>[ 5.668924] mc: Linux media interface: v0.10
10754 18:10:30.277199 <6>[ 5.679102] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10755 18:10:30.284318 <4>[ 5.679341] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10756 18:10:30.293957 <6>[ 5.695305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10757 18:10:30.300456 <4>[ 5.702901] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10758 18:10:30.307461 <6>[ 5.703433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10759 18:10:30.314059 <6>[ 5.712599] videodev: Linux video capture interface: v2.00
10760 18:10:30.323599 <4>[ 5.718745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10761 18:10:30.330285 <3>[ 5.726578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 18:10:30.340868 <6>[ 5.733969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10763 18:10:30.346485 <3>[ 5.741460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 18:10:30.356667 <6>[ 5.749538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10765 18:10:30.363271 <3>[ 5.757686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 18:10:30.369741 <6>[ 5.765973] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10767 18:10:30.380095 <3>[ 5.773866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 18:10:30.386450 <6>[ 5.774078] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10769 18:10:30.393282 <6>[ 5.778747] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10770 18:10:30.399524 <6>[ 5.778751] pci_bus 0000:00: root bus resource [bus 00-ff]
10771 18:10:30.406793 <6>[ 5.778755] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10772 18:10:30.416043 <6>[ 5.778757] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10773 18:10:30.422777 <6>[ 5.778781] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10774 18:10:30.429511 <6>[ 5.778794] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10775 18:10:30.436278 <6>[ 5.778855] pci 0000:00:00.0: supports D1 D2
10776 18:10:30.442482 <6>[ 5.778857] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10777 18:10:30.449366 <6>[ 5.779746] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10778 18:10:30.456043 <6>[ 5.779816] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10779 18:10:30.462696 <6>[ 5.779840] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10780 18:10:30.472401 <6>[ 5.779855] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10781 18:10:30.479005 <6>[ 5.779870] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10782 18:10:30.482455 <6>[ 5.779972] pci 0000:01:00.0: supports D1 D2
10783 18:10:30.489253 <6>[ 5.779973] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10784 18:10:30.499382 <6>[ 5.781572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10785 18:10:30.506036 <3>[ 5.789699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 18:10:30.515647 <6>[ 5.797252] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10787 18:10:30.522368 <6>[ 5.797257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10788 18:10:30.529148 <6>[ 5.797472] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10789 18:10:30.538693 <3>[ 5.804780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 18:10:30.545348 <6>[ 5.810316] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10791 18:10:30.555009 <3>[ 5.817361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 18:10:30.561674 <4>[ 5.818109] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10793 18:10:30.568185 <4>[ 5.818109] Fallback method does not support PEC.
10794 18:10:30.574874 <6>[ 5.827192] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10795 18:10:30.584819 <6>[ 5.832134] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10796 18:10:30.594959 <3>[ 5.833397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 18:10:30.601698 <3>[ 5.833449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 18:10:30.611221 <3>[ 5.836945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 18:10:30.618101 <6>[ 5.840887] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10800 18:10:30.627771 <3>[ 5.845425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 18:10:30.634275 <6>[ 5.852352] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10802 18:10:30.644079 <3>[ 5.860516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 18:10:30.654141 <6>[ 5.861231] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10804 18:10:30.660639 <6>[ 5.861596] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10805 18:10:30.670639 <3>[ 5.863342] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 18:10:30.680245 <6>[ 5.866819] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10807 18:10:30.686903 <3>[ 5.874284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 18:10:30.693169 <6>[ 5.881779] pci 0000:00:00.0: PCI bridge to [bus 01]
10809 18:10:30.696887 <6>[ 5.882219] Bluetooth: Core ver 2.22
10810 18:10:30.699940 <6>[ 5.882281] NET: Registered PF_BLUETOOTH protocol family
10811 18:10:30.707059 <6>[ 5.882282] Bluetooth: HCI device and connection manager initialized
10812 18:10:30.713249 <6>[ 5.882297] Bluetooth: HCI socket layer initialized
10813 18:10:30.719679 <6>[ 5.882303] Bluetooth: L2CAP socket layer initialized
10814 18:10:30.723050 <6>[ 5.882311] Bluetooth: SCO socket layer initialized
10815 18:10:30.730121 <6>[ 5.883340] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10816 18:10:30.736292 <6>[ 5.885832] remoteproc remoteproc0: scp is available
10817 18:10:30.742907 <6>[ 5.885910] remoteproc remoteproc0: powering up scp
10818 18:10:30.749974 <6>[ 5.885917] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10819 18:10:30.755956 <6>[ 5.885950] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10820 18:10:30.762741 <3>[ 5.889275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10821 18:10:30.773517 <6>[ 5.893775] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10822 18:10:30.779114 <3>[ 5.900628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10823 18:10:30.786066 <6>[ 5.908664] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10824 18:10:30.792624 <3>[ 5.916530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 18:10:30.799552 <6>[ 5.925039] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10826 18:10:30.806010 <6>[ 5.925408] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10827 18:10:30.819110 <6>[ 5.926434] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10828 18:10:30.825521 <6>[ 5.926524] usbcore: registered new interface driver uvcvideo
10829 18:10:30.832382 <3>[ 5.933475] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 18:10:30.842501 <3>[ 5.933480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 18:10:30.848948 <6>[ 5.940888] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10832 18:10:30.855322 <3>[ 5.948449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 18:10:30.861675 <6>[ 5.949076] usbcore: registered new interface driver btusb
10834 18:10:30.872007 <4>[ 5.950476] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10835 18:10:30.878241 <3>[ 5.950488] Bluetooth: hci0: Failed to load firmware file (-2)
10836 18:10:30.884915 <3>[ 5.950492] Bluetooth: hci0: Failed to set up firmware (-2)
10837 18:10:30.894997 <4>[ 5.950496] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10838 18:10:30.901220 <6>[ 5.979739] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10839 18:10:30.907917 <5>[ 5.980045] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10840 18:10:30.914581 <5>[ 5.995894] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10841 18:10:30.921277 <6>[ 6.011288] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10842 18:10:30.930988 <6>[ 6.011322] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10843 18:10:30.937644 <6>[ 6.011331] remoteproc remoteproc0: remote processor scp is now up
10844 18:10:30.944141 <5>[ 6.011982] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10845 18:10:30.954283 <6>[ 6.029834] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10846 18:10:30.964249 <4>[ 6.036654] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10847 18:10:30.967330 <6>[ 6.036659] cfg80211: failed to load regulatory.db
10848 18:10:30.973893 <6>[ 6.129031] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10849 18:10:30.984033 <6>[ 6.137235] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10850 18:10:30.990285 <6>[ 6.141267] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10851 18:10:31.011255 <6>[ 6.416462] mt7921e 0000:01:00.0: ASIC revision: 79610010
10852 18:10:31.114627 <6>[ 6.516093] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10853 18:10:31.117618 <6>[ 6.516093]
10854 18:10:31.129343 Begin: Loading essential drivers ... done.
10855 18:10:31.132142 Begin: Running /scripts/init-premount ... done.
10856 18:10:31.139073 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10857 18:10:31.148434 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10858 18:10:31.151730 Device /sys/class/net/eth0 found
10859 18:10:31.152197 done.
10860 18:10:31.166870 Begin: Waiting up to 180 secs for any network device to become available ... done.
10861 18:10:31.215703 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10862 18:10:31.223182 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10863 18:10:31.229673 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10864 18:10:31.236499 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10865 18:10:31.242956 host : mt8192-asurada-spherion-r0-cbg-9
10866 18:10:31.249480 domain : lava-rack
10867 18:10:31.252709 rootserver: 192.168.201.1 rootpath:
10868 18:10:31.256122 filename :
10869 18:10:31.380601 <6>[ 6.783033] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10870 18:10:31.404673 done.
10871 18:10:31.413416 Begin: Running /scripts/nfs-bottom ... done.
10872 18:10:31.431634 Begin: Running /scripts/init-bottom ... done.
10873 18:10:32.765867 <6>[ 8.171645] NET: Registered PF_INET6 protocol family
10874 18:10:32.773616 <6>[ 8.179031] Segment Routing with IPv6
10875 18:10:32.776903 <6>[ 8.183035] In-situ OAM (IOAM) with IPv6
10876 18:10:32.955331 <30>[ 8.331264] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10877 18:10:32.958426 <30>[ 8.364423] systemd[1]: Detected architecture arm64.
10878 18:10:32.967757
10879 18:10:32.970992 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10880 18:10:32.971073
10881 18:10:33.001118 <30>[ 8.406210] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10882 18:10:34.086032 <30>[ 9.488771] systemd[1]: Queued start job for default target graphical.target.
10883 18:10:34.127214 <30>[ 9.529630] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10884 18:10:34.133911 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10885 18:10:34.156040 <30>[ 9.558361] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10886 18:10:34.165928 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10887 18:10:34.184263 <30>[ 9.586350] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10888 18:10:34.193681 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10889 18:10:34.211407 <30>[ 9.614035] systemd[1]: Created slice user.slice - User and Session Slice.
10890 18:10:34.217975 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10891 18:10:34.241636 <30>[ 9.640900] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10892 18:10:34.251282 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10893 18:10:34.270000 <30>[ 9.668846] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10894 18:10:34.276306 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10895 18:10:34.304631 <30>[ 9.697252] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10896 18:10:34.314687 <30>[ 9.717151] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10897 18:10:34.321286 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10898 18:10:34.338000 <30>[ 9.740684] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10899 18:10:34.347892 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10900 18:10:34.362313 <30>[ 9.764659] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10901 18:10:34.371907 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10902 18:10:34.386753 <30>[ 9.792715] systemd[1]: Reached target paths.target - Path Units.
10903 18:10:34.397018 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10904 18:10:34.414783 <30>[ 9.817068] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10905 18:10:34.420940 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10906 18:10:34.434679 <30>[ 9.840617] systemd[1]: Reached target slices.target - Slice Units.
10907 18:10:34.444658 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10908 18:10:34.458670 <30>[ 9.864657] systemd[1]: Reached target swap.target - Swaps.
10909 18:10:34.465297 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10910 18:10:34.486659 <30>[ 9.889127] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10911 18:10:34.496619 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10912 18:10:34.514479 <30>[ 9.917100] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10913 18:10:34.524841 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10914 18:10:34.544587 <30>[ 9.947205] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10915 18:10:34.554369 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10916 18:10:34.571603 <30>[ 9.974070] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10917 18:10:34.581130 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10918 18:10:34.598630 <30>[ 10.001255] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10919 18:10:34.605243 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10920 18:10:34.623580 <30>[ 10.026104] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10921 18:10:34.633527 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10922 18:10:34.652828 <30>[ 10.055471] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10923 18:10:34.662629 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10924 18:10:34.679118 <30>[ 10.081793] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10925 18:10:34.688917 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10926 18:10:34.746225 <30>[ 10.148854] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10927 18:10:34.752836 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10928 18:10:34.774952 <30>[ 10.177389] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10929 18:10:34.781358 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10930 18:10:34.807142 <30>[ 10.209462] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10931 18:10:34.813666 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10932 18:10:34.841030 <30>[ 10.236899] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10933 18:10:34.890767 <30>[ 10.293439] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10934 18:10:34.901270 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10935 18:10:34.923733 <30>[ 10.326319] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10936 18:10:34.930729 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10937 18:10:34.955632 <30>[ 10.358174] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10938 18:10:34.962502 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10939 18:10:34.996272 <6>[ 10.398677] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10940 18:10:35.027477 <30>[ 10.429723] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10941 18:10:35.033689 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10942 18:10:35.061828 <30>[ 10.464051] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10943 18:10:35.071308 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10944 18:10:35.138748 <30>[ 10.541338] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10945 18:10:35.145163 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10946 18:10:35.173867 <30>[ 10.576249] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10947 18:10:35.180452 Startin<6>[ 10.586100] fuse: init (API version 7.37)
10948 18:10:35.187151 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10949 18:10:35.212632 <30>[ 10.614495] systemd[1]: Starting systemd-journald.service - Journal Service...
10950 18:10:35.219003 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10951 18:10:35.299163 <30>[ 10.701533] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10952 18:10:35.306108 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10953 18:10:35.339165 <30>[ 10.738041] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10954 18:10:35.345953 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10955 18:10:35.370262 <3>[ 10.772371] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 18:10:35.379984 <30>[ 10.774811] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10957 18:10:35.386794 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10958 18:10:35.401513 <3>[ 10.803311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 18:10:35.414632 <30>[ 10.816797] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10960 18:10:35.420974 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10961 18:10:35.447740 <3>[ 10.849753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 18:10:35.454383 <30>[ 10.851854] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10963 18:10:35.464721 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10964 18:10:35.476673 <3>[ 10.878826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 18:10:35.486704 <30>[ 10.888556] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10966 18:10:35.493265 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10967 18:10:35.506321 <3>[ 10.908505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 18:10:35.518923 <30>[ 10.920884] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10969 18:10:35.525317 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10970 18:10:35.536405 <3>[ 10.938822] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 18:10:35.547964 <30>[ 10.949896] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10972 18:10:35.558100 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10973 18:10:35.568337 <3>[ 10.970826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 18:10:35.579341 <30>[ 10.981726] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10975 18:10:35.586132 <30>[ 10.989851] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10976 18:10:35.599904 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 11.001560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 18:10:35.606534 onfigfs…[0m - Load Kernel Module configfs.
10978 18:10:35.623883 <30>[ 11.025217] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10979 18:10:35.630329 <30>[ 11.033291] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10980 18:10:35.640295 <3>[ 11.034241] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10981 18:10:35.647220 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10982 18:10:35.664626 <30>[ 11.069382] systemd[1]: modprobe@drm.service: Deactivated successfully.
10983 18:10:35.674406 <3>[ 11.071818] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 18:10:35.681319 <30>[ 11.076786] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10985 18:10:35.690805 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10986 18:10:35.705389 <3>[ 11.107278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 18:10:35.715089 <30>[ 11.117223] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10988 18:10:35.725435 <30>[ 11.125517] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10989 18:10:35.735350 [[0;32m OK [0m] Finished [0<3>[ 11.137040] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 18:10:35.741959 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10991 18:10:35.760663 <30>[ 11.162058] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10992 18:10:35.766972 <30>[ 11.169577] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10993 18:10:35.776997 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10994 18:10:35.795219 <30>[ 11.197213] systemd[1]: Started systemd-journald.service - Journal Service.
10995 18:10:35.801600 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10996 18:10:35.824314 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10997 18:10:35.843501 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10998 18:10:35.864030 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10999 18:10:35.884297 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11000 18:10:35.900828 <4>[ 11.295246] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11001 18:10:35.907568 <3>[ 11.310910] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11002 18:10:35.917106 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11003 18:10:35.983060 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11004 18:10:36.007900 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11005 18:10:36.036595 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11006 18:10:36.063268 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11007 18:10:36.099173 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11008 18:10:36.127299 Startin<46>[ 11.530543] systemd-journald[311]: Received client request to flush runtime journal.
11009 18:10:36.134034 g [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11010 18:10:36.178549 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11011 18:10:36.200127 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11012 18:10:36.223083 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11013 18:10:36.247057 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11014 18:10:36.268038 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11015 18:10:36.924506 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11016 18:10:36.972208 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11017 18:10:37.568695 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11018 18:10:37.629379 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11019 18:10:37.646549 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11020 18:10:37.662140 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11021 18:10:37.714804 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11022 18:10:37.740787 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11023 18:10:38.003010 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11024 18:10:38.056144 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11025 18:10:38.131847 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11026 18:10:38.383549 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11027 18:10:38.422762 <6>[ 13.828930] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11028 18:10:38.464806 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11029 18:10:38.498754 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11030 18:10:38.624125 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11031 18:10:38.642337 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11032 18:10:38.659094 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11033 18:10:38.707141 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11034 18:10:38.731870 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11035 18:10:38.807816 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11036 18:10:38.825150 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11037 18:10:38.846692 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11038 18:10:38.895401 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11039 18:10:38.915208 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11040 18:10:38.936171 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11041 18:10:38.958575 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11042 18:10:38.979115 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11043 18:10:39.009401 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11044 18:10:39.029415 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11045 18:10:39.046291 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11046 18:10:39.066263 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11047 18:10:39.086560 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11048 18:10:39.102473 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11049 18:10:39.118335 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11050 18:10:39.137894 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11051 18:10:39.154394 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11052 18:10:39.170476 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11053 18:10:39.216150 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11054 18:10:39.250202 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11055 18:10:39.319458 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11056 18:10:39.344164 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11057 18:10:39.427747 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11058 18:10:39.470708 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11059 18:10:39.499056 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11060 18:10:39.522482 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11061 18:10:39.543446 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11062 18:10:39.700190 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11063 18:10:39.727484 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11064 18:10:39.750118 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11065 18:10:39.767257 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11066 18:10:39.813741 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11067 18:10:39.868290 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11068 18:10:39.958302
11069 18:10:39.961393 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11070 18:10:39.961482
11071 18:10:39.964356 debian-bookworm-arm64 login: root (automatic login)
11072 18:10:39.964436
11073 18:10:40.272017 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11074 18:10:40.272151
11075 18:10:40.278464 The programs included with the Debian GNU/Linux system are free software;
11076 18:10:40.285013 the exact distribution terms for each program are described in the
11077 18:10:40.288741 individual files in /usr/share/doc/*/copyright.
11078 18:10:40.288829
11079 18:10:40.295199 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11080 18:10:40.298880 permitted by applicable law.
11081 18:10:40.385051 Matched prompt #10: / #
11083 18:10:40.385306 Setting prompt string to ['/ #']
11084 18:10:40.385399 end: 2.2.5.1 login-action (duration 00:00:17) [common]
11086 18:10:40.385585 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
11087 18:10:40.385689 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11088 18:10:40.385758 Setting prompt string to ['/ #']
11089 18:10:40.385818 Forcing a shell prompt, looking for ['/ #']
11091 18:10:40.436097 / #
11092 18:10:40.436316 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11093 18:10:40.436439 Waiting using forced prompt support (timeout 00:02:30)
11094 18:10:40.442146
11095 18:10:40.442657 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11096 18:10:40.442864 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11098 18:10:40.543552 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7'
11099 18:10:40.550146 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14291485/extract-nfsrootfs-dho7ccp7'
11101 18:10:40.651922 / # export NFS_SERVER_IP='192.168.201.1'
11102 18:10:40.659223 export NFS_SERVER_IP='192.168.201.1'
11103 18:10:40.660408 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11104 18:10:40.660949 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11105 18:10:40.661417 end: 2 depthcharge-action (duration 00:01:39) [common]
11106 18:10:40.661925 start: 3 lava-test-retry (timeout 00:30:00) [common]
11107 18:10:40.662755 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11108 18:10:40.663206 Using namespace: common
11110 18:10:40.764349 / # #
11111 18:10:40.765077 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11112 18:10:40.770713 #
11113 18:10:40.771445 Using /lava-14291485
11115 18:10:40.872833 / # export SHELL=/bin/sh
11116 18:10:40.879136 export SHELL=/bin/sh
11118 18:10:40.980710 / # . /lava-14291485/environment
11119 18:10:40.986184 . /lava-14291485/environment
11121 18:10:41.093131 / # /lava-14291485/bin/lava-test-runner /lava-14291485/0
11122 18:10:41.093751 Test shell timeout: 10s (minimum of the action and connection timeout)
11123 18:10:41.099337 /lava-14291485/bin/lava-test-runner /lava-14291485/0
11124 18:10:41.374899 + export TESTRUN_ID=0_lc-compliance
11125 18:10:41.380778 + cd /lava-14291485/0/tests/0_lc-compliance
11126 18:10:41.381201 + cat uuid
11127 18:10:41.393294 + UUID=14291485_1.6.2.3.1
11128 18:10:41.393710 + set +x
11129 18:10:41.399886 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14291485_1.6.2.3.1>
11130 18:10:41.400779 Received signal: <STARTRUN> 0_lc-compliance 14291485_1.6.2.3.1
11131 18:10:41.401141 Starting test lava.0_lc-compliance (14291485_1.6.2.3.1)
11132 18:10:41.401538 Skipping test definition patterns.
11133 18:10:41.403031 + /usr/bin/lc-compliance-parser.sh
11134 18:10:43.091772 [0:00:18.378606154] [415] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11135 18:10:43.095080 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11136 18:10:43.110970 [0:00:18.398449846] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 18:10:43.165746 [0:00:18.453213154] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11138 18:10:43.184838 [==========] Running 120 tests from 1 test suite.
11139 18:10:43.219111 [0:00:18.506720923] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 18:10:43.272239 [0:00:18.559650769] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 18:10:43.275532 [----------] Global test environment set-up.
11142 18:10:43.367808 [----------] 120 tests from CaptureTests/SingleStream
11143 18:10:43.463643 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11144 18:10:43.537795 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11145 18:10:43.538680 Received signal: <TESTSET> START CaptureTests/SingleStream
11146 18:10:43.539048 Starting test_set CaptureTests/SingleStream
11147 18:10:43.541006 Camera needs 4 requests, can't test only 1
11148 18:10:43.632101 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11149 18:10:43.700865 [0:00:18.988121461] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 18:10:43.725002
11151 18:10:43.827278 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (56 ms)
11152 18:10:43.958235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11153 18:10:43.959045 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11155 18:10:43.983894 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11156 18:10:44.051591 Camera needs 4 requests, can't test only 2
11157 18:10:44.142189 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11158 18:10:44.221607
11159 18:10:44.318773 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)
11160 18:10:44.395896 [0:00:19.683604923] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 18:10:44.445638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11162 18:10:44.446394 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11164 18:10:44.463749 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11165 18:10:44.529127 Camera needs 4 requests, can't test only 3
11166 18:10:44.624368 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11167 18:10:44.713396
11168 18:10:44.805441 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (53 ms)
11169 18:10:44.915194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11170 18:10:44.915941 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11172 18:10:44.934436 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11173 18:10:44.994741 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (427 ms)
11174 18:10:45.097502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11175 18:10:45.097957 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11177 18:10:45.114463 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11178 18:10:45.177240 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (694 ms)
11179 18:10:45.286540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11180 18:10:45.286986 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11182 18:10:45.303120 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11183 18:10:45.643207 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1256 ms)
11184 18:10:45.653133 [0:00:20.940791538] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11185 18:10:45.755473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11186 18:10:45.756216 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11188 18:10:45.773062 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11189 18:10:47.460802 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1817 ms)
11190 18:10:47.470156 [0:00:22.757231077] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 18:10:47.570816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11192 18:10:47.571306 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11194 18:10:47.590068 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11195 18:10:50.185653 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2725 ms)
11196 18:10:50.196144 [0:00:25.484059462] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11197 18:10:50.306456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11198 18:10:50.307246 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11200 18:10:50.326074 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11201 18:10:54.383969 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4198 ms)
11202 18:10:54.393496 [0:00:29.682138308] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11203 18:10:54.507708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11204 18:10:54.508103 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11206 18:10:54.526599 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11207 18:11:00.505016 <6>[ 35.916592] vpu: disabling
11208 18:11:00.508288 <6>[ 35.919697] vproc2: disabling
11209 18:11:00.511941 <6>[ 35.923374] vproc1: disabling
11210 18:11:00.515854 <6>[ 35.927345] vaud18: disabling
11211 18:11:00.523204 <6>[ 35.931250] vsram_others: disabling
11212 18:11:00.526432 <6>[ 35.935414] va09: disabling
11213 18:11:00.529528 <6>[ 35.938801] vsram_md: disabling
11214 18:11:00.532627 <6>[ 35.942540] Vgpu: disabling
11215 18:11:00.961471 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6578 ms)
11216 18:11:00.971386 [0:00:36.260472924] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11217 18:11:01.027327 [0:00:36.316798539] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 18:11:01.082265 [0:00:36.371870386] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11219 18:11:01.091767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11220 18:11:01.092462 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11222 18:11:01.111731 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11223 18:11:01.138527 [0:00:36.427773001] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11224 18:11:01.180769 Camera needs 4 requests, can't test only 1
11225 18:11:01.272504 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11226 18:11:01.364010
11227 18:11:01.465991 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (56 ms)
11228 18:11:01.584474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11229 18:11:01.585190 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11231 18:11:01.607293 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11232 18:11:01.670900 Camera needs 4 requests, can't test only 2
11233 18:11:01.763109 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11234 18:11:01.836555 [0:00:37.125977386] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 18:11:01.857411
11236 18:11:01.956522 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11237 18:11:02.073366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11238 18:11:02.074104 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11240 18:11:02.096812 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11241 18:11:02.161371 Camera needs 4 requests, can't test only 3
11242 18:11:02.255464 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11243 18:11:02.349039
11244 18:11:02.453723 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
11245 18:11:02.569267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11246 18:11:02.570011 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11248 18:11:02.590907 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11249 18:11:02.654404 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (697 ms)
11250 18:11:02.741525 [0:00:38.031529309] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11251 18:11:02.773160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11252 18:11:02.773436 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11254 18:11:02.791951 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11255 18:11:02.851597 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (906 ms)
11256 18:11:02.962018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11257 18:11:02.962332 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11259 18:11:02.981872 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11260 18:11:03.988152 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1253 ms)
11261 18:11:04.001008 [0:00:39.287453155] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 18:11:04.116046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11263 18:11:04.116946 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11265 18:11:04.135453 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11266 18:11:05.806325 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1818 ms)
11267 18:11:05.819171 [0:00:41.105948463] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11268 18:11:05.902648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11269 18:11:05.902965 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11271 18:11:05.918473 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11272 18:11:08.535611 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2728 ms)
11273 18:11:08.548521 [0:00:43.835375463] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11274 18:11:08.655881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11275 18:11:08.656598 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11277 18:11:08.677844 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11278 18:11:12.733468 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4198 ms)
11279 18:11:12.745989 [0:00:48.033360771] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11280 18:11:12.868611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11281 18:11:12.869331 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11283 18:11:12.886773 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11284 18:11:19.311229 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6578 ms)
11285 18:11:19.324033 [0:00:54.612127233] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11286 18:11:19.376981 [0:00:54.668417541] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 18:11:19.432307 [0:00:54.723905541] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 18:11:19.445378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11289 18:11:19.446051 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11291 18:11:19.465311 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11292 18:11:19.487879 [0:00:54.779449156] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11293 18:11:19.532346 Camera needs 4 requests, can't test only 1
11294 18:11:19.618712 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11295 18:11:19.710487
11296 18:11:19.809603 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (56 ms)
11297 18:11:19.922244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11298 18:11:19.922983 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11300 18:11:19.940199 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11301 18:11:20.002050 Camera needs 4 requests, can't test only 2
11302 18:11:20.101929 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11303 18:11:20.183322 [0:00:55.474948694] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 18:11:20.183452
11305 18:11:20.264400 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11306 18:11:20.369379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11307 18:11:20.369749 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11309 18:11:20.390370 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11310 18:11:20.453860 Camera needs 4 requests, can't test only 3
11311 18:11:20.544034 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 18:11:20.626725
11313 18:11:20.723302 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11314 18:11:20.832033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11315 18:11:20.832380 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11317 18:11:20.849780 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11318 18:11:20.902126 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (696 ms)
11319 18:11:21.000007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11320 18:11:21.000384 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11322 18:11:21.015756 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11323 18:11:21.079785 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (905 ms)
11324 18:11:21.093060 [0:00:56.381522079] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11325 18:11:21.179939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11326 18:11:21.180300 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11328 18:11:21.196622 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11329 18:11:22.340674 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1257 ms)
11330 18:11:22.350728 [0:00:57.639548464] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 18:11:22.439883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11332 18:11:22.440206 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11334 18:11:22.457648 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11335 18:11:24.154948 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1817 ms)
11336 18:11:24.168309 [0:00:59.457387618] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11337 18:11:24.258561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11338 18:11:24.258876 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11340 18:11:24.275482 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11341 18:11:26.884917 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2729 ms)
11342 18:11:26.897736 [0:01:02.187130310] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11343 18:11:26.991082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11344 18:11:26.991400 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11346 18:11:27.009650 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11347 18:11:31.082012 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4197 ms)
11348 18:11:31.095055 [0:01:06.385020003] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11349 18:11:31.183807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11350 18:11:31.184125 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11352 18:11:31.201998 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11353 18:11:37.660681 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6578 ms)
11354 18:11:37.674092 [0:01:12.963942465] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11355 18:11:37.726885 [0:01:13.020195003] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 18:11:37.782340 [0:01:13.075648465] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 18:11:37.788920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11358 18:11:37.789743 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11360 18:11:37.807710 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11361 18:11:37.837385 [0:01:13.131051234] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11362 18:11:37.872346 Camera needs 4 requests, can't test only 1
11363 18:11:37.970832 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11364 18:11:38.064839
11365 18:11:38.163407 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11366 18:11:38.284425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11367 18:11:38.285224 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11369 18:11:38.306892 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11370 18:11:38.374717 Camera needs 4 requests, can't test only 2
11371 18:11:38.469896 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11372 18:11:38.532232 [0:01:13.826343003] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 18:11:38.554734
11374 18:11:38.644688 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (55 ms)
11375 18:11:38.759150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11376 18:11:38.759447 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11378 18:11:38.779653 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11379 18:11:38.839300 Camera needs 4 requests, can't test only 3
11380 18:11:38.934059 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11381 18:11:39.018388
11382 18:11:39.122804 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (56 ms)
11383 18:11:39.232188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11384 18:11:39.232643 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11386 18:11:39.249494 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11387 18:11:39.313939 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (694 ms)
11388 18:11:39.424838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11389 18:11:39.425578 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11391 18:11:39.438877 [0:01:14.732192388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11392 18:11:39.448149 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11393 18:11:39.516094 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (905 ms)
11394 18:11:39.623401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11395 18:11:39.623785 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11397 18:11:39.642884 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11398 18:11:40.686236 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1256 ms)
11399 18:11:40.699046 [0:01:15.989720388] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 18:11:40.804309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11401 18:11:40.805003 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11403 18:11:40.823944 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11404 18:11:42.504221 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1818 ms)
11405 18:11:42.517146 [0:01:17.807799542] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 18:11:42.627512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11407 18:11:42.628236 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11409 18:11:42.646524 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11410 18:11:45.232051 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2728 ms)
11411 18:11:45.244773 [0:01:20.536132619] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 18:11:45.354918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11413 18:11:45.355658 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11415 18:11:45.375859 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11416 18:11:49.430104 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4198 ms)
11417 18:11:49.443130 [0:01:24.734966542] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 18:11:49.553385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11419 18:11:49.554131 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11421 18:11:49.575274 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11422 18:11:56.007980 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6578 ms)
11423 18:11:56.021131 [0:01:31.313132773] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 18:11:56.073086 [0:01:31.368804389] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 18:11:56.129061 [0:01:31.424735697] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 18:11:56.135550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11427 18:11:56.136336 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11429 18:11:56.148667 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11430 18:11:56.184527 [0:01:31.480060235] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11431 18:11:56.212854 Camera needs 4 requests, can't test only 1
11432 18:11:56.307716 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11433 18:11:56.400225
11434 18:11:56.499188 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11435 18:11:56.610860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11436 18:11:56.611622 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11438 18:11:56.630053 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11439 18:11:56.686119 Camera needs 4 requests, can't test only 2
11440 18:11:56.776526 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11441 18:11:56.855775
11442 18:11:56.945908 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (55 ms)
11443 18:11:57.040274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11444 18:11:57.040586 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11446 18:11:57.054695 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11447 18:11:57.108478 Camera needs 4 requests, can't test only 3
11448 18:11:57.194514 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11449 18:11:57.274379
11450 18:11:57.362473 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (55 ms)
11451 18:11:57.456753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11452 18:11:57.457056 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11454 18:11:57.472712 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11455 18:11:58.255159 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2079 ms)
11456 18:11:58.268232 [0:01:33.560980543] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 18:11:58.373297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11458 18:11:58.374098 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11460 18:11:58.391778 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11461 18:12:00.972463 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2717 ms)
11462 18:12:00.985278 [0:01:36.277979312] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11463 18:12:01.091449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11464 18:12:01.092411 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11466 18:12:01.110553 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11467 18:12:04.734220 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3761 ms)
11468 18:12:04.746597 [0:01:40.040453159] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 18:12:04.844574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11470 18:12:04.844886 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11472 18:12:04.863201 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11473 18:12:10.174758 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5441 ms)
11474 18:12:10.187408 [0:01:45.481789236] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11475 18:12:10.296195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11476 18:12:10.297008 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11478 18:12:10.315366 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11479 18:12:18.349284 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8175 ms)
11480 18:12:18.362360 [0:01:53.657390621] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11481 18:12:18.483824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11482 18:12:18.484568 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11484 18:12:18.504364 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11485 18:12:30.930937 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12583 ms)
11486 18:12:30.944380 [0:02:06.240454929] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11487 18:12:31.055192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11488 18:12:31.056104 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11490 18:12:31.075232 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11491 18:12:50.654076 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19725 ms)
11492 18:12:50.667456 [0:02:25.965657238] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11493 18:12:50.719571 [0:02:26.021344469] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 18:12:50.776016 [0:02:26.078211315] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 18:12:50.782712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11496 18:12:50.783008 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11498 18:12:50.794148 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11499 18:12:50.833051 [0:02:26.135004238] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 18:12:50.854871 Camera needs 4 requests, can't test only 1
11501 18:12:50.937063 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11502 18:12:51.022513
11503 18:12:51.117236 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (56 ms)
11504 18:12:51.226133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11505 18:12:51.226969 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11507 18:12:51.240671 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11508 18:12:51.302081 Camera needs 4 requests, can't test only 2
11509 18:12:51.387207 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11510 18:12:51.473394
11511 18:12:51.577573 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11512 18:12:51.673426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11513 18:12:51.673739 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11515 18:12:51.685426 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11516 18:12:51.740259 Camera needs 4 requests, can't test only 3
11517 18:12:51.809990 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11518 18:12:51.883403
11519 18:12:51.973484 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)
11520 18:12:52.067389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11521 18:12:52.067732 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11523 18:12:52.082106 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11524 18:12:52.907752 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2080 ms)
11525 18:12:52.917838 [0:02:28.216483931] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 18:12:53.022569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11527 18:12:53.022892 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11529 18:12:53.036252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11530 18:12:55.620316 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2712 ms)
11531 18:12:55.630412 [0:02:30.929165546] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11532 18:12:55.739110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11533 18:12:55.739990 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11535 18:12:55.753996 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11536 18:12:59.381242 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3760 ms)
11537 18:12:59.390906 [0:02:34.690093623] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 18:12:59.503374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11539 18:12:59.504104 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11541 18:12:59.518898 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11542 18:13:04.822253 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5442 ms)
11543 18:13:04.832228 [0:02:40.132043470] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 18:13:04.939119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11545 18:13:04.939859 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11547 18:13:04.954970 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11548 18:13:12.996164 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8174 ms)
11549 18:13:13.005946 [0:02:48.306603547] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 18:13:13.118271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11551 18:13:13.119031 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11553 18:13:13.134687 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11554 18:13:25.577332 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12582 ms)
11555 18:13:25.587109 [0:03:00.889522163] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 18:13:25.692216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11557 18:13:25.693086 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11559 18:13:25.706283 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11560 18:13:45.299817 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19724 ms)
11561 18:13:45.309686 [0:03:20.613989780] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 18:13:45.362531 [0:03:20.670289626] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 18:13:45.417589 [0:03:20.725740011] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 18:13:45.424156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11565 18:13:45.424831 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11567 18:13:45.441921 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11568 18:13:45.475462 [0:03:20.783254242] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 18:13:45.513190 Camera needs 4 requests, can't test only 1
11570 18:13:45.601303 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11571 18:13:45.696037
11572 18:13:45.797420 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11573 18:13:45.909148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11574 18:13:45.909914 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11576 18:13:45.924929 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11577 18:13:45.989953 Camera needs 4 requests, can't test only 2
11578 18:13:46.083352 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11579 18:13:46.170411
11580 18:13:46.271832 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11581 18:13:46.381320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11582 18:13:46.382123 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11584 18:13:46.398685 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11585 18:13:46.463283 Camera needs 4 requests, can't test only 3
11586 18:13:46.561899 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11587 18:13:46.658139
11588 18:13:46.763375 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (56 ms)
11589 18:13:46.881645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11590 18:13:46.882375 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11592 18:13:46.897689 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11593 18:13:47.550504 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2081 ms)
11594 18:13:47.559831 [0:03:22.865017626] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11595 18:13:47.663835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11596 18:13:47.664554 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11598 18:13:47.678368 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11599 18:13:50.262220 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2712 ms)
11600 18:13:50.272154 [0:03:25.577524165] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11601 18:13:50.384888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11602 18:13:50.385199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11604 18:13:50.400537 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11605 18:13:54.024550 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3762 ms)
11606 18:13:54.034199 [0:03:29.339587934] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11607 18:13:54.149917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11608 18:13:54.150692 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11610 18:13:54.167560 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11611 18:13:59.464961 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5441 ms)
11612 18:13:59.474512 [0:03:34.781093550] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11613 18:13:59.584447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11614 18:13:59.584861 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11616 18:13:59.602841 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11617 18:14:07.639250 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8175 ms)
11618 18:14:07.649230 [0:03:42.956229627] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11619 18:14:07.760010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11620 18:14:07.760808 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11622 18:14:07.776176 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11623 18:14:20.221884 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12583 ms)
11624 18:14:20.232071 [0:03:55.540338551] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11625 18:14:20.337276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11626 18:14:20.337857 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11628 18:14:20.352068 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11629 18:14:39.944314 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19724 ms)
11630 18:14:39.954137 [0:04:15.264373552] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11631 18:14:40.007214 [0:04:15.320964399] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11632 18:14:40.062816 [0:04:15.377085322] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 18:14:40.080382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11634 18:14:40.081153 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11636 18:14:40.096721 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11637 18:14:40.116664 [0:04:15.430796783] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11638 18:14:40.166578 Camera needs 4 requests, can't test only 1
11639 18:14:40.264982 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11640 18:14:40.354255
11641 18:14:40.455173 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11642 18:14:40.564195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11643 18:14:40.564917 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11645 18:14:40.581398 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11646 18:14:40.647107 Camera needs 4 requests, can't test only 2
11647 18:14:40.746296 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11648 18:14:40.838881
11649 18:14:40.935270 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (56 ms)
11650 18:14:41.048416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11651 18:14:41.049153 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11653 18:14:41.064895 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11654 18:14:41.131291 Camera needs 4 requests, can't test only 3
11655 18:14:41.218668 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11656 18:14:41.311105
11657 18:14:41.413995 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (54 ms)
11658 18:14:41.526461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11659 18:14:41.527184 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11661 18:14:41.541666 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11662 18:14:42.191963 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2079 ms)
11663 18:14:42.201228 [0:04:17.511613476] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11664 18:14:42.310354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11665 18:14:42.311060 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11667 18:14:42.329276 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11668 18:14:44.903000 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2711 ms)
11669 18:14:44.913141 [0:04:20.224928630] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11670 18:14:45.023381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11671 18:14:45.024093 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11673 18:14:45.039411 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11674 18:14:48.665318 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3762 ms)
11675 18:14:48.675300 [0:04:23.987898707] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11676 18:14:48.784024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11677 18:14:48.784743 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11679 18:14:48.800491 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11680 18:14:54.107816 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5443 ms)
11681 18:14:54.117642 [0:04:29.431465323] [415] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11682 18:14:54.225042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11683 18:14:54.225752 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11685 18:14:54.240254 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11686 18:40:40.662965 Marking unfinished test run as failed
11689 18:40:40.664553 end: 3.1 lava-test-shell (duration 00:30:00) [common]
11691 18:40:40.665474 lava-test-retry failed: 1 of 1 attempts. 'lava-test-shell timed out after 1800 seconds'
11693 18:40:40.666276 end: 3 lava-test-retry (duration 00:30:00) [common]
11695 18:40:40.667368 Cleaning after the job
11696 18:40:40.667850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/ramdisk
11697 18:40:40.677556 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/kernel
11698 18:40:40.711411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/dtb
11699 18:40:40.711750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/nfsrootfs
11700 18:40:40.757714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291485/tftp-deploy-kh0bjebm/modules
11701 18:40:40.763316 start: 4.1 power-off (timeout 00:00:30) [common]
11702 18:40:40.763480 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11703 18:40:40.982427 >> Command sent successfully.
11704 18:40:40.994577 Returned 0 in 0 seconds
11705 18:40:41.096228 end: 4.1 power-off (duration 00:00:00) [common]
11707 18:40:41.097892 start: 4.2 read-feedback (timeout 00:10:00) [common]
11708 18:40:41.099485 Listened to connection for namespace 'common' for up to 1s
11709 18:40:42.099718 Finalising connection for namespace 'common'
11710 18:40:42.100663 Disconnecting from shell: Finalise
11711 18:40:42.201817 end: 4.2 read-feedback (duration 00:00:01) [common]
11712 18:40:42.202606 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291485
11713 18:40:42.460030 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291485
11714 18:40:42.460229 TestError: A test failed to run, look at the error message.