Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 20
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 18:11:02.941794 lava-dispatcher, installed at version: 2024.03
2 18:11:02.942003 start: 0 validate
3 18:11:02.942162 Start time: 2024-06-11 18:11:02.942153+00:00 (UTC)
4 18:11:02.942326 Using caching service: 'http://localhost/cache/?uri=%s'
5 18:11:02.942509 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 18:11:03.223052 Using caching service: 'http://localhost/cache/?uri=%s'
7 18:11:03.223276 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 18:11:03.489075 Using caching service: 'http://localhost/cache/?uri=%s'
9 18:11:03.489255 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 18:11:03.754181 Using caching service: 'http://localhost/cache/?uri=%s'
11 18:11:03.754363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-17-g24b63cdc814f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 18:11:04.022442 validate duration: 1.08
14 18:11:04.022744 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:11:04.022855 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:11:04.022964 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:11:04.023087 Not decompressing ramdisk as can be used compressed.
18 18:11:04.023192 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 18:11:04.023279 saving as /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/ramdisk/rootfs.cpio.gz
20 18:11:04.023357 total size: 28105535 (26 MB)
21 18:11:04.024433 progress 0 % (0 MB)
22 18:11:04.032142 progress 5 % (1 MB)
23 18:11:04.039781 progress 10 % (2 MB)
24 18:11:04.047513 progress 15 % (4 MB)
25 18:11:04.055273 progress 20 % (5 MB)
26 18:11:04.062945 progress 25 % (6 MB)
27 18:11:04.070587 progress 30 % (8 MB)
28 18:11:04.078323 progress 35 % (9 MB)
29 18:11:04.086102 progress 40 % (10 MB)
30 18:11:04.093663 progress 45 % (12 MB)
31 18:11:04.101314 progress 50 % (13 MB)
32 18:11:04.109027 progress 55 % (14 MB)
33 18:11:04.116647 progress 60 % (16 MB)
34 18:11:04.124226 progress 65 % (17 MB)
35 18:11:04.131925 progress 70 % (18 MB)
36 18:11:04.139647 progress 75 % (20 MB)
37 18:11:04.147317 progress 80 % (21 MB)
38 18:11:04.155035 progress 85 % (22 MB)
39 18:11:04.162186 progress 90 % (24 MB)
40 18:11:04.169520 progress 95 % (25 MB)
41 18:11:04.177104 progress 100 % (26 MB)
42 18:11:04.177346 26 MB downloaded in 0.15 s (174.06 MB/s)
43 18:11:04.177557 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:11:04.177833 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:11:04.177934 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:11:04.178024 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:11:04.178164 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 18:11:04.178239 saving as /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/kernel/Image
50 18:11:04.178302 total size: 54813184 (52 MB)
51 18:11:04.178364 No compression specified
52 18:11:04.179547 progress 0 % (0 MB)
53 18:11:04.194588 progress 5 % (2 MB)
54 18:11:04.209721 progress 10 % (5 MB)
55 18:11:04.224476 progress 15 % (7 MB)
56 18:11:04.239347 progress 20 % (10 MB)
57 18:11:04.254295 progress 25 % (13 MB)
58 18:11:04.268994 progress 30 % (15 MB)
59 18:11:04.284057 progress 35 % (18 MB)
60 18:11:04.299075 progress 40 % (20 MB)
61 18:11:04.313942 progress 45 % (23 MB)
62 18:11:04.328995 progress 50 % (26 MB)
63 18:11:04.344012 progress 55 % (28 MB)
64 18:11:04.358689 progress 60 % (31 MB)
65 18:11:04.373723 progress 65 % (34 MB)
66 18:11:04.388652 progress 70 % (36 MB)
67 18:11:04.403559 progress 75 % (39 MB)
68 18:11:04.418589 progress 80 % (41 MB)
69 18:11:04.433199 progress 85 % (44 MB)
70 18:11:04.448151 progress 90 % (47 MB)
71 18:11:04.462670 progress 95 % (49 MB)
72 18:11:04.477425 progress 100 % (52 MB)
73 18:11:04.477693 52 MB downloaded in 0.30 s (174.60 MB/s)
74 18:11:04.477900 end: 1.2.1 http-download (duration 00:00:00) [common]
76 18:11:04.478286 end: 1.2 download-retry (duration 00:00:00) [common]
77 18:11:04.478404 start: 1.3 download-retry (timeout 00:10:00) [common]
78 18:11:04.478526 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 18:11:04.478693 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 18:11:04.478804 saving as /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/dtb/mt8192-asurada-spherion-r0.dtb
81 18:11:04.478906 total size: 47258 (0 MB)
82 18:11:04.479007 No compression specified
83 18:11:04.480816 progress 69 % (0 MB)
84 18:11:04.481136 progress 100 % (0 MB)
85 18:11:04.481360 0 MB downloaded in 0.00 s (18.39 MB/s)
86 18:11:04.481544 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:11:04.481938 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:11:04.482064 start: 1.4 download-retry (timeout 00:10:00) [common]
90 18:11:04.482189 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 18:11:04.482343 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-17-g24b63cdc814f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 18:11:04.482446 saving as /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/modules/modules.tar
93 18:11:04.482547 total size: 8618176 (8 MB)
94 18:11:04.482646 Using unxz to decompress xz
95 18:11:04.487303 progress 0 % (0 MB)
96 18:11:04.506246 progress 5 % (0 MB)
97 18:11:04.534086 progress 10 % (0 MB)
98 18:11:04.564186 progress 15 % (1 MB)
99 18:11:04.588406 progress 20 % (1 MB)
100 18:11:04.611861 progress 25 % (2 MB)
101 18:11:04.635455 progress 30 % (2 MB)
102 18:11:04.662463 progress 35 % (2 MB)
103 18:11:04.687742 progress 40 % (3 MB)
104 18:11:04.710933 progress 45 % (3 MB)
105 18:11:04.735054 progress 50 % (4 MB)
106 18:11:04.760997 progress 55 % (4 MB)
107 18:11:04.785845 progress 60 % (4 MB)
108 18:11:04.810280 progress 65 % (5 MB)
109 18:11:04.837069 progress 70 % (5 MB)
110 18:11:04.860846 progress 75 % (6 MB)
111 18:11:04.887112 progress 80 % (6 MB)
112 18:11:04.911645 progress 85 % (7 MB)
113 18:11:04.937204 progress 90 % (7 MB)
114 18:11:04.962759 progress 95 % (7 MB)
115 18:11:04.989742 progress 100 % (8 MB)
116 18:11:04.994209 8 MB downloaded in 0.51 s (16.06 MB/s)
117 18:11:04.994447 end: 1.4.1 http-download (duration 00:00:01) [common]
119 18:11:04.994704 end: 1.4 download-retry (duration 00:00:01) [common]
120 18:11:04.994801 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 18:11:04.994897 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 18:11:04.994979 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:11:04.995068 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 18:11:04.995287 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs
125 18:11:04.995414 makedir: /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin
126 18:11:04.995517 makedir: /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/tests
127 18:11:04.995612 makedir: /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/results
128 18:11:04.995727 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-add-keys
129 18:11:04.995869 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-add-sources
130 18:11:04.995996 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-background-process-start
131 18:11:04.996120 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-background-process-stop
132 18:11:04.996241 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-common-functions
133 18:11:04.996361 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-echo-ipv4
134 18:11:04.996482 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-install-packages
135 18:11:04.996641 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-installed-packages
136 18:11:04.996761 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-os-build
137 18:11:04.996882 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-probe-channel
138 18:11:04.997004 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-probe-ip
139 18:11:04.997124 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-target-ip
140 18:11:04.997243 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-target-mac
141 18:11:04.997361 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-target-storage
142 18:11:04.997485 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-case
143 18:11:04.997605 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-event
144 18:11:04.997741 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-feedback
145 18:11:04.997862 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-raise
146 18:11:04.997981 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-reference
147 18:11:04.998101 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-runner
148 18:11:04.998221 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-set
149 18:11:04.998342 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-test-shell
150 18:11:04.998465 Updating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-install-packages (oe)
151 18:11:04.998612 Updating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/bin/lava-installed-packages (oe)
152 18:11:04.998738 Creating /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/environment
153 18:11:04.998836 LAVA metadata
154 18:11:04.998916 - LAVA_JOB_ID=14291494
155 18:11:04.998982 - LAVA_DISPATCHER_IP=192.168.201.1
156 18:11:04.999083 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 18:11:04.999154 skipped lava-vland-overlay
158 18:11:04.999229 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 18:11:04.999313 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 18:11:04.999385 skipped lava-multinode-overlay
161 18:11:04.999459 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 18:11:04.999542 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 18:11:04.999616 Loading test definitions
164 18:11:04.999734 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 18:11:04.999829 Using /lava-14291494 at stage 0
166 18:11:05.000136 uuid=14291494_1.5.2.3.1 testdef=None
167 18:11:05.000226 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 18:11:05.000312 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 18:11:05.000853 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 18:11:05.001079 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 18:11:05.001688 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 18:11:05.001918 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 18:11:05.002493 runner path: /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 14291494_1.5.2.3.1
176 18:11:05.002646 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 18:11:05.002855 Creating lava-test-runner.conf files
179 18:11:05.002920 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14291494/lava-overlay-juqjsigs/lava-14291494/0 for stage 0
180 18:11:05.003009 - 0_v4l2-compliance-mtk-vcodec-enc
181 18:11:05.003105 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 18:11:05.003192 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 18:11:05.010317 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 18:11:05.010425 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 18:11:05.010512 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 18:11:05.010596 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 18:11:05.010685 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 18:11:05.877536 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 18:11:05.877918 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 18:11:05.878030 extracting modules file /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14291494/extract-overlay-ramdisk-uadu4900/ramdisk
191 18:11:06.087649 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 18:11:06.087814 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 18:11:06.087908 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291494/compress-overlay-h65qfs01/overlay-1.5.2.4.tar.gz to ramdisk
194 18:11:06.087981 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14291494/compress-overlay-h65qfs01/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14291494/extract-overlay-ramdisk-uadu4900/ramdisk
195 18:11:06.094316 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 18:11:06.094425 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 18:11:06.094516 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 18:11:06.094607 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 18:11:06.094684 Building ramdisk /var/lib/lava/dispatcher/tmp/14291494/extract-overlay-ramdisk-uadu4900/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14291494/extract-overlay-ramdisk-uadu4900/ramdisk
200 18:11:06.778671 >> 275947 blocks
201 18:11:10.835884 rename /var/lib/lava/dispatcher/tmp/14291494/extract-overlay-ramdisk-uadu4900/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/ramdisk/ramdisk.cpio.gz
202 18:11:10.836282 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 18:11:10.836402 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 18:11:10.836506 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 18:11:10.836681 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/kernel/Image']
206 18:11:23.758318 Returned 0 in 12 seconds
207 18:11:23.858929 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/kernel/image.itb
208 18:11:24.449690 output: FIT description: Kernel Image image with one or more FDT blobs
209 18:11:24.450035 output: Created: Tue Jun 11 19:11:24 2024
210 18:11:24.450108 output: Image 0 (kernel-1)
211 18:11:24.450173 output: Description:
212 18:11:24.450238 output: Created: Tue Jun 11 19:11:24 2024
213 18:11:24.450298 output: Type: Kernel Image
214 18:11:24.450356 output: Compression: lzma compressed
215 18:11:24.450416 output: Data Size: 13125101 Bytes = 12817.48 KiB = 12.52 MiB
216 18:11:24.450474 output: Architecture: AArch64
217 18:11:24.450533 output: OS: Linux
218 18:11:24.450592 output: Load Address: 0x00000000
219 18:11:24.450654 output: Entry Point: 0x00000000
220 18:11:24.450715 output: Hash algo: crc32
221 18:11:24.450773 output: Hash value: 7a9e9d3e
222 18:11:24.450830 output: Image 1 (fdt-1)
223 18:11:24.450888 output: Description: mt8192-asurada-spherion-r0
224 18:11:24.450945 output: Created: Tue Jun 11 19:11:24 2024
225 18:11:24.450999 output: Type: Flat Device Tree
226 18:11:24.451053 output: Compression: uncompressed
227 18:11:24.451106 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 18:11:24.451160 output: Architecture: AArch64
229 18:11:24.451213 output: Hash algo: crc32
230 18:11:24.451265 output: Hash value: 0f8e4d2e
231 18:11:24.451318 output: Image 2 (ramdisk-1)
232 18:11:24.451372 output: Description: unavailable
233 18:11:24.451425 output: Created: Tue Jun 11 19:11:24 2024
234 18:11:24.451478 output: Type: RAMDisk Image
235 18:11:24.451532 output: Compression: Unknown Compression
236 18:11:24.451585 output: Data Size: 41215902 Bytes = 40249.90 KiB = 39.31 MiB
237 18:11:24.451638 output: Architecture: AArch64
238 18:11:24.451697 output: OS: Linux
239 18:11:24.451755 output: Load Address: unavailable
240 18:11:24.451809 output: Entry Point: unavailable
241 18:11:24.451862 output: Hash algo: crc32
242 18:11:24.451916 output: Hash value: e5315210
243 18:11:24.451969 output: Default Configuration: 'conf-1'
244 18:11:24.452022 output: Configuration 0 (conf-1)
245 18:11:24.452075 output: Description: mt8192-asurada-spherion-r0
246 18:11:24.452129 output: Kernel: kernel-1
247 18:11:24.452182 output: Init Ramdisk: ramdisk-1
248 18:11:24.452235 output: FDT: fdt-1
249 18:11:24.452288 output: Loadables: kernel-1
250 18:11:24.452340 output:
251 18:11:24.452555 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 18:11:24.452689 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 18:11:24.452796 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 18:11:24.452889 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 18:11:24.452972 No LXC device requested
256 18:11:24.453051 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 18:11:24.453136 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 18:11:24.453214 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 18:11:24.453285 Checking files for TFTP limit of 4294967296 bytes.
260 18:11:24.453772 end: 1 tftp-deploy (duration 00:00:20) [common]
261 18:11:24.453871 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 18:11:24.453965 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 18:11:24.454083 substitutions:
264 18:11:24.454150 - {DTB}: 14291494/tftp-deploy-_xa68jvm/dtb/mt8192-asurada-spherion-r0.dtb
265 18:11:24.454214 - {INITRD}: 14291494/tftp-deploy-_xa68jvm/ramdisk/ramdisk.cpio.gz
266 18:11:24.454275 - {KERNEL}: 14291494/tftp-deploy-_xa68jvm/kernel/Image
267 18:11:24.454334 - {LAVA_MAC}: None
268 18:11:24.454391 - {PRESEED_CONFIG}: None
269 18:11:24.454447 - {PRESEED_LOCAL}: None
270 18:11:24.454503 - {RAMDISK}: 14291494/tftp-deploy-_xa68jvm/ramdisk/ramdisk.cpio.gz
271 18:11:24.454559 - {ROOT_PART}: None
272 18:11:24.454614 - {ROOT}: None
273 18:11:24.454669 - {SERVER_IP}: 192.168.201.1
274 18:11:24.454723 - {TEE}: None
275 18:11:24.454779 Parsed boot commands:
276 18:11:24.454834 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 18:11:24.455002 Parsed boot commands: tftpboot 192.168.201.1 14291494/tftp-deploy-_xa68jvm/kernel/image.itb 14291494/tftp-deploy-_xa68jvm/kernel/cmdline
278 18:11:24.455090 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 18:11:24.455176 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 18:11:24.455267 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 18:11:24.455354 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 18:11:24.455427 Not connected, no need to disconnect.
283 18:11:24.455501 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 18:11:24.455580 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 18:11:24.455656 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 18:11:24.458905 Setting prompt string to ['lava-test: # ']
287 18:11:24.459234 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 18:11:24.459338 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 18:11:24.459442 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 18:11:24.459565 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 18:11:24.459737 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
292 18:11:38.072462 Returned 0 in 13 seconds
293 18:11:38.173821 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 18:11:38.175344 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 18:11:38.175906 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 18:11:38.176374 Setting prompt string to 'Starting depthcharge on Spherion...'
298 18:11:38.176795 Changing prompt to 'Starting depthcharge on Spherion...'
299 18:11:38.177176 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 18:11:38.179202 [Enter `^Ec?' for help]
301 18:11:38.179678
302 18:11:38.180021
303 18:11:38.180460 F0: 102B 0000
304 18:11:38.180865
305 18:11:38.181185 F3: 1001 0000 [0200]
306 18:11:38.181495
307 18:11:38.181805 F3: 1001 0000
308 18:11:38.182099
309 18:11:38.182382 F7: 102D 0000
310 18:11:38.182668
311 18:11:38.182952 F1: 0000 0000
312 18:11:38.183237
313 18:11:38.183515 V0: 0000 0000 [0001]
314 18:11:38.183798
315 18:11:38.184100 00: 0007 8000
316 18:11:38.184408
317 18:11:38.184716 01: 0000 0000
318 18:11:38.185010
319 18:11:38.185289 BP: 0C00 0209 [0000]
320 18:11:38.185571
321 18:11:38.185848 G0: 1182 0000
322 18:11:38.186125
323 18:11:38.186404 EC: 0000 0021 [4000]
324 18:11:38.186681
325 18:11:38.186972 S7: 0000 0000 [0000]
326 18:11:38.187259
327 18:11:38.187615 CC: 0000 0000 [0001]
328 18:11:38.187954
329 18:11:38.188284 T0: 0000 0040 [010F]
330 18:11:38.188786
331 18:11:38.189238 Jump to BL
332 18:11:38.189694
333 18:11:38.190147
334 18:11:38.190581
335 18:11:38.190881 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
336 18:11:38.191182 ARM64: Exception handlers installed.
337 18:11:38.191470 ARM64: Testing exception
338 18:11:38.191753 ARM64: Done test exception
339 18:11:38.192034 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
340 18:11:38.192322 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
341 18:11:38.192656 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
342 18:11:38.193028 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
343 18:11:38.193330 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
344 18:11:38.193618 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
345 18:11:38.193905 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
346 18:11:38.194188 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
347 18:11:38.194473 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
348 18:11:38.194759 WDT: Last reset was cold boot
349 18:11:38.195037 SPI1(PAD0) initialized at 2873684 Hz
350 18:11:38.195318 SPI5(PAD0) initialized at 992727 Hz
351 18:11:38.195599 VBOOT: Loading verstage.
352 18:11:38.195924 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
353 18:11:38.196378 FMAP: Found "FLASH" version 1.1 at 0x20000.
354 18:11:38.196856 FMAP: base = 0x0 size = 0x800000 #areas = 25
355 18:11:38.197157 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
356 18:11:38.197445 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
357 18:11:38.197732 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
358 18:11:38.198018 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
359 18:11:38.198304
360 18:11:38.198583
361 18:11:38.198863 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
362 18:11:38.199146 ARM64: Exception handlers installed.
363 18:11:38.199425 ARM64: Testing exception
364 18:11:38.199782 ARM64: Done test exception
365 18:11:38.200068 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
366 18:11:38.200353 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 18:11:38.200653 Probing TPM: . done!
368 18:11:38.200936 TPM ready after 0 ms
369 18:11:38.201218 Connected to device vid:did:rid of 1ae0:0028:00
370 18:11:38.201500 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
371 18:11:38.201785 Initialized TPM device CR50 revision 0
372 18:11:38.202067 tlcl_send_startup: Startup return code is 0
373 18:11:38.202345 TPM: setup succeeded
374 18:11:38.202661 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
375 18:11:38.202950 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
376 18:11:38.203229 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
377 18:11:38.203509 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 18:11:38.203792 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
379 18:11:38.204073 in-header: 03 07 00 00 08 00 00 00
380 18:11:38.204351 in-data: aa e4 47 04 13 02 00 00
381 18:11:38.204712 Chrome EC: UHEPI supported
382 18:11:38.205145 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
383 18:11:38.205445 in-header: 03 a9 00 00 08 00 00 00
384 18:11:38.205730 in-data: 84 60 60 08 00 00 00 00
385 18:11:38.206009 Phase 1
386 18:11:38.206311 FMAP: area GBB found @ 3f5000 (12032 bytes)
387 18:11:38.206601 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
388 18:11:38.206830 VB2:vb2_check_recovery() Recovery was requested manually
389 18:11:38.207033 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
390 18:11:38.207235 Recovery requested (1009000e)
391 18:11:38.207434 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 18:11:38.207632 tlcl_extend: response is 0
393 18:11:38.207830 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 18:11:38.208033 tlcl_extend: response is 0
395 18:11:38.208232 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 18:11:38.208431 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 18:11:38.208671 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 18:11:38.208877
399 18:11:38.209075
400 18:11:38.209315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 18:11:38.209568 ARM64: Exception handlers installed.
402 18:11:38.209787 ARM64: Testing exception
403 18:11:38.209988 ARM64: Done test exception
404 18:11:38.210188 pmic_efuse_setting: Set efuses in 11 msecs
405 18:11:38.210387 pmwrap_interface_init: Select PMIF_VLD_RDY
406 18:11:38.210589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 18:11:38.210831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 18:11:38.211366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 18:11:38.211695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 18:11:38.211886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 18:11:38.212119 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 18:11:38.212322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 18:11:38.212481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 18:11:38.212662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 18:11:38.212818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 18:11:38.212970 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 18:11:38.213123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 18:11:38.213275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 18:11:38.213428 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 18:11:38.213580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 18:11:38.213734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 18:11:38.213887 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 18:11:38.214039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 18:11:38.214191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 18:11:38.214342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 18:11:38.214527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 18:11:38.214690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 18:11:38.214843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 18:11:38.214994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 18:11:38.215172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 18:11:38.215343 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 18:11:38.215502 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 18:11:38.215672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 18:11:38.215842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 18:11:38.216001 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 18:11:38.216153 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 18:11:38.216303 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 18:11:38.216454 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 18:11:38.216632 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 18:11:38.216756 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 18:11:38.216878 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 18:11:38.217000 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 18:11:38.217122 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 18:11:38.217242 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 18:11:38.217363 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 18:11:38.217484 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 18:11:38.217605 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 18:11:38.217726 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 18:11:38.217847 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 18:11:38.217967 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 18:11:38.218088 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 18:11:38.218209 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 18:11:38.218330 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 18:11:38.218451 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 18:11:38.218572 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 18:11:38.218692 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 18:11:38.218813 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 18:11:38.218936 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 18:11:38.219057 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 18:11:38.219178 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 18:11:38.219299 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 18:11:38.219421 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 18:11:38.219541 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 18:11:38.219662 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 18:11:38.219782 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1a
466 18:11:38.219903 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 18:11:38.220023 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 18:11:38.220145 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 18:11:38.220264 [RTC]rtc_get_frequency_meter,154: input=15, output=771
470 18:11:38.220384 [RTC]rtc_get_frequency_meter,154: input=23, output=958
471 18:11:38.220506 [RTC]rtc_get_frequency_meter,154: input=19, output=864
472 18:11:38.220640 [RTC]rtc_get_frequency_meter,154: input=17, output=819
473 18:11:38.220762 [RTC]rtc_get_frequency_meter,154: input=16, output=795
474 18:11:38.220882 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
475 18:11:38.221003 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
476 18:11:38.221123 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
477 18:11:38.221243 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
478 18:11:38.221590 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
479 18:11:38.221723 ADC[4]: Raw value=902876 ID=7
480 18:11:38.221827 ADC[3]: Raw value=213179 ID=1
481 18:11:38.221928 RAM Code: 0x71
482 18:11:38.222030 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
483 18:11:38.222133 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
484 18:11:38.222237 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
485 18:11:38.222339 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
486 18:11:38.222441 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
487 18:11:38.222542 in-header: 03 07 00 00 08 00 00 00
488 18:11:38.222643 in-data: aa e4 47 04 13 02 00 00
489 18:11:38.222743 Chrome EC: UHEPI supported
490 18:11:38.222845 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
491 18:11:38.222947 in-header: 03 a9 00 00 08 00 00 00
492 18:11:38.223047 in-data: 84 60 60 08 00 00 00 00
493 18:11:38.223147 MRC: failed to locate region type 0.
494 18:11:38.223248 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
495 18:11:38.223350 DRAM-K: Running full calibration
496 18:11:38.223450 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
497 18:11:38.223552 header.status = 0x0
498 18:11:38.223653 header.version = 0x6 (expected: 0x6)
499 18:11:38.223753 header.size = 0xd00 (expected: 0xd00)
500 18:11:38.223854 header.flags = 0x0
501 18:11:38.223955 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
502 18:11:38.224056 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
503 18:11:38.224158 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
504 18:11:38.224259 dram_init: ddr_geometry: 2
505 18:11:38.224358 [EMI] MDL number = 2
506 18:11:38.224459 [EMI] Get MDL freq = 0
507 18:11:38.224572 dram_init: ddr_type: 0
508 18:11:38.224677 is_discrete_lpddr4: 1
509 18:11:38.224777 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
510 18:11:38.224878
511 18:11:38.224977
512 18:11:38.225077 [Bian_co] ETT version 0.0.0.1
513 18:11:38.225179 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
514 18:11:38.225280
515 18:11:38.225380 dramc_set_vcore_voltage set vcore to 650000
516 18:11:38.225482 Read voltage for 800, 4
517 18:11:38.225582 Vio18 = 0
518 18:11:38.225683 Vcore = 650000
519 18:11:38.225783 Vdram = 0
520 18:11:38.225883 Vddq = 0
521 18:11:38.225984 Vmddr = 0
522 18:11:38.226084 dram_init: config_dvfs: 1
523 18:11:38.226184 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
524 18:11:38.226285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
525 18:11:38.226388 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
526 18:11:38.226489 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
527 18:11:38.226607 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
528 18:11:38.226694 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
529 18:11:38.226781 MEM_TYPE=3, freq_sel=18
530 18:11:38.226867 sv_algorithm_assistance_LP4_1600
531 18:11:38.226953 ============ PULL DRAM RESETB DOWN ============
532 18:11:38.227042 ========== PULL DRAM RESETB DOWN end =========
533 18:11:38.227130 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
534 18:11:38.227218 ===================================
535 18:11:38.227305 LPDDR4 DRAM CONFIGURATION
536 18:11:38.227392 ===================================
537 18:11:38.227479 EX_ROW_EN[0] = 0x0
538 18:11:38.227565 EX_ROW_EN[1] = 0x0
539 18:11:38.227652 LP4Y_EN = 0x0
540 18:11:38.227739 WORK_FSP = 0x0
541 18:11:38.227826 WL = 0x2
542 18:11:38.227912 RL = 0x2
543 18:11:38.227999 BL = 0x2
544 18:11:38.228084 RPST = 0x0
545 18:11:38.228171 RD_PRE = 0x0
546 18:11:38.228256 WR_PRE = 0x1
547 18:11:38.228342 WR_PST = 0x0
548 18:11:38.228429 DBI_WR = 0x0
549 18:11:38.228516 DBI_RD = 0x0
550 18:11:38.228620 OTF = 0x1
551 18:11:38.228709 ===================================
552 18:11:38.228796 ===================================
553 18:11:38.228884 ANA top config
554 18:11:38.228969 ===================================
555 18:11:38.229057 DLL_ASYNC_EN = 0
556 18:11:38.229144 ALL_SLAVE_EN = 1
557 18:11:38.229231 NEW_RANK_MODE = 1
558 18:11:38.229322 DLL_IDLE_MODE = 1
559 18:11:38.229408 LP45_APHY_COMB_EN = 1
560 18:11:38.229496 TX_ODT_DIS = 1
561 18:11:38.229582 NEW_8X_MODE = 1
562 18:11:38.229670 ===================================
563 18:11:38.229757 ===================================
564 18:11:38.229844 data_rate = 1600
565 18:11:38.229931 CKR = 1
566 18:11:38.230018 DQ_P2S_RATIO = 8
567 18:11:38.230105 ===================================
568 18:11:38.230192 CA_P2S_RATIO = 8
569 18:11:38.230279 DQ_CA_OPEN = 0
570 18:11:38.230366 DQ_SEMI_OPEN = 0
571 18:11:38.230453 CA_SEMI_OPEN = 0
572 18:11:38.230539 CA_FULL_RATE = 0
573 18:11:38.230625 DQ_CKDIV4_EN = 1
574 18:11:38.230710 CA_CKDIV4_EN = 1
575 18:11:38.230797 CA_PREDIV_EN = 0
576 18:11:38.230883 PH8_DLY = 0
577 18:11:38.230969 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
578 18:11:38.231056 DQ_AAMCK_DIV = 4
579 18:11:38.231142 CA_AAMCK_DIV = 4
580 18:11:38.231229 CA_ADMCK_DIV = 4
581 18:11:38.231314 DQ_TRACK_CA_EN = 0
582 18:11:38.231401 CA_PICK = 800
583 18:11:38.231488 CA_MCKIO = 800
584 18:11:38.231575 MCKIO_SEMI = 0
585 18:11:38.231667 PLL_FREQ = 3068
586 18:11:38.231742 DQ_UI_PI_RATIO = 32
587 18:11:38.231817 CA_UI_PI_RATIO = 0
588 18:11:38.231893 ===================================
589 18:11:38.231968 ===================================
590 18:11:38.232045 memory_type:LPDDR4
591 18:11:38.232120 GP_NUM : 10
592 18:11:38.232196 SRAM_EN : 1
593 18:11:38.232271 MD32_EN : 0
594 18:11:38.232347 ===================================
595 18:11:38.232424 [ANA_INIT] >>>>>>>>>>>>>>
596 18:11:38.232499 <<<<<< [CONFIGURE PHASE]: ANA_TX
597 18:11:38.232589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
598 18:11:38.232667 ===================================
599 18:11:38.232964 data_rate = 1600,PCW = 0X7600
600 18:11:38.233052 ===================================
601 18:11:38.233131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
602 18:11:38.233210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
603 18:11:38.233288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 18:11:38.233366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
605 18:11:38.233442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
606 18:11:38.233518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
607 18:11:38.233594 [ANA_INIT] flow start
608 18:11:38.233671 [ANA_INIT] PLL >>>>>>>>
609 18:11:38.233746 [ANA_INIT] PLL <<<<<<<<
610 18:11:38.233821 [ANA_INIT] MIDPI >>>>>>>>
611 18:11:38.233896 [ANA_INIT] MIDPI <<<<<<<<
612 18:11:38.233972 [ANA_INIT] DLL >>>>>>>>
613 18:11:38.234048 [ANA_INIT] flow end
614 18:11:38.234124 ============ LP4 DIFF to SE enter ============
615 18:11:38.234200 ============ LP4 DIFF to SE exit ============
616 18:11:38.234277 [ANA_INIT] <<<<<<<<<<<<<
617 18:11:38.234353 [Flow] Enable top DCM control >>>>>
618 18:11:38.234430 [Flow] Enable top DCM control <<<<<
619 18:11:38.234506 Enable DLL master slave shuffle
620 18:11:38.234583 ==============================================================
621 18:11:38.234660 Gating Mode config
622 18:11:38.234735 ==============================================================
623 18:11:38.234811 Config description:
624 18:11:38.234888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
625 18:11:38.234965 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
626 18:11:38.235042 SELPH_MODE 0: By rank 1: By Phase
627 18:11:38.235118 ==============================================================
628 18:11:38.235195 GAT_TRACK_EN = 1
629 18:11:38.235271 RX_GATING_MODE = 2
630 18:11:38.235347 RX_GATING_TRACK_MODE = 2
631 18:11:38.235422 SELPH_MODE = 1
632 18:11:38.235498 PICG_EARLY_EN = 1
633 18:11:38.235575 VALID_LAT_VALUE = 1
634 18:11:38.235651 ==============================================================
635 18:11:38.235728 Enter into Gating configuration >>>>
636 18:11:38.235804 Exit from Gating configuration <<<<
637 18:11:38.235880 Enter into DVFS_PRE_config >>>>>
638 18:11:38.235957 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
639 18:11:38.236038 Exit from DVFS_PRE_config <<<<<
640 18:11:38.236114 Enter into PICG configuration >>>>
641 18:11:38.236190 Exit from PICG configuration <<<<
642 18:11:38.236266 [RX_INPUT] configuration >>>>>
643 18:11:38.236342 [RX_INPUT] configuration <<<<<
644 18:11:38.236426 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
645 18:11:38.236507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
646 18:11:38.236606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
647 18:11:38.236685 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
648 18:11:38.236754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
649 18:11:38.236821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
650 18:11:38.236889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
651 18:11:38.236957 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
652 18:11:38.237037 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
653 18:11:38.237107 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
654 18:11:38.237175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
655 18:11:38.237261 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
656 18:11:38.237330 ===================================
657 18:11:38.237407 LPDDR4 DRAM CONFIGURATION
658 18:11:38.237477 ===================================
659 18:11:38.237546 EX_ROW_EN[0] = 0x0
660 18:11:38.237627 EX_ROW_EN[1] = 0x0
661 18:11:38.237696 LP4Y_EN = 0x0
662 18:11:38.237766 WORK_FSP = 0x0
663 18:11:38.237835 WL = 0x2
664 18:11:38.237903 RL = 0x2
665 18:11:38.237970 BL = 0x2
666 18:11:38.238037 RPST = 0x0
667 18:11:38.238104 RD_PRE = 0x0
668 18:11:38.238171 WR_PRE = 0x1
669 18:11:38.238239 WR_PST = 0x0
670 18:11:38.238307 DBI_WR = 0x0
671 18:11:38.238373 DBI_RD = 0x0
672 18:11:38.238452 OTF = 0x1
673 18:11:38.238523 ===================================
674 18:11:38.238593 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
675 18:11:38.238670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
676 18:11:38.238738 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
677 18:11:38.238806 ===================================
678 18:11:38.238874 LPDDR4 DRAM CONFIGURATION
679 18:11:38.238941 ===================================
680 18:11:38.239008 EX_ROW_EN[0] = 0x10
681 18:11:38.239075 EX_ROW_EN[1] = 0x0
682 18:11:38.239143 LP4Y_EN = 0x0
683 18:11:38.239211 WORK_FSP = 0x0
684 18:11:38.239278 WL = 0x2
685 18:11:38.239345 RL = 0x2
686 18:11:38.239425 BL = 0x2
687 18:11:38.239493 RPST = 0x0
688 18:11:38.239561 RD_PRE = 0x0
689 18:11:38.239637 WR_PRE = 0x1
690 18:11:38.239706 WR_PST = 0x0
691 18:11:38.239773 DBI_WR = 0x0
692 18:11:38.239841 DBI_RD = 0x0
693 18:11:38.239908 OTF = 0x1
694 18:11:38.239976 ===================================
695 18:11:38.240044 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
696 18:11:38.240112 nWR fixed to 40
697 18:11:38.240181 [ModeRegInit_LP4] CH0 RK0
698 18:11:38.240248 [ModeRegInit_LP4] CH0 RK1
699 18:11:38.240315 [ModeRegInit_LP4] CH1 RK0
700 18:11:38.240382 [ModeRegInit_LP4] CH1 RK1
701 18:11:38.240462 match AC timing 13
702 18:11:38.240532 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
703 18:11:38.240606 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
704 18:11:38.240691 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
705 18:11:38.240761 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
706 18:11:38.241039 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
707 18:11:38.241117 [EMI DOE] emi_dcm 0
708 18:11:38.241188 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
709 18:11:38.241274 ==
710 18:11:38.241345 Dram Type= 6, Freq= 0, CH_0, rank 0
711 18:11:38.241417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
712 18:11:38.241486 ==
713 18:11:38.241555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
714 18:11:38.241637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
715 18:11:38.241699 [CA 0] Center 38 (7~69) winsize 63
716 18:11:38.241760 [CA 1] Center 38 (7~69) winsize 63
717 18:11:38.241821 [CA 2] Center 35 (5~66) winsize 62
718 18:11:38.241882 [CA 3] Center 35 (5~66) winsize 62
719 18:11:38.241943 [CA 4] Center 35 (4~66) winsize 63
720 18:11:38.242003 [CA 5] Center 33 (3~64) winsize 62
721 18:11:38.242064
722 18:11:38.242125 [CmdBusTrainingLP45] Vref(ca) range 1: 32
723 18:11:38.242187
724 18:11:38.242247 [CATrainingPosCal] consider 1 rank data
725 18:11:38.242308 u2DelayCellTimex100 = 270/100 ps
726 18:11:38.242368 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
727 18:11:38.242429 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
728 18:11:38.242490 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
729 18:11:38.242551 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
730 18:11:38.242611 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
731 18:11:38.242672 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
732 18:11:38.242732
733 18:11:38.242793 CA PerBit enable=1, Macro0, CA PI delay=33
734 18:11:38.242854
735 18:11:38.242914 [CBTSetCACLKResult] CA Dly = 33
736 18:11:38.242974 CS Dly: 6 (0~37)
737 18:11:38.243035 ==
738 18:11:38.243096 Dram Type= 6, Freq= 0, CH_0, rank 1
739 18:11:38.243157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
740 18:11:38.243219 ==
741 18:11:38.243281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
742 18:11:38.243342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
743 18:11:38.243403 [CA 0] Center 38 (7~69) winsize 63
744 18:11:38.243464 [CA 1] Center 38 (8~69) winsize 62
745 18:11:38.243525 [CA 2] Center 36 (5~67) winsize 63
746 18:11:38.243586 [CA 3] Center 36 (5~67) winsize 63
747 18:11:38.243647 [CA 4] Center 35 (4~66) winsize 63
748 18:11:38.243708 [CA 5] Center 34 (4~65) winsize 62
749 18:11:38.243769
750 18:11:38.243830 [CmdBusTrainingLP45] Vref(ca) range 1: 34
751 18:11:38.243891
752 18:11:38.243952 [CATrainingPosCal] consider 2 rank data
753 18:11:38.244013 u2DelayCellTimex100 = 270/100 ps
754 18:11:38.244074 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
755 18:11:38.244135 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
756 18:11:38.244195 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
757 18:11:38.244256 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
758 18:11:38.244318 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
759 18:11:38.244379 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
760 18:11:38.244440
761 18:11:38.244500 CA PerBit enable=1, Macro0, CA PI delay=34
762 18:11:38.244566
763 18:11:38.244627 [CBTSetCACLKResult] CA Dly = 34
764 18:11:38.244688 CS Dly: 6 (0~38)
765 18:11:38.244748
766 18:11:38.244809 ----->DramcWriteLeveling(PI) begin...
767 18:11:38.244872 ==
768 18:11:38.244933 Dram Type= 6, Freq= 0, CH_0, rank 0
769 18:11:38.244994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
770 18:11:38.245055 ==
771 18:11:38.245115 Write leveling (Byte 0): 32 => 32
772 18:11:38.245177 Write leveling (Byte 1): 32 => 32
773 18:11:38.245238 DramcWriteLeveling(PI) end<-----
774 18:11:38.245298
775 18:11:38.245359 ==
776 18:11:38.245420 Dram Type= 6, Freq= 0, CH_0, rank 0
777 18:11:38.245480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 18:11:38.245541 ==
779 18:11:38.245602 [Gating] SW mode calibration
780 18:11:38.245663 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
781 18:11:38.245726 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
782 18:11:38.245787 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
783 18:11:38.245849 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
784 18:11:38.245910 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
785 18:11:38.245970 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 18:11:38.246031 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 18:11:38.246092 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 18:11:38.246153 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 18:11:38.246214 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 18:11:38.246274 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 18:11:38.246335 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 18:11:38.246395 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 18:11:38.246456 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 18:11:38.246517 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 18:11:38.246578 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 18:11:38.246648 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 18:11:38.246703 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 18:11:38.246759 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
799 18:11:38.246814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 18:11:38.246870 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 18:11:38.246925 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 18:11:38.246980 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 18:11:38.247038 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 18:11:38.247095 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 18:11:38.247150 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 18:11:38.247206 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 18:11:38.247261 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 18:11:38.247317 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
809 18:11:38.247372 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
810 18:11:38.247428 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 18:11:38.247483 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 18:11:38.247539 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 18:11:38.247595 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 18:11:38.247842 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 18:11:38.247904 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
816 18:11:38.247961 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
817 18:11:38.248017 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 18:11:38.248073 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 18:11:38.248129 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 18:11:38.248185 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 18:11:38.248240 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 18:11:38.248296 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 18:11:38.248352 0 11 4 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
824 18:11:38.248407 0 11 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
825 18:11:38.248462 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
826 18:11:38.248517 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 18:11:38.248578 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 18:11:38.248634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 18:11:38.248690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 18:11:38.248745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 18:11:38.248800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 18:11:38.248856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
833 18:11:38.248912 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 18:11:38.248967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 18:11:38.249022 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 18:11:38.249078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 18:11:38.249133 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 18:11:38.249188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 18:11:38.249243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 18:11:38.249299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 18:11:38.249354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 18:11:38.249410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 18:11:38.249466 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 18:11:38.249522 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 18:11:38.249578 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 18:11:38.249633 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 18:11:38.249689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 18:11:38.249744 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 18:11:38.249800 Total UI for P1: 0, mck2ui 16
850 18:11:38.249856 best dqsien dly found for B0: ( 0, 14, 4)
851 18:11:38.249912 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 18:11:38.249968 Total UI for P1: 0, mck2ui 16
853 18:11:38.250024 best dqsien dly found for B1: ( 0, 14, 8)
854 18:11:38.250079 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 18:11:38.250135 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
856 18:11:38.250191
857 18:11:38.250246 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 18:11:38.250302 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
859 18:11:38.250358 [Gating] SW calibration Done
860 18:11:38.250414 ==
861 18:11:38.250470 Dram Type= 6, Freq= 0, CH_0, rank 0
862 18:11:38.250526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 18:11:38.250581 ==
864 18:11:38.250637 RX Vref Scan: 0
865 18:11:38.250692
866 18:11:38.250748 RX Vref 0 -> 0, step: 1
867 18:11:38.250803
868 18:11:38.250858 RX Delay -130 -> 252, step: 16
869 18:11:38.250914 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 18:11:38.250970 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 18:11:38.251025 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
872 18:11:38.251081 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 18:11:38.251136 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 18:11:38.251191 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 18:11:38.251247 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 18:11:38.251302 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 18:11:38.251356 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 18:11:38.251410 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 18:11:38.251465 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 18:11:38.251519 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 18:11:38.251574 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 18:11:38.251641 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 18:11:38.251695 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 18:11:38.251748 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 18:11:38.251801 ==
886 18:11:38.251854 Dram Type= 6, Freq= 0, CH_0, rank 0
887 18:11:38.251908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 18:11:38.251963 ==
889 18:11:38.252017 DQS Delay:
890 18:11:38.252071 DQS0 = 0, DQS1 = 0
891 18:11:38.252126 DQM Delay:
892 18:11:38.252180 DQM0 = 92, DQM1 = 79
893 18:11:38.252234 DQ Delay:
894 18:11:38.252288 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
895 18:11:38.252344 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 18:11:38.252399 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 18:11:38.252453 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
898 18:11:38.252508
899 18:11:38.252565
900 18:11:38.252620 ==
901 18:11:38.252674 Dram Type= 6, Freq= 0, CH_0, rank 0
902 18:11:38.252729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 18:11:38.252785 ==
904 18:11:38.252840
905 18:11:38.252893
906 18:11:38.252948 TX Vref Scan disable
907 18:11:38.253002 == TX Byte 0 ==
908 18:11:38.253056 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
909 18:11:38.253111 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
910 18:11:38.253165 == TX Byte 1 ==
911 18:11:38.253220 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
912 18:11:38.253274 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
913 18:11:38.253328 ==
914 18:11:38.253382 Dram Type= 6, Freq= 0, CH_0, rank 0
915 18:11:38.253437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 18:11:38.253491 ==
917 18:11:38.253546 TX Vref=22, minBit 6, minWin=27, winSum=441
918 18:11:38.253601 TX Vref=24, minBit 8, minWin=27, winSum=446
919 18:11:38.253655 TX Vref=26, minBit 8, minWin=27, winSum=449
920 18:11:38.253710 TX Vref=28, minBit 9, minWin=27, winSum=456
921 18:11:38.253765 TX Vref=30, minBit 5, minWin=28, winSum=459
922 18:11:38.254013 TX Vref=32, minBit 3, minWin=28, winSum=459
923 18:11:38.254076 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
924 18:11:38.254134
925 18:11:38.254189 Final TX Range 1 Vref 30
926 18:11:38.254244
927 18:11:38.254299 ==
928 18:11:38.254354 Dram Type= 6, Freq= 0, CH_0, rank 0
929 18:11:38.254409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 18:11:38.254464 ==
931 18:11:38.254519
932 18:11:38.254574
933 18:11:38.254628 TX Vref Scan disable
934 18:11:38.254683 == TX Byte 0 ==
935 18:11:38.254738 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
936 18:11:38.254793 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
937 18:11:38.254847 == TX Byte 1 ==
938 18:11:38.254901 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
939 18:11:38.254956 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
940 18:11:38.255011
941 18:11:38.255065 [DATLAT]
942 18:11:38.255120 Freq=800, CH0 RK0
943 18:11:38.255178
944 18:11:38.255233 DATLAT Default: 0xa
945 18:11:38.255287 0, 0xFFFF, sum = 0
946 18:11:38.255342 1, 0xFFFF, sum = 0
947 18:11:38.255398 2, 0xFFFF, sum = 0
948 18:11:38.255453 3, 0xFFFF, sum = 0
949 18:11:38.255508 4, 0xFFFF, sum = 0
950 18:11:38.255563 5, 0xFFFF, sum = 0
951 18:11:38.255618 6, 0xFFFF, sum = 0
952 18:11:38.255672 7, 0xFFFF, sum = 0
953 18:11:38.255727 8, 0xFFFF, sum = 0
954 18:11:38.255782 9, 0x0, sum = 1
955 18:11:38.255837 10, 0x0, sum = 2
956 18:11:38.255892 11, 0x0, sum = 3
957 18:11:38.255947 12, 0x0, sum = 4
958 18:11:38.256002 best_step = 10
959 18:11:38.256055
960 18:11:38.256109 ==
961 18:11:38.256163 Dram Type= 6, Freq= 0, CH_0, rank 0
962 18:11:38.256218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 18:11:38.256273 ==
964 18:11:38.256328 RX Vref Scan: 1
965 18:11:38.256382
966 18:11:38.256436 Set Vref Range= 32 -> 127
967 18:11:38.256490
968 18:11:38.256544 RX Vref 32 -> 127, step: 1
969 18:11:38.256603
970 18:11:38.256657 RX Delay -95 -> 252, step: 8
971 18:11:38.256712
972 18:11:38.256767 Set Vref, RX VrefLevel [Byte0]: 32
973 18:11:38.256821 [Byte1]: 32
974 18:11:38.256875
975 18:11:38.256929 Set Vref, RX VrefLevel [Byte0]: 33
976 18:11:38.256983 [Byte1]: 33
977 18:11:38.257037
978 18:11:38.257091 Set Vref, RX VrefLevel [Byte0]: 34
979 18:11:38.257145 [Byte1]: 34
980 18:11:38.257199
981 18:11:38.257252 Set Vref, RX VrefLevel [Byte0]: 35
982 18:11:38.257306 [Byte1]: 35
983 18:11:38.257360
984 18:11:38.257414 Set Vref, RX VrefLevel [Byte0]: 36
985 18:11:38.257467 [Byte1]: 36
986 18:11:38.257520
987 18:11:38.257575 Set Vref, RX VrefLevel [Byte0]: 37
988 18:11:38.257629 [Byte1]: 37
989 18:11:38.257683
990 18:11:38.257737 Set Vref, RX VrefLevel [Byte0]: 38
991 18:11:38.257792 [Byte1]: 38
992 18:11:38.257846
993 18:11:38.257900 Set Vref, RX VrefLevel [Byte0]: 39
994 18:11:38.257954 [Byte1]: 39
995 18:11:38.258008
996 18:11:38.258062 Set Vref, RX VrefLevel [Byte0]: 40
997 18:11:38.258116 [Byte1]: 40
998 18:11:38.258169
999 18:11:38.258223 Set Vref, RX VrefLevel [Byte0]: 41
1000 18:11:38.258278 [Byte1]: 41
1001 18:11:38.258332
1002 18:11:38.258386 Set Vref, RX VrefLevel [Byte0]: 42
1003 18:11:38.258440 [Byte1]: 42
1004 18:11:38.258494
1005 18:11:38.258548 Set Vref, RX VrefLevel [Byte0]: 43
1006 18:11:38.258602 [Byte1]: 43
1007 18:11:38.258656
1008 18:11:38.258710 Set Vref, RX VrefLevel [Byte0]: 44
1009 18:11:38.258764 [Byte1]: 44
1010 18:11:38.258818
1011 18:11:38.258872 Set Vref, RX VrefLevel [Byte0]: 45
1012 18:11:38.258926 [Byte1]: 45
1013 18:11:38.258980
1014 18:11:38.259034 Set Vref, RX VrefLevel [Byte0]: 46
1015 18:11:38.259088 [Byte1]: 46
1016 18:11:38.259142
1017 18:11:38.259196 Set Vref, RX VrefLevel [Byte0]: 47
1018 18:11:38.259251 [Byte1]: 47
1019 18:11:38.259306
1020 18:11:38.259360 Set Vref, RX VrefLevel [Byte0]: 48
1021 18:11:38.259415 [Byte1]: 48
1022 18:11:38.259469
1023 18:11:38.259522 Set Vref, RX VrefLevel [Byte0]: 49
1024 18:11:38.259577 [Byte1]: 49
1025 18:11:38.259639
1026 18:11:38.259695 Set Vref, RX VrefLevel [Byte0]: 50
1027 18:11:38.259750 [Byte1]: 50
1028 18:11:38.259805
1029 18:11:38.259859 Set Vref, RX VrefLevel [Byte0]: 51
1030 18:11:38.259914 [Byte1]: 51
1031 18:11:38.259968
1032 18:11:38.260021 Set Vref, RX VrefLevel [Byte0]: 52
1033 18:11:38.260075 [Byte1]: 52
1034 18:11:38.260129
1035 18:11:38.260182 Set Vref, RX VrefLevel [Byte0]: 53
1036 18:11:38.260235 [Byte1]: 53
1037 18:11:38.260288
1038 18:11:38.260341 Set Vref, RX VrefLevel [Byte0]: 54
1039 18:11:38.260395 [Byte1]: 54
1040 18:11:38.260448
1041 18:11:38.260501 Set Vref, RX VrefLevel [Byte0]: 55
1042 18:11:38.260558 [Byte1]: 55
1043 18:11:38.260611
1044 18:11:38.260664 Set Vref, RX VrefLevel [Byte0]: 56
1045 18:11:38.260718 [Byte1]: 56
1046 18:11:38.260771
1047 18:11:38.260825 Set Vref, RX VrefLevel [Byte0]: 57
1048 18:11:38.260878 [Byte1]: 57
1049 18:11:38.260931
1050 18:11:38.260984 Set Vref, RX VrefLevel [Byte0]: 58
1051 18:11:38.261038 [Byte1]: 58
1052 18:11:38.261091
1053 18:11:38.261144 Set Vref, RX VrefLevel [Byte0]: 59
1054 18:11:38.261197 [Byte1]: 59
1055 18:11:38.261250
1056 18:11:38.261303 Set Vref, RX VrefLevel [Byte0]: 60
1057 18:11:38.261356 [Byte1]: 60
1058 18:11:38.261409
1059 18:11:38.261462 Set Vref, RX VrefLevel [Byte0]: 61
1060 18:11:38.261516 [Byte1]: 61
1061 18:11:38.261569
1062 18:11:38.261621 Set Vref, RX VrefLevel [Byte0]: 62
1063 18:11:38.261674 [Byte1]: 62
1064 18:11:38.261726
1065 18:11:38.261778 Set Vref, RX VrefLevel [Byte0]: 63
1066 18:11:38.261830 [Byte1]: 63
1067 18:11:38.261883
1068 18:11:38.261936 Set Vref, RX VrefLevel [Byte0]: 64
1069 18:11:38.261988 [Byte1]: 64
1070 18:11:38.262041
1071 18:11:38.262093 Set Vref, RX VrefLevel [Byte0]: 65
1072 18:11:38.262145 [Byte1]: 65
1073 18:11:38.262198
1074 18:11:38.262249 Set Vref, RX VrefLevel [Byte0]: 66
1075 18:11:38.262302 [Byte1]: 66
1076 18:11:38.262355
1077 18:11:38.262407 Set Vref, RX VrefLevel [Byte0]: 67
1078 18:11:38.262461 [Byte1]: 67
1079 18:11:38.262513
1080 18:11:38.262567 Set Vref, RX VrefLevel [Byte0]: 68
1081 18:11:38.262620 [Byte1]: 68
1082 18:11:38.262673
1083 18:11:38.262726 Set Vref, RX VrefLevel [Byte0]: 69
1084 18:11:38.262779 [Byte1]: 69
1085 18:11:38.262832
1086 18:11:38.262885 Set Vref, RX VrefLevel [Byte0]: 70
1087 18:11:38.262938 [Byte1]: 70
1088 18:11:38.262991
1089 18:11:38.263044 Set Vref, RX VrefLevel [Byte0]: 71
1090 18:11:38.263098 [Byte1]: 71
1091 18:11:38.263151
1092 18:11:38.263204 Set Vref, RX VrefLevel [Byte0]: 72
1093 18:11:38.263447 [Byte1]: 72
1094 18:11:38.263508
1095 18:11:38.263563 Set Vref, RX VrefLevel [Byte0]: 73
1096 18:11:38.263617 [Byte1]: 73
1097 18:11:38.263671
1098 18:11:38.263724 Set Vref, RX VrefLevel [Byte0]: 74
1099 18:11:38.263777 [Byte1]: 74
1100 18:11:38.263831
1101 18:11:38.263885 Set Vref, RX VrefLevel [Byte0]: 75
1102 18:11:38.263938 [Byte1]: 75
1103 18:11:38.263991
1104 18:11:38.264044 Set Vref, RX VrefLevel [Byte0]: 76
1105 18:11:38.264097 [Byte1]: 76
1106 18:11:38.264150
1107 18:11:38.264203 Set Vref, RX VrefLevel [Byte0]: 77
1108 18:11:38.264257 [Byte1]: 77
1109 18:11:38.264310
1110 18:11:38.264363 Set Vref, RX VrefLevel [Byte0]: 78
1111 18:11:38.264416 [Byte1]: 78
1112 18:11:38.264469
1113 18:11:38.264522 Final RX Vref Byte 0 = 62 to rank0
1114 18:11:38.264648 Final RX Vref Byte 1 = 62 to rank0
1115 18:11:38.264703 Final RX Vref Byte 0 = 62 to rank1
1116 18:11:38.264756 Final RX Vref Byte 1 = 62 to rank1==
1117 18:11:38.264810 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 18:11:38.264864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 18:11:38.264918 ==
1120 18:11:38.264972 DQS Delay:
1121 18:11:38.265025 DQS0 = 0, DQS1 = 0
1122 18:11:38.265078 DQM Delay:
1123 18:11:38.265131 DQM0 = 93, DQM1 = 81
1124 18:11:38.265185 DQ Delay:
1125 18:11:38.265237 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1126 18:11:38.265291 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1127 18:11:38.265344 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1128 18:11:38.265398 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1129 18:11:38.265450
1130 18:11:38.265503
1131 18:11:38.265557 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1132 18:11:38.265611 CH0 RK0: MR19=606, MR18=3B36
1133 18:11:38.265664 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1134 18:11:38.265718
1135 18:11:38.265771 ----->DramcWriteLeveling(PI) begin...
1136 18:11:38.265824 ==
1137 18:11:38.265878 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 18:11:38.265932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 18:11:38.265986 ==
1140 18:11:38.266039 Write leveling (Byte 0): 31 => 31
1141 18:11:38.266093 Write leveling (Byte 1): 29 => 29
1142 18:11:38.266146 DramcWriteLeveling(PI) end<-----
1143 18:11:38.266200
1144 18:11:38.266253 ==
1145 18:11:38.266306 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 18:11:38.266359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 18:11:38.266413 ==
1148 18:11:38.266466 [Gating] SW mode calibration
1149 18:11:38.266520 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 18:11:38.266574 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 18:11:38.266628 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 18:11:38.266683 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 18:11:38.266736 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 18:11:38.266790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 18:11:38.266843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 18:11:38.266897 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 18:11:38.266951 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 18:11:38.267005 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 18:11:38.267058 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 18:11:38.267112 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 18:11:38.267165 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 18:11:38.267219 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 18:11:38.267272 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 18:11:38.267325 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 18:11:38.267378 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 18:11:38.267431 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 18:11:38.267484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1168 18:11:38.267537 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1169 18:11:38.267590 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 18:11:38.267643 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 18:11:38.267696 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 18:11:38.267749 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 18:11:38.267803 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 18:11:38.267856 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 18:11:38.267909 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 18:11:38.267962 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1177 18:11:38.268016 0 9 8 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (1 1)
1178 18:11:38.268069 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 18:11:38.268127 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 18:11:38.268180 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 18:11:38.268233 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 18:11:38.268287 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 18:11:38.268341 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 18:11:38.268394 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 1)
1185 18:11:38.268448 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
1186 18:11:38.268502 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 18:11:38.268574 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 18:11:38.268641 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 18:11:38.268695 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 18:11:38.268748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 18:11:38.268802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 18:11:38.268855 0 11 4 | B1->B0 | 2626 3232 | 0 0 | (0 0) (1 1)
1193 18:11:38.268909 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1194 18:11:38.268962 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 18:11:38.269016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 18:11:38.269069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 18:11:38.269123 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 18:11:38.269199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 18:11:38.269446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 18:11:38.269507 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1201 18:11:38.269562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 18:11:38.269616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 18:11:38.269670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 18:11:38.269724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 18:11:38.269778 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 18:11:38.269832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 18:11:38.269885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 18:11:38.269939 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 18:11:38.269993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 18:11:38.270047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 18:11:38.270099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 18:11:38.270152 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 18:11:38.270206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 18:11:38.270260 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 18:11:38.270312 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 18:11:38.270365 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 18:11:38.270418 Total UI for P1: 0, mck2ui 16
1218 18:11:38.270473 best dqsien dly found for B0: ( 0, 14, 2)
1219 18:11:38.270527 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 18:11:38.270581 Total UI for P1: 0, mck2ui 16
1221 18:11:38.270635 best dqsien dly found for B1: ( 0, 14, 4)
1222 18:11:38.270689 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1223 18:11:38.270742 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1224 18:11:38.270795
1225 18:11:38.270848 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1226 18:11:38.270901 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1227 18:11:38.270954 [Gating] SW calibration Done
1228 18:11:38.271007 ==
1229 18:11:38.271061 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 18:11:38.271115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 18:11:38.271169 ==
1232 18:11:38.271222 RX Vref Scan: 0
1233 18:11:38.271275
1234 18:11:38.271328 RX Vref 0 -> 0, step: 1
1235 18:11:38.271381
1236 18:11:38.271434 RX Delay -130 -> 252, step: 16
1237 18:11:38.271517 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1238 18:11:38.271571 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 18:11:38.271625 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1240 18:11:38.271678 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1241 18:11:38.271731 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 18:11:38.271784 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1243 18:11:38.271838 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1244 18:11:38.271891 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1245 18:11:38.271944 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1246 18:11:38.271998 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1247 18:11:38.272057 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 18:11:38.272111 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 18:11:38.272164 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1250 18:11:38.272218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1251 18:11:38.272271 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 18:11:38.272324 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1253 18:11:38.272377 ==
1254 18:11:38.272431 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 18:11:38.272485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 18:11:38.272539 ==
1257 18:11:38.272634 DQS Delay:
1258 18:11:38.272688 DQS0 = 0, DQS1 = 0
1259 18:11:38.272741 DQM Delay:
1260 18:11:38.272794 DQM0 = 88, DQM1 = 79
1261 18:11:38.272847 DQ Delay:
1262 18:11:38.272901 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1263 18:11:38.272954 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1264 18:11:38.273008 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1265 18:11:38.273061 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1266 18:11:38.273114
1267 18:11:38.273168
1268 18:11:38.273221 ==
1269 18:11:38.273275 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 18:11:38.273328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 18:11:38.273382 ==
1272 18:11:38.273435
1273 18:11:38.273487
1274 18:11:38.273540 TX Vref Scan disable
1275 18:11:38.273594 == TX Byte 0 ==
1276 18:11:38.273647 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1277 18:11:38.273701 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1278 18:11:38.273755 == TX Byte 1 ==
1279 18:11:38.273807 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1280 18:11:38.273861 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1281 18:11:38.273914 ==
1282 18:11:38.273967 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 18:11:38.274020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 18:11:38.274081 ==
1285 18:11:38.274136 TX Vref=22, minBit 8, minWin=27, winSum=449
1286 18:11:38.274190 TX Vref=24, minBit 1, minWin=27, winSum=448
1287 18:11:38.274244 TX Vref=26, minBit 8, minWin=27, winSum=452
1288 18:11:38.274298 TX Vref=28, minBit 8, minWin=27, winSum=452
1289 18:11:38.274352 TX Vref=30, minBit 12, minWin=27, winSum=455
1290 18:11:38.274406 TX Vref=32, minBit 10, minWin=27, winSum=454
1291 18:11:38.274459 [TxChooseVref] Worse bit 12, Min win 27, Win sum 455, Final Vref 30
1292 18:11:38.274513
1293 18:11:38.274566 Final TX Range 1 Vref 30
1294 18:11:38.274619
1295 18:11:38.274669 ==
1296 18:11:38.274720 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 18:11:38.274772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 18:11:38.274825 ==
1299 18:11:38.274877
1300 18:11:38.274927
1301 18:11:38.274978 TX Vref Scan disable
1302 18:11:38.275029 == TX Byte 0 ==
1303 18:11:38.275081 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1304 18:11:38.275133 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1305 18:11:38.275184 == TX Byte 1 ==
1306 18:11:38.275236 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 18:11:38.275287 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 18:11:38.275338
1309 18:11:38.275389 [DATLAT]
1310 18:11:38.275440 Freq=800, CH0 RK1
1311 18:11:38.275492
1312 18:11:38.275543 DATLAT Default: 0xa
1313 18:11:38.275593 0, 0xFFFF, sum = 0
1314 18:11:38.275645 1, 0xFFFF, sum = 0
1315 18:11:38.275698 2, 0xFFFF, sum = 0
1316 18:11:38.275750 3, 0xFFFF, sum = 0
1317 18:11:38.275802 4, 0xFFFF, sum = 0
1318 18:11:38.275854 5, 0xFFFF, sum = 0
1319 18:11:38.275906 6, 0xFFFF, sum = 0
1320 18:11:38.275958 7, 0xFFFF, sum = 0
1321 18:11:38.276009 8, 0xFFFF, sum = 0
1322 18:11:38.276061 9, 0x0, sum = 1
1323 18:11:38.276113 10, 0x0, sum = 2
1324 18:11:38.276166 11, 0x0, sum = 3
1325 18:11:38.276218 12, 0x0, sum = 4
1326 18:11:38.276271 best_step = 10
1327 18:11:38.276322
1328 18:11:38.276372 ==
1329 18:11:38.276423 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 18:11:38.276667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 18:11:38.276728 ==
1332 18:11:38.276781 RX Vref Scan: 0
1333 18:11:38.276833
1334 18:11:38.276884 RX Vref 0 -> 0, step: 1
1335 18:11:38.276935
1336 18:11:38.276985 RX Delay -79 -> 252, step: 8
1337 18:11:38.277037 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1338 18:11:38.277089 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1339 18:11:38.277142 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1340 18:11:38.277194 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1341 18:11:38.277245 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1342 18:11:38.277297 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1343 18:11:38.277348 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 18:11:38.277399 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 18:11:38.277450 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1346 18:11:38.277502 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1347 18:11:38.277553 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1348 18:11:38.277605 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1349 18:11:38.277656 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1350 18:11:38.277721 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1351 18:11:38.277775 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 18:11:38.277827 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1353 18:11:38.277879 ==
1354 18:11:38.277938 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 18:11:38.277991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 18:11:38.278043 ==
1357 18:11:38.278095 DQS Delay:
1358 18:11:38.278147 DQS0 = 0, DQS1 = 0
1359 18:11:38.278205 DQM Delay:
1360 18:11:38.278258 DQM0 = 91, DQM1 = 82
1361 18:11:38.278310 DQ Delay:
1362 18:11:38.278361 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1363 18:11:38.278427 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1364 18:11:38.278480 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1365 18:11:38.278532 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1366 18:11:38.278586
1367 18:11:38.278637
1368 18:11:38.278688 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1369 18:11:38.278741 CH0 RK1: MR19=606, MR18=411B
1370 18:11:38.278793 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1371 18:11:38.278845 [RxdqsGatingPostProcess] freq 800
1372 18:11:38.278897 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 18:11:38.278949 Pre-setting of DQS Precalculation
1374 18:11:38.279001 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 18:11:38.279052 ==
1376 18:11:38.279103 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 18:11:38.279156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 18:11:38.279208 ==
1379 18:11:38.279259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 18:11:38.279312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 18:11:38.279364 [CA 0] Center 36 (6~67) winsize 62
1382 18:11:38.279416 [CA 1] Center 36 (6~67) winsize 62
1383 18:11:38.279467 [CA 2] Center 34 (4~65) winsize 62
1384 18:11:38.279518 [CA 3] Center 34 (3~65) winsize 63
1385 18:11:38.279569 [CA 4] Center 34 (4~65) winsize 62
1386 18:11:38.279621 [CA 5] Center 33 (3~64) winsize 62
1387 18:11:38.279671
1388 18:11:38.279722 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1389 18:11:38.279774
1390 18:11:38.279826 [CATrainingPosCal] consider 1 rank data
1391 18:11:38.279878 u2DelayCellTimex100 = 270/100 ps
1392 18:11:38.279929 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 18:11:38.279980 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 18:11:38.280032 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 18:11:38.280083 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1396 18:11:38.280134 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1397 18:11:38.280186 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 18:11:38.280237
1399 18:11:38.280288 CA PerBit enable=1, Macro0, CA PI delay=33
1400 18:11:38.280344
1401 18:11:38.280431 [CBTSetCACLKResult] CA Dly = 33
1402 18:11:38.280513 CS Dly: 5 (0~36)
1403 18:11:38.280625 ==
1404 18:11:38.280680 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 18:11:38.280733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 18:11:38.280786 ==
1407 18:11:38.280841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 18:11:38.280894 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 18:11:38.280946 [CA 0] Center 36 (6~67) winsize 62
1410 18:11:38.280998 [CA 1] Center 37 (6~68) winsize 63
1411 18:11:38.281050 [CA 2] Center 35 (5~66) winsize 62
1412 18:11:38.281102 [CA 3] Center 34 (4~65) winsize 62
1413 18:11:38.281153 [CA 4] Center 34 (4~65) winsize 62
1414 18:11:38.281205 [CA 5] Center 34 (4~65) winsize 62
1415 18:11:38.281257
1416 18:11:38.281312 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1417 18:11:38.281368
1418 18:11:38.281420 [CATrainingPosCal] consider 2 rank data
1419 18:11:38.281473 u2DelayCellTimex100 = 270/100 ps
1420 18:11:38.281531 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 18:11:38.281586 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 18:11:38.281638 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 18:11:38.281691 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 18:11:38.281750 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 18:11:38.281802 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 18:11:38.281853
1427 18:11:38.281910 CA PerBit enable=1, Macro0, CA PI delay=34
1428 18:11:38.281965
1429 18:11:38.282016 [CBTSetCACLKResult] CA Dly = 34
1430 18:11:38.282068 CS Dly: 6 (0~38)
1431 18:11:38.282123
1432 18:11:38.282174 ----->DramcWriteLeveling(PI) begin...
1433 18:11:38.282226 ==
1434 18:11:38.282283 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 18:11:38.282338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 18:11:38.282391 ==
1437 18:11:38.282442 Write leveling (Byte 0): 28 => 28
1438 18:11:38.282507 Write leveling (Byte 1): 29 => 29
1439 18:11:38.282590 DramcWriteLeveling(PI) end<-----
1440 18:11:38.282674
1441 18:11:38.282756 ==
1442 18:11:38.282837 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 18:11:38.282921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 18:11:38.283002 ==
1445 18:11:38.283082 [Gating] SW mode calibration
1446 18:11:38.283136 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 18:11:38.283190 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 18:11:38.283249 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 18:11:38.283304 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1450 18:11:38.283358 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 18:11:38.283607 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 18:11:38.283678 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 18:11:38.283733 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 18:11:38.283786 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 18:11:38.283842 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 18:11:38.283895 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 18:11:38.283947 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 18:11:38.283999 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 18:11:38.284062 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 18:11:38.284115 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 18:11:38.284167 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 18:11:38.284229 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 18:11:38.284282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 18:11:38.284334 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1465 18:11:38.284391 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1466 18:11:38.284477 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 18:11:38.284581 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 18:11:38.284653 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 18:11:38.284705 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 18:11:38.284758 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 18:11:38.284809 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 18:11:38.284861 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 18:11:38.284913 0 9 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
1474 18:11:38.284965 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1475 18:11:38.285016 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 18:11:38.285068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 18:11:38.285119 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 18:11:38.285172 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 18:11:38.285223 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 18:11:38.285275 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1481 18:11:38.285327 0 10 4 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (1 0)
1482 18:11:38.285378 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1483 18:11:38.285430 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 18:11:38.285481 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 18:11:38.285534 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 18:11:38.285585 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 18:11:38.285637 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 18:11:38.285689 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1489 18:11:38.285741 0 11 4 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (1 1)
1490 18:11:38.285793 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1491 18:11:38.285845 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 18:11:38.285897 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 18:11:38.285949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 18:11:38.286000 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 18:11:38.286052 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 18:11:38.286104 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1497 18:11:38.286156 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 18:11:38.286207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 18:11:38.286258 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 18:11:38.286310 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 18:11:38.286362 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 18:11:38.286413 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 18:11:38.286465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 18:11:38.286516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 18:11:38.286568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 18:11:38.286619 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 18:11:38.286671 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 18:11:38.286723 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 18:11:38.286774 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 18:11:38.286825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 18:11:38.286877 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 18:11:38.286929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1513 18:11:38.286980 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 18:11:38.287031 Total UI for P1: 0, mck2ui 16
1515 18:11:38.287083 best dqsien dly found for B0: ( 0, 14, 0)
1516 18:11:38.287135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 18:11:38.287186 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 18:11:38.287239 Total UI for P1: 0, mck2ui 16
1519 18:11:38.287291 best dqsien dly found for B1: ( 0, 14, 6)
1520 18:11:38.287343 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1521 18:11:38.287395 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1522 18:11:38.287447
1523 18:11:38.287498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1524 18:11:38.287551 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 18:11:38.287602 [Gating] SW calibration Done
1526 18:11:38.287654 ==
1527 18:11:38.287706 Dram Type= 6, Freq= 0, CH_1, rank 0
1528 18:11:38.287758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1529 18:11:38.287810 ==
1530 18:11:38.287862 RX Vref Scan: 0
1531 18:11:38.287914
1532 18:11:38.287965 RX Vref 0 -> 0, step: 1
1533 18:11:38.288017
1534 18:11:38.288068 RX Delay -130 -> 252, step: 16
1535 18:11:38.288119 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1536 18:11:38.288171 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1537 18:11:38.288224 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1538 18:11:38.288276 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1539 18:11:38.288328 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1540 18:11:38.288404 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1541 18:11:38.288677 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1542 18:11:38.288845 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1543 18:11:38.289048 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1544 18:11:38.289131 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1545 18:11:38.289191 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1546 18:11:38.289249 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1547 18:11:38.289306 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1548 18:11:38.289361 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1549 18:11:38.289416 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1550 18:11:38.289471 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1551 18:11:38.289526 ==
1552 18:11:38.289580 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 18:11:38.289646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 18:11:38.289720 ==
1555 18:11:38.289836 DQS Delay:
1556 18:11:38.289891 DQS0 = 0, DQS1 = 0
1557 18:11:38.289945 DQM Delay:
1558 18:11:38.289998 DQM0 = 86, DQM1 = 80
1559 18:11:38.290051 DQ Delay:
1560 18:11:38.290104 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1561 18:11:38.290158 DQ4 =77, DQ5 =93, DQ6 =101, DQ7 =85
1562 18:11:38.290237 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1563 18:11:38.290295 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1564 18:11:38.290349
1565 18:11:38.290402
1566 18:11:38.290454 ==
1567 18:11:38.290507 Dram Type= 6, Freq= 0, CH_1, rank 0
1568 18:11:38.290561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1569 18:11:38.290614 ==
1570 18:11:38.290667
1571 18:11:38.290719
1572 18:11:38.290771 TX Vref Scan disable
1573 18:11:38.290823 == TX Byte 0 ==
1574 18:11:38.290876 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 18:11:38.290929 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 18:11:38.290981 == TX Byte 1 ==
1577 18:11:38.291033 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 18:11:38.291086 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 18:11:38.291138 ==
1580 18:11:38.291191 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 18:11:38.291244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 18:11:38.291297 ==
1583 18:11:38.291350 TX Vref=22, minBit 10, minWin=27, winSum=449
1584 18:11:38.291403 TX Vref=24, minBit 15, minWin=27, winSum=453
1585 18:11:38.291456 TX Vref=26, minBit 13, minWin=27, winSum=453
1586 18:11:38.291509 TX Vref=28, minBit 15, minWin=27, winSum=456
1587 18:11:38.291561 TX Vref=30, minBit 15, minWin=27, winSum=458
1588 18:11:38.291614 TX Vref=32, minBit 15, minWin=27, winSum=458
1589 18:11:38.291667 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 30
1590 18:11:38.291719
1591 18:11:38.291771 Final TX Range 1 Vref 30
1592 18:11:38.291824
1593 18:11:38.291876 ==
1594 18:11:38.291928 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 18:11:38.291980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 18:11:38.292033 ==
1597 18:11:38.292085
1598 18:11:38.292137
1599 18:11:38.292188 TX Vref Scan disable
1600 18:11:38.292241 == TX Byte 0 ==
1601 18:11:38.292293 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 18:11:38.292346 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 18:11:38.292399 == TX Byte 1 ==
1604 18:11:38.292451 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1605 18:11:38.292504 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1606 18:11:38.292586
1607 18:11:38.292654 [DATLAT]
1608 18:11:38.292706 Freq=800, CH1 RK0
1609 18:11:38.292759
1610 18:11:38.292811 DATLAT Default: 0xa
1611 18:11:38.292863 0, 0xFFFF, sum = 0
1612 18:11:38.292916 1, 0xFFFF, sum = 0
1613 18:11:38.292969 2, 0xFFFF, sum = 0
1614 18:11:38.293021 3, 0xFFFF, sum = 0
1615 18:11:38.293074 4, 0xFFFF, sum = 0
1616 18:11:38.293125 5, 0xFFFF, sum = 0
1617 18:11:38.293178 6, 0xFFFF, sum = 0
1618 18:11:38.293230 7, 0xFFFF, sum = 0
1619 18:11:38.293291 8, 0xFFFF, sum = 0
1620 18:11:38.293364 9, 0x0, sum = 1
1621 18:11:38.293421 10, 0x0, sum = 2
1622 18:11:38.293475 11, 0x0, sum = 3
1623 18:11:38.293528 12, 0x0, sum = 4
1624 18:11:38.293581 best_step = 10
1625 18:11:38.293633
1626 18:11:38.293686 ==
1627 18:11:38.293737 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 18:11:38.293790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 18:11:38.293843 ==
1630 18:11:38.293896 RX Vref Scan: 1
1631 18:11:38.293948
1632 18:11:38.294000 Set Vref Range= 32 -> 127
1633 18:11:38.294053
1634 18:11:38.294104 RX Vref 32 -> 127, step: 1
1635 18:11:38.294156
1636 18:11:38.294208 RX Delay -95 -> 252, step: 8
1637 18:11:38.294260
1638 18:11:38.294312 Set Vref, RX VrefLevel [Byte0]: 32
1639 18:11:38.294364 [Byte1]: 32
1640 18:11:38.294416
1641 18:11:38.294468 Set Vref, RX VrefLevel [Byte0]: 33
1642 18:11:38.294520 [Byte1]: 33
1643 18:11:38.294572
1644 18:11:38.294624 Set Vref, RX VrefLevel [Byte0]: 34
1645 18:11:38.294676 [Byte1]: 34
1646 18:11:38.294728
1647 18:11:38.294780 Set Vref, RX VrefLevel [Byte0]: 35
1648 18:11:38.294833 [Byte1]: 35
1649 18:11:38.294886
1650 18:11:38.294938 Set Vref, RX VrefLevel [Byte0]: 36
1651 18:11:38.294990 [Byte1]: 36
1652 18:11:38.295042
1653 18:11:38.295095 Set Vref, RX VrefLevel [Byte0]: 37
1654 18:11:38.295147 [Byte1]: 37
1655 18:11:38.295199
1656 18:11:38.295251 Set Vref, RX VrefLevel [Byte0]: 38
1657 18:11:38.295304 [Byte1]: 38
1658 18:11:38.295356
1659 18:11:38.295407 Set Vref, RX VrefLevel [Byte0]: 39
1660 18:11:38.295459 [Byte1]: 39
1661 18:11:38.295511
1662 18:11:38.295563 Set Vref, RX VrefLevel [Byte0]: 40
1663 18:11:38.295615 [Byte1]: 40
1664 18:11:38.295666
1665 18:11:38.295718 Set Vref, RX VrefLevel [Byte0]: 41
1666 18:11:38.295770 [Byte1]: 41
1667 18:11:38.295822
1668 18:11:38.295874 Set Vref, RX VrefLevel [Byte0]: 42
1669 18:11:38.295926 [Byte1]: 42
1670 18:11:38.295978
1671 18:11:38.296030 Set Vref, RX VrefLevel [Byte0]: 43
1672 18:11:38.296081 [Byte1]: 43
1673 18:11:38.296133
1674 18:11:38.296185 Set Vref, RX VrefLevel [Byte0]: 44
1675 18:11:38.296237 [Byte1]: 44
1676 18:11:38.296288
1677 18:11:38.296340 Set Vref, RX VrefLevel [Byte0]: 45
1678 18:11:38.296392 [Byte1]: 45
1679 18:11:38.296444
1680 18:11:38.296496 Set Vref, RX VrefLevel [Byte0]: 46
1681 18:11:38.296559 [Byte1]: 46
1682 18:11:38.296649
1683 18:11:38.296701 Set Vref, RX VrefLevel [Byte0]: 47
1684 18:11:38.296753 [Byte1]: 47
1685 18:11:38.296804
1686 18:11:38.296856 Set Vref, RX VrefLevel [Byte0]: 48
1687 18:11:38.296933 [Byte1]: 48
1688 18:11:38.296989
1689 18:11:38.297041 Set Vref, RX VrefLevel [Byte0]: 49
1690 18:11:38.297095 [Byte1]: 49
1691 18:11:38.297147
1692 18:11:38.297203 Set Vref, RX VrefLevel [Byte0]: 50
1693 18:11:38.297257 [Byte1]: 50
1694 18:11:38.297309
1695 18:11:38.297361 Set Vref, RX VrefLevel [Byte0]: 51
1696 18:11:38.297413 [Byte1]: 51
1697 18:11:38.297466
1698 18:11:38.297518 Set Vref, RX VrefLevel [Byte0]: 52
1699 18:11:38.297569 [Byte1]: 52
1700 18:11:38.297622
1701 18:11:38.297868 Set Vref, RX VrefLevel [Byte0]: 53
1702 18:11:38.297927 [Byte1]: 53
1703 18:11:38.297982
1704 18:11:38.298035 Set Vref, RX VrefLevel [Byte0]: 54
1705 18:11:38.298088 [Byte1]: 54
1706 18:11:38.298141
1707 18:11:38.298193 Set Vref, RX VrefLevel [Byte0]: 55
1708 18:11:38.298245 [Byte1]: 55
1709 18:11:38.298298
1710 18:11:38.298350 Set Vref, RX VrefLevel [Byte0]: 56
1711 18:11:38.298402 [Byte1]: 56
1712 18:11:38.298455
1713 18:11:38.298507 Set Vref, RX VrefLevel [Byte0]: 57
1714 18:11:38.298559 [Byte1]: 57
1715 18:11:38.298611
1716 18:11:38.298664 Set Vref, RX VrefLevel [Byte0]: 58
1717 18:11:38.298716 [Byte1]: 58
1718 18:11:38.298768
1719 18:11:38.298820 Set Vref, RX VrefLevel [Byte0]: 59
1720 18:11:38.298872 [Byte1]: 59
1721 18:11:38.298924
1722 18:11:38.298976 Set Vref, RX VrefLevel [Byte0]: 60
1723 18:11:38.299028 [Byte1]: 60
1724 18:11:38.299080
1725 18:11:38.299133 Set Vref, RX VrefLevel [Byte0]: 61
1726 18:11:38.299185 [Byte1]: 61
1727 18:11:38.299237
1728 18:11:38.299289 Set Vref, RX VrefLevel [Byte0]: 62
1729 18:11:38.299341 [Byte1]: 62
1730 18:11:38.299394
1731 18:11:38.299446 Set Vref, RX VrefLevel [Byte0]: 63
1732 18:11:38.299498 [Byte1]: 63
1733 18:11:38.299551
1734 18:11:38.299611 Set Vref, RX VrefLevel [Byte0]: 64
1735 18:11:38.299665 [Byte1]: 64
1736 18:11:38.299718
1737 18:11:38.299769 Set Vref, RX VrefLevel [Byte0]: 65
1738 18:11:38.299821 [Byte1]: 65
1739 18:11:38.299883
1740 18:11:38.299975 Set Vref, RX VrefLevel [Byte0]: 66
1741 18:11:38.300058 [Byte1]: 66
1742 18:11:38.300140
1743 18:11:38.300221 Set Vref, RX VrefLevel [Byte0]: 67
1744 18:11:38.300303 [Byte1]: 67
1745 18:11:38.300384
1746 18:11:38.300465 Set Vref, RX VrefLevel [Byte0]: 68
1747 18:11:38.300554 [Byte1]: 68
1748 18:11:38.300648
1749 18:11:38.300701 Set Vref, RX VrefLevel [Byte0]: 69
1750 18:11:38.300754 [Byte1]: 69
1751 18:11:38.300806
1752 18:11:38.300858 Set Vref, RX VrefLevel [Byte0]: 70
1753 18:11:38.300910 [Byte1]: 70
1754 18:11:38.300963
1755 18:11:38.301015 Set Vref, RX VrefLevel [Byte0]: 71
1756 18:11:38.301067 [Byte1]: 71
1757 18:11:38.301119
1758 18:11:38.301171 Set Vref, RX VrefLevel [Byte0]: 72
1759 18:11:38.301223 [Byte1]: 72
1760 18:11:38.301276
1761 18:11:38.301327 Set Vref, RX VrefLevel [Byte0]: 73
1762 18:11:38.301380 [Byte1]: 73
1763 18:11:38.301432
1764 18:11:38.301484 Set Vref, RX VrefLevel [Byte0]: 74
1765 18:11:38.301535 [Byte1]: 74
1766 18:11:38.301587
1767 18:11:38.301639 Set Vref, RX VrefLevel [Byte0]: 75
1768 18:11:38.301692 [Byte1]: 75
1769 18:11:38.301744
1770 18:11:38.301796 Set Vref, RX VrefLevel [Byte0]: 76
1771 18:11:38.301848 [Byte1]: 76
1772 18:11:38.301900
1773 18:11:38.301952 Set Vref, RX VrefLevel [Byte0]: 77
1774 18:11:38.302005 [Byte1]: 77
1775 18:11:38.302058
1776 18:11:38.302110 Final RX Vref Byte 0 = 51 to rank0
1777 18:11:38.302162 Final RX Vref Byte 1 = 63 to rank0
1778 18:11:38.302215 Final RX Vref Byte 0 = 51 to rank1
1779 18:11:38.302267 Final RX Vref Byte 1 = 63 to rank1==
1780 18:11:38.302320 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 18:11:38.302373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 18:11:38.302426 ==
1783 18:11:38.302478 DQS Delay:
1784 18:11:38.302531 DQS0 = 0, DQS1 = 0
1785 18:11:38.302583 DQM Delay:
1786 18:11:38.302639 DQM0 = 90, DQM1 = 83
1787 18:11:38.302702 DQ Delay:
1788 18:11:38.302760 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =84
1789 18:11:38.302813 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =84
1790 18:11:38.302865 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1791 18:11:38.302918 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1792 18:11:38.302971
1793 18:11:38.303023
1794 18:11:38.303075 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1795 18:11:38.303137 CH1 RK0: MR19=606, MR18=2E4B
1796 18:11:38.303190 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1797 18:11:38.303243
1798 18:11:38.303322 ----->DramcWriteLeveling(PI) begin...
1799 18:11:38.303379 ==
1800 18:11:38.303432 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 18:11:38.303485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 18:11:38.303538 ==
1803 18:11:38.303591 Write leveling (Byte 0): 25 => 25
1804 18:11:38.303643 Write leveling (Byte 1): 30 => 30
1805 18:11:38.303695 DramcWriteLeveling(PI) end<-----
1806 18:11:38.303748
1807 18:11:38.303800 ==
1808 18:11:38.303852 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 18:11:38.303904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 18:11:38.303957 ==
1811 18:11:38.304010 [Gating] SW mode calibration
1812 18:11:38.304062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 18:11:38.304115 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 18:11:38.304169 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 18:11:38.304222 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1816 18:11:38.304275 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 18:11:38.304327 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 18:11:38.304379 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 18:11:38.304431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 18:11:38.304483 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 18:11:38.304535 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 18:11:38.304637 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 18:11:38.304690 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 18:11:38.304743 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 18:11:38.304796 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 18:11:38.304848 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 18:11:38.304901 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 18:11:38.304953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 18:11:38.305006 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 18:11:38.305059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 18:11:38.305112 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 18:11:38.305164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 18:11:38.305216 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 18:11:38.305462 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 18:11:38.305521 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 18:11:38.305575 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 18:11:38.305628 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 18:11:38.305681 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 18:11:38.305734 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1840 18:11:38.305787 0 9 8 | B1->B0 | 3434 3333 | 0 0 | (0 0) (1 1)
1841 18:11:38.305839 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 18:11:38.305891 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 18:11:38.305952 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 18:11:38.306006 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 18:11:38.306058 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 18:11:38.306110 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1847 18:11:38.306164 0 10 4 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (0 0)
1848 18:11:38.306217 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 18:11:38.306269 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 18:11:38.306321 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 18:11:38.306374 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 18:11:38.306427 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 18:11:38.306479 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 18:11:38.306531 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 18:11:38.306584 0 11 4 | B1->B0 | 3030 2f2f | 0 1 | (1 1) (0 0)
1856 18:11:38.306636 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 18:11:38.306688 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 18:11:38.306753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 18:11:38.306819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 18:11:38.306874 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 18:11:38.306926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 18:11:38.306978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 18:11:38.307035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1864 18:11:38.307103 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 18:11:38.307156 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 18:11:38.307209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 18:11:38.307261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 18:11:38.307313 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 18:11:38.307365 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 18:11:38.307417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 18:11:38.307470 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 18:11:38.307522 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 18:11:38.307574 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 18:11:38.307627 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 18:11:38.307679 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 18:11:38.307731 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 18:11:38.307784 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 18:11:38.307835 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 18:11:38.307888 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1880 18:11:38.307941 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 18:11:38.307994 Total UI for P1: 0, mck2ui 16
1882 18:11:38.308046 best dqsien dly found for B0: ( 0, 14, 6)
1883 18:11:38.308099 Total UI for P1: 0, mck2ui 16
1884 18:11:38.308151 best dqsien dly found for B1: ( 0, 14, 4)
1885 18:11:38.308204 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1886 18:11:38.308257 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 18:11:38.308309
1888 18:11:38.308360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1889 18:11:38.308412 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 18:11:38.308464 [Gating] SW calibration Done
1891 18:11:38.308516 ==
1892 18:11:38.308615 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 18:11:38.308683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 18:11:38.308736 ==
1895 18:11:38.308789 RX Vref Scan: 0
1896 18:11:38.308841
1897 18:11:38.308893 RX Vref 0 -> 0, step: 1
1898 18:11:38.308946
1899 18:11:38.308998 RX Delay -130 -> 252, step: 16
1900 18:11:38.309051 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1901 18:11:38.309104 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1902 18:11:38.309156 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1903 18:11:38.309209 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1904 18:11:38.309260 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1905 18:11:38.309312 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1906 18:11:38.309364 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1907 18:11:38.309417 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1908 18:11:38.309468 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1909 18:11:38.309520 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1910 18:11:38.309573 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 18:11:38.309625 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1912 18:11:38.309677 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1913 18:11:38.309738 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1914 18:11:38.309812 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 18:11:38.309867 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1916 18:11:38.309920 ==
1917 18:11:38.309972 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 18:11:38.475086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 18:11:38.475376 ==
1920 18:11:38.475557 DQS Delay:
1921 18:11:38.475726 DQS0 = 0, DQS1 = 0
1922 18:11:38.475890 DQM Delay:
1923 18:11:38.476049 DQM0 = 87, DQM1 = 79
1924 18:11:38.476204 DQ Delay:
1925 18:11:38.476358 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1926 18:11:38.476511 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1927 18:11:38.476747 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1928 18:11:38.476944 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1929 18:11:38.477130
1930 18:11:38.477314
1931 18:11:38.477496 ==
1932 18:11:38.477677 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 18:11:38.477865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 18:11:38.478049 ==
1935 18:11:38.478230
1936 18:11:38.478408
1937 18:11:38.478588 TX Vref Scan disable
1938 18:11:38.479205 == TX Byte 0 ==
1939 18:11:38.479666 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1940 18:11:38.480109 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1941 18:11:38.480570 == TX Byte 1 ==
1942 18:11:38.481008 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1943 18:11:38.481448 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1944 18:11:38.481880 ==
1945 18:11:38.482309 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 18:11:38.482739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 18:11:38.483168 ==
1948 18:11:38.483420 TX Vref=22, minBit 13, minWin=27, winSum=451
1949 18:11:38.483620 TX Vref=24, minBit 15, minWin=27, winSum=455
1950 18:11:38.483812 TX Vref=26, minBit 13, minWin=27, winSum=454
1951 18:11:38.484001 TX Vref=28, minBit 8, minWin=28, winSum=460
1952 18:11:38.484185 TX Vref=30, minBit 8, minWin=28, winSum=461
1953 18:11:38.484371 TX Vref=32, minBit 9, minWin=27, winSum=458
1954 18:11:38.484579 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1955 18:11:38.484776
1956 18:11:38.484960 Final TX Range 1 Vref 30
1957 18:11:38.485144
1958 18:11:38.485326 ==
1959 18:11:38.485508 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 18:11:38.485691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 18:11:38.485877 ==
1962 18:11:38.486058
1963 18:11:38.486240
1964 18:11:38.486419 TX Vref Scan disable
1965 18:11:38.486599 == TX Byte 0 ==
1966 18:11:38.486780 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1967 18:11:38.486962 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1968 18:11:38.487144 == TX Byte 1 ==
1969 18:11:38.487323 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1970 18:11:38.487505 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1971 18:11:38.487687
1972 18:11:38.487867 [DATLAT]
1973 18:11:38.488046 Freq=800, CH1 RK1
1974 18:11:38.488227
1975 18:11:38.488407 DATLAT Default: 0xa
1976 18:11:38.488614 0, 0xFFFF, sum = 0
1977 18:11:38.488806 1, 0xFFFF, sum = 0
1978 18:11:38.489011 2, 0xFFFF, sum = 0
1979 18:11:38.489199 3, 0xFFFF, sum = 0
1980 18:11:38.489382 4, 0xFFFF, sum = 0
1981 18:11:38.489566 5, 0xFFFF, sum = 0
1982 18:11:38.489749 6, 0xFFFF, sum = 0
1983 18:11:38.489932 7, 0xFFFF, sum = 0
1984 18:11:38.490115 8, 0xFFFF, sum = 0
1985 18:11:38.490299 9, 0x0, sum = 1
1986 18:11:38.490480 10, 0x0, sum = 2
1987 18:11:38.490664 11, 0x0, sum = 3
1988 18:11:38.490846 12, 0x0, sum = 4
1989 18:11:38.491052 best_step = 10
1990 18:11:38.491239
1991 18:11:38.491418 ==
1992 18:11:38.491599 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 18:11:38.491781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 18:11:38.491963 ==
1995 18:11:38.492144 RX Vref Scan: 0
1996 18:11:38.492324
1997 18:11:38.492510 RX Vref 0 -> 0, step: 1
1998 18:11:38.492711
1999 18:11:38.492900 RX Delay -95 -> 252, step: 8
2000 18:11:38.493090 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2001 18:11:38.493282 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2002 18:11:38.493470 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2003 18:11:38.493662 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2004 18:11:38.493848 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2005 18:11:38.494036 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2006 18:11:38.494224 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2007 18:11:38.494412 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2008 18:11:38.494600 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 18:11:38.494789 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2010 18:11:38.494975 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2011 18:11:38.495163 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 18:11:38.495350 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2013 18:11:38.495540 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2014 18:11:38.495726 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 18:11:38.495915 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2016 18:11:38.496101 ==
2017 18:11:38.496288 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 18:11:38.496475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 18:11:38.496677 ==
2020 18:11:38.496867 DQS Delay:
2021 18:11:38.497054 DQS0 = 0, DQS1 = 0
2022 18:11:38.497241 DQM Delay:
2023 18:11:38.497428 DQM0 = 90, DQM1 = 82
2024 18:11:38.497614 DQ Delay:
2025 18:11:38.497801 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2026 18:11:38.497989 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2027 18:11:38.498177 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2028 18:11:38.498367 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2029 18:11:38.498552
2030 18:11:38.498737
2031 18:11:38.498923 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2032 18:11:38.499114 CH1 RK1: MR19=606, MR18=3B10
2033 18:11:38.499302 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2034 18:11:38.499493 [RxdqsGatingPostProcess] freq 800
2035 18:11:38.499678 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 18:11:38.499866 Pre-setting of DQS Precalculation
2037 18:11:38.500053 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 18:11:38.500242 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 18:11:38.500431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 18:11:38.500632
2041 18:11:38.500820
2042 18:11:38.501006 [Calibration Summary] 1600 Mbps
2043 18:11:38.501193 CH 0, Rank 0
2044 18:11:38.501379 SW Impedance : PASS
2045 18:11:38.501568 DUTY Scan : NO K
2046 18:11:38.501754 ZQ Calibration : PASS
2047 18:11:38.501941 Jitter Meter : NO K
2048 18:11:38.502128 CBT Training : PASS
2049 18:11:38.502317 Write leveling : PASS
2050 18:11:38.502505 RX DQS gating : PASS
2051 18:11:38.502692 RX DQ/DQS(RDDQC) : PASS
2052 18:11:38.502877 TX DQ/DQS : PASS
2053 18:11:38.503066 RX DATLAT : PASS
2054 18:11:38.503253 RX DQ/DQS(Engine): PASS
2055 18:11:38.503440 TX OE : NO K
2056 18:11:38.503627 All Pass.
2057 18:11:38.503813
2058 18:11:38.503998 CH 0, Rank 1
2059 18:11:38.504186 SW Impedance : PASS
2060 18:11:38.504373 DUTY Scan : NO K
2061 18:11:38.504569 ZQ Calibration : PASS
2062 18:11:38.504761 Jitter Meter : NO K
2063 18:11:38.504947 CBT Training : PASS
2064 18:11:38.505134 Write leveling : PASS
2065 18:11:38.505320 RX DQS gating : PASS
2066 18:11:38.505508 RX DQ/DQS(RDDQC) : PASS
2067 18:11:38.505696 TX DQ/DQS : PASS
2068 18:11:38.505884 RX DATLAT : PASS
2069 18:11:38.506069 RX DQ/DQS(Engine): PASS
2070 18:11:38.506262 TX OE : NO K
2071 18:11:38.506479 All Pass.
2072 18:11:38.506664
2073 18:11:38.506807 CH 1, Rank 0
2074 18:11:38.506953 SW Impedance : PASS
2075 18:11:38.507098 DUTY Scan : NO K
2076 18:11:38.507242 ZQ Calibration : PASS
2077 18:11:38.507384 Jitter Meter : NO K
2078 18:11:38.507527 CBT Training : PASS
2079 18:11:38.507670 Write leveling : PASS
2080 18:11:38.507814 RX DQS gating : PASS
2081 18:11:38.507957 RX DQ/DQS(RDDQC) : PASS
2082 18:11:38.508099 TX DQ/DQS : PASS
2083 18:11:38.508515 RX DATLAT : PASS
2084 18:11:38.508888 RX DQ/DQS(Engine): PASS
2085 18:11:38.509226 TX OE : NO K
2086 18:11:38.509561 All Pass.
2087 18:11:38.509891
2088 18:11:38.510089 CH 1, Rank 1
2089 18:11:38.510241 SW Impedance : PASS
2090 18:11:38.510390 DUTY Scan : NO K
2091 18:11:38.510536 ZQ Calibration : PASS
2092 18:11:38.510691 Jitter Meter : NO K
2093 18:11:38.510840 CBT Training : PASS
2094 18:11:38.510985 Write leveling : PASS
2095 18:11:38.511130 RX DQS gating : PASS
2096 18:11:38.511274 RX DQ/DQS(RDDQC) : PASS
2097 18:11:38.511417 TX DQ/DQS : PASS
2098 18:11:38.511561 RX DATLAT : PASS
2099 18:11:38.511698 RX DQ/DQS(Engine): PASS
2100 18:11:38.511815 TX OE : NO K
2101 18:11:38.511932 All Pass.
2102 18:11:38.512049
2103 18:11:38.512166 DramC Write-DBI off
2104 18:11:38.512283 PER_BANK_REFRESH: Hybrid Mode
2105 18:11:38.512400 TX_TRACKING: ON
2106 18:11:38.512516 [GetDramInforAfterCalByMRR] Vendor 6.
2107 18:11:38.512642 [GetDramInforAfterCalByMRR] Revision 606.
2108 18:11:38.512780 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 18:11:38.512901 MR0 0x3b3b
2110 18:11:38.513019 MR8 0x5151
2111 18:11:38.513137 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 18:11:38.513262
2113 18:11:38.513378 MR0 0x3b3b
2114 18:11:38.513493 MR8 0x5151
2115 18:11:38.513608 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 18:11:38.513726
2117 18:11:38.513843 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 18:11:38.513963 [FAST_K] Save calibration result to emmc
2119 18:11:38.514080 [FAST_K] Save calibration result to emmc
2120 18:11:38.514198 dram_init: config_dvfs: 1
2121 18:11:38.514315 dramc_set_vcore_voltage set vcore to 662500
2122 18:11:38.514433 Read voltage for 1200, 2
2123 18:11:38.514549 Vio18 = 0
2124 18:11:38.514665 Vcore = 662500
2125 18:11:38.514781 Vdram = 0
2126 18:11:38.514899 Vddq = 0
2127 18:11:38.515014 Vmddr = 0
2128 18:11:38.515130 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 18:11:38.515247 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 18:11:38.515365 MEM_TYPE=3, freq_sel=15
2131 18:11:38.515480 sv_algorithm_assistance_LP4_1600
2132 18:11:38.515596 ============ PULL DRAM RESETB DOWN ============
2133 18:11:38.515714 ========== PULL DRAM RESETB DOWN end =========
2134 18:11:38.515831 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 18:11:38.515947 ===================================
2136 18:11:38.516063 LPDDR4 DRAM CONFIGURATION
2137 18:11:38.516179 ===================================
2138 18:11:38.516295 EX_ROW_EN[0] = 0x0
2139 18:11:38.516411 EX_ROW_EN[1] = 0x0
2140 18:11:38.516526 LP4Y_EN = 0x0
2141 18:11:38.516672 WORK_FSP = 0x0
2142 18:11:38.516771 WL = 0x4
2143 18:11:38.516870 RL = 0x4
2144 18:11:38.516967 BL = 0x2
2145 18:11:38.517064 RPST = 0x0
2146 18:11:38.517161 RD_PRE = 0x0
2147 18:11:38.517258 WR_PRE = 0x1
2148 18:11:38.517355 WR_PST = 0x0
2149 18:11:38.517452 DBI_WR = 0x0
2150 18:11:38.517550 DBI_RD = 0x0
2151 18:11:38.517648 OTF = 0x1
2152 18:11:38.517746 ===================================
2153 18:11:38.517844 ===================================
2154 18:11:38.517942 ANA top config
2155 18:11:38.518039 ===================================
2156 18:11:38.518137 DLL_ASYNC_EN = 0
2157 18:11:38.518235 ALL_SLAVE_EN = 0
2158 18:11:38.518334 NEW_RANK_MODE = 1
2159 18:11:38.518433 DLL_IDLE_MODE = 1
2160 18:11:38.518530 LP45_APHY_COMB_EN = 1
2161 18:11:38.518628 TX_ODT_DIS = 1
2162 18:11:38.518727 NEW_8X_MODE = 1
2163 18:11:38.518826 ===================================
2164 18:11:38.518925 ===================================
2165 18:11:38.519024 data_rate = 2400
2166 18:11:38.519121 CKR = 1
2167 18:11:38.519220 DQ_P2S_RATIO = 8
2168 18:11:38.519317 ===================================
2169 18:11:38.519416 CA_P2S_RATIO = 8
2170 18:11:38.519514 DQ_CA_OPEN = 0
2171 18:11:38.519611 DQ_SEMI_OPEN = 0
2172 18:11:38.519708 CA_SEMI_OPEN = 0
2173 18:11:38.519806 CA_FULL_RATE = 0
2174 18:11:38.519902 DQ_CKDIV4_EN = 0
2175 18:11:38.520000 CA_CKDIV4_EN = 0
2176 18:11:38.520097 CA_PREDIV_EN = 0
2177 18:11:38.520195 PH8_DLY = 17
2178 18:11:38.520293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 18:11:38.520390 DQ_AAMCK_DIV = 4
2180 18:11:38.520488 CA_AAMCK_DIV = 4
2181 18:11:38.520597 CA_ADMCK_DIV = 4
2182 18:11:38.520696 DQ_TRACK_CA_EN = 0
2183 18:11:38.520794 CA_PICK = 1200
2184 18:11:38.520893 CA_MCKIO = 1200
2185 18:11:38.520991 MCKIO_SEMI = 0
2186 18:11:38.521089 PLL_FREQ = 2366
2187 18:11:38.521186 DQ_UI_PI_RATIO = 32
2188 18:11:38.521284 CA_UI_PI_RATIO = 0
2189 18:11:38.521382 ===================================
2190 18:11:38.521481 ===================================
2191 18:11:38.521579 memory_type:LPDDR4
2192 18:11:38.521681 GP_NUM : 10
2193 18:11:38.521766 SRAM_EN : 1
2194 18:11:38.521850 MD32_EN : 0
2195 18:11:38.521933 ===================================
2196 18:11:38.522018 [ANA_INIT] >>>>>>>>>>>>>>
2197 18:11:38.522102 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 18:11:38.522188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 18:11:38.522272 ===================================
2200 18:11:38.522357 data_rate = 2400,PCW = 0X5b00
2201 18:11:38.522443 ===================================
2202 18:11:38.522527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 18:11:38.522613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 18:11:38.522697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 18:11:38.522783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 18:11:38.522868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 18:11:38.522956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 18:11:38.523042 [ANA_INIT] flow start
2209 18:11:38.523127 [ANA_INIT] PLL >>>>>>>>
2210 18:11:38.523212 [ANA_INIT] PLL <<<<<<<<
2211 18:11:38.523297 [ANA_INIT] MIDPI >>>>>>>>
2212 18:11:38.523380 [ANA_INIT] MIDPI <<<<<<<<
2213 18:11:38.523465 [ANA_INIT] DLL >>>>>>>>
2214 18:11:38.523549 [ANA_INIT] DLL <<<<<<<<
2215 18:11:38.523633 [ANA_INIT] flow end
2216 18:11:38.523717 ============ LP4 DIFF to SE enter ============
2217 18:11:38.523803 ============ LP4 DIFF to SE exit ============
2218 18:11:38.523888 [ANA_INIT] <<<<<<<<<<<<<
2219 18:11:38.523973 [Flow] Enable top DCM control >>>>>
2220 18:11:38.524278 [Flow] Enable top DCM control <<<<<
2221 18:11:38.524377 Enable DLL master slave shuffle
2222 18:11:38.524465 ==============================================================
2223 18:11:38.524565 Gating Mode config
2224 18:11:38.524655 ==============================================================
2225 18:11:38.524742 Config description:
2226 18:11:38.524827 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 18:11:38.524914 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 18:11:38.525001 SELPH_MODE 0: By rank 1: By Phase
2229 18:11:38.525087 ==============================================================
2230 18:11:38.525173 GAT_TRACK_EN = 1
2231 18:11:38.525258 RX_GATING_MODE = 2
2232 18:11:38.525342 RX_GATING_TRACK_MODE = 2
2233 18:11:38.525428 SELPH_MODE = 1
2234 18:11:38.525513 PICG_EARLY_EN = 1
2235 18:11:38.525598 VALID_LAT_VALUE = 1
2236 18:11:38.525683 ==============================================================
2237 18:11:38.525768 Enter into Gating configuration >>>>
2238 18:11:38.525853 Exit from Gating configuration <<<<
2239 18:11:38.525938 Enter into DVFS_PRE_config >>>>>
2240 18:11:38.526023 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 18:11:38.526110 Exit from DVFS_PRE_config <<<<<
2242 18:11:38.526195 Enter into PICG configuration >>>>
2243 18:11:38.526280 Exit from PICG configuration <<<<
2244 18:11:38.526365 [RX_INPUT] configuration >>>>>
2245 18:11:38.526450 [RX_INPUT] configuration <<<<<
2246 18:11:38.526535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 18:11:38.526629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 18:11:38.526704 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 18:11:38.526779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 18:11:38.526854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 18:11:38.526929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 18:11:38.527022 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 18:11:38.527099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 18:11:38.527174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 18:11:38.527250 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 18:11:38.527324 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 18:11:38.527399 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 18:11:38.527473 ===================================
2259 18:11:38.527549 LPDDR4 DRAM CONFIGURATION
2260 18:11:38.527623 ===================================
2261 18:11:38.527697 EX_ROW_EN[0] = 0x0
2262 18:11:38.527772 EX_ROW_EN[1] = 0x0
2263 18:11:38.527846 LP4Y_EN = 0x0
2264 18:11:38.527920 WORK_FSP = 0x0
2265 18:11:38.527994 WL = 0x4
2266 18:11:38.528068 RL = 0x4
2267 18:11:38.528142 BL = 0x2
2268 18:11:38.528215 RPST = 0x0
2269 18:11:38.528289 RD_PRE = 0x0
2270 18:11:38.528363 WR_PRE = 0x1
2271 18:11:38.528437 WR_PST = 0x0
2272 18:11:38.528511 DBI_WR = 0x0
2273 18:11:38.528596 DBI_RD = 0x0
2274 18:11:38.528672 OTF = 0x1
2275 18:11:38.528747 ===================================
2276 18:11:38.528822 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 18:11:38.528896 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 18:11:38.528972 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 18:11:38.529047 ===================================
2280 18:11:38.529122 LPDDR4 DRAM CONFIGURATION
2281 18:11:38.529196 ===================================
2282 18:11:38.529269 EX_ROW_EN[0] = 0x10
2283 18:11:38.529344 EX_ROW_EN[1] = 0x0
2284 18:11:38.529417 LP4Y_EN = 0x0
2285 18:11:38.529491 WORK_FSP = 0x0
2286 18:11:38.529565 WL = 0x4
2287 18:11:38.529639 RL = 0x4
2288 18:11:38.529713 BL = 0x2
2289 18:11:38.529787 RPST = 0x0
2290 18:11:38.529860 RD_PRE = 0x0
2291 18:11:38.529934 WR_PRE = 0x1
2292 18:11:38.530008 WR_PST = 0x0
2293 18:11:38.530082 DBI_WR = 0x0
2294 18:11:38.530155 DBI_RD = 0x0
2295 18:11:38.530226 OTF = 0x1
2296 18:11:38.530299 ===================================
2297 18:11:38.530372 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 18:11:38.530445 ==
2299 18:11:38.530516 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 18:11:38.530589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 18:11:38.530661 ==
2302 18:11:38.530733 [Duty_Offset_Calibration]
2303 18:11:38.530805 B0:2 B1:0 CA:1
2304 18:11:38.530893
2305 18:11:38.530970 [DutyScan_Calibration_Flow] k_type=0
2306 18:11:38.531043
2307 18:11:38.531114 ==CLK 0==
2308 18:11:38.531186 Final CLK duty delay cell = -4
2309 18:11:38.531259 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2310 18:11:38.531332 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2311 18:11:38.531420 [-4] AVG Duty = 4953%(X100)
2312 18:11:38.531493
2313 18:11:38.531564 CH0 CLK Duty spec in!! Max-Min= 156%
2314 18:11:38.531645 [DutyScan_Calibration_Flow] ====Done====
2315 18:11:38.531710
2316 18:11:38.531773 [DutyScan_Calibration_Flow] k_type=1
2317 18:11:38.531838
2318 18:11:38.531901 ==DQS 0 ==
2319 18:11:38.531965 Final DQS duty delay cell = 0
2320 18:11:38.532030 [0] MAX Duty = 5187%(X100), DQS PI = 30
2321 18:11:38.532095 [0] MIN Duty = 4938%(X100), DQS PI = 0
2322 18:11:38.532159 [0] AVG Duty = 5062%(X100)
2323 18:11:38.532224
2324 18:11:38.532287 ==DQS 1 ==
2325 18:11:38.532351 Final DQS duty delay cell = -4
2326 18:11:38.532415 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2327 18:11:38.532480 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2328 18:11:38.532544 [-4] AVG Duty = 5015%(X100)
2329 18:11:38.532613
2330 18:11:38.532697 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2331 18:11:38.532763
2332 18:11:38.532828 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2333 18:11:38.532892 [DutyScan_Calibration_Flow] ====Done====
2334 18:11:38.532957
2335 18:11:38.533022 [DutyScan_Calibration_Flow] k_type=3
2336 18:11:38.533088
2337 18:11:38.533152 ==DQM 0 ==
2338 18:11:38.533216 Final DQM duty delay cell = 0
2339 18:11:38.533280 [0] MAX Duty = 5062%(X100), DQS PI = 24
2340 18:11:38.533345 [0] MIN Duty = 4813%(X100), DQS PI = 0
2341 18:11:38.533621 [0] AVG Duty = 4937%(X100)
2342 18:11:38.533783
2343 18:11:38.533935 ==DQM 1 ==
2344 18:11:38.534089 Final DQM duty delay cell = 0
2345 18:11:38.534243 [0] MAX Duty = 5187%(X100), DQS PI = 46
2346 18:11:38.534398 [0] MIN Duty = 4969%(X100), DQS PI = 24
2347 18:11:38.534551 [0] AVG Duty = 5078%(X100)
2348 18:11:38.534704
2349 18:11:38.534857 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2350 18:11:38.534946
2351 18:11:38.535014 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2352 18:11:38.535080 [DutyScan_Calibration_Flow] ====Done====
2353 18:11:38.535146
2354 18:11:38.535211 [DutyScan_Calibration_Flow] k_type=2
2355 18:11:38.535277
2356 18:11:38.535341 ==DQ 0 ==
2357 18:11:38.535407 Final DQ duty delay cell = 0
2358 18:11:38.535472 [0] MAX Duty = 5125%(X100), DQS PI = 32
2359 18:11:38.535537 [0] MIN Duty = 5000%(X100), DQS PI = 0
2360 18:11:38.535602 [0] AVG Duty = 5062%(X100)
2361 18:11:38.535667
2362 18:11:38.535731 ==DQ 1 ==
2363 18:11:38.535796 Final DQ duty delay cell = 4
2364 18:11:38.535861 [4] MAX Duty = 5093%(X100), DQS PI = 6
2365 18:11:38.535926 [4] MIN Duty = 5031%(X100), DQS PI = 0
2366 18:11:38.535991 [4] AVG Duty = 5062%(X100)
2367 18:11:38.536054
2368 18:11:38.536118 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2369 18:11:38.536183
2370 18:11:38.536247 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2371 18:11:38.536311 [DutyScan_Calibration_Flow] ====Done====
2372 18:11:38.536376 ==
2373 18:11:38.536440 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 18:11:38.536505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 18:11:38.536582 ==
2376 18:11:38.536657 [Duty_Offset_Calibration]
2377 18:11:38.536716 B0:0 B1:-1 CA:2
2378 18:11:38.536773
2379 18:11:38.536833 [DutyScan_Calibration_Flow] k_type=0
2380 18:11:38.536891
2381 18:11:38.536949 ==CLK 0==
2382 18:11:38.537006 Final CLK duty delay cell = 0
2383 18:11:38.537065 [0] MAX Duty = 5156%(X100), DQS PI = 18
2384 18:11:38.537123 [0] MIN Duty = 4938%(X100), DQS PI = 44
2385 18:11:38.537181 [0] AVG Duty = 5047%(X100)
2386 18:11:38.537239
2387 18:11:38.537296 CH1 CLK Duty spec in!! Max-Min= 218%
2388 18:11:38.537355 [DutyScan_Calibration_Flow] ====Done====
2389 18:11:38.537413
2390 18:11:38.537471 [DutyScan_Calibration_Flow] k_type=1
2391 18:11:38.537530
2392 18:11:38.537588 ==DQS 0 ==
2393 18:11:38.537646 Final DQS duty delay cell = 0
2394 18:11:38.537704 [0] MAX Duty = 5093%(X100), DQS PI = 24
2395 18:11:38.537763 [0] MIN Duty = 4969%(X100), DQS PI = 0
2396 18:11:38.537821 [0] AVG Duty = 5031%(X100)
2397 18:11:38.537878
2398 18:11:38.537936 ==DQS 1 ==
2399 18:11:38.537993 Final DQS duty delay cell = 0
2400 18:11:38.538052 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 18:11:38.538110 [0] MIN Duty = 4844%(X100), DQS PI = 36
2402 18:11:38.538167 [0] AVG Duty = 5000%(X100)
2403 18:11:38.538225
2404 18:11:38.538283 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2405 18:11:38.538340
2406 18:11:38.538398 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2407 18:11:38.538455 [DutyScan_Calibration_Flow] ====Done====
2408 18:11:38.538514
2409 18:11:38.538571 [DutyScan_Calibration_Flow] k_type=3
2410 18:11:38.538629
2411 18:11:38.538687 ==DQM 0 ==
2412 18:11:38.538745 Final DQM duty delay cell = 4
2413 18:11:38.538803 [4] MAX Duty = 5093%(X100), DQS PI = 22
2414 18:11:38.538862 [4] MIN Duty = 4938%(X100), DQS PI = 44
2415 18:11:38.538919 [4] AVG Duty = 5015%(X100)
2416 18:11:38.538977
2417 18:11:38.539035 ==DQM 1 ==
2418 18:11:38.539093 Final DQM duty delay cell = 0
2419 18:11:38.539151 [0] MAX Duty = 5249%(X100), DQS PI = 60
2420 18:11:38.539209 [0] MIN Duty = 4875%(X100), DQS PI = 36
2421 18:11:38.539267 [0] AVG Duty = 5062%(X100)
2422 18:11:38.539325
2423 18:11:38.539383 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2424 18:11:38.539440
2425 18:11:38.539497 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2426 18:11:38.539555 [DutyScan_Calibration_Flow] ====Done====
2427 18:11:38.539613
2428 18:11:38.539671 [DutyScan_Calibration_Flow] k_type=2
2429 18:11:38.539729
2430 18:11:38.539787 ==DQ 0 ==
2431 18:11:38.539845 Final DQ duty delay cell = 0
2432 18:11:38.539904 [0] MAX Duty = 5031%(X100), DQS PI = 16
2433 18:11:38.539962 [0] MIN Duty = 4938%(X100), DQS PI = 30
2434 18:11:38.540020 [0] AVG Duty = 4984%(X100)
2435 18:11:38.540078
2436 18:11:38.540135 ==DQ 1 ==
2437 18:11:38.540193 Final DQ duty delay cell = 0
2438 18:11:38.540252 [0] MAX Duty = 5031%(X100), DQS PI = 2
2439 18:11:38.540310 [0] MIN Duty = 4782%(X100), DQS PI = 36
2440 18:11:38.540368 [0] AVG Duty = 4906%(X100)
2441 18:11:38.540426
2442 18:11:38.540483 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2443 18:11:38.540541
2444 18:11:38.540608 CH1 DQ 1 Duty spec in!! Max-Min= 249%
2445 18:11:38.540667 [DutyScan_Calibration_Flow] ====Done====
2446 18:11:38.540724 nWR fixed to 30
2447 18:11:38.540783 [ModeRegInit_LP4] CH0 RK0
2448 18:11:38.540841 [ModeRegInit_LP4] CH0 RK1
2449 18:11:38.540899 [ModeRegInit_LP4] CH1 RK0
2450 18:11:38.540956 [ModeRegInit_LP4] CH1 RK1
2451 18:11:38.541014 match AC timing 7
2452 18:11:38.541072 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 18:11:38.541131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 18:11:38.541189 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 18:11:38.541248 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 18:11:38.541306 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 18:11:38.541364 ==
2458 18:11:38.541422 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 18:11:38.541481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 18:11:38.541540 ==
2461 18:11:38.541598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 18:11:38.541668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2463 18:11:38.541722 [CA 0] Center 38 (8~69) winsize 62
2464 18:11:38.541775 [CA 1] Center 38 (8~69) winsize 62
2465 18:11:38.541828 [CA 2] Center 35 (5~66) winsize 62
2466 18:11:38.541881 [CA 3] Center 35 (4~66) winsize 63
2467 18:11:38.541934 [CA 4] Center 34 (4~65) winsize 62
2468 18:11:38.541987 [CA 5] Center 33 (3~63) winsize 61
2469 18:11:38.542039
2470 18:11:38.542092 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 18:11:38.542146
2472 18:11:38.542198 [CATrainingPosCal] consider 1 rank data
2473 18:11:38.542251 u2DelayCellTimex100 = 270/100 ps
2474 18:11:38.542304 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 18:11:38.542358 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2476 18:11:38.542411 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 18:11:38.542465 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2478 18:11:38.542517 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2479 18:11:38.542581 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2480 18:11:38.542635
2481 18:11:38.542688 CA PerBit enable=1, Macro0, CA PI delay=33
2482 18:11:38.542741
2483 18:11:38.542794 [CBTSetCACLKResult] CA Dly = 33
2484 18:11:38.542847 CS Dly: 6 (0~37)
2485 18:11:38.542900 ==
2486 18:11:38.542953 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 18:11:38.543007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 18:11:38.543060 ==
2489 18:11:38.543113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 18:11:38.543365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2491 18:11:38.543427 [CA 0] Center 39 (8~70) winsize 63
2492 18:11:38.543482 [CA 1] Center 38 (8~69) winsize 62
2493 18:11:38.543541 [CA 2] Center 35 (5~66) winsize 62
2494 18:11:38.543595 [CA 3] Center 35 (5~66) winsize 62
2495 18:11:38.543649 [CA 4] Center 34 (4~65) winsize 62
2496 18:11:38.543702 [CA 5] Center 34 (4~64) winsize 61
2497 18:11:38.543755
2498 18:11:38.543808 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2499 18:11:38.543862
2500 18:11:38.543914 [CATrainingPosCal] consider 2 rank data
2501 18:11:38.543967 u2DelayCellTimex100 = 270/100 ps
2502 18:11:38.544022 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 18:11:38.544075 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 18:11:38.544128 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 18:11:38.544181 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 18:11:38.544235 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2507 18:11:38.544288 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2508 18:11:38.544341
2509 18:11:38.544394 CA PerBit enable=1, Macro0, CA PI delay=33
2510 18:11:38.544448
2511 18:11:38.544500 [CBTSetCACLKResult] CA Dly = 33
2512 18:11:38.544559 CS Dly: 7 (0~39)
2513 18:11:38.544613
2514 18:11:38.544666 ----->DramcWriteLeveling(PI) begin...
2515 18:11:38.544720 ==
2516 18:11:38.544773 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 18:11:38.544826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 18:11:38.544881 ==
2519 18:11:38.544934 Write leveling (Byte 0): 35 => 35
2520 18:11:38.544988 Write leveling (Byte 1): 30 => 30
2521 18:11:38.545041 DramcWriteLeveling(PI) end<-----
2522 18:11:38.545094
2523 18:11:38.545148 ==
2524 18:11:38.545201 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 18:11:38.545254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 18:11:38.545307 ==
2527 18:11:38.545361 [Gating] SW mode calibration
2528 18:11:38.545414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 18:11:38.545469 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 18:11:38.545522 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 18:11:38.545576 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2532 18:11:38.545630 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 18:11:38.545683 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 18:11:38.545737 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 18:11:38.545790 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 18:11:38.545843 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2537 18:11:38.545896 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2538 18:11:38.545949 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2539 18:11:38.546002 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 18:11:38.546056 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 18:11:38.546110 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 18:11:38.546163 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 18:11:38.546216 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 18:11:38.546269 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2545 18:11:38.546322 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2546 18:11:38.546375 1 1 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2547 18:11:38.546427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 18:11:38.546480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 18:11:38.546533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 18:11:38.546586 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 18:11:38.546638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 18:11:38.546691 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 18:11:38.546744 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 18:11:38.546797 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 18:11:38.546850 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 18:11:38.546904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 18:11:38.546957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 18:11:38.547011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 18:11:38.547063 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 18:11:38.547116 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 18:11:38.547169 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 18:11:38.547221 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 18:11:38.547274 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 18:11:38.547327 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 18:11:38.547380 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 18:11:38.547433 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 18:11:38.547485 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 18:11:38.547538 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 18:11:38.547591 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 18:11:38.547644 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 18:11:38.547697 Total UI for P1: 0, mck2ui 16
2572 18:11:38.547750 best dqsien dly found for B0: ( 1, 3, 28)
2573 18:11:38.547804 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 18:11:38.547858 Total UI for P1: 0, mck2ui 16
2575 18:11:38.547911 best dqsien dly found for B1: ( 1, 4, 0)
2576 18:11:38.547964 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2577 18:11:38.548017 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2578 18:11:38.548070
2579 18:11:38.548122 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2580 18:11:38.548176 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 18:11:38.548228 [Gating] SW calibration Done
2582 18:11:38.548281 ==
2583 18:11:38.548334 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 18:11:38.548387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 18:11:38.548440 ==
2586 18:11:38.548493 RX Vref Scan: 0
2587 18:11:38.548548
2588 18:11:38.548635 RX Vref 0 -> 0, step: 1
2589 18:11:38.548688
2590 18:11:38.548741 RX Delay -40 -> 252, step: 8
2591 18:11:38.548794 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2592 18:11:38.548847 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2593 18:11:38.548901 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2594 18:11:38.548954 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2595 18:11:38.549203 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2596 18:11:38.549333 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2597 18:11:38.549458 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2598 18:11:38.549583 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2599 18:11:38.549709 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2600 18:11:38.549834 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2601 18:11:38.549959 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2602 18:11:38.550085 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2603 18:11:38.550210 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2604 18:11:38.550335 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2605 18:11:38.550407 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2606 18:11:38.550463 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2607 18:11:38.550517 ==
2608 18:11:38.550571 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 18:11:38.550625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 18:11:38.550680 ==
2611 18:11:38.550733 DQS Delay:
2612 18:11:38.550786 DQS0 = 0, DQS1 = 0
2613 18:11:38.550840 DQM Delay:
2614 18:11:38.550893 DQM0 = 122, DQM1 = 110
2615 18:11:38.550946 DQ Delay:
2616 18:11:38.550999 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2617 18:11:38.551052 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2618 18:11:38.551106 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2619 18:11:38.551160 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2620 18:11:38.551212
2621 18:11:38.551266
2622 18:11:38.551319 ==
2623 18:11:38.551371 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 18:11:38.551424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 18:11:38.551478 ==
2626 18:11:38.551531
2627 18:11:38.551588
2628 18:11:38.551641 TX Vref Scan disable
2629 18:11:38.551694 == TX Byte 0 ==
2630 18:11:38.551747 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2631 18:11:38.551802 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2632 18:11:38.551855 == TX Byte 1 ==
2633 18:11:38.551907 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2634 18:11:38.551960 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2635 18:11:38.552013 ==
2636 18:11:38.552066 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 18:11:38.552119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 18:11:38.552172 ==
2639 18:11:38.552225 TX Vref=22, minBit 0, minWin=24, winSum=410
2640 18:11:38.552279 TX Vref=24, minBit 1, minWin=24, winSum=412
2641 18:11:38.552332 TX Vref=26, minBit 7, minWin=24, winSum=418
2642 18:11:38.552385 TX Vref=28, minBit 5, minWin=25, winSum=422
2643 18:11:38.552438 TX Vref=30, minBit 3, minWin=25, winSum=426
2644 18:11:38.552491 TX Vref=32, minBit 1, minWin=25, winSum=420
2645 18:11:38.552545 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 30
2646 18:11:38.552640
2647 18:11:38.552693 Final TX Range 1 Vref 30
2648 18:11:38.552747
2649 18:11:38.552799 ==
2650 18:11:38.552851 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 18:11:38.552905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 18:11:38.552958 ==
2653 18:11:38.553011
2654 18:11:38.553063
2655 18:11:38.553116 TX Vref Scan disable
2656 18:11:38.553169 == TX Byte 0 ==
2657 18:11:38.553223 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2658 18:11:38.553277 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2659 18:11:38.553329 == TX Byte 1 ==
2660 18:11:38.553382 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2661 18:11:38.553435 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2662 18:11:38.553488
2663 18:11:38.553540 [DATLAT]
2664 18:11:38.553593 Freq=1200, CH0 RK0
2665 18:11:38.553646
2666 18:11:38.553698 DATLAT Default: 0xd
2667 18:11:38.553751 0, 0xFFFF, sum = 0
2668 18:11:38.553805 1, 0xFFFF, sum = 0
2669 18:11:38.553859 2, 0xFFFF, sum = 0
2670 18:11:38.553913 3, 0xFFFF, sum = 0
2671 18:11:38.553966 4, 0xFFFF, sum = 0
2672 18:11:38.554020 5, 0xFFFF, sum = 0
2673 18:11:38.554073 6, 0xFFFF, sum = 0
2674 18:11:38.554127 7, 0xFFFF, sum = 0
2675 18:11:38.554181 8, 0xFFFF, sum = 0
2676 18:11:38.554250 9, 0xFFFF, sum = 0
2677 18:11:38.554308 10, 0xFFFF, sum = 0
2678 18:11:38.554363 11, 0xFFFF, sum = 0
2679 18:11:38.554417 12, 0x0, sum = 1
2680 18:11:38.554471 13, 0x0, sum = 2
2681 18:11:38.554525 14, 0x0, sum = 3
2682 18:11:38.554578 15, 0x0, sum = 4
2683 18:11:38.554631 best_step = 13
2684 18:11:38.554683
2685 18:11:38.554735 ==
2686 18:11:38.554788 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 18:11:38.554841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 18:11:38.554895 ==
2689 18:11:38.554948 RX Vref Scan: 1
2690 18:11:38.555002
2691 18:11:38.555054 Set Vref Range= 32 -> 127
2692 18:11:38.555107
2693 18:11:38.555160 RX Vref 32 -> 127, step: 1
2694 18:11:38.555212
2695 18:11:38.555265 RX Delay -13 -> 252, step: 4
2696 18:11:38.555318
2697 18:11:38.555371 Set Vref, RX VrefLevel [Byte0]: 32
2698 18:11:38.555423 [Byte1]: 32
2699 18:11:38.555477
2700 18:11:38.555530 Set Vref, RX VrefLevel [Byte0]: 33
2701 18:11:38.555583 [Byte1]: 33
2702 18:11:38.555635
2703 18:11:38.555688 Set Vref, RX VrefLevel [Byte0]: 34
2704 18:11:38.555741 [Byte1]: 34
2705 18:11:38.555793
2706 18:11:38.555846 Set Vref, RX VrefLevel [Byte0]: 35
2707 18:11:38.555899 [Byte1]: 35
2708 18:11:38.555952
2709 18:11:38.556004 Set Vref, RX VrefLevel [Byte0]: 36
2710 18:11:38.556057 [Byte1]: 36
2711 18:11:38.556110
2712 18:11:38.556163 Set Vref, RX VrefLevel [Byte0]: 37
2713 18:11:38.556216 [Byte1]: 37
2714 18:11:38.556268
2715 18:11:38.556321 Set Vref, RX VrefLevel [Byte0]: 38
2716 18:11:38.556374 [Byte1]: 38
2717 18:11:38.556426
2718 18:11:38.556478 Set Vref, RX VrefLevel [Byte0]: 39
2719 18:11:38.556531 [Byte1]: 39
2720 18:11:38.556645
2721 18:11:38.556701 Set Vref, RX VrefLevel [Byte0]: 40
2722 18:11:38.556753 [Byte1]: 40
2723 18:11:38.556806
2724 18:11:38.556859 Set Vref, RX VrefLevel [Byte0]: 41
2725 18:11:38.556912 [Byte1]: 41
2726 18:11:38.556965
2727 18:11:38.557017 Set Vref, RX VrefLevel [Byte0]: 42
2728 18:11:38.557071 [Byte1]: 42
2729 18:11:38.557124
2730 18:11:38.557176 Set Vref, RX VrefLevel [Byte0]: 43
2731 18:11:38.557230 [Byte1]: 43
2732 18:11:38.557283
2733 18:11:38.557336 Set Vref, RX VrefLevel [Byte0]: 44
2734 18:11:38.557389 [Byte1]: 44
2735 18:11:38.557441
2736 18:11:38.557494 Set Vref, RX VrefLevel [Byte0]: 45
2737 18:11:38.557547 [Byte1]: 45
2738 18:11:38.557600
2739 18:11:38.557652 Set Vref, RX VrefLevel [Byte0]: 46
2740 18:11:38.557706 [Byte1]: 46
2741 18:11:38.557759
2742 18:11:38.557812 Set Vref, RX VrefLevel [Byte0]: 47
2743 18:11:38.557865 [Byte1]: 47
2744 18:11:38.557918
2745 18:11:38.557971 Set Vref, RX VrefLevel [Byte0]: 48
2746 18:11:38.558024 [Byte1]: 48
2747 18:11:38.558077
2748 18:11:38.558129 Set Vref, RX VrefLevel [Byte0]: 49
2749 18:11:38.558181 [Byte1]: 49
2750 18:11:38.558234
2751 18:11:38.558287 Set Vref, RX VrefLevel [Byte0]: 50
2752 18:11:38.558340 [Byte1]: 50
2753 18:11:38.558393
2754 18:11:38.558639 Set Vref, RX VrefLevel [Byte0]: 51
2755 18:11:38.558701 [Byte1]: 51
2756 18:11:38.558755
2757 18:11:38.558809 Set Vref, RX VrefLevel [Byte0]: 52
2758 18:11:38.558863 [Byte1]: 52
2759 18:11:38.558917
2760 18:11:38.558969 Set Vref, RX VrefLevel [Byte0]: 53
2761 18:11:38.559023 [Byte1]: 53
2762 18:11:38.559076
2763 18:11:38.559129 Set Vref, RX VrefLevel [Byte0]: 54
2764 18:11:38.559182 [Byte1]: 54
2765 18:11:38.559235
2766 18:11:38.559288 Set Vref, RX VrefLevel [Byte0]: 55
2767 18:11:38.559340 [Byte1]: 55
2768 18:11:38.559393
2769 18:11:38.559445 Set Vref, RX VrefLevel [Byte0]: 56
2770 18:11:38.559498 [Byte1]: 56
2771 18:11:38.559551
2772 18:11:38.559604 Set Vref, RX VrefLevel [Byte0]: 57
2773 18:11:38.559656 [Byte1]: 57
2774 18:11:38.559709
2775 18:11:38.559762 Set Vref, RX VrefLevel [Byte0]: 58
2776 18:11:38.559814 [Byte1]: 58
2777 18:11:38.559867
2778 18:11:38.559919 Set Vref, RX VrefLevel [Byte0]: 59
2779 18:11:38.559972 [Byte1]: 59
2780 18:11:38.560025
2781 18:11:38.560077 Set Vref, RX VrefLevel [Byte0]: 60
2782 18:11:38.560130 [Byte1]: 60
2783 18:11:38.560183
2784 18:11:38.560236 Set Vref, RX VrefLevel [Byte0]: 61
2785 18:11:38.560290 [Byte1]: 61
2786 18:11:38.560342
2787 18:11:38.560394 Set Vref, RX VrefLevel [Byte0]: 62
2788 18:11:38.560447 [Byte1]: 62
2789 18:11:38.560500
2790 18:11:38.560560 Set Vref, RX VrefLevel [Byte0]: 63
2791 18:11:38.560656 [Byte1]: 63
2792 18:11:38.560708
2793 18:11:38.560761 Set Vref, RX VrefLevel [Byte0]: 64
2794 18:11:38.560814 [Byte1]: 64
2795 18:11:38.560866
2796 18:11:38.560918 Set Vref, RX VrefLevel [Byte0]: 65
2797 18:11:38.560971 [Byte1]: 65
2798 18:11:38.561024
2799 18:11:38.561076 Set Vref, RX VrefLevel [Byte0]: 66
2800 18:11:38.561129 [Byte1]: 66
2801 18:11:38.561183
2802 18:11:38.561234 Set Vref, RX VrefLevel [Byte0]: 67
2803 18:11:38.561287 [Byte1]: 67
2804 18:11:38.561340
2805 18:11:38.561392 Set Vref, RX VrefLevel [Byte0]: 68
2806 18:11:38.561445 [Byte1]: 68
2807 18:11:38.561498
2808 18:11:38.561550 Set Vref, RX VrefLevel [Byte0]: 69
2809 18:11:38.561603 [Byte1]: 69
2810 18:11:38.561657
2811 18:11:38.561710 Set Vref, RX VrefLevel [Byte0]: 70
2812 18:11:38.561762 [Byte1]: 70
2813 18:11:38.561815
2814 18:11:38.561868 Set Vref, RX VrefLevel [Byte0]: 71
2815 18:11:38.561921 [Byte1]: 71
2816 18:11:38.561973
2817 18:11:38.562026 Final RX Vref Byte 0 = 60 to rank0
2818 18:11:38.562079 Final RX Vref Byte 1 = 49 to rank0
2819 18:11:38.562138 Final RX Vref Byte 0 = 60 to rank1
2820 18:11:38.562191 Final RX Vref Byte 1 = 49 to rank1==
2821 18:11:38.562245 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 18:11:38.562298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 18:11:38.562352 ==
2824 18:11:38.562404 DQS Delay:
2825 18:11:38.562457 DQS0 = 0, DQS1 = 0
2826 18:11:38.562510 DQM Delay:
2827 18:11:38.562563 DQM0 = 123, DQM1 = 109
2828 18:11:38.562616 DQ Delay:
2829 18:11:38.562669 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2830 18:11:38.562721 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2831 18:11:38.562775 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2832 18:11:38.562828 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2833 18:11:38.562881
2834 18:11:38.562933
2835 18:11:38.562986 [DQSOSCAuto] RK0, (LSB)MR18= 0xd09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2836 18:11:38.563040 CH0 RK0: MR19=404, MR18=D09
2837 18:11:38.563093 CH0_RK0: MR19=0x404, MR18=0xD09, DQSOSC=405, MR23=63, INC=39, DEC=26
2838 18:11:38.563146
2839 18:11:38.563199 ----->DramcWriteLeveling(PI) begin...
2840 18:11:38.563253 ==
2841 18:11:38.563306 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 18:11:38.563359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 18:11:38.563412 ==
2844 18:11:38.563465 Write leveling (Byte 0): 36 => 36
2845 18:11:38.563518 Write leveling (Byte 1): 29 => 29
2846 18:11:38.563571 DramcWriteLeveling(PI) end<-----
2847 18:11:38.563624
2848 18:11:38.563676 ==
2849 18:11:38.563728 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 18:11:38.563781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 18:11:38.563835 ==
2852 18:11:38.563888 [Gating] SW mode calibration
2853 18:11:38.563941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 18:11:38.563995 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 18:11:38.564049 0 15 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2856 18:11:38.564102 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 18:11:38.564156 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 18:11:38.564209 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 18:11:38.564262 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 18:11:38.564315 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 18:11:38.564368 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 18:11:38.564421 0 15 28 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 0)
2863 18:11:38.564474 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2864 18:11:38.564527 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 18:11:38.564609 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 18:11:38.564676 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 18:11:38.564729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 18:11:38.564782 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 18:11:38.564834 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2870 18:11:38.564888 1 0 28 | B1->B0 | 3333 3d3d | 0 0 | (1 1) (0 0)
2871 18:11:38.564941 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 18:11:38.564994 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 18:11:38.565047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 18:11:38.565099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 18:11:38.565153 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 18:11:38.565205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 18:11:38.565258 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 18:11:38.565311 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 18:11:38.565381 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2880 18:11:38.565718 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 18:11:38.565886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 18:11:38.566014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 18:11:38.566141 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 18:11:38.566268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 18:11:38.566411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 18:11:38.566540 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 18:11:38.566670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 18:11:38.566800 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 18:11:38.566891 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 18:11:38.566950 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 18:11:38.567006 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 18:11:38.567061 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 18:11:38.567117 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 18:11:38.567171 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2895 18:11:38.567226 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2896 18:11:38.567281 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 18:11:38.567336 Total UI for P1: 0, mck2ui 16
2898 18:11:38.567391 best dqsien dly found for B0: ( 1, 3, 30)
2899 18:11:38.567447 Total UI for P1: 0, mck2ui 16
2900 18:11:38.567503 best dqsien dly found for B1: ( 1, 3, 30)
2901 18:11:38.567558 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2902 18:11:38.567612 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2903 18:11:38.567667
2904 18:11:38.567721 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 18:11:38.567777 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2906 18:11:38.567832 [Gating] SW calibration Done
2907 18:11:38.567886 ==
2908 18:11:38.567941 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 18:11:38.567996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 18:11:38.568052 ==
2911 18:11:38.568106 RX Vref Scan: 0
2912 18:11:38.568161
2913 18:11:38.568215 RX Vref 0 -> 0, step: 1
2914 18:11:38.568269
2915 18:11:38.568323 RX Delay -40 -> 252, step: 8
2916 18:11:38.568377 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2917 18:11:38.568432 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2918 18:11:38.568486 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2919 18:11:38.568541 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2920 18:11:38.568620 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2921 18:11:38.568674 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2922 18:11:38.568726 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2923 18:11:38.568780 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2924 18:11:38.568833 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2925 18:11:38.568902 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 18:11:38.568956 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2927 18:11:38.569016 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2928 18:11:38.569084 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2929 18:11:38.569137 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2930 18:11:38.569191 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 18:11:38.569245 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2932 18:11:38.569298 ==
2933 18:11:38.569351 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 18:11:38.569405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 18:11:38.569458 ==
2936 18:11:38.569511 DQS Delay:
2937 18:11:38.569563 DQS0 = 0, DQS1 = 0
2938 18:11:38.883743 DQM Delay:
2939 18:11:38.883972 DQM0 = 120, DQM1 = 108
2940 18:11:38.884103 DQ Delay:
2941 18:11:38.884225 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2942 18:11:38.884343 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2943 18:11:38.884459 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2944 18:11:38.884591 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2945 18:11:38.884734
2946 18:11:38.884909
2947 18:11:38.885174 ==
2948 18:11:38.885395 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 18:11:38.885543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 18:11:38.885664 ==
2951 18:11:38.885779
2952 18:11:38.885891
2953 18:11:38.886001 TX Vref Scan disable
2954 18:11:38.886111 == TX Byte 0 ==
2955 18:11:38.886263 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2956 18:11:38.886375 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2957 18:11:38.886485 == TX Byte 1 ==
2958 18:11:38.886595 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2959 18:11:38.886705 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2960 18:11:38.886814 ==
2961 18:11:38.886924 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 18:11:38.887033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 18:11:38.887142 ==
2964 18:11:38.887405 TX Vref=22, minBit 1, minWin=25, winSum=420
2965 18:11:38.887623 TX Vref=24, minBit 0, minWin=25, winSum=423
2966 18:11:38.887749 TX Vref=26, minBit 4, minWin=25, winSum=429
2967 18:11:38.887862 TX Vref=28, minBit 0, minWin=26, winSum=432
2968 18:11:38.887973 TX Vref=30, minBit 0, minWin=27, winSum=435
2969 18:11:38.888089 TX Vref=32, minBit 0, minWin=26, winSum=433
2970 18:11:38.888200 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
2971 18:11:38.888310
2972 18:11:38.888465 Final TX Range 1 Vref 30
2973 18:11:38.888631
2974 18:11:38.888744 ==
2975 18:11:38.888855 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 18:11:38.888964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 18:11:38.889076 ==
2978 18:11:38.889184
2979 18:11:38.889292
2980 18:11:38.889401 TX Vref Scan disable
2981 18:11:38.889509 == TX Byte 0 ==
2982 18:11:38.889618 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2983 18:11:38.889726 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2984 18:11:38.889835 == TX Byte 1 ==
2985 18:11:38.889942 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2986 18:11:38.890051 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2987 18:11:38.890158
2988 18:11:38.890265 [DATLAT]
2989 18:11:38.890372 Freq=1200, CH0 RK1
2990 18:11:38.890481
2991 18:11:38.890588 DATLAT Default: 0xd
2992 18:11:38.890696 0, 0xFFFF, sum = 0
2993 18:11:38.890808 1, 0xFFFF, sum = 0
2994 18:11:38.890923 2, 0xFFFF, sum = 0
2995 18:11:38.891037 3, 0xFFFF, sum = 0
2996 18:11:38.891147 4, 0xFFFF, sum = 0
2997 18:11:38.891255 5, 0xFFFF, sum = 0
2998 18:11:38.891364 6, 0xFFFF, sum = 0
2999 18:11:38.891473 7, 0xFFFF, sum = 0
3000 18:11:38.891582 8, 0xFFFF, sum = 0
3001 18:11:38.891691 9, 0xFFFF, sum = 0
3002 18:11:38.891826 10, 0xFFFF, sum = 0
3003 18:11:38.892077 11, 0xFFFF, sum = 0
3004 18:11:38.892284 12, 0x0, sum = 1
3005 18:11:38.892459 13, 0x0, sum = 2
3006 18:11:38.892625 14, 0x0, sum = 3
3007 18:11:38.892740 15, 0x0, sum = 4
3008 18:11:38.892852 best_step = 13
3009 18:11:38.892962
3010 18:11:38.893069 ==
3011 18:11:38.893334 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 18:11:38.893546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 18:11:38.893670 ==
3014 18:11:38.893781 RX Vref Scan: 0
3015 18:11:38.893891
3016 18:11:38.894257 RX Vref 0 -> 0, step: 1
3017 18:11:38.894385
3018 18:11:38.894497 RX Delay -21 -> 252, step: 4
3019 18:11:38.894609 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3020 18:11:38.894721 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3021 18:11:38.894835 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3022 18:11:38.894948 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3023 18:11:38.895071 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3024 18:11:38.895187 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3025 18:11:38.895301 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3026 18:11:38.895412 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3027 18:11:38.895523 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3028 18:11:38.895634 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3029 18:11:38.895746 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3030 18:11:38.895866 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3031 18:11:38.896132 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3032 18:11:38.896351 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3033 18:11:38.896532 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3034 18:11:38.896674 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3035 18:11:38.896791 ==
3036 18:11:38.896904 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 18:11:38.897021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 18:11:38.897137 ==
3039 18:11:38.897249 DQS Delay:
3040 18:11:38.897361 DQS0 = 0, DQS1 = 0
3041 18:11:38.897473 DQM Delay:
3042 18:11:38.897585 DQM0 = 119, DQM1 = 108
3043 18:11:38.897695 DQ Delay:
3044 18:11:38.897806 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3045 18:11:38.897917 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3046 18:11:38.898029 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3047 18:11:38.898141 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3048 18:11:38.898254
3049 18:11:38.898364
3050 18:11:38.898475 [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3051 18:11:38.898590 CH0 RK1: MR19=403, MR18=FF6
3052 18:11:38.898702 CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26
3053 18:11:38.898817 [RxdqsGatingPostProcess] freq 1200
3054 18:11:38.898928 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 18:11:38.899041 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 18:11:38.899153 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 18:11:38.899264 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 18:11:38.899376 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 18:11:38.899488 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 18:11:38.899599 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 18:11:38.899711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 18:11:38.899821 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 18:11:38.899932 Pre-setting of DQS Precalculation
3064 18:11:38.900044 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 18:11:38.900155 ==
3066 18:11:38.900265 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 18:11:38.900377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 18:11:38.900489 ==
3069 18:11:38.900619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 18:11:38.900734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3071 18:11:38.900847 [CA 0] Center 37 (7~68) winsize 62
3072 18:11:38.900958 [CA 1] Center 37 (7~68) winsize 62
3073 18:11:38.901070 [CA 2] Center 35 (5~65) winsize 61
3074 18:11:38.901180 [CA 3] Center 34 (4~65) winsize 62
3075 18:11:38.901291 [CA 4] Center 34 (4~65) winsize 62
3076 18:11:38.901402 [CA 5] Center 33 (3~64) winsize 62
3077 18:11:38.901512
3078 18:11:38.901621 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3079 18:11:38.901732
3080 18:11:38.901844 [CATrainingPosCal] consider 1 rank data
3081 18:11:38.901974 u2DelayCellTimex100 = 270/100 ps
3082 18:11:38.902230 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 18:11:38.902432 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 18:11:38.902556 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3085 18:11:38.902671 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 18:11:38.902786 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3087 18:11:38.902906 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 18:11:38.903064
3089 18:11:38.903178 CA PerBit enable=1, Macro0, CA PI delay=33
3090 18:11:38.903292
3091 18:11:38.903404 [CBTSetCACLKResult] CA Dly = 33
3092 18:11:38.903517 CS Dly: 5 (0~36)
3093 18:11:38.903663 ==
3094 18:11:38.903941 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 18:11:38.904141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 18:11:38.904265 ==
3097 18:11:38.904381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 18:11:38.904496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3099 18:11:38.904630 [CA 0] Center 38 (8~68) winsize 61
3100 18:11:38.904745 [CA 1] Center 38 (7~69) winsize 63
3101 18:11:38.904858 [CA 2] Center 35 (5~66) winsize 62
3102 18:11:38.904970 [CA 3] Center 35 (5~65) winsize 61
3103 18:11:38.905083 [CA 4] Center 35 (5~65) winsize 61
3104 18:11:38.905194 [CA 5] Center 34 (4~64) winsize 61
3105 18:11:38.905323
3106 18:11:38.905435 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 18:11:38.905547
3108 18:11:38.905659 [CATrainingPosCal] consider 2 rank data
3109 18:11:38.905771 u2DelayCellTimex100 = 270/100 ps
3110 18:11:38.905884 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3111 18:11:38.905996 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3112 18:11:38.906124 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3113 18:11:38.906372 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3114 18:11:38.906588 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 18:11:38.906792 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 18:11:38.907046
3117 18:11:38.907258 CA PerBit enable=1, Macro0, CA PI delay=34
3118 18:11:38.907400
3119 18:11:38.907549 [CBTSetCACLKResult] CA Dly = 34
3120 18:11:38.907689 CS Dly: 6 (0~39)
3121 18:11:38.907803
3122 18:11:38.907917 ----->DramcWriteLeveling(PI) begin...
3123 18:11:38.908035 ==
3124 18:11:38.908149 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 18:11:38.908263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 18:11:38.908375 ==
3127 18:11:38.908639 Write leveling (Byte 0): 27 => 27
3128 18:11:38.908850 Write leveling (Byte 1): 28 => 28
3129 18:11:38.908983 DramcWriteLeveling(PI) end<-----
3130 18:11:38.909099
3131 18:11:38.909213 ==
3132 18:11:38.909326 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 18:11:38.909439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 18:11:38.909553 ==
3135 18:11:38.909664 [Gating] SW mode calibration
3136 18:11:38.909788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 18:11:38.910296 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 18:11:38.910586 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 18:11:38.910857 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 18:11:38.911124 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 18:11:38.911389 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 18:11:38.911649 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 18:11:38.911910 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3144 18:11:38.912168 0 15 24 | B1->B0 | 2e2e 2a2a | 1 1 | (1 0) (1 0)
3145 18:11:38.912428 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3146 18:11:38.912621 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 18:11:38.912746 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 18:11:38.912864 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 18:11:38.912981 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 18:11:38.913095 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 18:11:38.913210 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3152 18:11:38.913323 1 0 24 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
3153 18:11:38.913436 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 18:11:38.913548 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 18:11:38.913669 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 18:11:38.913804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 18:11:38.913920 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 18:11:38.914033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 18:11:38.914146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 18:11:38.914259 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3161 18:11:38.914373 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3162 18:11:38.914485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 18:11:38.914598 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 18:11:38.914768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 18:11:38.914885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 18:11:38.914998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 18:11:38.915112 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 18:11:38.915226 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 18:11:38.915339 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 18:11:38.915451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 18:11:38.915563 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 18:11:38.915675 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 18:11:38.915786 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 18:11:38.915897 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 18:11:38.916009 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 18:11:38.916121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 18:11:38.916233 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 18:11:38.916344 Total UI for P1: 0, mck2ui 16
3179 18:11:38.916459 best dqsien dly found for B0: ( 1, 3, 24)
3180 18:11:38.916587 Total UI for P1: 0, mck2ui 16
3181 18:11:38.916712 best dqsien dly found for B1: ( 1, 3, 24)
3182 18:11:38.916808 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3183 18:11:38.916904 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3184 18:11:38.917000
3185 18:11:38.917095 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3186 18:11:38.917223 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3187 18:11:38.917322 [Gating] SW calibration Done
3188 18:11:38.917418 ==
3189 18:11:38.917514 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 18:11:38.917612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 18:11:38.917707 ==
3192 18:11:38.917801 RX Vref Scan: 0
3193 18:11:38.917895
3194 18:11:38.917989 RX Vref 0 -> 0, step: 1
3195 18:11:38.918083
3196 18:11:38.918176 RX Delay -40 -> 252, step: 8
3197 18:11:38.918282 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3198 18:11:38.918381 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3199 18:11:38.918476 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3200 18:11:38.918572 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3201 18:11:38.918668 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3202 18:11:38.918762 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3203 18:11:38.918857 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3204 18:11:38.918952 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3205 18:11:38.919047 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3206 18:11:38.919141 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3207 18:11:38.919235 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3208 18:11:38.919330 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3209 18:11:38.919424 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3210 18:11:38.919519 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3211 18:11:38.919613 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3212 18:11:38.919707 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3213 18:11:38.919801 ==
3214 18:11:38.919895 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 18:11:38.919989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 18:11:38.920084 ==
3217 18:11:38.920178 DQS Delay:
3218 18:11:38.920299 DQS0 = 0, DQS1 = 0
3219 18:11:38.920461 DQM Delay:
3220 18:11:38.920613 DQM0 = 120, DQM1 = 112
3221 18:11:38.920714 DQ Delay:
3222 18:11:38.920810 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3223 18:11:38.920907 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3224 18:11:38.921002 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3225 18:11:38.921098 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3226 18:11:38.921193
3227 18:11:38.921286
3228 18:11:38.921380 ==
3229 18:11:38.921474 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 18:11:38.921570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 18:11:38.921681 ==
3232 18:11:38.921764
3233 18:11:38.921846
3234 18:11:38.921928 TX Vref Scan disable
3235 18:11:38.922011 == TX Byte 0 ==
3236 18:11:38.922092 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3237 18:11:38.922176 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3238 18:11:38.922258 == TX Byte 1 ==
3239 18:11:38.922340 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 18:11:38.922423 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 18:11:38.922506 ==
3242 18:11:38.922588 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 18:11:38.922882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 18:11:38.922947 ==
3245 18:11:38.923003 TX Vref=22, minBit 11, minWin=24, winSum=405
3246 18:11:38.923060 TX Vref=24, minBit 11, minWin=24, winSum=408
3247 18:11:38.923116 TX Vref=26, minBit 9, minWin=25, winSum=413
3248 18:11:38.923172 TX Vref=28, minBit 10, minWin=25, winSum=420
3249 18:11:38.923228 TX Vref=30, minBit 10, minWin=25, winSum=423
3250 18:11:38.923284 TX Vref=32, minBit 1, minWin=26, winSum=424
3251 18:11:38.923340 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3252 18:11:38.923396
3253 18:11:38.923451 Final TX Range 1 Vref 32
3254 18:11:38.923506
3255 18:11:38.923561 ==
3256 18:11:38.923616 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 18:11:38.923678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 18:11:38.923744 ==
3259 18:11:38.923800
3260 18:11:38.923855
3261 18:11:38.923911 TX Vref Scan disable
3262 18:11:38.923966 == TX Byte 0 ==
3263 18:11:38.924022 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3264 18:11:38.924078 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3265 18:11:38.924133 == TX Byte 1 ==
3266 18:11:38.924188 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 18:11:38.924243 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 18:11:38.924298
3269 18:11:38.924353 [DATLAT]
3270 18:11:38.924408 Freq=1200, CH1 RK0
3271 18:11:38.924463
3272 18:11:38.924517 DATLAT Default: 0xd
3273 18:11:38.924622 0, 0xFFFF, sum = 0
3274 18:11:38.924680 1, 0xFFFF, sum = 0
3275 18:11:38.924736 2, 0xFFFF, sum = 0
3276 18:11:38.924792 3, 0xFFFF, sum = 0
3277 18:11:38.924847 4, 0xFFFF, sum = 0
3278 18:11:38.924903 5, 0xFFFF, sum = 0
3279 18:11:38.924959 6, 0xFFFF, sum = 0
3280 18:11:38.925014 7, 0xFFFF, sum = 0
3281 18:11:38.925095 8, 0xFFFF, sum = 0
3282 18:11:38.925165 9, 0xFFFF, sum = 0
3283 18:11:38.925221 10, 0xFFFF, sum = 0
3284 18:11:38.925276 11, 0xFFFF, sum = 0
3285 18:11:38.925332 12, 0x0, sum = 1
3286 18:11:38.925387 13, 0x0, sum = 2
3287 18:11:38.925443 14, 0x0, sum = 3
3288 18:11:38.925498 15, 0x0, sum = 4
3289 18:11:38.925554 best_step = 13
3290 18:11:38.925609
3291 18:11:38.925664 ==
3292 18:11:38.925718 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 18:11:38.925774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 18:11:38.925828 ==
3295 18:11:38.925881 RX Vref Scan: 1
3296 18:11:38.925934
3297 18:11:38.925992 Set Vref Range= 32 -> 127
3298 18:11:38.926077
3299 18:11:38.926132 RX Vref 32 -> 127, step: 1
3300 18:11:38.926185
3301 18:11:38.926239 RX Delay -13 -> 252, step: 4
3302 18:11:38.926293
3303 18:11:38.926346 Set Vref, RX VrefLevel [Byte0]: 32
3304 18:11:38.926399 [Byte1]: 32
3305 18:11:38.926452
3306 18:11:38.926505 Set Vref, RX VrefLevel [Byte0]: 33
3307 18:11:38.926558 [Byte1]: 33
3308 18:11:38.926611
3309 18:11:38.926664 Set Vref, RX VrefLevel [Byte0]: 34
3310 18:11:38.926717 [Byte1]: 34
3311 18:11:38.926770
3312 18:11:38.926822 Set Vref, RX VrefLevel [Byte0]: 35
3313 18:11:38.926875 [Byte1]: 35
3314 18:11:38.926928
3315 18:11:38.926980 Set Vref, RX VrefLevel [Byte0]: 36
3316 18:11:38.927034 [Byte1]: 36
3317 18:11:38.927087
3318 18:11:38.927140 Set Vref, RX VrefLevel [Byte0]: 37
3319 18:11:38.927206 [Byte1]: 37
3320 18:11:38.927263
3321 18:11:38.927317 Set Vref, RX VrefLevel [Byte0]: 38
3322 18:11:38.927370 [Byte1]: 38
3323 18:11:38.927423
3324 18:11:38.927476 Set Vref, RX VrefLevel [Byte0]: 39
3325 18:11:38.927529 [Byte1]: 39
3326 18:11:38.927582
3327 18:11:38.927635 Set Vref, RX VrefLevel [Byte0]: 40
3328 18:11:38.927688 [Byte1]: 40
3329 18:11:38.927741
3330 18:11:38.927794 Set Vref, RX VrefLevel [Byte0]: 41
3331 18:11:38.927847 [Byte1]: 41
3332 18:11:38.927899
3333 18:11:38.927951 Set Vref, RX VrefLevel [Byte0]: 42
3334 18:11:38.928005 [Byte1]: 42
3335 18:11:38.928057
3336 18:11:38.928110 Set Vref, RX VrefLevel [Byte0]: 43
3337 18:11:38.928164 [Byte1]: 43
3338 18:11:38.928218
3339 18:11:38.928270 Set Vref, RX VrefLevel [Byte0]: 44
3340 18:11:38.928323 [Byte1]: 44
3341 18:11:38.928376
3342 18:11:38.928428 Set Vref, RX VrefLevel [Byte0]: 45
3343 18:11:38.928482 [Byte1]: 45
3344 18:11:38.928534
3345 18:11:38.928632 Set Vref, RX VrefLevel [Byte0]: 46
3346 18:11:38.928686 [Byte1]: 46
3347 18:11:38.928740
3348 18:11:38.928793 Set Vref, RX VrefLevel [Byte0]: 47
3349 18:11:38.928845 [Byte1]: 47
3350 18:11:38.928899
3351 18:11:38.928952 Set Vref, RX VrefLevel [Byte0]: 48
3352 18:11:38.929005 [Byte1]: 48
3353 18:11:38.929058
3354 18:11:38.929111 Set Vref, RX VrefLevel [Byte0]: 49
3355 18:11:38.929164 [Byte1]: 49
3356 18:11:38.929217
3357 18:11:38.929269 Set Vref, RX VrefLevel [Byte0]: 50
3358 18:11:38.929322 [Byte1]: 50
3359 18:11:38.929375
3360 18:11:38.929427 Set Vref, RX VrefLevel [Byte0]: 51
3361 18:11:38.929480 [Byte1]: 51
3362 18:11:38.929533
3363 18:11:38.929586 Set Vref, RX VrefLevel [Byte0]: 52
3364 18:11:38.929639 [Byte1]: 52
3365 18:11:38.929692
3366 18:11:38.929744 Set Vref, RX VrefLevel [Byte0]: 53
3367 18:11:38.929797 [Byte1]: 53
3368 18:11:38.929850
3369 18:11:38.929902 Set Vref, RX VrefLevel [Byte0]: 54
3370 18:11:38.929955 [Byte1]: 54
3371 18:11:38.930007
3372 18:11:38.930060 Set Vref, RX VrefLevel [Byte0]: 55
3373 18:11:38.930113 [Byte1]: 55
3374 18:11:38.930165
3375 18:11:38.930218 Set Vref, RX VrefLevel [Byte0]: 56
3376 18:11:38.930271 [Byte1]: 56
3377 18:11:38.930342
3378 18:11:38.930397 Set Vref, RX VrefLevel [Byte0]: 57
3379 18:11:38.930451 [Byte1]: 57
3380 18:11:38.930505
3381 18:11:38.930558 Set Vref, RX VrefLevel [Byte0]: 58
3382 18:11:38.930611 [Byte1]: 58
3383 18:11:38.930663
3384 18:11:38.930716 Set Vref, RX VrefLevel [Byte0]: 59
3385 18:11:38.930769 [Byte1]: 59
3386 18:11:38.930822
3387 18:11:38.930875 Set Vref, RX VrefLevel [Byte0]: 60
3388 18:11:38.930928 [Byte1]: 60
3389 18:11:38.930981
3390 18:11:38.931034 Set Vref, RX VrefLevel [Byte0]: 61
3391 18:11:38.931087 [Byte1]: 61
3392 18:11:38.931139
3393 18:11:38.931192 Set Vref, RX VrefLevel [Byte0]: 62
3394 18:11:38.931245 [Byte1]: 62
3395 18:11:38.931299
3396 18:11:38.931351 Set Vref, RX VrefLevel [Byte0]: 63
3397 18:11:38.931404 [Byte1]: 63
3398 18:11:38.931457
3399 18:11:38.931509 Set Vref, RX VrefLevel [Byte0]: 64
3400 18:11:38.931562 [Byte1]: 64
3401 18:11:38.931614
3402 18:11:38.931670 Set Vref, RX VrefLevel [Byte0]: 65
3403 18:11:38.931739 [Byte1]: 65
3404 18:11:38.931794
3405 18:11:38.931847 Set Vref, RX VrefLevel [Byte0]: 66
3406 18:11:38.931900 [Byte1]: 66
3407 18:11:38.931953
3408 18:11:38.932006 Final RX Vref Byte 0 = 52 to rank0
3409 18:11:38.932060 Final RX Vref Byte 1 = 52 to rank0
3410 18:11:38.932309 Final RX Vref Byte 0 = 52 to rank1
3411 18:11:38.932370 Final RX Vref Byte 1 = 52 to rank1==
3412 18:11:38.932425 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 18:11:38.932480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 18:11:38.932535 ==
3415 18:11:38.932633 DQS Delay:
3416 18:11:38.932688 DQS0 = 0, DQS1 = 0
3417 18:11:38.932741 DQM Delay:
3418 18:11:38.932793 DQM0 = 119, DQM1 = 112
3419 18:11:38.932847 DQ Delay:
3420 18:11:38.932901 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3421 18:11:38.932955 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3422 18:11:38.933009 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3423 18:11:38.933063 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =118
3424 18:11:38.933116
3425 18:11:38.933169
3426 18:11:38.933221 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3427 18:11:38.933276 CH1 RK0: MR19=404, MR18=518
3428 18:11:38.933330 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3429 18:11:38.933384
3430 18:11:38.933436 ----->DramcWriteLeveling(PI) begin...
3431 18:11:38.933491 ==
3432 18:11:38.933544 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 18:11:38.933598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 18:11:38.933664 ==
3435 18:11:38.933721 Write leveling (Byte 0): 25 => 25
3436 18:11:38.933775 Write leveling (Byte 1): 29 => 29
3437 18:11:38.933829 DramcWriteLeveling(PI) end<-----
3438 18:11:38.933883
3439 18:11:38.933936 ==
3440 18:11:38.933989 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 18:11:38.934043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 18:11:38.934096 ==
3443 18:11:38.934149 [Gating] SW mode calibration
3444 18:11:38.934203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 18:11:38.934257 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 18:11:38.934311 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 18:11:38.934365 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 18:11:38.934419 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 18:11:38.934473 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 18:11:38.934527 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 18:11:38.934580 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 18:11:38.934633 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (0 1)
3453 18:11:38.934686 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
3454 18:11:38.934739 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 18:11:38.934797 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 18:11:38.934850 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 18:11:38.934904 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 18:11:38.934958 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 18:11:38.935011 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 18:11:38.935064 1 0 24 | B1->B0 | 3939 2323 | 0 0 | (1 1) (0 0)
3461 18:11:38.935118 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3462 18:11:38.935171 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 18:11:38.935224 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 18:11:38.935277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 18:11:38.935331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 18:11:38.935383 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 18:11:38.935436 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 18:11:38.935490 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3469 18:11:38.935542 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3470 18:11:38.935595 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 18:11:38.935648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 18:11:38.935701 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 18:11:38.935754 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 18:11:38.935807 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 18:11:38.935860 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 18:11:38.935913 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 18:11:38.935966 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 18:11:38.936019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 18:11:38.936072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 18:11:38.936125 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 18:11:38.936178 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 18:11:38.936232 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 18:11:38.936285 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3484 18:11:38.936338 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 18:11:38.936391 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 18:11:38.936445 Total UI for P1: 0, mck2ui 16
3487 18:11:38.936498 best dqsien dly found for B0: ( 1, 3, 22)
3488 18:11:38.936562 Total UI for P1: 0, mck2ui 16
3489 18:11:38.936652 best dqsien dly found for B1: ( 1, 3, 24)
3490 18:11:38.936706 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3491 18:11:38.936759 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3492 18:11:38.936813
3493 18:11:38.936877 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3494 18:11:38.936932 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3495 18:11:38.936985 [Gating] SW calibration Done
3496 18:11:38.937038 ==
3497 18:11:38.937092 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 18:11:38.937158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 18:11:38.937216 ==
3500 18:11:38.937270 RX Vref Scan: 0
3501 18:11:38.937323
3502 18:11:38.937375 RX Vref 0 -> 0, step: 1
3503 18:11:38.937429
3504 18:11:38.937482 RX Delay -40 -> 252, step: 8
3505 18:11:38.937535 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3506 18:11:38.937588 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3507 18:11:38.937642 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3508 18:11:38.937695 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3509 18:11:38.937747 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3510 18:11:38.937801 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3511 18:11:38.937854 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3512 18:11:38.937907 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3513 18:11:38.937960 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3514 18:11:38.938204 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3515 18:11:38.938264 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3516 18:11:38.938318 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3517 18:11:38.938372 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3518 18:11:38.938426 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3519 18:11:38.938479 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3520 18:11:38.938533 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3521 18:11:38.938619 ==
3522 18:11:38.938672 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 18:11:38.938726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 18:11:38.938781 ==
3525 18:11:38.938834 DQS Delay:
3526 18:11:38.938886 DQS0 = 0, DQS1 = 0
3527 18:11:38.938940 DQM Delay:
3528 18:11:38.938994 DQM0 = 120, DQM1 = 113
3529 18:11:38.939047 DQ Delay:
3530 18:11:38.939100 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3531 18:11:38.939153 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3532 18:11:38.939210 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3533 18:11:38.939263 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =127
3534 18:11:38.939317
3535 18:11:38.939369
3536 18:11:38.939421 ==
3537 18:11:38.939474 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 18:11:38.939527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 18:11:38.939580 ==
3540 18:11:38.939633
3541 18:11:38.939686
3542 18:11:38.939737 TX Vref Scan disable
3543 18:11:38.939790 == TX Byte 0 ==
3544 18:11:38.939843 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3545 18:11:38.939896 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3546 18:11:38.939949 == TX Byte 1 ==
3547 18:11:38.940001 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3548 18:11:38.940054 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3549 18:11:38.940107 ==
3550 18:11:38.940160 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 18:11:38.940213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 18:11:38.940285 ==
3553 18:11:38.940340 TX Vref=22, minBit 1, minWin=25, winSum=415
3554 18:11:38.940395 TX Vref=24, minBit 3, minWin=25, winSum=419
3555 18:11:38.940449 TX Vref=26, minBit 1, minWin=26, winSum=426
3556 18:11:38.940502 TX Vref=28, minBit 0, minWin=26, winSum=428
3557 18:11:38.940564 TX Vref=30, minBit 1, minWin=26, winSum=429
3558 18:11:38.940620 TX Vref=32, minBit 9, minWin=25, winSum=425
3559 18:11:38.940674 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3560 18:11:38.940727
3561 18:11:38.940781 Final TX Range 1 Vref 30
3562 18:11:38.940834
3563 18:11:38.940887 ==
3564 18:11:38.940939 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 18:11:38.940992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 18:11:38.941045 ==
3567 18:11:38.941098
3568 18:11:38.941150
3569 18:11:38.941203 TX Vref Scan disable
3570 18:11:38.941256 == TX Byte 0 ==
3571 18:11:38.941309 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3572 18:11:38.941362 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3573 18:11:38.941416 == TX Byte 1 ==
3574 18:11:38.941469 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3575 18:11:38.941523 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3576 18:11:38.941576
3577 18:11:38.941628 [DATLAT]
3578 18:11:38.941681 Freq=1200, CH1 RK1
3579 18:11:38.941734
3580 18:11:38.941786 DATLAT Default: 0xd
3581 18:11:38.941840 0, 0xFFFF, sum = 0
3582 18:11:38.941894 1, 0xFFFF, sum = 0
3583 18:11:38.941948 2, 0xFFFF, sum = 0
3584 18:11:38.942002 3, 0xFFFF, sum = 0
3585 18:11:38.942056 4, 0xFFFF, sum = 0
3586 18:11:38.942110 5, 0xFFFF, sum = 0
3587 18:11:38.942163 6, 0xFFFF, sum = 0
3588 18:11:38.942221 7, 0xFFFF, sum = 0
3589 18:11:38.942277 8, 0xFFFF, sum = 0
3590 18:11:38.942331 9, 0xFFFF, sum = 0
3591 18:11:38.942385 10, 0xFFFF, sum = 0
3592 18:11:38.942439 11, 0xFFFF, sum = 0
3593 18:11:38.942493 12, 0x0, sum = 1
3594 18:11:38.942547 13, 0x0, sum = 2
3595 18:11:38.942601 14, 0x0, sum = 3
3596 18:11:38.942655 15, 0x0, sum = 4
3597 18:11:38.942709 best_step = 13
3598 18:11:38.942762
3599 18:11:38.942815 ==
3600 18:11:38.942869 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 18:11:38.942922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 18:11:38.942975 ==
3603 18:11:38.943028 RX Vref Scan: 0
3604 18:11:38.943081
3605 18:11:38.943133 RX Vref 0 -> 0, step: 1
3606 18:11:38.943186
3607 18:11:38.943251 RX Delay -13 -> 252, step: 4
3608 18:11:38.943306 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3609 18:11:38.943360 iDelay=195, Bit 1, Center 112 (51 ~ 174) 124
3610 18:11:38.943413 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3611 18:11:38.943466 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3612 18:11:38.943520 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3613 18:11:38.943574 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3614 18:11:38.943627 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3615 18:11:38.943696 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3616 18:11:38.943754 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3617 18:11:38.943808 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3618 18:11:38.943861 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3619 18:11:38.943914 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3620 18:11:38.943968 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3621 18:11:38.944021 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3622 18:11:38.944078 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3623 18:11:38.944132 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3624 18:11:38.944186 ==
3625 18:11:38.944238 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 18:11:38.944292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 18:11:38.944346 ==
3628 18:11:38.944400 DQS Delay:
3629 18:11:38.944452 DQS0 = 0, DQS1 = 0
3630 18:11:38.944506 DQM Delay:
3631 18:11:38.944564 DQM0 = 119, DQM1 = 113
3632 18:11:38.944651 DQ Delay:
3633 18:11:38.944704 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =118
3634 18:11:38.944758 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3635 18:11:38.944811 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3636 18:11:38.944864 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3637 18:11:38.944918
3638 18:11:38.944970
3639 18:11:38.945023 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3640 18:11:38.945077 CH1 RK1: MR19=403, MR18=9ED
3641 18:11:38.945131 CH1_RK1: MR19=0x403, MR18=0x9ED, DQSOSC=406, MR23=63, INC=39, DEC=26
3642 18:11:38.945184 [RxdqsGatingPostProcess] freq 1200
3643 18:11:38.945238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3644 18:11:38.945291 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 18:11:38.945345 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 18:11:38.945398 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 18:11:38.945451 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 18:11:38.945504 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 18:11:38.945557 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 18:11:38.945611 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 18:11:38.945664 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 18:11:38.945717 Pre-setting of DQS Precalculation
3653 18:11:38.945964 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3654 18:11:38.946026 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3655 18:11:38.946082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3656 18:11:38.946136
3657 18:11:38.946189
3658 18:11:38.946242 [Calibration Summary] 2400 Mbps
3659 18:11:38.946296 CH 0, Rank 0
3660 18:11:38.946349 SW Impedance : PASS
3661 18:11:38.946403 DUTY Scan : NO K
3662 18:11:38.946456 ZQ Calibration : PASS
3663 18:11:38.946509 Jitter Meter : NO K
3664 18:11:38.946562 CBT Training : PASS
3665 18:11:38.946614 Write leveling : PASS
3666 18:11:38.946668 RX DQS gating : PASS
3667 18:11:38.946721 RX DQ/DQS(RDDQC) : PASS
3668 18:11:38.946774 TX DQ/DQS : PASS
3669 18:11:38.946827 RX DATLAT : PASS
3670 18:11:38.946880 RX DQ/DQS(Engine): PASS
3671 18:11:38.946936 TX OE : NO K
3672 18:11:38.946991 All Pass.
3673 18:11:38.947044
3674 18:11:38.947109 CH 0, Rank 1
3675 18:11:38.947166 SW Impedance : PASS
3676 18:11:38.947220 DUTY Scan : NO K
3677 18:11:38.947273 ZQ Calibration : PASS
3678 18:11:38.947326 Jitter Meter : NO K
3679 18:11:38.947380 CBT Training : PASS
3680 18:11:38.947433 Write leveling : PASS
3681 18:11:38.947486 RX DQS gating : PASS
3682 18:11:38.947539 RX DQ/DQS(RDDQC) : PASS
3683 18:11:38.947592 TX DQ/DQS : PASS
3684 18:11:38.947649 RX DATLAT : PASS
3685 18:11:38.947703 RX DQ/DQS(Engine): PASS
3686 18:11:38.947755 TX OE : NO K
3687 18:11:38.947808 All Pass.
3688 18:11:38.947861
3689 18:11:38.947914 CH 1, Rank 0
3690 18:11:38.947967 SW Impedance : PASS
3691 18:11:38.948020 DUTY Scan : NO K
3692 18:11:38.948072 ZQ Calibration : PASS
3693 18:11:38.948126 Jitter Meter : NO K
3694 18:11:38.948179 CBT Training : PASS
3695 18:11:38.948232 Write leveling : PASS
3696 18:11:38.948289 RX DQS gating : PASS
3697 18:11:38.948344 RX DQ/DQS(RDDQC) : PASS
3698 18:11:38.948397 TX DQ/DQS : PASS
3699 18:11:38.948450 RX DATLAT : PASS
3700 18:11:38.948503 RX DQ/DQS(Engine): PASS
3701 18:11:38.948605 TX OE : NO K
3702 18:11:38.948662 All Pass.
3703 18:11:38.948715
3704 18:11:38.948767 CH 1, Rank 1
3705 18:11:38.948820 SW Impedance : PASS
3706 18:11:38.948873 DUTY Scan : NO K
3707 18:11:38.948925 ZQ Calibration : PASS
3708 18:11:38.948978 Jitter Meter : NO K
3709 18:11:38.949031 CBT Training : PASS
3710 18:11:38.949083 Write leveling : PASS
3711 18:11:38.949136 RX DQS gating : PASS
3712 18:11:38.949189 RX DQ/DQS(RDDQC) : PASS
3713 18:11:38.949246 TX DQ/DQS : PASS
3714 18:11:38.949299 RX DATLAT : PASS
3715 18:11:38.949352 RX DQ/DQS(Engine): PASS
3716 18:11:38.949404 TX OE : NO K
3717 18:11:38.949457 All Pass.
3718 18:11:38.949510
3719 18:11:38.949563 DramC Write-DBI off
3720 18:11:38.949616 PER_BANK_REFRESH: Hybrid Mode
3721 18:11:38.949670 TX_TRACKING: ON
3722 18:11:38.949723 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3723 18:11:38.949777 [FAST_K] Save calibration result to emmc
3724 18:11:38.949831 dramc_set_vcore_voltage set vcore to 650000
3725 18:11:38.949884 Read voltage for 600, 5
3726 18:11:38.949937 Vio18 = 0
3727 18:11:38.949990 Vcore = 650000
3728 18:11:38.950043 Vdram = 0
3729 18:11:38.950096 Vddq = 0
3730 18:11:38.950149 Vmddr = 0
3731 18:11:38.950205 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3732 18:11:38.950306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3733 18:11:38.950389 MEM_TYPE=3, freq_sel=19
3734 18:11:38.950475 sv_algorithm_assistance_LP4_1600
3735 18:11:38.950561 ============ PULL DRAM RESETB DOWN ============
3736 18:11:38.950629 ========== PULL DRAM RESETB DOWN end =========
3737 18:11:38.950684 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3738 18:11:38.950740 ===================================
3739 18:11:38.950795 LPDDR4 DRAM CONFIGURATION
3740 18:11:38.950849 ===================================
3741 18:11:38.950903 EX_ROW_EN[0] = 0x0
3742 18:11:38.950957 EX_ROW_EN[1] = 0x0
3743 18:11:38.951010 LP4Y_EN = 0x0
3744 18:11:38.951063 WORK_FSP = 0x0
3745 18:11:38.951116 WL = 0x2
3746 18:11:38.951169 RL = 0x2
3747 18:11:38.951222 BL = 0x2
3748 18:11:38.951275 RPST = 0x0
3749 18:11:38.951327 RD_PRE = 0x0
3750 18:11:38.951380 WR_PRE = 0x1
3751 18:11:38.951433 WR_PST = 0x0
3752 18:11:38.951486 DBI_WR = 0x0
3753 18:11:38.951539 DBI_RD = 0x0
3754 18:11:38.951591 OTF = 0x1
3755 18:11:38.951644 ===================================
3756 18:11:38.951698 ===================================
3757 18:11:38.951751 ANA top config
3758 18:11:38.951804 ===================================
3759 18:11:38.951857 DLL_ASYNC_EN = 0
3760 18:11:38.951910 ALL_SLAVE_EN = 1
3761 18:11:38.951963 NEW_RANK_MODE = 1
3762 18:11:38.952017 DLL_IDLE_MODE = 1
3763 18:11:38.952070 LP45_APHY_COMB_EN = 1
3764 18:11:38.952123 TX_ODT_DIS = 1
3765 18:11:38.952176 NEW_8X_MODE = 1
3766 18:11:38.952230 ===================================
3767 18:11:38.952283 ===================================
3768 18:11:38.952337 data_rate = 1200
3769 18:11:38.952390 CKR = 1
3770 18:11:38.952444 DQ_P2S_RATIO = 8
3771 18:11:38.952496 ===================================
3772 18:11:38.952572 CA_P2S_RATIO = 8
3773 18:11:38.952647 DQ_CA_OPEN = 0
3774 18:11:38.952700 DQ_SEMI_OPEN = 0
3775 18:11:38.952753 CA_SEMI_OPEN = 0
3776 18:11:38.952806 CA_FULL_RATE = 0
3777 18:11:38.952859 DQ_CKDIV4_EN = 1
3778 18:11:38.952912 CA_CKDIV4_EN = 1
3779 18:11:38.952966 CA_PREDIV_EN = 0
3780 18:11:38.953018 PH8_DLY = 0
3781 18:11:38.953072 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3782 18:11:38.953125 DQ_AAMCK_DIV = 4
3783 18:11:38.953178 CA_AAMCK_DIV = 4
3784 18:11:38.953231 CA_ADMCK_DIV = 4
3785 18:11:38.953283 DQ_TRACK_CA_EN = 0
3786 18:11:38.953336 CA_PICK = 600
3787 18:11:38.953389 CA_MCKIO = 600
3788 18:11:38.953442 MCKIO_SEMI = 0
3789 18:11:38.953495 PLL_FREQ = 2288
3790 18:11:38.953549 DQ_UI_PI_RATIO = 32
3791 18:11:38.953602 CA_UI_PI_RATIO = 0
3792 18:11:38.953655 ===================================
3793 18:11:38.953720 ===================================
3794 18:11:38.953778 memory_type:LPDDR4
3795 18:11:38.953864 GP_NUM : 10
3796 18:11:38.953949 SRAM_EN : 1
3797 18:11:38.954033 MD32_EN : 0
3798 18:11:38.954115 ===================================
3799 18:11:38.954172 [ANA_INIT] >>>>>>>>>>>>>>
3800 18:11:38.954418 <<<<<< [CONFIGURE PHASE]: ANA_TX
3801 18:11:38.954480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3802 18:11:38.954535 ===================================
3803 18:11:38.954590 data_rate = 1200,PCW = 0X5800
3804 18:11:38.954644 ===================================
3805 18:11:38.954698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3806 18:11:38.954751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 18:11:38.954805 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 18:11:38.954859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3809 18:11:38.954913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3810 18:11:38.954966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3811 18:11:38.955020 [ANA_INIT] flow start
3812 18:11:38.955092 [ANA_INIT] PLL >>>>>>>>
3813 18:11:38.955148 [ANA_INIT] PLL <<<<<<<<
3814 18:11:38.955201 [ANA_INIT] MIDPI >>>>>>>>
3815 18:11:38.955254 [ANA_INIT] MIDPI <<<<<<<<
3816 18:11:38.955307 [ANA_INIT] DLL >>>>>>>>
3817 18:11:38.955360 [ANA_INIT] flow end
3818 18:11:38.955414 ============ LP4 DIFF to SE enter ============
3819 18:11:38.955469 ============ LP4 DIFF to SE exit ============
3820 18:11:38.955523 [ANA_INIT] <<<<<<<<<<<<<
3821 18:11:38.955577 [Flow] Enable top DCM control >>>>>
3822 18:11:38.955630 [Flow] Enable top DCM control <<<<<
3823 18:11:38.955683 Enable DLL master slave shuffle
3824 18:11:38.955737 ==============================================================
3825 18:11:38.955791 Gating Mode config
3826 18:11:38.955844 ==============================================================
3827 18:11:38.955897 Config description:
3828 18:11:38.955951 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3829 18:11:38.956005 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3830 18:11:38.956060 SELPH_MODE 0: By rank 1: By Phase
3831 18:11:38.956113 ==============================================================
3832 18:11:38.956167 GAT_TRACK_EN = 1
3833 18:11:38.956221 RX_GATING_MODE = 2
3834 18:11:38.956274 RX_GATING_TRACK_MODE = 2
3835 18:11:38.956326 SELPH_MODE = 1
3836 18:11:38.956379 PICG_EARLY_EN = 1
3837 18:11:38.956432 VALID_LAT_VALUE = 1
3838 18:11:38.956485 ==============================================================
3839 18:11:38.956539 Enter into Gating configuration >>>>
3840 18:11:38.956640 Exit from Gating configuration <<<<
3841 18:11:38.956694 Enter into DVFS_PRE_config >>>>>
3842 18:11:38.956781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3843 18:11:38.956867 Exit from DVFS_PRE_config <<<<<
3844 18:11:38.956951 Enter into PICG configuration >>>>
3845 18:11:38.957041 Exit from PICG configuration <<<<
3846 18:11:38.957133 [RX_INPUT] configuration >>>>>
3847 18:11:38.957221 [RX_INPUT] configuration <<<<<
3848 18:11:38.957313 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3849 18:11:38.957372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3850 18:11:38.957429 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 18:11:38.957484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 18:11:38.957539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 18:11:38.957593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 18:11:38.957647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3855 18:11:38.957701 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3856 18:11:38.957754 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3857 18:11:38.957807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3858 18:11:38.957860 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3859 18:11:38.957914 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3860 18:11:38.957967 ===================================
3861 18:11:38.958021 LPDDR4 DRAM CONFIGURATION
3862 18:11:38.958074 ===================================
3863 18:11:38.958128 EX_ROW_EN[0] = 0x0
3864 18:11:38.958181 EX_ROW_EN[1] = 0x0
3865 18:11:38.958233 LP4Y_EN = 0x0
3866 18:11:38.958286 WORK_FSP = 0x0
3867 18:11:38.958339 WL = 0x2
3868 18:11:38.958392 RL = 0x2
3869 18:11:38.958443 BL = 0x2
3870 18:11:38.958496 RPST = 0x0
3871 18:11:38.958549 RD_PRE = 0x0
3872 18:11:38.958601 WR_PRE = 0x1
3873 18:11:38.958653 WR_PST = 0x0
3874 18:11:38.958706 DBI_WR = 0x0
3875 18:11:38.958758 DBI_RD = 0x0
3876 18:11:38.958811 OTF = 0x1
3877 18:11:38.958863 ===================================
3878 18:11:38.958916 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3879 18:11:38.958969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3880 18:11:38.959022 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3881 18:11:38.959076 ===================================
3882 18:11:38.959128 LPDDR4 DRAM CONFIGURATION
3883 18:11:38.959181 ===================================
3884 18:11:38.959234 EX_ROW_EN[0] = 0x10
3885 18:11:38.959287 EX_ROW_EN[1] = 0x0
3886 18:11:38.959340 LP4Y_EN = 0x0
3887 18:11:38.959392 WORK_FSP = 0x0
3888 18:11:38.959445 WL = 0x2
3889 18:11:38.959498 RL = 0x2
3890 18:11:38.959551 BL = 0x2
3891 18:11:38.959604 RPST = 0x0
3892 18:11:38.959657 RD_PRE = 0x0
3893 18:11:38.959710 WR_PRE = 0x1
3894 18:11:38.959762 WR_PST = 0x0
3895 18:11:38.959815 DBI_WR = 0x0
3896 18:11:38.959867 DBI_RD = 0x0
3897 18:11:38.959919 OTF = 0x1
3898 18:11:38.959972 ===================================
3899 18:11:38.960026 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3900 18:11:38.960079 nWR fixed to 30
3901 18:11:38.960146 [ModeRegInit_LP4] CH0 RK0
3902 18:11:38.960203 [ModeRegInit_LP4] CH0 RK1
3903 18:11:38.960709 [ModeRegInit_LP4] CH1 RK0
3904 18:11:38.963778 [ModeRegInit_LP4] CH1 RK1
3905 18:11:38.963859 match AC timing 17
3906 18:11:38.970682 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3907 18:11:38.973652 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3908 18:11:38.977230 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3909 18:11:38.983705 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3910 18:11:38.987084 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3911 18:11:38.987172 ==
3912 18:11:38.991056 Dram Type= 6, Freq= 0, CH_0, rank 0
3913 18:11:38.994143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3914 18:11:38.994302 ==
3915 18:11:39.000694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3916 18:11:39.007300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3917 18:11:39.010524 [CA 0] Center 36 (6~67) winsize 62
3918 18:11:39.013986 [CA 1] Center 36 (6~67) winsize 62
3919 18:11:39.016972 [CA 2] Center 34 (4~65) winsize 62
3920 18:11:39.020534 [CA 3] Center 34 (4~65) winsize 62
3921 18:11:39.023778 [CA 4] Center 34 (4~65) winsize 62
3922 18:11:39.027275 [CA 5] Center 33 (3~64) winsize 62
3923 18:11:39.027509
3924 18:11:39.030179 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3925 18:11:39.030354
3926 18:11:39.033743 [CATrainingPosCal] consider 1 rank data
3927 18:11:39.036796 u2DelayCellTimex100 = 270/100 ps
3928 18:11:39.040341 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3929 18:11:39.043373 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3930 18:11:39.094568 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 18:11:39.095004 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3932 18:11:39.095397 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3933 18:11:39.095712 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3934 18:11:39.096087
3935 18:11:39.096383 CA PerBit enable=1, Macro0, CA PI delay=33
3936 18:11:39.096814
3937 18:11:39.097155 [CBTSetCACLKResult] CA Dly = 33
3938 18:11:39.097461 CS Dly: 4 (0~35)
3939 18:11:39.097767 ==
3940 18:11:39.098117 Dram Type= 6, Freq= 0, CH_0, rank 1
3941 18:11:39.098429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3942 18:11:39.098748 ==
3943 18:11:39.099050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3944 18:11:39.099327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3945 18:11:39.099645 [CA 0] Center 36 (6~67) winsize 62
3946 18:11:39.099935 [CA 1] Center 36 (6~67) winsize 62
3947 18:11:39.100268 [CA 2] Center 35 (5~66) winsize 62
3948 18:11:39.100759 [CA 3] Center 35 (4~66) winsize 63
3949 18:11:39.103304 [CA 4] Center 34 (3~65) winsize 63
3950 18:11:39.106754 [CA 5] Center 33 (3~64) winsize 62
3951 18:11:39.107164
3952 18:11:39.110164 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3953 18:11:39.110575
3954 18:11:39.113466 [CATrainingPosCal] consider 2 rank data
3955 18:11:39.116933 u2DelayCellTimex100 = 270/100 ps
3956 18:11:39.120014 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3957 18:11:39.123624 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 18:11:39.126410 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3959 18:11:39.133542 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 18:11:39.136651 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 18:11:39.140186 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3962 18:11:39.140504
3963 18:11:39.143310 CA PerBit enable=1, Macro0, CA PI delay=33
3964 18:11:39.143631
3965 18:11:39.146679 [CBTSetCACLKResult] CA Dly = 33
3966 18:11:39.146996 CS Dly: 4 (0~36)
3967 18:11:39.147191
3968 18:11:39.150082 ----->DramcWriteLeveling(PI) begin...
3969 18:11:39.150402 ==
3970 18:11:39.153024 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 18:11:39.160143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 18:11:39.160632 ==
3973 18:11:39.163120 Write leveling (Byte 0): 33 => 33
3974 18:11:39.166478 Write leveling (Byte 1): 31 => 31
3975 18:11:39.170183 DramcWriteLeveling(PI) end<-----
3976 18:11:39.170927
3977 18:11:39.171350 ==
3978 18:11:39.172919 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 18:11:39.176177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 18:11:39.176822 ==
3981 18:11:39.180295 [Gating] SW mode calibration
3982 18:11:39.186714 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 18:11:39.190067 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3984 18:11:39.196782 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 18:11:39.200076 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 18:11:39.203413 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3987 18:11:39.209596 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
3988 18:11:39.213075 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3989 18:11:39.216281 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 18:11:39.222819 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 18:11:39.226309 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 18:11:39.229582 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 18:11:39.235957 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 18:11:39.239518 0 10 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
3995 18:11:39.242617 0 10 12 | B1->B0 | 2d2d 4040 | 1 0 | (0 0) (1 1)
3996 18:11:39.249260 0 10 16 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
3997 18:11:39.252796 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 18:11:39.255898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 18:11:39.262812 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 18:11:39.265897 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 18:11:39.269152 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 18:11:39.275747 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 18:11:39.278944 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 18:11:39.282584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 18:11:39.288906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4006 18:11:39.292452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 18:11:39.295957 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 18:11:39.302653 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 18:11:39.305891 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 18:11:39.308744 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 18:11:39.315429 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 18:11:39.318905 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 18:11:39.322232 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 18:11:39.328659 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 18:11:39.332257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 18:11:39.335339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 18:11:39.342497 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 18:11:39.345727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 18:11:39.349011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4020 18:11:39.352226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4021 18:11:39.355402 Total UI for P1: 0, mck2ui 16
4022 18:11:39.359252 best dqsien dly found for B0: ( 0, 13, 12)
4023 18:11:39.365443 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 18:11:39.368806 Total UI for P1: 0, mck2ui 16
4025 18:11:39.371976 best dqsien dly found for B1: ( 0, 13, 16)
4026 18:11:39.375859 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4027 18:11:39.379185 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4028 18:11:39.379823
4029 18:11:39.382516 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4030 18:11:39.385237 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4031 18:11:39.388652 [Gating] SW calibration Done
4032 18:11:39.389210 ==
4033 18:11:39.392248 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 18:11:39.395376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 18:11:39.395939 ==
4036 18:11:39.398571 RX Vref Scan: 0
4037 18:11:39.399039
4038 18:11:39.401963 RX Vref 0 -> 0, step: 1
4039 18:11:39.402430
4040 18:11:39.402801 RX Delay -230 -> 252, step: 16
4041 18:11:39.408718 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4042 18:11:39.412265 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4043 18:11:39.415615 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4044 18:11:39.418554 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4045 18:11:39.425048 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4046 18:11:39.428846 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4047 18:11:39.432036 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4048 18:11:39.435645 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4049 18:11:39.438649 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4050 18:11:39.445524 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4051 18:11:39.448372 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4052 18:11:39.452253 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4053 18:11:39.454996 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4054 18:11:39.461601 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4055 18:11:39.465065 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4056 18:11:39.468409 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4057 18:11:39.468925 ==
4058 18:11:39.471848 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 18:11:39.475146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 18:11:39.478480 ==
4061 18:11:39.479243 DQS Delay:
4062 18:11:39.479900 DQS0 = 0, DQS1 = 0
4063 18:11:39.481402 DQM Delay:
4064 18:11:39.482070 DQM0 = 52, DQM1 = 42
4065 18:11:39.484694 DQ Delay:
4066 18:11:39.485167 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4067 18:11:39.488625 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4068 18:11:39.491951 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4069 18:11:39.494929 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4070 18:11:39.498195
4071 18:11:39.498644
4072 18:11:39.499015 ==
4073 18:11:39.501881 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 18:11:39.505453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 18:11:39.506034 ==
4076 18:11:39.506416
4077 18:11:39.506764
4078 18:11:39.508155 TX Vref Scan disable
4079 18:11:39.508724 == TX Byte 0 ==
4080 18:11:39.515099 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4081 18:11:39.518126 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4082 18:11:39.518606 == TX Byte 1 ==
4083 18:11:39.524828 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 18:11:39.528265 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 18:11:39.528869 ==
4086 18:11:39.531723 Dram Type= 6, Freq= 0, CH_0, rank 0
4087 18:11:39.534817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4088 18:11:39.535386 ==
4089 18:11:39.535767
4090 18:11:39.536116
4091 18:11:39.538175 TX Vref Scan disable
4092 18:11:39.541724 == TX Byte 0 ==
4093 18:11:39.544898 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4094 18:11:39.548243 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4095 18:11:39.551893 == TX Byte 1 ==
4096 18:11:39.554547 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4097 18:11:39.558233 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4098 18:11:39.558798
4099 18:11:39.561681 [DATLAT]
4100 18:11:39.562249 Freq=600, CH0 RK0
4101 18:11:39.562629
4102 18:11:39.564585 DATLAT Default: 0x9
4103 18:11:39.565066 0, 0xFFFF, sum = 0
4104 18:11:39.567937 1, 0xFFFF, sum = 0
4105 18:11:39.568616 2, 0xFFFF, sum = 0
4106 18:11:39.571379 3, 0xFFFF, sum = 0
4107 18:11:39.571944 4, 0xFFFF, sum = 0
4108 18:11:39.574808 5, 0xFFFF, sum = 0
4109 18:11:39.575284 6, 0xFFFF, sum = 0
4110 18:11:39.577900 7, 0xFFFF, sum = 0
4111 18:11:39.578376 8, 0x0, sum = 1
4112 18:11:39.581712 9, 0x0, sum = 2
4113 18:11:39.582276 10, 0x0, sum = 3
4114 18:11:39.584414 11, 0x0, sum = 4
4115 18:11:39.585011 best_step = 9
4116 18:11:39.585389
4117 18:11:39.585761 ==
4118 18:11:39.587881 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 18:11:39.594835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 18:11:39.595309 ==
4121 18:11:39.595849 RX Vref Scan: 1
4122 18:11:39.596373
4123 18:11:39.598150 RX Vref 0 -> 0, step: 1
4124 18:11:39.598617
4125 18:11:39.601473 RX Delay -179 -> 252, step: 8
4126 18:11:39.601945
4127 18:11:39.604892 Set Vref, RX VrefLevel [Byte0]: 60
4128 18:11:39.607918 [Byte1]: 49
4129 18:11:39.608471
4130 18:11:39.611377 Final RX Vref Byte 0 = 60 to rank0
4131 18:11:39.614937 Final RX Vref Byte 1 = 49 to rank0
4132 18:11:39.618096 Final RX Vref Byte 0 = 60 to rank1
4133 18:11:39.621050 Final RX Vref Byte 1 = 49 to rank1==
4134 18:11:39.624624 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 18:11:39.628032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 18:11:39.628611 ==
4137 18:11:39.631155 DQS Delay:
4138 18:11:39.631577 DQS0 = 0, DQS1 = 0
4139 18:11:39.631915 DQM Delay:
4140 18:11:39.634589 DQM0 = 48, DQM1 = 39
4141 18:11:39.635014 DQ Delay:
4142 18:11:39.637923 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4143 18:11:39.641523 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4144 18:11:39.644746 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4145 18:11:39.648000 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4146 18:11:39.648422
4147 18:11:39.648788
4148 18:11:39.658153 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c56, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4149 18:11:39.658684 CH0 RK0: MR19=808, MR18=5C56
4150 18:11:39.664767 CH0_RK0: MR19=0x808, MR18=0x5C56, DQSOSC=392, MR23=63, INC=170, DEC=113
4151 18:11:39.665326
4152 18:11:39.667801 ----->DramcWriteLeveling(PI) begin...
4153 18:11:39.668371 ==
4154 18:11:39.671278 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 18:11:39.677634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 18:11:39.678113 ==
4157 18:11:39.681069 Write leveling (Byte 0): 35 => 35
4158 18:11:39.684451 Write leveling (Byte 1): 31 => 31
4159 18:11:39.684963 DramcWriteLeveling(PI) end<-----
4160 18:11:39.687863
4161 18:11:39.688422 ==
4162 18:11:39.691149 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 18:11:39.694560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 18:11:39.695036 ==
4165 18:11:39.697491 [Gating] SW mode calibration
4166 18:11:39.704173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4167 18:11:39.707647 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4168 18:11:39.714492 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 18:11:39.717901 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 18:11:39.721408 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 18:11:39.727800 0 9 12 | B1->B0 | 3333 3333 | 0 0 | (0 1) (0 0)
4172 18:11:39.730782 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4173 18:11:39.734161 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 18:11:39.740737 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 18:11:39.744175 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 18:11:39.747463 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 18:11:39.753780 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 18:11:39.757297 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 18:11:39.760995 0 10 12 | B1->B0 | 2e2e 3333 | 0 0 | (1 1) (0 0)
4180 18:11:39.767369 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4181 18:11:39.770390 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 18:11:39.773907 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 18:11:39.780314 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 18:11:39.783860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 18:11:39.786721 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 18:11:39.793769 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 18:11:39.796700 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4188 18:11:39.800231 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 18:11:39.806894 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 18:11:39.810120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 18:11:39.813485 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 18:11:39.820072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 18:11:39.823543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 18:11:39.826844 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 18:11:39.833247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 18:11:39.837011 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 18:11:39.839854 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 18:11:39.846985 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 18:11:39.850111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 18:11:39.853533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 18:11:39.860383 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 18:11:39.863069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 18:11:39.866738 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4204 18:11:39.870141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 18:11:39.873122 Total UI for P1: 0, mck2ui 16
4206 18:11:39.876756 best dqsien dly found for B0: ( 0, 13, 12)
4207 18:11:39.879620 Total UI for P1: 0, mck2ui 16
4208 18:11:39.883138 best dqsien dly found for B1: ( 0, 13, 12)
4209 18:11:39.886119 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4210 18:11:39.893054 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4211 18:11:39.893510
4212 18:11:39.896488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4213 18:11:39.899840 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 18:11:39.903022 [Gating] SW calibration Done
4215 18:11:39.903452 ==
4216 18:11:39.906366 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 18:11:39.909676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 18:11:39.910112 ==
4219 18:11:39.912774 RX Vref Scan: 0
4220 18:11:39.913201
4221 18:11:39.913542 RX Vref 0 -> 0, step: 1
4222 18:11:39.913936
4223 18:11:39.916264 RX Delay -230 -> 252, step: 16
4224 18:11:39.919622 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4225 18:11:39.926568 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4226 18:11:39.929722 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4227 18:11:39.932969 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4228 18:11:39.935938 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4229 18:11:39.942731 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4230 18:11:39.945899 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4231 18:11:39.949471 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4232 18:11:39.952586 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4233 18:11:39.956348 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4234 18:11:39.963073 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4235 18:11:39.966018 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4236 18:11:39.969562 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4237 18:11:39.972469 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4238 18:11:39.979318 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4239 18:11:39.982822 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4240 18:11:39.983348 ==
4241 18:11:39.986188 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 18:11:39.989516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 18:11:39.990042 ==
4244 18:11:39.992651 DQS Delay:
4245 18:11:39.993033 DQS0 = 0, DQS1 = 0
4246 18:11:39.993361 DQM Delay:
4247 18:11:39.996250 DQM0 = 48, DQM1 = 42
4248 18:11:39.996813 DQ Delay:
4249 18:11:39.999316 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4250 18:11:40.002798 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4251 18:11:40.006284 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4252 18:11:40.009225 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4253 18:11:40.009658
4254 18:11:40.010043
4255 18:11:40.010366 ==
4256 18:11:40.012875 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 18:11:40.018984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 18:11:40.019582 ==
4259 18:11:40.019937
4260 18:11:40.020257
4261 18:11:40.020609 TX Vref Scan disable
4262 18:11:40.022764 == TX Byte 0 ==
4263 18:11:40.026125 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4264 18:11:40.032484 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4265 18:11:40.033063 == TX Byte 1 ==
4266 18:11:40.035830 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4267 18:11:40.042820 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4268 18:11:40.043347 ==
4269 18:11:40.046115 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 18:11:40.049456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 18:11:40.049980 ==
4272 18:11:40.050331
4273 18:11:40.050651
4274 18:11:40.052461 TX Vref Scan disable
4275 18:11:40.055934 == TX Byte 0 ==
4276 18:11:40.059387 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4277 18:11:40.062595 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4278 18:11:40.065688 == TX Byte 1 ==
4279 18:11:40.069076 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4280 18:11:40.072097 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4281 18:11:40.072528
4282 18:11:40.072911 [DATLAT]
4283 18:11:40.075769 Freq=600, CH0 RK1
4284 18:11:40.076476
4285 18:11:40.079337 DATLAT Default: 0x9
4286 18:11:40.079805 0, 0xFFFF, sum = 0
4287 18:11:40.082374 1, 0xFFFF, sum = 0
4288 18:11:40.082853 2, 0xFFFF, sum = 0
4289 18:11:40.085402 3, 0xFFFF, sum = 0
4290 18:11:40.086031 4, 0xFFFF, sum = 0
4291 18:11:40.089142 5, 0xFFFF, sum = 0
4292 18:11:40.089619 6, 0xFFFF, sum = 0
4293 18:11:40.092494 7, 0xFFFF, sum = 0
4294 18:11:40.092991 8, 0x0, sum = 1
4295 18:11:40.095495 9, 0x0, sum = 2
4296 18:11:40.095916 10, 0x0, sum = 3
4297 18:11:40.096253 11, 0x0, sum = 4
4298 18:11:40.099004 best_step = 9
4299 18:11:40.099380
4300 18:11:40.099692 ==
4301 18:11:40.102371 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 18:11:40.105747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 18:11:40.106168 ==
4304 18:11:40.108936 RX Vref Scan: 0
4305 18:11:40.109354
4306 18:11:40.109683 RX Vref 0 -> 0, step: 1
4307 18:11:40.112406
4308 18:11:40.112854 RX Delay -179 -> 252, step: 8
4309 18:11:40.119946 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4310 18:11:40.123639 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4311 18:11:40.126808 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4312 18:11:40.129664 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4313 18:11:40.133312 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4314 18:11:40.139754 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4315 18:11:40.143121 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4316 18:11:40.146377 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4317 18:11:40.150388 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4318 18:11:40.153425 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4319 18:11:40.159527 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4320 18:11:40.163114 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4321 18:11:40.166367 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4322 18:11:40.169818 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4323 18:11:40.176413 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4324 18:11:40.180013 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4325 18:11:40.180439 ==
4326 18:11:40.183231 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 18:11:40.186512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 18:11:40.186939 ==
4329 18:11:40.189915 DQS Delay:
4330 18:11:40.190422 DQS0 = 0, DQS1 = 0
4331 18:11:40.190757 DQM Delay:
4332 18:11:40.193468 DQM0 = 48, DQM1 = 39
4333 18:11:40.193974 DQ Delay:
4334 18:11:40.196626 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4335 18:11:40.200104 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4336 18:11:40.203066 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4337 18:11:40.206618 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4338 18:11:40.207134
4339 18:11:40.207467
4340 18:11:40.216126 [DQSOSCAuto] RK1, (LSB)MR18= 0x6430, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4341 18:11:40.216581 CH0 RK1: MR19=808, MR18=6430
4342 18:11:40.223117 CH0_RK1: MR19=0x808, MR18=0x6430, DQSOSC=391, MR23=63, INC=171, DEC=114
4343 18:11:40.225953 [RxdqsGatingPostProcess] freq 600
4344 18:11:40.232655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4345 18:11:40.236330 Pre-setting of DQS Precalculation
4346 18:11:40.240130 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4347 18:11:40.240688 ==
4348 18:11:40.243149 Dram Type= 6, Freq= 0, CH_1, rank 0
4349 18:11:40.249643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 18:11:40.250101 ==
4351 18:11:40.253420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4352 18:11:40.259569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4353 18:11:40.263131 [CA 0] Center 35 (5~66) winsize 62
4354 18:11:40.266173 [CA 1] Center 35 (5~66) winsize 62
4355 18:11:40.269776 [CA 2] Center 34 (3~65) winsize 63
4356 18:11:40.273092 [CA 3] Center 33 (3~64) winsize 62
4357 18:11:40.276173 [CA 4] Center 34 (3~65) winsize 63
4358 18:11:40.279782 [CA 5] Center 33 (3~64) winsize 62
4359 18:11:40.280234
4360 18:11:40.282972 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4361 18:11:40.283526
4362 18:11:40.286242 [CATrainingPosCal] consider 1 rank data
4363 18:11:40.289316 u2DelayCellTimex100 = 270/100 ps
4364 18:11:40.292914 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4365 18:11:40.296224 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4366 18:11:40.299497 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 18:11:40.306161 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 18:11:40.309224 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4369 18:11:40.313174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4370 18:11:40.313735
4371 18:11:40.315952 CA PerBit enable=1, Macro0, CA PI delay=33
4372 18:11:40.316500
4373 18:11:40.319354 [CBTSetCACLKResult] CA Dly = 33
4374 18:11:40.319808 CS Dly: 5 (0~36)
4375 18:11:40.320167 ==
4376 18:11:40.322357 Dram Type= 6, Freq= 0, CH_1, rank 1
4377 18:11:40.329059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 18:11:40.329612 ==
4379 18:11:40.332780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 18:11:40.338926 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 18:11:40.343217 [CA 0] Center 35 (5~66) winsize 62
4382 18:11:40.346223 [CA 1] Center 35 (5~66) winsize 62
4383 18:11:40.349441 [CA 2] Center 34 (4~65) winsize 62
4384 18:11:40.353002 [CA 3] Center 34 (4~65) winsize 62
4385 18:11:40.355696 [CA 4] Center 34 (4~65) winsize 62
4386 18:11:40.359088 [CA 5] Center 34 (3~65) winsize 63
4387 18:11:40.359543
4388 18:11:40.362588 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 18:11:40.363040
4390 18:11:40.365888 [CATrainingPosCal] consider 2 rank data
4391 18:11:40.369498 u2DelayCellTimex100 = 270/100 ps
4392 18:11:40.372617 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4393 18:11:40.375783 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4394 18:11:40.382232 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 18:11:40.385332 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4396 18:11:40.388922 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 18:11:40.392013 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 18:11:40.392096
4399 18:11:40.395549 CA PerBit enable=1, Macro0, CA PI delay=33
4400 18:11:40.395632
4401 18:11:40.398962 [CBTSetCACLKResult] CA Dly = 33
4402 18:11:40.399048 CS Dly: 5 (0~36)
4403 18:11:40.399113
4404 18:11:40.401921 ----->DramcWriteLeveling(PI) begin...
4405 18:11:40.405582 ==
4406 18:11:40.408941 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 18:11:40.411997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 18:11:40.412079 ==
4409 18:11:40.415505 Write leveling (Byte 0): 28 => 28
4410 18:11:40.418971 Write leveling (Byte 1): 32 => 32
4411 18:11:40.421791 DramcWriteLeveling(PI) end<-----
4412 18:11:40.421874
4413 18:11:40.421938 ==
4414 18:11:40.425316 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 18:11:40.428969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 18:11:40.429052 ==
4417 18:11:40.431950 [Gating] SW mode calibration
4418 18:11:40.438821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4419 18:11:40.441767 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4420 18:11:40.448491 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 18:11:40.452012 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 18:11:40.455037 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 18:11:40.461864 0 9 12 | B1->B0 | 2727 2525 | 0 0 | (0 1) (0 0)
4424 18:11:40.465155 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 18:11:40.468438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 18:11:40.475017 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 18:11:40.478520 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 18:11:40.481958 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 18:11:40.488346 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 18:11:40.491862 0 10 8 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4431 18:11:40.494855 0 10 12 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
4432 18:11:40.501929 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 18:11:40.504941 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 18:11:40.508513 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 18:11:40.515076 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 18:11:40.518198 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 18:11:40.521544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 18:11:40.527960 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 18:11:40.531605 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4440 18:11:40.535110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 18:11:40.541410 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 18:11:40.545159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 18:11:40.548411 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 18:11:40.554964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 18:11:40.558512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 18:11:40.561745 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 18:11:40.568295 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 18:11:40.571272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 18:11:40.574937 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 18:11:40.581374 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 18:11:40.584870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 18:11:40.588228 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 18:11:40.591466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 18:11:40.598554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 18:11:40.601444 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4456 18:11:40.605030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 18:11:40.608230 Total UI for P1: 0, mck2ui 16
4458 18:11:40.611430 best dqsien dly found for B0: ( 0, 13, 12)
4459 18:11:40.615117 Total UI for P1: 0, mck2ui 16
4460 18:11:40.618034 best dqsien dly found for B1: ( 0, 13, 12)
4461 18:11:40.621661 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4462 18:11:40.628198 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4463 18:11:40.628635
4464 18:11:40.631692 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4465 18:11:40.635101 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4466 18:11:40.638790 [Gating] SW calibration Done
4467 18:11:40.639353 ==
4468 18:11:40.641626 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 18:11:40.645151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 18:11:40.645725 ==
4471 18:11:40.646102 RX Vref Scan: 0
4472 18:11:40.648614
4473 18:11:40.649181 RX Vref 0 -> 0, step: 1
4474 18:11:40.649556
4475 18:11:40.652130 RX Delay -230 -> 252, step: 16
4476 18:11:40.655245 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4477 18:11:40.661904 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4478 18:11:40.664718 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4479 18:11:40.668053 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4480 18:11:40.671224 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4481 18:11:40.674591 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4482 18:11:40.681941 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4483 18:11:40.684726 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4484 18:11:40.688234 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4485 18:11:40.691549 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4486 18:11:40.694941 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4487 18:11:40.701284 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4488 18:11:40.704326 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4489 18:11:40.707739 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4490 18:11:40.714531 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4491 18:11:40.718024 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4492 18:11:40.718594 ==
4493 18:11:40.720788 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 18:11:40.724525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 18:11:40.725139 ==
4496 18:11:40.725513 DQS Delay:
4497 18:11:40.727690 DQS0 = 0, DQS1 = 0
4498 18:11:40.728153 DQM Delay:
4499 18:11:40.731219 DQM0 = 53, DQM1 = 39
4500 18:11:40.731782 DQ Delay:
4501 18:11:40.734338 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4502 18:11:40.737926 DQ4 =57, DQ5 =57, DQ6 =65, DQ7 =49
4503 18:11:40.741410 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4504 18:11:40.744508 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4505 18:11:40.745124
4506 18:11:40.745499
4507 18:11:40.745841 ==
4508 18:11:40.747293 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 18:11:40.750660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 18:11:40.754137 ==
4511 18:11:40.754602
4512 18:11:40.754967
4513 18:11:40.755306 TX Vref Scan disable
4514 18:11:40.757651 == TX Byte 0 ==
4515 18:11:40.760923 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4516 18:11:40.767327 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4517 18:11:40.767896 == TX Byte 1 ==
4518 18:11:40.770835 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4519 18:11:40.777373 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4520 18:11:40.777953 ==
4521 18:11:40.780596 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 18:11:40.784083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 18:11:40.784865 ==
4524 18:11:40.785252
4525 18:11:40.785603
4526 18:11:40.787219 TX Vref Scan disable
4527 18:11:40.790929 == TX Byte 0 ==
4528 18:11:40.794262 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4529 18:11:40.797088 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4530 18:11:40.800862 == TX Byte 1 ==
4531 18:11:40.803783 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4532 18:11:40.807454 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4533 18:11:40.808030
4534 18:11:40.808410 [DATLAT]
4535 18:11:40.810952 Freq=600, CH1 RK0
4536 18:11:40.811528
4537 18:11:40.814029 DATLAT Default: 0x9
4538 18:11:40.814605 0, 0xFFFF, sum = 0
4539 18:11:40.817576 1, 0xFFFF, sum = 0
4540 18:11:40.818158 2, 0xFFFF, sum = 0
4541 18:11:40.820764 3, 0xFFFF, sum = 0
4542 18:11:40.821245 4, 0xFFFF, sum = 0
4543 18:11:40.824010 5, 0xFFFF, sum = 0
4544 18:11:40.824639 6, 0xFFFF, sum = 0
4545 18:11:40.827524 7, 0xFFFF, sum = 0
4546 18:11:40.828110 8, 0x0, sum = 1
4547 18:11:40.830451 9, 0x0, sum = 2
4548 18:11:40.831038 10, 0x0, sum = 3
4549 18:11:40.831430 11, 0x0, sum = 4
4550 18:11:40.833774 best_step = 9
4551 18:11:40.834245
4552 18:11:40.834618 ==
4553 18:11:40.837103 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 18:11:40.840407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 18:11:40.841043 ==
4556 18:11:40.843712 RX Vref Scan: 1
4557 18:11:40.844281
4558 18:11:40.844718 RX Vref 0 -> 0, step: 1
4559 18:11:40.847304
4560 18:11:40.847874 RX Delay -179 -> 252, step: 8
4561 18:11:40.848259
4562 18:11:40.850672 Set Vref, RX VrefLevel [Byte0]: 52
4563 18:11:40.854193 [Byte1]: 52
4564 18:11:40.858201
4565 18:11:40.858706 Final RX Vref Byte 0 = 52 to rank0
4566 18:11:40.861240 Final RX Vref Byte 1 = 52 to rank0
4567 18:11:40.864754 Final RX Vref Byte 0 = 52 to rank1
4568 18:11:40.867918 Final RX Vref Byte 1 = 52 to rank1==
4569 18:11:40.871477 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 18:11:40.877868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 18:11:40.878450 ==
4572 18:11:40.878859 DQS Delay:
4573 18:11:40.879214 DQS0 = 0, DQS1 = 0
4574 18:11:40.881231 DQM Delay:
4575 18:11:40.881751 DQM0 = 49, DQM1 = 41
4576 18:11:40.884701 DQ Delay:
4577 18:11:40.888028 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4578 18:11:40.891657 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4579 18:11:40.892235 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4580 18:11:40.898175 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4581 18:11:40.898749
4582 18:11:40.899125
4583 18:11:40.904628 [DQSOSCAuto] RK0, (LSB)MR18= 0x4970, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4584 18:11:40.907990 CH1 RK0: MR19=808, MR18=4970
4585 18:11:40.914630 CH1_RK0: MR19=0x808, MR18=0x4970, DQSOSC=388, MR23=63, INC=174, DEC=116
4586 18:11:40.915193
4587 18:11:40.918204 ----->DramcWriteLeveling(PI) begin...
4588 18:11:40.918776 ==
4589 18:11:40.921021 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 18:11:40.924812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 18:11:40.925381 ==
4592 18:11:40.927741 Write leveling (Byte 0): 29 => 29
4593 18:11:40.931180 Write leveling (Byte 1): 30 => 30
4594 18:11:40.934034 DramcWriteLeveling(PI) end<-----
4595 18:11:40.934505
4596 18:11:40.934882 ==
4597 18:11:40.937704 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 18:11:40.941172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 18:11:40.941738 ==
4600 18:11:40.944700 [Gating] SW mode calibration
4601 18:11:40.950987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4602 18:11:40.957167 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4603 18:11:40.960711 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 18:11:40.967119 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 18:11:40.970516 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
4606 18:11:40.974121 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 1) (1 0)
4607 18:11:40.980722 0 9 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4608 18:11:40.983913 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 18:11:40.987172 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 18:11:40.994008 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 18:11:40.997179 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 18:11:41.000640 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 18:11:41.004250 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 18:11:41.010612 0 10 12 | B1->B0 | 3e3e 2d2d | 0 0 | (0 0) (0 0)
4615 18:11:41.013782 0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
4616 18:11:41.017243 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 18:11:41.023882 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 18:11:41.026931 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 18:11:41.030447 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 18:11:41.037005 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 18:11:41.040720 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 18:11:41.043716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4623 18:11:41.050144 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 18:11:41.053501 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 18:11:41.057143 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 18:11:41.063812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 18:11:41.067315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 18:11:41.069942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 18:11:41.076777 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 18:11:41.080634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 18:11:41.083498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 18:11:41.090391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 18:11:41.093763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 18:11:41.096446 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 18:11:41.103545 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 18:11:41.106911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 18:11:41.109952 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 18:11:41.116588 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 18:11:41.117166 Total UI for P1: 0, mck2ui 16
4640 18:11:41.123127 best dqsien dly found for B0: ( 0, 13, 10)
4641 18:11:41.123726 Total UI for P1: 0, mck2ui 16
4642 18:11:41.126572 best dqsien dly found for B1: ( 0, 13, 10)
4643 18:11:41.132932 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4644 18:11:41.136006 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4645 18:11:41.136283
4646 18:11:41.139408 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4647 18:11:41.142499 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4648 18:11:41.145959 [Gating] SW calibration Done
4649 18:11:41.146180 ==
4650 18:11:41.149619 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 18:11:41.152535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 18:11:41.152732 ==
4653 18:11:41.155983 RX Vref Scan: 0
4654 18:11:41.156134
4655 18:11:41.156273 RX Vref 0 -> 0, step: 1
4656 18:11:41.156403
4657 18:11:41.159576 RX Delay -230 -> 252, step: 16
4658 18:11:41.166113 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4659 18:11:41.169038 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4660 18:11:41.172529 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4661 18:11:41.175954 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4662 18:11:41.179201 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4663 18:11:41.185860 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4664 18:11:41.189386 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4665 18:11:41.192272 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4666 18:11:41.195810 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4667 18:11:41.199234 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4668 18:11:41.206043 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4669 18:11:41.209389 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4670 18:11:41.212453 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4671 18:11:41.215821 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4672 18:11:41.222536 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4673 18:11:41.225642 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4674 18:11:41.225726 ==
4675 18:11:41.228993 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 18:11:41.231992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 18:11:41.232075 ==
4678 18:11:41.235646 DQS Delay:
4679 18:11:41.235730 DQS0 = 0, DQS1 = 0
4680 18:11:41.238673 DQM Delay:
4681 18:11:41.238757 DQM0 = 51, DQM1 = 46
4682 18:11:41.238822 DQ Delay:
4683 18:11:41.242209 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4684 18:11:41.245625 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4685 18:11:41.248769 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4686 18:11:41.252218 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4687 18:11:41.252300
4688 18:11:41.252366
4689 18:11:41.252426 ==
4690 18:11:41.255644 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 18:11:41.261879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 18:11:41.261964 ==
4693 18:11:41.262031
4694 18:11:41.262093
4695 18:11:41.264980 TX Vref Scan disable
4696 18:11:41.265063 == TX Byte 0 ==
4697 18:11:41.268415 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4698 18:11:41.275378 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4699 18:11:41.275463 == TX Byte 1 ==
4700 18:11:41.278299 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4701 18:11:41.285016 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4702 18:11:41.285111 ==
4703 18:11:41.288524 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 18:11:41.291881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 18:11:41.291967 ==
4706 18:11:41.292033
4707 18:11:41.292093
4708 18:11:41.295015 TX Vref Scan disable
4709 18:11:41.298074 == TX Byte 0 ==
4710 18:11:41.301553 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 18:11:41.304740 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 18:11:41.308048 == TX Byte 1 ==
4713 18:11:41.311295 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4714 18:11:41.314782 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4715 18:11:41.314867
4716 18:11:41.318200 [DATLAT]
4717 18:11:41.318282 Freq=600, CH1 RK1
4718 18:11:41.318349
4719 18:11:41.321215 DATLAT Default: 0x9
4720 18:11:41.321298 0, 0xFFFF, sum = 0
4721 18:11:41.324729 1, 0xFFFF, sum = 0
4722 18:11:41.324812 2, 0xFFFF, sum = 0
4723 18:11:41.327755 3, 0xFFFF, sum = 0
4724 18:11:41.327839 4, 0xFFFF, sum = 0
4725 18:11:41.331131 5, 0xFFFF, sum = 0
4726 18:11:41.331216 6, 0xFFFF, sum = 0
4727 18:11:41.334737 7, 0xFFFF, sum = 0
4728 18:11:41.334821 8, 0x0, sum = 1
4729 18:11:41.338142 9, 0x0, sum = 2
4730 18:11:41.338227 10, 0x0, sum = 3
4731 18:11:41.341290 11, 0x0, sum = 4
4732 18:11:41.341373 best_step = 9
4733 18:11:41.341438
4734 18:11:41.341498 ==
4735 18:11:41.344836 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 18:11:41.347806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 18:11:41.351366 ==
4738 18:11:41.351484 RX Vref Scan: 0
4739 18:11:41.351554
4740 18:11:41.354745 RX Vref 0 -> 0, step: 1
4741 18:11:41.354829
4742 18:11:41.357907 RX Delay -163 -> 252, step: 8
4743 18:11:41.360942 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4744 18:11:41.364705 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4745 18:11:41.371054 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4746 18:11:41.374563 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4747 18:11:41.378065 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4748 18:11:41.380909 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4749 18:11:41.384687 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4750 18:11:41.391217 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4751 18:11:41.394752 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4752 18:11:41.397733 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4753 18:11:41.401216 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4754 18:11:41.404258 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4755 18:11:41.411105 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4756 18:11:41.414570 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4757 18:11:41.417656 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4758 18:11:41.421053 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4759 18:11:41.421170 ==
4760 18:11:41.424378 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 18:11:41.431032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 18:11:41.431130 ==
4763 18:11:41.431198 DQS Delay:
4764 18:11:41.434501 DQS0 = 0, DQS1 = 0
4765 18:11:41.434586 DQM Delay:
4766 18:11:41.434653 DQM0 = 49, DQM1 = 43
4767 18:11:41.437568 DQ Delay:
4768 18:11:41.440939 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4769 18:11:41.444502 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4770 18:11:41.447514 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4771 18:11:41.451132 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4772 18:11:41.451216
4773 18:11:41.451282
4774 18:11:41.457733 [DQSOSCAuto] RK1, (LSB)MR18= 0x5b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4775 18:11:41.461123 CH1 RK1: MR19=808, MR18=5B21
4776 18:11:41.467668 CH1_RK1: MR19=0x808, MR18=0x5B21, DQSOSC=392, MR23=63, INC=170, DEC=113
4777 18:11:41.470938 [RxdqsGatingPostProcess] freq 600
4778 18:11:41.474086 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4779 18:11:41.477604 Pre-setting of DQS Precalculation
4780 18:11:41.484002 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4781 18:11:41.490898 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4782 18:11:41.497291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4783 18:11:41.497391
4784 18:11:41.497458
4785 18:11:41.500814 [Calibration Summary] 1200 Mbps
4786 18:11:41.500898 CH 0, Rank 0
4787 18:11:41.503835 SW Impedance : PASS
4788 18:11:41.507297 DUTY Scan : NO K
4789 18:11:41.507381 ZQ Calibration : PASS
4790 18:11:41.510522 Jitter Meter : NO K
4791 18:11:41.514100 CBT Training : PASS
4792 18:11:41.514185 Write leveling : PASS
4793 18:11:41.517346 RX DQS gating : PASS
4794 18:11:41.521077 RX DQ/DQS(RDDQC) : PASS
4795 18:11:41.521188 TX DQ/DQS : PASS
4796 18:11:41.523860 RX DATLAT : PASS
4797 18:11:41.527397 RX DQ/DQS(Engine): PASS
4798 18:11:41.527482 TX OE : NO K
4799 18:11:41.527550 All Pass.
4800 18:11:41.530643
4801 18:11:41.530726 CH 0, Rank 1
4802 18:11:41.533740 SW Impedance : PASS
4803 18:11:41.533825 DUTY Scan : NO K
4804 18:11:41.537181 ZQ Calibration : PASS
4805 18:11:41.537266 Jitter Meter : NO K
4806 18:11:41.540693 CBT Training : PASS
4807 18:11:41.543779 Write leveling : PASS
4808 18:11:41.543864 RX DQS gating : PASS
4809 18:11:41.547205 RX DQ/DQS(RDDQC) : PASS
4810 18:11:41.550848 TX DQ/DQS : PASS
4811 18:11:41.550939 RX DATLAT : PASS
4812 18:11:41.553800 RX DQ/DQS(Engine): PASS
4813 18:11:41.557362 TX OE : NO K
4814 18:11:41.557447 All Pass.
4815 18:11:41.557513
4816 18:11:41.557573 CH 1, Rank 0
4817 18:11:41.560478 SW Impedance : PASS
4818 18:11:41.563825 DUTY Scan : NO K
4819 18:11:41.563911 ZQ Calibration : PASS
4820 18:11:41.566877 Jitter Meter : NO K
4821 18:11:41.570339 CBT Training : PASS
4822 18:11:41.570433 Write leveling : PASS
4823 18:11:41.573779 RX DQS gating : PASS
4824 18:11:41.576986 RX DQ/DQS(RDDQC) : PASS
4825 18:11:41.577073 TX DQ/DQS : PASS
4826 18:11:41.580166 RX DATLAT : PASS
4827 18:11:41.583646 RX DQ/DQS(Engine): PASS
4828 18:11:41.583740 TX OE : NO K
4829 18:11:41.583808 All Pass.
4830 18:11:41.587146
4831 18:11:41.587230 CH 1, Rank 1
4832 18:11:41.590639 SW Impedance : PASS
4833 18:11:41.590737 DUTY Scan : NO K
4834 18:11:41.593782 ZQ Calibration : PASS
4835 18:11:41.593867 Jitter Meter : NO K
4836 18:11:41.596943 CBT Training : PASS
4837 18:11:41.600304 Write leveling : PASS
4838 18:11:41.600390 RX DQS gating : PASS
4839 18:11:41.603756 RX DQ/DQS(RDDQC) : PASS
4840 18:11:41.606821 TX DQ/DQS : PASS
4841 18:11:41.606908 RX DATLAT : PASS
4842 18:11:41.610349 RX DQ/DQS(Engine): PASS
4843 18:11:41.613586 TX OE : NO K
4844 18:11:41.613671 All Pass.
4845 18:11:41.613738
4846 18:11:41.616976 DramC Write-DBI off
4847 18:11:41.617061 PER_BANK_REFRESH: Hybrid Mode
4848 18:11:41.620278 TX_TRACKING: ON
4849 18:11:41.626956 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4850 18:11:41.633338 [FAST_K] Save calibration result to emmc
4851 18:11:41.636889 dramc_set_vcore_voltage set vcore to 662500
4852 18:11:41.636984 Read voltage for 933, 3
4853 18:11:41.640336 Vio18 = 0
4854 18:11:41.640422 Vcore = 662500
4855 18:11:41.640489 Vdram = 0
4856 18:11:41.643794 Vddq = 0
4857 18:11:41.643880 Vmddr = 0
4858 18:11:41.646798 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4859 18:11:41.653861 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4860 18:11:41.656798 MEM_TYPE=3, freq_sel=17
4861 18:11:41.660325 sv_algorithm_assistance_LP4_1600
4862 18:11:41.663529 ============ PULL DRAM RESETB DOWN ============
4863 18:11:41.666920 ========== PULL DRAM RESETB DOWN end =========
4864 18:11:41.669933 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 18:11:41.673588 ===================================
4866 18:11:41.676592 LPDDR4 DRAM CONFIGURATION
4867 18:11:41.679983 ===================================
4868 18:11:41.683523 EX_ROW_EN[0] = 0x0
4869 18:11:41.683649 EX_ROW_EN[1] = 0x0
4870 18:11:41.686538 LP4Y_EN = 0x0
4871 18:11:41.686623 WORK_FSP = 0x0
4872 18:11:41.690097 WL = 0x3
4873 18:11:41.690183 RL = 0x3
4874 18:11:41.693119 BL = 0x2
4875 18:11:41.693204 RPST = 0x0
4876 18:11:41.696328 RD_PRE = 0x0
4877 18:11:41.699870 WR_PRE = 0x1
4878 18:11:41.699960 WR_PST = 0x0
4879 18:11:41.703264 DBI_WR = 0x0
4880 18:11:41.703351 DBI_RD = 0x0
4881 18:11:41.706363 OTF = 0x1
4882 18:11:41.709722 ===================================
4883 18:11:41.713157 ===================================
4884 18:11:41.713243 ANA top config
4885 18:11:41.716805 ===================================
4886 18:11:41.719692 DLL_ASYNC_EN = 0
4887 18:11:41.719778 ALL_SLAVE_EN = 1
4888 18:11:41.722919 NEW_RANK_MODE = 1
4889 18:11:41.726814 DLL_IDLE_MODE = 1
4890 18:11:41.729637 LP45_APHY_COMB_EN = 1
4891 18:11:41.733125 TX_ODT_DIS = 1
4892 18:11:41.733210 NEW_8X_MODE = 1
4893 18:11:41.736491 ===================================
4894 18:11:41.739963 ===================================
4895 18:11:41.742952 data_rate = 1866
4896 18:11:41.746452 CKR = 1
4897 18:11:41.750011 DQ_P2S_RATIO = 8
4898 18:11:41.753156 ===================================
4899 18:11:41.756615 CA_P2S_RATIO = 8
4900 18:11:41.756701 DQ_CA_OPEN = 0
4901 18:11:41.759700 DQ_SEMI_OPEN = 0
4902 18:11:41.763251 CA_SEMI_OPEN = 0
4903 18:11:41.766911 CA_FULL_RATE = 0
4904 18:11:41.769845 DQ_CKDIV4_EN = 1
4905 18:11:41.773567 CA_CKDIV4_EN = 1
4906 18:11:41.773682 CA_PREDIV_EN = 0
4907 18:11:41.776485 PH8_DLY = 0
4908 18:11:41.779817 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4909 18:11:41.783200 DQ_AAMCK_DIV = 4
4910 18:11:41.786876 CA_AAMCK_DIV = 4
4911 18:11:41.789748 CA_ADMCK_DIV = 4
4912 18:11:41.789835 DQ_TRACK_CA_EN = 0
4913 18:11:41.793272 CA_PICK = 933
4914 18:11:41.796407 CA_MCKIO = 933
4915 18:11:41.799863 MCKIO_SEMI = 0
4916 18:11:41.803208 PLL_FREQ = 3732
4917 18:11:41.806438 DQ_UI_PI_RATIO = 32
4918 18:11:41.810004 CA_UI_PI_RATIO = 0
4919 18:11:41.812995 ===================================
4920 18:11:41.816242 ===================================
4921 18:11:41.816328 memory_type:LPDDR4
4922 18:11:41.819622 GP_NUM : 10
4923 18:11:41.822900 SRAM_EN : 1
4924 18:11:41.822985 MD32_EN : 0
4925 18:11:41.826356 ===================================
4926 18:11:41.829830 [ANA_INIT] >>>>>>>>>>>>>>
4927 18:11:41.833091 <<<<<< [CONFIGURE PHASE]: ANA_TX
4928 18:11:41.836179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4929 18:11:41.839669 ===================================
4930 18:11:41.842979 data_rate = 1866,PCW = 0X8f00
4931 18:11:41.846021 ===================================
4932 18:11:41.849437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4933 18:11:41.852993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4934 18:11:41.859736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 18:11:41.863215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4936 18:11:41.866355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4937 18:11:41.869949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4938 18:11:41.872871 [ANA_INIT] flow start
4939 18:11:41.876219 [ANA_INIT] PLL >>>>>>>>
4940 18:11:41.876306 [ANA_INIT] PLL <<<<<<<<
4941 18:11:41.879705 [ANA_INIT] MIDPI >>>>>>>>
4942 18:11:41.882759 [ANA_INIT] MIDPI <<<<<<<<
4943 18:11:41.882846 [ANA_INIT] DLL >>>>>>>>
4944 18:11:41.886205 [ANA_INIT] flow end
4945 18:11:41.889384 ============ LP4 DIFF to SE enter ============
4946 18:11:41.896443 ============ LP4 DIFF to SE exit ============
4947 18:11:41.896543 [ANA_INIT] <<<<<<<<<<<<<
4948 18:11:41.899682 [Flow] Enable top DCM control >>>>>
4949 18:11:41.902587 [Flow] Enable top DCM control <<<<<
4950 18:11:41.905847 Enable DLL master slave shuffle
4951 18:11:41.912791 ==============================================================
4952 18:11:41.912908 Gating Mode config
4953 18:11:41.919230 ==============================================================
4954 18:11:41.922753 Config description:
4955 18:11:41.929275 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4956 18:11:41.935862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4957 18:11:41.942503 SELPH_MODE 0: By rank 1: By Phase
4958 18:11:41.949569 ==============================================================
4959 18:11:41.949689 GAT_TRACK_EN = 1
4960 18:11:41.952483 RX_GATING_MODE = 2
4961 18:11:41.956128 RX_GATING_TRACK_MODE = 2
4962 18:11:41.959098 SELPH_MODE = 1
4963 18:11:41.962626 PICG_EARLY_EN = 1
4964 18:11:41.966210 VALID_LAT_VALUE = 1
4965 18:11:41.972831 ==============================================================
4966 18:11:41.975702 Enter into Gating configuration >>>>
4967 18:11:41.979247 Exit from Gating configuration <<<<
4968 18:11:41.982765 Enter into DVFS_PRE_config >>>>>
4969 18:11:41.992362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4970 18:11:41.995703 Exit from DVFS_PRE_config <<<<<
4971 18:11:41.999350 Enter into PICG configuration >>>>
4972 18:11:42.002425 Exit from PICG configuration <<<<
4973 18:11:42.005522 [RX_INPUT] configuration >>>>>
4974 18:11:42.005609 [RX_INPUT] configuration <<<<<
4975 18:11:42.012307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4976 18:11:42.019080 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4977 18:11:42.022109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 18:11:42.028859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 18:11:42.035710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 18:11:42.042405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 18:11:42.045341 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4982 18:11:42.048745 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4983 18:11:42.055496 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4984 18:11:42.058510 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4985 18:11:42.062048 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4986 18:11:42.068579 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4987 18:11:42.072083 ===================================
4988 18:11:42.072192 LPDDR4 DRAM CONFIGURATION
4989 18:11:42.075243 ===================================
4990 18:11:42.078648 EX_ROW_EN[0] = 0x0
4991 18:11:42.082044 EX_ROW_EN[1] = 0x0
4992 18:11:42.082135 LP4Y_EN = 0x0
4993 18:11:42.085566 WORK_FSP = 0x0
4994 18:11:42.085675 WL = 0x3
4995 18:11:42.088438 RL = 0x3
4996 18:11:42.088524 BL = 0x2
4997 18:11:42.092198 RPST = 0x0
4998 18:11:42.092284 RD_PRE = 0x0
4999 18:11:42.095155 WR_PRE = 0x1
5000 18:11:42.095240 WR_PST = 0x0
5001 18:11:42.098515 DBI_WR = 0x0
5002 18:11:42.098601 DBI_RD = 0x0
5003 18:11:42.101971 OTF = 0x1
5004 18:11:42.105090 ===================================
5005 18:11:42.108741 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5006 18:11:42.112140 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5007 18:11:42.115509 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5008 18:11:42.118511 ===================================
5009 18:11:42.122059 LPDDR4 DRAM CONFIGURATION
5010 18:11:42.125100 ===================================
5011 18:11:42.128519 EX_ROW_EN[0] = 0x10
5012 18:11:42.128617 EX_ROW_EN[1] = 0x0
5013 18:11:42.132250 LP4Y_EN = 0x0
5014 18:11:42.132337 WORK_FSP = 0x0
5015 18:11:42.135361 WL = 0x3
5016 18:11:42.135446 RL = 0x3
5017 18:11:42.138772 BL = 0x2
5018 18:11:42.141807 RPST = 0x0
5019 18:11:42.141893 RD_PRE = 0x0
5020 18:11:42.145053 WR_PRE = 0x1
5021 18:11:42.145138 WR_PST = 0x0
5022 18:11:42.148502 DBI_WR = 0x0
5023 18:11:42.148596 DBI_RD = 0x0
5024 18:11:42.152042 OTF = 0x1
5025 18:11:42.155088 ===================================
5026 18:11:42.158367 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5027 18:11:42.163885 nWR fixed to 30
5028 18:11:42.166977 [ModeRegInit_LP4] CH0 RK0
5029 18:11:42.167077 [ModeRegInit_LP4] CH0 RK1
5030 18:11:42.170439 [ModeRegInit_LP4] CH1 RK0
5031 18:11:42.173944 [ModeRegInit_LP4] CH1 RK1
5032 18:11:42.174080 match AC timing 9
5033 18:11:42.180509 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5034 18:11:42.183567 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5035 18:11:42.187081 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5036 18:11:42.193678 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5037 18:11:42.196837 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5038 18:11:42.196931 ==
5039 18:11:42.200264 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 18:11:42.203560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5041 18:11:42.203651 ==
5042 18:11:42.210300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5043 18:11:42.216687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5044 18:11:42.220148 [CA 0] Center 38 (7~69) winsize 63
5045 18:11:42.223729 [CA 1] Center 38 (8~69) winsize 62
5046 18:11:42.226580 [CA 2] Center 35 (5~66) winsize 62
5047 18:11:42.230027 [CA 3] Center 34 (4~65) winsize 62
5048 18:11:42.233722 [CA 4] Center 34 (4~65) winsize 62
5049 18:11:42.236756 [CA 5] Center 33 (3~64) winsize 62
5050 18:11:42.236843
5051 18:11:42.239846 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5052 18:11:42.239931
5053 18:11:42.243245 [CATrainingPosCal] consider 1 rank data
5054 18:11:42.246697 u2DelayCellTimex100 = 270/100 ps
5055 18:11:42.250004 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5056 18:11:42.253144 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5057 18:11:42.256685 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5058 18:11:42.260142 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5059 18:11:42.263047 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5060 18:11:42.269942 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5061 18:11:42.270070
5062 18:11:42.273118 CA PerBit enable=1, Macro0, CA PI delay=33
5063 18:11:42.273204
5064 18:11:42.276667 [CBTSetCACLKResult] CA Dly = 33
5065 18:11:42.276753 CS Dly: 6 (0~37)
5066 18:11:42.276820 ==
5067 18:11:42.279743 Dram Type= 6, Freq= 0, CH_0, rank 1
5068 18:11:42.283190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 18:11:42.286710 ==
5070 18:11:42.289719 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 18:11:42.296701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5072 18:11:42.299750 [CA 0] Center 38 (8~69) winsize 62
5073 18:11:42.303238 [CA 1] Center 38 (8~69) winsize 62
5074 18:11:42.306397 [CA 2] Center 36 (6~66) winsize 61
5075 18:11:42.309894 [CA 3] Center 35 (5~66) winsize 62
5076 18:11:42.312966 [CA 4] Center 35 (4~66) winsize 63
5077 18:11:42.316456 [CA 5] Center 34 (4~65) winsize 62
5078 18:11:42.316544
5079 18:11:42.319880 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5080 18:11:42.319965
5081 18:11:42.322869 [CATrainingPosCal] consider 2 rank data
5082 18:11:42.326230 u2DelayCellTimex100 = 270/100 ps
5083 18:11:42.329608 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5084 18:11:42.333183 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5085 18:11:42.336466 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5086 18:11:42.339501 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5087 18:11:42.346368 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5088 18:11:42.349757 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5089 18:11:42.349848
5090 18:11:42.352886 CA PerBit enable=1, Macro0, CA PI delay=34
5091 18:11:42.353013
5092 18:11:42.355951 [CBTSetCACLKResult] CA Dly = 34
5093 18:11:42.356045 CS Dly: 7 (0~39)
5094 18:11:42.356114
5095 18:11:42.359379 ----->DramcWriteLeveling(PI) begin...
5096 18:11:42.359465 ==
5097 18:11:42.363007 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 18:11:42.369442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 18:11:42.369541 ==
5100 18:11:42.372938 Write leveling (Byte 0): 31 => 31
5101 18:11:42.376004 Write leveling (Byte 1): 30 => 30
5102 18:11:42.376091 DramcWriteLeveling(PI) end<-----
5103 18:11:42.376157
5104 18:11:42.379531 ==
5105 18:11:42.382535 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 18:11:42.386006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 18:11:42.386100 ==
5108 18:11:42.389575 [Gating] SW mode calibration
5109 18:11:42.396036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5110 18:11:42.399081 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5111 18:11:42.406154 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5112 18:11:42.409198 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 18:11:42.412952 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 18:11:42.418979 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 18:11:42.422537 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 18:11:42.425907 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 18:11:42.432296 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5118 18:11:42.435794 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
5119 18:11:42.439203 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5120 18:11:42.446001 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 18:11:42.448892 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 18:11:42.452270 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 18:11:42.459245 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 18:11:42.462618 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 18:11:42.465602 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5126 18:11:42.472399 0 15 28 | B1->B0 | 2e2e 4646 | 1 0 | (1 1) (0 0)
5127 18:11:42.475820 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5128 18:11:42.478842 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 18:11:42.485752 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 18:11:42.488908 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 18:11:42.492303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 18:11:42.498901 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 18:11:42.501973 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5134 18:11:42.505491 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5135 18:11:42.508959 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 18:11:42.515339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 18:11:42.518786 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 18:11:42.522193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 18:11:42.528801 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 18:11:42.531873 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 18:11:42.535285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 18:11:42.541974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 18:11:42.545403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 18:11:42.548954 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 18:11:42.555515 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 18:11:42.558958 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 18:11:42.562245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 18:11:42.568385 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 18:11:42.571796 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5150 18:11:42.575134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5151 18:11:42.581831 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5152 18:11:42.581937 Total UI for P1: 0, mck2ui 16
5153 18:11:42.588471 best dqsien dly found for B0: ( 1, 2, 26)
5154 18:11:42.591975 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 18:11:42.595463 Total UI for P1: 0, mck2ui 16
5156 18:11:42.598554 best dqsien dly found for B1: ( 1, 2, 30)
5157 18:11:42.601962 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5158 18:11:42.605022 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5159 18:11:42.605109
5160 18:11:42.608594 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5161 18:11:42.611660 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5162 18:11:42.615152 [Gating] SW calibration Done
5163 18:11:42.615239 ==
5164 18:11:42.618144 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 18:11:42.621568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 18:11:42.624758 ==
5167 18:11:42.624845 RX Vref Scan: 0
5168 18:11:42.624910
5169 18:11:42.628348 RX Vref 0 -> 0, step: 1
5170 18:11:42.628433
5171 18:11:42.631850 RX Delay -80 -> 252, step: 8
5172 18:11:42.634777 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5173 18:11:42.638188 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5174 18:11:42.641642 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5175 18:11:42.644903 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5176 18:11:42.651478 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5177 18:11:42.654513 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5178 18:11:42.657694 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5179 18:11:42.661408 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5180 18:11:42.664713 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5181 18:11:42.667795 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5182 18:11:42.674695 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5183 18:11:42.677993 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5184 18:11:42.680984 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5185 18:11:42.684587 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5186 18:11:42.687652 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5187 18:11:42.691233 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5188 18:11:42.694166 ==
5189 18:11:42.697622 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 18:11:42.700865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 18:11:42.700954 ==
5192 18:11:42.701021 DQS Delay:
5193 18:11:42.704387 DQS0 = 0, DQS1 = 0
5194 18:11:42.704475 DQM Delay:
5195 18:11:42.707847 DQM0 = 106, DQM1 = 90
5196 18:11:42.707932 DQ Delay:
5197 18:11:42.710834 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5198 18:11:42.714318 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5199 18:11:42.717777 DQ8 =87, DQ9 =79, DQ10 =91, DQ11 =87
5200 18:11:42.720852 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5201 18:11:42.720940
5202 18:11:42.721006
5203 18:11:42.721066 ==
5204 18:11:42.724358 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 18:11:42.727792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 18:11:42.727880 ==
5207 18:11:42.730755
5208 18:11:42.730841
5209 18:11:42.730907 TX Vref Scan disable
5210 18:11:42.734308 == TX Byte 0 ==
5211 18:11:42.737800 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5212 18:11:42.740834 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5213 18:11:42.744143 == TX Byte 1 ==
5214 18:11:42.747107 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5215 18:11:42.750680 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5216 18:11:42.750769 ==
5217 18:11:42.753655 Dram Type= 6, Freq= 0, CH_0, rank 0
5218 18:11:42.760350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5219 18:11:42.760493 ==
5220 18:11:42.760587
5221 18:11:42.760665
5222 18:11:42.760724 TX Vref Scan disable
5223 18:11:42.764730 == TX Byte 0 ==
5224 18:11:42.768062 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5225 18:11:42.774890 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5226 18:11:42.775027 == TX Byte 1 ==
5227 18:11:42.778237 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5228 18:11:42.784933 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5229 18:11:42.785072
5230 18:11:42.785140 [DATLAT]
5231 18:11:42.785202 Freq=933, CH0 RK0
5232 18:11:42.785261
5233 18:11:42.788328 DATLAT Default: 0xd
5234 18:11:42.788422 0, 0xFFFF, sum = 0
5235 18:11:42.791335 1, 0xFFFF, sum = 0
5236 18:11:42.791428 2, 0xFFFF, sum = 0
5237 18:11:42.794775 3, 0xFFFF, sum = 0
5238 18:11:42.797887 4, 0xFFFF, sum = 0
5239 18:11:42.797993 5, 0xFFFF, sum = 0
5240 18:11:42.801391 6, 0xFFFF, sum = 0
5241 18:11:42.801498 7, 0xFFFF, sum = 0
5242 18:11:42.804870 8, 0xFFFF, sum = 0
5243 18:11:42.804971 9, 0xFFFF, sum = 0
5244 18:11:42.807831 10, 0x0, sum = 1
5245 18:11:42.807920 11, 0x0, sum = 2
5246 18:11:42.811276 12, 0x0, sum = 3
5247 18:11:42.811367 13, 0x0, sum = 4
5248 18:11:42.811436 best_step = 11
5249 18:11:42.811498
5250 18:11:42.814862 ==
5251 18:11:42.817989 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 18:11:42.820969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 18:11:42.821078 ==
5254 18:11:42.821147 RX Vref Scan: 1
5255 18:11:42.821211
5256 18:11:42.824493 RX Vref 0 -> 0, step: 1
5257 18:11:42.824632
5258 18:11:42.827975 RX Delay -53 -> 252, step: 4
5259 18:11:42.828062
5260 18:11:42.830942 Set Vref, RX VrefLevel [Byte0]: 60
5261 18:11:42.834244 [Byte1]: 49
5262 18:11:42.834348
5263 18:11:42.837772 Final RX Vref Byte 0 = 60 to rank0
5264 18:11:42.840921 Final RX Vref Byte 1 = 49 to rank0
5265 18:11:42.844325 Final RX Vref Byte 0 = 60 to rank1
5266 18:11:42.847816 Final RX Vref Byte 1 = 49 to rank1==
5267 18:11:42.851306 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 18:11:42.854275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 18:11:42.857861 ==
5270 18:11:42.857977 DQS Delay:
5271 18:11:42.858044 DQS0 = 0, DQS1 = 0
5272 18:11:42.860935 DQM Delay:
5273 18:11:42.861029 DQM0 = 108, DQM1 = 91
5274 18:11:42.864597 DQ Delay:
5275 18:11:42.867465 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5276 18:11:42.871121 DQ4 =108, DQ5 =100, DQ6 =120, DQ7 =116
5277 18:11:42.874512 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5278 18:11:42.877405 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =98
5279 18:11:42.877511
5280 18:11:42.877579
5281 18:11:42.884586 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5282 18:11:42.887350 CH0 RK0: MR19=505, MR18=2622
5283 18:11:42.894360 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5284 18:11:42.894512
5285 18:11:42.897515 ----->DramcWriteLeveling(PI) begin...
5286 18:11:42.897628 ==
5287 18:11:42.900970 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 18:11:42.904174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 18:11:42.904290 ==
5290 18:11:42.907555 Write leveling (Byte 0): 34 => 34
5291 18:11:42.910743 Write leveling (Byte 1): 29 => 29
5292 18:11:42.914165 DramcWriteLeveling(PI) end<-----
5293 18:11:42.914264
5294 18:11:42.914332 ==
5295 18:11:42.917620 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 18:11:42.920513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 18:11:42.924051 ==
5298 18:11:42.924167 [Gating] SW mode calibration
5299 18:11:42.930744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5300 18:11:42.937145 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5301 18:11:42.940600 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 18:11:42.947245 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 18:11:42.950840 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 18:11:42.954004 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 18:11:42.960504 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 18:11:42.964113 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 18:11:42.967259 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5308 18:11:42.974043 0 14 28 | B1->B0 | 2c2c 2727 | 1 1 | (0 1) (1 0)
5309 18:11:42.976990 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 18:11:42.980740 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 18:11:42.987509 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 18:11:42.990956 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 18:11:42.993742 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 18:11:42.997154 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 18:11:43.003732 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5316 18:11:43.007370 0 15 28 | B1->B0 | 3a3a 3e3d | 0 1 | (0 0) (0 0)
5317 18:11:43.010661 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 18:11:43.017251 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 18:11:43.020744 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 18:11:43.023693 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 18:11:43.030301 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 18:11:43.033886 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 18:11:43.036869 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5324 18:11:43.043921 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5325 18:11:43.046898 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 18:11:43.050533 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 18:11:43.057047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 18:11:43.060255 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 18:11:43.063368 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 18:11:43.070370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 18:11:43.073215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 18:11:43.076764 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 18:11:43.083464 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 18:11:43.086887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 18:11:43.090151 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 18:11:43.096906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 18:11:43.100297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 18:11:43.103606 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 18:11:43.110211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 18:11:43.113643 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5341 18:11:43.116752 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 18:11:43.120220 Total UI for P1: 0, mck2ui 16
5343 18:11:43.123600 best dqsien dly found for B0: ( 1, 2, 28)
5344 18:11:43.126687 Total UI for P1: 0, mck2ui 16
5345 18:11:43.130160 best dqsien dly found for B1: ( 1, 2, 28)
5346 18:11:43.133291 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5347 18:11:43.136542 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5348 18:11:43.136661
5349 18:11:43.140161 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5350 18:11:43.146659 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5351 18:11:43.146759 [Gating] SW calibration Done
5352 18:11:43.146825 ==
5353 18:11:43.150087 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 18:11:43.156365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 18:11:43.156458 ==
5356 18:11:43.156525 RX Vref Scan: 0
5357 18:11:43.156594
5358 18:11:43.159709 RX Vref 0 -> 0, step: 1
5359 18:11:43.159792
5360 18:11:43.163217 RX Delay -80 -> 252, step: 8
5361 18:11:43.166239 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5362 18:11:43.169918 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5363 18:11:43.172831 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5364 18:11:43.176242 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5365 18:11:43.183247 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5366 18:11:43.186671 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5367 18:11:43.189634 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5368 18:11:43.193077 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5369 18:11:43.196280 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5370 18:11:43.203161 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5371 18:11:43.206299 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5372 18:11:43.209785 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5373 18:11:43.212932 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5374 18:11:43.216358 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5375 18:11:43.219537 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5376 18:11:43.225947 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5377 18:11:43.226052 ==
5378 18:11:43.229573 Dram Type= 6, Freq= 0, CH_0, rank 1
5379 18:11:43.233103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5380 18:11:43.233195 ==
5381 18:11:43.233262 DQS Delay:
5382 18:11:43.236111 DQS0 = 0, DQS1 = 0
5383 18:11:43.236197 DQM Delay:
5384 18:11:43.239594 DQM0 = 105, DQM1 = 91
5385 18:11:43.239681 DQ Delay:
5386 18:11:43.242645 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5387 18:11:43.246266 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5388 18:11:43.249818 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5389 18:11:43.252759 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5390 18:11:43.252846
5391 18:11:43.252914
5392 18:11:43.252976 ==
5393 18:11:43.256115 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 18:11:43.259248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 18:11:43.262611 ==
5396 18:11:43.262699
5397 18:11:43.262766
5398 18:11:43.262827 TX Vref Scan disable
5399 18:11:43.266236 == TX Byte 0 ==
5400 18:11:43.269070 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5401 18:11:43.272427 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5402 18:11:43.275993 == TX Byte 1 ==
5403 18:11:43.279537 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5404 18:11:43.282615 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5405 18:11:43.286067 ==
5406 18:11:43.286162 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 18:11:43.292486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 18:11:43.292619 ==
5409 18:11:43.292687
5410 18:11:43.292747
5411 18:11:43.296082 TX Vref Scan disable
5412 18:11:43.296167 == TX Byte 0 ==
5413 18:11:43.302505 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5414 18:11:43.305900 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5415 18:11:43.305994 == TX Byte 1 ==
5416 18:11:43.312715 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5417 18:11:43.315677 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5418 18:11:43.315769
5419 18:11:43.315835 [DATLAT]
5420 18:11:43.319382 Freq=933, CH0 RK1
5421 18:11:43.319467
5422 18:11:43.319532 DATLAT Default: 0xb
5423 18:11:43.322445 0, 0xFFFF, sum = 0
5424 18:11:43.322530 1, 0xFFFF, sum = 0
5425 18:11:43.326076 2, 0xFFFF, sum = 0
5426 18:11:43.326162 3, 0xFFFF, sum = 0
5427 18:11:43.329365 4, 0xFFFF, sum = 0
5428 18:11:43.329454 5, 0xFFFF, sum = 0
5429 18:11:43.332429 6, 0xFFFF, sum = 0
5430 18:11:43.332516 7, 0xFFFF, sum = 0
5431 18:11:43.335974 8, 0xFFFF, sum = 0
5432 18:11:43.336062 9, 0xFFFF, sum = 0
5433 18:11:43.338997 10, 0x0, sum = 1
5434 18:11:43.339103 11, 0x0, sum = 2
5435 18:11:43.342580 12, 0x0, sum = 3
5436 18:11:43.342667 13, 0x0, sum = 4
5437 18:11:43.345610 best_step = 11
5438 18:11:43.345695
5439 18:11:43.345761 ==
5440 18:11:43.349212 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 18:11:43.352150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 18:11:43.352237 ==
5443 18:11:43.356018 RX Vref Scan: 0
5444 18:11:43.356103
5445 18:11:43.356169 RX Vref 0 -> 0, step: 1
5446 18:11:43.356230
5447 18:11:43.359068 RX Delay -53 -> 252, step: 4
5448 18:11:43.366043 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5449 18:11:43.369605 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5450 18:11:43.372583 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5451 18:11:43.375881 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5452 18:11:43.379285 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5453 18:11:43.385855 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5454 18:11:43.389519 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5455 18:11:43.392431 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5456 18:11:43.395758 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5457 18:11:43.399083 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5458 18:11:43.405646 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5459 18:11:43.408959 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5460 18:11:43.412160 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5461 18:11:43.415897 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5462 18:11:43.418851 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5463 18:11:43.425567 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5464 18:11:43.425675 ==
5465 18:11:43.428998 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 18:11:43.432492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 18:11:43.432618 ==
5468 18:11:43.432684 DQS Delay:
5469 18:11:43.435479 DQS0 = 0, DQS1 = 0
5470 18:11:43.435563 DQM Delay:
5471 18:11:43.439115 DQM0 = 104, DQM1 = 92
5472 18:11:43.439211 DQ Delay:
5473 18:11:43.442107 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5474 18:11:43.445461 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5475 18:11:43.449113 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =92
5476 18:11:43.452126 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5477 18:11:43.452213
5478 18:11:43.452280
5479 18:11:43.462062 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5480 18:11:43.462170 CH0 RK1: MR19=505, MR18=2606
5481 18:11:43.468830 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5482 18:11:43.472257 [RxdqsGatingPostProcess] freq 933
5483 18:11:43.478765 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5484 18:11:43.482013 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 18:11:43.485439 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 18:11:43.488979 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 18:11:43.492111 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 18:11:43.492204 best DQS0 dly(2T, 0.5T) = (0, 10)
5489 18:11:43.495581 best DQS1 dly(2T, 0.5T) = (0, 10)
5490 18:11:43.498489 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5491 18:11:43.501819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5492 18:11:43.505468 Pre-setting of DQS Precalculation
5493 18:11:43.512102 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5494 18:11:43.512223 ==
5495 18:11:43.515026 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 18:11:43.518701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 18:11:43.518800 ==
5498 18:11:43.525028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5499 18:11:43.531594 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5500 18:11:43.535166 [CA 0] Center 37 (7~68) winsize 62
5501 18:11:43.538150 [CA 1] Center 37 (7~68) winsize 62
5502 18:11:43.541711 [CA 2] Center 36 (6~66) winsize 61
5503 18:11:43.544828 [CA 3] Center 34 (4~65) winsize 62
5504 18:11:43.548295 [CA 4] Center 35 (5~66) winsize 62
5505 18:11:43.552009 [CA 5] Center 34 (4~65) winsize 62
5506 18:11:43.552100
5507 18:11:43.554854 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5508 18:11:43.554939
5509 18:11:43.558329 [CATrainingPosCal] consider 1 rank data
5510 18:11:43.561376 u2DelayCellTimex100 = 270/100 ps
5511 18:11:43.564821 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5512 18:11:43.568271 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5513 18:11:43.571381 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5514 18:11:43.574881 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5515 18:11:43.577884 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5516 18:11:43.581432 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5517 18:11:43.581522
5518 18:11:43.588274 CA PerBit enable=1, Macro0, CA PI delay=34
5519 18:11:43.588381
5520 18:11:43.588450 [CBTSetCACLKResult] CA Dly = 34
5521 18:11:43.591312 CS Dly: 6 (0~37)
5522 18:11:43.591397 ==
5523 18:11:43.594883 Dram Type= 6, Freq= 0, CH_1, rank 1
5524 18:11:43.598005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 18:11:43.598092 ==
5526 18:11:43.604924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 18:11:43.611634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 18:11:43.614966 [CA 0] Center 38 (8~69) winsize 62
5529 18:11:43.618342 [CA 1] Center 38 (8~69) winsize 62
5530 18:11:43.621790 [CA 2] Center 35 (5~66) winsize 62
5531 18:11:43.625111 [CA 3] Center 35 (5~65) winsize 61
5532 18:11:43.628381 [CA 4] Center 35 (5~65) winsize 61
5533 18:11:43.631573 [CA 5] Center 34 (4~64) winsize 61
5534 18:11:43.631664
5535 18:11:43.634973 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 18:11:43.635060
5537 18:11:43.638539 [CATrainingPosCal] consider 2 rank data
5538 18:11:43.641566 u2DelayCellTimex100 = 270/100 ps
5539 18:11:43.645124 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5540 18:11:43.648127 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5541 18:11:43.651700 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5542 18:11:43.654797 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5543 18:11:43.658285 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5544 18:11:43.661735 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5545 18:11:43.661830
5546 18:11:43.668094 CA PerBit enable=1, Macro0, CA PI delay=34
5547 18:11:43.668255
5548 18:11:43.668354 [CBTSetCACLKResult] CA Dly = 34
5549 18:11:43.671176 CS Dly: 7 (0~39)
5550 18:11:43.671262
5551 18:11:43.674837 ----->DramcWriteLeveling(PI) begin...
5552 18:11:43.674925 ==
5553 18:11:43.678367 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 18:11:43.681254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 18:11:43.681342 ==
5556 18:11:43.684766 Write leveling (Byte 0): 28 => 28
5557 18:11:43.688196 Write leveling (Byte 1): 28 => 28
5558 18:11:43.691598 DramcWriteLeveling(PI) end<-----
5559 18:11:43.691689
5560 18:11:43.691756 ==
5561 18:11:43.694581 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 18:11:43.698219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 18:11:43.701265 ==
5564 18:11:43.701352 [Gating] SW mode calibration
5565 18:11:43.711135 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5566 18:11:43.714541 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5567 18:11:43.717810 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 18:11:43.724521 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 18:11:43.727700 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 18:11:43.731017 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 18:11:43.737358 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 18:11:43.740968 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5573 18:11:43.744467 0 14 24 | B1->B0 | 3030 3131 | 0 0 | (0 1) (0 1)
5574 18:11:43.751168 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 18:11:43.754155 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 18:11:43.757708 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 18:11:43.764302 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 18:11:43.767738 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 18:11:43.770593 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 18:11:43.777824 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 18:11:43.780859 0 15 24 | B1->B0 | 2727 2e2e | 0 0 | (0 0) (0 0)
5582 18:11:43.784256 0 15 28 | B1->B0 | 4444 3f3f | 0 0 | (0 0) (0 0)
5583 18:11:43.790747 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 18:11:43.794111 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 18:11:43.797621 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 18:11:43.804340 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 18:11:43.807280 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 18:11:43.810290 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 18:11:43.817023 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5590 18:11:43.820468 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 18:11:43.823763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 18:11:43.830618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 18:11:43.833906 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 18:11:43.837258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 18:11:43.843883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 18:11:43.846964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 18:11:43.850359 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 18:11:43.857039 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 18:11:43.860530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 18:11:43.863818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 18:11:43.867134 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 18:11:43.873803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 18:11:43.876831 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 18:11:43.880569 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5605 18:11:43.887134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 18:11:43.890613 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5607 18:11:43.893632 Total UI for P1: 0, mck2ui 16
5608 18:11:43.896987 best dqsien dly found for B0: ( 1, 2, 22)
5609 18:11:43.900324 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 18:11:43.903359 Total UI for P1: 0, mck2ui 16
5611 18:11:43.906853 best dqsien dly found for B1: ( 1, 2, 26)
5612 18:11:43.909870 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5613 18:11:43.913453 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5614 18:11:43.916680
5615 18:11:43.920060 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5616 18:11:43.923469 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5617 18:11:43.926517 [Gating] SW calibration Done
5618 18:11:43.926604 ==
5619 18:11:43.930095 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 18:11:43.933243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 18:11:43.933330 ==
5622 18:11:43.933397 RX Vref Scan: 0
5623 18:11:43.933459
5624 18:11:43.936560 RX Vref 0 -> 0, step: 1
5625 18:11:43.936679
5626 18:11:43.939971 RX Delay -80 -> 252, step: 8
5627 18:11:43.943591 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5628 18:11:43.946668 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5629 18:11:43.953433 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5630 18:11:43.956797 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5631 18:11:43.959892 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5632 18:11:43.963353 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5633 18:11:43.967052 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5634 18:11:43.970033 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5635 18:11:43.976412 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5636 18:11:43.979724 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5637 18:11:43.983140 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5638 18:11:43.986763 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5639 18:11:43.989777 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5640 18:11:43.993217 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5641 18:11:43.999670 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5642 18:11:44.002947 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5643 18:11:44.003044 ==
5644 18:11:44.006344 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 18:11:44.010002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 18:11:44.010089 ==
5647 18:11:44.012862 DQS Delay:
5648 18:11:44.012946 DQS0 = 0, DQS1 = 0
5649 18:11:44.013011 DQM Delay:
5650 18:11:44.016371 DQM0 = 102, DQM1 = 95
5651 18:11:44.016454 DQ Delay:
5652 18:11:44.019727 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =103
5653 18:11:44.023175 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5654 18:11:44.026540 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5655 18:11:44.029916 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5656 18:11:44.030003
5657 18:11:44.030069
5658 18:11:44.033229 ==
5659 18:11:44.033313 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 18:11:44.039625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 18:11:44.039736 ==
5662 18:11:44.039804
5663 18:11:44.039865
5664 18:11:44.042997 TX Vref Scan disable
5665 18:11:44.043083 == TX Byte 0 ==
5666 18:11:44.046486 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5667 18:11:44.053038 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5668 18:11:44.053132 == TX Byte 1 ==
5669 18:11:44.056018 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5670 18:11:44.062757 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5671 18:11:44.062856 ==
5672 18:11:44.066216 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 18:11:44.069378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 18:11:44.069465 ==
5675 18:11:44.069532
5676 18:11:44.069592
5677 18:11:44.073069 TX Vref Scan disable
5678 18:11:44.075802 == TX Byte 0 ==
5679 18:11:44.079512 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5680 18:11:44.082881 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5681 18:11:44.085895 == TX Byte 1 ==
5682 18:11:44.089342 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5683 18:11:44.092793 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5684 18:11:44.092890
5685 18:11:44.092959 [DATLAT]
5686 18:11:44.095844 Freq=933, CH1 RK0
5687 18:11:44.095928
5688 18:11:44.099272 DATLAT Default: 0xd
5689 18:11:44.099357 0, 0xFFFF, sum = 0
5690 18:11:44.102785 1, 0xFFFF, sum = 0
5691 18:11:44.102870 2, 0xFFFF, sum = 0
5692 18:11:44.105777 3, 0xFFFF, sum = 0
5693 18:11:44.105862 4, 0xFFFF, sum = 0
5694 18:11:44.109203 5, 0xFFFF, sum = 0
5695 18:11:44.109290 6, 0xFFFF, sum = 0
5696 18:11:44.112772 7, 0xFFFF, sum = 0
5697 18:11:44.112860 8, 0xFFFF, sum = 0
5698 18:11:44.115873 9, 0xFFFF, sum = 0
5699 18:11:44.115976 10, 0x0, sum = 1
5700 18:11:44.119376 11, 0x0, sum = 2
5701 18:11:44.119463 12, 0x0, sum = 3
5702 18:11:44.122532 13, 0x0, sum = 4
5703 18:11:44.122620 best_step = 11
5704 18:11:44.122689
5705 18:11:44.122749 ==
5706 18:11:44.125721 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 18:11:44.129199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 18:11:44.132836 ==
5709 18:11:44.132915 RX Vref Scan: 1
5710 18:11:44.132979
5711 18:11:44.136058 RX Vref 0 -> 0, step: 1
5712 18:11:44.136135
5713 18:11:44.136197 RX Delay -53 -> 252, step: 4
5714 18:11:44.139199
5715 18:11:44.139274 Set Vref, RX VrefLevel [Byte0]: 52
5716 18:11:44.142648 [Byte1]: 52
5717 18:11:44.147442
5718 18:11:44.147547 Final RX Vref Byte 0 = 52 to rank0
5719 18:11:44.150653 Final RX Vref Byte 1 = 52 to rank0
5720 18:11:44.153884 Final RX Vref Byte 0 = 52 to rank1
5721 18:11:44.157274 Final RX Vref Byte 1 = 52 to rank1==
5722 18:11:44.160693 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 18:11:44.167288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 18:11:44.167395 ==
5725 18:11:44.167464 DQS Delay:
5726 18:11:44.170440 DQS0 = 0, DQS1 = 0
5727 18:11:44.170526 DQM Delay:
5728 18:11:44.170594 DQM0 = 103, DQM1 = 96
5729 18:11:44.173823 DQ Delay:
5730 18:11:44.176938 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5731 18:11:44.180406 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5732 18:11:44.183859 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5733 18:11:44.186873 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5734 18:11:44.186967
5735 18:11:44.187053
5736 18:11:44.193808 [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5737 18:11:44.196865 CH1 RK0: MR19=505, MR18=1931
5738 18:11:44.203820 CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43
5739 18:11:44.203938
5740 18:11:44.207045 ----->DramcWriteLeveling(PI) begin...
5741 18:11:44.207138 ==
5742 18:11:44.210185 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 18:11:44.213525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 18:11:44.217152 ==
5745 18:11:44.217241 Write leveling (Byte 0): 29 => 29
5746 18:11:44.220163 Write leveling (Byte 1): 28 => 28
5747 18:11:44.223720 DramcWriteLeveling(PI) end<-----
5748 18:11:44.223805
5749 18:11:44.223871 ==
5750 18:11:44.227222 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 18:11:44.233584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 18:11:44.233685 ==
5753 18:11:44.233753 [Gating] SW mode calibration
5754 18:11:44.243342 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5755 18:11:44.246669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5756 18:11:44.253470 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5757 18:11:44.256944 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 18:11:44.260011 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 18:11:44.266542 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 18:11:44.270178 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 18:11:44.273362 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 18:11:44.276938 0 14 24 | B1->B0 | 2f2f 3333 | 0 1 | (0 0) (1 1)
5763 18:11:44.283433 0 14 28 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
5764 18:11:44.286881 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 18:11:44.290016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 18:11:44.296855 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 18:11:44.300317 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 18:11:44.303284 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 18:11:44.310023 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 18:11:44.313511 0 15 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5771 18:11:44.316874 0 15 28 | B1->B0 | 4242 3939 | 0 0 | (0 0) (0 0)
5772 18:11:44.323564 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 18:11:44.326591 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 18:11:44.329980 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 18:11:44.336825 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 18:11:44.339854 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 18:11:44.343320 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 18:11:44.349807 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5779 18:11:44.353361 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 18:11:44.356526 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 18:11:44.363217 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 18:11:44.366925 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 18:11:44.369796 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 18:11:44.376322 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 18:11:44.379875 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 18:11:44.383439 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 18:11:44.386653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 18:11:44.392971 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 18:11:44.396511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 18:11:44.399624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 18:11:44.406643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 18:11:44.409591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 18:11:44.412835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 18:11:44.419538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5795 18:11:44.422842 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5796 18:11:44.426534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 18:11:44.429674 Total UI for P1: 0, mck2ui 16
5798 18:11:44.432914 best dqsien dly found for B0: ( 1, 2, 26)
5799 18:11:44.436308 Total UI for P1: 0, mck2ui 16
5800 18:11:44.439705 best dqsien dly found for B1: ( 1, 2, 26)
5801 18:11:44.443088 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5802 18:11:44.446680 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5803 18:11:44.446771
5804 18:11:44.453026 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5805 18:11:44.456394 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5806 18:11:44.456487 [Gating] SW calibration Done
5807 18:11:44.459787 ==
5808 18:11:44.462788 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 18:11:44.466185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 18:11:44.466304 ==
5811 18:11:44.466375 RX Vref Scan: 0
5812 18:11:44.466437
5813 18:11:44.469883 RX Vref 0 -> 0, step: 1
5814 18:11:44.469969
5815 18:11:44.472942 RX Delay -80 -> 252, step: 8
5816 18:11:44.476437 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5817 18:11:44.479351 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5818 18:11:44.482979 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5819 18:11:44.489363 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5820 18:11:44.492855 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5821 18:11:44.495982 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5822 18:11:44.499411 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5823 18:11:44.502536 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5824 18:11:44.505984 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5825 18:11:44.512897 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5826 18:11:44.515839 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5827 18:11:44.519202 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5828 18:11:44.522594 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5829 18:11:44.526100 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5830 18:11:44.529633 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5831 18:11:44.536207 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5832 18:11:44.536310 ==
5833 18:11:44.539359 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 18:11:44.542721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 18:11:44.542834 ==
5836 18:11:44.542929 DQS Delay:
5837 18:11:44.545935 DQS0 = 0, DQS1 = 0
5838 18:11:44.546020 DQM Delay:
5839 18:11:44.549206 DQM0 = 101, DQM1 = 96
5840 18:11:44.549293 DQ Delay:
5841 18:11:44.552672 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5842 18:11:44.556066 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5843 18:11:44.559129 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5844 18:11:44.562640 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5845 18:11:44.562731
5846 18:11:44.562797
5847 18:11:44.562857 ==
5848 18:11:44.566012 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 18:11:44.572371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 18:11:44.572479 ==
5851 18:11:44.572554
5852 18:11:44.572653
5853 18:11:44.572712 TX Vref Scan disable
5854 18:11:44.576277 == TX Byte 0 ==
5855 18:11:44.579306 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5856 18:11:44.586516 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5857 18:11:44.586621 == TX Byte 1 ==
5858 18:11:44.589473 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5859 18:11:44.596436 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5860 18:11:44.596606 ==
5861 18:11:44.599545 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 18:11:44.602672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 18:11:44.602759 ==
5864 18:11:44.602825
5865 18:11:44.602885
5866 18:11:44.606179 TX Vref Scan disable
5867 18:11:44.606263 == TX Byte 0 ==
5868 18:11:44.612675 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5869 18:11:44.616142 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5870 18:11:44.616233 == TX Byte 1 ==
5871 18:11:44.622526 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5872 18:11:44.625946 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5873 18:11:44.626037
5874 18:11:44.626103 [DATLAT]
5875 18:11:44.629345 Freq=933, CH1 RK1
5876 18:11:44.629430
5877 18:11:44.629495 DATLAT Default: 0xb
5878 18:11:44.632485 0, 0xFFFF, sum = 0
5879 18:11:44.632630 1, 0xFFFF, sum = 0
5880 18:11:44.635909 2, 0xFFFF, sum = 0
5881 18:11:44.635997 3, 0xFFFF, sum = 0
5882 18:11:44.639003 4, 0xFFFF, sum = 0
5883 18:11:44.642577 5, 0xFFFF, sum = 0
5884 18:11:44.642667 6, 0xFFFF, sum = 0
5885 18:11:44.646069 7, 0xFFFF, sum = 0
5886 18:11:44.646156 8, 0xFFFF, sum = 0
5887 18:11:44.649347 9, 0xFFFF, sum = 0
5888 18:11:44.649434 10, 0x0, sum = 1
5889 18:11:44.652637 11, 0x0, sum = 2
5890 18:11:44.652724 12, 0x0, sum = 3
5891 18:11:44.652790 13, 0x0, sum = 4
5892 18:11:44.655969 best_step = 11
5893 18:11:44.656052
5894 18:11:44.656117 ==
5895 18:11:44.658938 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 18:11:44.662476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 18:11:44.662564 ==
5898 18:11:44.665438 RX Vref Scan: 0
5899 18:11:44.665524
5900 18:11:44.669045 RX Vref 0 -> 0, step: 1
5901 18:11:44.669130
5902 18:11:44.669196 RX Delay -53 -> 252, step: 4
5903 18:11:44.676353 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5904 18:11:44.679964 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5905 18:11:44.682919 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5906 18:11:44.686390 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5907 18:11:44.689987 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5908 18:11:44.696437 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5909 18:11:44.699893 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5910 18:11:44.702955 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5911 18:11:44.706458 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5912 18:11:44.709459 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5913 18:11:44.716373 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5914 18:11:44.719516 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5915 18:11:44.722970 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5916 18:11:44.726553 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5917 18:11:44.729540 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5918 18:11:44.736002 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5919 18:11:44.736101 ==
5920 18:11:44.739648 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 18:11:44.742559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 18:11:44.742648 ==
5923 18:11:44.742715 DQS Delay:
5924 18:11:44.745956 DQS0 = 0, DQS1 = 0
5925 18:11:44.746043 DQM Delay:
5926 18:11:44.749552 DQM0 = 105, DQM1 = 97
5927 18:11:44.749636 DQ Delay:
5928 18:11:44.752870 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5929 18:11:44.756161 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5930 18:11:44.759539 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =92
5931 18:11:44.762848 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5932 18:11:44.762938
5933 18:11:44.763005
5934 18:11:44.772671 [DQSOSCAuto] RK1, (LSB)MR18= 0x2502, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5935 18:11:44.776187 CH1 RK1: MR19=505, MR18=2502
5936 18:11:44.779342 CH1_RK1: MR19=0x505, MR18=0x2502, DQSOSC=410, MR23=63, INC=64, DEC=42
5937 18:11:44.782415 [RxdqsGatingPostProcess] freq 933
5938 18:11:44.789537 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5939 18:11:44.792506 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 18:11:44.795941 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 18:11:44.799500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 18:11:44.802889 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 18:11:44.805828 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 18:11:44.809531 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 18:11:44.812395 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 18:11:44.815917 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 18:11:44.816006 Pre-setting of DQS Precalculation
5948 18:11:44.822623 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5949 18:11:44.829328 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5950 18:11:44.835749 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5951 18:11:44.835853
5952 18:11:44.835918
5953 18:11:44.839138 [Calibration Summary] 1866 Mbps
5954 18:11:44.842634 CH 0, Rank 0
5955 18:11:44.842724 SW Impedance : PASS
5956 18:11:44.845679 DUTY Scan : NO K
5957 18:11:44.848958 ZQ Calibration : PASS
5958 18:11:44.849047 Jitter Meter : NO K
5959 18:11:44.852462 CBT Training : PASS
5960 18:11:44.855410 Write leveling : PASS
5961 18:11:44.855495 RX DQS gating : PASS
5962 18:11:44.858854 RX DQ/DQS(RDDQC) : PASS
5963 18:11:44.858940 TX DQ/DQS : PASS
5964 18:11:44.862146 RX DATLAT : PASS
5965 18:11:44.865554 RX DQ/DQS(Engine): PASS
5966 18:11:44.865644 TX OE : NO K
5967 18:11:44.868966 All Pass.
5968 18:11:44.869052
5969 18:11:44.869118 CH 0, Rank 1
5970 18:11:44.872153 SW Impedance : PASS
5971 18:11:44.872237 DUTY Scan : NO K
5972 18:11:44.875554 ZQ Calibration : PASS
5973 18:11:44.879097 Jitter Meter : NO K
5974 18:11:44.879185 CBT Training : PASS
5975 18:11:44.882521 Write leveling : PASS
5976 18:11:44.885524 RX DQS gating : PASS
5977 18:11:44.885610 RX DQ/DQS(RDDQC) : PASS
5978 18:11:44.888691 TX DQ/DQS : PASS
5979 18:11:44.892019 RX DATLAT : PASS
5980 18:11:44.892105 RX DQ/DQS(Engine): PASS
5981 18:11:44.895713 TX OE : NO K
5982 18:11:44.895798 All Pass.
5983 18:11:44.895865
5984 18:11:44.898779 CH 1, Rank 0
5985 18:11:44.898862 SW Impedance : PASS
5986 18:11:44.902193 DUTY Scan : NO K
5987 18:11:44.905190 ZQ Calibration : PASS
5988 18:11:44.905275 Jitter Meter : NO K
5989 18:11:44.908756 CBT Training : PASS
5990 18:11:44.908843 Write leveling : PASS
5991 18:11:44.912185 RX DQS gating : PASS
5992 18:11:44.915285 RX DQ/DQS(RDDQC) : PASS
5993 18:11:44.915371 TX DQ/DQS : PASS
5994 18:11:44.918756 RX DATLAT : PASS
5995 18:11:44.922146 RX DQ/DQS(Engine): PASS
5996 18:11:44.922233 TX OE : NO K
5997 18:11:44.925586 All Pass.
5998 18:11:44.925672
5999 18:11:44.925776 CH 1, Rank 1
6000 18:11:44.928454 SW Impedance : PASS
6001 18:11:44.928587 DUTY Scan : NO K
6002 18:11:44.932078 ZQ Calibration : PASS
6003 18:11:44.935189 Jitter Meter : NO K
6004 18:11:44.935275 CBT Training : PASS
6005 18:11:44.938756 Write leveling : PASS
6006 18:11:44.941942 RX DQS gating : PASS
6007 18:11:44.942028 RX DQ/DQS(RDDQC) : PASS
6008 18:11:44.945363 TX DQ/DQS : PASS
6009 18:11:44.948878 RX DATLAT : PASS
6010 18:11:44.948965 RX DQ/DQS(Engine): PASS
6011 18:11:44.951967 TX OE : NO K
6012 18:11:44.952051 All Pass.
6013 18:11:44.952118
6014 18:11:44.955110 DramC Write-DBI off
6015 18:11:44.958178 PER_BANK_REFRESH: Hybrid Mode
6016 18:11:44.958267 TX_TRACKING: ON
6017 18:11:44.968314 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6018 18:11:44.971524 [FAST_K] Save calibration result to emmc
6019 18:11:44.974872 dramc_set_vcore_voltage set vcore to 650000
6020 18:11:44.978123 Read voltage for 400, 6
6021 18:11:44.978214 Vio18 = 0
6022 18:11:44.978280 Vcore = 650000
6023 18:11:44.981568 Vdram = 0
6024 18:11:44.981654 Vddq = 0
6025 18:11:44.981719 Vmddr = 0
6026 18:11:44.988340 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6027 18:11:44.991423 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6028 18:11:44.994856 MEM_TYPE=3, freq_sel=20
6029 18:11:44.997958 sv_algorithm_assistance_LP4_800
6030 18:11:45.001506 ============ PULL DRAM RESETB DOWN ============
6031 18:11:45.004894 ========== PULL DRAM RESETB DOWN end =========
6032 18:11:45.011151 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6033 18:11:45.014575 ===================================
6034 18:11:45.018153 LPDDR4 DRAM CONFIGURATION
6035 18:11:45.018243 ===================================
6036 18:11:45.021131 EX_ROW_EN[0] = 0x0
6037 18:11:45.024510 EX_ROW_EN[1] = 0x0
6038 18:11:45.024602 LP4Y_EN = 0x0
6039 18:11:45.027934 WORK_FSP = 0x0
6040 18:11:45.028021 WL = 0x2
6041 18:11:45.031258 RL = 0x2
6042 18:11:45.031344 BL = 0x2
6043 18:11:45.034794 RPST = 0x0
6044 18:11:45.034878 RD_PRE = 0x0
6045 18:11:45.037886 WR_PRE = 0x1
6046 18:11:45.037969 WR_PST = 0x0
6047 18:11:45.041325 DBI_WR = 0x0
6048 18:11:45.041408 DBI_RD = 0x0
6049 18:11:45.044350 OTF = 0x1
6050 18:11:45.047872 ===================================
6051 18:11:45.051228 ===================================
6052 18:11:45.051316 ANA top config
6053 18:11:45.054500 ===================================
6054 18:11:45.057585 DLL_ASYNC_EN = 0
6055 18:11:45.061506 ALL_SLAVE_EN = 1
6056 18:11:45.064512 NEW_RANK_MODE = 1
6057 18:11:45.064618 DLL_IDLE_MODE = 1
6058 18:11:45.067848 LP45_APHY_COMB_EN = 1
6059 18:11:45.071140 TX_ODT_DIS = 1
6060 18:11:45.074299 NEW_8X_MODE = 1
6061 18:11:45.077567 ===================================
6062 18:11:45.081021 ===================================
6063 18:11:45.084222 data_rate = 800
6064 18:11:45.084313 CKR = 1
6065 18:11:45.087722 DQ_P2S_RATIO = 4
6066 18:11:45.090806 ===================================
6067 18:11:45.094375 CA_P2S_RATIO = 4
6068 18:11:45.097509 DQ_CA_OPEN = 0
6069 18:11:45.100932 DQ_SEMI_OPEN = 1
6070 18:11:45.104333 CA_SEMI_OPEN = 1
6071 18:11:45.104424 CA_FULL_RATE = 0
6072 18:11:45.107500 DQ_CKDIV4_EN = 0
6073 18:11:45.110997 CA_CKDIV4_EN = 1
6074 18:11:45.114544 CA_PREDIV_EN = 0
6075 18:11:45.117501 PH8_DLY = 0
6076 18:11:45.121019 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6077 18:11:45.121110 DQ_AAMCK_DIV = 0
6078 18:11:45.124133 CA_AAMCK_DIV = 0
6079 18:11:45.127560 CA_ADMCK_DIV = 4
6080 18:11:45.131107 DQ_TRACK_CA_EN = 0
6081 18:11:45.133967 CA_PICK = 800
6082 18:11:45.137587 CA_MCKIO = 400
6083 18:11:45.141026 MCKIO_SEMI = 400
6084 18:11:45.141118 PLL_FREQ = 3016
6085 18:11:45.144170 DQ_UI_PI_RATIO = 32
6086 18:11:45.147560 CA_UI_PI_RATIO = 32
6087 18:11:45.151078 ===================================
6088 18:11:45.154176 ===================================
6089 18:11:45.157568 memory_type:LPDDR4
6090 18:11:45.157660 GP_NUM : 10
6091 18:11:45.161001 SRAM_EN : 1
6092 18:11:45.164215 MD32_EN : 0
6093 18:11:45.167179 ===================================
6094 18:11:45.167291 [ANA_INIT] >>>>>>>>>>>>>>
6095 18:11:45.170833 <<<<<< [CONFIGURE PHASE]: ANA_TX
6096 18:11:45.174077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6097 18:11:45.177464 ===================================
6098 18:11:45.180518 data_rate = 800,PCW = 0X7400
6099 18:11:45.183971 ===================================
6100 18:11:45.187268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6101 18:11:45.193940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 18:11:45.203976 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 18:11:45.210622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6104 18:11:45.214146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6105 18:11:45.217296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6106 18:11:45.217496 [ANA_INIT] flow start
6107 18:11:45.220350 [ANA_INIT] PLL >>>>>>>>
6108 18:11:45.223753 [ANA_INIT] PLL <<<<<<<<
6109 18:11:45.223843 [ANA_INIT] MIDPI >>>>>>>>
6110 18:11:45.227325 [ANA_INIT] MIDPI <<<<<<<<
6111 18:11:45.230355 [ANA_INIT] DLL >>>>>>>>
6112 18:11:45.230470 [ANA_INIT] flow end
6113 18:11:45.237239 ============ LP4 DIFF to SE enter ============
6114 18:11:45.240509 ============ LP4 DIFF to SE exit ============
6115 18:11:45.243675 [ANA_INIT] <<<<<<<<<<<<<
6116 18:11:45.247196 [Flow] Enable top DCM control >>>>>
6117 18:11:45.250183 [Flow] Enable top DCM control <<<<<
6118 18:11:45.250273 Enable DLL master slave shuffle
6119 18:11:45.257212 ==============================================================
6120 18:11:45.260179 Gating Mode config
6121 18:11:45.263720 ==============================================================
6122 18:11:45.266650 Config description:
6123 18:11:45.276934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6124 18:11:45.283523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6125 18:11:45.287047 SELPH_MODE 0: By rank 1: By Phase
6126 18:11:45.293472 ==============================================================
6127 18:11:45.296838 GAT_TRACK_EN = 0
6128 18:11:45.300195 RX_GATING_MODE = 2
6129 18:11:45.303241 RX_GATING_TRACK_MODE = 2
6130 18:11:45.306891 SELPH_MODE = 1
6131 18:11:45.306981 PICG_EARLY_EN = 1
6132 18:11:45.309982 VALID_LAT_VALUE = 1
6133 18:11:45.316612 ==============================================================
6134 18:11:45.320230 Enter into Gating configuration >>>>
6135 18:11:45.323895 Exit from Gating configuration <<<<
6136 18:11:45.326918 Enter into DVFS_PRE_config >>>>>
6137 18:11:45.336796 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6138 18:11:45.339935 Exit from DVFS_PRE_config <<<<<
6139 18:11:45.343370 Enter into PICG configuration >>>>
6140 18:11:45.346887 Exit from PICG configuration <<<<
6141 18:11:45.349895 [RX_INPUT] configuration >>>>>
6142 18:11:45.353517 [RX_INPUT] configuration <<<<<
6143 18:11:45.356838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6144 18:11:45.363481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6145 18:11:45.370237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 18:11:45.376759 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 18:11:45.380072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6148 18:11:45.386464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6149 18:11:45.393339 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6150 18:11:45.396595 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6151 18:11:45.399926 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6152 18:11:45.402873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6153 18:11:45.406183 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6154 18:11:45.413252 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 18:11:45.416331 ===================================
6156 18:11:45.419984 LPDDR4 DRAM CONFIGURATION
6157 18:11:45.423066 ===================================
6158 18:11:45.423153 EX_ROW_EN[0] = 0x0
6159 18:11:45.426617 EX_ROW_EN[1] = 0x0
6160 18:11:45.426726 LP4Y_EN = 0x0
6161 18:11:45.429720 WORK_FSP = 0x0
6162 18:11:45.429802 WL = 0x2
6163 18:11:45.433062 RL = 0x2
6164 18:11:45.433144 BL = 0x2
6165 18:11:45.436504 RPST = 0x0
6166 18:11:45.436652 RD_PRE = 0x0
6167 18:11:45.439568 WR_PRE = 0x1
6168 18:11:45.439651 WR_PST = 0x0
6169 18:11:45.443190 DBI_WR = 0x0
6170 18:11:45.443273 DBI_RD = 0x0
6171 18:11:45.446578 OTF = 0x1
6172 18:11:45.449537 ===================================
6173 18:11:45.453112 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6174 18:11:45.456058 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6175 18:11:45.462726 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 18:11:45.466392 ===================================
6177 18:11:45.466493 LPDDR4 DRAM CONFIGURATION
6178 18:11:45.469902 ===================================
6179 18:11:45.472727 EX_ROW_EN[0] = 0x10
6180 18:11:45.476114 EX_ROW_EN[1] = 0x0
6181 18:11:45.476201 LP4Y_EN = 0x0
6182 18:11:45.479461 WORK_FSP = 0x0
6183 18:11:45.479585 WL = 0x2
6184 18:11:45.482972 RL = 0x2
6185 18:11:45.483066 BL = 0x2
6186 18:11:45.486291 RPST = 0x0
6187 18:11:45.486376 RD_PRE = 0x0
6188 18:11:45.489674 WR_PRE = 0x1
6189 18:11:45.489776 WR_PST = 0x0
6190 18:11:45.492958 DBI_WR = 0x0
6191 18:11:45.493045 DBI_RD = 0x0
6192 18:11:45.495965 OTF = 0x1
6193 18:11:45.499476 ===================================
6194 18:11:45.506251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6195 18:11:45.509483 nWR fixed to 30
6196 18:11:45.512929 [ModeRegInit_LP4] CH0 RK0
6197 18:11:45.513017 [ModeRegInit_LP4] CH0 RK1
6198 18:11:45.515951 [ModeRegInit_LP4] CH1 RK0
6199 18:11:45.519509 [ModeRegInit_LP4] CH1 RK1
6200 18:11:45.519595 match AC timing 19
6201 18:11:45.526186 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6202 18:11:45.529685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6203 18:11:45.532746 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6204 18:11:45.539340 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6205 18:11:45.542905 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6206 18:11:45.543001 ==
6207 18:11:45.545969 Dram Type= 6, Freq= 0, CH_0, rank 0
6208 18:11:45.549510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 18:11:45.549596 ==
6210 18:11:45.555852 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 18:11:45.562952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6212 18:11:45.565957 [CA 0] Center 36 (8~64) winsize 57
6213 18:11:45.566057 [CA 1] Center 36 (8~64) winsize 57
6214 18:11:45.569127 [CA 2] Center 36 (8~64) winsize 57
6215 18:11:45.572500 [CA 3] Center 36 (8~64) winsize 57
6216 18:11:45.575772 [CA 4] Center 36 (8~64) winsize 57
6217 18:11:45.579176 [CA 5] Center 36 (8~64) winsize 57
6218 18:11:45.579270
6219 18:11:45.582637 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6220 18:11:45.582723
6221 18:11:45.589125 [CATrainingPosCal] consider 1 rank data
6222 18:11:45.589218 u2DelayCellTimex100 = 270/100 ps
6223 18:11:45.595639 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 18:11:45.599074 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 18:11:45.602679 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 18:11:45.605884 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 18:11:45.608756 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 18:11:45.612128 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 18:11:45.612220
6230 18:11:45.615619 CA PerBit enable=1, Macro0, CA PI delay=36
6231 18:11:45.615709
6232 18:11:45.618612 [CBTSetCACLKResult] CA Dly = 36
6233 18:11:45.622237 CS Dly: 1 (0~32)
6234 18:11:45.622327 ==
6235 18:11:45.625314 Dram Type= 6, Freq= 0, CH_0, rank 1
6236 18:11:45.628683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 18:11:45.628773 ==
6238 18:11:45.635495 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 18:11:45.638966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6240 18:11:45.641869 [CA 0] Center 36 (8~64) winsize 57
6241 18:11:45.645329 [CA 1] Center 36 (8~64) winsize 57
6242 18:11:45.648708 [CA 2] Center 36 (8~64) winsize 57
6243 18:11:45.651766 [CA 3] Center 36 (8~64) winsize 57
6244 18:11:45.655178 [CA 4] Center 36 (8~64) winsize 57
6245 18:11:45.658228 [CA 5] Center 36 (8~64) winsize 57
6246 18:11:45.658339
6247 18:11:45.661840 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6248 18:11:45.661935
6249 18:11:45.664934 [CATrainingPosCal] consider 2 rank data
6250 18:11:45.668463 u2DelayCellTimex100 = 270/100 ps
6251 18:11:45.671421 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 18:11:45.675013 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 18:11:45.681701 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 18:11:45.685038 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 18:11:45.687975 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 18:11:45.691386 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 18:11:45.691499
6258 18:11:45.694742 CA PerBit enable=1, Macro0, CA PI delay=36
6259 18:11:45.694872
6260 18:11:45.698245 [CBTSetCACLKResult] CA Dly = 36
6261 18:11:45.698335 CS Dly: 1 (0~32)
6262 18:11:45.698401
6263 18:11:45.701529 ----->DramcWriteLeveling(PI) begin...
6264 18:11:45.704500 ==
6265 18:11:45.707963 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 18:11:45.711310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 18:11:45.711407 ==
6268 18:11:45.714819 Write leveling (Byte 0): 40 => 8
6269 18:11:45.717623 Write leveling (Byte 1): 32 => 0
6270 18:11:45.721094 DramcWriteLeveling(PI) end<-----
6271 18:11:45.721179
6272 18:11:45.721245 ==
6273 18:11:45.724677 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 18:11:45.727643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 18:11:45.727727 ==
6276 18:11:45.731195 [Gating] SW mode calibration
6277 18:11:45.737698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6278 18:11:45.744331 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6279 18:11:45.747898 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 18:11:45.750955 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 18:11:45.757765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 18:11:45.761167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 18:11:45.764222 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 18:11:45.767700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 18:11:45.774281 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 18:11:45.777369 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 18:11:45.780797 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 18:11:45.784295 Total UI for P1: 0, mck2ui 16
6289 18:11:45.787721 best dqsien dly found for B0: ( 0, 14, 24)
6290 18:11:45.791081 Total UI for P1: 0, mck2ui 16
6291 18:11:45.794091 best dqsien dly found for B1: ( 0, 14, 24)
6292 18:11:45.797537 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6293 18:11:45.804234 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6294 18:11:45.804346
6295 18:11:45.807572 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 18:11:45.811007 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 18:11:45.814317 [Gating] SW calibration Done
6298 18:11:45.814405 ==
6299 18:11:45.817334 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 18:11:45.820776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 18:11:45.820874 ==
6302 18:11:45.820938 RX Vref Scan: 0
6303 18:11:45.824047
6304 18:11:45.824131 RX Vref 0 -> 0, step: 1
6305 18:11:45.824195
6306 18:11:45.827186 RX Delay -410 -> 252, step: 16
6307 18:11:45.830791 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6308 18:11:45.837440 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6309 18:11:45.840420 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6310 18:11:45.843979 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6311 18:11:45.847343 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6312 18:11:45.853986 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6313 18:11:45.857507 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6314 18:11:45.860627 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6315 18:11:45.864021 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6316 18:11:45.870608 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6317 18:11:45.874171 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6318 18:11:45.877206 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6319 18:11:45.880266 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6320 18:11:45.886934 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6321 18:11:45.890327 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6322 18:11:45.893633 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6323 18:11:45.893717 ==
6324 18:11:45.896954 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 18:11:45.903749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 18:11:45.903837 ==
6327 18:11:45.903901 DQS Delay:
6328 18:11:45.906779 DQS0 = 27, DQS1 = 43
6329 18:11:45.906861 DQM Delay:
6330 18:11:45.906925 DQM0 = 12, DQM1 = 13
6331 18:11:45.910439 DQ Delay:
6332 18:11:45.913582 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6333 18:11:45.913668 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6334 18:11:45.916935 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6335 18:11:45.920185 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6336 18:11:45.920268
6337 18:11:45.923720
6338 18:11:45.923802 ==
6339 18:11:45.926990 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 18:11:45.930567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 18:11:45.930649 ==
6342 18:11:45.930713
6343 18:11:45.930772
6344 18:11:45.933578 TX Vref Scan disable
6345 18:11:45.933659 == TX Byte 0 ==
6346 18:11:45.937044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 18:11:45.943628 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 18:11:45.943721 == TX Byte 1 ==
6349 18:11:45.947166 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6350 18:11:45.953834 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6351 18:11:45.953917 ==
6352 18:11:45.956755 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 18:11:45.960416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 18:11:45.960500 ==
6355 18:11:45.960589
6356 18:11:45.960665
6357 18:11:45.963319 TX Vref Scan disable
6358 18:11:45.963400 == TX Byte 0 ==
6359 18:11:45.966686 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 18:11:45.973579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 18:11:45.973667 == TX Byte 1 ==
6362 18:11:45.976533 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 18:11:45.983203 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 18:11:45.983294
6365 18:11:45.983359 [DATLAT]
6366 18:11:45.986763 Freq=400, CH0 RK0
6367 18:11:45.986846
6368 18:11:45.986910 DATLAT Default: 0xf
6369 18:11:45.989731 0, 0xFFFF, sum = 0
6370 18:11:45.989814 1, 0xFFFF, sum = 0
6371 18:11:45.993420 2, 0xFFFF, sum = 0
6372 18:11:45.993507 3, 0xFFFF, sum = 0
6373 18:11:45.996331 4, 0xFFFF, sum = 0
6374 18:11:45.996441 5, 0xFFFF, sum = 0
6375 18:11:45.999652 6, 0xFFFF, sum = 0
6376 18:11:45.999759 7, 0xFFFF, sum = 0
6377 18:11:46.003089 8, 0xFFFF, sum = 0
6378 18:11:46.003171 9, 0xFFFF, sum = 0
6379 18:11:46.006447 10, 0xFFFF, sum = 0
6380 18:11:46.006530 11, 0xFFFF, sum = 0
6381 18:11:46.009531 12, 0xFFFF, sum = 0
6382 18:11:46.009614 13, 0x0, sum = 1
6383 18:11:46.012850 14, 0x0, sum = 2
6384 18:11:46.012932 15, 0x0, sum = 3
6385 18:11:46.016433 16, 0x0, sum = 4
6386 18:11:46.016543 best_step = 14
6387 18:11:46.016644
6388 18:11:46.016732 ==
6389 18:11:46.019524 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 18:11:46.026287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 18:11:46.026381 ==
6392 18:11:46.026445 RX Vref Scan: 1
6393 18:11:46.026505
6394 18:11:46.029588 RX Vref 0 -> 0, step: 1
6395 18:11:46.029669
6396 18:11:46.032926 RX Delay -327 -> 252, step: 8
6397 18:11:46.033009
6398 18:11:46.036090 Set Vref, RX VrefLevel [Byte0]: 60
6399 18:11:46.039527 [Byte1]: 49
6400 18:11:46.042574
6401 18:11:46.042662 Final RX Vref Byte 0 = 60 to rank0
6402 18:11:46.046010 Final RX Vref Byte 1 = 49 to rank0
6403 18:11:46.049444 Final RX Vref Byte 0 = 60 to rank1
6404 18:11:46.052884 Final RX Vref Byte 1 = 49 to rank1==
6405 18:11:46.056262 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 18:11:46.062948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 18:11:46.063040 ==
6408 18:11:46.063105 DQS Delay:
6409 18:11:46.063166 DQS0 = 28, DQS1 = 48
6410 18:11:46.066411 DQM Delay:
6411 18:11:46.066493 DQM0 = 10, DQM1 = 14
6412 18:11:46.069257 DQ Delay:
6413 18:11:46.072654 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6414 18:11:46.072738 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6415 18:11:46.075978 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6416 18:11:46.079543 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6417 18:11:46.079634
6418 18:11:46.079700
6419 18:11:46.089512 [DQSOSCAuto] RK0, (LSB)MR18= 0xada4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6420 18:11:46.092495 CH0 RK0: MR19=C0C, MR18=ADA4
6421 18:11:46.099153 CH0_RK0: MR19=0xC0C, MR18=0xADA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6422 18:11:46.099267 ==
6423 18:11:46.102546 Dram Type= 6, Freq= 0, CH_0, rank 1
6424 18:11:46.105881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 18:11:46.105982 ==
6426 18:11:46.109235 [Gating] SW mode calibration
6427 18:11:46.115747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6428 18:11:46.119158 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6429 18:11:46.125615 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 18:11:46.129444 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 18:11:46.132310 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 18:11:46.139183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 18:11:46.142797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 18:11:46.145820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 18:11:46.152322 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 18:11:46.155823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 18:11:46.159385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 18:11:46.162592 Total UI for P1: 0, mck2ui 16
6439 18:11:46.165617 best dqsien dly found for B0: ( 0, 14, 24)
6440 18:11:46.169220 Total UI for P1: 0, mck2ui 16
6441 18:11:46.172171 best dqsien dly found for B1: ( 0, 14, 24)
6442 18:11:46.175514 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6443 18:11:46.178854 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6444 18:11:46.178949
6445 18:11:46.185468 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 18:11:46.188909 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 18:11:46.192221 [Gating] SW calibration Done
6448 18:11:46.192312 ==
6449 18:11:46.195753 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 18:11:46.198728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 18:11:46.198812 ==
6452 18:11:46.198878 RX Vref Scan: 0
6453 18:11:46.198939
6454 18:11:46.202160 RX Vref 0 -> 0, step: 1
6455 18:11:46.202244
6456 18:11:46.205682 RX Delay -410 -> 252, step: 16
6457 18:11:46.208911 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6458 18:11:46.215780 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6459 18:11:46.218951 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6460 18:11:46.222365 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6461 18:11:46.225831 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6462 18:11:46.232231 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6463 18:11:46.235579 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6464 18:11:46.238948 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6465 18:11:46.241916 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6466 18:11:46.248500 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6467 18:11:46.252167 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6468 18:11:46.255618 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6469 18:11:46.258671 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6470 18:11:46.265361 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6471 18:11:46.268970 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6472 18:11:46.271972 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6473 18:11:46.272063 ==
6474 18:11:46.275514 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 18:11:46.278384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 18:11:46.281784 ==
6477 18:11:46.281892 DQS Delay:
6478 18:11:46.281959 DQS0 = 27, DQS1 = 43
6479 18:11:46.285242 DQM Delay:
6480 18:11:46.285335 DQM0 = 9, DQM1 = 15
6481 18:11:46.288726 DQ Delay:
6482 18:11:46.288824 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6483 18:11:46.292154 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6484 18:11:46.295182 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6485 18:11:46.298640 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6486 18:11:46.298739
6487 18:11:46.298805
6488 18:11:46.298866 ==
6489 18:11:46.301724 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 18:11:46.308719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 18:11:46.308821 ==
6492 18:11:46.308888
6493 18:11:46.308949
6494 18:11:46.309007 TX Vref Scan disable
6495 18:11:46.312236 == TX Byte 0 ==
6496 18:11:46.315163 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6497 18:11:46.318645 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6498 18:11:46.321945 == TX Byte 1 ==
6499 18:11:46.325300 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6500 18:11:46.328657 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6501 18:11:46.328743 ==
6502 18:11:46.331623 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 18:11:46.338673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 18:11:46.338769 ==
6505 18:11:46.338836
6506 18:11:46.338898
6507 18:11:46.341557 TX Vref Scan disable
6508 18:11:46.341641 == TX Byte 0 ==
6509 18:11:46.344907 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6510 18:11:46.348429 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6511 18:11:46.351577 == TX Byte 1 ==
6512 18:11:46.354996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6513 18:11:46.358064 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6514 18:11:46.361379
6515 18:11:46.361464 [DATLAT]
6516 18:11:46.361531 Freq=400, CH0 RK1
6517 18:11:46.361593
6518 18:11:46.364969 DATLAT Default: 0xe
6519 18:11:46.365053 0, 0xFFFF, sum = 0
6520 18:11:46.368514 1, 0xFFFF, sum = 0
6521 18:11:46.368644 2, 0xFFFF, sum = 0
6522 18:11:46.371500 3, 0xFFFF, sum = 0
6523 18:11:46.371586 4, 0xFFFF, sum = 0
6524 18:11:46.375107 5, 0xFFFF, sum = 0
6525 18:11:46.375191 6, 0xFFFF, sum = 0
6526 18:11:46.378058 7, 0xFFFF, sum = 0
6527 18:11:46.381633 8, 0xFFFF, sum = 0
6528 18:11:46.381730 9, 0xFFFF, sum = 0
6529 18:11:46.385042 10, 0xFFFF, sum = 0
6530 18:11:46.385126 11, 0xFFFF, sum = 0
6531 18:11:46.387946 12, 0xFFFF, sum = 0
6532 18:11:46.388031 13, 0x0, sum = 1
6533 18:11:46.391158 14, 0x0, sum = 2
6534 18:11:46.391277 15, 0x0, sum = 3
6535 18:11:46.394776 16, 0x0, sum = 4
6536 18:11:46.394871 best_step = 14
6537 18:11:46.394938
6538 18:11:46.394998 ==
6539 18:11:46.398088 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 18:11:46.401197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 18:11:46.401282 ==
6542 18:11:46.404492 RX Vref Scan: 0
6543 18:11:46.404615
6544 18:11:46.408156 RX Vref 0 -> 0, step: 1
6545 18:11:46.408240
6546 18:11:46.408307 RX Delay -327 -> 252, step: 8
6547 18:11:46.416923 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6548 18:11:46.419743 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6549 18:11:46.423675 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6550 18:11:46.426630 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6551 18:11:46.433498 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6552 18:11:46.436640 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6553 18:11:46.439958 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6554 18:11:46.443460 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6555 18:11:46.450134 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6556 18:11:46.453158 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6557 18:11:46.456567 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6558 18:11:46.460128 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6559 18:11:46.466705 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6560 18:11:46.469741 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6561 18:11:46.473185 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6562 18:11:46.479728 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6563 18:11:46.479857 ==
6564 18:11:46.483215 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 18:11:46.486235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 18:11:46.486345 ==
6567 18:11:46.486441 DQS Delay:
6568 18:11:46.489709 DQS0 = 28, DQS1 = 44
6569 18:11:46.489819 DQM Delay:
6570 18:11:46.493039 DQM0 = 9, DQM1 = 15
6571 18:11:46.493152 DQ Delay:
6572 18:11:46.496414 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6573 18:11:46.499956 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6574 18:11:46.503018 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6575 18:11:46.506411 DQ12 =20, DQ13 =24, DQ14 =28, DQ15 =20
6576 18:11:46.506524
6577 18:11:46.506621
6578 18:11:46.513386 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6579 18:11:46.516477 CH0 RK1: MR19=C0C, MR18=BA6C
6580 18:11:46.522866 CH0_RK1: MR19=0xC0C, MR18=0xBA6C, DQSOSC=386, MR23=63, INC=396, DEC=264
6581 18:11:46.526209 [RxdqsGatingPostProcess] freq 400
6582 18:11:46.533065 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6583 18:11:46.533189 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 18:11:46.536463 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 18:11:46.539794 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 18:11:46.542746 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 18:11:46.546049 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 18:11:46.549550 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 18:11:46.553097 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 18:11:46.556008 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 18:11:46.559473 Pre-setting of DQS Precalculation
6592 18:11:46.562935 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6593 18:11:46.566118 ==
6594 18:11:46.569548 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 18:11:46.573049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 18:11:46.573160 ==
6597 18:11:46.576041 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 18:11:46.582885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6599 18:11:46.585937 [CA 0] Center 36 (8~64) winsize 57
6600 18:11:46.589546 [CA 1] Center 36 (8~64) winsize 57
6601 18:11:46.592523 [CA 2] Center 36 (8~64) winsize 57
6602 18:11:46.596059 [CA 3] Center 36 (8~64) winsize 57
6603 18:11:46.599447 [CA 4] Center 36 (8~64) winsize 57
6604 18:11:46.602808 [CA 5] Center 36 (8~64) winsize 57
6605 18:11:46.602925
6606 18:11:46.606287 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6607 18:11:46.606396
6608 18:11:46.609450 [CATrainingPosCal] consider 1 rank data
6609 18:11:46.612476 u2DelayCellTimex100 = 270/100 ps
6610 18:11:46.615853 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 18:11:46.619560 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 18:11:46.622669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 18:11:46.625940 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 18:11:46.632813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 18:11:46.635988 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 18:11:46.636104
6617 18:11:46.639482 CA PerBit enable=1, Macro0, CA PI delay=36
6618 18:11:46.639594
6619 18:11:46.642760 [CBTSetCACLKResult] CA Dly = 36
6620 18:11:46.642868 CS Dly: 1 (0~32)
6621 18:11:46.642963 ==
6622 18:11:46.646174 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 18:11:46.649642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 18:11:46.652535 ==
6625 18:11:46.656373 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 18:11:46.662730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6627 18:11:46.666471 [CA 0] Center 36 (8~64) winsize 57
6628 18:11:46.669360 [CA 1] Center 36 (8~64) winsize 57
6629 18:11:46.672920 [CA 2] Center 36 (8~64) winsize 57
6630 18:11:46.676016 [CA 3] Center 36 (8~64) winsize 57
6631 18:11:46.679583 [CA 4] Center 36 (8~64) winsize 57
6632 18:11:46.682753 [CA 5] Center 36 (8~64) winsize 57
6633 18:11:46.682865
6634 18:11:46.685799 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6635 18:11:46.685907
6636 18:11:46.689268 [CATrainingPosCal] consider 2 rank data
6637 18:11:46.692892 u2DelayCellTimex100 = 270/100 ps
6638 18:11:46.695827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 18:11:46.699258 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 18:11:46.702753 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 18:11:46.705892 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 18:11:46.709343 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 18:11:46.712786 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 18:11:46.712896
6645 18:11:46.715744 CA PerBit enable=1, Macro0, CA PI delay=36
6646 18:11:46.715852
6647 18:11:46.719249 [CBTSetCACLKResult] CA Dly = 36
6648 18:11:46.722822 CS Dly: 1 (0~32)
6649 18:11:46.722934
6650 18:11:46.725736 ----->DramcWriteLeveling(PI) begin...
6651 18:11:46.725846 ==
6652 18:11:46.729222 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 18:11:46.732876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 18:11:46.732995 ==
6655 18:11:46.736225 Write leveling (Byte 0): 40 => 8
6656 18:11:46.739213 Write leveling (Byte 1): 32 => 0
6657 18:11:46.742603 DramcWriteLeveling(PI) end<-----
6658 18:11:46.742713
6659 18:11:46.742808 ==
6660 18:11:46.746050 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 18:11:46.749484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 18:11:46.749591 ==
6663 18:11:46.752817 [Gating] SW mode calibration
6664 18:11:46.759018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6665 18:11:46.765700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6666 18:11:46.769191 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 18:11:46.775808 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 18:11:46.778823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 18:11:46.782518 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 18:11:46.785546 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 18:11:46.792112 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 18:11:46.795654 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 18:11:46.799216 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 18:11:46.805860 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 18:11:46.809266 Total UI for P1: 0, mck2ui 16
6676 18:11:46.812286 best dqsien dly found for B0: ( 0, 14, 24)
6677 18:11:46.812374 Total UI for P1: 0, mck2ui 16
6678 18:11:46.819165 best dqsien dly found for B1: ( 0, 14, 24)
6679 18:11:46.822335 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6680 18:11:46.825919 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6681 18:11:46.826006
6682 18:11:46.828981 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 18:11:46.832323 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 18:11:46.835557 [Gating] SW calibration Done
6685 18:11:46.835644 ==
6686 18:11:46.838898 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 18:11:46.842375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 18:11:46.842462 ==
6689 18:11:46.845430 RX Vref Scan: 0
6690 18:11:46.845514
6691 18:11:46.848913 RX Vref 0 -> 0, step: 1
6692 18:11:46.849024
6693 18:11:46.849114 RX Delay -410 -> 252, step: 16
6694 18:11:46.855673 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6695 18:11:46.858590 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6696 18:11:46.862057 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6697 18:11:46.865567 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6698 18:11:46.871833 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6699 18:11:46.875255 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6700 18:11:46.878391 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6701 18:11:46.881859 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6702 18:11:46.888312 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6703 18:11:46.891828 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6704 18:11:46.894945 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6705 18:11:46.901953 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6706 18:11:46.905051 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6707 18:11:46.908461 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6708 18:11:46.911527 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6709 18:11:46.918340 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6710 18:11:46.918443 ==
6711 18:11:46.921796 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 18:11:46.924886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 18:11:46.924973 ==
6714 18:11:46.925040 DQS Delay:
6715 18:11:46.928236 DQS0 = 27, DQS1 = 43
6716 18:11:46.928320 DQM Delay:
6717 18:11:46.931763 DQM0 = 6, DQM1 = 16
6718 18:11:46.931850 DQ Delay:
6719 18:11:46.934744 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6720 18:11:46.938189 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6721 18:11:46.941648 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6722 18:11:46.944691 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6723 18:11:46.944779
6724 18:11:46.944876
6725 18:11:46.944962 ==
6726 18:11:46.948180 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 18:11:46.951686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 18:11:46.951774 ==
6729 18:11:46.951841
6730 18:11:46.951901
6731 18:11:46.954831 TX Vref Scan disable
6732 18:11:46.957826 == TX Byte 0 ==
6733 18:11:46.961148 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 18:11:46.964679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 18:11:46.964771 == TX Byte 1 ==
6736 18:11:46.971293 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6737 18:11:46.974851 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6738 18:11:46.974948 ==
6739 18:11:46.977855 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 18:11:46.981360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 18:11:46.981447 ==
6742 18:11:46.981513
6743 18:11:46.984360
6744 18:11:46.984469 TX Vref Scan disable
6745 18:11:46.987915 == TX Byte 0 ==
6746 18:11:46.990924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 18:11:46.994429 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 18:11:46.998156 == TX Byte 1 ==
6749 18:11:47.001105 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6750 18:11:47.004521 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6751 18:11:47.004650
6752 18:11:47.004717 [DATLAT]
6753 18:11:47.007652 Freq=400, CH1 RK0
6754 18:11:47.007747
6755 18:11:47.011162 DATLAT Default: 0xf
6756 18:11:47.011247 0, 0xFFFF, sum = 0
6757 18:11:47.014365 1, 0xFFFF, sum = 0
6758 18:11:47.014452 2, 0xFFFF, sum = 0
6759 18:11:47.017741 3, 0xFFFF, sum = 0
6760 18:11:47.017827 4, 0xFFFF, sum = 0
6761 18:11:47.021145 5, 0xFFFF, sum = 0
6762 18:11:47.021232 6, 0xFFFF, sum = 0
6763 18:11:47.024166 7, 0xFFFF, sum = 0
6764 18:11:47.024277 8, 0xFFFF, sum = 0
6765 18:11:47.027671 9, 0xFFFF, sum = 0
6766 18:11:47.027756 10, 0xFFFF, sum = 0
6767 18:11:47.031177 11, 0xFFFF, sum = 0
6768 18:11:47.031263 12, 0xFFFF, sum = 0
6769 18:11:47.034289 13, 0x0, sum = 1
6770 18:11:47.034374 14, 0x0, sum = 2
6771 18:11:47.037755 15, 0x0, sum = 3
6772 18:11:47.037842 16, 0x0, sum = 4
6773 18:11:47.040847 best_step = 14
6774 18:11:47.040954
6775 18:11:47.041021 ==
6776 18:11:47.044316 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 18:11:47.047420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 18:11:47.047505 ==
6779 18:11:47.050847 RX Vref Scan: 1
6780 18:11:47.050931
6781 18:11:47.050997 RX Vref 0 -> 0, step: 1
6782 18:11:47.051057
6783 18:11:47.054250 RX Delay -327 -> 252, step: 8
6784 18:11:47.054335
6785 18:11:47.057761 Set Vref, RX VrefLevel [Byte0]: 52
6786 18:11:47.060597 [Byte1]: 52
6787 18:11:47.065067
6788 18:11:47.065169 Final RX Vref Byte 0 = 52 to rank0
6789 18:11:47.068703 Final RX Vref Byte 1 = 52 to rank0
6790 18:11:47.071707 Final RX Vref Byte 0 = 52 to rank1
6791 18:11:47.075086 Final RX Vref Byte 1 = 52 to rank1==
6792 18:11:47.078273 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 18:11:47.085252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 18:11:47.085362 ==
6795 18:11:47.085431 DQS Delay:
6796 18:11:47.085493 DQS0 = 32, DQS1 = 40
6797 18:11:47.088969 DQM Delay:
6798 18:11:47.089054 DQM0 = 11, DQM1 = 12
6799 18:11:47.091806 DQ Delay:
6800 18:11:47.095121 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6801 18:11:47.095217 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6802 18:11:47.098609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6803 18:11:47.102107 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6804 18:11:47.102197
6805 18:11:47.102264
6806 18:11:47.111589 [DQSOSCAuto] RK0, (LSB)MR18= 0x95d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6807 18:11:47.115138 CH1 RK0: MR19=C0C, MR18=95D0
6808 18:11:47.121543 CH1_RK0: MR19=0xC0C, MR18=0x95D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6809 18:11:47.121653 ==
6810 18:11:47.124960 Dram Type= 6, Freq= 0, CH_1, rank 1
6811 18:11:47.128460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 18:11:47.128611 ==
6813 18:11:47.131726 [Gating] SW mode calibration
6814 18:11:47.138610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6815 18:11:47.141673 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6816 18:11:47.148322 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 18:11:47.151508 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 18:11:47.155343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 18:11:47.161810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 18:11:47.164987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 18:11:47.168253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 18:11:47.175089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 18:11:47.178218 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 18:11:47.181471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 18:11:47.185102 Total UI for P1: 0, mck2ui 16
6826 18:11:47.188114 best dqsien dly found for B0: ( 0, 14, 24)
6827 18:11:47.191804 Total UI for P1: 0, mck2ui 16
6828 18:11:47.194887 best dqsien dly found for B1: ( 0, 14, 24)
6829 18:11:47.198217 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6830 18:11:47.201270 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6831 18:11:47.201354
6832 18:11:47.208394 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 18:11:47.211406 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 18:11:47.214843 [Gating] SW calibration Done
6835 18:11:47.214932 ==
6836 18:11:47.218454 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 18:11:47.221282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 18:11:47.221392 ==
6839 18:11:47.221485 RX Vref Scan: 0
6840 18:11:47.221574
6841 18:11:47.224718 RX Vref 0 -> 0, step: 1
6842 18:11:47.224796
6843 18:11:47.227973 RX Delay -410 -> 252, step: 16
6844 18:11:47.231540 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6845 18:11:47.238162 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6846 18:11:47.241637 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6847 18:11:47.244764 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6848 18:11:47.248194 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6849 18:11:47.251249 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6850 18:11:47.257923 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6851 18:11:47.261301 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6852 18:11:47.264795 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6853 18:11:47.268272 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6854 18:11:47.274723 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6855 18:11:47.278014 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6856 18:11:47.281268 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6857 18:11:47.288095 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6858 18:11:47.291557 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6859 18:11:47.294625 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6860 18:11:47.294726 ==
6861 18:11:47.298044 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 18:11:47.301112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 18:11:47.304694 ==
6864 18:11:47.304812 DQS Delay:
6865 18:11:47.304906 DQS0 = 35, DQS1 = 35
6866 18:11:47.307715 DQM Delay:
6867 18:11:47.307822 DQM0 = 16, DQM1 = 11
6868 18:11:47.311193 DQ Delay:
6869 18:11:47.311334 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6870 18:11:47.314774 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6871 18:11:47.318151 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6872 18:11:47.321223 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6873 18:11:47.321333
6874 18:11:47.321427
6875 18:11:47.321516 ==
6876 18:11:47.324741 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 18:11:47.331236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 18:11:47.331371 ==
6879 18:11:47.331438
6880 18:11:47.331498
6881 18:11:47.334615 TX Vref Scan disable
6882 18:11:47.334694 == TX Byte 0 ==
6883 18:11:47.337683 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6884 18:11:47.341086 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6885 18:11:47.344738 == TX Byte 1 ==
6886 18:11:47.347578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6887 18:11:47.350801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6888 18:11:47.354302 ==
6889 18:11:47.357834 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 18:11:47.360773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 18:11:47.360859 ==
6892 18:11:47.360929
6893 18:11:47.360991
6894 18:11:47.364171 TX Vref Scan disable
6895 18:11:47.364255 == TX Byte 0 ==
6896 18:11:47.367791 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6897 18:11:47.374659 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6898 18:11:47.374749 == TX Byte 1 ==
6899 18:11:47.377514 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6900 18:11:47.380740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6901 18:11:47.384126
6902 18:11:47.384240 [DATLAT]
6903 18:11:47.384312 Freq=400, CH1 RK1
6904 18:11:47.384376
6905 18:11:47.387510 DATLAT Default: 0xe
6906 18:11:47.387593 0, 0xFFFF, sum = 0
6907 18:11:47.390828 1, 0xFFFF, sum = 0
6908 18:11:47.390912 2, 0xFFFF, sum = 0
6909 18:11:47.394363 3, 0xFFFF, sum = 0
6910 18:11:47.394478 4, 0xFFFF, sum = 0
6911 18:11:47.397520 5, 0xFFFF, sum = 0
6912 18:11:47.400933 6, 0xFFFF, sum = 0
6913 18:11:47.401022 7, 0xFFFF, sum = 0
6914 18:11:47.404544 8, 0xFFFF, sum = 0
6915 18:11:47.404669 9, 0xFFFF, sum = 0
6916 18:11:47.407544 10, 0xFFFF, sum = 0
6917 18:11:47.407646 11, 0xFFFF, sum = 0
6918 18:11:47.411333 12, 0xFFFF, sum = 0
6919 18:11:47.411471 13, 0x0, sum = 1
6920 18:11:47.414197 14, 0x0, sum = 2
6921 18:11:47.414278 15, 0x0, sum = 3
6922 18:11:47.417662 16, 0x0, sum = 4
6923 18:11:47.417753 best_step = 14
6924 18:11:47.417816
6925 18:11:47.417875 ==
6926 18:11:47.420726 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 18:11:47.424226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 18:11:47.424335 ==
6929 18:11:47.427271 RX Vref Scan: 0
6930 18:11:47.427345
6931 18:11:47.430845 RX Vref 0 -> 0, step: 1
6932 18:11:47.430948
6933 18:11:47.431035 RX Delay -311 -> 252, step: 8
6934 18:11:47.439632 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6935 18:11:47.442694 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6936 18:11:47.446204 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6937 18:11:47.449325 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6938 18:11:47.455860 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6939 18:11:47.459447 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6940 18:11:47.462497 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6941 18:11:47.466080 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6942 18:11:47.472483 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6943 18:11:47.475767 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6944 18:11:47.479128 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6945 18:11:47.485457 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6946 18:11:47.488856 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6947 18:11:47.492535 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6948 18:11:47.495572 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6949 18:11:47.502170 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6950 18:11:47.502260 ==
6951 18:11:47.505779 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 18:11:47.509161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 18:11:47.509246 ==
6954 18:11:47.509312 DQS Delay:
6955 18:11:47.512228 DQS0 = 32, DQS1 = 36
6956 18:11:47.512310 DQM Delay:
6957 18:11:47.515781 DQM0 = 12, DQM1 = 11
6958 18:11:47.515864 DQ Delay:
6959 18:11:47.519226 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6960 18:11:47.522704 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6961 18:11:47.525738 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6962 18:11:47.529137 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6963 18:11:47.529220
6964 18:11:47.529285
6965 18:11:47.535637 [DQSOSCAuto] RK1, (LSB)MR18= 0xa650, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6966 18:11:47.539194 CH1 RK1: MR19=C0C, MR18=A650
6967 18:11:47.545523 CH1_RK1: MR19=0xC0C, MR18=0xA650, DQSOSC=389, MR23=63, INC=390, DEC=260
6968 18:11:47.548970 [RxdqsGatingPostProcess] freq 400
6969 18:11:47.555556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6970 18:11:47.555643 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 18:11:47.558937 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 18:11:47.562003 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 18:11:47.565665 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 18:11:47.568731 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 18:11:47.572113 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 18:11:47.575772 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 18:11:47.578761 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 18:11:47.582181 Pre-setting of DQS Precalculation
6979 18:11:47.588803 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6980 18:11:47.595333 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6981 18:11:47.602141 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6982 18:11:47.602250
6983 18:11:47.602318
6984 18:11:47.605643 [Calibration Summary] 800 Mbps
6985 18:11:47.605726 CH 0, Rank 0
6986 18:11:47.608528 SW Impedance : PASS
6987 18:11:47.608650 DUTY Scan : NO K
6988 18:11:47.612332 ZQ Calibration : PASS
6989 18:11:47.615257 Jitter Meter : NO K
6990 18:11:47.615339 CBT Training : PASS
6991 18:11:47.618407 Write leveling : PASS
6992 18:11:47.622195 RX DQS gating : PASS
6993 18:11:47.622279 RX DQ/DQS(RDDQC) : PASS
6994 18:11:47.625229 TX DQ/DQS : PASS
6995 18:11:47.628787 RX DATLAT : PASS
6996 18:11:47.628869 RX DQ/DQS(Engine): PASS
6997 18:11:47.631871 TX OE : NO K
6998 18:11:47.631955 All Pass.
6999 18:11:47.632020
7000 18:11:47.635201 CH 0, Rank 1
7001 18:11:47.635284 SW Impedance : PASS
7002 18:11:47.638553 DUTY Scan : NO K
7003 18:11:47.642153 ZQ Calibration : PASS
7004 18:11:47.642238 Jitter Meter : NO K
7005 18:11:47.645475 CBT Training : PASS
7006 18:11:47.648978 Write leveling : NO K
7007 18:11:47.649061 RX DQS gating : PASS
7008 18:11:47.651999 RX DQ/DQS(RDDQC) : PASS
7009 18:11:47.652081 TX DQ/DQS : PASS
7010 18:11:47.655503 RX DATLAT : PASS
7011 18:11:47.658595 RX DQ/DQS(Engine): PASS
7012 18:11:47.658679 TX OE : NO K
7013 18:11:47.662100 All Pass.
7014 18:11:47.662192
7015 18:11:47.662258 CH 1, Rank 0
7016 18:11:47.665087 SW Impedance : PASS
7017 18:11:47.665172 DUTY Scan : NO K
7018 18:11:47.668817 ZQ Calibration : PASS
7019 18:11:47.671854 Jitter Meter : NO K
7020 18:11:47.671937 CBT Training : PASS
7021 18:11:47.675438 Write leveling : PASS
7022 18:11:47.678381 RX DQS gating : PASS
7023 18:11:47.678465 RX DQ/DQS(RDDQC) : PASS
7024 18:11:47.681864 TX DQ/DQS : PASS
7025 18:11:47.685344 RX DATLAT : PASS
7026 18:11:47.685428 RX DQ/DQS(Engine): PASS
7027 18:11:47.688761 TX OE : NO K
7028 18:11:47.688846 All Pass.
7029 18:11:47.688911
7030 18:11:47.692010 CH 1, Rank 1
7031 18:11:47.692093 SW Impedance : PASS
7032 18:11:47.695047 DUTY Scan : NO K
7033 18:11:47.698464 ZQ Calibration : PASS
7034 18:11:47.698550 Jitter Meter : NO K
7035 18:11:47.701557 CBT Training : PASS
7036 18:11:47.705080 Write leveling : NO K
7037 18:11:47.705166 RX DQS gating : PASS
7038 18:11:47.708731 RX DQ/DQS(RDDQC) : PASS
7039 18:11:47.708814 TX DQ/DQS : PASS
7040 18:11:47.711751 RX DATLAT : PASS
7041 18:11:47.715151 RX DQ/DQS(Engine): PASS
7042 18:11:47.715235 TX OE : NO K
7043 18:11:47.718193 All Pass.
7044 18:11:47.718276
7045 18:11:47.718340 DramC Write-DBI off
7046 18:11:47.721931 PER_BANK_REFRESH: Hybrid Mode
7047 18:11:47.725079 TX_TRACKING: ON
7048 18:11:47.731754 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7049 18:11:47.735219 [FAST_K] Save calibration result to emmc
7050 18:11:47.738291 dramc_set_vcore_voltage set vcore to 725000
7051 18:11:47.741683 Read voltage for 1600, 0
7052 18:11:47.741770 Vio18 = 0
7053 18:11:47.745137 Vcore = 725000
7054 18:11:47.745220 Vdram = 0
7055 18:11:47.745301 Vddq = 0
7056 18:11:47.748119 Vmddr = 0
7057 18:11:47.751503 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7058 18:11:47.758480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7059 18:11:47.758580 MEM_TYPE=3, freq_sel=13
7060 18:11:47.761422 sv_algorithm_assistance_LP4_3733
7061 18:11:47.768397 ============ PULL DRAM RESETB DOWN ============
7062 18:11:47.771494 ========== PULL DRAM RESETB DOWN end =========
7063 18:11:47.774984 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7064 18:11:47.777959 ===================================
7065 18:11:47.781521 LPDDR4 DRAM CONFIGURATION
7066 18:11:47.785016 ===================================
7067 18:11:47.788076 EX_ROW_EN[0] = 0x0
7068 18:11:47.788166 EX_ROW_EN[1] = 0x0
7069 18:11:47.791657 LP4Y_EN = 0x0
7070 18:11:47.791745 WORK_FSP = 0x1
7071 18:11:47.794550 WL = 0x5
7072 18:11:47.794678 RL = 0x5
7073 18:11:47.798384 BL = 0x2
7074 18:11:47.798469 RPST = 0x0
7075 18:11:47.801599 RD_PRE = 0x0
7076 18:11:47.801692 WR_PRE = 0x1
7077 18:11:47.804935 WR_PST = 0x1
7078 18:11:47.805019 DBI_WR = 0x0
7079 18:11:47.808297 DBI_RD = 0x0
7080 18:11:47.808382 OTF = 0x1
7081 18:11:47.811353 ===================================
7082 18:11:47.814900 ===================================
7083 18:11:47.817963 ANA top config
7084 18:11:47.821552 ===================================
7085 18:11:47.824567 DLL_ASYNC_EN = 0
7086 18:11:47.824666 ALL_SLAVE_EN = 0
7087 18:11:47.828155 NEW_RANK_MODE = 1
7088 18:11:47.831324 DLL_IDLE_MODE = 1
7089 18:11:47.834768 LP45_APHY_COMB_EN = 1
7090 18:11:47.834851 TX_ODT_DIS = 0
7091 18:11:47.837759 NEW_8X_MODE = 1
7092 18:11:47.841182 ===================================
7093 18:11:47.844818 ===================================
7094 18:11:47.847693 data_rate = 3200
7095 18:11:47.851300 CKR = 1
7096 18:11:47.854594 DQ_P2S_RATIO = 8
7097 18:11:47.857840 ===================================
7098 18:11:47.860821 CA_P2S_RATIO = 8
7099 18:11:47.860906 DQ_CA_OPEN = 0
7100 18:11:47.864334 DQ_SEMI_OPEN = 0
7101 18:11:47.867726 CA_SEMI_OPEN = 0
7102 18:11:47.871319 CA_FULL_RATE = 0
7103 18:11:47.874438 DQ_CKDIV4_EN = 0
7104 18:11:47.877416 CA_CKDIV4_EN = 0
7105 18:11:47.877502 CA_PREDIV_EN = 0
7106 18:11:47.880950 PH8_DLY = 12
7107 18:11:47.884423 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7108 18:11:47.887375 DQ_AAMCK_DIV = 4
7109 18:11:47.890792 CA_AAMCK_DIV = 4
7110 18:11:47.894310 CA_ADMCK_DIV = 4
7111 18:11:47.894395 DQ_TRACK_CA_EN = 0
7112 18:11:47.897202 CA_PICK = 1600
7113 18:11:47.900468 CA_MCKIO = 1600
7114 18:11:47.903854 MCKIO_SEMI = 0
7115 18:11:47.907555 PLL_FREQ = 3068
7116 18:11:47.910942 DQ_UI_PI_RATIO = 32
7117 18:11:47.913821 CA_UI_PI_RATIO = 0
7118 18:11:47.917343 ===================================
7119 18:11:47.920372 ===================================
7120 18:11:47.920457 memory_type:LPDDR4
7121 18:11:47.923889 GP_NUM : 10
7122 18:11:47.927366 SRAM_EN : 1
7123 18:11:47.927453 MD32_EN : 0
7124 18:11:47.930264 ===================================
7125 18:11:47.933822 [ANA_INIT] >>>>>>>>>>>>>>
7126 18:11:47.937465 <<<<<< [CONFIGURE PHASE]: ANA_TX
7127 18:11:47.940464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7128 18:11:47.943868 ===================================
7129 18:11:47.946870 data_rate = 3200,PCW = 0X7600
7130 18:11:47.950514 ===================================
7131 18:11:47.953407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7132 18:11:47.956932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 18:11:47.963705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 18:11:47.966790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7135 18:11:47.970224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7136 18:11:47.973706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7137 18:11:47.976727 [ANA_INIT] flow start
7138 18:11:47.980438 [ANA_INIT] PLL >>>>>>>>
7139 18:11:47.980524 [ANA_INIT] PLL <<<<<<<<
7140 18:11:47.983486 [ANA_INIT] MIDPI >>>>>>>>
7141 18:11:47.986967 [ANA_INIT] MIDPI <<<<<<<<
7142 18:11:47.989937 [ANA_INIT] DLL >>>>>>>>
7143 18:11:47.990023 [ANA_INIT] DLL <<<<<<<<
7144 18:11:47.993424 [ANA_INIT] flow end
7145 18:11:47.996904 ============ LP4 DIFF to SE enter ============
7146 18:11:47.999786 ============ LP4 DIFF to SE exit ============
7147 18:11:48.003173 [ANA_INIT] <<<<<<<<<<<<<
7148 18:11:48.006418 [Flow] Enable top DCM control >>>>>
7149 18:11:48.009714 [Flow] Enable top DCM control <<<<<
7150 18:11:48.013176 Enable DLL master slave shuffle
7151 18:11:48.019854 ==============================================================
7152 18:11:48.019946 Gating Mode config
7153 18:11:48.026506 ==============================================================
7154 18:11:48.026598 Config description:
7155 18:11:48.036685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7156 18:11:48.043170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7157 18:11:48.049783 SELPH_MODE 0: By rank 1: By Phase
7158 18:11:48.053240 ==============================================================
7159 18:11:48.056255 GAT_TRACK_EN = 1
7160 18:11:48.059784 RX_GATING_MODE = 2
7161 18:11:48.063274 RX_GATING_TRACK_MODE = 2
7162 18:11:48.066609 SELPH_MODE = 1
7163 18:11:48.069630 PICG_EARLY_EN = 1
7164 18:11:48.073312 VALID_LAT_VALUE = 1
7165 18:11:48.079684 ==============================================================
7166 18:11:48.083224 Enter into Gating configuration >>>>
7167 18:11:48.083317 Exit from Gating configuration <<<<
7168 18:11:48.086238 Enter into DVFS_PRE_config >>>>>
7169 18:11:48.099644 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7170 18:11:48.102959 Exit from DVFS_PRE_config <<<<<
7171 18:11:48.106483 Enter into PICG configuration >>>>
7172 18:11:48.109736 Exit from PICG configuration <<<<
7173 18:11:48.109821 [RX_INPUT] configuration >>>>>
7174 18:11:48.113018 [RX_INPUT] configuration <<<<<
7175 18:11:48.119361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7176 18:11:48.122684 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7177 18:11:48.129885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 18:11:48.136263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 18:11:48.142768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7180 18:11:48.149377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7181 18:11:48.152811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7182 18:11:48.155908 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7183 18:11:48.162950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7184 18:11:48.165970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7185 18:11:48.169388 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7186 18:11:48.172796 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 18:11:48.176395 ===================================
7188 18:11:48.179294 LPDDR4 DRAM CONFIGURATION
7189 18:11:48.182953 ===================================
7190 18:11:48.185999 EX_ROW_EN[0] = 0x0
7191 18:11:48.186083 EX_ROW_EN[1] = 0x0
7192 18:11:48.189620 LP4Y_EN = 0x0
7193 18:11:48.189703 WORK_FSP = 0x1
7194 18:11:48.192496 WL = 0x5
7195 18:11:48.192636 RL = 0x5
7196 18:11:48.195995 BL = 0x2
7197 18:11:48.196079 RPST = 0x0
7198 18:11:48.199127 RD_PRE = 0x0
7199 18:11:48.199211 WR_PRE = 0x1
7200 18:11:48.202816 WR_PST = 0x1
7201 18:11:48.202900 DBI_WR = 0x0
7202 18:11:48.206216 DBI_RD = 0x0
7203 18:11:48.206299 OTF = 0x1
7204 18:11:48.209087 ===================================
7205 18:11:48.216220 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7206 18:11:48.219529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7207 18:11:48.222488 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 18:11:48.225949 ===================================
7209 18:11:48.229248 LPDDR4 DRAM CONFIGURATION
7210 18:11:48.232754 ===================================
7211 18:11:48.235770 EX_ROW_EN[0] = 0x10
7212 18:11:48.235855 EX_ROW_EN[1] = 0x0
7213 18:11:48.239227 LP4Y_EN = 0x0
7214 18:11:48.239311 WORK_FSP = 0x1
7215 18:11:48.242845 WL = 0x5
7216 18:11:48.242929 RL = 0x5
7217 18:11:48.245959 BL = 0x2
7218 18:11:48.246043 RPST = 0x0
7219 18:11:48.249362 RD_PRE = 0x0
7220 18:11:48.249446 WR_PRE = 0x1
7221 18:11:48.252373 WR_PST = 0x1
7222 18:11:48.252457 DBI_WR = 0x0
7223 18:11:48.255825 DBI_RD = 0x0
7224 18:11:48.255913 OTF = 0x1
7225 18:11:48.259412 ===================================
7226 18:11:48.265516 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7227 18:11:48.265600 ==
7228 18:11:48.268952 Dram Type= 6, Freq= 0, CH_0, rank 0
7229 18:11:48.275569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7230 18:11:48.275713 ==
7231 18:11:48.275783 [Duty_Offset_Calibration]
7232 18:11:48.279030 B0:2 B1:0 CA:1
7233 18:11:48.279119
7234 18:11:48.282590 [DutyScan_Calibration_Flow] k_type=0
7235 18:11:48.290654
7236 18:11:48.290752 ==CLK 0==
7237 18:11:48.294046 Final CLK duty delay cell = -4
7238 18:11:48.297125 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7239 18:11:48.300755 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7240 18:11:48.304163 [-4] AVG Duty = 4906%(X100)
7241 18:11:48.304249
7242 18:11:48.307182 CH0 CLK Duty spec in!! Max-Min= 187%
7243 18:11:48.310670 [DutyScan_Calibration_Flow] ====Done====
7244 18:11:48.310756
7245 18:11:48.313741 [DutyScan_Calibration_Flow] k_type=1
7246 18:11:48.330355
7247 18:11:48.330486 ==DQS 0 ==
7248 18:11:48.333298 Final DQS duty delay cell = 0
7249 18:11:48.336835 [0] MAX Duty = 5218%(X100), DQS PI = 34
7250 18:11:48.340217 [0] MIN Duty = 4938%(X100), DQS PI = 60
7251 18:11:48.343227 [0] AVG Duty = 5078%(X100)
7252 18:11:48.343313
7253 18:11:48.343379 ==DQS 1 ==
7254 18:11:48.346758 Final DQS duty delay cell = -4
7255 18:11:48.350333 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7256 18:11:48.353243 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7257 18:11:48.356760 [-4] AVG Duty = 4984%(X100)
7258 18:11:48.356854
7259 18:11:48.359885 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7260 18:11:48.359975
7261 18:11:48.363293 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7262 18:11:48.366660 [DutyScan_Calibration_Flow] ====Done====
7263 18:11:48.366758
7264 18:11:48.369898 [DutyScan_Calibration_Flow] k_type=3
7265 18:11:48.387792
7266 18:11:48.387950 ==DQM 0 ==
7267 18:11:48.391282 Final DQM duty delay cell = 0
7268 18:11:48.394262 [0] MAX Duty = 5093%(X100), DQS PI = 26
7269 18:11:48.397818 [0] MIN Duty = 4813%(X100), DQS PI = 50
7270 18:11:48.398021 [0] AVG Duty = 4953%(X100)
7271 18:11:48.401112
7272 18:11:48.401199 ==DQM 1 ==
7273 18:11:48.404193 Final DQM duty delay cell = 0
7274 18:11:48.407491 [0] MAX Duty = 5249%(X100), DQS PI = 30
7275 18:11:48.411295 [0] MIN Duty = 5000%(X100), DQS PI = 20
7276 18:11:48.414147 [0] AVG Duty = 5124%(X100)
7277 18:11:48.414229
7278 18:11:48.417555 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7279 18:11:48.417672
7280 18:11:48.420803 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7281 18:11:48.423966 [DutyScan_Calibration_Flow] ====Done====
7282 18:11:48.424153
7283 18:11:48.427265 [DutyScan_Calibration_Flow] k_type=2
7284 18:11:48.444781
7285 18:11:48.444928 ==DQ 0 ==
7286 18:11:48.448260 Final DQ duty delay cell = 0
7287 18:11:48.451728 [0] MAX Duty = 5124%(X100), DQS PI = 34
7288 18:11:48.454619 [0] MIN Duty = 5000%(X100), DQS PI = 0
7289 18:11:48.454711 [0] AVG Duty = 5062%(X100)
7290 18:11:48.458186
7291 18:11:48.458273 ==DQ 1 ==
7292 18:11:48.461218 Final DQ duty delay cell = 0
7293 18:11:48.464854 [0] MAX Duty = 4969%(X100), DQS PI = 44
7294 18:11:48.468261 [0] MIN Duty = 4875%(X100), DQS PI = 10
7295 18:11:48.468367 [0] AVG Duty = 4922%(X100)
7296 18:11:48.468431
7297 18:11:48.471857 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7298 18:11:48.474741
7299 18:11:48.474823 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7300 18:11:48.481714 [DutyScan_Calibration_Flow] ====Done====
7301 18:11:48.481825 ==
7302 18:11:48.485114 Dram Type= 6, Freq= 0, CH_1, rank 0
7303 18:11:48.488170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 18:11:48.488284 ==
7305 18:11:48.491618 [Duty_Offset_Calibration]
7306 18:11:48.491717 B0:0 B1:-1 CA:2
7307 18:11:48.491805
7308 18:11:48.494850 [DutyScan_Calibration_Flow] k_type=0
7309 18:11:48.505251
7310 18:11:48.505369 ==CLK 0==
7311 18:11:48.508229 Final CLK duty delay cell = 0
7312 18:11:48.511743 [0] MAX Duty = 5156%(X100), DQS PI = 42
7313 18:11:48.515237 [0] MIN Duty = 4906%(X100), DQS PI = 12
7314 18:11:48.518084 [0] AVG Duty = 5031%(X100)
7315 18:11:48.518176
7316 18:11:48.521766 CH1 CLK Duty spec in!! Max-Min= 250%
7317 18:11:48.525062 [DutyScan_Calibration_Flow] ====Done====
7318 18:11:48.525179
7319 18:11:48.527962 [DutyScan_Calibration_Flow] k_type=1
7320 18:11:48.544736
7321 18:11:48.544884 ==DQS 0 ==
7322 18:11:48.548175 Final DQS duty delay cell = 0
7323 18:11:48.551792 [0] MAX Duty = 5062%(X100), DQS PI = 8
7324 18:11:48.554833 [0] MIN Duty = 5000%(X100), DQS PI = 0
7325 18:11:48.554915 [0] AVG Duty = 5031%(X100)
7326 18:11:48.558173
7327 18:11:48.558253 ==DQS 1 ==
7328 18:11:48.561240 Final DQS duty delay cell = 0
7329 18:11:48.564915 [0] MAX Duty = 5187%(X100), DQS PI = 26
7330 18:11:48.567992 [0] MIN Duty = 4813%(X100), DQS PI = 4
7331 18:11:48.568073 [0] AVG Duty = 5000%(X100)
7332 18:11:48.571444
7333 18:11:48.574528 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7334 18:11:48.574609
7335 18:11:48.577921 CH1 DQS 1 Duty spec in!! Max-Min= 374%
7336 18:11:48.581496 [DutyScan_Calibration_Flow] ====Done====
7337 18:11:48.581611
7338 18:11:48.584451 [DutyScan_Calibration_Flow] k_type=3
7339 18:11:48.602135
7340 18:11:48.602244 ==DQM 0 ==
7341 18:11:48.605782 Final DQM duty delay cell = 4
7342 18:11:48.608735 [4] MAX Duty = 5125%(X100), DQS PI = 22
7343 18:11:48.612270 [4] MIN Duty = 4938%(X100), DQS PI = 0
7344 18:11:48.612379 [4] AVG Duty = 5031%(X100)
7345 18:11:48.615407
7346 18:11:48.615487 ==DQM 1 ==
7347 18:11:48.618732 Final DQM duty delay cell = 0
7348 18:11:48.622272 [0] MAX Duty = 5281%(X100), DQS PI = 26
7349 18:11:48.625266 [0] MIN Duty = 4875%(X100), DQS PI = 4
7350 18:11:48.625351 [0] AVG Duty = 5078%(X100)
7351 18:11:48.628850
7352 18:11:48.632283 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7353 18:11:48.632367
7354 18:11:48.635615 CH1 DQM 1 Duty spec in!! Max-Min= 406%
7355 18:11:48.638847 [DutyScan_Calibration_Flow] ====Done====
7356 18:11:48.638931
7357 18:11:48.642243 [DutyScan_Calibration_Flow] k_type=2
7358 18:11:48.659359
7359 18:11:48.659459 ==DQ 0 ==
7360 18:11:48.662285 Final DQ duty delay cell = 0
7361 18:11:48.665798 [0] MAX Duty = 5093%(X100), DQS PI = 22
7362 18:11:48.668875 [0] MIN Duty = 4938%(X100), DQS PI = 0
7363 18:11:48.668959 [0] AVG Duty = 5015%(X100)
7364 18:11:48.669025
7365 18:11:48.672255 ==DQ 1 ==
7366 18:11:48.675494 Final DQ duty delay cell = 0
7367 18:11:48.678936 [0] MAX Duty = 5062%(X100), DQS PI = 32
7368 18:11:48.682021 [0] MIN Duty = 4813%(X100), DQS PI = 0
7369 18:11:48.682104 [0] AVG Duty = 4937%(X100)
7370 18:11:48.682170
7371 18:11:48.685749 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7372 18:11:48.688721
7373 18:11:48.692199 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7374 18:11:48.695631 [DutyScan_Calibration_Flow] ====Done====
7375 18:11:48.698722 nWR fixed to 30
7376 18:11:48.698806 [ModeRegInit_LP4] CH0 RK0
7377 18:11:48.701857 [ModeRegInit_LP4] CH0 RK1
7378 18:11:48.705296 [ModeRegInit_LP4] CH1 RK0
7379 18:11:48.708432 [ModeRegInit_LP4] CH1 RK1
7380 18:11:48.708514 match AC timing 5
7381 18:11:48.712071 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7382 18:11:48.718738 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7383 18:11:48.721691 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7384 18:11:48.728570 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7385 18:11:48.731956 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7386 18:11:48.732039 [MiockJmeterHQA]
7387 18:11:48.732105
7388 18:11:48.734970 [DramcMiockJmeter] u1RxGatingPI = 0
7389 18:11:48.738324 0 : 4362, 4137
7390 18:11:48.738407 4 : 4254, 4029
7391 18:11:48.741691 8 : 4363, 4137
7392 18:11:48.741776 12 : 4252, 4027
7393 18:11:48.741862 16 : 4363, 4138
7394 18:11:48.745038 20 : 4255, 4029
7395 18:11:48.745124 24 : 4361, 4137
7396 18:11:48.748253 28 : 4252, 4027
7397 18:11:48.748339 32 : 4250, 4026
7398 18:11:48.751681 36 : 4250, 4027
7399 18:11:48.751766 40 : 4361, 4137
7400 18:11:48.755161 44 : 4361, 4137
7401 18:11:48.755245 48 : 4250, 4027
7402 18:11:48.755329 52 : 4250, 4027
7403 18:11:48.758593 56 : 4250, 4027
7404 18:11:48.758678 60 : 4249, 4027
7405 18:11:48.761753 64 : 4253, 4029
7406 18:11:48.761838 68 : 4360, 4138
7407 18:11:48.765190 72 : 4250, 4026
7408 18:11:48.765276 76 : 4250, 4027
7409 18:11:48.765360 80 : 4249, 4027
7410 18:11:48.768267 84 : 4252, 4029
7411 18:11:48.768352 88 : 4250, 3789
7412 18:11:48.771764 92 : 4361, 0
7413 18:11:48.771849 96 : 4249, 0
7414 18:11:48.771953 100 : 4360, 0
7415 18:11:48.775281 104 : 4250, 0
7416 18:11:48.775366 108 : 4250, 0
7417 18:11:48.778349 112 : 4249, 0
7418 18:11:48.778434 116 : 4363, 0
7419 18:11:48.778518 120 : 4250, 0
7420 18:11:48.781817 124 : 4250, 0
7421 18:11:48.781903 128 : 4250, 0
7422 18:11:48.784736 132 : 4253, 0
7423 18:11:48.784822 136 : 4250, 0
7424 18:11:48.784906 140 : 4250, 0
7425 18:11:48.788301 144 : 4252, 0
7426 18:11:48.788386 148 : 4250, 0
7427 18:11:48.791739 152 : 4250, 0
7428 18:11:48.791824 156 : 4363, 0
7429 18:11:48.791908 160 : 4361, 0
7430 18:11:48.794784 164 : 4361, 0
7431 18:11:48.794869 168 : 4363, 0
7432 18:11:48.794953 172 : 4250, 0
7433 18:11:48.798052 176 : 4250, 0
7434 18:11:48.798137 180 : 4250, 0
7435 18:11:48.801808 184 : 4250, 0
7436 18:11:48.801893 188 : 4252, 0
7437 18:11:48.801960 192 : 4250, 0
7438 18:11:48.804843 196 : 4250, 0
7439 18:11:48.804928 200 : 4250, 25
7440 18:11:48.808248 204 : 4250, 2886
7441 18:11:48.808332 208 : 4250, 4027
7442 18:11:48.811248 212 : 4360, 4137
7443 18:11:48.811333 216 : 4250, 4026
7444 18:11:48.814721 220 : 4250, 4027
7445 18:11:48.814805 224 : 4360, 4138
7446 18:11:48.814873 228 : 4250, 4027
7447 18:11:48.817868 232 : 4250, 4026
7448 18:11:48.817953 236 : 4363, 4140
7449 18:11:48.821516 240 : 4250, 4027
7450 18:11:48.821601 244 : 4250, 4027
7451 18:11:48.824873 248 : 4250, 4027
7452 18:11:48.824957 252 : 4253, 4029
7453 18:11:48.828224 256 : 4250, 4027
7454 18:11:48.828309 260 : 4252, 4029
7455 18:11:48.831629 264 : 4360, 4137
7456 18:11:48.831714 268 : 4250, 4026
7457 18:11:48.834702 272 : 4250, 4027
7458 18:11:48.834787 276 : 4360, 4138
7459 18:11:48.838186 280 : 4249, 4027
7460 18:11:48.838271 284 : 4250, 4026
7461 18:11:48.838337 288 : 4363, 4139
7462 18:11:48.841614 292 : 4250, 4027
7463 18:11:48.841728 296 : 4250, 4027
7464 18:11:48.844601 300 : 4250, 4026
7465 18:11:48.844685 304 : 4253, 4029
7466 18:11:48.847955 308 : 4250, 4027
7467 18:11:48.848039 312 : 4250, 3953
7468 18:11:48.851437 316 : 4360, 1815
7469 18:11:48.851522
7470 18:11:48.851588 MIOCK jitter meter ch=0
7471 18:11:48.854695
7472 18:11:48.854778 1T = (316-92) = 224 dly cells
7473 18:11:48.861089 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7474 18:11:48.861173 ==
7475 18:11:48.864510 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 18:11:48.867835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 18:11:48.867920 ==
7478 18:11:48.874944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 18:11:48.877782 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 18:11:48.884500 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 18:11:48.888045 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 18:11:48.897949 [CA 0] Center 42 (12~73) winsize 62
7483 18:11:48.901574 [CA 1] Center 42 (12~72) winsize 61
7484 18:11:48.904605 [CA 2] Center 37 (7~67) winsize 61
7485 18:11:48.908132 [CA 3] Center 37 (7~67) winsize 61
7486 18:11:48.911157 [CA 4] Center 36 (6~66) winsize 61
7487 18:11:48.914645 [CA 5] Center 35 (5~65) winsize 61
7488 18:11:48.914729
7489 18:11:48.918213 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 18:11:48.918297
7491 18:11:48.921342 [CATrainingPosCal] consider 1 rank data
7492 18:11:48.924286 u2DelayCellTimex100 = 290/100 ps
7493 18:11:48.927831 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7494 18:11:48.934315 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7495 18:11:48.937905 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7496 18:11:48.941199 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7497 18:11:48.944809 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7498 18:11:48.948056 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7499 18:11:48.948153
7500 18:11:48.951429 CA PerBit enable=1, Macro0, CA PI delay=35
7501 18:11:48.951512
7502 18:11:48.954738 [CBTSetCACLKResult] CA Dly = 35
7503 18:11:48.954825 CS Dly: 9 (0~40)
7504 18:11:48.960936 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 18:11:48.964449 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 18:11:48.964578 ==
7507 18:11:48.967851 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 18:11:48.971482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 18:11:48.971566 ==
7510 18:11:48.977614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 18:11:48.981085 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 18:11:48.987721 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 18:11:48.991106 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 18:11:49.001334 [CA 0] Center 43 (14~73) winsize 60
7515 18:11:49.004264 [CA 1] Center 43 (13~73) winsize 61
7516 18:11:49.007766 [CA 2] Center 38 (9~68) winsize 60
7517 18:11:49.011197 [CA 3] Center 38 (8~68) winsize 61
7518 18:11:49.014282 [CA 4] Center 37 (7~67) winsize 61
7519 18:11:49.017858 [CA 5] Center 36 (6~66) winsize 61
7520 18:11:49.017940
7521 18:11:49.020920 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 18:11:49.021002
7523 18:11:49.024477 [CATrainingPosCal] consider 2 rank data
7524 18:11:49.027568 u2DelayCellTimex100 = 290/100 ps
7525 18:11:49.030902 CA0 delay=43 (14~73),Diff = 8 PI (26 cell)
7526 18:11:49.037599 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7527 18:11:49.041095 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7528 18:11:49.044132 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 18:11:49.047568 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7530 18:11:49.050879 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7531 18:11:49.050961
7532 18:11:49.054178 CA PerBit enable=1, Macro0, CA PI delay=35
7533 18:11:49.054261
7534 18:11:49.057557 [CBTSetCACLKResult] CA Dly = 35
7535 18:11:49.060887 CS Dly: 10 (0~43)
7536 18:11:49.064295 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 18:11:49.067706 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 18:11:49.067788
7539 18:11:49.071129 ----->DramcWriteLeveling(PI) begin...
7540 18:11:49.071213 ==
7541 18:11:49.074089 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 18:11:49.077692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 18:11:49.080573 ==
7544 18:11:49.084083 Write leveling (Byte 0): 37 => 37
7545 18:11:49.084166 Write leveling (Byte 1): 31 => 31
7546 18:11:49.087639 DramcWriteLeveling(PI) end<-----
7547 18:11:49.087722
7548 18:11:49.087787 ==
7549 18:11:49.090693 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 18:11:49.097367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 18:11:49.097452 ==
7552 18:11:49.100895 [Gating] SW mode calibration
7553 18:11:49.107535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 18:11:49.110861 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 18:11:49.117091 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 18:11:49.120637 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 18:11:49.123633 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
7558 18:11:49.130311 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 18:11:49.133871 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7560 18:11:49.137436 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7561 18:11:49.143880 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 18:11:49.147260 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 18:11:49.150272 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 18:11:49.157000 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7565 18:11:49.160442 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7566 18:11:49.163656 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7567 18:11:49.170271 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7568 18:11:49.173580 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7569 18:11:49.176741 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 18:11:49.183233 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 18:11:49.186741 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 18:11:49.189834 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 18:11:49.193287 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
7574 18:11:49.200233 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7575 18:11:49.203418 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7576 18:11:49.207031 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7577 18:11:49.213471 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 18:11:49.216381 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 18:11:49.220106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 18:11:49.226661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 18:11:49.229715 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 18:11:49.233266 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 18:11:49.239772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7584 18:11:49.243171 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 18:11:49.246399 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 18:11:49.252997 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 18:11:49.256511 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 18:11:49.259477 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 18:11:49.266246 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 18:11:49.269686 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 18:11:49.272817 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 18:11:49.279729 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 18:11:49.283058 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 18:11:49.286138 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 18:11:49.292710 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 18:11:49.296163 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 18:11:49.299330 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 18:11:49.305824 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 18:11:49.309469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7600 18:11:49.312457 Total UI for P1: 0, mck2ui 16
7601 18:11:49.316185 best dqsien dly found for B0: ( 1, 9, 10)
7602 18:11:49.319487 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 18:11:49.326075 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 18:11:49.326230 Total UI for P1: 0, mck2ui 16
7605 18:11:49.332564 best dqsien dly found for B1: ( 1, 9, 20)
7606 18:11:49.335948 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7607 18:11:49.339057 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7608 18:11:49.339188
7609 18:11:49.342562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7610 18:11:49.346219 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7611 18:11:49.349142 [Gating] SW calibration Done
7612 18:11:49.349296 ==
7613 18:11:49.352676 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 18:11:49.356121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 18:11:49.356301 ==
7616 18:11:49.359168 RX Vref Scan: 0
7617 18:11:49.359336
7618 18:11:49.359406 RX Vref 0 -> 0, step: 1
7619 18:11:49.359469
7620 18:11:49.362529 RX Delay 0 -> 252, step: 8
7621 18:11:49.365491 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7622 18:11:49.372264 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7623 18:11:49.375695 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7624 18:11:49.379242 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7625 18:11:49.382075 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 18:11:49.385604 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7627 18:11:49.392307 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 18:11:49.395299 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7629 18:11:49.398914 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7630 18:11:49.401950 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7631 18:11:49.405366 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7632 18:11:49.411972 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7633 18:11:49.415430 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7634 18:11:49.418518 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7635 18:11:49.422005 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 18:11:49.425104 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7637 18:11:49.428761 ==
7638 18:11:49.428932 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 18:11:49.435190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 18:11:49.435348 ==
7641 18:11:49.435431 DQS Delay:
7642 18:11:49.438574 DQS0 = 0, DQS1 = 0
7643 18:11:49.438665 DQM Delay:
7644 18:11:49.441671 DQM0 = 138, DQM1 = 126
7645 18:11:49.441756 DQ Delay:
7646 18:11:49.445169 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7647 18:11:49.448744 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7648 18:11:49.451912 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7649 18:11:49.455278 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =131
7650 18:11:49.455369
7651 18:11:49.455437
7652 18:11:49.455498 ==
7653 18:11:49.458600 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 18:11:49.465043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 18:11:49.465146 ==
7656 18:11:49.465215
7657 18:11:49.465277
7658 18:11:49.465338 TX Vref Scan disable
7659 18:11:49.468487 == TX Byte 0 ==
7660 18:11:49.471841 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7661 18:11:49.478621 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7662 18:11:49.478721 == TX Byte 1 ==
7663 18:11:49.482039 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7664 18:11:49.488535 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7665 18:11:49.488728 ==
7666 18:11:49.491782 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 18:11:49.495202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 18:11:49.495295 ==
7669 18:11:49.508955
7670 18:11:49.512323 TX Vref early break, caculate TX vref
7671 18:11:49.515874 TX Vref=16, minBit 4, minWin=23, winSum=380
7672 18:11:49.518988 TX Vref=18, minBit 4, minWin=23, winSum=384
7673 18:11:49.522196 TX Vref=20, minBit 1, minWin=24, winSum=396
7674 18:11:49.525580 TX Vref=22, minBit 7, minWin=24, winSum=406
7675 18:11:49.528956 TX Vref=24, minBit 0, minWin=25, winSum=416
7676 18:11:49.535593 TX Vref=26, minBit 0, minWin=26, winSum=425
7677 18:11:49.538918 TX Vref=28, minBit 2, minWin=25, winSum=427
7678 18:11:49.541962 TX Vref=30, minBit 0, minWin=26, winSum=423
7679 18:11:49.545561 TX Vref=32, minBit 0, minWin=25, winSum=417
7680 18:11:49.548694 TX Vref=34, minBit 7, minWin=24, winSum=406
7681 18:11:49.552063 TX Vref=36, minBit 1, minWin=24, winSum=394
7682 18:11:49.558719 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
7683 18:11:49.558806
7684 18:11:49.562147 Final TX Range 0 Vref 26
7685 18:11:49.562231
7686 18:11:49.562297 ==
7687 18:11:49.565572 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 18:11:49.568524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 18:11:49.568657 ==
7690 18:11:49.568725
7691 18:11:49.568786
7692 18:11:49.572027 TX Vref Scan disable
7693 18:11:49.578876 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7694 18:11:49.578996 == TX Byte 0 ==
7695 18:11:49.582076 u2DelayCellOfst[0]=10 cells (3 PI)
7696 18:11:49.585290 u2DelayCellOfst[1]=13 cells (4 PI)
7697 18:11:49.588503 u2DelayCellOfst[2]=10 cells (3 PI)
7698 18:11:49.591869 u2DelayCellOfst[3]=10 cells (3 PI)
7699 18:11:49.595183 u2DelayCellOfst[4]=6 cells (2 PI)
7700 18:11:49.598682 u2DelayCellOfst[5]=0 cells (0 PI)
7701 18:11:49.601776 u2DelayCellOfst[6]=16 cells (5 PI)
7702 18:11:49.605303 u2DelayCellOfst[7]=13 cells (4 PI)
7703 18:11:49.608774 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7704 18:11:49.611757 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7705 18:11:49.615248 == TX Byte 1 ==
7706 18:11:49.618812 u2DelayCellOfst[8]=0 cells (0 PI)
7707 18:11:49.621941 u2DelayCellOfst[9]=0 cells (0 PI)
7708 18:11:49.622030 u2DelayCellOfst[10]=6 cells (2 PI)
7709 18:11:49.625271 u2DelayCellOfst[11]=3 cells (1 PI)
7710 18:11:49.628436 u2DelayCellOfst[12]=10 cells (3 PI)
7711 18:11:49.631724 u2DelayCellOfst[13]=10 cells (3 PI)
7712 18:11:49.635284 u2DelayCellOfst[14]=13 cells (4 PI)
7713 18:11:49.638343 u2DelayCellOfst[15]=10 cells (3 PI)
7714 18:11:49.645306 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7715 18:11:49.648319 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7716 18:11:49.648404 DramC Write-DBI on
7717 18:11:49.648469 ==
7718 18:11:49.651909 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 18:11:49.658543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 18:11:49.658627 ==
7721 18:11:49.658692
7722 18:11:49.658753
7723 18:11:49.658812 TX Vref Scan disable
7724 18:11:49.662609 == TX Byte 0 ==
7725 18:11:49.665807 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7726 18:11:49.669106 == TX Byte 1 ==
7727 18:11:49.672530 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7728 18:11:49.675516 DramC Write-DBI off
7729 18:11:49.675599
7730 18:11:49.675665 [DATLAT]
7731 18:11:49.675726 Freq=1600, CH0 RK0
7732 18:11:49.675785
7733 18:11:49.678755 DATLAT Default: 0xf
7734 18:11:49.681940 0, 0xFFFF, sum = 0
7735 18:11:49.682024 1, 0xFFFF, sum = 0
7736 18:11:49.685746 2, 0xFFFF, sum = 0
7737 18:11:49.685830 3, 0xFFFF, sum = 0
7738 18:11:49.689029 4, 0xFFFF, sum = 0
7739 18:11:49.689113 5, 0xFFFF, sum = 0
7740 18:11:49.692377 6, 0xFFFF, sum = 0
7741 18:11:49.692460 7, 0xFFFF, sum = 0
7742 18:11:49.695736 8, 0xFFFF, sum = 0
7743 18:11:49.695819 9, 0xFFFF, sum = 0
7744 18:11:49.698691 10, 0xFFFF, sum = 0
7745 18:11:49.698775 11, 0xFFFF, sum = 0
7746 18:11:49.701887 12, 0xFFFF, sum = 0
7747 18:11:49.701971 13, 0xFFFF, sum = 0
7748 18:11:49.705495 14, 0x0, sum = 1
7749 18:11:49.705582 15, 0x0, sum = 2
7750 18:11:49.708524 16, 0x0, sum = 3
7751 18:11:49.708632 17, 0x0, sum = 4
7752 18:11:49.712142 best_step = 15
7753 18:11:49.712225
7754 18:11:49.712292 ==
7755 18:11:49.715220 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 18:11:49.718687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 18:11:49.718774 ==
7758 18:11:49.722172 RX Vref Scan: 1
7759 18:11:49.722271
7760 18:11:49.722338 Set Vref Range= 24 -> 127
7761 18:11:49.722400
7762 18:11:49.725741 RX Vref 24 -> 127, step: 1
7763 18:11:49.725860
7764 18:11:49.728756 RX Delay 19 -> 252, step: 4
7765 18:11:49.728840
7766 18:11:49.731824 Set Vref, RX VrefLevel [Byte0]: 24
7767 18:11:49.735153 [Byte1]: 24
7768 18:11:49.735237
7769 18:11:49.738727 Set Vref, RX VrefLevel [Byte0]: 25
7770 18:11:49.742120 [Byte1]: 25
7771 18:11:49.742205
7772 18:11:49.745601 Set Vref, RX VrefLevel [Byte0]: 26
7773 18:11:49.748539 [Byte1]: 26
7774 18:11:49.752571
7775 18:11:49.752655 Set Vref, RX VrefLevel [Byte0]: 27
7776 18:11:49.755740 [Byte1]: 27
7777 18:11:49.760394
7778 18:11:49.760491 Set Vref, RX VrefLevel [Byte0]: 28
7779 18:11:49.763465 [Byte1]: 28
7780 18:11:49.768025
7781 18:11:49.768108 Set Vref, RX VrefLevel [Byte0]: 29
7782 18:11:49.770981 [Byte1]: 29
7783 18:11:49.775451
7784 18:11:49.775534 Set Vref, RX VrefLevel [Byte0]: 30
7785 18:11:49.778851 [Byte1]: 30
7786 18:11:49.783039
7787 18:11:49.783122 Set Vref, RX VrefLevel [Byte0]: 31
7788 18:11:49.786374 [Byte1]: 31
7789 18:11:49.790741
7790 18:11:49.790823 Set Vref, RX VrefLevel [Byte0]: 32
7791 18:11:49.793715 [Byte1]: 32
7792 18:11:49.797933
7793 18:11:49.798016 Set Vref, RX VrefLevel [Byte0]: 33
7794 18:11:49.801326 [Byte1]: 33
7795 18:11:49.805911
7796 18:11:49.805996 Set Vref, RX VrefLevel [Byte0]: 34
7797 18:11:49.808930 [Byte1]: 34
7798 18:11:49.813470
7799 18:11:49.813552 Set Vref, RX VrefLevel [Byte0]: 35
7800 18:11:49.816406 [Byte1]: 35
7801 18:11:49.821038
7802 18:11:49.821120 Set Vref, RX VrefLevel [Byte0]: 36
7803 18:11:49.824097 [Byte1]: 36
7804 18:11:49.828508
7805 18:11:49.828631 Set Vref, RX VrefLevel [Byte0]: 37
7806 18:11:49.831692 [Byte1]: 37
7807 18:11:49.836136
7808 18:11:49.836218 Set Vref, RX VrefLevel [Byte0]: 38
7809 18:11:49.839537 [Byte1]: 38
7810 18:11:49.843643
7811 18:11:49.843726 Set Vref, RX VrefLevel [Byte0]: 39
7812 18:11:49.847000 [Byte1]: 39
7813 18:11:49.851142
7814 18:11:49.851224 Set Vref, RX VrefLevel [Byte0]: 40
7815 18:11:49.854189 [Byte1]: 40
7816 18:11:49.858731
7817 18:11:49.858814 Set Vref, RX VrefLevel [Byte0]: 41
7818 18:11:49.861862 [Byte1]: 41
7819 18:11:49.866208
7820 18:11:49.866291 Set Vref, RX VrefLevel [Byte0]: 42
7821 18:11:49.869661 [Byte1]: 42
7822 18:11:49.873632
7823 18:11:49.873715 Set Vref, RX VrefLevel [Byte0]: 43
7824 18:11:49.877114 [Byte1]: 43
7825 18:11:49.881537
7826 18:11:49.881620 Set Vref, RX VrefLevel [Byte0]: 44
7827 18:11:49.884981 [Byte1]: 44
7828 18:11:49.889018
7829 18:11:49.889100 Set Vref, RX VrefLevel [Byte0]: 45
7830 18:11:49.892267 [Byte1]: 45
7831 18:11:49.896459
7832 18:11:49.896541 Set Vref, RX VrefLevel [Byte0]: 46
7833 18:11:49.899946 [Byte1]: 46
7834 18:11:49.904322
7835 18:11:49.904404 Set Vref, RX VrefLevel [Byte0]: 47
7836 18:11:49.907407 [Byte1]: 47
7837 18:11:49.911653
7838 18:11:49.911761 Set Vref, RX VrefLevel [Byte0]: 48
7839 18:11:49.914784 [Byte1]: 48
7840 18:11:49.919244
7841 18:11:49.919327 Set Vref, RX VrefLevel [Byte0]: 49
7842 18:11:49.922458 [Byte1]: 49
7843 18:11:49.926862
7844 18:11:49.926944 Set Vref, RX VrefLevel [Byte0]: 50
7845 18:11:49.930329 [Byte1]: 50
7846 18:11:49.934372
7847 18:11:49.934454 Set Vref, RX VrefLevel [Byte0]: 51
7848 18:11:49.938063 [Byte1]: 51
7849 18:11:49.941944
7850 18:11:49.942026 Set Vref, RX VrefLevel [Byte0]: 52
7851 18:11:49.945318 [Byte1]: 52
7852 18:11:49.949740
7853 18:11:49.949822 Set Vref, RX VrefLevel [Byte0]: 53
7854 18:11:49.952732 [Byte1]: 53
7855 18:11:49.956970
7856 18:11:49.957052 Set Vref, RX VrefLevel [Byte0]: 54
7857 18:11:49.960498 [Byte1]: 54
7858 18:11:49.964462
7859 18:11:49.964544 Set Vref, RX VrefLevel [Byte0]: 55
7860 18:11:49.967983 [Byte1]: 55
7861 18:11:49.972480
7862 18:11:49.972584 Set Vref, RX VrefLevel [Byte0]: 56
7863 18:11:49.975514 [Byte1]: 56
7864 18:11:49.979932
7865 18:11:49.980014 Set Vref, RX VrefLevel [Byte0]: 57
7866 18:11:49.983288 [Byte1]: 57
7867 18:11:49.987713
7868 18:11:49.987795 Set Vref, RX VrefLevel [Byte0]: 58
7869 18:11:49.990704 [Byte1]: 58
7870 18:11:49.994975
7871 18:11:49.995057 Set Vref, RX VrefLevel [Byte0]: 59
7872 18:11:49.998151 [Byte1]: 59
7873 18:11:50.002424
7874 18:11:50.002506 Set Vref, RX VrefLevel [Byte0]: 60
7875 18:11:50.005752 [Byte1]: 60
7876 18:11:50.010087
7877 18:11:50.010168 Set Vref, RX VrefLevel [Byte0]: 61
7878 18:11:50.013528 [Byte1]: 61
7879 18:11:50.017684
7880 18:11:50.017765 Set Vref, RX VrefLevel [Byte0]: 62
7881 18:11:50.021041 [Byte1]: 62
7882 18:11:50.025145
7883 18:11:50.025227 Set Vref, RX VrefLevel [Byte0]: 63
7884 18:11:50.028714 [Byte1]: 63
7885 18:11:50.032843
7886 18:11:50.032925 Set Vref, RX VrefLevel [Byte0]: 64
7887 18:11:50.036195 [Byte1]: 64
7888 18:11:50.040195
7889 18:11:50.040278 Set Vref, RX VrefLevel [Byte0]: 65
7890 18:11:50.043691 [Byte1]: 65
7891 18:11:50.048011
7892 18:11:50.048094 Set Vref, RX VrefLevel [Byte0]: 66
7893 18:11:50.051433 [Byte1]: 66
7894 18:11:50.055404
7895 18:11:50.055486 Set Vref, RX VrefLevel [Byte0]: 67
7896 18:11:50.058905 [Byte1]: 67
7897 18:11:50.063019
7898 18:11:50.063101 Set Vref, RX VrefLevel [Byte0]: 68
7899 18:11:50.066560 [Byte1]: 68
7900 18:11:50.070581
7901 18:11:50.070664 Set Vref, RX VrefLevel [Byte0]: 69
7902 18:11:50.073759 [Byte1]: 69
7903 18:11:50.078295
7904 18:11:50.078377 Set Vref, RX VrefLevel [Byte0]: 70
7905 18:11:50.081737 [Byte1]: 70
7906 18:11:50.085775
7907 18:11:50.085857 Set Vref, RX VrefLevel [Byte0]: 71
7908 18:11:50.089308 [Byte1]: 71
7909 18:11:50.093151
7910 18:11:50.093233 Set Vref, RX VrefLevel [Byte0]: 72
7911 18:11:50.096657 [Byte1]: 72
7912 18:11:50.101073
7913 18:11:50.101169 Set Vref, RX VrefLevel [Byte0]: 73
7914 18:11:50.104414 [Byte1]: 73
7915 18:11:50.108514
7916 18:11:50.108646 Set Vref, RX VrefLevel [Byte0]: 74
7917 18:11:50.112037 [Byte1]: 74
7918 18:11:50.116473
7919 18:11:50.116614 Set Vref, RX VrefLevel [Byte0]: 75
7920 18:11:50.119280 [Byte1]: 75
7921 18:11:50.123771
7922 18:11:50.123853 Set Vref, RX VrefLevel [Byte0]: 76
7923 18:11:50.127326 [Byte1]: 76
7924 18:11:50.131384
7925 18:11:50.131465 Set Vref, RX VrefLevel [Byte0]: 77
7926 18:11:50.134784 [Byte1]: 77
7927 18:11:50.138805
7928 18:11:50.138888 Set Vref, RX VrefLevel [Byte0]: 78
7929 18:11:50.141980 [Byte1]: 78
7930 18:11:50.146581
7931 18:11:50.146702 Set Vref, RX VrefLevel [Byte0]: 79
7932 18:11:50.149532 [Byte1]: 79
7933 18:11:50.154134
7934 18:11:50.154217 Final RX Vref Byte 0 = 63 to rank0
7935 18:11:50.157217 Final RX Vref Byte 1 = 61 to rank0
7936 18:11:50.160789 Final RX Vref Byte 0 = 63 to rank1
7937 18:11:50.163717 Final RX Vref Byte 1 = 61 to rank1==
7938 18:11:50.167377 Dram Type= 6, Freq= 0, CH_0, rank 0
7939 18:11:50.174007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 18:11:50.174092 ==
7941 18:11:50.174159 DQS Delay:
7942 18:11:50.174221 DQS0 = 0, DQS1 = 0
7943 18:11:50.177113 DQM Delay:
7944 18:11:50.177195 DQM0 = 136, DQM1 = 123
7945 18:11:50.180528 DQ Delay:
7946 18:11:50.183563 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7947 18:11:50.186918 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7948 18:11:50.190895 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7949 18:11:50.193835 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =130
7950 18:11:50.193918
7951 18:11:50.193984
7952 18:11:50.194045
7953 18:11:50.197369 [DramC_TX_OE_Calibration] TA2
7954 18:11:50.200312 Original DQ_B0 (3 6) =30, OEN = 27
7955 18:11:50.203747 Original DQ_B1 (3 6) =30, OEN = 27
7956 18:11:50.206987 24, 0x0, End_B0=24 End_B1=24
7957 18:11:50.207072 25, 0x0, End_B0=25 End_B1=25
7958 18:11:50.210465 26, 0x0, End_B0=26 End_B1=26
7959 18:11:50.213817 27, 0x0, End_B0=27 End_B1=27
7960 18:11:50.217104 28, 0x0, End_B0=28 End_B1=28
7961 18:11:50.220502 29, 0x0, End_B0=29 End_B1=29
7962 18:11:50.220625 30, 0x0, End_B0=30 End_B1=30
7963 18:11:50.223710 31, 0x4545, End_B0=30 End_B1=30
7964 18:11:50.227123 Byte0 end_step=30 best_step=27
7965 18:11:50.230301 Byte1 end_step=30 best_step=27
7966 18:11:50.233573 Byte0 TX OE(2T, 0.5T) = (3, 3)
7967 18:11:50.236884 Byte1 TX OE(2T, 0.5T) = (3, 3)
7968 18:11:50.236985
7969 18:11:50.237069
7970 18:11:50.243703 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7971 18:11:50.246704 CH0 RK0: MR19=303, MR18=1C1A
7972 18:11:50.253770 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7973 18:11:50.253850
7974 18:11:50.257108 ----->DramcWriteLeveling(PI) begin...
7975 18:11:50.257184 ==
7976 18:11:50.259988 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 18:11:50.263474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 18:11:50.263552 ==
7979 18:11:50.267067 Write leveling (Byte 0): 38 => 38
7980 18:11:50.269998 Write leveling (Byte 1): 28 => 28
7981 18:11:50.273587 DramcWriteLeveling(PI) end<-----
7982 18:11:50.273665
7983 18:11:50.273728 ==
7984 18:11:50.276980 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 18:11:50.280025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 18:11:50.280108 ==
7987 18:11:50.283669 [Gating] SW mode calibration
7988 18:11:50.290166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7989 18:11:50.296516 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7990 18:11:50.299957 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 18:11:50.303250 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 18:11:50.310107 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7993 18:11:50.313119 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
7994 18:11:50.316375 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 18:11:50.323111 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 18:11:50.326380 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 18:11:50.329703 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 18:11:50.336207 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 18:11:50.339815 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 18:11:50.343210 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 18:11:50.349886 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
8002 18:11:50.352990 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8003 18:11:50.356464 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 18:11:50.362898 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 18:11:50.366491 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 18:11:50.369420 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 18:11:50.376079 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 18:11:50.379682 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8009 18:11:50.383168 1 6 12 | B1->B0 | 2f2e 4343 | 1 1 | (0 0) (0 0)
8010 18:11:50.389820 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8011 18:11:50.392863 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 18:11:50.396240 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 18:11:50.402640 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 18:11:50.405914 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 18:11:50.409425 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 18:11:50.416103 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 18:11:50.419168 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8018 18:11:50.422507 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 18:11:50.429433 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 18:11:50.432654 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 18:11:50.436032 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 18:11:50.442792 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 18:11:50.446286 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 18:11:50.449293 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 18:11:50.452922 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 18:11:50.459373 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 18:11:50.462801 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 18:11:50.466050 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 18:11:50.472932 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 18:11:50.475848 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 18:11:50.479014 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 18:11:50.485769 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 18:11:50.489335 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 18:11:50.492515 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 18:11:50.495952 Total UI for P1: 0, mck2ui 16
8036 18:11:50.499396 best dqsien dly found for B0: ( 1, 9, 12)
8037 18:11:50.502816 Total UI for P1: 0, mck2ui 16
8038 18:11:50.505706 best dqsien dly found for B1: ( 1, 9, 14)
8039 18:11:50.509198 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8040 18:11:50.512480 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8041 18:11:50.512601
8042 18:11:50.519134 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8043 18:11:50.522459 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8044 18:11:50.525735 [Gating] SW calibration Done
8045 18:11:50.525819 ==
8046 18:11:50.529272 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 18:11:50.532489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 18:11:50.532629 ==
8049 18:11:50.532700 RX Vref Scan: 0
8050 18:11:50.532763
8051 18:11:50.535902 RX Vref 0 -> 0, step: 1
8052 18:11:50.535985
8053 18:11:50.539166 RX Delay 0 -> 252, step: 8
8054 18:11:50.542201 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8055 18:11:50.545827 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8056 18:11:50.552313 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8057 18:11:50.555501 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8058 18:11:50.559097 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8059 18:11:50.562162 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8060 18:11:50.565596 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8061 18:11:50.568896 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8062 18:11:50.575911 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8063 18:11:50.578864 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8064 18:11:50.582432 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8065 18:11:50.585448 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8066 18:11:50.591985 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8067 18:11:50.595437 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8068 18:11:50.598524 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8069 18:11:50.602104 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8070 18:11:50.602189 ==
8071 18:11:50.605464 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 18:11:50.608842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 18:11:50.612065 ==
8074 18:11:50.612149 DQS Delay:
8075 18:11:50.612215 DQS0 = 0, DQS1 = 0
8076 18:11:50.615464 DQM Delay:
8077 18:11:50.615547 DQM0 = 136, DQM1 = 125
8078 18:11:50.618722 DQ Delay:
8079 18:11:50.622111 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8080 18:11:50.625556 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8081 18:11:50.628734 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
8082 18:11:50.632175 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8083 18:11:50.632258
8084 18:11:50.632325
8085 18:11:50.632386 ==
8086 18:11:50.635537 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 18:11:50.638928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 18:11:50.639012 ==
8089 18:11:50.641778
8090 18:11:50.641861
8091 18:11:50.641927 TX Vref Scan disable
8092 18:11:50.645032 == TX Byte 0 ==
8093 18:11:50.648644 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8094 18:11:50.652204 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8095 18:11:50.655268 == TX Byte 1 ==
8096 18:11:50.658428 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8097 18:11:50.661955 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8098 18:11:50.662034 ==
8099 18:11:50.665071 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 18:11:50.671665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 18:11:50.671748 ==
8102 18:11:50.686065
8103 18:11:50.689077 TX Vref early break, caculate TX vref
8104 18:11:50.692558 TX Vref=16, minBit 0, minWin=23, winSum=387
8105 18:11:50.696215 TX Vref=18, minBit 12, minWin=23, winSum=397
8106 18:11:50.699306 TX Vref=20, minBit 3, minWin=24, winSum=405
8107 18:11:50.702764 TX Vref=22, minBit 8, minWin=24, winSum=410
8108 18:11:50.705806 TX Vref=24, minBit 2, minWin=25, winSum=417
8109 18:11:50.712542 TX Vref=26, minBit 0, minWin=26, winSum=428
8110 18:11:50.715630 TX Vref=28, minBit 0, minWin=26, winSum=428
8111 18:11:50.719053 TX Vref=30, minBit 0, minWin=26, winSum=425
8112 18:11:50.722409 TX Vref=32, minBit 13, minWin=25, winSum=420
8113 18:11:50.725826 TX Vref=34, minBit 0, minWin=25, winSum=409
8114 18:11:50.729376 TX Vref=36, minBit 2, minWin=24, winSum=404
8115 18:11:50.735987 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8116 18:11:50.736070
8117 18:11:50.738946 Final TX Range 0 Vref 26
8118 18:11:50.739028
8119 18:11:50.739094 ==
8120 18:11:50.742228 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 18:11:50.745530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 18:11:50.745612 ==
8123 18:11:50.745678
8124 18:11:50.748728
8125 18:11:50.748809 TX Vref Scan disable
8126 18:11:50.755952 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8127 18:11:50.756034 == TX Byte 0 ==
8128 18:11:50.758836 u2DelayCellOfst[0]=13 cells (4 PI)
8129 18:11:50.762450 u2DelayCellOfst[1]=20 cells (6 PI)
8130 18:11:50.765465 u2DelayCellOfst[2]=13 cells (4 PI)
8131 18:11:50.768991 u2DelayCellOfst[3]=13 cells (4 PI)
8132 18:11:50.771838 u2DelayCellOfst[4]=10 cells (3 PI)
8133 18:11:50.775529 u2DelayCellOfst[5]=0 cells (0 PI)
8134 18:11:50.778444 u2DelayCellOfst[6]=20 cells (6 PI)
8135 18:11:50.781828 u2DelayCellOfst[7]=20 cells (6 PI)
8136 18:11:50.785475 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8137 18:11:50.788493 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8138 18:11:50.792057 == TX Byte 1 ==
8139 18:11:50.795199 u2DelayCellOfst[8]=0 cells (0 PI)
8140 18:11:50.798768 u2DelayCellOfst[9]=3 cells (1 PI)
8141 18:11:50.801737 u2DelayCellOfst[10]=6 cells (2 PI)
8142 18:11:50.804930 u2DelayCellOfst[11]=3 cells (1 PI)
8143 18:11:50.808530 u2DelayCellOfst[12]=10 cells (3 PI)
8144 18:11:50.811793 u2DelayCellOfst[13]=10 cells (3 PI)
8145 18:11:50.811876 u2DelayCellOfst[14]=13 cells (4 PI)
8146 18:11:50.815355 u2DelayCellOfst[15]=10 cells (3 PI)
8147 18:11:50.821763 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8148 18:11:50.825230 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8149 18:11:50.828659 DramC Write-DBI on
8150 18:11:50.828742 ==
8151 18:11:50.831578 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 18:11:50.835056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 18:11:50.835140 ==
8154 18:11:50.835206
8155 18:11:50.835267
8156 18:11:50.838347 TX Vref Scan disable
8157 18:11:50.838429 == TX Byte 0 ==
8158 18:11:50.844498 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8159 18:11:50.844603 == TX Byte 1 ==
8160 18:11:50.848022 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8161 18:11:50.851492 DramC Write-DBI off
8162 18:11:50.851574
8163 18:11:50.851641 [DATLAT]
8164 18:11:50.855006 Freq=1600, CH0 RK1
8165 18:11:50.855089
8166 18:11:50.855155 DATLAT Default: 0xf
8167 18:11:50.857969 0, 0xFFFF, sum = 0
8168 18:11:50.858053 1, 0xFFFF, sum = 0
8169 18:11:50.861455 2, 0xFFFF, sum = 0
8170 18:11:50.864500 3, 0xFFFF, sum = 0
8171 18:11:50.864637 4, 0xFFFF, sum = 0
8172 18:11:50.868087 5, 0xFFFF, sum = 0
8173 18:11:50.868170 6, 0xFFFF, sum = 0
8174 18:11:50.871211 7, 0xFFFF, sum = 0
8175 18:11:50.871295 8, 0xFFFF, sum = 0
8176 18:11:50.874996 9, 0xFFFF, sum = 0
8177 18:11:50.875080 10, 0xFFFF, sum = 0
8178 18:11:50.877807 11, 0xFFFF, sum = 0
8179 18:11:50.877891 12, 0xFFFF, sum = 0
8180 18:11:50.881308 13, 0xFFFF, sum = 0
8181 18:11:50.881392 14, 0x0, sum = 1
8182 18:11:50.884667 15, 0x0, sum = 2
8183 18:11:50.884751 16, 0x0, sum = 3
8184 18:11:50.887744 17, 0x0, sum = 4
8185 18:11:50.887827 best_step = 15
8186 18:11:50.887910
8187 18:11:50.887973 ==
8188 18:11:50.891310 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 18:11:50.894790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 18:11:50.897845 ==
8191 18:11:50.897927 RX Vref Scan: 0
8192 18:11:50.897993
8193 18:11:50.901475 RX Vref 0 -> 0, step: 1
8194 18:11:50.901557
8195 18:11:50.904478 RX Delay 19 -> 252, step: 4
8196 18:11:50.907992 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8197 18:11:50.910991 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8198 18:11:50.914385 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8199 18:11:50.921418 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8200 18:11:50.924333 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8201 18:11:50.927705 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8202 18:11:50.931136 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8203 18:11:50.934150 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8204 18:11:50.940868 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8205 18:11:50.944119 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8206 18:11:50.947705 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8207 18:11:50.950857 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8208 18:11:50.954282 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8209 18:11:50.960636 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8210 18:11:50.964071 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8211 18:11:50.967814 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8212 18:11:50.967897 ==
8213 18:11:50.970799 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 18:11:50.974311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 18:11:50.974394 ==
8216 18:11:50.977259 DQS Delay:
8217 18:11:50.977341 DQS0 = 0, DQS1 = 0
8218 18:11:50.980894 DQM Delay:
8219 18:11:50.980976 DQM0 = 132, DQM1 = 123
8220 18:11:50.981042 DQ Delay:
8221 18:11:50.987340 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =128
8222 18:11:50.990706 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8223 18:11:50.994098 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8224 18:11:50.997171 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8225 18:11:50.997254
8226 18:11:50.997319
8227 18:11:50.997381
8228 18:11:51.000796 [DramC_TX_OE_Calibration] TA2
8229 18:11:51.003779 Original DQ_B0 (3 6) =30, OEN = 27
8230 18:11:51.007270 Original DQ_B1 (3 6) =30, OEN = 27
8231 18:11:51.007353 24, 0x0, End_B0=24 End_B1=24
8232 18:11:51.010872 25, 0x0, End_B0=25 End_B1=25
8233 18:11:51.013807 26, 0x0, End_B0=26 End_B1=26
8234 18:11:51.017191 27, 0x0, End_B0=27 End_B1=27
8235 18:11:51.020743 28, 0x0, End_B0=28 End_B1=28
8236 18:11:51.020837 29, 0x0, End_B0=29 End_B1=29
8237 18:11:51.024144 30, 0x0, End_B0=30 End_B1=30
8238 18:11:51.027013 31, 0x4141, End_B0=30 End_B1=30
8239 18:11:51.030511 Byte0 end_step=30 best_step=27
8240 18:11:51.034022 Byte1 end_step=30 best_step=27
8241 18:11:51.034106 Byte0 TX OE(2T, 0.5T) = (3, 3)
8242 18:11:51.037375 Byte1 TX OE(2T, 0.5T) = (3, 3)
8243 18:11:51.037460
8244 18:11:51.037525
8245 18:11:51.047123 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps
8246 18:11:51.050478 CH0 RK1: MR19=303, MR18=1E0B
8247 18:11:51.053779 CH0_RK1: MR19=0x303, MR18=0x1E0B, DQSOSC=394, MR23=63, INC=23, DEC=15
8248 18:11:51.056738 [RxdqsGatingPostProcess] freq 1600
8249 18:11:51.063631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8250 18:11:51.067171 best DQS0 dly(2T, 0.5T) = (1, 1)
8251 18:11:51.070169 best DQS1 dly(2T, 0.5T) = (1, 1)
8252 18:11:51.073810 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8253 18:11:51.076837 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8254 18:11:51.080336 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 18:11:51.083744 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 18:11:51.086824 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 18:11:51.086910 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 18:11:51.090335 Pre-setting of DQS Precalculation
8259 18:11:51.096931 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8260 18:11:51.097016 ==
8261 18:11:51.100426 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 18:11:51.103491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 18:11:51.103579 ==
8264 18:11:51.110075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 18:11:51.113796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 18:11:51.117171 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 18:11:51.123599 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 18:11:51.133030 [CA 0] Center 42 (12~72) winsize 61
8269 18:11:51.135909 [CA 1] Center 42 (12~72) winsize 61
8270 18:11:51.139414 [CA 2] Center 38 (9~68) winsize 60
8271 18:11:51.142762 [CA 3] Center 37 (8~67) winsize 60
8272 18:11:51.146111 [CA 4] Center 37 (8~67) winsize 60
8273 18:11:51.149313 [CA 5] Center 37 (7~67) winsize 61
8274 18:11:51.149396
8275 18:11:51.152885 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8276 18:11:51.152968
8277 18:11:51.156216 [CATrainingPosCal] consider 1 rank data
8278 18:11:51.159573 u2DelayCellTimex100 = 290/100 ps
8279 18:11:51.163136 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8280 18:11:51.169641 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8281 18:11:51.172938 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8282 18:11:51.176484 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8283 18:11:51.179539 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8284 18:11:51.182949 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8285 18:11:51.183084
8286 18:11:51.186029 CA PerBit enable=1, Macro0, CA PI delay=37
8287 18:11:51.186112
8288 18:11:51.189408 [CBTSetCACLKResult] CA Dly = 37
8289 18:11:51.189490 CS Dly: 9 (0~40)
8290 18:11:51.195946 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 18:11:51.199699 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 18:11:51.199797 ==
8293 18:11:51.202643 Dram Type= 6, Freq= 0, CH_1, rank 1
8294 18:11:51.206074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 18:11:51.206157 ==
8296 18:11:51.212832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 18:11:51.215836 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 18:11:51.222449 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 18:11:51.225896 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 18:11:51.236138 [CA 0] Center 42 (13~72) winsize 60
8301 18:11:51.239118 [CA 1] Center 42 (12~72) winsize 61
8302 18:11:51.242738 [CA 2] Center 37 (8~67) winsize 60
8303 18:11:51.245574 [CA 3] Center 37 (8~66) winsize 59
8304 18:11:51.249324 [CA 4] Center 37 (8~66) winsize 59
8305 18:11:51.252720 [CA 5] Center 36 (7~66) winsize 60
8306 18:11:51.252802
8307 18:11:51.255607 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 18:11:51.255687
8309 18:11:51.258991 [CATrainingPosCal] consider 2 rank data
8310 18:11:51.262447 u2DelayCellTimex100 = 290/100 ps
8311 18:11:51.269113 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
8312 18:11:51.272513 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8313 18:11:51.275469 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8314 18:11:51.279107 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8315 18:11:51.282598 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8316 18:11:51.285559 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8317 18:11:51.285639
8318 18:11:51.289158 CA PerBit enable=1, Macro0, CA PI delay=36
8319 18:11:51.289239
8320 18:11:51.292075 [CBTSetCACLKResult] CA Dly = 36
8321 18:11:51.295852 CS Dly: 9 (0~41)
8322 18:11:51.298756 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 18:11:51.302237 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 18:11:51.302318
8325 18:11:51.305301 ----->DramcWriteLeveling(PI) begin...
8326 18:11:51.305382 ==
8327 18:11:51.308963 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 18:11:51.312497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 18:11:51.315565 ==
8330 18:11:51.315645 Write leveling (Byte 0): 25 => 25
8331 18:11:51.318988 Write leveling (Byte 1): 28 => 28
8332 18:11:51.322204 DramcWriteLeveling(PI) end<-----
8333 18:11:51.322285
8334 18:11:51.322349 ==
8335 18:11:51.325636 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 18:11:51.332062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 18:11:51.332142 ==
8338 18:11:51.335490 [Gating] SW mode calibration
8339 18:11:51.341833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8340 18:11:51.345266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8341 18:11:51.351777 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 18:11:51.355197 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 18:11:51.358506 1 4 8 | B1->B0 | 3030 3232 | 0 1 | (0 0) (1 1)
8344 18:11:51.365326 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 18:11:51.368365 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 18:11:51.371810 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 18:11:51.378549 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 18:11:51.381702 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 18:11:51.385224 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 18:11:51.391822 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8351 18:11:51.394833 1 5 8 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
8352 18:11:51.398450 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8353 18:11:51.404775 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 18:11:51.408268 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 18:11:51.411750 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 18:11:51.415047 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 18:11:51.421620 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 18:11:51.424777 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 18:11:51.428418 1 6 8 | B1->B0 | 3c3c 4343 | 0 1 | (0 0) (0 0)
8360 18:11:51.435032 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 18:11:51.438281 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 18:11:51.441560 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 18:11:51.447890 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 18:11:51.451430 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 18:11:51.454910 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 18:11:51.461258 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 18:11:51.464698 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8368 18:11:51.468152 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 18:11:51.474689 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 18:11:51.477930 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 18:11:51.481430 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 18:11:51.488029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 18:11:51.491094 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 18:11:51.494583 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 18:11:51.501014 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 18:11:51.504605 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 18:11:51.507577 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 18:11:51.514543 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 18:11:51.517942 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 18:11:51.521665 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 18:11:51.527704 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 18:11:51.531264 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8383 18:11:51.534722 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 18:11:51.537830 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8385 18:11:51.541268 Total UI for P1: 0, mck2ui 16
8386 18:11:51.544452 best dqsien dly found for B0: ( 1, 9, 6)
8387 18:11:51.551249 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 18:11:51.554263 Total UI for P1: 0, mck2ui 16
8389 18:11:51.557934 best dqsien dly found for B1: ( 1, 9, 10)
8390 18:11:51.561004 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8391 18:11:51.564397 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8392 18:11:51.564482
8393 18:11:51.567763 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8394 18:11:51.571156 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8395 18:11:51.574461 [Gating] SW calibration Done
8396 18:11:51.574544 ==
8397 18:11:51.577945 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 18:11:51.580908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 18:11:51.580993 ==
8400 18:11:51.584195 RX Vref Scan: 0
8401 18:11:51.584277
8402 18:11:51.587691 RX Vref 0 -> 0, step: 1
8403 18:11:51.587775
8404 18:11:51.587841 RX Delay 0 -> 252, step: 8
8405 18:11:51.590793 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8406 18:11:51.597892 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8407 18:11:51.600938 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8408 18:11:51.604517 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8409 18:11:51.607655 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8410 18:11:51.611278 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8411 18:11:51.617765 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8412 18:11:51.620925 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8413 18:11:51.624037 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8414 18:11:51.627618 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8415 18:11:51.630574 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8416 18:11:51.637661 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8417 18:11:51.640680 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8418 18:11:51.644120 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8419 18:11:51.647643 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8420 18:11:51.653938 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8421 18:11:51.654033 ==
8422 18:11:51.657455 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 18:11:51.660908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 18:11:51.661000 ==
8425 18:11:51.661068 DQS Delay:
8426 18:11:51.663788 DQS0 = 0, DQS1 = 0
8427 18:11:51.663871 DQM Delay:
8428 18:11:51.667236 DQM0 = 136, DQM1 = 130
8429 18:11:51.667319 DQ Delay:
8430 18:11:51.670400 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8431 18:11:51.673665 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8432 18:11:51.677044 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8433 18:11:51.680448 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8434 18:11:51.680532
8435 18:11:51.680640
8436 18:11:51.683881 ==
8437 18:11:51.683965 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 18:11:51.690300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 18:11:51.690385 ==
8440 18:11:51.690451
8441 18:11:51.690510
8442 18:11:51.693564 TX Vref Scan disable
8443 18:11:51.693647 == TX Byte 0 ==
8444 18:11:51.696987 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8445 18:11:51.703569 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8446 18:11:51.703658 == TX Byte 1 ==
8447 18:11:51.707163 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8448 18:11:51.713824 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8449 18:11:51.713908 ==
8450 18:11:51.716592 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 18:11:51.719938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 18:11:51.720022 ==
8453 18:11:51.732773
8454 18:11:51.736257 TX Vref early break, caculate TX vref
8455 18:11:51.739894 TX Vref=16, minBit 10, minWin=21, winSum=369
8456 18:11:51.742817 TX Vref=18, minBit 10, minWin=21, winSum=378
8457 18:11:51.746435 TX Vref=20, minBit 8, minWin=23, winSum=388
8458 18:11:51.749316 TX Vref=22, minBit 10, minWin=22, winSum=395
8459 18:11:51.752750 TX Vref=24, minBit 8, minWin=24, winSum=408
8460 18:11:51.759714 TX Vref=26, minBit 10, minWin=24, winSum=412
8461 18:11:51.763032 TX Vref=28, minBit 10, minWin=25, winSum=420
8462 18:11:51.765882 TX Vref=30, minBit 9, minWin=23, winSum=412
8463 18:11:51.769316 TX Vref=32, minBit 9, minWin=23, winSum=400
8464 18:11:51.772774 TX Vref=34, minBit 9, minWin=23, winSum=395
8465 18:11:51.779250 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28
8466 18:11:51.779334
8467 18:11:51.782557 Final TX Range 0 Vref 28
8468 18:11:51.782642
8469 18:11:51.782708 ==
8470 18:11:51.786050 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 18:11:51.789147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 18:11:51.789231 ==
8473 18:11:51.789297
8474 18:11:51.789361
8475 18:11:51.792811 TX Vref Scan disable
8476 18:11:51.799430 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8477 18:11:51.799514 == TX Byte 0 ==
8478 18:11:51.802717 u2DelayCellOfst[0]=16 cells (5 PI)
8479 18:11:51.805832 u2DelayCellOfst[1]=10 cells (3 PI)
8480 18:11:51.809393 u2DelayCellOfst[2]=0 cells (0 PI)
8481 18:11:51.812779 u2DelayCellOfst[3]=6 cells (2 PI)
8482 18:11:51.815684 u2DelayCellOfst[4]=6 cells (2 PI)
8483 18:11:51.819333 u2DelayCellOfst[5]=16 cells (5 PI)
8484 18:11:51.822789 u2DelayCellOfst[6]=16 cells (5 PI)
8485 18:11:51.825780 u2DelayCellOfst[7]=3 cells (1 PI)
8486 18:11:51.829313 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8487 18:11:51.832315 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8488 18:11:51.835849 == TX Byte 1 ==
8489 18:11:51.839427 u2DelayCellOfst[8]=0 cells (0 PI)
8490 18:11:51.839511 u2DelayCellOfst[9]=3 cells (1 PI)
8491 18:11:51.842544 u2DelayCellOfst[10]=13 cells (4 PI)
8492 18:11:51.846002 u2DelayCellOfst[11]=3 cells (1 PI)
8493 18:11:51.849010 u2DelayCellOfst[12]=16 cells (5 PI)
8494 18:11:51.852431 u2DelayCellOfst[13]=16 cells (5 PI)
8495 18:11:51.855867 u2DelayCellOfst[14]=16 cells (5 PI)
8496 18:11:51.858916 u2DelayCellOfst[15]=20 cells (6 PI)
8497 18:11:51.862338 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8498 18:11:51.868722 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 18:11:51.868805 DramC Write-DBI on
8500 18:11:51.868871 ==
8501 18:11:51.872242 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 18:11:51.879138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 18:11:51.879223 ==
8504 18:11:51.879288
8505 18:11:51.879349
8506 18:11:51.879408 TX Vref Scan disable
8507 18:11:51.882673 == TX Byte 0 ==
8508 18:11:51.886223 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8509 18:11:51.889128 == TX Byte 1 ==
8510 18:11:51.892608 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 18:11:51.895939 DramC Write-DBI off
8512 18:11:51.896021
8513 18:11:51.896087 [DATLAT]
8514 18:11:51.896147 Freq=1600, CH1 RK0
8515 18:11:51.896206
8516 18:11:51.899349 DATLAT Default: 0xf
8517 18:11:51.899432 0, 0xFFFF, sum = 0
8518 18:11:51.902386 1, 0xFFFF, sum = 0
8519 18:11:51.905886 2, 0xFFFF, sum = 0
8520 18:11:51.905969 3, 0xFFFF, sum = 0
8521 18:11:51.908977 4, 0xFFFF, sum = 0
8522 18:11:51.909060 5, 0xFFFF, sum = 0
8523 18:11:51.912423 6, 0xFFFF, sum = 0
8524 18:11:51.912538 7, 0xFFFF, sum = 0
8525 18:11:51.915953 8, 0xFFFF, sum = 0
8526 18:11:51.916036 9, 0xFFFF, sum = 0
8527 18:11:51.918975 10, 0xFFFF, sum = 0
8528 18:11:51.919058 11, 0xFFFF, sum = 0
8529 18:11:51.922534 12, 0xFFFF, sum = 0
8530 18:11:51.922617 13, 0xFFFF, sum = 0
8531 18:11:51.925578 14, 0x0, sum = 1
8532 18:11:51.925661 15, 0x0, sum = 2
8533 18:11:51.929032 16, 0x0, sum = 3
8534 18:11:51.929114 17, 0x0, sum = 4
8535 18:11:51.932101 best_step = 15
8536 18:11:51.932182
8537 18:11:51.932247 ==
8538 18:11:51.935556 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 18:11:51.938984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 18:11:51.939066 ==
8541 18:11:51.942063 RX Vref Scan: 1
8542 18:11:51.942144
8543 18:11:51.942210 Set Vref Range= 24 -> 127
8544 18:11:51.942270
8545 18:11:51.945716 RX Vref 24 -> 127, step: 1
8546 18:11:51.945797
8547 18:11:51.948718 RX Delay 19 -> 252, step: 4
8548 18:11:51.948799
8549 18:11:51.952045 Set Vref, RX VrefLevel [Byte0]: 24
8550 18:11:51.955630 [Byte1]: 24
8551 18:11:51.955711
8552 18:11:51.958659 Set Vref, RX VrefLevel [Byte0]: 25
8553 18:11:51.961970 [Byte1]: 25
8554 18:11:51.965570
8555 18:11:51.965652 Set Vref, RX VrefLevel [Byte0]: 26
8556 18:11:51.968566 [Byte1]: 26
8557 18:11:51.972948
8558 18:11:51.973057 Set Vref, RX VrefLevel [Byte0]: 27
8559 18:11:51.976205 [Byte1]: 27
8560 18:11:51.980494
8561 18:11:51.980612 Set Vref, RX VrefLevel [Byte0]: 28
8562 18:11:51.983900 [Byte1]: 28
8563 18:11:51.988104
8564 18:11:51.988213 Set Vref, RX VrefLevel [Byte0]: 29
8565 18:11:51.991425 [Byte1]: 29
8566 18:11:51.995423
8567 18:11:51.995506 Set Vref, RX VrefLevel [Byte0]: 30
8568 18:11:51.998860 [Byte1]: 30
8569 18:11:52.003091
8570 18:11:52.003175 Set Vref, RX VrefLevel [Byte0]: 31
8571 18:11:52.006723 [Byte1]: 31
8572 18:11:52.010662
8573 18:11:52.010796 Set Vref, RX VrefLevel [Byte0]: 32
8574 18:11:52.014252 [Byte1]: 32
8575 18:11:52.018153
8576 18:11:52.018235 Set Vref, RX VrefLevel [Byte0]: 33
8577 18:11:52.021830 [Byte1]: 33
8578 18:11:52.025785
8579 18:11:52.025867 Set Vref, RX VrefLevel [Byte0]: 34
8580 18:11:52.029332 [Byte1]: 34
8581 18:11:52.033718
8582 18:11:52.033800 Set Vref, RX VrefLevel [Byte0]: 35
8583 18:11:52.036831 [Byte1]: 35
8584 18:11:52.040871
8585 18:11:52.040953 Set Vref, RX VrefLevel [Byte0]: 36
8586 18:11:52.044290 [Byte1]: 36
8587 18:11:52.048873
8588 18:11:52.048955 Set Vref, RX VrefLevel [Byte0]: 37
8589 18:11:52.051872 [Byte1]: 37
8590 18:11:52.056424
8591 18:11:52.056506 Set Vref, RX VrefLevel [Byte0]: 38
8592 18:11:52.059815 [Byte1]: 38
8593 18:11:52.063781
8594 18:11:52.063863 Set Vref, RX VrefLevel [Byte0]: 39
8595 18:11:52.067112 [Byte1]: 39
8596 18:11:52.071513
8597 18:11:52.071596 Set Vref, RX VrefLevel [Byte0]: 40
8598 18:11:52.074570 [Byte1]: 40
8599 18:11:52.078955
8600 18:11:52.079038 Set Vref, RX VrefLevel [Byte0]: 41
8601 18:11:52.082373 [Byte1]: 41
8602 18:11:52.086322
8603 18:11:52.089710 Set Vref, RX VrefLevel [Byte0]: 42
8604 18:11:52.093186 [Byte1]: 42
8605 18:11:52.093269
8606 18:11:52.096458 Set Vref, RX VrefLevel [Byte0]: 43
8607 18:11:52.099889 [Byte1]: 43
8608 18:11:52.099998
8609 18:11:52.102823 Set Vref, RX VrefLevel [Byte0]: 44
8610 18:11:52.106520 [Byte1]: 44
8611 18:11:52.106604
8612 18:11:52.109460 Set Vref, RX VrefLevel [Byte0]: 45
8613 18:11:52.112985 [Byte1]: 45
8614 18:11:52.116970
8615 18:11:52.117053 Set Vref, RX VrefLevel [Byte0]: 46
8616 18:11:52.120107 [Byte1]: 46
8617 18:11:52.124259
8618 18:11:52.124343 Set Vref, RX VrefLevel [Byte0]: 47
8619 18:11:52.127806 [Byte1]: 47
8620 18:11:52.131877
8621 18:11:52.131960 Set Vref, RX VrefLevel [Byte0]: 48
8622 18:11:52.135292 [Byte1]: 48
8623 18:11:52.139777
8624 18:11:52.139860 Set Vref, RX VrefLevel [Byte0]: 49
8625 18:11:52.142839 [Byte1]: 49
8626 18:11:52.147104
8627 18:11:52.147188 Set Vref, RX VrefLevel [Byte0]: 50
8628 18:11:52.150540 [Byte1]: 50
8629 18:11:52.154522
8630 18:11:52.154604 Set Vref, RX VrefLevel [Byte0]: 51
8631 18:11:52.157881 [Byte1]: 51
8632 18:11:52.162359
8633 18:11:52.162443 Set Vref, RX VrefLevel [Byte0]: 52
8634 18:11:52.165448 [Byte1]: 52
8635 18:11:52.170126
8636 18:11:52.170209 Set Vref, RX VrefLevel [Byte0]: 53
8637 18:11:52.172963 [Byte1]: 53
8638 18:11:52.177428
8639 18:11:52.177514 Set Vref, RX VrefLevel [Byte0]: 54
8640 18:11:52.180815 [Byte1]: 54
8641 18:11:52.185106
8642 18:11:52.185189 Set Vref, RX VrefLevel [Byte0]: 55
8643 18:11:52.188133 [Byte1]: 55
8644 18:11:52.192585
8645 18:11:52.192668 Set Vref, RX VrefLevel [Byte0]: 56
8646 18:11:52.195598 [Byte1]: 56
8647 18:11:52.200016
8648 18:11:52.200099 Set Vref, RX VrefLevel [Byte0]: 57
8649 18:11:52.203476 [Byte1]: 57
8650 18:11:52.207737
8651 18:11:52.207821 Set Vref, RX VrefLevel [Byte0]: 58
8652 18:11:52.211212 [Byte1]: 58
8653 18:11:52.215240
8654 18:11:52.215323 Set Vref, RX VrefLevel [Byte0]: 59
8655 18:11:52.221563 [Byte1]: 59
8656 18:11:52.221647
8657 18:11:52.225198 Set Vref, RX VrefLevel [Byte0]: 60
8658 18:11:52.227988 [Byte1]: 60
8659 18:11:52.228089
8660 18:11:52.231541 Set Vref, RX VrefLevel [Byte0]: 61
8661 18:11:52.235065 [Byte1]: 61
8662 18:11:52.235148
8663 18:11:52.238038 Set Vref, RX VrefLevel [Byte0]: 62
8664 18:11:52.241478 [Byte1]: 62
8665 18:11:52.245465
8666 18:11:52.245551 Set Vref, RX VrefLevel [Byte0]: 63
8667 18:11:52.249149 [Byte1]: 63
8668 18:11:52.253161
8669 18:11:52.253245 Set Vref, RX VrefLevel [Byte0]: 64
8670 18:11:52.256252 [Byte1]: 64
8671 18:11:52.260714
8672 18:11:52.260799 Set Vref, RX VrefLevel [Byte0]: 65
8673 18:11:52.264228 [Byte1]: 65
8674 18:11:52.268240
8675 18:11:52.268326 Set Vref, RX VrefLevel [Byte0]: 66
8676 18:11:52.271901 [Byte1]: 66
8677 18:11:52.275862
8678 18:11:52.275948 Set Vref, RX VrefLevel [Byte0]: 67
8679 18:11:52.279281 [Byte1]: 67
8680 18:11:52.283616
8681 18:11:52.283699 Set Vref, RX VrefLevel [Byte0]: 68
8682 18:11:52.286700 [Byte1]: 68
8683 18:11:52.291060
8684 18:11:52.291175 Set Vref, RX VrefLevel [Byte0]: 69
8685 18:11:52.294117 [Byte1]: 69
8686 18:11:52.298359
8687 18:11:52.298441 Set Vref, RX VrefLevel [Byte0]: 70
8688 18:11:52.302163 [Byte1]: 70
8689 18:11:52.306018
8690 18:11:52.306102 Set Vref, RX VrefLevel [Byte0]: 71
8691 18:11:52.309469 [Byte1]: 71
8692 18:11:52.313815
8693 18:11:52.313897 Set Vref, RX VrefLevel [Byte0]: 72
8694 18:11:52.317271 [Byte1]: 72
8695 18:11:52.321335
8696 18:11:52.321417 Set Vref, RX VrefLevel [Byte0]: 73
8697 18:11:52.324815 [Byte1]: 73
8698 18:11:52.328958
8699 18:11:52.329040 Set Vref, RX VrefLevel [Byte0]: 74
8700 18:11:52.332059 [Byte1]: 74
8701 18:11:52.336678
8702 18:11:52.336759 Set Vref, RX VrefLevel [Byte0]: 75
8703 18:11:52.339674 [Byte1]: 75
8704 18:11:52.344163
8705 18:11:52.344246 Set Vref, RX VrefLevel [Byte0]: 76
8706 18:11:52.347089 [Byte1]: 76
8707 18:11:52.351819
8708 18:11:52.351901 Set Vref, RX VrefLevel [Byte0]: 77
8709 18:11:52.354847 [Byte1]: 77
8710 18:11:52.359317
8711 18:11:52.359398 Final RX Vref Byte 0 = 61 to rank0
8712 18:11:52.362327 Final RX Vref Byte 1 = 62 to rank0
8713 18:11:52.365878 Final RX Vref Byte 0 = 61 to rank1
8714 18:11:52.368849 Final RX Vref Byte 1 = 62 to rank1==
8715 18:11:52.372517 Dram Type= 6, Freq= 0, CH_1, rank 0
8716 18:11:52.379099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 18:11:52.379182 ==
8718 18:11:52.379248 DQS Delay:
8719 18:11:52.379308 DQS0 = 0, DQS1 = 0
8720 18:11:52.382509 DQM Delay:
8721 18:11:52.382590 DQM0 = 134, DQM1 = 129
8722 18:11:52.385568 DQ Delay:
8723 18:11:52.388992 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =132
8724 18:11:52.392161 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8725 18:11:52.395838 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =124
8726 18:11:52.398983 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8727 18:11:52.399066
8728 18:11:52.399131
8729 18:11:52.399191
8730 18:11:52.402117 [DramC_TX_OE_Calibration] TA2
8731 18:11:52.405617 Original DQ_B0 (3 6) =30, OEN = 27
8732 18:11:52.408925 Original DQ_B1 (3 6) =30, OEN = 27
8733 18:11:52.412238 24, 0x0, End_B0=24 End_B1=24
8734 18:11:52.412323 25, 0x0, End_B0=25 End_B1=25
8735 18:11:52.415639 26, 0x0, End_B0=26 End_B1=26
8736 18:11:52.418643 27, 0x0, End_B0=27 End_B1=27
8737 18:11:52.421972 28, 0x0, End_B0=28 End_B1=28
8738 18:11:52.425450 29, 0x0, End_B0=29 End_B1=29
8739 18:11:52.425536 30, 0x0, End_B0=30 End_B1=30
8740 18:11:52.428489 31, 0x4545, End_B0=30 End_B1=30
8741 18:11:52.431979 Byte0 end_step=30 best_step=27
8742 18:11:52.435537 Byte1 end_step=30 best_step=27
8743 18:11:52.438463 Byte0 TX OE(2T, 0.5T) = (3, 3)
8744 18:11:52.441951 Byte1 TX OE(2T, 0.5T) = (3, 3)
8745 18:11:52.442035
8746 18:11:52.442102
8747 18:11:52.448889 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8748 18:11:52.451920 CH1 RK0: MR19=303, MR18=1826
8749 18:11:52.458601 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8750 18:11:52.458686
8751 18:11:52.461873 ----->DramcWriteLeveling(PI) begin...
8752 18:11:52.461959 ==
8753 18:11:52.465504 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 18:11:52.468469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 18:11:52.468583 ==
8756 18:11:52.472093 Write leveling (Byte 0): 27 => 27
8757 18:11:52.475566 Write leveling (Byte 1): 29 => 29
8758 18:11:52.478672 DramcWriteLeveling(PI) end<-----
8759 18:11:52.478756
8760 18:11:52.478822 ==
8761 18:11:52.482215 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 18:11:52.485206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 18:11:52.485291 ==
8764 18:11:52.488813 [Gating] SW mode calibration
8765 18:11:52.495339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8766 18:11:52.502221 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8767 18:11:52.505074 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 18:11:52.508521 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 18:11:52.515512 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8770 18:11:52.518409 1 4 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8771 18:11:52.521584 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 18:11:52.528674 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 18:11:52.531691 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 18:11:52.534871 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 18:11:52.541864 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 18:11:52.544842 1 5 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8777 18:11:52.548417 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
8778 18:11:52.554728 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8779 18:11:52.558356 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 18:11:52.561330 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 18:11:52.568214 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 18:11:52.571307 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 18:11:52.575136 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 18:11:52.581209 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8785 18:11:52.584578 1 6 8 | B1->B0 | 4242 2323 | 1 0 | (0 0) (0 0)
8786 18:11:52.588028 1 6 12 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
8787 18:11:52.594588 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 18:11:52.597593 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 18:11:52.601002 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 18:11:52.607617 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 18:11:52.610816 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 18:11:52.614440 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 18:11:52.620985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8794 18:11:52.624077 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8795 18:11:52.627434 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8796 18:11:52.633908 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 18:11:52.637635 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 18:11:52.640728 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 18:11:52.647336 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 18:11:52.650506 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 18:11:52.654071 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 18:11:52.660512 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 18:11:52.664014 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 18:11:52.666886 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 18:11:52.673570 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 18:11:52.677117 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 18:11:52.680195 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 18:11:52.686836 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8809 18:11:52.690186 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8810 18:11:52.693879 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8811 18:11:52.700334 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 18:11:52.700417 Total UI for P1: 0, mck2ui 16
8813 18:11:52.706782 best dqsien dly found for B0: ( 1, 9, 8)
8814 18:11:52.706869 Total UI for P1: 0, mck2ui 16
8815 18:11:52.713281 best dqsien dly found for B1: ( 1, 9, 8)
8816 18:11:52.716335 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8817 18:11:52.720066 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8818 18:11:52.720152
8819 18:11:52.723176 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8820 18:11:52.726429 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8821 18:11:52.730127 [Gating] SW calibration Done
8822 18:11:52.730211 ==
8823 18:11:52.733431 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 18:11:52.736703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 18:11:52.736788 ==
8826 18:11:52.740118 RX Vref Scan: 0
8827 18:11:52.740208
8828 18:11:52.740276 RX Vref 0 -> 0, step: 1
8829 18:11:52.740340
8830 18:11:52.743153 RX Delay 0 -> 252, step: 8
8831 18:11:52.746127 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8832 18:11:52.753227 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8833 18:11:52.756223 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8834 18:11:52.759646 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8835 18:11:52.763125 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8836 18:11:52.766264 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8837 18:11:52.772786 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8838 18:11:52.776300 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8839 18:11:52.779382 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8840 18:11:52.782823 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8841 18:11:52.786414 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8842 18:11:52.792821 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8843 18:11:52.795837 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8844 18:11:52.799538 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8845 18:11:52.802543 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8846 18:11:52.806038 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8847 18:11:52.809520 ==
8848 18:11:52.812537 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 18:11:52.816123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 18:11:52.816209 ==
8851 18:11:52.816276 DQS Delay:
8852 18:11:52.819050 DQS0 = 0, DQS1 = 0
8853 18:11:52.819135 DQM Delay:
8854 18:11:52.822482 DQM0 = 136, DQM1 = 132
8855 18:11:52.822566 DQ Delay:
8856 18:11:52.825856 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8857 18:11:52.829402 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8858 18:11:52.832473 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8859 18:11:52.835678 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8860 18:11:52.835762
8861 18:11:52.835829
8862 18:11:52.838978 ==
8863 18:11:52.839063 Dram Type= 6, Freq= 0, CH_1, rank 1
8864 18:11:52.845495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8865 18:11:52.845582 ==
8866 18:11:52.845650
8867 18:11:52.845711
8868 18:11:52.849159 TX Vref Scan disable
8869 18:11:52.849243 == TX Byte 0 ==
8870 18:11:52.852212 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8871 18:11:52.858762 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8872 18:11:52.858846 == TX Byte 1 ==
8873 18:11:52.862447 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8874 18:11:52.868776 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8875 18:11:52.868861 ==
8876 18:11:52.871978 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 18:11:52.875679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 18:11:52.875765 ==
8879 18:11:52.888183
8880 18:11:52.891784 TX Vref early break, caculate TX vref
8881 18:11:52.895319 TX Vref=16, minBit 9, minWin=22, winSum=383
8882 18:11:52.898237 TX Vref=18, minBit 9, minWin=22, winSum=388
8883 18:11:52.901754 TX Vref=20, minBit 8, minWin=23, winSum=396
8884 18:11:52.904825 TX Vref=22, minBit 11, minWin=23, winSum=405
8885 18:11:52.908511 TX Vref=24, minBit 9, minWin=24, winSum=411
8886 18:11:52.914869 TX Vref=26, minBit 9, minWin=24, winSum=413
8887 18:11:52.917909 TX Vref=28, minBit 11, minWin=24, winSum=416
8888 18:11:52.921626 TX Vref=30, minBit 8, minWin=24, winSum=411
8889 18:11:52.924785 TX Vref=32, minBit 10, minWin=23, winSum=399
8890 18:11:52.928182 TX Vref=34, minBit 9, minWin=23, winSum=393
8891 18:11:52.934544 [TxChooseVref] Worse bit 11, Min win 24, Win sum 416, Final Vref 28
8892 18:11:52.934630
8893 18:11:52.938293 Final TX Range 0 Vref 28
8894 18:11:52.938378
8895 18:11:52.938444 ==
8896 18:11:52.941419 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 18:11:52.944585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 18:11:52.944670 ==
8899 18:11:52.944737
8900 18:11:52.944798
8901 18:11:52.947900 TX Vref Scan disable
8902 18:11:52.954763 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8903 18:11:52.954848 == TX Byte 0 ==
8904 18:11:52.957807 u2DelayCellOfst[0]=16 cells (5 PI)
8905 18:11:52.961402 u2DelayCellOfst[1]=10 cells (3 PI)
8906 18:11:52.964428 u2DelayCellOfst[2]=0 cells (0 PI)
8907 18:11:52.968005 u2DelayCellOfst[3]=6 cells (2 PI)
8908 18:11:52.970916 u2DelayCellOfst[4]=10 cells (3 PI)
8909 18:11:52.974178 u2DelayCellOfst[5]=20 cells (6 PI)
8910 18:11:52.977711 u2DelayCellOfst[6]=16 cells (5 PI)
8911 18:11:52.981284 u2DelayCellOfst[7]=6 cells (2 PI)
8912 18:11:52.984271 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8913 18:11:52.987794 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8914 18:11:52.991450 == TX Byte 1 ==
8915 18:11:52.994454 u2DelayCellOfst[8]=0 cells (0 PI)
8916 18:11:52.994538 u2DelayCellOfst[9]=3 cells (1 PI)
8917 18:11:52.997847 u2DelayCellOfst[10]=10 cells (3 PI)
8918 18:11:53.000938 u2DelayCellOfst[11]=3 cells (1 PI)
8919 18:11:53.004521 u2DelayCellOfst[12]=13 cells (4 PI)
8920 18:11:53.007595 u2DelayCellOfst[13]=16 cells (5 PI)
8921 18:11:53.011056 u2DelayCellOfst[14]=16 cells (5 PI)
8922 18:11:53.014112 u2DelayCellOfst[15]=16 cells (5 PI)
8923 18:11:53.017658 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8924 18:11:53.024161 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8925 18:11:53.024248 DramC Write-DBI on
8926 18:11:53.024316 ==
8927 18:11:53.027716 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 18:11:53.034175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 18:11:53.034260 ==
8930 18:11:53.034327
8931 18:11:53.034388
8932 18:11:53.034447 TX Vref Scan disable
8933 18:11:53.038071 == TX Byte 0 ==
8934 18:11:53.041126 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8935 18:11:53.044452 == TX Byte 1 ==
8936 18:11:53.047682 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8937 18:11:53.051077 DramC Write-DBI off
8938 18:11:53.051160
8939 18:11:53.051228 [DATLAT]
8940 18:11:53.051290 Freq=1600, CH1 RK1
8941 18:11:53.051349
8942 18:11:53.054479 DATLAT Default: 0xf
8943 18:11:53.054572 0, 0xFFFF, sum = 0
8944 18:11:53.057783 1, 0xFFFF, sum = 0
8945 18:11:53.061166 2, 0xFFFF, sum = 0
8946 18:11:53.061250 3, 0xFFFF, sum = 0
8947 18:11:53.064530 4, 0xFFFF, sum = 0
8948 18:11:53.064635 5, 0xFFFF, sum = 0
8949 18:11:53.067624 6, 0xFFFF, sum = 0
8950 18:11:53.067708 7, 0xFFFF, sum = 0
8951 18:11:53.071159 8, 0xFFFF, sum = 0
8952 18:11:53.071243 9, 0xFFFF, sum = 0
8953 18:11:53.074676 10, 0xFFFF, sum = 0
8954 18:11:53.074760 11, 0xFFFF, sum = 0
8955 18:11:53.077638 12, 0xFFFF, sum = 0
8956 18:11:53.077722 13, 0xFFFF, sum = 0
8957 18:11:53.081180 14, 0x0, sum = 1
8958 18:11:53.081312 15, 0x0, sum = 2
8959 18:11:53.084222 16, 0x0, sum = 3
8960 18:11:53.084338 17, 0x0, sum = 4
8961 18:11:53.087342 best_step = 15
8962 18:11:53.087450
8963 18:11:53.087551 ==
8964 18:11:53.090700 Dram Type= 6, Freq= 0, CH_1, rank 1
8965 18:11:53.094237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8966 18:11:53.094347 ==
8967 18:11:53.097651 RX Vref Scan: 0
8968 18:11:53.097761
8969 18:11:53.097860 RX Vref 0 -> 0, step: 1
8970 18:11:53.097955
8971 18:11:53.100801 RX Delay 19 -> 252, step: 4
8972 18:11:53.104189 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8973 18:11:53.110808 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8974 18:11:53.114518 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8975 18:11:53.117500 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8976 18:11:53.121054 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8977 18:11:53.123923 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8978 18:11:53.130854 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8979 18:11:53.133903 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8980 18:11:53.137493 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8981 18:11:53.140571 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8982 18:11:53.144076 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8983 18:11:53.150855 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8984 18:11:53.154349 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8985 18:11:53.157347 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8986 18:11:53.160530 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8987 18:11:53.164229 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8988 18:11:53.167121 ==
8989 18:11:53.167204 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 18:11:53.174358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 18:11:53.174442 ==
8992 18:11:53.174508 DQS Delay:
8993 18:11:53.177312 DQS0 = 0, DQS1 = 0
8994 18:11:53.177394 DQM Delay:
8995 18:11:53.180820 DQM0 = 134, DQM1 = 129
8996 18:11:53.180902 DQ Delay:
8997 18:11:53.184093 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8998 18:11:53.187115 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8999 18:11:53.190468 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9000 18:11:53.193903 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =140
9001 18:11:53.193985
9002 18:11:53.194050
9003 18:11:53.194110
9004 18:11:53.197561 [DramC_TX_OE_Calibration] TA2
9005 18:11:53.200436 Original DQ_B0 (3 6) =30, OEN = 27
9006 18:11:53.203950 Original DQ_B1 (3 6) =30, OEN = 27
9007 18:11:53.207568 24, 0x0, End_B0=24 End_B1=24
9008 18:11:53.210652 25, 0x0, End_B0=25 End_B1=25
9009 18:11:53.210735 26, 0x0, End_B0=26 End_B1=26
9010 18:11:53.213798 27, 0x0, End_B0=27 End_B1=27
9011 18:11:53.217307 28, 0x0, End_B0=28 End_B1=28
9012 18:11:53.220837 29, 0x0, End_B0=29 End_B1=29
9013 18:11:53.220934 30, 0x0, End_B0=30 End_B1=30
9014 18:11:53.223876 31, 0x5151, End_B0=30 End_B1=30
9015 18:11:53.227361 Byte0 end_step=30 best_step=27
9016 18:11:53.230360 Byte1 end_step=30 best_step=27
9017 18:11:53.233880 Byte0 TX OE(2T, 0.5T) = (3, 3)
9018 18:11:53.237407 Byte1 TX OE(2T, 0.5T) = (3, 3)
9019 18:11:53.237490
9020 18:11:53.237554
9021 18:11:53.244064 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9022 18:11:53.246926 CH1 RK1: MR19=303, MR18=1D08
9023 18:11:53.253763 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9024 18:11:53.257177 [RxdqsGatingPostProcess] freq 1600
9025 18:11:53.260105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9026 18:11:53.263462 best DQS0 dly(2T, 0.5T) = (1, 1)
9027 18:11:53.266865 best DQS1 dly(2T, 0.5T) = (1, 1)
9028 18:11:53.270038 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9029 18:11:53.273567 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9030 18:11:53.277118 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 18:11:53.280271 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 18:11:53.283721 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 18:11:53.286708 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 18:11:53.290040 Pre-setting of DQS Precalculation
9035 18:11:53.293373 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9036 18:11:53.300067 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9037 18:11:53.310243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9038 18:11:53.310334
9039 18:11:53.310400
9040 18:11:53.313658 [Calibration Summary] 3200 Mbps
9041 18:11:53.313740 CH 0, Rank 0
9042 18:11:53.316743 SW Impedance : PASS
9043 18:11:53.316826 DUTY Scan : NO K
9044 18:11:53.320238 ZQ Calibration : PASS
9045 18:11:53.323799 Jitter Meter : NO K
9046 18:11:53.323883 CBT Training : PASS
9047 18:11:53.326831 Write leveling : PASS
9048 18:11:53.326908 RX DQS gating : PASS
9049 18:11:53.329938 RX DQ/DQS(RDDQC) : PASS
9050 18:11:53.333340 TX DQ/DQS : PASS
9051 18:11:53.333416 RX DATLAT : PASS
9052 18:11:53.336760 RX DQ/DQS(Engine): PASS
9053 18:11:53.339784 TX OE : PASS
9054 18:11:53.339858 All Pass.
9055 18:11:53.339920
9056 18:11:53.339980 CH 0, Rank 1
9057 18:11:53.343430 SW Impedance : PASS
9058 18:11:53.346227 DUTY Scan : NO K
9059 18:11:53.346310 ZQ Calibration : PASS
9060 18:11:53.349801 Jitter Meter : NO K
9061 18:11:53.353534 CBT Training : PASS
9062 18:11:53.353617 Write leveling : PASS
9063 18:11:53.356364 RX DQS gating : PASS
9064 18:11:53.359865 RX DQ/DQS(RDDQC) : PASS
9065 18:11:53.359948 TX DQ/DQS : PASS
9066 18:11:53.363344 RX DATLAT : PASS
9067 18:11:53.366699 RX DQ/DQS(Engine): PASS
9068 18:11:53.366787 TX OE : PASS
9069 18:11:53.369520 All Pass.
9070 18:11:53.369602
9071 18:11:53.369668 CH 1, Rank 0
9072 18:11:53.373082 SW Impedance : PASS
9073 18:11:53.373165 DUTY Scan : NO K
9074 18:11:53.376368 ZQ Calibration : PASS
9075 18:11:53.379487 Jitter Meter : NO K
9076 18:11:53.379570 CBT Training : PASS
9077 18:11:53.383086 Write leveling : PASS
9078 18:11:53.386214 RX DQS gating : PASS
9079 18:11:53.386297 RX DQ/DQS(RDDQC) : PASS
9080 18:11:53.389739 TX DQ/DQS : PASS
9081 18:11:53.389821 RX DATLAT : PASS
9082 18:11:53.393065 RX DQ/DQS(Engine): PASS
9083 18:11:53.396440 TX OE : PASS
9084 18:11:53.396555 All Pass.
9085 18:11:53.396662
9086 18:11:53.396725 CH 1, Rank 1
9087 18:11:53.399391 SW Impedance : PASS
9088 18:11:53.402824 DUTY Scan : NO K
9089 18:11:53.402943 ZQ Calibration : PASS
9090 18:11:53.406149 Jitter Meter : NO K
9091 18:11:53.409395 CBT Training : PASS
9092 18:11:53.409478 Write leveling : PASS
9093 18:11:53.412804 RX DQS gating : PASS
9094 18:11:53.416291 RX DQ/DQS(RDDQC) : PASS
9095 18:11:53.416400 TX DQ/DQS : PASS
9096 18:11:53.419399 RX DATLAT : PASS
9097 18:11:53.422807 RX DQ/DQS(Engine): PASS
9098 18:11:53.422890 TX OE : PASS
9099 18:11:53.426225 All Pass.
9100 18:11:53.426308
9101 18:11:53.426374 DramC Write-DBI on
9102 18:11:53.429297 PER_BANK_REFRESH: Hybrid Mode
9103 18:11:53.429383 TX_TRACKING: ON
9104 18:11:53.439165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9105 18:11:53.446170 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9106 18:11:53.456163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9107 18:11:53.459669 [FAST_K] Save calibration result to emmc
9108 18:11:53.462570 sync common calibartion params.
9109 18:11:53.462653 sync cbt_mode0:1, 1:1
9110 18:11:53.465908 dram_init: ddr_geometry: 2
9111 18:11:53.469322 dram_init: ddr_geometry: 2
9112 18:11:53.469405 dram_init: ddr_geometry: 2
9113 18:11:53.472776 0:dram_rank_size:100000000
9114 18:11:53.476176 1:dram_rank_size:100000000
9115 18:11:53.479157 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9116 18:11:53.482667 DFS_SHUFFLE_HW_MODE: ON
9117 18:11:53.485821 dramc_set_vcore_voltage set vcore to 725000
9118 18:11:53.489474 Read voltage for 1600, 0
9119 18:11:53.489557 Vio18 = 0
9120 18:11:53.492846 Vcore = 725000
9121 18:11:53.492938 Vdram = 0
9122 18:11:53.493004 Vddq = 0
9123 18:11:53.493065 Vmddr = 0
9124 18:11:53.495848 switch to 3200 Mbps bootup
9125 18:11:53.499146 [DramcRunTimeConfig]
9126 18:11:53.499229 PHYPLL
9127 18:11:53.502471 DPM_CONTROL_AFTERK: ON
9128 18:11:53.502555 PER_BANK_REFRESH: ON
9129 18:11:53.505921 REFRESH_OVERHEAD_REDUCTION: ON
9130 18:11:53.509466 CMD_PICG_NEW_MODE: OFF
9131 18:11:53.509544 XRTWTW_NEW_MODE: ON
9132 18:11:53.512875 XRTRTR_NEW_MODE: ON
9133 18:11:53.512959 TX_TRACKING: ON
9134 18:11:53.516023 RDSEL_TRACKING: OFF
9135 18:11:53.519601 DQS Precalculation for DVFS: ON
9136 18:11:53.519685 RX_TRACKING: OFF
9137 18:11:53.519760 HW_GATING DBG: ON
9138 18:11:53.522614 ZQCS_ENABLE_LP4: ON
9139 18:11:53.526151 RX_PICG_NEW_MODE: ON
9140 18:11:53.526234 TX_PICG_NEW_MODE: ON
9141 18:11:53.529130 ENABLE_RX_DCM_DPHY: ON
9142 18:11:53.532741 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9143 18:11:53.535919 DUMMY_READ_FOR_TRACKING: OFF
9144 18:11:53.536003 !!! SPM_CONTROL_AFTERK: OFF
9145 18:11:53.539264 !!! SPM could not control APHY
9146 18:11:53.542901 IMPEDANCE_TRACKING: ON
9147 18:11:53.542984 TEMP_SENSOR: ON
9148 18:11:53.545731 HW_SAVE_FOR_SR: OFF
9149 18:11:53.549270 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9150 18:11:53.552261 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9151 18:11:53.552345 Read ODT Tracking: ON
9152 18:11:53.555871 Refresh Rate DeBounce: ON
9153 18:11:53.558897 DFS_NO_QUEUE_FLUSH: ON
9154 18:11:53.562451 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9155 18:11:53.562535 ENABLE_DFS_RUNTIME_MRW: OFF
9156 18:11:53.565467 DDR_RESERVE_NEW_MODE: ON
9157 18:11:53.568867 MR_CBT_SWITCH_FREQ: ON
9158 18:11:53.568952 =========================
9159 18:11:53.589313 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9160 18:11:53.592353 dram_init: ddr_geometry: 2
9161 18:11:53.610695 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9162 18:11:53.614238 dram_init: dram init end (result: 0)
9163 18:11:53.620716 DRAM-K: Full calibration passed in 24540 msecs
9164 18:11:53.623809 MRC: failed to locate region type 0.
9165 18:11:53.623894 DRAM rank0 size:0x100000000,
9166 18:11:53.627358 DRAM rank1 size=0x100000000
9167 18:11:53.637536 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9168 18:11:53.643943 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9169 18:11:53.650868 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9170 18:11:53.657041 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9171 18:11:53.660464 DRAM rank0 size:0x100000000,
9172 18:11:53.663885 DRAM rank1 size=0x100000000
9173 18:11:53.663970 CBMEM:
9174 18:11:53.666935 IMD: root @ 0xfffff000 254 entries.
9175 18:11:53.670275 IMD: root @ 0xffffec00 62 entries.
9176 18:11:53.673784 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9177 18:11:53.677163 WARNING: RO_VPD is uninitialized or empty.
9178 18:11:53.683588 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9179 18:11:53.690681 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9180 18:11:53.703255 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9181 18:11:53.714623 BS: romstage times (exec / console): total (unknown) / 24031 ms
9182 18:11:53.714726
9183 18:11:53.714794
9184 18:11:53.724794 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9185 18:11:53.728163 ARM64: Exception handlers installed.
9186 18:11:53.731580 ARM64: Testing exception
9187 18:11:53.734833 ARM64: Done test exception
9188 18:11:53.734917 Enumerating buses...
9189 18:11:53.738270 Show all devs... Before device enumeration.
9190 18:11:53.741237 Root Device: enabled 1
9191 18:11:53.744741 CPU_CLUSTER: 0: enabled 1
9192 18:11:53.744824 CPU: 00: enabled 1
9193 18:11:53.747936 Compare with tree...
9194 18:11:53.748020 Root Device: enabled 1
9195 18:11:53.751352 CPU_CLUSTER: 0: enabled 1
9196 18:11:53.754770 CPU: 00: enabled 1
9197 18:11:53.754853 Root Device scanning...
9198 18:11:53.758254 scan_static_bus for Root Device
9199 18:11:53.761265 CPU_CLUSTER: 0 enabled
9200 18:11:53.764528 scan_static_bus for Root Device done
9201 18:11:53.767666 scan_bus: bus Root Device finished in 8 msecs
9202 18:11:53.767749 done
9203 18:11:53.774596 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9204 18:11:53.777889 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9205 18:11:53.784301 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9206 18:11:53.787707 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9207 18:11:53.790874 Allocating resources...
9208 18:11:53.794535 Reading resources...
9209 18:11:53.797605 Root Device read_resources bus 0 link: 0
9210 18:11:53.797714 DRAM rank0 size:0x100000000,
9211 18:11:53.801098 DRAM rank1 size=0x100000000
9212 18:11:53.804262 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9213 18:11:53.807620 CPU: 00 missing read_resources
9214 18:11:53.811160 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9215 18:11:53.817506 Root Device read_resources bus 0 link: 0 done
9216 18:11:53.817592 Done reading resources.
9217 18:11:53.824174 Show resources in subtree (Root Device)...After reading.
9218 18:11:53.827679 Root Device child on link 0 CPU_CLUSTER: 0
9219 18:11:53.830811 CPU_CLUSTER: 0 child on link 0 CPU: 00
9220 18:11:53.840846 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9221 18:11:53.840940 CPU: 00
9222 18:11:53.844308 Root Device assign_resources, bus 0 link: 0
9223 18:11:53.847321 CPU_CLUSTER: 0 missing set_resources
9224 18:11:53.853899 Root Device assign_resources, bus 0 link: 0 done
9225 18:11:53.853984 Done setting resources.
9226 18:11:53.860767 Show resources in subtree (Root Device)...After assigning values.
9227 18:11:53.863913 Root Device child on link 0 CPU_CLUSTER: 0
9228 18:11:53.868211 CPU_CLUSTER: 0 child on link 0 CPU: 00
9229 18:11:53.877665 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9230 18:11:53.877752 CPU: 00
9231 18:11:53.880533 Done allocating resources.
9232 18:11:53.884398 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9233 18:11:53.887412 Enabling resources...
9234 18:11:53.887498 done.
9235 18:11:53.894170 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9236 18:11:53.894256 Initializing devices...
9237 18:11:53.897513 Root Device init
9238 18:11:53.897598 init hardware done!
9239 18:11:53.900850 0x00000018: ctrlr->caps
9240 18:11:53.903846 52.000 MHz: ctrlr->f_max
9241 18:11:53.903933 0.400 MHz: ctrlr->f_min
9242 18:11:53.907293 0x40ff8080: ctrlr->voltages
9243 18:11:53.907381 sclk: 390625
9244 18:11:53.910359 Bus Width = 1
9245 18:11:53.910443 sclk: 390625
9246 18:11:53.913896 Bus Width = 1
9247 18:11:53.913981 Early init status = 3
9248 18:11:53.920717 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9249 18:11:53.923633 in-header: 03 fc 00 00 01 00 00 00
9250 18:11:53.923721 in-data: 00
9251 18:11:53.930272 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9252 18:11:53.934839 in-header: 03 fd 00 00 00 00 00 00
9253 18:11:53.937833 in-data:
9254 18:11:53.941414 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9255 18:11:53.946127 in-header: 03 fc 00 00 01 00 00 00
9256 18:11:53.949136 in-data: 00
9257 18:11:53.952196 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9258 18:11:53.958201 in-header: 03 fd 00 00 00 00 00 00
9259 18:11:53.961872 in-data:
9260 18:11:53.964812 [SSUSB] Setting up USB HOST controller...
9261 18:11:53.968175 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9262 18:11:53.971668 [SSUSB] phy power-on done.
9263 18:11:53.974996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9264 18:11:53.981534 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9265 18:11:53.984942 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9266 18:11:53.991120 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9267 18:11:53.998056 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9268 18:11:54.004522 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9269 18:11:54.011452 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9270 18:11:54.018001 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9271 18:11:54.021428 SPM: binary array size = 0x9dc
9272 18:11:54.024326 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9273 18:11:54.031376 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9274 18:11:54.037866 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9275 18:11:54.041420 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9276 18:11:54.048006 configure_display: Starting display init
9277 18:11:54.081242 anx7625_power_on_init: Init interface.
9278 18:11:54.084687 anx7625_disable_pd_protocol: Disabled PD feature.
9279 18:11:54.087683 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9280 18:11:54.115722 anx7625_start_dp_work: Secure OCM version=00
9281 18:11:54.119252 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9282 18:11:54.133712 sp_tx_get_edid_block: EDID Block = 1
9283 18:11:54.236755 Extracted contents:
9284 18:11:54.239734 header: 00 ff ff ff ff ff ff 00
9285 18:11:54.243236 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9286 18:11:54.246468 version: 01 04
9287 18:11:54.249957 basic params: 95 1f 11 78 0a
9288 18:11:54.253288 chroma info: 76 90 94 55 54 90 27 21 50 54
9289 18:11:54.256819 established: 00 00 00
9290 18:11:54.263508 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9291 18:11:54.266445 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9292 18:11:54.273320 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9293 18:11:54.279937 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9294 18:11:54.286511 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9295 18:11:54.290129 extensions: 00
9296 18:11:54.290209 checksum: fb
9297 18:11:54.290273
9298 18:11:54.293007 Manufacturer: IVO Model 57d Serial Number 0
9299 18:11:54.296472 Made week 0 of 2020
9300 18:11:54.296559 EDID version: 1.4
9301 18:11:54.299849 Digital display
9302 18:11:54.303134 6 bits per primary color channel
9303 18:11:54.303218 DisplayPort interface
9304 18:11:54.306495 Maximum image size: 31 cm x 17 cm
9305 18:11:54.310062 Gamma: 220%
9306 18:11:54.310142 Check DPMS levels
9307 18:11:54.313400 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9308 18:11:54.316277 First detailed timing is preferred timing
9309 18:11:54.319829 Established timings supported:
9310 18:11:54.323129 Standard timings supported:
9311 18:11:54.323208 Detailed timings
9312 18:11:54.329734 Hex of detail: 383680a07038204018303c0035ae10000019
9313 18:11:54.333225 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9314 18:11:54.339502 0780 0798 07c8 0820 hborder 0
9315 18:11:54.342974 0438 043b 0447 0458 vborder 0
9316 18:11:54.343054 -hsync -vsync
9317 18:11:54.346580 Did detailed timing
9318 18:11:54.349555 Hex of detail: 000000000000000000000000000000000000
9319 18:11:54.353042 Manufacturer-specified data, tag 0
9320 18:11:54.359734 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9321 18:11:54.359814 ASCII string: InfoVision
9322 18:11:54.366306 Hex of detail: 000000fe00523134304e574635205248200a
9323 18:11:54.369349 ASCII string: R140NWF5 RH
9324 18:11:54.369428 Checksum
9325 18:11:54.369491 Checksum: 0xfb (valid)
9326 18:11:54.376348 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9327 18:11:54.379439 DSI data_rate: 832800000 bps
9328 18:11:54.382757 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9329 18:11:54.389135 anx7625_parse_edid: pixelclock(138800).
9330 18:11:54.392725 hactive(1920), hsync(48), hfp(24), hbp(88)
9331 18:11:54.396152 vactive(1080), vsync(12), vfp(3), vbp(17)
9332 18:11:54.399496 anx7625_dsi_config: config dsi.
9333 18:11:54.405696 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9334 18:11:54.418775 anx7625_dsi_config: success to config DSI
9335 18:11:54.421817 anx7625_dp_start: MIPI phy setup OK.
9336 18:11:54.425239 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9337 18:11:54.428203 mtk_ddp_mode_set invalid vrefresh 60
9338 18:11:54.431805 main_disp_path_setup
9339 18:11:54.431886 ovl_layer_smi_id_en
9340 18:11:54.434802 ovl_layer_smi_id_en
9341 18:11:54.434883 ccorr_config
9342 18:11:54.434946 aal_config
9343 18:11:54.438339 gamma_config
9344 18:11:54.438419 postmask_config
9345 18:11:54.441731 dither_config
9346 18:11:54.445097 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9347 18:11:54.451706 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9348 18:11:54.454870 Root Device init finished in 554 msecs
9349 18:11:54.458138 CPU_CLUSTER: 0 init
9350 18:11:54.465157 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9351 18:11:54.468185 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9352 18:11:54.471714 APU_MBOX 0x190000b0 = 0x10001
9353 18:11:54.474677 APU_MBOX 0x190001b0 = 0x10001
9354 18:11:54.478285 APU_MBOX 0x190005b0 = 0x10001
9355 18:11:54.481781 APU_MBOX 0x190006b0 = 0x10001
9356 18:11:54.484842 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9357 18:11:54.497806 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9358 18:11:54.509737 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9359 18:11:54.516368 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9360 18:11:54.528242 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9361 18:11:54.537269 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9362 18:11:54.540866 CPU_CLUSTER: 0 init finished in 81 msecs
9363 18:11:54.543828 Devices initialized
9364 18:11:54.547473 Show all devs... After init.
9365 18:11:54.547568 Root Device: enabled 1
9366 18:11:54.550774 CPU_CLUSTER: 0: enabled 1
9367 18:11:54.554164 CPU: 00: enabled 1
9368 18:11:54.557163 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9369 18:11:54.560542 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9370 18:11:54.563729 ELOG: NV offset 0x57f000 size 0x1000
9371 18:11:54.570368 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9372 18:11:54.576960 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9373 18:11:54.580478 ELOG: Event(17) added with size 13 at 2024-06-11 18:10:28 UTC
9374 18:11:54.583635 out: cmd=0x121: 03 db 21 01 00 00 00 00
9375 18:11:54.588425 in-header: 03 1b 00 00 2c 00 00 00
9376 18:11:54.601939 in-data: 23 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 18:11:54.608541 ELOG: Event(A1) added with size 10 at 2024-06-11 18:10:28 UTC
9378 18:11:54.612015 ELOG: Event(16) added with size 11 at 2024-06-11 18:10:28 UTC
9379 18:11:54.698628 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9380 18:11:54.705124 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9381 18:11:54.711627 ELOG: Event(A0) added with size 9 at 2024-06-11 18:10:29 UTC
9382 18:11:54.715075 elog_add_boot_reason: Logged dev mode boot
9383 18:11:54.718366 BS: BS_POST_DEVICE entry times (exec / console): 83 / 74 ms
9384 18:11:54.721718 Finalize devices...
9385 18:11:54.721801 Devices finalized
9386 18:11:54.728583 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 18:11:54.731890 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9388 18:11:54.735121 in-header: 03 07 00 00 08 00 00 00
9389 18:11:54.738624 in-data: aa e4 47 04 13 02 00 00
9390 18:11:54.741733 Chrome EC: UHEPI supported
9391 18:11:54.748154 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9392 18:11:54.751744 in-header: 03 a9 00 00 08 00 00 00
9393 18:11:54.754802 in-data: 84 60 60 08 00 00 00 00
9394 18:11:54.758280 ELOG: Event(91) added with size 10 at 2024-06-11 18:10:29 UTC
9395 18:11:54.764534 Chrome EC: clear events_b mask to 0x0000000020004000
9396 18:11:54.771761 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9397 18:11:54.775045 in-header: 03 fd 00 00 00 00 00 00
9398 18:11:54.775129 in-data:
9399 18:11:54.781644 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9400 18:11:54.785241 Writing coreboot table at 0xffe64000
9401 18:11:54.788627 0. 000000000010a000-0000000000113fff: RAMSTAGE
9402 18:11:54.791792 1. 0000000040000000-00000000400fffff: RAM
9403 18:11:54.798571 2. 0000000040100000-000000004032afff: RAMSTAGE
9404 18:11:54.801679 3. 000000004032b000-00000000545fffff: RAM
9405 18:11:54.804852 4. 0000000054600000-000000005465ffff: BL31
9406 18:11:54.808203 5. 0000000054660000-00000000ffe63fff: RAM
9407 18:11:54.814828 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9408 18:11:54.818488 7. 0000000100000000-000000023fffffff: RAM
9409 18:11:54.821684 Passing 5 GPIOs to payload:
9410 18:11:54.825059 NAME | PORT | POLARITY | VALUE
9411 18:11:54.827989 EC in RW | 0x000000aa | low | undefined
9412 18:11:54.834860 EC interrupt | 0x00000005 | low | undefined
9413 18:11:54.838134 TPM interrupt | 0x000000ab | high | undefined
9414 18:11:54.844686 SD card detect | 0x00000011 | high | undefined
9415 18:11:54.848082 speaker enable | 0x00000093 | high | undefined
9416 18:11:54.851201 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9417 18:11:54.854677 in-header: 03 f9 00 00 02 00 00 00
9418 18:11:54.857721 in-data: 02 00
9419 18:11:54.857803 ADC[4]: Raw value=901032 ID=7
9420 18:11:54.861281 ADC[3]: Raw value=213179 ID=1
9421 18:11:54.864531 RAM Code: 0x71
9422 18:11:54.864650 ADC[6]: Raw value=74502 ID=0
9423 18:11:54.867944 ADC[5]: Raw value=212441 ID=1
9424 18:11:54.871515 SKU Code: 0x1
9425 18:11:54.874547 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1bf3
9426 18:11:54.878131 coreboot table: 964 bytes.
9427 18:11:54.881235 IMD ROOT 0. 0xfffff000 0x00001000
9428 18:11:54.884747 IMD SMALL 1. 0xffffe000 0x00001000
9429 18:11:54.887763 RO MCACHE 2. 0xffffc000 0x00001104
9430 18:11:54.891355 CONSOLE 3. 0xfff7c000 0x00080000
9431 18:11:54.894323 FMAP 4. 0xfff7b000 0x00000452
9432 18:11:54.897814 TIME STAMP 5. 0xfff7a000 0x00000910
9433 18:11:54.901177 VBOOT WORK 6. 0xfff66000 0x00014000
9434 18:11:54.904272 RAMOOPS 7. 0xffe66000 0x00100000
9435 18:11:54.907893 COREBOOT 8. 0xffe64000 0x00002000
9436 18:11:54.907977 IMD small region:
9437 18:11:54.911298 IMD ROOT 0. 0xffffec00 0x00000400
9438 18:11:54.914263 VPD 1. 0xffffeb80 0x0000006c
9439 18:11:54.917855 MMC STATUS 2. 0xffffeb60 0x00000004
9440 18:11:54.924413 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9441 18:11:54.930747 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 18:11:54.970984 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9443 18:11:54.974031 Checking segment from ROM address 0x40100000
9444 18:11:54.977492 Checking segment from ROM address 0x4010001c
9445 18:11:54.983994 Loading segment from ROM address 0x40100000
9446 18:11:54.984099 code (compression=0)
9447 18:11:54.994200 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 18:11:55.000858 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 18:11:55.000993 it's not compressed!
9450 18:11:55.007827 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 18:11:55.014016 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 18:11:55.031559 Loading segment from ROM address 0x4010001c
9453 18:11:55.031710 Entry Point 0x80000000
9454 18:11:55.034904 Loaded segments
9455 18:11:55.038245 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 18:11:55.044677 Jumping to boot code at 0x80000000(0xffe64000)
9457 18:11:55.051210 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 18:11:55.058285 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 18:11:55.065808 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9460 18:11:55.069468 Checking segment from ROM address 0x40100000
9461 18:11:55.072359 Checking segment from ROM address 0x4010001c
9462 18:11:55.079257 Loading segment from ROM address 0x40100000
9463 18:11:55.079341 code (compression=1)
9464 18:11:55.085854 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 18:11:55.095499 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 18:11:55.095599 using LZMA
9467 18:11:55.104091 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 18:11:55.110843 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 18:11:55.114286 Loading segment from ROM address 0x4010001c
9470 18:11:55.114372 Entry Point 0x54601000
9471 18:11:55.117435 Loaded segments
9472 18:11:55.120737 NOTICE: MT8192 bl31_setup
9473 18:11:55.127822 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 18:11:55.131014 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 18:11:55.134241 WARNING: region 0:
9476 18:11:55.137760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 18:11:55.137846 WARNING: region 1:
9478 18:11:55.144411 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 18:11:55.147693 WARNING: region 2:
9480 18:11:55.151111 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 18:11:55.154311 WARNING: region 3:
9482 18:11:55.157295 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 18:11:55.160829 WARNING: region 4:
9484 18:11:55.167324 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 18:11:55.167410 WARNING: region 5:
9486 18:11:55.170476 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 18:11:55.173835 WARNING: region 6:
9488 18:11:55.177485 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 18:11:55.180492 WARNING: region 7:
9490 18:11:55.184062 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 18:11:55.190557 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 18:11:55.193630 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 18:11:55.200523 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 18:11:55.203689 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 18:11:55.206908 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 18:11:55.213643 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 18:11:55.217229 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 18:11:55.220297 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 18:11:55.227195 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 18:11:55.230594 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 18:11:55.237047 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 18:11:55.240443 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 18:11:55.243860 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 18:11:55.250429 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 18:11:55.253804 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 18:11:55.257062 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 18:11:55.263582 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 18:11:55.267111 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 18:11:55.273584 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 18:11:55.276993 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 18:11:55.280110 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 18:11:55.286572 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 18:11:55.289666 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 18:11:55.296281 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 18:11:55.299895 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 18:11:55.302887 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 18:11:55.309794 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 18:11:55.312875 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 18:11:55.319747 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 18:11:55.323218 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 18:11:55.326811 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 18:11:55.333285 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 18:11:55.336238 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 18:11:55.339429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 18:11:55.342853 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 18:11:55.349629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 18:11:55.353010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 18:11:55.356488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 18:11:55.359360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 18:11:55.366479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 18:11:55.369434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 18:11:55.373100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 18:11:55.376264 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 18:11:55.382673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 18:11:55.386402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 18:11:55.389652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 18:11:55.396186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 18:11:55.399843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 18:11:55.402846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 18:11:55.409490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 18:11:55.412993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 18:11:55.415975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 18:11:55.422922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 18:11:55.425807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 18:11:55.432723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 18:11:55.436254 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 18:11:55.442908 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 18:11:55.445832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 18:11:55.452308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 18:11:55.455530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 18:11:55.459023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 18:11:55.465962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 18:11:55.469093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 18:11:55.475603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 18:11:55.479015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 18:11:55.485722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 18:11:55.489101 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 18:11:55.492197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 18:11:55.498933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 18:11:55.502460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 18:11:55.509037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 18:11:55.512111 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 18:11:55.518851 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 18:11:55.522287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 18:11:55.528780 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 18:11:55.532280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 18:11:55.535733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 18:11:55.542342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 18:11:55.545803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 18:11:55.552219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 18:11:55.555575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 18:11:55.562021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 18:11:55.565456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 18:11:55.568791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 18:11:55.575568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 18:11:55.578900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 18:11:55.585395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 18:11:55.588917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 18:11:55.595445 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 18:11:55.598812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 18:11:55.605455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 18:11:55.608343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 18:11:55.611751 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 18:11:55.618370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 18:11:55.621961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 18:11:55.628410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 18:11:55.631852 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 18:11:55.634878 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 18:11:55.641737 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 18:11:55.645288 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 18:11:55.648160 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 18:11:55.651709 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 18:11:55.658201 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 18:11:55.661564 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 18:11:55.668355 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 18:11:55.671687 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 18:11:55.675025 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 18:11:55.681948 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 18:11:55.684853 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 18:11:55.691464 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 18:11:55.695049 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 18:11:55.697865 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 18:11:55.704466 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 18:11:55.707933 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 18:11:55.714619 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 18:11:55.717823 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 18:11:55.721246 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 18:11:55.727897 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 18:11:55.730964 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 18:11:55.734449 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 18:11:55.737744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 18:11:55.744434 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 18:11:55.747958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 18:11:55.751080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 18:11:55.757687 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 18:11:55.761019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 18:11:55.764454 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 18:11:55.770910 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 18:11:55.774473 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 18:11:55.781034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 18:11:55.784306 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 18:11:55.787729 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 18:11:55.794362 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 18:11:55.797353 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 18:11:55.804315 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 18:11:55.807190 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 18:11:55.810660 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 18:11:55.817628 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 18:11:55.820764 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 18:11:55.827251 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 18:11:55.830472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 18:11:55.833847 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 18:11:55.840927 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 18:11:55.843936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 18:11:55.847436 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 18:11:55.854018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 18:11:55.857390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 18:11:55.863703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 18:11:55.867506 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 18:11:55.870474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 18:11:55.877156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 18:11:55.880417 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 18:11:55.887054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 18:11:55.890713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 18:11:55.893750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 18:11:55.900297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 18:11:55.903834 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 18:11:55.910256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 18:11:55.913704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 18:11:55.916846 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 18:11:55.923755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 18:11:55.926926 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 18:11:55.933337 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 18:11:55.936781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 18:11:55.940027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 18:11:55.946972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 18:11:55.949935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 18:11:55.953404 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 18:11:55.959927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 18:11:55.963427 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 18:11:55.969833 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 18:11:55.973291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 18:11:55.976603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 18:11:55.982856 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 18:11:55.986664 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 18:11:55.992886 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 18:11:55.996404 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 18:11:55.999459 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 18:11:56.006713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 18:11:56.009855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 18:11:56.016120 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 18:11:56.019587 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 18:11:56.023200 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 18:11:56.029726 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 18:11:56.032855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 18:11:56.039464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 18:11:56.042949 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 18:11:56.045975 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 18:11:56.052866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 18:11:56.056027 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 18:11:56.062544 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 18:11:56.066060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 18:11:56.072494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 18:11:56.075775 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 18:11:56.079459 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 18:11:56.085655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 18:11:56.089055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 18:11:56.095721 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 18:11:56.099232 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 18:11:56.102396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 18:11:56.108964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 18:11:56.112521 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 18:11:56.118991 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 18:11:56.122443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 18:11:56.129046 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 18:11:56.132521 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 18:11:56.135665 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 18:11:56.142621 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 18:11:56.145674 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 18:11:56.152370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 18:11:56.156113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 18:11:56.159198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 18:11:56.165610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 18:11:56.169232 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 18:11:56.175828 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 18:11:56.178884 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 18:11:56.182542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 18:11:56.188994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 18:11:56.192400 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 18:11:56.199167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 18:11:56.202569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 18:11:56.209030 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 18:11:56.212129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 18:11:56.215753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 18:11:56.222270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 18:11:56.225712 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 18:11:56.232246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 18:11:56.235215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 18:11:56.238859 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 18:11:56.245350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 18:11:56.248877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 18:11:56.251951 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 18:11:56.255319 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 18:11:56.262181 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 18:11:56.265246 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 18:11:56.268747 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 18:11:56.275286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 18:11:56.278739 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 18:11:56.281810 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 18:11:56.288597 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 18:11:56.292037 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 18:11:56.298805 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 18:11:56.301964 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 18:11:56.305210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 18:11:56.311806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 18:11:56.315347 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 18:11:56.318373 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 18:11:56.325319 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 18:11:56.328321 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 18:11:56.331749 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 18:11:56.338601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 18:11:56.341729 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 18:11:56.348775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 18:11:56.351782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 18:11:56.355320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 18:11:56.361752 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 18:11:56.365275 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 18:11:56.368708 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 18:11:56.375116 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 18:11:56.378789 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 18:11:56.382108 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 18:11:56.388717 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 18:11:56.392082 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 18:11:56.395047 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 18:11:56.401832 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 18:11:56.405198 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 18:11:56.411569 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 18:11:56.415223 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 18:11:56.418433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 18:11:56.421446 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 18:11:56.428026 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 18:11:56.431524 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 18:11:56.434913 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 18:11:56.438007 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 18:11:56.444431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 18:11:56.447891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 18:11:56.451173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 18:11:56.454718 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 18:11:56.461258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 18:11:56.464291 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 18:11:56.467706 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 18:11:56.474624 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 18:11:56.477641 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 18:11:56.481220 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 18:11:56.487558 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 18:11:56.491189 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 18:11:56.497625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 18:11:56.500929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 18:11:56.507766 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 18:11:56.511108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 18:11:56.514203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 18:11:56.520976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 18:11:56.524010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 18:11:56.531059 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 18:11:56.534038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 18:11:56.537524 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 18:11:56.544262 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 18:11:56.547201 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 18:11:56.550755 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 18:11:56.557420 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 18:11:56.560455 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 18:11:56.567422 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 18:11:56.570484 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 18:11:56.577079 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 18:11:56.580501 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 18:11:56.583609 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 18:11:56.590497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 18:11:56.593652 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 18:11:56.600372 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 18:11:56.603574 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 18:11:56.610116 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 18:11:56.613573 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 18:11:56.617260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 18:11:56.623489 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 18:11:56.627177 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 18:11:56.633739 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 18:11:56.637188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 18:11:56.640179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 18:11:56.646592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 18:11:56.649883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 18:11:56.656569 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 18:11:56.660036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 18:11:56.663157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 18:11:56.670195 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 18:11:56.673179 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 18:11:56.679845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 18:11:56.683423 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 18:11:56.686912 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 18:11:56.693461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 18:11:56.696586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 18:11:56.703432 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 18:11:56.706785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 18:11:56.709744 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 18:11:56.716761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 18:11:56.719634 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 18:11:56.726576 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 18:11:56.729963 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 18:11:56.733004 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 18:11:56.739869 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 18:11:56.743332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 18:11:56.749544 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 18:11:56.752970 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 18:11:56.760075 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 18:11:56.763220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 18:11:56.766721 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 18:11:56.772718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 18:11:56.776298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 18:11:56.782816 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 18:11:56.786174 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 18:11:56.789702 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 18:11:56.796292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 18:11:56.799787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 18:11:56.806392 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 18:11:56.809620 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 18:11:56.813138 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 18:11:56.819569 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 18:11:56.823091 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 18:11:56.829287 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 18:11:56.832706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 18:11:56.839417 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 18:11:56.842856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 18:11:56.846129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 18:11:56.852401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 18:11:56.856145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 18:11:56.862780 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 18:11:56.865752 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 18:11:56.872802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 18:11:56.875896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 18:11:56.882509 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 18:11:56.885728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 18:11:56.889377 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 18:11:56.895825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 18:11:56.899002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 18:11:56.906057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 18:11:56.908954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 18:11:56.915795 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 18:11:56.919132 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 18:11:56.922679 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 18:11:56.928974 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 18:11:56.932355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 18:11:56.939067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 18:11:56.942229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 18:11:56.949264 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 18:11:56.952687 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 18:11:56.955599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 18:11:56.962511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 18:11:56.966004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 18:11:56.972495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 18:11:56.975489 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 18:11:56.982559 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 18:11:56.985705 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 18:11:56.991909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 18:11:56.995466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 18:11:56.998812 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 18:11:57.005439 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 18:11:57.009027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 18:11:57.015519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 18:11:57.018864 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 18:11:57.025328 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 18:11:57.028774 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 18:11:57.032034 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 18:11:57.038366 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 18:11:57.041870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 18:11:57.048845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 18:11:57.051812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 18:11:57.055446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 18:11:57.061735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 18:11:57.065312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 18:11:57.071795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 18:11:57.074824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 18:11:57.082076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 18:11:57.085044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 18:11:57.091867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 18:11:57.094841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 18:11:57.101838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 18:11:57.104970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 18:11:57.111445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 18:11:57.114975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 18:11:57.121545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 18:11:57.124747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 18:11:57.131523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 18:11:57.135077 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 18:11:57.141839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 18:11:57.144779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 18:11:57.151686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 18:11:57.154760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 18:11:57.161278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 18:11:57.164493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 18:11:57.171473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 18:11:57.174943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 18:11:57.181570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 18:11:57.184524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 18:11:57.191106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 18:11:57.194581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 18:11:57.197717 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 18:11:57.201186 INFO: [APUAPC] vio 0
9927 18:11:57.207625 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 18:11:57.211169 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 18:11:57.214344 INFO: [APUAPC] D0_APC_0: 0x400510
9930 18:11:57.217787 INFO: [APUAPC] D0_APC_1: 0x0
9931 18:11:57.220974 INFO: [APUAPC] D0_APC_2: 0x1540
9932 18:11:57.224406 INFO: [APUAPC] D0_APC_3: 0x0
9933 18:11:57.227663 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 18:11:57.231079 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 18:11:57.234434 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 18:11:57.237670 INFO: [APUAPC] D1_APC_3: 0x0
9937 18:11:57.240826 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 18:11:57.244667 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 18:11:57.247606 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 18:11:57.250852 INFO: [APUAPC] D2_APC_3: 0x0
9941 18:11:57.254457 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 18:11:57.257455 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 18:11:57.260914 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 18:11:57.260996 INFO: [APUAPC] D3_APC_3: 0x0
9945 18:11:57.267504 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 18:11:57.270493 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 18:11:57.273966 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 18:11:57.274075 INFO: [APUAPC] D4_APC_3: 0x0
9949 18:11:57.277402 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 18:11:57.283945 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 18:11:57.284030 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 18:11:57.287183 INFO: [APUAPC] D5_APC_3: 0x0
9953 18:11:57.290714 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 18:11:57.293687 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 18:11:57.297197 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 18:11:57.300249 INFO: [APUAPC] D6_APC_3: 0x0
9957 18:11:57.303789 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 18:11:57.306900 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 18:11:57.310196 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 18:11:57.313746 INFO: [APUAPC] D7_APC_3: 0x0
9961 18:11:57.317328 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 18:11:57.320723 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 18:11:57.323710 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 18:11:57.327173 INFO: [APUAPC] D8_APC_3: 0x0
9965 18:11:57.330584 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 18:11:57.333371 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 18:11:57.337154 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 18:11:57.340085 INFO: [APUAPC] D9_APC_3: 0x0
9969 18:11:57.343589 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 18:11:57.346816 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 18:11:57.350265 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 18:11:57.353724 INFO: [APUAPC] D10_APC_3: 0x0
9973 18:11:57.357080 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 18:11:57.360149 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 18:11:57.363632 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 18:11:57.366730 INFO: [APUAPC] D11_APC_3: 0x0
9977 18:11:57.370230 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 18:11:57.373606 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 18:11:57.377136 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 18:11:57.379936 INFO: [APUAPC] D12_APC_3: 0x0
9981 18:11:57.383455 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 18:11:57.387227 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 18:11:57.390391 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 18:11:57.393256 INFO: [APUAPC] D13_APC_3: 0x0
9985 18:11:57.396690 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 18:11:57.400276 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 18:11:57.403276 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 18:11:57.407168 INFO: [APUAPC] D14_APC_3: 0x0
9989 18:11:57.410083 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 18:11:57.413316 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 18:11:57.417038 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 18:11:57.420077 INFO: [APUAPC] D15_APC_3: 0x0
9993 18:11:57.423672 INFO: [APUAPC] APC_CON: 0x4
9994 18:11:57.426792 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 18:11:57.430160 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 18:11:57.433674 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 18:11:57.437008 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 18:11:57.437089 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 18:11:57.440068 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 18:11:57.443504 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 18:11:57.447052 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 18:11:57.450240 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 18:11:57.453744 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 18:11:57.456495 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 18:11:57.460512 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 18:11:57.463487 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 18:11:57.466999 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 18:11:57.467080 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 18:11:57.470421 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 18:11:57.473528 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 18:11:57.477094 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 18:11:57.480033 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 18:11:57.483550 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 18:11:57.486674 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 18:11:57.490279 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 18:11:57.493285 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 18:11:57.496722 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 18:11:57.500257 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 18:11:57.503197 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 18:11:57.506692 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 18:11:57.509760 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 18:11:57.509841 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 18:11:57.513198 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 18:11:57.516598 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 18:11:57.519754 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 18:11:57.523334 INFO: [NOCDAPC] APC_CON: 0x4
10027 18:11:57.526322 INFO: [APUAPC] set_apusys_apc done
10028 18:11:57.529916 INFO: [DEVAPC] devapc_init done
10029 18:11:57.532940 INFO: GICv3 without legacy support detected.
10030 18:11:57.539976 INFO: ARM GICv3 driver initialized in EL3
10031 18:11:57.542847 INFO: Maximum SPI INTID supported: 639
10032 18:11:57.546369 INFO: BL31: Initializing runtime services
10033 18:11:57.552833 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 18:11:57.552917 INFO: SPM: enable CPC mode
10035 18:11:57.559650 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 18:11:57.563024 INFO: BL31: Preparing for EL3 exit to normal world
10037 18:11:57.569717 INFO: Entry point address = 0x80000000
10038 18:11:57.569803 INFO: SPSR = 0x8
10039 18:11:57.575644
10040 18:11:57.575726
10041 18:11:57.575791
10042 18:11:57.578716 Starting depthcharge on Spherion...
10043 18:11:57.578799
10044 18:11:57.578865 Wipe memory regions:
10045 18:11:57.578924
10046 18:11:57.579493 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10047 18:11:57.579593 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10048 18:11:57.579676 Setting prompt string to ['asurada:']
10049 18:11:57.579753 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10050 18:11:57.582185 [0x00000040000000, 0x00000054600000)
10051 18:11:57.704579
10052 18:11:57.704763 [0x00000054660000, 0x00000080000000)
10053 18:11:57.965018
10054 18:11:57.965174 [0x000000821a7280, 0x000000ffe64000)
10055 18:11:58.709870
10056 18:11:58.710030 [0x00000100000000, 0x00000240000000)
10057 18:12:00.599223
10058 18:12:00.602196 Initializing XHCI USB controller at 0x11200000.
10059 18:12:01.640486
10060 18:12:01.643852 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 18:12:01.644275
10062 18:12:01.644645
10063 18:12:01.645533 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 18:12:01.746926 asurada: tftpboot 192.168.201.1 14291494/tftp-deploy-_xa68jvm/kernel/image.itb 14291494/tftp-deploy-_xa68jvm/kernel/cmdline
10066 18:12:01.747145 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 18:12:01.747252 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10068 18:12:01.751259 tftpboot 192.168.201.1 14291494/tftp-deploy-_xa68jvm/kernel/image.itp-deploy-_xa68jvm/kernel/cmdline
10069 18:12:01.751347
10070 18:12:01.751414 Waiting for link
10071 18:12:01.909840
10072 18:12:01.910029 R8152: Initializing
10073 18:12:01.910133
10074 18:12:01.913232 Version 9 (ocp_data = 6010)
10075 18:12:01.913432
10076 18:12:01.916334 R8152: Done initializing
10077 18:12:01.916505
10078 18:12:01.916670 Adding net device
10079 18:12:03.788155
10080 18:12:03.788289 done.
10081 18:12:03.788362
10082 18:12:03.788425 MAC: 00:e0:4c:72:2d:d6
10083 18:12:03.788486
10084 18:12:03.791322 Sending DHCP discover... done.
10085 18:12:03.791408
10086 18:12:03.794772 Waiting for reply... done.
10087 18:12:03.794858
10088 18:12:03.798351 Sending DHCP request... done.
10089 18:12:03.798436
10090 18:12:03.798503 Waiting for reply... done.
10091 18:12:03.798566
10092 18:12:03.801541 My ip is 192.168.201.21
10093 18:12:03.801624
10094 18:12:03.804674 The DHCP server ip is 192.168.201.1
10095 18:12:03.804758
10096 18:12:03.808420 TFTP server IP predefined by user: 192.168.201.1
10097 18:12:03.808531
10098 18:12:03.814490 Bootfile predefined by user: 14291494/tftp-deploy-_xa68jvm/kernel/image.itb
10099 18:12:03.814574
10100 18:12:03.818221 Sending tftp read request... done.
10101 18:12:03.818304
10102 18:12:03.821211 Waiting for the transfer...
10103 18:12:03.821304
10104 18:12:04.086255 00000000 ################################################################
10105 18:12:04.086388
10106 18:12:04.331205 00080000 ################################################################
10107 18:12:04.331371
10108 18:12:04.573395 00100000 ################################################################
10109 18:12:04.573562
10110 18:12:04.820007 00180000 ################################################################
10111 18:12:04.820172
10112 18:12:05.063454 00200000 ################################################################
10113 18:12:05.063614
10114 18:12:05.307747 00280000 ################################################################
10115 18:12:05.307917
10116 18:12:05.563199 00300000 ################################################################
10117 18:12:05.563366
10118 18:12:05.820381 00380000 ################################################################
10119 18:12:05.820511
10120 18:12:06.071961 00400000 ################################################################
10121 18:12:06.072102
10122 18:12:06.322464 00480000 ################################################################
10123 18:12:06.322604
10124 18:12:06.592189 00500000 ################################################################
10125 18:12:06.592319
10126 18:12:06.886492 00580000 ################################################################
10127 18:12:06.886629
10128 18:12:07.171676 00600000 ################################################################
10129 18:12:07.171868
10130 18:12:07.436823 00680000 ################################################################
10131 18:12:07.436992
10132 18:12:07.712314 00700000 ################################################################
10133 18:12:07.712457
10134 18:12:07.993266 00780000 ################################################################
10135 18:12:07.993403
10136 18:12:08.258217 00800000 ################################################################
10137 18:12:08.258350
10138 18:12:08.504432 00880000 ################################################################
10139 18:12:08.504584
10140 18:12:08.753145 00900000 ################################################################
10141 18:12:08.753278
10142 18:12:09.018173 00980000 ################################################################
10143 18:12:09.018307
10144 18:12:09.266445 00a00000 ################################################################
10145 18:12:09.266580
10146 18:12:09.514351 00a80000 ################################################################
10147 18:12:09.514512
10148 18:12:09.762102 00b00000 ################################################################
10149 18:12:09.762241
10150 18:12:10.013022 00b80000 ################################################################
10151 18:12:10.013160
10152 18:12:10.269523 00c00000 ################################################################
10153 18:12:10.269661
10154 18:12:10.526927 00c80000 ################################################################
10155 18:12:10.527059
10156 18:12:10.773186 00d00000 ################################################################
10157 18:12:10.773323
10158 18:12:11.024820 00d80000 ################################################################
10159 18:12:11.024981
10160 18:12:11.277697 00e00000 ################################################################
10161 18:12:11.277863
10162 18:12:11.526174 00e80000 ################################################################
10163 18:12:11.526341
10164 18:12:11.779307 00f00000 ################################################################
10165 18:12:11.779470
10166 18:12:12.026153 00f80000 ################################################################
10167 18:12:12.026286
10168 18:12:12.278316 01000000 ################################################################
10169 18:12:12.278459
10170 18:12:12.550992 01080000 ################################################################
10171 18:12:12.551175
10172 18:12:12.832824 01100000 ################################################################
10173 18:12:12.832988
10174 18:12:13.088055 01180000 ################################################################
10175 18:12:13.088189
10176 18:12:13.344140 01200000 ################################################################
10177 18:12:13.344349
10178 18:12:13.622469 01280000 ################################################################
10179 18:12:13.622607
10180 18:12:13.873701 01300000 ################################################################
10181 18:12:13.873860
10182 18:12:14.122934 01380000 ################################################################
10183 18:12:14.123113
10184 18:12:14.376923 01400000 ################################################################
10185 18:12:14.377059
10186 18:12:14.623127 01480000 ################################################################
10187 18:12:14.623279
10188 18:12:14.868424 01500000 ################################################################
10189 18:12:14.868581
10190 18:12:15.116508 01580000 ################################################################
10191 18:12:15.116670
10192 18:12:15.363950 01600000 ################################################################
10193 18:12:15.364095
10194 18:12:15.611531 01680000 ################################################################
10195 18:12:15.611664
10196 18:12:15.857480 01700000 ################################################################
10197 18:12:15.857613
10198 18:12:16.103859 01780000 ################################################################
10199 18:12:16.104013
10200 18:12:16.377391 01800000 ################################################################
10201 18:12:16.377527
10202 18:12:16.646580 01880000 ################################################################
10203 18:12:16.646733
10204 18:12:16.906984 01900000 ################################################################
10205 18:12:16.907155
10206 18:12:17.153162 01980000 ################################################################
10207 18:12:17.153295
10208 18:12:17.399302 01a00000 ################################################################
10209 18:12:17.399459
10210 18:12:17.646904 01a80000 ################################################################
10211 18:12:17.647076
10212 18:12:17.892471 01b00000 ################################################################
10213 18:12:17.892616
10214 18:12:18.156764 01b80000 ################################################################
10215 18:12:18.157074
10216 18:12:18.399532 01c00000 ################################################################
10217 18:12:18.399672
10218 18:12:18.656813 01c80000 ################################################################
10219 18:12:18.656999
10220 18:12:18.901840 01d00000 ################################################################
10221 18:12:18.902044
10222 18:12:19.170916 01d80000 ################################################################
10223 18:12:19.171083
10224 18:12:19.418784 01e00000 ################################################################
10225 18:12:19.418966
10226 18:12:19.697335 01e80000 ################################################################
10227 18:12:19.697478
10228 18:12:19.955723 01f00000 ################################################################
10229 18:12:19.955869
10230 18:12:20.208063 01f80000 ################################################################
10231 18:12:20.208208
10232 18:12:20.465976 02000000 ################################################################
10233 18:12:20.466119
10234 18:12:20.720881 02080000 ################################################################
10235 18:12:20.721027
10236 18:12:20.974778 02100000 ################################################################
10237 18:12:20.974946
10238 18:12:21.237819 02180000 ################################################################
10239 18:12:21.237980
10240 18:12:21.507442 02200000 ################################################################
10241 18:12:21.507625
10242 18:12:21.762697 02280000 ################################################################
10243 18:12:21.762874
10244 18:12:22.034144 02300000 ################################################################
10245 18:12:22.034292
10246 18:12:22.289542 02380000 ################################################################
10247 18:12:22.289694
10248 18:12:22.542445 02400000 ################################################################
10249 18:12:22.542594
10250 18:12:22.798880 02480000 ################################################################
10251 18:12:22.799031
10252 18:12:23.049640 02500000 ################################################################
10253 18:12:23.049808
10254 18:12:23.318554 02580000 ################################################################
10255 18:12:23.318694
10256 18:12:23.598859 02600000 ################################################################
10257 18:12:23.598995
10258 18:12:23.888907 02680000 ################################################################
10259 18:12:23.889044
10260 18:12:24.154350 02700000 ################################################################
10261 18:12:24.154485
10262 18:12:24.425464 02780000 ################################################################
10263 18:12:24.425599
10264 18:12:24.690363 02800000 ################################################################
10265 18:12:24.690499
10266 18:12:24.954838 02880000 ################################################################
10267 18:12:24.954971
10268 18:12:25.212973 02900000 ################################################################
10269 18:12:25.213134
10270 18:12:25.519141 02980000 ################################################################
10271 18:12:25.519309
10272 18:12:25.789431 02a00000 ################################################################
10273 18:12:25.789566
10274 18:12:26.047493 02a80000 ################################################################
10275 18:12:26.047629
10276 18:12:26.332093 02b00000 ################################################################
10277 18:12:26.332231
10278 18:12:26.615438 02b80000 ################################################################
10279 18:12:26.615578
10280 18:12:26.864640 02c00000 ################################################################
10281 18:12:26.864811
10282 18:12:27.148976 02c80000 ################################################################
10283 18:12:27.149145
10284 18:12:27.428486 02d00000 ################################################################
10285 18:12:27.428674
10286 18:12:27.688983 02d80000 ################################################################
10287 18:12:27.689130
10288 18:12:27.976993 02e00000 ################################################################
10289 18:12:27.977129
10290 18:12:28.258646 02e80000 ################################################################
10291 18:12:28.258793
10292 18:12:28.519727 02f00000 ################################################################
10293 18:12:28.519861
10294 18:12:28.780369 02f80000 ################################################################
10295 18:12:28.780543
10296 18:12:29.047493 03000000 ################################################################
10297 18:12:29.047663
10298 18:12:29.317433 03080000 ################################################################
10299 18:12:29.317585
10300 18:12:29.571413 03100000 ################################################################
10301 18:12:29.571561
10302 18:12:29.833143 03180000 ################################################################
10303 18:12:29.833292
10304 18:12:30.125050 03200000 ################################################################
10305 18:12:30.125185
10306 18:12:30.461935 03280000 ################################################################
10307 18:12:30.462073
10308 18:12:30.726503 03300000 ################################################################
10309 18:12:30.726647
10310 18:12:30.929870 03380000 ################################################ done.
10311 18:12:30.930027
10312 18:12:30.933223 The bootfile was 54390298 bytes long.
10313 18:12:30.933332
10314 18:12:30.936521 Sending tftp read request... done.
10315 18:12:30.936623
10316 18:12:30.940410 Waiting for the transfer...
10317 18:12:30.940605
10318 18:12:30.940712 00000000 # done.
10319 18:12:30.943455
10320 18:12:30.950217 Command line loaded dynamically from TFTP file: 14291494/tftp-deploy-_xa68jvm/kernel/cmdline
10321 18:12:30.950407
10322 18:12:30.963874 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10323 18:12:30.964132
10324 18:12:30.964275 Loading FIT.
10325 18:12:30.964396
10326 18:12:30.966666 Image ramdisk-1 has 41215902 bytes.
10327 18:12:30.966821
10328 18:12:30.970249 Image fdt-1 has 47258 bytes.
10329 18:12:30.970428
10330 18:12:30.973513 Image kernel-1 has 13125101 bytes.
10331 18:12:30.973715
10332 18:12:30.983952 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10333 18:12:30.984257
10334 18:12:31.000591 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10335 18:12:31.001090
10336 18:12:31.003774 Choosing best match conf-1 for compat google,spherion-rev2.
10337 18:12:31.009332
10338 18:12:31.014458 Connected to device vid:did:rid of 1ae0:0028:00
10339 18:12:31.021446
10340 18:12:31.024287 tpm_get_response: command 0x17b, return code 0x0
10341 18:12:31.024857
10342 18:12:31.028070 ec_init: CrosEC protocol v3 supported (256, 248)
10343 18:12:31.033129
10344 18:12:31.036259 tpm_cleanup: add release locality here.
10345 18:12:31.036894
10346 18:12:31.037267 Shutting down all USB controllers.
10347 18:12:31.039409
10348 18:12:31.039868 Removing current net device
10349 18:12:31.040235
10350 18:12:31.046187 Exiting depthcharge with code 4 at timestamp: 62909165
10351 18:12:31.046753
10352 18:12:31.049391 LZMA decompressing kernel-1 to 0x821a6718
10353 18:12:31.049864
10354 18:12:31.052353 LZMA decompressing kernel-1 to 0x40000000
10355 18:12:32.669967
10356 18:12:32.670381 jumping to kernel
10357 18:12:32.672164 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10358 18:12:32.672678 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10359 18:12:32.673058 Setting prompt string to ['Linux version [0-9]']
10360 18:12:32.673402 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10361 18:12:32.673765 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10362 18:12:32.752523
10363 18:12:32.756081 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10364 18:12:32.759247 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10365 18:12:32.759410 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10366 18:12:32.759528 Setting prompt string to []
10367 18:12:32.759647 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10368 18:12:32.759763 Using line separator: #'\n'#
10369 18:12:32.759860 No login prompt set.
10370 18:12:32.759956 Parsing kernel messages
10371 18:12:32.760044 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10372 18:12:32.760203 [login-action] Waiting for messages, (timeout 00:03:52)
10373 18:12:32.760308 Waiting using forced prompt support (timeout 00:01:56)
10374 18:12:32.779261 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j225340-arm64-gcc-10-defconfig-arm64-chromebook-x2t4v) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024
10375 18:12:32.782383 [ 0.000000] random: crng init done
10376 18:12:32.789536 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10377 18:12:32.789696 [ 0.000000] efi: UEFI not found.
10378 18:12:32.799383 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10379 18:12:32.805732 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10380 18:12:32.816091 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10381 18:12:32.826316 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10382 18:12:32.832866 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10383 18:12:32.835927 [ 0.000000] printk: bootconsole [mtk8250] enabled
10384 18:12:32.844629 [ 0.000000] NUMA: No NUMA configuration found
10385 18:12:32.851524 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10386 18:12:32.858188 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10387 18:12:32.858392 [ 0.000000] Zone ranges:
10388 18:12:32.864933 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10389 18:12:32.868323 [ 0.000000] DMA32 empty
10390 18:12:32.874910 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10391 18:12:32.878521 [ 0.000000] Movable zone start for each node
10392 18:12:32.881320 [ 0.000000] Early memory node ranges
10393 18:12:32.887883 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10394 18:12:32.895018 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10395 18:12:32.901415 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10396 18:12:32.908638 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10397 18:12:32.915030 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10398 18:12:32.921376 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10399 18:12:32.977425 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10400 18:12:32.984313 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10401 18:12:32.990792 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10402 18:12:32.994411 [ 0.000000] psci: probing for conduit method from DT.
10403 18:12:33.001201 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10404 18:12:33.004114 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10405 18:12:33.011023 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10406 18:12:33.014757 [ 0.000000] psci: SMC Calling Convention v1.2
10407 18:12:33.021246 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10408 18:12:33.024747 [ 0.000000] Detected VIPT I-cache on CPU0
10409 18:12:33.031206 [ 0.000000] CPU features: detected: GIC system register CPU interface
10410 18:12:33.037738 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10411 18:12:33.044493 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10412 18:12:33.051089 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10413 18:12:33.058042 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10414 18:12:33.064892 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10415 18:12:33.071143 [ 0.000000] alternatives: applying boot alternatives
10416 18:12:33.074252 [ 0.000000] Fallback order for Node 0: 0
10417 18:12:33.080766 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10418 18:12:33.084330 [ 0.000000] Policy zone: Normal
10419 18:12:33.100884 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10420 18:12:33.111085 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10421 18:12:33.121983 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10422 18:12:33.131954 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10423 18:12:33.138818 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10424 18:12:33.141632 <6>[ 0.000000] software IO TLB: area num 8.
10425 18:12:33.198262 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10426 18:12:33.348373 <6>[ 0.000000] Memory: 7923812K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428956K reserved, 32768K cma-reserved)
10427 18:12:33.355172 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10428 18:12:33.361945 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10429 18:12:33.364711 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10430 18:12:33.371147 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10431 18:12:33.378416 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10432 18:12:33.381440 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10433 18:12:33.391371 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10434 18:12:33.397899 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10435 18:12:33.401282 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10436 18:12:33.408862 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10437 18:12:33.412576 <6>[ 0.000000] GICv3: 608 SPIs implemented
10438 18:12:33.419383 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10439 18:12:33.422617 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10440 18:12:33.425662 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10441 18:12:33.435990 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10442 18:12:33.445419 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10443 18:12:33.459212 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10444 18:12:33.465606 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10445 18:12:33.474945 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10446 18:12:33.487843 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10447 18:12:33.494294 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10448 18:12:33.501265 <6>[ 0.009185] Console: colour dummy device 80x25
10449 18:12:33.510968 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10450 18:12:33.514135 <6>[ 0.024448] pid_max: default: 32768 minimum: 301
10451 18:12:33.521078 <6>[ 0.029319] LSM: Security Framework initializing
10452 18:12:33.527501 <6>[ 0.034258] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10453 18:12:33.537702 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 18:12:33.544634 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10455 18:12:33.551184 <6>[ 0.058932] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 18:12:33.557770 <6>[ 0.065273] cblist_init_generic: Setting adjustable number of callback queues.
10457 18:12:33.564414 <6>[ 0.072699] cblist_init_generic: Setting shift to 3 and lim to 1.
10458 18:12:33.571086 <6>[ 0.079101] rcu: Hierarchical SRCU implementation.
10459 18:12:33.577880 <6>[ 0.084116] rcu: Max phase no-delay instances is 1000.
10460 18:12:33.581117 <6>[ 0.091173] EFI services will not be available.
10461 18:12:33.587580 <6>[ 0.096129] smp: Bringing up secondary CPUs ...
10462 18:12:33.595744 <6>[ 0.101180] Detected VIPT I-cache on CPU1
10463 18:12:33.601784 <6>[ 0.101252] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10464 18:12:33.609249 <6>[ 0.101283] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10465 18:12:33.612243 <6>[ 0.101625] Detected VIPT I-cache on CPU2
10466 18:12:33.619149 <6>[ 0.101679] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10467 18:12:33.625366 <6>[ 0.101696] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10468 18:12:33.632082 <6>[ 0.101957] Detected VIPT I-cache on CPU3
10469 18:12:33.638795 <6>[ 0.102005] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10470 18:12:33.645540 <6>[ 0.102020] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10471 18:12:33.649011 <6>[ 0.102324] CPU features: detected: Spectre-v4
10472 18:12:33.656014 <6>[ 0.102331] CPU features: detected: Spectre-BHB
10473 18:12:33.659104 <6>[ 0.102336] Detected PIPT I-cache on CPU4
10474 18:12:33.665576 <6>[ 0.102395] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10475 18:12:33.672908 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10476 18:12:33.675678 <6>[ 0.102703] Detected PIPT I-cache on CPU5
10477 18:12:33.686007 <6>[ 0.102765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10478 18:12:33.692368 <6>[ 0.102781] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10479 18:12:33.695431 <6>[ 0.103066] Detected PIPT I-cache on CPU6
10480 18:12:33.702293 <6>[ 0.103130] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10481 18:12:33.709142 <6>[ 0.103146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10482 18:12:33.712665 <6>[ 0.103444] Detected PIPT I-cache on CPU7
10483 18:12:33.719221 <6>[ 0.103501] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10484 18:12:33.726235 <6>[ 0.103517] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10485 18:12:33.732313 <6>[ 0.103563] smp: Brought up 1 node, 8 CPUs
10486 18:12:33.735907 <6>[ 0.244887] SMP: Total of 8 processors activated.
10487 18:12:33.742549 <6>[ 0.249809] CPU features: detected: 32-bit EL0 Support
10488 18:12:33.752196 <6>[ 0.255205] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10489 18:12:33.755426 <6>[ 0.264005] CPU features: detected: Common not Private translations
10490 18:12:33.762515 <6>[ 0.270521] CPU features: detected: CRC32 instructions
10491 18:12:33.769378 <6>[ 0.275872] CPU features: detected: RCpc load-acquire (LDAPR)
10492 18:12:33.776038 <6>[ 0.281833] CPU features: detected: LSE atomic instructions
10493 18:12:33.779584 <6>[ 0.287650] CPU features: detected: Privileged Access Never
10494 18:12:33.786120 <6>[ 0.293429] CPU features: detected: RAS Extension Support
10495 18:12:33.792704 <6>[ 0.299038] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10496 18:12:33.795866 <6>[ 0.306301] CPU: All CPU(s) started at EL2
10497 18:12:33.802361 <6>[ 0.310644] alternatives: applying system-wide alternatives
10498 18:12:33.813097 <6>[ 0.321473] devtmpfs: initialized
10499 18:12:33.825497 <6>[ 0.330274] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10500 18:12:33.835519 <6>[ 0.340237] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10501 18:12:33.842017 <6>[ 0.348254] pinctrl core: initialized pinctrl subsystem
10502 18:12:33.845565 <6>[ 0.354928] DMI not present or invalid.
10503 18:12:33.852420 <6>[ 0.359337] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10504 18:12:33.858870 <6>[ 0.366181] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10505 18:12:33.869105 <6>[ 0.373771] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10506 18:12:33.876143 <6>[ 0.381994] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10507 18:12:33.882201 <6>[ 0.390239] audit: initializing netlink subsys (disabled)
10508 18:12:33.891927 <5>[ 0.395933] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10509 18:12:33.895349 <6>[ 0.396655] thermal_sys: Registered thermal governor 'step_wise'
10510 18:12:33.902146 <6>[ 0.403901] thermal_sys: Registered thermal governor 'power_allocator'
10511 18:12:33.908971 <6>[ 0.410157] cpuidle: using governor menu
10512 18:12:33.912035 <6>[ 0.421122] NET: Registered PF_QIPCRTR protocol family
10513 18:12:33.918986 <6>[ 0.426600] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10514 18:12:33.925705 <6>[ 0.433701] ASID allocator initialised with 32768 entries
10515 18:12:33.932337 <6>[ 0.440281] Serial: AMBA PL011 UART driver
10516 18:12:33.940642 <4>[ 0.449115] Trying to register duplicate clock ID: 134
10517 18:12:33.999425 <6>[ 0.510713] KASLR enabled
10518 18:12:34.013250 <6>[ 0.518439] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10519 18:12:34.020010 <6>[ 0.525452] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10520 18:12:34.027343 <6>[ 0.531943] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10521 18:12:34.033686 <6>[ 0.538949] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10522 18:12:34.040002 <6>[ 0.545435] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10523 18:12:34.046856 <6>[ 0.552438] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10524 18:12:34.053507 <6>[ 0.558923] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10525 18:12:34.059999 <6>[ 0.565926] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10526 18:12:34.063602 <6>[ 0.573334] ACPI: Interpreter disabled.
10527 18:12:34.071788 <6>[ 0.579765] iommu: Default domain type: Translated
10528 18:12:34.078696 <6>[ 0.584878] iommu: DMA domain TLB invalidation policy: strict mode
10529 18:12:34.081579 <5>[ 0.591540] SCSI subsystem initialized
10530 18:12:34.088310 <6>[ 0.595707] usbcore: registered new interface driver usbfs
10531 18:12:34.094449 <6>[ 0.601441] usbcore: registered new interface driver hub
10532 18:12:34.098083 <6>[ 0.606995] usbcore: registered new device driver usb
10533 18:12:34.104731 <6>[ 0.613095] pps_core: LinuxPPS API ver. 1 registered
10534 18:12:34.114726 <6>[ 0.618290] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10535 18:12:34.118396 <6>[ 0.627637] PTP clock support registered
10536 18:12:34.121243 <6>[ 0.631883] EDAC MC: Ver: 3.0.0
10537 18:12:34.128497 <6>[ 0.637043] FPGA manager framework
10538 18:12:34.135151 <6>[ 0.640731] Advanced Linux Sound Architecture Driver Initialized.
10539 18:12:34.139049 <6>[ 0.647505] vgaarb: loaded
10540 18:12:34.145201 <6>[ 0.650648] clocksource: Switched to clocksource arch_sys_counter
10541 18:12:34.148501 <5>[ 0.657085] VFS: Disk quotas dquot_6.6.0
10542 18:12:34.154939 <6>[ 0.661271] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10543 18:12:34.157999 <6>[ 0.668460] pnp: PnP ACPI: disabled
10544 18:12:34.166832 <6>[ 0.675199] NET: Registered PF_INET protocol family
10545 18:12:34.176743 <6>[ 0.680795] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10546 18:12:34.188384 <6>[ 0.693126] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10547 18:12:34.198296 <6>[ 0.701938] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10548 18:12:34.204887 <6>[ 0.709908] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10549 18:12:34.214935 <6>[ 0.718608] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10550 18:12:34.221010 <6>[ 0.728363] TCP: Hash tables configured (established 65536 bind 65536)
10551 18:12:34.228245 <6>[ 0.735225] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10552 18:12:34.237792 <6>[ 0.742422] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 18:12:34.244453 <6>[ 0.750126] NET: Registered PF_UNIX/PF_LOCAL protocol family
10554 18:12:34.248143 <6>[ 0.756283] RPC: Registered named UNIX socket transport module.
10555 18:12:34.254702 <6>[ 0.762436] RPC: Registered udp transport module.
10556 18:12:34.257716 <6>[ 0.767368] RPC: Registered tcp transport module.
10557 18:12:34.264738 <6>[ 0.772300] RPC: Registered tcp NFSv4.1 backchannel transport module.
10558 18:12:34.271015 <6>[ 0.778966] PCI: CLS 0 bytes, default 64
10559 18:12:34.274114 <6>[ 0.783301] Unpacking initramfs...
10560 18:12:34.298266 <6>[ 0.802765] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10561 18:12:34.307908 <6>[ 0.811418] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10562 18:12:34.311385 <6>[ 0.820257] kvm [1]: IPA Size Limit: 40 bits
10563 18:12:34.317575 <6>[ 0.824785] kvm [1]: GICv3: no GICV resource entry
10564 18:12:34.321199 <6>[ 0.829805] kvm [1]: disabling GICv2 emulation
10565 18:12:34.328103 <6>[ 0.834494] kvm [1]: GIC system register CPU interface enabled
10566 18:12:34.330664 <6>[ 0.840664] kvm [1]: vgic interrupt IRQ18
10567 18:12:34.338101 <6>[ 0.845017] kvm [1]: VHE mode initialized successfully
10568 18:12:34.344317 <5>[ 0.851520] Initialise system trusted keyrings
10569 18:12:34.350851 <6>[ 0.856333] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10570 18:12:34.358552 <6>[ 0.866556] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10571 18:12:34.365168 <5>[ 0.872987] NFS: Registering the id_resolver key type
10572 18:12:34.368084 <5>[ 0.878294] Key type id_resolver registered
10573 18:12:34.374949 <5>[ 0.882709] Key type id_legacy registered
10574 18:12:34.381372 <6>[ 0.886989] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10575 18:12:34.388206 <6>[ 0.893912] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10576 18:12:34.394470 <6>[ 0.901630] 9p: Installing v9fs 9p2000 file system support
10577 18:12:34.432026 <5>[ 0.940339] Key type asymmetric registered
10578 18:12:34.435617 <5>[ 0.944670] Asymmetric key parser 'x509' registered
10579 18:12:34.445024 <6>[ 0.949811] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10580 18:12:34.448625 <6>[ 0.957428] io scheduler mq-deadline registered
10581 18:12:34.451921 <6>[ 0.962229] io scheduler kyber registered
10582 18:12:34.470908 <6>[ 0.979249] EINJ: ACPI disabled.
10583 18:12:34.503749 <4>[ 1.005218] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 18:12:34.513224 <4>[ 1.015870] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 18:12:34.529188 <6>[ 1.037018] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10586 18:12:34.536761 <6>[ 1.045062] printk: console [ttyS0] disabled
10587 18:12:34.564974 <6>[ 1.069690] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10588 18:12:34.571192 <6>[ 1.079169] printk: console [ttyS0] enabled
10589 18:12:34.574668 <6>[ 1.079169] printk: console [ttyS0] enabled
10590 18:12:34.581259 <6>[ 1.088066] printk: bootconsole [mtk8250] disabled
10591 18:12:34.584870 <6>[ 1.088066] printk: bootconsole [mtk8250] disabled
10592 18:12:34.591156 <6>[ 1.099352] SuperH (H)SCI(F) driver initialized
10593 18:12:34.594593 <6>[ 1.104625] msm_serial: driver initialized
10594 18:12:34.608418 <6>[ 1.113588] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10595 18:12:34.618343 <6>[ 1.122134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10596 18:12:34.625010 <6>[ 1.130678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10597 18:12:34.634989 <6>[ 1.139306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10598 18:12:34.644917 <6>[ 1.148019] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10599 18:12:34.651898 <6>[ 1.156741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10600 18:12:34.661684 <6>[ 1.165283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10601 18:12:34.668025 <6>[ 1.174088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10602 18:12:34.678012 <6>[ 1.182632] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10603 18:12:34.690015 <6>[ 1.198202] loop: module loaded
10604 18:12:34.696371 <6>[ 1.204211] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10605 18:12:34.719222 <4>[ 1.227268] mtk-pmic-keys: Failed to locate of_node [id: -1]
10606 18:12:34.726052 <6>[ 1.234176] megasas: 07.719.03.00-rc1
10607 18:12:34.735567 <6>[ 1.243758] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10608 18:12:34.742531 <6>[ 1.250036] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10609 18:12:34.758539 <6>[ 1.266598] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10610 18:12:34.814582 <6>[ 1.316172] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10611 18:12:36.004432 <6>[ 2.513003] Freeing initrd memory: 40244K
10612 18:12:36.016764 <6>[ 2.524874] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10613 18:12:36.027606 <6>[ 2.535642] tun: Universal TUN/TAP device driver, 1.6
10614 18:12:36.030536 <6>[ 2.541695] thunder_xcv, ver 1.0
10615 18:12:36.033956 <6>[ 2.545203] thunder_bgx, ver 1.0
10616 18:12:36.036865 <6>[ 2.548700] nicpf, ver 1.0
10617 18:12:36.047263 <6>[ 2.552702] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10618 18:12:36.050891 <6>[ 2.560177] hns3: Copyright (c) 2017 Huawei Corporation.
10619 18:12:36.057669 <6>[ 2.565765] hclge is initializing
10620 18:12:36.060799 <6>[ 2.569345] e1000: Intel(R) PRO/1000 Network Driver
10621 18:12:36.067058 <6>[ 2.574474] e1000: Copyright (c) 1999-2006 Intel Corporation.
10622 18:12:36.070576 <6>[ 2.580486] e1000e: Intel(R) PRO/1000 Network Driver
10623 18:12:36.077613 <6>[ 2.585701] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10624 18:12:36.083879 <6>[ 2.591886] igb: Intel(R) Gigabit Ethernet Network Driver
10625 18:12:36.090423 <6>[ 2.597535] igb: Copyright (c) 2007-2014 Intel Corporation.
10626 18:12:36.097355 <6>[ 2.603370] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10627 18:12:36.104022 <6>[ 2.609888] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10628 18:12:36.107313 <6>[ 2.616352] sky2: driver version 1.30
10629 18:12:36.113624 <6>[ 2.621271] usbcore: registered new device driver r8152-cfgselector
10630 18:12:36.120318 <6>[ 2.627806] usbcore: registered new interface driver r8152
10631 18:12:36.127020 <6>[ 2.633617] VFIO - User Level meta-driver version: 0.3
10632 18:12:36.133473 <6>[ 2.641840] usbcore: registered new interface driver usb-storage
10633 18:12:36.139961 <6>[ 2.648287] usbcore: registered new device driver onboard-usb-hub
10634 18:12:36.149075 <6>[ 2.657423] mt6397-rtc mt6359-rtc: registered as rtc0
10635 18:12:36.158563 <6>[ 2.662886] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-11T18:11:10 UTC (1718129470)
10636 18:12:36.162320 <6>[ 2.672444] i2c_dev: i2c /dev entries driver
10637 18:12:36.175917 <4>[ 2.684433] cpu cpu0: supply cpu not found, using dummy regulator
10638 18:12:36.182301 <4>[ 2.690869] cpu cpu1: supply cpu not found, using dummy regulator
10639 18:12:36.189471 <4>[ 2.697275] cpu cpu2: supply cpu not found, using dummy regulator
10640 18:12:36.196117 <4>[ 2.703673] cpu cpu3: supply cpu not found, using dummy regulator
10641 18:12:36.202657 <4>[ 2.710094] cpu cpu4: supply cpu not found, using dummy regulator
10642 18:12:36.208929 <4>[ 2.716489] cpu cpu5: supply cpu not found, using dummy regulator
10643 18:12:36.215845 <4>[ 2.722892] cpu cpu6: supply cpu not found, using dummy regulator
10644 18:12:36.222397 <4>[ 2.729287] cpu cpu7: supply cpu not found, using dummy regulator
10645 18:12:36.242430 <6>[ 2.750961] cpu cpu0: EM: created perf domain
10646 18:12:36.245973 <6>[ 2.755908] cpu cpu4: EM: created perf domain
10647 18:12:36.253090 <6>[ 2.761463] sdhci: Secure Digital Host Controller Interface driver
10648 18:12:36.259678 <6>[ 2.767896] sdhci: Copyright(c) Pierre Ossman
10649 18:12:36.266473 <6>[ 2.772854] Synopsys Designware Multimedia Card Interface Driver
10650 18:12:36.273160 <6>[ 2.779491] sdhci-pltfm: SDHCI platform and OF driver helper
10651 18:12:36.276527 <6>[ 2.779533] mmc0: CQHCI version 5.10
10652 18:12:36.282937 <6>[ 2.789598] ledtrig-cpu: registered to indicate activity on CPUs
10653 18:12:36.289778 <6>[ 2.796645] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10654 18:12:36.296059 <6>[ 2.803717] usbcore: registered new interface driver usbhid
10655 18:12:36.299576 <6>[ 2.809540] usbhid: USB HID core driver
10656 18:12:36.306039 <6>[ 2.813738] spi_master spi0: will run message pump with realtime priority
10657 18:12:36.359609 <6>[ 2.861303] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10658 18:12:36.379593 <6>[ 2.877960] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10659 18:12:36.382855 <6>[ 2.885129] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10660 18:12:36.389968 <6>[ 2.894894] cros-ec-spi spi0.0: Chrome EC device registered
10661 18:12:36.393353 <6>[ 2.903390] mmc0: Command Queue Engine enabled
10662 18:12:36.400099 <6>[ 2.908132] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10663 18:12:36.406769 <6>[ 2.915563] mmcblk0: mmc0:0001 DA4128 116 GiB
10664 18:12:36.417176 <6>[ 2.918663] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 18:12:36.423678 <6>[ 2.924220] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10666 18:12:36.427136 <6>[ 2.930989] NET: Registered PF_PACKET protocol family
10667 18:12:36.433685 <6>[ 2.936936] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10668 18:12:36.436502 <6>[ 2.940887] 9pnet: Installing 9P2000 support
10669 18:12:36.443306 <6>[ 2.946672] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10670 18:12:36.447080 <5>[ 2.950574] Key type dns_resolver registered
10671 18:12:36.453571 <6>[ 2.956402] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10672 18:12:36.456798 <6>[ 2.960803] registered taskstats version 1
10673 18:12:36.463280 <5>[ 2.971175] Loading compiled-in X.509 certificates
10674 18:12:36.489746 <4>[ 2.991710] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10675 18:12:36.499993 <4>[ 3.002420] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10676 18:12:36.513910 <6>[ 3.022299] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10677 18:12:36.520598 <6>[ 3.029190] xhci-mtk 11200000.usb: xHCI Host Controller
10678 18:12:36.527701 <6>[ 3.034694] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10679 18:12:36.537492 <6>[ 3.042551] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10680 18:12:36.544192 <6>[ 3.051983] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10681 18:12:36.551053 <6>[ 3.058077] xhci-mtk 11200000.usb: xHCI Host Controller
10682 18:12:36.557674 <6>[ 3.063676] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10683 18:12:36.564038 <6>[ 3.071389] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10684 18:12:36.570815 <6>[ 3.079268] hub 1-0:1.0: USB hub found
10685 18:12:36.574231 <6>[ 3.083302] hub 1-0:1.0: 1 port detected
10686 18:12:36.584434 <6>[ 3.087619] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10687 18:12:36.587863 <6>[ 3.096402] hub 2-0:1.0: USB hub found
10688 18:12:36.590623 <6>[ 3.100444] hub 2-0:1.0: 1 port detected
10689 18:12:36.599804 <6>[ 3.108354] mtk-msdc 11f70000.mmc: Got CD GPIO
10690 18:12:36.612431 <6>[ 3.117623] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10691 18:12:36.622514 <6>[ 3.126017] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10692 18:12:36.629124 <6>[ 3.134359] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10693 18:12:36.638877 <6>[ 3.142702] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10694 18:12:36.645274 <6>[ 3.151042] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10695 18:12:36.655550 <6>[ 3.159381] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10696 18:12:36.662100 <6>[ 3.167722] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10697 18:12:36.672126 <6>[ 3.176060] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10698 18:12:36.678332 <6>[ 3.184400] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10699 18:12:36.688294 <6>[ 3.192739] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10700 18:12:36.695224 <6>[ 3.201077] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10701 18:12:36.705149 <6>[ 3.209422] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10702 18:12:36.711577 <6>[ 3.217760] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10703 18:12:36.721282 <6>[ 3.226097] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10704 18:12:36.728331 <6>[ 3.234435] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10705 18:12:36.734549 <6>[ 3.243171] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10706 18:12:36.741389 <6>[ 3.250317] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10707 18:12:36.748844 <6>[ 3.257078] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10708 18:12:36.758987 <6>[ 3.263872] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10709 18:12:36.765555 <6>[ 3.270813] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10710 18:12:36.772366 <6>[ 3.277686] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10711 18:12:36.781934 <6>[ 3.286826] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10712 18:12:36.792082 <6>[ 3.295947] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10713 18:12:36.802484 <6>[ 3.305241] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10714 18:12:36.811561 <6>[ 3.314708] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10715 18:12:36.818712 <6>[ 3.324179] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10716 18:12:36.828528 <6>[ 3.333300] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10717 18:12:36.838110 <6>[ 3.342767] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10718 18:12:36.848072 <6>[ 3.351886] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10719 18:12:36.858344 <6>[ 3.361180] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10720 18:12:36.868373 <6>[ 3.371341] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10721 18:12:36.877811 <6>[ 3.383043] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10722 18:12:37.005120 <6>[ 3.510931] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10723 18:12:37.160129 <6>[ 3.669069] hub 1-1:1.0: USB hub found
10724 18:12:37.163698 <6>[ 3.673556] hub 1-1:1.0: 4 ports detected
10725 18:12:37.175559 <6>[ 3.684324] hub 1-1:1.0: USB hub found
10726 18:12:37.178684 <6>[ 3.688701] hub 1-1:1.0: 4 ports detected
10727 18:12:37.285744 <6>[ 3.791247] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 18:12:37.312004 <6>[ 3.820921] hub 2-1:1.0: USB hub found
10729 18:12:37.315348 <6>[ 3.825465] hub 2-1:1.0: 3 ports detected
10730 18:12:37.326623 <6>[ 3.835177] hub 2-1:1.0: USB hub found
10731 18:12:37.330152 <6>[ 3.839562] hub 2-1:1.0: 3 ports detected
10732 18:12:37.501772 <6>[ 4.007045] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10733 18:12:37.633446 <6>[ 4.141974] hub 1-1.4:1.0: USB hub found
10734 18:12:37.636399 <6>[ 4.146499] hub 1-1.4:1.0: 2 ports detected
10735 18:12:37.650985 <6>[ 4.159807] hub 1-1.4:1.0: USB hub found
10736 18:12:37.654099 <6>[ 4.164445] hub 1-1.4:1.0: 2 ports detected
10737 18:12:37.713227 <6>[ 4.219039] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10738 18:12:37.821680 <6>[ 4.327288] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 18:12:37.853473 <4>[ 4.359034] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10740 18:12:37.863842 <4>[ 4.368133] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10741 18:12:37.903014 <6>[ 4.411865] r8152 2-1.3:1.0 eth0: v1.12.13
10742 18:12:37.953576 <6>[ 4.458809] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10743 18:12:38.149885 <6>[ 4.654984] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10744 18:12:39.663094 <6>[ 6.171465] r8152 2-1.3:1.0 eth0: carrier on
10745 18:12:42.493444 <5>[ 6.202775] Sending DHCP requests .., OK
10746 18:12:42.500540 <6>[ 9.007184] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10747 18:12:42.503448 <6>[ 9.015536] IP-Config: Complete:
10748 18:12:42.516903 <6>[ 9.019121] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10749 18:12:42.523310 <6>[ 9.029842] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10750 18:12:42.533309 <6>[ 9.038465] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10751 18:12:42.536580 <6>[ 9.038474] nameserver0=192.168.201.1
10752 18:12:42.540073 <6>[ 9.050666] clk: Disabling unused clocks
10753 18:12:42.543851 <6>[ 9.056385] ALSA device list:
10754 18:12:42.550571 <6>[ 9.059642] No soundcards found.
10755 18:12:42.557969 <6>[ 9.067193] Freeing unused kernel memory: 8512K
10756 18:12:42.561056 <6>[ 9.072158] Run /init as init process
10757 18:12:42.591185 <6>[ 9.100100] NET: Registered PF_INET6 protocol family
10758 18:12:42.597704 <6>[ 9.106597] Segment Routing with IPv6
10759 18:12:42.601041 <6>[ 9.110590] In-situ OAM (IOAM) with IPv6
10760 18:12:42.645226 <30>[ 9.127868] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10761 18:12:42.652061 <30>[ 9.161028] systemd[1]: Detected architecture arm64.
10762 18:12:42.652699
10763 18:12:42.658338 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10764 18:12:42.658808
10765 18:12:42.673744 <30>[ 9.183080] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10766 18:12:42.796015 <30>[ 9.302260] systemd[1]: Queued start job for default target graphical.target.
10767 18:12:42.830977 <30>[ 9.336634] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10768 18:12:42.837110 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10769 18:12:42.857599 <30>[ 9.363591] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10770 18:12:42.867294 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10771 18:12:42.887093 <30>[ 9.392940] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10772 18:12:42.896743 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10773 18:12:42.913169 <30>[ 9.419331] systemd[1]: Created slice user.slice - User and Session Slice.
10774 18:12:42.919632 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10775 18:12:42.940207 <30>[ 9.443010] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10776 18:12:42.947045 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10777 18:12:42.968807 <30>[ 9.471581] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10778 18:12:42.975395 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10779 18:12:43.003152 <30>[ 9.499050] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10780 18:12:43.012926 <30>[ 9.518893] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10781 18:12:43.019289 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10782 18:12:43.037811 <30>[ 9.543279] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10783 18:12:43.047376 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10784 18:12:43.065289 <30>[ 9.571379] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10785 18:12:43.074907 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10786 18:12:43.089818 <30>[ 9.599515] systemd[1]: Reached target paths.target - Path Units.
10787 18:12:43.100467 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10788 18:12:43.117140 <30>[ 9.623395] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10789 18:12:43.123687 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10790 18:12:43.137218 <30>[ 9.647015] systemd[1]: Reached target slices.target - Slice Units.
10791 18:12:43.147283 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10792 18:12:43.161768 <30>[ 9.671430] systemd[1]: Reached target swap.target - Swaps.
10793 18:12:43.168274 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10794 18:12:43.189235 <30>[ 9.695426] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10795 18:12:43.199683 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10796 18:12:43.218170 <30>[ 9.723788] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10797 18:12:43.227768 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10798 18:12:43.247021 <30>[ 9.752505] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10799 18:12:43.256536 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10800 18:12:43.273736 <30>[ 9.779673] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10801 18:12:43.283470 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10802 18:12:43.301740 <30>[ 9.807539] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10803 18:12:43.308255 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10804 18:12:43.325486 <30>[ 9.831605] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10805 18:12:43.335427 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10806 18:12:43.354179 <30>[ 9.860315] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10807 18:12:43.363858 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10808 18:12:43.382325 <30>[ 9.888037] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10809 18:12:43.392072 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10810 18:12:43.433090 <30>[ 9.938990] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10811 18:12:43.439554 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10812 18:12:43.461464 <30>[ 9.967324] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10813 18:12:43.468026 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10814 18:12:43.493620 <30>[ 9.999312] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10815 18:12:43.499812 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10816 18:12:43.527976 <30>[ 10.027379] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10817 18:12:43.565244 <30>[ 10.071388] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10818 18:12:43.575030 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10819 18:12:43.597969 <30>[ 10.104217] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10820 18:12:43.604862 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10821 18:12:43.630445 <30>[ 10.136252] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10822 18:12:43.643068 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 10.149810] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10823 18:12:43.646746 Module dm_mod...
10824 18:12:43.705251 <30>[ 10.211520] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10825 18:12:43.711742 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10826 18:12:43.734205 <30>[ 10.240144] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10827 18:12:43.743738 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10828 18:12:43.766582 <30>[ 10.272315] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10829 18:12:43.773056 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10830 18:12:43.825213 <30>[ 10.331427] systemd[1]: Starting systemd-journald.service - Journal Service...
10831 18:12:43.831789 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10832 18:12:43.852178 <30>[ 10.358187] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10833 18:12:43.858737 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10834 18:12:43.885874 <30>[ 10.388526] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10835 18:12:43.892673 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10836 18:12:43.949378 <30>[ 10.455529] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10837 18:12:43.959418 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10838 18:12:43.982874 <30>[ 10.488705] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10839 18:12:43.989372 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10840 18:12:44.017553 <30>[ 10.523289] systemd[1]: Started systemd-journald.service - Journal Service.
10841 18:12:44.024048 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10842 18:12:44.045338 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10843 18:12:44.062411 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10844 18:12:44.082582 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10845 18:12:44.102790 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10846 18:12:44.124172 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10847 18:12:44.144101 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10848 18:12:44.167706 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10849 18:12:44.188345 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10850 18:12:44.209990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10851 18:12:44.230799 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10852 18:12:44.250166 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10853 18:12:44.271391 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10854 18:12:44.277754 See 'systemctl status systemd-remount-fs.service' for details.
10855 18:12:44.287920 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10856 18:12:44.307817 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10857 18:12:44.361025 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10858 18:12:44.379532 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10859 18:12:44.393456 <46>[ 10.899765] systemd-journald[183]: Received client request to flush runtime journal.
10860 18:12:44.405881 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10861 18:12:44.428062 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10862 18:12:44.448187 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10863 18:12:44.471780 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10864 18:12:44.490567 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10865 18:12:44.514622 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10866 18:12:44.534684 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10867 18:12:44.554268 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10868 18:12:44.606334 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10869 18:12:44.627442 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10870 18:12:44.644654 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10871 18:12:44.664507 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10872 18:12:44.725272 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10873 18:12:44.754561 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10874 18:12:44.779249 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10875 18:12:44.803664 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10876 18:12:44.842644 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10877 18:12:45.014076 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10878 18:12:45.037200 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10879 18:12:45.064869 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10880 18:12:45.114289 [[0;32m OK [0m] Finished [0;1;39msystemd-up<5>[ 11.620657] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10881 18:12:45.117561 date-ut…cord System Boot/Shutdown in UTMP.
10882 18:12:45.139637 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10883 18:12:45.158923 <5>[ 11.665488] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10884 18:12:45.168959 <5>[ 11.674224] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10885 18:12:45.175604 <4>[ 11.683046] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10886 18:12:45.182027 <6>[ 11.692051] cfg80211: failed to load regulatory.db
10887 18:12:45.188982 <3>[ 11.694037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 18:12:45.198733 <6>[ 11.695415] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10889 18:12:45.205287 <6>[ 11.695442] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10890 18:12:45.215077 <6>[ 11.695452] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10891 18:12:45.222130 <6>[ 11.704814] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10892 18:12:45.231571 <3>[ 11.705251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 18:12:45.238616 <4>[ 11.720028] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10894 18:12:45.248524 <3>[ 11.721556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 18:12:45.255295 <6>[ 11.734912] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10896 18:12:45.262220 <4>[ 11.739367] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10897 18:12:45.272047 <3>[ 11.745194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 18:12:45.278255 <3>[ 11.745231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 18:12:45.288868 <3>[ 11.745236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 18:12:45.294991 <3>[ 11.745245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 18:12:45.301384 <3>[ 11.745251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 18:12:45.311228 <3>[ 11.745308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 18:12:45.318189 <3>[ 11.745349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 18:12:45.327966 <3>[ 11.745351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 18:12:45.334433 <3>[ 11.745354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10906 18:12:45.344452 <3>[ 11.745384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 18:12:45.350984 <3>[ 11.745387] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10908 18:12:45.361073 <3>[ 11.745389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 18:12:45.367574 <3>[ 11.745392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 18:12:45.377595 <3>[ 11.745395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 18:12:45.384217 <3>[ 11.745418] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10912 18:12:45.390761 <6>[ 11.746677] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10913 18:12:45.397764 <6>[ 11.784532] mc: Linux media interface: v0.10
10914 18:12:45.407527 <4>[ 11.785773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10915 18:12:45.414177 <6>[ 11.794483] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10916 18:12:45.420347 <6>[ 11.802124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10917 18:12:45.427332 <6>[ 11.829575] videodev: Linux video capture interface: v2.00
10918 18:12:45.433977 <6>[ 11.829644] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10919 18:12:45.440503 <6>[ 11.829663] pci_bus 0000:00: root bus resource [bus 00-ff]
10920 18:12:45.447241 <6>[ 11.829674] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10921 18:12:45.456763 <6>[ 11.829681] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10922 18:12:45.463756 <6>[ 11.829730] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10923 18:12:45.470296 <6>[ 11.829754] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10924 18:12:45.476823 <6>[ 11.829860] pci 0000:00:00.0: supports D1 D2
10925 18:12:45.483549 <6>[ 11.829865] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10926 18:12:45.489820 <6>[ 11.833963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10927 18:12:45.499818 <6>[ 11.836213] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10928 18:12:45.506815 <6>[ 11.844055] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10929 18:12:45.516335 <4>[ 11.848879] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10930 18:12:45.519705 <4>[ 11.848879] Fallback method does not support PEC.
10931 18:12:45.526482 <6>[ 11.850488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10932 18:12:45.533398 <6>[ 11.865571] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10933 18:12:45.543042 <6>[ 11.866524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10934 18:12:45.553118 <6>[ 11.867380] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10935 18:12:45.563233 <6>[ 11.872671] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10936 18:12:45.569793 <6>[ 11.874792] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10937 18:12:45.579835 <6>[ 11.880668] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10938 18:12:45.586061 <6>[ 11.883155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10939 18:12:45.596035 <6>[ 11.891244] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10940 18:12:45.602758 <6>[ 11.902734] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10941 18:12:45.609508 <6>[ 11.907298] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10942 18:12:45.612801 <6>[ 11.907863] pci 0000:01:00.0: supports D1 D2
10943 18:12:45.619548 <6>[ 11.914940] remoteproc remoteproc0: scp is available
10944 18:12:45.626308 <6>[ 11.921400] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10945 18:12:45.632651 <6>[ 11.929007] remoteproc remoteproc0: powering up scp
10946 18:12:45.639359 <6>[ 11.929016] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10947 18:12:45.645717 <6>[ 11.929056] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10948 18:12:45.649122 <6>[ 11.947720] Bluetooth: Core ver 2.22
10949 18:12:45.655974 <6>[ 11.962795] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10950 18:12:45.662697 <6>[ 11.972745] NET: Registered PF_BLUETOOTH protocol family
10951 18:12:45.669192 <6>[ 11.973715] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10952 18:12:45.682723 <6>[ 11.974880] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10953 18:12:45.689178 <6>[ 11.975087] usbcore: registered new interface driver uvcvideo
10954 18:12:45.695779 <6>[ 11.978904] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10955 18:12:45.701829 <6>[ 11.986355] Bluetooth: HCI device and connection manager initialized
10956 18:12:45.711780 <6>[ 11.990854] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10957 18:12:45.715701 <6>[ 11.997741] Bluetooth: HCI socket layer initialized
10958 18:12:45.721684 <6>[ 11.998610] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10959 18:12:45.731641 <6>[ 12.005627] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10960 18:12:45.735398 <6>[ 12.013539] Bluetooth: L2CAP socket layer initialized
10961 18:12:45.745383 <6>[ 12.021786] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10962 18:12:45.748140 <6>[ 12.035515] Bluetooth: SCO socket layer initialized
10963 18:12:45.758508 <6>[ 12.043233] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10964 18:12:45.761257 <6>[ 12.043246] pci 0000:00:00.0: PCI bridge to [bus 01]
10965 18:12:45.768238 <6>[ 12.054772] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10966 18:12:45.778313 <6>[ 12.054807] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10967 18:12:45.784741 <6>[ 12.054814] remoteproc remoteproc0: remote processor scp is now up
10968 18:12:45.791027 <6>[ 12.057315] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10969 18:12:45.797797 <6>[ 12.057617] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10970 18:12:45.807862 <6>[ 12.078426] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10971 18:12:45.814087 <6>[ 12.085258] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10972 18:12:45.821210 <6>[ 12.097790] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10973 18:12:45.827509 <6>[ 12.103363] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10974 18:12:45.833848 <6>[ 12.103456] usbcore: registered new interface driver btusb
10975 18:12:45.843984 <4>[ 12.110551] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10976 18:12:45.850864 <6>[ 12.210835] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10977 18:12:45.857284 <3>[ 12.217149] Bluetooth: hci0: Failed to load firmware file (-2)
10978 18:12:45.864119 <6>[ 12.225299] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10979 18:12:45.867320 <6>[ 12.242679] mt7921e 0000:01:00.0: ASIC revision: 79610010
10980 18:12:45.874088 <3>[ 12.245105] Bluetooth: hci0: Failed to set up firmware (-2)
10981 18:12:45.883878 <6>[ 12.345503] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10982 18:12:45.884349 <6>[ 12.345503]
10983 18:12:45.893668 <4>[ 12.347284] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10984 18:12:45.903305 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10985 18:12:45.920600 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10986 18:12:45.957895 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10987 18:12:45.977491 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10988 18:12:45.998438 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10989 18:12:46.044388 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10990 18:12:46.056770 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10991 18:12:46.076004 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10992 18:12:46.092698 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10993 18:12:46.107852 <6>[ 12.614867] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10994 18:12:46.117842 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10995 18:12:46.135841 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10996 18:12:46.152135 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10997 18:12:46.171687 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10998 18:12:46.178267 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10999 18:12:46.196294 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11000 18:12:46.241739 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11001 18:12:46.267162 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11002 18:12:46.289047 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11003 18:12:46.310135 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11004 18:12:46.342008 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11005 18:12:46.384740 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11006 18:12:46.405191 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11007 18:12:46.423784 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11008 18:12:46.480424 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11009 18:12:46.501268 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11010 18:12:46.520679 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11011 18:12:46.542087 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11012 18:12:46.560274 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11013 18:12:46.620845 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11014 18:12:46.659539 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11015 18:12:46.699111
11016 18:12:46.702524 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11017 18:12:46.703262
11018 18:12:46.706139 debian-bookworm-arm64 login: root (automatic login)
11019 18:12:46.706598
11020 18:12:46.728907 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 11 17:44:14 UTC 2024 aarch64
11021 18:12:46.729359
11022 18:12:46.735339 The programs included with the Debian GNU/Linux system are free software;
11023 18:12:46.742172 the exact distribution terms for each program are described in the
11024 18:12:46.745576 individual files in /usr/share/doc/*/copyright.
11025 18:12:46.746007
11026 18:12:46.752127 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11027 18:12:46.755261 permitted by applicable law.
11028 18:12:46.757021 Matched prompt #10: / #
11030 18:12:46.758289 Setting prompt string to ['/ #']
11031 18:12:46.758771 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11033 18:12:46.759744 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11034 18:12:46.760183 start: 2.2.6 expect-shell-connection (timeout 00:03:38) [common]
11035 18:12:46.760592 Setting prompt string to ['/ #']
11036 18:12:46.760920 Forcing a shell prompt, looking for ['/ #']
11038 18:12:46.811739 / #
11039 18:12:46.812304 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11040 18:12:46.812890 Waiting using forced prompt support (timeout 00:02:30)
11041 18:12:46.818180
11042 18:12:46.818936 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11043 18:12:46.819443 start: 2.2.7 export-device-env (timeout 00:03:38) [common]
11044 18:12:46.819914 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11045 18:12:46.820449 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
11046 18:12:46.820900 end: 2 depthcharge-action (duration 00:01:22) [common]
11047 18:12:46.821443 start: 3 lava-test-retry (timeout 00:08:17) [common]
11048 18:12:46.821894 start: 3.1 lava-test-shell (timeout 00:08:17) [common]
11049 18:12:46.822382 Using namespace: common
11051 18:12:46.923627 / # #
11052 18:12:46.924335 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11053 18:12:46.929992 #
11054 18:12:46.930850 Using /lava-14291494
11056 18:12:47.032056 / # export SHELL=/bin/sh
11057 18:12:47.032946 <6>[ 13.477446] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11058 18:12:47.037892 export SHELL=/bin/sh
11060 18:12:47.139463 / # . /lava-14291494/environment
11061 18:12:47.145453 . /lava-14291494/environment
11063 18:12:47.247341 / # /lava-14291494/bin/lava-test-runner /lava-14291494/0
11064 18:12:47.248000 Test shell timeout: 10s (minimum of the action and connection timeout)
11065 18:12:47.253528 /lava-14291494/bin/lava-test-runner /lava-14291494/0
11066 18:12:47.273888 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11067 18:12:47.280519 + cd /lava-14291494/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11068 18:12:47.281059 + cat uuid
11069 18:12:47.283758 + UUID=14291494_1.5.2.3.1
11070 18:12:47.284232 + set +x
11071 18:12:47.290644 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 14291494_1.5.2.3.1>
11072 18:12:47.291580 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 14291494_1.5.2.3.1
11073 18:12:47.292075 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (14291494_1.5.2.3.1)
11074 18:12:47.292535 Skipping test definition patterns.
11075 18:12:47.293658 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11076 18:12:47.297400 Received signal: <TESTCASE> TEST_CASE_ID<4
11077 18:12:47.297917 Ignoring malformed parameter for signal: "TEST_CASE_ID<4".
11078 18:12:47.303806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID<4>[ 13.811535] use of bytesused == 0 is deprecated and will be removed in the future,
11079 18:12:47.310534 =device-presence<4>[ 13.819581] use the actual size instead.
11080 18:12:47.311091 RESULT=pass>
11081 18:12:47.313884 device: /dev/video2
11082 18:12:47.324506 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11083 18:12:47.333954 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11084 18:12:47.340098
11085 18:12:47.352456 Compliance test for mtk-vcodec-enc device /dev/video2:
11086 18:12:47.359979
11087 18:12:47.374411 Driver Info:
11088 18:12:47.384778 Driver name : mtk-vcodec-enc
11089 18:12:47.399222 Card type : MT8192 video encoder
11090 18:12:47.409727 Bus info : platform:17020000.vcodec
11091 18:12:47.417644 Driver version : 6.1.92
11092 18:12:47.430746 Capabilities : 0x84204000
11093 18:12:47.441467 Video Memory-to-Memory Multiplanar
11094 18:12:47.450989 Streaming
11095 18:12:47.461020 Extended Pix Format
11096 18:12:47.473917 Device Capabilities
11097 18:12:47.485252 Device Caps : 0x04204000
11098 18:12:47.500404 Video Memory-to-Memory Multiplanar
11099 18:12:47.512699 Streaming
11100 18:12:47.525240 Extended Pix Format
11101 18:12:47.538328 Detected Stateful Encoder
11102 18:12:47.551852
11103 18:12:47.564257 Required ioctls:
11104 18:12:47.582765 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11105 18:12:47.583333 test VIDIOC_QUERYCAP: OK
11106 18:12:47.583995 Received signal: <TESTSET> START Required-ioctls
11107 18:12:47.584404 Starting test_set Required-ioctls
11108 18:12:47.607422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11109 18:12:47.608257 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11111 18:12:47.609963 test invalid ioctls: OK
11112 18:12:47.632790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11113 18:12:47.633436
11114 18:12:47.634280 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11116 18:12:47.640761 Allow for multiple opens:
11117 18:12:47.648341 <LAVA_SIGNAL_TESTSET STOP>
11118 18:12:47.649120 Received signal: <TESTSET> STOP
11119 18:12:47.649530 Closing test_set Required-ioctls
11120 18:12:47.657822 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11121 18:12:47.658491 Received signal: <TESTSET> START Allow-for-multiple-opens
11122 18:12:47.658849 Starting test_set Allow-for-multiple-opens
11123 18:12:47.661258 test second /dev/video2 open: OK
11124 18:12:47.680646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11125 18:12:47.681507 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11127 18:12:47.683557 test VIDIOC_QUERYCAP: OK
11128 18:12:47.704298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11129 18:12:47.705208 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11131 18:12:47.707176 test VIDIOC_G/S_PRIORITY: OK
11132 18:12:47.732403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11133 18:12:47.733319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11135 18:12:47.735073 test for unlimited opens: OK
11136 18:12:47.755499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11137 18:12:47.756071
11138 18:12:47.756858 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11140 18:12:47.766581 Debug ioctls:
11141 18:12:47.773490 <LAVA_SIGNAL_TESTSET STOP>
11142 18:12:47.774353 Received signal: <TESTSET> STOP
11143 18:12:47.774771 Closing test_set Allow-for-multiple-opens
11144 18:12:47.783202 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11145 18:12:47.784054 Received signal: <TESTSET> START Debug-ioctls
11146 18:12:47.784522 Starting test_set Debug-ioctls
11147 18:12:47.786918 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11148 18:12:47.808758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11149 18:12:47.809665 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11151 18:12:47.815066 test VIDIOC_LOG_STATUS: OK (Not Supported)
11152 18:12:47.833282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11153 18:12:47.833847
11154 18:12:47.834481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11156 18:12:47.843788 Input ioctls:
11157 18:12:47.850589 <LAVA_SIGNAL_TESTSET STOP>
11158 18:12:47.851411 Received signal: <TESTSET> STOP
11159 18:12:47.851793 Closing test_set Debug-ioctls
11160 18:12:47.859967 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11161 18:12:47.860763 Received signal: <TESTSET> START Input-ioctls
11162 18:12:47.861154 Starting test_set Input-ioctls
11163 18:12:47.863416 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11164 18:12:47.888855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11165 18:12:47.889693 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11167 18:12:47.891715 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11168 18:12:47.910768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11169 18:12:47.911574 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11171 18:12:47.917621 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11172 18:12:47.942857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11173 18:12:47.943772 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11175 18:12:47.948875 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11176 18:12:47.965864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11177 18:12:47.966683 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11179 18:12:47.969469 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11180 18:12:47.992424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11181 18:12:47.993317 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11183 18:12:47.995839 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11184 18:12:48.017541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11185 18:12:48.018392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11187 18:12:48.020684 Inputs: 0 Audio Inputs: 0 Tuners: 0
11188 18:12:48.028163
11189 18:12:48.049212 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11190 18:12:48.071801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11191 18:12:48.072694 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11193 18:12:48.078248 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11194 18:12:48.096463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11195 18:12:48.097332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11197 18:12:48.102771 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11198 18:12:48.125348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11199 18:12:48.126179 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11201 18:12:48.128351 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11202 18:12:48.148699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11203 18:12:48.149514 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11205 18:12:48.155533 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11206 18:12:48.172772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11207 18:12:48.173243
11208 18:12:48.174031 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11210 18:12:48.196466 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11211 18:12:48.219963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11212 18:12:48.220771 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11214 18:12:48.226623 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11215 18:12:48.249688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11216 18:12:48.250525 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11218 18:12:48.252960 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11219 18:12:48.271151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11220 18:12:48.271981 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11222 18:12:48.274701 test VIDIOC_G/S_EDID: OK (Not Supported)
11223 18:12:48.295782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11224 18:12:48.296367
11225 18:12:48.297087 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11227 18:12:48.304590 Control ioctls:
11228 18:12:48.311310 <LAVA_SIGNAL_TESTSET STOP>
11229 18:12:48.312038 Received signal: <TESTSET> STOP
11230 18:12:48.312430 Closing test_set Input-ioctls
11231 18:12:48.320833 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11232 18:12:48.321652 Received signal: <TESTSET> START Control-ioctls
11233 18:12:48.322061 Starting test_set Control-ioctls
11234 18:12:48.323635 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11235 18:12:48.349432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11236 18:12:48.350271 test VIDIOC_QUERYCTRL: OK
11237 18:12:48.351165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11239 18:12:48.372339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11240 18:12:48.373127 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11242 18:12:48.375666 test VIDIOC_G/S_CTRL: OK
11243 18:12:48.397882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11244 18:12:48.398550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11246 18:12:48.400705 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11247 18:12:48.427968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11248 18:12:48.428803 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11250 18:12:48.434418 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11251 18:12:48.440135 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11252 18:12:48.467131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11253 18:12:48.468130 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11255 18:12:48.470495 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11256 18:12:48.490521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11257 18:12:48.491242 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11259 18:12:48.493782 Standard Controls: 16 Private Controls: 0
11260 18:12:48.500494
11261 18:12:48.511033 Format ioctls:
11262 18:12:48.516659 <LAVA_SIGNAL_TESTSET STOP>
11263 18:12:48.517497 Received signal: <TESTSET> STOP
11264 18:12:48.517888 Closing test_set Control-ioctls
11265 18:12:48.525907 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11266 18:12:48.526740 Received signal: <TESTSET> START Format-ioctls
11267 18:12:48.527154 Starting test_set Format-ioctls
11268 18:12:48.528958 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11269 18:12:48.558142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11270 18:12:48.558981 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11272 18:12:48.561183 test VIDIOC_G/S_PARM: OK
11273 18:12:48.580232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11274 18:12:48.581137 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11276 18:12:48.583722 test VIDIOC_G_FBUF: OK (Not Supported)
11277 18:12:48.606277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11278 18:12:48.607118 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11280 18:12:48.609220 test VIDIOC_G_FMT: OK
11281 18:12:48.632608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11282 18:12:48.633466 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11284 18:12:48.635373 test VIDIOC_TRY_FMT: OK
11285 18:12:48.656052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11286 18:12:48.656897 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11288 18:12:48.662641 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11289 18:12:48.670920 test VIDIOC_S_FMT: FAIL
11290 18:12:48.695942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11291 18:12:48.696765 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11293 18:12:48.698934 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11294 18:12:48.720316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11295 18:12:48.721215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11297 18:12:48.723643 test Cropping: OK
11298 18:12:48.744781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11299 18:12:48.745626 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11301 18:12:48.747055 test Composing: OK (Not Supported)
11302 18:12:48.767845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11303 18:12:48.768692 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11305 18:12:48.771538 test Scaling: OK (Not Supported)
11306 18:12:48.792591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11307 18:12:48.793173
11308 18:12:48.793815 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11310 18:12:48.804236 Codec ioctls:
11311 18:12:48.812953 <LAVA_SIGNAL_TESTSET STOP>
11312 18:12:48.813779 Received signal: <TESTSET> STOP
11313 18:12:48.814170 Closing test_set Format-ioctls
11314 18:12:48.824230 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11315 18:12:48.825150 Received signal: <TESTSET> START Codec-ioctls
11316 18:12:48.825553 Starting test_set Codec-ioctls
11317 18:12:48.827341 test VIDIOC_(TRY_)ENCODER_CMD: OK
11318 18:12:48.850054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11319 18:12:48.850887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11321 18:12:48.856504 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11322 18:12:48.873942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11323 18:12:48.874763 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11325 18:12:48.880512 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11326 18:12:48.899584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11327 18:12:48.900138
11328 18:12:48.900800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11330 18:12:48.911547 Buffer ioctls:
11331 18:12:48.920259 <LAVA_SIGNAL_TESTSET STOP>
11332 18:12:48.921155 Received signal: <TESTSET> STOP
11333 18:12:48.921548 Closing test_set Codec-ioctls
11334 18:12:48.929742 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11335 18:12:48.930579 Received signal: <TESTSET> START Buffer-ioctls
11336 18:12:48.930978 Starting test_set Buffer-ioctls
11337 18:12:48.932908 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11338 18:12:48.956719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11339 18:12:48.957553 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11341 18:12:48.959584 test CREATE_BUFS maximum buffers: OK
11342 18:12:48.976156 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11344 18:12:48.979135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11345 18:12:48.979608 test VIDIOC_EXPBUF: OK
11346 18:12:48.999833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11347 18:12:49.000686 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11349 18:12:49.002796 test Requests: OK (Not Supported)
11350 18:12:49.025794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11351 18:12:49.026373
11352 18:12:49.027046 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11354 18:12:49.035562 Test input 0:
11355 18:12:49.047717
11356 18:12:49.057862 Streaming ioctls:
11357 18:12:49.065940 <LAVA_SIGNAL_TESTSET STOP>
11358 18:12:49.066783 Received signal: <TESTSET> STOP
11359 18:12:49.067206 Closing test_set Buffer-ioctls
11360 18:12:49.077983 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11361 18:12:49.078705 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11362 18:12:49.079097 Starting test_set Streaming-ioctls_Test-input-0
11363 18:12:49.080977 test read/write: OK (Not Supported)
11364 18:12:49.105537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11365 18:12:49.106350 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11367 18:12:49.111943 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11368 18:12:49.118577 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11369 18:12:49.126312 test blocking wait: FAIL
11370 18:12:49.154494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11371 18:12:49.155308 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11373 18:12:49.161217 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11374 18:12:49.166810 test MMAP (select): FAIL
11375 18:12:49.190416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11376 18:12:49.191244 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11378 18:12:49.197004 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11379 18:12:49.200952 test MMAP (epoll): FAIL
11380 18:12:49.225640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11381 18:12:49.226314 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11383 18:12:49.232033 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11384 18:12:49.239011 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11385 18:12:49.246766 test USERPTR (select): FAIL
11386 18:12:49.270514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11387 18:12:49.271501 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11389 18:12:49.276990 test DMABUF: Cannot test, specify --expbuf-device
11390 18:12:49.281517
11391 18:12:49.299345 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11392 18:12:49.302463 <LAVA_TEST_RUNNER EXIT>
11393 18:12:49.303315 ok: lava_test_shell seems to have completed
11394 18:12:49.303723 Marking unfinished test run as failed
11396 18:12:49.308967 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11397 18:12:49.309659 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11398 18:12:49.310143 end: 3 lava-test-retry (duration 00:00:02) [common]
11399 18:12:49.310627 start: 4 finalize (timeout 00:08:15) [common]
11400 18:12:49.311121 start: 4.1 power-off (timeout 00:00:30) [common]
11401 18:12:49.312191 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11402 18:12:49.568344 >> Command sent successfully.
11403 18:12:49.578522 Returned 0 in 0 seconds
11404 18:12:49.679883 end: 4.1 power-off (duration 00:00:00) [common]
11406 18:12:49.681473 start: 4.2 read-feedback (timeout 00:08:14) [common]
11407 18:12:49.682728 Listened to connection for namespace 'common' for up to 1s
11408 18:12:50.683444 Finalising connection for namespace 'common'
11409 18:12:50.683739 Disconnecting from shell: Finalise
11410 18:12:50.683893 / #
11411 18:12:50.784643 end: 4.2 read-feedback (duration 00:00:01) [common]
11412 18:12:50.785377 end: 4 finalize (duration 00:00:01) [common]
11413 18:12:50.786012 Cleaning after the job
11414 18:12:50.786527 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/ramdisk
11415 18:12:50.806798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/kernel
11416 18:12:50.838470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/dtb
11417 18:12:50.838763 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14291494/tftp-deploy-_xa68jvm/modules
11418 18:12:50.846221 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14291494
11419 18:12:50.905839 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14291494
11420 18:12:50.906024 Job finished correctly